From grosser at fim.uni-passau.de Mon Jul 4 00:26:17 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 04 Jul 2011 00:26:17 -0500 Subject: [llvm-commits] [PATCH] SuccIterator on bbs without terminator insts In-Reply-To: <4E1106A7.10101@mxc.ca> References: <4E10F310.4060705@fim.uni-passau.de> <4E1106A7.10101@mxc.ca> Message-ID: <4E114EF9.8080105@fim.uni-passau.de> On 07/03/2011 07:17 PM, Nick Lewycky wrote: > Tobias Grosser wrote: >> Hi, >> >> this patch removes the assert, that triggers if SuccIterator is >> constructed for a basic block without a terminator instruction. Instead >> of triggering an assert a succ_end() iterator is returned. This models a >> basic block with zero successors and allows us to use F->viewCFG() on >> incompletely constructed functions. >> >> OK to commit? > > Intuitively no, because all basic blocks are required to have > terminators. But I suspect you ran into this for a reason, and tools > like succ_begin/end() may not be able to assume that the CFG is valid at > any point in time because the IR is being modified. Could you explain > more about what you were doing which triggered this? It's pretty easy. In Polly we modify the CFG by adding some additional basic blocks (actually a branch that contains an optimized code path). Once in a while (because of a bug in Polly or somewhere in LLVM) I have a failing test case. My first step to investigate a bug is to put a breakpoint at the place in the code where I suspect the bug (or an assert triggered). My next step is to call F->viewCFG() to see the current state of the CFG. Unfortunately this almost never works, as the CFG is at this point not yet fully constructed and consequently the above assert triggers. In general I believe for debugging it would be very helpful if F->viewCFG() would already work during the construction of the CFG. > Would it be > difficult to avoid calling succ_begin() on malformed basic blocks? Yes. The problem is viewCFG() and in general the Graph printing infrastructure use the normal GraphTraits description of the CFG, which again calls the succ_begin/end() functions. Hence, viewCFG() only works on incomplete functions/basic blocks if the normal GraphTraits and the succ_begin/end() iterators can handle incomplete basic blocks. This is currently not the case (because of the assert). I personally see no problem removing the assert, because conceptually a basic block without any terminator is just a basic block with zero successors. There is also no need to enforce the required form of the LLVM-IR through the succ_begin()/end() iterators, as we have a dedicated verification pass for this. Cheers Tobi From x.tong at utoronto.ca Mon Jul 4 10:14:12 2011 From: x.tong at utoronto.ca (Xin Tong Utoronto) Date: Mon, 4 Jul 2011 11:14:12 -0400 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch Message-ID: Hi All This patch is intended to provide support for LLVM JIT adaptive compilation on x86 platforms. The implementation of the adaptive compilation framework is one of the Google Summer of Code 2011 projects ( http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). The patch is created against the LLVM branch below. It is currently reviewed by Eric Christoper at Apple and will be applied to the LLVM branch ( https://echristo@ llvm.org/svn/llvm-project/llvm/branches/GSoC/adaptive-compilation). But more eyes are definitely welcome. Originally, the LLVM adaptive compilation framework was intended to be applied to LLVM head stream, but due to concerns regarding the upcoming major changes on ExecutionEngine and MCJIT. it is now worked in a branch and hopefully applied to the head stream once the MCJIT changes have been completed. * * *This patch involves changes to * include/llvm/Target/TargetJITInfo.h lib/Target/X86/X86JITInfo.h lib/Target/X86/X86JITInfo.cpp lib/Target/ARM/ARMJITInfo.h lib/Target/ARM/ARMJITInfo.cpp lib/Target/PowerPC/PPCJITInfo.h lib/Target/PowerPC/PPCJITInfo.cpp lib/ExecutionEngine/JIT/JITEmitter.cpp lib/ExecutionEngine/JIT/JIT.h lib/ExecutionEngine/JIT/JIT.cpp *This was tested on x86 and x86-64 under Ubuntu with* * * llvm test-suite *There were no regressions for the O0 - O3 JIT compilation. Additionally, adaptive compilation currently gives better performance numbers than O1 - O3 as shown.* lli -O0 Total Time is 1068.37 lli -O1 Total Time is 1395.68 lli -O2 Total Time is 1394.81 lli -O3 Total Time is 1395.76 lli -adaptive-comp Total Time is 1119.23 Thank You Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/2631243a/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: x86_adaptivecomp.patch Type: application/octet-stream Size: 26515 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/2631243a/attachment.obj From rdivacky at freebsd.org Mon Jul 4 10:42:45 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 04 Jul 2011 15:42:45 -0000 Subject: [llvm-commits] [llvm] r134376 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <20110704154245.591582A6C12C@llvm.org> Author: rdivacky Date: Mon Jul 4 10:42:45 2011 New Revision: 134376 URL: http://llvm.org/viewvc/llvm-project?rev=134376&view=rev Log: Remove accidentaly left node from previous iteration of the patch. Noticed by Benjamin Kramer! Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=134376&r1=134375&r2=134376&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 4 10:42:45 2011 @@ -1321,9 +1321,6 @@ SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, DAG.getConstant(8, MVT::i32), ISD::SETLT); - SDValue Area = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, RegSaveArea, - OverflowArea); - // adjustment constant gpr_index * 4/8 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, From x.tong at utoronto.ca Mon Jul 4 10:58:05 2011 From: x.tong at utoronto.ca (Xin Tong Utoronto) Date: Mon, 4 Jul 2011 11:58:05 -0400 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch In-Reply-To: <4e11d99c.8521e70a.2556.2dfeSMTPIN_ADDED@mx.google.com> References: <4e11d99c.8521e70a.2556.2dfeSMTPIN_ADDED@mx.google.com> Message-ID: The original numbers are the same as what are given here. As the lli -O0 - O3 is virtually the same as before if adaptive compilation is not enabled. Thanks Xin On Mon, Jul 4, 2011 at 11:17 AM, James Molloy wrote: > Hi Xin,**** > > ** ** > > What were the original numbers before adaptive compilation?**** > > ** ** > > Cheers,**** > > ** ** > > James**** > > ** ** > > *From:* llvm-commits-bounces at cs.uiuc.edu [mailto: > llvm-commits-bounces at cs.uiuc.edu] *On Behalf Of *Xin Tong Utoronto > *Sent:* 04 July 2011 16:14 > *To:* llvm-commits at cs.uiuc.edu > *Subject:* [llvm-commits] [llvm jit adaptive-compilation] : Adaptive > compilation framework x86 Patch**** > > ** ** > > Hi All**** > > **** > > This patch is intended to provide support for LLVM JIT adaptive compilation > on x86 platforms. The implementation of the adaptive compilation framework > is one of the Google Summer of Code 2011 projects ( > http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). > The patch is created against the LLVM branch below. It is currently > reviewed by Eric Christoper at Apple and will be applied to the LLVM branch ( > https://echristo@ > llvm.org/svn/llvm-project/llvm/branches/GSoC/adaptive-compilation). But > more eyes are definitely welcome. Originally, the LLVM adaptive compilation > framework was intended to be applied to LLVM head stream, but due to > concerns regarding the upcoming major changes on ExecutionEngine and MCJIT. > it is now worked in a branch and hopefully applied to the head stream once > the MCJIT changes have been completed.**** > > ** ** > > *This patch involves changes to ***** > > **** > > include/llvm/Target/TargetJITInfo.h**** > > lib/Target/X86/X86JITInfo.h**** > > lib/Target/X86/X86JITInfo.cpp**** > > lib/Target/ARM/ARMJITInfo.h**** > > lib/Target/ARM/ARMJITInfo.cpp**** > > lib/Target/PowerPC/PPCJITInfo.h**** > > lib/Target/PowerPC/PPCJITInfo.cpp**** > > lib/ExecutionEngine/JIT/JITEmitter.cpp**** > > lib/ExecutionEngine/JIT/JIT.h**** > > lib/ExecutionEngine/JIT/JIT.cpp**** > > **** > > *This was tested on x86 and x86-64 under Ubuntu with***** > > ** ** > > llvm test-suite**** > > **** > > *There were no regressions for the O0 - O3 JIT compilation. Additionally, > adaptive compilation currently gives better performance numbers than O1 - O3 > as shown.***** > > **** > > lli -O0**** > > Total Time is 1068.37**** > > lli -O1**** > > Total Time is 1395.68**** > > **** > > lli -O2**** > > Total Time is 1394.81**** > > **** > > lli -O3**** > > Total Time is 1395.76**** > > **** > > lli -adaptive-comp**** > > Total Time is 1119.23**** > > **** > > **** > > Thank You**** > > Xin Tong **** > -- Kind Regards Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/af22b51a/attachment.html From james.molloy at arm.com Mon Jul 4 10:17:36 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 4 Jul 2011 16:17:36 +0100 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch In-Reply-To: References: Message-ID: <000201cc3a5d$81e54e80$85afeb80$@molloy@arm.com> Hi Xin, What were the original numbers before adaptive compilation? Cheers, James From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Xin Tong Utoronto Sent: 04 July 2011 16:14 To: llvm-commits at cs.uiuc.edu Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch Hi All This patch is intended to provide support for LLVM JIT adaptive compilation on x86 platforms. The implementation of the adaptive compilation framework is one of the Google Summer of Code 2011 projects ( http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). The patch is created against the LLVM branch below. It is currently reviewed by Eric Christoper at Apple and will be applied to the LLVM branch ( https://echristo@ llvm.org/svn/llvm-project/llvm/branches/GSoC/adaptive-compilation). But more eyes are definitely welcome. Originally, the LLVM adaptive compilation framework was intended to be applied to LLVM head stream, but due to concerns regarding the upcoming major changes on ExecutionEngine and MCJIT. it is now worked in a branch and hopefully applied to the head stream once the MCJIT changes have been completed. This patch involves changes to include/llvm/Target/TargetJITInfo.h lib/Target/X86/X86JITInfo.h lib/Target/X86/X86JITInfo.cpp lib/Target/ARM/ARMJITInfo.h lib/Target/ARM/ARMJITInfo.cpp lib/Target/PowerPC/PPCJITInfo.h lib/Target/PowerPC/PPCJITInfo.cpp lib/ExecutionEngine/JIT/JITEmitter.cpp lib/ExecutionEngine/JIT/JIT.h lib/ExecutionEngine/JIT/JIT.cpp This was tested on x86 and x86-64 under Ubuntu with llvm test-suite There were no regressions for the O0 - O3 JIT compilation. Additionally, adaptive compilation currently gives better performance numbers than O1 - O3 as shown. lli -O0 Total Time is 1068.37 lli -O1 Total Time is 1395.68 lli -O2 Total Time is 1394.81 lli -O3 Total Time is 1395.76 lli -adaptive-comp Total Time is 1119.23 Thank You Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/4216c99a/attachment.html From echristo at apple.com Mon Jul 4 13:16:32 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 04 Jul 2011 11:16:32 -0700 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch In-Reply-To: References: <4e11d99c.8521e70a.2556.2dfeSMTPIN_ADDED@mx.google.com> Message-ID: <35C48A86-CFB9-42C3-8FAA-051E3B6C1030@apple.com> On Jul 4, 2011, at 8:58 AM, Xin Tong Utoronto wrote: > The original numbers are the same as what are given here. As the lli -O0 - O3 is virtually the same as before if adaptive compilation is not enabled. "The same" isn't a number? So, that's giving total time to run the testsuite on x86 in seconds I gather. How about individual tests? Any significant regressions? Progressions? What were the top 10 of each? -eric From x.tong at utoronto.ca Mon Jul 4 13:44:19 2011 From: x.tong at utoronto.ca (Xin Tong Utoronto) Date: Mon, 4 Jul 2011 14:44:19 -0400 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch In-Reply-To: <35C48A86-CFB9-42C3-8FAA-051E3B6C1030@apple.com> References: <4e11d99c.8521e70a.2556.2dfeSMTPIN_ADDED@mx.google.com> <35C48A86-CFB9-42C3-8FAA-051E3B6C1030@apple.com> Message-ID: Thanks Xin On Mon, Jul 4, 2011 at 2:16 PM, Eric Christopher wrote: > > On Jul 4, 2011, at 8:58 AM, Xin Tong Utoronto wrote: > > > The original numbers are the same as what are given here. As the lli -O0 > - O3 is virtually the same as before if adaptive compilation is not enabled. > > "The same" isn't a number? > > So, that's giving total time to run the testsuite on x86 in seconds I > gather. How about individual tests? Any significant regressions? > Progressions? What were the top 10 of each? > Honestly I do not have the original numbers, I will launch a run now and post later today or tomorrow. Right, the total time is in seconds. I will report on progressions and regressions as well in the next post. -Xin > > -eric > -- Kind Regards Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/4c1e5ad6/attachment.html From benny.kra at googlemail.com Mon Jul 4 15:16:36 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 04 Jul 2011 20:16:36 -0000 Subject: [llvm-commits] [llvm] r134379 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll Message-ID: <20110704201636.86E0D2A6C12C@llvm.org> Author: d0k Date: Mon Jul 4 15:16:36 2011 New Revision: 134379 URL: http://llvm.org/viewvc/llvm-project?rev=134379&view=rev Log: PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use. This can pessimize code, inequalities are generally more expensive. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/test/Transforms/InstCombine/icmp.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=134379&r1=134378&r2=134379&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Mon Jul 4 15:16:36 2011 @@ -1454,7 +1454,11 @@ return new ICmpInst(isICMP_NE ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE, LHSI, Constant::getNullValue(RHS->getType())); - + + // Don't perform the following transforms if the AND has multiple uses + if (!BO->hasOneUse()) + break; + // Replace (and X, (1 << size(X)-1) != 0) with x s< 0 if (BOC->getValue().isSignBit()) { Value *X = BO->getOperand(0); Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=134379&r1=134378&r2=134379&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Jul 4 15:16:36 2011 @@ -547,3 +547,15 @@ %cmp = icmp eq i32 %sub, 123 ret i1 %cmp } + +; PR10267 Don't make icmps more expensive when no other inst is subsumed. +declare void @foo(i32) +; CHECK: @test57 +; CHECK: %and = and i32 %a, -2 +; CHECK: %cmp = icmp ne i32 %and, 0 +define i1 @test57(i32 %a) { + %and = and i32 %a, -2 + %cmp = icmp ne i32 %and, 0 + call void @foo(i32 %and) + ret i1 %cmp +} From clattner at apple.com Mon Jul 4 16:48:52 2011 From: clattner at apple.com (Chris Lattner) Date: Mon, 04 Jul 2011 14:48:52 -0700 Subject: [llvm-commits] [PATCH] SuccIterator on bbs without terminator insts In-Reply-To: <4E114EF9.8080105@fim.uni-passau.de> References: <4E10F310.4060705@fim.uni-passau.de> <4E1106A7.10101@mxc.ca> <4E114EF9.8080105@fim.uni-passau.de> Message-ID: <9F6878CC-83C4-462C-9C11-C730F3C74144@apple.com> On Jul 3, 2011, at 10:26 PM, Tobias Grosser wrote: >> Intuitively no, because all basic blocks are required to have >> terminators. But I suspect you ran into this for a reason, and tools >> like succ_begin/end() may not be able to assume that the CFG is valid at >> any point in time because the IR is being modified. Could you explain >> more about what you were doing which triggered this? > > It's pretty easy. > > In Polly we modify the CFG by adding some additional basic blocks > (actually a branch that contains an optimized code path). Once in a > while (because of a bug in Polly or somewhere in LLVM) I have a failing > test case. My first step to investigate a bug is to put a breakpoint at > the place in the code where I suspect the bug (or an assert triggered). > My next step is to call F->viewCFG() to see the current state of the > CFG. Unfortunately this almost never works, as the CFG is at this point > not yet fully constructed and consequently the above assert triggers. > > In general I believe for debugging it would be very helpful if > F->viewCFG() would already work during the construction of the CFG. I agree with Nick that this is really counterintuitive, but your logic makes sense to me. Please commit with a comment explaining that getTerminator() is allowed to return null for malformed CFGs. -Chris From grosser at fim.uni-passau.de Mon Jul 4 18:09:02 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 04 Jul 2011 23:09:02 -0000 Subject: [llvm-commits] [llvm] r134398 - /llvm/trunk/include/llvm/Support/CFG.h Message-ID: <20110704230902.CBFA12A6C12C@llvm.org> Author: grosser Date: Mon Jul 4 18:09:02 2011 New Revision: 134398 URL: http://llvm.org/viewvc/llvm-project?rev=134398&view=rev Log: SuccIterator on bbs without terminator insts Remove the assert that triggers if SuccIterator is constructed for a basic block without a terminator instruction. Instead of triggering an assert a succ_end() iterator is returned. This models a basic block with zero successors and allows us to use F->viewCFG() on incompletely constructed functions. Modified: llvm/trunk/include/llvm/Support/CFG.h Modified: llvm/trunk/include/llvm/Support/CFG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=134398&r1=134397&r2=134398&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CFG.h (original) +++ llvm/trunk/include/llvm/Support/CFG.h Mon Jul 4 18:09:02 2011 @@ -109,11 +109,18 @@ // TODO: This can be random access iterator, only operator[] missing. explicit inline SuccIterator(Term_ T) : Term(T), idx(0) {// begin iterator - assert(T && "getTerminator returned null!"); } inline SuccIterator(Term_ T, bool) // end iterator - : Term(T), idx(Term->getNumSuccessors()) { - assert(T && "getTerminator returned null!"); + : Term(T) { + if (Term) + idx = Term->getNumSuccessors(); + else + // Term == NULL happens, if a basic block is not fully constructed and + // consequently getTerminator() returns NULL. In this case we construct a + // SuccIterator which describes a basic block that has zero successors. + // Defining SuccIterator for incomplete and malformed CFGs is especially + // useful for debugging. + idx = 0; } inline const Self &operator=(const Self &I) { @@ -201,6 +208,7 @@ /// Get the source BB of this iterator. inline BB_ *getSource() { + assert(Term && "Source not available, if basic block was malformed"); return Term->getParent(); } }; From grosser at fim.uni-passau.de Mon Jul 4 18:15:55 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 04 Jul 2011 18:15:55 -0500 Subject: [llvm-commits] [PATCH] SuccIterator on bbs without terminator insts In-Reply-To: <9F6878CC-83C4-462C-9C11-C730F3C74144@apple.com> References: <4E10F310.4060705@fim.uni-passau.de> <4E1106A7.10101@mxc.ca> <4E114EF9.8080105@fim.uni-passau.de> <9F6878CC-83C4-462C-9C11-C730F3C74144@apple.com> Message-ID: <4E1249AB.7070707@fim.uni-passau.de> On 07/04/2011 04:48 PM, Chris Lattner wrote: > On Jul 3, 2011, at 10:26 PM, Tobias Grosser wrote: >>> Intuitively no, because all basic blocks are required to have >>> terminators. But I suspect you ran into this for a reason, and tools >>> like succ_begin/end() may not be able to assume that the CFG is valid at >>> any point in time because the IR is being modified. Could you explain >>> more about what you were doing which triggered this? >> >> It's pretty easy. >> >> In Polly we modify the CFG by adding some additional basic blocks >> (actually a branch that contains an optimized code path). Once in a >> while (because of a bug in Polly or somewhere in LLVM) I have a failing >> test case. My first step to investigate a bug is to put a breakpoint at >> the place in the code where I suspect the bug (or an assert triggered). >> My next step is to call F->viewCFG() to see the current state of the >> CFG. Unfortunately this almost never works, as the CFG is at this point >> not yet fully constructed and consequently the above assert triggers. >> >> In general I believe for debugging it would be very helpful if >> F->viewCFG() would already work during the construction of the CFG. > > I agree with Nick that this is really counterintuitive, but your logic makes sense to me. Please commit with a comment explaining that getTerminator() is allowed to return null for malformed CFGs. Committed in 134398. Cheers Tobi From grosser at fim.uni-passau.de Mon Jul 4 18:18:17 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 04 Jul 2011 23:18:17 -0000 Subject: [llvm-commits] [polly] r134400 - /polly/trunk/test/CodeGen/single_loop_param.ll Message-ID: <20110704231817.E48092A6C12C@llvm.org> Author: grosser Date: Mon Jul 4 18:18:17 2011 New Revision: 134400 URL: http://llvm.org/viewvc/llvm-project?rev=134400&view=rev Log: test: Remove redundant function definition The latest version of LLVM fails, if a function is defined twice in an LLVM bitcode file. Modified: polly/trunk/test/CodeGen/single_loop_param.ll Modified: polly/trunk/test/CodeGen/single_loop_param.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_param.ll?rev=134400&r1=134399&r2=134400&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_param.ll (original) +++ polly/trunk/test/CodeGen/single_loop_param.ll Mon Jul 4 18:18:17 2011 @@ -70,9 +70,6 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind - -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind - ; CHECK: if (M >= 1) { ; CHECK: for (c2=0;c2<=M-1;c2++) { ; CHECK: Stmt_bb2(c2); From rpaulo at apple.com Mon Jul 4 19:26:06 2011 From: rpaulo at apple.com (Rui Paulo) Date: Mon, 04 Jul 2011 17:26:06 -0700 Subject: [llvm-commits] Patch: add contains to ImmutableList Message-ID: <360E1DF3-0EA5-45A2-AD20-63CE242E1D48@apple.com> Hi, Attached is a patch to add a contains method to ImmutableList. I need this in the clang Static Analyzer. Regards, -- Rui Paulo -------------- next part -------------- A non-text attachment was scrubbed... Name: contains.diff Type: application/octet-stream Size: 751 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110704/f26a070e/attachment.obj From nicholas at mxc.ca Mon Jul 4 21:53:22 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 04 Jul 2011 19:53:22 -0700 Subject: [llvm-commits] Patch: add contains to ImmutableList In-Reply-To: <360E1DF3-0EA5-45A2-AD20-63CE242E1D48@apple.com> References: <360E1DF3-0EA5-45A2-AD20-63CE242E1D48@apple.com> Message-ID: <4E127CA2.9050705@mxc.ca> Rui Paulo wrote: > Hi, > > Attached is a patch to add a contains method to ImmutableList. I need this in the clang Static Analyzer. Do you really need "this->" here?: + for (iterator I = this->begin(), E = this->end(); I != E; ++I) { Yes the type is templated, but it doesn't have a template base. Secondly: + if (*I == V) The existing code in ImmutableList does not care at all about how T::operator== works, instead assuming that the objects in the list are uniqued by address. If that assumption is okay with you, you may want to write "if (I == &V)" instead. Finally, are you sure that doing an O(n) scan is OK for your use case? I'll take your word for it if it's really the right thing to do, but just having this may encourage poor algorithm choices by others. As an alternative, how about a function which takes a T* and returns the ImmutableList::iterator pointing to the right element or the end() iterator if it's not a member? Do you have commit access? Nick From nicholas at mxc.ca Mon Jul 4 22:02:09 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 04 Jul 2011 20:02:09 -0700 Subject: [llvm-commits] Patch: add contains to ImmutableList In-Reply-To: <4E127CA2.9050705@mxc.ca> References: <360E1DF3-0EA5-45A2-AD20-63CE242E1D48@apple.com> <4E127CA2.9050705@mxc.ca> Message-ID: <4E127EB1.7010101@mxc.ca> Nick Lewycky wrote: > Rui Paulo wrote: >> Hi, >> >> Attached is a patch to add a contains method to ImmutableList. I need this in the clang Static Analyzer. > > Do you really need "this->" here?: > > + for (iterator I = this->begin(), E = this->end(); I != E; ++I) { > > Yes the type is templated, but it doesn't have a template base. > > Secondly: > > + if (*I == V) > > The existing code in ImmutableList does not care at all about how > T::operator== works, instead assuming that the objects in the list are > uniqued by address. If that assumption is okay with you, you may want to > write "if (I ==&V)" instead. On further reflection, that wouldn't work properly when T=int, for example, as the ImmutableList would have an intrusive linked list node for the '5' element whose doesn't match the '5' you just passed in (from the stack). Nick > Finally, are you sure that doing an O(n) scan is OK for your use case? > I'll take your word for it if it's really the right thing to do, but > just having this may encourage poor algorithm choices by others. > > As an alternative, how about a function which takes a T* and returns the > ImmutableList::iterator pointing to the right element or the end() > iterator if it's not a member? > > Do you have commit access? > > Nick > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rdivacky at freebsd.org Tue Jul 5 07:22:51 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 5 Jul 2011 14:22:51 +0200 Subject: [llvm-commits] [PATCH]: don't use MO_DARWIN_STUB on non-darwin Message-ID: <20110705122251.GA23536@freebsd.org> Hi, In the PPC backend there's this flag MO_DARWIN_STUB that should be set on Darwin < 10.5. The condition to set it is wrong imho. The attached patch fixes it. With the patch I am able to build dynamic libraries that links on FreeBSD (because the flag should not be set there). In the patch I basically change if ((!MacOSX || (MacOSXVersion < 10.5) to if ((MacOSX && (MacOSXVersion < 10.5) OK to commit? Or is there some hidden magic behind this that I dont see? roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ppc-darwin.patch Type: text/x-diff Size: 1164 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/969659e8/attachment.bin From bigcheesegs at gmail.com Tue Jul 5 09:48:59 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 05 Jul 2011 14:48:59 -0000 Subject: [llvm-commits] [llvm] r134408 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20110705144859.608652A6C12C@llvm.org> Author: mspencer Date: Tue Jul 5 09:48:59 2011 New Revision: 134408 URL: http://llvm.org/viewvc/llvm-project?rev=134408&view=rev Log: Fix warnings. Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134408&r1=134407&r2=134408&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 09:48:59 2011 @@ -117,7 +117,7 @@ error_code COFFObjectFile::getSymbolAddress(DataRefImpl Symb, uint64_t &Result) const { const coff_symbol *symb = toSymb(Symb); - const coff_section *Section; + const coff_section *Section = NULL; if (error_code ec = getSection(symb->SectionNumber, Section)) return ec; char Type; @@ -138,7 +138,7 @@ // in the same section as this symbol, and looking for either the next // symbol, or the end of the section. const coff_symbol *symb = toSymb(Symb); - const coff_section *Section; + const coff_section *Section = NULL; if (error_code ec = getSection(symb->SectionNumber, Section)) return ec; char Type; @@ -171,7 +171,7 @@ uint32_t Characteristics = 0; if (symb->SectionNumber > 0) { - const coff_section *Section; + const coff_section *Section = NULL; if (error_code ec = getSection(symb->SectionNumber, Section)) return ec; Characteristics = Section->Characteristics; From bigcheesegs at gmail.com Tue Jul 5 09:49:08 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 05 Jul 2011 14:49:08 -0000 Subject: [llvm-commits] [llvm] r134409 - /llvm/trunk/include/llvm/Object/ObjectFile.h Message-ID: <20110705144908.97E4D2A6C12C@llvm.org> Author: mspencer Date: Tue Jul 5 09:49:08 2011 New Revision: 134409 URL: http://llvm.org/viewvc/llvm-project?rev=134409&view=rev Log: Fix 80-col. Modified: llvm/trunk/include/llvm/Object/ObjectFile.h Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=134409&r1=134408&r2=134409&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Tue Jul 5 09:49:08 2011 @@ -44,7 +44,10 @@ const ObjectFile *OwningObject; public: - RelocationRef() : OwningObject(NULL) { std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl)); } + RelocationRef() : OwningObject(NULL) { + std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl)); + } + RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner); bool operator==(const RelocationRef &Other) const; @@ -59,7 +62,10 @@ const ObjectFile *OwningObject; public: - SymbolRef() : OwningObject(NULL) { std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); } + SymbolRef() : OwningObject(NULL) { + std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); + } + SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner); bool operator==(const SymbolRef &Other) const; @@ -86,7 +92,10 @@ const ObjectFile *OwningObject; public: - SectionRef() : OwningObject(NULL) { std::memset(&SectionPimpl, 0, sizeof(SectionPimpl)); } + SectionRef() : OwningObject(NULL) { + std::memset(&SectionPimpl, 0, sizeof(SectionPimpl)); + } + SectionRef(DataRefImpl SectionP, const ObjectFile *Owner); bool operator==(const SectionRef &Other) const; From grosser at fim.uni-passau.de Tue Jul 5 10:23:26 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:26 -0500 Subject: [llvm-commits] [PATCH 0/6] Cleanup DisplayGraph and make F->viewCFG() non-blocking Message-ID: Hi, while debugging I figured out that the F->viewCFG() function blocks until the graph viewer is closed. This is anoying, as I often would like to keep the graph open while I continue my debugging session. To solve this problem I looked into the DisplayGraph function and figured out that displaying a graph without waiting for the viewer to return was already available, but hidden between lines of redundant code and many preprocessor macros. The feature was also only available for a single graph viewer (ghostview). This patchset restructures the DisplayGraph function such that it is more readable and that common code is actually shared between the different viewers. It also adds support for non-blocking graph viewing for all viewers. The last patch enables this non-blocking behaviour for the F->viewCFG() function, but keeps the blocking behaviour of 'opt -view-cfg'. Besides the size of the patches, almost all do not intend any functional changes. If, because of missing test cases, a small bug slipped in, it should be easy to understand and fix. Just bug me, if DisplayGraph starts to act weird. OK to commit? Tobi Tobias Grosser (6): Use a separate function to get graph viewer path Use a separate function to translate from dot to ps DisplayGraph: Delete dot file earlier Use a separate function to select the graph viewer DisplayGraph: Unify code of the different viewers F->viewCFG() does not wait any more. include/llvm/Support/GraphWriter.h | 14 ++- lib/Analysis/CFGPrinter.cpp | 14 ++- lib/Support/GraphWriter.cpp | 207 ++++++++++++++++++++++-------------- 3 files changed, 147 insertions(+), 88 deletions(-) From grosser at fim.uni-passau.de Tue Jul 5 10:23:27 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:27 -0500 Subject: [llvm-commits] [PATCH 1/6] Use a separate function to get graph viewer path In-Reply-To: References: Message-ID: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> This reduces the size of the DisplayGraph function, moves many preprocessor macros out of the main function and is a step to our long term goal of detecting the graph viewer at run time. No functional change intended. --- include/llvm/Support/GraphWriter.h | 8 ++++ lib/Support/GraphWriter.cpp | 68 ++++++++++++++++++++++++++--------- 2 files changed, 58 insertions(+), 18 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Use-a-separate-function-to-get-graph-viewer-path.patch Type: text/x-patch Size: 5067 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/fbc73aeb/attachment.bin From grosser at fim.uni-passau.de Tue Jul 5 10:23:28 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:28 -0500 Subject: [llvm-commits] [PATCH 2/6] Use a separate function to translate from dot to ps In-Reply-To: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> References: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> Message-ID: This reduces the size of the DisplayGraph function quite a bit. No functional change intended. --- lib/Support/GraphWriter.cpp | 130 +++++++++++++++++++++++-------------------- 1 files changed, 70 insertions(+), 60 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Use-a-separate-function-to-translate-from-dot-to-ps.patch Type: text/x-patch Size: 4196 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/61ed3491/attachment.bin From grosser at fim.uni-passau.de Tue Jul 5 10:23:30 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:30 -0500 Subject: [llvm-commits] [PATCH 4/6] Use a separate function to select the graph viewer In-Reply-To: References: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> Message-ID: This moves all the compile time decisions in a single function. Later this function can be enhanced such that we can select the graph viewer at run time. No functional change intended. --- include/llvm/Support/GraphWriter.h | 3 +- lib/Support/GraphWriter.cpp | 167 ++++++++++++++++++++--------------- 2 files changed, 97 insertions(+), 73 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0004-Use-a-separate-function-to-select-the-graph-viewer.patch Type: text/x-patch Size: 7106 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/f49d6028/attachment.bin From grosser at fim.uni-passau.de Tue Jul 5 10:23:29 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:29 -0500 Subject: [llvm-commits] [PATCH 3/6] DisplayGraph: Delete dot file earlier In-Reply-To: References: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> Message-ID: We delete the dot file as early as possible to unify the control flow. --- lib/Support/GraphWriter.cpp | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-DisplayGraph-Delete-dot-file-earlier.patch Type: text/x-patch Size: 1385 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/79bf93f1/attachment.bin From grosser at fim.uni-passau.de Tue Jul 5 10:23:32 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:32 -0500 Subject: [llvm-commits] [PATCH 6/6] F->viewCFG() does not wait any more. In-Reply-To: <8e8a89a999f46e0a7a8de48c4fc7dcde4940ab7e.1309878809.git.tobias@grosser.es> References: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> <8e8a89a999f46e0a7a8de48c4fc7dcde4940ab7e.1309878809.git.tobias@grosser.es> Message-ID: <6286526c717311b23fd599dd8ee8985d00fb26ad.1309878809.git.tobias@grosser.es> F->viewCFG() is mainly used from the debugger. There it is often useful to keep the graph available, while continuing debugging. Hence, we do not want to wait until the graph viewer is closed, but return immediately. This patch does not change the blocking behaviour of 'opt -view-cfg'. --- include/llvm/Support/GraphWriter.h | 5 +++-- lib/Analysis/CFGPrinter.cpp | 14 ++++++++++---- 2 files changed, 13 insertions(+), 6 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0006-F-viewCFG-does-not-wait-any-more.patch Type: text/x-patch Size: 2294 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/4954e3e5/attachment-0001.bin From grosser at fim.uni-passau.de Tue Jul 5 10:23:31 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 5 Jul 2011 10:23:31 -0500 Subject: [llvm-commits] [PATCH 5/6] DisplayGraph: Unify code of the different viewers In-Reply-To: References: <9d9a58fec4ac3a272dd94e4adfb1c2a523cc23dd.1309878809.git.tobias@grosser.es> Message-ID: <8e8a89a999f46e0a7a8de48c4fc7dcde4940ab7e.1309878809.git.tobias@grosser.es> Restructure the code, such that code that needs to be executed for all viewers is shared. This patch also adds the 'wait' feature to all viewers. This feature was previously only implemented for ghostview. --- lib/Support/GraphWriter.cpp | 101 +++++++++++++++++-------------------------- 1 files changed, 40 insertions(+), 61 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-DisplayGraph-Unify-code-of-the-different-viewers.patch Type: text/x-patch Size: 4299 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/b9d0ec35/attachment-0001.bin From stoklund at 2pi.dk Tue Jul 5 10:38:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 05 Jul 2011 15:38:37 -0000 Subject: [llvm-commits] [llvm] r134412 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110705153837.B5E3B2A6C12C@llvm.org> Author: stoklund Date: Tue Jul 5 10:38:37 2011 New Revision: 134412 URL: http://llvm.org/viewvc/llvm-project?rev=134412&view=rev Log: Tweak comment and debug output. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134412&r1=134411&r2=134412&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jul 5 10:38:37 2011 @@ -958,7 +958,8 @@ // // ~ Interference after last use. // |---o---o--o| Live-out on stack, late last use. - // =========____ Copy to stack after LSP, overlap MainIntv. + // ============ Copy to stack after LSP, overlap MainIntv. + // \_____ Stack interval is live-out. // if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) { assert(RegIn && "Stack-in, stack-out should already be handled"); @@ -998,8 +999,8 @@ // The interference is overlapping somewhere we wanted to use MainIntv. That // means we need to create a local interval that can be allocated a // different register. - DEBUG(dbgs() << ", creating local interval.\n"); unsigned LocalIntv = SE->openIntv(); + DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n"); // We may be creating copies directly between MainIntv and LocalIntv, // bypassing the stack interval. When we do that, we should never use the From stoklund at 2pi.dk Tue Jul 5 10:38:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 05 Jul 2011 15:38:41 -0000 Subject: [llvm-commits] [llvm] r134413 - in /llvm/trunk: lib/CodeGen/InlineSpiller.cpp lib/CodeGen/LiveRangeEdit.cpp test/CodeGen/X86/crash.ll Message-ID: <20110705153841.399C52A6C12E@llvm.org> Author: stoklund Date: Tue Jul 5 10:38:41 2011 New Revision: 134413 URL: http://llvm.org/viewvc/llvm-project?rev=134413&view=rev Log: Fix PR10277. Remat during spilling triggers dead code elimination. If a phi-def becomes unused, that may also cause live ranges to split into separate connected components. This type of splitting is different from normal live range splitting. In particular, there may not be a common original interval. When the split range is its own original, make sure that the new siblings are also their own originals. The range being split cannot be used as an original since it doesn't cover the new siblings. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp llvm/trunk/test/CodeGen/X86/crash.ll Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=134413&r1=134412&r2=134413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Jul 5 10:38:41 2011 @@ -425,6 +425,7 @@ // Check possible sibling copies. if (VNI->isPHIDef() || VNI->getCopy()) { VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def); + assert(OrigVNI && "Def outside original live range"); if (OrigVNI->def != VNI->def) DefMI = traceSiblingValue(Reg, VNI, OrigVNI); } Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=134413&r1=134412&r2=134413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Tue Jul 5 10:38:41 2011 @@ -298,10 +298,16 @@ if (NumComp <= 1) continue; ++NumFracRanges; + bool IsOriginal = VRM.getOriginal(LI->reg) == LI->reg; DEBUG(dbgs() << NumComp << " components: " << *LI << '\n'); SmallVector Dups(1, LI); for (unsigned i = 1; i != NumComp; ++i) { Dups.push_back(&createFrom(LI->reg, LIS, VRM)); + // If LI is an original interval that hasn't been split yet, make the new + // intervals their own originals instead of referring to LI. The original + // interval must contain all the split products, and LI doesn't. + if (IsOriginal) + VRM.setIsSplitFromReg(Dups.back()->reg, 0); if (delegate_) delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg); } Modified: llvm/trunk/test/CodeGen/X86/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/crash.ll?rev=134413&r1=134412&r2=134413&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/crash.ll (original) +++ llvm/trunk/test/CodeGen/X86/crash.ll Tue Jul 5 10:38:41 2011 @@ -215,3 +215,104 @@ } declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +; PR10277 +; This test has dead code elimination caused by remat during spilling. +; DCE causes a live interval to break into connected components. +; One of the components is spilled. + +%t2 = type { i8 } +%t9 = type { %t10 } +%t10 = type { %t11 } +%t11 = type { %t12 } +%t12 = type { %t13*, %t13*, %t13* } +%t13 = type { %t14*, %t15, %t15 } +%t14 = type opaque +%t15 = type { i8, i32, i32 } +%t16 = type { %t17, i8* } +%t17 = type { %t18 } +%t18 = type { %t19 } +%t19 = type { %t20*, %t20*, %t20* } +%t20 = type { i32, i32 } +%t21 = type { %t13* } + +define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { +bb: + %tmp = load %t9** undef, align 4, !tbaa !0 + %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 + %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 + br label %bb4 + +bb4: ; preds = %bb37, %bb + %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ] + %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ] + br i1 undef, label %bb34, label %bb7 + +bb7: ; preds = %bb4 + %tmp8 = load i32* undef, align 4 + %tmp9 = and i96 %tmp6, 4294967040 + %tmp10 = zext i32 %tmp8 to i96 + %tmp11 = shl nuw nsw i96 %tmp10, 32 + %tmp12 = or i96 %tmp9, %tmp11 + %tmp13 = or i96 %tmp12, 1 + %tmp14 = load i32* undef, align 4 + %tmp15 = and i96 %tmp5, 4294967040 + %tmp16 = zext i32 %tmp14 to i96 + %tmp17 = shl nuw nsw i96 %tmp16, 32 + %tmp18 = or i96 %tmp15, %tmp17 + %tmp19 = or i96 %tmp18, 1 + %tmp20 = load i8* undef, align 1 + %tmp21 = and i8 %tmp20, 1 + %tmp22 = icmp ne i8 %tmp21, 0 + %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13 + %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19 + store i96 %tmp24, i96* undef, align 4 + %tmp25 = load %t13** %tmp3, align 4 + %tmp26 = icmp eq %t13* %tmp25, undef + br i1 %tmp26, label %bb28, label %bb27 + +bb27: ; preds = %bb7 + br label %bb29 + +bb28: ; preds = %bb7 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb29 + +bb29: ; preds = %bb28, %bb27 + store i96 %tmp23, i96* undef, align 4 + %tmp30 = load %t13** %tmp3, align 4 + br i1 false, label %bb33, label %bb31 + +bb31: ; preds = %bb29 + %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1 + store %t13* %tmp32, %t13** %tmp3, align 4 + br label %bb37 + +bb33: ; preds = %bb29 + unreachable + +bb34: ; preds = %bb4 + br i1 undef, label %bb36, label %bb35 + +bb35: ; preds = %bb34 + store %t13* null, %t13** %tmp3, align 4 + br label %bb37 + +bb36: ; preds = %bb34 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb37 + +bb37: ; preds = %bb36, %bb35, %bb31 + %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ] + %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ] + %tmp40 = add i32 undef, 1 + br label %bb4 +} + +declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) + +declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind + +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind From grosbach at apple.com Tue Jul 5 11:05:50 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 05 Jul 2011 16:05:50 -0000 Subject: [llvm-commits] [llvm] r134415 - /llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Message-ID: <20110705160550.AC7722A6C12C@llvm.org> Author: grosbach Date: Tue Jul 5 11:05:50 2011 New Revision: 134415 URL: http://llvm.org/viewvc/llvm-project?rev=134415&view=rev Log: ARM estimateStackSize() needs to account for simplified call frames. If the function allocates reserved stack space for callee argument frames, estimateStackSize() needs to account for that, as it doesn't show up as ordinary frame objects. Otherwise, a callee with a large argument list will throw off the calculations for whether to allocate an emergency spill slot and we get assert() failures in the register scavenger. rdar://9715469 Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134415&r1=134414&r2=134415&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Jul 5 11:05:50 2011 @@ -739,20 +739,52 @@ /// estimateStackSize - Estimate and return the size of the frame. /// FIXME: Make generic? static unsigned estimateStackSize(MachineFunction &MF) { - const MachineFrameInfo *FFI = MF.getFrameInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); + unsigned MaxAlign = MFI->getMaxAlignment(); int Offset = 0; - for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { - int FixedOff = -FFI->getObjectOffset(i); + + // This code is very, very similar to PEI::calculateFrameObjectOffsets(). + // It really should be refactored to share code. Until then, changes + // should keep in mind that there's tight coupling between the two. + + for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) { + int FixedOff = -MFI->getObjectOffset(i); if (FixedOff > Offset) Offset = FixedOff; } - for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { - if (FFI->isDeadObjectIndex(i)) + for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { + if (MFI->isDeadObjectIndex(i)) continue; - Offset += FFI->getObjectSize(i); - unsigned Align = FFI->getObjectAlignment(i); + Offset += MFI->getObjectSize(i); + unsigned Align = MFI->getObjectAlignment(i); // Adjust to alignment boundary Offset = (Offset+Align-1)/Align*Align; + + MaxAlign = std::max(Align, MaxAlign); } + + if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF)) + Offset += MFI->getMaxCallFrameSize(); + + // Round up the size to a multiple of the alignment. If the function has + // any calls or alloca's, align to the target's StackAlignment value to + // ensure that the callee's frame or the alloca data is suitably aligned; + // otherwise, for leaf functions, align to the TransientStackAlignment + // value. + unsigned StackAlign; + if (MFI->adjustsStack() || MFI->hasVarSizedObjects() || + (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0)) + StackAlign = TFI->getStackAlignment(); + else + StackAlign = TFI->getTransientStackAlignment(); + + // If the frame pointer is eliminated, all frame offsets will be relative to + // SP not FP. Align to MaxAlign so this works. + StackAlign = std::max(StackAlign, MaxAlign); + unsigned AlignMask = StackAlign - 1; + Offset = (Offset + AlignMask) & ~uint64_t(AlignMask); + return (unsigned)Offset; } From bob.wilson at apple.com Tue Jul 5 11:15:47 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 05 Jul 2011 09:15:47 -0700 Subject: [llvm-commits] Built-in "expect" support In-Reply-To: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> References: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> Message-ID: <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> On Jul 2, 2011, at 6:00 PM, Jakub Staszak wrote: > Hello, > > This patch introduces built-in support. It uses llvm.expect intrinsics to create "branch_weights" metadata if run with -md-expect or with -O. > > Comments are welcome. I think the new "expect" intrinsic should be overloaded for all integer types, instead of being forced to i64 only. Although it should work OK without the overloading, I can imagine cases where the extra sign/zero-extends and truncates for i64 could change the way the code is optimized. Overloading it just seems like a better fit for how this intrinsic is used. Unless I missed something, this is your first patch using the "block_weights" metadata, and you haven't yet described the intended usage or format of that metadata. You'll need to provide those details and some documentation. For now, let's proceed with the understanding that everything about "block_weights" metadata is tentative and subject to change. The "expect" intrinsic should have the IntrNoMem property, not IntrReadArgMem. I think your new pass should run after early CSE. One of the reasons we decided to implement builtin_expect this way is to allow some simple propagation of builtin_expect calls that are not directly inside conditionals. You haven't implemented that yet, but early CSE should help when the time comes. The long methods in your MetadataExpect pass should be defined outside the class. The arbitrary constants "4" and "64" for likely and unlikely branch weights should not be used directly. These should be symbolic constants defined in the MetadataExpect class. Once we have more code using this, we may want to adjust those values. The "MetadataExpect" and "md-expect" names are not very descriptive of what the transform pass does, which is to convert expect intrinsics to block_weights metadata. I'll see if I can think of better alternatives -- let me know if you have ideas. Please add a comment for your change to IntrinsicLowering.cpp From rafael.espindola at gmail.com Tue Jul 5 11:45:37 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 05 Jul 2011 12:45:37 -0400 Subject: [llvm-commits] [llvm] r134413 - in /llvm/trunk: lib/CodeGen/InlineSpiller.cpp lib/CodeGen/LiveRangeEdit.cpp test/CodeGen/X86/crash.ll In-Reply-To: <20110705153841.399C52A6C12E@llvm.org> References: <20110705153841.399C52A6C12E@llvm.org> Message-ID: <4E133FB1.9010506@gmail.com> On 07/05/2011 11:38 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jul 5 10:38:41 2011 > New Revision: 134413 > > URL: http://llvm.org/viewvc/llvm-project?rev=134413&view=rev > Log: > Fix PR10277. > > Remat during spilling triggers dead code elimination. If a phi-def > becomes unused, that may also cause live ranges to split into separate > connected components. > > This type of splitting is different from normal live range splitting. In > particular, there may not be a common original interval. > > When the split range is its own original, make sure that the new > siblings are also their own originals. The range being split cannot be > used as an original since it doesn't cover the new siblings. > Thanks! I had just managed to produce a testcase without tail duplication :-) Do you have a reference on what was going on? Why do we track the original live interval when splitting? Cheers, Rafael From joerg at britannica.bec.de Tue Jul 5 11:51:10 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Tue, 5 Jul 2011 18:51:10 +0200 Subject: [llvm-commits] [PATCH 2/6] Use a separate function to translate from dot to ps In-Reply-To: References: Message-ID: <20110705165109.GA14428@britannica.bec.de> On Tue, Jul 05, 2011 at 10:23:28AM -0500, Tobias Grosser wrote: > + sys::Path prog; > + > + // Set default grapher > +#if HAVE_CIRCO > + prog = sys::Path(LLVM_PATH_CIRCO); > +#endif > +#if HAVE_TWOPI > + prog = sys::Path(LLVM_PATH_TWOPI); > +#endif > +#if HAVE_NEATO > + prog = sys::Path(LLVM_PATH_NEATO); > +#endif > +#if HAVE_FDP > + prog = sys::Path(LLVM_PATH_FDP); > +#endif > +#if HAVE_DOT > + prog = sys::Path(LLVM_PATH_DOT); > +#endif > + > + // Find which program the user wants > +#if HAVE_DOT > + if (program == GraphProgram::DOT) > + prog = sys::Path(LLVM_PATH_DOT); > +#endif > +#if (HAVE_FDP) > + if (program == GraphProgram::FDP) > + prog = sys::Path(LLVM_PATH_FDP); > +#endif > +#if (HAVE_NEATO) > + if (program == GraphProgram::NEATO) > + prog = sys::Path(LLVM_PATH_NEATO); > +#endif > +#if (HAVE_TWOPI) > + if (program == GraphProgram::TWOPI) > + prog = sys::Path(LLVM_PATH_TWOPI); > +#endif > +#if (HAVE_CIRCO) > + if (program == GraphProgram::CIRCO) > + prog = sys::Path(LLVM_PATH_CIRCO); > +#endif This is assigning prog at least twice. This should be a switch on program and default to dot/fdp/neato/twopi/circo without full path if it couldn't be found during installation. I would even argue that no full path should be hard-coded without a good reason, but that's a separate change. Joerg From atrick at apple.com Tue Jul 5 13:19:39 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 05 Jul 2011 18:19:39 -0000 Subject: [llvm-commits] [llvm] r134423 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110705181939.DAD2A2A6C12C@llvm.org> Author: atrick Date: Tue Jul 5 13:19:39 2011 New Revision: 134423 URL: http://llvm.org/viewvc/llvm-project?rev=134423&view=rev Log: indvars -disable-iv-rewrite: avoid multiple IVs in weird cases. Putting back the helper that I removed on 7/1 to do this right. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134423&r1=134422&r2=134423&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jul 5 13:19:39 2011 @@ -608,6 +608,8 @@ Instruction *NarrowDef, Instruction *WideDef); + const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); + Instruction *WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, Instruction *WideDef); @@ -704,6 +706,33 @@ return true; } +// GetWideRecurrence - Is this instruction potentially interesting from IVUsers' +// perspective after widening it's type? In other words, can the extend be +// safely hoisted out of the loop with SCEV reducing the value to a recurrence +// on the same loop. If so, return the sign or zero extended +// recurrence. Otherwise return NULL. +const SCEVAddRecExpr *WidenIV::GetWideRecurrence(Instruction *NarrowUse) { + if (!SE->isSCEVable(NarrowUse->getType())) + return 0; + + const SCEV *NarrowExpr = SE->getSCEV(NarrowUse); + if (SE->getTypeSizeInBits(NarrowExpr->getType()) + >= SE->getTypeSizeInBits(WideType)) { + // NarrowUse implicitly widens its operand. e.g. a gep with a narrow + // index. So don't follow this use. + return 0; + } + + const SCEV *WideExpr = IsSigned ? + SE->getSignExtendExpr(NarrowExpr, WideType) : + SE->getZeroExtendExpr(NarrowExpr, WideType); + const SCEVAddRecExpr *AddRec = dyn_cast(WideExpr); + if (!AddRec || AddRec->getLoop() != L) + return 0; + + return AddRec; +} + /// WidenIVUse - Determine whether an individual user of the narrow IV can be /// widened. If so, return the wide clone of the user. Instruction *WidenIV::WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, @@ -753,24 +782,7 @@ } // Does this user itself evaluate to a recurrence after widening? - const SCEVAddRecExpr *WideAddRec = 0; - if (SE->isSCEVable(NarrowUse->getType())) { - const SCEV *NarrowExpr = SE->getSCEV(NarrowUse); - if (SE->getTypeSizeInBits(NarrowExpr->getType()) - >= SE->getTypeSizeInBits(WideType)) { - // NarrowUse implicitly widens its operand. e.g. a gep with a narrow - // index. We have already extended the operand, so we're done. - return 0; - } - const SCEV *WideExpr = IsSigned ? - SE->getSignExtendExpr(NarrowExpr, WideType) : - SE->getZeroExtendExpr(NarrowExpr, WideType); - - // Only widen past values that evaluate to a recurrence in the same loop. - const SCEVAddRecExpr *AddRec = dyn_cast(WideExpr); - if (AddRec && AddRec->getLoop() == L) - WideAddRec = AddRec; - } + const SCEVAddRecExpr *WideAddRec = GetWideRecurrence(NarrowUse); if (!WideAddRec) { // This user does not evaluate to a recurence after widening, so don't // follow it. Instead insert a Trunc to kill off the original use, From eli.friedman at gmail.com Tue Jul 5 13:21:20 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 05 Jul 2011 18:21:20 -0000 Subject: [llvm-commits] [llvm] r134424 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-64.s Message-ID: <20110705182120.9A67D2A6C12C@llvm.org> Author: efriedma Date: Tue Jul 5 13:21:20 2011 New Revision: 134424 URL: http://llvm.org/viewvc/llvm-project?rev=134424&view=rev Log: Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134424&r1=134423&r2=134424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Jul 5 13:21:20 2011 @@ -710,23 +710,6 @@ } } - // FIXME: Hack to recognize vpclmuldq - if (PatchedName.startswith("vpclmul")) { - unsigned CLMULQuadWordSelect = StringSwitch( - PatchedName.slice(7, PatchedName.size() - 2)) - .Case("lqlq", 0x00) // src1[63:0], src2[63:0] - .Case("hqlq", 0x01) // src1[127:64], src2[63:0] - .Case("lqhq", 0x10) // src1[63:0], src2[127:64] - .Case("hqhq", 0x11) // src1[127:64], src2[127:64] - .Default(~0U); - if (CLMULQuadWordSelect != ~0U) { - ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect, - getParser().getContext()); - assert(PatchedName.endswith("dq") && "Unexpected mnemonic!"); - PatchedName = "vpclmulqdq"; - } - } - Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc)); if (ExtraImmOp) Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=134424&r1=134423&r2=134424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Tue Jul 5 13:21:20 2011 @@ -460,6 +460,11 @@ class CLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern> : Ii8, TA, + OpSize, Requires<[HasCLMUL]>; + +class AVXCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TA, OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>; // FMA3 Instruction Templates Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=134424&r1=134423&r2=134424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 5 13:21:20 2011 @@ -5195,33 +5195,52 @@ // CLMUL Instructions //===----------------------------------------------------------------------===// -// Only the AVX version of CLMUL instructions are described here. - // Carry-less Multiplication instructions -def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), +let Constraints = "$src1 = $dst" in { +def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, i8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + []>; + +def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, i8imm:$src3), + "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}", + []>; +} + +// AVX carry-less Multiplication instructions +def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>; -def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), +def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2, i8imm:$src3), "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>; -// Assembler Only -multiclass avx_vpclmul { - def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>; - - def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>; + +multiclass pclmul_alias { + def : InstAlias; + + def : InstAlias; + + def : InstAlias; + + def : InstAlias; } -defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">; -defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">; -defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">; -defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">; +defm : pclmul_alias<"hqhq", 0x11>; +defm : pclmul_alias<"hqlq", 0x01>; +defm : pclmul_alias<"lqhq", 0x10>; +defm : pclmul_alias<"lqlq", 0x00>; //===----------------------------------------------------------------------===// // AVX Instructions Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=134424&r1=134423&r2=134424&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Tue Jul 5 13:21:20 2011 @@ -1148,3 +1148,19 @@ // CHECK: movntiq movntiq %rax, (%rdi) movnti %rax, (%rdi) + +// CHECK: pclmulqdq $17, %xmm0, %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x11] +pclmulhqhqdq %xmm0, %xmm1 + +// CHECK: pclmulqdq $1, %xmm0, %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x01] +pclmulqdq $1, %xmm0, %xmm1 + +// CHECK: pclmulqdq $16, (%rdi), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x10] +pclmullqhqdq (%rdi), %xmm1 + +// CHECK: pclmulqdq $0, (%rdi), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x00] +pclmulqdq $0, (%rdi), %xmm1 From tobias at grosser.es Tue Jul 5 13:32:42 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 05 Jul 2011 13:32:42 -0500 Subject: [llvm-commits] [PATCH 2/6] Use a separate function to translate from dot to ps In-Reply-To: <20110705165109.GA14428@britannica.bec.de> References: <20110705165109.GA14428@britannica.bec.de> Message-ID: <4E1358CA.6030102@grosser.es> On 07/05/2011 11:51 AM, Joerg Sonnenberger wrote: > On Tue, Jul 05, 2011 at 10:23:28AM -0500, Tobias Grosser wrote: >> + sys::Path prog; >> + >> + // Set default grapher >> +#if HAVE_CIRCO >> + prog = sys::Path(LLVM_PATH_CIRCO); >> +#endif >> +#if HAVE_TWOPI >> + prog = sys::Path(LLVM_PATH_TWOPI); >> +#endif >> +#if HAVE_NEATO >> + prog = sys::Path(LLVM_PATH_NEATO); >> +#endif >> +#if HAVE_FDP >> + prog = sys::Path(LLVM_PATH_FDP); >> +#endif >> +#if HAVE_DOT >> + prog = sys::Path(LLVM_PATH_DOT); >> +#endif >> + >> + // Find which program the user wants >> +#if HAVE_DOT >> + if (program == GraphProgram::DOT) >> + prog = sys::Path(LLVM_PATH_DOT); >> +#endif >> +#if (HAVE_FDP) >> + if (program == GraphProgram::FDP) >> + prog = sys::Path(LLVM_PATH_FDP); >> +#endif >> +#if (HAVE_NEATO) >> + if (program == GraphProgram::NEATO) >> + prog = sys::Path(LLVM_PATH_NEATO); >> +#endif >> +#if (HAVE_TWOPI) >> + if (program == GraphProgram::TWOPI) >> + prog = sys::Path(LLVM_PATH_TWOPI); >> +#endif >> +#if (HAVE_CIRCO) >> + if (program == GraphProgram::CIRCO) >> + prog = sys::Path(LLVM_PATH_CIRCO); >> +#endif > > This is assigning prog at least twice. This should be a switch on > program and default to dot/fdp/neato/twopi/circo without full path if it > couldn't be found during installation. I would even argue that no full > path should be hard-coded without a good reason, but that's a separate > change. Hi Joerg, first of all, this is the existing code and the only thing I did was to move it into a separate function such that this code is split into smaller more understandable pieces. For this patch I would prefer to not touch the existing code to make it very clear that the comment "No functional change intended" actually holds. In general I fully agree with you that hardcoding paths is not a good idea. Making this change should be a lot easier, after the DisplayGraph function became a little bit more readable. In respect of replacing this chain of conditions with a switch, As stated before, I would prefer to not do this in this commit. I attached a patch that could be committed in a subsequent commit. This patch also does not change the behaviour, but changes only the style. The resulting code will be: switch (program) { #if HAVE_DOT case GraphProgram::DOT: prog = sys::Path(LLVM_PATH_DOT); break; #endif #if HAVE_FDP case GraphProgram::FDP: prog = sys::Path(LLVM_PATH_FDP); break; #endif #if HAVE_NEATO case GraphProgram::NEATO: prog = sys::Path(LLVM_PATH_NEATO); break; #endif #if HAVE_TWOPI case GraphProgram::TWOPI: prog = sys::Path(LLVM_PATH_TWOPI); break; #endif #if HAVE_CIRCO case GraphProgram::CIRCO: prog = sys::Path(LLVM_PATH_CIRCO); break; #endif default: #if HAVE_DOT prog = sys::Path(LLVM_PATH_DOT); #elif HAVE_FDP prog = sys::Path(LLVM_PATH_FDP); #elif HAVE_NEATO prog = sys::Path(LLVM_PATH_NEATO); #elif HAVE_TWOPI prog = sys::Path(LLVM_PATH_TWOPI); #elif HAVE_CIRCO prog = sys::Path(LLVM_PATH_CIRCO); #else llvm_unreachable("No graph program available"); #endif } Reducing/removing the use of absolute paths is not yet done. I agree this is something we want, however I have not yet thought enough about this to provide a robust patch. Tobi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0007-GraphWriter-Use-switch-for-chain-of-conditions.patch Type: text/x-diff Size: 2773 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/85b45479/attachment.bin From rafael.espindola at gmail.com Tue Jul 5 13:41:47 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 05 Jul 2011 18:41:47 -0000 Subject: [llvm-commits] [llvm] r134427 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20110705184147.E8F872A6C12C@llvm.org> Author: rafael Date: Tue Jul 5 13:41:47 2011 New Revision: 134427 URL: http://llvm.org/viewvc/llvm-project?rev=134427&view=rev Log: Compare all 4 bytes of the header. Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134427&r1=134426&r2=134427&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 13:41:47 2011 @@ -309,8 +309,9 @@ if (!checkSize(Data, ec, 0x3c + 8)) return; HeaderStart += *reinterpret_cast(base() + 0x3c); // Check the PE header. ("PE\0\0") - if (StringRef(reinterpret_cast(base() + HeaderStart), 4) - != "PE\0\0") { + StringRef Actual(reinterpret_cast(base() + HeaderStart), 4); + StringRef Expcted("PE\0\0", 4); + if (Actual != Expcted) { ec = object_error::parse_failed; return; } From stoklund at 2pi.dk Tue Jul 5 13:46:42 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 05 Jul 2011 18:46:42 -0000 Subject: [llvm-commits] [llvm] r134428 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110705184642.71F6B2A6C12C@llvm.org> Author: stoklund Date: Tue Jul 5 13:46:42 2011 New Revision: 134428 URL: http://llvm.org/viewvc/llvm-project?rev=134428&view=rev Log: Break infinite loop when the Hopfield network oscillates. This is impossible in theory, I can prove it. In practice, our near-zero threshold can cause the network to oscillate between equally good solutions. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134428&r1=134427&r2=134428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jul 5 13:46:42 2011 @@ -649,8 +649,6 @@ for (;;) { ArrayRef NewBundles = SpillPlacer->getRecentPositive(); - if (NewBundles.empty()) - break; // Find new through blocks in the periphery of PrefRegBundles. for (int i = 0, e = NewBundles.size(); i != e; ++i) { unsigned Bundle = NewBundles[i]; @@ -670,12 +668,12 @@ } } // Any new blocks to add? - if (ActiveBlocks.size() > AddedTo) { - ArrayRef Add(&ActiveBlocks[AddedTo], - ActiveBlocks.size() - AddedTo); - addThroughConstraints(Intf, Add); - AddedTo = ActiveBlocks.size(); - } + if (ActiveBlocks.size() == AddedTo) + break; + addThroughConstraints(Intf, + ArrayRef(ActiveBlocks).slice(AddedTo)); + AddedTo = ActiveBlocks.size(); + // Perhaps iterating can enable more bundles? SpillPlacer->iterate(); } From raghesh.a at gmail.com Tue Jul 5 13:51:34 2011 From: raghesh.a at gmail.com (Raghesh Aloor) Date: Tue, 05 Jul 2011 18:51:34 -0000 Subject: [llvm-commits] [polly] r134429 - in /polly/trunk/www: documentation.html documentation/memaccess.html Message-ID: <20110705185134.DD7CB2A6C12C@llvm.org> Author: raghesh Date: Tue Jul 5 13:51:34 2011 New Revision: 134429 URL: http://llvm.org/viewvc/llvm-project?rev=134429&view=rev Log: www: Updating memaccess documentation This is a complete rewrite to memaccess.html file. This removed some unwanted html tags. Modified: polly/trunk/www/documentation.html polly/trunk/www/documentation/memaccess.html Modified: polly/trunk/www/documentation.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation.html?rev=134429&r1=134428&r2=134429&view=diff ============================================================================== --- polly/trunk/www/documentation.html (original) +++ polly/trunk/www/documentation.html Tue Jul 5 13:51:34 2011 @@ -18,8 +18,8 @@ Modified: polly/trunk/www/documentation/memaccess.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=134429&r1=134428&r2=134429&view=diff ============================================================================== --- polly/trunk/www/documentation/memaccess.html (original) +++ polly/trunk/www/documentation/memaccess.html Tue Jul 5 13:51:34 2011 @@ -1,143 +1,87 @@ - + + - - memaccess.html + + Polly - Memory access optimizations + + -
Support -for -memory access -transformations in Polly
-
-
This project adds -memory access transformations to Polly. In many cases
-changing the memory access pattern yields to better data -locality or removes
-dependences that would otherwise block -transformations. They may also
-allow LLVM to use registers to store -certain values.
-
-
-An examples which uses this feature is given below
-
-

+ +
+ +

Polly - Memory access optimizations

+ +

WARNING: This project is part of the Google Summer of Code 2011. Hence, +it is currently not finished, but it is in the design and implementation stage. +The Ideas/Plans described here may not yet be implemented in Polly and may be +changed during the actual implementation.

+ +The project which adds memory access transformations to Polly. In many cases +changing the memory access pattern yields to better data locality or removes +dependences that would otherwise block transformations. + +

An examples which uses this feature is given below.

+ Consider the following loop -
    -
      -
    -
-
for -(i = 0; i < 8; i++)
-sum += A[i];
-
-
-With support for memory access transformation this loop can be executed
-in parallel. It can be -transformed to
-
-
-
<create -and -initialize an array 'tmp' -with size 4>
-for (i = 0; i < 8; i++) {
-tmp[i % 4] += A[i];
-}
-sum = tmp[0] + tmp[1] + tmp[2] -+ tmp[3];
-
-
-With the help of some optimizer (like -PluTo) the following code can be
-generated, where the outer loop is -parallel. -

parfor (ii = -0; ii < 4; ii++) {
-    tmp[ii] = 0;
-    for (i = ii * 2; i < (ii+1) * 2; i++)
-        tmp[ii] += A[i];

-

}
-sum = tmp[0] + tmp[1] + tmp[2] + -tmp[3];
-

-

TODO
-

-

Step 1
-

-Polly exports its polyhedral description in a JSCoP file. Define how -memory
-
layout transformations are going to be expressed in Polly and -in -the JSCOP file.
-A simple example is given below.
-
-Consider the following loop.
-
-
for -(i -= 0; i < 12; i++)
-     A[i] = 0;
-
-
-In the JSCOP file the memory is represented as follows.
-
-
   -"accesses": -[{
-           -"kind": -"write",
-           -"relation": -"{ -Stmt[i] -> A[i] -}"
-    }]
-
-
-Suppose -we want to perform a transformation such that the following
-code is generated
-
-
for -(i -= 0; i < 12; i++)
- -     A[0] = i;
-
-
-The corresponding JSCOP file represenation would be
-
-
    -"accesses": -[{
-           -"kind": -"read",
-           -"relation": -"{ -Stmt[i] -> A[0] -}"
-    }]
-
-
-We need to detect this access function change.
+
+for (i = 0; i < 8; i++)
+  sum += A[i];
+
+Through memory access transformations this loop can be executed in parallel. +It can be transformed to +
+// Create and initialize an array 'tmp' with size 4
+for (i = 0; i < 8; i++)
+  tmp[i % 4] += A[i];
+sum = tmp[0] + tmp[1] + tmp[2] + tmp[3];
+
+ +Optimizers like PluTo can schedule the code such that an outer, parallel +loop is created: +
+parfor (ii = 0; ii < 4; ii++) {
+  tmp[ii] = 0;
+  for (i = ii * 2; i < (ii+1) * 2; i++)
+    tmp[ii] += A[i];
+  }
+sum = tmp[0] + tmp[1] + tmp[2] + tmp[3];
+
+ +

TODO

+

Step 1

+Polly exports its polyhedral description in a JSCoP file. Define how memory +layout transformations are expressed in Polly and in the JSCOP file. +Example: + +

Consider the following loop.

+
+for (i = 0; i < 12; i++)
+  A[i] = 0;
+
+In the JSCOP file the memory accesses are represented as follows. +
+"accesses": [{
+        "kind": "write",
+                "relation": "{ Stmt[i] -> A[i] }"
+}]
+
+To perform a transformation we generate the following code: +
+for (i = 0; i < 12; i++)
+  A[0] = i;
+
+The representation in the JSCoP file is: +
+"accesses": [{
+        "kind": "read",
+                "relation": "{ Stmt[i] -> A[0] }"
+}]
+
+We need to detect this access function change.
- + From mcrosier at apple.com Tue Jul 5 13:55:31 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 05 Jul 2011 18:55:31 -0000 Subject: [llvm-commits] [llvm] r134430 - /llvm/trunk/lib/Support/Unix/Path.inc Message-ID: <20110705185531.F2B5B2A6C12C@llvm.org> Author: mcrosier Date: Tue Jul 5 13:55:31 2011 New Revision: 134430 URL: http://llvm.org/viewvc/llvm-project?rev=134430&view=rev Log: By default mkstemp() creates a temporary file with mode 0600, but the mode used for open is 0666. Therefore, add the necessary permission bits for consistency. rdar://8621462 Modified: llvm/trunk/lib/Support/Unix/Path.inc Modified: llvm/trunk/lib/Support/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Path.inc?rev=134430&r1=134429&r2=134430&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/Path.inc (original) +++ llvm/trunk/lib/Support/Unix/Path.inc Tue Jul 5 13:55:31 2011 @@ -842,6 +842,9 @@ // Save the name path = FNBuffer; + + // By default mkstemp sets the mode to 0600, so update mode bits now. + AddPermissionBits (*this, 0666); #elif defined(HAVE_MKTEMP) // If we don't have mkstemp, use the old and obsolete mktemp function. if (mktemp(FNBuffer) == 0) From dpatel at apple.com Tue Jul 5 13:58:22 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 05 Jul 2011 18:58:22 -0000 Subject: [llvm-commits] [llvm] r134431 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20110705185822.C89922A6C12C@llvm.org> Author: dpatel Date: Tue Jul 5 13:58:22 2011 New Revision: 134431 URL: http://llvm.org/viewvc/llvm-project?rev=134431&view=rev Log: Clear debug loc while updating insert point. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=134431&r1=134430&r2=134431&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Tue Jul 5 13:58:22 2011 @@ -73,6 +73,7 @@ void SetInsertPoint(BasicBlock *TheBB) { BB = TheBB; InsertPt = BB->end(); + CurDbgLocation = DebugLoc(); } /// SetInsertPoint - This specifies that created instructions should be From benny.kra at googlemail.com Tue Jul 5 14:08:30 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 5 Jul 2011 21:08:30 +0200 Subject: [llvm-commits] [llvm] r134427 - /llvm/trunk/lib/Object/COFFObjectFile.cpp In-Reply-To: <20110705184147.E8F872A6C12C@llvm.org> References: <20110705184147.E8F872A6C12C@llvm.org> Message-ID: On 05.07.2011, at 20:41, Rafael Espindola wrote: > Author: rafael > Date: Tue Jul 5 13:41:47 2011 > New Revision: 134427 > > URL: http://llvm.org/viewvc/llvm-project?rev=134427&view=rev > Log: > Compare all 4 bytes of the header. > > Modified: > llvm/trunk/lib/Object/COFFObjectFile.cpp > > Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134427&r1=134426&r2=134427&view=diff > ============================================================================== > --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) > +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 13:41:47 2011 > @@ -309,8 +309,9 @@ > if (!checkSize(Data, ec, 0x3c + 8)) return; > HeaderStart += *reinterpret_cast(base() + 0x3c); > // Check the PE header. ("PE\0\0") > - if (StringRef(reinterpret_cast(base() + HeaderStart), 4) > - != "PE\0\0") { > + StringRef Actual(reinterpret_cast(base() + HeaderStart), 4); > + StringRef Expcted("PE\0\0", 4); > + if (Actual != Expcted) { > ec = object_error::parse_failed; > return; > } Typo: Expcted also, a plain memcmp would be easier on the eyes if (std::memcmp(base() + HeaderStart, "PE\0\0", 4)) From grosser at fim.uni-passau.de Tue Jul 5 14:13:22 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 05 Jul 2011 19:13:22 -0000 Subject: [llvm-commits] [polly] r134432 - /polly/trunk/test/CodeGen/ Message-ID: <20110705191322.70EF52A6C12C@llvm.org> Author: grosser Date: Tue Jul 5 14:13:21 2011 New Revision: 134432 URL: http://llvm.org/viewvc/llvm-project?rev=134432&view=rev Log: test: Do not pipe the .ll file into opt The construct '< %s' complicates debugging with gdb --args as the content of %s is interpreted as gdb input. Modified: polly/trunk/test/CodeGen/20100617.ll polly/trunk/test/CodeGen/20100622.ll polly/trunk/test/CodeGen/20100707.ll polly/trunk/test/CodeGen/20100707_2.ll polly/trunk/test/CodeGen/20100708.ll polly/trunk/test/CodeGen/20100708_2.ll polly/trunk/test/CodeGen/20100713.ll polly/trunk/test/CodeGen/20100713_2.ll polly/trunk/test/CodeGen/20100717.ll polly/trunk/test/CodeGen/20100718-DomInfo-2.ll polly/trunk/test/CodeGen/20100718-DomInfo.ll polly/trunk/test/CodeGen/20100720-MultipleConditions.ll polly/trunk/test/CodeGen/PHIInExit.ll polly/trunk/test/CodeGen/do_pluto_matmult.ll polly/trunk/test/CodeGen/loop_with_condition.ll polly/trunk/test/CodeGen/loop_with_condition_ineq.ll polly/trunk/test/CodeGen/loop_with_condition_nested.ll polly/trunk/test/CodeGen/pluto_matmult.ll polly/trunk/test/CodeGen/reduction.ll polly/trunk/test/CodeGen/reduction_2.ll polly/trunk/test/CodeGen/scev.ll polly/trunk/test/CodeGen/sequential_loops.ll polly/trunk/test/CodeGen/single_do_loop_int_max_iterations.ll polly/trunk/test/CodeGen/single_do_loop_int_param_iterations.ll polly/trunk/test/CodeGen/single_do_loop_ll_max_iterations.ll polly/trunk/test/CodeGen/single_do_loop_one_iteration.ll polly/trunk/test/CodeGen/single_do_loop_scev_replace.ll polly/trunk/test/CodeGen/single_loop.ll polly/trunk/test/CodeGen/single_loop_int_max_iterations.ll polly/trunk/test/CodeGen/single_loop_ll_max_iterations.ll polly/trunk/test/CodeGen/single_loop_one_iteration.ll polly/trunk/test/CodeGen/single_loop_param.ll polly/trunk/test/CodeGen/single_loop_uint_max_iterations.ll polly/trunk/test/CodeGen/single_loop_ull_max_iterations.ll polly/trunk/test/CodeGen/single_loop_zero_iterations.ll polly/trunk/test/CodeGen/test.ll Modified: polly/trunk/test/CodeGen/20100617.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100617.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100617.ll (original) +++ polly/trunk/test/CodeGen/20100617.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'a' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100622.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100622.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100622.ll (original) +++ polly/trunk/test/CodeGen/20100622.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; RUN: opt %loadPolly %defaultOpts -polly-detect -analyze %s | not FileCheck %s ; ModuleID = 'a' Modified: polly/trunk/test/CodeGen/20100707.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100707.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100707.ll (original) +++ polly/trunk/test/CodeGen/20100707.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'a' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100707_2.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100707_2.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100707_2.ll (original) +++ polly/trunk/test/CodeGen/20100707_2.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100708.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100708.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100708.ll (original) +++ polly/trunk/test/CodeGen/20100708.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-detect < %s +; RUN: opt %loadPolly %defaultOpts -polly-detect %s ; ModuleID = '/tmp/bug.ll' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100708_2.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100708_2.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100708_2.ll (original) +++ polly/trunk/test/CodeGen/20100708_2.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = '/home/grosser/Projekte/polly/git/tools/polly/test/CodeGen/20100708_2.ll' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/20100713.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100713.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100713.ll (original) +++ polly/trunk/test/CodeGen/20100713.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100713_2.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100713_2.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100713_2.ll (original) +++ polly/trunk/test/CodeGen/20100713_2.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100717.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100717.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100717.ll (original) +++ polly/trunk/test/CodeGen/20100717.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen -disable-output < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -disable-output %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100718-DomInfo-2.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100718-DomInfo-2.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100718-DomInfo-2.ll (original) +++ polly/trunk/test/CodeGen/20100718-DomInfo-2.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen -verify-dom-info -disable-output < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -verify-dom-info -disable-output %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100718-DomInfo.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100718-DomInfo.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100718-DomInfo.ll (original) +++ polly/trunk/test/CodeGen/20100718-DomInfo.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen -verify-dom-info -disable-output < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -verify-dom-info -disable-output %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/20100720-MultipleConditions.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/20100720-MultipleConditions.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/20100720-MultipleConditions.ll (original) +++ polly/trunk/test/CodeGen/20100720-MultipleConditions.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s ; ModuleID = '20100720-MultipleConditions.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/PHIInExit.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/PHIInExit.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/PHIInExit.ll (original) +++ polly/trunk/test/CodeGen/PHIInExit.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/do_pluto_matmult.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/do_pluto_matmult.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/do_pluto_matmult.ll (original) +++ polly/trunk/test/CodeGen/do_pluto_matmult.ll Tue Jul 5 14:13:21 2011 @@ -1,11 +1,11 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen -disable-output < %s -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze < %s | FileCheck -check-prefix=IMPORT %s -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-import-jscop-postfix=valid_reverse -polly-cloog -analyze < %s | FileCheck -check-prefix=REVERSE %s > /dev/null -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-import-jscop-postfix=invalid_reverse -polly-cloog -analyze < %s 2>&1 | FileCheck -check-prefix=INVALID %s > /dev/null -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze < %s | FileCheck -check-prefix=IMPORT %s -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-codegen < %s | lli | diff %s.result - -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-codegen -S < %s | FileCheck -check-prefix=CODEGEN %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -disable-output %s +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze %s | FileCheck -check-prefix=IMPORT %s +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-import-jscop-postfix=valid_reverse -polly-cloog -analyze %s | FileCheck -check-prefix=REVERSE %s > /dev/null +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-import-jscop-postfix=invalid_reverse -polly-cloog -analyze %s 2>&1 | FileCheck -check-prefix=INVALID %s > /dev/null +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze %s | FileCheck -check-prefix=IMPORT %s +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-codegen %s | lli | diff %s.result - +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-codegen -S %s | FileCheck -check-prefix=CODEGEN %s ; ModuleID = 'do_pluto_matmult.s' Modified: polly/trunk/test/CodeGen/loop_with_condition.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/loop_with_condition.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/loop_with_condition.ll (original) +++ polly/trunk/test/CodeGen/loop_with_condition.ll Tue Jul 5 14:13:21 2011 @@ -1,6 +1,6 @@ ; ModuleID = 'loop_with_condition.s' -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/loop_with_condition_ineq.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/loop_with_condition_ineq.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/loop_with_condition_ineq.ll (original) +++ polly/trunk/test/CodeGen/loop_with_condition_ineq.ll Tue Jul 5 14:13:21 2011 @@ -1,6 +1,6 @@ ; ModuleID = 'loop_with_condition_ineq.s' -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/loop_with_condition_nested.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/loop_with_condition_nested.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/loop_with_condition_nested.ll (original) +++ polly/trunk/test/CodeGen/loop_with_condition_nested.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli ; ModuleID = 'loop_with_condition_nested.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/pluto_matmult.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/pluto_matmult.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/pluto_matmult.ll (original) +++ polly/trunk/test/CodeGen/pluto_matmult.ll Tue Jul 5 14:13:21 2011 @@ -1,6 +1,6 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s > /dev/null -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze -S < %s | FileCheck -check-prefix=IMPORT %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s > /dev/null +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=`dirname %s` -polly-cloog -analyze -S %s | FileCheck -check-prefix=IMPORT %s ; ModuleID = 'pluto-matmul.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/reduction.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/reduction.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/reduction.ll (original) +++ polly/trunk/test/CodeGen/reduction.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-codegen -S < %s 2>&1 | not FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -S %s 2>&1 | not FileCheck %s ; RUN: opt %loadPolly %defaultOpts -polly-codegen | lli ; XFAIL: * ; ModuleID = 'reduction.s' Modified: polly/trunk/test/CodeGen/reduction_2.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/reduction_2.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/reduction_2.ll (original) +++ polly/trunk/test/CodeGen/reduction_2.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli ; ModuleID = 'reduction_2.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/scev.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/scev.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/scev.ll (original) +++ polly/trunk/test/CodeGen/scev.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-detect < %s +; RUN: opt %loadPolly %defaultOpts -polly-detect %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/sequential_loops.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/sequential_loops.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/sequential_loops.ll (original) +++ polly/trunk/test/CodeGen/sequential_loops.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli - +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli - ; ModuleID = 'sequential_loops.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/single_do_loop_int_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_do_loop_int_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_do_loop_int_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_do_loop_int_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,7 +1,7 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -O3 < %s | lli -; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 < %s | lli -; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=%d -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -O3 %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-import-jscop -polly-import-jscop-dir=%d -polly-codegen %s | lli ; ModuleID = 'single_do_loop_int_max_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/single_do_loop_int_param_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_do_loop_int_param_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_do_loop_int_param_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_do_loop_int_param_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze %s | FileCheck %s ; XFAIL: * ; ModuleID = 'single_do_loop_int_param_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_do_loop_ll_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_do_loop_ll_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_do_loop_ll_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_do_loop_ll_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 < %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 %s ; ModuleID = 'single_do_loop_ll_max_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/single_do_loop_one_iteration.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_do_loop_one_iteration.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_do_loop_one_iteration.ll (original) +++ polly/trunk/test/CodeGen/single_do_loop_one_iteration.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 %s | lli ; XFAIL: * ; ModuleID = 'single_do_loop_one_iteration.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_do_loop_scev_replace.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_do_loop_scev_replace.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_do_loop_scev_replace.ll (original) +++ polly/trunk/test/CodeGen/single_do_loop_scev_replace.ll Tue Jul 5 14:13:21 2011 @@ -1,6 +1,6 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts < %s | lli -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli ; ModuleID = 'single_do_loop_scev_replace.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/single_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop.ll (original) +++ polly/trunk/test/CodeGen/single_loop.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli - +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli - ; ModuleID = 'single_loop.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: polly/trunk/test/CodeGen/single_loop_int_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_int_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_int_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_loop_int_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 < %s | lli +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen -O3 %s | lli ; ModuleID = 'single_loop_int_max_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_loop_ll_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_ll_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_ll_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_loop_ll_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S %s | FileCheck %s ; ModuleID = 'single_loop_ll_max_iterations.s' ; Modified: polly/trunk/test/CodeGen/single_loop_one_iteration.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_one_iteration.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_one_iteration.ll (original) +++ polly/trunk/test/CodeGen/single_loop_one_iteration.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s ; ModuleID = 'single_loop_one_iteration.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_loop_param.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_param.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_param.ll (original) +++ polly/trunk/test/CodeGen/single_loop_param.ll Tue Jul 5 14:13:21 2011 @@ -1,5 +1,5 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze < %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-codegen < %s | lli - +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-codegen %s | lli - ; ModuleID = 'single_loop_param.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" Modified: polly/trunk/test/CodeGen/single_loop_uint_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_uint_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_uint_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_loop_uint_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze %s | FileCheck %s ; XFAIL: * ; ModuleID = 'single_loop_uint_max_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_loop_ull_max_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_ull_max_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_ull_max_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_loop_ull_max_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog-scop -S -analyze %s | FileCheck %s ; XFAIL: * ; ModuleID = 'single_loop_ull_max_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/single_loop_zero_iterations.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_zero_iterations.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/single_loop_zero_iterations.ll (original) +++ polly/trunk/test/CodeGen/single_loop_zero_iterations.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -polly-cloog -analyze -S %s | FileCheck %s ; ModuleID = 'single_loop_zero_iterations.s' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: polly/trunk/test/CodeGen/test.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/test.ll?rev=134432&r1=134431&r2=134432&view=diff ============================================================================== --- polly/trunk/test/CodeGen/test.ll (original) +++ polly/trunk/test/CodeGen/test.ll Tue Jul 5 14:13:21 2011 @@ -1,4 +1,4 @@ -; RUN: opt %loadPolly %defaultOpts -O3 -polly-cloog -analyze -S < %s | FileCheck %s +; RUN: opt %loadPolly %defaultOpts -O3 -polly-cloog -analyze -S %s | FileCheck %s ; XFAIL: * ; ModuleID = 'test.c' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" From rafael.espindola at gmail.com Tue Jul 5 14:13:27 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 05 Jul 2011 19:13:27 -0000 Subject: [llvm-commits] [llvm] r134433 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20110705191328.0169F2A6C12D@llvm.org> Author: rafael Date: Tue Jul 5 14:13:27 2011 New Revision: 134433 URL: http://llvm.org/viewvc/llvm-project?rev=134433&view=rev Log: Fix typo. Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134433&r1=134432&r2=134433&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 14:13:27 2011 @@ -310,8 +310,8 @@ HeaderStart += *reinterpret_cast(base() + 0x3c); // Check the PE header. ("PE\0\0") StringRef Actual(reinterpret_cast(base() + HeaderStart), 4); - StringRef Expcted("PE\0\0", 4); - if (Actual != Expcted) { + StringRef Expected("PE\0\0", 4); + if (Actual != Expect) { ec = object_error::parse_failed; return; } From grosser at fim.uni-passau.de Tue Jul 5 14:13:32 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 05 Jul 2011 19:13:32 -0000 Subject: [llvm-commits] [polly] r134434 - /polly/trunk/lib/CodeGeneration.cpp Message-ID: <20110705191332.2A6262A6C12C@llvm.org> Author: grosser Date: Tue Jul 5 14:13:31 2011 New Revision: 134434 URL: http://llvm.org/viewvc/llvm-project?rev=134434&view=rev Log: CodeGen: Adapt to change of PHI operand storage Commit 133435 "Change how PHINodes store their operands" broke Polly. Fix this breakage by adapting to the changes in the commit. Modified: polly/trunk/lib/CodeGeneration.cpp Modified: polly/trunk/lib/CodeGeneration.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=134434&r1=134433&r2=134434&view=diff ============================================================================== --- polly/trunk/lib/CodeGeneration.cpp (original) +++ polly/trunk/lib/CodeGeneration.cpp Tue Jul 5 14:13:31 2011 @@ -727,9 +727,6 @@ PN = Statement->getInductionVariableForDimension(Dimension); const Value *V = PN; - if (PN->getNumOperands() == 2) - V = *(PN->use_begin()); - if (VectorVMap) (*VectorVMap)[vectorDim][V] = RHS; From grosser at fim.uni-passau.de Tue Jul 5 14:13:42 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 05 Jul 2011 19:13:42 -0000 Subject: [llvm-commits] [polly] r134435 - /polly/trunk/www/documentation/memaccess.html Message-ID: <20110705191342.0F7E32A6C12C@llvm.org> Author: grosser Date: Tue Jul 5 14:13:41 2011 New Revision: 134435 URL: http://llvm.org/viewvc/llvm-project?rev=134435&view=rev Log: www/memaccess: Fix forgotten typo Modified: polly/trunk/www/documentation/memaccess.html Modified: polly/trunk/www/documentation/memaccess.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=134435&r1=134434&r2=134435&view=diff ============================================================================== --- polly/trunk/www/documentation/memaccess.html (original) +++ polly/trunk/www/documentation/memaccess.html Tue Jul 5 14:13:41 2011 @@ -19,7 +19,7 @@ The Ideas/Plans described here may not yet be implemented in Polly and may be changed during the actual implementation.

-The project which adds memory access transformations to Polly. In many cases +This project adds memory access transformations to Polly. In many cases changing the memory access pattern yields to better data locality or removes dependences that would otherwise block transformations. From rafael.espindola at gmail.com Tue Jul 5 14:17:10 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 05 Jul 2011 19:17:10 -0000 Subject: [llvm-commits] [llvm] r134436 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20110705191710.83C662A6C12C@llvm.org> Author: rafael Date: Tue Jul 5 14:17:10 2011 New Revision: 134436 URL: http://llvm.org/viewvc/llvm-project?rev=134436&view=rev Log: Really fix typo :-( Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134436&r1=134435&r2=134436&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 14:17:10 2011 @@ -311,7 +311,7 @@ // Check the PE header. ("PE\0\0") StringRef Actual(reinterpret_cast(base() + HeaderStart), 4); StringRef Expected("PE\0\0", 4); - if (Actual != Expect) { + if (Actual != Expected) { ec = object_error::parse_failed; return; } From joerg at britannica.bec.de Tue Jul 5 15:11:34 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Tue, 5 Jul 2011 22:11:34 +0200 Subject: [llvm-commits] [PATCH 2/6] Use a separate function to translate from dot to ps In-Reply-To: <4E1358CA.6030102@grosser.es> References: <20110705165109.GA14428@britannica.bec.de> <4E1358CA.6030102@grosser.es> Message-ID: <20110705201134.GC8569@britannica.bec.de> On Tue, Jul 05, 2011 at 01:32:42PM -0500, Tobias Grosser wrote: > first of all, this is the existing code and the only thing I did was > to move it into a separate function such that this code is split > into smaller more understandable pieces. For this patch I would > prefer to not touch the existing code to make it very clear that the > comment "No functional change intended" actually holds. I don't believe much in shuffling code around and cleaning it up later. > In respect of replacing this chain of conditions with a switch, As > stated before, I would prefer to not do this in this commit. I > attached a patch that could be committed in a subsequent commit. > This patch also does not change the behaviour, but changes only the > style. The resulting code will be: > > switch (program) { > #if HAVE_DOT > case GraphProgram::DOT: prog = sys::Path(LLVM_PATH_DOT); break; > #endif > #if HAVE_FDP > case GraphProgram::FDP: prog = sys::Path(LLVM_PATH_FDP); break; > #endif > #if HAVE_NEATO > case GraphProgram::NEATO: prog = sys::Path(LLVM_PATH_NEATO); break; > #endif > #if HAVE_TWOPI > case GraphProgram::TWOPI: prog = sys::Path(LLVM_PATH_TWOPI); break; > #endif > #if HAVE_CIRCO > case GraphProgram::CIRCO: prog = sys::Path(LLVM_PATH_CIRCO); break; > #endif > default: > > #if HAVE_DOT > prog = sys::Path(LLVM_PATH_DOT); > #elif HAVE_FDP > prog = sys::Path(LLVM_PATH_FDP); > #elif HAVE_NEATO > prog = sys::Path(LLVM_PATH_NEATO); > #elif HAVE_TWOPI > prog = sys::Path(LLVM_PATH_TWOPI); > #elif HAVE_CIRCO > prog = sys::Path(LLVM_PATH_CIRCO); > #else > > llvm_unreachable("No graph program available"); > #endif > > } Go back a step and consider this code from the perspective of building binary packages. Why do I need to have graphviz installed at configure time of LLVM? This should just be switch (program) { case GraphProgram::DOT: prog = "dot"; break; case GraphProgram::FDP: prog = "fdp"; break; ... default: llvm_unreachable("Invalid graph program"); } If really necessary, make it possible to map the program to hard-coded path names, but I don't think that's very useful. In that case, it would certainly be much easier to specify the path to dot and use the -K option. Joerg From joerg at britannica.bec.de Tue Jul 5 15:17:32 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Tue, 5 Jul 2011 22:17:32 +0200 Subject: [llvm-commits] [llvm] r134430 - /llvm/trunk/lib/Support/Unix/Path.inc In-Reply-To: <20110705185531.F2B5B2A6C12C@llvm.org> References: <20110705185531.F2B5B2A6C12C@llvm.org> Message-ID: <20110705201732.GD8569@britannica.bec.de> On Tue, Jul 05, 2011 at 06:55:31PM -0000, Chad Rosier wrote: > Author: mcrosier > Date: Tue Jul 5 13:55:31 2011 > New Revision: 134430 > > URL: http://llvm.org/viewvc/llvm-project?rev=134430&view=rev > Log: > By default mkstemp() creates a temporary file with mode 0600, but the mode > used for open is 0666. Therefore, add the necessary permission bits for > consistency. > rdar://8621462 > > Modified: > llvm/trunk/lib/Support/Unix/Path.inc > > Modified: llvm/trunk/lib/Support/Unix/Path.inc > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Path.inc?rev=134430&r1=134429&r2=134430&view=diff > ============================================================================== > --- llvm/trunk/lib/Support/Unix/Path.inc (original) > +++ llvm/trunk/lib/Support/Unix/Path.inc Tue Jul 5 13:55:31 2011 > @@ -842,6 +842,9 @@ > > // Save the name > path = FNBuffer; > + > + // By default mkstemp sets the mode to 0600, so update mode bits now. > + AddPermissionBits (*this, 0666); > #elif defined(HAVE_MKTEMP) > // If we don't have mkstemp, use the old and obsolete mktemp function. > if (mktemp(FNBuffer) == 0) Isn't the correct approach the reverse? Make sure that all temporary files use the least permissible bits? Joerg From stoklund at 2pi.dk Tue Jul 5 15:19:20 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 05 Jul 2011 13:19:20 -0700 Subject: [llvm-commits] [llvm] r134413 - in /llvm/trunk: lib/CodeGen/InlineSpiller.cpp lib/CodeGen/LiveRangeEdit.cpp test/CodeGen/X86/crash.ll In-Reply-To: <4E133FB1.9010506@gmail.com> References: <20110705153841.399C52A6C12E@llvm.org> <4E133FB1.9010506@gmail.com> Message-ID: <1C8569D8-76B1-46B2-A241-E6DF94F01E4C@2pi.dk> On Jul 5, 2011, at 9:45 AM, Rafael ?vila de Esp?ndola wrote: > On 07/05/2011 11:38 AM, Jakob Stoklund Olesen wrote: >> Author: stoklund >> Date: Tue Jul 5 10:38:41 2011 >> New Revision: 134413 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134413&view=rev >> Log: >> Fix PR10277. >> >> Remat during spilling triggers dead code elimination. If a phi-def >> becomes unused, that may also cause live ranges to split into separate >> connected components. >> >> This type of splitting is different from normal live range splitting. In >> particular, there may not be a common original interval. >> >> When the split range is its own original, make sure that the new >> siblings are also their own originals. The range being split cannot be >> used as an original since it doesn't cover the new siblings. >> > > Thanks! > > I had just managed to produce a testcase without tail duplication :-) > > Do you have a reference on what was going on? Why do we track the > original live interval when splitting? It is used mostly by the spiller when hoisting spills. See InlineSpiller::traceSiblingValue and surrounding methods. /jakob From benny.kra at googlemail.com Tue Jul 5 15:28:00 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 05 Jul 2011 20:28:00 -0000 Subject: [llvm-commits] [llvm] r134439 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20110705202800.A7F7E2A6C12C@llvm.org> Author: d0k Date: Tue Jul 5 15:28:00 2011 New Revision: 134439 URL: http://llvm.org/viewvc/llvm-project?rev=134439&view=rev Log: Use memcmp. Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=134439&r1=134438&r2=134439&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Jul 5 15:28:00 2011 @@ -309,9 +309,7 @@ if (!checkSize(Data, ec, 0x3c + 8)) return; HeaderStart += *reinterpret_cast(base() + 0x3c); // Check the PE header. ("PE\0\0") - StringRef Actual(reinterpret_cast(base() + HeaderStart), 4); - StringRef Expected("PE\0\0", 4); - if (Actual != Expected) { + if (std::memcmp(base() + HeaderStart, "PE\0\0", 4) != 0) { ec = object_error::parse_failed; return; } From gkistanova at gmail.com Tue Jul 5 15:32:20 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 5 Jul 2011 13:32:20 -0700 Subject: [llvm-commits] New clang builder FreeBSD 8.2-RELEASE amd64 Message-ID: Hello everyone, New builder added to llvm.org buildbot. It's clang build running on FreeBSD 8.2-RELEASE amd64: http://google1.osuosl.org:8011/builders/clang-X86_64-freebsd Thanks Galina From pichet2000 at gmail.com Tue Jul 5 16:08:26 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Tue, 5 Jul 2011 17:08:26 -0400 Subject: [llvm-commits] [llvm] r134268 - in /llvm/trunk: lib/Analysis/IVUsers.cpp test/CodeGen/X86/lsr-nonaffine.ll In-Reply-To: References: <20110701220520.297C22A6C12C@llvm.org> Message-ID: On Fri, Jul 1, 2011 at 11:52 PM, Jakob Stoklund Olesen wrote: > > On Jul 1, 2011, at 8:17 PM, Francois Pichet wrote: > > +; CHECK: ? ? ? ?xorl %eax, %eax > > +; CHECK-NEXT: ? align > > +; CHECK-NEXT: BB0_1: > > +; CHECK-NEXT: ? movq ?%rax, (%rdx) > > +; CHECK-NEXT: ? addq ?%rsi, %rax > > +; CHECK-NEXT: ? cmpq ?%rdi, %rax > > +; CHECK-NEXT: ? jl > > +; CHECK-NEXT: ? imulq %rax, %rax > > +; CHECK-NEXT: ? ret > > This fails under MSVC: > The output is instead: > foo: > ???????xorl ???%eax, %eax > ???????.align ?16, 0x90 > .LBB0_1: > ???????movq ???%rax, (%r8) > ???????addq ???%rdx, %rax > ???????cmpq ???%rcx, %rax > ???????jl ?????.LBB0_1 > ???????imulq ??%rax, %rax > ???????ret > > Any idea? > > Unit tests should only mention explicit registers when a specific register > is required for correctness. > Otherwise, use FileCheck variables. > One of these days, I am going to add -regalloc=random? > /jakob > Interesting! I know close to nothing about register allocation algorithms but I am curious to know where does that nondeterminism comes from? From tobias at grosser.es Tue Jul 5 16:16:02 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 05 Jul 2011 16:16:02 -0500 Subject: [llvm-commits] [PATCH 2/6] Use a separate function to translate from dot to ps In-Reply-To: <20110705201134.GC8569@britannica.bec.de> References: <20110705165109.GA14428@britannica.bec.de> <4E1358CA.6030102@grosser.es> <20110705201134.GC8569@britannica.bec.de> Message-ID: <4E137F12.1010201@grosser.es> On 07/05/2011 03:11 PM, Joerg Sonnenberger wrote: > On Tue, Jul 05, 2011 at 01:32:42PM -0500, Tobias Grosser wrote: >> first of all, this is the existing code and the only thing I did was >> to move it into a separate function such that this code is split >> into smaller more understandable pieces. For this patch I would >> prefer to not touch the existing code to make it very clear that the >> comment "No functional change intended" actually holds. > > I don't believe much in shuffling code around and cleaning it up later. I believe very much in small, evolutionary changes - especially if there are no test cases available and I do not know why people implemented stuff the way it is today. The goal of these patches was to make the function more readable and to uniformly provide non-blocking behavior for all graph viewers, but to otherwise keep the current behavior and to not introducing any bugs. To achieve this, I tried to change as little as possible. >> In respect of replacing this chain of conditions with a switch, As >> stated before, I would prefer to not do this in this commit. I >> attached a patch that could be committed in a subsequent commit. >> This patch also does not change the behaviour, but changes only the >> style. The resulting code will be: >> >> switch (program) { >> #if HAVE_DOT >> case GraphProgram::DOT: prog = sys::Path(LLVM_PATH_DOT); break; >> #endif >> #if HAVE_FDP >> case GraphProgram::FDP: prog = sys::Path(LLVM_PATH_FDP); break; >> #endif >> #if HAVE_NEATO >> case GraphProgram::NEATO: prog = sys::Path(LLVM_PATH_NEATO); break; >> #endif >> #if HAVE_TWOPI >> case GraphProgram::TWOPI: prog = sys::Path(LLVM_PATH_TWOPI); break; >> #endif >> #if HAVE_CIRCO >> case GraphProgram::CIRCO: prog = sys::Path(LLVM_PATH_CIRCO); break; >> #endif >> default: >> >> #if HAVE_DOT >> prog = sys::Path(LLVM_PATH_DOT); >> #elif HAVE_FDP >> prog = sys::Path(LLVM_PATH_FDP); >> #elif HAVE_NEATO >> prog = sys::Path(LLVM_PATH_NEATO); >> #elif HAVE_TWOPI >> prog = sys::Path(LLVM_PATH_TWOPI); >> #elif HAVE_CIRCO >> prog = sys::Path(LLVM_PATH_CIRCO); >> #else >> >> llvm_unreachable("No graph program available"); >> #endif >> >> } > > Go back a step and consider this code from the perspective of building > binary packages. Why do I need to have graphviz installed at configure > time of LLVM? I do not know. I just know that it is like this today and there is no reason to change this, just because I want to provide a clean and consistent implementation for non-blocking F->viewCFG(). Those are orthogonal problems. Even though these are orthogonal problems I support your idea of not relying on absolute paths. Yet, I would prefer if we could tackle this, after these cleanup patches are committed. > switch (program) { > case GraphProgram::DOT: prog = "dot"; break; > case GraphProgram::FDP: prog = "fdp"; break; > ... > default: > llvm_unreachable("Invalid graph program"); > } Your code has no fallback if one of the graphviz tools is not available. This was available in the old code. As I personally do not use this part of the DisplayGraph code and do not know if someone else needs this, I would be afraid to remove this feature. > If really necessary, make it possible to map the program to hard-coded > path names, but I don't think that's very useful. In that case, it would > certainly be much easier to specify the path to dot and use the -K > option. As said above, I do not know why people implemented this the way it is today and how people use this feature. I would strongly prefer to not change anything, where I do not fully understand the requirements. If you are interested in triggering the absolute path problem, you may also want to look into the use of LLVM_PATH_GRAPHVIZ, LLVM_PATH_XDOT_PY, LLVM_PATH_GV and LLVM_PATH_DOTTY as well as the selection of the default graph viewer: static GraphViewProgram::Name selectGraphViewer() { #if HAVE_GRAPHVIZ return GraphViewProgram::GRAPHVIZ; #elif HAVE_XDOT_PY return GraphViewProgram::XDOT_PY; #elif (HAVE_GV && (HAVE_DOT || HAVE_FDP || HAVE_NEATO || HAVE_TWOPI || \ HAVE_CIRCO)) return GraphViewProgram::GV; #elif HAVE_DOTTY return GraphViewProgram::DOTTY; #else return GraphViewProgram::NONE; #endif } We most probably need to check for each of the different viewers if its available in the path and if it is executable. Then we need to remove the detection of the absolute paths from autoconf and cmake. And we may want to think about a way to select the graph viewer in case there are several viewers available. The current way to only provide the path for the viewer you want will not work any more. As these changes would probably increase this patchset quite a bit, I wonder if it is possible to commit my changes first and to trigger the absolute path problem afterwords. Cheers Tobi From dpatel at apple.com Tue Jul 5 16:16:28 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 05 Jul 2011 21:16:28 -0000 Subject: [llvm-commits] [llvm] r134440 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20110705211628.6CC422A6C12C@llvm.org> Author: dpatel Date: Tue Jul 5 16:16:28 2011 New Revision: 134440 URL: http://llvm.org/viewvc/llvm-project?rev=134440&view=rev Log: Speculatively revert r134431. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=134440&r1=134439&r2=134440&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Tue Jul 5 16:16:28 2011 @@ -73,7 +73,6 @@ void SetInsertPoint(BasicBlock *TheBB) { BB = TheBB; InsertPt = BB->end(); - CurDbgLocation = DebugLoc(); } /// SetInsertPoint - This specifies that created instructions should be From stoklund at 2pi.dk Tue Jul 5 16:19:43 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 05 Jul 2011 14:19:43 -0700 Subject: [llvm-commits] [llvm] r134268 - in /llvm/trunk: lib/Analysis/IVUsers.cpp test/CodeGen/X86/lsr-nonaffine.ll In-Reply-To: References: <20110701220520.297C22A6C12C@llvm.org> Message-ID: On Jul 5, 2011, at 2:08 PM, Francois Pichet wrote: > On Fri, Jul 1, 2011 at 11:52 PM, Jakob Stoklund Olesen wrote: >> Unit tests should only mention explicit registers when a specific register >> is required for correctness. >> Otherwise, use FileCheck variables. >> One of these days, I am going to add -regalloc=random? >> /jakob >> > > Interesting! I know close to nothing about register allocation > algorithms but I am curious to know where does that nondeterminism > comes from? It's not a non-determinism, Windows has different callee-saved registers, and therefore a different allocation order. However, there are many equally good solutions to the register allocation problem, and unit tests should not depend on what the register allocator happens to pick (deterministically) today. Takumi's fix of this test is not correct, a small change to the register allocator will break it again. See test/CodeGen/X86/abi-isel.ll for examples of using FileCheck variables to avoid this problem. /jakob From dpatel at apple.com Tue Jul 5 16:48:22 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 05 Jul 2011 21:48:22 -0000 Subject: [llvm-commits] [llvm] r134441 - in /llvm/trunk/lib: Analysis/ScalarEvolutionExpander.cpp Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110705214822.67D972A6C12C@llvm.org> Author: dpatel Date: Tue Jul 5 16:48:22 2011 New Revision: 134441 URL: http://llvm.org/viewvc/llvm-project?rev=134441&view=rev Log: Preserve debug loc. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=134441&r1=134440&r2=134441&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Jul 5 16:48:22 2011 @@ -955,7 +955,7 @@ // at IVIncInsertPos. Instruction *InsertPos = L == IVIncInsertLoop ? IVIncInsertPos : Pred->getTerminator(); - Builder.SetInsertPoint(InsertPos->getParent(), InsertPos); + Builder.SetInsertPoint(InsertPos); Value *IncV; // If the PHI is a pointer, use a GEP, otherwise use an add or sub. if (isPointer) { Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134441&r1=134440&r2=134441&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jul 5 16:48:22 2011 @@ -339,7 +339,7 @@ << " RHS:\t" << *RHS << "\n"); ICmpInst *Cond = new ICmpInst(BI, Opcode, CmpIndVar, ExitCnt, "exitcond"); - + Cond->setDebugLoc(BI->getDebugLoc()); Value *OrigCond = BI->getCondition(); // It's tempting to use replaceAllUsesWith here to fully replace the old // comparison, but that's not immediately safe, since users of the old From gohman at apple.com Tue Jul 5 17:01:44 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 05 Jul 2011 22:01:44 -0000 Subject: [llvm-commits] [llvm] r134444 - in /llvm/trunk: include/llvm/Support/PassManagerBuilder.h lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <20110705220144.B13582A6C12C@llvm.org> Author: djg Date: Tue Jul 5 17:01:44 2011 New Revision: 134444 URL: http://llvm.org/viewvc/llvm-project?rev=134444&view=rev Log: Remove the ObjC ARC passes from the default optimization list, and add extension points to be used by clang. Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134444&r1=134443&r2=134444&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Tue Jul 5 17:01:44 2011 @@ -67,7 +67,12 @@ /// EP_LoopOptimizerEnd - This extension point allows adding loop passes to /// the end of the loop optimizer. - EP_LoopOptimizerEnd + EP_LoopOptimizerEnd, + + /// EP_ScalarOptimizerLate - This extension point allows adding optimization + /// passes after most of the main optimizations, but before the last + /// cleanup-ish optimizations. + EP_ScalarOptimizerLate }; /// The Optimization Level - Specify the basic optimization level. @@ -188,7 +193,6 @@ MPM.add(createArgumentPromotionPass()); // Scalarize uninlined fn args // Start of function pass. - MPM.add(createObjCARCExpandPass()); // Canonicalize ObjC ARC code. // Break up aggregate allocas, using SSAUpdater. MPM.add(createScalarReplAggregatesPass(-1, false)); MPM.add(createEarlyCSEPass()); // Catch trivial redundancies @@ -224,7 +228,9 @@ MPM.add(createJumpThreadingPass()); // Thread jumps MPM.add(createCorrelatedValuePropagationPass()); MPM.add(createDeadStoreEliminationPass()); // Delete dead stores - MPM.add(createObjCARCOptPass()); // Objective-C ARC optimizations. + + addExtensionsToPM(EP_ScalarOptimizerLate, MPM); + MPM.add(createAggressiveDCEPass()); // Delete dead instructions MPM.add(createCFGSimplificationPass()); // Merge & remove BBs MPM.add(createInstructionCombiningPass()); // Clean up after everything. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134444&r1=134443&r2=134444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Jul 5 17:01:44 2011 @@ -303,10 +303,6 @@ if (!DisableVerify) PM.add(createVerifierPass()); - // Simplify ObjC ARC code. This is done late because it makes re-optimization - // difficult. - PM.add(createObjCARCContractPass()); - // Run loop strength reduction before anything else. if (OptLevel != CodeGenOpt::None && !DisableLSR) { PM.add(createLoopStrengthReducePass(getTargetLowering())); From gohman at apple.com Tue Jul 5 17:09:19 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 05 Jul 2011 22:09:19 -0000 Subject: [llvm-commits] [llvm] r134447 - /llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll Message-ID: <20110705220919.73EFD2A6C12C@llvm.org> Author: djg Date: Tue Jul 5 17:09:19 2011 New Revision: 134447 URL: http://llvm.org/viewvc/llvm-project?rev=134447&view=rev Log: Revert r134366 and add an explicit triple to make this test host-independent. Modified: llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll Modified: llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll?rev=134447&r1=134446&r2=134447&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll Tue Jul 5 17:09:19 2011 @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -march=x86-64 -o - < %s | FileCheck %s +; RUN: llc -asm-verbose=false -march=x86-64 -mtriple=x86_64-apple-darwin -o - < %s | FileCheck %s ; LSR should leave non-affine expressions alone because it currently ; doesn't know how to do anything with them, and when it tries, it @@ -7,9 +7,9 @@ ; CHECK: xorl %eax, %eax ; CHECK-NEXT: align ; CHECK-NEXT: BB0_1: -; CHECK-NEXT: movq %rax, (%{{rdx|r8}}) -; CHECK-NEXT: addq %{{rsi|rdx}}, %rax -; CHECK-NEXT: cmpq %{{rdi|rcx}}, %rax +; CHECK-NEXT: movq %rax, (%rdx) +; CHECK-NEXT: addq %rsi, %rax +; CHECK-NEXT: cmpq %rdi, %rax ; CHECK-NEXT: jl ; CHECK-NEXT: imulq %rax, %rax ; CHECK-NEXT: ret From grosser at fim.uni-passau.de Tue Jul 5 17:15:53 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 05 Jul 2011 22:15:53 -0000 Subject: [llvm-commits] [polly] r134448 - /polly/trunk/lib/ScheduleOptimizer.cpp Message-ID: <20110705221553.C1FA42A6C12C@llvm.org> Author: grosser Date: Tue Jul 5 17:15:53 2011 New Revision: 134448 URL: http://llvm.org/viewvc/llvm-project?rev=134448&view=rev Log: ScheduleOpt: Fix some bugs isl changed a function name, we did not properly initialize some variables and we freed an isl_ctx object. Modified: polly/trunk/lib/ScheduleOptimizer.cpp Modified: polly/trunk/lib/ScheduleOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=134448&r1=134447&r2=134448&view=diff ============================================================================== --- polly/trunk/lib/ScheduleOptimizer.cpp (original) +++ polly/trunk/lib/ScheduleOptimizer.cpp Tue Jul 5 17:15:53 2011 @@ -205,7 +205,6 @@ partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap); isl_dim_free(dim); - isl_ctx_free(ctx); return partialSchedule; } @@ -286,6 +285,11 @@ isl_union_map *partialSchedule; band = isl_band_list_get_band(blist, i); partialSchedule = getTiledPartialSchedule(band); + int scheduleDimensions = isl_band_n_member(band); + isl_dim *dim = isl_union_map_get_dim(partialSchedule); + int parameterDimensions = isl_dim_size(dim, isl_dim_param); + isl_dim_free(dim); + if (isl_band_has_children(band)) { isl_band_list *children = isl_band_get_children(band); @@ -296,11 +300,10 @@ isl_map *tileMap; isl_union_map *tileUnionMap; isl_ctx *ctx; - int scheduleDimensions, parameterDimensions; ctx = isl_union_map_get_ctx(partialSchedule); for (int i = scheduleDimensions - 1 ; i >= 0 ; i--) { - if (isl_band_member_is_parallel(band, i)) { + if (isl_band_member_is_zero_distance(band, i)) { tileMap = getPrevectorMap(ctx, scheduleDimensions + i, scheduleDimensions * 2, parameterDimensions); @@ -313,7 +316,7 @@ } if (finalSchedule) - isl_union_map_union(finalSchedule, partialSchedule); + finalSchedule = isl_union_map_union(finalSchedule, partialSchedule); else finalSchedule = partialSchedule; From grosbach at apple.com Tue Jul 5 17:28:41 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 05 Jul 2011 15:28:41 -0700 Subject: [llvm-commits] Add to RuntimeDyld support different object formats In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE17F1ACBF5D@mail.accesssoftek.com> References: <6AE1604EE3EC5F4296C096518C6B77EE17F1ACBF5D@mail.accesssoftek.com> Message-ID: <4D93170A-8936-444E-8E4D-6FEABE985AF8@apple.com> Hi Danil, This looks reasonable to me. A few minor tweaks and we're set: 1. "MachODyldImpl" should probably just be "MachORuntimeDyld" or "RuntimeDyldMachO". The "Impl" suffix is an artifact of the internal vs. external aspects of the existing class, which isn't a distinction the derived classes need to make. 2. Since loadObject() is lazilly creating the runtime linker, it should probably also store off the object file type of the first loaded object and validate that subsequent objects are of the same type before trying to pass them into the linker. 3. Please scrub your changes for trailing whitespace before checking in. A brief brain-dump of some things I've been thinking about but may not be readily apparent from the code as it currently exists: As you continue, please keep an eye out for things we can do to share more logic between the different runtime linkers. For example, I'm hoping we can share logic for determining whether all symbols have been resolved, for managing multiple object files, for mapping symbols to target addresses, etc.. When performing relocations, keep in mind that the address that should be relocated for the symbol is not necessarily the same as the address either in the object file where it's loaded or the address allocated by the JITMemoryManager. Consider the case where the compiler is a server process which copies the code (and data) into a client process' address space (perhaps on a remote target). The relocations will need to reflect where the code and data live when it runs, not where it was compiled. The JITMemoryManager doesn't currently have the flexibility to completely handle all of the above. For example, there's no clean way to link back from the object module to the source IR constructs for the current JITMM interfaces, so we do by-name lookups to get a mapping. For things that don't have linker-visible names (constant strings, constant pool entries, etc.), this breaks down. We'll need to do some refactoring to get that stuff to play nicely together. Thanks for working on this! -Jim On Jul 1, 2011, at 12:55 AM, Danil Malyshev wrote: > Hello everyone, > > Please find attached the patch for review. > This patch re-factors the RuntimeDyldImpl to support multiple formats as following: > > ? All MachO-specific code has been moved to a new MachODyldImpl class which derives from RuntimeDyldImpl. > ? Changed RuntimeDyldImpl class to keep only code common for all formats. > ? Changed RuntimeDyld::loadObject() to figure out the given object format and instantiate a specific implementation (for now only MachO is supported, but I?ll add implementation for ELF in the coming patches). > > How does it look? > > > Regards, > Danil > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Jul 5 18:08:55 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 05 Jul 2011 23:08:55 -0000 Subject: [llvm-commits] [test-suite] r134450 - /test-suite/trunk/TEST.lineinfo.Makefile Message-ID: <20110705230855.436B12A6C12C@llvm.org> Author: dpatel Date: Tue Jul 5 18:08:55 2011 New Revision: 134450 URL: http://llvm.org/viewvc/llvm-project?rev=134450&view=rev Log: cleanup. Modified: test-suite/trunk/TEST.lineinfo.Makefile Modified: test-suite/trunk/TEST.lineinfo.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.lineinfo.Makefile?rev=134450&r1=134449&r2=134450&view=diff ============================================================================== --- test-suite/trunk/TEST.lineinfo.Makefile (original) +++ test-suite/trunk/TEST.lineinfo.Makefile Tue Jul 5 18:08:55 2011 @@ -12,54 +12,8 @@ REPORTS_TO_GEN := dbg REPORTS_SUFFIX := $(addsuffix .report.txt, $(REPORTS_TO_GEN)) -Output/%.bp: %.c Output/.dir - $(LCC) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc - $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ - -Output/%.bp: %.cpp Output/.dir - $(LCXX) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc - $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ - -Output/%.bp: %.m Output/.dir - $(LCC) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc - $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ - -Output/%.bp: %.mm Output/.dir - $(LCXX) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc - $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ - $(PROGRAMS_TO_TEST:%=test.$(TEST).%): \ -test.$(TEST).%: Output/%.bp Output/%.dbg Output/%.dbg.opt Output/%.native.dbg Output/%.native.dbg.opt - @-is_skip=0; \ - if test "$*" == "reversefile"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "spellcheck"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "sumcol"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "wc"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "wordfreq"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "exptree"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "ray"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "oscar"; then \ - is_skip=1; \ - fi; \ - if test "$*" == "spirit"; then \ - is_skip=1; \ - fi; \ - if test $$is_skip == 0; then \ - $(PROJ_SRC_ROOT)/PrintLineNo.sh $*; \ - $(PROJ_SRC_ROOT)/FindMissingLineNo.py $* $(PROJ_SRC_ROOT);\ - fi +test.$(TEST).%: Output/%.dbg Output/%.dbg.opt Output/%.native.dbg Output/%.native.dbg.opt + $(PROJ_SRC_ROOT)/PrintLineNo.sh $*; \ + $(PROJ_SRC_ROOT)/FindMissingLineNo.py $* $(PROJ_SRC_ROOT); From jstaszak at apple.com Tue Jul 5 18:12:11 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 05 Jul 2011 16:12:11 -0700 Subject: [llvm-commits] Built-in "expect" support In-Reply-To: <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> References: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> Message-ID: <95FAB0DA-CF44-4059-BAF8-B7A958FC8BC2@apple.com> On Jul 5, 2011, at 9:15 AM, Bob Wilson wrote: > > On Jul 2, 2011, at 6:00 PM, Jakub Staszak wrote: > >> Hello, >> >> This patch introduces built-in support. It uses llvm.expect intrinsics to create "branch_weights" metadata if run with -md-expect or with -O. >> >> Comments are welcome. > > > I think the new "expect" intrinsic should be overloaded for all integer types, instead of being forced to i64 only. Although it should work OK without the overloading, I can imagine cases where the extra sign/zero-extends and truncates for i64 could change the way the code is optimized. Overloading it just seems like a better fit for how this intrinsic is used. > I used llvm_anyint_ty. It seems to work. > Unless I missed something, this is your first patch using the "block_weights" metadata, and you haven't yet described the intended usage or format of that metadata. You'll need to provide those details and some documentation. For now, let's proceed with the understanding that everything about "block_weights" metadata is tentative and subject to change. > I'm working on the documentation right now. > The "expect" intrinsic should have the IntrNoMem property, not IntrReadArgMem. > Oh, sure. > I think your new pass should run after early CSE. One of the reasons we decided to implement builtin_expect this way is to allow some simple propagation of builtin_expect calls that are not directly inside conditionals. You haven't implemented that yet, but early CSE should help when the time comes. > OK. > The long methods in your MetadataExpect pass should be defined outside the class. > Done. > The arbitrary constants "4" and "64" for likely and unlikely branch weights should not be used directly. These should be symbolic constants defined in the MetadataExpect class. Once we have more code using this, we may want to adjust those values. > Done. > The "MetadataExpect" and "md-expect" names are not very descriptive of what the transform pass does, which is to convert expect intrinsics to block_weights metadata. I'll see if I can think of better alternatives -- let me know if you have ideas. > LowerExpectIntrinsics? ExpectToBlockWeights? {Lower/Transform}ExpectsToBlockWeights? > Please add a comment for your change to IntrinsicLowering.cpp Done. - Kuba From jstaszak at apple.com Tue Jul 5 18:51:30 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Tue, 05 Jul 2011 16:51:30 -0700 Subject: [llvm-commits] Branch Weight Metdata Doc Message-ID: <2E12C1D4-E395-4D4A-AD67-FF60B5DE6DA2@apple.com> Hello, This introduces some basic informations about branch weight metadata and built-in "expect". Ok to commit? -Kuba -------------- next part -------------- An HTML attachment was scrubbed... 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URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/3a3ff2db/attachment-0001.html From evan.cheng at apple.com Tue Jul 5 21:02:33 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 02:02:33 -0000 Subject: [llvm-commits] [llvm] r134457 - in /llvm/trunk: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h utils/TableGen/AsmWriterEmitter.cpp Message-ID: <20110706020233.C01A02A6C12C@llvm.org> Author: evancheng Date: Tue Jul 5 21:02:33 2011 New Revision: 134457 URL: http://llvm.org/viewvc/llvm-project?rev=134457&view=rev Log: Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134457&r1=134456&r2=134457&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Tue Jul 5 21:02:33 2011 @@ -33,9 +33,6 @@ X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) { - // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures( - &TM.getSubtarget())); } void X86ATTInstPrinter::printRegName(raw_ostream &OS, Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=134457&r1=134456&r2=134457&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Tue Jul 5 21:02:33 2011 @@ -30,8 +30,6 @@ virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; - // Methods used to print the alias of an instruction. - unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const; // Autogenerated by tblgen, returns true if we successfully printed an // alias. bool printAliasInstr(const MCInst *MI, raw_ostream &OS); Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=134457&r1=134456&r2=134457&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Jul 5 21:02:33 2011 @@ -606,92 +606,29 @@ } namespace { - -/// SubtargetFeatureInfo - Helper class for storing information on a subtarget -/// feature which participates in instruction matching. -struct SubtargetFeatureInfo { - /// \brief The predicate record for this feature. - const Record *TheDef; - - /// \brief An unique index assigned to represent this feature. - unsigned Index; - - SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} - - /// \brief The name of the enumerated constant identifying this feature. - std::string getEnumName() const { - return "Feature_" + TheDef->getName(); - } -}; - -struct AsmWriterInfo { - /// Map of Predicate records to their subtarget information. - std::map SubtargetFeatures; - - /// getSubtargetFeature - Lookup or create the subtarget feature info for the - /// given operand. - SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const { - assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); - std::map::const_iterator I = - SubtargetFeatures.find(Def); - return I == SubtargetFeatures.end() ? 0 : I->second; - } - - void addReqFeatures(const std::vector &Features) { - for (std::vector::const_iterator - I = Features.begin(), E = Features.end(); I != E; ++I) { - const Record *Pred = *I; - - // Ignore predicates that are not intended for the assembler. - if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) - continue; - - if (Pred->getName().empty()) - throw TGError(Pred->getLoc(), "Predicate has no name!"); - - // Don't add the predicate again. - if (getSubtargetFeature(Pred)) - continue; - - unsigned FeatureNo = SubtargetFeatures.size(); - SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); - assert(FeatureNo < 32 && "Too many subtarget features!"); - } - } - - const SubtargetFeatureInfo *getFeatureInfo(const Record *R) { - return SubtargetFeatures[R]; - } -}; - // IAPrinter - Holds information about an InstAlias. Two InstAliases match if // they both have the same conditionals. In which case, we cannot print out the // alias for that pattern. class IAPrinter { - AsmWriterInfo &AWI; std::vector Conds; std::map OpMap; std::string Result; std::string AsmString; std::vector ReqFeatures; public: - IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS) - : AWI(Info), Result(R), AsmString(AS) {} + IAPrinter(std::string R, std::string AS) + : Result(R), AsmString(AS) {} void addCond(const std::string &C) { Conds.push_back(C); } - void addReqFeatures(const std::vector &Features) { - AWI.addReqFeatures(Features); - ReqFeatures = Features; - } void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } - bool print(raw_ostream &O) { + void print(raw_ostream &O) { if (Conds.empty() && ReqFeatures.empty()) { O.indent(6) << "return true;\n"; - return false; + return; } O << "if ("; @@ -706,27 +643,6 @@ O << *I; } - if (!ReqFeatures.empty()) { - if (Conds.begin() != Conds.end()) { - O << " &&\n"; - O.indent(8); - } else { - O << "if ("; - } - - std::string Req; - raw_string_ostream ReqO(Req); - - for (std::vector::iterator - I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) { - if (I != ReqFeatures.begin()) ReqO << " | "; - ReqO << AWI.getFeatureInfo(*I)->getEnumName(); - } - - O << "(AvailableFeatures & (" << ReqO.str() << ")) == (" - << ReqO.str() << ')'; - } - O << ") {\n"; O.indent(6) << "// " << Result << "\n"; O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; @@ -738,7 +654,6 @@ O.indent(6) << "break;\n"; O.indent(4) << '}'; - return !ReqFeatures.empty(); } bool operator==(const IAPrinter &RHS) { @@ -770,53 +685,6 @@ } // end anonymous namespace -/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag -/// definitions. -static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info, - raw_ostream &O) { - O << "namespace {\n\n"; - O << "// Flags for subtarget features that participate in " - << "alias instruction matching.\n"; - O << "enum SubtargetFeatureFlag {\n"; - - for (std::map::const_iterator - I = Info.SubtargetFeatures.begin(), - E = Info.SubtargetFeatures.end(); I != E; ++I) { - SubtargetFeatureInfo &SFI = *I->second; - O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; - } - - O << " Feature_None = 0\n"; - O << "};\n\n"; - O << "} // end anonymous namespace\n\n"; -} - -/// EmitComputeAvailableFeatures - Emit the function to compute the list of -/// available features given a subtarget. -static void EmitComputeAvailableFeatures(AsmWriterInfo &Info, - Record *AsmWriter, - CodeGenTarget &Target, - raw_ostream &O) { - std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - - O << "unsigned " << Target.getName() << ClassName << "::\n" - << "ComputeAvailableFeatures(const " << Target.getName() - << "Subtarget *Subtarget) const {\n"; - O << " unsigned Features = 0;\n"; - - for (std::map::const_iterator - I = Info.SubtargetFeatures.begin(), - E = Info.SubtargetFeatures.end(); I != E; ++I) { - SubtargetFeatureInfo &SFI = *I->second; - O << " if (" << SFI.TheDef->getValueAsString("CondString") - << ")\n"; - O << " Features |= " << SFI.getEnumName() << ";\n"; - } - - O << " return Features;\n"; - O << "}\n\n"; -} - static void EmitGetMapOperandNumber(raw_ostream &O) { O << "static unsigned getMapOperandNumber(" << "const SmallVectorImpl > &OpMap,\n"; @@ -960,7 +828,6 @@ // A map of which conditions need to be met for each instruction operand // before it can be matched to the mnemonic. std::map > IAPrinterMap; - AsmWriterInfo AWI; for (std::map >::iterator I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { @@ -977,9 +844,8 @@ if (NumResultOps < CountNumOperands(CGA->AsmString)) continue; - IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(), + IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), CGA->AsmString); - IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates")); std::string Cond; Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); @@ -1049,9 +915,6 @@ } } - EmitSubtargetFeatureFlagEnumeration(AWI, O); - EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O); - std::string Header; raw_string_ostream HeaderO(Header); @@ -1061,7 +924,6 @@ std::string Cases; raw_string_ostream CasesO(Cases); - bool NeedAvailableFeatures = false; for (std::map >::iterator I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { @@ -1092,7 +954,7 @@ II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { IAPrinter *IAP = *II; CasesO.indent(4); - NeedAvailableFeatures |= IAP->print(CasesO); + IAP->print(CasesO); CasesO << '\n'; } @@ -1112,8 +974,6 @@ O << HeaderO.str(); O.indent(2) << "StringRef AsmString;\n"; O.indent(2) << "SmallVector, 4> OpMap;\n"; - if (NeedAvailableFeatures) - O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n"; O.indent(2) << "switch (MI->getOpcode()) {\n"; O.indent(2) << "default: return false;\n"; O << CasesO.str(); From stoklund at 2pi.dk Tue Jul 5 21:30:52 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 5 Jul 2011 19:30:52 -0700 Subject: [llvm-commits] [llvm] r134268 - in /llvm/trunk: lib/Analysis/IVUsers.cpp test/CodeGen/X86/lsr-nonaffine.ll In-Reply-To: References: <20110701220520.297C22A6C12C@llvm.org> Message-ID: On Jul 5, 2011, at 2:19 PM, Jakob Stoklund Olesen wrote: > > On Jul 5, 2011, at 2:08 PM, Francois Pichet wrote: > >> On Fri, Jul 1, 2011 at 11:52 PM, Jakob Stoklund Olesen wrote: >>> Unit tests should only mention explicit registers when a specific register >>> is required for correctness. >>> Otherwise, use FileCheck variables. >>> One of these days, I am going to add -regalloc=random? >>> /jakob >>> >> >> Interesting! I know close to nothing about register allocation >> algorithms but I am curious to know where does that nondeterminism >> comes from? > > It's not a non-determinism, Windows has different callee-saved registers, and therefore a different allocation order. > > However, there are many equally good solutions to the register allocation problem, and unit tests should not depend on what the register allocator happens to pick (deterministically) today. > > Takumi's fix of this test is not correct, a small change to the register allocator will break it again. I discussed this with Dan, and it turns out that this function has only one optimal register allocation. All the registers are either ingoing arguments or the return value. In that case, it is perfectly fine to check for specific registers, and Takumi's fix for the Windows ABI was also OK. Dan has changed the test to use a fixed triple, so the Windows ABI should no longer be an issue. /jakob From nicholas at mxc.ca Wed Jul 6 01:26:38 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 05 Jul 2011 23:26:38 -0700 Subject: [llvm-commits] patch: go crazy, compute bits for an entire add instruction Message-ID: <4E14001E.1040801@mxc.ca> This is a patch to ComputeMaskedBits primarily, though it's hard to observe the effect in a small testcase without also adding more smarts someplace else, which this patch does for instsimplify. When faced with an add instruction, ComputeMaskedBits will look at the leading bits and the trailing bits to attempt to establish a pattern -- and it does a decent job. However, there may be bits we could calculate in the middle, which we currently don't. Go wild, try to compute every bit in an add. This requires a new loop that is O(n) in the number of bits, which I think is sensible enough given that most values will be either 32 or 64 bits, making this effectively a constant-time operation. Please review! If this patch is okay, I'm going to do it for sub as well obviously, but eventually for multiply. Currently if we transform some things to mul (using mul as a bit-spreading operation, basically) we lose optimization power because we can no longer analyze it as well as the equivalent series of shifts with add's/or's. Nick -------------- next part -------------- A non-text attachment was scrubbed... Name: compute-add-bits.patch Type: text/x-patch Size: 7495 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110705/6432ba9c/attachment-0001.bin From bob.wilson at apple.com Wed Jul 6 11:06:01 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 06 Jul 2011 09:06:01 -0700 Subject: [llvm-commits] Built-in "expect" support In-Reply-To: <95FAB0DA-CF44-4059-BAF8-B7A958FC8BC2@apple.com> References: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> <95FAB0DA-CF44-4059-BAF8-B7A958FC8BC2@apple.com> Message-ID: On Jul 5, 2011, at 4:12 PM, Jakub Staszak wrote: >> The "MetadataExpect" and "md-expect" names are not very descriptive of what the transform pass does, which is to convert expect intrinsics to block_weights metadata. I'll see if I can think of better alternatives -- let me know if you have ideas. >> > LowerExpectIntrinsics? > ExpectToBlockWeights? > {Lower/Transform}ExpectsToBlockWeights? LowerExpectIntrinsics sounds good. Please go ahead and commit. From jstaszak at apple.com Wed Jul 6 11:14:37 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 09:14:37 -0700 Subject: [llvm-commits] Built-in "expect" support In-Reply-To: References: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> <95FAB0DA-CF44-4059-BAF8-B7A958FC8BC2@apple.com> Message-ID: On Jul 6, 2011, at 9:06 AM, Bob Wilson wrote: > > LowerExpectIntrinsics sounds good. Please go ahead and commit. I think that LowerExpectIntrinsic (no "s") would be better. - Kuba From bob.wilson at apple.com Wed Jul 6 11:15:53 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 06 Jul 2011 09:15:53 -0700 Subject: [llvm-commits] Built-in "expect" support In-Reply-To: References: <8FEF2DE3-2F1B-417E-A79F-DB6CF76B5949@apple.com> <794AD71F-6FFF-4A2A-A0FF-B0CBE00A6235@apple.com> <95FAB0DA-CF44-4059-BAF8-B7A958FC8BC2@apple.com> Message-ID: <6DFFD88E-8A10-4EC1-A8A7-10830521C1A4@apple.com> On Jul 6, 2011, at 9:14 AM, Jakub Staszak wrote: > > On Jul 6, 2011, at 9:06 AM, Bob Wilson wrote: > >> >> LowerExpectIntrinsics sounds good. Please go ahead and commit. > > I think that LowerExpectIntrinsic (no "s") would be better. OK From x.tong at utoronto.ca Wed Jul 6 11:31:32 2011 From: x.tong at utoronto.ca (Xin Tong Utoronto) Date: Wed, 6 Jul 2011 12:31:32 -0400 Subject: [llvm-commits] [llvm jit adaptive-compilation] : Adaptive compilation framework x86 Patch In-Reply-To: References: <4e11d99c.8521e70a.2556.2dfeSMTPIN_ADDED@mx.google.com> <35C48A86-CFB9-42C3-8FAA-051E3B6C1030@apple.com> Message-ID: Before the adaptive compilation framework is added lli ?O0 Total Time is 1064.27 seconds lli ?O1 Total Time is 1401.42 seconds lli ?O2 Total Time is 1389.2 seconds lli ?O3 Total Time is 1391.49 seconds After the adaptive compilation framework is added lli -O0 Total Time is 1068.37s lli -O1 Total Time is 1395.68s lli -O2Total Time is 1394.81s lli -O3 Total Time is 1395.76s lli -adaptive-comp Total Time is 1119.23s As you can see that the performance number before the adaptive compilation framework is added is very close to the performance number after the adaptive compilation framework is added. This makes senses, as when the adaptive compilation framework is not enabled, the code executed for lli -O0 ? O3 is almost the same as before. I also compared the top 5 test cases for lli O1 ? O3 && lli ?adaptive-comp after the adaptive compilation framework is added. There are 417 test cases in the llvm-test suite. Here are the results for top 5. Luckily the top 5 are the same for all the runs. lli O0 lli O1 lli O2 lli O3 lli adaptive MultiSource/Benchmarks/PAQ8p/paq8p 150.47 95.84 95.56 95.71 108.55 MultiSource/Applications/lemon/lemon 85.47 522.86 522.95 521.93 91.2 MultiSource/Benchmarks/mafft/pairlocalalign 52.97 30.03 29.92 30.33 50.65 SingleSource/Benchmarks/CoyoteBench/huffbench 50.62 40.55 40.76 40.78 46.63 MultiSource/Benchmarks/SciMark2-C/scimark2 29.04 29.15 28.94 29.02 29.33 % of Time Accounted For %Time = 34.5% %Time = 51.47 % %Time = 51.48% %Time = 51.42% %Time = 29.16% Progressions and regressions: Adaptive compilation performs better than O0 on paq8p, which implies there are easily identified hotspots in the program. However, it is slower than O0 in all other 4 test cases. There might be caused by the overhead of recompilation. Adaptive compilation performs a lot better than O1 , O2 and O3 in lemon, by looking into the lemon test case, I found that Lemon forks a lots of processes 20 * 8 and each process is doing a little bit of work. Because all of these processes inherit command line options from their parents, they are all optimizing at the same level. The optimization starting at O1 takes significantly more time than O0 in this case (about x3). Therefore, most of the time is spent in compiling rather than doing useful work. >From the results above, it is easy to see that adaptive compilation does offer some benefits in some programs, especially ones with easily identifiable hotspots. It, however, suffers from recompilation overhead. Currently, the recompilation in JIT happens synchronously, i.e. the application waits for the compilation to finish. Next step is to implement asynchronous compilation for adaptive compilation, i.e. Compilation Threads. -- Kind Regards Xin Tong On Mon, Jul 4, 2011 at 2:44 PM, Xin Tong Utoronto wrote: > > > Thanks > > Xin > > > On Mon, Jul 4, 2011 at 2:16 PM, Eric Christopher wrote: > >> >> On Jul 4, 2011, at 8:58 AM, Xin Tong Utoronto wrote: >> >> > The original numbers are the same as what are given here. As the lli -O0 >> - O3 is virtually the same as before if adaptive compilation is not enabled. >> >> "The same" isn't a number? >> >> So, that's giving total time to run the testsuite on x86 in seconds I >> gather. How about individual tests? Any significant regressions? >> Progressions? What were the top 10 of each? >> > > Honestly I do not have the original numbers, I will launch a run now and > post later today or tomorrow. Right, the total time is in seconds. I will > report on progressions and regressions as well in the next post. > > -Xin > >> >> -eric >> > > > > -- > Kind Regards > > Xin Tong > -- Kind Regards Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110706/0a7ce505/attachment.html From tobias at grosser.es Wed Jul 6 11:39:17 2011 From: tobias at grosser.es (Tobias Grosser) Date: Wed, 6 Jul 2011 11:39:17 -0500 Subject: [llvm-commits] [PATCH] LICM: Do not loose alignment on promotion Message-ID: The promotion code lost any alignment information, when hoisting loads and stores out of the loop. This lead to incorrect aligned memory accesses. We now use the largest alignment we can prove to be correct. --- lib/Transforms/Scalar/LICM.cpp | 38 ++++++++++++++++++++----- test/Transforms/LICM/2011-07-06-Alignment.ll | 26 +++++++++++++++++ 2 files changed, 56 insertions(+), 8 deletions(-) create mode 100644 test/Transforms/LICM/2011-07-06-Alignment.ll OK to commit? Tobi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-LICM-Do-not-loose-alignment-on-promotion.patch Type: text/x-patch Size: 5192 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110706/3065aef5/attachment.bin From greened at obbligato.org Wed Jul 6 11:54:14 2011 From: greened at obbligato.org (David Greene) Date: Wed, 06 Jul 2011 16:54:14 -0000 Subject: [llvm-commits] [llvm] r134498 - /llvm/trunk/utils/llvmbuild Message-ID: <20110706165414.AE32E2A6C12C@llvm.org> Author: greened Date: Wed Jul 6 11:54:14 2011 New Revision: 134498 URL: http://llvm.org/viewvc/llvm-project?rev=134498&view=rev Log: Allow tagless builds and fix debug build configuration. Modified: llvm/trunk/utils/llvmbuild Modified: llvm/trunk/utils/llvmbuild URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvmbuild?rev=134498&r1=134497&r2=134498&view=diff ============================================================================== --- llvm/trunk/utils/llvmbuild (original) +++ llvm/trunk/utils/llvmbuild Wed Jul 6 11:54:14 2011 @@ -200,7 +200,8 @@ # See if we can find source directories. for src in options.src: - for component in ["llvm", "llvm-gcc", "gcc", "dragonegg"]: + for component in components: + component = component.rstrip("2") compsrc = src + "/" + component if (not os.path.isdir(compsrc)): parser.error("'" + compsrc + "' does not exist") @@ -410,6 +411,8 @@ configure_flags = dict( llvm=dict(debug=["--prefix=" + self.install_prefix, "--with-extra-options=-Werror", + "--enable-assertions", + "--disable-optimized", "--with-cxx-include-root=" + cxxroot, "--with-cxx-include-arch=" + cxxarch], release=["--prefix=" + self.install_prefix, @@ -419,7 +422,9 @@ "--with-cxx-include-arch=" + cxxarch], paranoid=["--prefix=" + self.install_prefix, "--with-extra-options=-Werror", + "--enable-assertions", "--enable-expensive-checks", + "--disable-optimized", "--with-cxx-include-root=" + cxxroot, "--with-cxx-include-arch=" + cxxarch]), llvm_gcc=dict(debug=["--prefix=" + self.install_prefix, @@ -444,6 +449,8 @@ "--enable-languages=c,c++"]), llvm2=dict(debug=["--prefix=" + self.install_prefix, "--with-extra-options=-Werror", + "--enable-assertions", + "--disable-optimized", "--with-llvmgccdir=" + self.install_prefix + "/bin", "--with-cxx-include-root=" + cxxroot, "--with-cxx-include-arch=" + cxxarch], @@ -455,7 +462,9 @@ "--with-cxx-include-arch=" + cxxarch], paranoid=["--prefix=" + self.install_prefix, "--with-extra-options=-Werror", + "--enable-assertions", "--enable-expensive-checks", + "--disable-optimized", "--with-llvmgccdir=" + self.install_prefix + "/bin", "--with-cxx-include-root=" + cxxroot, "--with-cxx-include-arch=" + cxxarch]), @@ -611,7 +620,7 @@ release=dict(), paranoid=dict())) - for component in ["llvm", "llvm-gcc", "llvm2", "gcc", "dragonegg"]: + for component in components: comp = component[:] srcdir = source + "/" + comp.rstrip("2") @@ -625,7 +634,7 @@ config_args = configure_flags[comp_key][build][:] config_args.extend(getattr(self.options, - "extra_" + comp_key + "extra_" + comp_key.rstrip("2") + "_config_flags").split()) self.logger.info("Configuring " + component + " in " + builddir) @@ -703,6 +712,8 @@ # Global constants build_abbrev = dict(debug="dbg", release="opt", paranoid="par") +#components = ["llvm", "llvm-gcc", "llvm2", "gcc", "dragonegg"] +components = ["llvm", "llvm2", "gcc", "dragonegg"] # Parse options parser = optparse.OptionParser(version="%prog 1.0") @@ -718,7 +729,10 @@ format='%(name)-13s: %(message)s') source_abbrev = get_path_abbrevs(set(options.src)) -branch_abbrev = get_path_abbrevs(set(options.branch)) + +branch_abbrev = None +if options.branch is not None: + branch_abbrev = get_path_abbrevs(set(options.branch)) work_queue = queue.Queue() From enderby at apple.com Wed Jul 6 12:23:46 2011 From: enderby at apple.com (Kevin Enderby) Date: Wed, 06 Jul 2011 17:23:46 -0000 Subject: [llvm-commits] [llvm] r134501 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s Message-ID: <20110706172346.53B872A6C12C@llvm.org> Author: enderby Date: Wed Jul 6 12:23:46 2011 New Revision: 134501 URL: http://llvm.org/viewvc/llvm-project?rev=134501&view=rev Log: Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a push with a small constant produces a 2-byte push. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134501&r1=134500&r2=134501&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jul 6 12:23:46 2011 @@ -669,7 +669,7 @@ } let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in { -def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm), +def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), "push{q}\t$imm", []>; def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), "push{q}\t$imm", []>; Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=134501&r1=134500&r2=134501&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Wed Jul 6 12:23:46 2011 @@ -219,6 +219,12 @@ // CHECK: pushq $1 push $1 +// rdar://9716860 +pushq $1 +// CHECK: encoding: [0x6a,0x01] +pushq $1111111 +// CHECK: encoding: [0x68,0x47,0xf4,0x10,0x00] + // rdar://8017530 // CHECK: sldtw 4 sldt 4 From enderby at apple.com Wed Jul 6 12:55:21 2011 From: enderby at apple.com (Kevin Enderby) Date: Wed, 06 Jul 2011 17:55:21 -0000 Subject: [llvm-commits] [llvm] r134511 - /llvm/trunk/test/MC/ELF/relocation.s Message-ID: <20110706175521.292702A6C12C@llvm.org> Author: enderby Date: Wed Jul 6 12:55:20 2011 New Revision: 134511 URL: http://llvm.org/viewvc/llvm-project?rev=134511&view=rev Log: Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. Modified: llvm/trunk/test/MC/ELF/relocation.s Modified: llvm/trunk/test/MC/ELF/relocation.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation.s?rev=134511&r1=134510&r2=134511&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/relocation.s (original) +++ llvm/trunk/test/MC/ELF/relocation.s Wed Jul 6 12:55:20 2011 @@ -92,23 +92,23 @@ // CHECK: # Relocation 0x0000000b // CHECK-NEXT: (('r_offset', 0x0000004e) // CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) +// CHECK-NEXT: ('r_type', 0x0000000e) // CHECK-NEXT: ('r_addend', 0x00000000) // CHECK: # Relocation 0x0000000c -// CHECK-NEXT: (('r_offset', 0x00000055) +// CHECK-NEXT: (('r_offset', 0x00000052) // CHECK-NEXT: ('r_sym', 0x00000006) // CHECK-NEXT: ('r_type', 0x00000002) // CHECK-NEXT: ('r_addend', 0xfffffffc) // CHECK: # Relocation 0x0000000d -// CHECK-NEXT: (('r_offset', 0x0000005c) +// CHECK-NEXT: (('r_offset', 0x00000059) // CHECK-NEXT: ('r_sym', 0x00000006) // CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000005c) +// CHECK-NEXT: ('r_addend', 0x00000059) // CHECK: # Relocation 0x0000000e -// CHECK-NEXT: (('r_offset', 0x00000063) +// CHECK-NEXT: (('r_offset', 0x00000060) // CHECK-NEXT: ('r_sym', 0x00000002) // CHECK-NEXT: ('r_type', 0x0000000b) // CHECK-NEXT: ('r_addend', 0x00000000) From grosser at fim.uni-passau.de Wed Jul 6 13:04:59 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 06 Jul 2011 18:04:59 -0000 Subject: [llvm-commits] [polly] r134512 - /polly/trunk/utils/pollycc Message-ID: <20110706180500.0624E2A6C12C@llvm.org> Author: grosser Date: Wed Jul 6 13:04:59 2011 New Revision: 134512 URL: http://llvm.org/viewvc/llvm-project?rev=134512&view=rev Log: pollycc: Fix error message if PoCC/Pluto are not available Modified: polly/trunk/utils/pollycc Modified: polly/trunk/utils/pollycc URL: http://llvm.org/viewvc/llvm-project/polly/trunk/utils/pollycc?rev=134512&r1=134511&r2=134512&view=diff ============================================================================== --- polly/trunk/utils/pollycc (original) +++ polly/trunk/utils/pollycc Wed Jul 6 13:04:59 2011 @@ -351,7 +351,7 @@ subprocess.call(commandLine) -def checkExecutables(pollyLib): +def checkExecutables(pollyLib, pluto): commandLine = ['opt', '-load', pollyLib, '-help'] try: proc = subprocess.Popen(commandLine, stdout=subprocess.PIPE, @@ -361,8 +361,9 @@ if not stdout_value.count('polly-prepare'): sys.exit('Polly support not available in opt') - if not stdout_value.count('polly-optimize'): - sys.exit('Polly compiled without POCC/Pluto support') + if pluto and not stdout_value.count('Optimize the scop using pocc'): + sys.exit('Polly compiled without POCC/Pluto support. -ftile and -fpluto' + ' will not work.') except OSError: print 'error: opt cannot be executed: ' print 'failing command: \n' + " ".join(commandLine) @@ -393,7 +394,7 @@ pollyLib = os.environ['LIBPOLLY'] - checkExecutables(pollyLib) + checkExecutables(pollyLib, args.fpluto) assemblyFiles = createAssemblyFiles(args.files, args, pollyLib) createOutputFiles(assemblyFiles, args) From grosser at fim.uni-passau.de Wed Jul 6 13:05:05 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 06 Jul 2011 18:05:05 -0000 Subject: [llvm-commits] [polly] r134513 - /polly/trunk/lib/Exchange/ScopLib.cpp Message-ID: <20110706180505.E3B5E2A6C12D@llvm.org> Author: grosser Date: Wed Jul 6 13:05:05 2011 New Revision: 134513 URL: http://llvm.org/viewvc/llvm-project?rev=134513&view=rev Log: ScopLib: Add missing include Modified: polly/trunk/lib/Exchange/ScopLib.cpp Modified: polly/trunk/lib/Exchange/ScopLib.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/ScopLib.cpp?rev=134513&r1=134512&r2=134513&view=diff ============================================================================== --- polly/trunk/lib/Exchange/ScopLib.cpp (original) +++ polly/trunk/lib/Exchange/ScopLib.cpp Wed Jul 6 13:05:05 2011 @@ -24,6 +24,7 @@ #include "stdio.h" #include "isl/set.h" +#include "isl/map.h" #include "isl/constraint.h" using namespace llvm; From nlewycky at google.com Wed Jul 6 13:10:56 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 6 Jul 2011 11:10:56 -0700 Subject: [llvm-commits] [llvm] r123501 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/SSAUpdater.cpp In-Reply-To: <20110115001235.758832A6C12C@llvm.org> References: <20110115001235.758832A6C12C@llvm.org> Message-ID: On 14 January 2011 16:12, Chris Lattner wrote: > Author: lattner > Date: Fri Jan 14 18:12:35 2011 > New Revision: 123501 > > URL: http://llvm.org/viewvc/llvm-project?rev=123501&view=rev > Log: > Generalize LoadAndStorePromoter a bit and switch LICM > to use it. > > Modified: > llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h > llvm/trunk/lib/Transforms/Scalar/LICM.cpp > llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp > llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp > > Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=123501&r1=123500&r2=123501&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original) > +++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Fri Jan 14 > 18:12:35 2011 > @@ -118,15 +118,17 @@ > /// virtual methods. > /// > class LoadAndStorePromoter { > +protected: > + SSAUpdater &SSA; > public: > - LoadAndStorePromoter() {} > + LoadAndStorePromoter(const SmallVectorImpl &Insts, > + SSAUpdater &S, StringRef Name = StringRef()); > virtual ~LoadAndStorePromoter() {} > > /// run - This does the promotion. Insts is a list of loads and stores > to > /// promote, and Name is the basename for the PHIs to insert. After this > is > /// complete, the loads and stores are removed from the code. > - void run(StringRef Name, const SmallVectorImpl &Insts, > - SSAUpdater *SSA = 0); > + void run(const SmallVectorImpl &Insts) const; > > > /// Return true if the specified instruction is in the Inst list (which > was > @@ -139,6 +141,21 @@ > return true; > return false; > } > + > + /// doExtraRewritesBeforeFinalDeletion - This hook is invoked after all > the > + /// stores are found and inserted as available values, but > But what? NIck > + virtual void doExtraRewritesBeforeFinalDeletion() const { > + } > + > + /// replaceLoadWithValue - Clients can choose to implement this to get > + /// notified right before a load is RAUW'd another value. > + virtual void replaceLoadWithValue(LoadInst *LI, Value *V) const { > + } > + > + /// This is called before each instruction is deleted. > + virtual void instructionDeleted(Instruction *I) const { > + } > + > }; > > } // End llvm namespace > > Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=123501&r1=123500&r2=123501&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Fri Jan 14 18:12:35 2011 > @@ -595,6 +595,53 @@ > return true; > } > > +namespace { > + class LoopPromoter : public LoadAndStorePromoter { > + Value *SomePtr; // Designated pointer to store to. > + SmallPtrSet &PointerMustAliases; > + SmallVectorImpl &LoopExitBlocks; > + AliasSetTracker &AST; > + public: > + LoopPromoter(Value *SP, > + const SmallVectorImpl &Insts, SSAUpdater > &S, > + SmallPtrSet &PMA, > + SmallVectorImpl &LEB, AliasSetTracker &ast) > + : LoadAndStorePromoter(Insts, S), SomePtr(SP), > PointerMustAliases(PMA), > + LoopExitBlocks(LEB), AST(ast) {} > + > + virtual bool isInstInList(Instruction *I, > + const SmallVectorImpl &) const > { > + Value *Ptr; > + if (LoadInst *LI = dyn_cast(I)) > + Ptr = LI->getOperand(0); > + else > + Ptr = cast(I)->getPointerOperand(); > + return PointerMustAliases.count(Ptr); > + } > + > + virtual void doExtraRewritesBeforeFinalDeletion() const { > + // Insert stores after in the loop exit blocks. Each exit block > gets a > + // store of the live-out values that feed them. Since we've already > told > + // the SSA updater about the defs in the loop and the preheader > + // definition, it is all set and we can start using it. > + for (unsigned i = 0, e = LoopExitBlocks.size(); i != e; ++i) { > + BasicBlock *ExitBlock = LoopExitBlocks[i]; > + Value *LiveInValue = SSA.GetValueInMiddleOfBlock(ExitBlock); > + Instruction *InsertPos = ExitBlock->getFirstNonPHI(); > + new StoreInst(LiveInValue, SomePtr, InsertPos); > + } > + } > + > + virtual void replaceLoadWithValue(LoadInst *LI, Value *V) const { > + // Update alias analysis. > + AST.copyValue(LI, V); > + } > + virtual void instructionDeleted(Instruction *I) const { > + AST.deleteValue(I); > + } > + }; > +} // end anon namespace > + > /// PromoteAliasSet - Try to promote memory values to scalars by sinking > /// stores out of the loop and moving loads to before the loop. We do > this by > /// looping over the stores in the loop, looking for stores to Must > pointers > @@ -679,179 +726,43 @@ > Changed = true; > ++NumPromoted; > > + SmallVector ExitBlocks; > + CurLoop->getUniqueExitBlocks(ExitBlocks); > + > // We use the SSAUpdater interface to insert phi nodes as required. > SmallVector NewPHIs; > SSAUpdater SSA(&NewPHIs); > + LoopPromoter Promoter(SomePtr, LoopUses, SSA, PointerMustAliases, > ExitBlocks, > + *CurAST); > > - // It wants to know some value of the same type as what we'll be > inserting. > - Value *SomeValue; > - if (isa(LoopUses[0])) > - SomeValue = LoopUses[0]; > - else > - SomeValue = cast(LoopUses[0])->getOperand(0); > - SSA.Initialize(SomeValue->getType(), SomeValue->getName()); > - > - // First step: bucket up uses of the pointers by the block they occur > in. > - // This is important because we have to handle multiple defs/uses in a > block > - // ourselves: SSAUpdater is purely for cross-block references. > - // FIXME: Want a TinyVector since there is usually 0/1 > element. > - DenseMap > UsesByBlock; > - for (unsigned i = 0, e = LoopUses.size(); i != e; ++i) { > - Instruction *User = LoopUses[i]; > - UsesByBlock[User->getParent()].push_back(User); > - } > - > - // Okay, now we can iterate over all the blocks in the loop with uses, > - // processing them. Keep track of which loads are loading a live-in > value. > - SmallVector LiveInLoads; > - DenseMap ReplacedLoads; > - > - for (unsigned LoopUse = 0, e = LoopUses.size(); LoopUse != e; ++LoopUse) > { > - Instruction *User = LoopUses[LoopUse]; > - std::vector &BlockUses = UsesByBlock[User->getParent()]; > - > - // If this block has already been processed, ignore this repeat use. > - if (BlockUses.empty()) continue; > - > - // Okay, this is the first use in the block. If this block just has a > - // single user in it, we can rewrite it trivially. > - if (BlockUses.size() == 1) { > - // If it is a store, it is a trivial def of the value in the block. > - if (isa(User)) { > - SSA.AddAvailableValue(User->getParent(), > - cast(User)->getOperand(0)); > - } else { > - // Otherwise it is a load, queue it to rewrite as a live-in load. > - LiveInLoads.push_back(cast(User)); > - } > - BlockUses.clear(); > - continue; > - } > - > - // Otherwise, check to see if this block is all loads. If so, we can > queue > - // them all as live in loads. > - bool HasStore = false; > - for (unsigned i = 0, e = BlockUses.size(); i != e; ++i) { > - if (isa(BlockUses[i])) { > - HasStore = true; > - break; > - } > - } > - > - if (!HasStore) { > - for (unsigned i = 0, e = BlockUses.size(); i != e; ++i) > - LiveInLoads.push_back(cast(BlockUses[i])); > - BlockUses.clear(); > - continue; > - } > - > - // Otherwise, we have mixed loads and stores (or just a bunch of > stores). > - // Since SSAUpdater is purely for cross-block values, we need to > determine > - // the order of these instructions in the block. If the first use in > the > - // block is a load, then it uses the live in value. The last store > defines > - // the live out value. We handle this by doing a linear scan of the > block. > - BasicBlock *BB = User->getParent(); > - Value *StoredValue = 0; > - for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E; > ++II) { > - if (LoadInst *L = dyn_cast(II)) { > - // If this is a load from an unrelated pointer, ignore it. > - if (!PointerMustAliases.count(L->getOperand(0))) continue; > - > - // If we haven't seen a store yet, this is a live in use, > otherwise > - // use the stored value. > - if (StoredValue) { > - L->replaceAllUsesWith(StoredValue); > - ReplacedLoads[L] = StoredValue; > - } else { > - LiveInLoads.push_back(L); > - } > - continue; > - } > - > - if (StoreInst *S = dyn_cast(II)) { > - // If this is a store to an unrelated pointer, ignore it. > - if (!PointerMustAliases.count(S->getOperand(1))) continue; > - > - // Remember that this is the active value in the block. > - StoredValue = S->getOperand(0); > - } > - } > - > - // The last stored value that happened is the live-out for the block. > - assert(StoredValue && "Already checked that there is a store in > block"); > - SSA.AddAvailableValue(BB, StoredValue); > - BlockUses.clear(); > - } > - > - // Now that all the intra-loop values are classified, set up the > preheader. > - // It gets a load of the pointer we're promoting, and it is the live-out > value > - // from the preheader. > - LoadInst *PreheaderLoad = new > LoadInst(SomePtr,SomePtr->getName()+".promoted", > - Preheader->getTerminator()); > + // Set up the preheader to have a definition of the value. It is the > live-out > + // value from the preheader that uses in the loop will use. > + LoadInst *PreheaderLoad = > + new LoadInst(SomePtr, SomePtr->getName()+".promoted", > + Preheader->getTerminator()); > SSA.AddAvailableValue(Preheader, PreheaderLoad); > > - // Now that the preheader is good to go, set up the exit blocks. Each > exit > - // block gets a store of the live-out values that feed them. Since > we've > - // already told the SSA updater about the defs in the loop and the > preheader > - // definition, it is all set and we can start using it. > - SmallVector ExitBlocks; > - CurLoop->getUniqueExitBlocks(ExitBlocks); > - for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) { > - BasicBlock *ExitBlock = ExitBlocks[i]; > - Value *LiveInValue = SSA.GetValueInMiddleOfBlock(ExitBlock); > - Instruction *InsertPos = ExitBlock->getFirstNonPHI(); > - new StoreInst(LiveInValue, SomePtr, InsertPos); > + // Copy any value stored to or loaded from a must-alias of the pointer. > + if (PreheaderLoad->getType()->isPointerTy()) { > + Value *SomeValue; > + if (LoadInst *LI = dyn_cast(LoopUses[0])) > + SomeValue = LI; > + else > + SomeValue = cast(LoopUses[0])->getValueOperand(); > + > + CurAST->copyValue(SomeValue, PreheaderLoad); > } > > - // Okay, now we rewrite all loads that use live-in values in the loop, > - // inserting PHI nodes as necessary. > - for (unsigned i = 0, e = LiveInLoads.size(); i != e; ++i) { > - LoadInst *ALoad = LiveInLoads[i]; > - Value *NewVal = SSA.GetValueInMiddleOfBlock(ALoad->getParent()); > - ALoad->replaceAllUsesWith(NewVal); > - CurAST->copyValue(ALoad, NewVal); > - ReplacedLoads[ALoad] = NewVal; > - } > + // Rewrite all the loads in the loop and remember all the definitions > from > + // stores in the loop. > + Promoter.run(LoopUses); > > // If the preheader load is itself a pointer, we need to tell alias > analysis > // about the new pointer we created in the preheader block and about any > PHI > // nodes that just got inserted. > if (PreheaderLoad->getType()->isPointerTy()) { > - // Copy any value stored to or loaded from a must-alias of the > pointer. > - CurAST->copyValue(SomeValue, PreheaderLoad); > - > for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) > - CurAST->copyValue(SomeValue, NewPHIs[i]); > - } > - > - // Now that everything is rewritten, delete the old instructions from > the body > - // of the loop. They should all be dead now. > - for (unsigned i = 0, e = LoopUses.size(); i != e; ++i) { > - Instruction *User = LoopUses[i]; > - > - // If this is a load that still has uses, then the load must have been > added > - // as a live value in the SSAUpdate data structure for a block (e.g. > because > - // the loaded value was stored later). In this case, we need to > recursively > - // propagate the updates until we get to the real value. > - if (!User->use_empty()) { > - Value *NewVal = ReplacedLoads[User]; > - assert(NewVal && "not a replaced load?"); > - > - // Propagate down to the ultimate replacee. The intermediately > loads > - // could theoretically already have been deleted, so we don't want > to > - // dereference the Value*'s. > - DenseMap::iterator RLI = ReplacedLoads.find(NewVal); > - while (RLI != ReplacedLoads.end()) { > - NewVal = RLI->second; > - RLI = ReplacedLoads.find(NewVal); > - } > - > - User->replaceAllUsesWith(NewVal); > - CurAST->copyValue(User, NewVal); > - } > - > - CurAST->deleteValue(User); > - User->eraseFromParent(); > + CurAST->copyValue(PreheaderLoad, NewPHIs[i]); > } > > // fwew, we're done! > > Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123501&r1=123500&r2=123501&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jan 14 > 18:12:35 2011 > @@ -844,20 +844,13 @@ > class AllocaPromoter : public LoadAndStorePromoter { > AllocaInst *AI; > public: > - AllocaPromoter() : AI(0) {} > + AllocaPromoter(const SmallVectorImpl &Insts, SSAUpdater > &S) > + : LoadAndStorePromoter(Insts, S), AI(0) {} > > - void run(AllocaInst *AI, SSAUpdater &SSA) { > + void run(AllocaInst *AI, const SmallVectorImpl &Insts) { > // Remember which alloca we're promoting (for isInstInList). > this->AI = AI; > - > - // Build the list of instructions to promote. > - SmallVector Insts; > - for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); > - UI != E; ++UI) > - Insts.push_back(cast(*UI)); > - > - LoadAndStorePromoter::run(AI->getName(), Insts, &SSA); > - > + LoadAndStorePromoter::run(Insts); > AI->eraseFromParent(); > } > > @@ -882,7 +875,7 @@ > BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the > function > > bool Changed = false; > - > + SmallVector Insts; > while (1) { > Allocas.clear(); > > @@ -899,9 +892,17 @@ > PromoteMemToReg(Allocas, *DT, *DF); > else { > SSAUpdater SSA; > - AllocaPromoter Promoter; > - for (unsigned i = 0, e = Allocas.size(); i != e; ++i) > - Promoter.run(Allocas[i], SSA); > + for (unsigned i = 0, e = Allocas.size(); i != e; ++i) { > + AllocaInst *AI = Allocas[i]; > + > + // Build list of instructions to promote. > + for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); > + UI != E; ++UI) > + Insts.push_back(cast(*UI)); > + > + AllocaPromoter(Insts, SSA).run(AI, Insts); > + Insts.clear(); > + } > } > NumPromoted += Allocas.size(); > Changed = true; > > Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=123501&r1=123500&r2=123501&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Fri Jan 14 18:12:35 2011 > @@ -348,23 +348,25 @@ > // LoadAndStorePromoter Implementation > > //===----------------------------------------------------------------------===// > > -void LoadAndStorePromoter::run(StringRef BaseName, > - const SmallVectorImpl &Insts, > - SSAUpdater *SSA) { > +LoadAndStorePromoter:: > +LoadAndStorePromoter(const SmallVectorImpl &Insts, > + SSAUpdater &S, StringRef BaseName) : SSA(S) { > if (Insts.empty()) return; > > - // If no SSAUpdater was provided, use a default one. This allows the > client > - // to capture inserted PHI nodes etc if they want. > - SSAUpdater DefaultSSA; > - if (SSA == 0) SSA = &DefaultSSA; > - > - const Type *ValTy; > + Value *SomeVal; > if (LoadInst *LI = dyn_cast(Insts[0])) > - ValTy = LI->getType(); > + SomeVal = LI; > else > - ValTy = cast(Insts[0])->getOperand(0)->getType(); > - > - SSA->Initialize(ValTy, BaseName); > + SomeVal = cast(Insts[0])->getOperand(0); > + > + if (BaseName.empty()) > + BaseName = SomeVal->getName(); > + SSA.Initialize(SomeVal->getType(), BaseName); > +} > + > + > +void LoadAndStorePromoter:: > +run(const SmallVectorImpl &Insts) const { > > // First step: bucket up uses of the alloca by the block they occur in. > // This is important because we have to handle multiple defs/uses in a > block > @@ -396,7 +398,7 @@ > if (BlockUses.size() == 1) { > // If it is a store, it is a trivial def of the value in the block. > if (StoreInst *SI = dyn_cast(User)) > - SSA->AddAvailableValue(BB, SI->getOperand(0)); > + SSA.AddAvailableValue(BB, SI->getOperand(0)); > else > // Otherwise it is a load, queue it to rewrite as a live-in load. > LiveInLoads.push_back(cast(User)); > @@ -437,6 +439,7 @@ > // If we haven't seen a store yet, this is a live in use, otherwise > // use the stored value. > if (StoredValue) { > + replaceLoadWithValue(L, StoredValue); > L->replaceAllUsesWith(StoredValue); > ReplacedLoads[L] = StoredValue; > } else { > @@ -456,7 +459,7 @@ > > // The last stored value that happened is the live-out for the block. > assert(StoredValue && "Already checked that there is a store in > block"); > - SSA->AddAvailableValue(BB, StoredValue); > + SSA.AddAvailableValue(BB, StoredValue); > BlockUses.clear(); > } > > @@ -464,11 +467,15 @@ > // inserting PHI nodes as necessary. > for (unsigned i = 0, e = LiveInLoads.size(); i != e; ++i) { > LoadInst *ALoad = LiveInLoads[i]; > - Value *NewVal = SSA->GetValueInMiddleOfBlock(ALoad->getParent()); > + Value *NewVal = SSA.GetValueInMiddleOfBlock(ALoad->getParent()); > + replaceLoadWithValue(ALoad, NewVal); > ALoad->replaceAllUsesWith(NewVal); > ReplacedLoads[ALoad] = NewVal; > } > > + // Allow the client to do stuff before we start nuking things. > + doExtraRewritesBeforeFinalDeletion(); > + > // Now that everything is rewritten, delete the old instructions from the > // function. They should all be dead now. > for (unsigned i = 0, e = Insts.size(); i != e; ++i) { > @@ -491,9 +498,11 @@ > RLI = ReplacedLoads.find(NewVal); > } > > + replaceLoadWithValue(cast(User), NewVal); > User->replaceAllUsesWith(NewVal); > } > > + instructionDeleted(User); > User->eraseFromParent(); > } > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110706/53769586/attachment.html From jstaszak at apple.com Wed Jul 6 13:22:43 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 18:22:43 -0000 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/LowerExpectIntrinsic/ Message-ID: <20110706182243.7DE702A6C12C@llvm.org> Author: kuba Date: Wed Jul 6 13:22:43 2011 New Revision: 134516 URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev Log: Introduce "expect" intrinsic instructions. Added: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp llvm/trunk/test/CodeGen/Generic/builtin-expect.ll llvm/trunk/test/Transforms/LowerExpectIntrinsic/ llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp Modified: llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/LLVMContext.h llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Support/PassManagerBuilder.h llvm/trunk/include/llvm/Transforms/Scalar.h llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Transforms/Scalar/Scalar.cpp llvm/trunk/lib/Transforms/Utils/CMakeLists.txt llvm/trunk/lib/VMCore/LLVMContext.cpp Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Wed Jul 6 13:22:43 2011 @@ -141,6 +141,7 @@ void initializeLoopUnswitchPass(PassRegistry&); void initializeLoopIdiomRecognizePass(PassRegistry&); void initializeLowerAtomicPass(PassRegistry&); +void initializeLowerExpectIntrinsicPass(PassRegistry&); void initializeLowerIntrinsicsPass(PassRegistry&); void initializeLowerInvokePass(PassRegistry&); void initializeLowerSetJmpPass(PassRegistry&); Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Wed Jul 6 13:22:43 2011 @@ -266,6 +266,11 @@ [IntrNoMem]>, GCCBuiltin<"__builtin_object_size">; +//===------------------------- Expect Intrinsics --------------------------===// +// +def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, + LLVMMatchType<0>], [IntrNoMem]>; + //===-------------------- Bit Manipulation Intrinsics ---------------------===// // Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Wed Jul 6 13:22:43 2011 @@ -39,7 +39,8 @@ // compile-time performance optimization, not a correctness optimization. enum { MD_dbg = 0, // "dbg" - MD_tbaa = 1 // "tbaa" + MD_tbaa = 1, // "tbaa" + MD_prof = 2 // "prof" }; /// getMDKindID - Return a unique non-zero ID for the specified metadata kind. Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jul 6 13:22:43 2011 @@ -92,6 +92,7 @@ (void) llvm::createLoopUnswitchPass(); (void) llvm::createLoopIdiomPass(); (void) llvm::createLoopRotatePass(); + (void) llvm::createLowerExpectIntrinsicPass(); (void) llvm::createLowerInvokePass(); (void) llvm::createLowerSetJmpPass(); (void) llvm::createLowerSwitchPass(); Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Wed Jul 6 13:22:43 2011 @@ -152,6 +152,7 @@ FPM.add(createCFGSimplificationPass()); FPM.add(createScalarReplAggregatesPass()); FPM.add(createEarlyCSEPass()); + FPM.add(createLowerExpectIntrinsicPass()); } /// populateModulePassManager - This sets up the primary pass manager. Modified: llvm/trunk/include/llvm/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm/Transforms/Scalar.h Wed Jul 6 13:22:43 2011 @@ -361,6 +361,14 @@ FunctionPass *createInstructionSimplifierPass(); extern char &InstructionSimplifierID; + +//===----------------------------------------------------------------------===// +// +// LowerExpectIntriniscs - Removes llvm.expect intrinsics and creates +// "block_weights" metadata. +FunctionPass *createLowerExpectIntrinsicPass(); + + } // End llvm namespace #endif Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jul 6 13:22:43 2011 @@ -353,6 +353,13 @@ report_fatal_error("Code generator does not support intrinsic function '"+ Callee->getName()+"'!"); + case Intrinsic::expect: { + // Just replace __builtin_expect(exp, c) with EXP. + Value *V = CI->getArgOperand(0); + CI->replaceAllUsesWith(V); + break; + } + // The setjmp/longjmp intrinsics should only exist in the code if it was // never optimized (ie, right out of the CFE), or if it has been hacked on // by the lowerinvoke pass. In both cases, the right thing to do is to Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 6 13:22:43 2011 @@ -4771,6 +4771,13 @@ case Intrinsic::flt_rounds: setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); return 0; + + case Intrinsic::expect: { + // Just replace __builtin_expect(exp, c) with EXP. + setValue(&I, getValue(I.getArgOperand(0))); + return 0; + } + case Intrinsic::trap: { StringRef TrapFuncName = getTrapFunctionName(); if (TrapFuncName.empty()) { Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Wed Jul 6 13:22:43 2011 @@ -48,6 +48,7 @@ initializeLoopUnswitchPass(Registry); initializeLoopIdiomRecognizePass(Registry); initializeLowerAtomicPass(Registry); + initializeLowerExpectIntrinsicPass(Registry); initializeMemCpyOptPass(Registry); initializeObjCARCAliasAnalysisPass(Registry); initializeObjCARCExpandPass(Registry); Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Wed Jul 6 13:22:43 2011 @@ -14,6 +14,7 @@ Local.cpp LoopSimplify.cpp LoopUnroll.cpp + LowerExpectIntrinsic.cpp LowerInvoke.cpp LowerSwitch.cpp Mem2Reg.cpp Added: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=134516&view=auto ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (added) +++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Wed Jul 6 13:22:43 2011 @@ -0,0 +1,163 @@ +#define DEBUG_TYPE "lower-expect-intrinsic" +#include "llvm/Constants.h" +#include "llvm/Function.h" +#include "llvm/BasicBlock.h" +#include "llvm/LLVMContext.h" +#include "llvm/Instructions.h" +#include "llvm/Intrinsics.h" +#include "llvm/Metadata.h" +#include "llvm/Pass.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/Statistic.h" +#include + +using namespace llvm; + +STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled"); + +static cl::opt +LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64), + cl::desc("Weight of the branch likely to be taken (default = 64)")); +static cl::opt +UnlikelyBranchWeight("unlikely-branch-weight", cl::Hidden, cl::init(4), + cl::desc("Weight of the branch unlikely to be taken (default = 4)")); + +namespace { + + class LowerExpectIntrinsic : public FunctionPass { + + bool HandleSwitchExpect(SwitchInst *SI); + + bool HandleIfExpect(BranchInst *BI); + + public: + static char ID; + LowerExpectIntrinsic() : FunctionPass(ID) { + initializeLowerExpectIntrinsicPass(*PassRegistry::getPassRegistry()); + } + + bool runOnFunction(Function &F); + }; +} + + +bool LowerExpectIntrinsic::HandleSwitchExpect(SwitchInst *SI) { + CallInst *CI = dyn_cast(SI->getCondition()); + if (!CI) + return false; + + Function *Fn = CI->getCalledFunction(); + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) + return false; + + Value *ArgValue = CI->getArgOperand(0); + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); + if (!ExpectedValue) + return false; + + LLVMContext &Context = CI->getContext(); + const Type *Int32Ty = Type::getInt32Ty(Context); + + unsigned caseNo = SI->findCaseValue(ExpectedValue); + std::vector Vec; + unsigned n = SI->getNumCases(); + Vec.resize(n + 1); // +1 for MDString + + Vec[0] = MDString::get(Context, "branch_weights"); + for (unsigned i = 0; i < n; ++i) { + Vec[i + 1] = ConstantInt::get(Int32Ty, i == caseNo ? LikelyBranchWeight : UnlikelyBranchWeight); + } + + MDNode *WeightsNode = llvm::MDNode::get(Context, Vec); + SI->setMetadata(LLVMContext::MD_prof, WeightsNode); + + SI->setCondition(ArgValue); + return true; +} + + +bool LowerExpectIntrinsic::HandleIfExpect(BranchInst *BI) { + if (BI->isUnconditional()) + return false; + + // Handle non-optimized IR code like: + // %expval = call i64 @llvm.expect.i64.i64(i64 %conv1, i64 1) + // %tobool = icmp ne i64 %expval, 0 + // br i1 %tobool, label %if.then, label %if.end + + ICmpInst *CmpI = dyn_cast(BI->getCondition()); + if (!CmpI || CmpI->getPredicate() != CmpInst::ICMP_NE) + return false; + + CallInst *CI = dyn_cast(CmpI->getOperand(0)); + if (!CI) + return false; + + Function *Fn = CI->getCalledFunction(); + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) + return false; + + Value *ArgValue = CI->getArgOperand(0); + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); + if (!ExpectedValue) + return false; + + LLVMContext &Context = CI->getContext(); + const Type *Int32Ty = Type::getInt32Ty(Context); + bool Likely = ExpectedValue->isOne(); + + // If expect value is equal to 1 it means that we are more likely to take + // branch 0, in other case more likely is branch 1. + Value *Ops[] = { + MDString::get(Context, "branch_weights"), + ConstantInt::get(Int32Ty, Likely ? LikelyBranchWeight : UnlikelyBranchWeight), + ConstantInt::get(Int32Ty, Likely ? UnlikelyBranchWeight : LikelyBranchWeight) + }; + + MDNode *WeightsNode = MDNode::get(Context, ArrayRef(Ops, 3)); + BI->setMetadata(LLVMContext::MD_prof, WeightsNode); + + CmpI->setOperand(0, ArgValue); + return true; +} + + +bool LowerExpectIntrinsic::runOnFunction(Function &F) { + for (Function::iterator I = F.begin(), E = F.end(); I != E;) { + BasicBlock *BB = I++; + + // Create "block_weights" metadata. + if (BranchInst *BI = dyn_cast(BB->getTerminator())) { + if (HandleIfExpect(BI)) + IfHandled++; + } else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { + if (HandleSwitchExpect(SI)) + IfHandled++; + } + + // remove llvm.expect intrinsics. + for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); + BI != BE; ) { + CallInst *CI = dyn_cast(BI++); + if (!CI) + continue; + + Function *Fn = CI->getCalledFunction(); + if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) + CI->eraseFromParent(); + } + } + + return false; +} + + +char LowerExpectIntrinsic::ID = 0; +INITIALIZE_PASS(LowerExpectIntrinsic, "lower-expect", "Lower 'expect' " + "Intrinsics", false, false) + +FunctionPass *llvm::createLowerExpectIntrinsicPass() { + return new LowerExpectIntrinsic(); +} Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=134516&r1=134515&r2=134516&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Wed Jul 6 13:22:43 2011 @@ -39,6 +39,10 @@ // Create the 'tbaa' metadata kind. unsigned TBAAID = getMDKindID("tbaa"); assert(TBAAID == MD_tbaa && "tbaa kind id drifted"); (void)TBAAID; + + // Create the 'prof' metadata kind. + unsigned ProfID = getMDKindID("prof"); + assert(ProfID == MD_prof && "prof kind id drifted"); (void)ProfID; } LLVMContext::~LLVMContext() { delete pImpl; } Added: llvm/trunk/test/CodeGen/Generic/builtin-expect.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/builtin-expect.ll?rev=134516&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/builtin-expect.ll (added) +++ llvm/trunk/test/CodeGen/Generic/builtin-expect.ll Wed Jul 6 13:22:43 2011 @@ -0,0 +1,223 @@ +; RUN: llc < %s + +define i32 @test1(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i64 @llvm.expect.i64(i64, i64) nounwind readnone + +declare i32 @f(...) + +define i32 @test2(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test3(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot.ext = zext i1 %lnot to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool1 = icmp ne i64 %expval, 0 + br i1 %tobool1, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test4(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot1 = xor i1 %lnot, true + %lnot.ext = zext i1 %lnot1 to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool2 = icmp ne i64 %expval, 0 + br i1 %tobool2, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test5(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp slt i32 %tmp, 0 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test6(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + switch i64 %expval, label %sw.epilog [ + i64 1, label %sw.bb + i64 2, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + store i32 0, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test7(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + switch i64 %expval, label %sw.epilog [ + i64 2, label %sw.bb + i64 3, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + %tmp1 = load i32* %x.addr, align 4 + store i32 %tmp1, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 0, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test8(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1) + %tobool = icmp ne i32 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i32 @llvm.expect.i32(i32, i32) nounwind readnone + Added: llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll?rev=134516&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll (added) +++ llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll Wed Jul 6 13:22:43 2011 @@ -0,0 +1,251 @@ +; RUN: opt -lower-expect -strip-dead-prototypes -S -o - < %s | FileCheck %s + +; CHECK: @test1 +define i32 @test1(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1) + %tobool = icmp ne i64 %expval, 0 +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i64 @llvm.expect.i64(i64, i64) nounwind readnone + +declare i32 @f(...) + +; CHECK: @test2 +define i32 @test2(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool = icmp ne i64 %expval, 0 +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test3 +define i32 @test3(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot.ext = zext i1 %lnot to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool1 = icmp ne i64 %expval, 0 +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %tobool1, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test4 +define i32 @test4(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot1 = xor i1 %lnot, true + %lnot.ext = zext i1 %lnot1 to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool2 = icmp ne i64 %expval, 0 +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %tobool2, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test5 +define i32 @test5(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp slt i32 %tmp, 0 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0) + %tobool = icmp ne i64 %expval, 0 +; CHECK: !prof !1 +; CHECK-NOT: @llvm.expect + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test6 +define i32 @test6(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) +; CHECK: !prof !2 +; CHECK-NOT: @llvm.expect + switch i64 %expval, label %sw.epilog [ + i64 1, label %sw.bb + i64 2, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + store i32 0, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test7 +define i32 @test7(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) +; CHECK: !prof !3 +; CHECK-NOT: @llvm.expect + switch i64 %expval, label %sw.epilog [ + i64 2, label %sw.bb + i64 3, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + %tmp1 = load i32* %x.addr, align 4 + store i32 %tmp1, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 0, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +; CHECK: @test8 +define i32 @test8(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1) + %tobool = icmp ne i32 %expval, 0 +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i32 @llvm.expect.i32(i32, i32) nounwind readnone + +; CHECK: !0 = metadata !{metadata !"branch_weights", i32 64, i32 4} +; CHECK: !1 = metadata !{metadata !"branch_weights", i32 4, i32 64} +; CHECK: !2 = metadata !{metadata !"branch_weights", i32 4, i32 64, i32 4} +; CHECK: !3 = metadata !{metadata !"branch_weights", i32 64, i32 4, i32 4} Added: llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp?rev=134516&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp (added) +++ llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp Wed Jul 6 13:22:43 2011 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] From eli.friedman at gmail.com Wed Jul 6 13:24:43 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 6 Jul 2011 11:24:43 -0700 Subject: [llvm-commits] [PATCH] LICM: Do not loose alignment on promotion In-Reply-To: References: Message-ID: On Wed, Jul 6, 2011 at 9:39 AM, Tobias Grosser wrote: > > The promotion code lost any alignment information, when hoisting loads and > stores out of the loop. This lead to incorrect aligned memory accesses. We now > use the largest alignment we can prove to be correct. > --- > > ?lib/Transforms/Scalar/LICM.cpp ? ? ? ? ? ? ? | ? 38 ++++++++++++++++++++----- > ?test/Transforms/LICM/2011-07-06-Alignment.ll | ? 26 +++++++++++++++++ > ?2 files changed, 56 insertions(+), 8 deletions(-) > ?create mode 100644 test/Transforms/LICM/2011-07-06-Alignment.ll > > OK to commit? Looks like your patch has tabs; please remove. Otherwise, looks fine; although, since I touched that code pretty recently, I'm surprised I didn't spot that issue. -Eli From wendling at apple.com Wed Jul 6 13:29:55 2011 From: wendling at apple.com (Bill Wendling) Date: Wed, 06 Jul 2011 11:29:55 -0700 Subject: [llvm-commits] [llvm] r134457 - in /llvm/trunk: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h utils/TableGen/AsmWriterEmitter.cpp In-Reply-To: <20110706020233.C01A02A6C12C@llvm.org> References: <20110706020233.C01A02A6C12C@llvm.org> Message-ID: Hi Evan, Does this mean that an InstAlias can no longer have a "Requires" clause added to it? -bw On Jul 5, 2011, at 7:02 PM, Evan Cheng wrote: > Author: evancheng > Date: Tue Jul 5 21:02:33 2011 > New Revision: 134457 > > URL: http://llvm.org/viewvc/llvm-project?rev=134457&view=rev > Log: > Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. > > Modified: > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134457&r1=134456&r2=134457&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Tue Jul 5 21:02:33 2011 > @@ -33,9 +33,6 @@ > > X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) > : MCInstPrinter(MAI) { > - // Initialize the set of available features. > - setAvailableFeatures(ComputeAvailableFeatures( > - &TM.getSubtarget())); > } > > void X86ATTInstPrinter::printRegName(raw_ostream &OS, > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=134457&r1=134456&r2=134457&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Tue Jul 5 21:02:33 2011 > @@ -30,8 +30,6 @@ > virtual void printInst(const MCInst *MI, raw_ostream &OS); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > - // Methods used to print the alias of an instruction. > - unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const; > // Autogenerated by tblgen, returns true if we successfully printed an > // alias. > bool printAliasInstr(const MCInst *MI, raw_ostream &OS); > > Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=134457&r1=134456&r2=134457&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Jul 5 21:02:33 2011 > @@ -606,92 +606,29 @@ > } > > namespace { > - > -/// SubtargetFeatureInfo - Helper class for storing information on a subtarget > -/// feature which participates in instruction matching. > -struct SubtargetFeatureInfo { > - /// \brief The predicate record for this feature. > - const Record *TheDef; > - > - /// \brief An unique index assigned to represent this feature. > - unsigned Index; > - > - SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} > - > - /// \brief The name of the enumerated constant identifying this feature. > - std::string getEnumName() const { > - return "Feature_" + TheDef->getName(); > - } > -}; > - > -struct AsmWriterInfo { > - /// Map of Predicate records to their subtarget information. > - std::map SubtargetFeatures; > - > - /// getSubtargetFeature - Lookup or create the subtarget feature info for the > - /// given operand. > - SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const { > - assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); > - std::map::const_iterator I = > - SubtargetFeatures.find(Def); > - return I == SubtargetFeatures.end() ? 0 : I->second; > - } > - > - void addReqFeatures(const std::vector &Features) { > - for (std::vector::const_iterator > - I = Features.begin(), E = Features.end(); I != E; ++I) { > - const Record *Pred = *I; > - > - // Ignore predicates that are not intended for the assembler. > - if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) > - continue; > - > - if (Pred->getName().empty()) > - throw TGError(Pred->getLoc(), "Predicate has no name!"); > - > - // Don't add the predicate again. > - if (getSubtargetFeature(Pred)) > - continue; > - > - unsigned FeatureNo = SubtargetFeatures.size(); > - SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); > - assert(FeatureNo < 32 && "Too many subtarget features!"); > - } > - } > - > - const SubtargetFeatureInfo *getFeatureInfo(const Record *R) { > - return SubtargetFeatures[R]; > - } > -}; > - > // IAPrinter - Holds information about an InstAlias. Two InstAliases match if > // they both have the same conditionals. In which case, we cannot print out the > // alias for that pattern. > class IAPrinter { > - AsmWriterInfo &AWI; > std::vector Conds; > std::map OpMap; > std::string Result; > std::string AsmString; > std::vector ReqFeatures; > public: > - IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS) > - : AWI(Info), Result(R), AsmString(AS) {} > + IAPrinter(std::string R, std::string AS) > + : Result(R), AsmString(AS) {} > > void addCond(const std::string &C) { Conds.push_back(C); } > - void addReqFeatures(const std::vector &Features) { > - AWI.addReqFeatures(Features); > - ReqFeatures = Features; > - } > > void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } > unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } > bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } > > - bool print(raw_ostream &O) { > + void print(raw_ostream &O) { > if (Conds.empty() && ReqFeatures.empty()) { > O.indent(6) << "return true;\n"; > - return false; > + return; > } > > O << "if ("; > @@ -706,27 +643,6 @@ > O << *I; > } > > - if (!ReqFeatures.empty()) { > - if (Conds.begin() != Conds.end()) { > - O << " &&\n"; > - O.indent(8); > - } else { > - O << "if ("; > - } > - > - std::string Req; > - raw_string_ostream ReqO(Req); > - > - for (std::vector::iterator > - I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) { > - if (I != ReqFeatures.begin()) ReqO << " | "; > - ReqO << AWI.getFeatureInfo(*I)->getEnumName(); > - } > - > - O << "(AvailableFeatures & (" << ReqO.str() << ")) == (" > - << ReqO.str() << ')'; > - } > - > O << ") {\n"; > O.indent(6) << "// " << Result << "\n"; > O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; > @@ -738,7 +654,6 @@ > > O.indent(6) << "break;\n"; > O.indent(4) << '}'; > - return !ReqFeatures.empty(); > } > > bool operator==(const IAPrinter &RHS) { > @@ -770,53 +685,6 @@ > > } // end anonymous namespace > > -/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag > -/// definitions. > -static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info, > - raw_ostream &O) { > - O << "namespace {\n\n"; > - O << "// Flags for subtarget features that participate in " > - << "alias instruction matching.\n"; > - O << "enum SubtargetFeatureFlag {\n"; > - > - for (std::map::const_iterator > - I = Info.SubtargetFeatures.begin(), > - E = Info.SubtargetFeatures.end(); I != E; ++I) { > - SubtargetFeatureInfo &SFI = *I->second; > - O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; > - } > - > - O << " Feature_None = 0\n"; > - O << "};\n\n"; > - O << "} // end anonymous namespace\n\n"; > -} > - > -/// EmitComputeAvailableFeatures - Emit the function to compute the list of > -/// available features given a subtarget. > -static void EmitComputeAvailableFeatures(AsmWriterInfo &Info, > - Record *AsmWriter, > - CodeGenTarget &Target, > - raw_ostream &O) { > - std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); > - > - O << "unsigned " << Target.getName() << ClassName << "::\n" > - << "ComputeAvailableFeatures(const " << Target.getName() > - << "Subtarget *Subtarget) const {\n"; > - O << " unsigned Features = 0;\n"; > - > - for (std::map::const_iterator > - I = Info.SubtargetFeatures.begin(), > - E = Info.SubtargetFeatures.end(); I != E; ++I) { > - SubtargetFeatureInfo &SFI = *I->second; > - O << " if (" << SFI.TheDef->getValueAsString("CondString") > - << ")\n"; > - O << " Features |= " << SFI.getEnumName() << ";\n"; > - } > - > - O << " return Features;\n"; > - O << "}\n\n"; > -} > - > static void EmitGetMapOperandNumber(raw_ostream &O) { > O << "static unsigned getMapOperandNumber(" > << "const SmallVectorImpl > &OpMap,\n"; > @@ -960,7 +828,6 @@ > // A map of which conditions need to be met for each instruction operand > // before it can be matched to the mnemonic. > std::map > IAPrinterMap; > - AsmWriterInfo AWI; > > for (std::map >::iterator > I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { > @@ -977,9 +844,8 @@ > if (NumResultOps < CountNumOperands(CGA->AsmString)) > continue; > > - IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(), > + IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), > CGA->AsmString); > - IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates")); > > std::string Cond; > Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); > @@ -1049,9 +915,6 @@ > } > } > > - EmitSubtargetFeatureFlagEnumeration(AWI, O); > - EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O); > - > std::string Header; > raw_string_ostream HeaderO(Header); > > @@ -1061,7 +924,6 @@ > > std::string Cases; > raw_string_ostream CasesO(Cases); > - bool NeedAvailableFeatures = false; > > for (std::map >::iterator > I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { > @@ -1092,7 +954,7 @@ > II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { > IAPrinter *IAP = *II; > CasesO.indent(4); > - NeedAvailableFeatures |= IAP->print(CasesO); > + IAP->print(CasesO); > CasesO << '\n'; > } > > @@ -1112,8 +974,6 @@ > O << HeaderO.str(); > O.indent(2) << "StringRef AsmString;\n"; > O.indent(2) << "SmallVector, 4> OpMap;\n"; > - if (NeedAvailableFeatures) > - O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n"; > O.indent(2) << "switch (MI->getOpcode()) {\n"; > O.indent(2) << "default: return false;\n"; > O << CasesO.str(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jstaszak at apple.com Wed Jul 6 13:31:02 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 18:31:02 -0000 Subject: [llvm-commits] [llvm] r134517 - in /llvm/trunk/docs: BranchWeightMetadata.html index.html Message-ID: <20110706183102.EFFD02A6C12C@llvm.org> Author: kuba Date: Wed Jul 6 13:31:02 2011 New Revision: 134517 URL: http://llvm.org/viewvc/llvm-project?rev=134517&view=rev Log: Add documenation about "branch_weight" metadata and __builtin_expect instruction Added: llvm/trunk/docs/BranchWeightMetadata.html Modified: llvm/trunk/docs/index.html Added: llvm/trunk/docs/BranchWeightMetadata.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/BranchWeightMetadata.html?rev=134517&view=auto ============================================================================== --- llvm/trunk/docs/BranchWeightMetadata.html (added) +++ llvm/trunk/docs/BranchWeightMetadata.html Wed Jul 6 13:31:02 2011 @@ -0,0 +1,163 @@ + + + + LLVM Branch Weight Metadata + + + + +

+ LLVM Branch Weight Metadata +

+ +
    +
  1. Introduction
  2. +
  3. Supported Instructions
  4. +
  5. Built-in "expect" Instruction
  6. +
  7. CFG Modifications
  8. +
+ +
+

Written by Jakub Staszak

+
+ +

+ Introduction +

+
+

Branch Weight Metadata represents branch weights as its likeliness to +be taken. Metadata is assigned to the TerminatorInst as a +MDNode of the MD_prof kind. The first operator is always a +MDString node with the string "branch_weights". Number of operators +depends on the terminator type.

+ +

Branch weights might be fetch from the profiling file, or generated based on +__builtin_expect instruction. +

+ +

All weights are represented as an unsigned 32-bit values, where higher value +indicates greater chance to be taken.

+
+ +

+ Supported Instructions +

+ +
+

BranchInst

+
+

Metadata is only assign to the conditional branches. There are two extra + operarands, for the true and the false branch.

+
+
+
+!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <TRUE_BRANCH_WEIGHT>,
+  i32 <FALSE_BRANCH_WEIGHT>
+}
+  
+
+ +

SwitchInst

+
+

Branch weights are assign to every case (including default case + which is always case #0).

+
+
+
+!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <DEFAULT_BRANCH_WEIGHT>
+  [ , i32 <CASE_BRANCH_WEIGHT> ... ]
+}
+  
+
+ +

IndirectBrInst

+
+

Branch weights are assign to every destination.

+
+
+
+!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <LABEL_BRANCH_WEIGHT>
+  [ , i32 <LABEL_BRANCH_WEIGHT> ... ]
+}
+  
+
+ +

Other

+
+

Other terminator instructions are not allowed to contain Branch Weight + Metadata.

+
+
+ +

+ Built-in "expect" Instructions +

+
+

__builtin_expect(long exp, long c) instruction provides branch + prediction information. The return value is the value of exp.

+ +

It is especially useful in conditional statements. Currently Clang supports + two conditional statements: +

+

if statement

+
+

The exp parameter is the condition. The c parameter is + the expected comparision value. If it is equal to 1 (true), the condition is + likely to be true, in other case condition is likely to be false. For example: +

+
+
+
+  if (__builtin_expect(x > 0, 1)) {
+    // This block is likely to be taken.
+  }
+  
+
+ +

switch statement

+
+

The exp parameter is the value. The c parameter is the + expected value. If the expected value doesn't show on the cases list, the + default case is assumed to be likely taken.

+
+
+
+  switch (__builtin_expect(x, 5)) {
+  default: break;
+  case 0:  // ...
+  case 3:  // ...
+  case 5:  // This case is likely to be taken.
+  }
+  
+
+
+ +

+ CFG Modifications +

+
+

Branch Weight Metatada is not proof against CFG changes. If terminator +operands' are changed some action should be taken. In other case some +misoptimizations may occur due to incorrent branch prediction information.

+
+ +
+
+ Valid CSS + Valid HTML 4.01 + + Jakub Staszak
+ LLVM Compiler Infrastructure
+
+ + + Modified: llvm/trunk/docs/index.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=134517&r1=134516&r2=134517&view=diff ============================================================================== --- llvm/trunk/docs/index.html (original) +++ llvm/trunk/docs/index.html Wed Jul 6 13:31:02 2011 @@ -164,6 +164,7 @@
  • How To Release LLVM To The Public - This is a guide to preparing LLVM releases. Most developers can ignore it.
  • +
  • Doxygen generated documentation (classes) @@ -239,6 +240,10 @@
  • The GDB JIT interface - How to debug JITed code with GDB.
  • + +
  • Branch Weight Metadata - Provides +information about Branch Prediction Information.
  • + From eli.friedman at gmail.com Wed Jul 6 13:33:37 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 6 Jul 2011 11:33:37 -0700 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/Low Message-ID: On Wed, Jul 6, 2011 at 11:22 AM, Jakub Staszak wrote: > Author: kuba > Date: Wed Jul ?6 13:22:43 2011 > New Revision: 134516 > > URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev > Log: > Introduce "expect" intrinsic instructions. > > > Added: > ? ?llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp > ? ?llvm/trunk/test/CodeGen/Generic/builtin-expect.ll > ? ?llvm/trunk/test/Transforms/LowerExpectIntrinsic/ > ? ?llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll > ? ?llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp > Modified: > ? ?llvm/trunk/include/llvm/InitializePasses.h > ? ?llvm/trunk/include/llvm/Intrinsics.td > ? ?llvm/trunk/include/llvm/LLVMContext.h > ? ?llvm/trunk/include/llvm/LinkAllPasses.h > ? ?llvm/trunk/include/llvm/Support/PassManagerBuilder.h > ? ?llvm/trunk/include/llvm/Transforms/Scalar.h > ? ?llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > ? ?llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > ? ?llvm/trunk/lib/Transforms/Scalar/Scalar.cpp > ? ?llvm/trunk/lib/Transforms/Utils/CMakeLists.txt > ? ?llvm/trunk/lib/VMCore/LLVMContext.cpp > > Modified: llvm/trunk/include/llvm/InitializePasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/InitializePasses.h (original) > +++ llvm/trunk/include/llvm/InitializePasses.h Wed Jul ?6 13:22:43 2011 > @@ -141,6 +141,7 @@ > ?void initializeLoopUnswitchPass(PassRegistry&); > ?void initializeLoopIdiomRecognizePass(PassRegistry&); > ?void initializeLowerAtomicPass(PassRegistry&); > +void initializeLowerExpectIntrinsicPass(PassRegistry&); > ?void initializeLowerIntrinsicsPass(PassRegistry&); > ?void initializeLowerInvokePass(PassRegistry&); > ?void initializeLowerSetJmpPass(PassRegistry&); > > Modified: llvm/trunk/include/llvm/Intrinsics.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Intrinsics.td (original) > +++ llvm/trunk/include/llvm/Intrinsics.td Wed Jul ?6 13:22:43 2011 > @@ -266,6 +266,11 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?[IntrNoMem]>, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?GCCBuiltin<"__builtin_object_size">; > > +//===------------------------- Expect Intrinsics --------------------------===// > +// > +def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?LLVMMatchType<0>], [IntrNoMem]>; > + > ?//===-------------------- Bit Manipulation Intrinsics ---------------------===// > ?// > > > Modified: llvm/trunk/include/llvm/LLVMContext.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/LLVMContext.h (original) > +++ llvm/trunk/include/llvm/LLVMContext.h Wed Jul ?6 13:22:43 2011 > @@ -39,7 +39,8 @@ > ? // compile-time performance optimization, not a correctness optimization. > ? enum { > ? ? MD_dbg = 0, ?// "dbg" > - ? ?MD_tbaa = 1 ?// "tbaa" > + ? ?MD_tbaa = 1, // "tbaa" > + ? ?MD_prof = 2 ?// "prof" > ? }; > > ? /// getMDKindID - Return a unique non-zero ID for the specified metadata kind. > > Modified: llvm/trunk/include/llvm/LinkAllPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/LinkAllPasses.h (original) > +++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jul ?6 13:22:43 2011 > @@ -92,6 +92,7 @@ > ? ? ? (void) llvm::createLoopUnswitchPass(); > ? ? ? (void) llvm::createLoopIdiomPass(); > ? ? ? (void) llvm::createLoopRotatePass(); > + ? ? ?(void) llvm::createLowerExpectIntrinsicPass(); > ? ? ? (void) llvm::createLowerInvokePass(); > ? ? ? (void) llvm::createLowerSetJmpPass(); > ? ? ? (void) llvm::createLowerSwitchPass(); > > Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) > +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Wed Jul ?6 13:22:43 2011 > @@ -152,6 +152,7 @@ > ? ? FPM.add(createCFGSimplificationPass()); > ? ? FPM.add(createScalarReplAggregatesPass()); > ? ? FPM.add(createEarlyCSEPass()); > + ? ?FPM.add(createLowerExpectIntrinsicPass()); > ? } > > ? /// populateModulePassManager - This sets up the primary pass manager. > > Modified: llvm/trunk/include/llvm/Transforms/Scalar.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) > +++ llvm/trunk/include/llvm/Transforms/Scalar.h Wed Jul ?6 13:22:43 2011 > @@ -361,6 +361,14 @@ > ?FunctionPass *createInstructionSimplifierPass(); > ?extern char &InstructionSimplifierID; > > + > +//===----------------------------------------------------------------------===// > +// > +// LowerExpectIntriniscs - Removes llvm.expect intrinsics and creates > +// "block_weights" metadata. > +FunctionPass *createLowerExpectIntrinsicPass(); > + > + > ?} // End llvm namespace > > ?#endif > > Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jul ?6 13:22:43 2011 > @@ -353,6 +353,13 @@ > ? ? report_fatal_error("Code generator does not support intrinsic function '"+ > ? ? ? ? ? ? ? ? ? ? ? Callee->getName()+"'!"); > > + ?case Intrinsic::expect: { > + ? ?// Just replace __builtin_expect(exp, c) with EXP. > + ? ?Value *V = CI->getArgOperand(0); > + ? ?CI->replaceAllUsesWith(V); > + ? ?break; > + ?} > + > ? ? // The setjmp/longjmp intrinsics should only exist in the code if it was > ? ? // never optimized (ie, right out of the CFE), or if it has been hacked on > ? ? // by the lowerinvoke pass. ?In both cases, the right thing to do is to > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul ?6 13:22:43 2011 > @@ -4771,6 +4771,13 @@ > ? case Intrinsic::flt_rounds: > ? ? setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); > ? ? return 0; > + > + ?case Intrinsic::expect: { > + ? ?// Just replace __builtin_expect(exp, c) with EXP. > + ? ?setValue(&I, getValue(I.getArgOperand(0))); > + ? ?return 0; > + ?} > + > ? case Intrinsic::trap: { > ? ? StringRef TrapFuncName = getTrapFunctionName(); > ? ? if (TrapFuncName.empty()) { > > Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Wed Jul ?6 13:22:43 2011 > @@ -48,6 +48,7 @@ > ? initializeLoopUnswitchPass(Registry); > ? initializeLoopIdiomRecognizePass(Registry); > ? initializeLowerAtomicPass(Registry); > + ?initializeLowerExpectIntrinsicPass(Registry); > ? initializeMemCpyOptPass(Registry); > ? initializeObjCARCAliasAnalysisPass(Registry); > ? initializeObjCARCExpandPass(Registry); > > Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) > +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Wed Jul ?6 13:22:43 2011 > @@ -14,6 +14,7 @@ > ? Local.cpp > ? LoopSimplify.cpp > ? LoopUnroll.cpp > + ?LowerExpectIntrinsic.cpp > ? LowerInvoke.cpp > ? LowerSwitch.cpp > ? Mem2Reg.cpp > > Added: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=134516&view=auto > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (added) > +++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Wed Jul ?6 13:22:43 2011 > @@ -0,0 +1,163 @@ > +#define DEBUG_TYPE "lower-expect-intrinsic" > +#include "llvm/Constants.h" > +#include "llvm/Function.h" > +#include "llvm/BasicBlock.h" > +#include "llvm/LLVMContext.h" > +#include "llvm/Instructions.h" > +#include "llvm/Intrinsics.h" > +#include "llvm/Metadata.h" > +#include "llvm/Pass.h" > +#include "llvm/Transforms/Scalar.h" > +#include "llvm/Support/CommandLine.h" > +#include "llvm/Support/Debug.h" > +#include "llvm/ADT/Statistic.h" > +#include > + > +using namespace llvm; > + > +STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled"); > + > +static cl::opt > +LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64), > + ? ? ? ? ? ? ? ? ? cl::desc("Weight of the branch likely to be taken (default = 64)")); > +static cl::opt > +UnlikelyBranchWeight("unlikely-branch-weight", cl::Hidden, cl::init(4), > + ? ? ? ? ? ? ? ? ? cl::desc("Weight of the branch unlikely to be taken (default = 4)")); > + > +namespace { > + > + ?class LowerExpectIntrinsic : public FunctionPass { > + > + ? ?bool HandleSwitchExpect(SwitchInst *SI); > + > + ? ?bool HandleIfExpect(BranchInst *BI); > + > + ?public: > + ? ?static char ID; > + ? ?LowerExpectIntrinsic() : FunctionPass(ID) { > + ? ? ?initializeLowerExpectIntrinsicPass(*PassRegistry::getPassRegistry()); > + ? ?} > + > + ? ?bool runOnFunction(Function &F); > + ?}; > +} > + > + > +bool LowerExpectIntrinsic::HandleSwitchExpect(SwitchInst *SI) { > + ?CallInst *CI = dyn_cast(SI->getCondition()); > + ?if (!CI) > + ? ?return false; > + > + ?Function *Fn = CI->getCalledFunction(); > + ?if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) > + ? ?return false; > + > + ?Value *ArgValue = CI->getArgOperand(0); > + ?ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); > + ?if (!ExpectedValue) > + ? ?return false; > + > + ?LLVMContext &Context = CI->getContext(); > + ?const Type *Int32Ty = Type::getInt32Ty(Context); > + > + ?unsigned caseNo = SI->findCaseValue(ExpectedValue); > + ?std::vector Vec; > + ?unsigned n = SI->getNumCases(); > + ?Vec.resize(n + 1); // +1 for MDString > + > + ?Vec[0] = MDString::get(Context, "branch_weights"); > + ?for (unsigned i = 0; i < n; ++i) { > + ? ?Vec[i + 1] = ConstantInt::get(Int32Ty, i == caseNo ? LikelyBranchWeight : UnlikelyBranchWeight); > + ?} > + > + ?MDNode *WeightsNode = llvm::MDNode::get(Context, Vec); > + ?SI->setMetadata(LLVMContext::MD_prof, WeightsNode); > + > + ?SI->setCondition(ArgValue); > + ?return true; > +} > + > + > +bool LowerExpectIntrinsic::HandleIfExpect(BranchInst *BI) { > + ?if (BI->isUnconditional()) > + ? ?return false; > + > + ?// Handle non-optimized IR code like: > + ?// ? %expval = call i64 @llvm.expect.i64.i64(i64 %conv1, i64 1) > + ?// ? %tobool = icmp ne i64 %expval, 0 > + ?// ? br i1 %tobool, label %if.then, label %if.end > + > + ?ICmpInst *CmpI = dyn_cast(BI->getCondition()); > + ?if (!CmpI || CmpI->getPredicate() != CmpInst::ICMP_NE) > + ? ?return false; > + > + ?CallInst *CI = dyn_cast(CmpI->getOperand(0)); > + ?if (!CI) > + ? ?return false; > + > + ?Function *Fn = CI->getCalledFunction(); > + ?if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) > + ? ?return false; > + > + ?Value *ArgValue = CI->getArgOperand(0); > + ?ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); > + ?if (!ExpectedValue) > + ? ?return false; > + > + ?LLVMContext &Context = CI->getContext(); > + ?const Type *Int32Ty = Type::getInt32Ty(Context); > + ?bool Likely = ExpectedValue->isOne(); > + > + ?// If expect value is equal to 1 it means that we are more likely to take > + ?// branch 0, in other case more likely is branch 1. > + ?Value *Ops[] = { > + ? ?MDString::get(Context, "branch_weights"), > + ? ?ConstantInt::get(Int32Ty, Likely ? LikelyBranchWeight : UnlikelyBranchWeight), > + ? ?ConstantInt::get(Int32Ty, Likely ? UnlikelyBranchWeight : LikelyBranchWeight) > + ?}; > + > + ?MDNode *WeightsNode = MDNode::get(Context, ArrayRef(Ops, 3)); > + ?BI->setMetadata(LLVMContext::MD_prof, WeightsNode); > + > + ?CmpI->setOperand(0, ArgValue); > + ?return true; > +} > + > + > +bool LowerExpectIntrinsic::runOnFunction(Function &F) { > + ?for (Function::iterator I = F.begin(), E = F.end(); I != E;) { > + ? ?BasicBlock *BB = I++; > + > + ? ?// Create "block_weights" metadata. > + ? ?if (BranchInst *BI = dyn_cast(BB->getTerminator())) { > + ? ? ?if (HandleIfExpect(BI)) > + ? ? ? ?IfHandled++; > + ? ?} else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { > + ? ? ?if (HandleSwitchExpect(SI)) > + ? ? ? ?IfHandled++; > + ? ?} > + > + ? ?// remove llvm.expect intrinsics. > + ? ?for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); > + ? ? ? ? BI != BE; ) { > + ? ? ?CallInst *CI = dyn_cast(BI++); > + ? ? ?if (!CI) > + ? ? ? ?continue; > + > + ? ? ?Function *Fn = CI->getCalledFunction(); > + ? ? ?if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) > + ? ? ? ?CI->eraseFromParent(); > + ? ?} > + ?} These loops look relatively expensive... have you done benchmarking here? -Eli From jstaszak at apple.com Wed Jul 6 13:46:15 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 11:46:15 -0700 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/Low In-Reply-To: References: Message-ID: <30E52997-E463-4FDF-9791-E6A2707BDB4A@apple.com> Yeah, I don't remember the exact numbers but It looked fine. I will double check that. - Kuba On Jul 6, 2011, at 11:33 AM, Eli Friedman wrote: > On Wed, Jul 6, 2011 at 11:22 AM, Jakub Staszak wrote: >> Author: kuba >> Date: Wed Jul 6 13:22:43 2011 >> New Revision: 134516 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev >> Log: >> Introduce "expect" intrinsic instructions. >> >> >> Added: >> llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp >> llvm/trunk/test/CodeGen/Generic/builtin-expect.ll >> llvm/trunk/test/Transforms/LowerExpectIntrinsic/ >> llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll >> llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp >> Modified: >> llvm/trunk/include/llvm/InitializePasses.h >> llvm/trunk/include/llvm/Intrinsics.td >> llvm/trunk/include/llvm/LLVMContext.h >> llvm/trunk/include/llvm/LinkAllPasses.h >> llvm/trunk/include/llvm/Support/PassManagerBuilder.h >> llvm/trunk/include/llvm/Transforms/Scalar.h >> llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp >> llvm/trunk/lib/Transforms/Scalar/Scalar.cpp >> llvm/trunk/lib/Transforms/Utils/CMakeLists.txt >> llvm/trunk/lib/VMCore/LLVMContext.cpp >> >> Modified: llvm/trunk/include/llvm/InitializePasses.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/InitializePasses.h (original) >> +++ llvm/trunk/include/llvm/InitializePasses.h Wed Jul 6 13:22:43 2011 >> @@ -141,6 +141,7 @@ >> void initializeLoopUnswitchPass(PassRegistry&); >> void initializeLoopIdiomRecognizePass(PassRegistry&); >> void initializeLowerAtomicPass(PassRegistry&); >> +void initializeLowerExpectIntrinsicPass(PassRegistry&); >> void initializeLowerIntrinsicsPass(PassRegistry&); >> void initializeLowerInvokePass(PassRegistry&); >> void initializeLowerSetJmpPass(PassRegistry&); >> >> Modified: llvm/trunk/include/llvm/Intrinsics.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/Intrinsics.td (original) >> +++ llvm/trunk/include/llvm/Intrinsics.td Wed Jul 6 13:22:43 2011 >> @@ -266,6 +266,11 @@ >> [IntrNoMem]>, >> GCCBuiltin<"__builtin_object_size">; >> >> +//===------------------------- Expect Intrinsics --------------------------===// >> +// >> +def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, >> + LLVMMatchType<0>], [IntrNoMem]>; >> + >> //===-------------------- Bit Manipulation Intrinsics ---------------------===// >> // >> >> >> Modified: llvm/trunk/include/llvm/LLVMContext.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/LLVMContext.h (original) >> +++ llvm/trunk/include/llvm/LLVMContext.h Wed Jul 6 13:22:43 2011 >> @@ -39,7 +39,8 @@ >> // compile-time performance optimization, not a correctness optimization. >> enum { >> MD_dbg = 0, // "dbg" >> - MD_tbaa = 1 // "tbaa" >> + MD_tbaa = 1, // "tbaa" >> + MD_prof = 2 // "prof" >> }; >> >> /// getMDKindID - Return a unique non-zero ID for the specified metadata kind. >> >> Modified: llvm/trunk/include/llvm/LinkAllPasses.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/LinkAllPasses.h (original) >> +++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jul 6 13:22:43 2011 >> @@ -92,6 +92,7 @@ >> (void) llvm::createLoopUnswitchPass(); >> (void) llvm::createLoopIdiomPass(); >> (void) llvm::createLoopRotatePass(); >> + (void) llvm::createLowerExpectIntrinsicPass(); >> (void) llvm::createLowerInvokePass(); >> (void) llvm::createLowerSetJmpPass(); >> (void) llvm::createLowerSwitchPass(); >> >> Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) >> +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Wed Jul 6 13:22:43 2011 >> @@ -152,6 +152,7 @@ >> FPM.add(createCFGSimplificationPass()); >> FPM.add(createScalarReplAggregatesPass()); >> FPM.add(createEarlyCSEPass()); >> + FPM.add(createLowerExpectIntrinsicPass()); >> } >> >> /// populateModulePassManager - This sets up the primary pass manager. >> >> Modified: llvm/trunk/include/llvm/Transforms/Scalar.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) >> +++ llvm/trunk/include/llvm/Transforms/Scalar.h Wed Jul 6 13:22:43 2011 >> @@ -361,6 +361,14 @@ >> FunctionPass *createInstructionSimplifierPass(); >> extern char &InstructionSimplifierID; >> >> + >> +//===----------------------------------------------------------------------===// >> +// >> +// LowerExpectIntriniscs - Removes llvm.expect intrinsics and creates >> +// "block_weights" metadata. >> +FunctionPass *createLowerExpectIntrinsicPass(); >> + >> + >> } // End llvm namespace >> >> #endif >> >> Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) >> +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jul 6 13:22:43 2011 >> @@ -353,6 +353,13 @@ >> report_fatal_error("Code generator does not support intrinsic function '"+ >> Callee->getName()+"'!"); >> >> + case Intrinsic::expect: { >> + // Just replace __builtin_expect(exp, c) with EXP. >> + Value *V = CI->getArgOperand(0); >> + CI->replaceAllUsesWith(V); >> + break; >> + } >> + >> // The setjmp/longjmp intrinsics should only exist in the code if it was >> // never optimized (ie, right out of the CFE), or if it has been hacked on >> // by the lowerinvoke pass. In both cases, the right thing to do is to >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 6 13:22:43 2011 >> @@ -4771,6 +4771,13 @@ >> case Intrinsic::flt_rounds: >> setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); >> return 0; >> + >> + case Intrinsic::expect: { >> + // Just replace __builtin_expect(exp, c) with EXP. >> + setValue(&I, getValue(I.getArgOperand(0))); >> + return 0; >> + } >> + >> case Intrinsic::trap: { >> StringRef TrapFuncName = getTrapFunctionName(); >> if (TrapFuncName.empty()) { >> >> Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) >> +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Wed Jul 6 13:22:43 2011 >> @@ -48,6 +48,7 @@ >> initializeLoopUnswitchPass(Registry); >> initializeLoopIdiomRecognizePass(Registry); >> initializeLowerAtomicPass(Registry); >> + initializeLowerExpectIntrinsicPass(Registry); >> initializeMemCpyOptPass(Registry); >> initializeObjCARCAliasAnalysisPass(Registry); >> initializeObjCARCExpandPass(Registry); >> >> Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=134516&r1=134515&r2=134516&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) >> +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Wed Jul 6 13:22:43 2011 >> @@ -14,6 +14,7 @@ >> Local.cpp >> LoopSimplify.cpp >> LoopUnroll.cpp >> + LowerExpectIntrinsic.cpp >> LowerInvoke.cpp >> LowerSwitch.cpp >> Mem2Reg.cpp >> >> Added: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=134516&view=auto >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (added) >> +++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Wed Jul 6 13:22:43 2011 >> @@ -0,0 +1,163 @@ >> +#define DEBUG_TYPE "lower-expect-intrinsic" >> +#include "llvm/Constants.h" >> +#include "llvm/Function.h" >> +#include "llvm/BasicBlock.h" >> +#include "llvm/LLVMContext.h" >> +#include "llvm/Instructions.h" >> +#include "llvm/Intrinsics.h" >> +#include "llvm/Metadata.h" >> +#include "llvm/Pass.h" >> +#include "llvm/Transforms/Scalar.h" >> +#include "llvm/Support/CommandLine.h" >> +#include "llvm/Support/Debug.h" >> +#include "llvm/ADT/Statistic.h" >> +#include >> + >> +using namespace llvm; >> + >> +STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled"); >> + >> +static cl::opt >> +LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64), >> + cl::desc("Weight of the branch likely to be taken (default = 64)")); >> +static cl::opt >> +UnlikelyBranchWeight("unlikely-branch-weight", cl::Hidden, cl::init(4), >> + cl::desc("Weight of the branch unlikely to be taken (default = 4)")); >> + >> +namespace { >> + >> + class LowerExpectIntrinsic : public FunctionPass { >> + >> + bool HandleSwitchExpect(SwitchInst *SI); >> + >> + bool HandleIfExpect(BranchInst *BI); >> + >> + public: >> + static char ID; >> + LowerExpectIntrinsic() : FunctionPass(ID) { >> + initializeLowerExpectIntrinsicPass(*PassRegistry::getPassRegistry()); >> + } >> + >> + bool runOnFunction(Function &F); >> + }; >> +} >> + >> + >> +bool LowerExpectIntrinsic::HandleSwitchExpect(SwitchInst *SI) { >> + CallInst *CI = dyn_cast(SI->getCondition()); >> + if (!CI) >> + return false; >> + >> + Function *Fn = CI->getCalledFunction(); >> + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) >> + return false; >> + >> + Value *ArgValue = CI->getArgOperand(0); >> + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); >> + if (!ExpectedValue) >> + return false; >> + >> + LLVMContext &Context = CI->getContext(); >> + const Type *Int32Ty = Type::getInt32Ty(Context); >> + >> + unsigned caseNo = SI->findCaseValue(ExpectedValue); >> + std::vector Vec; >> + unsigned n = SI->getNumCases(); >> + Vec.resize(n + 1); // +1 for MDString >> + >> + Vec[0] = MDString::get(Context, "branch_weights"); >> + for (unsigned i = 0; i < n; ++i) { >> + Vec[i + 1] = ConstantInt::get(Int32Ty, i == caseNo ? LikelyBranchWeight : UnlikelyBranchWeight); >> + } >> + >> + MDNode *WeightsNode = llvm::MDNode::get(Context, Vec); >> + SI->setMetadata(LLVMContext::MD_prof, WeightsNode); >> + >> + SI->setCondition(ArgValue); >> + return true; >> +} >> + >> + >> +bool LowerExpectIntrinsic::HandleIfExpect(BranchInst *BI) { >> + if (BI->isUnconditional()) >> + return false; >> + >> + // Handle non-optimized IR code like: >> + // %expval = call i64 @llvm.expect.i64.i64(i64 %conv1, i64 1) >> + // %tobool = icmp ne i64 %expval, 0 >> + // br i1 %tobool, label %if.then, label %if.end >> + >> + ICmpInst *CmpI = dyn_cast(BI->getCondition()); >> + if (!CmpI || CmpI->getPredicate() != CmpInst::ICMP_NE) >> + return false; >> + >> + CallInst *CI = dyn_cast(CmpI->getOperand(0)); >> + if (!CI) >> + return false; >> + >> + Function *Fn = CI->getCalledFunction(); >> + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) >> + return false; >> + >> + Value *ArgValue = CI->getArgOperand(0); >> + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); >> + if (!ExpectedValue) >> + return false; >> + >> + LLVMContext &Context = CI->getContext(); >> + const Type *Int32Ty = Type::getInt32Ty(Context); >> + bool Likely = ExpectedValue->isOne(); >> + >> + // If expect value is equal to 1 it means that we are more likely to take >> + // branch 0, in other case more likely is branch 1. >> + Value *Ops[] = { >> + MDString::get(Context, "branch_weights"), >> + ConstantInt::get(Int32Ty, Likely ? LikelyBranchWeight : UnlikelyBranchWeight), >> + ConstantInt::get(Int32Ty, Likely ? UnlikelyBranchWeight : LikelyBranchWeight) >> + }; >> + >> + MDNode *WeightsNode = MDNode::get(Context, ArrayRef(Ops, 3)); >> + BI->setMetadata(LLVMContext::MD_prof, WeightsNode); >> + >> + CmpI->setOperand(0, ArgValue); >> + return true; >> +} >> + >> + >> +bool LowerExpectIntrinsic::runOnFunction(Function &F) { >> + for (Function::iterator I = F.begin(), E = F.end(); I != E;) { >> + BasicBlock *BB = I++; >> + >> + // Create "block_weights" metadata. >> + if (BranchInst *BI = dyn_cast(BB->getTerminator())) { >> + if (HandleIfExpect(BI)) >> + IfHandled++; >> + } else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { >> + if (HandleSwitchExpect(SI)) >> + IfHandled++; >> + } >> + >> + // remove llvm.expect intrinsics. >> + for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); >> + BI != BE; ) { >> + CallInst *CI = dyn_cast(BI++); >> + if (!CI) >> + continue; >> + >> + Function *Fn = CI->getCalledFunction(); >> + if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) >> + CI->eraseFromParent(); >> + } >> + } > > These loops look relatively expensive... have you done benchmarking here? > > -Eli From evan.cheng at apple.com Wed Jul 6 14:05:31 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 12:05:31 -0700 Subject: [llvm-commits] [llvm] r134457 - in /llvm/trunk: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h utils/TableGen/AsmWriterEmitter.cpp In-Reply-To: References: <20110706020233.C01A02A6C12C@llvm.org> Message-ID: <543CED00-86CF-47A5-A44A-3D9A566369C9@apple.com> Right. If we want to do this, we should figure out a better way to handle this. We want to eliminate the dependency of asm writer on the target layer. Evan On Jul 6, 2011, at 11:29 AM, Bill Wendling wrote: > Hi Evan, > > Does this mean that an InstAlias can no longer have a "Requires" clause added to it? > > -bw > > On Jul 5, 2011, at 7:02 PM, Evan Cheng wrote: > >> Author: evancheng >> Date: Tue Jul 5 21:02:33 2011 >> New Revision: 134457 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134457&view=rev >> Log: >> Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. >> >> Modified: >> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp >> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h >> llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134457&r1=134456&r2=134457&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Tue Jul 5 21:02:33 2011 >> @@ -33,9 +33,6 @@ >> >> X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) >> : MCInstPrinter(MAI) { >> - // Initialize the set of available features. >> - setAvailableFeatures(ComputeAvailableFeatures( >> - &TM.getSubtarget())); >> } >> >> void X86ATTInstPrinter::printRegName(raw_ostream &OS, >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=134457&r1=134456&r2=134457&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Tue Jul 5 21:02:33 2011 >> @@ -30,8 +30,6 @@ >> virtual void printInst(const MCInst *MI, raw_ostream &OS); >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> >> - // Methods used to print the alias of an instruction. >> - unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const; >> // Autogenerated by tblgen, returns true if we successfully printed an >> // alias. >> bool printAliasInstr(const MCInst *MI, raw_ostream &OS); >> >> Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=134457&r1=134456&r2=134457&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Jul 5 21:02:33 2011 >> @@ -606,92 +606,29 @@ >> } >> >> namespace { >> - >> -/// SubtargetFeatureInfo - Helper class for storing information on a subtarget >> -/// feature which participates in instruction matching. >> -struct SubtargetFeatureInfo { >> - /// \brief The predicate record for this feature. >> - const Record *TheDef; >> - >> - /// \brief An unique index assigned to represent this feature. >> - unsigned Index; >> - >> - SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} >> - >> - /// \brief The name of the enumerated constant identifying this feature. >> - std::string getEnumName() const { >> - return "Feature_" + TheDef->getName(); >> - } >> -}; >> - >> -struct AsmWriterInfo { >> - /// Map of Predicate records to their subtarget information. >> - std::map SubtargetFeatures; >> - >> - /// getSubtargetFeature - Lookup or create the subtarget feature info for the >> - /// given operand. >> - SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const { >> - assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); >> - std::map::const_iterator I = >> - SubtargetFeatures.find(Def); >> - return I == SubtargetFeatures.end() ? 0 : I->second; >> - } >> - >> - void addReqFeatures(const std::vector &Features) { >> - for (std::vector::const_iterator >> - I = Features.begin(), E = Features.end(); I != E; ++I) { >> - const Record *Pred = *I; >> - >> - // Ignore predicates that are not intended for the assembler. >> - if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) >> - continue; >> - >> - if (Pred->getName().empty()) >> - throw TGError(Pred->getLoc(), "Predicate has no name!"); >> - >> - // Don't add the predicate again. >> - if (getSubtargetFeature(Pred)) >> - continue; >> - >> - unsigned FeatureNo = SubtargetFeatures.size(); >> - SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); >> - assert(FeatureNo < 32 && "Too many subtarget features!"); >> - } >> - } >> - >> - const SubtargetFeatureInfo *getFeatureInfo(const Record *R) { >> - return SubtargetFeatures[R]; >> - } >> -}; >> - >> // IAPrinter - Holds information about an InstAlias. Two InstAliases match if >> // they both have the same conditionals. In which case, we cannot print out the >> // alias for that pattern. >> class IAPrinter { >> - AsmWriterInfo &AWI; >> std::vector Conds; >> std::map OpMap; >> std::string Result; >> std::string AsmString; >> std::vector ReqFeatures; >> public: >> - IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS) >> - : AWI(Info), Result(R), AsmString(AS) {} >> + IAPrinter(std::string R, std::string AS) >> + : Result(R), AsmString(AS) {} >> >> void addCond(const std::string &C) { Conds.push_back(C); } >> - void addReqFeatures(const std::vector &Features) { >> - AWI.addReqFeatures(Features); >> - ReqFeatures = Features; >> - } >> >> void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } >> unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } >> bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } >> >> - bool print(raw_ostream &O) { >> + void print(raw_ostream &O) { >> if (Conds.empty() && ReqFeatures.empty()) { >> O.indent(6) << "return true;\n"; >> - return false; >> + return; >> } >> >> O << "if ("; >> @@ -706,27 +643,6 @@ >> O << *I; >> } >> >> - if (!ReqFeatures.empty()) { >> - if (Conds.begin() != Conds.end()) { >> - O << " &&\n"; >> - O.indent(8); >> - } else { >> - O << "if ("; >> - } >> - >> - std::string Req; >> - raw_string_ostream ReqO(Req); >> - >> - for (std::vector::iterator >> - I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) { >> - if (I != ReqFeatures.begin()) ReqO << " | "; >> - ReqO << AWI.getFeatureInfo(*I)->getEnumName(); >> - } >> - >> - O << "(AvailableFeatures & (" << ReqO.str() << ")) == (" >> - << ReqO.str() << ')'; >> - } >> - >> O << ") {\n"; >> O.indent(6) << "// " << Result << "\n"; >> O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; >> @@ -738,7 +654,6 @@ >> >> O.indent(6) << "break;\n"; >> O.indent(4) << '}'; >> - return !ReqFeatures.empty(); >> } >> >> bool operator==(const IAPrinter &RHS) { >> @@ -770,53 +685,6 @@ >> >> } // end anonymous namespace >> >> -/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag >> -/// definitions. >> -static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info, >> - raw_ostream &O) { >> - O << "namespace {\n\n"; >> - O << "// Flags for subtarget features that participate in " >> - << "alias instruction matching.\n"; >> - O << "enum SubtargetFeatureFlag {\n"; >> - >> - for (std::map::const_iterator >> - I = Info.SubtargetFeatures.begin(), >> - E = Info.SubtargetFeatures.end(); I != E; ++I) { >> - SubtargetFeatureInfo &SFI = *I->second; >> - O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; >> - } >> - >> - O << " Feature_None = 0\n"; >> - O << "};\n\n"; >> - O << "} // end anonymous namespace\n\n"; >> -} >> - >> -/// EmitComputeAvailableFeatures - Emit the function to compute the list of >> -/// available features given a subtarget. >> -static void EmitComputeAvailableFeatures(AsmWriterInfo &Info, >> - Record *AsmWriter, >> - CodeGenTarget &Target, >> - raw_ostream &O) { >> - std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); >> - >> - O << "unsigned " << Target.getName() << ClassName << "::\n" >> - << "ComputeAvailableFeatures(const " << Target.getName() >> - << "Subtarget *Subtarget) const {\n"; >> - O << " unsigned Features = 0;\n"; >> - >> - for (std::map::const_iterator >> - I = Info.SubtargetFeatures.begin(), >> - E = Info.SubtargetFeatures.end(); I != E; ++I) { >> - SubtargetFeatureInfo &SFI = *I->second; >> - O << " if (" << SFI.TheDef->getValueAsString("CondString") >> - << ")\n"; >> - O << " Features |= " << SFI.getEnumName() << ";\n"; >> - } >> - >> - O << " return Features;\n"; >> - O << "}\n\n"; >> -} >> - >> static void EmitGetMapOperandNumber(raw_ostream &O) { >> O << "static unsigned getMapOperandNumber(" >> << "const SmallVectorImpl > &OpMap,\n"; >> @@ -960,7 +828,6 @@ >> // A map of which conditions need to be met for each instruction operand >> // before it can be matched to the mnemonic. >> std::map > IAPrinterMap; >> - AsmWriterInfo AWI; >> >> for (std::map >::iterator >> I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { >> @@ -977,9 +844,8 @@ >> if (NumResultOps < CountNumOperands(CGA->AsmString)) >> continue; >> >> - IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(), >> + IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), >> CGA->AsmString); >> - IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates")); >> >> std::string Cond; >> Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); >> @@ -1049,9 +915,6 @@ >> } >> } >> >> - EmitSubtargetFeatureFlagEnumeration(AWI, O); >> - EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O); >> - >> std::string Header; >> raw_string_ostream HeaderO(Header); >> >> @@ -1061,7 +924,6 @@ >> >> std::string Cases; >> raw_string_ostream CasesO(Cases); >> - bool NeedAvailableFeatures = false; >> >> for (std::map >::iterator >> I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { >> @@ -1092,7 +954,7 @@ >> II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { >> IAPrinter *IAP = *II; >> CasesO.indent(4); >> - NeedAvailableFeatures |= IAP->print(CasesO); >> + IAP->print(CasesO); >> CasesO << '\n'; >> } >> >> @@ -1112,8 +974,6 @@ >> O << HeaderO.str(); >> O.indent(2) << "StringRef AsmString;\n"; >> O.indent(2) << "SmallVector, 4> OpMap;\n"; >> - if (NeedAvailableFeatures) >> - O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n"; >> O.indent(2) << "switch (MI->getOpcode()) {\n"; >> O.indent(2) << "default: return false;\n"; >> O << CasesO.str(); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From grosser at fim.uni-passau.de Wed Jul 6 14:19:55 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 06 Jul 2011 19:19:55 -0000 Subject: [llvm-commits] [llvm] r134520 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2011-07-06-Alignment.ll Message-ID: <20110706191955.8C9E42A6C12C@llvm.org> Author: grosser Date: Wed Jul 6 14:19:55 2011 New Revision: 134520 URL: http://llvm.org/viewvc/llvm-project?rev=134520&view=rev Log: LICM: Do not loose alignment on promotion The promotion code lost any alignment information, when hoisting loads and stores out of the loop. This lead to incorrect aligned memory accesses. We now use the largest alignment we can prove to be correct. Added: llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=134520&r1=134519&r2=134520&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 6 14:19:55 2011 @@ -606,14 +606,16 @@ SmallVectorImpl &LoopExitBlocks; AliasSetTracker &AST; DebugLoc DL; + int Alignment; public: LoopPromoter(Value *SP, const SmallVectorImpl &Insts, SSAUpdater &S, SmallPtrSet &PMA, SmallVectorImpl &LEB, AliasSetTracker &ast, - DebugLoc dl) + DebugLoc dl, int alignment) : LoadAndStorePromoter(Insts, S, 0, 0), SomePtr(SP), - PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl) {} + PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl), + Alignment(alignment) {} virtual bool isInstInList(Instruction *I, const SmallVectorImpl &) const { @@ -635,6 +637,7 @@ Value *LiveInValue = SSA.GetValueInMiddleOfBlock(ExitBlock); Instruction *InsertPos = ExitBlock->getFirstNonPHI(); StoreInst *NewSI = new StoreInst(LiveInValue, SomePtr, InsertPos); + NewSI->setAlignment(Alignment); NewSI->setDebugLoc(DL); } } @@ -680,10 +683,14 @@ // It is safe to promote P if all uses are direct load/stores and if at // least one is guaranteed to be executed. bool GuaranteedToExecute = false; - + SmallVector LoopUses; SmallPtrSet PointerMustAliases; + // We start with an alignment of one and try to find instructions that allow + // us to prove better alignment. + unsigned Alignment = 1; + // Check that all of the pointers in the alias set have the same type. We // cannot (yet) promote a memory location that is loaded and stored in // different sizes. @@ -706,24 +713,38 @@ // If there is an non-load/store instruction in the loop, we can't promote // it. - if (isa(Use)) + unsigned InstAlignment; + if (LoadInst *load = dyn_cast(Use)) { assert(!cast(Use)->isVolatile() && "AST broken"); - else if (isa(Use)) { + InstAlignment = load->getAlignment(); + } else if (StoreInst *store = dyn_cast(Use)) { // Stores *of* the pointer are not interesting, only stores *to* the // pointer. if (Use->getOperand(1) != ASIV) continue; + InstAlignment = store->getAlignment(); assert(!cast(Use)->isVolatile() && "AST broken"); } else return; // Not a load or store. - + + // If the alignment of this instruction allows us to specify a more + // restrictive (and performant) alignment and if we are sure this + // instruction will be executed, update the alignment. + // Larger is better, with the exception of 0 being the best alignment. + if ((InstAlignment > Alignment || InstAlignment == 0) + && (Alignment != 0)) + if (isSafeToExecuteUnconditionally(*Use)) { + GuaranteedToExecute = true; + Alignment = InstAlignment; + } + if (!GuaranteedToExecute) GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use); LoopUses.push_back(Use); } } - + // If there isn't a guaranteed-to-execute instruction, we can't promote. if (!GuaranteedToExecute) return; @@ -746,13 +767,14 @@ SmallVector NewPHIs; SSAUpdater SSA(&NewPHIs); LoopPromoter Promoter(SomePtr, LoopUses, SSA, PointerMustAliases, ExitBlocks, - *CurAST, DL); + *CurAST, DL, Alignment); // Set up the preheader to have a definition of the value. It is the live-out // value from the preheader that uses in the loop will use. LoadInst *PreheaderLoad = new LoadInst(SomePtr, SomePtr->getName()+".promoted", Preheader->getTerminator()); + PreheaderLoad->setAlignment(Alignment); PreheaderLoad->setDebugLoc(DL); SSA.AddAvailableValue(Preheader, PreheaderLoad); Added: llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll?rev=134520&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll (added) +++ llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll Wed Jul 6 14:19:55 2011 @@ -0,0 +1,26 @@ +; RUN: opt -licm -S %s | FileCheck %s + + at A = common global [1024 x float] zeroinitializer, align 4 + +define i32 @main() nounwind { +entry: + br label %for.cond + +for.cond: + %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr [1024 x float]* @A, i64 0, i64 3 + %vecidx = bitcast float* %arrayidx to <4 x float>* + store <4 x float> zeroinitializer, <4 x float>* %vecidx, align 4 + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp ne i64 %indvar, 1024 + br i1 %exitcond, label %for.body, label %for.end + +for.body: + br label %for.cond + +for.end: + ret i32 0 +} + +;CHECK: store <4 x float> {{.*}} align 4 + From grosser at fim.uni-passau.de Wed Jul 6 14:20:02 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 06 Jul 2011 19:20:02 -0000 Subject: [llvm-commits] [llvm] r134521 - /llvm/trunk/lib/Transforms/Scalar/LICM.cpp Message-ID: <20110706192002.541DD2A6C12D@llvm.org> Author: grosser Date: Wed Jul 6 14:20:02 2011 New Revision: 134521 URL: http://llvm.org/viewvc/llvm-project?rev=134521&view=rev Log: LICM: Remove trailing white spaces Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=134521&r1=134520&r2=134521&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 6 14:20:02 2011 @@ -178,7 +178,7 @@ Pass *llvm::createLICMPass() { return new LICM(); } /// Hoist expressions out of the specified loop. Note, alias info for inner -/// loop is not preserved so it is not a good idea to run LICM multiple +/// loop is not preserved so it is not a good idea to run LICM multiple /// times on one loop. /// bool LICM::runOnLoop(Loop *L, LPPassManager &LPM) { @@ -199,13 +199,13 @@ // What if InnerLoop was modified by other passes ? CurAST->add(*InnerAST); - + // Once we've incorporated the inner loop's AST into ours, we don't need the // subloop's anymore. delete InnerAST; LoopToAliasSetMap.erase(InnerL); } - + CurLoop = L; // Get the preheader block to move instructions into... @@ -245,7 +245,7 @@ I != E; ++I) PromoteAliasSet(*I); } - + // Clear out loops state information for the next iteration CurLoop = 0; Preheader = 0; @@ -283,7 +283,7 @@ for (BasicBlock::iterator II = BB->end(); II != BB->begin(); ) { Instruction &I = *--II; - + // If the instruction is dead, we would try to sink it because it isn't used // in the loop, instead, just delete it. if (isInstructionTriviallyDead(&I)) { @@ -336,7 +336,7 @@ I.eraseFromParent(); continue; } - + // Try hoisting the instruction out to the preheader. We can only do this // if all of the operands of the instruction are loop invariant and if it // is safe to hoist the instruction. @@ -364,7 +364,7 @@ // in the same alias set as something that ends up being modified. if (AA->pointsToConstantMemory(LI->getOperand(0))) return true; - + // Don't hoist loads which have may-aliased stores in loop. uint64_t Size = 0; if (LI->getType()->isSized()) @@ -470,7 +470,7 @@ } return; } - + if (ExitBlocks.empty()) { // The instruction is actually dead if there ARE NO exit blocks. CurAST->deleteValue(&I); @@ -482,30 +482,30 @@ I.eraseFromParent(); return; } - + // Otherwise, if we have multiple exits, use the SSAUpdater to do all of the // hard work of inserting PHI nodes as necessary. SmallVector NewPHIs; SSAUpdater SSA(&NewPHIs); - + if (!I.use_empty()) SSA.Initialize(I.getType(), I.getName()); - + // Insert a copy of the instruction in each exit block of the loop that is // dominated by the instruction. Each exit block is known to only be in the // ExitBlocks list once. BasicBlock *InstOrigBB = I.getParent(); unsigned NumInserted = 0; - + for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) { BasicBlock *ExitBlock = ExitBlocks[i]; - + if (!DT->dominates(InstOrigBB, ExitBlock)) continue; - + // Insert the code after the last PHI node. BasicBlock::iterator InsertPt = ExitBlock->getFirstNonPHI(); - + // If this is the first exit block processed, just move the original // instruction, otherwise clone the original instruction and insert // the copy. @@ -519,12 +519,12 @@ New->setName(I.getName()+".le"); ExitBlock->getInstList().insert(InsertPt, New); } - + // Now that we have inserted the instruction, inform SSAUpdater. if (!I.use_empty()) SSA.AddAvailableValue(ExitBlock, New); } - + // If the instruction doesn't dominate any exit blocks, it must be dead. if (NumInserted == 0) { CurAST->deleteValue(&I); @@ -533,7 +533,7 @@ I.eraseFromParent(); return; } - + // Next, rewrite uses of the instruction, inserting PHI nodes as needed. for (Value::use_iterator UI = I.use_begin(), UE = I.use_end(); UI != UE; ) { // Grab the use before incrementing the iterator. @@ -542,12 +542,12 @@ ++UI; SSA.RewriteUseAfterInsertions(U); } - + // Update CurAST for NewPHIs if I had pointer type. if (I.getType()->isPointerTy()) for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) CurAST->copyValue(&I, NewPHIs[i]); - + // Finally, remove the instruction from CurAST. It is no longer in the loop. CurAST->deleteValue(&I); } @@ -616,7 +616,7 @@ : LoadAndStorePromoter(Insts, S, 0, 0), SomePtr(SP), PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl), Alignment(alignment) {} - + virtual bool isInstInList(Instruction *I, const SmallVectorImpl &) const { Value *Ptr; @@ -626,7 +626,7 @@ Ptr = cast(I)->getPointerOperand(); return PointerMustAliases.count(Ptr); } - + virtual void doExtraRewritesBeforeFinalDeletion() const { // Insert stores after in the loop exit blocks. Each exit block gets a // store of the live-out values that feed them. Since we've already told @@ -664,7 +664,7 @@ if (AS.isForwardingAliasSet() || !AS.isMod() || !AS.isMustAlias() || AS.isVolatile() || !CurLoop->isLoopInvariant(AS.begin()->getValue())) return; - + assert(!AS.empty() && "Must alias set should have at least one pointer element in it!"); Value *SomePtr = AS.begin()->getValue(); @@ -679,7 +679,7 @@ // tmp = *P; for () { if (c) tmp +=1; } *P = tmp; // // is not safe, because *P may only be valid to access if 'c' is true. - // + // // It is safe to promote P if all uses are direct load/stores and if at // least one is guaranteed to be executed. bool GuaranteedToExecute = false; @@ -697,20 +697,20 @@ for (AliasSet::iterator ASI = AS.begin(), E = AS.end(); ASI != E; ++ASI) { Value *ASIV = ASI->getValue(); PointerMustAliases.insert(ASIV); - + // Check that all of the pointers in the alias set have the same type. We // cannot (yet) promote a memory location that is loaded and stored in // different sizes. if (SomePtr->getType() != ASIV->getType()) return; - + for (Value::use_iterator UI = ASIV->use_begin(), UE = ASIV->use_end(); UI != UE; ++UI) { // Ignore instructions that are outside the loop. Instruction *Use = dyn_cast(*UI); if (!Use || !CurLoop->contains(Use)) continue; - + // If there is an non-load/store instruction in the loop, we can't promote // it. unsigned InstAlignment; @@ -740,7 +740,7 @@ if (!GuaranteedToExecute) GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use); - + LoopUses.push_back(Use); } } @@ -748,9 +748,9 @@ // If there isn't a guaranteed-to-execute instruction, we can't promote. if (!GuaranteedToExecute) return; - + // Otherwise, this is safe to promote, lets do it! - DEBUG(dbgs() << "LICM: Promoting value stored to in loop: " <<*SomePtr<<'\n'); + DEBUG(dbgs() << "LICM: Promoting value stored to in loop: " <<*SomePtr<<'\n'); Changed = true; ++NumPromoted; @@ -762,13 +762,13 @@ SmallVector ExitBlocks; CurLoop->getUniqueExitBlocks(ExitBlocks); - + // We use the SSAUpdater interface to insert phi nodes as required. SmallVector NewPHIs; SSAUpdater SSA(&NewPHIs); LoopPromoter Promoter(SomePtr, LoopUses, SSA, PointerMustAliases, ExitBlocks, *CurAST, DL, Alignment); - + // Set up the preheader to have a definition of the value. It is the live-out // value from the preheader that uses in the loop will use. LoadInst *PreheaderLoad = From tobias at grosser.es Wed Jul 6 14:20:52 2011 From: tobias at grosser.es (Tobias Grosser) Date: Wed, 06 Jul 2011 14:20:52 -0500 Subject: [llvm-commits] [PATCH] LICM: Do not loose alignment on promotion In-Reply-To: References: Message-ID: <4E14B594.2020603@grosser.es> On 07/06/2011 01:24 PM, Eli Friedman wrote: > On Wed, Jul 6, 2011 at 9:39 AM, Tobias Grosser wrote: >> >> The promotion code lost any alignment information, when hoisting loads and >> stores out of the loop. This lead to incorrect aligned memory accesses. We now >> use the largest alignment we can prove to be correct. >> --- >> >> lib/Transforms/Scalar/LICM.cpp | 38 ++++++++++++++++++++----- >> test/Transforms/LICM/2011-07-06-Alignment.ll | 26 +++++++++++++++++ >> 2 files changed, 56 insertions(+), 8 deletions(-) >> create mode 100644 test/Transforms/LICM/2011-07-06-Alignment.ll >> >> OK to commit? > > Looks like your patch has tabs; please remove. Done. > Otherwise, looks fine; although, since I touched that code pretty > recently, I'm surprised I didn't spot that issue. Committed in 134520. Cheers Tobi From evan.cheng at apple.com Wed Jul 6 14:36:19 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 12:36:19 -0700 Subject: [llvm-commits] [llvm] r134428 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp In-Reply-To: <20110705184642.71F6B2A6C12C@llvm.org> References: <20110705184642.71F6B2A6C12C@llvm.org> Message-ID: A greedy neural network?! :-) Evan On Jul 5, 2011, at 11:46 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jul 5 13:46:42 2011 > New Revision: 134428 > > URL: http://llvm.org/viewvc/llvm-project?rev=134428&view=rev > Log: > Break infinite loop when the Hopfield network oscillates. > > This is impossible in theory, I can prove it. In practice, our near-zero > threshold can cause the network to oscillate between equally good > solutions. > > > > Modified: > llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134428&r1=134427&r2=134428&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jul 5 13:46:42 2011 > @@ -649,8 +649,6 @@ > > for (;;) { > ArrayRef NewBundles = SpillPlacer->getRecentPositive(); > - if (NewBundles.empty()) > - break; > // Find new through blocks in the periphery of PrefRegBundles. > for (int i = 0, e = NewBundles.size(); i != e; ++i) { > unsigned Bundle = NewBundles[i]; > @@ -670,12 +668,12 @@ > } > } > // Any new blocks to add? > - if (ActiveBlocks.size() > AddedTo) { > - ArrayRef Add(&ActiveBlocks[AddedTo], > - ActiveBlocks.size() - AddedTo); > - addThroughConstraints(Intf, Add); > - AddedTo = ActiveBlocks.size(); > - } > + if (ActiveBlocks.size() == AddedTo) > + break; > + addThroughConstraints(Intf, > + ArrayRef(ActiveBlocks).slice(AddedTo)); > + AddedTo = ActiveBlocks.size(); > + > // Perhaps iterating can enable more bundles? > SpillPlacer->iterate(); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Wed Jul 6 14:39:01 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 06 Jul 2011 12:39:01 -0700 Subject: [llvm-commits] [llvm] r134428 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp In-Reply-To: References: <20110705184642.71F6B2A6C12C@llvm.org> Message-ID: <6D5759AB-AB93-41A5-A42F-C909317D9973@apple.com> On Jul 6, 2011, at 12:36 PM, Evan Cheng wrote: > A greedy neural network?! :-) They are supposed to map the human brain ;) -eric From evan.cheng at apple.com Wed Jul 6 14:45:42 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 19:45:42 -0000 Subject: [llvm-commits] [llvm] r134525 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/InstPrinter/ lib/Target/MBlaze/ lib/Target/MBlaze/InstPrinter/ lib/Target/MSP430/ lib/Target/MSP430/InstPrinter/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/X86/ lib/Target/X86/InstPrinter/ tools/llvm-mc/ tools/llvm-objdump/ Message-ID: <20110706194542.9F58B2A6C12C@llvm.org> Author: evancheng Date: Wed Jul 6 14:45:42 2011 New Revision: 134525 URL: http://llvm.org/viewvc/llvm-project?rev=134525&view=rev Log: createMCInstPrinter doesn't need TargetMachine anymore. Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp llvm/trunk/tools/llvm-mc/Disassembler.cpp llvm/trunk/tools/llvm-mc/Disassembler.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Jul 6 14:45:42 2011 @@ -85,7 +85,6 @@ TargetMachine &TM); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI); typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const Target &T, @@ -334,12 +333,11 @@ return MCDisassemblerCtorFn(*this); } - MCInstPrinter *createMCInstPrinter(TargetMachine &TM, - unsigned SyntaxVariant, + MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant, const MCAsmInfo &MAI) const { if (!MCInstPrinterCtorFn) return 0; - return MCInstPrinterCtorFn(*this, TM, SyntaxVariant, MAI); + return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI); } Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jul 6 14:45:42 2011 @@ -136,7 +136,7 @@ default: return true; case CGFT_AssemblyFile: { MCInstPrinter *InstPrinter = - getTarget().createMCInstPrinter(*this, MAI.getAssemblerDialect(), MAI); + getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI); // Create a code emitter if asked to show the encoding. MCCodeEmitter *MCE = 0; Modified: llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGEmit.cpp Wed Jul 6 14:45:42 2011 @@ -45,6 +45,7 @@ unsigned Reg = 0; for (SUnit::const_succ_iterator II = SU->Succs.begin(), EE = SU->Succs.end(); II != EE; ++II) { + if (II->isCtrl()) continue; // ignore chain preds if (II->getReg()) { Reg = II->getReg(); break; Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jul 6 14:45:42 2011 @@ -79,7 +79,7 @@ // Set up the instruction printer. int AsmPrinterVariant = MAI->getAssemblerDialect(); - MCInstPrinter *IP = TheTarget->createMCInstPrinter(*TM, AsmPrinterVariant, + MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant, *MAI); assert(IP && "Unable to create instruction printer!"); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Jul 6 14:45:42 2011 @@ -193,8 +193,7 @@ InstString.reset(new std::string); InstStream.reset(new raw_string_ostream(*InstString)); - InstPrinter.reset(Tgt->createMCInstPrinter(*TargetMachine, LLVMSyntaxVariant, - *AsmInfo)); + InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo)); if (!InstPrinter) return; Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -1954,11 +1954,10 @@ //===----------------------------------------------------------------------===// static MCInstPrinter *createARMMCInstPrinter(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new ARMInstPrinter(TM, MAI); + return new ARMInstPrinter(MAI); return 0; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jul 6 14:45:42 2011 @@ -19,11 +19,10 @@ namespace llvm { class MCOperand; -class TargetMachine; class ARMInstPrinter : public MCInstPrinter { public: - ARMInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) + ARMInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} virtual void printInst(const MCInst *MI, raw_ostream &O); Modified: llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h (original) +++ llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h Wed Jul 6 14:45:42 2011 @@ -18,11 +18,10 @@ namespace llvm { class MCOperand; - class TargetMachine; class MBlazeInstPrinter : public MCInstPrinter { public: - MBlazeInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) + MBlazeInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} virtual void printInst(const MCInst *MI, raw_ostream &O); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -319,11 +319,10 @@ } static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new MBlazeInstPrinter(TM, MAI); + return new MBlazeInstPrinter(MAI); return 0; } Modified: llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h (original) +++ llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h Wed Jul 6 14:45:42 2011 @@ -18,11 +18,10 @@ namespace llvm { class MCOperand; - class TargetMachine; class MSP430InstPrinter : public MCInstPrinter { public: - MSP430InstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) + MSP430InstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} virtual void printInst(const MCInst *MI, raw_ostream &O); Modified: llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -164,11 +164,10 @@ } static MCInstPrinter *createMSP430MCInstPrinter(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new MSP430InstPrinter(TM, MAI); + return new MSP430InstPrinter(MAI); return 0; } Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Wed Jul 6 14:45:42 2011 @@ -19,14 +19,12 @@ namespace llvm { class MCOperand; -class TargetMachine; class PPCInstPrinter : public MCInstPrinter { // 0 -> AIX, 1 -> Darwin. unsigned SyntaxVariant; public: - PPCInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI, - unsigned syntaxVariant) + PPCInstPrinter(const MCAsmInfo &MAI, unsigned syntaxVariant) : MCInstPrinter(MAI), SyntaxVariant(syntaxVariant) {} bool isDarwinSyntax() const { Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -680,10 +680,9 @@ } static MCInstPrinter *createPPCMCInstPrinter(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI) { - return new PPCInstPrinter(TM, MAI, SyntaxVariant); + return new PPCInstPrinter(MAI, SyntaxVariant); } Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -15,7 +15,6 @@ #define DEBUG_TYPE "asm-printer" #include "X86ATTInstPrinter.h" #include "X86InstComments.h" -#include "X86Subtarget.h" #include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" @@ -31,7 +30,7 @@ #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter.inc" -X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) +X86ATTInstPrinter::X86ATTInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) { } Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Wed Jul 6 14:45:42 2011 @@ -19,12 +19,10 @@ namespace llvm { class MCOperand; -class X86Subtarget; -class TargetMachine; class X86ATTInstPrinter : public MCInstPrinter { public: - X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); + X86ATTInstPrinter(const MCAsmInfo &MAI); virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -15,7 +15,6 @@ #define DEBUG_TYPE "asm-printer" #include "X86IntelInstPrinter.h" #include "X86InstComments.h" -#include "X86Subtarget.h" #include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Wed Jul 6 14:45:42 2011 @@ -20,11 +20,10 @@ namespace llvm { class MCOperand; -class TargetMachine; class X86IntelInstPrinter : public MCInstPrinter { public: - X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) + X86IntelInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Wed Jul 6 14:45:42 2011 @@ -709,13 +709,12 @@ //===----------------------------------------------------------------------===// static MCInstPrinter *createX86MCInstPrinter(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new X86ATTInstPrinter(TM, MAI); + return new X86ATTInstPrinter(MAI); if (SyntaxVariant == 1) - return new X86IntelInstPrinter(TM, MAI); + return new X86IntelInstPrinter(MAI); return 0; } Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original) +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Jul 6 14:45:42 2011 @@ -127,7 +127,7 @@ return false; } -int Disassembler::disassemble(const Target &T, TargetMachine &TM, +int Disassembler::disassemble(const Target &T, const std::string &Triple, MemoryBuffer &Buffer, raw_ostream &Out) { @@ -146,7 +146,7 @@ } int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); - OwningPtr IP(T.createMCInstPrinter(TM, AsmPrinterVariant, + OwningPtr IP(T.createMCInstPrinter(AsmPrinterVariant, *AsmInfo)); if (!IP) { errs() << "error: no instruction printer for target " << Triple << '\n'; Modified: llvm/trunk/tools/llvm-mc/Disassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.h?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/Disassembler.h (original) +++ llvm/trunk/tools/llvm-mc/Disassembler.h Wed Jul 6 14:45:42 2011 @@ -21,13 +21,11 @@ class MemoryBuffer; class Target; -class TargetMachine; class raw_ostream; class Disassembler { public: static int disassemble(const Target &target, - TargetMachine &TM, const std::string &tripleString, MemoryBuffer &buffer, raw_ostream &Out); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jul 6 14:45:42 2011 @@ -343,7 +343,7 @@ // FIXME: There is a bit of code duplication with addPassesToEmitFile. if (FileType == OFT_AssemblyFile) { MCInstPrinter *IP = - TheTarget->createMCInstPrinter(*TM, OutputAsmVariant, *MAI); + TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI); MCCodeEmitter *CE = 0; TargetAsmBackend *TAB = 0; if (ShowEncoding) { @@ -426,7 +426,7 @@ return 1; } - Res = Disassembler::disassemble(*TheTarget, *TM, TripleName, + Res = Disassembler::disassemble(*TheTarget, TripleName, *Buffer.take(), Out->os()); } Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=134525&r1=134524&r2=134525&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Jul 6 14:45:42 2011 @@ -38,7 +38,6 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/system_error.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSelect.h" #include @@ -196,22 +195,9 @@ return; } - // FIXME: We shouldn't need to do this (and link in codegen). - // When we split this out, we should do it in a way that makes - // it straightforward to switch subtargets on the fly (.e.g, - // the .cpu and .code16 directives). - std::string FeaturesStr; - std::string CPU; - OwningPtr TM(TheTarget->createTargetMachine(TripleName, CPU, - FeaturesStr)); - if (!TM) { - errs() << "error: could not create target for triple " << TripleName << "\n"; - return; - } - int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); OwningPtr IP(TheTarget->createMCInstPrinter( - *TM, AsmPrinterVariant, *AsmInfo)); + AsmPrinterVariant, *AsmInfo)); if (!IP) { errs() << "error: no instruction printer for target " << TripleName << '\n'; return; From stoklund at 2pi.dk Wed Jul 6 14:56:24 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 06 Jul 2011 12:56:24 -0700 Subject: [llvm-commits] [llvm] r134428 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp In-Reply-To: References: <20110705184642.71F6B2A6C12C@llvm.org> Message-ID: <325ED6C2-4716-4BA4-8BAE-0199DEA26965@2pi.dk> On Jul 6, 2011, at 12:36 PM, Evan Cheng wrote: > A greedy neural network?! :-) That's right. If you feed him bad code, he will be very upset ;-) But this is not in any way an attempt at AI. It just so happens that the equation describing the optimal region for splitting is identical to the Hopfield network energy equation. The same equation also describes the ground state of a spin glass. /jakob From wendling at apple.com Wed Jul 6 15:17:37 2011 From: wendling at apple.com (Bill Wendling) Date: Wed, 06 Jul 2011 13:17:37 -0700 Subject: [llvm-commits] [llvm] r134457 - in /llvm/trunk: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h utils/TableGen/AsmWriterEmitter.cpp In-Reply-To: <543CED00-86CF-47A5-A44A-3D9A566369C9@apple.com> References: <20110706020233.C01A02A6C12C@llvm.org> <543CED00-86CF-47A5-A44A-3D9A566369C9@apple.com> Message-ID: <0BA87A66-63AB-49BF-8EDE-41CA5F54A32A@apple.com> On Jul 6, 2011, at 12:05 PM, Evan Cheng wrote: > Right. If we want to do this, we should figure out a better way to handle this. We want to eliminate the dependency of asm writer on the target layer. > Okay, great! This gets rid of that horribleness that I had to put into the inst-alias printer. The documentation needs to be updated too. :-) -bw From isanbard at gmail.com Wed Jul 6 15:33:48 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Jul 2011 20:33:48 -0000 Subject: [llvm-commits] [llvm] r134527 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetRegisterInfo.h lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.h Message-ID: <20110706203348.8C9292A6C12C@llvm.org> Author: void Date: Wed Jul 6 15:33:48 2011 New Revision: 134527 URL: http://llvm.org/viewvc/llvm-project?rev=134527&view=rev Log: Constify getCompactUnwindRegNum. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=134527&r1=134526&r2=134527&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jul 6 15:33:48 2011 @@ -107,8 +107,8 @@ return TRI->getSEHRegNum(RegNum); } - int getCompactUnwindRegNum(unsigned RegNum) const { - return TRI->getCompactUnwindRegNum(RegNum); + int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { + return TRI->getCompactUnwindRegNum(RegNum, isEH); } }; Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=134527&r1=134526&r2=134527&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Jul 6 15:33:48 2011 @@ -723,7 +723,7 @@ /// getCompactUnwindRegNum - This function maps the register to the number for /// compact unwind encoding. Return -1 if the register isn't valid. - virtual int getCompactUnwindRegNum(unsigned) const { + virtual int getCompactUnwindRegNum(unsigned, bool) const { return -1; } }; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134527&r1=134526&r2=134527&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Jul 6 15:33:48 2011 @@ -107,8 +107,8 @@ /// getCompactUnwindRegNum - This function maps the register to the number for /// compact unwind encoding. Return -1 if the register isn't valid. -int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum) const { - switch (RegNum) { +int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { + switch (getLLVMRegNum(RegNum, isEH)) { case X86::EBX: case X86::RBX: return 1; case X86::ECX: case X86::R12: return 2; case X86::EDX: case X86::R13: return 3; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=134527&r1=134526&r2=134527&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Wed Jul 6 15:33:48 2011 @@ -83,7 +83,7 @@ /// getCompactUnwindRegNum - This function maps the register to the number for /// compact unwind encoding. Return -1 if the register isn't valid. - int getCompactUnwindRegNum(unsigned RegNum) const; + int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const; /// Code Generation virtual methods... /// From eli.friedman at gmail.com Wed Jul 6 15:48:27 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 06 Jul 2011 20:48:27 -0000 Subject: [llvm-commits] [llvm] r134528 - /llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Message-ID: <20110706204827.991322A6C12C@llvm.org> Author: efriedma Date: Wed Jul 6 15:48:27 2011 New Revision: 134528 URL: http://llvm.org/viewvc/llvm-project?rev=134528&view=rev Log: Remove some unnecessary includes. Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=134528&r1=134527&r2=134528&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Jul 6 15:48:27 2011 @@ -14,12 +14,6 @@ //===----------------------------------------------------------------------===// #include "llvm/Object/ObjectFile.h" -// This config must be included before llvm-config.h. -#include "llvm/Config/config.h" -#include "../../lib/MC/MCDisassembler/EDDisassembler.h" -#include "../../lib/MC/MCDisassembler/EDInst.h" -#include "../../lib/MC/MCDisassembler/EDOperand.h" -#include "../../lib/MC/MCDisassembler/EDToken.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmInfo.h" @@ -41,8 +35,6 @@ #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSelect.h" #include -#include -#include #include using namespace llvm; using namespace object; From atrick at apple.com Wed Jul 6 15:50:43 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 06 Jul 2011 20:50:43 -0000 Subject: [llvm-commits] [llvm] r134530 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll Message-ID: <20110706205043.C5B3A2A6C12C@llvm.org> Author: atrick Date: Wed Jul 6 15:50:43 2011 New Revision: 134530 URL: http://llvm.org/viewvc/llvm-project?rev=134530&view=rev Log: indvars -disable-iv-rewrite: Added SimplifyCongruentIVs. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134530&r1=134529&r2=134530&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jul 6 15:50:43 2011 @@ -58,6 +58,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Target/TargetData.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" @@ -72,6 +73,7 @@ STATISTIC(NumElimExt , "Number of IV sign/zero extends eliminated"); STATISTIC(NumElimRem , "Number of IV remainder operations eliminated"); STATISTIC(NumElimCmp , "Number of IV comparisons eliminated"); +STATISTIC(NumElimIV , "Number of congruent IVs eliminated"); static cl::opt DisableIVRewrite( "disable-iv-rewrite", cl::Hidden, @@ -79,12 +81,15 @@ namespace { class IndVarSimplify : public LoopPass { + typedef DenseMap ExprToIVMapTy; + IVUsers *IU; LoopInfo *LI; ScalarEvolution *SE; DominatorTree *DT; TargetData *TD; + ExprToIVMapTy ExprToIVMap; SmallVector DeadInsts; bool Changed; public: @@ -114,6 +119,11 @@ } private: + virtual void releaseMemory() { + ExprToIVMap.clear(); + DeadInsts.clear(); + } + bool isValidRewrite(Value *FromVal, Value *ToVal); void SimplifyIVUsers(SCEVExpander &Rewriter); @@ -133,6 +143,8 @@ void RewriteLoopExitValues(Loop *L, SCEVExpander &Rewriter); + void SimplifyCongruentIVs(Loop *L); + void RewriteIVExpressions(Loop *L, SCEVExpander &Rewriter); void SinkUnusedInvariants(Loop *L); @@ -1129,7 +1141,7 @@ // Instructions processed by SimplifyIVUsers for CurrIV. SmallPtrSet Simplified; - // Use-def pairs if IVUsers waiting to be processed for CurrIV. + // Use-def pairs if IV users waiting to be processed for CurrIV. SmallVector, 8> SimpleIVUsers; // Push users of the current LoopPhi. In rare cases, pushIVUsers may be @@ -1175,6 +1187,45 @@ } } +/// SimplifyCongruentIVs - Check for congruent phis in this loop header and +/// populate ExprToIVMap for use later. +/// +void IndVarSimplify::SimplifyCongruentIVs(Loop *L) { + for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) { + PHINode *Phi = cast(I); + const SCEV *S = SE->getSCEV(Phi); + ExprToIVMapTy::const_iterator Pos; + bool Inserted; + tie(Pos, Inserted) = ExprToIVMap.insert(std::make_pair(S, Phi)); + if (Inserted) + continue; + PHINode *OrigPhi = Pos->second; + // Replacing the congruent phi is sufficient because acyclic redundancy + // elimination, CSE/GVN, should handle the rest. However, once SCEV proves + // that a phi is congruent, it's almost certain to be the head of an IV + // user cycle that is isomorphic with the original phi. So it's worth + // eagerly cleaning up the common case of a single IV increment. + if (BasicBlock *LatchBlock = L->getLoopLatch()) { + Instruction *OrigInc = + cast(OrigPhi->getIncomingValueForBlock(LatchBlock)); + Instruction *IsomorphicInc = + cast(Phi->getIncomingValueForBlock(LatchBlock)); + if (OrigInc != IsomorphicInc && + SE->getSCEV(OrigInc) == SE->getSCEV(IsomorphicInc) && + HoistStep(OrigInc, IsomorphicInc, DT)) { + DEBUG(dbgs() << "INDVARS: Eliminated congruent iv.inc: " + << *IsomorphicInc << '\n'); + IsomorphicInc->replaceAllUsesWith(OrigInc); + DeadInsts.push_back(IsomorphicInc); + } + } + DEBUG(dbgs() << "INDVARS: Eliminated congruent iv: " << *Phi << '\n'); + ++NumElimIV; + Phi->replaceAllUsesWith(OrigPhi); + DeadInsts.push_back(Phi); + } +} + bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) { // If LoopSimplify form is not available, stay out of trouble. Some notes: // - LSR currently only supports LoopSimplify-form loops. Indvars' @@ -1194,6 +1245,7 @@ DT = &getAnalysis(); TD = getAnalysisIfAvailable(); + ExprToIVMap.clear(); DeadInsts.clear(); Changed = false; @@ -1230,6 +1282,11 @@ if (!DisableIVRewrite) SimplifyIVUsers(Rewriter); + // Eliminate redundant IV cycles and populate ExprToIVMap. + // TODO: use ExprToIVMap to allow LFTR without canonical IVs + if (DisableIVRewrite) + SimplifyCongruentIVs(L); + // Compute the type of the largest recurrence expression, and decide whether // a canonical induction variable should be inserted. const Type *LargestType = 0; Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134530&r1=134529&r2=134530&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Wed Jul 6 15:50:43 2011 @@ -270,3 +270,53 @@ return: ret i32 %i.0 } + +; Eliminate the congruent phis j, k, and l. +; Eliminate the redundant IV increments k.next and l.next. +; Two phis should remain, one starting at %init, and one at %init1. +; Two increments should remain, one by %step and one by %step1. +; CHECK: loop: +; CHECK: phi i32 +; CHECK: phi i32 +; CHECK-NOT: phi +; CHECK: add i32 +; CHECK: add i32 +; CHECK-NOT: add +; CHECK: return: +; +; Five live-outs should remain. +; CHECK: lcssa = phi +; CHECK: lcssa = phi +; CHECK: lcssa = phi +; CHECK: lcssa = phi +; CHECK: lcssa = phi +; CHECK-NOT: phi +; CHECK: ret +define i32 @isomorphic(i32 %init, i32 %step, i32 %lim) nounwind { +entry: + %step1 = add i32 %step, 1 + %init1 = add i32 %init, %step1 + %l.0 = sub i32 %init1, %step1 + br label %loop + +loop: + %ii = phi i32 [ %init1, %entry ], [ %ii.next, %loop ] + %i = phi i32 [ %init, %entry ], [ %ii, %loop ] + %j = phi i32 [ %init, %entry ], [ %j.next, %loop ] + %k = phi i32 [ %init1, %entry ], [ %k.next, %loop ] + %l = phi i32 [ %l.0, %entry ], [ %l.next, %loop ] + %ii.next = add i32 %ii, %step1 + %j.next = add i32 %j, %step1 + %k.next = add i32 %k, %step1 + %l.step = add i32 %l, %step + %l.next = add i32 %l.step, 1 + %cmp = icmp ne i32 %ii.next, %lim + br i1 %cmp, label %loop, label %return + +return: + %sum1 = add i32 %i, %j.next + %sum2 = add i32 %sum1, %k.next + %sum3 = add i32 %sum1, %l.step + %sum4 = add i32 %sum1, %l.next + ret i32 %sum4 +} Modified: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll?rev=134530&r1=134529&r2=134530&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll Wed Jul 6 15:50:43 2011 @@ -1,9 +1,9 @@ -; RUN: opt < %s -indvars -instcombine -S | \ -; RUN: grep {store i32 0} +; RUN: opt < %s -indvars -instcombine -S | FileCheck %s +; RUN: opt < %s -indvars -disable-iv-rewrite -instcombine -S | FileCheck %s +; ; Test that -indvars can reduce variable stride IVs. If it can reduce variable -; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without +; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without ; cycles, allowing the tmp.21 subtraction to be eliminated. -; END. define void @vnum_test8(i32* %data) { entry: @@ -20,6 +20,7 @@ %tmp.16 = getelementptr i32* %data, i32 %tmp.9 ; [#uses=1] br label %no_exit +; CHECK: store i32 0 no_exit: ; preds = %no_exit, %no_exit.preheader %iv.ui = phi i32 [ 0, %no_exit.preheader ], [ %iv..inc.ui, %no_exit ] ; [#uses=1] %iv. = phi i32 [ %tmp.5, %no_exit.preheader ], [ %iv..inc, %no_exit ] ; [#uses=2] From eli.friedman at gmail.com Wed Jul 6 15:56:26 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 06 Jul 2011 20:56:26 -0000 Subject: [llvm-commits] [llvm] r134532 - /llvm/trunk/lib/Support/Triple.cpp Message-ID: <20110706205626.F08C42A6C12C@llvm.org> Author: efriedma Date: Wed Jul 6 15:56:26 2011 New Revision: 134532 URL: http://llvm.org/viewvc/llvm-project?rev=134532&view=rev Log: Fix missing triple support for RTEMS target. Modified: llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=134532&r1=134531&r2=134532&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Wed Jul 6 15:56:26 2011 @@ -351,6 +351,8 @@ return Haiku; else if (OSName.startswith("minix")) return Minix; + else if (OSName.startswith("rtems")) + return RTEMS; else return UnknownOS; } From grosbach at apple.com Wed Jul 6 15:57:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 06 Jul 2011 20:57:35 -0000 Subject: [llvm-commits] [llvm] r134533 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110706205735.55F192A6C12C@llvm.org> Author: grosbach Date: Wed Jul 6 15:57:35 2011 New Revision: 134533 URL: http://llvm.org/viewvc/llvm-project?rev=134533&view=rev Log: Remove un-used encoding info from Pseudo MLAv5. Pseudo-instructions don't have encoding information, as they're lowered to real instructions by the time we're doing binary encoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134533&r1=134532&r2=134533&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 6 15:57:35 2011 @@ -2698,10 +2698,7 @@ (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), Size4Bytes, IIC_iMAC32, [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, - Requires<[IsARM, NoV6]> { - bits<4> Ra; - let Inst{15-12} = Ra; -} + Requires<[IsARM, NoV6]>; def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, From atrick at apple.com Wed Jul 6 16:07:10 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 06 Jul 2011 21:07:10 -0000 Subject: [llvm-commits] [llvm] r134537 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110706210710.436CA2A6C12C@llvm.org> Author: atrick Date: Wed Jul 6 16:07:10 2011 New Revision: 134537 URL: http://llvm.org/viewvc/llvm-project?rev=134537&view=rev Log: indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be more careful about referencing values. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134537&r1=134536&r2=134537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jul 6 16:07:10 2011 @@ -81,7 +81,7 @@ namespace { class IndVarSimplify : public LoopPass { - typedef DenseMap ExprToIVMapTy; + typedef DenseMap< const SCEV *, AssertingVH > ExprToIVMapTy; IVUsers *IU; LoopInfo *LI; @@ -1375,6 +1375,7 @@ // can be deleted in the loop below, causing the AssertingVH in the cache to // trigger. Rewriter.clear(); + ExprToIVMap.clear(); // Now that we're done iterating through lists, clean up any instructions // which are now dead. From dpatel at apple.com Wed Jul 6 16:09:55 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 06 Jul 2011 21:09:55 -0000 Subject: [llvm-commits] [llvm] r134538 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/SSAUpdater.cpp Message-ID: <20110706210955.A067B2A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 16:09:55 2011 New Revision: 134538 URL: http://llvm.org/viewvc/llvm-project?rev=134538&view=rev Log: Simplify. Consolidate dbg.declare handling in AllocaPromoter. Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=134538&r1=134537&r2=134538&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Wed Jul 6 16:09:55 2011 @@ -122,12 +122,9 @@ class LoadAndStorePromoter { protected: SSAUpdater &SSA; - DbgDeclareInst *DDI; - DIBuilder *DIB; public: LoadAndStorePromoter(const SmallVectorImpl &Insts, - SSAUpdater &S, DbgDeclareInst *DDI, DIBuilder *DIB, - StringRef Name = StringRef()); + SSAUpdater &S, StringRef Name = StringRef()); virtual ~LoadAndStorePromoter() {} /// run - This does the promotion. Insts is a list of loads and stores to @@ -161,6 +158,10 @@ virtual void instructionDeleted(Instruction *I) const { } + /// updateDebugInfo - This is called to update debug info associated with the + /// instruction. + virtual void updateDebugInfo(Instruction *I) const { + } }; } // End llvm namespace Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=134538&r1=134537&r2=134538&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 6 16:09:55 2011 @@ -613,7 +613,7 @@ SmallPtrSet &PMA, SmallVectorImpl &LEB, AliasSetTracker &ast, DebugLoc dl, int alignment) - : LoadAndStorePromoter(Insts, S, 0, 0), SomePtr(SP), + : LoadAndStorePromoter(Insts, S), SomePtr(SP), PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl), Alignment(alignment) {} Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=134538&r1=134537&r2=134538&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jul 6 16:09:55 2011 @@ -1094,16 +1094,21 @@ namespace { class AllocaPromoter : public LoadAndStorePromoter { AllocaInst *AI; + DbgDeclareInst *DDI; + DIBuilder *DIB; public: AllocaPromoter(const SmallVectorImpl &Insts, SSAUpdater &S, - DbgDeclareInst *DD, DIBuilder *&DB) - : LoadAndStorePromoter(Insts, S, DD, DB), AI(0) {} + DIBuilder *DB) + : LoadAndStorePromoter(Insts, S), AI(0), DDI(0), DIB(DB) {} void run(AllocaInst *AI, const SmallVectorImpl &Insts) { // Remember which alloca we're promoting (for isInstInList). this->AI = AI; + DDI = FindAllocaDbgDeclare(AI); LoadAndStorePromoter::run(Insts); AI->eraseFromParent(); + if (DDI) + DDI->eraseFromParent(); } virtual bool isInstInList(Instruction *I, @@ -1112,6 +1117,15 @@ return LI->getOperand(0) == AI; return cast(I)->getPointerOperand() == AI; } + + virtual void updateDebugInfo(Instruction *I) const { + if (!DDI) + return; + if (StoreInst *SI = dyn_cast(I)) + ConvertDebugDeclareToDebugValue(DDI, SI, *DIB); + else if (LoadInst *LI = dyn_cast(I)) + ConvertDebugDeclareToDebugValue(DDI, LI, *DIB); + } }; } // end anon namespace @@ -1381,10 +1395,9 @@ DT = &getAnalysis(); BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function - + DIBuilder DIB(*F.getParent()); bool Changed = false; SmallVector Insts; - DIBuilder *DIB = 0; while (1) { Allocas.clear(); @@ -1408,11 +1421,7 @@ for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ++UI) Insts.push_back(cast(*UI)); - - DbgDeclareInst *DDI = FindAllocaDbgDeclare(AI); - if (DDI && !DIB) - DIB = new DIBuilder(*AI->getParent()->getParent()->getParent()); - AllocaPromoter(Insts, SSA, DDI, DIB).run(AI, Insts); + AllocaPromoter(Insts, SSA, &DIB).run(AI, Insts); Insts.clear(); } } @@ -1420,10 +1429,6 @@ Changed = true; } - // FIXME: Is there a better way to handle the lazy initialization of DIB - // so that there doesn't need to be an explicit delete? - delete DIB; - return Changed; } Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=134538&r1=134537&r2=134538&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Wed Jul 6 16:09:55 2011 @@ -16,7 +16,6 @@ #include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/Analysis/DIBuilder.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Support/AlignOf.h" #include "llvm/Support/Allocator.h" @@ -358,8 +357,7 @@ LoadAndStorePromoter:: LoadAndStorePromoter(const SmallVectorImpl &Insts, - SSAUpdater &S, DbgDeclareInst *DD, DIBuilder *DB, - StringRef BaseName) : SSA(S), DDI(DD), DIB(DB) { + SSAUpdater &S, StringRef BaseName) : SSA(S) { if (Insts.empty()) return; Value *SomeVal; @@ -407,8 +405,7 @@ if (BlockUses.size() == 1) { // If it is a store, it is a trivial def of the value in the block. if (StoreInst *SI = dyn_cast(User)) { - if (DDI) - ConvertDebugDeclareToDebugValue(DDI, SI, *DIB); + updateDebugInfo(SI); SSA.AddAvailableValue(BB, SI->getOperand(0)); } else // Otherwise it is a load, queue it to rewrite as a live-in load. @@ -462,9 +459,7 @@ if (StoreInst *SI = dyn_cast(II)) { // If this is a store to an unrelated pointer, ignore it. if (!isInstInList(SI, Insts)) continue; - - if (DDI) - ConvertDebugDeclareToDebugValue(DDI, SI, *DIB); + updateDebugInfo(SI); // Remember that this is the active value in the block. StoredValue = SI->getOperand(0); @@ -522,7 +517,4 @@ instructionDeleted(User); User->eraseFromParent(); } - - if (DDI) - DDI->eraseFromParent(); } From grosbach at apple.com Wed Jul 6 16:33:39 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 06 Jul 2011 21:33:39 -0000 Subject: [llvm-commits] [llvm] r134539 - in /llvm/trunk: include/llvm/Target/Target.td utils/TableGen/ARMDecoderEmitter.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/EDEmitter.cpp utils/TableGen/FixedLenDecoderEmitter.cpp Message-ID: <20110706213339.2EB0F2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 6 16:33:38 2011 New Revision: 134539 URL: http://llvm.org/viewvc/llvm-project?rev=134539&view=rev Log: Don't require pseudo-instructions to carry encoding information. For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp llvm/trunk/utils/TableGen/CodeEmitterGen.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h llvm/trunk/utils/TableGen/EDEmitter.cpp llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Wed Jul 6 16:33:38 2011 @@ -324,6 +324,9 @@ bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? + bit isPseudo = 0; // Is this instruction a pseudo-instruction? + // If so, won't have encoding information for + // the [MC]CodeEmitter stuff. // Side effect flags - When set, the flags have these meanings: // @@ -338,6 +341,11 @@ // Is this instruction a "real" instruction (with a distinct machine // encoding), or is it a pseudo instruction used for codegen modeling // purposes. + // FIXME: For now this is distinct from isPseudo, above, as code-gen-only + // instructions can (and often do) still have encoding information + // associated with them. Once we've migrated all of them over to true + // pseudo-instructions that are lowered to real instructions prior to + // the printer/emitter, we can remove this attribute and just use isPseudo. bit isCodeGenOnly = 0; // Is this instruction a pseudo instruction for use by the assembler parser. Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jul 6 16:33:38 2011 @@ -421,6 +421,9 @@ protected: // Populates the insn given the uid. void insnWithID(insn_t &Insn, unsigned Opcode) const { + if (AllInstructions[Opcode]->isPseudo) + return; + BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); for (unsigned i = 0; i < BIT_WIDTH; ++i) Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Wed Jul 6 16:33:38 2011 @@ -34,7 +34,8 @@ for (std::vector::iterator I = Insts.begin(), E = Insts.end(); I != E; ++I) { Record *R = *I; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; BitsInit *BI = R->getValueAsBitsInit("Inst"); @@ -231,7 +232,8 @@ const CodeGenInstruction *CGI = *IN; Record *R = CGI->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") { + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { o << " 0U,\n"; continue; } @@ -255,7 +257,8 @@ for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); IC != EC; ++IC) { Record *R = *IC; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; const std::string &InstName = R->getValueAsString("Namespace") + "::" + R->getName(); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Wed Jul 6 16:33:38 2011 @@ -311,6 +311,7 @@ isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove"); hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); + isPseudo = R->getValueAsBit("isPseudo"); ImplicitDefs = R->getValueAsListOfDefs("Defs"); ImplicitUses = R->getValueAsListOfDefs("Uses"); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Wed Jul 6 16:33:38 2011 @@ -235,6 +235,7 @@ bool isAsCheapAsAMove; bool hasExtraSrcRegAllocReq; bool hasExtraDefRegAllocReq; + bool isPseudo; CodeGenInstruction(Record *R); Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Jul 6 16:33:38 2011 @@ -774,6 +774,11 @@ for (index = 0; index < numInstructions; ++index) { const CodeGenInstruction& inst = *numberedInstructions[index]; + // We don't need to do anything for pseudo-instructions, as we'll never + // see them here. We'll only see real instructions. + if (inst.isPseudo) + continue; + CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter; infoArray.addEntry(infoStruct); Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=134539&r1=134538&r2=134539&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Jul 6 16:33:38 2011 @@ -1225,14 +1225,14 @@ // // This also removes pseudo instructions from considerations of disassembly, // which is a better design and less fragile than the name matchings. - BitsInit &Bits = getBitsField(Def, "Inst"); - if (Bits.allInComplete()) return false; - // Ignore "asm parser only" instructions. if (Def.getValueAsBit("isAsmParserOnly") || Def.getValueAsBit("isCodeGenOnly")) return false; + BitsInit &Bits = getBitsField(Def, "Inst"); + if (Bits.allInComplete()) return false; + std::vector InsnOperands; // If the instruction has specified a custom decoding hook, use that instead @@ -1354,7 +1354,8 @@ void FixedLenDecoderEmitter::populateInstructions() { for (unsigned i = 0, e = NumberedInstructions.size(); i < e; ++i) { Record *R = NumberedInstructions[i]->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; if (populateInstruction(*NumberedInstructions[i], i)) From grosbach at apple.com Wed Jul 6 16:35:46 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 06 Jul 2011 21:35:46 -0000 Subject: [llvm-commits] [llvm] r134540 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20110706213546.6A7D12A6C12C@llvm.org> Author: grosbach Date: Wed Jul 6 16:35:46 2011 New Revision: 134540 URL: http://llvm.org/viewvc/llvm-project?rev=134540&view=rev Log: Mark ARM pseudo-instructions as isPseudo. This allows us to remove the (bogus and unneeded) encoding information from the pseudo-instruction class definitions. All of the pseudos that haven't been converted yet and still need encoding information instance from the normal instruction classes and explicitly set isCodeGenOnly, and so are distinct from this change. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=134540&r1=134539&r2=134540&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 6 16:35:46 2011 @@ -282,15 +282,13 @@ : InstTemplate; class PseudoInst pattern> - // FIXME: This really should derive from InstTemplate instead, as pseudos - // don't need encoding information. TableGen doesn't like that - // currently. Need to figure out why and fix it. - : InstARM { + : InstTemplate { let OutOperandList = oops; let InOperandList = iops; let Pattern = pattern; let isCodeGenOnly = 1; + let isPseudo = 1; } // PseudoInst that's ARM-mode only. From nicholas at mxc.ca Wed Jul 6 16:59:48 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 06 Jul 2011 21:59:48 -0000 Subject: [llvm-commits] [llvm] r134545 - /llvm/trunk/include/llvm/ADT/ImmutableList.h Message-ID: <20110706215948.F24222A6C12C@llvm.org> Author: nicholas Date: Wed Jul 6 16:59:48 2011 New Revision: 134545 URL: http://llvm.org/viewvc/llvm-project?rev=134545&view=rev Log: Add ImmutableList::contains(). Patch by Rui Paulo! Modified: llvm/trunk/include/llvm/ADT/ImmutableList.h Modified: llvm/trunk/include/llvm/ADT/ImmutableList.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableList.h?rev=134545&r1=134544&r2=134545&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableList.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableList.h Wed Jul 6 16:59:48 2011 @@ -103,6 +103,14 @@ /// isEmpty - Returns true if the list is empty. bool isEmpty() const { return !X; } + bool contains(const T& V) const { + for (iterator I = begin(), E = end(); I != E; ++I) { + if (*I == V) + return true; + } + return false; + } + /// isEqual - Returns true if two lists are equal. Because all lists created /// from the same ImmutableListFactory are uniqued, this has O(1) complexity /// because it the contents of the list do not need to be compared. Note From evan.cheng at apple.com Wed Jul 6 17:01:53 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 22:01:53 -0000 Subject: [llvm-commits] [llvm] r134546 - in /llvm/trunk/lib/Target/X86: InstPrinter/X86ATTInstPrinter.cpp InstPrinter/X86InstComments.cpp InstPrinter/X86IntelInstPrinter.cpp MCTargetDesc/CMakeLists.txt MCTargetDesc/X86MCTargetDesc.cpp MCTargetDesc/X86MCTargetDesc.h MCTargetDesc/X86TargetDesc.cpp MCTargetDesc/X86TargetDesc.h X86.h Message-ID: <20110706220153.744542A6C12C@llvm.org> Author: evancheng Date: Wed Jul 6 17:01:53 2011 New Revision: 134546 URL: http://llvm.org/viewvc/llvm-project?rev=134546&view=rev Log: Rename files for consistency. Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp - copied, changed from r134542, llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h - copied, changed from r134542, llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Removed: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/X86/X86.h Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134546&r1=134545&r2=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Wed Jul 6 17:01:53 2011 @@ -15,7 +15,7 @@ #define DEBUG_TYPE "asm-printer" #include "X86ATTInstPrinter.h" #include "X86InstComments.h" -#include "MCTargetDesc/X86TargetDesc.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=134546&r1=134545&r2=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Wed Jul 6 17:01:53 2011 @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "X86InstComments.h" -#include "MCTargetDesc/X86TargetDesc.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" #include "../Utils/X86ShuffleDecode.h" Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=134546&r1=134545&r2=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Wed Jul 6 17:01:53 2011 @@ -15,7 +15,7 @@ #define DEBUG_TYPE "asm-printer" #include "X86IntelInstPrinter.h" #include "X86InstComments.h" -#include "MCTargetDesc/X86TargetDesc.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=134546&r1=134545&r2=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Wed Jul 6 17:01:53 2011 @@ -1,2 +1,2 @@ -add_llvm_library(LLVMX86Desc X86TargetDesc.cpp) +add_llvm_library(LLVMX86Desc X86MCTargetDesc.cpp) Copied: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (from r134542, llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?p2=llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp&p1=llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp&r1=134542&r2=134546&rev=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Wed Jul 6 17:01:53 2011 @@ -1,4 +1,4 @@ -//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===// +//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "X86TargetDesc.h" +#include "X86MCTargetDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Copied: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (from r134542, llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?p2=llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h&p1=llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h&r1=134542&r2=134546&rev=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Wed Jul 6 17:01:53 2011 @@ -1,4 +1,4 @@ -//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===// +//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef X86TARGETDESC_H -#define X86TARGETDESC_H +#ifndef X86MCTARGETDESC_H +#define X86MCTARGETDESC_H namespace llvm { class Target; Removed: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=134545&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (removed) @@ -1,74 +0,0 @@ -//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file provides X86 specific target descriptions. -// -//===----------------------------------------------------------------------===// - -#include "X86TargetDesc.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" - -#define GET_REGINFO_MC_DESC -#include "X86GenRegisterInfo.inc" - -#define GET_INSTRINFO_MC_DESC -#include "X86GenInstrInfo.inc" - -#define GET_SUBTARGETINFO_MC_DESC -#include "X86GenSubtargetInfo.inc" - -using namespace llvm; - -MCInstrInfo *createX86MCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitX86MCInstrInfo(X); - return X; -} - -MCRegisterInfo *createX86MCRegisterInfo() { - MCRegisterInfo *X = new MCRegisterInfo(); - InitX86MCRegisterInfo(X); - return X; -} - -MCSubtargetInfo *createX86MCSubtargetInfo() { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X); - return X; -} - -// Force static initialization. -extern "C" void LLVMInitializeX86MCInstrInfo() { - RegisterMCInstrInfo X(TheX86_32Target); - RegisterMCInstrInfo Y(TheX86_64Target); - - TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); -} - -extern "C" void LLVMInitializeX86MCRegInfo() { - RegisterMCRegInfo X(TheX86_32Target); - RegisterMCRegInfo Y(TheX86_64Target); - - TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); -} - -extern "C" void LLVMInitializeX86MCSubtargetInfo() { - RegisterMCSubtargetInfo X(TheX86_32Target); - RegisterMCSubtargetInfo Y(TheX86_64Target); - - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, - createX86MCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, - createX86MCSubtargetInfo); -} Removed: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=134545&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (removed) @@ -1,34 +0,0 @@ -//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file provides X86 specific target descriptions. -// -//===----------------------------------------------------------------------===// - -#ifndef X86TARGETDESC_H -#define X86TARGETDESC_H - -namespace llvm { -class Target; - -extern Target TheX86_32Target, TheX86_64Target; -} // End llvm namespace - -// Defines symbolic names for X86 registers. This defines a mapping from -// register name to register number. -// -#define GET_REGINFO_ENUM -#include "X86GenRegisterInfo.inc" - -// Defines symbolic names for the X86 instructions. -// -#define GET_INSTRINFO_ENUM -#include "X86GenInstrInfo.inc" - -#endif Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=134546&r1=134545&r2=134546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Wed Jul 6 17:01:53 2011 @@ -15,7 +15,7 @@ #ifndef TARGET_X86_H #define TARGET_X86_H -#include "MCTargetDesc/X86TargetDesc.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/Support/DataTypes.h" #include "llvm/Target/TargetMachine.h" From evan.cheng at apple.com Wed Jul 6 17:02:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 22:02:34 -0000 Subject: [llvm-commits] [llvm] r134547 - in /llvm/trunk/lib/Target/ARM: ARMBaseInfo.h CMakeLists.txt MCTargetDesc/ MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h MCTargetDesc/CMakeLists.txt MCTargetDesc/Makefile Makefile Message-ID: <20110706220234.EAF152A6C12C@llvm.org> Author: evancheng Date: Wed Jul 6 17:02:34 2011 New Revision: 134547 URL: http://llvm.org/viewvc/llvm-project?rev=134547&view=rev Log: Add ARM MC registry routines. Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/Makefile Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=134547&r1=134546&r2=134547&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Jul 6 17:02:34 2011 @@ -17,22 +17,12 @@ #ifndef ARMBASEINFO_H #define ARMBASEINFO_H +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" // Note that the following auto-generated files only defined enum types, and // so are safe to include here. -// Defines symbolic names for ARM registers. This defines a mapping from -// register name to register number. -// -#define GET_REGINFO_ENUM -#include "ARMGenRegisterInfo.inc" - -// Defines symbolic names for the ARM instructions. -// -#define GET_INSTRINFO_ENUM -#include "ARMGenInstrInfo.inc" - namespace llvm { // Enums corresponding to ARM condition codes Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134547&r1=134546&r2=134547&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jul 6 17:02:34 2011 @@ -65,3 +65,4 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) add_subdirectory(InstPrinter) +add_subdirectory(MCTargetDesc) Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134547&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (added) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 6 17:02:34 2011 @@ -0,0 +1,74 @@ +//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides ARM specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "ARMMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_REGINFO_MC_DESC +#include "ARMGenRegisterInfo.inc" + +#define GET_INSTRINFO_MC_DESC +#include "ARMGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "ARMGenSubtargetInfo.inc" + +using namespace llvm; + +MCInstrInfo *createARMMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitARMMCInstrInfo(X); + return X; +} + +MCRegisterInfo *createARMMCRegisterInfo() { + MCRegisterInfo *X = new MCRegisterInfo(); + InitARMMCRegisterInfo(X); + return X; +} + +MCSubtargetInfo *createARMMCSubtargetInfo() { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitARMMCSubtargetInfo(X); + return X; +} + +// Force static initialization. +extern "C" void LLVMInitializeARMMCInstrInfo() { + RegisterMCInstrInfo X(TheARMTarget); + RegisterMCInstrInfo Y(TheThumbTarget); + + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); +} + +extern "C" void LLVMInitializeARMMCRegInfo() { + RegisterMCRegInfo X(TheARMTarget); + RegisterMCRegInfo Y(TheThumbTarget); + + TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); +} + +extern "C" void LLVMInitializeARMMCSubtargetInfo() { + RegisterMCSubtargetInfo X(TheARMTarget); + RegisterMCSubtargetInfo Y(TheThumbTarget); + + TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, + createARMMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, + createARMMCSubtargetInfo); +} Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134547&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (added) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jul 6 17:02:34 2011 @@ -0,0 +1,34 @@ +//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides ARM specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef ARMMCTARGETDESC_H +#define ARMMCTARGETDESC_H + +namespace llvm { +class Target; + +extern Target TheARMTarget, TheThumbTarget; +} // End llvm namespace + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" + +// Defines symbolic names for the ARM instructions. +// +#define GET_INSTRINFO_ENUM +#include "ARMGenInstrInfo.inc" + +#endif Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=134547&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Wed Jul 6 17:02:34 2011 @@ -0,0 +1,2 @@ +add_llvm_library(LLVMARMDesc ARMMCTargetDesc.cpp) + Added: llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile?rev=134547&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile (added) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile Wed Jul 6 17:02:34 2011 @@ -0,0 +1,16 @@ +##===- lib/Target/ARM/TargetDesc/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMARMDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common Modified: llvm/trunk/lib/Target/ARM/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=134547&r1=134546&r2=134547&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Makefile (original) +++ llvm/trunk/lib/Target/ARM/Makefile Wed Jul 6 17:02:34 2011 @@ -19,6 +19,6 @@ ARMGenDecoderTables.inc ARMGenEDInfo.inc \ ARMGenFastISel.inc ARMGenMCCodeEmitter.inc -DIRS = InstPrinter AsmParser Disassembler TargetInfo +DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common From dpatel at apple.com Wed Jul 6 17:06:11 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 06 Jul 2011 22:06:11 -0000 Subject: [llvm-commits] [llvm] r134549 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110706220611.C402E2A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 17:06:11 2011 New Revision: 134549 URL: http://llvm.org/viewvc/llvm-project?rev=134549&view=rev Log: Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=134549&r1=134548&r2=134549&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jul 6 17:06:11 2011 @@ -30,6 +30,7 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/Pass.h" +#include "llvm/Analysis/DebugInfo.h" #include "llvm/Analysis/DIBuilder.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/Loads.h" @@ -1094,21 +1095,37 @@ namespace { class AllocaPromoter : public LoadAndStorePromoter { AllocaInst *AI; - DbgDeclareInst *DDI; DIBuilder *DIB; + SmallVector DDIs; + SmallVector DVIs; public: AllocaPromoter(const SmallVectorImpl &Insts, SSAUpdater &S, DIBuilder *DB) - : LoadAndStorePromoter(Insts, S), AI(0), DDI(0), DIB(DB) {} + : LoadAndStorePromoter(Insts, S), AI(0), DIB(DB) {} void run(AllocaInst *AI, const SmallVectorImpl &Insts) { // Remember which alloca we're promoting (for isInstInList). this->AI = AI; - DDI = FindAllocaDbgDeclare(AI); + if (MDNode *DebugNode = MDNode::getIfExists(AI->getContext(), AI)) + for (Value::use_iterator UI = DebugNode->use_begin(), + E = DebugNode->use_end(); UI != E; ++UI) + if (DbgDeclareInst *DDI = dyn_cast(*UI)) + DDIs.push_back(DDI); + else if (DbgValueInst *DVI = dyn_cast(*UI)) + DVIs.push_back(DVI); + LoadAndStorePromoter::run(Insts); AI->eraseFromParent(); - if (DDI) + for (SmallVector::iterator I = DDIs.begin(), + E = DDIs.end(); I != E; ++I) { + DbgDeclareInst *DDI = *I; DDI->eraseFromParent(); + } + for (SmallVector::iterator I = DVIs.begin(), + E = DVIs.end(); I != E; ++I) { + DbgValueInst *DVI = *I; + DVI->eraseFromParent(); + } } virtual bool isInstInList(Instruction *I, @@ -1118,13 +1135,43 @@ return cast(I)->getPointerOperand() == AI; } - virtual void updateDebugInfo(Instruction *I) const { - if (!DDI) - return; - if (StoreInst *SI = dyn_cast(I)) - ConvertDebugDeclareToDebugValue(DDI, SI, *DIB); - else if (LoadInst *LI = dyn_cast(I)) - ConvertDebugDeclareToDebugValue(DDI, LI, *DIB); + virtual void updateDebugInfo(Instruction *Inst) const { + for (SmallVector::const_iterator I = DDIs.begin(), + E = DDIs.end(); I != E; ++I) { + DbgDeclareInst *DDI = *I; + if (StoreInst *SI = dyn_cast(Inst)) + ConvertDebugDeclareToDebugValue(DDI, SI, *DIB); + else if (LoadInst *LI = dyn_cast(Inst)) + ConvertDebugDeclareToDebugValue(DDI, LI, *DIB); + } + for (SmallVector::const_iterator I = DVIs.begin(), + E = DVIs.end(); I != E; ++I) { + DbgValueInst *DVI = *I; + if (StoreInst *SI = dyn_cast(Inst)) { + Instruction *DbgVal = NULL; + // If an argument is zero extended then use argument directly. The ZExt + // may be zapped by an optimization pass in future. + Argument *ExtendedArg = NULL; + if (ZExtInst *ZExt = dyn_cast(SI->getOperand(0))) + ExtendedArg = dyn_cast(ZExt->getOperand(0)); + if (SExtInst *SExt = dyn_cast(SI->getOperand(0))) + ExtendedArg = dyn_cast(SExt->getOperand(0)); + if (ExtendedArg) + DbgVal = DIB->insertDbgValueIntrinsic(ExtendedArg, 0, + DIVariable(DVI->getVariable()), + SI); + else + DbgVal = DIB->insertDbgValueIntrinsic(SI->getOperand(0), 0, + DIVariable(DVI->getVariable()), + SI); + DbgVal->setDebugLoc(SI->getDebugLoc()); + } else if (LoadInst *LI = dyn_cast(Inst)) { + Instruction *DbgVal = + DIB->insertDbgValueIntrinsic(LI->getOperand(0), 0, + DIVariable(DVI->getVariable()), LI); + DbgVal->setDebugLoc(LI->getDebugLoc()); + } + } } }; } // end anon namespace From resistor at mac.com Wed Jul 6 17:37:00 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 06 Jul 2011 22:37:00 -0000 Subject: [llvm-commits] [llvm] r134554 - in /llvm/trunk: include/llvm/ADT/SmallVector.h unittests/ADT/SmallVectorTest.cpp Message-ID: <20110706223700.2364F2A6C12C@llvm.org> Author: resistor Date: Wed Jul 6 17:36:59 2011 New Revision: 134554 URL: http://llvm.org/viewvc/llvm-project?rev=134554&view=rev Log: Fix a subtle issue in SmallVector. The following code did not work as expected: vec.insert(vec.begin(), vec[3]); The issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space. The method needs to specifically detect and handle this case to correctly match std::vector's semantics. Thanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem. Modified: llvm/trunk/include/llvm/ADT/SmallVector.h llvm/trunk/unittests/ADT/SmallVectorTest.cpp Modified: llvm/trunk/include/llvm/ADT/SmallVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=134554&r1=134553&r2=134554&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallVector.h (original) +++ llvm/trunk/include/llvm/ADT/SmallVector.h Wed Jul 6 17:36:59 2011 @@ -410,7 +410,14 @@ this->setEnd(this->end()+1); // Push everything else over. std::copy_backward(I, this->end()-1, this->end()); - *I = Elt; + + // If we just moved the element we're inserting, be sure to update + // the reference. + const T *EltPtr = &Elt; + if (I <= EltPtr && EltPtr < this->EndX) + ++EltPtr; + + *I = *EltPtr; return I; } size_t EltNo = I-this->begin(); Modified: llvm/trunk/unittests/ADT/SmallVectorTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/SmallVectorTest.cpp?rev=134554&r1=134553&r2=134554&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/SmallVectorTest.cpp (original) +++ llvm/trunk/unittests/ADT/SmallVectorTest.cpp Wed Jul 6 17:36:59 2011 @@ -35,26 +35,26 @@ Constructable() : value(0) { ++numConstructorCalls; } - + Constructable(int val) : value(val) { ++numConstructorCalls; } - + Constructable(const Constructable & src) { value = src.value; ++numConstructorCalls; } - + ~Constructable() { ++numDestructorCalls; } - + Constructable & operator=(const Constructable & src) { value = src.value; ++numAssignmentCalls; return *this; } - + int getValue() const { return abs(value); } @@ -64,7 +64,7 @@ numDestructorCalls = 0; numAssignmentCalls = 0; } - + static int getNumConstructorCalls() { return numConstructorCalls; } @@ -91,10 +91,10 @@ class SmallVectorTest : public testing::Test { protected: typedef SmallVector VectorType; - + VectorType theVector; VectorType otherVector; - + void SetUp() { Constructable::reset(); } @@ -111,7 +111,7 @@ // Assert that theVector contains the specified values, in order. void assertValuesInOrder(VectorType & v, size_t size, ...) { EXPECT_EQ(size, v.size()); - + va_list ap; va_start(ap, size); for (size_t i = 0; i < size; ++i) { @@ -121,7 +121,7 @@ va_end(ap); } - + // Generate a sequence of values to initialize the vector. void makeSequence(VectorType & v, int start, int end) { for (int i = start; i <= end; ++i) { @@ -155,18 +155,24 @@ theVector.push_back(Constructable(2)); assertValuesInOrder(theVector, 2u, 1, 2); + // Insert at beginning + theVector.insert(theVector.begin(), theVector[1]); + assertValuesInOrder(theVector, 3u, 2, 1, 2); + // Pop one element theVector.pop_back(); - assertValuesInOrder(theVector, 1u, 1); + assertValuesInOrder(theVector, 2u, 2, 1); - // Pop another element + // Pop remaining elements + theVector.pop_back(); theVector.pop_back(); assertEmpty(theVector); - + // Check number of constructor calls. Should be 2 for each list element, - // one for the argument to push_back, and one for the list element itself. - EXPECT_EQ(4, Constructable::getNumConstructorCalls()); - EXPECT_EQ(4, Constructable::getNumDestructorCalls()); + // one for the argument to push_back, one for the argument to insert, + // and one for the list element itself. + EXPECT_EQ(5, Constructable::getNumConstructorCalls()); + EXPECT_EQ(5, Constructable::getNumDestructorCalls()); } // Clear test. @@ -198,7 +204,7 @@ SCOPED_TRACE("ResizeGrowTest"); theVector.resize(2); - + // The extra constructor/destructor calls come from the temporary object used // to initialize the contents of the resized array (via copy construction). EXPECT_EQ(3, Constructable::getNumConstructorCalls()); @@ -226,10 +232,10 @@ for (int i = 0; i < 10; ++i) { EXPECT_EQ(i+1, theVector[i].getValue()); } - + // Now resize back to fixed size. theVector.resize(1); - + assertValuesInOrder(theVector, 1u, 1); } @@ -364,13 +370,13 @@ makeSequence(theVector, 1, 3); makeSequence(otherVector, 1, 3); - + EXPECT_TRUE(theVector == otherVector); EXPECT_FALSE(theVector != otherVector); otherVector.clear(); makeSequence(otherVector, 2, 4); - + EXPECT_FALSE(theVector == otherVector); EXPECT_TRUE(theVector != otherVector); } From echristo at apple.com Wed Jul 6 17:41:18 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 06 Jul 2011 22:41:18 -0000 Subject: [llvm-commits] [llvm] r134555 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20110706224119.104462A6C12C@llvm.org> Author: echristo Date: Wed Jul 6 17:41:18 2011 New Revision: 134555 URL: http://llvm.org/viewvc/llvm-project?rev=134555&view=rev Log: Grammar and 80-col. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=134555&r1=134554&r2=134555&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul 6 17:41:18 2011 @@ -3326,13 +3326,13 @@ const TargetLowering &TLI) { assert((SrcAlign == 0 || SrcAlign >= DstAlign) && "Expecting memcpy / memset source to meet alignment requirement!"); - // If 'SrcAlign' is zero, that means the memory operation does not need load - // the value, i.e. memset or memcpy from constant string. Otherwise, it's - // the inferred alignment of the source. 'DstAlign', on the other hand, is the - // specified alignment of the memory operation. If it is zero, that means - // it's possible to change the alignment of the destination. 'MemcpyStrSrc' - // indicates whether the memcpy source is constant so it does not need to be - // loaded. + // If 'SrcAlign' is zero, that means the memory operation does not need to + // load the value, i.e. memset or memcpy from constant string. Otherwise, + // it's the inferred alignment of the source. 'DstAlign', on the other hand, + // is the specified alignment of the memory operation. If it is zero, that + // means it's possible to change the alignment of the destination. + // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does + // not need to be loaded. EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign, NonScalarIntSafe, MemcpyStrSrc, DAG.getMachineFunction()); From isanbard at gmail.com Wed Jul 6 17:52:32 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Jul 2011 22:52:32 -0000 Subject: [llvm-commits] [llvm] r134557 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20110706225232.4A8532A6C12C@llvm.org> Author: void Date: Wed Jul 6 17:52:32 2011 New Revision: 134557 URL: http://llvm.org/viewvc/llvm-project?rev=134557&view=rev Log: Clean up the #includes. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134557&r1=134556&r2=134557&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jul 6 17:52:32 2011 @@ -7,22 +7,21 @@ // //===----------------------------------------------------------------------===// -#include "llvm/ADT/FoldingSet.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCDwarf.h" -#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCObjectWriter.h" -#include "llvm/ADT/SmallString.h" -#include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetAsmBackend.h" #include "llvm/Target/TargetAsmInfo.h" +#include "llvm/ADT/FoldingSet.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Twine.h" using namespace llvm; // Given a special op, return the address skip amount (in units of From dpatel at apple.com Wed Jul 6 18:09:51 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 06 Jul 2011 23:09:51 -0000 Subject: [llvm-commits] [llvm] r134559 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110706230951.4359D2A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 18:09:51 2011 New Revision: 134559 URL: http://llvm.org/viewvc/llvm-project?rev=134559&view=rev Log: Typo. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=134559&r1=134558&r2=134559&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Jul 6 18:09:51 2011 @@ -123,7 +123,7 @@ /// getNext - Return the next UserValue in the equivalence class. UserValue *getNext() const { return next; } - /// match - Does this UserValue match the aprameters? + /// match - Does this UserValue match the parameters? bool match(const MDNode *Var, unsigned Offset) const { return Var == variable && Offset == offset; } From dpatel at apple.com Wed Jul 6 18:26:18 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 06 Jul 2011 23:26:18 -0000 Subject: [llvm-commits] [llvm] r134561 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110706232618.80FD72A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 18:26:18 2011 New Revision: 134561 URL: http://llvm.org/viewvc/llvm-project?rev=134561&view=rev Log: Remove dead code. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134561&r1=134560&r2=134561&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jul 6 18:26:18 2011 @@ -1846,8 +1846,6 @@ assert(UserVariables.empty() && DbgValues.empty() && "Maps weren't cleaned"); - /// ProcessedArgs - Collection of arguments already processed. - SmallPtrSet ProcessedArgs; const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); /// LiveUserVar - Map physreg numbers to the MDNode they contain. std::vector LiveUserVar(TRI->getNumRegs()); From grosbach at apple.com Wed Jul 6 18:38:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 06 Jul 2011 23:38:13 -0000 Subject: [llvm-commits] [llvm] r134563 - /llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Message-ID: <20110706233813.941CE2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 6 18:38:13 2011 New Revision: 134563 URL: http://llvm.org/viewvc/llvm-project?rev=134563&view=rev Log: Typo. Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=134563&r1=134562&r2=134563&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Jul 6 18:38:13 2011 @@ -1744,7 +1744,7 @@ Record *R = DI->getDef(); // Direct reference to a leaf DagNode or PatFrag? Turn it into a - // TreePatternNode if its own. For example: + // TreePatternNode of its own. For example: /// (foo GPR, imm) -> (foo GPR, (imm)) if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) return ParseTreePattern(new DagInit(DI, "", From dpatel at apple.com Wed Jul 6 18:39:26 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 06 Jul 2011 23:39:26 -0000 Subject: [llvm-commits] [test-suite] r134564 - /test-suite/trunk/CollectDebugInfoUsingLLDB.py Message-ID: <20110706233926.8632B2A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 18:39:26 2011 New Revision: 134564 URL: http://llvm.org/viewvc/llvm-project?rev=134564&view=rev Log: Simplify. Modified: test-suite/trunk/CollectDebugInfoUsingLLDB.py Modified: test-suite/trunk/CollectDebugInfoUsingLLDB.py URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/CollectDebugInfoUsingLLDB.py?rev=134564&r1=134563&r2=134564&view=diff ============================================================================== --- test-suite/trunk/CollectDebugInfoUsingLLDB.py (original) +++ test-suite/trunk/CollectDebugInfoUsingLLDB.py Wed Jul 6 18:39:26 2011 @@ -202,7 +202,7 @@ # Launch the process. Since we specified synchronous mode, we won't return # from this function until we hit the breakpoint at main sberror = lldb.SBError() - process = target.Launch (None, None, os.ctermid(), os.ctermid(), os.ctermid(), None, 0, False, sberror) + process = target.LaunchSimple(None, None, None) # Make sure the launch went ok while stopped_at_breakpoint(process): # print "stopped at a bp" From eli.friedman at gmail.com Wed Jul 6 18:41:49 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 06 Jul 2011 23:41:49 -0000 Subject: [llvm-commits] [llvm] r134565 - in /llvm/trunk/lib/CodeGen: BranchFolding.cpp BranchFolding.h Message-ID: <20110706234149.2398D2A6C12C@llvm.org> Author: efriedma Date: Wed Jul 6 18:41:48 2011 New Revision: 134565 URL: http://llvm.org/viewvc/llvm-project?rev=134565&view=rev Log: When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/BranchFolding.h Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=134565&r1=134564&r2=134565&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Jul 6 18:41:48 2011 @@ -366,11 +366,31 @@ return TailLen; } +void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB, + MachineBasicBlock *NewMBB) { + if (RS) { + RS->enterBasicBlock(CurMBB); + if (!CurMBB->empty()) + RS->forward(prior(CurMBB->end())); + BitVector RegsLiveAtExit(TRI->getNumRegs()); + RS->getRegsUsed(RegsLiveAtExit, false); + for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++) + if (RegsLiveAtExit[i]) + NewMBB->addLiveIn(i); + } +} + /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything /// after it, replacing it with an unconditional branch to NewDest. void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, MachineBasicBlock *NewDest) { + MachineBasicBlock *CurMBB = OldInst->getParent(); + TII->ReplaceTailWithBranchTo(OldInst, NewDest); + + // For targets that use the register scavenger, we must maintain LiveIns. + MaintainLiveIns(CurMBB, NewDest); + ++NumTailMerge; } @@ -399,16 +419,7 @@ NewMBB->splice(NewMBB->end(), &CurMBB, BBI1, CurMBB.end()); // For targets that use the register scavenger, we must maintain LiveIns. - if (RS) { - RS->enterBasicBlock(&CurMBB); - if (!CurMBB.empty()) - RS->forward(prior(CurMBB.end())); - BitVector RegsLiveAtExit(TRI->getNumRegs()); - RS->getRegsUsed(RegsLiveAtExit, false); - for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++) - if (RegsLiveAtExit[i]) - NewMBB->addLiveIn(i); - } + MaintainLiveIns(&CurMBB, NewMBB); return NewMBB; } Modified: llvm/trunk/lib/CodeGen/BranchFolding.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.h?rev=134565&r1=134564&r2=134565&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.h (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.h Wed Jul 6 18:41:48 2011 @@ -95,6 +95,8 @@ bool TailMergeBlocks(MachineFunction &MF); bool TryTailMergeBlocks(MachineBasicBlock* SuccBB, MachineBasicBlock* PredBB); + void MaintainLiveIns(MachineBasicBlock *CurMBB, + MachineBasicBlock *NewMBB); void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, MachineBasicBlock *NewDest); MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB, From jstaszak at apple.com Wed Jul 6 18:50:16 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 23:50:16 -0000 Subject: [llvm-commits] [llvm] r134566 - /llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Message-ID: <20110706235016.E57152A6C12C@llvm.org> Author: kuba Date: Wed Jul 6 18:50:16 2011 New Revision: 134566 URL: http://llvm.org/viewvc/llvm-project?rev=134566&view=rev Log: Fix a bug in the "expect" intrinsic lowering. Modified: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Modified: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=134566&r1=134565&r2=134566&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Wed Jul 6 18:50:16 2011 @@ -145,8 +145,11 @@ continue; Function *Fn = CI->getCalledFunction(); - if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) + if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) { + Value *Exp = CI->getArgOperand(0); + CI->replaceAllUsesWith(Exp); CI->eraseFromParent(); + } } } From dpatel at apple.com Wed Jul 6 19:05:58 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Jul 2011 00:05:58 -0000 Subject: [llvm-commits] [llvm] r134568 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110707000558.EE5DE2A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 19:05:58 2011 New Revision: 134568 URL: http://llvm.org/viewvc/llvm-project?rev=134568&view=rev Log: Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=134568&r1=134567&r2=134568&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jul 6 19:05:58 2011 @@ -1164,12 +1164,12 @@ DbgVal = DIB->insertDbgValueIntrinsic(SI->getOperand(0), 0, DIVariable(DVI->getVariable()), SI); - DbgVal->setDebugLoc(SI->getDebugLoc()); + DbgVal->setDebugLoc(DVI->getDebugLoc()); } else if (LoadInst *LI = dyn_cast(Inst)) { Instruction *DbgVal = DIB->insertDbgValueIntrinsic(LI->getOperand(0), 0, DIVariable(DVI->getVariable()), LI); - DbgVal->setDebugLoc(LI->getDebugLoc()); + DbgVal->setDebugLoc(DVI->getDebugLoc()); } } } From evan.cheng at apple.com Wed Jul 6 19:08:19 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 00:08:19 -0000 Subject: [llvm-commits] [llvm] r134569 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h Message-ID: <20110707000819.518322A6C12C@llvm.org> Author: evancheng Date: Wed Jul 6 19:08:19 2011 New Revision: 134569 URL: http://llvm.org/viewvc/llvm-project?rev=134569&view=rev Log: Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Jul 6 19:08:19 2011 @@ -27,7 +27,7 @@ "Enable VFP3 instructions">; def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", "Enable NEON instructions">; -def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", +def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", "Does not support ARM mode execution">; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jul 6 19:08:19 2011 @@ -37,7 +37,7 @@ cl::desc("Disallow all unaligned memory accesses")); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool isT) + const std::string &FS) : ARMGenSubtargetInfo() , ARMArchVersion(V4) , ARMProcFamily(Others) @@ -46,8 +46,8 @@ , SlowFPVMLx(false) , HasVMLxForwarding(false) , SlowFPBrcc(false) - , IsThumb(isT) - , ThumbMode(Thumb1) + , IsThumb(false) + , HasThumb2(false) , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) @@ -68,65 +68,8 @@ , TargetTriple(TT) , TargetABI(ARM_ABI_APCS) { // Determine default and user specified characteristics - - // When no arch is specified either by CPU or by attributes, make the default - // ARMv4T. - const char *ARMArchFeature = ""; if (CPUString.empty()) CPUString = "generic"; - if (CPUString == "generic" && (FS.empty() || FS == "generic")) { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } - - // Set the boolean corresponding to the current target triple, or the default - // if one cannot be determined, to true. - unsigned Len = TT.length(); - unsigned Idx = 0; - - if (Len >= 5 && TT.substr(0, 4) == "armv") - Idx = 4; - else if (Len >= 6 && TT.substr(0, 5) == "thumb") { - IsThumb = true; - if (Len >= 7 && TT[5] == 'v') - Idx = 6; - } - if (Idx) { - unsigned SubVer = TT[Idx]; - if (SubVer >= '7' && SubVer <= '9') { - ARMArchVersion = V7A; - ARMArchFeature = "+v7a"; - if (Len >= Idx+2 && TT[Idx+1] == 'm') { - ARMArchVersion = V7M; - ARMArchFeature = "+v7m"; - } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { - ARMArchVersion = V7EM; - ARMArchFeature = "+v7em"; - } - } else if (SubVer == '6') { - ARMArchVersion = V6; - ARMArchFeature = "+v6"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { - ARMArchVersion = V6T2; - ARMArchFeature = "+v6t2"; - } - } else if (SubVer == '5') { - ARMArchVersion = V5T; - ARMArchFeature = "+v5t"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { - ARMArchVersion = V5TE; - ARMArchFeature = "+v5te"; - } - } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } else { - ARMArchVersion = V4; - ARMArchFeature = ""; - } - } - } if (TT.find("eabi") != std::string::npos) TargetABI = ARM_ABI_AAPCS; @@ -134,12 +77,20 @@ // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string FSWithArch = std::string(ARMArchFeature); - if (FSWithArch.empty()) - FSWithArch = FS; - else if (!FS.empty()) - FSWithArch = FSWithArch + "," + FS; - ParseSubtargetFeatures(FSWithArch, CPUString); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS; + else + ArchFS = FS; + } + + ParseSubtargetFeatures(ArchFS, CPUString); + + // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a + // ARM version or CPU and then remove this. + if (ARMArchVersion < V6T2 && hasThumb2()) + ARMArchVersion = V6T2; // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); @@ -147,12 +98,6 @@ // After parsing Itineraries, set ItinData.IssueWidth. computeIssueWidth(); - // Thumb2 implies at least V6T2. - if (ARMArchVersion >= V6T2) - ThumbMode = Thumb2; - else if (ThumbMode >= Thumb2) - ARMArchVersion = V6T2; - if (isAAPCS_ABI()) stackAlignment = 8; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jul 6 19:08:19 2011 @@ -14,6 +14,7 @@ #ifndef ARMSUBTARGET_H #define ARMSUBTARGET_H +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/ADT/Triple.h" @@ -39,11 +40,6 @@ None, VFPv2, VFPv3, NEON }; - enum ThumbTypeEnum { - Thumb1, - Thumb2 - }; - /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, /// V6, V6T2, V7A, V7M, V7EM. ARMArchEnum ARMArchVersion; @@ -73,8 +69,8 @@ /// IsThumb - True if we are in thumb mode, false if in ARM mode. bool IsThumb; - /// ThumbMode - Indicates supported Thumb version. - ThumbTypeEnum ThumbMode; + /// HasThumb2 - True if Thumb2 instructions are supported. + bool HasThumb2; /// NoARM - True if subtarget does not support ARM mode execution. bool NoARM; @@ -161,7 +157,7 @@ /// of the specified triple. /// ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool isThumb); + const std::string &FS); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. @@ -217,9 +213,9 @@ bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } bool isThumb() const { return IsThumb; } - bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } - bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } - bool hasThumb2() const { return ThumbMode >= Thumb2; } + bool isThumb1Only() const { return IsThumb && !HasThumb2; } + bool isThumb2() const { return IsThumb && HasThumb2; } + bool hasThumb2() const { return HasThumb2; } bool isR9Reserved() const { return IsR9Reserved; } Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jul 6 19:08:19 2011 @@ -79,10 +79,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, - const std::string &FS, - bool isThumb) + const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, CPU, FS, isThumb), + Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { DefRelocModel = getRelocationModel(); @@ -95,7 +94,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget), + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -113,7 +112,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS, true), + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jul 6 19:08:19 2011 @@ -41,8 +41,7 @@ public: ARMBaseTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool isThumb); + const std::string &CPU, const std::string &FS); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 6 19:08:19 2011 @@ -72,3 +72,49 @@ TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, createARMMCSubtargetInfo); } + +std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { + // Set the boolean corresponding to the current target triple, or the default + // if one cannot be determined, to true. + unsigned Len = TT.size(); + unsigned Idx = 0; + + if (Len >= 5 && TT.substr(0, 4) == "armv") + Idx = 4; + else if (Len >= 6 && TT.substr(0, 5) == "thumb") { + IsThumb = true; + if (Len >= 7 && TT[5] == 'v') + Idx = 6; + } + + std::string ARMArchFeature; + if (Idx) { + unsigned SubVer = TT[Idx]; + if (SubVer >= '7' && SubVer <= '9') { + ARMArchFeature = "+v7a"; + if (Len >= Idx+2 && TT[Idx+1] == 'm') { + ARMArchFeature = "+v7m"; + } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { + ARMArchFeature = "+v7em"; + } + } else if (SubVer == '6') { + ARMArchFeature = "+v6"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { + ARMArchFeature = "+v6t2"; + } + } else if (SubVer == '5') { + ARMArchFeature = "+v5t"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { + ARMArchFeature = "+v5te"; + } + } else if (SubVer == '4') { + if (Len >= Idx+2 && TT[Idx+1] == 't') { + ARMArchFeature = "+v4t"; + } else { + ARMArchFeature = ""; + } + } + } + + return ARMArchFeature; +} Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134569&r1=134568&r2=134569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jul 6 19:08:19 2011 @@ -14,10 +14,18 @@ #ifndef ARMMCTARGETDESC_H #define ARMMCTARGETDESC_H +#include + namespace llvm { class Target; +class StringRef; extern Target TheARMTarget, TheThumbTarget; + +namespace ARM_MC { + std::string ParseARMTriple(StringRef TT, bool &IsThumb); +} + } // End llvm namespace // Defines symbolic names for ARM registers. This defines a mapping from From dpatel at apple.com Wed Jul 6 19:14:27 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Jul 2011 00:14:27 -0000 Subject: [llvm-commits] [llvm] r134572 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110707001427.930762A6C12C@llvm.org> Author: dpatel Date: Wed Jul 6 19:14:27 2011 New Revision: 134572 URL: http://llvm.org/viewvc/llvm-project?rev=134572&view=rev Log: Add DEBUG messages. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134572&r1=134571&r2=134572&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jul 6 19:14:27 2011 @@ -1885,8 +1885,12 @@ if (Prev->isDebugValue()) { // Coalesce identical entries at the end of History. if (History.size() >= 2 && - Prev->isIdenticalTo(History[History.size() - 2])) + Prev->isIdenticalTo(History[History.size() - 2])) { + DEBUG(dbgs() << "Coalesce identical DBG_VALUE entries:\n" + << "\t" << *Prev + << "\t" << *History[History.size() - 2] << "\n"); History.pop_back(); + } // Terminate old register assignments that don't reach MI; MachineFunction::const_iterator PrevMBB = Prev->getParent(); @@ -1896,9 +1900,12 @@ // its basic block. MachineBasicBlock::const_iterator LastMI = PrevMBB->getLastNonDebugInstr(); - if (LastMI == PrevMBB->end()) + if (LastMI == PrevMBB->end()) { // Drop DBG_VALUE for empty range. + DEBUG(dbgs() << "Drop DBG_VALUE for empty range:\n" + << "\t" << *Prev << "\n"); History.pop_back(); + } else { // Terminate after LastMI. History.push_back(LastMI); From clattner at apple.com Wed Jul 6 19:31:50 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 06 Jul 2011 17:31:50 -0700 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/LowerExpectIntrinsic/ In-Reply-To: <20110706182243.7DE702A6C12C@llvm.org> References: <20110706182243.7DE702A6C12C@llvm.org> Message-ID: <2D61D6E4-1D32-49D8-A2A3-61714051E44A@apple.com> On Jul 6, 2011, at 11:22 AM, Jakub Staszak wrote: > Author: kuba > Date: Wed Jul 6 13:22:43 2011 > New Revision: 134516 > > URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev > Log: > Introduce "expect" intrinsic instructions. > Hi Kuba, Why is this introducing a new pass to do lowering? -Chris > > Added: > llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp > llvm/trunk/test/CodeGen/Generic/builtin-expect.ll > llvm/trunk/test/Transforms/LowerExpectIntrinsic/ > llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll > llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp > Modified: > llvm/trunk/include/llvm/InitializePasses.h > llvm/trunk/include/llvm/Intrinsics.td > llvm/trunk/include/llvm/LLVMContext.h > llvm/trunk/include/llvm/LinkAllPasses.h > llvm/trunk/include/llvm/Support/PassManagerBuilder.h > llvm/trunk/include/llvm/Transforms/Scalar.h > llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > llvm/trunk/lib/Transforms/Scalar/Scalar.cpp > llvm/trunk/lib/Transforms/Utils/CMakeLists.txt > llvm/trunk/lib/VMCore/LLVMContext.cpp > > Modified: llvm/trunk/include/llvm/InitializePasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/InitializePasses.h (original) > +++ llvm/trunk/include/llvm/InitializePasses.h Wed Jul 6 13:22:43 2011 > @@ -141,6 +141,7 @@ > void initializeLoopUnswitchPass(PassRegistry&); > void initializeLoopIdiomRecognizePass(PassRegistry&); > void initializeLowerAtomicPass(PassRegistry&); > +void initializeLowerExpectIntrinsicPass(PassRegistry&); > void initializeLowerIntrinsicsPass(PassRegistry&); > void initializeLowerInvokePass(PassRegistry&); > void initializeLowerSetJmpPass(PassRegistry&); > > Modified: llvm/trunk/include/llvm/Intrinsics.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Intrinsics.td (original) > +++ llvm/trunk/include/llvm/Intrinsics.td Wed Jul 6 13:22:43 2011 > @@ -266,6 +266,11 @@ > [IntrNoMem]>, > GCCBuiltin<"__builtin_object_size">; > > +//===------------------------- Expect Intrinsics --------------------------===// > +// > +def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, > + LLVMMatchType<0>], [IntrNoMem]>; > + > //===-------------------- Bit Manipulation Intrinsics ---------------------===// > // > > > Modified: llvm/trunk/include/llvm/LLVMContext.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/LLVMContext.h (original) > +++ llvm/trunk/include/llvm/LLVMContext.h Wed Jul 6 13:22:43 2011 > @@ -39,7 +39,8 @@ > // compile-time performance optimization, not a correctness optimization. > enum { > MD_dbg = 0, // "dbg" > - MD_tbaa = 1 // "tbaa" > + MD_tbaa = 1, // "tbaa" > + MD_prof = 2 // "prof" > }; > > /// getMDKindID - Return a unique non-zero ID for the specified metadata kind. > > Modified: llvm/trunk/include/llvm/LinkAllPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/LinkAllPasses.h (original) > +++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jul 6 13:22:43 2011 > @@ -92,6 +92,7 @@ > (void) llvm::createLoopUnswitchPass(); > (void) llvm::createLoopIdiomPass(); > (void) llvm::createLoopRotatePass(); > + (void) llvm::createLowerExpectIntrinsicPass(); > (void) llvm::createLowerInvokePass(); > (void) llvm::createLowerSetJmpPass(); > (void) llvm::createLowerSwitchPass(); > > Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) > +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Wed Jul 6 13:22:43 2011 > @@ -152,6 +152,7 @@ > FPM.add(createCFGSimplificationPass()); > FPM.add(createScalarReplAggregatesPass()); > FPM.add(createEarlyCSEPass()); > + FPM.add(createLowerExpectIntrinsicPass()); > } > > /// populateModulePassManager - This sets up the primary pass manager. > > Modified: llvm/trunk/include/llvm/Transforms/Scalar.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) > +++ llvm/trunk/include/llvm/Transforms/Scalar.h Wed Jul 6 13:22:43 2011 > @@ -361,6 +361,14 @@ > FunctionPass *createInstructionSimplifierPass(); > extern char &InstructionSimplifierID; > > + > +//===----------------------------------------------------------------------===// > +// > +// LowerExpectIntriniscs - Removes llvm.expect intrinsics and creates > +// "block_weights" metadata. > +FunctionPass *createLowerExpectIntrinsicPass(); > + > + > } // End llvm namespace > > #endif > > Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jul 6 13:22:43 2011 > @@ -353,6 +353,13 @@ > report_fatal_error("Code generator does not support intrinsic function '"+ > Callee->getName()+"'!"); > > + case Intrinsic::expect: { > + // Just replace __builtin_expect(exp, c) with EXP. > + Value *V = CI->getArgOperand(0); > + CI->replaceAllUsesWith(V); > + break; > + } > + > // The setjmp/longjmp intrinsics should only exist in the code if it was > // never optimized (ie, right out of the CFE), or if it has been hacked on > // by the lowerinvoke pass. In both cases, the right thing to do is to > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 6 13:22:43 2011 > @@ -4771,6 +4771,13 @@ > case Intrinsic::flt_rounds: > setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); > return 0; > + > + case Intrinsic::expect: { > + // Just replace __builtin_expect(exp, c) with EXP. > + setValue(&I, getValue(I.getArgOperand(0))); > + return 0; > + } > + > case Intrinsic::trap: { > StringRef TrapFuncName = getTrapFunctionName(); > if (TrapFuncName.empty()) { > > Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Wed Jul 6 13:22:43 2011 > @@ -48,6 +48,7 @@ > initializeLoopUnswitchPass(Registry); > initializeLoopIdiomRecognizePass(Registry); > initializeLowerAtomicPass(Registry); > + initializeLowerExpectIntrinsicPass(Registry); > initializeMemCpyOptPass(Registry); > initializeObjCARCAliasAnalysisPass(Registry); > initializeObjCARCExpandPass(Registry); > > Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) > +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Wed Jul 6 13:22:43 2011 > @@ -14,6 +14,7 @@ > Local.cpp > LoopSimplify.cpp > LoopUnroll.cpp > + LowerExpectIntrinsic.cpp > LowerInvoke.cpp > LowerSwitch.cpp > Mem2Reg.cpp > > Added: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=134516&view=auto > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (added) > +++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Wed Jul 6 13:22:43 2011 > @@ -0,0 +1,163 @@ > +#define DEBUG_TYPE "lower-expect-intrinsic" > +#include "llvm/Constants.h" > +#include "llvm/Function.h" > +#include "llvm/BasicBlock.h" > +#include "llvm/LLVMContext.h" > +#include "llvm/Instructions.h" > +#include "llvm/Intrinsics.h" > +#include "llvm/Metadata.h" > +#include "llvm/Pass.h" > +#include "llvm/Transforms/Scalar.h" > +#include "llvm/Support/CommandLine.h" > +#include "llvm/Support/Debug.h" > +#include "llvm/ADT/Statistic.h" > +#include > + > +using namespace llvm; > + > +STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled"); > + > +static cl::opt > +LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64), > + cl::desc("Weight of the branch likely to be taken (default = 64)")); > +static cl::opt > +UnlikelyBranchWeight("unlikely-branch-weight", cl::Hidden, cl::init(4), > + cl::desc("Weight of the branch unlikely to be taken (default = 4)")); > + > +namespace { > + > + class LowerExpectIntrinsic : public FunctionPass { > + > + bool HandleSwitchExpect(SwitchInst *SI); > + > + bool HandleIfExpect(BranchInst *BI); > + > + public: > + static char ID; > + LowerExpectIntrinsic() : FunctionPass(ID) { > + initializeLowerExpectIntrinsicPass(*PassRegistry::getPassRegistry()); > + } > + > + bool runOnFunction(Function &F); > + }; > +} > + > + > +bool LowerExpectIntrinsic::HandleSwitchExpect(SwitchInst *SI) { > + CallInst *CI = dyn_cast(SI->getCondition()); > + if (!CI) > + return false; > + > + Function *Fn = CI->getCalledFunction(); > + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) > + return false; > + > + Value *ArgValue = CI->getArgOperand(0); > + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); > + if (!ExpectedValue) > + return false; > + > + LLVMContext &Context = CI->getContext(); > + const Type *Int32Ty = Type::getInt32Ty(Context); > + > + unsigned caseNo = SI->findCaseValue(ExpectedValue); > + std::vector Vec; > + unsigned n = SI->getNumCases(); > + Vec.resize(n + 1); // +1 for MDString > + > + Vec[0] = MDString::get(Context, "branch_weights"); > + for (unsigned i = 0; i < n; ++i) { > + Vec[i + 1] = ConstantInt::get(Int32Ty, i == caseNo ? LikelyBranchWeight : UnlikelyBranchWeight); > + } > + > + MDNode *WeightsNode = llvm::MDNode::get(Context, Vec); > + SI->setMetadata(LLVMContext::MD_prof, WeightsNode); > + > + SI->setCondition(ArgValue); > + return true; > +} > + > + > +bool LowerExpectIntrinsic::HandleIfExpect(BranchInst *BI) { > + if (BI->isUnconditional()) > + return false; > + > + // Handle non-optimized IR code like: > + // %expval = call i64 @llvm.expect.i64.i64(i64 %conv1, i64 1) > + // %tobool = icmp ne i64 %expval, 0 > + // br i1 %tobool, label %if.then, label %if.end > + > + ICmpInst *CmpI = dyn_cast(BI->getCondition()); > + if (!CmpI || CmpI->getPredicate() != CmpInst::ICMP_NE) > + return false; > + > + CallInst *CI = dyn_cast(CmpI->getOperand(0)); > + if (!CI) > + return false; > + > + Function *Fn = CI->getCalledFunction(); > + if (!Fn || Fn->getIntrinsicID() != Intrinsic::expect) > + return false; > + > + Value *ArgValue = CI->getArgOperand(0); > + ConstantInt *ExpectedValue = dyn_cast(CI->getArgOperand(1)); > + if (!ExpectedValue) > + return false; > + > + LLVMContext &Context = CI->getContext(); > + const Type *Int32Ty = Type::getInt32Ty(Context); > + bool Likely = ExpectedValue->isOne(); > + > + // If expect value is equal to 1 it means that we are more likely to take > + // branch 0, in other case more likely is branch 1. > + Value *Ops[] = { > + MDString::get(Context, "branch_weights"), > + ConstantInt::get(Int32Ty, Likely ? LikelyBranchWeight : UnlikelyBranchWeight), > + ConstantInt::get(Int32Ty, Likely ? UnlikelyBranchWeight : LikelyBranchWeight) > + }; > + > + MDNode *WeightsNode = MDNode::get(Context, ArrayRef(Ops, 3)); > + BI->setMetadata(LLVMContext::MD_prof, WeightsNode); > + > + CmpI->setOperand(0, ArgValue); > + return true; > +} > + > + > +bool LowerExpectIntrinsic::runOnFunction(Function &F) { > + for (Function::iterator I = F.begin(), E = F.end(); I != E;) { > + BasicBlock *BB = I++; > + > + // Create "block_weights" metadata. > + if (BranchInst *BI = dyn_cast(BB->getTerminator())) { > + if (HandleIfExpect(BI)) > + IfHandled++; > + } else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { > + if (HandleSwitchExpect(SI)) > + IfHandled++; > + } > + > + // remove llvm.expect intrinsics. > + for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); > + BI != BE; ) { > + CallInst *CI = dyn_cast(BI++); > + if (!CI) > + continue; > + > + Function *Fn = CI->getCalledFunction(); > + if (Fn && Fn->getIntrinsicID() == Intrinsic::expect) > + CI->eraseFromParent(); > + } > + } > + > + return false; > +} > + > + > +char LowerExpectIntrinsic::ID = 0; > +INITIALIZE_PASS(LowerExpectIntrinsic, "lower-expect", "Lower 'expect' " > + "Intrinsics", false, false) > + > +FunctionPass *llvm::createLowerExpectIntrinsicPass() { > + return new LowerExpectIntrinsic(); > +} > > Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=134516&r1=134515&r2=134516&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) > +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Wed Jul 6 13:22:43 2011 > @@ -39,6 +39,10 @@ > // Create the 'tbaa' metadata kind. > unsigned TBAAID = getMDKindID("tbaa"); > assert(TBAAID == MD_tbaa && "tbaa kind id drifted"); (void)TBAAID; > + > + // Create the 'prof' metadata kind. > + unsigned ProfID = getMDKindID("prof"); > + assert(ProfID == MD_prof && "prof kind id drifted"); (void)ProfID; > } > LLVMContext::~LLVMContext() { delete pImpl; } > > > Added: llvm/trunk/test/CodeGen/Generic/builtin-expect.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/builtin-expect.ll?rev=134516&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Generic/builtin-expect.ll (added) > +++ llvm/trunk/test/CodeGen/Generic/builtin-expect.ll Wed Jul 6 13:22:43 2011 > @@ -0,0 +1,223 @@ > +; RUN: llc < %s > + > +define i32 @test1(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp sgt i32 %tmp, 1 > + %conv = zext i1 %cmp to i32 > + %conv1 = sext i32 %conv to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1) > + %tobool = icmp ne i64 %expval, 0 > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +declare i64 @llvm.expect.i64(i64, i64) nounwind readnone > + > +declare i32 @f(...) > + > +define i32 @test2(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool = icmp ne i64 %expval, 0 > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test3(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %tobool = icmp ne i32 %tmp, 0 > + %lnot = xor i1 %tobool, true > + %lnot.ext = zext i1 %lnot to i32 > + %conv = sext i32 %lnot.ext to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool1 = icmp ne i64 %expval, 0 > + br i1 %tobool1, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test4(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %tobool = icmp ne i32 %tmp, 0 > + %lnot = xor i1 %tobool, true > + %lnot1 = xor i1 %lnot, true > + %lnot.ext = zext i1 %lnot1 to i32 > + %conv = sext i32 %lnot.ext to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool2 = icmp ne i64 %expval, 0 > + br i1 %tobool2, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test5(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp slt i32 %tmp, 0 > + %conv = zext i1 %cmp to i32 > + %conv1 = sext i32 %conv to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0) > + %tobool = icmp ne i64 %expval, 0 > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test6(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + switch i64 %expval, label %sw.epilog [ > + i64 1, label %sw.bb > + i64 2, label %sw.bb > + ] > + > +sw.bb: ; preds = %entry, %entry > + store i32 0, i32* %retval > + br label %return > + > +sw.epilog: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %sw.epilog, %sw.bb > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test7(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + switch i64 %expval, label %sw.epilog [ > + i64 2, label %sw.bb > + i64 3, label %sw.bb > + ] > + > +sw.bb: ; preds = %entry, %entry > + %tmp1 = load i32* %x.addr, align 4 > + store i32 %tmp1, i32* %retval > + br label %return > + > +sw.epilog: ; preds = %entry > + store i32 0, i32* %retval > + br label %return > + > +return: ; preds = %sw.epilog, %sw.bb > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +define i32 @test8(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp sgt i32 %tmp, 1 > + %conv = zext i1 %cmp to i32 > + %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1) > + %tobool = icmp ne i32 %expval, 0 > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +declare i32 @llvm.expect.i32(i32, i32) nounwind readnone > + > > Added: llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll?rev=134516&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll (added) > +++ llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll Wed Jul 6 13:22:43 2011 > @@ -0,0 +1,251 @@ > +; RUN: opt -lower-expect -strip-dead-prototypes -S -o - < %s | FileCheck %s > + > +; CHECK: @test1 > +define i32 @test1(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp sgt i32 %tmp, 1 > + %conv = zext i1 %cmp to i32 > + %conv1 = sext i32 %conv to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1) > + %tobool = icmp ne i64 %expval, 0 > +; CHECK: !prof !0 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +declare i64 @llvm.expect.i64(i64, i64) nounwind readnone > + > +declare i32 @f(...) > + > +; CHECK: @test2 > +define i32 @test2(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool = icmp ne i64 %expval, 0 > +; CHECK: !prof !0 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test3 > +define i32 @test3(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %tobool = icmp ne i32 %tmp, 0 > + %lnot = xor i1 %tobool, true > + %lnot.ext = zext i1 %lnot to i32 > + %conv = sext i32 %lnot.ext to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool1 = icmp ne i64 %expval, 0 > +; CHECK: !prof !0 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool1, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test4 > +define i32 @test4(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %tobool = icmp ne i32 %tmp, 0 > + %lnot = xor i1 %tobool, true > + %lnot1 = xor i1 %lnot, true > + %lnot.ext = zext i1 %lnot1 to i32 > + %conv = sext i32 %lnot.ext to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > + %tobool2 = icmp ne i64 %expval, 0 > +; CHECK: !prof !0 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool2, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test5 > +define i32 @test5(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp slt i32 %tmp, 0 > + %conv = zext i1 %cmp to i32 > + %conv1 = sext i32 %conv to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0) > + %tobool = icmp ne i64 %expval, 0 > +; CHECK: !prof !1 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test6 > +define i32 @test6(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > +; CHECK: !prof !2 > +; CHECK-NOT: @llvm.expect > + switch i64 %expval, label %sw.epilog [ > + i64 1, label %sw.bb > + i64 2, label %sw.bb > + ] > + > +sw.bb: ; preds = %entry, %entry > + store i32 0, i32* %retval > + br label %return > + > +sw.epilog: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %sw.epilog, %sw.bb > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test7 > +define i32 @test7(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %conv = sext i32 %tmp to i64 > + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) > +; CHECK: !prof !3 > +; CHECK-NOT: @llvm.expect > + switch i64 %expval, label %sw.epilog [ > + i64 2, label %sw.bb > + i64 3, label %sw.bb > + ] > + > +sw.bb: ; preds = %entry, %entry > + %tmp1 = load i32* %x.addr, align 4 > + store i32 %tmp1, i32* %retval > + br label %return > + > +sw.epilog: ; preds = %entry > + store i32 0, i32* %retval > + br label %return > + > +return: ; preds = %sw.epilog, %sw.bb > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +; CHECK: @test8 > +define i32 @test8(i32 %x) nounwind uwtable ssp { > +entry: > + %retval = alloca i32, align 4 > + %x.addr = alloca i32, align 4 > + store i32 %x, i32* %x.addr, align 4 > + %tmp = load i32* %x.addr, align 4 > + %cmp = icmp sgt i32 %tmp, 1 > + %conv = zext i1 %cmp to i32 > + %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1) > + %tobool = icmp ne i32 %expval, 0 > +; CHECK: !prof !0 > +; CHECK-NOT: @llvm.expect > + br i1 %tobool, label %if.then, label %if.end > + > +if.then: ; preds = %entry > + %call = call i32 (...)* @f() > + store i32 %call, i32* %retval > + br label %return > + > +if.end: ; preds = %entry > + store i32 1, i32* %retval > + br label %return > + > +return: ; preds = %if.end, %if.then > + %0 = load i32* %retval > + ret i32 %0 > +} > + > +declare i32 @llvm.expect.i32(i32, i32) nounwind readnone > + > +; CHECK: !0 = metadata !{metadata !"branch_weights", i32 64, i32 4} > +; CHECK: !1 = metadata !{metadata !"branch_weights", i32 4, i32 64} > +; CHECK: !2 = metadata !{metadata !"branch_weights", i32 4, i32 64, i32 4} > +; CHECK: !3 = metadata !{metadata !"branch_weights", i32 64, i32 4, i32 4} > > Added: llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp?rev=134516&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp (added) > +++ llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp Wed Jul 6 13:22:43 2011 > @@ -0,0 +1,3 @@ > +load_lib llvm.exp > + > +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From lhames at gmail.com Wed Jul 6 19:36:02 2011 From: lhames at gmail.com (Lang Hames) Date: Thu, 07 Jul 2011 00:36:02 -0000 Subject: [llvm-commits] [llvm] r134573 - /llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll Message-ID: <20110707003602.395442A6C12C@llvm.org> Author: lhames Date: Wed Jul 6 19:36:02 2011 New Revision: 134573 URL: http://llvm.org/viewvc/llvm-project?rev=134573&view=rev Log: Added a testcase for PR10220. Added: llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll Added: llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll?rev=134573&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll Wed Jul 6 19:36:02 2011 @@ -0,0 +1,15 @@ +; RUN: llc < %s +; This used to cause ScheduleDAG to crash during EmitPhysRegCopy when it mistook +; followed a non-control dependence, PR10220. + +define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp { +entry: + %c = load i256* %cc + %d = load i256* %dd + %add = add nsw i256 %c, %d + store i256 %add, i256* %a, align 8 + %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376 + %add6 = add nsw i256 %or, %d + store i256 %add6, i256* %b, align 8 + ret void +} From jstaszak at apple.com Wed Jul 6 19:36:12 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 06 Jul 2011 17:36:12 -0700 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/LowerExpectIntrinsic/ In-Reply-To: <2D61D6E4-1D32-49D8-A2A3-61714051E44A@apple.com> References: <20110706182243.7DE702A6C12C@llvm.org> <2D61D6E4-1D32-49D8-A2A3-61714051E44A@apple.com> Message-ID: <76383BF1-2644-43F0-BE4E-B83C07C17A4E@apple.com> On Jul 6, 2011, at 5:31 PM, Chris Lattner wrote: > > On Jul 6, 2011, at 11:22 AM, Jakub Staszak wrote: > >> Author: kuba >> Date: Wed Jul 6 13:22:43 2011 >> New Revision: 134516 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev >> Log: >> Introduce "expect" intrinsic instructions. >> > > Hi Kuba, > > Why is this introducing a new pass to do lowering? > > -Chris Hi Chris, This is the idea which came out in some discussions here. Do you think we should merge this pass with the other one? - Kuba From grosbach at apple.com Wed Jul 6 19:48:02 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 07 Jul 2011 00:48:02 -0000 Subject: [llvm-commits] [llvm] r134576 - in /llvm/trunk/utils/TableGen: CodeGenInstruction.cpp CodeGenInstruction.h Message-ID: <20110707004802.BD8052A6C12E@llvm.org> Author: grosbach Date: Wed Jul 6 19:48:02 2011 New Revision: 134576 URL: http://llvm.org/viewvc/llvm-project?rev=134576&view=rev Log: Add isCodeGenOnly value to the CodeGenInstruction class. So users of a CGI don't have to look up the value directly from the original Record; just like the rest of the convenience values in the class. Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=134576&r1=134575&r2=134576&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Wed Jul 6 19:48:02 2011 @@ -311,6 +311,7 @@ isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove"); hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); + isCodeGenOnly = R->getValueAsBit("isCodeGenOnly"); isPseudo = R->getValueAsBit("isPseudo"); ImplicitDefs = R->getValueAsListOfDefs("Defs"); ImplicitUses = R->getValueAsListOfDefs("Uses"); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=134576&r1=134575&r2=134576&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Wed Jul 6 19:48:02 2011 @@ -235,6 +235,7 @@ bool isAsCheapAsAMove; bool hasExtraSrcRegAllocReq; bool hasExtraDefRegAllocReq; + bool isCodeGenOnly; bool isPseudo; From isanbard at gmail.com Wed Jul 6 19:54:13 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 00:54:13 -0000 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h Message-ID: <20110707005413.494DB2A6C12C@llvm.org> Author: void Date: Wed Jul 6 19:54:13 2011 New Revision: 134577 URL: http://llvm.org/viewvc/llvm-project?rev=134577&view=rev Log: Add a target hook to encode the compact unwind information. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/include/llvm/Target/TargetFrameLowering.h llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/Target/TargetAsmInfo.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.h Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jul 6 19:54:13 2011 @@ -30,8 +30,9 @@ unsigned PointerSize; bool IsLittleEndian; TargetFrameLowering::StackDirection StackDir; - const TargetRegisterInfo *TRI; std::vector InitialFrameState; + const TargetRegisterInfo *TRI; + const TargetFrameLowering *TFI; const TargetLoweringObjectFile *TLOF; public: @@ -83,6 +84,11 @@ return TLOF->isFunctionEHFrameSymbolPrivate(); } + int getCompactUnwindEncoding(const std::vector &Instrs, + int DataAlignmentFactor, bool IsEH) const { + return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); + } + const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const { return TRI->getCalleeSavedRegs(MF); } @@ -106,10 +112,6 @@ int getSEHRegNum(unsigned RegNum) const { return TRI->getSEHRegNum(RegNum); } - - int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { - return TRI->getCompactUnwindRegNum(RegNum, isEH); - } }; } Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameLowering.h?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetFrameLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Wed Jul 6 19:54:13 2011 @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETFRAMELOWERING_H #define LLVM_TARGET_TARGETFRAMELOWERING_H +#include "llvm/MC/MCDwarf.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include @@ -189,6 +190,14 @@ /// virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { } + + /// getCompactUnwindEncoding - Get the compact unwind encoding for the + /// function. Return 0 if the compact unwind isn't available. + virtual uint32_t getCompactUnwindEncoding(const std::vector&, + int /*DataAlignmentFactor*/, + bool /*IsEH*/) const { + return 0; + } }; } // End llvm namespace Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jul 6 19:54:13 2011 @@ -499,7 +499,6 @@ bool UsingCFI; bool IsEH; const MCSymbol *SectionStart; - public: FrameEmitterImpl(bool usingCFI, bool isEH, const MCSymbol *sectionStart) : CFAOffset(0), CIENum(0), UsingCFI(usingCFI), IsEH(isEH), @@ -714,6 +713,11 @@ // .quad __gxx_personality // .quad except_tab1 + uint32_t Encoding = + TAI.getCompactUnwindEncoding(Frame.Instructions, + getDataAlignmentFactor(Streamer), IsEH); + if (!Encoding) return false; + Streamer.SwitchSection(TAI.getCompactUnwindSection()); // Range Start @@ -728,12 +732,10 @@ if (VerboseAsm) Streamer.AddComment("Range Length"); Streamer.EmitAbsValue(Range, 4); - // FIXME: // Compact Encoding - const std::vector &Moves = TAI.getInitialFrameState(); - uint32_t Encoding = 0; Size = getSizeForEncoding(Streamer, dwarf::DW_EH_PE_udata4); - if (VerboseAsm) Streamer.AddComment("Compact Unwind Encoding"); + if (VerboseAsm) Streamer.AddComment(Twine("Compact Unwind Encoding: 0x") + + Twine(llvm::utohexstr(Encoding))); Streamer.EmitIntValue(Encoding, Size); // Personality Function @@ -774,7 +776,7 @@ streamer.EmitLabel(sectionStart); CIENum++; - MCSymbol *sectionEnd = streamer.getContext().CreateTempSymbol(); + MCSymbol *sectionEnd = context.CreateTempSymbol(); // Length const MCExpr *Length = MakeStartMinusEndExpr(streamer, *sectionStart, Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Wed Jul 6 19:54:13 2011 @@ -20,8 +20,9 @@ const TargetData &TD = *TM.getTargetData(); IsLittleEndian = TD.isLittleEndian(); PointerSize = TD.getPointerSize(); - const TargetFrameLowering &TFI = *TM.getFrameLowering(); - StackDir = TFI.getStackGrowthDirection(); + + TFI = TM.getFrameLowering(); + StackDir = TFI->getStackGrowthDirection(); TRI = TM.getRegisterInfo(); - TFI.getInitialFrameState(InitialFrameState); + TFI->getInitialFrameState(InitialFrameState); } Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Jul 6 19:54:13 2011 @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" @@ -1029,3 +1030,100 @@ FrameIdx = 0; } } + +uint32_t X86FrameLowering:: +getCompactUnwindEncoding(const std::vector &Instrs, + int DataAlignmentFactor, bool IsEH) const { + uint32_t Encoding = 0; + int CFAOffset = 0; + const TargetRegisterInfo *TRI = TM.getRegisterInfo(); + SmallVector SavedRegs; + int FramePointerReg = -1; + + for (std::vector::const_iterator + I = Instrs.begin(), E = Instrs.end(); I != E; ++I) { + const MCCFIInstruction &Inst = *I; + MCSymbol *Label = Inst.getLabel(); + + // Ignore invalid labels. + if (Label && !Label->isDefined()) continue; + + unsigned Operation = Inst.getOperation(); + if (Operation != MCCFIInstruction::Move && + Operation != MCCFIInstruction::RelMove) + // FIXME: We can't handle this frame just yet. + return 0; + + const MachineLocation &Dst = Inst.getDestination(); + const MachineLocation &Src = Inst.getSource(); + const bool IsRelative = (Operation == MCCFIInstruction::RelMove); + + if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { + if (Src.getReg() == MachineLocation::VirtualFP) { + // DW_CFA_def_cfa_offset + if (IsRelative) + CFAOffset += Src.getOffset(); + else + CFAOffset = -Src.getOffset(); + } // else DW_CFA_def_cfa + + continue; + } + + if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { + // DW_CFA_def_cfa_register + FramePointerReg = Dst.getReg(); + continue; + } + + unsigned Reg = Src.getReg(); + int Offset = Dst.getOffset(); + if (IsRelative) + Offset -= CFAOffset; + Offset /= DataAlignmentFactor; + + if (Offset < 0) { + // FIXME: Handle? + // DW_CFA_offset_extended_sf + return 0; + } else if (Reg < 64) { + // DW_CFA_offset + Reg + SavedRegs.push_back(Reg); + } else { + // FIXME: Handle? + // DW_CFA_offset_extended + return 0; + } + } + + CFAOffset /= 4; + + // Check if the offset is too big. + if ((CFAOffset & 0xFF) != CFAOffset) + return 0; + + // Bail if there are too many registers to encode. + unsigned NumRegsToEncode = SavedRegs.size() - (FramePointerReg != -1 ? 1 : 0); + if (NumRegsToEncode > 5) return 0; + + if (TRI->getLLVMRegNum(FramePointerReg, IsEH) != X86::EBP && + TRI->getLLVMRegNum(FramePointerReg, IsEH) != X86::RBP) + // FIXME: Handle frameless version! + return 0; + + Encoding |= 1 << 24; + Encoding |= (CFAOffset & 0xFF) << 16; + + unsigned Idx = 0; + for (SmallVectorImpl::iterator + I = SavedRegs.begin(), E = SavedRegs.end(); I != E; ++I) { + if (*I == unsigned(FramePointerReg)) continue; + + int CURegNum = TRI->getCompactUnwindRegNum(*I, IsEH); + if (CURegNum == -1) return 0; + + Encoding |= (CURegNum & 0x7) << (Idx++ * 3); + } + + return Encoding; +} Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=134577&r1=134576&r2=134577&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Wed Jul 6 19:54:13 2011 @@ -15,6 +15,7 @@ #define X86_FRAMELOWERING_H #include "X86Subtarget.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/Target/TargetFrameLowering.h" namespace llvm { @@ -58,6 +59,9 @@ void getInitialFrameState(std::vector &Moves) const; int getFrameIndexOffset(const MachineFunction &MF, int FI) const; + + uint32_t getCompactUnwindEncoding(const std::vector &Instrs, + int DataAlignmentFactor, bool IsEH) const; }; } // End llvm namespace From clattner at apple.com Wed Jul 6 20:59:29 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 06 Jul 2011 18:59:29 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: <20110707005413.494DB2A6C12C@llvm.org> References: <20110707005413.494DB2A6C12C@llvm.org> Message-ID: <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> On Jul 6, 2011, at 5:54 PM, Bill Wendling wrote: > Author: void > Date: Wed Jul 6 19:54:13 2011 > New Revision: 134577 > > URL: http://llvm.org/viewvc/llvm-project?rev=134577&view=rev > Log: > Add a target hook to encode the compact unwind information. Ok. > +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Wed Jul 6 19:54:13 2011 > @@ -14,6 +14,7 @@ > #ifndef LLVM_TARGET_TARGETFRAMELOWERING_H > #define LLVM_TARGET_TARGETFRAMELOWERING_H > > +#include "llvm/MC/MCDwarf.h" > #include "llvm/CodeGen/MachineBasicBlock.h" Please forward declare MCCFIInstruction. > @@ -189,6 +190,14 @@ > /// > virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { > } > + > + /// getCompactUnwindEncoding - Get the compact unwind encoding for the > + /// function. Return 0 if the compact unwind isn't available. > + virtual uint32_t getCompactUnwindEncoding(const std::vector&, > + int /*DataAlignmentFactor*/, > + bool /*IsEH*/) const { Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? -Chris From eli.friedman at gmail.com Wed Jul 6 22:04:50 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 6 Jul 2011 20:04:50 -0700 Subject: [llvm-commits] [llvm] r134569 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h In-Reply-To: <20110707000819.518322A6C12C@llvm.org> References: <20110707000819.518322A6C12C@llvm.org> Message-ID: On Wed, Jul 6, 2011 at 5:08 PM, Evan Cheng wrote: > Author: evancheng > Date: Wed Jul ?6 19:08:19 2011 > New Revision: 134569 > > URL: http://llvm.org/viewvc/llvm-project?rev=134569&view=rev > Log: > Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. This appears to be making tests fail on multiple bots ( for example, http://google1.osuosl.org:8011/builders/llvm-x86_64-linux/builds/7701 ). -Eli > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARM.td > ? ?llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > ? ?llvm/trunk/lib/Target/ARM/ARMSubtarget.h > ? ?llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > ? ?llvm/trunk/lib/Target/ARM/ARMTargetMachine.h > ? ?llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > ? ?llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > > Modified: llvm/trunk/lib/Target/ARM/ARM.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARM.td (original) > +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Jul ?6 19:08:19 2011 > @@ -27,7 +27,7 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Enable VFP3 instructions">; > ?def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Enable NEON instructions">; > -def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", > +def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Enable Thumb2 instructions">; > ?def FeatureNoARM ?: SubtargetFeature<"noarm", "NoARM", "true", > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Does not support ARM mode execution">; > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jul ?6 19:08:19 2011 > @@ -37,7 +37,7 @@ > ? ? ? ? ? ? cl::desc("Disallow all unaligned memory accesses")); > > ?ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, > - ? ? ? ? ? ? ? ? ? ? ? ? ? const std::string &FS, bool isT) > + ? ? ? ? ? ? ? ? ? ? ? ? ? const std::string &FS) > ? : ARMGenSubtargetInfo() > ? , ARMArchVersion(V4) > ? , ARMProcFamily(Others) > @@ -46,8 +46,8 @@ > ? , SlowFPVMLx(false) > ? , HasVMLxForwarding(false) > ? , SlowFPBrcc(false) > - ?, IsThumb(isT) > - ?, ThumbMode(Thumb1) > + ?, IsThumb(false) > + ?, HasThumb2(false) > ? , NoARM(false) > ? , PostRAScheduler(false) > ? , IsR9Reserved(ReserveR9) > @@ -68,65 +68,8 @@ > ? , TargetTriple(TT) > ? , TargetABI(ARM_ABI_APCS) { > ? // Determine default and user specified characteristics > - > - ?// When no arch is specified either by CPU or by attributes, make the default > - ?// ARMv4T. > - ?const char *ARMArchFeature = ""; > ? if (CPUString.empty()) > ? ? CPUString = "generic"; > - ?if (CPUString == "generic" && (FS.empty() || FS == "generic")) { > - ? ?ARMArchVersion = V4T; > - ? ?ARMArchFeature = "+v4t"; > - ?} > - > - ?// Set the boolean corresponding to the current target triple, or the default > - ?// if one cannot be determined, to true. > - ?unsigned Len = TT.length(); > - ?unsigned Idx = 0; > - > - ?if (Len >= 5 && TT.substr(0, 4) == "armv") > - ? ?Idx = 4; > - ?else if (Len >= 6 && TT.substr(0, 5) == "thumb") { > - ? ?IsThumb = true; > - ? ?if (Len >= 7 && TT[5] == 'v') > - ? ? ?Idx = 6; > - ?} > - ?if (Idx) { > - ? ?unsigned SubVer = TT[Idx]; > - ? ?if (SubVer >= '7' && SubVer <= '9') { > - ? ? ?ARMArchVersion = V7A; > - ? ? ?ARMArchFeature = "+v7a"; > - ? ? ?if (Len >= Idx+2 && TT[Idx+1] == 'm') { > - ? ? ? ?ARMArchVersion = V7M; > - ? ? ? ?ARMArchFeature = "+v7m"; > - ? ? ?} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { > - ? ? ? ?ARMArchVersion = V7EM; > - ? ? ? ?ARMArchFeature = "+v7em"; > - ? ? ?} > - ? ?} else if (SubVer == '6') { > - ? ? ?ARMArchVersion = V6; > - ? ? ?ARMArchFeature = "+v6"; > - ? ? ?if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { > - ? ? ? ?ARMArchVersion = V6T2; > - ? ? ? ?ARMArchFeature = "+v6t2"; > - ? ? ?} > - ? ?} else if (SubVer == '5') { > - ? ? ?ARMArchVersion = V5T; > - ? ? ?ARMArchFeature = "+v5t"; > - ? ? ?if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { > - ? ? ? ?ARMArchVersion = V5TE; > - ? ? ? ?ARMArchFeature = "+v5te"; > - ? ? ?} > - ? ?} else if (SubVer == '4') { > - ? ? ?if (Len >= Idx+2 && TT[Idx+1] == 't') { > - ? ? ? ?ARMArchVersion = V4T; > - ? ? ? ?ARMArchFeature = "+v4t"; > - ? ? ?} else { > - ? ? ? ?ARMArchVersion = V4; > - ? ? ? ?ARMArchFeature = ""; > - ? ? ?} > - ? ?} > - ?} > > ? if (TT.find("eabi") != std::string::npos) > ? ? TargetABI = ARM_ABI_AAPCS; > @@ -134,12 +77,20 @@ > ? // Insert the architecture feature derived from the target triple into the > ? // feature string. This is important for setting features that are implied > ? // based on the architecture version. > - ?std::string FSWithArch = std::string(ARMArchFeature); > - ?if (FSWithArch.empty()) > - ? ?FSWithArch = FS; > - ?else if (!FS.empty()) > - ? ?FSWithArch = FSWithArch + "," + FS; > - ?ParseSubtargetFeatures(FSWithArch, CPUString); > + ?std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); > + ?if (!FS.empty()) { > + ? ?if (!ArchFS.empty()) > + ? ? ?ArchFS = ArchFS + "," + FS; > + ? ?else > + ? ? ?ArchFS = FS; > + ?} > + > + ?ParseSubtargetFeatures(ArchFS, CPUString); > + > + ?// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a > + ?// ARM version or CPU and then remove this. > + ?if (ARMArchVersion < V6T2 && hasThumb2()) > + ? ?ARMArchVersion = V6T2; > > ? // Initialize scheduling itinerary for the specified CPU. > ? InstrItins = getInstrItineraryForCPU(CPUString); > @@ -147,12 +98,6 @@ > ? // After parsing Itineraries, set ItinData.IssueWidth. > ? computeIssueWidth(); > > - ?// Thumb2 implies at least V6T2. > - ?if (ARMArchVersion >= V6T2) > - ? ?ThumbMode = Thumb2; > - ?else if (ThumbMode >= Thumb2) > - ? ?ARMArchVersion = V6T2; > - > ? if (isAAPCS_ABI()) > ? ? stackAlignment = 8; > > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jul ?6 19:08:19 2011 > @@ -14,6 +14,7 @@ > ?#ifndef ARMSUBTARGET_H > ?#define ARMSUBTARGET_H > > +#include "MCTargetDesc/ARMMCTargetDesc.h" > ?#include "llvm/Target/TargetSubtargetInfo.h" > ?#include "llvm/MC/MCInstrItineraries.h" > ?#include "llvm/ADT/Triple.h" > @@ -39,11 +40,6 @@ > ? ? None, VFPv2, VFPv3, NEON > ? }; > > - ?enum ThumbTypeEnum { > - ? ?Thumb1, > - ? ?Thumb2 > - ?}; > - > ? /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, > ? /// V6, V6T2, V7A, V7M, V7EM. > ? ARMArchEnum ARMArchVersion; > @@ -73,8 +69,8 @@ > ? /// IsThumb - True if we are in thumb mode, false if in ARM mode. > ? bool IsThumb; > > - ?/// ThumbMode - Indicates supported Thumb version. > - ?ThumbTypeEnum ThumbMode; > + ?/// HasThumb2 - True if Thumb2 instructions are supported. > + ?bool HasThumb2; > > ? /// NoARM - True if subtarget does not support ARM mode execution. > ? bool NoARM; > @@ -161,7 +157,7 @@ > ? /// of the specified triple. > ? /// > ? ARMSubtarget(const std::string &TT, const std::string &CPU, > - ? ? ? ? ? ? ? const std::string &FS, bool isThumb); > + ? ? ? ? ? ? ? const std::string &FS); > > ? /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size > ? /// that still makes it profitable to inline the call. > @@ -217,9 +213,9 @@ > ? bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } > > ? bool isThumb() const { return IsThumb; } > - ?bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } > - ?bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } > - ?bool hasThumb2() const { return ThumbMode >= Thumb2; } > + ?bool isThumb1Only() const { return IsThumb && !HasThumb2; } > + ?bool isThumb2() const { return IsThumb && HasThumb2; } > + ?bool hasThumb2() const { return HasThumb2; } > > ? bool isR9Reserved() const { return IsR9Reserved; } > > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jul ?6 19:08:19 2011 > @@ -79,10 +79,9 @@ > ?ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &TT, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &CPU, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const std::string &FS, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isThumb) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const std::string &FS) > ? : LLVMTargetMachine(T, TT), > - ? ?Subtarget(TT, CPU, FS, isThumb), > + ? ?Subtarget(TT, CPU, FS), > ? ? JITInfo(), > ? ? InstrItins(Subtarget.getInstrItineraryData()) { > ? DefRelocModel = getRelocationModel(); > @@ -95,7 +94,7 @@ > ?ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &CPU, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS) > - ?: ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget), > + ?: ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), > ? ? DataLayout(Subtarget.isAPCS_ABI() ? > ? ? ? ? ? ? ? ?std::string("e-p:32:32-f64:32:64-i64:32:64-" > ? ? ? ? ? ? ? ? ? ? ? ? ? ?"v128:32:128-v64:32:64-n32") : > @@ -113,7 +112,7 @@ > ?ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &CPU, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS) > - ?: ARMBaseTargetMachine(T, TT, CPU, FS, true), > + ?: ARMBaseTargetMachine(T, TT, CPU, FS), > ? ? InstrInfo(Subtarget.hasThumb2() > ? ? ? ? ? ? ? ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) > ? ? ? ? ? ? ? : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jul ?6 19:08:19 2011 > @@ -41,8 +41,7 @@ > > ?public: > ? ARMBaseTargetMachine(const Target &T, const std::string &TT, > - ? ? ? ? ? ? ? ? ? ? ? const std::string &CPU, const std::string &FS, > - ? ? ? ? ? ? ? ? ? ? ? bool isThumb); > + ? ? ? ? ? ? ? ? ? ? ? const std::string &CPU, const std::string &FS); > > ? virtual ? ? ? ARMJITInfo ? ? ? *getJITInfo() ? ? ? ? { return &JITInfo; } > ? virtual const ARMSubtarget ?*getSubtargetImpl() const { return &Subtarget; } > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul ?6 19:08:19 2011 > @@ -72,3 +72,49 @@ > ? TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createARMMCSubtargetInfo); > ?} > + > +std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { > + ?// Set the boolean corresponding to the current target triple, or the default > + ?// if one cannot be determined, to true. > + ?unsigned Len = TT.size(); > + ?unsigned Idx = 0; > + > + ?if (Len >= 5 && TT.substr(0, 4) == "armv") > + ? ?Idx = 4; > + ?else if (Len >= 6 && TT.substr(0, 5) == "thumb") { > + ? ?IsThumb = true; > + ? ?if (Len >= 7 && TT[5] == 'v') > + ? ? ?Idx = 6; > + ?} > + > + ?std::string ARMArchFeature; > + ?if (Idx) { > + ? ?unsigned SubVer = TT[Idx]; > + ? ?if (SubVer >= '7' && SubVer <= '9') { > + ? ? ?ARMArchFeature = "+v7a"; > + ? ? ?if (Len >= Idx+2 && TT[Idx+1] == 'm') { > + ? ? ? ?ARMArchFeature = "+v7m"; > + ? ? ?} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { > + ? ? ? ?ARMArchFeature = "+v7em"; > + ? ? ?} > + ? ?} else if (SubVer == '6') { > + ? ? ?ARMArchFeature = "+v6"; > + ? ? ?if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { > + ? ? ? ?ARMArchFeature = "+v6t2"; > + ? ? ?} > + ? ?} else if (SubVer == '5') { > + ? ? ?ARMArchFeature = "+v5t"; > + ? ? ?if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { > + ? ? ? ?ARMArchFeature = "+v5te"; > + ? ? ?} > + ? ?} else if (SubVer == '4') { > + ? ? ?if (Len >= Idx+2 && TT[Idx+1] == 't') { > + ? ? ? ?ARMArchFeature = "+v4t"; > + ? ? ?} else { > + ? ? ? ?ARMArchFeature = ""; > + ? ? ?} > + ? ?} > + ?} > + > + ?return ARMArchFeature; > +} > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134569&r1=134568&r2=134569&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jul ?6 19:08:19 2011 > @@ -14,10 +14,18 @@ > ?#ifndef ARMMCTARGETDESC_H > ?#define ARMMCTARGETDESC_H > > +#include > + > ?namespace llvm { > ?class Target; > +class StringRef; > > ?extern Target TheARMTarget, TheThumbTarget; > + > +namespace ARM_MC { > + ?std::string ParseARMTriple(StringRef TT, bool &IsThumb); > +} > + > ?} // End llvm namespace > > ?// Defines symbolic names for ARM registers. ?This defines a mapping from > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Wed Jul 6 22:51:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Jul 2011 20:51:49 -0700 Subject: [llvm-commits] [llvm] r134569 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h In-Reply-To: References: <20110707000819.518322A6C12C@llvm.org> Message-ID: <54326AA6-465D-402C-BA08-D714395DDB28@apple.com> I have follow-on patch that should fix these. Evan On Jul 6, 2011, at 8:04 PM, Eli Friedman wrote: > On Wed, Jul 6, 2011 at 5:08 PM, Evan Cheng wrote: >> Author: evancheng >> Date: Wed Jul 6 19:08:19 2011 >> New Revision: 134569 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134569&view=rev >> Log: >> Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. > > This appears to be making tests fail on multiple bots ( for example, > http://google1.osuosl.org:8011/builders/llvm-x86_64-linux/builds/7701 > ). > > -Eli > >> Modified: >> llvm/trunk/lib/Target/ARM/ARM.td >> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> >> Modified: llvm/trunk/lib/Target/ARM/ARM.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARM.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Jul 6 19:08:19 2011 >> @@ -27,7 +27,7 @@ >> "Enable VFP3 instructions">; >> def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", >> "Enable NEON instructions">; >> -def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", >> +def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", >> "Enable Thumb2 instructions">; >> def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", >> "Does not support ARM mode execution">; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jul 6 19:08:19 2011 >> @@ -37,7 +37,7 @@ >> cl::desc("Disallow all unaligned memory accesses")); >> >> ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, >> - const std::string &FS, bool isT) >> + const std::string &FS) >> : ARMGenSubtargetInfo() >> , ARMArchVersion(V4) >> , ARMProcFamily(Others) >> @@ -46,8 +46,8 @@ >> , SlowFPVMLx(false) >> , HasVMLxForwarding(false) >> , SlowFPBrcc(false) >> - , IsThumb(isT) >> - , ThumbMode(Thumb1) >> + , IsThumb(false) >> + , HasThumb2(false) >> , NoARM(false) >> , PostRAScheduler(false) >> , IsR9Reserved(ReserveR9) >> @@ -68,65 +68,8 @@ >> , TargetTriple(TT) >> , TargetABI(ARM_ABI_APCS) { >> // Determine default and user specified characteristics >> - >> - // When no arch is specified either by CPU or by attributes, make the default >> - // ARMv4T. >> - const char *ARMArchFeature = ""; >> if (CPUString.empty()) >> CPUString = "generic"; >> - if (CPUString == "generic" && (FS.empty() || FS == "generic")) { >> - ARMArchVersion = V4T; >> - ARMArchFeature = "+v4t"; >> - } >> - >> - // Set the boolean corresponding to the current target triple, or the default >> - // if one cannot be determined, to true. >> - unsigned Len = TT.length(); >> - unsigned Idx = 0; >> - >> - if (Len >= 5 && TT.substr(0, 4) == "armv") >> - Idx = 4; >> - else if (Len >= 6 && TT.substr(0, 5) == "thumb") { >> - IsThumb = true; >> - if (Len >= 7 && TT[5] == 'v') >> - Idx = 6; >> - } >> - if (Idx) { >> - unsigned SubVer = TT[Idx]; >> - if (SubVer >= '7' && SubVer <= '9') { >> - ARMArchVersion = V7A; >> - ARMArchFeature = "+v7a"; >> - if (Len >= Idx+2 && TT[Idx+1] == 'm') { >> - ARMArchVersion = V7M; >> - ARMArchFeature = "+v7m"; >> - } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { >> - ARMArchVersion = V7EM; >> - ARMArchFeature = "+v7em"; >> - } >> - } else if (SubVer == '6') { >> - ARMArchVersion = V6; >> - ARMArchFeature = "+v6"; >> - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { >> - ARMArchVersion = V6T2; >> - ARMArchFeature = "+v6t2"; >> - } >> - } else if (SubVer == '5') { >> - ARMArchVersion = V5T; >> - ARMArchFeature = "+v5t"; >> - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { >> - ARMArchVersion = V5TE; >> - ARMArchFeature = "+v5te"; >> - } >> - } else if (SubVer == '4') { >> - if (Len >= Idx+2 && TT[Idx+1] == 't') { >> - ARMArchVersion = V4T; >> - ARMArchFeature = "+v4t"; >> - } else { >> - ARMArchVersion = V4; >> - ARMArchFeature = ""; >> - } >> - } >> - } >> >> if (TT.find("eabi") != std::string::npos) >> TargetABI = ARM_ABI_AAPCS; >> @@ -134,12 +77,20 @@ >> // Insert the architecture feature derived from the target triple into the >> // feature string. This is important for setting features that are implied >> // based on the architecture version. >> - std::string FSWithArch = std::string(ARMArchFeature); >> - if (FSWithArch.empty()) >> - FSWithArch = FS; >> - else if (!FS.empty()) >> - FSWithArch = FSWithArch + "," + FS; >> - ParseSubtargetFeatures(FSWithArch, CPUString); >> + std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); >> + if (!FS.empty()) { >> + if (!ArchFS.empty()) >> + ArchFS = ArchFS + "," + FS; >> + else >> + ArchFS = FS; >> + } >> + >> + ParseSubtargetFeatures(ArchFS, CPUString); >> + >> + // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a >> + // ARM version or CPU and then remove this. >> + if (ARMArchVersion < V6T2 && hasThumb2()) >> + ARMArchVersion = V6T2; >> >> // Initialize scheduling itinerary for the specified CPU. >> InstrItins = getInstrItineraryForCPU(CPUString); >> @@ -147,12 +98,6 @@ >> // After parsing Itineraries, set ItinData.IssueWidth. >> computeIssueWidth(); >> >> - // Thumb2 implies at least V6T2. >> - if (ARMArchVersion >= V6T2) >> - ThumbMode = Thumb2; >> - else if (ThumbMode >= Thumb2) >> - ARMArchVersion = V6T2; >> - >> if (isAAPCS_ABI()) >> stackAlignment = 8; >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jul 6 19:08:19 2011 >> @@ -14,6 +14,7 @@ >> #ifndef ARMSUBTARGET_H >> #define ARMSUBTARGET_H >> >> +#include "MCTargetDesc/ARMMCTargetDesc.h" >> #include "llvm/Target/TargetSubtargetInfo.h" >> #include "llvm/MC/MCInstrItineraries.h" >> #include "llvm/ADT/Triple.h" >> @@ -39,11 +40,6 @@ >> None, VFPv2, VFPv3, NEON >> }; >> >> - enum ThumbTypeEnum { >> - Thumb1, >> - Thumb2 >> - }; >> - >> /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, >> /// V6, V6T2, V7A, V7M, V7EM. >> ARMArchEnum ARMArchVersion; >> @@ -73,8 +69,8 @@ >> /// IsThumb - True if we are in thumb mode, false if in ARM mode. >> bool IsThumb; >> >> - /// ThumbMode - Indicates supported Thumb version. >> - ThumbTypeEnum ThumbMode; >> + /// HasThumb2 - True if Thumb2 instructions are supported. >> + bool HasThumb2; >> >> /// NoARM - True if subtarget does not support ARM mode execution. >> bool NoARM; >> @@ -161,7 +157,7 @@ >> /// of the specified triple. >> /// >> ARMSubtarget(const std::string &TT, const std::string &CPU, >> - const std::string &FS, bool isThumb); >> + const std::string &FS); >> >> /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size >> /// that still makes it profitable to inline the call. >> @@ -217,9 +213,9 @@ >> bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } >> >> bool isThumb() const { return IsThumb; } >> - bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } >> - bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } >> - bool hasThumb2() const { return ThumbMode >= Thumb2; } >> + bool isThumb1Only() const { return IsThumb && !HasThumb2; } >> + bool isThumb2() const { return IsThumb && HasThumb2; } >> + bool hasThumb2() const { return HasThumb2; } >> >> bool isR9Reserved() const { return IsR9Reserved; } >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jul 6 19:08:19 2011 >> @@ -79,10 +79,9 @@ >> ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, >> const std::string &TT, >> const std::string &CPU, >> - const std::string &FS, >> - bool isThumb) >> + const std::string &FS) >> : LLVMTargetMachine(T, TT), >> - Subtarget(TT, CPU, FS, isThumb), >> + Subtarget(TT, CPU, FS), >> JITInfo(), >> InstrItins(Subtarget.getInstrItineraryData()) { >> DefRelocModel = getRelocationModel(); >> @@ -95,7 +94,7 @@ >> ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget), >> + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), >> DataLayout(Subtarget.isAPCS_ABI() ? >> std::string("e-p:32:32-f64:32:64-i64:32:64-" >> "v128:32:128-v64:32:64-n32") : >> @@ -113,7 +112,7 @@ >> ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : ARMBaseTargetMachine(T, TT, CPU, FS, true), >> + : ARMBaseTargetMachine(T, TT, CPU, FS), >> InstrInfo(Subtarget.hasThumb2() >> ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) >> : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), >> >> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jul 6 19:08:19 2011 >> @@ -41,8 +41,7 @@ >> >> public: >> ARMBaseTargetMachine(const Target &T, const std::string &TT, >> - const std::string &CPU, const std::string &FS, >> - bool isThumb); >> + const std::string &CPU, const std::string &FS); >> >> virtual ARMJITInfo *getJITInfo() { return &JITInfo; } >> virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 6 19:08:19 2011 >> @@ -72,3 +72,49 @@ >> TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, >> createARMMCSubtargetInfo); >> } >> + >> +std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { >> + // Set the boolean corresponding to the current target triple, or the default >> + // if one cannot be determined, to true. >> + unsigned Len = TT.size(); >> + unsigned Idx = 0; >> + >> + if (Len >= 5 && TT.substr(0, 4) == "armv") >> + Idx = 4; >> + else if (Len >= 6 && TT.substr(0, 5) == "thumb") { >> + IsThumb = true; >> + if (Len >= 7 && TT[5] == 'v') >> + Idx = 6; >> + } >> + >> + std::string ARMArchFeature; >> + if (Idx) { >> + unsigned SubVer = TT[Idx]; >> + if (SubVer >= '7' && SubVer <= '9') { >> + ARMArchFeature = "+v7a"; >> + if (Len >= Idx+2 && TT[Idx+1] == 'm') { >> + ARMArchFeature = "+v7m"; >> + } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { >> + ARMArchFeature = "+v7em"; >> + } >> + } else if (SubVer == '6') { >> + ARMArchFeature = "+v6"; >> + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { >> + ARMArchFeature = "+v6t2"; >> + } >> + } else if (SubVer == '5') { >> + ARMArchFeature = "+v5t"; >> + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { >> + ARMArchFeature = "+v5te"; >> + } >> + } else if (SubVer == '4') { >> + if (Len >= Idx+2 && TT[Idx+1] == 't') { >> + ARMArchFeature = "+v4t"; >> + } else { >> + ARMArchFeature = ""; >> + } >> + } >> + } >> + >> + return ARMArchFeature; >> +} >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134569&r1=134568&r2=134569&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jul 6 19:08:19 2011 >> @@ -14,10 +14,18 @@ >> #ifndef ARMMCTARGETDESC_H >> #define ARMMCTARGETDESC_H >> >> +#include >> + >> namespace llvm { >> class Target; >> +class StringRef; >> >> extern Target TheARMTarget, TheThumbTarget; >> + >> +namespace ARM_MC { >> + std::string ParseARMTriple(StringRef TT, bool &IsThumb); >> +} >> + >> } // End llvm namespace >> >> // Defines symbolic names for ARM registers. This defines a mapping from >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From evan.cheng at apple.com Wed Jul 6 22:55:05 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 03:55:05 -0000 Subject: [llvm-commits] [llvm] r134590 - in /llvm/trunk: lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/ test/CodeGen/ARM/ test/CodeGen/Thumb/ test/CodeGen/Thumb2/ test/MC/ARM/ Message-ID: <20110707035505.E8A8C2A6C12C@llvm.org> Author: evancheng Date: Wed Jul 6 22:55:05 2011 New Revision: 134590 URL: http://llvm.org/viewvc/llvm-project?rev=134590&view=rev Log: Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/test/CodeGen/ARM/2009-10-30.ll llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll llvm/trunk/test/CodeGen/ARM/armv4.ll llvm/trunk/test/CodeGen/ARM/bfx.ll llvm/trunk/test/CodeGen/ARM/call.ll llvm/trunk/test/CodeGen/ARM/globals.ll llvm/trunk/test/CodeGen/ARM/hello.ll llvm/trunk/test/CodeGen/ARM/iabs.ll llvm/trunk/test/CodeGen/ARM/ifcvt1.ll llvm/trunk/test/CodeGen/ARM/ifcvt2.ll llvm/trunk/test/CodeGen/ARM/ifcvt3.ll llvm/trunk/test/CodeGen/ARM/indirectbr.ll llvm/trunk/test/CodeGen/ARM/ldr_frame.ll llvm/trunk/test/CodeGen/ARM/phi.ll llvm/trunk/test/CodeGen/ARM/prefetch.ll llvm/trunk/test/CodeGen/ARM/truncstore-dag-combine.ll llvm/trunk/test/CodeGen/Thumb/barrier.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-clz.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-rev.ll llvm/trunk/test/MC/ARM/prefetch.ll Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Jul 6 22:55:05 2011 @@ -21,12 +21,14 @@ // ARM Subtarget features. // -def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2", +def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", "Enable VFP2 instructions">; -def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3", - "Enable VFP3 instructions">; -def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", - "Enable NEON instructions">; +def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", + "Enable VFP3 instructions", + [FeatureVFP2]>; +def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", + "Enable NEON instructions", + [FeatureVFP3]>; def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", @@ -84,33 +86,23 @@ "Supports Multiprocessing extension">; // ARM architectures. -def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T", +def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "ARM v4T">; -def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T", - "ARM v5T">; -def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE", - "ARM v5TE, v5TEj, v5TExp">; -def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6", - "ARM v6">; -def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M", - "ARM v6m", - [FeatureNoARM, FeatureDB]>; -def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2", +def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", + "ARM v5T", + [HasV4TOps]>; +def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", + "ARM v5TE, v5TEj, v5TExp", + [HasV5TOps]>; +def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", + "ARM v6", + [HasV5TEOps]>; +def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "ARM v6t2", - [FeatureThumb2, FeatureDSPThumb2]>; -def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A", - "ARM v7A", - [FeatureThumb2, FeatureNEON, FeatureDB, - FeatureDSPThumb2]>; -def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M", - "ARM v7M", - [FeatureThumb2, FeatureNoARM, FeatureDB, - FeatureHWDiv]>; -def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM", - "ARM v7E-M", - [FeatureThumb2, FeatureNoARM, FeatureDB, - FeatureHWDiv, FeatureDSPThumb2, - FeatureT2XtPk]>; + [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>; +def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", + "ARM v7", + [HasV6T2Ops]>; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -145,64 +137,76 @@ def : ProcNoItin<"strongarm1110", []>; // V4T Processors. -def : ProcNoItin<"arm7tdmi", [ArchV4T]>; -def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; -def : ProcNoItin<"arm710t", [ArchV4T]>; -def : ProcNoItin<"arm720t", [ArchV4T]>; -def : ProcNoItin<"arm9", [ArchV4T]>; -def : ProcNoItin<"arm9tdmi", [ArchV4T]>; -def : ProcNoItin<"arm920", [ArchV4T]>; -def : ProcNoItin<"arm920t", [ArchV4T]>; -def : ProcNoItin<"arm922t", [ArchV4T]>; -def : ProcNoItin<"arm940t", [ArchV4T]>; -def : ProcNoItin<"ep9312", [ArchV4T]>; +def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; +def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; +def : ProcNoItin<"arm710t", [HasV4TOps]>; +def : ProcNoItin<"arm720t", [HasV4TOps]>; +def : ProcNoItin<"arm9", [HasV4TOps]>; +def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; +def : ProcNoItin<"arm920", [HasV4TOps]>; +def : ProcNoItin<"arm920t", [HasV4TOps]>; +def : ProcNoItin<"arm922t", [HasV4TOps]>; +def : ProcNoItin<"arm940t", [HasV4TOps]>; +def : ProcNoItin<"ep9312", [HasV4TOps]>; // V5T Processors. -def : ProcNoItin<"arm10tdmi", [ArchV5T]>; -def : ProcNoItin<"arm1020t", [ArchV5T]>; +def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; +def : ProcNoItin<"arm1020t", [HasV5TOps]>; // V5TE Processors. -def : ProcNoItin<"arm9e", [ArchV5TE]>; -def : ProcNoItin<"arm926ej-s", [ArchV5TE]>; -def : ProcNoItin<"arm946e-s", [ArchV5TE]>; -def : ProcNoItin<"arm966e-s", [ArchV5TE]>; -def : ProcNoItin<"arm968e-s", [ArchV5TE]>; -def : ProcNoItin<"arm10e", [ArchV5TE]>; -def : ProcNoItin<"arm1020e", [ArchV5TE]>; -def : ProcNoItin<"arm1022e", [ArchV5TE]>; -def : ProcNoItin<"xscale", [ArchV5TE]>; -def : ProcNoItin<"iwmmxt", [ArchV5TE]>; +def : ProcNoItin<"arm9e", [HasV5TEOps]>; +def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; +def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm10e", [HasV5TEOps]>; +def : ProcNoItin<"arm1020e", [HasV5TEOps]>; +def : ProcNoItin<"arm1022e", [HasV5TEOps]>; +def : ProcNoItin<"xscale", [HasV5TEOps]>; +def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; // V6 Processors. -def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>; -def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>; -def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>; -def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; // V6M Processors. -def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>; +def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, + FeatureDB]>; // V6T2 Processors. -def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>; -def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2, +def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>; +def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -// V7 Processors. +// V7a Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, ProcA8]>; + [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2]>; def : Processor<"cortex-a9", CortexA9Itineraries, - [ArchV7A, ProcA9]>; + [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2]>; def : Processor<"cortex-a9-mp", CortexA9Itineraries, - [ArchV7A, ProcA9, FeatureMP]>; + [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2, FeatureMP]>; // V7M Processors. -def : ProcNoItin<"cortex-m3", [ArchV7M]>; -def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>; +def : ProcNoItin<"cortex-m3", [HasV7Ops, + FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv]>; + +// V7EM Processors. +def : ProcNoItin<"cortex-m4", [HasV7Ops, + FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv, FeatureDSPThumb2, + FeatureT2XtPk, FeatureVFP2, + FeatureVFPOnlySP]>; //===----------------------------------------------------------------------===// // Register File Description Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jul 6 22:55:05 2011 @@ -39,9 +39,16 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : ARMGenSubtargetInfo() - , ARMArchVersion(V4) , ARMProcFamily(Others) - , ARMFPUType(None) + , HasV4TOps(false) + , HasV5TOps(false) + , HasV5TEOps(false) + , HasV6Ops(false) + , HasV6T2Ops(false) + , HasV7Ops(false) + , HasVFPv2(false) + , HasVFPv3(false) + , HasNEON(false) , UseNEONForSinglePrecisionFP(false) , SlowFPVMLx(false) , HasVMLxForwarding(false) @@ -89,8 +96,8 @@ // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a // ARM version or CPU and then remove this. - if (ARMArchVersion < V6T2 && hasThumb2()) - ARMArchVersion = V6T2; + if (!HasV6T2Ops && hasThumb2()) + HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); @@ -104,7 +111,7 @@ if (!isTargetDarwin()) UseMovt = hasV6T2Ops(); else { - IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); + IsR9Reserved = ReserveR9 | !HasV6Ops; UseMovt = DarwinUseMOVT && hasV6T2Ops(); } Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jul 6 22:55:05 2011 @@ -28,27 +28,27 @@ class ARMSubtarget : public ARMGenSubtargetInfo { protected: - enum ARMArchEnum { - V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM - }; - enum ARMProcFamilyEnum { Others, CortexA8, CortexA9 }; - enum ARMFPEnum { - None, VFPv2, VFPv3, NEON - }; - - /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, - /// V6, V6T2, V7A, V7M, V7EM. - ARMArchEnum ARMArchVersion; - /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. ARMProcFamilyEnum ARMProcFamily; - /// ARMFPUType - Floating Point Unit type. - ARMFPEnum ARMFPUType; + /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops - + /// Specify whether target support specific ARM ISA variants. + bool HasV4TOps; + bool HasV5TOps; + bool HasV5TEOps; + bool HasV6Ops; + bool HasV6T2Ops; + bool HasV7Ops; + + /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are + /// supported. + bool HasVFPv2; + bool HasVFPv3; + bool HasNEON; /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been /// specified. Use the method useNEONForSinglePrecisionFP() to @@ -172,23 +172,24 @@ void computeIssueWidth(); - bool hasV4TOps() const { return ARMArchVersion >= V4T; } - bool hasV5TOps() const { return ARMArchVersion >= V5T; } - bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } - bool hasV6Ops() const { return ARMArchVersion >= V6; } - bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } - bool hasV7Ops() const { return ARMArchVersion >= V7A; } + bool hasV4TOps() const { return HasV4TOps; } + bool hasV5TOps() const { return HasV5TOps; } + bool hasV5TEOps() const { return HasV5TEOps; } + bool hasV6Ops() const { return HasV6Ops; } + bool hasV6T2Ops() const { return HasV6T2Ops; } + bool hasV7Ops() const { return HasV7Ops; } bool isCortexA8() const { return ARMProcFamily == CortexA8; } bool isCortexA9() const { return ARMProcFamily == CortexA9; } bool hasARMOps() const { return !NoARM; } - bool hasVFP2() const { return ARMFPUType >= VFPv2; } - bool hasVFP3() const { return ARMFPUType >= VFPv3; } - bool hasNEON() const { return ARMFPUType >= NEON; } + bool hasVFP2() const { return HasVFPv2; } + bool hasVFP3() const { return HasVFPv3; } + bool hasNEON() const { return HasNEON; } bool useNEONForSinglePrecisionFP() const { return hasNEON() && UseNEONForSinglePrecisionFP; } + bool hasDivide() const { return HasHardwareDivide; } bool hasT2ExtractPack() const { return HasT2ExtractPack; } bool hasDataBarrier() const { return HasDataBarrier; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 6 22:55:05 2011 @@ -91,29 +91,28 @@ if (Idx) { unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { - ARMArchFeature = "+v7a"; if (Len >= Idx+2 && TT[Idx+1] == 'm') { - ARMArchFeature = "+v7m"; + // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv + ARMArchFeature = "+v7,+noarm,+db,+hwdiv"; } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { - ARMArchFeature = "+v7em"; - } + // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, + // FeatureT2XtPk + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk"; + } else + // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2 + ARMArchFeature = "+v7,+neon,+db,+t2dsp"; } else if (SubVer == '6') { - ARMArchFeature = "+v6"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') ARMArchFeature = "+v6t2"; - } + else + ARMArchFeature = "+v6"; } else if (SubVer == '5') { - ARMArchFeature = "+v5t"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') ARMArchFeature = "+v5te"; - } - } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') { - ARMArchFeature = "+v4t"; - } else { - ARMArchFeature = ""; - } - } + else + ARMArchFeature = "+v5t"; + } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't') + ARMArchFeature = "+v4t"; } return ARMArchFeature; Modified: llvm/trunk/test/CodeGen/ARM/2009-10-30.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-30.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-10-30.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-10-30.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s ; This test checks that the address of the varg arguments is correctly ; computed when there are 5 or more regular arguments. Modified: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Wed Jul 6 22:55:05 2011 @@ -1,7 +1,7 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ -; RUN: -mattr=-neon -mattr=+vfp2 \ +; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s Modified: llvm/trunk/test/CodeGen/ARM/armv4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/armv4.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/armv4.ll (original) +++ llvm/trunk/test/CodeGen/ARM/armv4.ll Wed Jul 6 22:55:05 2011 @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB Modified: llvm/trunk/test/CodeGen/ARM/bfx.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfx.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bfx.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bfx.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s define i32 @sbfx1(i32 %a) { ; CHECK: sbfx1 Modified: llvm/trunk/test/CodeGen/ARM/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/call.ll (original) +++ llvm/trunk/test/CodeGen/ARM/call.ll Wed Jul 6 22:55:05 2011 @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi\ ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/globals.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/globals.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/globals.ll (original) +++ llvm/trunk/test/CodeGen/ARM/globals.ll Wed Jul 6 22:55:05 2011 @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC -; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC @G = external global i32 Modified: llvm/trunk/test/CodeGen/ARM/hello.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hello.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/hello.ll (original) +++ llvm/trunk/test/CodeGen/ARM/hello.ll Wed Jul 6 22:55:05 2011 @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 -; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 +; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" Modified: llvm/trunk/test/CodeGen/ARM/iabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/iabs.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/iabs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/iabs.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: ;; add r3, r0, r0, asr #31 Modified: llvm/trunk/test/CodeGen/ARM/ifcvt1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt1.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt1.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt1.ll Wed Jul 6 22:55:05 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep bx | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1 define i32 @t1(i32 %a, i32 %b) { %tmp2 = icmp eq i32 %a, 0 Modified: llvm/trunk/test/CodeGen/ARM/ifcvt2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt2.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt2.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: Modified: llvm/trunk/test/CodeGen/ARM/ifcvt3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt3.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt3.ll Wed Jul 6 22:55:05 2011 @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep cmpne | count 1 -; RUN: llc < %s -march=arm | grep bx | count 2 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { switch i32 %c, label %cond_next [ Modified: llvm/trunk/test/CodeGen/ARM/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/indirectbr.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/indirectbr.ll (original) +++ llvm/trunk/test/CodeGen/ARM/indirectbr.ll Wed Jul 6 22:55:05 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2 @nextaddr = global i8* null ; [#uses=2] Modified: llvm/trunk/test/CodeGen/ARM/ldr_frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldr_frame.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ldr_frame.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ldr_frame.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define i32 @f1() { %buf = alloca [32 x i32], align 4 Modified: llvm/trunk/test/CodeGen/ARM/phi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/phi.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/phi.ll (original) +++ llvm/trunk/test/CodeGen/ARM/phi.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc -march=arm < %s | FileCheck %s +; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s ; define i32 @test1(i1 %a, i32* %b) { @@ -20,4 +20,4 @@ %r = load i32* %gep ; CHECK-NEXT: bx lr ret i32 %r -} \ No newline at end of file +} Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original) +++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Wed Jul 6 22:55:05 2011 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 Modified: llvm/trunk/test/CodeGen/ARM/truncstore-dag-combine.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/truncstore-dag-combine.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/truncstore-dag-combine.ll (original) +++ llvm/trunk/test/CodeGen/ARM/truncstore-dag-combine.ll Wed Jul 6 22:55:05 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | not grep orr -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define void @bar(i8* %P, i16* %Q) { entry: Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/barrier.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/barrier.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/barrier.ll Wed Jul 6 22:55:05 2011 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M +; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-clz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-clz.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-clz.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-clz.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-rev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-rev.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-rev.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-rev.ll Wed Jul 6 22:55:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: Modified: llvm/trunk/test/MC/ARM/prefetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/prefetch.ll?rev=134590&r1=134589&r2=134590&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/prefetch.ll (original) +++ llvm/trunk/test/MC/ARM/prefetch.ll Wed Jul 6 22:55:05 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2 ; rdar://8924681 define void @t1(i8* %ptr) nounwind { From lhames at gmail.com Wed Jul 6 23:31:51 2011 From: lhames at gmail.com (Lang Hames) Date: Thu, 07 Jul 2011 04:31:51 -0000 Subject: [llvm-commits] [llvm] r134592 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20110707043151.5C4E22A6C12C@llvm.org> Author: lhames Date: Wed Jul 6 23:31:51 2011 New Revision: 134592 URL: http://llvm.org/viewvc/llvm-project?rev=134592&view=rev Log: Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The hasPredecessorHelper function allows predecessors to be cached to speed up repeated invocations. This fixes PR10186. X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X) Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with empty Visited and Worklist sets (i.e. no caching over invocations). Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited and Worklist to speed up repeated calls. The Visited set is searched for X before going to the worklist to further search the DAG if necessary. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=134592&r1=134591&r2=134592&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jul 6 23:31:51 2011 @@ -23,6 +23,7 @@ #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/ilist_node.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/ISDOpcodes.h" @@ -496,11 +497,29 @@ /// bool isOperandOf(SDNode *N) const; - /// isPredecessorOf - Return true if this node is a predecessor of N. This - /// node is either an operand of N or it can be reached by recursively + /// isPredecessorOf - Return true if this node is a predecessor of N. + /// NOTE: Implemented on top of hasPredecessor and every bit as + /// expensive. Use carefully. + bool isPredecessorOf(const SDNode *N) const { return N->hasPredecessor(this); } + + /// hasPredecessor - Return true if N is a predecessor of this node. + /// N is either an operand of this node, or can be reached by recursively + /// traversing up the operands. + /// NOTE: This is an expensive method. Use it carefully. + bool hasPredecessor(const SDNode *N) const; + + /// hasPredecesorHelper - Return true if N is a predecessor of this node. + /// N is either an operand of this node, or can be reached by recursively /// traversing up the operands. - /// NOTE: this is an expensive method. Use it carefully. - bool isPredecessorOf(SDNode *N) const; + /// In this helper the Visited and worklist sets are held externally to + /// cache predecessors over multiple invocations. If you want to test for + /// multiple predecessors this method is preferable to multiple calls to + /// hasPredecessor. Be sure to clear Visited and Worklist if the DAG + /// changes. + /// NOTE: This is still very expensive. Use carefully. + bool hasPredecessorHelper(const SDNode *N, + SmallPtrSet &Visited, + SmallVector &Worklist) const; /// getNumOperands - Return the number of values used by this operation. /// Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=134592&r1=134591&r2=134592&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jul 6 23:31:51 2011 @@ -5929,12 +5929,17 @@ // Now check for #3 and #4. bool RealUse = false; + + // Caches for hasPredecessorHelper + SmallPtrSet Visited; + SmallVector Worklist; + for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), E = Ptr.getNode()->use_end(); I != E; ++I) { SDNode *Use = *I; if (Use == N) continue; - if (Use->isPredecessorOf(N)) + if (N->hasPredecessorHelper(Use, Visited, Worklist)) return false; if (!((Use->getOpcode() == ISD::LOAD && Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=134592&r1=134591&r2=134592&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul 6 23:31:51 2011 @@ -5691,24 +5691,39 @@ return false; } -/// isPredecessorOf - Return true if this node is a predecessor of N. This node -/// is either an operand of N or it can be reached by traversing up the operands. -/// NOTE: this is an expensive method. Use it carefully. -bool SDNode::isPredecessorOf(SDNode *N) const { - SmallPtrSet Visited; - SmallVector Worklist; - Worklist.push_back(N); - - do { - N = Worklist.pop_back_val(); - for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - SDNode *Op = N->getOperand(i).getNode(); - if (Op == this) - return true; +/// hasPredecessor - Return true if N is a predecessor of this node. +/// N is either an operand of this node, or can be reached by recursively +/// traversing up the operands. +/// NOTE: This is an expensive method. Use it carefully. +bool SDNode::hasPredecessor(const SDNode *N) const { + SmallPtrSet Visited; + SmallVector Worklist; + return hasPredecessorHelper(N, Visited, Worklist); +} + +bool SDNode::hasPredecessorHelper(const SDNode *N, + SmallPtrSet &Visited, + SmallVector &Worklist) const { + if (Visited.empty()) { + Worklist.push_back(this); + } else { + // Take a look in the visited set. If we've already encountered this node + // we needn't search further. + if (Visited.count(N)) + return true; + } + + // Haven't visited N yet. Continue the search. + while (!Worklist.empty()) { + const SDNode *M = Worklist.pop_back_val(); + for (unsigned i = 0, e = M->getNumOperands(); i != e; ++i) { + SDNode *Op = M->getOperand(i).getNode(); if (Visited.insert(Op)) Worklist.push_back(Op); + if (Op == N) + return true; } - } while (!Worklist.empty()); + } return false; } From isanbard at gmail.com Wed Jul 6 23:40:55 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 6 Jul 2011 21:40:55 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> Message-ID: On Jul 6, 2011, at 6:59 PM, Chris Lattner wrote: > On Jul 6, 2011, at 5:54 PM, Bill Wendling wrote: > >> Author: void >> Date: Wed Jul 6 19:54:13 2011 >> New Revision: 134577 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134577&view=rev >> Log: >> Add a target hook to encode the compact unwind information. > > Ok. > >> +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Wed Jul 6 19:54:13 2011 >> @@ -14,6 +14,7 @@ >> #ifndef LLVM_TARGET_TARGETFRAMELOWERING_H >> #define LLVM_TARGET_TARGETFRAMELOWERING_H >> >> +#include "llvm/MC/MCDwarf.h" >> #include "llvm/CodeGen/MachineBasicBlock.h" > > Please forward declare MCCFIInstruction. > I can't. See below. >> @@ -189,6 +190,14 @@ >> /// >> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >> } >> + >> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >> + /// function. Return 0 if the compact unwind isn't available. >> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >> + int /*DataAlignmentFactor*/, >> + bool /*IsEH*/) const { > > Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? > Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: /usr/include/c++/4.2.1/bits/stl_vector.h:493:41: error: arithmetic on a pointer to an incomplete type 'llvm::MCCFIInstruction' { return *(this->_M_impl._M_start + __n); } ~~~~~~~~~~~~~~~~~~~~~~ ^ /Users/void/llvm/llvm.src/include/llvm/ADT/ArrayRef.h:65:37: note: in instantiation of member function 'std::vector >::operator[]' requested here : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} ^ /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function 'llvm::ArrayRef::ArrayRef' requested here return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); ^ /Users/void/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:25:9: note: forward declaration of 'llvm::MCCFIInstruction' class MCCFIInstruction; ^ Otherwise, done. -bw From isanbard at gmail.com Wed Jul 6 23:42:01 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 04:42:01 -0000 Subject: [llvm-commits] [llvm] r134595 - in /llvm/trunk: include/llvm/Target/TargetFrameLowering.h lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h Message-ID: <20110707044201.D0A1F2A6C12D@llvm.org> Author: void Date: Wed Jul 6 23:42:01 2011 New Revision: 134595 URL: http://llvm.org/viewvc/llvm-project?rev=134595&view=rev Log: Use ArrayRef instead of a std::vector&. Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.h Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameLowering.h?rev=134595&r1=134594&r2=134595&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetFrameLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Wed Jul 6 23:42:01 2011 @@ -14,8 +14,9 @@ #ifndef LLVM_TARGET_TARGETFRAMELOWERING_H #define LLVM_TARGET_TARGETFRAMELOWERING_H -#include "llvm/MC/MCDwarf.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/MC/MCDwarf.h" +#include "llvm/ADT/ArrayRef.h" #include #include @@ -193,9 +194,9 @@ /// getCompactUnwindEncoding - Get the compact unwind encoding for the /// function. Return 0 if the compact unwind isn't available. - virtual uint32_t getCompactUnwindEncoding(const std::vector&, - int /*DataAlignmentFactor*/, - bool /*IsEH*/) const { + virtual uint32_t getCompactUnwindEncoding(ArrayRef Instrs, + int DataAlignmentFactor, + bool IsEH) const { return 0; } }; Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=134595&r1=134594&r2=134595&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Jul 6 23:42:01 2011 @@ -1032,7 +1032,7 @@ } uint32_t X86FrameLowering:: -getCompactUnwindEncoding(const std::vector &Instrs, +getCompactUnwindEncoding(ArrayRef Instrs, int DataAlignmentFactor, bool IsEH) const { uint32_t Encoding = 0; int CFAOffset = 0; @@ -1040,7 +1040,7 @@ SmallVector SavedRegs; int FramePointerReg = -1; - for (std::vector::const_iterator + for (ArrayRef::const_iterator I = Instrs.begin(), E = Instrs.end(); I != E; ++I) { const MCCFIInstruction &Inst = *I; MCSymbol *Label = Inst.getLabel(); Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=134595&r1=134594&r2=134595&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Wed Jul 6 23:42:01 2011 @@ -60,7 +60,7 @@ void getInitialFrameState(std::vector &Moves) const; int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - uint32_t getCompactUnwindEncoding(const std::vector &Instrs, + uint32_t getCompactUnwindEncoding(ArrayRef Instrs, int DataAlignmentFactor, bool IsEH) const; }; From sabre at nondot.org Thu Jul 7 00:12:37 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 07 Jul 2011 05:12:37 -0000 Subject: [llvm-commits] [llvm] r134599 - /llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Message-ID: <20110707051237.3E7A82A6C12C@llvm.org> Author: lattner Date: Thu Jul 7 00:12:37 2011 New Revision: 134599 URL: http://llvm.org/viewvc/llvm-project?rev=134599&view=rev Log: use a more efficient check for 'is metadata' Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=134599&r1=134598&r2=134599&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Thu Jul 7 00:12:37 2011 @@ -44,9 +44,9 @@ /// number that holds the resolved value. typedef std::vector > ResolveConstantsTy; ResolveConstantsTy ResolveConstants; - LLVMContext& Context; + LLVMContext &Context; public: - BitcodeReaderValueList(LLVMContext& C) : Context(C) {} + BitcodeReaderValueList(LLVMContext &C) : Context(C) {} ~BitcodeReaderValueList() { assert(ResolveConstants.empty() && "Constants not resolved?"); } @@ -212,10 +212,9 @@ private: const Type *getTypeByID(unsigned ID, bool isTypeTable = false); Value *getFnValueByID(unsigned ID, const Type *Ty) { - if (Ty == Type::getMetadataTy(Context)) + if (Ty->isMetadataTy()) return MDValueList.getValueFwdRef(ID); - else - return ValueList.getValueFwdRef(ID, Ty); + return ValueList.getValueFwdRef(ID, Ty); } BasicBlock *getBasicBlock(unsigned ID) const { if (ID >= FunctionBBs.size()) return 0; // Invalid ID From sabre at nondot.org Thu Jul 7 00:29:18 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 07 Jul 2011 05:29:18 -0000 Subject: [llvm-commits] [llvm] r134601 - /llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Message-ID: <20110707052918.EBEB12A6C12C@llvm.org> Author: lattner Date: Thu Jul 7 00:29:18 2011 New Revision: 134601 URL: http://llvm.org/viewvc/llvm-project?rev=134601&view=rev Log: type can be null Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=134601&r1=134600&r2=134601&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Thu Jul 7 00:29:18 2011 @@ -212,7 +212,7 @@ private: const Type *getTypeByID(unsigned ID, bool isTypeTable = false); Value *getFnValueByID(unsigned ID, const Type *Ty) { - if (Ty->isMetadataTy()) + if (Ty && Ty->isMetadataTy()) return MDValueList.getValueFwdRef(ID); return ValueList.getValueFwdRef(ID, Ty); } From evan.cheng at apple.com Thu Jul 7 02:07:08 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 07:07:08 -0000 Subject: [llvm-commits] [llvm] r134606 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/MCTargetDesc/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20110707070709.4C2D62A6C12C@llvm.org> Author: evancheng Date: Thu Jul 7 02:07:08 2011 New Revision: 134606 URL: http://llvm.org/viewvc/llvm-project?rev=134606&view=rev Log: Compute feature bits at time of MCSubtargetInfo initialization. Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/MC/MCSubtargetInfo.cpp llvm/trunk/lib/MC/SubtargetFeature.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.h llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.h llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp llvm/trunk/lib/Target/Sparc/SparcSubtarget.h llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp llvm/trunk/lib/Target/XCore/XCoreSubtarget.h llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Thu Jul 7 02:07:08 2011 @@ -34,30 +34,29 @@ const unsigned *ForwardingPathes; // Forwarding pathes unsigned NumFeatures; // Number of processor features unsigned NumProcs; // Number of processors - + unsigned FeatureBits; // Feature bits for current CPU + public: - void InitMCSubtargetInfo(const SubtargetFeatureKV *PF, + void InitMCSubtargetInfo(StringRef CPU, StringRef FS, + const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *PI, const InstrStage *IS, const unsigned *OC, const unsigned *FP, - unsigned NF, unsigned NP) { - ProcFeatures = PF; - ProcDesc = PD; - ProcItins = PI; - Stages = IS; - OperandCycles = OC; - ForwardingPathes = FP; - NumFeatures = NF; - NumProcs = NP; + unsigned NF, unsigned NP); + + /// getFeatureBits - Get the feature bits. + /// + uint64_t getFeatureBits() const { + return FeatureBits; } + /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with + /// feature string), recompute and return feature bits. + uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS); + /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU. /// InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const; - - /// getFeatureBits - Get the feature bits for a CPU (optionally supplemented - /// with feature string). - uint64_t getFeatureBits(StringRef CPU, StringRef FS) const; }; } // End llvm namespace Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 02:07:08 2011 @@ -70,7 +70,9 @@ StringRef TT); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(void); + typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, + StringRef CPU, + StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, const std::string &CPU, @@ -269,10 +271,18 @@ /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// - MCSubtargetInfo *createMCSubtargetInfo() const { + /// \arg Triple - This argument is used to determine the target machine + /// feature set; it should always be provided. Generally this should be + /// either the target triple from the module, or the target triple of the + /// host if that does not exist. + /// \arg CPU - This specifies the name of the target CPU. + /// \arg Features - This specifies the string representation of the + /// additional target features. + MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, + StringRef Features) const { if (!MCSubtargetInfoCtorFn) return 0; - return MCSubtargetInfoCtorFn(); + return MCSubtargetInfoCtorFn(Triple, CPU, Features); } /// createTargetMachine - Create a target specific machine implementation @@ -824,7 +834,8 @@ TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); } private: - static MCSubtargetInfo *Allocator() { + static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, + StringRef FS) { return new MCSubtargetInfoImpl(); } }; Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original) +++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Thu Jul 7 02:07:08 2011 @@ -16,6 +16,38 @@ using namespace llvm; +void MCSubtargetInfo::InitMCSubtargetInfo(StringRef CPU, StringRef FS, + const SubtargetFeatureKV *PF, + const SubtargetFeatureKV *PD, + const SubtargetInfoKV *PI, + const InstrStage *IS, + const unsigned *OC, + const unsigned *FP, + unsigned NF, unsigned NP) { + ProcFeatures = PF; + ProcDesc = PD; + ProcItins = PI; + Stages = IS; + OperandCycles = OC; + ForwardingPathes = FP; + NumFeatures = NF; + NumProcs = NP; + + SubtargetFeatures Features(FS); + FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, + ProcFeatures, NumFeatures); +} + + +/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with +/// feature string) and recompute feature bits. +uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { + SubtargetFeatures Features(FS); + FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, + ProcFeatures, NumFeatures); + return FeatureBits; +} + InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { assert(ProcItins && "Instruction itineraries information not available!"); @@ -42,11 +74,3 @@ return InstrItineraryData(Stages, OperandCycles, ForwardingPathes, (InstrItinerary *)Found->Value); } - -/// getFeatureBits - Get the feature bits for a CPU (optionally supplemented -/// with feature string). -uint64_t MCSubtargetInfo::getFeatureBits(StringRef CPU, StringRef FS) const { - SubtargetFeatures Features(FS); - return Features.getFeatureBits(CPU, ProcDesc, NumProcs, - ProcFeatures, NumFeatures); -} Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jul 7 02:07:08 2011 @@ -231,8 +231,9 @@ size_t CPUTableSize, const SubtargetFeatureKV *FeatureTable, size_t FeatureTableSize) { - assert(CPUTable && "missing CPU table"); - assert(FeatureTable && "missing features table"); + if (!FeatureTableSize || !CPUTableSize) + return 0; + #ifndef NDEBUG for (size_t i = 1; i < CPUTableSize; i++) { assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 && @@ -249,24 +250,27 @@ if (CPU == "help") Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize); - // Find CPU entry - const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize); - // If there is a match - if (CPUEntry) { - // Set base feature bits - Bits = CPUEntry->Value; - - // Set the feature implied by this CPU feature, if any. - for (size_t i = 0; i < FeatureTableSize; ++i) { - const SubtargetFeatureKV &FE = FeatureTable[i]; - if (CPUEntry->Value & FE.Value) - SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); + // Find CPU entry if CPU name is specified. + if (!CPU.empty()) { + const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize); + // If there is a match + if (CPUEntry) { + // Set base feature bits + Bits = CPUEntry->Value; + + // Set the feature implied by this CPU feature, if any. + for (size_t i = 0; i < FeatureTableSize; ++i) { + const SubtargetFeatureKV &FE = FeatureTable[i]; + if (CPUEntry->Value & FE.Value) + SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); + } + } else { + errs() << "'" << CPU + << "' is not a recognized processor for this target" + << " (ignoring processor)\n"; } - } else { - errs() << "'" << CPU - << "' is not a recognized processor for this target" - << " (ignoring processor)\n"; } + // Iterate through each feature for (size_t i = 0, E = Features.size(); i < E; i++) { const StringRef Feature = Features[i]; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -38,7 +38,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) - : ARMGenSubtargetInfo() + : ARMGenSubtargetInfo(TT, CPU, FS) , ARMProcFamily(Others) , HasV4TOps(false) , HasV5TOps(false) @@ -78,9 +78,6 @@ if (CPUString.empty()) CPUString = "generic"; - if (TT.find("eabi") != std::string::npos) - TargetABI = ARM_ABI_AAPCS; - // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. @@ -92,7 +89,7 @@ ArchFS = FS; } - ParseSubtargetFeatures(ArchFS, CPUString); + ParseSubtargetFeatures(CPUString, ArchFS); // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a // ARM version or CPU and then remove this. @@ -105,6 +102,9 @@ // After parsing Itineraries, set ItinData.IssueWidth. computeIssueWidth(); + if (TT.find("eabi") != std::string::npos) + TargetABI = ARM_ABI_AAPCS; + if (isAAPCS_ABI()) stackAlignment = 8; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jul 7 02:07:08 2011 @@ -25,6 +25,7 @@ namespace llvm { class GlobalValue; +class StringRef; class ARMSubtarget : public ARMGenSubtargetInfo { protected: @@ -168,7 +169,7 @@ } /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void computeIssueWidth(); Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 02:07:08 2011 @@ -40,9 +40,10 @@ return X; } -MCSubtargetInfo *createARMMCSubtargetInfo() { +MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitARMMCSubtargetInfo(X); + InitARMMCSubtargetInfo(X, CPU, FS); return X; } Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -23,13 +23,13 @@ AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) - : AlphaGenSubtargetInfo(), HasCT(false) { + : AlphaGenSubtargetInfo(TT, CPU, FS), HasCT(false) { std::string CPUName = CPU; if (CPUName.empty()) CPUName = "generic"; // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ #include "AlphaGenSubtargetInfo.inc" namespace llvm { +class StringRe; class AlphaSubtarget : public AlphaGenSubtargetInfo { protected: @@ -39,7 +40,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); bool hasCT() const { return HasCT; } }; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -23,7 +23,7 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) - : BlackfinGenSubtargetInfo(), sdram(false), + : BlackfinGenSubtargetInfo(TT, CPU, FS), sdram(false), icplb(false), wa_mi_shift(false), wa_csync(false), @@ -39,5 +39,5 @@ if (CPUName.empty()) CPUName = "generic"; // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h Thu Jul 7 02:07:08 2011 @@ -21,6 +21,7 @@ #include "BlackfinGenSubtargetInfo.inc" namespace llvm { +class StringRef; class BlackfinSubtarget : public BlackfinGenSubtargetInfo { bool sdram; @@ -40,8 +41,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -25,7 +25,7 @@ SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : - SPUGenSubtargetInfo(), + SPUGenSubtargetInfo(TT, CPU, FS), StackAlignment(16), ProcDirective(SPU::DEFAULT_PROC), UseLargeMem(false) @@ -35,7 +35,7 @@ std::string default_cpu("v0"); // Parse features string. - ParseSubtargetFeatures(FS, default_cpu); + ParseSubtargetFeatures(default_cpu, FS); // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(default_cpu); Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Thu Jul 7 02:07:08 2011 @@ -23,6 +23,7 @@ namespace llvm { class GlobalValue; + class StringRef; namespace SPU { enum { @@ -57,7 +58,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// SetJITMode - This is called to inform the subtarget info that we are /// producing code for the JIT. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -26,7 +26,7 @@ MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS): - MBlazeGenSubtargetInfo(), + MBlazeGenSubtargetInfo(TT, CPU, FS), HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false), HasFPU(false), HasMul64(false), HasSqrt(false) { @@ -34,7 +34,7 @@ std::string CPUName = CPU; if (CPUName.empty()) CPUName = "mblaze"; - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); // Only use instruction scheduling if the selected CPU has an instruction // itinerary (the default CPU is the only one that doesn't). Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ #include "MBlazeGenSubtargetInfo.inc" namespace llvm { +class StringRef; class MBlazeSubtarget : public MBlazeGenSubtargetInfo { @@ -46,7 +47,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// Compute the number of maximum number of issues per cycle for the /// MBlaze scheduling itineraries. Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 02:07:08 2011 @@ -22,10 +22,11 @@ using namespace llvm; MSP430Subtarget::MSP430Subtarget(const std::string &TT, - const std::string &CPUIgnored, - const std::string &FS) { - std::string CPU = "generic"; + const std::string &CPU, + const std::string &FS) : + MSP430GenSubtargetInfo(TT, CPU, FS) { + std::string CPUName = "generic"; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(CPUName, FS); } Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ #include namespace llvm { +class StringRef; class MSP430Subtarget : public MSP430GenSubtargetInfo { bool ExtendedInsts; @@ -34,7 +35,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -23,7 +23,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little) : - MipsGenSubtargetInfo(), + MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false), @@ -35,7 +35,7 @@ MipsArchVersion = Mips1; // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ #include "MipsGenSubtargetInfo.inc" namespace llvm { +class StringRef; class MipsSubtarget : public MipsGenSubtargetInfo { @@ -99,7 +100,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); bool isMips1() const { return MipsArchVersion == Mips1; } bool isMips32() const { return MipsArchVersion >= Mips32; } Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -23,7 +23,7 @@ PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : PTXGenSubtargetInfo(), + : PTXGenSubtargetInfo(TT, CPU, FS), PTXTarget(PTX_COMPUTE_1_0), PTXVersion(PTX_VERSION_2_0), SupportsDouble(false), @@ -32,7 +32,7 @@ std::string TARGET = CPU; if (TARGET.empty()) TARGET = "generic"; - ParseSubtargetFeatures(FS, TARGET); + ParseSubtargetFeatures(TARGET, FS); } std::string PTXSubtarget::getTargetString() const { Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Thu Jul 7 02:07:08 2011 @@ -20,6 +20,8 @@ #include "PTXGenSubtargetInfo.inc" namespace llvm { +class StringRef; + class PTXSubtarget : public PTXGenSubtargetInfo { public: @@ -112,8 +114,7 @@ (PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE); } - void ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); }; // class PTXSubtarget } // namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -64,7 +64,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : PPCGenSubtargetInfo() + : PPCGenSubtargetInfo(TT, CPU, FS) , StackAlignment(16) , DarwinDirective(PPC::DIR_NONE) , IsGigaProcessor(false) @@ -88,7 +88,7 @@ #endif // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Thu Jul 7 02:07:08 2011 @@ -26,6 +26,7 @@ #undef PPC namespace llvm { +class StringRef; namespace PPC { // -m directive values. @@ -80,8 +81,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); - + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// SetJITMode - This is called to inform the subtarget info that we are /// producing code for the JIT. Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -22,7 +22,7 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) : - SparcGenSubtargetInfo(), + SparcGenSubtargetInfo(TT, CPU, FS), IsV9(false), V8DeprecatedInsts(false), IsVIS(false), @@ -39,5 +39,5 @@ IsV9 = CPUName == "v9"; // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); } Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Thu Jul 7 02:07:08 2011 @@ -21,6 +21,7 @@ #include "SparcGenSubtargetInfo.inc" namespace llvm { +class StringRef; class SparcSubtarget : public SparcGenSubtargetInfo { bool IsV9; @@ -38,7 +39,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); bool is64Bit() const { return Is64Bit; } std::string getDataLayout() const { Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -26,13 +26,13 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS): - SystemZGenSubtargetInfo(), HasZ10Insts(false) { + SystemZGenSubtargetInfo(TT, CPU, FS), HasZ10Insts(false) { std::string CPUName = CPU; if (CPUName.empty()) CPUName = "z9"; // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); } /// True if accessing the GV requires an extra load. Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ namespace llvm { class GlobalValue; +class StringRef; class TargetMachine; class SystemZSubtarget : public SystemZGenSubtargetInfo { @@ -35,7 +36,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); bool isZ10() const { return HasZ10Insts; } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 02:07:08 2011 @@ -40,9 +40,10 @@ return X; } -MCSubtargetInfo *createX86MCSubtargetInfo() { +MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X); + InitX86MCSubtargetInfo(X, CPU, FS); return X; } Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 02:07:08 2011 @@ -292,7 +292,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit, unsigned StackAlignOverride) - : X86GenSubtargetInfo() + : X86GenSubtargetInfo(TT, CPU, FS) , PICStyle(PICStyles::None) , X86SSELevel(NoMMXSSE) , X863DNowLevel(NoThreeDNow) @@ -320,7 +320,7 @@ std::string CPUName = CPU; if (CPUName.empty()) CPUName = sys::getHostCPUName(); - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); // All X86-64 CPUs also have SSE2, however user might request no SSE via // -mattr, so don't force SSELevel here. if (HasAVX) Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Jul 7 02:07:08 2011 @@ -24,6 +24,7 @@ namespace llvm { class GlobalValue; +class StringRef; class TargetMachine; /// PICStyles - The X86 backend supports a number of different styles of PIC. @@ -135,7 +136,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID /// instruction. Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 02:07:08 2011 @@ -23,6 +23,6 @@ XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) - : XCoreGenSubtargetInfo() + : XCoreGenSubtargetInfo(TT, CPU, FS) { } Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.h?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h Thu Jul 7 02:07:08 2011 @@ -22,6 +22,7 @@ #include "XCoreGenSubtargetInfo.inc" namespace llvm { +class StringRef; class XCoreSubtarget : public XCoreGenSubtargetInfo { @@ -34,7 +35,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); }; } // End llvm namespace Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134606&r1=134605&r2=134606&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 02:07:08 2011 @@ -605,8 +605,7 @@ << "// subtarget options.\n" << "void llvm::"; OS << Target; - OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" - << " const std::string &CPU) {\n" + OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n" << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"; @@ -615,11 +614,7 @@ return; } - OS << " SubtargetFeatures Features(FS);\n" - << " uint64_t Bits = Features.getFeatureBits(CPU, " - << Target << "SubTypeKV, " << NumProcs << ",\n" - << " " << Target << "FeatureKV, " - << NumFeatures << ");\n"; + OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n"; for (unsigned i = 0; i < Features.size(); i++) { // Next record @@ -629,10 +624,12 @@ const std::string &Attribute = R->getValueAsString("Attribute"); if (Value=="true" || Value=="false") - OS << " if ((Bits & " << Target << "::" << Instance << ") != 0) " + OS << " if ((Bits & " << Target << "::" + << Instance << ") != 0) " << Attribute << " = " << Value << ";\n"; else - OS << " if ((Bits & " << Target << "::" << Instance << ") != 0 && " + OS << " if ((Bits & " << Target << "::" + << Instance << ") != 0 && " << Attribute << " < " << Value << ") " << Attribute << " = " << Value << ";\n"; } @@ -663,8 +660,8 @@ // MCInstrInfo initialization routine. OS << "static inline void Init" << Target - << "MCSubtargetInfo(MCSubtargetInfo *II) {\n"; - OS << " II->InitMCSubtargetInfo("; + << "MCSubtargetInfo(MCSubtargetInfo *II, StringRef CPU, StringRef FS) {\n"; + OS << " II->InitMCSubtargetInfo(CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; else @@ -702,7 +699,8 @@ std::string ClassName = Target + "GenSubtargetInfo"; OS << "namespace llvm {\n"; OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" - << " explicit " << ClassName << "();\n" + << " explicit " << ClassName << "(StringRef TT, StringRef CPU, " + << "StringRef FS);\n" << "};\n"; OS << "} // End llvm namespace \n"; @@ -712,9 +710,10 @@ OS << "#undef GET_SUBTARGETINFO_CTOR\n"; OS << "namespace llvm {\n"; - OS << ClassName << "::" << ClassName << "()\n" + OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " + << "StringRef FS)\n" << " : TargetSubtargetInfo() {\n" - << " InitMCSubtargetInfo("; + << " InitMCSubtargetInfo(CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; else From evan.cheng at apple.com Thu Jul 7 02:45:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 07:45:49 -0000 Subject: [llvm-commits] [llvm] r134607 - /llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Message-ID: <20110707074550.017842A6C12D@llvm.org> Author: evancheng Date: Thu Jul 7 02:45:49 2011 New Revision: 134607 URL: http://llvm.org/viewvc/llvm-project?rev=134607&view=rev Log: Feature bits are 64-bits. Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=134607&r1=134606&r2=134607&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Thu Jul 7 02:45:49 2011 @@ -34,7 +34,7 @@ const unsigned *ForwardingPathes; // Forwarding pathes unsigned NumFeatures; // Number of processor features unsigned NumProcs; // Number of processors - unsigned FeatureBits; // Feature bits for current CPU + uint64_t FeatureBits; // Feature bits for current CPU public: void InitMCSubtargetInfo(StringRef CPU, StringRef FS, From evan.cheng at apple.com Thu Jul 7 03:26:46 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 08:26:46 -0000 Subject: [llvm-commits] [llvm] r134608 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h Message-ID: <20110707082646.C2ECE2A6C12D@llvm.org> Author: evancheng Date: Thu Jul 7 03:26:46 2011 New Revision: 134608 URL: http://llvm.org/viewvc/llvm-project?rev=134608&view=rev Log: Sink feature IsThumb into MC layer. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134608&r1=134607&r2=134608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jul 7 03:26:46 2011 @@ -16,6 +16,12 @@ include "llvm/Target/Target.td" +//===----------------------------------------------------------------------===// +// ARM Subtarget state. +// + +def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true", + "Thumb mode">; //===----------------------------------------------------------------------===// // ARM Subtarget features. @@ -85,23 +91,23 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; -// ARM architectures. +// ARM ISAs. def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", - "ARM v4T">; + "Support ARM v4T instructions">; def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", - "ARM v5T", + "Support ARM v5T instructions", [HasV4TOps]>; def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", - "ARM v5TE, v5TEj, v5TExp", + "Support ARM v5TE, v5TEj, and v5TExp instructions", [HasV5TOps]>; def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", - "ARM v6", + "Support ARM v6 instructions", [HasV5TEOps]>; def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", - "ARM v6t2", + "Support ARM v6t2 instructions", [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>; def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", - "ARM v7", + "Support ARM v7 instructions", [HasV6T2Ops]>; //===----------------------------------------------------------------------===// @@ -111,8 +117,6 @@ include "ARMSchedule.td" // ARM processor families. -def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others", - "One of the other ARM processor families">; def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", "Cortex-A8 ARM processors", [FeatureSlowFPBrcc, FeatureNEONForFP, Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134608&r1=134607&r2=134608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 03:26:46 2011 @@ -81,14 +81,13 @@ // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); + std::string ArchFS = ARM_MC::ParseARMTriple(TT); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = ArchFS + "," + FS; else ArchFS = FS; } - ParseSubtargetFeatures(CPUString, ArchFS); // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134608&r1=134607&r2=134608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 03:26:46 2011 @@ -42,8 +42,16 @@ MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { + std::string ArchFS = ARM_MC::ParseARMTriple(TT); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS.str(); + else + ArchFS = FS; + } + MCSubtargetInfo *X = new MCSubtargetInfo(); - InitARMMCSubtargetInfo(X, CPU, FS); + InitARMMCSubtargetInfo(X, CPU, ArchFS); return X; } @@ -74,16 +82,17 @@ createARMMCSubtargetInfo); } -std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { +std::string ARM_MC::ParseARMTriple(StringRef TT) { // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. unsigned Len = TT.size(); unsigned Idx = 0; + bool isThumb = false; if (Len >= 5 && TT.substr(0, 4) == "armv") Idx = 4; else if (Len >= 6 && TT.substr(0, 5) == "thumb") { - IsThumb = true; + isThumb = true; if (Len >= 7 && TT[5] == 'v') Idx = 6; } @@ -116,5 +125,12 @@ ARMArchFeature = "+v4t"; } + if (isThumb) { + if (ARMArchFeature.empty()) + ARMArchFeature = "+thumb"; + else + ARMArchFeature += ",+thumb"; + } + return ARMArchFeature; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134608&r1=134607&r2=134608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 03:26:46 2011 @@ -23,7 +23,7 @@ extern Target TheARMTarget, TheThumbTarget; namespace ARM_MC { - std::string ParseARMTriple(StringRef TT, bool &IsThumb); + std::string ParseARMTriple(StringRef TT); } } // End llvm namespace From zwarich at apple.com Thu Jul 7 03:28:53 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 07 Jul 2011 08:28:53 -0000 Subject: [llvm-commits] [llvm] r134609 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMInstrVFP.td Message-ID: <20110707082853.36D742A6C12C@llvm.org> Author: zwarich Date: Thu Jul 7 03:28:52 2011 New Revision: 134609 URL: http://llvm.org/viewvc/llvm-project?rev=134609&view=rev Log: The VMLA instruction and its friends are not actually fused; they're plain old multiply-accumulate instructions with separate rounding steps. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134609&r1=134608&r2=134609&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jul 7 03:28:52 2011 @@ -654,7 +654,7 @@ } /* TODO: ARMBuildAttrs::Allowed is not completely accurate, - * since NEON can have 1 (allowed) or 2 (fused MAC operations) */ + * since NEON can have 1 (allowed) or 2 (MAC operations) */ if (Subtarget->hasNEON()) { AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch, ARMBuildAttrs::Allowed); Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=134609&r1=134608&r2=134609&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Jul 7 03:28:52 2011 @@ -873,7 +873,7 @@ } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in' //===----------------------------------------------------------------------===// -// FP FMA Operations. +// FP Multiply-Accumulate Operations. // def VMLAD : ADbI<0b11100, 0b00, 0, 0, From lhames at gmail.com Thu Jul 7 04:19:56 2011 From: lhames at gmail.com (Lang Hames) Date: Thu, 7 Jul 2011 19:19:56 +1000 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics Message-ID: Enhance GVN to look though extractvalues for recognized intrinsics. This is a first step towards fixing http://llvm.org/bugs/show_bug.cgi?id=8817 . Could someone more familiar with GVN review this and let me know whether it's reasonable to commit? Thanks! - Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/6b99c202/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: PR8817.patch Type: text/x-patch Size: 5225 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/6b99c202/attachment.bin From james.molloy at arm.com Thu Jul 7 06:18:17 2011 From: james.molloy at arm.com (James Molloy) Date: Thu, 7 Jul 2011 12:18:17 +0100 Subject: [llvm-commits] [llvm] r134608 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h In-Reply-To: <20110707082646.C2ECE2A6C12D@llvm.org> References: <20110707082646.C2ECE2A6C12D@llvm.org> Message-ID: <000701cc3c97$92564f80$b702ee80$@molloy@arm.com> Hi Evan, This (or one of the very closely committed diffs) has broken ARM builds. For some reason the buildbot passed, but our internal builds (and a manual checkout just to be sure) all fail with a link error: Linking CXX executable ../../bin/llc ../../lib/libLLVMARMCodeGen.a(ARMSubtarget.cpp.o): In function `llvm::ARMSubtarget::ARMSubtarget(std::basic_string, std::allocator > const&, std::basic_string, std::allocator > const&, std::basic_string, std::allocator > const&)': ARMSubtarget.cpp:(.text+0x82c): undefined reference to `llvm::ARM_MC::ParseARMTriple(llvm::StringRef)' ../../lib/libLLVMARMCodeGen.a(ARMSubtarget.cpp.o): In function `llvm::ARMSubtarget::ARMSubtarget(std::basic_string, std::allocator > const&, std::basic_string, std::allocator > const&, std::basic_string, std::allocator > const&)': ARMSubtarget.cpp:(.text+0xf10): undefined reference to `llvm::ARM_MC::ParseARMTriple(llvm::StringRef)' collect2: ld returned 1 exit status Cheers, James > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Evan Cheng > Sent: 07 July 2011 09:27 > To: llvm-commits at cs.uiuc.edu > Subject: [llvm-commits] [llvm] r134608 - in /llvm/trunk/lib/Target/ARM: > ARM.td ARMSubtarget.cpp MCTargetDesc/ARMMCTargetDesc.cpp > MCTargetDesc/ARMMCTargetDesc.h > > Author: evancheng > Date: Thu Jul 7 03:26:46 2011 > New Revision: 134608 > > URL: http://llvm.org/viewvc/llvm-project?rev=134608&view=rev > Log: > Sink feature IsThumb into MC layer. > > Modified: > llvm/trunk/lib/Target/ARM/ARM.td > llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > > Modified: llvm/trunk/lib/Target/ARM/ARM.td > URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134608&r1=134607&r2=134608 > &view=diff > ======================================================================= > ======= > --- llvm/trunk/lib/Target/ARM/ARM.td (original) > +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jul 7 03:26:46 2011 > @@ -16,6 +16,12 @@ > > include "llvm/Target/Target.td" > > +//===----------------------------------------------------------------- > -----===// > +// ARM Subtarget state. > +// > + > +def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true", > + "Thumb mode">; > > //===----------------------------------------------------------------- > -----===// > // ARM Subtarget features. > @@ -85,23 +91,23 @@ > def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", > "Supports Multiprocessing > extension">; > > -// ARM architectures. > +// ARM ISAs. > def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", > - "ARM v4T">; > + "Support ARM v4T instructions">; > def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", > - "ARM v5T", > + "Support ARM v5T instructions", > [HasV4TOps]>; > def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", > - "ARM v5TE, v5TEj, v5TExp", > + "Support ARM v5TE, v5TEj, and v5TExp > instructions", > [HasV5TOps]>; > def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", > - "ARM v6", > + "Support ARM v6 instructions", > [HasV5TEOps]>; > def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", > - "ARM v6t2", > + "Support ARM v6t2 instructions", > [HasV6Ops, FeatureThumb2, > FeatureDSPThumb2]>; > def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", > - "ARM v7", > + "Support ARM v7 instructions", > [HasV6T2Ops]>; > > //===----------------------------------------------------------------- > -----===// > @@ -111,8 +117,6 @@ > include "ARMSchedule.td" > > // ARM processor families. > -def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", > "Others", > - "One of the other ARM processor > families">; > def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", > "Cortex-A8 ARM processors", > [FeatureSlowFPBrcc, > FeatureNEONForFP, > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134608&r1=134607 > &r2=134608&view=diff > ======================================================================= > ======= > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 03:26:46 2011 > @@ -81,14 +81,13 @@ > // Insert the architecture feature derived from the target triple > into the > // feature string. This is important for setting features that are > implied > // based on the architecture version. > - std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); > + std::string ArchFS = ARM_MC::ParseARMTriple(TT); > if (!FS.empty()) { > if (!ArchFS.empty()) > ArchFS = ArchFS + "," + FS; > else > ArchFS = FS; > } > - > ParseSubtargetFeatures(CPUString, ArchFS); > > // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly > specify a > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev= > 134608&r1=134607&r2=134608&view=diff > ======================================================================= > ======= > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul > 7 03:26:46 2011 > @@ -42,8 +42,16 @@ > > MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > StringRef FS) { > + std::string ArchFS = ARM_MC::ParseARMTriple(TT); > + if (!FS.empty()) { > + if (!ArchFS.empty()) > + ArchFS = ArchFS + "," + FS.str(); > + else > + ArchFS = FS; > + } > + > MCSubtargetInfo *X = new MCSubtargetInfo(); > - InitARMMCSubtargetInfo(X, CPU, FS); > + InitARMMCSubtargetInfo(X, CPU, ArchFS); > return X; > } > > @@ -74,16 +82,17 @@ > createARMMCSubtargetInfo); > } > > -std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { > +std::string ARM_MC::ParseARMTriple(StringRef TT) { > // Set the boolean corresponding to the current target triple, or > the default > // if one cannot be determined, to true. > unsigned Len = TT.size(); > unsigned Idx = 0; > > + bool isThumb = false; > if (Len >= 5 && TT.substr(0, 4) == "armv") > Idx = 4; > else if (Len >= 6 && TT.substr(0, 5) == "thumb") { > - IsThumb = true; > + isThumb = true; > if (Len >= 7 && TT[5] == 'v') > Idx = 6; > } > @@ -116,5 +125,12 @@ > ARMArchFeature = "+v4t"; > } > > + if (isThumb) { > + if (ARMArchFeature.empty()) > + ARMArchFeature = "+thumb"; > + else > + ARMArchFeature += ",+thumb"; > + } > + > return ARMArchFeature; > } > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=13 > 4608&r1=134607&r2=134608&view=diff > ======================================================================= > ======= > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 > 03:26:46 2011 > @@ -23,7 +23,7 @@ > extern Target TheARMTarget, TheThumbTarget; > > namespace ARM_MC { > - std::string ParseARMTriple(StringRef TT, bool &IsThumb); > + std::string ParseARMTriple(StringRef TT); > } > > } // End llvm namespace > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From fvbommel at gmail.com Thu Jul 7 10:10:17 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 7 Jul 2011 17:10:17 +0200 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics In-Reply-To: References: Message-ID: On 7 July 2011 11:19, Lang Hames wrote: > Enhance GVN to look though extractvalues for recognized intrinsics. This is > a first step towards fixing?http://llvm.org/bugs/show_bug.cgi?id=8817?. > Could someone more familiar with GVN review this and let me know whether > it's reasonable to commit? I'm not familiar with GVN internals, but I'm wondering why you're only handling the unsigned overflow variants? From dgregor at apple.com Thu Jul 7 10:59:22 2011 From: dgregor at apple.com (Douglas Gregor) Date: Thu, 07 Jul 2011 15:59:22 -0000 Subject: [llvm-commits] [llvm] r134614 - /llvm/trunk/lib/Target/ARM/CMakeLists.txt Message-ID: <20110707155922.AA3D02A6C12C@llvm.org> Author: dgregor Date: Thu Jul 7 10:59:22 2011 New Revision: 134614 URL: http://llvm.org/viewvc/llvm-project?rev=134614&view=rev Log: Fix CMake build Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134614&r1=134613&r2=134614&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Jul 7 10:59:22 2011 @@ -66,3 +66,5 @@ add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) + +target_link_libraries(LLVMARMCodeGen LLVMARMDesc) From clattner at apple.com Thu Jul 7 11:20:00 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 07 Jul 2011 09:20:00 -0700 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics In-Reply-To: References: Message-ID: <479C8C82-F5D6-4EAE-BF6E-D48FBAFBCAB3@apple.com> On Jul 7, 2011, at 2:19 AM, Lang Hames wrote: > Enhance GVN to look though extractvalues for recognized intrinsics. This is a first step towards fixing http://llvm.org/bugs/show_bug.cgi?id=8817 . > > Could someone more familiar with GVN review this and let me know whether it's reasonable to commit? Hi Lang, I think that Owen is the best one to handle this. In addition to handling the signed versions of these as well, does this correctly handle the case when the subtract comes first, and the cases when the overflow bit is actually used? In principle, we'd want to optimize: a = add i32 y, z ... b,c = addo(y,z) into: b,c = addo(y,z) a = b ... Unfortunately, I'm not familiar enough with the GVN value table stuff to check the details of the patch, thanks for working on this though! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/407ff059/attachment.html From evan.cheng at apple.com Thu Jul 7 11:22:35 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 09:22:35 -0700 Subject: [llvm-commits] [llvm] r134608 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h In-Reply-To: <000701cc3c97$92564f80$b702ee80$%molloy@arm.com> References: <20110707082646.C2ECE2A6C12D@llvm.org> <000701cc3c97$92564f80$b702ee80$%molloy@arm.com> Message-ID: <795D5E81-F4AC-4378-AB41-FCAB4EF4D6EF@apple.com> Doug's 134614 should have fixed this. Sorry about the breakage. Evan On Jul 7, 2011, at 4:18 AM, James Molloy wrote: > Hi Evan, > > This (or one of the very closely committed diffs) has broken ARM builds. For > some reason the buildbot passed, but our internal builds (and a manual > checkout just to be sure) all fail with a link error: > > Linking CXX executable ../../bin/llc > ../../lib/libLLVMARMCodeGen.a(ARMSubtarget.cpp.o): In function > `llvm::ARMSubtarget::ARMSubtarget(std::basic_string std::char_traits, std::allocator > const&, > std::basic_string, std::allocator > > const&, std::basic_string, std::allocator >> const&)': > ARMSubtarget.cpp:(.text+0x82c): undefined reference to > `llvm::ARM_MC::ParseARMTriple(llvm::StringRef)' > ../../lib/libLLVMARMCodeGen.a(ARMSubtarget.cpp.o): In function > `llvm::ARMSubtarget::ARMSubtarget(std::basic_string std::char_traits, std::allocator > const&, > std::basic_string, std::allocator > > const&, std::basic_string, std::allocator >> const&)': > ARMSubtarget.cpp:(.text+0xf10): undefined reference to > `llvm::ARM_MC::ParseARMTriple(llvm::StringRef)' > collect2: ld returned 1 exit status > > Cheers, > > James > >> -----Original Message----- >> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- >> bounces at cs.uiuc.edu] On Behalf Of Evan Cheng >> Sent: 07 July 2011 09:27 >> To: llvm-commits at cs.uiuc.edu >> Subject: [llvm-commits] [llvm] r134608 - in /llvm/trunk/lib/Target/ARM: >> ARM.td ARMSubtarget.cpp MCTargetDesc/ARMMCTargetDesc.cpp >> MCTargetDesc/ARMMCTargetDesc.h >> >> Author: evancheng >> Date: Thu Jul 7 03:26:46 2011 >> New Revision: 134608 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134608&view=rev >> Log: >> Sink feature IsThumb into MC layer. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARM.td >> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> >> Modified: llvm/trunk/lib/Target/ARM/ARM.td >> URL: http://llvm.org/viewvc/llvm- >> project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134608&r1=134607&r2=134608 >> &view=diff >> ======================================================================= >> ======= >> --- llvm/trunk/lib/Target/ARM/ARM.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jul 7 03:26:46 2011 >> @@ -16,6 +16,12 @@ >> >> include "llvm/Target/Target.td" >> >> +//===----------------------------------------------------------------- >> -----===// >> +// ARM Subtarget state. >> +// >> + >> +def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true", >> + "Thumb mode">; >> >> //===----------------------------------------------------------------- >> -----===// >> // ARM Subtarget features. >> @@ -85,23 +91,23 @@ >> def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", >> "Supports Multiprocessing >> extension">; >> >> -// ARM architectures. >> +// ARM ISAs. >> def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", >> - "ARM v4T">; >> + "Support ARM v4T instructions">; >> def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", >> - "ARM v5T", >> + "Support ARM v5T instructions", >> [HasV4TOps]>; >> def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", >> - "ARM v5TE, v5TEj, v5TExp", >> + "Support ARM v5TE, v5TEj, and v5TExp >> instructions", >> [HasV5TOps]>; >> def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", >> - "ARM v6", >> + "Support ARM v6 instructions", >> [HasV5TEOps]>; >> def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", >> - "ARM v6t2", >> + "Support ARM v6t2 instructions", >> [HasV6Ops, FeatureThumb2, >> FeatureDSPThumb2]>; >> def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", >> - "ARM v7", >> + "Support ARM v7 instructions", >> [HasV6T2Ops]>; >> >> //===----------------------------------------------------------------- >> -----===// >> @@ -111,8 +117,6 @@ >> include "ARMSchedule.td" >> >> // ARM processor families. >> -def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", >> "Others", >> - "One of the other ARM processor >> families">; >> def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", >> "Cortex-A8 ARM processors", >> [FeatureSlowFPBrcc, >> FeatureNEONForFP, >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> URL: http://llvm.org/viewvc/llvm- >> project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134608&r1=134607 >> &r2=134608&view=diff >> ======================================================================= >> ======= >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 03:26:46 2011 >> @@ -81,14 +81,13 @@ >> // Insert the architecture feature derived from the target triple >> into the >> // feature string. This is important for setting features that are >> implied >> // based on the architecture version. >> - std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb); >> + std::string ArchFS = ARM_MC::ParseARMTriple(TT); >> if (!FS.empty()) { >> if (!ArchFS.empty()) >> ArchFS = ArchFS + "," + FS; >> else >> ArchFS = FS; >> } >> - >> ParseSubtargetFeatures(CPUString, ArchFS); >> >> // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly >> specify a >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> URL: http://llvm.org/viewvc/llvm- >> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev= >> 134608&r1=134607&r2=134608&view=diff >> ======================================================================= >> ======= >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul >> 7 03:26:46 2011 >> @@ -42,8 +42,16 @@ >> >> MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, >> StringRef FS) { >> + std::string ArchFS = ARM_MC::ParseARMTriple(TT); >> + if (!FS.empty()) { >> + if (!ArchFS.empty()) >> + ArchFS = ArchFS + "," + FS.str(); >> + else >> + ArchFS = FS; >> + } >> + >> MCSubtargetInfo *X = new MCSubtargetInfo(); >> - InitARMMCSubtargetInfo(X, CPU, FS); >> + InitARMMCSubtargetInfo(X, CPU, ArchFS); >> return X; >> } >> >> @@ -74,16 +82,17 @@ >> createARMMCSubtargetInfo); >> } >> >> -std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { >> +std::string ARM_MC::ParseARMTriple(StringRef TT) { >> // Set the boolean corresponding to the current target triple, or >> the default >> // if one cannot be determined, to true. >> unsigned Len = TT.size(); >> unsigned Idx = 0; >> >> + bool isThumb = false; >> if (Len >= 5 && TT.substr(0, 4) == "armv") >> Idx = 4; >> else if (Len >= 6 && TT.substr(0, 5) == "thumb") { >> - IsThumb = true; >> + isThumb = true; >> if (Len >= 7 && TT[5] == 'v') >> Idx = 6; >> } >> @@ -116,5 +125,12 @@ >> ARMArchFeature = "+v4t"; >> } >> >> + if (isThumb) { >> + if (ARMArchFeature.empty()) >> + ARMArchFeature = "+thumb"; >> + else >> + ARMArchFeature += ",+thumb"; >> + } >> + >> return ARMArchFeature; >> } >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> URL: http://llvm.org/viewvc/llvm- >> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=13 >> 4608&r1=134607&r2=134608&view=diff >> ======================================================================= >> ======= >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 >> 03:26:46 2011 >> @@ -23,7 +23,7 @@ >> extern Target TheARMTarget, TheThumbTarget; >> >> namespace ARM_MC { >> - std::string ParseARMTriple(StringRef TT, bool &IsThumb); >> + std::string ParseARMTriple(StringRef TT); >> } >> >> } // End llvm namespace >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/02d3e53a/attachment-0001.html From evan.cheng at apple.com Thu Jul 7 11:22:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 09:22:48 -0700 Subject: [llvm-commits] [llvm] r134614 - /llvm/trunk/lib/Target/ARM/CMakeLists.txt In-Reply-To: <20110707155922.AA3D02A6C12C@llvm.org> References: <20110707155922.AA3D02A6C12C@llvm.org> Message-ID: <2043F6D3-60E3-4C8D-9B8A-510C58F5834C@apple.com> Thanks Doug. Evan On Jul 7, 2011, at 8:59 AM, Douglas Gregor wrote: > Author: dgregor > Date: Thu Jul 7 10:59:22 2011 > New Revision: 134614 > > URL: http://llvm.org/viewvc/llvm-project?rev=134614&view=rev > Log: > Fix CMake build > > Modified: > llvm/trunk/lib/Target/ARM/CMakeLists.txt > > Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134614&r1=134613&r2=134614&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) > +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Jul 7 10:59:22 2011 > @@ -66,3 +66,5 @@ > add_subdirectory(Disassembler) > add_subdirectory(InstPrinter) > add_subdirectory(MCTargetDesc) > + > +target_link_libraries(LLVMARMCodeGen LLVMARMDesc) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ofv at wanadoo.es Thu Jul 7 11:33:00 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 07 Jul 2011 16:33:00 -0000 Subject: [llvm-commits] [llvm] r134616 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Target/ARM/CMakeLists.txt Message-ID: <20110707163300.5DE1A2A6C12C@llvm.org> Author: ofv Date: Thu Jul 7 11:33:00 2011 New Revision: 134616 URL: http://llvm.org/viewvc/llvm-project?rev=134616&view=rev Log: Update CMake library dependencies Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake llvm/trunk/lib/Target/ARM/CMakeLists.txt Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=134616&r1=134615&r2=134616&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Thu Jul 7 11:33:00 2011 @@ -1,6 +1,7 @@ set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC) set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -21,7 +22,7 @@ set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMTarget) @@ -60,7 +61,7 @@ set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Info LLVMX86Utils) -set(MSVC_LIB_DEPS_LLVMX86Desc LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134616&r1=134615&r2=134616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Jul 7 11:33:00 2011 @@ -66,5 +66,3 @@ add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) - -target_link_libraries(LLVMARMCodeGen LLVMARMDesc) From joerg at bec.de Thu Jul 7 11:53:52 2011 From: joerg at bec.de (Joerg Sonnenberger) Date: Thu, 07 Jul 2011 16:53:52 -0000 Subject: [llvm-commits] [llvm] r134617 - /llvm/trunk/lib/Support/Triple.cpp Message-ID: <20110707165352.B8F0C2A6C12C@llvm.org> Author: joerg Date: Thu Jul 7 11:53:52 2011 New Revision: 134617 URL: http://llvm.org/viewvc/llvm-project?rev=134617&view=rev Log: Recognize mipseb as alias for mips for symmetry with mipsel. Modified: llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=134617&r1=134616&r2=134617&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Thu Jul 7 11:53:52 2011 @@ -282,7 +282,8 @@ return cellspu; else if (ArchName == "msp430") return msp430; - else if (ArchName == "mips" || ArchName == "mipsallegrex") + else if (ArchName == "mips" || ArchName == "mipseb" || + ArchName == "mipsallegrex") return mips; else if (ArchName == "mipsel" || ArchName == "mipsallegrexel" || ArchName == "psp") From clattner at apple.com Thu Jul 7 12:08:20 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 07 Jul 2011 10:08:20 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> Message-ID: <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> On Jul 6, 2011, at 9:40 PM, Bill Wendling wrote: >>> @@ -189,6 +190,14 @@ >>> /// >>> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >>> } >>> + >>> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >>> + /// function. Return 0 if the compact unwind isn't available. >>> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >>> + int /*DataAlignmentFactor*/, >>> + bool /*IsEH*/) const { >> >> Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? >> > Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: > /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function > 'llvm::ArrayRef::ArrayRef' requested here > return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); > ^ Please move the method body out of line. Also, please forward declare ArrayRef too. -Chris From resistor at mac.com Thu Jul 7 12:19:32 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 07 Jul 2011 10:19:32 -0700 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics In-Reply-To: <479C8C82-F5D6-4EAE-BF6E-D48FBAFBCAB3@apple.com> References: <479C8C82-F5D6-4EAE-BF6E-D48FBAFBCAB3@apple.com> Message-ID: On Jul 7, 2011, at 9:20 AM, Chris Lattner wrote: > I think that Owen is the best one to handle this. In addition to handling the signed versions of these as well, does this correctly handle the case when the subtract comes first, and the cases when the overflow bit is actually used? I don't see any issues with the use/non-use of the overflow bit. For the signed overflow versions, is it only the semantics of the overflow bit that are affected? Is the value part of the result the same between sadd/uadd? > In principle, we'd want to optimize: > > a = add i32 y, z > ... > b,c = addo(y,z) > > into: > > b,c = addo(y,z) > a = b > ? I don't think this patch will currently do this. What it will achieve is replacing all uses of b with uses of a, in your example. Fusing the add and the addo together would a good thing to handle, but it's not a very GVN-ish operation. It's mostly in the business of eliminating expressions, not mutating or injecting them. All that said, this patch is definitely an improvement over what we did before, and the code looks fine to me. Please document these future improvements in the PR, and go ahead and commit! --Owen From rafael.espindola at gmail.com Thu Jul 7 12:21:58 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 07 Jul 2011 13:21:58 -0400 Subject: [llvm-commits] [llvm] r134511 - /llvm/trunk/test/MC/ELF/relocation.s In-Reply-To: <20110706175521.292702A6C12C@llvm.org> References: <20110706175521.292702A6C12C@llvm.org> Message-ID: <4E15EB36.4080001@gmail.com> On 07/06/2011 01:55 PM, Kevin Enderby wrote: > Author: enderby > Date: Wed Jul 6 12:55:20 2011 > New Revision: 134511 > > URL: http://llvm.org/viewvc/llvm-project?rev=134511&view=rev > Log: > Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. Now for bar: pushq $bar we produce a R_X86_64_8 and gas produces a R_X86_64_32S. Since they are both sign extended, I think this is a valid improvement. Just wondering why gas doesn't do the same. Thanks, Rafael From dpatel at apple.com Thu Jul 7 12:45:33 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Jul 2011 17:45:33 -0000 Subject: [llvm-commits] [llvm] r134620 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <20110707174533.C14222A6C12C@llvm.org> Author: dpatel Date: Thu Jul 7 12:45:33 2011 New Revision: 134620 URL: http://llvm.org/viewvc/llvm-project?rev=134620&view=rev Log: If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=134620&r1=134619&r2=134620&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Jul 7 12:45:33 2011 @@ -802,6 +802,11 @@ return false; } } + // If DebugLoc does not match then two dbg.values are not identical. + if (isDebugValue()) + if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() + && getDebugLoc() != Other->getDebugLoc()) + return false; return true; } From ahatanak at gmail.com Thu Jul 7 12:54:21 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 7 Jul 2011 10:54:21 -0700 Subject: [llvm-commits] [PATCH][Review request] add flag to allow printing dwarf register numbers in cfi directives. Message-ID: This patch adds a flag in MCAsmInfo that indicates whether dwarf register numbers should be printed instead of symbolic register names in MCAsmStreamer::EmitRegisterName. This is necessary because some versions of GNU assembler won't accept code in which symbolic register names are used in cfi directives. There is no change in behavior unless the flag is explicitly set to true by a backend. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/756804d5/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: dwarfregnum1.patch Type: text/x-patch Size: 1886 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/756804d5/attachment.bin From isanbard at gmail.com Thu Jul 7 12:57:52 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 10:57:52 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> Message-ID: <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> n Jul 7, 2011, at 10:08 AM, Chris Lattner wrote: > On Jul 6, 2011, at 9:40 PM, Bill Wendling wrote: >>>> @@ -189,6 +190,14 @@ >>>> /// >>>> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >>>> } >>>> + >>>> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >>>> + /// function. Return 0 if the compact unwind isn't available. >>>> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >>>> + int /*DataAlignmentFactor*/, >>>> + bool /*IsEH*/) const { >>> >>> Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? >>> >> Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: >> /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function >> 'llvm::ArrayRef::ArrayRef' requested here >> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >> ^ > > Please move the method body out of line. Also, please forward declare ArrayRef too. > In file included from /Volumes/Sandbox/llvm/llvm.src/lib/Target/TargetAsmInfo.cpp:10: In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:19: In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:17: In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineBasicBlock.h:17: In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineInstr.h:28: In file included from /usr/include/c++/4.2.1/vector:69: /usr/include/c++/4.2.1/bits/stl_vector.h:493:41: error: arithmetic on a pointer to an incomplete type 'llvm::MCCFIInstruction' { return *(this->_M_impl._M_start + __n); } ~~~~~~~~~~~~~~~~~~~~~~ ^ /Volumes/Sandbox/llvm/llvm.src/include/llvm/ADT/ArrayRef.h:65:37: note: in instantiation of member function 'std::vector >::operator[]' requested here : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} ^ /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function 'llvm::ArrayRef::ArrayRef' requested here return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); ^ /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:24:9: note: forward declaration of 'llvm::MCCFIInstruction' class MCCFIInstruction; ^ -bw From rafael.espindola at gmail.com Thu Jul 7 13:04:51 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Thu, 07 Jul 2011 14:04:51 -0400 Subject: [llvm-commits] [PATCH][Review request] add flag to allow printing dwarf register numbers in cfi directives. In-Reply-To: References: Message-ID: <4E15F543.2070004@gmail.com> On 07/07/2011 01:54 PM, Akira Hatanaka wrote: > This patch adds a flag in MCAsmInfo that indicates whether dwarf > register numbers should be printed instead of symbolic register names in > MCAsmStreamer::EmitRegisterName. This is necessary because some versions > of GNU assembler won't accept code in which symbolic register names are > used in cfi directives. There is no change in behavior unless the flag > is explicitly set to true by a backend. LGTM. Cheers, Rafael From ahatanak at gmail.com Thu Jul 7 13:27:36 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 18:27:36 -0000 Subject: [llvm-commits] [llvm] r134622 - /llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Message-ID: <20110707182736.D36AE2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 13:27:36 2011 New Revision: 134622 URL: http://llvm.org/viewvc/llvm-project?rev=134622&view=rev Log: Add missing return statement. Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134622&r1=134621&r2=134622&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 13:27:36 2011 @@ -78,8 +78,10 @@ SmallString<128> Str; raw_svector_ostream OS(Str); - if (MI->isDebugValue()) + if (MI->isDebugValue()) { PrintDebugValueComment(MI, OS); + return; + } printInstruction(MI, OS); OutStreamer.EmitRawText(OS.str()); From dmalyshev at accesssoftek.com Thu Jul 7 13:33:59 2011 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Thu, 7 Jul 2011 11:33:59 -0700 Subject: [llvm-commits] Add to RuntimeDyld support different object formats In-Reply-To: <4D93170A-8936-444E-8E4D-6FEABE985AF8@apple.com> References: <6AE1604EE3EC5F4296C096518C6B77EE17F1ACBF5D@mail.accesssoftek.com> <4D93170A-8936-444E-8E4D-6FEABE985AF8@apple.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE17F1ACC34A@mail.accesssoftek.com> Hi, Please find attached the patch with the changes Jim has asked. > A brief brain-dump of some things I've been thinking about but may not > be readily apparent from the code as it currently exists: All of that makes sense. We also need to find a way to properly abstract and separate the target-specific relocations implementation from the file format and common code. I.e. ELF -> REL/RELA -> ARM Machine Type relocations. Regards, Danil -------------- next part -------------- A non-text attachment was scrubbed... Name: RuntimeDyld_different_object_formats-02.patch Type: application/octet-stream Size: 56317 bytes Desc: RuntimeDyld_different_object_formats-02.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/7530e054/attachment-0001.obj From ahatanak at gmail.com Thu Jul 7 13:57:00 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 18:57:00 -0000 Subject: [llvm-commits] [llvm] r134625 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsEmitGPRestore.cpp MipsISelDAGToDAG.cpp MipsISelLowering.cpp MipsInstrInfo.cpp MipsInstrInfo.td MipsRegisterInfo.cpp Message-ID: <20110707185700.C3BBE2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 13:57:00 2011 New Revision: 134625 URL: http://llvm.org/viewvc/llvm-project?rev=134625&view=rev Log: Reverse order of operands of address operand mem so that the base operand comes before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsEmitGPRestore.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 13:57:00 2011 @@ -412,18 +412,18 @@ // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. if (Modifier && !strcmp(Modifier, "stackloc")) { - printOperand(MI, opNum+1, O); - O << ", "; printOperand(MI, opNum, O); + O << ", "; + printOperand(MI, opNum+1, O); return; } // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) - printOperand(MI, opNum, O); - O << "("; printOperand(MI, opNum+1, O); + O << "("; + printOperand(MI, opNum, O); O << ")"; } Modified: llvm/trunk/lib/Target/Mips/MipsEmitGPRestore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsEmitGPRestore.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsEmitGPRestore.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsEmitGPRestore.cpp Thu Jul 7 13:57:00 2011 @@ -64,8 +64,8 @@ // Insert lw. ++I; DebugLoc dl = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addImm(0) - .addFrameIndex(FI); + BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI) + .addImm(0); Changed = true; } @@ -77,8 +77,8 @@ DebugLoc dl = I->getDebugLoc(); // emit lw $gp, ($gp save slot on stack) after jalr - BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addImm(0) - .addFrameIndex(FI); + BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI) + .addImm(0); Changed = true; } } Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jul 7 13:57:00 2011 @@ -113,7 +113,7 @@ /// ComplexPattern used on MipsInstrInfo /// Used on Mips Load/Store instructions bool MipsDAGToDAGISel:: -SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) { +SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { // if Address is FI, get the TargetFrameIndex. if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); @@ -200,7 +200,7 @@ SDValue N1 = N->getOperand(1); SDValue Offset0, Offset1, Base; - if (!SelectAddr(N1, Offset0, Base) || + if (!SelectAddr(N1, Base, Offset0) || N1.getValueType() != MVT::i32) return NULL; @@ -230,14 +230,14 @@ // lwc $f0, X($3) // lwc $f1, X+4($3) SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32, - MVT::Other, Offset0, Base, Chain); + MVT::Other, Base, Offset0, Chain); SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, NVT), 0); SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl, MVT::f64, Undef, SDValue(LD0, 0)); SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32, - MVT::Other, Offset1, Base, SDValue(LD0, 1)); + MVT::Other, Base, Offset1, SDValue(LD0, 1)); SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl, MVT::f64, I0, SDValue(LD1, 0)); @@ -264,7 +264,7 @@ SDValue N2 = N->getOperand(2); SDValue Offset0, Offset1, Base; - if (!SelectAddr(N2, Offset0, Base) || + if (!SelectAddr(N2, Base, Offset0) || N1.getValueType() != MVT::f64 || N2.getValueType() != MVT::i32) return NULL; @@ -294,12 +294,12 @@ // Generate: // swc $f0, X($3) // swc $f1, X+4($3) - SDValue Ops0[] = { FPEven, Offset0, Base, Chain }; + SDValue Ops0[] = { FPEven, Base, Offset0, Chain }; Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl, MVT::Other, Ops0, 4), 0); cast(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1); - SDValue Ops1[] = { FPOdd, Offset1, Base, Chain }; + SDValue Ops1[] = { FPOdd, Base, Offset1, Chain }; Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl, MVT::Other, Ops1, 4), 0); cast(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 7 13:57:00 2011 @@ -774,7 +774,7 @@ } BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Incr).addImm(0).addFrameIndex(fi); + .addReg(Incr).addFrameIndex(fi).addImm(0); } BB->addSuccessor(loopMBB); @@ -785,7 +785,7 @@ // sc tmp1, 0(ptr) // beq tmp1, $0, loopMBB BB = loopMBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval); if (Nand) { // and tmp2, oldval, incr @@ -798,10 +798,10 @@ } else { // lw tmp2, fi(sp) // load incr from stack // or tmp1, $zero, tmp2 - BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); } - BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB); BB->addSuccessor(loopMBB); @@ -910,7 +910,7 @@ } BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Incr2).addImm(0).addFrameIndex(fi); + .addReg(Incr2).addFrameIndex(fi).addImm(0); } BB->addSuccessor(loopMBB); @@ -923,7 +923,7 @@ // sc tmp9,0(addr) // beq tmp9,$0,loopMBB BB = loopMBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0); if (Nand) { // and tmp6, oldval, incr2 // nor tmp7, $0, tmp6 @@ -938,13 +938,13 @@ } else { // lw tmp6, fi(sp) // load incr2 from stack // or tmp7, $zero, tmp6 - BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addFrameIndex(fi).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); } BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB); BB->addSuccessor(loopMBB); @@ -1027,14 +1027,14 @@ // hoist "or" instruction out of the block loop2MBB. BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Newval).addImm(0).addFrameIndex(fi); + .addReg(Newval).addFrameIndex(fi).addImm(0); BB->addSuccessor(loop1MBB); // loop1MBB: // ll dest, 0(ptr) // bne dest, oldval, exitMBB BB = loop1MBB; - BuildMI(BB, dl, TII->get(Mips::LL), Dest).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BNE)) .addReg(Dest).addReg(Oldval).addMBB(exitMBB); BB->addSuccessor(exitMBB); @@ -1046,9 +1046,9 @@ // sc tmp1, 0(ptr) // beq tmp1, $0, loop1MBB BB = loop2MBB; - BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB); BB->addSuccessor(loop1MBB); @@ -1143,7 +1143,7 @@ // and oldval4,oldval3,mask // bne oldval4,oldval2,exitMBB BB = loop1MBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::BNE)) .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB); @@ -1159,7 +1159,7 @@ BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); BuildMI(BB, dl, TII->get(Mips::SC), Tmp7) - .addReg(Tmp7).addImm(0).addReg(Addr); + .addReg(Tmp7).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB); BB->addSuccessor(loop1MBB); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jul 7 13:57:00 2011 @@ -43,10 +43,10 @@ { if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || (MI->getOpcode() == Mips::LDC1)) { - if ((MI->getOperand(2).isFI()) && // is a stack slot - (MI->getOperand(1).isImm()) && // the imm is zero - (isZeroImm(MI->getOperand(1)))) { - FrameIndex = MI->getOperand(2).getIndex(); + if ((MI->getOperand(1).isFI()) && // is a stack slot + (MI->getOperand(2).isImm()) && // the imm is zero + (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } } @@ -64,10 +64,10 @@ { if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || (MI->getOpcode() == Mips::SDC1)) { - if ((MI->getOperand(2).isFI()) && // is a stack slot - (MI->getOperand(1).isImm()) && // the imm is zero - (isZeroImm(MI->getOperand(1)))) { - FrameIndex = MI->getOperand(2).getIndex(); + if ((MI->getOperand(1).isFI()) && // is a stack slot + (MI->getOperand(2).isImm()) && // the imm is zero + (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } } @@ -164,25 +164,25 @@ if (RC == Mips::CPURegsRegisterClass) BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); else if (RC == Mips::FGR32RegisterClass) BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); else if (RC == Mips::AFGR64RegisterClass) { if (!TM.getSubtarget().isMips1()) { BuildMI(MBB, I, DL, get(Mips::SDC1)) .addReg(SrcReg, getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); } else { const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo(); const unsigned *SubSet = TRI->getSubRegisters(SrcReg); BuildMI(MBB, I, DL, get(Mips::SWC1)) .addReg(SubSet[0], getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); BuildMI(MBB, I, DL, get(Mips::SWC1)) .addReg(SubSet[1], getKillRegState(isKill)) - .addImm(4).addFrameIndex(FI); + .addFrameIndex(FI).addImm(4); } } else llvm_unreachable("Register class not handled!"); @@ -198,20 +198,20 @@ if (I != MBB.end()) DL = I->getDebugLoc(); if (RC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI); + BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addFrameIndex(FI).addImm(0); else if (RC == Mips::FGR32RegisterClass) - BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI); + BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0); else if (RC == Mips::AFGR64RegisterClass) { if (!TM.getSubtarget().isMips1()) { - BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI); + BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0); } else { const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo(); const unsigned *SubSet = TRI->getSubRegisters(DestReg); BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0]) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1]) - .addImm(4).addFrameIndex(FI); + .addFrameIndex(FI).addImm(4); } } else llvm_unreachable("Register class not handled!"); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jul 7 13:57:00 2011 @@ -134,7 +134,7 @@ // Address operand def mem : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops simm16, CPURegs); + let MIOperandInfo = (ops CPURegs, simm16); } // Transformation Function - get the lower 16 bits. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134625&r1=134624&r2=134625&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jul 7 13:57:00 2011 @@ -224,7 +224,7 @@ return; } - Offset += MI.getOperand(i-1).getImm(); + Offset += MI.getOperand(i+1).getImm(); DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); @@ -262,7 +262,7 @@ BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO)); MI.getOperand(i).ChangeToRegister(NewReg, false); - MI.getOperand(i-1).ChangeToImmediate(NewImm); + MI.getOperand(i+1).ChangeToImmediate(NewImm); } unsigned MipsRegisterInfo:: From evan.cheng at apple.com Thu Jul 7 14:05:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 19:05:13 -0000 Subject: [llvm-commits] [llvm] r134626 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp ARMSubtarget.h MCTargetDesc/ARMMCTargetDesc.cpp Message-ID: <20110707190513.1F3292A6C12C@llvm.org> Author: evancheng Date: Thu Jul 7 14:05:12 2011 New Revision: 134626 URL: http://llvm.org/viewvc/llvm-project?rev=134626&view=rev Log: Rename attribute 'thumb' to a more descriptive 'thumb-mode'. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134626&r1=134625&r2=134626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jul 7 14:05:12 2011 @@ -20,7 +20,7 @@ // ARM Subtarget state. // -def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true", +def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", "Thumb mode">; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134626&r1=134625&r2=134626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 14:05:12 2011 @@ -53,7 +53,7 @@ , SlowFPVMLx(false) , HasVMLxForwarding(false) , SlowFPBrcc(false) - , IsThumb(false) + , InThumbMode(false) , HasThumb2(false) , NoARM(false) , PostRAScheduler(false) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134626&r1=134625&r2=134626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jul 7 14:05:12 2011 @@ -67,8 +67,8 @@ /// SlowFPBrcc - True if floating point compare + branch is slow. bool SlowFPBrcc; - /// IsThumb - True if we are in thumb mode, false if in ARM mode. - bool IsThumb; + /// InThumbMode - True if we are in thumb mode, false if in ARM mode. + bool InThumbMode; /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2; @@ -214,9 +214,9 @@ bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } - bool isThumb() const { return IsThumb; } - bool isThumb1Only() const { return IsThumb && !HasThumb2; } - bool isThumb2() const { return IsThumb && HasThumb2; } + bool isThumb() const { return InThumbMode; } + bool isThumb1Only() const { return InThumbMode && !HasThumb2; } + bool isThumb2() const { return InThumbMode && HasThumb2; } bool hasThumb2() const { return HasThumb2; } bool isR9Reserved() const { return IsR9Reserved; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134626&r1=134625&r2=134626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 14:05:12 2011 @@ -88,6 +88,7 @@ unsigned Len = TT.size(); unsigned Idx = 0; + // FIXME: Enahnce Triple helper class to extract ARM version. bool isThumb = false; if (Len >= 5 && TT.substr(0, 4) == "armv") Idx = 4; @@ -127,9 +128,9 @@ if (isThumb) { if (ARMArchFeature.empty()) - ARMArchFeature = "+thumb"; + ARMArchFeature = "+thumb-mode"; else - ARMArchFeature += ",+thumb"; + ARMArchFeature += ",+thumb-mode"; } return ARMArchFeature; From evan.cheng at apple.com Thu Jul 7 14:09:06 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 19:09:06 -0000 Subject: [llvm-commits] [llvm] r134627 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.h Message-ID: <20110707190906.942AB2A6C12C@llvm.org> Author: evancheng Date: Thu Jul 7 14:09:06 2011 New Revision: 134627 URL: http://llvm.org/viewvc/llvm-project?rev=134627&view=rev Log: Rewrite comment in English. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134627&r1=134626&r2=134627&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jul 7 14:09:06 2011 @@ -67,7 +67,7 @@ /// SlowFPBrcc - True if floating point compare + branch is slow. bool SlowFPBrcc; - /// InThumbMode - True if we are in thumb mode, false if in ARM mode. + /// InThumbMode - True if compiling for Thumb, false for ARM. bool InThumbMode; /// HasThumb2 - True if Thumb2 instructions are supported. From ahatanak at gmail.com Thu Jul 7 14:13:10 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 19:13:10 -0000 Subject: [llvm-commits] [llvm] r134628 - /llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Message-ID: <20110707191310.240302A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 14:13:09 2011 New Revision: 134628 URL: http://llvm.org/viewvc/llvm-project?rev=134628&view=rev Log: Simplify MipsRegisterInfo::eliminateFrameIndex. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134628&r1=134627&r2=134628&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jul 7 14:13:09 2011 @@ -218,51 +218,31 @@ else Offset = spOffset + stackSize; - if (MI.isDebugValue()) { - MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/); - MI.getOperand(i+1).ChangeToImmediate(Offset); - return; - } - Offset += MI.getOperand(i+1).getImm(); DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); - unsigned NewReg = 0; - int NewImm = 0; - MachineBasicBlock &MBB = *MI.getParent(); - bool ATUsed; - - // Offset fits in the 16-bit field - if (Offset < 0x8000 && Offset >= -0x8000) { - NewReg = FrameReg; - NewImm = Offset; - ATUsed = false; - } - else { - const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); + // If MI is not a debug value, make sure Offset fits in the 16-bit immediate + // field. + if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) { + MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = II->getDebugLoc(); - int ImmLo = (short)(Offset & 0xffff); int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) + ((Offset & 0x8000) != 0); // FIXME: change this when mips goes MC". - BuildMI(MBB, II, DL, TII->get(Mips::NOAT)); - BuildMI(MBB, II, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi); - BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(FrameReg) - .addReg(Mips::AT); - NewReg = Mips::AT; - NewImm = ImmLo; - - ATUsed = true; - } + BuildMI(MBB, II, DL, TII.get(Mips::NOAT)); + BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi); + BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg) + .addReg(Mips::AT); + FrameReg = Mips::AT; + Offset = (short)(Offset & 0xffff); - // FIXME: change this when mips goes MC". - if (ATUsed) BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO)); + } - MI.getOperand(i).ChangeToRegister(NewReg, false); - MI.getOperand(i+1).ChangeToImmediate(NewImm); + MI.getOperand(i).ChangeToRegister(FrameReg, false); + MI.getOperand(i+1).ChangeToImmediate(Offset); } unsigned MipsRegisterInfo:: From ahatanak at gmail.com Thu Jul 7 14:27:22 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 19:27:22 -0000 Subject: [llvm-commits] [llvm] r134629 - in /llvm/trunk/lib/Target/Mips: CMakeLists.txt MipsMCSymbolRefExpr.cpp MipsMCSymbolRefExpr.h Message-ID: <20110707192722.C470E2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 14:27:22 2011 New Revision: 134629 URL: http://llvm.org/viewvc/llvm-project?rev=134629&view=rev Log: Define class MipsMCSymbolRefExpr. Added: llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=134629&r1=134628&r2=134629&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jul 7 14:27:22 2011 @@ -17,6 +17,7 @@ MipsISelLowering.cpp MipsFrameLowering.cpp MipsMCAsmInfo.cpp + MipsMCSymbolRefExpr.cpp MipsRegisterInfo.cpp MipsSubtarget.cpp MipsTargetMachine.cpp Added: llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp?rev=134629&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp (added) +++ llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp Thu Jul 7 14:27:22 2011 @@ -0,0 +1,63 @@ +//===-- MipsMCSymbolRefExpr.cpp - Mips specific MC expression classes -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "mipsmcsymbolrefexpr" +#include "MipsMCSymbolRefExpr.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSymbol.h" +using namespace llvm; + +const MipsMCSymbolRefExpr* +MipsMCSymbolRefExpr::Create(VariantKind Kind, const MCSymbol *Symbol, + int Offset, MCContext &Ctx) { + return new (Ctx) MipsMCSymbolRefExpr(Kind, Symbol, Offset); +} + +void MipsMCSymbolRefExpr::PrintImpl(raw_ostream &OS) const { + switch (Kind) { + default: assert(0 && "Invalid kind!"); + case VK_Mips_None: break; + case VK_Mips_GPREL: OS << "%gp_rel("; break; + case VK_Mips_GOT_CALL: OS << "%call16("; break; + case VK_Mips_GOT: OS << "%got("; break; + case VK_Mips_ABS_HI: OS << "%hi("; break; + case VK_Mips_ABS_LO: OS << "%lo("; break; + case VK_Mips_TLSGD: OS << "%tlsgd("; break; + case VK_Mips_GOTTPREL: OS << "%gottprel("; break; + case VK_Mips_TPREL_HI: OS << "%tprel_hi("; break; + case VK_Mips_TPREL_LO: OS << "%tprel_lo("; break; + } + + OS << *Symbol; + + if (Offset) { + if (Offset > 0) + OS << '+'; + OS << Offset; + } + + if (Kind != VK_Mips_None) + OS << ')'; +} + +bool +MipsMCSymbolRefExpr::EvaluateAsRelocatableImpl(MCValue &Res, + const MCAsmLayout *Layout) const { + return false; +} + +void MipsMCSymbolRefExpr::AddValueSymbols(MCAssembler *Asm) const { + Asm->getOrCreateSymbolData(*Symbol); +} + +const MCSection *MipsMCSymbolRefExpr::FindAssociatedSection() const { + return Symbol->isDefined() ? &Symbol->getSection() : NULL; +} + Added: llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h?rev=134629&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h (added) +++ llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h Thu Jul 7 14:27:22 2011 @@ -0,0 +1,62 @@ +//===-- MipsMCSymbolRefExpr.h - Mips specific MCSymbolRefExpr class -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSMCSYMBOLREFEXPR_H +#define MIPSMCSYMBOLREFEXPR_H +#include "llvm/MC/MCExpr.h" + +namespace llvm { + +class MipsMCSymbolRefExpr : public MCTargetExpr { +public: + enum VariantKind { + VK_Mips_None, + VK_Mips_GPREL, + VK_Mips_GOT_CALL, + VK_Mips_GOT, + VK_Mips_ABS_HI, + VK_Mips_ABS_LO, + VK_Mips_TLSGD, + VK_Mips_GOTTPREL, + VK_Mips_TPREL_HI, + VK_Mips_TPREL_LO + }; + +private: + const VariantKind Kind; + const MCSymbol *Symbol; + int Offset; + + explicit MipsMCSymbolRefExpr(VariantKind _Kind, const MCSymbol *_Symbol, + int _Offset) + : Kind(_Kind), Symbol(_Symbol), Offset(_Offset) {} + +public: + static const MipsMCSymbolRefExpr *Create(VariantKind Kind, + const MCSymbol *Symbol, int Offset, + MCContext &Ctx); + + void PrintImpl(raw_ostream &OS) const; + bool EvaluateAsRelocatableImpl(MCValue &Res, + const MCAsmLayout *Layout) const; + void AddValueSymbols(MCAssembler *) const; + const MCSection *FindAssociatedSection() const; + + static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; + } + + static bool classof(const MipsMCSymbolRefExpr *) { return true; } + + int getOffset() const { return Offset; } + void setOffset(int O) { Offset = O; } +}; +} // end namespace llvm + +#endif From ahatanak at gmail.com Thu Jul 7 15:10:52 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 20:10:52 -0000 Subject: [llvm-commits] [llvm] r134630 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsAsmPrinter.h Message-ID: <20110707201052.DADE42A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 15:10:52 2011 New Revision: 134630 URL: http://llvm.org/viewvc/llvm-project?rev=134630&view=rev Log: Change visibility of MipsAsmPrinter. Added: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134630&r1=134629&r2=134630&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 15:10:52 2011 @@ -13,14 +13,12 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-asm-printer" +#include "MipsAsmPrinter.h" #include "Mips.h" -#include "MipsSubtarget.h" #include "MipsInstrInfo.h" -#include "MipsTargetMachine.h" #include "MipsMachineFunction.h" #include "llvm/BasicBlock.h" #include "llvm/Instructions.h" -#include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -31,7 +29,6 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" @@ -42,65 +39,20 @@ using namespace llvm; -namespace { - class MipsAsmPrinter : public AsmPrinter { - const MipsSubtarget *Subtarget; - public: - explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer) { - Subtarget = &TM.getSubtarget(); - } - - virtual const char *getPassName() const { - return "Mips Assembly Printer"; - } +#include "MipsGenAsmWriter.inc" - bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode, - raw_ostream &O); - bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode, - raw_ostream &O); - void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); - void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); - void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier = 0); - void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier = 0); - void printSavedRegsBitmask(raw_ostream &O); - void printHex32(unsigned int Value, raw_ostream &O); - - const char *getCurrentABIString() const; - void emitFrameDirective(); - - void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. - void EmitInstruction(const MachineInstr *MI) { - SmallString<128> Str; - raw_svector_ostream OS(Str); - - if (MI->isDebugValue()) { - PrintDebugValueComment(MI, OS); - return; - } +void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { + SmallString<128> Str; + raw_svector_ostream OS(Str); - printInstruction(MI, OS); - OutStreamer.EmitRawText(OS.str()); - } - virtual void EmitFunctionBodyStart(); - virtual void EmitFunctionBodyEnd(); - virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock* - MBB) const; - static const char *getRegisterName(unsigned RegNo); - - virtual void EmitFunctionEntryLabel(); - void EmitStartOfAsmFile(Module &M); - virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const; - - void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); - }; -} // end of anonymous namespace + if (MI->isDebugValue()) { + PrintDebugValueComment(MI, OS); + return; + } -#include "MipsGenAsmWriter.inc" + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); +} //===----------------------------------------------------------------------===// // Added: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h?rev=134630&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h (added) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h Thu Jul 7 15:10:52 2011 @@ -0,0 +1,75 @@ +//===-- MipsAsmPrinter.h - Mips LLVM assembly writer ----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Mips Assembly printer class. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSASMPRINTER_H +#define MIPSASMPRINTER_H + +#include "MipsSubtarget.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { +class MCStreamer; +class MachineInstr; +class raw_ostream; +class MachineBasicBlock; +class Module; + +class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { + const MipsSubtarget *Subtarget; + +public: + explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) { + Subtarget = &TM.getSubtarget(); + } + + virtual const char *getPassName() const { + return "Mips Assembly Printer"; + } + + // These two methods are autogen'd by tablegen. + void printInstruction(const MachineInstr *MI, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); + + void EmitInstruction(const MachineInstr *MI); + void printSavedRegsBitmask(raw_ostream &O); + void printHex32(unsigned int Value, raw_ostream &O); + void emitFrameDirective(); + const char *getCurrentABIString() const; + virtual void EmitFunctionEntryLabel(); + virtual void EmitFunctionBodyStart(); + virtual void EmitFunctionBodyEnd(); + virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock* + MBB) const; + bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); + bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier = 0); + void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier = 0); + void EmitStartOfAsmFile(Module &M); + virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const; + void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); +}; +} + +#endif + From ahatanak at gmail.com Thu Jul 7 15:24:54 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 20:24:54 -0000 Subject: [llvm-commits] [llvm] r134633 - in /llvm/trunk/lib/Target/Mips: CMakeLists.txt MipsMCInstLower.cpp MipsMCInstLower.h Message-ID: <20110707202454.6502A2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 15:24:54 2011 New Revision: 134633 URL: http://llvm.org/viewvc/llvm-project?rev=134633&view=rev Log: Define class MipsMCInstLower. Added: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=134633&r1=134632&r2=134633&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jul 7 15:24:54 2011 @@ -17,6 +17,7 @@ MipsISelLowering.cpp MipsFrameLowering.cpp MipsMCAsmInfo.cpp + MipsMCInstLower.cpp MipsMCSymbolRefExpr.cpp MipsRegisterInfo.cpp MipsSubtarget.cpp Added: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=134633&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (added) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Thu Jul 7 15:24:54 2011 @@ -0,0 +1,117 @@ +//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains code to lower Mips MachineInstrs to their corresponding +// MCInst records. +// +//===----------------------------------------------------------------------===// + +#include "MipsMCInstLower.h" +#include "MipsAsmPrinter.h" +#include "MipsInstrInfo.h" +#include "MipsMCSymbolRefExpr.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Target/Mangler.h" +using namespace llvm; + +MipsMCInstLower::MipsMCInstLower(Mangler *mang, const MachineFunction &mf, + MipsAsmPrinter &asmprinter) + : Ctx(mf.getContext()), Mang(mang), AsmPrinter(asmprinter) {} + +MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, + MachineOperandType MOTy) const { + MipsMCSymbolRefExpr::VariantKind Kind; + const MCSymbol *Symbol; + int Offset = 0; + + switch(MO.getTargetFlags()) { + case MipsII::MO_NO_FLAG: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; + case MipsII::MO_GPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GPREL; break; + case MipsII::MO_GOT_CALL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_CALL; break; + case MipsII::MO_GOT: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT; break; + case MipsII::MO_ABS_HI: Kind = MipsMCSymbolRefExpr::VK_Mips_ABS_HI; break; + case MipsII::MO_ABS_LO: Kind = MipsMCSymbolRefExpr::VK_Mips_ABS_LO; break; + case MipsII::MO_TLSGD: Kind = MipsMCSymbolRefExpr::VK_Mips_TLSGD; break; + case MipsII::MO_GOTTPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOTTPREL; break; + case MipsII::MO_TPREL_HI: Kind = MipsMCSymbolRefExpr::VK_Mips_TPREL_HI; break; + case MipsII::MO_TPREL_LO: Kind = MipsMCSymbolRefExpr::VK_Mips_TPREL_LO; break; + } + + switch (MOTy) { + case MachineOperand::MO_MachineBasicBlock: + Symbol = MO.getMBB()->getSymbol(); + break; + + case MachineOperand::MO_GlobalAddress: + Symbol = Mang->getSymbol(MO.getGlobal()); + break; + + case MachineOperand::MO_BlockAddress: + Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()); + break; + + case MachineOperand::MO_ExternalSymbol: + Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName()); + break; + + case MachineOperand::MO_JumpTableIndex: + Symbol = AsmPrinter.GetJTISymbol(MO.getIndex()); + break; + + case MachineOperand::MO_ConstantPoolIndex: + Symbol = AsmPrinter.GetCPISymbol(MO.getIndex()); + if (MO.getOffset()) + Offset = MO.getOffset(); + break; + + default: + llvm_unreachable(""); + } + + return MCOperand::CreateExpr(MipsMCSymbolRefExpr::Create(Kind, Symbol, Offset, + Ctx)); +} + +void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { + OutMI.setOpcode(MI->getOpcode()); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + MCOperand MCOp; + MachineOperandType MOTy = MO.getType(); + + switch (MOTy) { + default: + MI->dump(); + llvm_unreachable("unknown operand type"); + case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) continue; + MCOp = MCOperand::CreateReg(MO.getReg()); + break; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::CreateImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ExternalSymbol: + case MachineOperand::MO_JumpTableIndex: + case MachineOperand::MO_ConstantPoolIndex: + case MachineOperand::MO_BlockAddress: + MCOp = LowerSymbolOperand(MO, MOTy); + break; + } + + OutMI.addOperand(MCOp); + } +} Added: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=134633&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (added) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Thu Jul 7 15:24:54 2011 @@ -0,0 +1,43 @@ +//===-- MipsMCInstLower.h - Lower MachineInstr to MCInst -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSMCINSTLOWER_H +#define MIPSMCINSTLOWER_H +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Support/Compiler.h" + +namespace llvm { + class MCAsmInfo; + class MCContext; + class MCInst; + class MCOperand; + class MCSymbol; + class MachineInstr; + class MachineFunction; + class Mangler; + class MipsAsmPrinter; + +/// MipsMCInstLower - This class is used to lower an MachineInstr into an +// MCInst. +class LLVM_LIBRARY_VISIBILITY MipsMCInstLower { + typedef MachineOperand::MachineOperandType MachineOperandType; + MCContext &Ctx; + Mangler *Mang; + MipsAsmPrinter &AsmPrinter; +public: + MipsMCInstLower(Mangler *mang, const MachineFunction &MF, + MipsAsmPrinter &asmprinter); + void Lower(const MachineInstr *MI, MCInst &OutMI) const; +private: + MCOperand LowerSymbolOperand(const MachineOperand &MO, + MachineOperandType MOTy) const; +}; +} + +#endif From ahatanak at gmail.com Thu Jul 7 15:30:33 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 20:30:33 -0000 Subject: [llvm-commits] [llvm] r134635 - in /llvm/trunk: include/llvm/MC/MCAsmInfo.h lib/MC/MCAsmInfo.cpp lib/MC/MCAsmStreamer.cpp Message-ID: <20110707203033.93B572A6C12D@llvm.org> Author: ahatanak Date: Thu Jul 7 15:30:33 2011 New Revision: 134635 URL: http://llvm.org/viewvc/llvm-project?rev=134635&view=rev Log: This patch adds a flag in MCAsmInfo that indicates whether dwarf register numbers should be printed instead of symbolic register names in MCAsmStreamer::EmitRegisterName. This is necessary because some versions of GNU assembler won't accept code in which symbolic register names are used in cfi directives. There is no change in behavior unless the flag is explicitly set to true by a backend. Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h llvm/trunk/lib/MC/MCAsmInfo.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=134635&r1=134634&r2=134635&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Jul 7 15:30:33 2011 @@ -284,6 +284,10 @@ // use EmitLabelOffsetDifference. bool DwarfUsesLabelOffsetForRanges; + /// DwarfRegNumForCFI - True if dwarf register numbers are printed + /// instead of symbolic register names in .cfi_* directives. + bool DwarfRegNumForCFI; // Defaults to false; + //===--- CBE Asm Translation Table -----------------------------------===// const char *const *AsmTransCBE; // Defaults to empty @@ -475,6 +479,9 @@ bool doesDwarfUsesLabelOffsetForRanges() const { return DwarfUsesLabelOffsetForRanges; } + bool useDwarfRegNumForCFI() const { + return DwarfRegNumForCFI; + } const char *const *getAsmCBE() const { return AsmTransCBE; } Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=134635&r1=134634&r2=134635&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Jul 7 15:30:33 2011 @@ -78,6 +78,7 @@ DwarfRequiresRelocationForSectionOffset = true; DwarfSectionOffsetDirective = 0; DwarfUsesLabelOffsetForRanges = true; + DwarfRegNumForCFI = false; HasMicrosoftFastStdCallMangling = false; AsmTransCBE = 0; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=134635&r1=134634&r2=134635&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jul 7 15:30:33 2011 @@ -825,7 +825,7 @@ } void MCAsmStreamer::EmitRegisterName(int64_t Register) { - if (InstPrinter) { + if (InstPrinter && !MAI.useDwarfRegNumForCFI()) { const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); InstPrinter->printRegName(OS, LLVMRegister); From clattner at apple.com Thu Jul 7 15:37:29 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 07 Jul 2011 13:37:29 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> Message-ID: What are you trying to say here? -Chris On Jul 7, 2011, at 10:57 AM, Bill Wendling wrote: > > n Jul 7, 2011, at 10:08 AM, Chris Lattner wrote: > >> On Jul 6, 2011, at 9:40 PM, Bill Wendling wrote: >>>>> @@ -189,6 +190,14 @@ >>>>> /// >>>>> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >>>>> } >>>>> + >>>>> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >>>>> + /// function. Return 0 if the compact unwind isn't available. >>>>> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >>>>> + int /*DataAlignmentFactor*/, >>>>> + bool /*IsEH*/) const { >>>> >>>> Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? >>>> >>> Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: >>> /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function >>> 'llvm::ArrayRef::ArrayRef' requested here >>> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >>> ^ >> >> Please move the method body out of line. Also, please forward declare ArrayRef too. >> > In file included from /Volumes/Sandbox/llvm/llvm.src/lib/Target/TargetAsmInfo.cpp:10: > In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:19: > In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:17: > In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineBasicBlock.h:17: > In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineInstr.h:28: > In file included from /usr/include/c++/4.2.1/vector:69: > /usr/include/c++/4.2.1/bits/stl_vector.h:493:41: error: arithmetic on a pointer to an incomplete type 'llvm::MCCFIInstruction' > { return *(this->_M_impl._M_start + __n); } > ~~~~~~~~~~~~~~~~~~~~~~ ^ > /Volumes/Sandbox/llvm/llvm.src/include/llvm/ADT/ArrayRef.h:65:37: note: in instantiation of member function 'std::vector >::operator[]' requested > here > : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} > ^ > /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function 'llvm::ArrayRef::ArrayRef' requested here > return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); > ^ > /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:24:9: note: forward declaration of 'llvm::MCCFIInstruction' > class MCCFIInstruction; > ^ > > > -bw > From jstaszak at apple.com Thu Jul 7 15:48:00 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Thu, 07 Jul 2011 13:48:00 -0700 Subject: [llvm-commits] [llvm] r134516 - in /llvm/trunk: include/llvm/ include/llvm/Support/ include/llvm/Transforms/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ test/CodeGen/Generic/ test/Transforms/LowerExpectIntrinsic/ In-Reply-To: <2D61D6E4-1D32-49D8-A2A3-61714051E44A@apple.com> References: <20110706182243.7DE702A6C12C@llvm.org> <2D61D6E4-1D32-49D8-A2A3-61714051E44A@apple.com> Message-ID: <8B539270-D9EF-4587-BCCF-331ED6AFC611@apple.com> Hi Chris, Right now clang creates "expect" intrinsic for every __builtin_expect instruction. These intrinsics must be lowered early because in other case they can harm other optimizations. During the lowering we also create "branch_weight" metadata, which can be used by other optimizations using BranchProbability analysis. -Kuba On Jul 6, 2011, at 5:31 PM, Chris Lattner wrote: > > On Jul 6, 2011, at 11:22 AM, Jakub Staszak wrote: > >> Author: kuba >> Date: Wed Jul 6 13:22:43 2011 >> New Revision: 134516 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134516&view=rev >> Log: >> Introduce "expect" intrinsic instructions. >> > > Hi Kuba, > > Why is this introducing a new pass to do lowering? > > -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/1d10d4b9/attachment.html From isanbard at gmail.com Thu Jul 7 15:48:32 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 13:48:32 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> Message-ID: Sorry. I'm trying to say that moving the method body out of line results in the same error, just in a different place. -bw On Jul 7, 2011, at 1:37 PM, Chris Lattner wrote: > What are you trying to say here? > > -Chris > > > On Jul 7, 2011, at 10:57 AM, Bill Wendling wrote: > >> >> n Jul 7, 2011, at 10:08 AM, Chris Lattner wrote: >> >>> On Jul 6, 2011, at 9:40 PM, Bill Wendling wrote: >>>>>> @@ -189,6 +190,14 @@ >>>>>> /// >>>>>> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >>>>>> } >>>>>> + >>>>>> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >>>>>> + /// function. Return 0 if the compact unwind isn't available. >>>>>> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >>>>>> + int /*DataAlignmentFactor*/, >>>>>> + bool /*IsEH*/) const { >>>>> >>>>> Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? >>>>> >>>> Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: >>>> /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function >>>> 'llvm::ArrayRef::ArrayRef' requested here >>>> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >>>> ^ >>> >>> Please move the method body out of line. Also, please forward declare ArrayRef too. >>> >> In file included from /Volumes/Sandbox/llvm/llvm.src/lib/Target/TargetAsmInfo.cpp:10: >> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:19: >> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:17: >> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineBasicBlock.h:17: >> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineInstr.h:28: >> In file included from /usr/include/c++/4.2.1/vector:69: >> /usr/include/c++/4.2.1/bits/stl_vector.h:493:41: error: arithmetic on a pointer to an incomplete type 'llvm::MCCFIInstruction' >> { return *(this->_M_impl._M_start + __n); } >> ~~~~~~~~~~~~~~~~~~~~~~ ^ >> /Volumes/Sandbox/llvm/llvm.src/include/llvm/ADT/ArrayRef.h:65:37: note: in instantiation of member function 'std::vector >::operator[]' requested >> here >> : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} >> ^ >> /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function 'llvm::ArrayRef::ArrayRef' requested here >> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >> ^ >> /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:24:9: note: forward declaration of 'llvm::MCCFIInstruction' >> class MCCFIInstruction; >> ^ >> >> >> -bw >> > From ahatanak at gmail.com Thu Jul 7 15:54:20 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 20:54:20 -0000 Subject: [llvm-commits] [llvm] r134637 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsAsmPrinter.h MipsInstrInfo.td Message-ID: <20110707205420.DBB5D2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 15:54:20 2011 New Revision: 134637 URL: http://llvm.org/viewvc/llvm-project?rev=134637&view=rev Log: Rather than having printMemOperand change the way memory operands are printed based on a modifier, split it into two functions. Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134637&r1=134636&r2=134637&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 15:54:20 2011 @@ -359,17 +359,7 @@ } void MipsAsmPrinter:: -printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier) { - // when using stack locations for not load/store instructions - // print the same way as all normal 3 operand instructions. - if (Modifier && !strcmp(Modifier, "stackloc")) { - printOperand(MI, opNum, O); - O << ", "; - printOperand(MI, opNum+1, O); - return; - } - +printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) @@ -380,6 +370,16 @@ } void MipsAsmPrinter:: +printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) { + // when using stack locations for not load/store instructions + // print the same way as all normal 3 operand instructions. + printOperand(MI, opNum, O); + O << ", "; + printOperand(MI, opNum+1, O); + return; +} + +void MipsAsmPrinter:: printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier) { const MachineOperand& MO = MI->getOperand(opNum); Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h?rev=134637&r1=134636&r2=134637&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h Thu Jul 7 15:54:20 2011 @@ -61,8 +61,8 @@ raw_ostream &O); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); - void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier = 0); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); void EmitStartOfAsmFile(Module &M); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=134637&r1=134636&r2=134637&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jul 7 15:54:20 2011 @@ -137,6 +137,11 @@ let MIOperandInfo = (ops CPURegs, simm16); } +def mem_ea : Operand { + let PrintMethod = "printMemOperandEA"; + let MIOperandInfo = (ops CPURegs, simm16); +} + // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXFormgetZExtValue() & 0xFFFF); @@ -351,7 +356,7 @@ !strconcat(instr_asm, "\t$src"), [], IIHiLo>; class EffectiveAddress : - FI<0x09, (outs CPURegs:$dst), (ins mem:$addr), + FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr), instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; // Count Leading Ones/Zeros in Word @@ -680,13 +685,13 @@ // instructions. The same not happens for stack address copies, so an // add op with mem ComplexPattern is used and the stack address copy // can be matched. It's similar to Sparc LEA_ADDRi -def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; +def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">; // DynAlloc node points to dynamically allocated stack space. // $sp is added to the list of implicitly used registers to prevent dead code // elimination from removing instructions that modify $sp. let Uses = [SP] in -def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; +def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">; // MADD*/MSUB* def MADD : MArithR<0, "madd", MipsMAdd, 1>; From clattner at apple.com Thu Jul 7 15:54:55 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 07 Jul 2011 13:54:55 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> Message-ID: <0C0CAD81-C1F1-489D-9123-479B186C1409@apple.com> It looks like exactly the same error. I'll be more specific. Please move the method at TargetAsmInfo.h:89 out of line and forward declare the dwarf stuff and ArrayRef. -Chris On Jul 7, 2011, at 1:48 PM, Bill Wendling wrote: > Sorry. I'm trying to say that moving the method body out of line results in the same error, just in a different place. > > -bw > > On Jul 7, 2011, at 1:37 PM, Chris Lattner wrote: > >> What are you trying to say here? >> >> -Chris >> >> >> On Jul 7, 2011, at 10:57 AM, Bill Wendling wrote: >> >>> >>> n Jul 7, 2011, at 10:08 AM, Chris Lattner wrote: >>> >>>> On Jul 6, 2011, at 9:40 PM, Bill Wendling wrote: >>>>>>> @@ -189,6 +190,14 @@ >>>>>>> /// >>>>>>> virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { >>>>>>> } >>>>>>> + >>>>>>> + /// getCompactUnwindEncoding - Get the compact unwind encoding for the >>>>>>> + /// function. Return 0 if the compact unwind isn't available. >>>>>>> + virtual uint32_t getCompactUnwindEncoding(const std::vector&, >>>>>>> + int /*DataAlignmentFactor*/, >>>>>>> + bool /*IsEH*/) const { >>>>>> >>>>>> Please put names on these arguments like other stuff in this file. Instead of taking a const vector, should this take an ArrayRef? >>>>>> >>>>> Okay. Then I had to have the #include "llvm/MC/MCDwarf.h" in there or I get these errors: >>>>> /Users/void/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function >>>>> 'llvm::ArrayRef::ArrayRef' requested here >>>>> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >>>>> ^ >>>> >>>> Please move the method body out of line. Also, please forward declare ArrayRef too. >>>> >>> In file included from /Volumes/Sandbox/llvm/llvm.src/lib/Target/TargetAsmInfo.cpp:10: >>> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:19: >>> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:17: >>> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineBasicBlock.h:17: >>> In file included from /Volumes/Sandbox/llvm/llvm.src/include/llvm/CodeGen/MachineInstr.h:28: >>> In file included from /usr/include/c++/4.2.1/vector:69: >>> /usr/include/c++/4.2.1/bits/stl_vector.h:493:41: error: arithmetic on a pointer to an incomplete type 'llvm::MCCFIInstruction' >>> { return *(this->_M_impl._M_start + __n); } >>> ~~~~~~~~~~~~~~~~~~~~~~ ^ >>> /Volumes/Sandbox/llvm/llvm.src/include/llvm/ADT/ArrayRef.h:65:37: note: in instantiation of member function 'std::vector >::operator[]' requested >>> here >>> : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} >>> ^ >>> /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetAsmInfo.h:89:42: note: in instantiation of member function 'llvm::ArrayRef::ArrayRef' requested here >>> return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); >>> ^ >>> /Volumes/Sandbox/llvm/llvm.src/include/llvm/Target/TargetFrameLowering.h:24:9: note: forward declaration of 'llvm::MCCFIInstruction' >>> class MCCFIInstruction; >>> ^ >>> >>> >>> -bw >>> >> > From isanbard at gmail.com Thu Jul 7 15:59:43 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 13:59:43 -0700 Subject: [llvm-commits] [llvm] r134577 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h include/llvm/Target/TargetFrameLowering.h lib/MC/MCDwarf.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h In-Reply-To: <0C0CAD81-C1F1-489D-9123-479B186C1409@apple.com> References: <20110707005413.494DB2A6C12C@llvm.org> <40C0D3D6-CC6B-4CE8-AB3B-FEE02C31E8B8@apple.com> <829C6328-CAF1-481E-8B49-E8C4F2C81366@apple.com> <19A9442B-632F-48F3-957F-7660E98A50F2@gmail.com> <0C0CAD81-C1F1-489D-9123-479B186C1409@apple.com> Message-ID: On Jul 7, 2011, at 1:54 PM, Chris Lattner wrote: > It looks like exactly the same error. I'll be more specific. Please move the method at TargetAsmInfo.h:89 out of line and forward declare the dwarf stuff and ArrayRef. > Chris, That's what I did. And I got that error. What you're asking doesn't appear to be possible. -bw From isanbard at gmail.com Thu Jul 7 16:05:13 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Jul 2011 21:05:13 -0000 Subject: [llvm-commits] [llvm] r134640 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/Target/TargetAsmInfo.cpp Message-ID: <20110707210513.49BD92A6C12C@llvm.org> Author: void Date: Thu Jul 7 16:05:13 2011 New Revision: 134640 URL: http://llvm.org/viewvc/llvm-project?rev=134640&view=rev Log: Move a function out-of-line. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/lib/Target/TargetAsmInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=134640&r1=134639&r2=134640&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Thu Jul 7 16:05:13 2011 @@ -20,6 +20,7 @@ #include "llvm/Target/TargetRegisterInfo.h" namespace llvm { + template class ArrayRef; class MCSection; class MCContext; class MachineFunction; @@ -84,10 +85,8 @@ return TLOF->isFunctionEHFrameSymbolPrivate(); } - int getCompactUnwindEncoding(const std::vector &Instrs, - int DataAlignmentFactor, bool IsEH) const { - return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); - } + int getCompactUnwindEncoding(ArrayRef Instrs, + int DataAlignmentFactor, bool IsEH) const; const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const { return TRI->getCalleeSavedRegs(MF); Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=134640&r1=134639&r2=134640&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Thu Jul 7 16:05:13 2011 @@ -26,3 +26,9 @@ TRI = TM.getRegisterInfo(); TFI->getInitialFrameState(InitialFrameState); } + +int TargetAsmInfo::getCompactUnwindEncoding(ArrayRef Instrs, + int DataAlignmentFactor, + bool IsEH) const { + return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); +} From evan.cheng at apple.com Thu Jul 7 16:06:52 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 21:06:52 -0000 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2010-04-08-CoalescerBug.ll test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll test/CodeGen/X86/memcpy.ll test/CodeGen/X86/tlv-1.ll Message-ID: <20110707210652.4C2222A6C12C@llvm.org> Author: evancheng Date: Thu Jul 7 16:06:52 2011 New Revision: 134641 URL: http://llvm.org/viewvc/llvm-project?rev=134641&view=rev Log: Add Mode64Bit feature and sink it down to MC layer. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h llvm/trunk/lib/Target/X86/X86.td llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll llvm/trunk/test/CodeGen/X86/memcpy.ll llvm/trunk/test/CodeGen/X86/tlv-1.ll Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 16:06:52 2011 @@ -16,6 +16,8 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Support/Host.h" #define GET_REGINFO_MC_DESC #include "X86GenRegisterInfo.inc" @@ -28,6 +30,104 @@ using namespace llvm; + +std::string X86_MC::ParseX86Triple(StringRef TT) { + Triple TheTriple(TT); + if (TheTriple.getArch() == Triple::x86_64) + return "+64bit-mode"; + return ""; +} + +/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the +/// specified arguments. If we can't run cpuid on the host, return true. +bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, + unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { +#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) + #if defined(__GNUC__) + // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. + asm ("movq\t%%rbx, %%rsi\n\t" + "cpuid\n\t" + "xchgq\t%%rbx, %%rsi\n\t" + : "=a" (*rEAX), + "=S" (*rEBX), + "=c" (*rECX), + "=d" (*rEDX) + : "a" (value)); + return false; + #elif defined(_MSC_VER) + int registers[4]; + __cpuid(registers, value); + *rEAX = registers[0]; + *rEBX = registers[1]; + *rECX = registers[2]; + *rEDX = registers[3]; + return false; + #endif +#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) + #if defined(__GNUC__) + asm ("movl\t%%ebx, %%esi\n\t" + "cpuid\n\t" + "xchgl\t%%ebx, %%esi\n\t" + : "=a" (*rEAX), + "=S" (*rEBX), + "=c" (*rECX), + "=d" (*rEDX) + : "a" (value)); + return false; + #elif defined(_MSC_VER) + __asm { + mov eax,value + cpuid + mov esi,rEAX + mov dword ptr [esi],eax + mov esi,rEBX + mov dword ptr [esi],ebx + mov esi,rECX + mov dword ptr [esi],ecx + mov esi,rEDX + mov dword ptr [esi],edx + } + return false; + #endif +#endif + return true; +} + +void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, + unsigned &Model) { + Family = (EAX >> 8) & 0xf; // Bits 8 - 11 + Model = (EAX >> 4) & 0xf; // Bits 4 - 7 + if (Family == 6 || Family == 0xf) { + if (Family == 0xf) + // Examine extended family ID if family ID is F. + Family += (EAX >> 20) & 0xff; // Bits 20 - 27 + // Examine extended model ID if family ID is 6 or F. + Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 + } +} + +static bool hasX86_64() { + // FIXME: Code duplication. See X86Subtarget::AutoDetectSubtargetFeatures. + unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; + union { + unsigned u[3]; + char c[12]; + } text; + + if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) + return false; + + bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; + bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; + if (IsIntel || IsAMD) { + X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); + if ((EDX >> 29) & 0x1) + return true; + } + + return false; +} + MCInstrInfo *createX86MCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitX86MCInstrInfo(X); @@ -42,8 +142,24 @@ MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { + std::string ArchFS = X86_MC::ParseX86Triple(TT); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS.str(); + else + ArchFS = FS; + } + + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = sys::getHostCPUName(); + + if (ArchFS.empty() && CPUName.empty() && hasX86_64()) + // Auto-detect if host is 64-bit capable, it's the default if true. + ArchFS = "+64bit-mode"; + MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X, CPU, FS); + InitX86MCSubtargetInfo(X, CPU, ArchFS); return X; } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 16:06:52 2011 @@ -14,10 +14,24 @@ #ifndef X86MCTARGETDESC_H #define X86MCTARGETDESC_H +#include + namespace llvm { class Target; +class StringRef; extern Target TheX86_32Target, TheX86_64Target; + +namespace X86_MC { + std::string ParseX86Triple(StringRef TT); + + /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in + /// the specified arguments. If we can't run cpuid on the host, return true. + bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, + unsigned *rEBX, unsigned *rECX, unsigned *rEDX); + + void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); +} } // End llvm namespace // Defines symbolic names for X86 registers. This defines a mapping from Modified: llvm/trunk/lib/Target/X86/X86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.td (original) +++ llvm/trunk/lib/Target/X86/X86.td Thu Jul 7 16:06:52 2011 @@ -17,6 +17,13 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// +// X86 Subtarget state. +// + +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", + "64-bit mode (x86_64)">; + +//===----------------------------------------------------------------------===// // X86 Subtarget features. //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 16:06:52 2011 @@ -158,7 +158,7 @@ /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls /// to immediate address. bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { - if (Is64Bit) + if (In64BitMode) return false; return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } @@ -174,73 +174,6 @@ return 200; } -/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the -/// specified arguments. If we can't run cpuid on the host, return true. -static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, - unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { -#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) - #if defined(__GNUC__) - // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. - asm ("movq\t%%rbx, %%rsi\n\t" - "cpuid\n\t" - "xchgq\t%%rbx, %%rsi\n\t" - : "=a" (*rEAX), - "=S" (*rEBX), - "=c" (*rECX), - "=d" (*rEDX) - : "a" (value)); - return false; - #elif defined(_MSC_VER) - int registers[4]; - __cpuid(registers, value); - *rEAX = registers[0]; - *rEBX = registers[1]; - *rECX = registers[2]; - *rEDX = registers[3]; - return false; - #endif -#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) - #if defined(__GNUC__) - asm ("movl\t%%ebx, %%esi\n\t" - "cpuid\n\t" - "xchgl\t%%ebx, %%esi\n\t" - : "=a" (*rEAX), - "=S" (*rEBX), - "=c" (*rECX), - "=d" (*rEDX) - : "a" (value)); - return false; - #elif defined(_MSC_VER) - __asm { - mov eax,value - cpuid - mov esi,rEAX - mov dword ptr [esi],eax - mov esi,rEBX - mov dword ptr [esi],ebx - mov esi,rECX - mov dword ptr [esi],ecx - mov esi,rEDX - mov dword ptr [esi],edx - } - return false; - #endif -#endif - return true; -} - -static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { - Family = (EAX >> 8) & 0xf; // Bits 8 - 11 - Model = (EAX >> 4) & 0xf; // Bits 4 - 7 - if (Family == 6 || Family == 0xf) { - if (Family == 0xf) - // Examine extended family ID if family ID is F. - Family += (EAX >> 20) & 0xff; // Bits 20 - 27 - // Examine extended model ID if family ID is 6 or F. - Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 - } -} - void X86Subtarget::AutoDetectSubtargetFeatures() { unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; union { @@ -248,10 +181,10 @@ char c[12]; } text; - if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) + if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) return; - GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); + X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); if ((EDX >> 15) & 1) HasCMov = true; if ((EDX >> 23) & 1) X86SSELevel = MMX; @@ -276,13 +209,13 @@ // Determine if bit test memory instructions are slow. unsigned Family = 0; unsigned Model = 0; - DetectFamilyModel(EAX, Family, Model); + X86_MC::DetectFamilyModel(EAX, Family, Model); IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13); // If it's Nehalem, unaligned memory access is fast. if (Family == 15 && Model == 26) IsUAMemFast = true; - GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); + X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); HasX86_64 = (EDX >> 29) & 0x1; HasSSE4A = IsAMD && ((ECX >> 6) & 0x1); HasFMA4 = IsAMD && ((ECX >> 16) & 0x1); @@ -291,7 +224,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, - bool is64Bit, unsigned StackAlignOverride) + unsigned StackAlignOverride) : X86GenSubtargetInfo(TT, CPU, FS) , PICStyle(PICStyles::None) , X86SSELevel(NoMMXSSE) @@ -312,15 +245,26 @@ // FIXME: this is a known good value for Yonah. How about others? , MaxInlineSizeThreshold(128) , TargetTriple(TT) - , Is64Bit(is64Bit) { + , In64BitMode(false) { + // Insert the architecture feature derived from the target triple into the + // feature string. This is important for setting features that are implied + // based on the architecture version. + std::string ArchFS = X86_MC::ParseX86Triple(TT); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS; + else + ArchFS = FS; + } + + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = sys::getHostCPUName(); // Determine default and user specified characteristics - if (!CPU.empty() || !FS.empty()) { + if (!CPUName.empty() || !ArchFS.empty()) { // If feature string is not empty, parse features string. - std::string CPUName = CPU; - if (CPUName.empty()) - CPUName = sys::getHostCPUName(); - ParseSubtargetFeatures(CPUName, FS); + ParseSubtargetFeatures(CPUName, ArchFS); // All X86-64 CPUs also have SSE2, however user might request no SSE via // -mattr, so don't force SSELevel here. if (HasAVX) @@ -328,14 +272,19 @@ } else { // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); + + // If CPU is 64-bit capable, default to 64-bit mode if not specified. + In64BitMode = HasX86_64; + // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. - if (Is64Bit && !HasAVX && X86SSELevel < SSE2) + if (In64BitMode && !HasAVX && X86SSELevel < SSE2) X86SSELevel = SSE2; } // If requesting codegen for X86-64, make sure that 64-bit features // are enabled. - if (Is64Bit) { + // FIXME: Remove this feature since it's not actually being used. + if (In64BitMode) { HasX86_64 = true; // All 64-bit cpus have cmov support. @@ -345,7 +294,7 @@ DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"); - assert((!Is64Bit || HasX86_64) && + assert((!In64BitMode || HasX86_64) && "64-bit code requested on a subtarget that doesn't support it!"); // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both @@ -353,6 +302,6 @@ if (StackAlignOverride) stackAlignment = StackAlignOverride; else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() || - isTargetSolaris() || Is64Bit) + isTargetSolaris() || In64BitMode) stackAlignment = 16; } Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Jul 7 16:06:52 2011 @@ -112,9 +112,8 @@ Triple TargetTriple; private: - /// Is64Bit - True if the processor supports 64-bit instructions and - /// pointer size is 64 bit. - bool Is64Bit; + /// In64BitMode - True if compiling for 64-bit, false for 32-bit. + bool In64BitMode; public: @@ -122,7 +121,7 @@ /// of the specified triple. /// X86Subtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool is64Bit, + const std::string &FS, unsigned StackAlignOverride); /// getStackAlignment - Returns the minimum alignment known to hold of the @@ -142,7 +141,7 @@ /// instruction. void AutoDetectSubtargetFeatures(); - bool is64Bit() const { return Is64Bit; } + bool is64Bit() const { return In64BitMode; } PICStyles::Style getPICStyle() const { return PICStyle; } void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } @@ -200,7 +199,7 @@ } bool isTargetWin64() const { - return Is64Bit && (isTargetMingw() || isTargetWindows()); + return In64BitMode && (isTargetMingw() || isTargetWindows()); } bool isTargetEnvMacho() const { @@ -208,7 +207,7 @@ } bool isTargetWin32() const { - return !Is64Bit && (isTargetMingw() || isTargetWindows()); + return !In64BitMode && (isTargetMingw() || isTargetWindows()); } bool isPICStyleSet() const { return PICStyle != PICStyles::None; } Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 16:06:52 2011 @@ -120,7 +120,7 @@ const std::string &CPU, const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT), - Subtarget(TT, CPU, FS, is64Bit, StackAlignmentOverride), + Subtarget(TT, CPU, FS, StackAlignmentOverride), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { DefRelocModel = getRelocationModel(); Modified: llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll Thu Jul 7 16:06:52 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; rdar://7842028 ; Do not delete partially dead copy instructions. Modified: llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll Thu Jul 7 16:06:52 2011 @@ -1,4 +1,4 @@ -; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic -disable-fp-elim < %s | FileCheck %s +; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s ; %struct.type = type { %struct.subtype*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* } Modified: llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Thu Jul 7 16:06:52 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s +; RUN: llc < %s -combiner-alias-analysis -march=x86-64 -mcpu=core2 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" Modified: llvm/trunk/test/CodeGen/X86/memcpy.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memcpy.ll?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/memcpy.ll (original) +++ llvm/trunk/test/CodeGen/X86/memcpy.ll Thu Jul 7 16:06:52 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=DARWIN declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/tlv-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tlv-1.ll?rev=134641&r1=134640&r2=134641&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tlv-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/tlv-1.ll Thu Jul 7 16:06:52 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin -mcpu=core2 | FileCheck %s %struct.A = type { [48 x i8], i32, i32, i32 } From mcrosier at apple.com Thu Jul 7 16:31:16 2011 From: mcrosier at apple.com (Chad Rosier) Date: Thu, 07 Jul 2011 14:31:16 -0700 Subject: [llvm-commits] [llvm] r134430 - /llvm/trunk/lib/Support/Unix/Path.inc In-Reply-To: <20110705201732.GD8569@britannica.bec.de> References: <20110705185531.F2B5B2A6C12C@llvm.org> <20110705201732.GD8569@britannica.bec.de> Message-ID: On Jul 5, 2011, at 1:17 PM, Joerg Sonnenberger wrote: > On Tue, Jul 05, 2011 at 06:55:31PM -0000, Chad Rosier wrote: >> Author: mcrosier >> Date: Tue Jul 5 13:55:31 2011 >> New Revision: 134430 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134430&view=rev >> Log: >> By default mkstemp() creates a temporary file with mode 0600, but the mode >> used for open is 0666. Therefore, add the necessary permission bits for >> consistency. >> rdar://8621462 >> >> Modified: >> llvm/trunk/lib/Support/Unix/Path.inc >> >> Modified: llvm/trunk/lib/Support/Unix/Path.inc >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Path.inc?rev=134430&r1=134429&r2=134430&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Support/Unix/Path.inc (original) >> +++ llvm/trunk/lib/Support/Unix/Path.inc Tue Jul 5 13:55:31 2011 >> @@ -842,6 +842,9 @@ >> >> // Save the name >> path = FNBuffer; >> + >> + // By default mkstemp sets the mode to 0600, so update mode bits now. >> + AddPermissionBits (*this, 0666); >> #elif defined(HAVE_MKTEMP) >> // If we don't have mkstemp, use the old and obsolete mktemp function. >> if (mktemp(FNBuffer) == 0) > > Isn't the correct approach the reverse? Make sure that all temporary > files use the least permissible bits? This change pertains to clang generated object files. It's really the file name that's temporary, not the file itself (if that make sense); it's common for the temporary file to be renamed to the desired final output. I'm not necessarily thrilled with the change myself, but I believe it to be an improvement over what we had. This was also done to conform to how gcc generates object files (i.e., what was being request in the radar). Chad > Joerg > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From pichet2000 at gmail.com Thu Jul 7 16:40:40 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Thu, 7 Jul 2011 17:40:40 -0400 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta Message-ID: On Thu, Jul 7, 2011 at 5:06 PM, Evan Cheng wrote: > Author: evancheng > Date: Thu Jul ?7 16:06:52 2011 > New Revision: 134641 > > URL: http://llvm.org/viewvc/llvm-project?rev=134641&view=rev > Log: > Add Mode64Bit feature and sink it down to MC layer. > > Modified: > ? ?llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > ? ?llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > ? ?llvm/trunk/lib/Target/X86/X86.td > ? ?llvm/trunk/lib/Target/X86/X86Subtarget.cpp > ? ?llvm/trunk/lib/Target/X86/X86Subtarget.h > ? ?llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > ? ?llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll > ? ?llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll > ? ?llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll > ? ?llvm/trunk/test/CodeGen/X86/memcpy.ll > ? ?llvm/trunk/test/CodeGen/X86/tlv-1.ll > hi, I am using CMake + MSVC and clang doesn't link anymore: 3>------ Build started: Project: clang, Configuration: Release Win32 ------ 3> Creating library C:/dev/llvm/llvm_trunk2/lib/Release/clang.lib and object C:/dev/llvm/llvm_trunk2/lib/Release/clang.exp 3>LLVMX86CodeGen.lib(X86Subtarget.obj) : error LNK2019: unresolved external symbol "void __cdecl llvm::X86_MC::DetectFamilyModel(unsigned int,unsigned int &,unsigned int &)" (?DetectFamilyModel at X86_MC@llvm@@YAXIAAI0 at Z) referenced in function "public: void __thiscall llvm::X86Subtarget::AutoDetectSubtargetFeatures(void)" (?AutoDetectSubtargetFeatures at X86Subtarget@llvm@@QAEXXZ) 3>LLVMX86CodeGen.lib(X86Subtarget.obj) : error LNK2019: unresolved external symbol "bool __cdecl llvm::X86_MC::GetCpuIDAndInfo(unsigned int,unsigned int *,unsigned int *,unsigned int *,unsigned int *)" (?GetCpuIDAndInfo at X86_MC@llvm@@YA_NIPAI000 at Z) referenced in function "public: void __thiscall llvm::X86Subtarget::AutoDetectSubtargetFeatures(void)" (?AutoDetectSubtargetFeatures at X86Subtarget@llvm@@QAEXXZ) 3>LLVMX86CodeGen.lib(X86Subtarget.obj) : error LNK2019: unresolved external symbol "class std::basic_string,class std::allocator > __cdecl llvm::X86_MC::ParseX86Triple(class llvm::StringRef)" (?ParseX86Triple at X86_MC@llvm@@YA?AV?$basic_string at DU?$char_traits at D@std@@V?$allocator at D@2@@std@@VStringRef at 2@@Z) referenced in function "public: __thiscall llvm::X86Subtarget::X86Subtarget(class std::basic_string,class std::allocator > const &,class std::basic_string,class std::allocator > const &,class std::basic_string,class std::allocator > const &,unsigned int)" (??0X86Subtarget at llvm@@QAE at ABV?$basic_string at DU?$char_traits at D@std@@V?$allocator at D@2@@std@@00I at Z) From dpatel at apple.com Thu Jul 7 16:44:42 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Jul 2011 21:44:42 -0000 Subject: [llvm-commits] [llvm] r134643 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110707214442.8A0A82A6C12C@llvm.org> Author: dpatel Date: Thu Jul 7 16:44:42 2011 New Revision: 134643 URL: http://llvm.org/viewvc/llvm-project?rev=134643&view=rev Log: Add DEBUG message. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134643&r1=134642&r2=134643&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jul 7 16:44:42 2011 @@ -1428,6 +1428,8 @@ SLabel = FunctionEndSym; else { const MachineInstr *End = HI[1]; + DEBUG(dbgs() << "DotDebugLoc Pair:\n" + << "\t" << *Begin << "\t" << *End << "\n"); if (End->isDebugValue()) SLabel = getLabelBeforeInsn(End); else { From ahatanak at gmail.com Thu Jul 7 17:06:18 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 22:06:18 -0000 Subject: [llvm-commits] [llvm] r134645 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20110707220618.BA8D32A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 17:06:18 2011 New Revision: 134645 URL: http://llvm.org/viewvc/llvm-project?rev=134645&view=rev Log: Remove unnecessary newline. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=134645&r1=134644&r2=134645&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jul 7 17:06:18 2011 @@ -424,7 +424,7 @@ // are used, we have the same behavior, but get also a bunch of warnings // from the assembler. def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>; -def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc\n", []>; +def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>; let usesCustomInserter = 1 in { def ATOMIC_LOAD_ADD_I8 : MipsPseudo< From echristo at apple.com Thu Jul 7 17:29:03 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 07 Jul 2011 22:29:03 -0000 Subject: [llvm-commits] [llvm] r134647 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110707222903.3D9522A6C12C@llvm.org> Author: echristo Date: Thu Jul 7 17:29:03 2011 New Revision: 134647 URL: http://llvm.org/viewvc/llvm-project?rev=134647&view=rev Log: Remove a FIXME. All of the standard ones are in the list. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134647&r1=134646&r2=134647&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jul 7 17:29:03 2011 @@ -2623,7 +2623,6 @@ TargetLowering::ConstraintType TargetLowering::getConstraintType(const std::string &Constraint) const { - // FIXME: lots more standard ones to handle. if (Constraint.size() == 1) { switch (Constraint[0]) { default: break; From echristo at apple.com Thu Jul 7 17:29:07 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 07 Jul 2011 22:29:07 -0000 Subject: [llvm-commits] [llvm] r134648 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/inline-asm.ll Message-ID: <20110707222907.6C4792A6C12D@llvm.org> Author: echristo Date: Thu Jul 7 17:29:07 2011 New Revision: 134648 URL: http://llvm.org/viewvc/llvm-project?rev=134648&view=rev Log: Add support for the X86 'l' constraint. Fixes PR10149 and rdar://9738585 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/inline-asm.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134648&r1=134647&r2=134648&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 7 17:29:07 2011 @@ -12592,6 +12592,7 @@ case 'y': case 'x': case 'Y': + case 'l': return C_RegisterClass; case 'a': case 'b': Modified: llvm/trunk/test/CodeGen/X86/inline-asm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm.ll?rev=134648&r1=134647&r2=134648&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm.ll Thu Jul 7 17:29:07 2011 @@ -23,3 +23,10 @@ tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind ret void } + +; rdar://9738585 +define i32 @test5() nounwind { +entry: + %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind + ret i32 0 +} From echristo at apple.com Thu Jul 7 17:54:12 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 07 Jul 2011 22:54:12 -0000 Subject: [llvm-commits] [llvm] r134653 - /llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp Message-ID: <20110707225412.9641E2A6C12C@llvm.org> Author: echristo Date: Thu Jul 7 17:54:12 2011 New Revision: 134653 URL: http://llvm.org/viewvc/llvm-project?rev=134653&view=rev Log: Handle fpcr register. Part of PR10299 and rdar://9740322 Modified: llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp?rev=134653&r1=134652&r2=134653&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp Thu Jul 7 17:54:12 2011 @@ -45,13 +45,14 @@ "{flags}", "", "{dirflag}", "", "{fpsr}", "", + "{fpcr}", "", "{cc}", "cc", 0,0}; X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &Triple) { AsmTransCBE = x86_asm_table; AssemblerDialect = AsmWriterFlavor; - + bool is64Bit = Triple.getArch() == Triple::x86_64; TextAlignFillValue = 0x90; From chandlerc at google.com Thu Jul 7 18:38:43 2011 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 7 Jul 2011 16:38:43 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: Message-ID: I'm looking into this... On Thu, Jul 7, 2011 at 2:40 PM, Francois Pichet wrote: > hi, > > I am using CMake + MSVC and clang doesn't link anymore: > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/b9b870c3/attachment.html From evan.cheng at apple.com Thu Jul 7 18:39:31 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 16:39:31 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: Message-ID: <39F1D573-7B46-4A20-BBA0-A77C9464801E@apple.com> Thanks. It's a cmake dependency issue that I know little about. Evan On Jul 7, 2011, at 4:38 PM, Chandler Carruth wrote: > I'm looking into this... > > On Thu, Jul 7, 2011 at 2:40 PM, Francois Pichet wrote: > hi, > > I am using CMake + MSVC and clang doesn't link anymore: > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/61f10500/attachment.html From chandlerc at gmail.com Thu Jul 7 18:45:45 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 07 Jul 2011 23:45:45 -0000 Subject: [llvm-commits] [llvm] r134658 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110707234545.2D9302A6C12C@llvm.org> Author: chandlerc Date: Thu Jul 7 18:45:45 2011 New Revision: 134658 URL: http://llvm.org/viewvc/llvm-project?rev=134658&view=rev Log: Fix CMake build's library dependencies. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=134658&r1=134657&r2=134658&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Thu Jul 7 18:45:45 2011 @@ -60,7 +60,7 @@ set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils) -set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Info LLVMX86Utils) +set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) From chandlerc at google.com Thu Jul 7 18:48:54 2011 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 7 Jul 2011 16:48:54 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <39F1D573-7B46-4A20-BBA0-A77C9464801E@apple.com> References: <39F1D573-7B46-4A20-BBA0-A77C9464801E@apple.com> Message-ID: Should be fixed in r134658. It's pretty easy to tell when this is needed... the LibDeps.txt that's part of llvm-config is different after a build. :: shrug :: I'm looking into a fix to the CMake build for LLVM that makes finding and fixing dependencies like this much much easier. On Thu, Jul 7, 2011 at 4:39 PM, Evan Cheng wrote: > Thanks. It's a cmake dependency issue that I know little about. > > Evan > > On Jul 7, 2011, at 4:38 PM, Chandler Carruth wrote: > > I'm looking into this... > > On Thu, Jul 7, 2011 at 2:40 PM, Francois Pichet wrote: > >> hi, >> >> I am using CMake + MSVC and clang doesn't link anymore: >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/7a67171a/attachment.html From ahatanak at gmail.com Thu Jul 7 18:56:50 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 07 Jul 2011 23:56:50 -0000 Subject: [llvm-commits] [llvm] r134661 - in /llvm/trunk/lib/Target/Mips: CMakeLists.txt InstPrinter/ InstPrinter/CMakeLists.txt InstPrinter/Makefile InstPrinter/MipsInstPrinter.cpp InstPrinter/MipsInstPrinter.h Makefile Mips.td MipsAsmPrinter.cpp MipsAsmPrinter.h MipsISelLowering.cpp MipsInstrInfo.cpp MipsInstrInfo.h MipsMCAsmInfo.cpp Message-ID: <20110707235651.0C3F62A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 18:56:50 2011 New Revision: 134661 URL: http://llvm.org/viewvc/llvm-project?rev=134661&view=rev Log: Lower MachineInstr to MC Inst and print to .s files. Added: llvm/trunk/lib/Target/Mips/InstPrinter/ llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/Mips/InstPrinter/Makefile llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/Mips/Makefile llvm/trunk/lib/Target/Mips/Mips.td llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jul 7 18:56:50 2011 @@ -26,4 +26,5 @@ MipsSelectionDAGInfo.cpp ) +add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) Added: llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt?rev=134661&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt Thu Jul 7 18:56:50 2011 @@ -0,0 +1,6 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMMipsAsmPrinter + MipsInstPrinter.cpp + ) +add_dependencies(LLVMMipsAsmPrinter MipsCodeGenTable_gen) Added: llvm/trunk/lib/Target/Mips/InstPrinter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/Makefile?rev=134661&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/Makefile (added) +++ llvm/trunk/lib/Target/Mips/InstPrinter/Makefile Thu Jul 7 18:56:50 2011 @@ -0,0 +1,16 @@ +##===- lib/Target/Mips/AsmPrinter/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMMipsAsmPrinter + +# Hack: we need to include 'main' arm target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common Added: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=134661&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (added) +++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Thu Jul 7 18:56:50 2011 @@ -0,0 +1,125 @@ +//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an Mips MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "asm-printer" +#include "MipsInstPrinter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/StringExtras.h" +using namespace llvm; + +#define GET_INSTRUCTION_NAME +#include "MipsGenAsmWriter.inc" + +const char* Mips::MipsFCCToString(Mips::CondCode CC) { + switch (CC) { + case FCOND_F: + case FCOND_T: return "f"; + case FCOND_UN: + case FCOND_OR: return "un"; + case FCOND_OEQ: + case FCOND_UNE: return "eq"; + case FCOND_UEQ: + case FCOND_ONE: return "ueq"; + case FCOND_OLT: + case FCOND_UGE: return "olt"; + case FCOND_ULT: + case FCOND_OGE: return "ult"; + case FCOND_OLE: + case FCOND_UGT: return "ole"; + case FCOND_ULE: + case FCOND_OGT: return "ule"; + case FCOND_SF: + case FCOND_ST: return "sf"; + case FCOND_NGLE: + case FCOND_GLE: return "ngle"; + case FCOND_SEQ: + case FCOND_SNE: return "seq"; + case FCOND_NGL: + case FCOND_GL: return "ngl"; + case FCOND_LT: + case FCOND_NLT: return "lt"; + case FCOND_NGE: + case FCOND_GE: return "nge"; + case FCOND_LE: + case FCOND_NLE: return "le"; + case FCOND_NGT: + case FCOND_GT: return "ngt"; + } +} + +StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const { + return getInstructionName(Opcode); +} + +void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << '$' << LowercaseString(getRegisterName(RegNo)); +} + +void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { + printInstruction(MI, O); +} + +void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + printRegName(O, Op.getReg()); + return; + } + + if (Op.isImm()) { + O << Op.getImm(); + return; + } + + assert(Op.isExpr() && "unknown operand kind in printOperand"); + O << *Op.getExpr(); +} + +void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(opNum); + if (MO.isImm()) + O << (unsigned short int)MO.getImm(); + else + printOperand(MI, opNum, O); +} + +void MipsInstPrinter:: +printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { + // Load/Store memory operands -- imm($reg) + // If PIC target the target is loaded as the + // pattern lw $25,%call16($28) + printOperand(MI, opNum+1, O); + O << "("; + printOperand(MI, opNum, O); + O << ")"; +} + +void MipsInstPrinter:: +printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) { + // when using stack locations for not load/store instructions + // print the same way as all normal 3 operand instructions. + printOperand(MI, opNum, O); + O << ", "; + printOperand(MI, opNum+1, O); + return; +} + +void MipsInstPrinter:: +printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} Added: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h?rev=134661&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h (added) +++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h Thu Jul 7 18:56:50 2011 @@ -0,0 +1,100 @@ +//===-- MipsInstPrinter.h - Convert Mips MCInst to assembly syntax ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints a Mips MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSINSTPRINTER_H +#define MIPSINSTPRINTER_H +#include "llvm/MC/MCInstPrinter.h" + +namespace llvm { +// These enumeration declarations were orignally in MipsInstrInfo.h but +// had to be moved here to avoid circular dependencies between +// LLVMMipsCodeGen and LLVMMipsAsmPrinter. +namespace Mips { +// Mips Branch Codes +enum FPBranchCode { + BRANCH_F, + BRANCH_T, + BRANCH_FL, + BRANCH_TL, + BRANCH_INVALID +}; + +// Mips Condition Codes +enum CondCode { + // To be used with float branch True + FCOND_F, + FCOND_UN, + FCOND_OEQ, + FCOND_UEQ, + FCOND_OLT, + FCOND_ULT, + FCOND_OLE, + FCOND_ULE, + FCOND_SF, + FCOND_NGLE, + FCOND_SEQ, + FCOND_NGL, + FCOND_LT, + FCOND_NGE, + FCOND_LE, + FCOND_NGT, + + // To be used with float branch False + // This conditions have the same mnemonic as the + // above ones, but are used with a branch False; + FCOND_T, + FCOND_OR, + FCOND_UNE, + FCOND_ONE, + FCOND_UGE, + FCOND_OGE, + FCOND_UGT, + FCOND_OGT, + FCOND_ST, + FCOND_GLE, + FCOND_SNE, + FCOND_GL, + FCOND_NLT, + FCOND_GE, + FCOND_NLE, + FCOND_GT +}; + +const char *MipsFCCToString(Mips::CondCode CC); +} // end namespace Mips + +class TargetMachine; + +class MipsInstPrinter : public MCInstPrinter { +public: + MipsInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, raw_ostream &O); + static const char *getInstructionName(unsigned Opcode); + static const char *getRegisterName(unsigned RegNo); + + virtual StringRef getOpcodeName(unsigned Opcode) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; + virtual void printInst(const MCInst *MI, raw_ostream &O); + +private: + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O); + void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); + void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); + void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O); +}; +} // end namespace llvm + +#endif Modified: llvm/trunk/lib/Target/Mips/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Makefile (original) +++ llvm/trunk/lib/Target/Mips/Makefile Thu Jul 7 18:56:50 2011 @@ -13,11 +13,11 @@ # Make sure that tblgen is run, first thing. BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ - MipsGenAsmWriter.inc \ + MipsGenAsmWriter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtargetInfo.inc -DIRS = TargetInfo +DIRS = InstPrinter TargetInfo include $(LEVEL)/Makefile.common Modified: llvm/trunk/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td (original) +++ llvm/trunk/lib/Target/Mips/Mips.td Thu Jul 7 18:56:50 2011 @@ -88,6 +88,14 @@ FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd, FeatureMinMax, FeatureSwap, FeatureBitCount]>; +def MipsAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + bit isMCAsmWriter = 1; +} + def Mips : Target { let InstructionSet = MipsInstrInfo; + + let AssemblyWriters = [MipsAsmWriter]; } + Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 18:56:50 2011 @@ -17,6 +17,8 @@ #include "Mips.h" #include "MipsInstrInfo.h" #include "MipsMachineFunction.h" +#include "MipsMCInstLower.h" +#include "InstPrinter/MipsInstPrinter.h" #include "llvm/BasicBlock.h" #include "llvm/Instructions.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -25,6 +27,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInst.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" @@ -39,8 +42,6 @@ using namespace llvm; -#include "MipsGenAsmWriter.inc" - void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream OS(Str); @@ -50,8 +51,10 @@ return; } - printInstruction(MI, OS); - OutStreamer.EmitRawText(OS.str()); + MipsMCInstLower MCInstLowering(Mang, *MF, *this); + MCInst TmpInst0; + MCInstLowering.Lower(MI, TmpInst0); + OutStreamer.EmitInstruction(TmpInst0); } //===----------------------------------------------------------------------===// @@ -168,9 +171,9 @@ unsigned stackSize = MF->getFrameInfo()->getStackSize(); OutStreamer.EmitRawText("\t.frame\t$" + - Twine(LowercaseString(getRegisterName(stackReg))) + - "," + Twine(stackSize) + ",$" + - Twine(LowercaseString(getRegisterName(returnReg)))); + Twine(LowercaseString(MipsInstPrinter::getRegisterName(stackReg))) + + "," + Twine(stackSize) + ",$" + + Twine(LowercaseString(MipsInstPrinter::getRegisterName(returnReg)))); } /// Emit Set directives. @@ -279,7 +282,7 @@ const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isReg() && "unexpected inline asm memory operand"); - O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")"; + O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")"; return false; } @@ -305,7 +308,8 @@ switch (MO.getType()) { case MachineOperand::MO_Register: - O << '$' << LowercaseString(getRegisterName(MO.getReg())); + O << '$' + << LowercaseString(MipsInstPrinter::getRegisterName(MO.getReg())); break; case MachineOperand::MO_Immediate: @@ -420,7 +424,17 @@ } // Force static initialization. +static MCInstPrinter *createMipsMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + return new MipsInstPrinter(MAI); +} + extern "C" void LLVMInitializeMipsAsmPrinter() { RegisterAsmPrinter X(TheMipsTarget); RegisterAsmPrinter Y(TheMipselTarget); + + TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, createMipsMCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(TheMipselTarget, + createMipsMCInstPrinter); } Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h Thu Jul 7 18:56:50 2011 @@ -39,10 +39,6 @@ return "Mips Assembly Printer"; } - // These two methods are autogen'd by tablegen. - void printInstruction(const MachineInstr *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - void EmitInstruction(const MachineInstr *MI); void printSavedRegsBitmask(raw_ostream &O); void printHex32(unsigned int Value, raw_ostream &O); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 7 18:56:50 2011 @@ -23,6 +23,7 @@ #include "llvm/GlobalVariable.h" #include "llvm/Intrinsics.h" #include "llvm/CallingConv.h" +#include "InstPrinter/MipsInstPrinter.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jul 7 18:56:50 2011 @@ -14,6 +14,7 @@ #include "MipsInstrInfo.h" #include "MipsTargetMachine.h" #include "MipsMachineFunction.h" +#include "InstPrinter/MipsInstPrinter.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -29,6 +30,11 @@ : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} + +const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const { + return RI; +} + static bool isZeroImm(const MachineOperand &op) { return op.isImm() && op.getImm() == 0; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Thu Jul 7 18:56:50 2011 @@ -25,100 +25,9 @@ namespace llvm { namespace Mips { - - // Mips Branch Codes - enum FPBranchCode { - BRANCH_F, - BRANCH_T, - BRANCH_FL, - BRANCH_TL, - BRANCH_INVALID - }; - - // Mips Condition Codes - enum CondCode { - // To be used with float branch True - FCOND_F, - FCOND_UN, - FCOND_OEQ, - FCOND_UEQ, - FCOND_OLT, - FCOND_ULT, - FCOND_OLE, - FCOND_ULE, - FCOND_SF, - FCOND_NGLE, - FCOND_SEQ, - FCOND_NGL, - FCOND_LT, - FCOND_NGE, - FCOND_LE, - FCOND_NGT, - - // To be used with float branch False - // This conditions have the same mnemonic as the - // above ones, but are used with a branch False; - FCOND_T, - FCOND_OR, - FCOND_UNE, - FCOND_ONE, - FCOND_UGE, - FCOND_OGE, - FCOND_UGT, - FCOND_OGT, - FCOND_ST, - FCOND_GLE, - FCOND_SNE, - FCOND_GL, - FCOND_NLT, - FCOND_GE, - FCOND_NLE, - FCOND_GT - }; - /// GetOppositeBranchOpc - Return the inverse of the specified /// opcode, e.g. turning BEQ to BNE. unsigned GetOppositeBranchOpc(unsigned Opc); - - /// MipsCCToString - Map each FP condition code to its string - inline static const char *MipsFCCToString(Mips::CondCode CC) - { - switch (CC) { - default: llvm_unreachable("Unknown condition code"); - case FCOND_F: - case FCOND_T: return "f"; - case FCOND_UN: - case FCOND_OR: return "un"; - case FCOND_OEQ: - case FCOND_UNE: return "eq"; - case FCOND_UEQ: - case FCOND_ONE: return "ueq"; - case FCOND_OLT: - case FCOND_UGE: return "olt"; - case FCOND_ULT: - case FCOND_OGE: return "ult"; - case FCOND_OLE: - case FCOND_UGT: return "ole"; - case FCOND_ULE: - case FCOND_OGT: return "ule"; - case FCOND_SF: - case FCOND_ST: return "sf"; - case FCOND_NGLE: - case FCOND_GLE: return "ngle"; - case FCOND_SEQ: - case FCOND_SNE: return "seq"; - case FCOND_NGL: - case FCOND_GL: return "ngl"; - case FCOND_LT: - case FCOND_NLT: return "lt"; - case FCOND_NGE: - case FCOND_GE: return "nge"; - case FCOND_LE: - case FCOND_NLE: return "le"; - case FCOND_NGT: - case FCOND_GT: return "ngt"; - } - } } /// MipsII - This namespace holds all of the target specific flags that @@ -177,7 +86,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; } + virtual const MipsRegisterInfo &getRegisterInfo() const; /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of Modified: llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp?rev=134661&r1=134660&r2=134661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp Thu Jul 7 18:56:50 2011 @@ -28,4 +28,5 @@ SupportsDebugInformation = true; ExceptionsType = ExceptionHandling::DwarfCFI; HasLEB128 = true; + DwarfRegNumForCFI = true; } From ofv at wanadoo.es Thu Jul 7 19:01:45 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 08 Jul 2011 02:01:45 +0200 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta References: <39F1D573-7B46-4A20-BBA0-A77C9464801E@apple.com> Message-ID: <87mxgpljx2.fsf@wanadoo.es> Chandler Carruth writes: > Should be fixed in r134658. > > It's pretty easy to tell when this is needed... the LibDeps.txt that's part > of llvm-config is different after a build. :: shrug :: > > I'm looking into a fix to the CMake build for LLVM that makes finding and > fixing dependencies like this much much easier. Unless you configured for building just a set of LLVM Targets, LLVMLibDeps.cmake is automatically updated after a build, a fact easy to spot with just a `svn st', which supposedly you will do for reviewing your changes before committing. I don't know what else could we do here. From nlewycky at google.com Thu Jul 7 19:04:36 2011 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 7 Jul 2011 17:04:36 -0700 Subject: [llvm-commits] patch: support float/double in 'q'/'Q' constraint on x86 Message-ID: Faced with an inline asm 'q' constraint, GCC appears to put floats in 32-bit ABCD registers and on x86_64 puts doubles in 64-bit ABCD registers. This patch replicates that behaviour. GCC also puts 64-bit doubles into 32-bit ABCD registers in 32-bit mode. This patch does not replicate that behaviour, preferring the current technique of issuing a backend error. Please review! Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/562a74c7/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: pr9602.patch Type: text/x-patch Size: 2012 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/562a74c7/attachment-0001.bin From echristo at apple.com Thu Jul 7 19:04:56 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 08 Jul 2011 00:04:56 -0000 Subject: [llvm-commits] [llvm] r134664 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/membarrier.ll Message-ID: <20110708000456.C16C62A6C12C@llvm.org> Author: echristo Date: Thu Jul 7 19:04:56 2011 New Revision: 134664 URL: http://llvm.org/viewvc/llvm-project?rev=134664&view=rev Log: Go ahead and emit the barrier on x86-64 even without sse2. The processor supports it just fine. Fixes PR9675 and rdar://9740801 Added: llvm/trunk/test/CodeGen/X86/membarrier.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134664&r1=134663&r2=134664&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 7 19:04:56 2011 @@ -9067,10 +9067,11 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ DebugLoc dl = Op.getDebugLoc(); - if (!Subtarget->hasSSE2()) { + // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. + // There isn't any reason to disable it if the target processor supports it. + if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { SDValue Chain = Op.getOperand(0); - SDValue Zero = DAG.getConstant(0, - Subtarget->is64Bit() ? MVT::i64 : MVT::i32); + SDValue Zero = DAG.getConstant(0, MVT::i32); SDValue Ops[] = { DAG.getRegister(X86::ESP, MVT::i32), // Base DAG.getTargetConstant(1, MVT::i8), // Scale Added: llvm/trunk/test/CodeGen/X86/membarrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/membarrier.ll?rev=134664&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/membarrier.ll (added) +++ llvm/trunk/test/CodeGen/X86/membarrier.ll Thu Jul 7 19:04:56 2011 @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86-64 -mattr=-sse -O0 +; PR9675 + +define i32 @t() { +entry: + %i = alloca i32, align 4 + store i32 1, i32* %i, align 4 + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1) + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret i32 0 +} + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind From echristo at apple.com Thu Jul 7 19:16:33 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 07 Jul 2011 17:16:33 -0700 Subject: [llvm-commits] patch: support float/double in 'q'/'Q' constraint on x86 In-Reply-To: References: Message-ID: On Jul 7, 2011, at 5:04 PM, Nick Lewycky wrote: > Faced with an inline asm 'q' constraint, GCC appears to put floats in 32-bit ABCD registers and on x86_64 puts doubles in 64-bit ABCD registers. This patch replicates that behaviour. GCC also puts 64-bit doubles into 32-bit ABCD registers in 32-bit mode. This patch does not replicate that behaviour, preferring the current technique of issuing a backend error. > > Please review! Two words: "Eeew" and "OK" Thanks! -eric From nicholas at mxc.ca Thu Jul 7 19:19:27 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 08 Jul 2011 00:19:27 -0000 Subject: [llvm-commits] [llvm] r134665 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/inline-asm-q-regs.ll Message-ID: <20110708001927.A50592A6C12C@llvm.org> Author: nicholas Date: Thu Jul 7 19:19:27 2011 New Revision: 134665 URL: http://llvm.org/viewvc/llvm-project?rev=134665&view=rev Log: Let the inline asm 'q' constraint match float, and on 64-bit double too. Fixes PR9602! Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134665&r1=134664&r2=134665&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 7 19:19:27 2011 @@ -12891,19 +12891,19 @@ // in the normal allocation? case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. if (Subtarget->is64Bit()) { - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::f32) return std::make_pair(0U, X86::GR32RegisterClass); else if (VT == MVT::i16) return std::make_pair(0U, X86::GR16RegisterClass); else if (VT == MVT::i8) return std::make_pair(0U, X86::GR8RegisterClass); - else if (VT == MVT::i64) + else if (VT == MVT::i64 || VT == MVT::f64) return std::make_pair(0U, X86::GR64RegisterClass); break; } // 32-bit fallthrough case 'Q': // Q_REGS - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::f32) return std::make_pair(0U, X86::GR32_ABCDRegisterClass); else if (VT == MVT::i16) return std::make_pair(0U, X86::GR16_ABCDRegisterClass); Modified: llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll?rev=134665&r1=134664&r2=134665&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll Thu Jul 7 19:19:27 2011 @@ -3,8 +3,20 @@ %0 = type { i64, i64, i64, i64, i64 } ; type %0 -define void @t() nounwind { +define void @test1() nounwind { entry: %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] ret void } + +; PR9602 +define void @test2(float %tmp) nounwind { + call void asm sideeffect "$0", "q"(float %tmp) nounwind + call void asm sideeffect "$0", "Q"(float %tmp) nounwind + ret void +} + +define void @test3(double %tmp) nounwind { + call void asm sideeffect "$0", "q"(double %tmp) nounwind + ret void +} From stoklund at 2pi.dk Thu Jul 7 19:24:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 08 Jul 2011 00:24:04 -0000 Subject: [llvm-commits] [llvm] r134666 - /llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll Message-ID: <20110708002404.0DBA92A6C12C@llvm.org> Author: stoklund Date: Thu Jul 7 19:24:03 2011 New Revision: 134666 URL: http://llvm.org/viewvc/llvm-project?rev=134666&view=rev Log: Remove a test that no longer makes sense. It was testing a linear scan feature: Test if linearscan is unfavoring registers for allocation to allow more reuse of reloads from stack slots. The greedy register allocator doesn't access any stack slots in this function, so the linear scan feature was not being tested. Removed: llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll Removed: llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll?rev=134665&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (removed) @@ -1,121 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 77 -; rdar://6802189 - -; Test if linearscan is unfavoring registers for allocation to allow more reuse -; of reloads from stack slots. - - %struct.SHA_CTX = type { i32, i32, i32, i32, i32, i32, i32, [16 x i32], i32 } - -define fastcc void @sha1_block_data_order(%struct.SHA_CTX* nocapture %c, i8* %p, i64 %num) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %asmtmp511 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; [#uses=3] - %asmtmp513 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; [#uses=2] - %asmtmp516 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; [#uses=1] - %asmtmp517 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; [#uses=2] - %0 = xor i32 0, %asmtmp513 ; [#uses=0] - %1 = add i32 0, %asmtmp517 ; [#uses=1] - %2 = add i32 %1, 0 ; [#uses=1] - %3 = add i32 %2, 0 ; [#uses=1] - %asmtmp519 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; [#uses=1] - %4 = xor i32 0, %asmtmp511 ; [#uses=1] - %asmtmp520 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %4) nounwind ; [#uses=2] - %5 = xor i32 0, %asmtmp516 ; [#uses=1] - %6 = xor i32 %5, %asmtmp519 ; [#uses=1] - %7 = add i32 %asmtmp513, -899497514 ; [#uses=1] - %8 = add i32 %7, %asmtmp520 ; [#uses=1] - %9 = add i32 %8, %6 ; [#uses=1] - %10 = add i32 %9, 0 ; [#uses=1] - %asmtmp523 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; [#uses=1] - %asmtmp525 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %3) nounwind ; [#uses=2] - %11 = xor i32 0, %asmtmp525 ; [#uses=1] - %12 = add i32 0, %11 ; [#uses=1] - %13 = add i32 %12, 0 ; [#uses=2] - %asmtmp528 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %10) nounwind ; [#uses=1] - %14 = xor i32 0, %asmtmp520 ; [#uses=1] - %asmtmp529 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %14) nounwind ; [#uses=1] - %asmtmp530 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %13) nounwind ; [#uses=1] - %15 = add i32 0, %asmtmp530 ; [#uses=1] - %16 = xor i32 0, %asmtmp523 ; [#uses=1] - %asmtmp532 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %16) nounwind ; [#uses=2] - %asmtmp533 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %15) nounwind ; [#uses=1] - %17 = xor i32 %13, %asmtmp528 ; [#uses=1] - %18 = xor i32 %17, 0 ; [#uses=1] - %19 = add i32 %asmtmp525, -899497514 ; [#uses=1] - %20 = add i32 %19, %asmtmp532 ; [#uses=1] - %21 = add i32 %20, %18 ; [#uses=1] - %22 = add i32 %21, %asmtmp533 ; [#uses=1] - %23 = xor i32 0, %asmtmp511 ; [#uses=1] - %24 = xor i32 %23, 0 ; [#uses=1] - %asmtmp535 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %24) nounwind ; [#uses=3] - %25 = add i32 0, %asmtmp535 ; [#uses=1] - %26 = add i32 %25, 0 ; [#uses=1] - %27 = add i32 %26, 0 ; [#uses=1] - %28 = xor i32 0, %asmtmp529 ; [#uses=0] - %29 = xor i32 %22, 0 ; [#uses=1] - %30 = xor i32 %29, 0 ; [#uses=1] - %31 = add i32 0, %30 ; [#uses=1] - %32 = add i32 %31, 0 ; [#uses=3] - %asmtmp541 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; [#uses=2] - %asmtmp542 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %32) nounwind ; [#uses=1] - %33 = add i32 0, %asmtmp541 ; [#uses=1] - %34 = add i32 %33, 0 ; [#uses=1] - %35 = add i32 %34, %asmtmp542 ; [#uses=1] - %asmtmp543 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %27) nounwind ; [#uses=2] - %36 = xor i32 0, %asmtmp535 ; [#uses=0] - %37 = xor i32 %32, 0 ; [#uses=1] - %38 = xor i32 %37, %asmtmp543 ; [#uses=1] - %39 = add i32 0, %38 ; [#uses=1] - %40 = add i32 %39, 0 ; [#uses=2] - %asmtmp546 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %32) nounwind ; [#uses=1] - %asmtmp547 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; [#uses=2] - %41 = add i32 0, -899497514 ; [#uses=1] - %42 = add i32 %41, %asmtmp547 ; [#uses=1] - %43 = add i32 %42, 0 ; [#uses=1] - %44 = add i32 %43, 0 ; [#uses=3] - %asmtmp549 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %35) nounwind ; [#uses=2] - %45 = xor i32 0, %asmtmp541 ; [#uses=1] - %asmtmp550 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %45) nounwind ; [#uses=2] - %asmtmp551 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %44) nounwind ; [#uses=1] - %46 = xor i32 %40, %asmtmp546 ; [#uses=1] - %47 = xor i32 %46, %asmtmp549 ; [#uses=1] - %48 = add i32 %asmtmp543, -899497514 ; [#uses=1] - %49 = add i32 %48, %asmtmp550 ; [#uses=1] - %50 = add i32 %49, %47 ; [#uses=1] - %51 = add i32 %50, %asmtmp551 ; [#uses=1] - %asmtmp552 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %40) nounwind ; [#uses=2] - %52 = xor i32 %44, %asmtmp549 ; [#uses=1] - %53 = xor i32 %52, %asmtmp552 ; [#uses=1] - %54 = add i32 0, %53 ; [#uses=1] - %55 = add i32 %54, 0 ; [#uses=2] - %asmtmp555 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %44) nounwind ; [#uses=2] - %56 = xor i32 0, %asmtmp532 ; [#uses=1] - %57 = xor i32 %56, %asmtmp547 ; [#uses=1] - %asmtmp556 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %57) nounwind ; [#uses=1] - %58 = add i32 0, %asmtmp556 ; [#uses=1] - %59 = add i32 %58, 0 ; [#uses=1] - %60 = add i32 %59, 0 ; [#uses=1] - %asmtmp558 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %51) nounwind ; [#uses=1] - %61 = xor i32 %asmtmp517, %asmtmp511 ; [#uses=1] - %62 = xor i32 %61, %asmtmp535 ; [#uses=1] - %63 = xor i32 %62, %asmtmp550 ; [#uses=1] - %asmtmp559 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %63) nounwind ; [#uses=1] - %64 = xor i32 %55, %asmtmp555 ; [#uses=1] - %65 = xor i32 %64, %asmtmp558 ; [#uses=1] - %asmtmp561 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %55) nounwind ; [#uses=1] - %66 = add i32 %asmtmp552, -899497514 ; [#uses=1] - %67 = add i32 %66, %65 ; [#uses=1] - %68 = add i32 %67, %asmtmp559 ; [#uses=1] - %69 = add i32 %68, 0 ; [#uses=1] - %70 = add i32 %69, 0 ; [#uses=1] - store i32 %70, i32* null, align 4 - %71 = add i32 0, %60 ; [#uses=1] - store i32 %71, i32* null, align 4 - %72 = add i32 0, %asmtmp561 ; [#uses=1] - store i32 %72, i32* null, align 4 - %73 = add i32 0, %asmtmp555 ; [#uses=1] - store i32 %73, i32* null, align 4 - br label %bb -} From stoklund at 2pi.dk Thu Jul 7 19:24:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 08 Jul 2011 00:24:06 -0000 Subject: [llvm-commits] [llvm] r134667 - in /llvm/trunk/test/CodeGen/Thumb2: 2010-06-14-NEONCoalescer.ll lsr-deficiency.ll machine-licm.ll Message-ID: <20110708002406.EC75C2A6C12D@llvm.org> Author: stoklund Date: Thu Jul 7 19:24:06 2011 New Revision: 134667 URL: http://llvm.org/viewvc/llvm-project?rev=134667&view=rev Log: Fix more register allocation sensitive tests. Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=134667&r1=134666&r2=134667&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Thu Jul 7 19:24:06 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 -disable-branch-fold | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" @@ -26,7 +26,7 @@ ; CHECK: vldr.64 [[LDR:d.*]], ; CHECK: LPC0_0: ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] -; CHECK: vmov.f64 [[LDR]] +; CHECK-NOT: vmov.f64 [[ADD]] %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] %tmp7 = extractelement <2 x double> %5, i32 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll?rev=134667&r1=134666&r2=134667&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll Thu Jul 7 19:24:06 2011 @@ -13,16 +13,16 @@ define void @t() nounwind optsize { ; CHECK: t: -; CHECK: mov.w r2, #1000 +; CHECK: mov{{.*}}, #1000 entry: %.pre = load i32* @G, align 4 ; [#uses=1] br label %bb bb: ; preds = %bb, %entry ; CHECK: LBB0_1: -; CHECK: cmp r2, #0 -; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1 -; CHECK: mov r2, [[REGISTER]] +; CHECK: cmp [[R2:r[0-9]+]], #0 +; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1 +; CHECK: mov [[R2]], [[REGISTER]] %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; [#uses=1] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=2] Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=134667&r1=134666&r2=134667&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Thu Jul 7 19:24:06 2011 @@ -52,8 +52,8 @@ define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: ; CHECK: t2: -; CHECK: mov.w r3, #1065353216 -; CHECK: vdup.32 q{{.*}}, r3 +; CHECK: mov.w [[R3:r[0-9]+]], #1065353216 +; CHECK: vdup.32 q{{.*}}, [[R3]] br i1 undef, label %bb1, label %bb2 bb1: From ahatanak at gmail.com Thu Jul 7 19:26:26 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Fri, 08 Jul 2011 00:26:26 -0000 Subject: [llvm-commits] [llvm] r134668 - /llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Message-ID: <20110708002626.1404A2A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 19:26:25 2011 New Revision: 134668 URL: http://llvm.org/viewvc/llvm-project?rev=134668&view=rev Log: Make sure variable Kind is assigned a value to suppress warning. Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=134668&r1=134667&r2=134668&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Thu Jul 7 19:26:25 2011 @@ -35,7 +35,7 @@ int Offset = 0; switch(MO.getTargetFlags()) { - case MipsII::MO_NO_FLAG: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; + default: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; case MipsII::MO_GPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GPREL; break; case MipsII::MO_GOT_CALL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_CALL; break; case MipsII::MO_GOT: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT; break; From ahatanak at gmail.com Thu Jul 7 19:42:35 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Fri, 08 Jul 2011 00:42:35 -0000 Subject: [llvm-commits] [llvm] r134671 - /llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Message-ID: <20110708004235.C3F922A6C12C@llvm.org> Author: ahatanak Date: Thu Jul 7 19:42:35 2011 New Revision: 134671 URL: http://llvm.org/viewvc/llvm-project?rev=134671&view=rev Log: Raise assertion when MachineOperand has unexpected target flag. Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=134671&r1=134670&r2=134671&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Thu Jul 7 19:42:35 2011 @@ -35,7 +35,8 @@ int Offset = 0; switch(MO.getTargetFlags()) { - default: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; + default: assert(0 && "Invalid target flag!"); + case MipsII::MO_NO_FLAG: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; case MipsII::MO_GPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GPREL; break; case MipsII::MO_GOT_CALL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_CALL; break; case MipsII::MO_GOT: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT; break; From lhames at gmail.com Thu Jul 7 20:50:54 2011 From: lhames at gmail.com (Lang Hames) Date: Fri, 08 Jul 2011 01:50:54 -0000 Subject: [llvm-commits] [llvm] r134677 - in /llvm/trunk: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Message-ID: <20110708015054.CBE162A6C12C@llvm.org> Author: lhames Date: Thu Jul 7 20:50:54 2011 New Revision: 134677 URL: http://llvm.org/viewvc/llvm-project?rev=134677&view=rev Log: Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics. Added: llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=134677&r1=134676&r2=134677&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Jul 7 20:50:54 2011 @@ -91,6 +91,7 @@ uint32_t nextValueNumber; Expression create_expression(Instruction* I); + Expression create_extractvalue_expression(ExtractValueInst* EI); uint32_t lookup_or_add_call(CallInst* C); public: ValueTable() : nextValueNumber(1) { } @@ -141,7 +142,6 @@ // ValueTable Internal Functions //===----------------------------------------------------------------------===// - Expression ValueTable::create_expression(Instruction *I) { Expression e; e.type = I->getType(); @@ -150,12 +150,8 @@ OI != OE; ++OI) e.varargs.push_back(lookup_or_add(*OI)); - if (CmpInst *C = dyn_cast(I)) + if (CmpInst *C = dyn_cast(I)) { e.opcode = (C->getOpcode() << 8) | C->getPredicate(); - else if (ExtractValueInst *E = dyn_cast(I)) { - for (ExtractValueInst::idx_iterator II = E->idx_begin(), IE = E->idx_end(); - II != IE; ++II) - e.varargs.push_back(*II); } else if (InsertValueInst *E = dyn_cast(I)) { for (InsertValueInst::idx_iterator II = E->idx_begin(), IE = E->idx_end(); II != IE; ++II) @@ -165,6 +161,55 @@ return e; } +Expression ValueTable::create_extractvalue_expression(ExtractValueInst *EI) { + assert(EI != 0 && "Not an ExtractValueInst?"); + Expression e; + e.type = EI->getType(); + e.opcode = 0; + + IntrinsicInst *I = dyn_cast(EI->getAggregateOperand()); + if (I != 0 && EI->getNumIndices() == 1 && *EI->idx_begin() == 0 ) { + // EI might be an extract from one of our recognised intrinsics. If it + // is we'll synthesize a semantically equivalent expression instead on + // an extract value expression. + switch (I->getIntrinsicID()) { + case Intrinsic::uadd_with_overflow: + e.opcode = Instruction::Add; + break; + case Intrinsic::usub_with_overflow: + e.opcode = Instruction::Sub; + break; + case Intrinsic::umul_with_overflow: + e.opcode = Instruction::Mul; + break; + default: + break; + } + + if (e.opcode != 0) { + // Intrinsic recognized. Grab its args to finish building the expression. + assert(I->getNumArgOperands() == 2 && + "Expect two args for recognised intrinsics."); + e.varargs.push_back(lookup_or_add(I->getArgOperand(0))); + e.varargs.push_back(lookup_or_add(I->getArgOperand(1))); + return e; + } + } + + // Not a recognised intrinsic. Fall back to producing an extract value + // expression. + e.opcode = EI->getOpcode(); + for (Instruction::op_iterator OI = EI->op_begin(), OE = EI->op_end(); + OI != OE; ++OI) + e.varargs.push_back(lookup_or_add(*OI)); + + for (ExtractValueInst::idx_iterator II = EI->idx_begin(), IE = EI->idx_end(); + II != IE; ++II) + e.varargs.push_back(*II); + + return e; +} + //===----------------------------------------------------------------------===// // ValueTable External Functions //===----------------------------------------------------------------------===// @@ -336,11 +381,13 @@ case Instruction::ExtractElement: case Instruction::InsertElement: case Instruction::ShuffleVector: - case Instruction::ExtractValue: case Instruction::InsertValue: case Instruction::GetElementPtr: exp = create_expression(I); break; + case Instruction::ExtractValue: + exp = create_extractvalue_expression(cast(I)); + break; default: valueNumbering[V] = nextValueNumber; return nextValueNumber++; Added: llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll?rev=134677&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll (added) +++ llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Thu Jul 7 20:50:54 2011 @@ -0,0 +1,47 @@ +; RUN: opt < %s -gvn -S | FileCheck %s +; + +%0 = type { i64, i1 } + +define i64 @test1(i64 %a, i64 %b) nounwind ssp { +entry: + %uadd = tail call %0 @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) + %uadd.0 = extractvalue %0 %uadd, 0 + %add1 = add i64 %a, %b + ret i64 %add1 +} + +; CHECK: @test1 +; CHECK-NOT: add1 +; CHECK: ret + +define i64 @test2(i64 %a, i64 %b) nounwind ssp { +entry: + %usub = tail call %0 @llvm.usub.with.overflow.i64(i64 %a, i64 %b) + %usub.0 = extractvalue %0 %usub, 0 + %sub1 = sub i64 %a, %b + ret i64 %sub1 +} + +; CHECK: @test2 +; CHECK-NOT: sub1 +; CHECK: ret + +define i64 @test3(i64 %a, i64 %b) nounwind ssp { +entry: + %umul = tail call %0 @llvm.umul.with.overflow.i64(i64 %a, i64 %b) + %umul.0 = extractvalue %0 %umul, 0 + %mul1 = mul i64 %a, %b + ret i64 %mul1 +} + +; CHECK: @test3 +; CHECK-NOT: mul1 +; CHECK: ret + + +declare void @exit(i32) noreturn +declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone +declare %0 @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone +declare %0 @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone + From evan.cheng at apple.com Thu Jul 7 20:53:10 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 01:53:10 -0000 Subject: [llvm-commits] [llvm] r134678 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/AsmParser/ lib/Targe... Message-ID: <20110708015311.8FE762A6C12C@llvm.org> Author: evancheng Date: Thu Jul 7 20:53:10 2011 New Revision: 134678 URL: http://llvm.org/viewvc/llvm-project?rev=134678&view=rev Log: Eliminate asm parser's dependency on TargetMachine: - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/CBackend/CTargetMachine.h llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011 @@ -382,6 +382,15 @@ /// matcher, this is true. Targets should set this by inheriting their /// feature from the AssemblerPredicate class in addition to Predicate. bit AssemblerMatcherPredicate = 0; + + /// AssemblerCondString - Name of the subtarget feature being tested used + /// as alternative condition string used for assembler matcher. + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". + /// It can also list multiple features separated by ",". + /// e.g. "ModeThumb,FeatureThumb2" is translated to + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". + string AssemblerCondString = ""; } /// NoHonorSignDependentRounding - This predicate is true if support for @@ -689,8 +698,9 @@ /// AssemblerPredicate - This is a Predicate that can be used when the assembler /// matches instructions and aliases. -class AssemblerPredicate { +class AssemblerPredicate { bit AssemblerMatcherPredicate = 1; + string AssemblerCondString = cond; } Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 2011 @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H +#include "llvm/ADT/StringRef.h" #include #include @@ -91,7 +92,8 @@ TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT void operator=(const TargetMachine &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetMachine(const Target &); + TargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS); /// getSubtargetImpl - virtual method implemented by subclasses that returns /// a reference to that target's TargetSubtargetInfo-derived member variable. @@ -100,6 +102,12 @@ /// TheTarget - The Target that this machine was created for. const Target &TheTarget; + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target + /// feature strings the TargetMachine instance is created with. + std::string TargetTriple; + std::string TargetCPU; + std::string TargetFS; + /// AsmInfo - Contains target specific asm information. /// const MCAsmInfo *AsmInfo; @@ -115,6 +123,10 @@ const Target &getTarget() const { return TheTarget; } + const StringRef getTargetTriple() const { return TargetTriple; } + const StringRef getTargetCPU() const { return TargetCPU; } + const StringRef getTargetFeatureString() const { return TargetFS; } + // Interfaces to the major aspects of target machine information: // -- Instruction opcode and operand information // -- Pipelines and scheduling information @@ -295,10 +307,9 @@ /// implemented with the LLVM target-independent code generator. /// class LLVMTargetMachine : public TargetMachine { - std::string TargetTriple; - protected: // Can only create subclasses. - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); + LLVMTargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS); private: /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for @@ -311,9 +322,6 @@ virtual void setCodeModelForStatic(); public: - - const std::string &getTargetTriple() const { return TargetTriple; } - /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code /// generation. If OptLevel is None, the code generator should emit code as Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 2011 @@ -35,7 +35,6 @@ class MCInstPrinter; class MCInstrInfo; class MCRegisterInfo; - class MCSubtargetInfo; class MCStreamer; class TargetAsmBackend; class TargetAsmLexer; @@ -70,9 +69,6 @@ StringRef TT); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, - StringRef CPU, - StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, const std::string &CPU, @@ -83,8 +79,9 @@ const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P, - TargetMachine &TM); + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT, + StringRef CPU, StringRef Features, + MCAsmParser &P); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, unsigned SyntaxVariant, @@ -140,10 +137,6 @@ /// if registered. MCRegInfoCtorFnTy MCRegInfoCtorFn; - /// MCSubtargetInfoCtorFn - Constructor function for this target's - /// MCSubtargetInfo, if registered. - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; - /// TargetMachineCtorFn - Construction function for this target's /// TargetMachine, if registered. TargetMachineCtorTy TargetMachineCtorFn; @@ -269,22 +262,6 @@ return MCRegInfoCtorFn(); } - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. - /// - /// \arg Triple - This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. - /// \arg CPU - This specifies the name of the target CPU. - /// \arg Features - This specifies the string representation of the - /// additional target features. - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, - StringRef Features) const { - if (!MCSubtargetInfoCtorFn) - return 0; - return MCSubtargetInfoCtorFn(Triple, CPU, Features); - } - /// createTargetMachine - Create a target specific machine implementation /// for the specified \arg Triple. /// @@ -322,11 +299,11 @@ /// /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. - TargetAsmParser *createAsmParser(MCAsmParser &Parser, - TargetMachine &TM) const { + TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, + StringRef Features, MCAsmParser &Parser) const { if (!AsmParserCtorFn) return 0; - return AsmParserCtorFn(*this, Parser, TM); + return AsmParserCtorFn(*this, Triple, CPU, Features, Parser); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -528,22 +505,6 @@ T.MCRegInfoCtorFn = Fn; } - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for - /// the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCSubtargetInfo for the target. - static void RegisterMCSubtargetInfo(Target &T, - Target::MCSubtargetInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCSubtargetInfoCtorFn) - T.MCSubtargetInfoCtorFn = Fn; - } - /// RegisterTargetMachine - Register a TargetMachine implementation for the /// given target. /// @@ -820,40 +781,6 @@ } }; - /// RegisterMCSubtargetInfo - Helper template for registering a target - /// subtarget info implementation. This invokes the static "Create" method - /// on the class to actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCSubtargetInfo X(TheFooTarget); - /// } - template - struct RegisterMCSubtargetInfo { - RegisterMCSubtargetInfo(Target &T) { - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); - } - private: - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, - StringRef FS) { - return new MCSubtargetInfoImpl(); - } - }; - - /// RegisterMCSubtargetInfoFn - Helper template for registering a target - /// subtarget info implementation. This invokes the specified function to - /// do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCSubtargetInfoFn { - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCSubtargetInfo(T, Fn); - } - }; - /// RegisterTargetMachine - Helper template for registering a target machine /// implementation, for use in the target machine initialization /// function. Usage: @@ -931,9 +858,10 @@ } private: - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, - TargetMachine &TM) { - return new AsmParserImpl(T, P, TM); + static TargetAsmParser *Allocator(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + MCAsmParser &P) { + return new AsmParserImpl(T, TT, CPU, FS, P); } }; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 20:53:10 2011 @@ -111,7 +111,12 @@ OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI)); - OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, TM)); + + OwningPtr + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), + TM.getTargetCPU(), + TM.getTargetFeatureString(), + *Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -98,10 +98,10 @@ EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector")); -LLVMTargetMachine::LLVMTargetMachine(const Target &T, - const std::string &Triple) - : TargetMachine(T), TargetTriple(Triple) { - AsmInfo = T.createAsmInfo(TargetTriple); +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, + StringRef CPU, StringRef FS) + : TargetMachine(T, Triple, CPU, FS) { + AsmInfo = T.createAsmInfo(Triple); } // Set the default code model for the JIT for a generic target. @@ -143,7 +143,7 @@ TargetAsmBackend *TAB = 0; if (ShowMCEncoding) { MCE = getTarget().createCodeEmitter(*this, *Context); - TAB = getTarget().createAsmBackend(TargetTriple); + TAB = getTarget().createAsmBackend(getTargetTriple()); } MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, @@ -160,12 +160,12 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context, - *TAB, Out, MCE, + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), + *Context, *TAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); AsmStreamer.get()->InitSections(); @@ -241,12 +241,12 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; OwningPtr AsmStreamer; - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx, + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx, *TAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 20:53:10 2011 @@ -171,7 +171,7 @@ std::string featureString; TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, featureString)); - + const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); if (!registerInfo) @@ -183,7 +183,7 @@ if (!AsmInfo) return; - + Disassembler.reset(Tgt->createMCDisassembler()); if (!Disassembler) @@ -371,8 +371,10 @@ OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo)); - OwningPtr TargetParser(Tgt->createAsmParser(*genericParser, - *TargetMachine)); + + StringRef triple = tripleFromArch(Key.Arch); + OwningPtr TargetParser(Tgt->createAsmParser(triple, "", "", + *genericParser)); AsmToken OpcodeToken = genericParser->Lex(); AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 2011 @@ -41,6 +41,7 @@ class MCInst; class MCParsedAsmOperand; class MCStreamer; +class MCSubtargetInfo; template class SmallVectorImpl; class SourceMgr; class Target; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011 @@ -147,35 +147,48 @@ //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate; +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, + AssemblerPredicate<"HasV4TOps">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">; -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate; -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate; +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, + AssemblerPredicate<"HasV5TEOps">; +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, + AssemblerPredicate<"HasV6Ops">; def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate; +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, + AssemblerPredicate<"HasV6T2Ops">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate; +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, + AssemblerPredicate<"HasV7Ops">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate; -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate; -def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate; -def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate; -def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate; +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, + AssemblerPredicate<"FeatureVFP2">; +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, + AssemblerPredicate<"FeatureVFP3">; +def HasNEON : Predicate<"Subtarget->hasNEON()">, + AssemblerPredicate<"FeatureNEON">; +def HasFP16 : Predicate<"Subtarget->hasFP16()">, + AssemblerPredicate<"FeatureFP16">; +def HasDivide : Predicate<"Subtarget->hasDivide()">, + AssemblerPredicate<"FeatureHWDiv">; def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureT2XtPk">; def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureDSPThumb2">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureDB">; def HasMP : Predicate<"Subtarget->hasMPExtension()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureMP">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; -def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate; +def IsThumb : Predicate<"Subtarget->isThumb()">, + AssemblerPredicate<"ModeThumb">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate; -def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate; +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, + AssemblerPredicate<"ModeThumb,FeatureThumb2">; +def IsARM : Predicate<"!Subtarget->isThumb()">, + AssemblerPredicate<"!ModeThumb">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -18,9 +18,10 @@ #include "llvm/Support/CommandLine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "ARMGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -80,7 +80,7 @@ const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 20:53:10 2011 @@ -20,6 +20,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Support/SourceMgr.h" @@ -28,6 +29,10 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + using namespace llvm; namespace { @@ -36,7 +41,7 @@ class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; + MCSubtargetInfo *STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -79,6 +84,15 @@ void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode); + bool isThumb() const { + // FIXME: Can tablegen auto-generate this? + return (STI->getFeatureBits() & ARM::ModeThumb) != 0; + } + + bool isThumbOne() const { + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; + } + /// @name Auto-generated Match Functions /// { @@ -113,13 +127,15 @@ const SmallVectorImpl &); public: - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) - : TargetAsmParser(T), Parser(_Parser), TM(_TM) { - MCAsmParserExtension::Initialize(_Parser); - // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures( - &TM.getSubtarget())); - } + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &_Parser) + : TargetAsmParser(T), Parser(_Parser) { + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); + + MCAsmParserExtension::Initialize(_Parser); + // Initialize the set of available features. + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + } virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); @@ -1852,9 +1868,6 @@ void ARMAsmParser:: GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { - bool isThumbOne = TM.getSubtarget().isThumb1Only(); - bool isThumb = TM.getSubtarget().isThumb(); - if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || @@ -1863,7 +1876,7 @@ Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || Mnemonic == "eor" || Mnemonic == "smlal" || - (Mnemonic == "mov" && !isThumbOne)) { + (Mnemonic == "mov" && !isThumbOne())) { CanAcceptCarrySet = true; } else { CanAcceptCarrySet = false; @@ -1880,7 +1893,7 @@ CanAcceptPredicationCode = true; } - if (isThumb) + if (isThumb()) if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") CanAcceptPredicationCode = false; @@ -2207,12 +2220,12 @@ // includes Feature_IsThumb or not to match the right instructions. This is // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. if (Val == 16){ - assert(TM.getSubtarget().isThumb() && + assert(isThumb() && "switching between arm/thumb not yet suppported via .code 16)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); } else{ - assert(!TM.getSubtarget().isThumb() && + assert(!isThumb() && "switching between thumb/arm not yet suppported via .code 32)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 20:53:10 2011 @@ -23,65 +23,12 @@ #define GET_INSTRINFO_MC_DESC #include "ARMGenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #include "ARMGenSubtargetInfo.inc" using namespace llvm; -MCInstrInfo *createARMMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitARMMCInstrInfo(X); - return X; -} - -MCRegisterInfo *createARMMCRegisterInfo() { - MCRegisterInfo *X = new MCRegisterInfo(); - InitARMMCRegisterInfo(X); - return X; -} - -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - std::string ArchFS = ARM_MC::ParseARMTriple(TT); - if (!FS.empty()) { - if (!ArchFS.empty()) - ArchFS = ArchFS + "," + FS.str(); - else - ArchFS = FS; - } - - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitARMMCSubtargetInfo(X, CPU, ArchFS); - return X; -} - -// Force static initialization. -extern "C" void LLVMInitializeARMMCInstrInfo() { - RegisterMCInstrInfo X(TheARMTarget); - RegisterMCInstrInfo Y(TheThumbTarget); - - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); -} - -extern "C" void LLVMInitializeARMMCRegInfo() { - RegisterMCRegInfo X(TheARMTarget); - RegisterMCRegInfo Y(TheThumbTarget); - - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); -} - -extern "C" void LLVMInitializeARMMCSubtargetInfo() { - RegisterMCSubtargetInfo X(TheARMTarget); - RegisterMCSubtargetInfo Y(TheThumbTarget); - - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, - createARMMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, - createARMMCSubtargetInfo); -} - std::string ARM_MC::ParseARMTriple(StringRef TT) { // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. @@ -135,3 +82,47 @@ return ARMArchFeature; } + +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + std::string ArchFS = ARM_MC::ParseARMTriple(TT); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS.str(); + else + ArchFS = FS; + } + + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitARMMCSubtargetInfo(X, CPU, ArchFS); + return X; +} + +MCInstrInfo *createARMMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitARMMCInstrInfo(X); + return X; +} + +MCRegisterInfo *createARMMCRegisterInfo() { + MCRegisterInfo *X = new MCRegisterInfo(); + InitARMMCRegisterInfo(X); + return X; +} + +// Force static initialization. +extern "C" void LLVMInitializeARMMCInstrInfo() { + RegisterMCInstrInfo X(TheARMTarget); + RegisterMCInstrInfo Y(TheThumbTarget); + + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); +} + +extern "C" void LLVMInitializeARMMCRegInfo() { + RegisterMCRegInfo X(TheARMTarget); + RegisterMCRegInfo Y(TheThumbTarget); + + TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); +} Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 20:53:10 2011 @@ -17,6 +17,7 @@ #include namespace llvm { +class MCSubtargetInfo; class Target; class StringRef; @@ -24,6 +25,12 @@ namespace ARM_MC { std::string ParseARMTriple(StringRef TT); + + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. + /// This is exposed so Asm parser, etc. do not need to go through + /// TargetRegistry. + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS); } } // End llvm namespace Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -14,9 +14,10 @@ #include "AlphaSubtarget.h" #include "Alpha.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "AlphaGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -27,7 +27,7 @@ AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -13,9 +13,10 @@ #include "BlackfinSubtarget.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "BlackfinGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -28,7 +28,7 @@ const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 2011 @@ -22,7 +22,7 @@ struct CTargetMachine : public TargetMachine { CTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : TargetMachine(T) {} + : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -13,12 +13,13 @@ #include "SPUSubtarget.h" #include "SPU.h" -#include "llvm/ADT/SmallVector.h" #include "SPURegisterInfo.h" +#include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SPUGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -36,7 +36,7 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, const std::string &CPU,const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 20:53:10 2011 @@ -24,7 +24,7 @@ struct CPPTargetMachine : public TargetMachine { CPPTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : TargetMachine(T) {} + : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 20:53:10 2011 @@ -32,7 +32,6 @@ class MBlazeAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -64,8 +63,9 @@ public: - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &_Parser) + : TargetAsmParser(T), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -16,9 +16,10 @@ #include "MBlazeRegisterInfo.h" #include "llvm/Support/CommandLine.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MBlazeGenSubtargetInfo.inc" using namespace llvm; @@ -61,4 +62,3 @@ CriticalPathRCs.push_back(&MBlaze::GPRRegClass); return HasItin && OptLevel >= CodeGenOpt::Default; } - Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -81,7 +81,7 @@ MBlazeTargetMachine:: MBlazeTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS): - LLVMTargetMachine(T, TT), + LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 2011 @@ -14,9 +14,10 @@ #include "MSP430Subtarget.h" #include "MSP430.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MSP430GenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -30,7 +30,7 @@ const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -14,9 +14,10 @@ #include "MipsSubtarget.h" #include "Mips.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MipsGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -37,7 +37,7 @@ MipsTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool isLittle=false): - LLVMTargetMachine(T, TT), + LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -14,9 +14,10 @@ #include "PTXSubtarget.h" #include "llvm/Support/ErrorHandling.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "PTXGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -55,7 +55,7 @@ const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -17,9 +17,10 @@ #include "llvm/Target/TargetMachine.h" #include -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "PPCGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -69,7 +69,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -13,9 +13,10 @@ #include "SparcSubtarget.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SparcGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -32,7 +32,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -16,9 +16,10 @@ #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SystemZGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -26,7 +26,7 @@ const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -216,8 +216,9 @@ // TargetMachine Class // -TargetMachine::TargetMachine(const Target &T) - : TheTarget(T), AsmInfo(0), +TargetMachine::TargetMachine(const Target &T, + StringRef TT, StringRef CPU, StringRef FS) + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0), MCRelaxAll(false), MCNoExecStack(false), MCSaveTempLabels(false), Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 20:53:10 2011 @@ -15,6 +15,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -25,6 +26,10 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" + +#define GET_SUBTARGETINFO_ENUM +#include "X86GenSubtargetInfo.inc" + using namespace llvm; namespace { @@ -32,10 +37,7 @@ class X86ATTAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; - -protected: - unsigned Is64Bit : 1; + MCSubtargetInfo *STI; private: MCAsmParser &getParser() const { return Parser; } @@ -61,6 +63,11 @@ /// or %es:(%edi) in 32bit mode. bool isDstOp(X86Operand &Op); + bool is64Bit() { + // FIXME: Can tablegen auto-generate this? + return (STI->getFeatureBits() & X86::Mode64Bit) != 0; + } + /// @name Auto-generated Matcher Functions /// { @@ -70,12 +77,13 @@ /// } public: - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM) - : TargetAsmParser(T), Parser(parser), TM(TM) { + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &parser) + : TargetAsmParser(T), Parser(parser) { + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures( - &TM.getSubtarget())); + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); } virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); @@ -84,23 +92,6 @@ virtual bool ParseDirective(AsmToken DirectiveID); }; - -class X86_32ATTAsmParser : public X86ATTAsmParser { -public: - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) - : X86ATTAsmParser(T, Parser, TM) { - Is64Bit = false; - } -}; - -class X86_64ATTAsmParser : public X86ATTAsmParser { -public: - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) - : X86ATTAsmParser(T, Parser, TM) { - Is64Bit = true; - } -}; - } // end anonymous namespace /// @name Auto-generated Match Functions @@ -365,7 +356,7 @@ } // end anonymous namespace. bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI; + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; return (Op.isMem() && (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && @@ -375,7 +366,7 @@ } bool X86ATTAsmParser::isDstOp(X86Operand &Op) { - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI; + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; return Op.isMem() && Op.Mem.SegReg == X86::ES && isa(Op.Mem.Disp) && @@ -406,7 +397,7 @@ // FIXME: This should be done using Requires and // Requires so "eiz" usage in 64-bit instructions // can be also checked. - if (RegNo == X86::RIZ && !Is64Bit) + if (RegNo == X86::RIZ && !is64Bit()) return Error(Tok.getLoc(), "riz register in 64-bit mode only"); // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. @@ -826,7 +817,7 @@ // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" if (Name.startswith("movs") && Operands.size() == 3 && (Name == "movsb" || Name == "movsw" || Name == "movsl" || - (Is64Bit && Name == "movsq"))) { + (is64Bit() && Name == "movsq"))) { X86Operand &Op = *(X86Operand*)Operands.begin()[1]; X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; if (isSrcOp(Op) && isDstOp(Op2)) { @@ -839,7 +830,7 @@ // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" if (Name.startswith("lods") && Operands.size() == 3 && (Name == "lods" || Name == "lodsb" || Name == "lodsw" || - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) { + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { X86Operand *Op1 = static_cast(Operands[1]); X86Operand *Op2 = static_cast(Operands[2]); if (isSrcOp(*Op1) && Op2->isReg()) { @@ -869,7 +860,7 @@ // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" if (Name.startswith("stos") && Operands.size() == 3 && (Name == "stos" || Name == "stosb" || Name == "stosw" || - Name == "stosl" || (Is64Bit && Name == "stosq"))) { + Name == "stosl" || (is64Bit() && Name == "stosq"))) { X86Operand *Op1 = static_cast(Operands[1]); X86Operand *Op2 = static_cast(Operands[2]); if (isDstOp(*Op2) && Op1->isReg()) { @@ -1144,8 +1135,8 @@ // Force static initialization. extern "C" void LLVMInitializeX86AsmParser() { - RegisterAsmParser X(TheX86_32Target); - RegisterAsmParser Y(TheX86_64Target); + RegisterAsmParser X(TheX86_32Target); + RegisterAsmParser Y(TheX86_64Target); LLVMInitializeX86AsmLexer(); } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 20:53:10 2011 @@ -25,6 +25,7 @@ #define GET_INSTRINFO_MC_DESC #include "X86GenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #include "X86GenSubtargetInfo.inc" @@ -35,7 +36,7 @@ Triple TheTriple(TT); if (TheTriple.getArch() == Triple::x86_64) return "+64bit-mode"; - return ""; + return "-64bit-mode"; } /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the @@ -128,20 +129,8 @@ return false; } -MCInstrInfo *createX86MCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitX86MCInstrInfo(X); - return X; -} - -MCRegisterInfo *createX86MCRegisterInfo() { - MCRegisterInfo *X = new MCRegisterInfo(); - InitX86MCRegisterInfo(X); - return X; -} - -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { std::string ArchFS = X86_MC::ParseX86Triple(TT); if (!FS.empty()) { if (!ArchFS.empty()) @@ -159,7 +148,19 @@ ArchFS = "+64bit-mode"; MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X, CPU, ArchFS); + InitX86MCSubtargetInfo(X, CPUName, ArchFS); + return X; +} + +MCInstrInfo *createX86MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitX86MCInstrInfo(X); + return X; +} + +MCRegisterInfo *createX86MCRegisterInfo() { + MCRegisterInfo *X = new MCRegisterInfo(); + InitX86MCRegisterInfo(X); return X; } @@ -179,13 +180,3 @@ TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); } - -extern "C" void LLVMInitializeX86MCSubtargetInfo() { - RegisterMCSubtargetInfo X(TheX86_32Target); - RegisterMCSubtargetInfo Y(TheX86_64Target); - - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, - createX86MCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, - createX86MCSubtargetInfo); -} Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 20:53:10 2011 @@ -17,6 +17,7 @@ #include namespace llvm { +class MCSubtargetInfo; class Target; class StringRef; @@ -31,9 +32,17 @@ unsigned *rEBX, unsigned *rECX, unsigned *rEDX); void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); + + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. + /// This is exposed so Asm parser, etc. do not need to go through + /// TargetRegistry. + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS); } + } // End llvm namespace + // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011 @@ -438,8 +438,10 @@ def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate; -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate; +def In32BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit">; def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011 @@ -21,9 +21,10 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "X86GenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -119,7 +119,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, StackAlignmentOverride), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 2011 @@ -14,9 +14,10 @@ #include "XCoreSubtarget.h" #include "XCore.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "XCoreGenSubtargetInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 2011 @@ -23,7 +23,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011 @@ -371,7 +371,8 @@ OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI)); - OwningPtr TAP(TheTarget->createAsmParser(*Parser, *TM)); + OwningPtr + TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser)); if (!TAP) { errs() << ProgName << ": error: this target does not support assembly parsing.\n"; Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011 @@ -619,7 +619,10 @@ Context, *Streamer, *_target->getMCAsmInfo())); OwningPtr - TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get())); + TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(), + _target->getTargetCPU(), + _target->getTargetFeatureString(), + *Parser.get())); Parser->setTargetParser(*TAP); int Res = Parser->Run(false); if (Res) Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 2011 @@ -1817,15 +1817,43 @@ Info.AsmParser->getValueAsString("AsmParserClassName"); OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" - << "ComputeAvailableFeatures(const " << Info.Target.getName() - << "Subtarget *Subtarget) const {\n"; + << "ComputeAvailableFeatures(uint64_t FB) const {\n"; OS << " unsigned Features = 0;\n"; for (std::map::const_iterator it = Info.SubtargetFeatures.begin(), ie = Info.SubtargetFeatures.end(); it != ie; ++it) { SubtargetFeatureInfo &SFI = *it->second; - OS << " if (" << SFI.TheDef->getValueAsString("CondString") - << ")\n"; + + OS << " if ("; + StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString"); + std::pair Comma = Conds.split(','); + bool First = true; + do { + if (!First) + OS << " && "; + + bool Neg = false; + StringRef Cond = Comma.first; + if (Cond[0] == '!') { + Neg = true; + Cond = Cond.substr(1); + } + + OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; + if (Neg) + OS << " == 0"; + else + OS << " != 0"; + OS << ")"; + + if (Comma.second.empty()) + break; + + First = false; + Comma = Comma.second.split(','); + } while (true); + + OS << ")\n"; OS << " Features |= " << SFI.getEnumName() << ";\n"; } OS << " return Features;\n"; @@ -2140,8 +2168,7 @@ OS << "#undef GET_ASSEMBLER_HEADER\n"; OS << " // This should be included into the middle of the declaration of\n"; OS << " // your subclasses implementation of TargetAsmParser.\n"; - OS << " unsigned ComputeAvailableFeatures(const " << - Target.getName() << "Subtarget *Subtarget) const;\n"; + OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; OS << " enum MatchResultTy {\n"; OS << " Match_ConversionFail,\n"; OS << " Match_InvalidOperand,\n"; Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 2011 @@ -645,12 +645,18 @@ EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; + OS << "#undef GET_SUBTARGETINFO_ENUM\n"; + + OS << "namespace llvm {\n"; + Enumeration(OS, "SubtargetFeature", true); + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; + OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; OS << "namespace llvm {\n"; - Enumeration(OS, "SubtargetFeature", true); - OS<<"\n"; unsigned NumFeatures = FeatureKeyValues(OS); OS<<"\n"; unsigned NumProcs = CPUKeyValues(OS); From nlewycky at google.com Thu Jul 7 21:39:44 2011 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 7 Jul 2011 19:39:44 -0700 Subject: [llvm-commits] [llvm] r134678 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Black Message-ID: Hi Evan, is there a clang half to this change that's coming shortly? nlewycky at ducttape:~/llvm/tools/clang/tools/driver$ make llvm[0]: Compiling cc1as_main.cpp for Debug+Asserts build cc1as_main.cpp: In function ?bool ExecuteAssembler(::AssemblerInvocation&, clang::Diagnostic&)?: cc1as_main.cpp:311: error: no matching function for call to ?llvm::Target::createAsmParser(llvm::MCAsmParser&, llvm::TargetMachine&) const? /usr/local/google/home/nlewycky/llvm/include/llvm/Target/TargetRegistry.h:302: note: candidates are: llvm::TargetAsmParser* llvm::Target::createAsmParser(llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::MCAsmParser&) const make: *** [/usr/local/google/home/nlewycky/llvm/tools/clang/tools/driver/Debug+Asserts/cc1as_main.o] Error 1 Nick On 7 July 2011 18:53, Evan Cheng wrote: > Author: evancheng > Date: Thu Jul 7 20:53:10 2011 > New Revision: 134678 > > URL: http://llvm.org/viewvc/llvm-project?rev=134678&view=rev > Log: > Eliminate asm parser's dependency on TargetMachine: > - Each target asm parser now creates its own MCSubtatgetInfo (if needed). > - Changed AssemblerPredicate to take subtarget features which tablegen uses > to generate asm matcher subtarget feature queries. e.g. > "ModeThumb,FeatureThumb2" is translated to > "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". > > Modified: > llvm/trunk/include/llvm/Target/Target.td > llvm/trunk/include/llvm/Target/TargetMachine.h > llvm/trunk/include/llvm/Target/TargetRegistry.h > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp > llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp > llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp > llvm/trunk/lib/Target/CBackend/CTargetMachine.h > llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp > llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h > llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp > llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp > llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp > llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp > llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp > llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp > llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp > llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp > llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp > llvm/trunk/lib/Target/TargetMachine.cpp > llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > llvm/trunk/lib/Target/X86/X86InstrInfo.td > llvm/trunk/lib/Target/X86/X86Subtarget.cpp > llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp > llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > llvm/trunk/tools/llvm-mc/llvm-mc.cpp > llvm/trunk/tools/lto/LTOModule.cpp > llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > llvm/trunk/utils/TableGen/SubtargetEmitter.cpp > > Modified: llvm/trunk/include/llvm/Target/Target.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/Target.td (original) > +++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011 > @@ -382,6 +382,15 @@ > /// matcher, this is true. Targets should set this by inheriting their > /// feature from the AssemblerPredicate class in addition to Predicate. > bit AssemblerMatcherPredicate = 0; > + > + /// AssemblerCondString - Name of the subtarget feature being tested > used > + /// as alternative condition string used for assembler matcher. > + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". > + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". > + /// It can also list multiple features separated by ",". > + /// e.g. "ModeThumb,FeatureThumb2" is translated to > + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". > + string AssemblerCondString = ""; > } > > /// NoHonorSignDependentRounding - This predicate is true if support for > @@ -689,8 +698,9 @@ > > /// AssemblerPredicate - This is a Predicate that can be used when the > assembler > /// matches instructions and aliases. > -class AssemblerPredicate { > +class AssemblerPredicate { > bit AssemblerMatcherPredicate = 1; > + string AssemblerCondString = cond; > } > > > > Modified: llvm/trunk/include/llvm/Target/TargetMachine.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) > +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 2011 > @@ -14,6 +14,7 @@ > #ifndef LLVM_TARGET_TARGETMACHINE_H > #define LLVM_TARGET_TARGETMACHINE_H > > +#include "llvm/ADT/StringRef.h" > #include > #include > > @@ -91,7 +92,8 @@ > TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT > void operator=(const TargetMachine &); // DO NOT IMPLEMENT > protected: // Can only create subclasses. > - TargetMachine(const Target &); > + TargetMachine(const Target &T, StringRef TargetTriple, > + StringRef CPU, StringRef FS); > > /// getSubtargetImpl - virtual method implemented by subclasses that > returns > /// a reference to that target's TargetSubtargetInfo-derived member > variable. > @@ -100,6 +102,12 @@ > /// TheTarget - The Target that this machine was created for. > const Target &TheTarget; > > + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and > target > + /// feature strings the TargetMachine instance is created with. > + std::string TargetTriple; > + std::string TargetCPU; > + std::string TargetFS; > + > /// AsmInfo - Contains target specific asm information. > /// > const MCAsmInfo *AsmInfo; > @@ -115,6 +123,10 @@ > > const Target &getTarget() const { return TheTarget; } > > + const StringRef getTargetTriple() const { return TargetTriple; } > + const StringRef getTargetCPU() const { return TargetCPU; } > + const StringRef getTargetFeatureString() const { return TargetFS; } > + > // Interfaces to the major aspects of target machine information: > // -- Instruction opcode and operand information > // -- Pipelines and scheduling information > @@ -295,10 +307,9 @@ > /// implemented with the LLVM target-independent code generator. > /// > class LLVMTargetMachine : public TargetMachine { > - std::string TargetTriple; > - > protected: // Can only create subclasses. > - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); > + LLVMTargetMachine(const Target &T, StringRef TargetTriple, > + StringRef CPU, StringRef FS); > > private: > /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for > @@ -311,9 +322,6 @@ > virtual void setCodeModelForStatic(); > > public: > - > - const std::string &getTargetTriple() const { return TargetTriple; } > - > /// addPassesToEmitFile - Add passes to the specified pass manager to get > the > /// specified file emitted. Typically this will involve several steps of > code > /// generation. If OptLevel is None, the code generator should emit code > as > > Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) > +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 > 2011 > @@ -35,7 +35,6 @@ > class MCInstPrinter; > class MCInstrInfo; > class MCRegisterInfo; > - class MCSubtargetInfo; > class MCStreamer; > class TargetAsmBackend; > class TargetAsmLexer; > @@ -70,9 +69,6 @@ > StringRef TT); > typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); > typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); > - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, > - StringRef CPU, > - StringRef > Features); > typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, > const std::string &TT, > const std::string &CPU, > @@ -83,8 +79,9 @@ > const std::string &TT); > typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, > const MCAsmInfo &MAI); > - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target > &T,MCAsmParser &P, > - TargetMachine &TM); > + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef > TT, > + StringRef CPU, StringRef > Features, > + MCAsmParser &P); > typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); > typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, > unsigned SyntaxVariant, > @@ -140,10 +137,6 @@ > /// if registered. > MCRegInfoCtorFnTy MCRegInfoCtorFn; > > - /// MCSubtargetInfoCtorFn - Constructor function for this target's > - /// MCSubtargetInfo, if registered. > - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; > - > /// TargetMachineCtorFn - Construction function for this target's > /// TargetMachine, if registered. > TargetMachineCtorTy TargetMachineCtorFn; > @@ -269,22 +262,6 @@ > return MCRegInfoCtorFn(); > } > > - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. > - /// > - /// \arg Triple - This argument is used to determine the target > machine > - /// feature set; it should always be provided. Generally this should > be > - /// either the target triple from the module, or the target triple of > the > - /// host if that does not exist. > - /// \arg CPU - This specifies the name of the target CPU. > - /// \arg Features - This specifies the string representation of the > - /// additional target features. > - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef > CPU, > - StringRef Features) const { > - if (!MCSubtargetInfoCtorFn) > - return 0; > - return MCSubtargetInfoCtorFn(Triple, CPU, Features); > - } > - > /// createTargetMachine - Create a target specific machine > implementation > /// for the specified \arg Triple. > /// > @@ -322,11 +299,11 @@ > /// > /// \arg Parser - The target independent parser implementation to use > for > /// parsing and lexing. > - TargetAsmParser *createAsmParser(MCAsmParser &Parser, > - TargetMachine &TM) const { > + TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, > + StringRef Features, MCAsmParser > &Parser) const { > if (!AsmParserCtorFn) > return 0; > - return AsmParserCtorFn(*this, Parser, TM); > + return AsmParserCtorFn(*this, Triple, CPU, Features, Parser); > } > > /// createAsmPrinter - Create a target specific assembly printer pass. > This > @@ -528,22 +505,6 @@ > T.MCRegInfoCtorFn = Fn; > } > > - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo > implementation for > - /// the given target. > - /// > - /// Clients are responsible for ensuring that registration doesn't > occur > - /// while another thread is attempting to access the registry. > Typically > - /// this is done by initializing all targets at program startup. > - /// > - /// @param T - The target being registered. > - /// @param Fn - A function to construct a MCSubtargetInfo for the > target. > - static void RegisterMCSubtargetInfo(Target &T, > - Target::MCSubtargetInfoCtorFnTy > Fn) { > - // Ignore duplicate registration. > - if (!T.MCSubtargetInfoCtorFn) > - T.MCSubtargetInfoCtorFn = Fn; > - } > - > /// RegisterTargetMachine - Register a TargetMachine implementation for > the > /// given target. > /// > @@ -820,40 +781,6 @@ > } > }; > > - /// RegisterMCSubtargetInfo - Helper template for registering a target > - /// subtarget info implementation. This invokes the static "Create" > method > - /// on the class to actually do the construction. Usage: > - /// > - /// extern "C" void LLVMInitializeFooTarget() { > - /// extern Target TheFooTarget; > - /// RegisterMCSubtargetInfo X(TheFooTarget); > - /// } > - template > - struct RegisterMCSubtargetInfo { > - RegisterMCSubtargetInfo(Target &T) { > - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); > - } > - private: > - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, > - StringRef FS) { > - return new MCSubtargetInfoImpl(); > - } > - }; > - > - /// RegisterMCSubtargetInfoFn - Helper template for registering a target > - /// subtarget info implementation. This invokes the specified function > to > - /// do the construction. Usage: > - /// > - /// extern "C" void LLVMInitializeFooTarget() { > - /// extern Target TheFooTarget; > - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); > - /// } > - struct RegisterMCSubtargetInfoFn { > - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy > Fn) { > - TargetRegistry::RegisterMCSubtargetInfo(T, Fn); > - } > - }; > - > /// RegisterTargetMachine - Helper template for registering a target > machine > /// implementation, for use in the target machine initialization > /// function. Usage: > @@ -931,9 +858,10 @@ > } > > private: > - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, > - TargetMachine &TM) { > - return new AsmParserImpl(T, P, TM); > + static TargetAsmParser *Allocator(const Target &T, StringRef TT, > + StringRef CPU, StringRef FS, > + MCAsmParser &P) { > + return new AsmParserImpl(T, TT, CPU, FS, P); > } > }; > > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 > 20:53:10 2011 > @@ -111,7 +111,12 @@ > OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, > OutContext, OutStreamer, > *MAI)); > - OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, > TM)); > + > + OwningPtr > + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), > + TM.getTargetCPU(), > + TM.getTargetFeatureString(), > + *Parser)); > if (!TAP) > report_fatal_error("Inline asm not supported by this streamer because" > " we don't have an asm parser for this target\n"); > > Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) > +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -98,10 +98,10 @@ > EnableFastISelOption("fast-isel", cl::Hidden, > cl::desc("Enable the \"fast\" instruction selector")); > > -LLVMTargetMachine::LLVMTargetMachine(const Target &T, > - const std::string &Triple) > - : TargetMachine(T), TargetTriple(Triple) { > - AsmInfo = T.createAsmInfo(TargetTriple); > +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, > + StringRef CPU, StringRef FS) > + : TargetMachine(T, Triple, CPU, FS) { > + AsmInfo = T.createAsmInfo(Triple); > } > > // Set the default code model for the JIT for a generic target. > @@ -143,7 +143,7 @@ > TargetAsmBackend *TAB = 0; > if (ShowMCEncoding) { > MCE = getTarget().createCodeEmitter(*this, *Context); > - TAB = getTarget().createAsmBackend(TargetTriple); > + TAB = getTarget().createAsmBackend(getTargetTriple()); > } > > MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, > @@ -160,12 +160,12 @@ > // Create the code emitter for the target if it exists. If not, .o > file > // emission fails. > MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); > - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); > + TargetAsmBackend *TAB = > getTarget().createAsmBackend(getTargetTriple()); > if (MCE == 0 || TAB == 0) > return true; > > - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, > *Context, > - *TAB, Out, MCE, > + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), > + *Context, *TAB, > Out, MCE, > hasMCRelaxAll(), > > hasMCNoExecStack())); > AsmStreamer.get()->InitSections(); > @@ -241,12 +241,12 @@ > // Create the code emitter for the target if it exists. If not, .o file > // emission fails. > MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); > - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); > + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); > if (MCE == 0 || TAB == 0) > return true; > > OwningPtr AsmStreamer; > - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx, > + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), > *Ctx, > *TAB, Out, MCE, > hasMCRelaxAll(), > hasMCNoExecStack())); > > Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) > +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 20:53:10 > 2011 > @@ -171,7 +171,7 @@ > std::string featureString; > TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, > featureString)); > - > + > const TargetRegisterInfo *registerInfo = > TargetMachine->getRegisterInfo(); > > if (!registerInfo) > @@ -183,7 +183,7 @@ > > if (!AsmInfo) > return; > - > + > Disassembler.reset(Tgt->createMCDisassembler()); > > if (!Disassembler) > @@ -371,8 +371,10 @@ > OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, > context, > *streamer, > *AsmInfo)); > - OwningPtr > TargetParser(Tgt->createAsmParser(*genericParser, > - > *TargetMachine)); > + > + StringRef triple = tripleFromArch(Key.Arch); > + OwningPtr TargetParser(Tgt->createAsmParser(triple, "", > "", > + > *genericParser)); > > AsmToken OpcodeToken = genericParser->Lex(); > AsmToken NextToken = genericParser->Lex(); // consume next token, > because specificParser expects us to > > Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) > +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 > 2011 > @@ -41,6 +41,7 @@ > class MCInst; > class MCParsedAsmOperand; > class MCStreamer; > +class MCSubtargetInfo; > template class SmallVectorImpl; > class SourceMgr; > class Target; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011 > @@ -147,35 +147,48 @@ > > //===----------------------------------------------------------------------===// > // ARM Instruction Predicate Definitions. > // > -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, > AssemblerPredicate; > +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, > + AssemblerPredicate<"HasV4TOps">; > def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; > def HasV5T : Predicate<"Subtarget->hasV5TOps()">; > -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, > AssemblerPredicate; > -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, > AssemblerPredicate; > +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, > + AssemblerPredicate<"HasV5TEOps">; > +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, > + AssemblerPredicate<"HasV6Ops">; > def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; > -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, > AssemblerPredicate; > +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, > + AssemblerPredicate<"HasV6T2Ops">; > def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; > -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, > AssemblerPredicate; > +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, > + AssemblerPredicate<"HasV7Ops">; > def NoVFP : Predicate<"!Subtarget->hasVFP2()">; > -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, > AssemblerPredicate; > -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, > AssemblerPredicate; > -def HasNEON : Predicate<"Subtarget->hasNEON()">, > AssemblerPredicate; > -def HasFP16 : Predicate<"Subtarget->hasFP16()">, > AssemblerPredicate; > -def HasDivide : Predicate<"Subtarget->hasDivide()">, > AssemblerPredicate; > +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, > + AssemblerPredicate<"FeatureVFP2">; > +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, > + AssemblerPredicate<"FeatureVFP3">; > +def HasNEON : Predicate<"Subtarget->hasNEON()">, > + AssemblerPredicate<"FeatureNEON">; > +def HasFP16 : Predicate<"Subtarget->hasFP16()">, > + AssemblerPredicate<"FeatureFP16">; > +def HasDivide : Predicate<"Subtarget->hasDivide()">, > + AssemblerPredicate<"FeatureHWDiv">; > def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureT2XtPk">; > def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureDSPThumb2">; > def HasDB : Predicate<"Subtarget->hasDataBarrier()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureDB">; > def HasMP : Predicate<"Subtarget->hasMPExtension()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureMP">; > def UseNEONForFP : > Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; > def DontUseNEONForFP : > Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; > -def IsThumb : Predicate<"Subtarget->isThumb()">, > AssemblerPredicate; > +def IsThumb : Predicate<"Subtarget->isThumb()">, > + AssemblerPredicate<"ModeThumb">; > def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; > -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, > AssemblerPredicate; > -def IsARM : Predicate<"!Subtarget->isThumb()">, > AssemblerPredicate; > +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, > + > AssemblerPredicate<"ModeThumb,FeatureThumb2">; > +def IsARM : Predicate<"!Subtarget->isThumb()">, > + AssemblerPredicate<"!ModeThumb">; > def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; > def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; > > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -18,9 +18,10 @@ > #include "llvm/Support/CommandLine.h" > #include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "ARMGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -80,7 +80,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > JITInfo(), > InstrItins(Subtarget.getInstrItineraryData()) { > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 > 20:53:10 2011 > @@ -20,6 +20,7 @@ > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCExpr.h" > #include "llvm/MC/MCInst.h" > +#include "llvm/MC/MCSubtargetInfo.h" > #include "llvm/Target/TargetRegistry.h" > #include "llvm/Target/TargetAsmParser.h" > #include "llvm/Support/SourceMgr.h" > @@ -28,6 +29,10 @@ > #include "llvm/ADT/StringExtras.h" > #include "llvm/ADT/StringSwitch.h" > #include "llvm/ADT/Twine.h" > + > +#define GET_SUBTARGETINFO_ENUM > +#include "ARMGenSubtargetInfo.inc" > + > using namespace llvm; > > namespace { > @@ -36,7 +41,7 @@ > > class ARMAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > + MCSubtargetInfo *STI; > > MCAsmParser &getParser() const { return Parser; } > MCAsmLexer &getLexer() const { return Parser.getLexer(); } > @@ -79,6 +84,15 @@ > void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, > bool &CanAcceptPredicationCode); > > + bool isThumb() const { > + // FIXME: Can tablegen auto-generate this? > + return (STI->getFeatureBits() & ARM::ModeThumb) != 0; > + } > + > + bool isThumbOne() const { > + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; > + } > + > /// @name Auto-generated Match Functions > /// { > > @@ -113,13 +127,15 @@ > const > SmallVectorImpl &); > > public: > - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) > - : TargetAsmParser(T), Parser(_Parser), TM(_TM) { > - MCAsmParserExtension::Initialize(_Parser); > - // Initialize the set of available features. > - setAvailableFeatures(ComputeAvailableFeatures( > - &TM.getSubtarget())); > - } > + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, > + MCAsmParser &_Parser) > + : TargetAsmParser(T), Parser(_Parser) { > + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); > + > + MCAsmParserExtension::Initialize(_Parser); > + // Initialize the set of available features. > + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); > + } > > virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, > SmallVectorImpl > &Operands); > @@ -1852,9 +1868,6 @@ > void ARMAsmParser:: > GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, > bool &CanAcceptPredicationCode) { > - bool isThumbOne = TM.getSubtarget().isThumb1Only(); > - bool isThumb = TM.getSubtarget().isThumb(); > - > if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || > Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || > Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || > @@ -1863,7 +1876,7 @@ > Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || > Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || > Mnemonic == "eor" || Mnemonic == "smlal" || > - (Mnemonic == "mov" && !isThumbOne)) { > + (Mnemonic == "mov" && !isThumbOne())) { > CanAcceptCarrySet = true; > } else { > CanAcceptCarrySet = false; > @@ -1880,7 +1893,7 @@ > CanAcceptPredicationCode = true; > } > > - if (isThumb) > + if (isThumb()) > if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || > Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") > CanAcceptPredicationCode = false; > @@ -2207,12 +2220,12 @@ > // includes Feature_IsThumb or not to match the right instructions. This > is > // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. > if (Val == 16){ > - assert(TM.getSubtarget().isThumb() && > + assert(isThumb() && > "switching between arm/thumb not yet suppported via .code 16)"); > getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); > } > else{ > - assert(!TM.getSubtarget().isThumb() && > + assert(!isThumb() && > "switching between thumb/arm not yet suppported via .code 32)"); > getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); > } > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 > 20:53:10 2011 > @@ -23,65 +23,12 @@ > #define GET_INSTRINFO_MC_DESC > #include "ARMGenInstrInfo.inc" > > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #include "ARMGenSubtargetInfo.inc" > > using namespace llvm; > > -MCInstrInfo *createARMMCInstrInfo() { > - MCInstrInfo *X = new MCInstrInfo(); > - InitARMMCInstrInfo(X); > - return X; > -} > - > -MCRegisterInfo *createARMMCRegisterInfo() { > - MCRegisterInfo *X = new MCRegisterInfo(); > - InitARMMCRegisterInfo(X); > - return X; > -} > - > -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > - StringRef FS) { > - std::string ArchFS = ARM_MC::ParseARMTriple(TT); > - if (!FS.empty()) { > - if (!ArchFS.empty()) > - ArchFS = ArchFS + "," + FS.str(); > - else > - ArchFS = FS; > - } > - > - MCSubtargetInfo *X = new MCSubtargetInfo(); > - InitARMMCSubtargetInfo(X, CPU, ArchFS); > - return X; > -} > - > -// Force static initialization. > -extern "C" void LLVMInitializeARMMCInstrInfo() { > - RegisterMCInstrInfo X(TheARMTarget); > - RegisterMCInstrInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); > - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, > createARMMCInstrInfo); > -} > - > -extern "C" void LLVMInitializeARMMCRegInfo() { > - RegisterMCRegInfo X(TheARMTarget); > - RegisterMCRegInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCRegInfo(TheARMTarget, > createARMMCRegisterInfo); > - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, > createARMMCRegisterInfo); > -} > - > -extern "C" void LLVMInitializeARMMCSubtargetInfo() { > - RegisterMCSubtargetInfo X(TheARMTarget); > - RegisterMCSubtargetInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, > - createARMMCSubtargetInfo); > - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, > - createARMMCSubtargetInfo); > -} > - > std::string ARM_MC::ParseARMTriple(StringRef TT) { > // Set the boolean corresponding to the current target triple, or the > default > // if one cannot be determined, to true. > @@ -135,3 +82,47 @@ > > return ARMArchFeature; > } > + > +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef > CPU, > + StringRef FS) { > + std::string ArchFS = ARM_MC::ParseARMTriple(TT); > + if (!FS.empty()) { > + if (!ArchFS.empty()) > + ArchFS = ArchFS + "," + FS.str(); > + else > + ArchFS = FS; > + } > + > + MCSubtargetInfo *X = new MCSubtargetInfo(); > + InitARMMCSubtargetInfo(X, CPU, ArchFS); > + return X; > +} > + > +MCInstrInfo *createARMMCInstrInfo() { > + MCInstrInfo *X = new MCInstrInfo(); > + InitARMMCInstrInfo(X); > + return X; > +} > + > +MCRegisterInfo *createARMMCRegisterInfo() { > + MCRegisterInfo *X = new MCRegisterInfo(); > + InitARMMCRegisterInfo(X); > + return X; > +} > + > +// Force static initialization. > +extern "C" void LLVMInitializeARMMCInstrInfo() { > + RegisterMCInstrInfo X(TheARMTarget); > + RegisterMCInstrInfo Y(TheThumbTarget); > + > + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); > + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, > createARMMCInstrInfo); > +} > + > +extern "C" void LLVMInitializeARMMCRegInfo() { > + RegisterMCRegInfo X(TheARMTarget); > + RegisterMCRegInfo Y(TheThumbTarget); > + > + TargetRegistry::RegisterMCRegInfo(TheARMTarget, > createARMMCRegisterInfo); > + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, > createARMMCRegisterInfo); > +} > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 > 20:53:10 2011 > @@ -17,6 +17,7 @@ > #include > > namespace llvm { > +class MCSubtargetInfo; > class Target; > class StringRef; > > @@ -24,6 +25,12 @@ > > namespace ARM_MC { > std::string ParseARMTriple(StringRef TT); > + > + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. > + /// This is exposed so Asm parser, etc. do not need to go through > + /// TargetRegistry. > + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS); > } > > } // End llvm namespace > > Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "AlphaSubtarget.h" > #include "Alpha.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "AlphaGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -27,7 +27,7 @@ > AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string > &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout("e-f128:128:128-n64"), > FrameLowering(Subtarget), > Subtarget(TT, CPU, FS), > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 > 20:53:10 2011 > @@ -13,9 +13,10 @@ > > #include "BlackfinSubtarget.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "BlackfinGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 > 20:53:10 2011 > @@ -28,7 +28,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout("e-p:32:32-i64:32-f64:32-n32"), > Subtarget(TT, CPU, FS), > TLInfo(*this), > > Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) > +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 > 2011 > @@ -22,7 +22,7 @@ > struct CTargetMachine : public TargetMachine { > CTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS) > - : TargetMachine(T) {} > + : TargetMachine(T, TT, CPU, FS) {} > > virtual bool addPassesToEmitFile(PassManagerBase &PM, > formatted_raw_ostream &Out, > > Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -13,12 +13,13 @@ > > #include "SPUSubtarget.h" > #include "SPU.h" > -#include "llvm/ADT/SmallVector.h" > #include "SPURegisterInfo.h" > +#include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SPUGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -36,7 +36,7 @@ > > SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU,const std::string > &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout(Subtarget.getTargetDataString()), > InstrInfo(*this), > > Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) > +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 20:53:10 > 2011 > @@ -24,7 +24,7 @@ > struct CPPTargetMachine : public TargetMachine { > CPPTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS) > - : TargetMachine(T) {} > + : TargetMachine(T, TT, CPU, FS) {} > > virtual bool addPassesToEmitFile(PassManagerBase &PM, > formatted_raw_ostream &Out, > > Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 > 20:53:10 2011 > @@ -32,7 +32,6 @@ > > class MBlazeAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > > MCAsmParser &getParser() const { return Parser; } > MCAsmLexer &getLexer() const { return Parser.getLexer(); } > @@ -64,8 +63,9 @@ > > > public: > - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine > &_TM) > - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} > + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef > FS, > + MCAsmParser &_Parser) > + : TargetAsmParser(T), Parser(_Parser) {} > > virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, > SmallVectorImpl > &Operands); > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 > 2011 > @@ -16,9 +16,10 @@ > #include "MBlazeRegisterInfo.h" > #include "llvm/Support/CommandLine.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MBlazeGenSubtargetInfo.inc" > > using namespace llvm; > @@ -61,4 +62,3 @@ > CriticalPathRCs.push_back(&MBlaze::GPRRegClass); > return HasItin && OptLevel >= CodeGenOpt::Default; > } > - > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 > 20:53:10 2011 > @@ -81,7 +81,7 @@ > MBlazeTargetMachine:: > MBlazeTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS): > - LLVMTargetMachine(T, TT), > + LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), > InstrInfo(*this), > > Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 > 2011 > @@ -14,9 +14,10 @@ > #include "MSP430Subtarget.h" > #include "MSP430.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MSP430GenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 > 20:53:10 2011 > @@ -30,7 +30,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > // FIXME: Check TargetData string. > DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), > > Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "MipsSubtarget.h" > #include "Mips.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MipsGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -37,7 +37,7 @@ > MipsTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS, > bool isLittle=false): > - LLVMTargetMachine(T, TT), > + LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, isLittle), > DataLayout(isLittle ? > std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : > > Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "PTXSubtarget.h" > #include "llvm/Support/ErrorHandling.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "PTXGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -55,7 +55,7 @@ > const std::string &CPU, > const std::string &FS, > bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout(is64Bit ? DataLayout64 : DataLayout32), > Subtarget(TT, CPU, FS, is64Bit), > FrameLowering(Subtarget), > > Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -17,9 +17,10 @@ > #include "llvm/Target/TargetMachine.h" > #include > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "PPCGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -69,7 +69,7 @@ > PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS, bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, is64Bit), > DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), > FrameLowering(Subtarget), JITInfo(*this, is64Bit), > > Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -13,9 +13,10 @@ > > #include "SparcSubtarget.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SparcGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -32,7 +32,7 @@ > SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string > &TT, > const std::string &CPU, > const std::string &FS, bool is64bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, is64bit), > DataLayout(Subtarget.getDataLayout()), > TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 > 2011 > @@ -16,9 +16,10 @@ > #include "llvm/GlobalValue.h" > #include "llvm/Target/TargetMachine.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SystemZGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 > 20:53:10 2011 > @@ -26,7 +26,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > > DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" > "-f64:64:64-f128:128:128-a0:16:16-n32:64"), > > Modified: llvm/trunk/lib/Target/TargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -216,8 +216,9 @@ > // TargetMachine Class > // > > -TargetMachine::TargetMachine(const Target &T) > - : TheTarget(T), AsmInfo(0), > +TargetMachine::TargetMachine(const Target &T, > + StringRef TT, StringRef CPU, StringRef FS) > + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), > AsmInfo(0), > MCRelaxAll(false), > MCNoExecStack(false), > MCSaveTempLabels(false), > > Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 > 20:53:10 2011 > @@ -15,6 +15,7 @@ > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCExpr.h" > #include "llvm/MC/MCInst.h" > +#include "llvm/MC/MCSubtargetInfo.h" > #include "llvm/MC/MCParser/MCAsmLexer.h" > #include "llvm/MC/MCParser/MCAsmParser.h" > #include "llvm/MC/MCParser/MCParsedAsmOperand.h" > @@ -25,6 +26,10 @@ > #include "llvm/ADT/Twine.h" > #include "llvm/Support/SourceMgr.h" > #include "llvm/Support/raw_ostream.h" > + > +#define GET_SUBTARGETINFO_ENUM > +#include "X86GenSubtargetInfo.inc" > + > using namespace llvm; > > namespace { > @@ -32,10 +37,7 @@ > > class X86ATTAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > - > -protected: > - unsigned Is64Bit : 1; > + MCSubtargetInfo *STI; > > private: > MCAsmParser &getParser() const { return Parser; } > @@ -61,6 +63,11 @@ > /// or %es:(%edi) in 32bit mode. > bool isDstOp(X86Operand &Op); > > + bool is64Bit() { > + // FIXME: Can tablegen auto-generate this? > + return (STI->getFeatureBits() & X86::Mode64Bit) != 0; > + } > + > /// @name Auto-generated Matcher Functions > /// { > > @@ -70,12 +77,13 @@ > /// } > > public: > - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM) > - : TargetAsmParser(T), Parser(parser), TM(TM) { > + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef > FS, > + MCAsmParser &parser) > + : TargetAsmParser(T), Parser(parser) { > + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); > > // Initialize the set of available features. > - setAvailableFeatures(ComputeAvailableFeatures( > - &TM.getSubtarget())); > + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); > } > virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc > &EndLoc); > > @@ -84,23 +92,6 @@ > > virtual bool ParseDirective(AsmToken DirectiveID); > }; > - > -class X86_32ATTAsmParser : public X86ATTAsmParser { > -public: > - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine > &TM) > - : X86ATTAsmParser(T, Parser, TM) { > - Is64Bit = false; > - } > -}; > - > -class X86_64ATTAsmParser : public X86ATTAsmParser { > -public: > - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine > &TM) > - : X86ATTAsmParser(T, Parser, TM) { > - Is64Bit = true; > - } > -}; > - > } // end anonymous namespace > > /// @name Auto-generated Match Functions > @@ -365,7 +356,7 @@ > } // end anonymous namespace. > > bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { > - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI; > + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; > > return (Op.isMem() && > (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && > @@ -375,7 +366,7 @@ > } > > bool X86ATTAsmParser::isDstOp(X86Operand &Op) { > - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI; > + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; > > return Op.isMem() && Op.Mem.SegReg == X86::ES && > isa(Op.Mem.Disp) && > @@ -406,7 +397,7 @@ > // FIXME: This should be done using Requires and > // Requires so "eiz" usage in 64-bit instructions > // can be also checked. > - if (RegNo == X86::RIZ && !Is64Bit) > + if (RegNo == X86::RIZ && !is64Bit()) > return Error(Tok.getLoc(), "riz register in 64-bit mode only"); > > // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. > @@ -826,7 +817,7 @@ > // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" > if (Name.startswith("movs") && Operands.size() == 3 && > (Name == "movsb" || Name == "movsw" || Name == "movsl" || > - (Is64Bit && Name == "movsq"))) { > + (is64Bit() && Name == "movsq"))) { > X86Operand &Op = *(X86Operand*)Operands.begin()[1]; > X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; > if (isSrcOp(Op) && isDstOp(Op2)) { > @@ -839,7 +830,7 @@ > // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" > if (Name.startswith("lods") && Operands.size() == 3 && > (Name == "lods" || Name == "lodsb" || Name == "lodsw" || > - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) { > + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { > X86Operand *Op1 = static_cast(Operands[1]); > X86Operand *Op2 = static_cast(Operands[2]); > if (isSrcOp(*Op1) && Op2->isReg()) { > @@ -869,7 +860,7 @@ > // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" > if (Name.startswith("stos") && Operands.size() == 3 && > (Name == "stos" || Name == "stosb" || Name == "stosw" || > - Name == "stosl" || (Is64Bit && Name == "stosq"))) { > + Name == "stosl" || (is64Bit() && Name == "stosq"))) { > X86Operand *Op1 = static_cast(Operands[1]); > X86Operand *Op2 = static_cast(Operands[2]); > if (isDstOp(*Op2) && Op1->isReg()) { > @@ -1144,8 +1135,8 @@ > > // Force static initialization. > extern "C" void LLVMInitializeX86AsmParser() { > - RegisterAsmParser X(TheX86_32Target); > - RegisterAsmParser Y(TheX86_64Target); > + RegisterAsmParser X(TheX86_32Target); > + RegisterAsmParser Y(TheX86_64Target); > LLVMInitializeX86AsmLexer(); > } > > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 > 20:53:10 2011 > @@ -25,6 +25,7 @@ > #define GET_INSTRINFO_MC_DESC > #include "X86GenInstrInfo.inc" > > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #include "X86GenSubtargetInfo.inc" > > @@ -35,7 +36,7 @@ > Triple TheTriple(TT); > if (TheTriple.getArch() == Triple::x86_64) > return "+64bit-mode"; > - return ""; > + return "-64bit-mode"; > } > > /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values > in the > @@ -128,20 +129,8 @@ > return false; > } > > -MCInstrInfo *createX86MCInstrInfo() { > - MCInstrInfo *X = new MCInstrInfo(); > - InitX86MCInstrInfo(X); > - return X; > -} > - > -MCRegisterInfo *createX86MCRegisterInfo() { > - MCRegisterInfo *X = new MCRegisterInfo(); > - InitX86MCRegisterInfo(X); > - return X; > -} > - > -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > - StringRef FS) { > +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef > CPU, > + StringRef FS) { > std::string ArchFS = X86_MC::ParseX86Triple(TT); > if (!FS.empty()) { > if (!ArchFS.empty()) > @@ -159,7 +148,19 @@ > ArchFS = "+64bit-mode"; > > MCSubtargetInfo *X = new MCSubtargetInfo(); > - InitX86MCSubtargetInfo(X, CPU, ArchFS); > + InitX86MCSubtargetInfo(X, CPUName, ArchFS); > + return X; > +} > + > +MCInstrInfo *createX86MCInstrInfo() { > + MCInstrInfo *X = new MCInstrInfo(); > + InitX86MCInstrInfo(X); > + return X; > +} > + > +MCRegisterInfo *createX86MCRegisterInfo() { > + MCRegisterInfo *X = new MCRegisterInfo(); > + InitX86MCRegisterInfo(X); > return X; > } > > @@ -179,13 +180,3 @@ > TargetRegistry::RegisterMCRegInfo(TheX86_32Target, > createX86MCRegisterInfo); > TargetRegistry::RegisterMCRegInfo(TheX86_64Target, > createX86MCRegisterInfo); > } > - > -extern "C" void LLVMInitializeX86MCSubtargetInfo() { > - RegisterMCSubtargetInfo X(TheX86_32Target); > - RegisterMCSubtargetInfo Y(TheX86_64Target); > - > - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, > - createX86MCSubtargetInfo); > - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, > - createX86MCSubtargetInfo); > -} > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 > 20:53:10 2011 > @@ -17,6 +17,7 @@ > #include > > namespace llvm { > +class MCSubtargetInfo; > class Target; > class StringRef; > > @@ -31,9 +32,17 @@ > unsigned *rEBX, unsigned *rECX, unsigned *rEDX); > > void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); > + > + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. > + /// This is exposed so Asm parser, etc. do not need to go through > + /// TargetRegistry. > + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS); > } > + > } // End llvm namespace > > + > // Defines symbolic names for X86 registers. This defines a mapping from > // register name to register number. > // > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011 > @@ -438,8 +438,10 @@ > def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; > def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; > def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; > -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate; > -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate; > +def In32BitMode : Predicate<"!Subtarget->is64Bit()">, > + AssemblerPredicate<"!Mode64Bit">; > +def In64BitMode : Predicate<"Subtarget->is64Bit()">, > + AssemblerPredicate<"Mode64Bit">; > def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; > def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; > def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -21,9 +21,10 @@ > #include "llvm/Target/TargetMachine.h" > #include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "X86GenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -119,7 +119,7 @@ > X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS, bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, StackAlignmentOverride), > FrameLowering(*this, Subtarget), > ELFWriterInfo(is64Bit, true) { > > Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "XCoreSubtarget.h" > #include "XCore.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "XCoreGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 > 2011 > @@ -23,7 +23,7 @@ > XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string > &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" > "i16:16:32-i32:32:32-i64:32:32-n32"), > > Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) > +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011 > @@ -371,7 +371,8 @@ > > OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, > *Str.get(), *MAI)); > - OwningPtr TAP(TheTarget->createAsmParser(*Parser, > *TM)); > + OwningPtr > + TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, > *Parser)); > if (!TAP) { > errs() << ProgName > << ": error: this target does not support assembly parsing.\n"; > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011 > @@ -619,7 +619,10 @@ > Context, *Streamer, > > *_target->getMCAsmInfo())); > OwningPtr > - TAP(_target->getTarget().createAsmParser(*Parser.get(), > *_target.get())); > + TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(), > + _target->getTargetCPU(), > + > _target->getTargetFeatureString(), > + *Parser.get())); > Parser->setTargetParser(*TAP); > int Res = Parser->Run(false); > if (Res) > > Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 > 2011 > @@ -1817,15 +1817,43 @@ > Info.AsmParser->getValueAsString("AsmParserClassName"); > > OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" > - << "ComputeAvailableFeatures(const " << Info.Target.getName() > - << "Subtarget *Subtarget) const {\n"; > + << "ComputeAvailableFeatures(uint64_t FB) const {\n"; > OS << " unsigned Features = 0;\n"; > for (std::map::const_iterator > it = Info.SubtargetFeatures.begin(), > ie = Info.SubtargetFeatures.end(); it != ie; ++it) { > SubtargetFeatureInfo &SFI = *it->second; > - OS << " if (" << SFI.TheDef->getValueAsString("CondString") > - << ")\n"; > + > + OS << " if ("; > + StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString"); > + std::pair Comma = Conds.split(','); > + bool First = true; > + do { > + if (!First) > + OS << " && "; > + > + bool Neg = false; > + StringRef Cond = Comma.first; > + if (Cond[0] == '!') { > + Neg = true; > + Cond = Cond.substr(1); > + } > + > + OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; > + if (Neg) > + OS << " == 0"; > + else > + OS << " != 0"; > + OS << ")"; > + > + if (Comma.second.empty()) > + break; > + > + First = false; > + Comma = Comma.second.split(','); > + } while (true); > + > + OS << ")\n"; > OS << " Features |= " << SFI.getEnumName() << ";\n"; > } > OS << " return Features;\n"; > @@ -2140,8 +2168,7 @@ > OS << "#undef GET_ASSEMBLER_HEADER\n"; > OS << " // This should be included into the middle of the declaration > of\n"; > OS << " // your subclasses implementation of TargetAsmParser.\n"; > - OS << " unsigned ComputeAvailableFeatures(const " << > - Target.getName() << "Subtarget *Subtarget) const;\n"; > + OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) > const;\n"; > OS << " enum MatchResultTy {\n"; > OS << " Match_ConversionFail,\n"; > OS << " Match_InvalidOperand,\n"; > > Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff > > ============================================================================== > --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 2011 > @@ -645,12 +645,18 @@ > > EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); > > + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; > + OS << "#undef GET_SUBTARGETINFO_ENUM\n"; > + > + OS << "namespace llvm {\n"; > + Enumeration(OS, "SubtargetFeature", true); > + OS << "} // End llvm namespace \n"; > + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; > + > OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; > OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; > > OS << "namespace llvm {\n"; > - Enumeration(OS, "SubtargetFeature", true); > - OS<<"\n"; > unsigned NumFeatures = FeatureKeyValues(OS); > OS<<"\n"; > unsigned NumProcs = CPUKeyValues(OS); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/98188eee/attachment-0001.html From chandlerc at google.com Thu Jul 7 22:16:20 2011 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 7 Jul 2011 20:16:20 -0700 Subject: [llvm-commits] [llvm] r134678 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Black In-Reply-To: References: Message-ID: Fixed in r134680. On Thu, Jul 7, 2011 at 7:39 PM, Nick Lewycky wrote: > Hi Evan, is there a clang half to this change that's coming shortly? > > nlewycky at ducttape:~/llvm/tools/clang/tools/driver$ make > llvm[0]: Compiling cc1as_main.cpp for Debug+Asserts build > cc1as_main.cpp: In function ?bool > ExecuteAssembler(::AssemblerInvocation&, clang::Diagnostic&)?: > cc1as_main.cpp:311: error: no matching function for call to > ?llvm::Target::createAsmParser(llvm::MCAsmParser&, llvm::TargetMachine&) > const? > /usr/local/google/home/nlewycky/llvm/include/llvm/Target/TargetRegistry.h:302: > note: candidates are: llvm::TargetAsmParser* > llvm::Target::createAsmParser(llvm::StringRef, llvm::StringRef, > llvm::StringRef, llvm::MCAsmParser&) const > make: *** > [/usr/local/google/home/nlewycky/llvm/tools/clang/tools/driver/Debug+Asserts/cc1as_main.o] > Error 1 > > Nick > > On 7 July 2011 18:53, Evan Cheng wrote: > >> Author: evancheng >> Date: Thu Jul 7 20:53:10 2011 >> New Revision: 134678 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134678&view=rev >> Log: >> Eliminate asm parser's dependency on TargetMachine: >> - Each target asm parser now creates its own MCSubtatgetInfo (if needed). >> - Changed AssemblerPredicate to take subtarget features which tablegen >> uses >> to generate asm matcher subtarget feature queries. e.g. >> "ModeThumb,FeatureThumb2" is translated to >> "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". >> >> Modified: >> llvm/trunk/include/llvm/Target/Target.td >> llvm/trunk/include/llvm/Target/TargetMachine.h >> llvm/trunk/include/llvm/Target/TargetRegistry.h >> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp >> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp >> llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp >> llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h >> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp >> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp >> llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp >> llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp >> llvm/trunk/lib/Target/CBackend/CTargetMachine.h >> llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp >> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp >> llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h >> llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp >> llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp >> llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp >> llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp >> llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp >> llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp >> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp >> llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp >> llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp >> llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp >> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp >> llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp >> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp >> llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp >> llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp >> llvm/trunk/lib/Target/TargetMachine.cpp >> llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp >> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp >> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h >> llvm/trunk/lib/Target/X86/X86InstrInfo.td >> llvm/trunk/lib/Target/X86/X86Subtarget.cpp >> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp >> llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp >> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp >> llvm/trunk/tools/llvm-mc/llvm-mc.cpp >> llvm/trunk/tools/lto/LTOModule.cpp >> llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp >> llvm/trunk/utils/TableGen/SubtargetEmitter.cpp >> >> Modified: llvm/trunk/include/llvm/Target/Target.td >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/include/llvm/Target/Target.td (original) >> +++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011 >> @@ -382,6 +382,15 @@ >> /// matcher, this is true. Targets should set this by inheriting their >> /// feature from the AssemblerPredicate class in addition to Predicate. >> bit AssemblerMatcherPredicate = 0; >> + >> + /// AssemblerCondString - Name of the subtarget feature being tested >> used >> + /// as alternative condition string used for assembler matcher. >> + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". >> + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". >> + /// It can also list multiple features separated by ",". >> + /// e.g. "ModeThumb,FeatureThumb2" is translated to >> + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". >> + string AssemblerCondString = ""; >> } >> >> /// NoHonorSignDependentRounding - This predicate is true if support for >> @@ -689,8 +698,9 @@ >> >> /// AssemblerPredicate - This is a Predicate that can be used when the >> assembler >> /// matches instructions and aliases. >> -class AssemblerPredicate { >> +class AssemblerPredicate { >> bit AssemblerMatcherPredicate = 1; >> + string AssemblerCondString = cond; >> } >> >> >> >> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) >> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 >> 2011 >> @@ -14,6 +14,7 @@ >> #ifndef LLVM_TARGET_TARGETMACHINE_H >> #define LLVM_TARGET_TARGETMACHINE_H >> >> +#include "llvm/ADT/StringRef.h" >> #include >> #include >> >> @@ -91,7 +92,8 @@ >> TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT >> void operator=(const TargetMachine &); // DO NOT IMPLEMENT >> protected: // Can only create subclasses. >> - TargetMachine(const Target &); >> + TargetMachine(const Target &T, StringRef TargetTriple, >> + StringRef CPU, StringRef FS); >> >> /// getSubtargetImpl - virtual method implemented by subclasses that >> returns >> /// a reference to that target's TargetSubtargetInfo-derived member >> variable. >> @@ -100,6 +102,12 @@ >> /// TheTarget - The Target that this machine was created for. >> const Target &TheTarget; >> >> + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and >> target >> + /// feature strings the TargetMachine instance is created with. >> + std::string TargetTriple; >> + std::string TargetCPU; >> + std::string TargetFS; >> + >> /// AsmInfo - Contains target specific asm information. >> /// >> const MCAsmInfo *AsmInfo; >> @@ -115,6 +123,10 @@ >> >> const Target &getTarget() const { return TheTarget; } >> >> + const StringRef getTargetTriple() const { return TargetTriple; } >> + const StringRef getTargetCPU() const { return TargetCPU; } >> + const StringRef getTargetFeatureString() const { return TargetFS; } >> + >> // Interfaces to the major aspects of target machine information: >> // -- Instruction opcode and operand information >> // -- Pipelines and scheduling information >> @@ -295,10 +307,9 @@ >> /// implemented with the LLVM target-independent code generator. >> /// >> class LLVMTargetMachine : public TargetMachine { >> - std::string TargetTriple; >> - >> protected: // Can only create subclasses. >> - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); >> + LLVMTargetMachine(const Target &T, StringRef TargetTriple, >> + StringRef CPU, StringRef FS); >> >> private: >> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for >> @@ -311,9 +322,6 @@ >> virtual void setCodeModelForStatic(); >> >> public: >> - >> - const std::string &getTargetTriple() const { return TargetTriple; } >> - >> /// addPassesToEmitFile - Add passes to the specified pass manager to >> get the >> /// specified file emitted. Typically this will involve several steps >> of code >> /// generation. If OptLevel is None, the code generator should emit >> code as >> >> Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) >> +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 >> 2011 >> @@ -35,7 +35,6 @@ >> class MCInstPrinter; >> class MCInstrInfo; >> class MCRegisterInfo; >> - class MCSubtargetInfo; >> class MCStreamer; >> class TargetAsmBackend; >> class TargetAsmLexer; >> @@ -70,9 +69,6 @@ >> StringRef TT); >> typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); >> typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); >> - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, >> - StringRef CPU, >> - StringRef >> Features); >> typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, >> const std::string &TT, >> const std::string &CPU, >> @@ -83,8 +79,9 @@ >> const std::string &TT); >> typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, >> const MCAsmInfo &MAI); >> - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target >> &T,MCAsmParser &P, >> - TargetMachine &TM); >> + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, >> StringRef TT, >> + StringRef CPU, StringRef >> Features, >> + MCAsmParser &P); >> typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); >> typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, >> unsigned SyntaxVariant, >> @@ -140,10 +137,6 @@ >> /// if registered. >> MCRegInfoCtorFnTy MCRegInfoCtorFn; >> >> - /// MCSubtargetInfoCtorFn - Constructor function for this target's >> - /// MCSubtargetInfo, if registered. >> - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; >> - >> /// TargetMachineCtorFn - Construction function for this target's >> /// TargetMachine, if registered. >> TargetMachineCtorTy TargetMachineCtorFn; >> @@ -269,22 +262,6 @@ >> return MCRegInfoCtorFn(); >> } >> >> - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. >> - /// >> - /// \arg Triple - This argument is used to determine the target >> machine >> - /// feature set; it should always be provided. Generally this should >> be >> - /// either the target triple from the module, or the target triple of >> the >> - /// host if that does not exist. >> - /// \arg CPU - This specifies the name of the target CPU. >> - /// \arg Features - This specifies the string representation of the >> - /// additional target features. >> - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef >> CPU, >> - StringRef Features) const { >> - if (!MCSubtargetInfoCtorFn) >> - return 0; >> - return MCSubtargetInfoCtorFn(Triple, CPU, Features); >> - } >> - >> /// createTargetMachine - Create a target specific machine >> implementation >> /// for the specified \arg Triple. >> /// >> @@ -322,11 +299,11 @@ >> /// >> /// \arg Parser - The target independent parser implementation to use >> for >> /// parsing and lexing. >> - TargetAsmParser *createAsmParser(MCAsmParser &Parser, >> - TargetMachine &TM) const { >> + TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, >> + StringRef Features, MCAsmParser >> &Parser) const { >> if (!AsmParserCtorFn) >> return 0; >> - return AsmParserCtorFn(*this, Parser, TM); >> + return AsmParserCtorFn(*this, Triple, CPU, Features, Parser); >> } >> >> /// createAsmPrinter - Create a target specific assembly printer pass. >> This >> @@ -528,22 +505,6 @@ >> T.MCRegInfoCtorFn = Fn; >> } >> >> - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo >> implementation for >> - /// the given target. >> - /// >> - /// Clients are responsible for ensuring that registration doesn't >> occur >> - /// while another thread is attempting to access the registry. >> Typically >> - /// this is done by initializing all targets at program startup. >> - /// >> - /// @param T - The target being registered. >> - /// @param Fn - A function to construct a MCSubtargetInfo for the >> target. >> - static void RegisterMCSubtargetInfo(Target &T, >> - Target::MCSubtargetInfoCtorFnTy >> Fn) { >> - // Ignore duplicate registration. >> - if (!T.MCSubtargetInfoCtorFn) >> - T.MCSubtargetInfoCtorFn = Fn; >> - } >> - >> /// RegisterTargetMachine - Register a TargetMachine implementation >> for the >> /// given target. >> /// >> @@ -820,40 +781,6 @@ >> } >> }; >> >> - /// RegisterMCSubtargetInfo - Helper template for registering a target >> - /// subtarget info implementation. This invokes the static "Create" >> method >> - /// on the class to actually do the construction. Usage: >> - /// >> - /// extern "C" void LLVMInitializeFooTarget() { >> - /// extern Target TheFooTarget; >> - /// RegisterMCSubtargetInfo X(TheFooTarget); >> - /// } >> - template >> - struct RegisterMCSubtargetInfo { >> - RegisterMCSubtargetInfo(Target &T) { >> - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); >> - } >> - private: >> - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, >> - StringRef FS) { >> - return new MCSubtargetInfoImpl(); >> - } >> - }; >> - >> - /// RegisterMCSubtargetInfoFn - Helper template for registering a >> target >> - /// subtarget info implementation. This invokes the specified function >> to >> - /// do the construction. Usage: >> - /// >> - /// extern "C" void LLVMInitializeFooTarget() { >> - /// extern Target TheFooTarget; >> - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); >> - /// } >> - struct RegisterMCSubtargetInfoFn { >> - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy >> Fn) { >> - TargetRegistry::RegisterMCSubtargetInfo(T, Fn); >> - } >> - }; >> - >> /// RegisterTargetMachine - Helper template for registering a target >> machine >> /// implementation, for use in the target machine initialization >> /// function. Usage: >> @@ -931,9 +858,10 @@ >> } >> >> private: >> - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, >> - TargetMachine &TM) { >> - return new AsmParserImpl(T, P, TM); >> + static TargetAsmParser *Allocator(const Target &T, StringRef TT, >> + StringRef CPU, StringRef FS, >> + MCAsmParser &P) { >> + return new AsmParserImpl(T, TT, CPU, FS, P); >> } >> }; >> >> >> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -111,7 +111,12 @@ >> OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, >> OutContext, OutStreamer, >> *MAI)); >> - OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, >> TM)); >> + >> + OwningPtr >> + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), >> + TM.getTargetCPU(), >> + TM.getTargetFeatureString(), >> + *Parser)); >> if (!TAP) >> report_fatal_error("Inline asm not supported by this streamer because" >> " we don't have an asm parser for this target\n"); >> >> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) >> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011 >> @@ -98,10 +98,10 @@ >> EnableFastISelOption("fast-isel", cl::Hidden, >> cl::desc("Enable the \"fast\" instruction selector")); >> >> -LLVMTargetMachine::LLVMTargetMachine(const Target &T, >> - const std::string &Triple) >> - : TargetMachine(T), TargetTriple(Triple) { >> - AsmInfo = T.createAsmInfo(TargetTriple); >> +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, >> + StringRef CPU, StringRef FS) >> + : TargetMachine(T, Triple, CPU, FS) { >> + AsmInfo = T.createAsmInfo(Triple); >> } >> >> // Set the default code model for the JIT for a generic target. >> @@ -143,7 +143,7 @@ >> TargetAsmBackend *TAB = 0; >> if (ShowMCEncoding) { >> MCE = getTarget().createCodeEmitter(*this, *Context); >> - TAB = getTarget().createAsmBackend(TargetTriple); >> + TAB = getTarget().createAsmBackend(getTargetTriple()); >> } >> >> MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, >> @@ -160,12 +160,12 @@ >> // Create the code emitter for the target if it exists. If not, .o >> file >> // emission fails. >> MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); >> - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); >> + TargetAsmBackend *TAB = >> getTarget().createAsmBackend(getTargetTriple()); >> if (MCE == 0 || TAB == 0) >> return true; >> >> - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, >> *Context, >> - *TAB, Out, MCE, >> + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), >> + *Context, *TAB, >> Out, MCE, >> hasMCRelaxAll(), >> >> hasMCNoExecStack())); >> AsmStreamer.get()->InitSections(); >> @@ -241,12 +241,12 @@ >> // Create the code emitter for the target if it exists. If not, .o file >> // emission fails. >> MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); >> - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); >> + TargetAsmBackend *TAB = >> getTarget().createAsmBackend(getTargetTriple()); >> if (MCE == 0 || TAB == 0) >> return true; >> >> OwningPtr AsmStreamer; >> - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx, >> + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), >> *Ctx, >> *TAB, Out, MCE, >> hasMCRelaxAll(), >> hasMCNoExecStack())); >> >> Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) >> +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -171,7 +171,7 @@ >> std::string featureString; >> TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, >> featureString)); >> - >> + >> const TargetRegisterInfo *registerInfo = >> TargetMachine->getRegisterInfo(); >> >> if (!registerInfo) >> @@ -183,7 +183,7 @@ >> >> if (!AsmInfo) >> return; >> - >> + >> Disassembler.reset(Tgt->createMCDisassembler()); >> >> if (!Disassembler) >> @@ -371,8 +371,10 @@ >> OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, >> context, >> *streamer, >> *AsmInfo)); >> - OwningPtr >> TargetParser(Tgt->createAsmParser(*genericParser, >> - >> *TargetMachine)); >> + >> + StringRef triple = tripleFromArch(Key.Arch); >> + OwningPtr TargetParser(Tgt->createAsmParser(triple, >> "", "", >> + >> *genericParser)); >> >> AsmToken OpcodeToken = genericParser->Lex(); >> AsmToken NextToken = genericParser->Lex(); // consume next token, >> because specificParser expects us to >> >> Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) >> +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 >> 2011 >> @@ -41,6 +41,7 @@ >> class MCInst; >> class MCParsedAsmOperand; >> class MCStreamer; >> +class MCSubtargetInfo; >> template class SmallVectorImpl; >> class SourceMgr; >> class Target; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011 >> @@ -147,35 +147,48 @@ >> >> //===----------------------------------------------------------------------===// >> // ARM Instruction Predicate Definitions. >> // >> -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, >> AssemblerPredicate; >> +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, >> + AssemblerPredicate<"HasV4TOps">; >> def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; >> def HasV5T : Predicate<"Subtarget->hasV5TOps()">; >> -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, >> AssemblerPredicate; >> -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, >> AssemblerPredicate; >> +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, >> + AssemblerPredicate<"HasV5TEOps">; >> +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, >> + AssemblerPredicate<"HasV6Ops">; >> def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; >> -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, >> AssemblerPredicate; >> +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, >> + AssemblerPredicate<"HasV6T2Ops">; >> def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; >> -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, >> AssemblerPredicate; >> +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, >> + AssemblerPredicate<"HasV7Ops">; >> def NoVFP : Predicate<"!Subtarget->hasVFP2()">; >> -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, >> AssemblerPredicate; >> -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, >> AssemblerPredicate; >> -def HasNEON : Predicate<"Subtarget->hasNEON()">, >> AssemblerPredicate; >> -def HasFP16 : Predicate<"Subtarget->hasFP16()">, >> AssemblerPredicate; >> -def HasDivide : Predicate<"Subtarget->hasDivide()">, >> AssemblerPredicate; >> +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, >> + AssemblerPredicate<"FeatureVFP2">; >> +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, >> + AssemblerPredicate<"FeatureVFP3">; >> +def HasNEON : Predicate<"Subtarget->hasNEON()">, >> + AssemblerPredicate<"FeatureNEON">; >> +def HasFP16 : Predicate<"Subtarget->hasFP16()">, >> + AssemblerPredicate<"FeatureFP16">; >> +def HasDivide : Predicate<"Subtarget->hasDivide()">, >> + AssemblerPredicate<"FeatureHWDiv">; >> def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, >> - AssemblerPredicate; >> + AssemblerPredicate<"FeatureT2XtPk">; >> def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, >> - AssemblerPredicate; >> + AssemblerPredicate<"FeatureDSPThumb2">; >> def HasDB : Predicate<"Subtarget->hasDataBarrier()">, >> - AssemblerPredicate; >> + AssemblerPredicate<"FeatureDB">; >> def HasMP : Predicate<"Subtarget->hasMPExtension()">, >> - AssemblerPredicate; >> + AssemblerPredicate<"FeatureMP">; >> def UseNEONForFP : >> Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; >> def DontUseNEONForFP : >> Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; >> -def IsThumb : Predicate<"Subtarget->isThumb()">, >> AssemblerPredicate; >> +def IsThumb : Predicate<"Subtarget->isThumb()">, >> + AssemblerPredicate<"ModeThumb">; >> def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; >> -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, >> AssemblerPredicate; >> -def IsARM : Predicate<"!Subtarget->isThumb()">, >> AssemblerPredicate; >> +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, >> + >> AssemblerPredicate<"ModeThumb,FeatureThumb2">; >> +def IsARM : Predicate<"!Subtarget->isThumb()">, >> + AssemblerPredicate<"!ModeThumb">; >> def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; >> def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011 >> @@ -18,9 +18,10 @@ >> #include "llvm/Support/CommandLine.h" >> #include "llvm/ADT/SmallVector.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "ARMGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -80,7 +80,7 @@ >> const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> JITInfo(), >> InstrItins(Subtarget.getInstrItineraryData()) { >> >> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -20,6 +20,7 @@ >> #include "llvm/MC/MCStreamer.h" >> #include "llvm/MC/MCExpr.h" >> #include "llvm/MC/MCInst.h" >> +#include "llvm/MC/MCSubtargetInfo.h" >> #include "llvm/Target/TargetRegistry.h" >> #include "llvm/Target/TargetAsmParser.h" >> #include "llvm/Support/SourceMgr.h" >> @@ -28,6 +29,10 @@ >> #include "llvm/ADT/StringExtras.h" >> #include "llvm/ADT/StringSwitch.h" >> #include "llvm/ADT/Twine.h" >> + >> +#define GET_SUBTARGETINFO_ENUM >> +#include "ARMGenSubtargetInfo.inc" >> + >> using namespace llvm; >> >> namespace { >> @@ -36,7 +41,7 @@ >> >> class ARMAsmParser : public TargetAsmParser { >> MCAsmParser &Parser; >> - TargetMachine &TM; >> + MCSubtargetInfo *STI; >> >> MCAsmParser &getParser() const { return Parser; } >> MCAsmLexer &getLexer() const { return Parser.getLexer(); } >> @@ -79,6 +84,15 @@ >> void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, >> bool &CanAcceptPredicationCode); >> >> + bool isThumb() const { >> + // FIXME: Can tablegen auto-generate this? >> + return (STI->getFeatureBits() & ARM::ModeThumb) != 0; >> + } >> + >> + bool isThumbOne() const { >> + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == >> 0; >> + } >> + >> /// @name Auto-generated Match Functions >> /// { >> >> @@ -113,13 +127,15 @@ >> const >> SmallVectorImpl &); >> >> public: >> - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) >> - : TargetAsmParser(T), Parser(_Parser), TM(_TM) { >> - MCAsmParserExtension::Initialize(_Parser); >> - // Initialize the set of available features. >> - setAvailableFeatures(ComputeAvailableFeatures( >> - &TM.getSubtarget())); >> - } >> + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef >> FS, >> + MCAsmParser &_Parser) >> + : TargetAsmParser(T), Parser(_Parser) { >> + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); >> + >> + MCAsmParserExtension::Initialize(_Parser); >> + // Initialize the set of available features. >> + >> setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); >> + } >> >> virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, >> SmallVectorImpl >> &Operands); >> @@ -1852,9 +1868,6 @@ >> void ARMAsmParser:: >> GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, >> bool &CanAcceptPredicationCode) { >> - bool isThumbOne = TM.getSubtarget().isThumb1Only(); >> - bool isThumb = TM.getSubtarget().isThumb(); >> - >> if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || >> Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || >> Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || >> @@ -1863,7 +1876,7 @@ >> Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || >> Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || >> Mnemonic == "eor" || Mnemonic == "smlal" || >> - (Mnemonic == "mov" && !isThumbOne)) { >> + (Mnemonic == "mov" && !isThumbOne())) { >> CanAcceptCarrySet = true; >> } else { >> CanAcceptCarrySet = false; >> @@ -1880,7 +1893,7 @@ >> CanAcceptPredicationCode = true; >> } >> >> - if (isThumb) >> + if (isThumb()) >> if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || >> Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") >> CanAcceptPredicationCode = false; >> @@ -2207,12 +2220,12 @@ >> // includes Feature_IsThumb or not to match the right instructions. >> This is >> // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. >> if (Val == 16){ >> - assert(TM.getSubtarget().isThumb() && >> + assert(isThumb() && >> "switching between arm/thumb not yet suppported via .code 16)"); >> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); >> } >> else{ >> - assert(!TM.getSubtarget().isThumb() && >> + assert(!isThumb() && >> "switching between thumb/arm not yet suppported via .code >> 32)"); >> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); >> } >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -23,65 +23,12 @@ >> #define GET_INSTRINFO_MC_DESC >> #include "ARMGenInstrInfo.inc" >> >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #include "ARMGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> -MCInstrInfo *createARMMCInstrInfo() { >> - MCInstrInfo *X = new MCInstrInfo(); >> - InitARMMCInstrInfo(X); >> - return X; >> -} >> - >> -MCRegisterInfo *createARMMCRegisterInfo() { >> - MCRegisterInfo *X = new MCRegisterInfo(); >> - InitARMMCRegisterInfo(X); >> - return X; >> -} >> - >> -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, >> - StringRef FS) { >> - std::string ArchFS = ARM_MC::ParseARMTriple(TT); >> - if (!FS.empty()) { >> - if (!ArchFS.empty()) >> - ArchFS = ArchFS + "," + FS.str(); >> - else >> - ArchFS = FS; >> - } >> - >> - MCSubtargetInfo *X = new MCSubtargetInfo(); >> - InitARMMCSubtargetInfo(X, CPU, ArchFS); >> - return X; >> -} >> - >> -// Force static initialization. >> -extern "C" void LLVMInitializeARMMCInstrInfo() { >> - RegisterMCInstrInfo X(TheARMTarget); >> - RegisterMCInstrInfo Y(TheThumbTarget); >> - >> - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, >> createARMMCInstrInfo); >> - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, >> createARMMCInstrInfo); >> -} >> - >> -extern "C" void LLVMInitializeARMMCRegInfo() { >> - RegisterMCRegInfo X(TheARMTarget); >> - RegisterMCRegInfo Y(TheThumbTarget); >> - >> - TargetRegistry::RegisterMCRegInfo(TheARMTarget, >> createARMMCRegisterInfo); >> - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, >> createARMMCRegisterInfo); >> -} >> - >> -extern "C" void LLVMInitializeARMMCSubtargetInfo() { >> - RegisterMCSubtargetInfo X(TheARMTarget); >> - RegisterMCSubtargetInfo Y(TheThumbTarget); >> - >> - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, >> - createARMMCSubtargetInfo); >> - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, >> - createARMMCSubtargetInfo); >> -} >> - >> std::string ARM_MC::ParseARMTriple(StringRef TT) { >> // Set the boolean corresponding to the current target triple, or the >> default >> // if one cannot be determined, to true. >> @@ -135,3 +82,47 @@ >> >> return ARMArchFeature; >> } >> + >> +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef >> CPU, >> + StringRef FS) { >> + std::string ArchFS = ARM_MC::ParseARMTriple(TT); >> + if (!FS.empty()) { >> + if (!ArchFS.empty()) >> + ArchFS = ArchFS + "," + FS.str(); >> + else >> + ArchFS = FS; >> + } >> + >> + MCSubtargetInfo *X = new MCSubtargetInfo(); >> + InitARMMCSubtargetInfo(X, CPU, ArchFS); >> + return X; >> +} >> + >> +MCInstrInfo *createARMMCInstrInfo() { >> + MCInstrInfo *X = new MCInstrInfo(); >> + InitARMMCInstrInfo(X); >> + return X; >> +} >> + >> +MCRegisterInfo *createARMMCRegisterInfo() { >> + MCRegisterInfo *X = new MCRegisterInfo(); >> + InitARMMCRegisterInfo(X); >> + return X; >> +} >> + >> +// Force static initialization. >> +extern "C" void LLVMInitializeARMMCInstrInfo() { >> + RegisterMCInstrInfo X(TheARMTarget); >> + RegisterMCInstrInfo Y(TheThumbTarget); >> + >> + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, >> createARMMCInstrInfo); >> + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, >> createARMMCInstrInfo); >> +} >> + >> +extern "C" void LLVMInitializeARMMCRegInfo() { >> + RegisterMCRegInfo X(TheARMTarget); >> + RegisterMCRegInfo Y(TheThumbTarget); >> + >> + TargetRegistry::RegisterMCRegInfo(TheARMTarget, >> createARMMCRegisterInfo); >> + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, >> createARMMCRegisterInfo); >> +} >> >> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) >> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 >> 20:53:10 2011 >> @@ -17,6 +17,7 @@ >> #include >> >> namespace llvm { >> +class MCSubtargetInfo; >> class Target; >> class StringRef; >> >> @@ -24,6 +25,12 @@ >> >> namespace ARM_MC { >> std::string ParseARMTriple(StringRef TT); >> + >> + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. >> + /// This is exposed so Asm parser, etc. do not need to go through >> + /// TargetRegistry. >> + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, >> + StringRef FS); >> } >> >> } // End llvm namespace >> >> Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -14,9 +14,10 @@ >> #include "AlphaSubtarget.h" >> #include "Alpha.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "AlphaGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -27,7 +27,7 @@ >> AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> DataLayout("e-f128:128:128-n64"), >> FrameLowering(Subtarget), >> Subtarget(TT, CPU, FS), >> >> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -13,9 +13,10 @@ >> >> #include "BlackfinSubtarget.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "BlackfinGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -28,7 +28,7 @@ >> const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> DataLayout("e-p:32:32-i64:32-f64:32-n32"), >> Subtarget(TT, CPU, FS), >> TLInfo(*this), >> >> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) >> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 >> 2011 >> @@ -22,7 +22,7 @@ >> struct CTargetMachine : public TargetMachine { >> CTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, const std::string &FS) >> - : TargetMachine(T) {} >> + : TargetMachine(T, TT, CPU, FS) {} >> >> virtual bool addPassesToEmitFile(PassManagerBase &PM, >> formatted_raw_ostream &Out, >> >> Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -13,12 +13,13 @@ >> >> #include "SPUSubtarget.h" >> #include "SPU.h" >> -#include "llvm/ADT/SmallVector.h" >> #include "SPURegisterInfo.h" >> +#include "llvm/ADT/SmallVector.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "SPUGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -36,7 +36,7 @@ >> >> SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU,const >> std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> DataLayout(Subtarget.getTargetDataString()), >> InstrInfo(*this), >> >> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) >> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 >> 20:53:10 2011 >> @@ -24,7 +24,7 @@ >> struct CPPTargetMachine : public TargetMachine { >> CPPTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, const std::string &FS) >> - : TargetMachine(T) {} >> + : TargetMachine(T, TT, CPU, FS) {} >> >> virtual bool addPassesToEmitFile(PassManagerBase &PM, >> formatted_raw_ostream &Out, >> >> Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) >> +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -32,7 +32,6 @@ >> >> class MBlazeAsmParser : public TargetAsmParser { >> MCAsmParser &Parser; >> - TargetMachine &TM; >> >> MCAsmParser &getParser() const { return Parser; } >> MCAsmLexer &getLexer() const { return Parser.getLexer(); } >> @@ -64,8 +63,9 @@ >> >> >> public: >> - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine >> &_TM) >> - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} >> + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef >> FS, >> + MCAsmParser &_Parser) >> + : TargetAsmParser(T), Parser(_Parser) {} >> >> virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, >> SmallVectorImpl >> &Operands); >> >> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -16,9 +16,10 @@ >> #include "MBlazeRegisterInfo.h" >> #include "llvm/Support/CommandLine.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "MBlazeGenSubtargetInfo.inc" >> >> using namespace llvm; >> @@ -61,4 +62,3 @@ >> CriticalPathRCs.push_back(&MBlaze::GPRRegClass); >> return HasItin && OptLevel >= CodeGenOpt::Default; >> } >> - >> >> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -81,7 +81,7 @@ >> MBlazeTargetMachine:: >> MBlazeTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, const std::string &FS): >> - LLVMTargetMachine(T, TT), >> + LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), >> InstrInfo(*this), >> >> Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) >> +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -14,9 +14,10 @@ >> #include "MSP430Subtarget.h" >> #include "MSP430.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "MSP430GenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -30,7 +30,7 @@ >> const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> // FIXME: Check TargetData string. >> DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), >> >> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011 >> @@ -14,9 +14,10 @@ >> #include "MipsSubtarget.h" >> #include "Mips.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "MipsGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -37,7 +37,7 @@ >> MipsTargetMachine(const Target &T, const std::string &TT, >> const std::string &CPU, const std::string &FS, >> bool isLittle=false): >> - LLVMTargetMachine(T, TT), >> + LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS, isLittle), >> DataLayout(isLittle ? >> std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : >> >> Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011 >> @@ -14,9 +14,10 @@ >> #include "PTXSubtarget.h" >> #include "llvm/Support/ErrorHandling.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "PTXGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -55,7 +55,7 @@ >> const std::string &CPU, >> const std::string &FS, >> bool is64Bit) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> DataLayout(is64Bit ? DataLayout64 : DataLayout32), >> Subtarget(TT, CPU, FS, is64Bit), >> FrameLowering(Subtarget), >> >> Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -17,9 +17,10 @@ >> #include "llvm/Target/TargetMachine.h" >> #include >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "PPCGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -69,7 +69,7 @@ >> PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU, >> const std::string &FS, bool is64Bit) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS, is64Bit), >> DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), >> FrameLowering(Subtarget), JITInfo(*this, is64Bit), >> >> Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -13,9 +13,10 @@ >> >> #include "SparcSubtarget.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "SparcGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -32,7 +32,7 @@ >> SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU, >> const std::string &FS, bool >> is64bit) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS, is64bit), >> DataLayout(Subtarget.getDataLayout()), >> TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), >> >> Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -16,9 +16,10 @@ >> #include "llvm/GlobalValue.h" >> #include "llvm/Target/TargetMachine.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "SystemZGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -26,7 +26,7 @@ >> const std::string &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> >> DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" >> "-f64:64:64-f128:128:128-a0:16:16-n32:64"), >> >> Modified: llvm/trunk/lib/Target/TargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/TargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011 >> @@ -216,8 +216,9 @@ >> // TargetMachine Class >> // >> >> -TargetMachine::TargetMachine(const Target &T) >> - : TheTarget(T), AsmInfo(0), >> +TargetMachine::TargetMachine(const Target &T, >> + StringRef TT, StringRef CPU, StringRef FS) >> + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), >> AsmInfo(0), >> MCRelaxAll(false), >> MCNoExecStack(false), >> MCSaveTempLabels(false), >> >> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) >> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -15,6 +15,7 @@ >> #include "llvm/MC/MCStreamer.h" >> #include "llvm/MC/MCExpr.h" >> #include "llvm/MC/MCInst.h" >> +#include "llvm/MC/MCSubtargetInfo.h" >> #include "llvm/MC/MCParser/MCAsmLexer.h" >> #include "llvm/MC/MCParser/MCAsmParser.h" >> #include "llvm/MC/MCParser/MCParsedAsmOperand.h" >> @@ -25,6 +26,10 @@ >> #include "llvm/ADT/Twine.h" >> #include "llvm/Support/SourceMgr.h" >> #include "llvm/Support/raw_ostream.h" >> + >> +#define GET_SUBTARGETINFO_ENUM >> +#include "X86GenSubtargetInfo.inc" >> + >> using namespace llvm; >> >> namespace { >> @@ -32,10 +37,7 @@ >> >> class X86ATTAsmParser : public TargetAsmParser { >> MCAsmParser &Parser; >> - TargetMachine &TM; >> - >> -protected: >> - unsigned Is64Bit : 1; >> + MCSubtargetInfo *STI; >> >> private: >> MCAsmParser &getParser() const { return Parser; } >> @@ -61,6 +63,11 @@ >> /// or %es:(%edi) in 32bit mode. >> bool isDstOp(X86Operand &Op); >> >> + bool is64Bit() { >> + // FIXME: Can tablegen auto-generate this? >> + return (STI->getFeatureBits() & X86::Mode64Bit) != 0; >> + } >> + >> /// @name Auto-generated Matcher Functions >> /// { >> >> @@ -70,12 +77,13 @@ >> /// } >> >> public: >> - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine >> &TM) >> - : TargetAsmParser(T), Parser(parser), TM(TM) { >> + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef >> FS, >> + MCAsmParser &parser) >> + : TargetAsmParser(T), Parser(parser) { >> + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); >> >> // Initialize the set of available features. >> - setAvailableFeatures(ComputeAvailableFeatures( >> - &TM.getSubtarget())); >> + >> setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); >> } >> virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc >> &EndLoc); >> >> @@ -84,23 +92,6 @@ >> >> virtual bool ParseDirective(AsmToken DirectiveID); >> }; >> - >> -class X86_32ATTAsmParser : public X86ATTAsmParser { >> -public: >> - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine >> &TM) >> - : X86ATTAsmParser(T, Parser, TM) { >> - Is64Bit = false; >> - } >> -}; >> - >> -class X86_64ATTAsmParser : public X86ATTAsmParser { >> -public: >> - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine >> &TM) >> - : X86ATTAsmParser(T, Parser, TM) { >> - Is64Bit = true; >> - } >> -}; >> - >> } // end anonymous namespace >> >> /// @name Auto-generated Match Functions >> @@ -365,7 +356,7 @@ >> } // end anonymous namespace. >> >> bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { >> - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI; >> + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; >> >> return (Op.isMem() && >> (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && >> @@ -375,7 +366,7 @@ >> } >> >> bool X86ATTAsmParser::isDstOp(X86Operand &Op) { >> - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI; >> + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; >> >> return Op.isMem() && Op.Mem.SegReg == X86::ES && >> isa(Op.Mem.Disp) && >> @@ -406,7 +397,7 @@ >> // FIXME: This should be done using Requires and >> // Requires so "eiz" usage in 64-bit instructions >> // can be also checked. >> - if (RegNo == X86::RIZ && !Is64Bit) >> + if (RegNo == X86::RIZ && !is64Bit()) >> return Error(Tok.getLoc(), "riz register in 64-bit mode only"); >> >> // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. >> @@ -826,7 +817,7 @@ >> // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" >> if (Name.startswith("movs") && Operands.size() == 3 && >> (Name == "movsb" || Name == "movsw" || Name == "movsl" || >> - (Is64Bit && Name == "movsq"))) { >> + (is64Bit() && Name == "movsq"))) { >> X86Operand &Op = *(X86Operand*)Operands.begin()[1]; >> X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; >> if (isSrcOp(Op) && isDstOp(Op2)) { >> @@ -839,7 +830,7 @@ >> // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" >> if (Name.startswith("lods") && Operands.size() == 3 && >> (Name == "lods" || Name == "lodsb" || Name == "lodsw" || >> - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) { >> + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { >> X86Operand *Op1 = static_cast(Operands[1]); >> X86Operand *Op2 = static_cast(Operands[2]); >> if (isSrcOp(*Op1) && Op2->isReg()) { >> @@ -869,7 +860,7 @@ >> // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" >> if (Name.startswith("stos") && Operands.size() == 3 && >> (Name == "stos" || Name == "stosb" || Name == "stosw" || >> - Name == "stosl" || (Is64Bit && Name == "stosq"))) { >> + Name == "stosl" || (is64Bit() && Name == "stosq"))) { >> X86Operand *Op1 = static_cast(Operands[1]); >> X86Operand *Op2 = static_cast(Operands[2]); >> if (isDstOp(*Op2) && Op1->isReg()) { >> @@ -1144,8 +1135,8 @@ >> >> // Force static initialization. >> extern "C" void LLVMInitializeX86AsmParser() { >> - RegisterAsmParser X(TheX86_32Target); >> - RegisterAsmParser Y(TheX86_64Target); >> + RegisterAsmParser X(TheX86_32Target); >> + RegisterAsmParser Y(TheX86_64Target); >> LLVMInitializeX86AsmLexer(); >> } >> >> >> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) >> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 >> 20:53:10 2011 >> @@ -25,6 +25,7 @@ >> #define GET_INSTRINFO_MC_DESC >> #include "X86GenInstrInfo.inc" >> >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #include "X86GenSubtargetInfo.inc" >> >> @@ -35,7 +36,7 @@ >> Triple TheTriple(TT); >> if (TheTriple.getArch() == Triple::x86_64) >> return "+64bit-mode"; >> - return ""; >> + return "-64bit-mode"; >> } >> >> /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values >> in the >> @@ -128,20 +129,8 @@ >> return false; >> } >> >> -MCInstrInfo *createX86MCInstrInfo() { >> - MCInstrInfo *X = new MCInstrInfo(); >> - InitX86MCInstrInfo(X); >> - return X; >> -} >> - >> -MCRegisterInfo *createX86MCRegisterInfo() { >> - MCRegisterInfo *X = new MCRegisterInfo(); >> - InitX86MCRegisterInfo(X); >> - return X; >> -} >> - >> -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, >> - StringRef FS) { >> +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef >> CPU, >> + StringRef FS) { >> std::string ArchFS = X86_MC::ParseX86Triple(TT); >> if (!FS.empty()) { >> if (!ArchFS.empty()) >> @@ -159,7 +148,19 @@ >> ArchFS = "+64bit-mode"; >> >> MCSubtargetInfo *X = new MCSubtargetInfo(); >> - InitX86MCSubtargetInfo(X, CPU, ArchFS); >> + InitX86MCSubtargetInfo(X, CPUName, ArchFS); >> + return X; >> +} >> + >> +MCInstrInfo *createX86MCInstrInfo() { >> + MCInstrInfo *X = new MCInstrInfo(); >> + InitX86MCInstrInfo(X); >> + return X; >> +} >> + >> +MCRegisterInfo *createX86MCRegisterInfo() { >> + MCRegisterInfo *X = new MCRegisterInfo(); >> + InitX86MCRegisterInfo(X); >> return X; >> } >> >> @@ -179,13 +180,3 @@ >> TargetRegistry::RegisterMCRegInfo(TheX86_32Target, >> createX86MCRegisterInfo); >> TargetRegistry::RegisterMCRegInfo(TheX86_64Target, >> createX86MCRegisterInfo); >> } >> - >> -extern "C" void LLVMInitializeX86MCSubtargetInfo() { >> - RegisterMCSubtargetInfo X(TheX86_32Target); >> - RegisterMCSubtargetInfo Y(TheX86_64Target); >> - >> - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, >> - createX86MCSubtargetInfo); >> - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, >> - createX86MCSubtargetInfo); >> -} >> >> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) >> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 >> 20:53:10 2011 >> @@ -17,6 +17,7 @@ >> #include >> >> namespace llvm { >> +class MCSubtargetInfo; >> class Target; >> class StringRef; >> >> @@ -31,9 +32,17 @@ >> unsigned *rEBX, unsigned *rECX, unsigned *rEDX); >> >> void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); >> + >> + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. >> + /// This is exposed so Asm parser, etc. do not need to go through >> + /// TargetRegistry. >> + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, >> + StringRef FS); >> } >> + >> } // End llvm namespace >> >> + >> // Defines symbolic names for X86 registers. This defines a mapping from >> // register name to register number. >> // >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011 >> @@ -438,8 +438,10 @@ >> def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; >> def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; >> def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; >> -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, >> AssemblerPredicate; >> -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate; >> +def In32BitMode : Predicate<"!Subtarget->is64Bit()">, >> + AssemblerPredicate<"!Mode64Bit">; >> +def In64BitMode : Predicate<"Subtarget->is64Bit()">, >> + AssemblerPredicate<"Mode64Bit">; >> def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; >> def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; >> def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; >> >> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011 >> @@ -21,9 +21,10 @@ >> #include "llvm/Target/TargetMachine.h" >> #include "llvm/ADT/SmallVector.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "X86GenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -119,7 +119,7 @@ >> X86TargetMachine::X86TargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU, >> const std::string &FS, bool is64Bit) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS, StackAlignmentOverride), >> FrameLowering(*this, Subtarget), >> ELFWriterInfo(is64Bit, true) { >> >> Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -14,9 +14,10 @@ >> #include "XCoreSubtarget.h" >> #include "XCore.h" >> >> -#define GET_SUBTARGETINFO_CTOR >> +#define GET_SUBTARGETINFO_ENUM >> #define GET_SUBTARGETINFO_MC_DESC >> #define GET_SUBTARGETINFO_TARGET_DESC >> +#define GET_SUBTARGETINFO_CTOR >> #include "XCoreGenSubtargetInfo.inc" >> >> using namespace llvm; >> >> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -23,7 +23,7 @@ >> XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string >> &TT, >> const std::string &CPU, >> const std::string &FS) >> - : LLVMTargetMachine(T, TT), >> + : LLVMTargetMachine(T, TT, CPU, FS), >> Subtarget(TT, CPU, FS), >> DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" >> "i16:16:32-i32:32:32-i64:32:32-n32"), >> >> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) >> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011 >> @@ -371,7 +371,8 @@ >> >> OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, >> *Str.get(), *MAI)); >> - OwningPtr TAP(TheTarget->createAsmParser(*Parser, >> *TM)); >> + OwningPtr >> + TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, >> *Parser)); >> if (!TAP) { >> errs() << ProgName >> << ": error: this target does not support assembly parsing.\n"; >> >> Modified: llvm/trunk/tools/lto/LTOModule.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/tools/lto/LTOModule.cpp (original) >> +++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011 >> @@ -619,7 +619,10 @@ >> Context, *Streamer, >> >> *_target->getMCAsmInfo())); >> OwningPtr >> - TAP(_target->getTarget().createAsmParser(*Parser.get(), >> *_target.get())); >> + TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(), >> + _target->getTargetCPU(), >> + >> _target->getTargetFeatureString(), >> + *Parser.get())); >> Parser->setTargetParser(*TAP); >> int Res = Parser->Run(false); >> if (Res) >> >> Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -1817,15 +1817,43 @@ >> Info.AsmParser->getValueAsString("AsmParserClassName"); >> >> OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" >> - << "ComputeAvailableFeatures(const " << Info.Target.getName() >> - << "Subtarget *Subtarget) const {\n"; >> + << "ComputeAvailableFeatures(uint64_t FB) const {\n"; >> OS << " unsigned Features = 0;\n"; >> for (std::map::const_iterator >> it = Info.SubtargetFeatures.begin(), >> ie = Info.SubtargetFeatures.end(); it != ie; ++it) { >> SubtargetFeatureInfo &SFI = *it->second; >> - OS << " if (" << SFI.TheDef->getValueAsString("CondString") >> - << ")\n"; >> + >> + OS << " if ("; >> + StringRef Conds = >> SFI.TheDef->getValueAsString("AssemblerCondString"); >> + std::pair Comma = Conds.split(','); >> + bool First = true; >> + do { >> + if (!First) >> + OS << " && "; >> + >> + bool Neg = false; >> + StringRef Cond = Comma.first; >> + if (Cond[0] == '!') { >> + Neg = true; >> + Cond = Cond.substr(1); >> + } >> + >> + OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; >> + if (Neg) >> + OS << " == 0"; >> + else >> + OS << " != 0"; >> + OS << ")"; >> + >> + if (Comma.second.empty()) >> + break; >> + >> + First = false; >> + Comma = Comma.second.split(','); >> + } while (true); >> + >> + OS << ")\n"; >> OS << " Features |= " << SFI.getEnumName() << ";\n"; >> } >> OS << " return Features;\n"; >> @@ -2140,8 +2168,7 @@ >> OS << "#undef GET_ASSEMBLER_HEADER\n"; >> OS << " // This should be included into the middle of the declaration >> of\n"; >> OS << " // your subclasses implementation of TargetAsmParser.\n"; >> - OS << " unsigned ComputeAvailableFeatures(const " << >> - Target.getName() << "Subtarget *Subtarget) const;\n"; >> + OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) >> const;\n"; >> OS << " enum MatchResultTy {\n"; >> OS << " Match_ConversionFail,\n"; >> OS << " Match_InvalidOperand,\n"; >> >> Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff >> >> ============================================================================== >> --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 >> 2011 >> @@ -645,12 +645,18 @@ >> >> EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); >> >> + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; >> + OS << "#undef GET_SUBTARGETINFO_ENUM\n"; >> + >> + OS << "namespace llvm {\n"; >> + Enumeration(OS, "SubtargetFeature", true); >> + OS << "} // End llvm namespace \n"; >> + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; >> + >> OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; >> OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; >> >> OS << "namespace llvm {\n"; >> - Enumeration(OS, "SubtargetFeature", true); >> - OS<<"\n"; >> unsigned NumFeatures = FeatureKeyValues(OS); >> OS<<"\n"; >> unsigned NumProcs = CPUKeyValues(OS); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/dd1189c2/attachment-0001.html From evan.cheng at apple.com Thu Jul 7 22:36:36 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Jul 2011 20:36:36 -0700 Subject: [llvm-commits] [llvm] r134678 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Black In-Reply-To: References: Message-ID: <9ECB6B07-16CC-4CF9-A88A-C9CAC97EB5F9@apple.com> Thanks. Sorry I forgot to commit the clang change. :-( Evan On Jul 7, 2011, at 8:16 PM, Chandler Carruth wrote: > Fixed in r134680. > > On Thu, Jul 7, 2011 at 7:39 PM, Nick Lewycky wrote: > Hi Evan, is there a clang half to this change that's coming shortly? > > nlewycky at ducttape:~/llvm/tools/clang/tools/driver$ make > llvm[0]: Compiling cc1as_main.cpp for Debug+Asserts build > cc1as_main.cpp: In function ?bool ExecuteAssembler(::AssemblerInvocation&, clang::Diagnostic&)?: > cc1as_main.cpp:311: error: no matching function for call to ?llvm::Target::createAsmParser(llvm::MCAsmParser&, llvm::TargetMachine&) const? > /usr/local/google/home/nlewycky/llvm/include/llvm/Target/TargetRegistry.h:302: note: candidates are: llvm::TargetAsmParser* llvm::Target::createAsmParser(llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::MCAsmParser&) const > make: *** [/usr/local/google/home/nlewycky/llvm/tools/clang/tools/driver/Debug+Asserts/cc1as_main.o] Error 1 > > Nick > > On 7 July 2011 18:53, Evan Cheng wrote: > Author: evancheng > Date: Thu Jul 7 20:53:10 2011 > New Revision: 134678 > > URL: http://llvm.org/viewvc/llvm-project?rev=134678&view=rev > Log: > Eliminate asm parser's dependency on TargetMachine: > - Each target asm parser now creates its own MCSubtatgetInfo (if needed). > - Changed AssemblerPredicate to take subtarget features which tablegen uses > to generate asm matcher subtarget feature queries. e.g. > "ModeThumb,FeatureThumb2" is translated to > "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". > > Modified: > llvm/trunk/include/llvm/Target/Target.td > llvm/trunk/include/llvm/Target/TargetMachine.h > llvm/trunk/include/llvm/Target/TargetRegistry.h > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp > llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp > llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp > llvm/trunk/lib/Target/CBackend/CTargetMachine.h > llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp > llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h > llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp > llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp > llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp > llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp > llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp > llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp > llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp > llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp > llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp > llvm/trunk/lib/Target/TargetMachine.cpp > llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > llvm/trunk/lib/Target/X86/X86InstrInfo.td > llvm/trunk/lib/Target/X86/X86Subtarget.cpp > llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp > llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > llvm/trunk/tools/llvm-mc/llvm-mc.cpp > llvm/trunk/tools/lto/LTOModule.cpp > llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > llvm/trunk/utils/TableGen/SubtargetEmitter.cpp > > Modified: llvm/trunk/include/llvm/Target/Target.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/Target.td (original) > +++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011 > @@ -382,6 +382,15 @@ > /// matcher, this is true. Targets should set this by inheriting their > /// feature from the AssemblerPredicate class in addition to Predicate. > bit AssemblerMatcherPredicate = 0; > + > + /// AssemblerCondString - Name of the subtarget feature being tested used > + /// as alternative condition string used for assembler matcher. > + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". > + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". > + /// It can also list multiple features separated by ",". > + /// e.g. "ModeThumb,FeatureThumb2" is translated to > + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". > + string AssemblerCondString = ""; > } > > /// NoHonorSignDependentRounding - This predicate is true if support for > @@ -689,8 +698,9 @@ > > /// AssemblerPredicate - This is a Predicate that can be used when the assembler > /// matches instructions and aliases. > -class AssemblerPredicate { > +class AssemblerPredicate { > bit AssemblerMatcherPredicate = 1; > + string AssemblerCondString = cond; > } > > > > Modified: llvm/trunk/include/llvm/Target/TargetMachine.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) > +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 2011 > @@ -14,6 +14,7 @@ > #ifndef LLVM_TARGET_TARGETMACHINE_H > #define LLVM_TARGET_TARGETMACHINE_H > > +#include "llvm/ADT/StringRef.h" > #include > #include > > @@ -91,7 +92,8 @@ > TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT > void operator=(const TargetMachine &); // DO NOT IMPLEMENT > protected: // Can only create subclasses. > - TargetMachine(const Target &); > + TargetMachine(const Target &T, StringRef TargetTriple, > + StringRef CPU, StringRef FS); > > /// getSubtargetImpl - virtual method implemented by subclasses that returns > /// a reference to that target's TargetSubtargetInfo-derived member variable. > @@ -100,6 +102,12 @@ > /// TheTarget - The Target that this machine was created for. > const Target &TheTarget; > > + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target > + /// feature strings the TargetMachine instance is created with. > + std::string TargetTriple; > + std::string TargetCPU; > + std::string TargetFS; > + > /// AsmInfo - Contains target specific asm information. > /// > const MCAsmInfo *AsmInfo; > @@ -115,6 +123,10 @@ > > const Target &getTarget() const { return TheTarget; } > > + const StringRef getTargetTriple() const { return TargetTriple; } > + const StringRef getTargetCPU() const { return TargetCPU; } > + const StringRef getTargetFeatureString() const { return TargetFS; } > + > // Interfaces to the major aspects of target machine information: > // -- Instruction opcode and operand information > // -- Pipelines and scheduling information > @@ -295,10 +307,9 @@ > /// implemented with the LLVM target-independent code generator. > /// > class LLVMTargetMachine : public TargetMachine { > - std::string TargetTriple; > - > protected: // Can only create subclasses. > - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); > + LLVMTargetMachine(const Target &T, StringRef TargetTriple, > + StringRef CPU, StringRef FS); > > private: > /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for > @@ -311,9 +322,6 @@ > virtual void setCodeModelForStatic(); > > public: > - > - const std::string &getTargetTriple() const { return TargetTriple; } > - > /// addPassesToEmitFile - Add passes to the specified pass manager to get the > /// specified file emitted. Typically this will involve several steps of code > /// generation. If OptLevel is None, the code generator should emit code as > > Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) > +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 2011 > @@ -35,7 +35,6 @@ > class MCInstPrinter; > class MCInstrInfo; > class MCRegisterInfo; > - class MCSubtargetInfo; > class MCStreamer; > class TargetAsmBackend; > class TargetAsmLexer; > @@ -70,9 +69,6 @@ > StringRef TT); > typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); > typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); > - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, > - StringRef CPU, > - StringRef Features); > typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, > const std::string &TT, > const std::string &CPU, > @@ -83,8 +79,9 @@ > const std::string &TT); > typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, > const MCAsmInfo &MAI); > - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P, > - TargetMachine &TM); > + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT, > + StringRef CPU, StringRef Features, > + MCAsmParser &P); > typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); > typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, > unsigned SyntaxVariant, > @@ -140,10 +137,6 @@ > /// if registered. > MCRegInfoCtorFnTy MCRegInfoCtorFn; > > - /// MCSubtargetInfoCtorFn - Constructor function for this target's > - /// MCSubtargetInfo, if registered. > - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; > - > /// TargetMachineCtorFn - Construction function for this target's > /// TargetMachine, if registered. > TargetMachineCtorTy TargetMachineCtorFn; > @@ -269,22 +262,6 @@ > return MCRegInfoCtorFn(); > } > > - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. > - /// > - /// \arg Triple - This argument is used to determine the target machine > - /// feature set; it should always be provided. Generally this should be > - /// either the target triple from the module, or the target triple of the > - /// host if that does not exist. > - /// \arg CPU - This specifies the name of the target CPU. > - /// \arg Features - This specifies the string representation of the > - /// additional target features. > - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, > - StringRef Features) const { > - if (!MCSubtargetInfoCtorFn) > - return 0; > - return MCSubtargetInfoCtorFn(Triple, CPU, Features); > - } > - > /// createTargetMachine - Create a target specific machine implementation > /// for the specified \arg Triple. > /// > @@ -322,11 +299,11 @@ > /// > /// \arg Parser - The target independent parser implementation to use for > /// parsing and lexing. > - TargetAsmParser *createAsmParser(MCAsmParser &Parser, > - TargetMachine &TM) const { > + TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, > + StringRef Features, MCAsmParser &Parser) const { > if (!AsmParserCtorFn) > return 0; > - return AsmParserCtorFn(*this, Parser, TM); > + return AsmParserCtorFn(*this, Triple, CPU, Features, Parser); > } > > /// createAsmPrinter - Create a target specific assembly printer pass. This > @@ -528,22 +505,6 @@ > T.MCRegInfoCtorFn = Fn; > } > > - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for > - /// the given target. > - /// > - /// Clients are responsible for ensuring that registration doesn't occur > - /// while another thread is attempting to access the registry. Typically > - /// this is done by initializing all targets at program startup. > - /// > - /// @param T - The target being registered. > - /// @param Fn - A function to construct a MCSubtargetInfo for the target. > - static void RegisterMCSubtargetInfo(Target &T, > - Target::MCSubtargetInfoCtorFnTy Fn) { > - // Ignore duplicate registration. > - if (!T.MCSubtargetInfoCtorFn) > - T.MCSubtargetInfoCtorFn = Fn; > - } > - > /// RegisterTargetMachine - Register a TargetMachine implementation for the > /// given target. > /// > @@ -820,40 +781,6 @@ > } > }; > > - /// RegisterMCSubtargetInfo - Helper template for registering a target > - /// subtarget info implementation. This invokes the static "Create" method > - /// on the class to actually do the construction. Usage: > - /// > - /// extern "C" void LLVMInitializeFooTarget() { > - /// extern Target TheFooTarget; > - /// RegisterMCSubtargetInfo X(TheFooTarget); > - /// } > - template > - struct RegisterMCSubtargetInfo { > - RegisterMCSubtargetInfo(Target &T) { > - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); > - } > - private: > - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, > - StringRef FS) { > - return new MCSubtargetInfoImpl(); > - } > - }; > - > - /// RegisterMCSubtargetInfoFn - Helper template for registering a target > - /// subtarget info implementation. This invokes the specified function to > - /// do the construction. Usage: > - /// > - /// extern "C" void LLVMInitializeFooTarget() { > - /// extern Target TheFooTarget; > - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); > - /// } > - struct RegisterMCSubtargetInfoFn { > - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) { > - TargetRegistry::RegisterMCSubtargetInfo(T, Fn); > - } > - }; > - > /// RegisterTargetMachine - Helper template for registering a target machine > /// implementation, for use in the target machine initialization > /// function. Usage: > @@ -931,9 +858,10 @@ > } > > private: > - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, > - TargetMachine &TM) { > - return new AsmParserImpl(T, P, TM); > + static TargetAsmParser *Allocator(const Target &T, StringRef TT, > + StringRef CPU, StringRef FS, > + MCAsmParser &P) { > + return new AsmParserImpl(T, TT, CPU, FS, P); > } > }; > > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 20:53:10 2011 > @@ -111,7 +111,12 @@ > OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, > OutContext, OutStreamer, > *MAI)); > - OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, TM)); > + > + OwningPtr > + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), > + TM.getTargetCPU(), > + TM.getTargetFeatureString(), > + *Parser)); > if (!TAP) > report_fatal_error("Inline asm not supported by this streamer because" > " we don't have an asm parser for this target\n"); > > Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) > +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -98,10 +98,10 @@ > EnableFastISelOption("fast-isel", cl::Hidden, > cl::desc("Enable the \"fast\" instruction selector")); > > -LLVMTargetMachine::LLVMTargetMachine(const Target &T, > - const std::string &Triple) > - : TargetMachine(T), TargetTriple(Triple) { > - AsmInfo = T.createAsmInfo(TargetTriple); > +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, > + StringRef CPU, StringRef FS) > + : TargetMachine(T, Triple, CPU, FS) { > + AsmInfo = T.createAsmInfo(Triple); > } > > // Set the default code model for the JIT for a generic target. > @@ -143,7 +143,7 @@ > TargetAsmBackend *TAB = 0; > if (ShowMCEncoding) { > MCE = getTarget().createCodeEmitter(*this, *Context); > - TAB = getTarget().createAsmBackend(TargetTriple); > + TAB = getTarget().createAsmBackend(getTargetTriple()); > } > > MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, > @@ -160,12 +160,12 @@ > // Create the code emitter for the target if it exists. If not, .o file > // emission fails. > MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); > - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); > + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); > if (MCE == 0 || TAB == 0) > return true; > > - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context, > - *TAB, Out, MCE, > + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), > + *Context, *TAB, Out, MCE, > hasMCRelaxAll(), > hasMCNoExecStack())); > AsmStreamer.get()->InitSections(); > @@ -241,12 +241,12 @@ > // Create the code emitter for the target if it exists. If not, .o file > // emission fails. > MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); > - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); > + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); > if (MCE == 0 || TAB == 0) > return true; > > OwningPtr AsmStreamer; > - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx, > + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx, > *TAB, Out, MCE, > hasMCRelaxAll(), > hasMCNoExecStack())); > > Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) > +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 20:53:10 2011 > @@ -171,7 +171,7 @@ > std::string featureString; > TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, > featureString)); > - > + > const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); > > if (!registerInfo) > @@ -183,7 +183,7 @@ > > if (!AsmInfo) > return; > - > + > Disassembler.reset(Tgt->createMCDisassembler()); > > if (!Disassembler) > @@ -371,8 +371,10 @@ > OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, > context, *streamer, > *AsmInfo)); > - OwningPtr TargetParser(Tgt->createAsmParser(*genericParser, > - *TargetMachine)); > + > + StringRef triple = tripleFromArch(Key.Arch); > + OwningPtr TargetParser(Tgt->createAsmParser(triple, "", "", > + *genericParser)); > > AsmToken OpcodeToken = genericParser->Lex(); > AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to > > Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) > +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 2011 > @@ -41,6 +41,7 @@ > class MCInst; > class MCParsedAsmOperand; > class MCStreamer; > +class MCSubtargetInfo; > template class SmallVectorImpl; > class SourceMgr; > class Target; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011 > @@ -147,35 +147,48 @@ > //===----------------------------------------------------------------------===// > // ARM Instruction Predicate Definitions. > // > -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate; > +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, > + AssemblerPredicate<"HasV4TOps">; > def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; > def HasV5T : Predicate<"Subtarget->hasV5TOps()">; > -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate; > -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate; > +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, > + AssemblerPredicate<"HasV5TEOps">; > +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, > + AssemblerPredicate<"HasV6Ops">; > def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; > -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate; > +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, > + AssemblerPredicate<"HasV6T2Ops">; > def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; > -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate; > +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, > + AssemblerPredicate<"HasV7Ops">; > def NoVFP : Predicate<"!Subtarget->hasVFP2()">; > -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate; > -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate; > -def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate; > -def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate; > -def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate; > +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, > + AssemblerPredicate<"FeatureVFP2">; > +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, > + AssemblerPredicate<"FeatureVFP3">; > +def HasNEON : Predicate<"Subtarget->hasNEON()">, > + AssemblerPredicate<"FeatureNEON">; > +def HasFP16 : Predicate<"Subtarget->hasFP16()">, > + AssemblerPredicate<"FeatureFP16">; > +def HasDivide : Predicate<"Subtarget->hasDivide()">, > + AssemblerPredicate<"FeatureHWDiv">; > def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureT2XtPk">; > def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureDSPThumb2">; > def HasDB : Predicate<"Subtarget->hasDataBarrier()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureDB">; > def HasMP : Predicate<"Subtarget->hasMPExtension()">, > - AssemblerPredicate; > + AssemblerPredicate<"FeatureMP">; > def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; > def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; > -def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate; > +def IsThumb : Predicate<"Subtarget->isThumb()">, > + AssemblerPredicate<"ModeThumb">; > def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; > -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate; > -def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate; > +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, > + AssemblerPredicate<"ModeThumb,FeatureThumb2">; > +def IsARM : Predicate<"!Subtarget->isThumb()">, > + AssemblerPredicate<"!ModeThumb">; > def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; > def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; > > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -18,9 +18,10 @@ > #include "llvm/Support/CommandLine.h" > #include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "ARMGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -80,7 +80,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > JITInfo(), > InstrItins(Subtarget.getInstrItineraryData()) { > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 20:53:10 2011 > @@ -20,6 +20,7 @@ > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCExpr.h" > #include "llvm/MC/MCInst.h" > +#include "llvm/MC/MCSubtargetInfo.h" > #include "llvm/Target/TargetRegistry.h" > #include "llvm/Target/TargetAsmParser.h" > #include "llvm/Support/SourceMgr.h" > @@ -28,6 +29,10 @@ > #include "llvm/ADT/StringExtras.h" > #include "llvm/ADT/StringSwitch.h" > #include "llvm/ADT/Twine.h" > + > +#define GET_SUBTARGETINFO_ENUM > +#include "ARMGenSubtargetInfo.inc" > + > using namespace llvm; > > namespace { > @@ -36,7 +41,7 @@ > > class ARMAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > + MCSubtargetInfo *STI; > > MCAsmParser &getParser() const { return Parser; } > MCAsmLexer &getLexer() const { return Parser.getLexer(); } > @@ -79,6 +84,15 @@ > void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, > bool &CanAcceptPredicationCode); > > + bool isThumb() const { > + // FIXME: Can tablegen auto-generate this? > + return (STI->getFeatureBits() & ARM::ModeThumb) != 0; > + } > + > + bool isThumbOne() const { > + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; > + } > + > /// @name Auto-generated Match Functions > /// { > > @@ -113,13 +127,15 @@ > const SmallVectorImpl &); > > public: > - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) > - : TargetAsmParser(T), Parser(_Parser), TM(_TM) { > - MCAsmParserExtension::Initialize(_Parser); > - // Initialize the set of available features. > - setAvailableFeatures(ComputeAvailableFeatures( > - &TM.getSubtarget())); > - } > + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, > + MCAsmParser &_Parser) > + : TargetAsmParser(T), Parser(_Parser) { > + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); > + > + MCAsmParserExtension::Initialize(_Parser); > + // Initialize the set of available features. > + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); > + } > > virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, > SmallVectorImpl &Operands); > @@ -1852,9 +1868,6 @@ > void ARMAsmParser:: > GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, > bool &CanAcceptPredicationCode) { > - bool isThumbOne = TM.getSubtarget().isThumb1Only(); > - bool isThumb = TM.getSubtarget().isThumb(); > - > if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || > Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || > Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || > @@ -1863,7 +1876,7 @@ > Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || > Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || > Mnemonic == "eor" || Mnemonic == "smlal" || > - (Mnemonic == "mov" && !isThumbOne)) { > + (Mnemonic == "mov" && !isThumbOne())) { > CanAcceptCarrySet = true; > } else { > CanAcceptCarrySet = false; > @@ -1880,7 +1893,7 @@ > CanAcceptPredicationCode = true; > } > > - if (isThumb) > + if (isThumb()) > if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || > Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") > CanAcceptPredicationCode = false; > @@ -2207,12 +2220,12 @@ > // includes Feature_IsThumb or not to match the right instructions. This is > // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. > if (Val == 16){ > - assert(TM.getSubtarget().isThumb() && > + assert(isThumb() && > "switching between arm/thumb not yet suppported via .code 16)"); > getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); > } > else{ > - assert(!TM.getSubtarget().isThumb() && > + assert(!isThumb() && > "switching between thumb/arm not yet suppported via .code 32)"); > getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); > } > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 20:53:10 2011 > @@ -23,65 +23,12 @@ > #define GET_INSTRINFO_MC_DESC > #include "ARMGenInstrInfo.inc" > > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #include "ARMGenSubtargetInfo.inc" > > using namespace llvm; > > -MCInstrInfo *createARMMCInstrInfo() { > - MCInstrInfo *X = new MCInstrInfo(); > - InitARMMCInstrInfo(X); > - return X; > -} > - > -MCRegisterInfo *createARMMCRegisterInfo() { > - MCRegisterInfo *X = new MCRegisterInfo(); > - InitARMMCRegisterInfo(X); > - return X; > -} > - > -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > - StringRef FS) { > - std::string ArchFS = ARM_MC::ParseARMTriple(TT); > - if (!FS.empty()) { > - if (!ArchFS.empty()) > - ArchFS = ArchFS + "," + FS.str(); > - else > - ArchFS = FS; > - } > - > - MCSubtargetInfo *X = new MCSubtargetInfo(); > - InitARMMCSubtargetInfo(X, CPU, ArchFS); > - return X; > -} > - > -// Force static initialization. > -extern "C" void LLVMInitializeARMMCInstrInfo() { > - RegisterMCInstrInfo X(TheARMTarget); > - RegisterMCInstrInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); > - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); > -} > - > -extern "C" void LLVMInitializeARMMCRegInfo() { > - RegisterMCRegInfo X(TheARMTarget); > - RegisterMCRegInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); > - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); > -} > - > -extern "C" void LLVMInitializeARMMCSubtargetInfo() { > - RegisterMCSubtargetInfo X(TheARMTarget); > - RegisterMCSubtargetInfo Y(TheThumbTarget); > - > - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, > - createARMMCSubtargetInfo); > - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, > - createARMMCSubtargetInfo); > -} > - > std::string ARM_MC::ParseARMTriple(StringRef TT) { > // Set the boolean corresponding to the current target triple, or the default > // if one cannot be determined, to true. > @@ -135,3 +82,47 @@ > > return ARMArchFeature; > } > + > +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS) { > + std::string ArchFS = ARM_MC::ParseARMTriple(TT); > + if (!FS.empty()) { > + if (!ArchFS.empty()) > + ArchFS = ArchFS + "," + FS.str(); > + else > + ArchFS = FS; > + } > + > + MCSubtargetInfo *X = new MCSubtargetInfo(); > + InitARMMCSubtargetInfo(X, CPU, ArchFS); > + return X; > +} > + > +MCInstrInfo *createARMMCInstrInfo() { > + MCInstrInfo *X = new MCInstrInfo(); > + InitARMMCInstrInfo(X); > + return X; > +} > + > +MCRegisterInfo *createARMMCRegisterInfo() { > + MCRegisterInfo *X = new MCRegisterInfo(); > + InitARMMCRegisterInfo(X); > + return X; > +} > + > +// Force static initialization. > +extern "C" void LLVMInitializeARMMCInstrInfo() { > + RegisterMCInstrInfo X(TheARMTarget); > + RegisterMCInstrInfo Y(TheThumbTarget); > + > + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); > + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); > +} > + > +extern "C" void LLVMInitializeARMMCRegInfo() { > + RegisterMCRegInfo X(TheARMTarget); > + RegisterMCRegInfo Y(TheThumbTarget); > + > + TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); > + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); > +} > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 20:53:10 2011 > @@ -17,6 +17,7 @@ > #include > > namespace llvm { > +class MCSubtargetInfo; > class Target; > class StringRef; > > @@ -24,6 +25,12 @@ > > namespace ARM_MC { > std::string ParseARMTriple(StringRef TT); > + > + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. > + /// This is exposed so Asm parser, etc. do not need to go through > + /// TargetRegistry. > + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS); > } > > } // End llvm namespace > > Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "AlphaSubtarget.h" > #include "Alpha.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "AlphaGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -27,7 +27,7 @@ > AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout("e-f128:128:128-n64"), > FrameLowering(Subtarget), > Subtarget(TT, CPU, FS), > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -13,9 +13,10 @@ > > #include "BlackfinSubtarget.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "BlackfinGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -28,7 +28,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout("e-p:32:32-i64:32-f64:32-n32"), > Subtarget(TT, CPU, FS), > TLInfo(*this), > > Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) > +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 2011 > @@ -22,7 +22,7 @@ > struct CTargetMachine : public TargetMachine { > CTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS) > - : TargetMachine(T) {} > + : TargetMachine(T, TT, CPU, FS) {} > > virtual bool addPassesToEmitFile(PassManagerBase &PM, > formatted_raw_ostream &Out, > > Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -13,12 +13,13 @@ > > #include "SPUSubtarget.h" > #include "SPU.h" > -#include "llvm/ADT/SmallVector.h" > #include "SPURegisterInfo.h" > +#include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SPUGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -36,7 +36,7 @@ > > SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU,const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout(Subtarget.getTargetDataString()), > InstrInfo(*this), > > Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) > +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 20:53:10 2011 > @@ -24,7 +24,7 @@ > struct CPPTargetMachine : public TargetMachine { > CPPTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS) > - : TargetMachine(T) {} > + : TargetMachine(T, TT, CPU, FS) {} > > virtual bool addPassesToEmitFile(PassManagerBase &PM, > formatted_raw_ostream &Out, > > Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 20:53:10 2011 > @@ -32,7 +32,6 @@ > > class MBlazeAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > > MCAsmParser &getParser() const { return Parser; } > MCAsmLexer &getLexer() const { return Parser.getLexer(); } > @@ -64,8 +63,9 @@ > > > public: > - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) > - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} > + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, > + MCAsmParser &_Parser) > + : TargetAsmParser(T), Parser(_Parser) {} > > virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, > SmallVectorImpl &Operands); > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -16,9 +16,10 @@ > #include "MBlazeRegisterInfo.h" > #include "llvm/Support/CommandLine.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MBlazeGenSubtargetInfo.inc" > > using namespace llvm; > @@ -61,4 +62,3 @@ > CriticalPathRCs.push_back(&MBlaze::GPRRegClass); > return HasItin && OptLevel >= CodeGenOpt::Default; > } > - > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -81,7 +81,7 @@ > MBlazeTargetMachine:: > MBlazeTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS): > - LLVMTargetMachine(T, TT), > + LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), > InstrInfo(*this), > > Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "MSP430Subtarget.h" > #include "MSP430.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MSP430GenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -30,7 +30,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > // FIXME: Check TargetData string. > DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), > > Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "MipsSubtarget.h" > #include "Mips.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "MipsGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -37,7 +37,7 @@ > MipsTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, const std::string &FS, > bool isLittle=false): > - LLVMTargetMachine(T, TT), > + LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, isLittle), > DataLayout(isLittle ? > std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : > > Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "PTXSubtarget.h" > #include "llvm/Support/ErrorHandling.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "PTXGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -55,7 +55,7 @@ > const std::string &CPU, > const std::string &FS, > bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > DataLayout(is64Bit ? DataLayout64 : DataLayout32), > Subtarget(TT, CPU, FS, is64Bit), > FrameLowering(Subtarget), > > Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -17,9 +17,10 @@ > #include "llvm/Target/TargetMachine.h" > #include > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "PPCGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -69,7 +69,7 @@ > PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS, bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, is64Bit), > DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), > FrameLowering(Subtarget), JITInfo(*this, is64Bit), > > Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -13,9 +13,10 @@ > > #include "SparcSubtarget.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SparcGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -32,7 +32,7 @@ > SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS, bool is64bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, is64bit), > DataLayout(Subtarget.getDataLayout()), > TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -16,9 +16,10 @@ > #include "llvm/GlobalValue.h" > #include "llvm/Target/TargetMachine.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "SystemZGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -26,7 +26,7 @@ > const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" > "-f64:64:64-f128:128:128-a0:16:16-n32:64"), > > Modified: llvm/trunk/lib/Target/TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -216,8 +216,9 @@ > // TargetMachine Class > // > > -TargetMachine::TargetMachine(const Target &T) > - : TheTarget(T), AsmInfo(0), > +TargetMachine::TargetMachine(const Target &T, > + StringRef TT, StringRef CPU, StringRef FS) > + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0), > MCRelaxAll(false), > MCNoExecStack(false), > MCSaveTempLabels(false), > > Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 20:53:10 2011 > @@ -15,6 +15,7 @@ > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCExpr.h" > #include "llvm/MC/MCInst.h" > +#include "llvm/MC/MCSubtargetInfo.h" > #include "llvm/MC/MCParser/MCAsmLexer.h" > #include "llvm/MC/MCParser/MCAsmParser.h" > #include "llvm/MC/MCParser/MCParsedAsmOperand.h" > @@ -25,6 +26,10 @@ > #include "llvm/ADT/Twine.h" > #include "llvm/Support/SourceMgr.h" > #include "llvm/Support/raw_ostream.h" > + > +#define GET_SUBTARGETINFO_ENUM > +#include "X86GenSubtargetInfo.inc" > + > using namespace llvm; > > namespace { > @@ -32,10 +37,7 @@ > > class X86ATTAsmParser : public TargetAsmParser { > MCAsmParser &Parser; > - TargetMachine &TM; > - > -protected: > - unsigned Is64Bit : 1; > + MCSubtargetInfo *STI; > > private: > MCAsmParser &getParser() const { return Parser; } > @@ -61,6 +63,11 @@ > /// or %es:(%edi) in 32bit mode. > bool isDstOp(X86Operand &Op); > > + bool is64Bit() { > + // FIXME: Can tablegen auto-generate this? > + return (STI->getFeatureBits() & X86::Mode64Bit) != 0; > + } > + > /// @name Auto-generated Matcher Functions > /// { > > @@ -70,12 +77,13 @@ > /// } > > public: > - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM) > - : TargetAsmParser(T), Parser(parser), TM(TM) { > + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, > + MCAsmParser &parser) > + : TargetAsmParser(T), Parser(parser) { > + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); > > // Initialize the set of available features. > - setAvailableFeatures(ComputeAvailableFeatures( > - &TM.getSubtarget())); > + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); > } > virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); > > @@ -84,23 +92,6 @@ > > virtual bool ParseDirective(AsmToken DirectiveID); > }; > - > -class X86_32ATTAsmParser : public X86ATTAsmParser { > -public: > - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) > - : X86ATTAsmParser(T, Parser, TM) { > - Is64Bit = false; > - } > -}; > - > -class X86_64ATTAsmParser : public X86ATTAsmParser { > -public: > - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) > - : X86ATTAsmParser(T, Parser, TM) { > - Is64Bit = true; > - } > -}; > - > } // end anonymous namespace > > /// @name Auto-generated Match Functions > @@ -365,7 +356,7 @@ > } // end anonymous namespace. > > bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { > - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI; > + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; > > return (Op.isMem() && > (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && > @@ -375,7 +366,7 @@ > } > > bool X86ATTAsmParser::isDstOp(X86Operand &Op) { > - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI; > + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; > > return Op.isMem() && Op.Mem.SegReg == X86::ES && > isa(Op.Mem.Disp) && > @@ -406,7 +397,7 @@ > // FIXME: This should be done using Requires and > // Requires so "eiz" usage in 64-bit instructions > // can be also checked. > - if (RegNo == X86::RIZ && !Is64Bit) > + if (RegNo == X86::RIZ && !is64Bit()) > return Error(Tok.getLoc(), "riz register in 64-bit mode only"); > > // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. > @@ -826,7 +817,7 @@ > // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" > if (Name.startswith("movs") && Operands.size() == 3 && > (Name == "movsb" || Name == "movsw" || Name == "movsl" || > - (Is64Bit && Name == "movsq"))) { > + (is64Bit() && Name == "movsq"))) { > X86Operand &Op = *(X86Operand*)Operands.begin()[1]; > X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; > if (isSrcOp(Op) && isDstOp(Op2)) { > @@ -839,7 +830,7 @@ > // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" > if (Name.startswith("lods") && Operands.size() == 3 && > (Name == "lods" || Name == "lodsb" || Name == "lodsw" || > - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) { > + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { > X86Operand *Op1 = static_cast(Operands[1]); > X86Operand *Op2 = static_cast(Operands[2]); > if (isSrcOp(*Op1) && Op2->isReg()) { > @@ -869,7 +860,7 @@ > // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" > if (Name.startswith("stos") && Operands.size() == 3 && > (Name == "stos" || Name == "stosb" || Name == "stosw" || > - Name == "stosl" || (Is64Bit && Name == "stosq"))) { > + Name == "stosl" || (is64Bit() && Name == "stosq"))) { > X86Operand *Op1 = static_cast(Operands[1]); > X86Operand *Op2 = static_cast(Operands[2]); > if (isDstOp(*Op2) && Op1->isReg()) { > @@ -1144,8 +1135,8 @@ > > // Force static initialization. > extern "C" void LLVMInitializeX86AsmParser() { > - RegisterAsmParser X(TheX86_32Target); > - RegisterAsmParser Y(TheX86_64Target); > + RegisterAsmParser X(TheX86_32Target); > + RegisterAsmParser Y(TheX86_64Target); > LLVMInitializeX86AsmLexer(); > } > > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 20:53:10 2011 > @@ -25,6 +25,7 @@ > #define GET_INSTRINFO_MC_DESC > #include "X86GenInstrInfo.inc" > > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #include "X86GenSubtargetInfo.inc" > > @@ -35,7 +36,7 @@ > Triple TheTriple(TT); > if (TheTriple.getArch() == Triple::x86_64) > return "+64bit-mode"; > - return ""; > + return "-64bit-mode"; > } > > /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the > @@ -128,20 +129,8 @@ > return false; > } > > -MCInstrInfo *createX86MCInstrInfo() { > - MCInstrInfo *X = new MCInstrInfo(); > - InitX86MCInstrInfo(X); > - return X; > -} > - > -MCRegisterInfo *createX86MCRegisterInfo() { > - MCRegisterInfo *X = new MCRegisterInfo(); > - InitX86MCRegisterInfo(X); > - return X; > -} > - > -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > - StringRef FS) { > +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS) { > std::string ArchFS = X86_MC::ParseX86Triple(TT); > if (!FS.empty()) { > if (!ArchFS.empty()) > @@ -159,7 +148,19 @@ > ArchFS = "+64bit-mode"; > > MCSubtargetInfo *X = new MCSubtargetInfo(); > - InitX86MCSubtargetInfo(X, CPU, ArchFS); > + InitX86MCSubtargetInfo(X, CPUName, ArchFS); > + return X; > +} > + > +MCInstrInfo *createX86MCInstrInfo() { > + MCInstrInfo *X = new MCInstrInfo(); > + InitX86MCInstrInfo(X); > + return X; > +} > + > +MCRegisterInfo *createX86MCRegisterInfo() { > + MCRegisterInfo *X = new MCRegisterInfo(); > + InitX86MCRegisterInfo(X); > return X; > } > > @@ -179,13 +180,3 @@ > TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); > TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); > } > - > -extern "C" void LLVMInitializeX86MCSubtargetInfo() { > - RegisterMCSubtargetInfo X(TheX86_32Target); > - RegisterMCSubtargetInfo Y(TheX86_64Target); > - > - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, > - createX86MCSubtargetInfo); > - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, > - createX86MCSubtargetInfo); > -} > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 20:53:10 2011 > @@ -17,6 +17,7 @@ > #include > > namespace llvm { > +class MCSubtargetInfo; > class Target; > class StringRef; > > @@ -31,9 +32,17 @@ > unsigned *rEBX, unsigned *rECX, unsigned *rEDX); > > void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); > + > + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. > + /// This is exposed so Asm parser, etc. do not need to go through > + /// TargetRegistry. > + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > + StringRef FS); > } > + > } // End llvm namespace > > + > // Defines symbolic names for X86 registers. This defines a mapping from > // register name to register number. > // > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011 > @@ -438,8 +438,10 @@ > def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; > def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; > def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; > -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate; > -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate; > +def In32BitMode : Predicate<"!Subtarget->is64Bit()">, > + AssemblerPredicate<"!Mode64Bit">; > +def In64BitMode : Predicate<"Subtarget->is64Bit()">, > + AssemblerPredicate<"Mode64Bit">; > def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; > def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; > def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -21,9 +21,10 @@ > #include "llvm/Target/TargetMachine.h" > #include "llvm/ADT/SmallVector.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "X86GenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -119,7 +119,7 @@ > X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS, bool is64Bit) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS, StackAlignmentOverride), > FrameLowering(*this, Subtarget), > ELFWriterInfo(is64Bit, true) { > > Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 2011 > @@ -14,9 +14,10 @@ > #include "XCoreSubtarget.h" > #include "XCore.h" > > -#define GET_SUBTARGETINFO_CTOR > +#define GET_SUBTARGETINFO_ENUM > #define GET_SUBTARGETINFO_MC_DESC > #define GET_SUBTARGETINFO_TARGET_DESC > +#define GET_SUBTARGETINFO_CTOR > #include "XCoreGenSubtargetInfo.inc" > > using namespace llvm; > > Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 2011 > @@ -23,7 +23,7 @@ > XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, > const std::string &CPU, > const std::string &FS) > - : LLVMTargetMachine(T, TT), > + : LLVMTargetMachine(T, TT, CPU, FS), > Subtarget(TT, CPU, FS), > DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" > "i16:16:32-i32:32:32-i64:32:32-n32"), > > Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) > +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011 > @@ -371,7 +371,8 @@ > > OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, > *Str.get(), *MAI)); > - OwningPtr TAP(TheTarget->createAsmParser(*Parser, *TM)); > + OwningPtr > + TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser)); > if (!TAP) { > errs() << ProgName > << ": error: this target does not support assembly parsing.\n"; > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011 > @@ -619,7 +619,10 @@ > Context, *Streamer, > *_target->getMCAsmInfo())); > OwningPtr > - TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get())); > + TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(), > + _target->getTargetCPU(), > + _target->getTargetFeatureString(), > + *Parser.get())); > Parser->setTargetParser(*TAP); > int Res = Parser->Run(false); > if (Res) > > Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 2011 > @@ -1817,15 +1817,43 @@ > Info.AsmParser->getValueAsString("AsmParserClassName"); > > OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" > - << "ComputeAvailableFeatures(const " << Info.Target.getName() > - << "Subtarget *Subtarget) const {\n"; > + << "ComputeAvailableFeatures(uint64_t FB) const {\n"; > OS << " unsigned Features = 0;\n"; > for (std::map::const_iterator > it = Info.SubtargetFeatures.begin(), > ie = Info.SubtargetFeatures.end(); it != ie; ++it) { > SubtargetFeatureInfo &SFI = *it->second; > - OS << " if (" << SFI.TheDef->getValueAsString("CondString") > - << ")\n"; > + > + OS << " if ("; > + StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString"); > + std::pair Comma = Conds.split(','); > + bool First = true; > + do { > + if (!First) > + OS << " && "; > + > + bool Neg = false; > + StringRef Cond = Comma.first; > + if (Cond[0] == '!') { > + Neg = true; > + Cond = Cond.substr(1); > + } > + > + OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; > + if (Neg) > + OS << " == 0"; > + else > + OS << " != 0"; > + OS << ")"; > + > + if (Comma.second.empty()) > + break; > + > + First = false; > + Comma = Comma.second.split(','); > + } while (true); > + > + OS << ")\n"; > OS << " Features |= " << SFI.getEnumName() << ";\n"; > } > OS << " return Features;\n"; > @@ -2140,8 +2168,7 @@ > OS << "#undef GET_ASSEMBLER_HEADER\n"; > OS << " // This should be included into the middle of the declaration of\n"; > OS << " // your subclasses implementation of TargetAsmParser.\n"; > - OS << " unsigned ComputeAvailableFeatures(const " << > - Target.getName() << "Subtarget *Subtarget) const;\n"; > + OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; > OS << " enum MatchResultTy {\n"; > OS << " Match_ConversionFail,\n"; > OS << " Match_InvalidOperand,\n"; > > Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 2011 > @@ -645,12 +645,18 @@ > > EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); > > + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; > + OS << "#undef GET_SUBTARGETINFO_ENUM\n"; > + > + OS << "namespace llvm {\n"; > + Enumeration(OS, "SubtargetFeature", true); > + OS << "} // End llvm namespace \n"; > + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; > + > OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; > OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; > > OS << "namespace llvm {\n"; > - Enumeration(OS, "SubtargetFeature", true); > - OS<<"\n"; > unsigned NumFeatures = FeatureKeyValues(OS); > OS<<"\n"; > unsigned NumProcs = CPUKeyValues(OS); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110707/521f58a9/attachment-0001.html From fvbommel at gmail.com Fri Jul 8 01:29:46 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Fri, 8 Jul 2011 08:29:46 +0200 Subject: [llvm-commits] [llvm] r134677 - in /llvm/trunk: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll In-Reply-To: <20110708015054.CBE162A6C12C@llvm.org> References: <20110708015054.CBE162A6C12C@llvm.org> Message-ID: On 8 July 2011 03:50, Lang Hames wrote: > + ? ?switch (I->getIntrinsicID()) { > + ? ? ?case Intrinsic::uadd_with_overflow: > + ? ? ? ?e.opcode = Instruction::Add; > + ? ? ? ?break; > + ? ? ?case Intrinsic::usub_with_overflow: > + ? ? ? ?e.opcode = Instruction::Sub; > + ? ? ? ?break; > + ? ? ?case Intrinsic::umul_with_overflow: > + ? ? ? ?e.opcode = Instruction::Mul; > + ? ? ? ?break; > + ? ? ?default: > + ? ? ? ?break; > + ? ?} Still no signed variants? They should be as easy as duplicating each case line and changing a single character on each of the three new lines ('s/::u/::s/'). (Plus some extra texts, of course) From aggarwa4 at illinois.edu Fri Jul 8 02:55:01 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 08 Jul 2011 07:55:01 -0000 Subject: [llvm-commits] [poolalloc] r134693 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110708075501.2C07E2A6C12D@llvm.org> Author: aggarwa4 Date: Fri Jul 8 02:55:01 2011 New Revision: 134693 URL: http://llvm.org/viewvc/llvm-project?rev=134693&view=rev Log: Check that ptr is not null when initializing. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=134693&r1=134692&r2=134693&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Fri Jul 8 02:55:01 2011 @@ -27,7 +27,7 @@ * For now, run a version of the tool without the base fixed, and * choose address. */ -#define BASE ((TypeTagTy *)(0x2aaaac01e000)) +#define BASE ((TypeTagTy *)(0x2aaaad01e000)) /* * Do some macro magic to get mmap macros defined properly on all platforms. */ @@ -269,6 +269,8 @@ * 0xFF type indicates that any type can be read, */ void trackInitInst(void *ptr, uint64_t size, uint32_t tag) { + if(!ptr) + return; uintptr_t p = maskAddress(ptr); memset(&shadow_begin[p], 0xFF, size); #if DEBUG From lhames at gmail.com Fri Jul 8 03:04:09 2011 From: lhames at gmail.com (Lang Hames) Date: Fri, 8 Jul 2011 18:04:09 +1000 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics In-Reply-To: References: <479C8C82-F5D6-4EAE-BF6E-D48FBAFBCAB3@apple.com> Message-ID: Hi Chris, Frits, > I think that Owen is the best one to handle this. In addition to handling > the signed versions of these as well, does this correctly handle the case > when the subtract comes first, and the cases when the overflow bit is > actually used? > > I don't see any issues with the use/non-use of the overflow bit. For the > signed overflow versions, is it only the semantics of the overflow bit that > are affected? Is the value part of the result the same between sadd/uadd? Yep - use/non-use of the overflow bit should be a non-issue with this patch. Regarding the signed intrinsics: I've stayed conservative with this patch. I haven't checked the signed intrinsics yet to address Owen's question (do the semantics of the value parts change?). I'll try to find time for that tomorrow. > > In principle, we'd want to optimize: > > > > a = add i32 y, z > > ... > > b,c = addo(y,z) > > > > into: > > > > b,c = addo(y,z) > > a = b > > ? > > I don't think this patch will currently do this. No: This case won't be caught by my patch. Committed on Owen's advice in r134677. Cheers, Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110708/cac56f29/attachment.html From fvbommel at gmail.com Fri Jul 8 04:05:58 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Fri, 8 Jul 2011 11:05:58 +0200 Subject: [llvm-commits] [PATCH] GVN patch for overflow intrinsics In-Reply-To: References: <479C8C82-F5D6-4EAE-BF6E-D48FBAFBCAB3@apple.com> Message-ID: On 8 July 2011 10:04, Lang Hames wrote: > Hi Chris, Frits, >> >> > I think that Owen is the best one to handle this. ?In addition to >> > handling the signed versions of these as well, does this correctly handle >> > the case when the subtract comes first, and the cases when the overflow bit >> > is actually used? >> >> I don't see any issues with the use/non-use of the overflow bit. ?For the >> signed overflow versions, is it only the semantics of the overflow bit that >> are affected? ?Is the value part of the result the same between sadd/uadd? > > Yep - use/non-use of the overflow bit should be a non-issue with this patch. > Regarding the signed intrinsics: I've stayed conservative with this patch. I > haven't checked the signed intrinsics yet to address Owen's question (do the > semantics of the value parts change?). I'll try to find time for that > tomorrow. The value part of a signed add/sub/mul with overflow should be the same as that of an unsigned one, and the same as a regular add/sub/mul instruction in LLVM. This is the reason there are no signed or unsigned versions of add/sub/mul instructions(nsw/nuw flags notwithstanding): they would perform the same operation, so there's no need to distinguish them. Interesting detail: if calls to both uadd.with.overflow and sadd.with.overflow, with the same parameters, are in the same basic block then the code generator (at least, the one for x86-64) will only create a single 'add', and just read both flags afterward. Nice :). From benny.kra at googlemail.com Fri Jul 8 05:31:31 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 08 Jul 2011 10:31:31 -0000 Subject: [llvm-commits] [llvm] r134695 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/sdiv-exact.ll Message-ID: <20110708103131.29A452A6C12C@llvm.org> Author: d0k Date: Fri Jul 8 05:31:30 2011 New Revision: 134695 URL: http://llvm.org/viewvc/llvm-project?rev=134695&view=rev Log: Emit a more efficient magic number multiplication for exact sdivs. We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax Added: llvm/trunk/test/CodeGen/X86/sdiv-exact.ll Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=134695&r1=134694&r2=134695&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Jul 8 05:31:30 2011 @@ -1540,6 +1540,8 @@ //===--------------------------------------------------------------------===// // Div utility functions // + SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, + SelectionDAG &DAG) const; SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector* Created) const; SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134695&r1=134694&r2=134695&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 8 05:31:30 2011 @@ -2501,6 +2501,22 @@ Op1.getValueType(), Op1, Op2)); } +void SelectionDAGBuilder::visitSDiv(const User &I) { + const BinaryOperator *BO = cast(&I); + SDValue Op1 = getValue(I.getOperand(0)); + SDValue Op2 = getValue(I.getOperand(1)); + + // Turn exact SDivs into multiplications. + // FIXME: This should be in DAGCombiner, but it doesn't have access to the + // exact bit. + if (BO->isExact() && !isa(Op1) && + isa(Op2) && !cast(Op2)->isNullValue()) + setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); + else + setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), + Op1, Op2)); +} + void SelectionDAGBuilder::visitICmp(const User &I) { ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; if (const ICmpInst *IC = dyn_cast(&I)) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=134695&r1=134694&r2=134695&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Fri Jul 8 05:31:30 2011 @@ -467,7 +467,7 @@ void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } - void visitSDiv(const User &I) { visitBinary(I, ISD::SDIV); } + void visitSDiv(const User &I); void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } void visitAnd (const User &I) { visitBinary(I, ISD::AND); } void visitOr (const User &I) { visitBinary(I, ISD::OR); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134695&r1=134694&r2=134695&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jul 8 05:31:30 2011 @@ -3211,6 +3211,32 @@ return true; } +/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication +/// with the multiplicative inverse of the constant. +SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, + SelectionDAG &DAG) const { + ConstantSDNode *C = cast(Op2); + APInt d = C->getAPIntValue(); + assert(d != 0 && "Division by zero!"); + + // Shift the value upfront if it is even, so the LSB is one. + unsigned ShAmt = d.countTrailingZeros(); + if (ShAmt) { + // TODO: For UDIV use SRL instead of SRA. + SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); + Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); + d = d.ashr(ShAmt); + } + + // Calculate the multiplicative inverse, using Newton's method. + APInt t, xn = d; + while ((t = d*xn) != 1) + xn *= APInt(d.getBitWidth(), 2) - t; + + Op2 = DAG.getConstant(xn, Op1.getValueType()); + return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); +} + /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, /// return a DAG expression to select that will generate the same value by /// multiplying by a magic number. See: Added: llvm/trunk/test/CodeGen/X86/sdiv-exact.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sdiv-exact.ll?rev=134695&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sdiv-exact.ll (added) +++ llvm/trunk/test/CodeGen/X86/sdiv-exact.ll Fri Jul 8 05:31:30 2011 @@ -0,0 +1,18 @@ +; RUN: llc -march=x86 < %s | FileCheck %s + +define i32 @test1(i32 %x) { + %div = sdiv exact i32 %x, 25 + ret i32 %div +; CHECK: test1: +; CHECK: imull $-1030792151, 4(%esp) +; CHECK-NEXT: ret +} + +define i32 @test2(i32 %x) { + %div = sdiv exact i32 %x, 24 + ret i32 %div +; CHECK: test2: +; CHECK: sarl $3 +; CHECK-NEXT: imull $-1431655765 +; CHECK-NEXT: ret +} From geek4civic at gmail.com Fri Jul 8 05:45:15 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 08 Jul 2011 10:45:15 -0000 Subject: [llvm-commits] [llvm] r134696 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110708104515.B86E12A6C12C@llvm.org> Author: chapuni Date: Fri Jul 8 05:45:15 2011 New Revision: 134696 URL: http://llvm.org/viewvc/llvm-project?rev=134696&view=rev Log: cmake/modules/LLVMLibDeps.cmake: Update to appease cmake builds. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=134696&r1=134695&r2=134696&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jul 8 05:45:15 2011 @@ -1,4 +1,4 @@ -set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC) @@ -40,7 +40,8 @@ set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -58,10 +59,10 @@ set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) -set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Desc LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) -set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) From benny.kra at googlemail.com Fri Jul 8 07:08:24 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 08 Jul 2011 12:08:24 -0000 Subject: [llvm-commits] [llvm] r134699 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20110708120824.A3AA62A6C12C@llvm.org> Author: d0k Date: Fri Jul 8 07:08:24 2011 New Revision: 134699 URL: http://llvm.org/viewvc/llvm-project?rev=134699&view=rev Log: Apparently we can't expect a BinaryOperator here. Should fix llvm-gcc selfhost. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134699&r1=134698&r2=134699&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 8 07:08:24 2011 @@ -2502,14 +2502,14 @@ } void SelectionDAGBuilder::visitSDiv(const User &I) { - const BinaryOperator *BO = cast(&I); SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); // Turn exact SDivs into multiplications. // FIXME: This should be in DAGCombiner, but it doesn't have access to the // exact bit. - if (BO->isExact() && !isa(Op1) && + if (isa(&I) && cast(&I)->isExact() && + !isa(Op1) && isa(Op2) && !cast(Op2)->isNullValue()) setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); else From eli.friedman at gmail.com Fri Jul 8 10:56:52 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 08:56:52 -0700 Subject: [llvm-commits] [llvm] r134699 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp In-Reply-To: <20110708120824.A3AA62A6C12C@llvm.org> References: <20110708120824.A3AA62A6C12C@llvm.org> Message-ID: On Fri, Jul 8, 2011 at 5:08 AM, Benjamin Kramer wrote: > Author: d0k > Date: Fri Jul ?8 07:08:24 2011 > New Revision: 134699 > > URL: http://llvm.org/viewvc/llvm-project?rev=134699&view=rev > Log: > Apparently we can't expect a BinaryOperator here. Yes... the naming is a bit deceptive. You can expect an SDivOperator, but not a BinaryOperator. -Eli From aggarwa4 at illinois.edu Fri Jul 8 11:29:49 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 08 Jul 2011 16:29:49 -0000 Subject: [llvm-commits] [poolalloc] r134701 - in /poolalloc/trunk/lib/AssistDS: TypeChecks.cpp TypeChecksOpt.cpp Message-ID: <20110708162949.91BEB2A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jul 8 11:29:49 2011 New Revision: 134701 URL: http://llvm.org/viewvc/llvm-project?rev=134701&view=rev Log: We do not need to initialize the memory allocated by the alloca, in the non optimized version. It is only when we remove checks that initialization is needed. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134701&r1=134700&r2=134701&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jul 8 11:29:49 2011 @@ -1386,16 +1386,6 @@ // Insert code to set objects to 0 bool TypeChecks::visitAllocaInst(Module &M, AllocaInst &AI) { - // Set the object to be zero - // - // Add the memset function to the program. - Constant *memsetF = M.getOrInsertFunction ("llvm.memset.i64", VoidTy, - VoidPtrTy, - Int8Ty, - Int64Ty, - Int32Ty, - NULL); - const PointerType * PT = AI.getType(); const Type * ET = PT->getElementType(); Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); @@ -1406,13 +1396,6 @@ ArraySize->insertAfter(BCI); BinaryOperator *Size = BinaryOperator::Create(Instruction::Mul, AllocSize, ArraySize); Size->insertAfter(ArraySize); - std::vector Args2; - Args2.push_back(BCI); - Args2.push_back(ConstantInt::get(Int8Ty, 0)); - Args2.push_back(Size); - Args2.push_back(ConstantInt::get(Int32Ty, AI.getAlignment())); - CallInst *CI_Init = CallInst::Create(memsetF, Args2.begin(), Args2.end()); - CI_Init->insertAfter(Size); // Setting metadata to be 0(BOTTOM/Uninitialized) @@ -1421,7 +1404,7 @@ Args.push_back(Size); Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackUnInitInst, Args.begin(), Args.end()); - CI->insertAfter(CI_Init); + CI->insertAfter(Size); return true; } Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=134701&r1=134700&r2=134701&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Fri Jul 8 11:29:49 2011 @@ -66,6 +66,12 @@ TypeTagTy = Int8Ty; TypeTagPtrTy = PointerType::getUnqual(TypeTagTy); + Constant *memsetF = M.getOrInsertFunction ("llvm.memset.i64", VoidTy, + VoidPtrTy, + Int8Ty, + Int64Ty, + Int32Ty, + NULL); trackGlobal = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy,/*ptr*/ @@ -80,11 +86,11 @@ Int32Ty,/*tag*/ NULL); trackUnInitInst = M.getOrInsertFunction("trackUnInitInst", - VoidTy, - VoidPtrTy,/*ptr*/ - Int64Ty,/*size*/ - Int32Ty,/*tag*/ - NULL); + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); trackStoreInst = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy,/*ptr*/ @@ -108,13 +114,13 @@ Int32Ty,/*tag*/ NULL); setTypeInfo = M.getOrInsertFunction("setTypeInfo", - VoidTy, - VoidPtrTy,/*dest ptr*/ - TypeTagPtrTy,/*metadata*/ - Int64Ty,/*size*/ - TypeTagTy, - Int32Ty,/*tag*/ - NULL); + VoidTy, + VoidPtrTy,/*dest ptr*/ + TypeTagPtrTy,/*metadata*/ + Int64Ty,/*size*/ + TypeTagTy, + Int32Ty,/*tag*/ + NULL); trackStringInput = M.getOrInsertFunction("trackStringInput", VoidTy, VoidPtrTy, @@ -145,7 +151,7 @@ for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) { CallInst *CI = dyn_cast(User); assert(CI); - + if(TS->isTypeSafe(CI->getOperand(4)->stripPointerCasts(), CI->getParent()->getParent())) { toDelete.push_back(CI); } @@ -154,7 +160,7 @@ for(Value::use_iterator User = trackStoreInst->use_begin(); User != trackStoreInst->use_end(); ++User) { CallInst *CI = dyn_cast(User); assert(CI); - + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { toDelete.push_back(CI); } @@ -165,11 +171,21 @@ for(Value::use_iterator User = trackUnInitInst->use_begin(); User != trackUnInitInst->use_end(); ) { CallInst *CI = dyn_cast(User++); assert(CI); - + // check if operand is an alloca inst. if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { CI->setCalledFunction(trackInitInst); toDelete.push_back(CI); + + if(AllocaInst *AI = dyn_cast(CI->getOperand(1)->stripPointerCasts())) { + // Initialize the allocation to NULL + std::vector Args2; + Args2.push_back(CI->getOperand(1)); + Args2.push_back(ConstantInt::get(Int8Ty, 0)); + Args2.push_back(CI->getOperand(2)); + Args2.push_back(ConstantInt::get(Int32Ty, AI->getAlignment())); + CallInst::Create(memsetF, Args2.begin(), Args2.end(), "", CI); + } } } @@ -227,12 +243,6 @@ CallInst *CI = dyn_cast(User); assert(CI); if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { - Constant *memsetF = M.getOrInsertFunction ("llvm.memset.i64", VoidTy, - VoidPtrTy, - Int8Ty, - Int64Ty, - Int32Ty, - NULL); AllocaInst *AI = dyn_cast(CI->getOperand(3)->stripPointerCasts()); assert(AI); std::vectorArgs; From dag at cray.com Fri Jul 8 11:41:13 2011 From: dag at cray.com (David Greene) Date: Fri, 08 Jul 2011 11:41:13 -0500 Subject: [llvm-commits] [PATCH] Make TableGen Inits FoldingSetNodes Message-ID: A non-text attachment was scrubbed... Name: init.diff Type: text/x-patch Size: 249843 bytes Desc: Patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110708/de68b570/attachment-0001.bin From dpatel at apple.com Fri Jul 8 11:49:44 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 08 Jul 2011 16:49:44 -0000 Subject: [llvm-commits] [llvm] r134702 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h Message-ID: <20110708164944.242972A6C12C@llvm.org> Author: dpatel Date: Fri Jul 8 11:49:43 2011 New Revision: 134702 URL: http://llvm.org/viewvc/llvm-project?rev=134702&view=rev Log: Make provision to have floating point constants in .debug_loc expressions. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134702&r1=134701&r2=134702&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Jul 8 11:49:43 2011 @@ -1449,11 +1449,20 @@ DotDebugLocEntries. push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); } - // FIXME: Handle isFPImm also. else if (Begin->getOperand(0).isImm()) { DotDebugLocEntries. push_back(DotDebugLocEntry(FLabel, SLabel, Begin->getOperand(0).getImm())); + } else if (Begin->getOperand(0).isFPImm()) { + DotDebugLocEntries. + push_back(DotDebugLocEntry(FLabel, SLabel, + Begin->getOperand(0).getFPImm())); + } else if (Begin->getOperand(0).isCImm()) { + DotDebugLocEntries. + push_back(DotDebugLocEntry(FLabel, SLabel, + Begin->getOperand(0).getCImm())); + } else { + assert (0 && "Unexpected 3 operand DBG_VALUE instruction!"); } } else { MLoc = Asm->getDebugValueLocation(Begin); @@ -2608,56 +2617,61 @@ MCSymbol *end = Asm->OutStreamer.getContext().CreateTempSymbol(); Asm->EmitLabelDifference(end, begin, 2); Asm->OutStreamer.EmitLabel(begin); - if (Entry.isConstant()) { + if (Entry.isInt()) { DIBasicType BTy(DV.getType()); if (BTy.Verify() && (BTy.getEncoding() == dwarf::DW_ATE_signed || BTy.getEncoding() == dwarf::DW_ATE_signed_char)) { Asm->OutStreamer.AddComment("DW_OP_consts"); Asm->EmitInt8(dwarf::DW_OP_consts); - Asm->EmitSLEB128(Entry.getConstant()); + Asm->EmitSLEB128(Entry.getInt()); } else { Asm->OutStreamer.AddComment("DW_OP_constu"); Asm->EmitInt8(dwarf::DW_OP_constu); - Asm->EmitULEB128(Entry.getConstant()); + Asm->EmitULEB128(Entry.getInt()); } - } else if (DV.hasComplexAddress()) { - unsigned N = DV.getNumAddrElements(); - unsigned i = 0; - if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) { - if (Entry.Loc.getOffset()) { - i = 2; - Asm->EmitDwarfRegOp(Entry.Loc); - Asm->OutStreamer.AddComment("DW_OP_deref"); - Asm->EmitInt8(dwarf::DW_OP_deref); - Asm->OutStreamer.AddComment("DW_OP_plus_uconst"); - Asm->EmitInt8(dwarf::DW_OP_plus_uconst); - Asm->EmitSLEB128(DV.getAddrElement(1)); + } else if (Entry.isLocation()) { + if (!DV.hasComplexAddress()) + // Regular entry. + Asm->EmitDwarfRegOp(Entry.Loc); + else { + // Complex address entry. + unsigned N = DV.getNumAddrElements(); + unsigned i = 0; + if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) { + if (Entry.Loc.getOffset()) { + i = 2; + Asm->EmitDwarfRegOp(Entry.Loc); + Asm->OutStreamer.AddComment("DW_OP_deref"); + Asm->EmitInt8(dwarf::DW_OP_deref); + Asm->OutStreamer.AddComment("DW_OP_plus_uconst"); + Asm->EmitInt8(dwarf::DW_OP_plus_uconst); + Asm->EmitSLEB128(DV.getAddrElement(1)); + } else { + // If first address element is OpPlus then emit + // DW_OP_breg + Offset instead of DW_OP_reg + Offset. + MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1)); + Asm->EmitDwarfRegOp(Loc); + i = 2; + } } else { - // If first address element is OpPlus then emit - // DW_OP_breg + Offset instead of DW_OP_reg + Offset. - MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1)); - Asm->EmitDwarfRegOp(Loc); - i = 2; + Asm->EmitDwarfRegOp(Entry.Loc); + } + + // Emit remaining complex address elements. + for (; i < N; ++i) { + uint64_t Element = DV.getAddrElement(i); + if (Element == DIBuilder::OpPlus) { + Asm->EmitInt8(dwarf::DW_OP_plus_uconst); + Asm->EmitULEB128(DV.getAddrElement(++i)); + } else if (Element == DIBuilder::OpDeref) + Asm->EmitInt8(dwarf::DW_OP_deref); + else llvm_unreachable("unknown Opcode found in complex address"); } - } else { - Asm->EmitDwarfRegOp(Entry.Loc); - } - - // Emit remaining complex address elements. - for (; i < N; ++i) { - uint64_t Element = DV.getAddrElement(i); - if (Element == DIBuilder::OpPlus) { - Asm->EmitInt8(dwarf::DW_OP_plus_uconst); - Asm->EmitULEB128(DV.getAddrElement(++i)); - } else if (Element == DIBuilder::OpDeref) - Asm->EmitInt8(dwarf::DW_OP_deref); - else llvm_unreachable("unknown Opcode found in complex address"); } - } else { - // Regular entry. - Asm->EmitDwarfRegOp(Entry.Loc); } + // else ... ignore constant fp. There is not any good way to + // to represent them here in dwarf. Asm->OutStreamer.EmitLabel(end); } } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=134702&r1=134701&r2=134702&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Fri Jul 8 11:49:43 2011 @@ -69,17 +69,35 @@ const MDNode *Variable; bool Merged; bool Constant; - int64_t iConstant; + enum EntryType { + E_Location, + E_Integer, + E_ConstantFP, + E_ConstantInt + }; + enum EntryType EntryKind; + + union { + int64_t Int; + const ConstantFP *CFP; + const ConstantInt *CIP; + } Constants; DotDebugLocEntry() : Begin(0), End(0), Variable(0), Merged(false), - Constant(false), iConstant(0) {} + Constant(false) { Constants.Int = 0;} DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L, const MDNode *V) : Begin(B), End(E), Loc(L), Variable(V), Merged(false), - Constant(false), iConstant(0) {} + Constant(false) { Constants.Int = 0; EntryKind = E_Location; } DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, int64_t i) : Begin(B), End(E), Variable(0), Merged(false), - Constant(true), iConstant(i) {} + Constant(true) { Constants.Int = i; EntryKind = E_Integer; } + DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, const ConstantFP *FPtr) + : Begin(B), End(E), Variable(0), Merged(false), + Constant(true) { Constants.CFP = FPtr; EntryKind = E_ConstantFP; } + DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, const ConstantInt *IPtr) + : Begin(B), End(E), Variable(0), Merged(false), + Constant(true) { Constants.CIP = IPtr; EntryKind = E_ConstantInt; } /// Empty entries are also used as a trigger to emit temp label. Such /// labels are referenced is used to find debug_loc offset for a given DIE. @@ -91,8 +109,13 @@ Next->Begin = Begin; Merged = true; } - bool isConstant() { return Constant; } - int64_t getConstant() { return iConstant; } + bool isLocation() const { return EntryKind == E_Location; } + bool isInt() const { return EntryKind == E_Integer; } + bool isConstantFP() const { return EntryKind == E_ConstantFP; } + bool isConstantInt() const { return EntryKind == E_ConstantInt; } + int64_t getInt() { return Constants.Int; } + const ConstantFP *getConstantFP() { return Constants.CFP; } + const ConstantInt *getConstantInt() { return Constants.CIP; } } DotDebugLocEntry; //===----------------------------------------------------------------------===// From dpatel at apple.com Fri Jul 8 12:09:57 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 08 Jul 2011 17:09:57 -0000 Subject: [llvm-commits] [llvm] r134703 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110708170957.7FDED2A6C12C@llvm.org> Author: dpatel Date: Fri Jul 8 12:09:57 2011 New Revision: 134703 URL: http://llvm.org/viewvc/llvm-project?rev=134703&view=rev Log: Refactor. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134703&r1=134702&r2=134703&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Jul 8 12:09:57 2011 @@ -1355,6 +1355,34 @@ MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0; } +/// getDebugLocEntry - Get .debug_loc entry for the instraction range starting +/// at MI. +static DotDebugLocEntry getDebugLocEntry(AsmPrinter *Asm, + const MCSymbol *FLabel, + const MCSymbol *SLabel, + const MachineInstr *MI) { + const MDNode *Var = MI->getOperand(MI->getNumOperands() - 1).getMetadata(); + + if (MI->getNumOperands() != 3) { + MachineLocation MLoc = Asm->getDebugValueLocation(MI); + return DotDebugLocEntry(FLabel, SLabel, MLoc, Var); + } + if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) { + MachineLocation MLoc; + MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); + return DotDebugLocEntry(FLabel, SLabel, MLoc, Var); + } + if (MI->getOperand(0).isImm()) + return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getImm()); + if (MI->getOperand(0).isFPImm()) + return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getFPImm()); + if (MI->getOperand(0).isCImm()) + return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getCImm()); + + assert (0 && "Unexpected 3 operand DBG_VALUE instruction!"); + return DotDebugLocEntry(); +} + /// collectVariableInfo - Populate DbgScope entries with variables' info. void DwarfDebug::collectVariableInfo(const MachineFunction *MF, @@ -1441,34 +1469,7 @@ } // The value is valid until the next DBG_VALUE or clobber. - MachineLocation MLoc; - if (Begin->getNumOperands() == 3) { - if (Begin->getOperand(0).isReg() && Begin->getOperand(1).isImm()) { - MLoc.set(Begin->getOperand(0).getReg(), - Begin->getOperand(1).getImm()); - DotDebugLocEntries. - push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); - } - else if (Begin->getOperand(0).isImm()) { - DotDebugLocEntries. - push_back(DotDebugLocEntry(FLabel, SLabel, - Begin->getOperand(0).getImm())); - } else if (Begin->getOperand(0).isFPImm()) { - DotDebugLocEntries. - push_back(DotDebugLocEntry(FLabel, SLabel, - Begin->getOperand(0).getFPImm())); - } else if (Begin->getOperand(0).isCImm()) { - DotDebugLocEntries. - push_back(DotDebugLocEntry(FLabel, SLabel, - Begin->getOperand(0).getCImm())); - } else { - assert (0 && "Unexpected 3 operand DBG_VALUE instruction!"); - } - } else { - MLoc = Asm->getDebugValueLocation(Begin); - DotDebugLocEntries. - push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); - } + DotDebugLocEntries.push_back(getDebugLocEntry(Asm, FLabel, SLabel, Begin)); } DotDebugLocEntries.push_back(DotDebugLocEntry()); } From grosbach at apple.com Fri Jul 8 12:36:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 17:36:35 -0000 Subject: [llvm-commits] [llvm] r134704 - in /llvm/trunk: Makefile.rules include/llvm/Target/Target.td utils/TableGen/CMakeLists.txt utils/TableGen/PseudoLoweringEmitter.cpp utils/TableGen/PseudoLoweringEmitter.h utils/TableGen/TableGen.cpp Message-ID: <20110708173635.4CA5B2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 12:36:35 2011 New Revision: 134704 URL: http://llvm.org/viewvc/llvm-project?rev=134704&view=rev Log: TableGen'erated MC lowering for simple pseudo-instructions. This allows the (many) pseudo-instructions we have that map onto a single real instruction to have their expansion during MC lowering handled automatically instead of the current cumbersome manual expansion required. These sorts of pseudos are common when an instruction is used in situations that require different MachineInstr flags (isTerminator, isBranch, et. al.) than the generic instruction description has. For example, using a move to the PC to implement a branch. Added: llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/Target/Target.td llvm/trunk/utils/TableGen/CMakeLists.txt llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=134704&r1=134703&r2=134704&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Jul 8 12:36:35 2011 @@ -1750,6 +1750,11 @@ $(Echo) "Building $( { + dag ResultInst = Result; // The instruction to generate. + bit isPseudo = 1; +} + /// Predicates - These are extra conditionals which are turned into instruction /// selector matching code. Currently each predicate is just a string. class Predicate { Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=134704&r1=134703&r2=134704&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Fri Jul 8 12:36:35 2011 @@ -34,6 +34,7 @@ LLVMCConfigurationEmitter.cpp NeonEmitter.cpp OptParserEmitter.cpp + PseudoLoweringEmitter.cpp Record.cpp RegisterInfoEmitter.cpp SetTheory.cpp Added: llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp?rev=134704&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp (added) +++ llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp Fri Jul 8 12:36:35 2011 @@ -0,0 +1,243 @@ +//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "pseudo-lowering" +#include "Error.h" +#include "CodeGenInstruction.h" +#include "PseudoLoweringEmitter.h" +#include "Record.h" +#include "llvm/ADT/IndexedMap.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Debug.h" +#include +using namespace llvm; + +// FIXME: This pass currently can only expand a pseudo to a single instruction. +// The pseudo expansion really should take a list of dags, not just +// a single dag, so we can do fancier things. + +unsigned PseudoLoweringEmitter:: +addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, + IndexedMap &OperandMap, unsigned BaseIdx) { + unsigned OpsAdded = 0; + for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { + if (DefInit *DI = dynamic_cast(Dag->getArg(i))) { + // Physical register reference. Explicit check for the special case + // "zero_reg" definition. + if (DI->getDef()->isSubClassOf("Register") || + DI->getDef()->getName() == "zero_reg") { + OperandMap[BaseIdx + i].Kind = OpData::Reg; + OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); + ++OpsAdded; + continue; + } + + // Normal operands should always have the same type, or we have a + // problem. + // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. + assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); + if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) + throw TGError(Rec->getLoc(), + "Pseudo operand type '" + DI->getDef()->getName() + + "' does not match expansion operand type '" + + Insn.Operands[BaseIdx + i].Rec->getName() + "'"); + // Source operand maps to destination operand. The Data element + // will be filled in later, just set the Kind for now. Do it + // for each corresponding MachineInstr operand, not just the first. + for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) + OperandMap[BaseIdx + i + I].Kind = OpData::Operand; + OpsAdded += Insn.Operands[i].MINumOperands; + } else if (IntInit *II = dynamic_cast(Dag->getArg(i))) { + OperandMap[BaseIdx + i].Kind = OpData::Imm; + OperandMap[BaseIdx + i].Data.Imm = II->getValue(); + ++OpsAdded; + } else if (DagInit *SubDag = dynamic_cast(Dag->getArg(i))) { + // Just add the operands recursively. This is almost certainly + // a constant value for a complex operand (> 1 MI operand). + unsigned NewOps = + addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); + OpsAdded += NewOps; + // Since we added more than one, we also need to adjust the base. + BaseIdx += NewOps - 1; + } else + assert(0 && "Unhandled pseudo-expansion argument type!"); + } + return OpsAdded; +} + +void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { + DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); + + // Validate that the result pattern has the corrent number and types + // of arguments for the instruction it references. + DagInit *Dag = Rec->getValueAsDag("ResultInst"); + assert(Dag && "Missing result instruction in pseudo expansion!"); + DEBUG(dbgs() << " Result: " << *Dag << "\n"); + + DefInit *OpDef = dynamic_cast(Dag->getOperator()); + if (!OpDef) + throw TGError(Rec->getLoc(), Rec->getName() + + " has unexpected operator type!"); + Record *Operator = OpDef->getDef(); + if (!Operator->isSubClassOf("Instruction")) + throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + + "' is not an instruction!"); + + CodeGenInstruction Insn(Operator); + + if (Insn.isCodeGenOnly || Insn.isPseudo) + throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + + "' cannot be another pseudo instruction!"); + + if (Insn.Operands.size() != Dag->getNumArgs()) + throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + + "' operand count mismatch"); + + IndexedMap OperandMap; + OperandMap.grow(Insn.Operands.size()); + + addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); + + // If there are more operands that weren't in the DAG, they have to + // be operands that have default values, or we have an error. Currently, + // PredicateOperand and OptionalDefOperand both have default values. + + + // Validate that each result pattern argument has a matching (by name) + // argument in the source instruction, in either the (outs) or (ins) list. + // Also check that the type of the arguments match. + // + // Record the mapping of the source to result arguments for use by + // the lowering emitter. + CodeGenInstruction SourceInsn(Rec); + StringMap SourceOperands; + for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) + SourceOperands[SourceInsn.Operands[i].Name] = i; + + DEBUG(dbgs() << " Operand mapping:\n"); + for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { + // We've already handled constant values. Just map instruction operands + // here. + if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) + continue; + StringMap::iterator SourceOp = + SourceOperands.find(Dag->getArgName(i)); + if (SourceOp == SourceOperands.end()) + throw TGError(Rec->getLoc(), + "Pseudo output operand '" + Dag->getArgName(i) + + "' has no matching source operand."); + // Map the source operand to the destination operand index for each + // MachineInstr operand. + for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) + OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = + SourceOp->getValue(); + + DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i << "\n"); + } + + Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); +} + +void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { + // Emit file header. + EmitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); + + o << "bool " << Target.getName() + "AsmPrinter" << "::\n" + << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n" + << " const MachineInstr *MI) {\n" + << " switch (MI->getOpcode()) {\n" + << " default: return false;\n"; + for (unsigned i = 0, e = Expansions.size(); i != e; ++i) { + PseudoExpansion &Expansion = Expansions[i]; + CodeGenInstruction &Source = Expansion.Source; + CodeGenInstruction &Dest = Expansion.Dest; + o << " case " << Source.Namespace << "::" + << Source.TheDef->getName() << ": {\n" + << " MCInst TmpInst;\n" + << " MCOperand MCOp;\n" + << " TmpInst.setOpcode(" << Dest.Namespace << "::" + << Dest.TheDef->getName() << ");\n"; + + // Copy the operands from the source instruction. + // FIXME: Instruction operands with defaults values (predicates and cc_out + // in ARM, for example shouldn't need explicit values in the + // expansion DAG. + unsigned MIOpNo = 0; + for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E; + ++OpNo) { + o << " // Operand: " << Dest.Operands[OpNo].Name << "\n"; + for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands; + i != e; ++i) { + switch (Expansion.OperandMap[MIOpNo + i].Kind) { + default: + llvm_unreachable("Unknown operand type?!"); + case OpData::Operand: + o << " lowerOperand(MI->getOperand(" + << Source.Operands[Expansion.OperandMap[MIOpNo].Data + .Operand].MIOperandNo + i + << "), MCOp);\n" + << " TmpInst.addOperand(MCOp);\n"; + break; + case OpData::Imm: + o << " TmpInst.addOperand(MCOperand::CreateImm(" + << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; + break; + case OpData::Reg: { + Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; + o << " TmpInst.addOperand(MCOperand::CreateReg("; + // "zero_reg" is special. + if (Reg->getName() == "zero_reg") + o << "0"; + else + o << Reg->getValueAsString("Namespace") << "::" << Reg->getName(); + o << "));\n"; + break; + } + } + } + MIOpNo += Dest.Operands[OpNo].MINumOperands; + } + if (Dest.Operands.isVariadic) { + o << " // variable_ops\n"; + o << " for (unsigned i = " << MIOpNo + << ", e = MI->getNumOperands(); i != e; ++i)\n" + << " if (lowerOperand(MI->getOperand(i), MCOp))\n" + << " TmpInst.addOperand(MCOp);\n"; + } + o << " OutStreamer.EmitInstruction(TmpInst);\n" + << " break;\n" + << " }\n"; + } + o << " }\n return true;\n}\n\n"; +} + +void PseudoLoweringEmitter::run(raw_ostream &o) { + Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); + Record *InstructionClass = Records.getClass("PseudoInstExpansion"); + assert(ExpansionClass && "PseudoInstExpansion class definition missing!"); + assert(InstructionClass && "Instruction class definition missing!"); + + std::vector Insts; + for (std::map::const_iterator I = + Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) { + if (I->second->isSubClassOf(ExpansionClass) && + I->second->isSubClassOf(InstructionClass)) + Insts.push_back(I->second); + } + + // Process the pseudo expansion definitions, validating them as we do so. + for (unsigned i = 0, e = Insts.size(); i != e; ++i) + evaluateExpansion(Insts[i]); + + // Generate expansion code to lower the pseudo to an MCInst of the real + // instruction. + emitLoweringEmitter(o); +} + Added: llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h?rev=134704&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h (added) +++ llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h Fri Jul 8 12:36:35 2011 @@ -0,0 +1,65 @@ +//===- PseudoLoweringEmitter.h - PseudoLowering Generator -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef PSEUDOLOWERINGEMITTER_H +#define PSEUDOLOWERINGEMITTER_H + +#include "CodeGenInstruction.h" +#include "CodeGenTarget.h" +#include "TableGenBackend.h" +#include "llvm/ADT/IndexedMap.h" +#include "llvm/ADT/SmallVector.h" + +namespace llvm { + +class PseudoLoweringEmitter : public TableGenBackend { + struct OpData { + enum MapKind { Operand, Imm, Reg }; + MapKind Kind; + union { + unsigned Operand; // Operand number mapped to. + uint64_t Imm; // Integer immedate value. + Record *Reg; // Physical register. + } Data; + }; + struct PseudoExpansion { + CodeGenInstruction Source; // The source pseudo instruction definition. + CodeGenInstruction Dest; // The destination instruction to lower to. + IndexedMap OperandMap; + + PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d, + IndexedMap &m) : + Source(s), Dest(d), OperandMap(m) {} + }; + + RecordKeeper &Records; + + // It's overkill to have an instance of the full CodeGenTarget object, + // but it loads everything on demand, not in the constructor, so it's + // lightweight in performance, so it works out OK. + CodeGenTarget Target; + + SmallVector Expansions; + + unsigned addDagOperandMapping(Record *Rec, DagInit *Dag, + CodeGenInstruction &Insn, + IndexedMap &OperandMap, + unsigned BaseIdx); + void evaluateExpansion(Record *Pseudo); + void emitLoweringEmitter(raw_ostream &o); +public: + PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {} + + /// run - Output the pseudo-lowerings. + void run(raw_ostream &o); +}; + +} // end llvm namespace + +#endif Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=134704&r1=134703&r2=134704&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Fri Jul 8 12:36:35 2011 @@ -33,6 +33,7 @@ #include "LLVMCConfigurationEmitter.h" #include "NeonEmitter.h" #include "OptParserEmitter.h" +#include "PseudoLoweringEmitter.h" #include "Record.h" #include "RegisterInfoEmitter.h" #include "ARMDecoderEmitter.h" @@ -59,6 +60,7 @@ GenAsmMatcher, GenARMDecoder, GenDisassembler, + GenPseudoLowering, GenCallingConv, GenClangAttrClasses, GenClangAttrImpl, @@ -106,6 +108,8 @@ "Generate decoders for ARM/Thumb"), clEnumValN(GenDisassembler, "gen-disassembler", "Generate disassembler"), + clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", + "Generate pseudo instruction lowering"), clEnumValN(GenAsmMatcher, "gen-asm-matcher", "Generate assembly instruction matcher"), clEnumValN(GenDAGISel, "gen-dag-isel", @@ -314,6 +318,9 @@ case GenDisassembler: DisassemblerEmitter(Records).run(Out.os()); break; + case GenPseudoLowering: + PseudoLoweringEmitter(Records).run(Out.os()); + break; case GenOptParserDefs: OptParserEmitter(Records, true).run(Out.os()); break; From grosbach at apple.com Fri Jul 8 12:40:42 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 17:40:42 -0000 Subject: [llvm-commits] [llvm] r134705 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMAsmPrinter.h ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb.td ARMInstrThumb2.td ARMMCInstLower.cpp Makefile Message-ID: <20110708174042.D612A2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 12:40:42 2011 New Revision: 134705 URL: http://llvm.org/viewvc/llvm-project?rev=134705&view=rev Log: Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/Makefile Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 12:40:42 2011 @@ -1069,48 +1069,18 @@ extern cl::opt EnableARMEHABI; +// Simple pseudo-instructions have their lowering (with expansion to real +// instructions) auto-generated. +#include "ARMGenMCPseudoLowering.inc" + void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { - unsigned Opc = MI->getOpcode(); - switch (Opc) { - default: break; - case ARM::B: { - // B is just a Bcc with an 'always' predicate. - MCInst TmpInst; - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(ARM::Bcc); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - return; - } - case ARM::LDMIA_RET: { - // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as - // such has additional code-gen properties and scheduling information. - // To emit it, we just construct as normal and set the opcode to LDMIA_UPD. - MCInst TmpInst; - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(ARM::LDMIA_UPD); - OutStreamer.EmitInstruction(TmpInst); - return; - } - case ARM::t2LDMIA_RET: { - // As above for LDMIA_RET. Map to the tPOP instruction. - MCInst TmpInst; - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(ARM::t2LDMIA_UPD); - OutStreamer.EmitInstruction(TmpInst); + // Do any auto-generated pseudo lowerings. + if (emitPseudoExpansionLowering(OutStreamer, MI)) return; - } - case ARM::tPOP_RET: { - // As above for LDMIA_RET. Map to the tPOP instruction. - MCInst TmpInst; - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(ARM::tPOP); - OutStreamer.EmitInstruction(TmpInst); - return; - } + // Check for manual lowerings. + unsigned Opc = MI->getOpcode(); + switch (Opc) { case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass"); case ARM::DBG_VALUE: { if (isVerbose() && OutStreamer.hasRawTextSupport()) { @@ -1121,14 +1091,6 @@ } return; } - case ARM::tBfar: { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tBL); - TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create( - MI->getOperand(0).getMBB()->getSymbol(), OutContext))); - OutStreamer.EmitInstruction(TmpInst); - return; - } case ARM::LEApcrel: case ARM::tLEApcrel: case ARM::t2LEApcrel: { @@ -1159,19 +1121,6 @@ OutStreamer.EmitInstruction(TmpInst); return; } - case ARM::MOVPCRX: { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - return; - } // Darwin call instructions are just normal call instructions with different // clobber semantics (they clobber R9). case ARM::BLr9: @@ -1912,31 +1861,6 @@ OutStreamer.EmitInstruction(TmpInst); return; } - - // These are the pseudos created to comply with stricter operand restrictions - // on ARMv5. Lower them now to "normal" instructions, since all the - // restrictions are already satisfied. - case ARM::MULv5: - EmitPatchedInstruction(MI, ARM::MUL); - return; - case ARM::MLAv5: - EmitPatchedInstruction(MI, ARM::MLA); - return; - case ARM::SMULLv5: - EmitPatchedInstruction(MI, ARM::SMULL); - return; - case ARM::UMULLv5: - EmitPatchedInstruction(MI, ARM::UMULL); - return; - case ARM::SMLALv5: - EmitPatchedInstruction(MI, ARM::SMLAL); - return; - case ARM::UMLALv5: - EmitPatchedInstruction(MI, ARM::UMLAL); - return; - case ARM::UMAALv5: - EmitPatchedInstruction(MI, ARM::UMAAL); - return; } MCInst TmpInst; Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h Fri Jul 8 12:40:42 2011 @@ -21,6 +21,8 @@ namespace llvm { +class MCOperand; + namespace ARM { enum DW_ISA { DW_ISA_ARM_thumb = 1, @@ -72,6 +74,9 @@ void EmitStartOfAsmFile(Module &M); void EmitEndOfAsmFile(Module &M); + // lowerOperand - Convert a MachineOperand into the equivalent MCOperand. + bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp); + private: // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile() void emitAttributes(); @@ -84,6 +89,10 @@ void EmitUnwindingInstruction(const MachineInstr *MI); + // emitPseudoExpansionLowering - tblgen'erated. + bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, + const MachineInstr *MI); + public: void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); @@ -100,6 +109,7 @@ llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm; } + MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol); MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2, const MachineBasicBlock *MBB) const; MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const; @@ -107,7 +117,7 @@ MCSymbol *GetARMSJLJEHLabel(void) const; MCSymbol *GetARMGVSymbol(const GlobalValue *GV); - + /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV); Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Jul 8 12:40:42 2011 @@ -314,6 +314,25 @@ let SZ = sz; list Predicates = [IsThumb2]; } + +class ARMPseudoExpand pattern, + dag Result> + : ARMPseudoInst, + PseudoInstExpansion; + +class tPseudoExpand pattern, + dag Result> + : tPseudoInst, + PseudoInstExpansion; + +class t2PseudoExpand pattern, + dag Result> + : t2PseudoInst, + PseudoInstExpansion; + // Almost all ARM instructions are predicable. class I - // With that, however, we can't set isBranch, isTerminator, etc.. - def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst), - Size4Bytes, IIC_Br, [(brind GPR:$dst)]>, - Requires<[IsARM, NoV4T]>; } // All calls clobber the non-callee saved registers. SP is marked as @@ -1526,13 +1518,23 @@ } let isBranch = 1, isTerminator = 1 in { - // B is "predicable" since it's just a Bcc with an 'always' condition. + // FIXME: should be able to write a pattern for ARMBrcond, but can't use + // a two-value operand where a dag node expects two operands. :( + def Bcc : ABI<0b1010, (outs), (ins br_target:$target), + IIC_Br, "b", "\t$target", + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { + bits<24> target; + let Inst{23-0} = target; + } + let isBarrier = 1 in { + // B is "predicable" since it's just a Bcc with an 'always' condition. let isPredicable = 1 in // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly // should be sufficient. - def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br, - [(br bb:$target)]>; + // FIXME: Is B really a Barrier? That doesn't seem right. + def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br, + [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; let isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : ARMPseudoInst<(outs), @@ -1554,14 +1556,6 @@ } // isNotDuplicable = 1, isIndirectBranch = 1 } // isBarrier = 1 - // FIXME: should be able to write a pattern for ARMBrcond, but can't use - // a two-value operand where a dag node expects two operands. :( - def Bcc : ABI<0b1010, (outs), (ins br_target:$target), - IIC_Br, "b", "\t$target", - [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { - bits<24> target; - let Inst{23-0} = target; - } } // BLX (immediate) -- for disassembly only @@ -2030,9 +2024,10 @@ // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in -def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, - reglist:$regs, variable_ops), - Size4Bytes, IIC_iLoad_mBr, []>, +def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, + reglist:$regs, variable_ops), + Size4Bytes, IIC_iLoad_mBr, [], + (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, RegConstraint<"$Rn = $wb">; //===----------------------------------------------------------------------===// @@ -2690,28 +2685,26 @@ let Inst{3-0} = Rn; } +// FIXME: The v5 pseudos are only necessary for the additional Constraint +// property. Remove them when it's possible to add those properties +// on an individual MachineInstr, not just an instuction description. let isCommutable = 1 in { -let Constraints = "@earlyclobber $Rd" in -def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, - pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL32, - [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>, - Requires<[IsARM, NoV6]>; - def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]> { let Inst{15-12} = 0b0000; } -} let Constraints = "@earlyclobber $Rd" in -def MLAv5: ARMPseudoInst<(outs GPR:$Rd), - (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC32, - [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, +def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, + pred:$p, cc_out:$s), + Size4Bytes, IIC_iMUL32, + [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))], + (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; +} + def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, @@ -2720,6 +2713,14 @@ let Inst{15-12} = Ra; } +let Constraints = "@earlyclobber $Rd" in +def MLAv5: ARMPseudoExpand<(outs GPR:$Rd), + (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), + Size4Bytes, IIC_iMAC32, + [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))], + (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>, + Requires<[IsARM, NoV6]>; + def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, @@ -2735,49 +2736,34 @@ } // Extra precision multiplies with low / high results - let neverHasSideEffects = 1 in { let isCommutable = 1 in { -let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in { -def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi), - (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL64, []>, - Requires<[IsARM, NoV6]>; - -def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi), - (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL64, []>, - Requires<[IsARM, NoV6]>; -} - def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), - (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, + (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, Requires<[IsARM, HasV6]>; def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), - (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, + (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, Requires<[IsARM, HasV6]>; -} -// Multiply + accumulate let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in { -def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi), +def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC64, []>, + Size4Bytes, IIC_iMUL64, [], + (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; -def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi), - (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC64, []>, - Requires<[IsARM, NoV6]>; -def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi), + +def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC64, []>, + Size4Bytes, IIC_iMUL64, [], + (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; - +} } +// Multiply + accumulate def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, @@ -2800,6 +2786,25 @@ let Inst{11-8} = Rm; let Inst{3-0} = Rn; } + +let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in { +def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), + (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), + Size4Bytes, IIC_iMAC64, [], + (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, + Requires<[IsARM, NoV6]>; +def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), + (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), + Size4Bytes, IIC_iMAC64, [], + (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, + Requires<[IsARM, NoV6]>; +def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), + (ins GPR:$Rn, GPR:$Rm, pred:$p), + Size4Bytes, IIC_iMAC64, [], + (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>, + Requires<[IsARM, NoV6]>; +} + } // neverHasSideEffects // Most significant word multiply @@ -3838,6 +3843,13 @@ // Non-Instruction Patterns // +// ARMv4 indirect branch using (MOVr PC, dst) +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in + def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), + Size4Bytes, IIC_Br, [(brind GPR:$dst)], + (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, + Requires<[IsARM, NoV4T]>; + // Large immediate handling. // 32-bit immediate using two piece so_imms or movw + movt. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 12:40:42 2011 @@ -405,12 +405,6 @@ } } -// FIXME: remove when we have a way to marking a MI with these properties. -let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, - hasExtraDefRegAllocReq = 1 in -def tPOP_RET : tPseudoInst<(outs), (ins pred:$p, reglist:$regs, variable_ops), - Size2Bytes, IIC_iPop_Br, []>; - // All calls clobber the non-callee saved registers. SP is marked as a use to // prevent stack-pointer assignments that appear immediately before calls from // potentially appearing dead. @@ -528,8 +522,8 @@ // Just a pseudo for a tBL instruction. Needed to let regalloc know about // the clobber of LR. let Defs = [LR] in - def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target), - Size4Bytes, IIC_Br, []>; + def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target), + Size4Bytes, IIC_Br, [], (tBL t_bltarget:$target)>; def tBR_JTr : tPseudoInst<(outs), (ins tGPR:$target, i32imm:$jt, i32imm:$id), @@ -1477,3 +1471,12 @@ [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), imm:$cp))]>, Requires<[IsThumb, IsThumb1Only]>; + +// Pseudo-instruction for merged POP and return. +// FIXME: remove when we have a way to marking a MI with these properties. +let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, + hasExtraDefRegAllocReq = 1 in +def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), + Size2Bytes, IIC_iPop_Br, [], + (tPOP pred:$p, reglist:$regs)>; + Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul 8 12:40:42 2011 @@ -2978,9 +2978,10 @@ // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in -def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, +def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), - Size4Bytes, IIC_iLoad_mBr, []>, + Size4Bytes, IIC_iLoad_mBr, [], + (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, RegConstraint<"$Rn = $wb">; let isBranch = 1, isTerminator = 1, isBarrier = 1 in { Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Fri Jul 8 12:40:42 2011 @@ -23,43 +23,94 @@ using namespace llvm; -static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, - ARMAsmPrinter &Printer) { - MCContext &Ctx = Printer.OutContext; +MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, + const MCSymbol *Symbol) { const MCExpr *Expr; switch (MO.getTargetFlags()) { default: { - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, + OutContext); switch (MO.getTargetFlags()) { default: assert(0 && "Unknown target flag on symbol operand"); case 0: break; case ARMII::MO_LO16: - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); - Expr = ARMMCExpr::CreateLower16(Expr, Ctx); + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, + OutContext); + Expr = ARMMCExpr::CreateLower16(Expr, OutContext); break; case ARMII::MO_HI16: - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); - Expr = ARMMCExpr::CreateUpper16(Expr, Ctx); + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, + OutContext); + Expr = ARMMCExpr::CreateUpper16(Expr, OutContext); break; } break; } case ARMII::MO_PLT: - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx); + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, + OutContext); break; } if (!MO.isJTI() && MO.getOffset()) Expr = MCBinaryExpr::CreateAdd(Expr, - MCConstantExpr::Create(MO.getOffset(), Ctx), - Ctx); + MCConstantExpr::Create(MO.getOffset(), + OutContext), + OutContext); return MCOperand::CreateExpr(Expr); } +bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO, + MCOperand &MCOp) { + switch (MO.getType()) { + default: + assert(0 && "unknown operand type"); + return false; + case MachineOperand::MO_Register: + // Ignore all non-CPSR implicit register operands. + if (MO.isImplicit() && MO.getReg() != ARM::CPSR) + return false; + assert(!MO.getSubReg() && "Subregs should be eliminated!"); + MCOp = MCOperand::CreateReg(MO.getReg()); + break; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::CreateImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( + MO.getMBB()->getSymbol(), OutContext)); + break; + case MachineOperand::MO_GlobalAddress: + MCOp = GetSymbolRef(MO, Mang->getSymbol(MO.getGlobal())); + break; + case MachineOperand::MO_ExternalSymbol: + MCOp = GetSymbolRef(MO, + GetExternalSymbolSymbol(MO.getSymbolName())); + break; + case MachineOperand::MO_JumpTableIndex: + MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex())); + break; + case MachineOperand::MO_ConstantPoolIndex: + MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex())); + break; + case MachineOperand::MO_BlockAddress: + MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress())); + break; + case MachineOperand::MO_FPImmediate: { + APFloat Val = MO.getFPImm()->getValueAPF(); + bool ignored; + Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); + MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); + break; + } + } + return true; +} + void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP) { OutMI.setOpcode(MI->getOpcode()); @@ -68,48 +119,7 @@ const MachineOperand &MO = MI->getOperand(i); MCOperand MCOp; - switch (MO.getType()) { - default: - MI->dump(); - assert(0 && "unknown operand type"); - case MachineOperand::MO_Register: - // Ignore all non-CPSR implicit register operands. - if (MO.isImplicit() && MO.getReg() != ARM::CPSR) continue; - assert(!MO.getSubReg() && "Subregs should be eliminated!"); - MCOp = MCOperand::CreateReg(MO.getReg()); - break; - case MachineOperand::MO_Immediate: - MCOp = MCOperand::CreateImm(MO.getImm()); - break; - case MachineOperand::MO_MachineBasicBlock: - MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( - MO.getMBB()->getSymbol(), AP.OutContext)); - break; - case MachineOperand::MO_GlobalAddress: - MCOp = GetSymbolRef(MO, AP.Mang->getSymbol(MO.getGlobal()), AP); - break; - case MachineOperand::MO_ExternalSymbol: - MCOp = GetSymbolRef(MO, - AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); - break; - case MachineOperand::MO_JumpTableIndex: - MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP); - break; - case MachineOperand::MO_ConstantPoolIndex: - MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP); - break; - case MachineOperand::MO_BlockAddress: - MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP); - break; - case MachineOperand::MO_FPImmediate: { - APFloat Val = MO.getFPImm()->getValueAPF(); - bool ignored; - Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); - MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); - break; - } - } - - OutMI.addOperand(MCOp); + if (AP.lowerOperand(MO, MCOp)) + OutMI.addOperand(MCOp); } } Modified: llvm/trunk/lib/Target/ARM/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=134705&r1=134704&r2=134705&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Makefile (original) +++ llvm/trunk/lib/Target/ARM/Makefile Fri Jul 8 12:40:42 2011 @@ -17,7 +17,8 @@ ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \ ARMGenCodeEmitter.inc ARMGenCallingConv.inc \ ARMGenDecoderTables.inc ARMGenEDInfo.inc \ - ARMGenFastISel.inc ARMGenMCCodeEmitter.inc + ARMGenFastISel.inc ARMGenMCCodeEmitter.inc \ + ARMGenMCPseudoLowering.inc DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc From chandlerc at gmail.com Fri Jul 8 12:54:08 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Fri, 08 Jul 2011 17:54:08 -0000 Subject: [llvm-commits] [llvm] r134707 - /llvm/trunk/lib/Target/ARM/CMakeLists.txt Message-ID: <20110708175408.992782A6C12C@llvm.org> Author: chandlerc Date: Fri Jul 8 12:54:08 2011 New Revision: 134707 URL: http://llvm.org/viewvc/llvm-project?rev=134707&view=rev Log: Add CMake support for the new TableGen file introduced in r134705. Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134707&r1=134706&r2=134707&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Fri Jul 8 12:54:08 2011 @@ -4,6 +4,7 @@ tablegen(ARMGenInstrInfo.inc -gen-instr-info) tablegen(ARMGenCodeEmitter.inc -gen-emitter) tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter) +tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering) tablegen(ARMGenAsmWriter.inc -gen-asm-writer) tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher) tablegen(ARMGenDAGISel.inc -gen-dag-isel) From dpatel at apple.com Fri Jul 8 13:01:31 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 08 Jul 2011 18:01:31 -0000 Subject: [llvm-commits] [llvm] r134708 - in /llvm/trunk/lib/Transforms/Utils: CloneFunction.cpp InlineFunction.cpp Message-ID: <20110708180131.C0AFC2A6C12C@llvm.org> Author: dpatel Date: Fri Jul 8 13:01:31 2011 New Revision: 134708 URL: http://llvm.org/viewvc/llvm-project?rev=134708&view=rev Log: Refactor. It is inliner's responsibility to update line number information. Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=134708&r1=134707&r2=134708&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Fri Jul 8 13:01:31 2011 @@ -418,50 +418,14 @@ if (PHINode *PN = dyn_cast(I)) { // Skip over all PHI nodes, remembering them for later. BasicBlock::const_iterator OldI = BI->begin(); - for (; (PN = dyn_cast(I)); ++I, ++OldI) { - if (I->hasMetadata()) { - if (!TheCallDL.isUnknown()) { - DebugLoc IDL = I->getDebugLoc(); - if (!IDL.isUnknown()) { - DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL, - I->getContext()); - I->setDebugLoc(NewDL); - } - } else { - // The cloned instruction has dbg info but the call instruction - // does not have dbg info. Remove dbg info from cloned instruction. - I->setDebugLoc(DebugLoc()); - } - } + for (; (PN = dyn_cast(I)); ++I, ++OldI) PHIToResolve.push_back(cast(OldI)); - } } - // FIXME: - // FIXME: - // FIXME: Unclone all this metadata stuff. - // FIXME: - // FIXME: - // Otherwise, remap the rest of the instructions normally. - for (; I != NewBB->end(); ++I) { - if (I->hasMetadata()) { - if (!TheCallDL.isUnknown()) { - DebugLoc IDL = I->getDebugLoc(); - if (!IDL.isUnknown()) { - DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL, - I->getContext()); - I->setDebugLoc(NewDL); - } - } else { - // The cloned instruction has dbg info but the call instruction - // does not have dbg info. Remove dbg info from cloned instruction. - I->setDebugLoc(DebugLoc()); - } - } + for (; I != NewBB->end(); ++I) RemapInstruction(I, VMap, ModuleLevelChanges ? RF_None : RF_NoModuleLevelChanges); - } } // Defer PHI resolution until rest of function is resolved, PHI resolution Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=134708&r1=134707&r2=134708&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Fri Jul 8 13:01:31 2011 @@ -744,6 +744,41 @@ return false; } +/// updateInlinedAtInfo - Helper function used by fixupLineNumbers to recursively +/// update InlinedAtEntry of a DebugLoc. +static DebugLoc updateInlinedAtInfo(const DebugLoc &DL, + const DebugLoc &InlinedAtDL, + LLVMContext &Ctx) { + if (MDNode *IA = DL.getInlinedAt(Ctx)) { + DebugLoc NewInlinedAtDL + = updateInlinedAtInfo(DebugLoc::getFromDILocation(IA), InlinedAtDL, Ctx); + return DebugLoc::get(DL.getLine(), DL.getCol(), DL.getScope(Ctx), + NewInlinedAtDL.getAsMDNode(Ctx)); + } + + return DebugLoc::get(DL.getLine(), DL.getCol(), DL.getScope(Ctx), + InlinedAtDL.getAsMDNode(Ctx)); +} + + +/// fixupLineNumbers - Update inlined instructions' line numbers to +/// to encode location where these instructions are inlined. +static void fixupLineNumbers(Function *Fn, Function::iterator FI, + Instruction *TheCall) { + DebugLoc TheCallDL = TheCall->getDebugLoc(); + if (TheCallDL.isUnknown()) + return; + + for (; FI != Fn->end(); ++FI) { + for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); + BI != BE; ++BI) { + DebugLoc DL = BI->getDebugLoc(); + if (!DL.isUnknown()) + BI->setDebugLoc(updateInlinedAtInfo(DL, TheCallDL, BI->getContext())); + } + } +} + // InlineFunction - This function inlines the called function into the basic // block of the caller. This returns false if it is not possible to inline this // call. The program is still in a well defined state if this occurs though. @@ -846,6 +881,9 @@ // Update the callgraph if requested. if (IFI.CG) UpdateCallGraphAfterInlining(CS, FirstNewBlock, VMap, IFI); + + // Update inlined instructions' line number information. + fixupLineNumbers(Caller, FirstNewBlock, TheCall); } // If there are any alloca instructions in the block that used to be the entry From evan.cheng at apple.com Fri Jul 8 13:04:22 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 18:04:22 -0000 Subject: [llvm-commits] [llvm] r134709 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20110708180422.523D02A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 13:04:22 2011 New Revision: 134709 URL: http://llvm.org/viewvc/llvm-project?rev=134709&view=rev Log: Fix a dangling reference. Patch by Dave Abrahams. pr10311 Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134709&r1=134708&r2=134709&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Fri Jul 8 13:04:22 2011 @@ -1825,7 +1825,8 @@ SubtargetFeatureInfo &SFI = *it->second; OS << " if ("; - StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString"); + std::string CondStorage = SFI.TheDef->getValueAsString("AssemblerCondString"); + StringRef Conds = CondStorage; std::pair Comma = Conds.split(','); bool First = true; do { From sabre at nondot.org Fri Jul 8 13:12:50 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 08 Jul 2011 18:12:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r134710 - in /llvm-gcc-4.2/trunk/gcc: llvm-abi-default.cpp llvm-types.cpp Message-ID: <20110708181251.0B2712A6C12C@llvm.org> Author: lattner Date: Fri Jul 8 13:12:50 2011 New Revision: 134710 URL: http://llvm.org/viewvc/llvm-project?rev=134710&view=rev Log: greatly simplify the llvm.pch.types logic, eliminating the need to apply names to all the types. This also eliminates use of TypeSymbolTable.h which is going away. Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=134710&r1=134709&r2=134710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Fri Jul 8 13:12:50 2011 @@ -73,8 +73,8 @@ // not include variable sized fields here. std::vector Elts; if (Ty->isVoidTy()) { - // Handle void explicitly as an opaque type. - const Type *OpTy = OpaqueType::get(getGlobalContext()); + // Handle void explicitly as a {} type. + const Type *OpTy = StructType::get(getGlobalContext()); C.HandleScalarArgument(OpTy, type); ScalarElts.push_back(OpTy); } else if (isPassedByInvisibleReference(type)) { // variable size -> by-ref. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=134710&r1=134709&r2=134710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jul 8 13:12:50 2011 @@ -29,7 +29,6 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Assembly/Writer.h" @@ -122,94 +121,44 @@ // Erase type from LTypes vector static void llvmEraseLType(const Type *Ty) { - LTypesMapTy::iterator I = LTypesMap.find(Ty); if (I != LTypesMap.end()) { // It is OK to clear this entry instead of removing this entry // to avoid re-indexing of other entries. - LTypes[ LTypesMap[Ty] - 1] = NULL; + LTypes[LTypesMap[Ty] - 1] = NULL; LTypesMap.erase(I); } } // Read LLVM Types string table void readLLVMTypesStringTable() { - GlobalValue *V = TheModule->getNamedGlobal("llvm.pch.types"); if (!V) return; - // Value *GV = TheModule->getValueSymbolTable().lookup("llvm.pch.types"); - GlobalVariable *GV = cast(V); - ConstantStruct *LTypesNames = cast(GV->getOperand(0)); - - for (unsigned i = 0; i < LTypesNames->getNumOperands(); ++i) { - const Type *Ty = NULL; - - if (ConstantArray *CA = - dyn_cast(LTypesNames->getOperand(i))) { - std::string Str = CA->getAsString(); - Ty = TheModule->getTypeByName(Str); - assert (Ty != NULL && "Invalid Type in LTypes string table"); - } - // If V is not a string then it is empty. Insert NULL to represent - // empty entries. - LTypes.push_back(Ty); - } + const StructType *STy = cast(V->getType()->getElementType()); + LTypes.insert(LTypes.end(), STy->subtype_begin(), STy->subtype_end()); + // Now, llvm.pch.types value is not required so remove it from the symbol // table. - GV->eraseFromParent(); + V->eraseFromParent(); } // GCC tree's uses LTypes vector's index to reach LLVM types. -// Create a string table to hold these LLVM types' names. This string -// table will be used to recreate LTypes vector after loading PCH. +// Create a global variable with struct type that contains each of these. void writeLLVMTypesStringTable() { - if (LTypes.empty()) return; - std::vector LTypesNames; - std::map < const Type *, std::string > TypeNameMap; - - // Collect Type Names in advance. - const TypeSymbolTable &ST = TheModule->getTypeSymbolTable(); - TypeSymbolTable::const_iterator TI = ST.begin(); - for (; TI != ST.end(); ++TI) { - TypeNameMap[TI->second] = TI->first; - } - - // Populate LTypesNames vector. - for (std::vector::iterator I = LTypes.begin(), - E = LTypes.end(); I != E; ++I) { - const Type *Ty = *I; - - // Give names to nameless types. - if (Ty && TypeNameMap[Ty].empty()) { - std::string NewName = - TheModule->getTypeSymbolTable().getUniqueName("llvm.fe.ty"); - TheModule->addTypeName(NewName, Ty); - TypeNameMap[*I] = NewName; - } - - const std::string &TypeName = TypeNameMap[*I]; - LTypesNames.push_back(ConstantArray::get(Context, TypeName, false)); - } - - // Create string table. - Constant *LTypesNameTable = - ConstantStruct::getAnon(Context, LTypesNames, false); - + const StructType *AggregateTy = StructType::get(Context, LTypes); + // Create variable to hold this string table. - GlobalVariable *GV = new GlobalVariable(*TheModule, - LTypesNameTable->getType(), true, - GlobalValue::ExternalLinkage, - LTypesNameTable, - "llvm.pch.types"); - GV->setUnnamedAddr(true); + (void)new GlobalVariable(*TheModule, AggregateTy, true, + GlobalValue::ExternalLinkage, + /*noinit*/0, "llvm.pch.types"); } //===----------------------------------------------------------------------===// From sabre at nondot.org Fri Jul 8 13:13:39 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 08 Jul 2011 18:13:39 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r134711 - in /llvm-gcc-4.2/trunk/gcc: llvm-types.cpp llvm.h Message-ID: <20110708181339.9CA882A6C12C@llvm.org> Author: lattner Date: Fri Jul 8 13:13:39 2011 New Revision: 134711 URL: http://llvm.org/viewvc/llvm-project?rev=134711&view=rev Log: eliminate a dead function. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp llvm-gcc-4.2/trunk/gcc/llvm.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=134711&r1=134710&r2=134711&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jul 8 13:13:39 2011 @@ -311,18 +311,6 @@ DECL_BIT_FIELD_TYPE(field_decl) : TREE_TYPE (field_decl); } -/// refine_type_to - Cause all users of the opaque type old_type to switch -/// to the more concrete type new_type. -void refine_type_to(tree old_type, tree new_type) -{ - const OpaqueType *OldTy = cast_or_null(GET_TYPE_LLVM(old_type)); - if (OldTy) { - const Type *NewTy = ConvertType (new_type); - const_cast(OldTy)->refineAbstractTypeTo(NewTy); - } -} - - //===----------------------------------------------------------------------===// // Abstract Type Refinement Helpers //===----------------------------------------------------------------------===// Modified: llvm-gcc-4.2/trunk/gcc/llvm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm.h?rev=134711&r1=134710&r2=134711&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm.h Fri Jul 8 13:13:39 2011 @@ -115,10 +115,6 @@ /* llvm_call_llvm_shutdown - Release LLVM global state. */ void llvm_call_llvm_shutdown(void); -/* refine_type_to - Cause all users of the opaque type old_type to switch - * to the more concrete type new_type. - */ -void refine_type_to (union tree_node*, union tree_node*); #endif /* ENABLE_LLVM */ #endif From grosbach at apple.com Fri Jul 8 13:15:12 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 18:15:12 -0000 Subject: [llvm-commits] [llvm] r134712 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMInstrInfo.td Message-ID: <20110708181513.0F0B82A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 13:15:12 2011 New Revision: 134712 URL: http://llvm.org/viewvc/llvm-project?rev=134712&view=rev Log: Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. TableGen'erated MC lowering pseudo-expansion. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134712&r1=134711&r2=134712&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 13:15:12 2011 @@ -1123,24 +1123,6 @@ } // Darwin call instructions are just normal call instructions with different // clobber semantics (they clobber R9). - case ARM::BLr9: - case ARM::BLr9_pred: - case ARM::BLXr9: - case ARM::BLXr9_pred: { - unsigned newOpc; - switch (Opc) { - default: assert(0); - case ARM::BLr9: newOpc = ARM::BL; break; - case ARM::BLr9_pred: newOpc = ARM::BL_pred; break; - case ARM::BLXr9: newOpc = ARM::BLX; break; - case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break; - } - MCInst TmpInst; - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(newOpc); - OutStreamer.EmitInstruction(TmpInst); - return; - } case ARM::BXr9_CALL: case ARM::BX_CALL: { { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134712&r1=134711&r2=134712&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 8 13:15:12 2011 @@ -1429,24 +1429,29 @@ // moved above / below calls. Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], Uses = [R7, SP] in { - def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops), + def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops), Size4Bytes, IIC_Br, - [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>; + [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>, + Requires<[IsARM, IsDarwin]>; - def BLr9_pred : ARMPseudoInst<(outs), - (ins bltarget:$func, pred:$p, variable_ops), + def BLr9_pred : ARMPseudoExpand<(outs), + (ins bl_target:$func, pred:$p, variable_ops), Size4Bytes, IIC_Br, - [(ARMcall_pred tglobaladdr:$func)]>, + [(ARMcall_pred tglobaladdr:$func)], + (BL_pred bl_target:$func, pred:$p)>, Requires<[IsARM, IsDarwin]>; // ARMv5T and above - def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops), + def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops), Size4Bytes, IIC_Br, - [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>; + [(ARMcall GPR:$func)], + (BLX GPR:$func)>, + Requires<[IsARM, HasV5T, IsDarwin]>; - def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops), - Size4Bytes, IIC_Br, - [(ARMcall_pred GPR:$func)]>, + def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops), + Size4Bytes, IIC_Br, + [(ARMcall_pred GPR:$func)], + (BLX_pred GPR:$func, pred:$p)>, Requires<[IsARM, HasV5T, IsDarwin]>; // ARMv4T From grosbach at apple.com Fri Jul 8 13:26:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 18:26:27 -0000 Subject: [llvm-commits] [llvm] r134714 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110708182627.A837A2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 13:26:27 2011 New Revision: 134714 URL: http://llvm.org/viewvc/llvm-project?rev=134714&view=rev Log: Shuffle productions around a bit. No functional change. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134714&r1=134713&r2=134714&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 8 13:26:27 2011 @@ -1466,6 +1466,65 @@ Requires<[IsARM, NoV4T, IsDarwin]>; } +let isBranch = 1, isTerminator = 1 in { + // FIXME: should be able to write a pattern for ARMBrcond, but can't use + // a two-value operand where a dag node expects two operands. :( + def Bcc : ABI<0b1010, (outs), (ins br_target:$target), + IIC_Br, "b", "\t$target", + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { + bits<24> target; + let Inst{23-0} = target; + } + + let isBarrier = 1 in { + // B is "predicable" since it's just a Bcc with an 'always' condition. + let isPredicable = 1 in + // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly + // should be sufficient. + // FIXME: Is B really a Barrier? That doesn't seem right. + def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br, + [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; + + let isNotDuplicable = 1, isIndirectBranch = 1 in { + def BR_JTr : ARMPseudoInst<(outs), + (ins GPR:$target, i32imm:$jt, i32imm:$id), + SizeSpecial, IIC_Br, + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; + // FIXME: This shouldn't use the generic "addrmode2," but rather be split + // into i12 and rs suffixed versions. + def BR_JTm : ARMPseudoInst<(outs), + (ins addrmode2:$target, i32imm:$jt, i32imm:$id), + SizeSpecial, IIC_Br, + [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, + imm:$id)]>; + def BR_JTadd : ARMPseudoInst<(outs), + (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), + SizeSpecial, IIC_Br, + [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, + imm:$id)]>; + } // isNotDuplicable = 1, isIndirectBranch = 1 + } // isBarrier = 1 + +} + +// BLX (immediate) -- for disassembly only +def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary, + "blx\t$target", [/* pattern left blank */]>, + Requires<[IsARM, HasV5T]> { + let Inst{31-25} = 0b1111101; + bits<25> target; + let Inst{23-0} = target{24-1}; + let Inst{24} = target{0}; +} + +// Branch and Exchange Jazelle -- for disassembly only +def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", + [/* For disassembly only; pattern left blank */]> { + let Inst{23-20} = 0b0010; + //let Inst{19-8} = 0xfff; + let Inst{7-4} = 0b0010; +} + // Tail calls. // FIXME: The Thumb versions of these should live in ARMInstrThumb.td @@ -1522,64 +1581,9 @@ } } -let isBranch = 1, isTerminator = 1 in { - // FIXME: should be able to write a pattern for ARMBrcond, but can't use - // a two-value operand where a dag node expects two operands. :( - def Bcc : ABI<0b1010, (outs), (ins br_target:$target), - IIC_Br, "b", "\t$target", - [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { - bits<24> target; - let Inst{23-0} = target; - } - let isBarrier = 1 in { - // B is "predicable" since it's just a Bcc with an 'always' condition. - let isPredicable = 1 in - // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly - // should be sufficient. - // FIXME: Is B really a Barrier? That doesn't seem right. - def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br, - [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; - let isNotDuplicable = 1, isIndirectBranch = 1 in { - def BR_JTr : ARMPseudoInst<(outs), - (ins GPR:$target, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, - [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; - // FIXME: This shouldn't use the generic "addrmode2," but rather be split - // into i12 and rs suffixed versions. - def BR_JTm : ARMPseudoInst<(outs), - (ins addrmode2:$target, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, - [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, - imm:$id)]>; - def BR_JTadd : ARMPseudoInst<(outs), - (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, - [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, - imm:$id)]>; - } // isNotDuplicable = 1, isIndirectBranch = 1 - } // isBarrier = 1 - -} - -// BLX (immediate) -- for disassembly only -def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary, - "blx\t$target", [/* pattern left blank */]>, - Requires<[IsARM, HasV5T]> { - let Inst{31-25} = 0b1111101; - bits<25> target; - let Inst{23-0} = target{24-1}; - let Inst{24} = target{0}; -} -// Branch and Exchange Jazelle -- for disassembly only -def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", - [/* For disassembly only; pattern left blank */]> { - let Inst{23-20} = 0b0010; - //let Inst{19-8} = 0xfff; - let Inst{7-4} = 0b0010; -} // Secure Monitor Call is a system instruction -- for disassembly only def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", From echristo at apple.com Fri Jul 8 13:47:51 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 08 Jul 2011 11:47:51 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r134710 - in /llvm-gcc-4.2/trunk/gcc: llvm-abi-default.cpp llvm-types.cpp In-Reply-To: <20110708181251.0B2712A6C12C@llvm.org> References: <20110708181251.0B2712A6C12C@llvm.org> Message-ID: The buildbots seem a bit unhappy with this? -eric On Jul 8, 2011, at 11:12 AM, Chris Lattner wrote: > Author: lattner > Date: Fri Jul 8 13:12:50 2011 > New Revision: 134710 > > URL: http://llvm.org/viewvc/llvm-project?rev=134710&view=rev > Log: > greatly simplify the llvm.pch.types logic, eliminating the need to apply names to all the types. > This also eliminates use of TypeSymbolTable.h which is going away. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=134710&r1=134709&r2=134710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Fri Jul 8 13:12:50 2011 > @@ -73,8 +73,8 @@ > // not include variable sized fields here. > std::vector Elts; > if (Ty->isVoidTy()) { > - // Handle void explicitly as an opaque type. > - const Type *OpTy = OpaqueType::get(getGlobalContext()); > + // Handle void explicitly as a {} type. > + const Type *OpTy = StructType::get(getGlobalContext()); > C.HandleScalarArgument(OpTy, type); > ScalarElts.push_back(OpTy); > } else if (isPassedByInvisibleReference(type)) { // variable size -> by-ref. > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=134710&r1=134709&r2=134710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jul 8 13:12:50 2011 > @@ -29,7 +29,6 @@ > #include "llvm/Constants.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > -#include "llvm/TypeSymbolTable.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetMachine.h" > #include "llvm/Assembly/Writer.h" > @@ -122,94 +121,44 @@ > > // Erase type from LTypes vector > static void llvmEraseLType(const Type *Ty) { > - > LTypesMapTy::iterator I = LTypesMap.find(Ty); > > if (I != LTypesMap.end()) { > // It is OK to clear this entry instead of removing this entry > // to avoid re-indexing of other entries. > - LTypes[ LTypesMap[Ty] - 1] = NULL; > + LTypes[LTypesMap[Ty] - 1] = NULL; > LTypesMap.erase(I); > } > } > > // Read LLVM Types string table > void readLLVMTypesStringTable() { > - > GlobalValue *V = TheModule->getNamedGlobal("llvm.pch.types"); > if (!V) > return; > > - // Value *GV = TheModule->getValueSymbolTable().lookup("llvm.pch.types"); > - GlobalVariable *GV = cast(V); > - ConstantStruct *LTypesNames = cast(GV->getOperand(0)); > - > - for (unsigned i = 0; i < LTypesNames->getNumOperands(); ++i) { > - const Type *Ty = NULL; > - > - if (ConstantArray *CA = > - dyn_cast(LTypesNames->getOperand(i))) { > - std::string Str = CA->getAsString(); > - Ty = TheModule->getTypeByName(Str); > - assert (Ty != NULL && "Invalid Type in LTypes string table"); > - } > - // If V is not a string then it is empty. Insert NULL to represent > - // empty entries. > - LTypes.push_back(Ty); > - } > + const StructType *STy = cast(V->getType()->getElementType()); > > + LTypes.insert(LTypes.end(), STy->subtype_begin(), STy->subtype_end()); > + > // Now, llvm.pch.types value is not required so remove it from the symbol > // table. > - GV->eraseFromParent(); > + V->eraseFromParent(); > } > > > // GCC tree's uses LTypes vector's index to reach LLVM types. > -// Create a string table to hold these LLVM types' names. This string > -// table will be used to recreate LTypes vector after loading PCH. > +// Create a global variable with struct type that contains each of these. > void writeLLVMTypesStringTable() { > - > if (LTypes.empty()) > return; > > - std::vector LTypesNames; > - std::map < const Type *, std::string > TypeNameMap; > - > - // Collect Type Names in advance. > - const TypeSymbolTable &ST = TheModule->getTypeSymbolTable(); > - TypeSymbolTable::const_iterator TI = ST.begin(); > - for (; TI != ST.end(); ++TI) { > - TypeNameMap[TI->second] = TI->first; > - } > - > - // Populate LTypesNames vector. > - for (std::vector::iterator I = LTypes.begin(), > - E = LTypes.end(); I != E; ++I) { > - const Type *Ty = *I; > - > - // Give names to nameless types. > - if (Ty && TypeNameMap[Ty].empty()) { > - std::string NewName = > - TheModule->getTypeSymbolTable().getUniqueName("llvm.fe.ty"); > - TheModule->addTypeName(NewName, Ty); > - TypeNameMap[*I] = NewName; > - } > - > - const std::string &TypeName = TypeNameMap[*I]; > - LTypesNames.push_back(ConstantArray::get(Context, TypeName, false)); > - } > - > - // Create string table. > - Constant *LTypesNameTable = > - ConstantStruct::getAnon(Context, LTypesNames, false); > - > + const StructType *AggregateTy = StructType::get(Context, LTypes); > + > // Create variable to hold this string table. > - GlobalVariable *GV = new GlobalVariable(*TheModule, > - LTypesNameTable->getType(), true, > - GlobalValue::ExternalLinkage, > - LTypesNameTable, > - "llvm.pch.types"); > - GV->setUnnamedAddr(true); > + (void)new GlobalVariable(*TheModule, AggregateTy, true, > + GlobalValue::ExternalLinkage, > + /*noinit*/0, "llvm.pch.types"); > } > > //===----------------------------------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jlerouge at apple.com Fri Jul 8 13:48:28 2011 From: jlerouge at apple.com (Julien Lerouge) Date: Fri, 08 Jul 2011 11:48:28 -0700 Subject: [llvm-commits] [PATCH] PR10305 / MSCV error LNK2019: unresolved external symbol ___umoddi3 Message-ID: <20110708184827.GA54225@pom.apple.com> Ok to commit ? This patch just adds _aullrem, _allrem & _allmul to X86ISelLowering.cpp for Windows target (MSVC). -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com -------------- next part -------------- Index: test/CodeGen/X86/allrem-moddi3.ll =================================================================== --- test/CodeGen/X86/allrem-moddi3.ll (revision 0) +++ test/CodeGen/X86/allrem-moddi3.ll (revision 0) @@ -0,0 +1,19 @@ +; Test that, for a 64 bit signed rem, a libcall to allrem is made on Windows +; unless we have libgcc. + +; RUN: llc < %s -mtriple i386-pc-win32 | FileCheck %s +; RUN: llc < %s -mtriple i386-pc-cygwin | FileCheck %s -check-prefix USEDIVDI +; RUN: llc < %s -mtriple i386-pc-mingw32 | FileCheck %s -check-prefix USEDIVDI +; PR10305 +; END. + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly { +entry: + %conv4 = sext i32 %argc to i64 + %div = srem i64 84, %conv4 + %conv7 = trunc i64 %div to i32 + ret i32 %conv7 +} + +; CHECK: allrem +; USEDIVDI: moddi3 Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp (revision 134718) +++ lib/Target/X86/X86ISelLowering.cpp (working copy) @@ -235,10 +235,16 @@ // Setup Windows compiler runtime calls. setLibcallName(RTLIB::SDIV_I64, "_alldiv"); setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); + setLibcallName(RTLIB::SREM_I64, "_allrem"); + setLibcallName(RTLIB::UREM_I64, "_aullrem"); + setLibcallName(RTLIB::MUL_I64, "_allmul"); setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); } From grosbach at apple.com Fri Jul 8 13:50:22 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 18:50:22 -0000 Subject: [llvm-commits] [llvm] r134719 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/call-tc.ll Message-ID: <20110708185022.4DFBC2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 13:50:22 2011 New Revision: 134719 URL: http://llvm.org/viewvc/llvm-project?rev=134719&view=rev Log: Use ARMPseudoExpand for ARM tail calls. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/call-tc.ll Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134719&r1=134718&r2=134719&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 13:50:22 2011 @@ -1801,20 +1801,6 @@ } // Tail jump branches are really just branch instructions with additional // code-gen attributes. Convert them to the canonical form here. - case ARM::TAILJMPd: - case ARM::TAILJMPdND: { - MCInst TmpInst, TmpInst2; - // Lower the instruction as-is to get the operands properly converted. - LowerARMMachineInstrToMCInst(MI, TmpInst2, *this); - TmpInst.setOpcode(ARM::Bcc); - TmpInst.addOperand(TmpInst2.getOperand(0)); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("TAILCALL"); - OutStreamer.EmitInstruction(TmpInst); - return; - } case ARM::tTAILJMPd: case ARM::tTAILJMPdND: { MCInst TmpInst, TmpInst2; @@ -1827,14 +1813,10 @@ OutStreamer.EmitInstruction(TmpInst); return; } - case ARM::TAILJMPrND: case ARM::tTAILJMPrND: - case ARM::TAILJMPr: case ARM::tTAILJMPr: { - unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND) - ? ARM::BX : ARM::tBX; MCInst TmpInst; - TmpInst.setOpcode(newOpc); + TmpInst.setOpcode(ARM::tBX); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134719&r1=134718&r2=134719&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 8 13:50:22 2011 @@ -1538,17 +1538,19 @@ def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), IIC_Br, []>, Requires<[IsDarwin]>; - def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsARM, IsDarwin]>; + def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (Bcc br_target:$dst, (ops 14, zero_reg))>, + Requires<[IsARM, IsDarwin]>; def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), Size4Bytes, IIC_Br, []>, Requires<[IsThumb, IsDarwin]>; - def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsARM, IsDarwin]>; + def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (BX GPR:$dst)>, + Requires<[IsARM, IsDarwin]>; def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, @@ -1564,17 +1566,19 @@ def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), IIC_Br, []>, Requires<[IsNotDarwin]>; - def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsARM, IsNotDarwin]>; + def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (Bcc br_target:$dst, (ops 14, zero_reg))>, + Requires<[IsARM, IsNotDarwin]>; def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), Size4Bytes, IIC_Br, []>, Requires<[IsThumb, IsNotDarwin]>; - def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsARM, IsNotDarwin]>; + def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (BX GPR:$dst)>, + Requires<[IsARM, IsNotDarwin]>; def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, []>, Requires<[IsThumb, IsNotDarwin]>; Modified: llvm/trunk/test/CodeGen/ARM/call-tc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=134719&r1=134718&r2=134719&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/call-tc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/call-tc.ll Fri Jul 8 13:50:22 2011 @@ -15,11 +15,11 @@ define void @t2() { ; CHECKV6: t2: -; CHECKV6: bx r0 @ TAILCALL +; CHECKV6: bx r0 ; CHECKT2D: t2: ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr -; CHECKT2D-NEXT: bx r0 @ TAILCALL +; CHECKT2D-NEXT: bx r0 %tmp = load i32 ()** @t ; [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; [#uses=0] ret void @@ -27,11 +27,11 @@ define void @t3() { ; CHECKV6: t3: -; CHECKV6: b _t2 @ TAILCALL +; CHECKV6: b _t2 ; CHECKELF: t3: -; CHECKELF: b t2(PLT) @ TAILCALL +; CHECKELF: b t2(PLT) ; CHECKT2D: t3: -; CHECKT2D: b.w _t2 @ TAILCALL +; CHECKT2D: b.w _t2 tail call void @t2( ) ; [#uses=0] ret void @@ -41,9 +41,9 @@ define double @t4(double %a) nounwind readonly ssp { entry: ; CHECKV6: t4: -; CHECKV6: b _sin @ TAILCALL +; CHECKV6: b _sin ; CHECKELF: t4: -; CHECKELF: b sin(PLT) @ TAILCALL +; CHECKELF: b sin(PLT) %0 = tail call double @sin(double %a) nounwind readonly ; [#uses=1] ret double %0 } @@ -51,9 +51,9 @@ define float @t5(float %a) nounwind readonly ssp { entry: ; CHECKV6: t5: -; CHECKV6: b _sinf @ TAILCALL +; CHECKV6: b _sinf ; CHECKELF: t5: -; CHECKELF: b sinf(PLT) @ TAILCALL +; CHECKELF: b sinf(PLT) %0 = tail call float @sinf(float %a) nounwind readonly ; [#uses=1] ret float %0 } @@ -65,9 +65,9 @@ define i32 @t6(i32 %a, i32 %b) nounwind readnone { entry: ; CHECKV6: t6: -; CHECKV6: b ___divsi3 @ TAILCALL +; CHECKV6: b ___divsi3 ; CHECKELF: t6: -; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL +; CHECKELF: b __aeabi_idiv(PLT) %0 = sdiv i32 %a, %b ret i32 %0 } From echristo at apple.com Fri Jul 8 13:50:42 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 08 Jul 2011 11:50:42 -0700 Subject: [llvm-commits] [PATCH] PR10305 / MSCV error LNK2019: unresolved external symbol ___umoddi3 In-Reply-To: <20110708184827.GA54225@pom.apple.com> References: <20110708184827.GA54225@pom.apple.com> Message-ID: On Jul 8, 2011, at 11:48 AM, Julien Lerouge wrote: > Ok to commit ? This patch just adds _aullrem, _allrem & _allmul to > X86ISelLowering.cpp for Windows target (MSVC). Yep. You have access? -eric From benny.kra at googlemail.com Fri Jul 8 14:32:06 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 08 Jul 2011 19:32:06 -0000 Subject: [llvm-commits] [llvm] r134720 - /llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Message-ID: <20110708193206.AA6902A6C12C@llvm.org> Author: d0k Date: Fri Jul 8 14:32:06 2011 New Revision: 134720 URL: http://llvm.org/viewvc/llvm-project?rev=134720&view=rev Log: Remove unused copy of UpdateInlinedAtInfo. Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=134720&r1=134719&r2=134720&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Fri Jul 8 14:32:06 2011 @@ -342,18 +342,6 @@ Ops.size(), TD); } -static DebugLoc -UpdateInlinedAtInfo(const DebugLoc &InsnDL, const DebugLoc &TheCallDL, - LLVMContext &Ctx) { - DebugLoc NewLoc = TheCallDL; - if (MDNode *IA = InsnDL.getInlinedAt(Ctx)) - NewLoc = UpdateInlinedAtInfo(DebugLoc::getFromDILocation(IA), TheCallDL, - Ctx); - - return DebugLoc::get(InsnDL.getLine(), InsnDL.getCol(), - InsnDL.getScope(Ctx), NewLoc.getAsMDNode(Ctx)); -} - /// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto, /// except that it does some simple constant prop and DCE on the fly. The /// effect of this is to copy significantly less code in cases where (for From evan.cheng at apple.com Fri Jul 8 14:33:14 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 19:33:14 -0000 Subject: [llvm-commits] [llvm] r134721 - in /llvm/trunk: include/llvm/Target/TargetAsmParser.h include/llvm/Target/TargetRegistry.h lib/MC/MCParser/TargetAsmParser.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20110708193314.F39482A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 14:33:14 2011 New Revision: 134721 URL: http://llvm.org/viewvc/llvm-project?rev=134721&view=rev Log: TargetAsmParser doesn't need reference to Target. Modified: llvm/trunk/include/llvm/Target/TargetAsmParser.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/include/llvm/Target/TargetAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmParser.h?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmParser.h Fri Jul 8 14:33:14 2011 @@ -15,7 +15,6 @@ namespace llvm { class MCStreamer; class StringRef; -class Target; class SMLoc; class AsmToken; class MCParsedAsmOperand; @@ -26,23 +25,19 @@ TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetAsmParser(const Target &); + TargetAsmParser(); - /// The Target that this machine was created for. - const Target &TheTarget; - - /// The current set of available features. + /// AvailableFeatures - The current set of available features. unsigned AvailableFeatures; public: virtual ~TargetAsmParser(); - const Target &getTarget() const { return TheTarget; } - unsigned getAvailableFeatures() const { return AvailableFeatures; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0; + virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) = 0; /// ParseInstruction - Parse one assembly instruction. /// Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Fri Jul 8 14:33:14 2011 @@ -79,7 +79,7 @@ const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT, + typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT, StringRef CPU, StringRef Features, MCAsmParser &P); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); @@ -300,10 +300,11 @@ /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, - StringRef Features, MCAsmParser &Parser) const { + StringRef Features, + MCAsmParser &Parser) const { if (!AsmParserCtorFn) return 0; - return AsmParserCtorFn(*this, Triple, CPU, Features, Parser); + return AsmParserCtorFn(Triple, CPU, Features, Parser); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -858,10 +859,9 @@ } private: - static TargetAsmParser *Allocator(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - MCAsmParser &P) { - return new AsmParserImpl(T, TT, CPU, FS, P); + static TargetAsmParser *Allocator(StringRef TT, StringRef CPU, + StringRef FS, MCAsmParser &P) { + return new AsmParserImpl(TT, CPU, FS, P); } }; Modified: llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp Fri Jul 8 14:33:14 2011 @@ -10,8 +10,8 @@ #include "llvm/Target/TargetAsmParser.h" using namespace llvm; -TargetAsmParser::TargetAsmParser(const Target &T) - : TheTarget(T), AvailableFeatures(0) +TargetAsmParser::TargetAsmParser() + : AvailableFeatures(0) { } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 8 14:33:14 2011 @@ -41,7 +41,7 @@ class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; - MCSubtargetInfo *STI; + const MCSubtargetInfo *STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -127,9 +127,8 @@ const SmallVectorImpl &); public: - ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) { + ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) + : TargetAsmParser(), Parser(_Parser) { STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); MCAsmParserExtension::Initialize(_Parser); Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Fri Jul 8 14:33:14 2011 @@ -63,9 +63,9 @@ public: - MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) {} + : TargetAsmParser(), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134721&r1=134720&r2=134721&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jul 8 14:33:14 2011 @@ -37,7 +37,7 @@ class X86ATTAsmParser : public TargetAsmParser { MCAsmParser &Parser; - MCSubtargetInfo *STI; + const MCSubtargetInfo *STI; private: MCAsmParser &getParser() const { return Parser; } @@ -77,9 +77,9 @@ /// } public: - X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &parser) - : TargetAsmParser(T), Parser(parser) { + : TargetAsmParser(), Parser(parser) { STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); // Initialize the set of available features. From sabre at nondot.org Fri Jul 8 14:58:16 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 08 Jul 2011 19:58:16 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r134723 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <20110708195817.0053A2A6C12C@llvm.org> Author: lattner Date: Fri Jul 8 14:58:16 2011 New Revision: 134723 URL: http://llvm.org/viewvc/llvm-project?rev=134723&view=rev Log: fix failure on llvm-gcc-x86_64-darwin10-cross-i686-linux buildbot, void and function types cannot be in a struct, so wrap them with a pointer. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=134723&r1=134722&r2=134723&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jul 8 14:58:16 2011 @@ -139,7 +139,11 @@ const StructType *STy = cast(V->getType()->getElementType()); - LTypes.insert(LTypes.end(), STy->subtype_begin(), STy->subtype_end()); + for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) + if (const PointerType *PTy = dyn_cast(STy->getElementType(i))) + LTypes.push_back(PTy->getElementType()); + else + LTypes.push_back(Type::getVoidTy(Context)); // Now, llvm.pch.types value is not required so remove it from the symbol // table. @@ -153,10 +157,18 @@ if (LTypes.empty()) return; - const StructType *AggregateTy = StructType::get(Context, LTypes); + // Convert the LTypes list to a list of pointers. + std::vector PTys; + for (unsigned i = 0, e = LTypes.size(); i != e; ++i) { + // Cannot form pointer to void. Use i8 as a sentinel. + if (LTypes[i]->isVoidTy()) + PTys.push_back(Type::getInt8Ty(Context)); + else + PTys.push_back(LTypes[i]->getPointerTo()); + } // Create variable to hold this string table. - (void)new GlobalVariable(*TheModule, AggregateTy, true, + (void)new GlobalVariable(*TheModule, StructType::get(Context, PTys), true, GlobalValue::ExternalLinkage, /*noinit*/0, "llvm.pch.types"); } From eli.friedman at gmail.com Fri Jul 8 15:03:59 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 13:03:59 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta Message-ID: On Thu, Jul 7, 2011 at 2:06 PM, Evan Cheng wrote: > Author: evancheng > Date: Thu Jul ?7 16:06:52 2011 > New Revision: 134641 > > URL: http://llvm.org/viewvc/llvm-project?rev=134641&view=rev > Log: > Add Mode64Bit feature and sink it down to MC layer. > > Modified: > ? ?llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > ? ?llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > ? ?llvm/trunk/lib/Target/X86/X86.td > ? ?llvm/trunk/lib/Target/X86/X86Subtarget.cpp > ? ?llvm/trunk/lib/Target/X86/X86Subtarget.h > ? ?llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > ? ?llvm/trunk/test/CodeGen/X86/2010-04-08-CoalescerBug.ll > ? ?llvm/trunk/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll > ? ?llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll > ? ?llvm/trunk/test/CodeGen/X86/memcpy.ll > ? ?llvm/trunk/test/CodeGen/X86/tlv-1.ll > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134641&r1=134640&r2=134641&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul ?7 16:06:52 2011 > @@ -16,6 +16,8 @@ > ?#include "llvm/MC/MCRegisterInfo.h" > ?#include "llvm/MC/MCSubtargetInfo.h" > ?#include "llvm/Target/TargetRegistry.h" > +#include "llvm/ADT/Triple.h" > +#include "llvm/Support/Host.h" > > ?#define GET_REGINFO_MC_DESC > ?#include "X86GenRegisterInfo.inc" > @@ -28,6 +30,104 @@ > > ?using namespace llvm; > > + > +std::string X86_MC::ParseX86Triple(StringRef TT) { > + ?Triple TheTriple(TT); > + ?if (TheTriple.getArch() == Triple::x86_64) > + ? ?return "+64bit-mode"; > + ?return ""; > +} > + > +/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the > +/// specified arguments. ?If we can't run cpuid on the host, return true. > +bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { > +#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) > + ?#if defined(__GNUC__) > + ? ?// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. > + ? ?asm ("movq\t%%rbx, %%rsi\n\t" > + ? ? ? ? "cpuid\n\t" > + ? ? ? ? "xchgq\t%%rbx, %%rsi\n\t" > + ? ? ? ? : "=a" (*rEAX), > + ? ? ? ? ? "=S" (*rEBX), > + ? ? ? ? ? "=c" (*rECX), > + ? ? ? ? ? "=d" (*rEDX) > + ? ? ? ? : ?"a" (value)); > + ? ?return false; > + ?#elif defined(_MSC_VER) > + ? ?int registers[4]; > + ? ?__cpuid(registers, value); > + ? ?*rEAX = registers[0]; > + ? ?*rEBX = registers[1]; > + ? ?*rECX = registers[2]; > + ? ?*rEDX = registers[3]; > + ? ?return false; > + ?#endif > +#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) > + ?#if defined(__GNUC__) > + ? ?asm ("movl\t%%ebx, %%esi\n\t" > + ? ? ? ? "cpuid\n\t" > + ? ? ? ? "xchgl\t%%ebx, %%esi\n\t" > + ? ? ? ? : "=a" (*rEAX), > + ? ? ? ? ? "=S" (*rEBX), > + ? ? ? ? ? "=c" (*rECX), > + ? ? ? ? ? "=d" (*rEDX) > + ? ? ? ? : ?"a" (value)); > + ? ?return false; > + ?#elif defined(_MSC_VER) > + ? ?__asm { > + ? ? ?mov ? eax,value > + ? ? ?cpuid > + ? ? ?mov ? esi,rEAX > + ? ? ?mov ? dword ptr [esi],eax > + ? ? ?mov ? esi,rEBX > + ? ? ?mov ? dword ptr [esi],ebx > + ? ? ?mov ? esi,rECX > + ? ? ?mov ? dword ptr [esi],ecx > + ? ? ?mov ? esi,rEDX > + ? ? ?mov ? dword ptr [esi],edx > + ? ?} > + ? ?return false; > + ?#endif > +#endif > + ?return true; > +} > + > +void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned &Model) { > + ?Family = (EAX >> 8) & 0xf; // Bits 8 - 11 > + ?Model ?= (EAX >> 4) & 0xf; // Bits 4 - 7 > + ?if (Family == 6 || Family == 0xf) { > + ? ?if (Family == 0xf) > + ? ? ?// Examine extended family ID if family ID is F. > + ? ? ?Family += (EAX >> 20) & 0xff; ? ?// Bits 20 - 27 > + ? ?// Examine extended model ID if family ID is 6 or F. > + ? ?Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 > + ?} > +} > + > +static bool hasX86_64() { > + ?// FIXME: Code duplication. See X86Subtarget::AutoDetectSubtargetFeatures. > + ?unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; > + ?union { > + ? ?unsigned u[3]; > + ? ?char ? ? c[12]; > + ?} text; > + > + ?if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) > + ? ?return false; > + > + ?bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; > + ?bool IsAMD ? = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; > + ?if (IsIntel || IsAMD) { > + ? ?X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); > + ? ?if ((EDX >> 29) & 0x1) > + ? ? ?return true; > + ?} > + > + ?return false; > +} > + > ?MCInstrInfo *createX86MCInstrInfo() { > ? MCInstrInfo *X = new MCInstrInfo(); > ? InitX86MCInstrInfo(X); > @@ -42,8 +142,24 @@ > > ?MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef FS) { > + ?std::string ArchFS = X86_MC::ParseX86Triple(TT); > + ?if (!FS.empty()) { > + ? ?if (!ArchFS.empty()) > + ? ? ?ArchFS = ArchFS + "," + FS.str(); > + ? ?else > + ? ? ?ArchFS = FS; > + ?} > + > + ?std::string CPUName = CPU; > + ?if (CPUName.empty()) > + ? ?CPUName = sys::getHostCPUName(); > + > + ?if (ArchFS.empty() && CPUName.empty() && hasX86_64()) > + ? ?// Auto-detect if host is 64-bit capable, it's the default if true. > + ? ?ArchFS = "+64bit-mode"; > + > ? MCSubtargetInfo *X = new MCSubtargetInfo(); > - ?InitX86MCSubtargetInfo(X, CPU, FS); > + ?InitX86MCSubtargetInfo(X, CPU, ArchFS); > ? return X; > ?} > > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134641&r1=134640&r2=134641&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul ?7 16:06:52 2011 > @@ -14,10 +14,24 @@ > ?#ifndef X86MCTARGETDESC_H > ?#define X86MCTARGETDESC_H > > +#include > + > ?namespace llvm { > ?class Target; > +class StringRef; > > ?extern Target TheX86_32Target, TheX86_64Target; > + > +namespace X86_MC { > + ?std::string ParseX86Triple(StringRef TT); > + > + ?/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in > + ?/// the specified arguments. ?If we can't run cpuid on the host, return true. > + ?bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, > + ? ? ? ? ? ? ? ? ? ? ? unsigned *rEBX, unsigned *rECX, unsigned *rEDX); > + > + ?void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); > +} > ?} // End llvm namespace > > ?// Defines symbolic names for X86 registers. ?This defines a mapping from > > Modified: llvm/trunk/lib/Target/X86/X86.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=134641&r1=134640&r2=134641&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86.td (original) > +++ llvm/trunk/lib/Target/X86/X86.td Thu Jul ?7 16:06:52 2011 > @@ -17,6 +17,13 @@ > ?include "llvm/Target/Target.td" > > ?//===----------------------------------------------------------------------===// > +// X86 Subtarget state. > +// > + > +def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"64-bit mode (x86_64)">; > + > +//===----------------------------------------------------------------------===// > ?// X86 Subtarget features. > ?//===----------------------------------------------------------------------===// > > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134641&r1=134640&r2=134641&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul ?7 16:06:52 2011 > @@ -158,7 +158,7 @@ > ?/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls > ?/// to immediate address. > ?bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { > - ?if (Is64Bit) > + ?if (In64BitMode) > ? ? return false; > ? return isTargetELF() || TM.getRelocationModel() == Reloc::Static; > ?} > @@ -174,73 +174,6 @@ > ? return 200; > ?} > > -/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the > -/// specified arguments. ?If we can't run cpuid on the host, return true. > -static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { > -#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) > - ?#if defined(__GNUC__) > - ? ?// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. > - ? ?asm ("movq\t%%rbx, %%rsi\n\t" > - ? ? ? ? "cpuid\n\t" > - ? ? ? ? "xchgq\t%%rbx, %%rsi\n\t" > - ? ? ? ? : "=a" (*rEAX), > - ? ? ? ? ? "=S" (*rEBX), > - ? ? ? ? ? "=c" (*rECX), > - ? ? ? ? ? "=d" (*rEDX) > - ? ? ? ? : ?"a" (value)); > - ? ?return false; > - ?#elif defined(_MSC_VER) > - ? ?int registers[4]; > - ? ?__cpuid(registers, value); > - ? ?*rEAX = registers[0]; > - ? ?*rEBX = registers[1]; > - ? ?*rECX = registers[2]; > - ? ?*rEDX = registers[3]; > - ? ?return false; > - ?#endif > -#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) > - ?#if defined(__GNUC__) > - ? ?asm ("movl\t%%ebx, %%esi\n\t" > - ? ? ? ? "cpuid\n\t" > - ? ? ? ? "xchgl\t%%ebx, %%esi\n\t" > - ? ? ? ? : "=a" (*rEAX), > - ? ? ? ? ? "=S" (*rEBX), > - ? ? ? ? ? "=c" (*rECX), > - ? ? ? ? ? "=d" (*rEDX) > - ? ? ? ? : ?"a" (value)); > - ? ?return false; > - ?#elif defined(_MSC_VER) > - ? ?__asm { > - ? ? ?mov ? eax,value > - ? ? ?cpuid > - ? ? ?mov ? esi,rEAX > - ? ? ?mov ? dword ptr [esi],eax > - ? ? ?mov ? esi,rEBX > - ? ? ?mov ? dword ptr [esi],ebx > - ? ? ?mov ? esi,rECX > - ? ? ?mov ? dword ptr [esi],ecx > - ? ? ?mov ? esi,rEDX > - ? ? ?mov ? dword ptr [esi],edx > - ? ?} > - ? ?return false; > - ?#endif > -#endif > - ?return true; > -} > - > -static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { > - ?Family = (EAX >> 8) & 0xf; // Bits 8 - 11 > - ?Model ?= (EAX >> 4) & 0xf; // Bits 4 - 7 > - ?if (Family == 6 || Family == 0xf) { > - ? ?if (Family == 0xf) > - ? ? ?// Examine extended family ID if family ID is F. > - ? ? ?Family += (EAX >> 20) & 0xff; ? ?// Bits 20 - 27 > - ? ?// Examine extended model ID if family ID is 6 or F. > - ? ?Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 > - ?} > -} > - > ?void X86Subtarget::AutoDetectSubtargetFeatures() { > ? unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; > ? union { > @@ -248,10 +181,10 @@ > ? ? char ? ? c[12]; > ? } text; > > - ?if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) > + ?if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) > ? ? return; > > - ?GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); > + ?X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); > > ? if ((EDX >> 15) & 1) HasCMov = true; > ? if ((EDX >> 23) & 1) X86SSELevel = MMX; > @@ -276,13 +209,13 @@ > ? ? // Determine if bit test memory instructions are slow. > ? ? unsigned Family = 0; > ? ? unsigned Model ?= 0; > - ? ?DetectFamilyModel(EAX, Family, Model); > + ? ?X86_MC::DetectFamilyModel(EAX, Family, Model); > ? ? IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13); > ? ? // If it's Nehalem, unaligned memory access is fast. > ? ? if (Family == 15 && Model == 26) > ? ? ? IsUAMemFast = true; > > - ? ?GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); > + ? ?X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); > ? ? HasX86_64 = (EDX >> 29) & 0x1; > ? ? HasSSE4A = IsAMD && ((ECX >> 6) & 0x1); > ? ? HasFMA4 = IsAMD && ((ECX >> 16) & 0x1); > @@ -291,7 +224,7 @@ > > ?X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, > ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS, > - ? ? ? ? ? ? ? ? ? ? ? ? ? bool is64Bit, unsigned StackAlignOverride) > + ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned StackAlignOverride) > ? : X86GenSubtargetInfo(TT, CPU, FS) > ? , PICStyle(PICStyles::None) > ? , X86SSELevel(NoMMXSSE) > @@ -312,15 +245,26 @@ > ? // FIXME: this is a known good value for Yonah. How about others? > ? , MaxInlineSizeThreshold(128) > ? , TargetTriple(TT) > - ?, Is64Bit(is64Bit) { > + ?, In64BitMode(false) { > + ?// Insert the architecture feature derived from the target triple into the > + ?// feature string. This is important for setting features that are implied > + ?// based on the architecture version. > + ?std::string ArchFS = X86_MC::ParseX86Triple(TT); > + ?if (!FS.empty()) { > + ? ?if (!ArchFS.empty()) > + ? ? ?ArchFS = ArchFS + "," + FS; > + ? ?else > + ? ? ?ArchFS = FS; > + ?} > + > + ?std::string CPUName = CPU; > + ?if (CPUName.empty()) > + ? ?CPUName = sys::getHostCPUName(); > > ? // Determine default and user specified characteristics > - ?if (!CPU.empty() || !FS.empty()) { > + ?if (!CPUName.empty() || !ArchFS.empty()) { > ? ? // If feature string is not empty, parse features string. > - ? ?std::string CPUName = CPU; > - ? ?if (CPUName.empty()) > - ? ? ?CPUName = sys::getHostCPUName(); > - ? ?ParseSubtargetFeatures(CPUName, FS); > + ? ?ParseSubtargetFeatures(CPUName, ArchFS); > ? ? // All X86-64 CPUs also have SSE2, however user might request no SSE via > ? ? // -mattr, so don't force SSELevel here. > ? ? if (HasAVX) > @@ -328,14 +272,19 @@ > ? } else { > ? ? // Otherwise, use CPUID to auto-detect feature set. > ? ? AutoDetectSubtargetFeatures(); > + > + ? ?// If CPU is 64-bit capable, default to 64-bit mode if not specified. > + ? ?In64BitMode = HasX86_64; > + > ? ? // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. > - ? ?if (Is64Bit && !HasAVX && X86SSELevel < SSE2) > + ? ?if (In64BitMode && !HasAVX && X86SSELevel < SSE2) > ? ? ? X86SSELevel = SSE2; > ? } > > ? // If requesting codegen for X86-64, make sure that 64-bit features > ? // are enabled. > - ?if (Is64Bit) { > + ?// FIXME: Remove this feature since it's not actually being used. > + ?if (In64BitMode) { > ? ? HasX86_64 = true; > > ? ? // All 64-bit cpus have cmov support. > @@ -345,7 +294,7 @@ > ? DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel > ? ? ? ? ? ? ? ?<< ", 3DNowLevel " << X863DNowLevel > ? ? ? ? ? ? ? ?<< ", 64bit " << HasX86_64 << "\n"); > - ?assert((!Is64Bit || HasX86_64) && > + ?assert((!In64BitMode || HasX86_64) && > ? ? ? ? ?"64-bit code requested on a subtarget that doesn't support it!"); > > ? // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both > @@ -353,6 +302,6 @@ > ? if (StackAlignOverride) > ? ? stackAlignment = StackAlignOverride; > ? else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() || > - ? ? ? ? ? isTargetSolaris() || Is64Bit) > + ? ? ? ? ? isTargetSolaris() || In64BitMode) > ? ? stackAlignment = 16; > ?} The bit of this change in X86Subtarget.cpp appears to break tests anywhere that sys::getHostCPUName doesn't return the name of a known 64-bit-capable x86 CPU (ARM, older x86 CPUs, very new x86 CPUS). Please fix or revert. -Eli From eli.friedman at gmail.com Fri Jul 8 15:07:05 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 08 Jul 2011 20:07:05 -0000 Subject: [llvm-commits] [llvm] r134725 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20110708200705.607352A6C12C@llvm.org> Author: efriedma Date: Fri Jul 8 15:07:05 2011 New Revision: 134725 URL: http://llvm.org/viewvc/llvm-project?rev=134725&view=rev Log: Fix dangling pointer. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134725&r1=134724&r2=134725&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Fri Jul 8 15:07:05 2011 @@ -1153,7 +1153,7 @@ assert(FeatureNo < 32 && "Too many subtarget features!"); } - StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); + std::string CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); // Parse the instructions; we need to do this first so that we can gather the // singleton register classes. From clattner at apple.com Fri Jul 8 15:08:13 2011 From: clattner at apple.com (Chris Lattner) Date: Fri, 08 Jul 2011 13:08:13 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r134710 - in /llvm-gcc-4.2/trunk/gcc: llvm-abi-default.cpp llvm-types.cpp In-Reply-To: References: <20110708181251.0B2712A6C12C@llvm.org> Message-ID: On Jul 8, 2011, at 11:47 AM, Eric Christopher wrote: > The buildbots seem a bit unhappy with this? I see one failure on llvm-gcc-x86_64-darwin10-cross-i686-linux which should be fixed with a follow-on patch, are there other failures? -Chris > > -eric > > On Jul 8, 2011, at 11:12 AM, Chris Lattner wrote: > >> Author: lattner >> Date: Fri Jul 8 13:12:50 2011 >> New Revision: 134710 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134710&view=rev >> Log: >> greatly simplify the llvm.pch.types logic, eliminating the need to apply names to all the types. >> This also eliminates use of TypeSymbolTable.h which is going away. >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp >> llvm-gcc-4.2/trunk/gcc/llvm-types.cpp >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=134710&r1=134709&r2=134710&view=diff >> ============================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Fri Jul 8 13:12:50 2011 >> @@ -73,8 +73,8 @@ >> // not include variable sized fields here. >> std::vector Elts; >> if (Ty->isVoidTy()) { >> - // Handle void explicitly as an opaque type. >> - const Type *OpTy = OpaqueType::get(getGlobalContext()); >> + // Handle void explicitly as a {} type. >> + const Type *OpTy = StructType::get(getGlobalContext()); >> C.HandleScalarArgument(OpTy, type); >> ScalarElts.push_back(OpTy); >> } else if (isPassedByInvisibleReference(type)) { // variable size -> by-ref. >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=134710&r1=134709&r2=134710&view=diff >> ============================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jul 8 13:12:50 2011 >> @@ -29,7 +29,6 @@ >> #include "llvm/Constants.h" >> #include "llvm/DerivedTypes.h" >> #include "llvm/Module.h" >> -#include "llvm/TypeSymbolTable.h" >> #include "llvm/Target/TargetData.h" >> #include "llvm/Target/TargetMachine.h" >> #include "llvm/Assembly/Writer.h" >> @@ -122,94 +121,44 @@ >> >> // Erase type from LTypes vector >> static void llvmEraseLType(const Type *Ty) { >> - >> LTypesMapTy::iterator I = LTypesMap.find(Ty); >> >> if (I != LTypesMap.end()) { >> // It is OK to clear this entry instead of removing this entry >> // to avoid re-indexing of other entries. >> - LTypes[ LTypesMap[Ty] - 1] = NULL; >> + LTypes[LTypesMap[Ty] - 1] = NULL; >> LTypesMap.erase(I); >> } >> } >> >> // Read LLVM Types string table >> void readLLVMTypesStringTable() { >> - >> GlobalValue *V = TheModule->getNamedGlobal("llvm.pch.types"); >> if (!V) >> return; >> >> - // Value *GV = TheModule->getValueSymbolTable().lookup("llvm.pch.types"); >> - GlobalVariable *GV = cast(V); >> - ConstantStruct *LTypesNames = cast(GV->getOperand(0)); >> - >> - for (unsigned i = 0; i < LTypesNames->getNumOperands(); ++i) { >> - const Type *Ty = NULL; >> - >> - if (ConstantArray *CA = >> - dyn_cast(LTypesNames->getOperand(i))) { >> - std::string Str = CA->getAsString(); >> - Ty = TheModule->getTypeByName(Str); >> - assert (Ty != NULL && "Invalid Type in LTypes string table"); >> - } >> - // If V is not a string then it is empty. Insert NULL to represent >> - // empty entries. >> - LTypes.push_back(Ty); >> - } >> + const StructType *STy = cast(V->getType()->getElementType()); >> >> + LTypes.insert(LTypes.end(), STy->subtype_begin(), STy->subtype_end()); >> + >> // Now, llvm.pch.types value is not required so remove it from the symbol >> // table. >> - GV->eraseFromParent(); >> + V->eraseFromParent(); >> } >> >> >> // GCC tree's uses LTypes vector's index to reach LLVM types. >> -// Create a string table to hold these LLVM types' names. This string >> -// table will be used to recreate LTypes vector after loading PCH. >> +// Create a global variable with struct type that contains each of these. >> void writeLLVMTypesStringTable() { >> - >> if (LTypes.empty()) >> return; >> >> - std::vector LTypesNames; >> - std::map < const Type *, std::string > TypeNameMap; >> - >> - // Collect Type Names in advance. >> - const TypeSymbolTable &ST = TheModule->getTypeSymbolTable(); >> - TypeSymbolTable::const_iterator TI = ST.begin(); >> - for (; TI != ST.end(); ++TI) { >> - TypeNameMap[TI->second] = TI->first; >> - } >> - >> - // Populate LTypesNames vector. >> - for (std::vector::iterator I = LTypes.begin(), >> - E = LTypes.end(); I != E; ++I) { >> - const Type *Ty = *I; >> - >> - // Give names to nameless types. >> - if (Ty && TypeNameMap[Ty].empty()) { >> - std::string NewName = >> - TheModule->getTypeSymbolTable().getUniqueName("llvm.fe.ty"); >> - TheModule->addTypeName(NewName, Ty); >> - TypeNameMap[*I] = NewName; >> - } >> - >> - const std::string &TypeName = TypeNameMap[*I]; >> - LTypesNames.push_back(ConstantArray::get(Context, TypeName, false)); >> - } >> - >> - // Create string table. >> - Constant *LTypesNameTable = >> - ConstantStruct::getAnon(Context, LTypesNames, false); >> - >> + const StructType *AggregateTy = StructType::get(Context, LTypes); >> + >> // Create variable to hold this string table. >> - GlobalVariable *GV = new GlobalVariable(*TheModule, >> - LTypesNameTable->getType(), true, >> - GlobalValue::ExternalLinkage, >> - LTypesNameTable, >> - "llvm.pch.types"); >> - GV->setUnnamedAddr(true); >> + (void)new GlobalVariable(*TheModule, AggregateTy, true, >> + GlobalValue::ExternalLinkage, >> + /*noinit*/0, "llvm.pch.types"); >> } >> >> //===----------------------------------------------------------------------===// >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Fri Jul 8 15:13:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 20:13:35 -0000 Subject: [llvm-commits] [llvm] r134727 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td Message-ID: <20110708201335.9FC3B2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 15:13:35 2011 New Revision: 134727 URL: http://llvm.org/viewvc/llvm-project?rev=134727&view=rev Log: Move Thumb tail call pseudos to Thumb.td file. Fix a FIXME. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134727&r1=134726&r2=134727&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 8 15:13:35 2011 @@ -1527,7 +1527,6 @@ // Tail calls. -// FIXME: The Thumb versions of these should live in ARMInstrThumb.td let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { // Darwin versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], @@ -1543,18 +1542,11 @@ (Bcc br_target:$dst, (ops 14, zero_reg))>, Requires<[IsARM, IsDarwin]>; - def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsDarwin]>; - def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, [], (BX GPR:$dst)>, Requires<[IsARM, IsDarwin]>; - def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsDarwin]>; } // Non-Darwin versions (the difference is R9). @@ -1571,17 +1563,10 @@ (Bcc br_target:$dst, (ops 14, zero_reg))>, Requires<[IsARM, IsNotDarwin]>; - def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsNotDarwin]>; - def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, [], (BX GPR:$dst)>, Requires<[IsARM, IsNotDarwin]>; - def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsNotDarwin]>; } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134727&r1=134726&r2=134727&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 15:13:35 2011 @@ -571,6 +571,31 @@ } } +// Tail calls +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { + // Darwin versions. + let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], + Uses = [SP] in { + def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), + Size4Bytes, IIC_Br, + []>, Requires<[IsThumb, IsDarwin]>; + def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, + []>, Requires<[IsThumb, IsDarwin]>; + } + // Non-Darwin versions (the difference is R9). + let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], + Uses = [SP] in { + def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), + Size4Bytes, IIC_Br, + []>, Requires<[IsThumb, IsNotDarwin]>; + def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, + []>, Requires<[IsThumb, IsNotDarwin]>; + } +} + + // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only // A8.6.16 B: Encoding T1 // If Inst{11-8} == 0b1111 then SEE SVC From grosbach at apple.com Fri Jul 8 15:18:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 20:18:11 -0000 Subject: [llvm-commits] [llvm] r134729 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110708201811.6726A2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 15:18:11 2011 New Revision: 134729 URL: http://llvm.org/viewvc/llvm-project?rev=134729&view=rev Log: Add more info to FIXME. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134729&r1=134728&r2=134729&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 8 15:18:11 2011 @@ -1637,7 +1637,11 @@ return false; // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: - // emitEpilogue is not ready for them. + // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as + // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation + // support in the assembler and linker to be used. This would need to be + // fixed to fully support tail calls in Thumb1. + // // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take // LR. This means if we need to reload LR, it takes an extra instructions, // which outweighs the value of the tail call; but here we don't know yet From benny.kra at googlemail.com Fri Jul 8 15:18:13 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 08 Jul 2011 20:18:13 -0000 Subject: [llvm-commits] [llvm] r134730 - /llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Message-ID: <20110708201813.7DB922A6C12D@llvm.org> Author: d0k Date: Fri Jul 8 15:18:13 2011 New Revision: 134730 URL: http://llvm.org/viewvc/llvm-project?rev=134730&view=rev Log: Silence compiler warning. Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=134730&r1=134729&r2=134730&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Fri Jul 8 15:18:13 2011 @@ -15,6 +15,7 @@ #include "MipsInstPrinter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" using namespace llvm; @@ -57,6 +58,7 @@ case FCOND_NGT: case FCOND_GT: return "ngt"; } + llvm_unreachable("Impossible condition code!"); } StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const { From grosbach at apple.com Fri Jul 8 15:32:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 20:32:21 -0000 Subject: [llvm-commits] [llvm] r134732 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMInstrThumb.td ARMInstrThumb2.td Message-ID: <20110708203221.BD9D02A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 15:32:21 2011 New Revision: 134732 URL: http://llvm.org/viewvc/llvm-project?rev=134732&view=rev Log: Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134732&r1=134731&r2=134732&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 15:32:21 2011 @@ -1801,18 +1801,6 @@ } // Tail jump branches are really just branch instructions with additional // code-gen attributes. Convert them to the canonical form here. - case ARM::tTAILJMPd: - case ARM::tTAILJMPdND: { - MCInst TmpInst, TmpInst2; - LowerARMMachineInstrToMCInst(MI, TmpInst2, *this); - // The Darwin toolchain doesn't support tail call relocations of 16-bit - // branches. - TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB); - TmpInst.addOperand(TmpInst2.getOperand(0)); - OutStreamer.AddComment("TAILCALL"); - OutStreamer.EmitInstruction(TmpInst); - return; - } case ARM::tTAILJMPrND: case ARM::tTAILJMPr: { MCInst TmpInst; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134732&r1=134731&r2=134732&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 15:32:21 2011 @@ -576,9 +576,8 @@ // Darwin versions. let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { - def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsDarwin]>; + // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls + // on Darwin), so it's in ARMInstrThumb2.td. def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, []>, Requires<[IsThumb, IsDarwin]>; @@ -586,9 +585,10 @@ // Non-Darwin versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { - def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsNotDarwin]>; + def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (tB t_brtarget:$dst)>, + Requires<[IsThumb, IsNotDarwin]>; def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), Size4Bytes, IIC_Br, []>, Requires<[IsThumb, IsNotDarwin]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134732&r1=134731&r2=134732&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul 8 15:32:21 2011 @@ -3062,6 +3062,17 @@ let Inst{10-0} = target{11-1}; } +// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so +// it goes here. +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { + // Darwin version. + let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], + Uses = [SP] in + def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (t2B uncondbrtarget:$dst)>, + Requires<[IsThumb2, IsDarwin]>; +} // IT block let Defs = [ITSTATE] in From echristo at apple.com Fri Jul 8 15:37:08 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 08 Jul 2011 13:37:08 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r134710 - in /llvm-gcc-4.2/trunk/gcc: llvm-abi-default.cpp llvm-types.cpp In-Reply-To: References: <20110708181251.0B2712A6C12C@llvm.org> Message-ID: On Jul 8, 2011, at 1:08 PM, Chris Lattner wrote: > > On Jul 8, 2011, at 11:47 AM, Eric Christopher wrote: > >> The buildbots seem a bit unhappy with this? > > I see one failure on llvm-gcc-x86_64-darwin10-cross-i686-linux which should be fixed with a follow-on patch, are there other failures? Not as far as I know :) -eric From grosbach at apple.com Fri Jul 8 15:39:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 20:39:19 -0000 Subject: [llvm-commits] [llvm] r134734 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMInstrThumb.td Message-ID: <20110708203919.3740E2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 15:39:19 2011 New Revision: 134734 URL: http://llvm.org/viewvc/llvm-project?rev=134734&view=rev Log: Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134734&r1=134733&r2=134734&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 15:39:19 2011 @@ -1799,20 +1799,6 @@ } return; } - // Tail jump branches are really just branch instructions with additional - // code-gen attributes. Convert them to the canonical form here. - case ARM::tTAILJMPrND: - case ARM::tTAILJMPr: { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tBX); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("TAILCALL"); - OutStreamer.EmitInstruction(TmpInst); - return; - } } MCInst TmpInst; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134734&r1=134733&r2=134734&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 15:39:19 2011 @@ -578,9 +578,10 @@ Uses = [SP] in { // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls // on Darwin), so it's in ARMInstrThumb2.td. - def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsDarwin]>; + def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (tBX GPR:$dst, (ops 14, zero_reg))>, + Requires<[IsThumb, IsDarwin]>; } // Non-Darwin versions (the difference is R9). let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], @@ -589,9 +590,10 @@ Size4Bytes, IIC_Br, [], (tB t_brtarget:$dst)>, Requires<[IsThumb, IsNotDarwin]>; - def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, - []>, Requires<[IsThumb, IsNotDarwin]>; + def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), + Size4Bytes, IIC_Br, [], + (tBX GPR:$dst, (ops 14, zero_reg))>, + Requires<[IsThumb, IsNotDarwin]>; } } From stoklund at 2pi.dk Fri Jul 8 15:46:18 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 08 Jul 2011 20:46:18 -0000 Subject: [llvm-commits] [llvm] r134735 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/LiveIntervalUnion.cpp lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocGreedy.cpp lib/CodeGen/VirtRegMap.h test/CodeGen/ARM/lsr-unfolded-offset.ll test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll test/CodeGen/X86/divide-by-constant.ll test/CodeGen/X86/lsr-reuse-trunc.ll test/CodeGen/X86/peep-test-3.ll test/CodeGen/X86/sse3.ll Message-ID: <20110708204618.76A3D2A6C12C@llvm.org> Author: stoklund Date: Fri Jul 8 15:46:18 2011 New Revision: 134735 URL: http://llvm.org/viewvc/llvm-project?rev=134735&view=rev Log: Be more aggressive about following hints. RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/VirtRegMap.h llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll llvm/trunk/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll llvm/trunk/test/CodeGen/X86/divide-by-constant.ll llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll llvm/trunk/test/CodeGen/X86/peep-test-3.ll llvm/trunk/test/CodeGen/X86/sse3.ll Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Fri Jul 8 15:46:18 2011 @@ -225,6 +225,14 @@ return RegAllocHints[Reg]; } + /// getSimpleHint - Return the preferred register allocation hint, or 0 if a + /// standard simple hint (Type == 0) is not set. + unsigned getSimpleHint(unsigned Reg) const { + std::pair Hint = getRegAllocationHint(Reg); + return Hint.first ? 0 : Hint.second; + } + + //===--------------------------------------------------------------------===// // Physical Register Use Info //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Fri Jul 8 15:46:18 2011 @@ -244,7 +244,7 @@ // // For comments on how to speed it up, see Query::findIntersection(). unsigned LiveIntervalUnion::Query:: -collectInterferingVRegs(unsigned MaxInterferingRegs, float MaxWeight) { +collectInterferingVRegs(unsigned MaxInterferingRegs) { InterferenceResult IR = firstInterference(); LiveInterval::iterator VirtRegEnd = VirtReg->end(); LiveInterval *RecentInterferingVReg = NULL; @@ -287,10 +287,6 @@ RecentInterferingVReg = IR.LiveUnionI.value(); ++IR.LiveUnionI; - // Stop collecting when the max weight is exceeded. - if (RecentInterferingVReg->weight >= MaxWeight) - return InterferingVRegs.size(); - continue; } // VirtRegI may have advanced far beyond LiveUnionI, Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Fri Jul 8 15:46:18 2011 @@ -229,8 +229,7 @@ // Count the virtual registers in this union that interfere with this // query's live virtual register, up to maxInterferingRegs. - unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX, - float MaxWeight = HUGE_VALF); + unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX); // Was this virtual register visited during collectInterferingVRegs? bool isSeenInterference(LiveInterval *VReg) const; Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Jul 8 15:46:18 2011 @@ -133,6 +133,20 @@ } } + /// Cost of evicting interference. + struct EvictionCost { + unsigned BrokenHints; ///< Total number of broken hints. + float MaxWeight; ///< Maximum spill weight evicted. + + EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {} + + bool operator<(const EvictionCost &O) const { + if (BrokenHints != O.BrokenHints) + return BrokenHints < O.BrokenHints; + return MaxWeight < O.MaxWeight; + } + }; + // splitting state. std::auto_ptr SA; std::auto_ptr SE; @@ -197,8 +211,10 @@ void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&, SmallVectorImpl&); void calcGapWeights(unsigned, SmallVectorImpl&); - bool canEvict(LiveInterval &A, LiveInterval &B); - bool canEvictInterference(LiveInterval&, unsigned, float&); + bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); + bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&); + void evictInterference(LiveInterval&, unsigned, + SmallVectorImpl&); unsigned tryAssign(LiveInterval&, AllocationOrder&, SmallVectorImpl&); @@ -382,7 +398,21 @@ if (!PhysReg || Order.isHint(PhysReg)) return PhysReg; - // PhysReg is available. Try to evict interference from a cheaper alternative. + // PhysReg is available, but there may be a better choice. + + // If we missed a simple hint, try to cheaply evict interference from the + // preferred register. + if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) + if (Order.isHint(Hint)) { + DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); + EvictionCost MaxCost(1); + if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { + evictInterference(VirtReg, Hint, NewVRegs); + return Hint; + } + } + + // Try to evict interference from a cheaper alternative. unsigned Cost = TRI->getCostPerUse(PhysReg); // Most registers have 0 additional cost. @@ -400,23 +430,42 @@ // Interference eviction //===----------------------------------------------------------------------===// -/// canEvict - determine if A can evict the assigned live range B. The eviction -/// policy defined by this function together with the allocation order defined -/// by enqueue() decides which registers ultimately end up being split and -/// spilled. +/// shouldEvict - determine if A should evict the assigned live range B. The +/// eviction policy defined by this function together with the allocation order +/// defined by enqueue() decides which registers ultimately end up being split +/// and spilled. /// /// Cascade numbers are used to prevent infinite loops if this function is a /// cyclic relation. -bool RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) { +/// +/// @param A The live range to be assigned. +/// @param IsHint True when A is about to be assigned to its preferred +/// register. +/// @param B The live range to be evicted. +/// @param BreaksHint True when B is already assigned to its preferred register. +bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, + LiveInterval &B, bool BreaksHint) { + bool CanSplit = getStage(B) <= RS_Second; + + // Be fairly aggressive about following hints as long as the evictee can be + // split. + if (CanSplit && IsHint && !BreaksHint) + return true; + return A.weight > B.weight; } -/// canEvict - Return true if all interferences between VirtReg and PhysReg can -/// be evicted. -/// Return false if any interference is heavier than MaxWeight. -/// On return, set MaxWeight to the maximal spill weight of an interference. +/// canEvictInterference - Return true if all interferences between VirtReg and +/// PhysReg can be evicted. When OnlyCheap is set, don't do anything +/// +/// @param VirtReg Live range that is about to be assigned. +/// @param PhysReg Desired register for assignment. +/// @prarm IsHint True when PhysReg is VirtReg's preferred register. +/// @param MaxCost Only look for cheaper candidates and update with new cost +/// when returning true. +/// @returns True when interference can be evicted cheaper than MaxCost. bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, - float &MaxWeight) { + bool IsHint, EvictionCost &MaxCost) { // Find VirtReg's cascade number. This will be unassigned if VirtReg was never // involved in an eviction before. If a cascade number was assigned, deny // evicting anything with the same or a newer cascade number. This prevents @@ -428,11 +477,11 @@ if (!Cascade) Cascade = NextCascade; - float Weight = 0; + EvictionCost Cost; for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); // If there is 10 or more interferences, chances are one is heavier. - if (Q.collectInterferingVRegs(10, MaxWeight) >= 10) + if (Q.collectInterferingVRegs(10) >= 10) return false; // Check if any interfering live range is heavier than MaxWeight. @@ -440,19 +489,69 @@ LiveInterval *Intf = Q.interferingVRegs()[i - 1]; if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) return false; - if (Cascade <= ExtraRegInfo[Intf->reg].Cascade) + // Never evict spill products. They cannot split or spill. + if (getStage(*Intf) == RS_Spill) return false; - if (Intf->weight >= MaxWeight) + // Once a live range becomes small enough, it is urgent that we find a + // register for it. This is indicated by an infinite spill weight. These + // urgent live ranges get to evict almost anything. + bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); + // Only evict older cascades or live ranges without a cascade. + unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade; + if (Cascade <= IntfCascade) { + if (!Urgent) + return false; + // We permit breaking cascades for urgent evictions. It should be the + // last resort, though, so make it really expensive. + Cost.BrokenHints += 10; + } + // Would this break a satisfied hint? + bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); + // Update eviction cost. + Cost.BrokenHints += BreaksHint; + Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight); + // Abort if this would be too expensive. + if (!(Cost < MaxCost)) return false; - if (!canEvict(VirtReg, *Intf)) + // Finally, apply the eviction policy for non-urgent evictions. + if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) return false; - Weight = std::max(Weight, Intf->weight); } } - MaxWeight = Weight; + MaxCost = Cost; return true; } +/// evictInterference - Evict any interferring registers that prevent VirtReg +/// from being assigned to Physreg. This assumes that canEvictInterference +/// returned true. +void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, + SmallVectorImpl &NewVRegs) { + // Make sure that VirtReg has a cascade number, and assign that cascade + // number to every evicted register. These live ranges than then only be + // evicted by a newer cascade, preventing infinite loops. + unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; + if (!Cascade) + Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; + + DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) + << " interference: Cascade " << Cascade << '\n'); + for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { + LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); + assert(Q.seenAllInterferences() && "Didn't check all interfererences."); + for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) { + LiveInterval *Intf = Q.interferingVRegs()[i]; + unassign(*Intf, VRM->getPhys(Intf->reg)); + assert((ExtraRegInfo[Intf->reg].Cascade < Cascade || + VirtReg.isSpillable() < Intf->isSpillable()) && + "Cannot decrease cascade number, illegal eviction"); + ExtraRegInfo[Intf->reg].Cascade = Cascade; + ++NumEvicted; + NewVRegs.push_back(Intf); + } + } +} + /// tryEvict - Try to evict all interferences for a physreg. /// @param VirtReg Currently unassigned virtual register. /// @param Order Physregs to try. @@ -463,31 +562,37 @@ unsigned CostPerUseLimit) { NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled); - // Keep track of the lightest single interference seen so far. - float BestWeight = HUGE_VALF; + // Keep track of the cheapest interference seen so far. + EvictionCost BestCost(~0u); unsigned BestPhys = 0; + // When we are just looking for a reduced cost per use, don't break any + // hints, and only evict smaller spill weights. + if (CostPerUseLimit < ~0u) { + BestCost.BrokenHints = 0; + BestCost.MaxWeight = VirtReg.weight; + } + Order.rewind(); while (unsigned PhysReg = Order.next()) { if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit) continue; - // The first use of a register in a function has cost 1. - if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg)) - continue; - - float Weight = BestWeight; - if (!canEvictInterference(VirtReg, PhysReg, Weight)) - continue; + // The first use of a callee-saved register in a function has cost 1. + // Don't start using a CSR when the CostPerUseLimit is low. + if (CostPerUseLimit == 1) + if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) + if (!MRI->isPhysRegUsed(CSR)) { + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " + << PrintReg(CSR, TRI) << '\n'); + continue; + } - // This is an eviction candidate. - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " interference = " - << Weight << '\n'); - if (BestPhys && Weight >= BestWeight) + if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) continue; // Best so far. BestPhys = PhysReg; - BestWeight = Weight; + // Stop if the hint can be used. if (Order.isHint(PhysReg)) break; @@ -496,29 +601,7 @@ if (!BestPhys) return 0; - // We will evict interference. Make sure that VirtReg has a cascade number, - // and assign that cascade number to every evicted register. These live - // ranges than then only be evicted by a newer cascade, preventing infinite - // loops. - unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; - if (!Cascade) - Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; - - DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) - << " interference: Cascade " << Cascade << '\n'); - for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) { - LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); - assert(Q.seenAllInterferences() && "Didn't check all interfererences."); - for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) { - LiveInterval *Intf = Q.interferingVRegs()[i]; - unassign(*Intf, VRM->getPhys(Intf->reg)); - assert(ExtraRegInfo[Intf->reg].Cascade < Cascade && - "Cannot decrease cascade number, illegal eviction"); - ExtraRegInfo[Intf->reg].Cascade = Cascade; - ++NumEvicted; - NewVRegs.push_back(Intf); - } - } + evictInterference(VirtReg, BestPhys, NewVRegs); return BestPhys; } @@ -1552,7 +1635,7 @@ // If we couldn't allocate a register from spilling, there is probably some // invalid inline assembly. The base class wil report it. - if (Stage >= RS_Spill) + if (Stage >= RS_Spill || !VirtReg.isSpillable()) return ~0u; // Try splitting VirtReg or interferences. Modified: llvm/trunk/lib/CodeGen/VirtRegMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.h?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.h (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.h Fri Jul 8 15:46:18 2011 @@ -208,6 +208,11 @@ /// @brief returns the register allocation preference. unsigned getRegAllocPref(unsigned virtReg); + /// @brief returns true if VirtReg is assigned to its preferred physreg. + bool hasPreferredPhys(unsigned VirtReg) { + return getPhys(VirtReg) == getRegAllocPref(VirtReg); + } + /// @brief records virtReg is a split live interval from SReg. void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { Virt2SplitMap[virtReg] = SReg; Modified: llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-unfolded-offset.ll Fri Jul 8 15:46:18 2011 @@ -4,12 +4,13 @@ ; register pressure and therefore spilling. There is more room for improvement ; here. -; CHECK: sub sp, #{{32|24}} +; CHECK: sub sp, #{{32|28|24}} -; CHECK: ldr r{{.*}}, [sp, #4] -; CHECK-NEXT: ldr r{{.*}}, [sp, #16] -; CHECK-NEXT: ldr r{{.*}}, [sp, #12] -; CHECK-NEXT: adds +; CHECK: %for.inc +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: add target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.7.0" Modified: llvm/trunk/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll Fri Jul 8 15:46:18 2011 @@ -22,8 +22,11 @@ define void @t2() nounwind ssp { entry: ; CHECK: t2: -; CHECK: movl %eax, %ecx -; CHECK: %ecx = foo (%ecx, %eax) +; CHECK: movl +; CHECK: [[D2:%e.x]] = foo +; CHECK: ([[D2]], +; CHECK-NOT: [[D2]] +; CHECK: ) %b = alloca i32 ; [#uses=2] %a = alloca i32 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original) +++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Fri Jul 8 15:46:18 2011 @@ -40,7 +40,7 @@ %div = sdiv i16 %x, 33 ; [#uses=1] ret i16 %div ; CHECK: test4: -; CHECK: imull $1986, %eax, %eax +; CHECK: imull $1986, %eax, % } define i32 @test5(i32 %A) nounwind { Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Fri Jul 8 15:46:18 2011 @@ -5,8 +5,9 @@ ; stick with indexing here. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] -; CHECK: movaps -; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4) +; CHECK: cvtdq2ps +; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] +; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) ; CHECK: addq $4, %rax ; CHECK: cmpl %eax, (%{{rdx|r8}}) ; CHECK-NEXT: jg Modified: llvm/trunk/test/CodeGen/X86/peep-test-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peep-test-3.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/peep-test-3.ll (original) +++ llvm/trunk/test/CodeGen/X86/peep-test-3.ll Fri Jul 8 15:46:18 2011 @@ -9,7 +9,7 @@ %0 = ptrtoint float* %A to i32 ; [#uses=1] %1 = and i32 %0, 3 ; [#uses=1] %2 = xor i32 %IA, 1 ; [#uses=1] -; CHECK: orl %ecx, %edx +; CHECK: orl %e ; CHECK-NEXT: je %3 = or i32 %2, %1 ; [#uses=1] %4 = icmp eq i32 %3, 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/sse3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=134735&r1=134734&r2=134735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse3.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse3.ll Fri Jul 8 15:46:18 2011 @@ -169,10 +169,10 @@ ; X64: t10: ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax ; X64: unpcklpd [[X1:%xmm[0-9]+]] -; X64: pshuflw $8, [[X1]], [[X1]] -; X64: pinsrw $2, %eax, [[X1]] +; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] +; X64: pinsrw $2, %eax, [[X2]] ; X64: pextrw $6, [[X0]], %eax -; X64: pinsrw $3, %eax, [[X1]] +; X64: pinsrw $3, %eax, [[X2]] } From grosbach at apple.com Fri Jul 8 16:04:06 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 21:04:06 -0000 Subject: [llvm-commits] [llvm] r134737 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110708210406.1674B2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 16:04:05 2011 New Revision: 134737 URL: http://llvm.org/viewvc/llvm-project?rev=134737&view=rev Log: Shuffle productions around a bit. No functional change. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134737&r1=134736&r2=134737&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 16:04:05 2011 @@ -361,27 +361,6 @@ // Control Flow Instructions. // -let isReturn = 1, isTerminator = 1, isBarrier = 1 in { - def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", - [(ARMretflag)]>, - T1Special<{1,1,0,?}> { - // A6.2.3 & A8.6.25 - let Inst{6-3} = 0b1110; // Rm = lr - let Inst{2-0} = 0b000; - } - - // Alternative return instruction used by vararg functions. - def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), - IIC_Br, "bx\t$Rm", - []>, - T1Special<{1,1,0,?}> { - // A6.2.3 & A8.6.25 - bits<4> Rm; - let Inst{6-3} = Rm; - let Inst{2-0} = 0b000; - } -} - // Indirect branches let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, @@ -405,6 +384,27 @@ } } +let isReturn = 1, isTerminator = 1, isBarrier = 1 in { + def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", + [(ARMretflag)]>, + T1Special<{1,1,0,?}> { + // A6.2.3 & A8.6.25 + let Inst{6-3} = 0b1110; // Rm = lr + let Inst{2-0} = 0b000; + } + + // Alternative return instruction used by vararg functions. + def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), + IIC_Br, "bx\t$Rm", + []>, + T1Special<{1,1,0,?}> { + // A6.2.3 & A8.6.25 + bits<4> Rm; + let Inst{6-3} = Rm; + let Inst{2-0} = 0b000; + } +} + // All calls clobber the non-callee saved registers. SP is marked as a use to // prevent stack-pointer assignments that appear immediately before calls from // potentially appearing dead. From benny.kra at googlemail.com Fri Jul 8 16:06:23 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 08 Jul 2011 21:06:23 -0000 Subject: [llvm-commits] [llvm] r134738 - in /llvm/trunk/lib/Target: ARM/AsmParser/ARMAsmParser.cpp X86/AsmParser/X86AsmParser.cpp Message-ID: <20110708210624.03CE62A6C12C@llvm.org> Author: d0k Date: Fri Jul 8 16:06:23 2011 New Revision: 134738 URL: http://llvm.org/viewvc/llvm-project?rev=134738&view=rev Log: Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo. Found by valgrind. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134738&r1=134737&r2=134738&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 8 16:06:23 2011 @@ -25,6 +25,7 @@ #include "llvm/Target/TargetAsmParser.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -41,7 +42,7 @@ class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; - const MCSubtargetInfo *STI; + OwningPtr STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -128,8 +129,8 @@ public: ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) - : TargetAsmParser(), Parser(_Parser) { - STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); + : TargetAsmParser(), Parser(_Parser), + STI(ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS)) { MCAsmParserExtension::Initialize(_Parser); // Initialize the set of available features. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134738&r1=134737&r2=134738&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jul 8 16:06:23 2011 @@ -19,6 +19,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" @@ -37,7 +38,7 @@ class X86ATTAsmParser : public TargetAsmParser { MCAsmParser &Parser; - const MCSubtargetInfo *STI; + OwningPtr STI; private: MCAsmParser &getParser() const { return Parser; } @@ -79,8 +80,8 @@ public: X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &parser) - : TargetAsmParser(), Parser(parser) { - STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); + : TargetAsmParser(), Parser(parser), + STI(X86_MC::createX86MCSubtargetInfo(TT, CPU, FS)) { // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); From evan.cheng at apple.com Fri Jul 8 16:06:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 14:06:48 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: Message-ID: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> > > The bit of this change in X86Subtarget.cpp appears to break tests > anywhere that sys::getHostCPUName doesn't return the name of a known > 64-bit-capable x86 CPU (ARM, older x86 CPUs, very new x86 CPUS). > Please fix or revert. I don't see how the previous logic would have worked either. Do you know which tests are failing? They probably need to explicitly set -mcpu. Evan > > -Eli From grosbach at apple.com Fri Jul 8 16:10:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 21:10:35 -0000 Subject: [llvm-commits] [llvm] r134739 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110708211035.7B5AB2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 16:10:35 2011 New Revision: 134739 URL: http://llvm.org/viewvc/llvm-project?rev=134739&view=rev Log: Pseudo-ize tBX_RET and tBX_RET_vararg. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134739&r1=134738&r2=134739&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 16:10:35 2011 @@ -385,24 +385,13 @@ } let isReturn = 1, isTerminator = 1, isBarrier = 1 in { - def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", - [(ARMretflag)]>, - T1Special<{1,1,0,?}> { - // A6.2.3 & A8.6.25 - let Inst{6-3} = 0b1110; // Rm = lr - let Inst{2-0} = 0b000; - } + def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br, + [(ARMretflag)], (tBX LR, (ops 14, zero_reg))>; // Alternative return instruction used by vararg functions. - def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), - IIC_Br, "bx\t$Rm", - []>, - T1Special<{1,1,0,?}> { - // A6.2.3 & A8.6.25 - bits<4> Rm; - let Inst{6-3} = Rm; - let Inst{2-0} = 0b000; - } + def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm), + Size2Bytes, IIC_Br, [], + (tBX GPR:$Rm, (ops 14, zero_reg))>; } // All calls clobber the non-callee saved registers. SP is marked as a use to From evan.cheng at apple.com Fri Jul 8 16:14:15 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 21:14:15 -0000 Subject: [llvm-commits] [llvm] r134741 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp Message-ID: <20110708211415.2D93E2A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 16:14:14 2011 New Revision: 134741 URL: http://llvm.org/viewvc/llvm-project?rev=134741&view=rev Log: For non-x86 host, used generic as CPU name. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134741&r1=134740&r2=134741&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Fri Jul 8 16:14:14 2011 @@ -140,8 +140,13 @@ } std::string CPUName = CPU; - if (CPUName.empty()) + if (CPUName.empty()) { +#if defined (__x86_64__) || defined(__i386__) CPUName = sys::getHostCPUName(); +#else + CPUName = "generic"; +#endif + } if (ArchFS.empty() && CPUName.empty() && hasX86_64()) // Auto-detect if host is 64-bit capable, it's the default if true. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134741&r1=134740&r2=134741&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul 8 16:14:14 2011 @@ -258,12 +258,17 @@ ArchFS = FS; } - std::string CPUName = CPU; - if (CPUName.empty()) - CPUName = sys::getHostCPUName(); - // Determine default and user specified characteristics - if (!CPUName.empty() || !ArchFS.empty()) { + if (!ArchFS.empty()) { + std::string CPUName = CPU; + if (CPUName.empty()) { +#if defined (__x86_64__) || defined(__i386__) + CPUName = sys::getHostCPUName(); +#else + CPUName = "generic"; +#endif + } + // If feature string is not empty, parse features string. ParseSubtargetFeatures(CPUName, ArchFS); // All X86-64 CPUs also have SSE2, however user might request no SSE via From evan.cheng at apple.com Fri Jul 8 16:15:51 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 14:15:51 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> Message-ID: <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. Evan On Jul 8, 2011, at 2:06 PM, Evan Cheng wrote: >> >> The bit of this change in X86Subtarget.cpp appears to break tests >> anywhere that sys::getHostCPUName doesn't return the name of a known >> 64-bit-capable x86 CPU (ARM, older x86 CPUs, very new x86 CPUS). >> Please fix or revert. > > I don't see how the previous logic would have worked either. Do you know which tests are failing? They probably need to explicitly set -mcpu. > > Evan > >> >> -Eli > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jlerouge at apple.com Fri Jul 8 16:28:45 2011 From: jlerouge at apple.com (Julien Lerouge) Date: Fri, 08 Jul 2011 14:28:45 -0700 Subject: [llvm-commits] [PATCH] PR10305 / MSCV error LNK2019: unresolved external symbol ___umoddi3 In-Reply-To: References: <20110708184827.GA54225@pom.apple.com> Message-ID: <20110708212845.GB54225@pom.apple.com> On Fri, Jul 08, 2011 at 11:50:42AM -0700, Eric Christopher wrote: > > On Jul 8, 2011, at 11:48 AM, Julien Lerouge wrote: > > > Ok to commit ? This patch just adds _aullrem, _allrem & _allmul to > > X86ISelLowering.cpp for Windows target (MSVC). > > Yep. You have access? > Yes, thanks. -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From bob.wilson at apple.com Fri Jul 8 16:33:30 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 08 Jul 2011 14:33:30 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: I'm still getting the same failures. I'll look at updating X86.td. On Jul 8, 2011, at 2:15 PM, Evan Cheng wrote: > r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. > > Evan > > On Jul 8, 2011, at 2:06 PM, Evan Cheng wrote: > >>> >>> The bit of this change in X86Subtarget.cpp appears to break tests >>> anywhere that sys::getHostCPUName doesn't return the name of a known >>> 64-bit-capable x86 CPU (ARM, older x86 CPUs, very new x86 CPUS). >>> Please fix or revert. >> >> I don't see how the previous logic would have worked either. Do you know which tests are failing? They probably need to explicitly set -mcpu. >> >> Evan >> >>> >>> -Eli >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Fri Jul 8 16:35:14 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 14:35:14 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: > r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. r134741 does't help at all. Consider the case where we're compiling for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and we're on ARM. We end up in 64-bit mode, but with cmov and SSE disabled. Stuff explodes. -Eli From zwarich at apple.com Fri Jul 8 16:39:21 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 08 Jul 2011 21:39:21 -0000 Subject: [llvm-commits] [llvm] r134742 - in /llvm/trunk: docs/ include/llvm/ include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ test/CodeGen/X86/ Message-ID: <20110708213922.637A22A6C12C@llvm.org> Author: zwarich Date: Fri Jul 8 16:39:21 2011 New Revision: 134742 URL: http://llvm.org/viewvc/llvm-project?rev=134742&view=rev Log: Add an intrinsic and codegen support for fused multiply-accumulate. The intent is to use this for architectures that have a native FMA instruction. Added: llvm/trunk/test/CodeGen/X86/fma.ll Modified: llvm/trunk/docs/LangRef.html llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Fri Jul 8 16:39:21 2011 @@ -241,6 +241,7 @@
  • 'llvm.pow.*' Intrinsic
  • 'llvm.exp.*' Intrinsic
  • 'llvm.log.*' Intrinsic
  • +
  • 'llvm.fma.*' Intrinsic
  • Bit Manipulation Intrinsics @@ -6570,6 +6571,37 @@

    This function returns the same values as the libm log functions would, and handles error conditions in the same way.

    +

    + 'llvm.fma.*' Intrinsic +

    + +
    + +
    Syntax:
    +

    This is an overloaded intrinsic. You can use llvm.fma on any + floating point or vector of floating point type. Not all targets support all + types however.

    + +
    +  declare float     @llvm.fma.f32(float  %a, float  %b, float  %c)
    +  declare double    @llvm.fma.f64(double %a, double %b, double %c)
    +  declare x86_fp80  @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c)
    +  declare fp128     @llvm.fma.f128(fp128 %a, fp128 %b, fp128 %c)
    +  declare ppc_fp128 @llvm.fma.ppcf128(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c)
    +
    + +
    Overview:
    +

    The 'llvm.fma.*' intrinsics perform the fused multiply-accumulate + operation.

    + +
    Arguments:
    +

    The argument and return value are floating point numbers of the same + type.

    + +
    Semantics:
    +

    This function returns the same values as the libm fma functions + would.

    +
    Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Fri Jul 8 16:39:21 2011 @@ -232,7 +232,7 @@ SMULO, UMULO, // Simple binary floating point operators. - FADD, FSUB, FMUL, FDIV, FREM, + FADD, FSUB, FMUL, FMA, FDIV, FREM, // FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This // DAG node does not require that X and Y have the same type, just that they Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original) +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Fri Jul 8 16:39:21 2011 @@ -103,6 +103,10 @@ REM_F64, REM_F80, REM_PPCF128, + FMA_F32, + FMA_F64, + FMA_F80, + FMA_PPCF128, POWI_F32, POWI_F64, POWI_F80, Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Fri Jul 8 16:39:21 2011 @@ -255,6 +255,12 @@ def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; } +let Properties = [IntrNoMem] in { + def int_fma : Intrinsic<[llvm_anyfloat_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, + LLVMMatchType<0>]>; +} + // NOTE: these are internal interfaces. def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jul 8 16:39:21 2011 @@ -3351,6 +3351,10 @@ Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, RTLIB::REM_F80, RTLIB::REM_PPCF128)); break; + case ISD::FMA: + Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64, + RTLIB::FMA_F80, RTLIB::FMA_PPCF128)); + break; case ISD::FP16_TO_FP32: Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); break; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Fri Jul 8 16:39:21 2011 @@ -74,6 +74,7 @@ case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break; case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break; + case ISD::FMA: R = SoftenFloatRes_FMA(N); break; case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; @@ -294,6 +295,19 @@ NVT, &Op, 1, false, N->getDebugLoc()); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) { + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); + SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)), + GetSoftenedFloat(N->getOperand(1)), + GetSoftenedFloat(N->getOperand(2)) }; + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::FMA_F32, + RTLIB::FMA_F64, + RTLIB::FMA_F80, + RTLIB::FMA_PPCF128), + NVT, Ops, 3, false, N->getDebugLoc()); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), @@ -837,6 +851,7 @@ case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break; case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break; case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break; + case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break; case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; @@ -989,6 +1004,19 @@ GetPairElements(Call, Lo, Hi); } +void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo, + SDValue &Hi) { + SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; + SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::FMA_F32, + RTLIB::FMA_F64, + RTLIB::FMA_F80, + RTLIB::FMA_PPCF128), + N->getValueType(0), Ops, 3, false, + N->getDebugLoc()); + GetPairElements(Call, Lo, Hi); +} + void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jul 8 16:39:21 2011 @@ -378,6 +378,7 @@ SDValue SoftenFloatRes_FLOG(SDNode *N); SDValue SoftenFloatRes_FLOG2(SDNode *N); SDValue SoftenFloatRes_FLOG10(SDNode *N); + SDValue SoftenFloatRes_FMA(SDNode *N); SDValue SoftenFloatRes_FMUL(SDNode *N); SDValue SoftenFloatRes_FNEARBYINT(SDNode *N); SDValue SoftenFloatRes_FNEG(SDNode *N); @@ -442,6 +443,7 @@ void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi); + void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jul 8 16:39:21 2011 @@ -5878,6 +5878,7 @@ case ISD::FSUB: return "fsub"; case ISD::FMUL: return "fmul"; case ISD::FDIV: return "fdiv"; + case ISD::FMA: return "fma"; case ISD::FREM: return "frem"; case ISD::FCOPYSIGN: return "fcopysign"; case ISD::FGETSIGN: return "fgetsign"; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 8 16:39:21 2011 @@ -4651,6 +4651,13 @@ case Intrinsic::pow: visitPow(I); return 0; + case Intrinsic::fma: + setValue(&I, DAG.getNode(ISD::FMA, dl, + getValue(I.getArgOperand(0)).getValueType(), + getValue(I.getArgOperand(0)), + getValue(I.getArgOperand(1)), + getValue(I.getArgOperand(2)))); + return 0; case Intrinsic::convert_to_fp16: setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, MVT::i16, getValue(I.getArgOperand(0)))); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jul 8 16:39:21 2011 @@ -139,6 +139,10 @@ Names[RTLIB::REM_F64] = "fmod"; Names[RTLIB::REM_F80] = "fmodl"; Names[RTLIB::REM_PPCF128] = "fmodl"; + Names[RTLIB::FMA_F32] = "fmaf"; + Names[RTLIB::FMA_F64] = "fma"; + Names[RTLIB::FMA_F80] = "fmal"; + Names[RTLIB::FMA_PPCF128] = "fmal"; Names[RTLIB::POWI_F32] = "__powisf2"; Names[RTLIB::POWI_F64] = "__powidf2"; Names[RTLIB::POWI_F80] = "__powixf2"; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -708,6 +708,9 @@ setOperationAction(ISD::FPOW, MVT::f64, Expand); setOperationAction(ISD::FPOW, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + // Various VFP goodness if (!UseSoftFloat && !Subtarget->isThumb1Only()) { // int <-> fp are custom expanded into bit_convert + ARMISD ops. Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -122,6 +122,9 @@ setOperationAction(ISD::FPOW , MVT::f32, Expand); setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::SETCC, MVT::f32, Promote); setOperationAction(ISD::BITCAST, MVT::f32, Promote); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -221,6 +221,9 @@ setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -69,6 +69,7 @@ // Floating point operations which are not supported setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -146,6 +146,8 @@ setOperationAction(ISD::FLOG2, MVT::f32, Expand); setOperationAction(ISD::FLOG10, MVT::f32, Expand); setOperationAction(ISD::FEXP, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -125,10 +125,12 @@ setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand); setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FMA , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FMA , MVT::f32, Expand); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -754,9 +754,11 @@ setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand); + setOperationAction(ISD::FMA , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand); + setOperationAction(ISD::FMA , MVT::f32, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); setOperationAction(ISD::CTLZ , MVT::i32, Expand); Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -142,6 +142,8 @@ setOperationAction(ISD::FCOS, MVT::f64, Expand); setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); // We have only 64-bit bitconverts setOperationAction(ISD::BITCAST, MVT::f32, Expand); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134742&r1=134741&r2=134742&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul 8 16:39:21 2011 @@ -646,6 +646,10 @@ addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS } + // We don't support FMA. + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + // Long double always uses X87. if (!UseSoftFloat) { addRegisterClass(MVT::f80, X86::RFP80RegisterClass); @@ -670,6 +674,8 @@ setOperationAction(ISD::FSIN , MVT::f80 , Expand); setOperationAction(ISD::FCOS , MVT::f80 , Expand); } + + setOperationAction(ISD::FMA, MVT::f80, Expand); } // Always use a library call for pow. Added: llvm/trunk/test/CodeGen/X86/fma.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma.ll?rev=134742&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fma.ll (added) +++ llvm/trunk/test/CodeGen/X86/fma.ll Fri Jul 8 16:39:21 2011 @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s + +; CHECK: test_f32 +; CHECK: _fmaf + +define float @test_f32(float %a, float %b, float %c) nounwind readnone ssp { +entry: + %call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone + ret float %call +} + +; CHECK: test_f64 +; CHECK: _fma + +define double @test_f64(double %a, double %b, double %c) nounwind readnone ssp { +entry: + %call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone + ret double %call +} + +; CHECK: test_f80 +; CHECK: _fmal + +define x86_fp80 @test_f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone ssp { +entry: + %call = tail call x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone + ret x86_fp80 %call +} + +declare float @llvm.fma.f32(float, float, float) nounwind readnone +declare double @llvm.fma.f64(double, double, double) nounwind readnone +declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone From jlerouge at apple.com Fri Jul 8 16:40:25 2011 From: jlerouge at apple.com (Julien Lerouge) Date: Fri, 08 Jul 2011 21:40:25 -0000 Subject: [llvm-commits] [llvm] r134744 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/allrem-moddi3.ll Message-ID: <20110708214025.4F3EA2A6C12C@llvm.org> Author: jlerouge Date: Fri Jul 8 16:40:25 2011 New Revision: 134744 URL: http://llvm.org/viewvc/llvm-project?rev=134744&view=rev Log: Add _allrem, _aullrem and _allmul to the runtime for MSVC. http://llvm.org/bugs/show_bug.cgi?id=10305 Added: llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134744&r1=134743&r2=134744&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul 8 16:40:25 2011 @@ -235,10 +235,16 @@ // Setup Windows compiler runtime calls. setLibcallName(RTLIB::SDIV_I64, "_alldiv"); setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); + setLibcallName(RTLIB::SREM_I64, "_allrem"); + setLibcallName(RTLIB::UREM_I64, "_aullrem"); + setLibcallName(RTLIB::MUL_I64, "_allmul"); setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); + setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); } Added: llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll?rev=134744&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll (added) +++ llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll Fri Jul 8 16:40:25 2011 @@ -0,0 +1,19 @@ +; Test that, for a 64 bit signed rem, a libcall to allrem is made on Windows +; unless we have libgcc. + +; RUN: llc < %s -mtriple i386-pc-win32 | FileCheck %s +; RUN: llc < %s -mtriple i386-pc-cygwin | FileCheck %s -check-prefix USEMODDI +; RUN: llc < %s -mtriple i386-pc-mingw32 | FileCheck %s -check-prefix USEMODDI +; PR10305 +; END. + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly { +entry: + %conv4 = sext i32 %argc to i64 + %div = srem i64 84, %conv4 + %conv7 = trunc i64 %div to i32 + ret i32 %conv7 +} + +; CHECK: allrem +; USEMODDI: moddi3 From chandlerc at google.com Fri Jul 8 16:47:58 2011 From: chandlerc at google.com (Chandler Carruth) Date: Fri, 8 Jul 2011 14:47:58 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: On Fri, Jul 8, 2011 at 2:35 PM, Eli Friedman wrote: > On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: > > r134741 should handle the non-x86 hosts. For the other cases, we should > either fix tests or add specific CPUs to X86.td. > > r134741 does't help at all. Consider the case where we're compiling > for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and > we're on ARM. We end up in 64-bit mode, but with cmov and SSE > disabled. Stuff explodes. I think I'm seeing this as well, 96 tests failing with: LLVM ERROR: SSE register return with SSE disabled FWIW, I'm running these tests on a recent Intel processor host (westmere I think...) -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110708/0953e00a/attachment.html From grosbach at apple.com Fri Jul 8 16:50:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 21:50:05 -0000 Subject: [llvm-commits] [llvm] r134746 - in /llvm/trunk: lib/Target/ARM/ARMConstantIslandPass.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/Thumb1FrameLowering.cpp test/CodeGen/Thumb2/machine-licm.ll test/CodeGen/Thumb2/thumb2-bcc.ll test/CodeGen/Thumb2/thumb2-branch.ll test/CodeGen/Thumb2/thumb2-ifcvt1.ll Message-ID: <20110708215005.1EF1E2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 16:50:04 2011 New Revision: 134746 URL: http://llvm.org/viewvc/llvm-project?rev=134746&view=rev Log: Make tBX_RET and tBX_RET_vararg predicable. The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Jul 8 16:50:04 2011 @@ -1538,7 +1538,10 @@ if (MI->getOpcode() == ARM::tPOP_RET && MI->getOperand(2).getReg() == ARM::PC && MI->getNumExplicitOperands() == 3) { - BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); + // Create the new insn and copy the predicate from the old. + BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)); MI->eraseFromParent(); MadeChange = true; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 16:50:04 2011 @@ -385,13 +385,13 @@ } let isReturn = 1, isTerminator = 1, isBarrier = 1 in { - def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br, - [(ARMretflag)], (tBX LR, (ops 14, zero_reg))>; + def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br, + [(ARMretflag)], (tBX LR, pred:$p)>; // Alternative return instruction used by vararg functions. - def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm), + def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), Size2Bytes, IIC_Br, [], - (tBX GPR:$Rm, (ops 14, zero_reg))>; + (tBX GPR:$Rm, pred:$p)>; } // All calls clobber the non-callee saved registers. SP is marked as a use to Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Fri Jul 8 16:50:04 2011 @@ -273,8 +273,8 @@ emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) - .addReg(ARM::R3, RegState::Kill); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) + .addReg(ARM::R3, RegState::Kill)); // erase the old tBX_RET instruction MBB.erase(MBBI); } Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Jul 8 16:50:04 2011 @@ -8,26 +8,25 @@ define void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t1: -; CHECK: cbz +; CHECK: bxeq lr + %0 = icmp eq i32 %c, 0 ; [#uses=1] br i1 %0, label %return, label %bb.nph bb.nph: ; preds = %entry -; CHECK: BB#1 ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] ; CHECK: ldr{{.*}}, [r[[R2b]] -; CHECK: LBB0_2 +; CHECK: LBB0_ ; CHECK-NOT: LCPI0_0: -; PIC: BB#1 ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: add r[[R2]], pc ; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] ; PIC: ldr{{.*}}, [r[[R2b]] -; PIC: LBB0_2 +; PIC: LBB0_ ; PIC-NOT: LCPI0_0: ; PIC: .section %.pre = load i32* @GV, align 4 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll Fri Jul 8 16:50:04 2011 @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it +; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | not grep it +; If-conversion defeats the purpose of this test, which is to check CBZ +; generation, so turn it off. define i32 @t1(i32 %a, i32 %b, i32 %c) { ; CHECK: t1: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll Fri Jul 8 16:50:04 2011 @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -ifcvt-limit=0 -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s +; If-conversion defeats the purpose of this test, which is to check conditional +; branch generation, so turn it off. define i32 @f1(i32 %a, i32 %b, i32* %v) { entry: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=134746&r1=134745&r2=134746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Fri Jul 8 16:50:04 2011 @@ -2,8 +2,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK: t1: -; CHECK: it ne +; CHECK: ittt ne ; CHECK: cmpne +; CHECK: addne +; CHECK: bxne lr switch i32 %c, label %cond_next [ i32 1, label %cond_true i32 7, label %cond_true From eli.friedman at gmail.com Fri Jul 8 16:50:59 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 14:50:59 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: On Fri, Jul 8, 2011 at 2:47 PM, Chandler Carruth wrote: > On Fri, Jul 8, 2011 at 2:35 PM, Eli Friedman wrote: >> >> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >> > r134741 should handle the non-x86 hosts. For the other cases, we should >> > either fix tests or add specific CPUs to X86.td. >> >> r134741 does't help at all. ?Consider the case where we're compiling >> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >> we're on ARM. ?We end up in 64-bit mode, but with cmov and SSE >> disabled. ?Stuff explodes. > > I think I'm seeing this as well, 96 tests failing with:?LLVM ERROR: SSE > register return with SSE disabled > FWIW, I'm running these tests on a recent Intel processor host (westmere I > think...) Yes... it explodes there as well because we misdetect the host CPU type as "i686". That said, we shouldn't be using sys::getHostCPUName() in X86Subtarget::X86Subtarget in the first place. -Eli From evan.cheng at apple.com Fri Jul 8 16:54:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 14:54:23 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> On Jul 8, 2011, at 2:35 PM, Eli Friedman wrote: > On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. > > r134741 does't help at all. Consider the case where we're compiling > for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and > we're on ARM. We end up in 64-bit mode, but with cmov and SSE > disabled. Stuff explodes. That's why this hack is in X86Subtarget.cpp: // If requesting codegen for X86-64, make sure that 64-bit features // are enabled. // FIXME: Remove this feature since it's not actually being used. if (In64BitMode) { HasX86_64 = true; // All 64-bit cpus have cmov support. HasCMov = true; } Evan > > -Eli From eli.friedman at gmail.com Fri Jul 8 16:55:11 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 14:55:11 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> Message-ID: On Fri, Jul 8, 2011 at 2:54 PM, Evan Cheng wrote: > > On Jul 8, 2011, at 2:35 PM, Eli Friedman wrote: > >> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >>> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. >> >> r134741 does't help at all. ?Consider the case where we're compiling >> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >> we're on ARM. ?We end up in 64-bit mode, but with cmov and SSE >> disabled. ?Stuff explodes. > > That's why this hack is in X86Subtarget.cpp: > > ?// If requesting codegen for X86-64, make sure that 64-bit features > ?// are enabled. > ?// FIXME: Remove this feature since it's not actually being used. > ?if (In64BitMode) { > ? ?HasX86_64 = true; > > ? ?// All 64-bit cpus have cmov support. > ? ?HasCMov = true; > ?} In64BitMode is unconditionally false. -Eli From evan.cheng at apple.com Fri Jul 8 16:55:11 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 14:55:11 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> Message-ID: On Jul 8, 2011, at 2:50 PM, Eli Friedman wrote: > On Fri, Jul 8, 2011 at 2:47 PM, Chandler Carruth wrote: >> On Fri, Jul 8, 2011 at 2:35 PM, Eli Friedman wrote: >>> >>> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >>>> r134741 should handle the non-x86 hosts. For the other cases, we should >>>> either fix tests or add specific CPUs to X86.td. >>> >>> r134741 does't help at all. Consider the case where we're compiling >>> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >>> we're on ARM. We end up in 64-bit mode, but with cmov and SSE >>> disabled. Stuff explodes. >> >> I think I'm seeing this as well, 96 tests failing with: LLVM ERROR: SSE >> register return with SSE disabled >> FWIW, I'm running these tests on a recent Intel processor host (westmere I >> think...) > > Yes... it explodes there as well because we misdetect the host CPU > type as "i686". > > That said, we shouldn't be using sys::getHostCPUName() in > X86Subtarget::X86Subtarget in the first place. The code was broken before, it just wasn't triggered if no attributes are specified. It's no better if we default to "generic". I'm trying to figure a way to unbreak this. Evan > > -Eli From evan.cheng at apple.com Fri Jul 8 16:57:00 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 14:57:00 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> Message-ID: <0F0C6606-BB37-469F-A0D8-0DF22035C400@apple.com> On Jul 8, 2011, at 2:55 PM, Eli Friedman wrote: > On Fri, Jul 8, 2011 at 2:54 PM, Evan Cheng wrote: >> >> On Jul 8, 2011, at 2:35 PM, Eli Friedman wrote: >> >>> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >>>> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. >>> >>> r134741 does't help at all. Consider the case where we're compiling >>> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >>> we're on ARM. We end up in 64-bit mode, but with cmov and SSE >>> disabled. Stuff explodes. >> >> That's why this hack is in X86Subtarget.cpp: >> >> // If requesting codegen for X86-64, make sure that 64-bit features >> // are enabled. >> // FIXME: Remove this feature since it's not actually being used. >> if (In64BitMode) { >> HasX86_64 = true; >> >> // All 64-bit cpus have cmov support. >> HasCMov = true; >> } > > In64BitMode is unconditionally false. No ParseSubtargetFeatures can set it: if ((Bits & X86::Mode64Bit) != 0) In64BitMode = true; Evan > > -Eli From eli.friedman at gmail.com Fri Jul 8 17:03:25 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 15:03:25 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: <0F0C6606-BB37-469F-A0D8-0DF22035C400@apple.com> References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> <0F0C6606-BB37-469F-A0D8-0DF22035C400@apple.com> Message-ID: On Fri, Jul 8, 2011 at 2:57 PM, Evan Cheng wrote: > > On Jul 8, 2011, at 2:55 PM, Eli Friedman wrote: > >> On Fri, Jul 8, 2011 at 2:54 PM, Evan Cheng wrote: >>> >>> On Jul 8, 2011, at 2:35 PM, Eli Friedman wrote: >>> >>>> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >>>>> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. >>>> >>>> r134741 does't help at all. ?Consider the case where we're compiling >>>> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >>>> we're on ARM. ?We end up in 64-bit mode, but with cmov and SSE >>>> disabled. ?Stuff explodes. >>> >>> That's why this hack is in X86Subtarget.cpp: >>> >>> ?// If requesting codegen for X86-64, make sure that 64-bit features >>> ?// are enabled. >>> ?// FIXME: Remove this feature since it's not actually being used. >>> ?if (In64BitMode) { >>> ? ?HasX86_64 = true; >>> >>> ? ?// All 64-bit cpus have cmov support. >>> ? ?HasCMov = true; >>> ?} >> >> In64BitMode is unconditionally false. > > No ParseSubtargetFeatures can set it: > ?if ((Bits & X86::Mode64Bit) != 0) In64BitMode = true; Oh, right... but the hack doesn't handle SSE. -Eli From evan.cheng at apple.com Fri Jul 8 17:05:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 15:05:23 -0700 Subject: [llvm-commits] [llvm] r134641 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h lib/Target/X86/X86.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h lib/Target/X86/X86Ta In-Reply-To: References: <075E4DEB-97EF-4E8C-9930-FCA81A123EBE@apple.com> <1F08C959-ED1E-416F-A707-A1C1DA5F4485@apple.com> <3C30FF9D-29FB-4FE7-8207-0282C68F85C8@apple.com> <0F0C6606-BB37-469F-A0D8-0DF22035C400@apple.com> Message-ID: <411073A8-BB6D-44EE-849B-64D783088091@apple.com> On Jul 8, 2011, at 3:03 PM, Eli Friedman wrote: > On Fri, Jul 8, 2011 at 2:57 PM, Evan Cheng wrote: >> >> On Jul 8, 2011, at 2:55 PM, Eli Friedman wrote: >> >>> On Fri, Jul 8, 2011 at 2:54 PM, Evan Cheng wrote: >>>> >>>> On Jul 8, 2011, at 2:35 PM, Eli Friedman wrote: >>>> >>>>> On Fri, Jul 8, 2011 at 2:15 PM, Evan Cheng wrote: >>>>>> r134741 should handle the non-x86 hosts. For the other cases, we should either fix tests or add specific CPUs to X86.td. >>>>> >>>>> r134741 does't help at all. Consider the case where we're compiling >>>>> for a triple like x86_64-apple-macosx10.7.0, no CPU is specified, and >>>>> we're on ARM. We end up in 64-bit mode, but with cmov and SSE >>>>> disabled. Stuff explodes. >>>> >>>> That's why this hack is in X86Subtarget.cpp: >>>> >>>> // If requesting codegen for X86-64, make sure that 64-bit features >>>> // are enabled. >>>> // FIXME: Remove this feature since it's not actually being used. >>>> if (In64BitMode) { >>>> HasX86_64 = true; >>>> >>>> // All 64-bit cpus have cmov support. >>>> HasCMov = true; >>>> } >>> >>> In64BitMode is unconditionally false. >> >> No ParseSubtargetFeatures can set it: >> if ((Bits & X86::Mode64Bit) != 0) In64BitMode = true; > > Oh, right... but the hack doesn't handle SSE. That's because of this: // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) // without disabling 64-bit mode. Evan > > -Eli From bob.wilson at apple.com Fri Jul 8 17:09:33 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 08 Jul 2011 22:09:33 -0000 Subject: [llvm-commits] [llvm] r134749 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Message-ID: <20110708220933.8F2412A6C12C@llvm.org> Author: bwilson Date: Fri Jul 8 17:09:33 2011 New Revision: 134749 URL: http://llvm.org/viewvc/llvm-project?rev=134749&view=rev Log: Reapply a fixed version of r133285. This tightens up checking for overflow in alloca sizes, based on feedback from Duncan and John about the change in r132926. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=134749&r1=134748&r2=134749&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Fri Jul 8 17:09:33 2011 @@ -30,6 +30,14 @@ } if (BinaryOperator *I = dyn_cast(Val)) { + // Cannot look past anything that might overflow. + OverflowingBinaryOperator *OBI = dyn_cast(Val); + if (OBI && !OBI->hasNoUnsignedWrap()) { + Scale = 1; + Offset = 0; + return Val; + } + if (ConstantInt *RHS = dyn_cast(I->getOperand(1))) { if (I->getOpcode() == Instruction::Shl) { // This is a value scaled by '1 << the shift amt'. @@ -71,11 +79,6 @@ // This requires TargetData to get the alloca alignment and size information. if (!TD) return 0; - // Insist that the amount-to-allocate not overflow. - OverflowingBinaryOperator *OBI = - dyn_cast(AI.getOperand(0)); - if (OBI && !(OBI->hasNoSignedWrap() || OBI->hasNoUnsignedWrap())) return 0; - const PointerType *PTy = cast(CI.getType()); BuilderTy AllocaBuilder(*Builder); From bob.wilson at apple.com Fri Jul 8 17:09:35 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 08 Jul 2011 22:09:35 -0000 Subject: [llvm-commits] [llvm] r134750 - /llvm/trunk/lib/Support/Host.cpp Message-ID: <20110708220935.C63722A6C12D@llvm.org> Author: bwilson Date: Fri Jul 8 17:09:35 2011 New Revision: 134750 URL: http://llvm.org/viewvc/llvm-project?rev=134750&view=rev Log: Recognize Intel CPUs with Family=6 and Model=44. According to Intel Application Note 485, this value is used for "Intel Core i7 and Intel Xeon processor". Just include it with the other "corei7-avx" entries. Modified: llvm/trunk/lib/Support/Host.cpp Modified: llvm/trunk/lib/Support/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=134750&r1=134749&r2=134750&view=diff ============================================================================== --- llvm/trunk/lib/Support/Host.cpp (original) +++ llvm/trunk/lib/Support/Host.cpp Fri Jul 8 17:09:35 2011 @@ -215,6 +215,7 @@ case 37: // Intel Core i7, laptop version. return "corei7"; case 42: // SandyBridge + case 44: case 45: return "corei7-avx"; From gohman at apple.com Fri Jul 8 17:09:54 2011 From: gohman at apple.com (Dan Gohman) Date: Fri, 08 Jul 2011 15:09:54 -0700 Subject: [llvm-commits] [llvm] r134742 - in /llvm/trunk: docs/ include/llvm/ include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ test/CodeGen/X86/ In-Reply-To: <20110708213922.637A22A6C12C@llvm.org> References: <20110708213922.637A22A6C12C@llvm.org> Message-ID: On Jul 8, 2011, at 2:39 PM, Cameron Zwarich wrote: > > +
    Overview:
    > +

    The 'llvm.fma.*' intrinsics perform the fused multiply-accumulate > + operation.

    This should say "add" rather than "accumulate", since LLVM IR doesn't use accumulators. Dan From aggarwa4 at illinois.edu Fri Jul 8 17:10:54 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 08 Jul 2011 22:10:54 -0000 Subject: [llvm-commits] [poolalloc] r134751 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110708221054.782ED2A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jul 8 17:10:54 2011 New Revision: 134751 URL: http://llvm.org/viewvc/llvm-project?rev=134751&view=rev Log: Do not transform indirect call sites if an external functions is address taken and can be called through the call site. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134751&r1=134750&r2=134751&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jul 8 17:10:54 2011 @@ -128,6 +128,7 @@ bool TypeChecks::runOnModule(Module &M) { bool modified = false; // Flags whether we modified the module. + bool transformIndirectCalls = true; TD = &getAnalysis(); addrAnalysis = &getAnalysis(); @@ -169,8 +170,12 @@ // Recognize special cases for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; - if(F.isDeclaration()) + if(F.isDeclaration()) { + if(addrAnalysis->hasAddressTaken(&F)) + transformIndirectCalls = false; + continue; + } std::string name = F.getName(); if (strncmp(name.c_str(), "tc.", 3) == 0) continue; @@ -216,12 +221,14 @@ } // Modify all the address taken functions - while(!AddressTakenFunctions.empty()) { - Function *F = AddressTakenFunctions.back(); - AddressTakenFunctions.pop_back(); - if(F->isVarArg()) - continue; - visitAddressTakenFunction(M, *F); + if(transformIndirectCalls) { + while(!AddressTakenFunctions.empty()) { + Function *F = AddressTakenFunctions.back(); + AddressTakenFunctions.pop_back(); + if(F->isVarArg()) + continue; + visitAddressTakenFunction(M, *F); + } } for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { @@ -237,7 +244,7 @@ if(!isa(SI->getOperand(0))) modified |= visitStoreInst(M, *SI); } else if (LoadInst *LI = dyn_cast(&I)) { - modified |= visitLoadInst(M, *LI); + modified |= visitLoadInst(M, *LI); } else if (CallInst *CI = dyn_cast(&I)) { modified |= visitCallInst(M, *CI); } else if (InvokeInst *II = dyn_cast(&I)) { @@ -251,13 +258,15 @@ } // visit all the indirect call sites - std::set::iterator II = IndCalls.begin(); - for(; II != IndCalls.end();) { - Instruction *I = *II++; - modified |= visitIndirectCallSite(M,I); + if(transformIndirectCalls) { + std::set::iterator II = IndCalls.begin(); + for(; II != IndCalls.end();) { + Instruction *I = *II++; + modified |= visitIndirectCallSite(M,I); + } } - // visit all the uses of the address taken functions and modify if + // visit all the uses of the address taken functions and var arg functions and modify if // not being passed to external code std::map::iterator FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end(); for(;FI!=FE;++FI) { @@ -330,7 +339,7 @@ } void TypeChecks::initRuntimeCheckPrototypes(Module &M) { - + RegisterArgv = M.getOrInsertFunction("trackArgvType", VoidTy, Int32Ty, /*argc */ @@ -341,7 +350,7 @@ VoidTy, VoidPtrTy->getPointerTo(),/*envp*/ NULL); - + trackGlobal = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy,/*ptr*/ @@ -357,7 +366,7 @@ Int64Ty,/*count*/ Int32Ty,/*tag*/ NULL); - + trackInitInst = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy,/*ptr*/ @@ -395,13 +404,13 @@ Int32Ty,/*tag*/ NULL); setTypeInfo = M.getOrInsertFunction("setTypeInfo", - VoidTy, - VoidPtrTy,/*dest ptr*/ - TypeTagPtrTy,/*metadata*/ - Int64Ty,/*size*/ - TypeTagTy, - Int32Ty,/*tag*/ - NULL); + VoidTy, + VoidPtrTy,/*dest ptr*/ + TypeTagPtrTy,/*metadata*/ + Int64Ty,/*size*/ + TypeTagTy, + Int32Ty,/*tag*/ + NULL); copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy,/*dest ptr*/ @@ -840,7 +849,7 @@ // Find all uses of the function for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); ui != ue;ui ++) { - + // Check for call sites if(InvokeInst *II = dyn_cast(ui)) { std::vector Args; @@ -1602,7 +1611,8 @@ CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("getenv") || - F->getNameStr() == std::string("strerror")) { + F->getNameStr() == std::string("strerror") || + F->getNameStr() == std::string("inet_ntoa")) { CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI->insertAfter(I); std::vectorArgs; @@ -2122,13 +2132,13 @@ BitCast_MD_Map[BI] = AI; visitUses(BI, AI, BCI); //CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser())); - /*} else if(PtrToIntInst *P2I = dyn_cast(II)) { - visitUses(P2I, AI, BCI); - } else if(IntToPtrInst *I2P = dyn_cast(II)) { - visitUses(I2P, AI, BCI);*/ - }else { - CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser())); - } + /*} else if(PtrToIntInst *P2I = dyn_cast(II)) { + visitUses(P2I, AI, BCI); + } else if(IntToPtrInst *I2P = dyn_cast(II)) { + visitUses(I2P, AI, BCI);*/ + }else { + CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser())); + } } return true; } From zwarich at apple.com Fri Jul 8 17:13:55 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 08 Jul 2011 22:13:55 -0000 Subject: [llvm-commits] [llvm] r134752 - /llvm/trunk/docs/LangRef.html Message-ID: <20110708221355.7DA162A6C12C@llvm.org> Author: zwarich Date: Fri Jul 8 17:13:55 2011 New Revision: 134752 URL: http://llvm.org/viewvc/llvm-project?rev=134752&view=rev Log: Use add instead of accumulate. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=134752&r1=134751&r2=134752&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Fri Jul 8 17:13:55 2011 @@ -6591,7 +6591,7 @@
    Overview:
    -

    The 'llvm.fma.*' intrinsics perform the fused multiply-accumulate +

    The 'llvm.fma.*' intrinsics perform the fused multiply-add operation.

    Arguments:
    From eli.friedman at gmail.com Fri Jul 8 17:16:47 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 08 Jul 2011 22:16:47 -0000 Subject: [llvm-commits] [llvm] r134753 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/sse1.ll Message-ID: <20110708221647.5E4502A6C12C@llvm.org> Author: efriedma Date: Fri Jul 8 17:16:47 2011 New Revision: 134753 URL: http://llvm.org/viewvc/llvm-project?rev=134753&view=rev Log: Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/test/CodeGen/X86/sse1.ll Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134753&r1=134752&r2=134753&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Fri Jul 8 17:16:47 2011 @@ -35,7 +35,7 @@ std::string X86_MC::ParseX86Triple(StringRef TT) { Triple TheTriple(TT); if (TheTriple.getArch() == Triple::x86_64) - return "+64bit-mode"; + return "+64bit-mode,+64bit,+sse2"; return "-64bit-mode"; } @@ -107,28 +107,6 @@ } } -static bool hasX86_64() { - // FIXME: Code duplication. See X86Subtarget::AutoDetectSubtargetFeatures. - unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; - union { - unsigned u[3]; - char c[12]; - } text; - - if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) - return false; - - bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; - bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; - if (IsIntel || IsAMD) { - X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); - if ((EDX >> 29) & 0x1) - return true; - } - - return false; -} - MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { std::string ArchFS = X86_MC::ParseX86Triple(TT); @@ -148,10 +126,6 @@ #endif } - if (ArchFS.empty() && CPUName.empty() && hasX86_64()) - // Auto-detect if host is 64-bit capable, it's the default if true. - ArchFS = "+64bit-mode"; - MCSubtargetInfo *X = new MCSubtargetInfo(); InitX86MCSubtargetInfo(X, CPUName, ArchFS); return X; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134753&r1=134752&r2=134753&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul 8 17:16:47 2011 @@ -286,16 +286,6 @@ if (In64BitMode && !HasAVX && X86SSELevel < SSE2) X86SSELevel = SSE2; } - - // If requesting codegen for X86-64, make sure that 64-bit features - // are enabled. - // FIXME: Remove this feature since it's not actually being used. - if (In64BitMode) { - HasX86_64 = true; - - // All 64-bit cpus have cmov support. - HasCMov = true; - } DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel Modified: llvm/trunk/test/CodeGen/X86/sse1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse1.ll?rev=134753&r1=134752&r2=134753&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse1.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse1.ll Fri Jul 8 17:16:47 2011 @@ -1,6 +1,6 @@ ; Tests for SSE1 and below, without SSE2+. ; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s -; RUN: llc < %s -march=x86-64 -mcpu=pentium3 -O3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s define <8 x i16> @test1(<8 x i32> %a) nounwind { ; CHECK: test1 From grosbach at apple.com Fri Jul 8 17:25:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 22:25:24 -0000 Subject: [llvm-commits] [llvm] r134755 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110708222524.2D4C02A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 17:25:23 2011 New Revision: 134755 URL: http://llvm.org/viewvc/llvm-project?rev=134755&view=rev Log: Pseudo-ize tBRIND. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134755&r1=134754&r2=134755&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 17:25:23 2011 @@ -370,18 +370,6 @@ let Inst{6-3} = Rm; let Inst{2-0} = 0b000; } - - def tBRIND : TI<(outs), (ins GPR:$Rm), - IIC_Br, - "mov\tpc, $Rm", - [(brind GPR:$Rm)]>, - T1Special<{1,0,?,?}> { - // A8.6.97 - bits<4> Rm; - let Inst{7} = 1; // = Inst{7:2-0} = pc - let Inst{6-3} = Rm; - let Inst{2-0} = 0b111; - } } let isReturn = 1, isTerminator = 1, isBarrier = 1 in { @@ -1496,3 +1484,9 @@ Size2Bytes, IIC_iPop_Br, [], (tPOP pred:$p, reglist:$regs)>; +// Indirect branch using "mov pc, $Rm" +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { + def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm), + Size2Bytes, IIC_Br, [(brind GPR:$Rm)], + (tMOVr PC, GPR:$Rm, (ops 14, zero_reg))>; +} From evan.cheng at apple.com Fri Jul 8 17:29:33 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 22:29:33 -0000 Subject: [llvm-commits] [llvm] r134756 - in /llvm/trunk/test/CodeGen/X86: 2010-07-11-FPStackLoneUse.ll 2011-04-13-SchedCmpJmp.ll sse3.ll Message-ID: <20110708222933.6093E2A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 17:29:33 2011 New Revision: 134756 URL: http://llvm.org/viewvc/llvm-project?rev=134756&view=rev Log: Fix broken x86_64 tests which specify non-64-bit cpu's. Modified: llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll llvm/trunk/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll llvm/trunk/test/CodeGen/X86/sse3.ll Modified: llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll?rev=134756&r1=134755&r2=134756&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll Fri Jul 8 17:29:33 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=i486 +; RUN: llc < %s -mcpu=core2 ; PR7375 ; ; This function contains a block (while.cond) with a lonely RFP use that is Modified: llvm/trunk/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll?rev=134756&r1=134755&r2=134756&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll Fri Jul 8 17:29:33 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; Reduced from JavaScriptCore %"class.JSC::CodeLocationCall" = type { [8 x i8] } Modified: llvm/trunk/test/CodeGen/X86/sse3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=134756&r1=134755&r2=134756&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse3.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse3.ll Fri Jul 8 17:29:33 2011 @@ -1,6 +1,6 @@ -; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. +; These are tests for SSE3 codegen. -; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \ +; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \ ; RUN: | FileCheck %s --check-prefix=X64 ; Test for v8xi16 lowering where we extract the first element of the vector and From evan.cheng at apple.com Fri Jul 8 17:30:26 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 22:30:26 -0000 Subject: [llvm-commits] [llvm] r134757 - in /llvm/trunk/lib/Target/X86: X86Subtarget.cpp X86Subtarget.h X86TargetMachine.cpp Message-ID: <20110708223026.1280B2A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 17:30:25 2011 New Revision: 134757 URL: http://llvm.org/viewvc/llvm-project?rev=134757&view=rev Log: Restore old behavior. Always auto-detect features unless cpu or features are specified. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134757&r1=134756&r2=134757&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul 8 17:30:25 2011 @@ -225,7 +225,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, - unsigned StackAlignOverride) + unsigned StackAlignOverride, bool is64Bit) : X86GenSubtargetInfo(TT, CPU, FS) , PICStyle(PICStyles::None) , X86SSELevel(NoMMXSSE) @@ -246,20 +246,9 @@ // FIXME: this is a known good value for Yonah. How about others? , MaxInlineSizeThreshold(128) , TargetTriple(TT) - , In64BitMode(false) { - // Insert the architecture feature derived from the target triple into the - // feature string. This is important for setting features that are implied - // based on the architecture version. - std::string ArchFS = X86_MC::ParseX86Triple(TT); - if (!FS.empty()) { - if (!ArchFS.empty()) - ArchFS = ArchFS + "," + FS; - else - ArchFS = FS; - } - + , In64BitMode(is64Bit) { // Determine default and user specified characteristics - if (!ArchFS.empty()) { + if (!FS.empty() || !CPU.empty()) { std::string CPUName = CPU; if (CPUName.empty()) { #if defined (__x86_64__) || defined(__i386__) @@ -270,7 +259,8 @@ } // If feature string is not empty, parse features string. - ParseSubtargetFeatures(CPUName, ArchFS); + ParseSubtargetFeatures(CPUName, FS); + // All X86-64 CPUs also have SSE2, however user might request no SSE via // -mattr, so don't force SSELevel here. if (HasAVX) @@ -279,9 +269,6 @@ // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - // If CPU is 64-bit capable, default to 64-bit mode if not specified. - In64BitMode = HasX86_64; - // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. if (In64BitMode && !HasAVX && X86SSELevel < SSE2) X86SSELevel = SSE2; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134757&r1=134756&r2=134757&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Jul 8 17:30:25 2011 @@ -122,7 +122,7 @@ /// X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, - unsigned StackAlignOverride); + unsigned StackAlignOverride, bool is64Bit); /// getStackAlignment - Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must be maintained by every Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134757&r1=134756&r2=134757&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Fri Jul 8 17:30:25 2011 @@ -120,7 +120,7 @@ const std::string &CPU, const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT, CPU, FS), - Subtarget(TT, CPU, FS, StackAlignmentOverride), + Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { DefRelocModel = getRelocationModel(); From grosbach at apple.com Fri Jul 8 17:33:49 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 08 Jul 2011 22:33:49 -0000 Subject: [llvm-commits] [llvm] r134758 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110708223349.CF8CD2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 8 17:33:49 2011 New Revision: 134758 URL: http://llvm.org/viewvc/llvm-project?rev=134758&view=rev Log: Mark tBRIND as predicable. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134758&r1=134757&r2=134758&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 17:33:49 2011 @@ -1486,7 +1486,7 @@ // Indirect branch using "mov pc, $Rm" let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { - def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm), + def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), Size2Bytes, IIC_Br, [(brind GPR:$Rm)], - (tMOVr PC, GPR:$Rm, (ops 14, zero_reg))>; + (tMOVr PC, GPR:$Rm, pred:$p)>; } From bob.wilson at apple.com Fri Jul 8 17:33:59 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 08 Jul 2011 22:33:59 -0000 Subject: [llvm-commits] [llvm] r134759 - /llvm/trunk/lib/Support/Host.cpp Message-ID: <20110708223359.2A1A72A6C12C@llvm.org> Author: bwilson Date: Fri Jul 8 17:33:59 2011 New Revision: 134759 URL: http://llvm.org/viewvc/llvm-project?rev=134759&view=rev Log: Update comments for SandyBridge CPU identifiers. Modified: llvm/trunk/lib/Support/Host.cpp Modified: llvm/trunk/lib/Support/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=134759&r1=134758&r2=134759&view=diff ============================================================================== --- llvm/trunk/lib/Support/Host.cpp (original) +++ llvm/trunk/lib/Support/Host.cpp Fri Jul 8 17:33:59 2011 @@ -214,8 +214,12 @@ // As found in a Summer 2010 model iMac. case 37: // Intel Core i7, laptop version. return "corei7"; - case 42: // SandyBridge - case 44: + + // SandyBridge: + case 42: // Intel Core i7 processor. All processors are manufactured + // using the 32 nm process. + case 44: // Intel Core i7 processor and Intel Xeon processor. All + // processors are manufactured using the 32 nm process. case 45: return "corei7-avx"; From evan.cheng at apple.com Fri Jul 8 17:36:29 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 22:36:29 -0000 Subject: [llvm-commits] [llvm] r134760 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/mode-switch.s Message-ID: <20110708223629.5AD072A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 17:36:29 2011 New Revision: 134760 URL: http://llvm.org/viewvc/llvm-project?rev=134760&view=rev Log: Add support for ARM / Thumb mode switching with .code 16 and .code 32. Added: llvm/trunk/test/MC/ARM/mode-switch.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134760&r1=134759&r2=134760&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 8 17:36:29 2011 @@ -42,7 +42,11 @@ class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; - OwningPtr STI; + /// STI, ARM_STI, Thumb_STI - Subtarget info for ARM and Thumb modes. STI + /// points to either ARM_STI or Thumb_STI depending on the mode. + const MCSubtargetInfo *STI; + OwningPtr ARM_STI; + OwningPtr Thumb_STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -89,10 +93,13 @@ // FIXME: Can tablegen auto-generate this? return (STI->getFeatureBits() & ARM::ModeThumb) != 0; } - bool isThumbOne() const { return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; } + void SwitchMode() { + STI = isThumb() ? ARM_STI.get() : Thumb_STI.get(); + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + } /// @name Auto-generated Match Functions /// { @@ -129,10 +136,24 @@ public: ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) - : TargetAsmParser(), Parser(_Parser), - STI(ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS)) { - + : TargetAsmParser(), Parser(_Parser) { MCAsmParserExtension::Initialize(_Parser); + + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); + // FIXME: Design a better way to create two subtargets with only difference + // being a feature change. + if (isThumb()) { + Thumb_STI.reset(STI); + assert(TT.startswith("thumb") && "Unexpected Triple string for Thumb!"); + Twine ARM_TT = "arm" + TT.substr(5); + ARM_STI.reset(ARM_MC::createARMMCSubtargetInfo(ARM_TT.str(), CPU, FS)); + } else { + ARM_STI.reset(STI); + assert(TT.startswith("arm") && "Unexpected Triple string for ARM!"); + Twine Thumb_TT = "thumb" + TT.substr(3); + Thumb_STI.reset(ARM_MC::createARMMCSubtargetInfo(Thumb_TT.str(),CPU, FS)); + } + // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); } @@ -2215,18 +2236,11 @@ return Error(Parser.getTok().getLoc(), "unexpected token in directive"); Parser.Lex(); - // FIXME: We need to be able switch subtargets at this point so that - // MatchInstructionImpl() will work when it gets the AvailableFeatures which - // includes Feature_IsThumb or not to match the right instructions. This is - // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. - if (Val == 16){ - assert(isThumb() && - "switching between arm/thumb not yet suppported via .code 16)"); + if (Val == 16) { + if (!isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); - } - else{ - assert(!isThumb() && - "switching between thumb/arm not yet suppported via .code 32)"); + } else { + if (isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); } Added: llvm/trunk/test/MC/ARM/mode-switch.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=134760&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/mode-switch.s (added) +++ llvm/trunk/test/MC/ARM/mode-switch.s Fri Jul 8 17:36:29 2011 @@ -0,0 +1,16 @@ +@ Test ARM / Thumb mode switching with .code +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: add.w r0, r0, r1 @ encoding: [0x01,0x00,0x00,0xeb] + add.w r0, r0, r1 + +.code 32 +@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0] + add r0, r0, r1 + +.code 16 +@ CHECK: add r0, r0, r1 @ encoding: [0x40,0x18] + + add r0, r0, r1 From zwarich at apple.com Fri Jul 8 17:49:34 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 08 Jul 2011 22:49:34 -0000 Subject: [llvm-commits] [llvm] r134762 - /llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Message-ID: <20110708224934.370952A6C12C@llvm.org> Author: zwarich Date: Fri Jul 8 17:49:34 2011 New Revision: 134762 URL: http://llvm.org/viewvc/llvm-project?rev=134762&view=rev Log: Add an fma TableGen node. Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=134762&r1=134761&r2=134762&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Fri Jul 8 17:49:34 2011 @@ -353,6 +353,7 @@ def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; +def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; From evan.cheng at apple.com Fri Jul 8 17:49:42 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 22:49:42 -0000 Subject: [llvm-commits] [llvm] r134763 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110708224942.93CAB2A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 17:49:42 2011 New Revision: 134763 URL: http://llvm.org/viewvc/llvm-project?rev=134763&view=rev Log: Fix comment. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=134763&r1=134762&r2=134763&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Fri Jul 8 17:49:42 2011 @@ -1088,7 +1088,7 @@ } } - // FIXME: Node the fixup comments for Thumb2 are completely bogus since the + // FIXME: Note the fixup comments for Thumb2 are completely bogus since the // high order halfword of a 32-bit Thumb2 instruction is emitted first. OS << "encoding: ["; for (unsigned i = 0, e = Code.size(); i != e; ++i) { From evan.cheng at apple.com Fri Jul 8 17:49:55 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 22:49:55 -0000 Subject: [llvm-commits] [llvm] r134764 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110708224955.D53AE2A6C12C@llvm.org> Author: evancheng Date: Fri Jul 8 17:49:55 2011 New Revision: 134764 URL: http://llvm.org/viewvc/llvm-project?rev=134764&view=rev Log: Fix indentation. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134764&r1=134763&r2=134764&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 8 17:49:55 2011 @@ -2050,7 +2050,7 @@ // that updates the condition codes if it ends in 's'. So see if the // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut // operand with a value of CPSR. - else if(MatchResult == Match_MnemonicFail) { + else if (MatchResult == Match_MnemonicFail) { // Get the instruction mnemonic, which is the first token. StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); if (Mnemonic.substr(Mnemonic.size()-1) == "s") { @@ -2242,7 +2242,7 @@ } else { if (isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); - } + } return false; } From greened at obbligato.org Fri Jul 8 18:00:48 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 08 Jul 2011 18:00:48 -0500 Subject: [llvm-commits] [llvm] r134741 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp In-Reply-To: <20110708211415.2D93E2A6C12C@llvm.org> (Evan Cheng's message of "Fri, 08 Jul 2011 21:14:15 -0000") References: <20110708211415.2D93E2A6C12C@llvm.org> Message-ID: Evan Cheng writes: > Author: evancheng > Date: Fri Jul 8 16:14:14 2011 > New Revision: 134741 > > URL: http://llvm.org/viewvc/llvm-project?rev=134741&view=rev > Log: > For non-x86 host, used generic as CPU name. Newish x86 hosts are still broken. From eli.friedman at gmail.com Fri Jul 8 18:07:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 08 Jul 2011 23:07:42 -0000 Subject: [llvm-commits] [llvm] r134768 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp Message-ID: <20110708230742.CBB092A6C12C@llvm.org> Author: efriedma Date: Fri Jul 8 18:07:42 2011 New Revision: 134768 URL: http://llvm.org/viewvc/llvm-project?rev=134768&view=rev Log: Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134768&r1=134767&r2=134768&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Fri Jul 8 18:07:42 2011 @@ -35,7 +35,7 @@ std::string X86_MC::ParseX86Triple(StringRef TT) { Triple TheTriple(TT); if (TheTriple.getArch() == Triple::x86_64) - return "+64bit-mode,+64bit,+sse2"; + return "+64bit-mode"; return "-64bit-mode"; } Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134768&r1=134767&r2=134768&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul 8 18:07:42 2011 @@ -269,9 +269,14 @@ // Otherwise, use CPUID to auto-detect feature set. AutoDetectSubtargetFeatures(); - // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. - if (In64BitMode && !HasAVX && X86SSELevel < SSE2) - X86SSELevel = SSE2; + // Make sure 64-bit features are available in 64-bit mode. + if (In64BitMode) { + HasX86_64 = true; + HasCMov = true; + + if (!HasAVX && X86SSELevel < SSE2) + X86SSELevel = SSE2; + } } DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel From eli.friedman at gmail.com Fri Jul 8 18:08:57 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 16:08:57 -0700 Subject: [llvm-commits] [llvm] r134741 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp In-Reply-To: References: <20110708211415.2D93E2A6C12C@llvm.org> Message-ID: On Fri, Jul 8, 2011 at 4:00 PM, David A. Greene wrote: > Evan Cheng writes: > >> Author: evancheng >> Date: Fri Jul ?8 16:14:14 2011 >> New Revision: 134741 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134741&view=rev >> Log: >> For non-x86 host, used generic as CPU name. > > Newish x86 hosts are still broken. svn up again; everything should be fixed as of r134768. -Eli From greened at obbligato.org Fri Jul 8 18:28:20 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 08 Jul 2011 18:28:20 -0500 Subject: [llvm-commits] [llvm] r134741 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp In-Reply-To: (Eli Friedman's message of "Fri, 8 Jul 2011 16:08:57 -0700") References: <20110708211415.2D93E2A6C12C@llvm.org> Message-ID: Eli Friedman writes: > On Fri, Jul 8, 2011 at 4:00 PM, David A. Greene wrote: >> Evan Cheng writes: >> >>> Author: evancheng >>> Date: Fri Jul ?8 16:14:14 2011 >>> New Revision: 134741 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=134741&view=rev >>> Log: >>> For non-x86 host, used generic as CPU name. >> >> Newish x86 hosts are still broken. > > svn up again; everything should be fixed as of r134768. Now I am getting a lot of this: llc: lib/Target/X86/X86Subtarget.cpp:286: llvm::X86Subtarget::X86Subtarget(const std::string&, const std::string&, const std::string&, unsigned int, bool): Assertion `(!In64BitMode || HasX86_64) && "64-bit code requested on a subtarget that doesn't support it!"' failed. -Dave From greened at obbligato.org Fri Jul 8 18:29:18 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 08 Jul 2011 18:29:18 -0500 Subject: [llvm-commits] [llvm] r134768 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp In-Reply-To: <20110708230742.CBB092A6C12C@llvm.org> (Eli Friedman's message of "Fri, 08 Jul 2011 23:07:42 -0000") References: <20110708230742.CBB092A6C12C@llvm.org> Message-ID: Eli Friedman writes: > Author: efriedma > Date: Fri Jul 8 18:07:42 2011 > New Revision: 134768 > > URL: http://llvm.org/viewvc/llvm-project?rev=134768&view=rev > Log: > Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets. Still broken for unknown (I think) x86 targets. -Dave From eli.friedman at gmail.com Fri Jul 8 18:43:01 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 08 Jul 2011 23:43:01 -0000 Subject: [llvm-commits] [llvm] r134773 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <20110708234301.6AECC2A6C12C@llvm.org> Author: efriedma Date: Fri Jul 8 18:43:01 2011 New Revision: 134773 URL: http://llvm.org/viewvc/llvm-project?rev=134773&view=rev Log: Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134773&r1=134772&r2=134773&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul 8 18:43:01 2011 @@ -258,11 +258,19 @@ #endif } + // Make sure 64-bit features are available in 64-bit mode. (But make sure + // SSE2 can be turned off explicitly.) + std::string FullFS = FS; + if (In64BitMode) { + if (!FullFS.empty()) + FullFS = "+64bit,+sse2," + FullFS; + else + FullFS = "+64bit,+sse2"; + } + // If feature string is not empty, parse features string. - ParseSubtargetFeatures(CPUName, FS); + ParseSubtargetFeatures(CPUName, FullFS); - // All X86-64 CPUs also have SSE2, however user might request no SSE via - // -mattr, so don't force SSELevel here. if (HasAVX) X86SSELevel = NoMMXSSE; } else { From eli.friedman at gmail.com Fri Jul 8 18:44:24 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 8 Jul 2011 16:44:24 -0700 Subject: [llvm-commits] [llvm] r134768 - in /llvm/trunk/lib/Target/X86: MCTargetDesc/X86MCTargetDesc.cpp X86Subtarget.cpp In-Reply-To: References: <20110708230742.CBB092A6C12C@llvm.org> Message-ID: On Fri, Jul 8, 2011 at 4:29 PM, David A. Greene wrote: > Eli Friedman writes: > >> Author: efriedma >> Date: Fri Jul ?8 18:07:42 2011 >> New Revision: 134768 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134768&view=rev >> Log: >> Revert earlier unnecessary hack. ?Make sure we correctly force on 64bit and cmov for 64-bit targets. > > Still broken for unknown (I think) x86 targets. Thanks for pointing that out; r134773. -Eli From stoklund at 2pi.dk Fri Jul 8 19:25:03 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 09 Jul 2011 00:25:03 -0000 Subject: [llvm-commits] [llvm] r134776 - in /llvm/trunk: lib/CodeGen/InlineSpiller.cpp test/CodeGen/X86/reghinting.ll Message-ID: <20110709002503.CF9162A6C12C@llvm.org> Author: stoklund Date: Fri Jul 8 19:25:03 2011 New Revision: 134776 URL: http://llvm.org/viewvc/llvm-project?rev=134776&view=rev Log: Hoist spills within a basic block. Try to move spills as early as possible in their basic block. This can help eliminate interferences by shortening the live range being spilled. This fixes PR10221. Added: llvm/trunk/test/CodeGen/X86/reghinting.ll Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=134776&r1=134775&r2=134776&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Jul 8 19:25:03 2011 @@ -303,7 +303,8 @@ // Best spill candidate seen so far. This must dominate UseVNI. SibValueInfo SVI(UseReg, UseVNI); MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def); - unsigned SpillDepth = Loops.getLoopDepth(UseMBB); + MachineBasicBlock *SpillMBB = UseMBB; + unsigned SpillDepth = Loops.getLoopDepth(SpillMBB); bool SeenOrigPHI = false; // Original PHI met. do { @@ -316,15 +317,39 @@ // Is this value a better spill candidate? if (!isRegToSpill(Reg)) { MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def); - if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) { + if (MBB == SpillMBB) { + // This is an alternative def earlier in the same MBB. + // Hoist the spill as far as possible in SpillMBB. This can ease + // register pressure: + // + // x = def + // y = use x + // s = copy x + // + // Hoisting the spill of s to immediately after the def removes the + // interference between x and y: + // + // x = def + // spill x + // y = use x + // + if (VNI->def < SVI.SpillVNI->def) { + DEBUG(dbgs() << " hoist in BB#" << MBB->getNumber() << ": " + << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def + << '\n'); + SVI.SpillReg = Reg; + SVI.SpillVNI = VNI; + } + } else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) { // This is a valid spill location dominating UseVNI. // Prefer to spill at a smaller loop depth. unsigned Depth = Loops.getLoopDepth(MBB); - if (Depth < SpillDepth) { + if (Depth <= SpillDepth) { DEBUG(dbgs() << " spill depth " << Depth << ": " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def << '\n'); SVI.SpillReg = Reg; SVI.SpillVNI = VNI; + SpillMBB = MBB; SpillDepth = Depth; } } Added: llvm/trunk/test/CodeGen/X86/reghinting.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/reghinting.ll?rev=134776&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/reghinting.ll (added) +++ llvm/trunk/test/CodeGen/X86/reghinting.ll Fri Jul 8 19:25:03 2011 @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s +; PR10221 + +;; The registers %x and %y must both spill across the finit call. +;; Check that they are spilled early enough that not copies are needed for the +;; fadd and fpext. + +; CHECK: pr10221 +; CHECK-NOT: movaps +; CHECK: movss +; CHECK-NEXT: movss +; CHECK-NEXT: addss +; CHECK-NEXT: cvtss2sd +; CHECK-NEXT: finit + +define i32 @pr10221(float %x, float %y, i8** nocapture %_retval) nounwind uwtable ssp { +entry: + %add = fadd float %x, %y + %conv = fpext float %add to double + %call = tail call i32 @finit(double %conv) nounwind + %tobool = icmp eq i32 %call, 0 + br i1 %tobool, label %return, label %if.end + +if.end: ; preds = %entry + tail call void @foo(float %x, float %y) nounwind + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ 0, %if.end ], [ 5, %entry ] + ret i32 %retval.0 +} + +declare i32 @finit(double) + +declare void @foo(float, float) From lhames at gmail.com Fri Jul 8 19:25:11 2011 From: lhames at gmail.com (Lang Hames) Date: Sat, 09 Jul 2011 00:25:11 -0000 Subject: [llvm-commits] [llvm] r134777 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110709002511.822302A6C12C@llvm.org> Author: lhames Date: Fri Jul 8 19:25:11 2011 New Revision: 134777 URL: http://llvm.org/viewvc/llvm-project?rev=134777&view=rev Log: Added recognition for signed add/sub/mul with overflow intrinsics to GVN as per Chris and Frits suggestion. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=134777&r1=134776&r2=134777&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Fri Jul 8 19:25:11 2011 @@ -173,12 +173,15 @@ // is we'll synthesize a semantically equivalent expression instead on // an extract value expression. switch (I->getIntrinsicID()) { + case Intrinsic::sadd_with_overflow: case Intrinsic::uadd_with_overflow: e.opcode = Instruction::Add; break; + case Intrinsic::ssub_with_overflow: case Intrinsic::usub_with_overflow: e.opcode = Instruction::Sub; break; + case Intrinsic::smul_with_overflow: case Intrinsic::umul_with_overflow: e.opcode = Instruction::Mul; break; From lhames at gmail.com Fri Jul 8 19:36:55 2011 From: lhames at gmail.com (Lang Hames) Date: Sat, 09 Jul 2011 00:36:55 -0000 Subject: [llvm-commits] [llvm] r134778 - /llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Message-ID: <20110709003655.286AE2A6C12C@llvm.org> Author: lhames Date: Fri Jul 8 19:36:54 2011 New Revision: 134778 URL: http://llvm.org/viewvc/llvm-project?rev=134778&view=rev Log: Added test cases for GVN signed intrinsics recognition, r134777. Modified: llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Modified: llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll?rev=134778&r1=134777&r2=134778&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll (original) +++ llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Fri Jul 8 19:36:54 2011 @@ -39,9 +39,47 @@ ; CHECK-NOT: mul1 ; CHECK: ret +define i64 @test4(i64 %a, i64 %b) nounwind ssp { +entry: + %sadd = tail call %0 @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) + %sadd.0 = extractvalue %0 %sadd, 0 + %add1 = add i64 %a, %b + ret i64 %add1 +} + +; CHECK: @test4 +; CHECK-NOT: add1 +; CHECK: ret + +define i64 @test5(i64 %a, i64 %b) nounwind ssp { +entry: + %ssub = tail call %0 @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) + %ssub.0 = extractvalue %0 %ssub, 0 + %sub1 = sub i64 %a, %b + ret i64 %sub1 +} + +; CHECK: @test5 +; CHECK-NOT: sub1 +; CHECK: ret + +define i64 @test6(i64 %a, i64 %b) nounwind ssp { +entry: + %smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + %smul.0 = extractvalue %0 %smul, 0 + %mul1 = mul i64 %a, %b + ret i64 %mul1 +} + +; CHECK: @test6 +; CHECK-NOT: mul1 +; CHECK: ret declare void @exit(i32) noreturn declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone declare %0 @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone declare %0 @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone +declare %0 @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone +declare %0 @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone +declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone From lhames at gmail.com Fri Jul 8 19:49:21 2011 From: lhames at gmail.com (Lang Hames) Date: Sat, 9 Jul 2011 10:49:21 +1000 Subject: [llvm-commits] [llvm] r134677 - in /llvm/trunk: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll In-Reply-To: References: <20110708015054.CBE162A6C12C@llvm.org> Message-ID: Added in r134777. Thanks for the suggestion! - Lang. On Fri, Jul 8, 2011 at 4:29 PM, Frits van Bommel wrote: > On 8 July 2011 03:50, Lang Hames wrote: > > + switch (I->getIntrinsicID()) { > > + case Intrinsic::uadd_with_overflow: > > + e.opcode = Instruction::Add; > > + break; > > + case Intrinsic::usub_with_overflow: > > + e.opcode = Instruction::Sub; > > + break; > > + case Intrinsic::umul_with_overflow: > > + e.opcode = Instruction::Mul; > > + break; > > + default: > > + break; > > + } > > Still no signed variants? They should be as easy as duplicating each > case line and changing a single character on each of the three new > lines ('s/::u/::s/'). (Plus some extra texts, of course) > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110709/9db37d9f/attachment.html From stoklund at 2pi.dk Fri Jul 8 20:02:44 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 09 Jul 2011 01:02:44 -0000 Subject: [llvm-commits] [llvm] r134782 - /llvm/trunk/lib/CodeGen/InlineSpiller.cpp Message-ID: <20110709010244.84C322A6C12C@llvm.org> Author: stoklund Date: Fri Jul 8 20:02:44 2011 New Revision: 134782 URL: http://llvm.org/viewvc/llvm-project?rev=134782&view=rev Log: Oops, didn't mean to commit that. Spills should be hoisted out of loops, but we don't want to hoist them to dominating blocks at the same loop depth. That could cause the spills to be executed more often. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=134782&r1=134781&r2=134782&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Jul 8 20:02:44 2011 @@ -344,7 +344,7 @@ // This is a valid spill location dominating UseVNI. // Prefer to spill at a smaller loop depth. unsigned Depth = Loops.getLoopDepth(MBB); - if (Depth <= SpillDepth) { + if (Depth < SpillDepth) { DEBUG(dbgs() << " spill depth " << Depth << ": " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def << '\n'); SVI.SpillReg = Reg; From raghesh.a at gmail.com Fri Jul 8 22:10:23 2011 From: raghesh.a at gmail.com (Raghesh Aloor) Date: Sat, 09 Jul 2011 03:10:23 -0000 Subject: [llvm-commits] [polly] r134786 - in /polly/trunk/lib/Exchange: OpenScopExporter.cpp OpenScopImporter.cpp Message-ID: <20110709031023.19A302A6C12C@llvm.org> Author: raghesh Date: Fri Jul 8 22:10:22 2011 New Revision: 134786 URL: http://llvm.org/viewvc/llvm-project?rev=134786&view=rev Log: Fix for broken build isl/map.h is included in OpenScopExporter.cpp and OpenScopImporter.cpp Modified: polly/trunk/lib/Exchange/OpenScopExporter.cpp polly/trunk/lib/Exchange/OpenScopImporter.cpp Modified: polly/trunk/lib/Exchange/OpenScopExporter.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/OpenScopExporter.cpp?rev=134786&r1=134785&r2=134786&view=diff ============================================================================== --- polly/trunk/lib/Exchange/OpenScopExporter.cpp (original) +++ polly/trunk/lib/Exchange/OpenScopExporter.cpp Fri Jul 8 22:10:22 2011 @@ -25,6 +25,7 @@ #include "openscop/openscop.h" #include "stdio.h" +#include "isl/map.h" #include "isl/set.h" #include "isl/constraint.h" Modified: polly/trunk/lib/Exchange/OpenScopImporter.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/OpenScopImporter.cpp?rev=134786&r1=134785&r2=134786&view=diff ============================================================================== --- polly/trunk/lib/Exchange/OpenScopImporter.cpp (original) +++ polly/trunk/lib/Exchange/OpenScopImporter.cpp Fri Jul 8 22:10:22 2011 @@ -26,6 +26,7 @@ #define OPENSCOP_INT_T_IS_MP #include "openscop/openscop.h" +#include "isl/map.h" #include "isl/set.h" #include "isl/constraint.h" From evan.cheng at apple.com Sat Jul 9 00:47:47 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 09 Jul 2011 05:47:47 -0000 Subject: [llvm-commits] [llvm] r134795 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/AsmParser/ lib/Target/X86/MCTargetDesc/ ... Message-ID: <20110709054747.65E8A2A6C12C@llvm.org> Author: evancheng Date: Sat Jul 9 00:47:46 2011 New Revision: 134795 URL: http://llvm.org/viewvc/llvm-project?rev=134795&view=rev Log: Change createAsmParser to take a MCSubtargetInfo instead of triple, CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h llvm/trunk/include/llvm/MC/SubtargetFeature.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/include/llvm/Target/TargetSelect.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCSubtargetInfo.cpp llvm/trunk/lib/MC/SubtargetFeature.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Sat Jul 9 00:47:46 2011 @@ -34,7 +34,8 @@ const unsigned *ForwardingPathes; // Forwarding pathes unsigned NumFeatures; // Number of processor features unsigned NumProcs; // Number of processors - uint64_t FeatureBits; // Feature bits for current CPU + + uint64_t FeatureBits; // Feature bits for current CPU + FS public: void InitMCSubtargetInfo(StringRef CPU, StringRef FS, @@ -54,6 +55,14 @@ /// feature string), recompute and return feature bits. uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS); + /// ToggleFeature - Toggle a feature and returns the re-computed feature + /// bits. This version does not change the implied bits. + uint64_t ToggleFeature(uint64_t FB); + + /// ToggleFeature - Toggle a feature and returns the re-computed feature + /// bits. This version will also change all implied bits. + uint64_t ToggleFeature(StringRef FS); + /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU. /// InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const; Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Sat Jul 9 00:47:46 2011 @@ -82,6 +82,12 @@ /// Adding Features. void AddFeature(const StringRef String, bool IsEnabled = true); + /// ToggleFeature - Toggle a feature and returns the newly updated feature + /// bits. + uint64_t ToggleFeature(uint64_t Bits, const StringRef String, + const SubtargetFeatureKV *FeatureTable, + size_t FeatureTableSize); + /// Get feature bits of a CPU. uint64_t getFeatureBits(const StringRef CPU, const SubtargetFeatureKV *CPUTable, Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Sat Jul 9 00:47:46 2011 @@ -36,6 +36,7 @@ class MCInstrInfo; class MCRegisterInfo; class MCStreamer; + class MCSubtargetInfo; class TargetAsmBackend; class TargetAsmLexer; class TargetAsmParser; @@ -69,6 +70,9 @@ StringRef TT); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); + typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, + StringRef CPU, + StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, const std::string &CPU, @@ -79,8 +83,7 @@ const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT, - StringRef CPU, StringRef Features, + typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI, MCAsmParser &P); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, @@ -137,6 +140,10 @@ /// if registered. MCRegInfoCtorFnTy MCRegInfoCtorFn; + /// MCSubtargetInfoCtorFn - Constructor function for this target's + /// MCSubtargetInfo, if registered. + MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; + /// TargetMachineCtorFn - Construction function for this target's /// TargetMachine, if registered. TargetMachineCtorTy TargetMachineCtorFn; @@ -262,6 +269,22 @@ return MCRegInfoCtorFn(); } + /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. + /// + /// \arg Triple - This argument is used to determine the target machine + /// feature set; it should always be provided. Generally this should be + /// either the target triple from the module, or the target triple of the + /// host if that does not exist. + /// \arg CPU - This specifies the name of the target CPU. + /// \arg Features - This specifies the string representation of the + /// additional target features. + MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, + StringRef Features) const { + if (!MCSubtargetInfoCtorFn) + return 0; + return MCSubtargetInfoCtorFn(Triple, CPU, Features); + } + /// createTargetMachine - Create a target specific machine implementation /// for the specified \arg Triple. /// @@ -299,12 +322,11 @@ /// /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. - TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU, - StringRef Features, + TargetAsmParser *createAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser) const { if (!AsmParserCtorFn) return 0; - return AsmParserCtorFn(Triple, CPU, Features, Parser); + return AsmParserCtorFn(STI, Parser); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -506,6 +528,22 @@ T.MCRegInfoCtorFn = Fn; } + /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for + /// the given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCSubtargetInfo for the target. + static void RegisterMCSubtargetInfo(Target &T, + Target::MCSubtargetInfoCtorFnTy Fn) { + // Ignore duplicate registration. + if (!T.MCSubtargetInfoCtorFn) + T.MCSubtargetInfoCtorFn = Fn; + } + /// RegisterTargetMachine - Register a TargetMachine implementation for the /// given target. /// @@ -782,6 +820,40 @@ } }; + /// RegisterMCSubtargetInfo - Helper template for registering a target + /// subtarget info implementation. This invokes the static "Create" method + /// on the class to actually do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCSubtargetInfo X(TheFooTarget); + /// } + template + struct RegisterMCSubtargetInfo { + RegisterMCSubtargetInfo(Target &T) { + TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); + } + private: + static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, + StringRef FS) { + return new MCSubtargetInfoImpl(); + } + }; + + /// RegisterMCSubtargetInfoFn - Helper template for registering a target + /// subtarget info implementation. This invokes the specified function to + /// do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); + /// } + struct RegisterMCSubtargetInfoFn { + RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) { + TargetRegistry::RegisterMCSubtargetInfo(T, Fn); + } + }; + /// RegisterTargetMachine - Helper template for registering a target machine /// implementation, for use in the target machine initialization /// function. Usage: @@ -859,9 +931,8 @@ } private: - static TargetAsmParser *Allocator(StringRef TT, StringRef CPU, - StringRef FS, MCAsmParser &P) { - return new AsmParserImpl(TT, CPU, FS, P); + static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) { + return new AsmParserImpl(STI, P); } }; Modified: llvm/trunk/include/llvm/Target/TargetSelect.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Target/TargetSelect.h Sat Jul 9 00:47:46 2011 @@ -26,6 +26,10 @@ #define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(); #include "llvm/Config/Targets.def" +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCSubtargetInfo(); +#include "llvm/Config/Targets.def" + // Declare all of the available assembly printer initialization functions. #define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter(); #include "llvm/Config/AsmPrinters.def" @@ -35,7 +39,8 @@ #include "llvm/Config/AsmParsers.def" // Declare all of the available disassembler initialization functions. -#define LLVM_DISASSEMBLER(TargetName) void LLVMInitialize##TargetName##Disassembler(); +#define LLVM_DISASSEMBLER(TargetName) \ + void LLVMInitialize##TargetName##Disassembler(); #include "llvm/Config/Disassemblers.def" } @@ -63,6 +68,16 @@ #include "llvm/Config/Targets.def" } + /// InitializeAllMCSubtargetInfos - The main program should call this function + /// if it wants access to all available subtarget infos for targets that LLVM + /// is configured to support, to make them available via the TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCSubtargetInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo(); +#include "llvm/Config/Targets.def" + } + /// InitializeAllAsmPrinters - The main program should call this function if /// it wants all asm printers that LLVM is configured to support, to make them /// available via the TargetRegistry. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sat Jul 9 00:47:46 2011 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetMachine.h" @@ -112,11 +113,15 @@ OutContext, OutStreamer, *MAI)); - OwningPtr - TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), - TM.getTargetCPU(), - TM.getTargetFeatureString(), - *Parser)); + // FIXME: It would be nice if we can avoid createing a new instance of + // MCSubtargetInfo here given TargetSubtargetInfo is available. However, + // we have to watch out for asm directives which can change subtarget + // state. e.g. .code 16, .code 32. + OwningPtr + STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(), + TM.getTargetCPU(), + TM.getTargetFeatureString())); + OwningPtr TAP(TM.getTarget().createAsmParser(*STI, *Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Sat Jul 9 00:47:46 2011 @@ -23,6 +23,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -373,7 +374,8 @@ *AsmInfo)); StringRef triple = tripleFromArch(Key.Arch); - OwningPtr TargetParser(Tgt->createAsmParser(triple, "", "", + OwningPtr STI(Tgt->createMCSubtargetInfo(triple, "", "")); + OwningPtr TargetParser(Tgt->createAsmParser(*STI, *genericParser)); AsmToken OpcodeToken = genericParser->Lex(); Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original) +++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Sat Jul 9 00:47:46 2011 @@ -48,6 +48,23 @@ return FeatureBits; } +/// ToggleFeature - Toggle a feature and returns the re-computed feature +/// bits. This version does not change the implied bits. +uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { + FeatureBits ^= FB; + return FeatureBits; +} + +/// ToggleFeature - Toggle a feature and returns the re-computed feature +/// bits. This version will also change all implied bits. +uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { + SubtargetFeatures Features; + FeatureBits = Features.ToggleFeature(FeatureBits, FS, + ProcFeatures, NumFeatures); + return FeatureBits; +} + + InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { assert(ProcItins && "Instruction itineraries information not available!"); Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Sat Jul 9 00:47:46 2011 @@ -224,6 +224,38 @@ } } +/// ToggleFeature - Toggle a feature and returns the newly updated feature +/// bits. +uint64_t +SubtargetFeatures::ToggleFeature(uint64_t Bits, const StringRef Feature, + const SubtargetFeatureKV *FeatureTable, + size_t FeatureTableSize) { + // Find feature in table. + const SubtargetFeatureKV *FeatureEntry = + Find(StripFlag(Feature), FeatureTable, FeatureTableSize); + // If there is a match + if (FeatureEntry) { + if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) { + Bits &= ~FeatureEntry->Value; + + // For each feature that implies this, clear it. + ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); + } else { + Bits |= FeatureEntry->Value; + + // For each feature that this implies, set it. + SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); + } + } else { + errs() << "'" << Feature + << "' is not a recognized feature for this target" + << " (ignoring feature)\n"; + } + + return Bits; +} + + /// getFeatureBits - Get feature bits a CPU. /// uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU, Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Jul 9 00:47:46 2011 @@ -41,12 +41,8 @@ class ARMOperand; class ARMAsmParser : public TargetAsmParser { + MCSubtargetInfo &STI; MCAsmParser &Parser; - /// STI, ARM_STI, Thumb_STI - Subtarget info for ARM and Thumb modes. STI - /// points to either ARM_STI or Thumb_STI depending on the mode. - const MCSubtargetInfo *STI; - OwningPtr ARM_STI; - OwningPtr Thumb_STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -91,14 +87,14 @@ bool isThumb() const { // FIXME: Can tablegen auto-generate this? - return (STI->getFeatureBits() & ARM::ModeThumb) != 0; + return (STI.getFeatureBits() & ARM::ModeThumb) != 0; } bool isThumbOne() const { - return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; + return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; } void SwitchMode() { - STI = isThumb() ? ARM_STI.get() : Thumb_STI.get(); - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); + setAvailableFeatures(FB); } /// @name Auto-generated Match Functions @@ -135,27 +131,12 @@ const SmallVectorImpl &); public: - ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) - : TargetAsmParser(), Parser(_Parser) { + ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) + : TargetAsmParser(), STI(_STI), Parser(_Parser) { MCAsmParserExtension::Initialize(_Parser); - STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); - // FIXME: Design a better way to create two subtargets with only difference - // being a feature change. - if (isThumb()) { - Thumb_STI.reset(STI); - assert(TT.startswith("thumb") && "Unexpected Triple string for Thumb!"); - Twine ARM_TT = "arm" + TT.substr(5); - ARM_STI.reset(ARM_MC::createARMMCSubtargetInfo(ARM_TT.str(), CPU, FS)); - } else { - ARM_STI.reset(STI); - assert(TT.startswith("arm") && "Unexpected Triple string for ARM!"); - Twine Thumb_TT = "thumb" + TT.substr(3); - Thumb_STI.reset(ARM_MC::createARMMCSubtargetInfo(Thumb_TT.str(),CPU, FS)); - } - // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, @@ -2237,10 +2218,12 @@ Parser.Lex(); if (Val == 16) { - if (!isThumb()) SwitchMode(); + if (!isThumb()) + SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); } else { - if (isThumb()) SwitchMode(); + if (isThumb()) + SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Sat Jul 9 00:47:46 2011 @@ -112,17 +112,18 @@ // Force static initialization. extern "C" void LLVMInitializeARMMCInstrInfo() { - RegisterMCInstrInfo X(TheARMTarget); - RegisterMCInstrInfo Y(TheThumbTarget); - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); } extern "C" void LLVMInitializeARMMCRegInfo() { - RegisterMCRegInfo X(TheARMTarget); - RegisterMCRegInfo Y(TheThumbTarget); - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); } + +extern "C" void LLVMInitializeARMMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, + ARM_MC::createARMMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, + ARM_MC::createARMMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -13,6 +13,7 @@ #include "AlphaSubtarget.h" #include "Alpha.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -35,3 +36,15 @@ // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); } + +MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitAlphaMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeAlphaMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget, + createAlphaMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "BlackfinSubtarget.h" +#include "Blackfin.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -42,3 +44,15 @@ // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitBlackfinMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget, + createBlackfinMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Sat Jul 9 00:47:46 2011 @@ -37,6 +37,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetRegistry.h" @@ -61,6 +62,10 @@ RegisterTargetMachine X(TheCBackendTarget); } +extern "C" void LLVMInitializeCBackendMCSubtargetInfo() { + RegisterMCSubtargetInfo X(TheCBackendTarget); +} + namespace { class CBEMCAsmInfo : public MCAsmInfo { public: Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Sat Jul 9 00:47:46 2011 @@ -54,3 +54,9 @@ ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def ) + +# Produce llvm/Config/MCSubtargetInfos.def +configure_file( + ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in + ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def + ) Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -14,6 +14,7 @@ #include "SPUSubtarget.h" #include "SPU.h" #include "SPURegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" #define GET_SUBTARGETINFO_ENUM @@ -65,3 +66,15 @@ CriticalPathRCs.push_back(&SPU::VECREGRegClass); return OptLevel >= CodeGenOpt::Default; } + +MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSPUMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget, + createSPUMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Sat Jul 9 00:47:46 2011 @@ -23,6 +23,7 @@ #include "llvm/Pass.h" #include "llvm/PassManager.h" #include "llvm/TypeSymbolTable.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" @@ -75,6 +76,10 @@ RegisterTargetMachine X(TheCppBackendTarget); } +extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() { + RegisterMCSubtargetInfo X(TheCppBackendTarget); +} + namespace { typedef std::vector TypeList; typedef std::map TypeMap; Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Sat Jul 9 00:47:46 2011 @@ -63,8 +63,7 @@ public: - MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS, - MCAsmParser &_Parser) + MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) : TargetAsmParser(), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -15,6 +15,7 @@ #include "MBlaze.h" #include "MBlazeRegisterInfo.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -62,3 +63,15 @@ CriticalPathRCs.push_back(&MBlaze::GPRRegClass); return HasItin && OptLevel >= CodeGenOpt::Default; } + +MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMBlazeMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget, + createMBlazeMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Sat Jul 9 00:47:46 2011 @@ -13,6 +13,7 @@ #include "MSP430Subtarget.h" #include "MSP430.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -31,3 +32,15 @@ // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMSP430MCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMSP430MCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, + createMSP430MCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -13,6 +13,7 @@ #include "MipsSubtarget.h" #include "Mips.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -61,3 +62,15 @@ HasCondMov = true; } } + +MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMipsMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMipsMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, + createMipsMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -12,7 +12,9 @@ //===----------------------------------------------------------------------===// #include "PTXSubtarget.h" +#include "PTX.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -64,3 +66,18 @@ case PTX_VERSION_2_3: return "2.3"; } } + + +MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPTXMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePTXMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target, + createPTXMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target, + createPTXMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -15,6 +15,7 @@ #include "PPC.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegistry.h" #include #define GET_SUBTARGETINFO_ENUM @@ -140,3 +141,17 @@ return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage() || isDecl; } + +MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPPCMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePowerPCMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target, + createPPCMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target, + createPPCMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "SparcSubtarget.h" +#include "Sparc.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -42,3 +44,15 @@ // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSparcMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSparcMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, + createSparcMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -15,6 +15,7 @@ #include "SystemZ.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -53,3 +54,15 @@ return false; } + +MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSystemZMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSystemZMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, + createSystemZMCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Jul 9 00:47:46 2011 @@ -37,8 +37,8 @@ struct X86Operand; class X86ATTAsmParser : public TargetAsmParser { + MCSubtargetInfo &STI; MCAsmParser &Parser; - OwningPtr STI; private: MCAsmParser &getParser() const { return Parser; } @@ -66,7 +66,7 @@ bool is64Bit() { // FIXME: Can tablegen auto-generate this? - return (STI->getFeatureBits() & X86::Mode64Bit) != 0; + return (STI.getFeatureBits() & X86::Mode64Bit) != 0; } /// @name Auto-generated Matcher Functions @@ -78,13 +78,11 @@ /// } public: - X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS, - MCAsmParser &parser) - : TargetAsmParser(), Parser(parser), - STI(X86_MC::createX86MCSubtargetInfo(TT, CPU, FS)) { + X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser) + : TargetAsmParser(), STI(sti), Parser(parser) { // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Sat Jul 9 00:47:46 2011 @@ -145,17 +145,19 @@ // Force static initialization. extern "C" void LLVMInitializeX86MCInstrInfo() { - RegisterMCInstrInfo X(TheX86_32Target); - RegisterMCInstrInfo Y(TheX86_64Target); - TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); } extern "C" void LLVMInitializeX86MCRegInfo() { - RegisterMCRegInfo X(TheX86_32Target); - RegisterMCRegInfo Y(TheX86_64Target); - TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); } + + +extern "C" void LLVMInitializeX86MCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, + X86_MC::createX86MCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, + X86_MC::createX86MCSubtargetInfo); +} Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Sat Jul 9 00:47:46 2011 @@ -13,6 +13,7 @@ #include "XCoreSubtarget.h" #include "XCore.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -27,3 +28,16 @@ : XCoreGenSubtargetInfo(TT, CPU, FS) { } + + +MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitXCoreMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeXCoreMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, + createXCoreMCSubtargetInfo); +} Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Sat Jul 9 00:47:46 2011 @@ -201,6 +201,7 @@ // Initialize targets first, so that --version shows registered targets. InitializeAllTargets(); + InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sat Jul 9 00:47:46 2011 @@ -19,6 +19,7 @@ #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetAsmBackend.h" #include "llvm/Target/TargetAsmParser.h" @@ -340,6 +341,9 @@ TM->getTargetLowering()->getObjFileLowering(); const_cast(TLOF).Initialize(Ctx, *TM); + OwningPtr + STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); + // FIXME: There is a bit of code duplication with addPassesToEmitFile. if (FileType == OFT_AssemblyFile) { MCInstPrinter *IP = @@ -371,8 +375,7 @@ OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI)); - OwningPtr - TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser)); + OwningPtr TAP(TheTarget->createAsmParser(*STI, *Parser)); if (!TAP) { errs() << ProgName << ": error: this target does not support assembly parsing.\n"; @@ -448,6 +451,7 @@ llvm::InitializeAllTargetInfos(); // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); + llvm::InitializeAllMCSubtargetInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134795&r1=134794&r2=134795&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Sat Jul 9 00:47:46 2011 @@ -35,6 +35,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetAsmParser.h" @@ -618,11 +619,12 @@ OwningPtr Parser(createMCAsmParser(_target->getTarget(), SrcMgr, Context, *Streamer, *_target->getMCAsmInfo())); + OwningPtr STI(_target->getTarget(). + createMCSubtargetInfo(_target->getTargetTriple(), + _target->getTargetCPU(), + _target->getTargetFeatureString())); OwningPtr - TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(), - _target->getTargetCPU(), - _target->getTargetFeatureString(), - *Parser.get())); + TAP(_target->getTarget().createAsmParser(*STI, *Parser.get())); Parser->setTargetParser(*TAP); int Res = Parser->Run(false); if (Res) From geek4civic at gmail.com Sat Jul 9 01:20:08 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 9 Jul 2011 15:20:08 +0900 Subject: [llvm-commits] [llvm] r134795 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ Message-ID: > Modified: llvm/trunk/lib/Target/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134795&r1=134794&r2=134795&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CMakeLists.txt (original) > +++ llvm/trunk/lib/Target/CMakeLists.txt Sat Jul ?9 00:47:46 2011 > @@ -54,3 +54,9 @@ > ? ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in > ? ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def > ? ) > + > +# Produce llvm/Config/MCSubtargetInfos.def > +configure_file( > + ?${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in > + ?${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def > + ?) Who needs MCSubtargetInfos.def? or Where is MCSubtargetInfos.def.in ? ...Takumi From evan.cheng at apple.com Sat Jul 9 01:26:27 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 09 Jul 2011 06:26:27 -0000 Subject: [llvm-commits] [llvm] r134800 - /llvm/trunk/lib/Target/CMakeLists.txt Message-ID: <20110709062627.4514B2A6C12C@llvm.org> Author: evancheng Date: Sat Jul 9 01:26:27 2011 New Revision: 134800 URL: http://llvm.org/viewvc/llvm-project?rev=134800&view=rev Log: Revert accidental commit. Modified: llvm/trunk/lib/Target/CMakeLists.txt Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134800&r1=134799&r2=134800&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Sat Jul 9 01:26:27 2011 @@ -54,9 +54,3 @@ ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def ) - -# Produce llvm/Config/MCSubtargetInfos.def -configure_file( - ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in - ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def - ) From evan.cheng at apple.com Sat Jul 9 01:27:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Jul 2011 23:27:37 -0700 Subject: [llvm-commits] [llvm] r134795 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ In-Reply-To: References: Message-ID: <3896605A-3742-43B9-A809-6A2B363A95A3@apple.com> Sorry, fixed. Evan On Jul 8, 2011, at 11:20 PM, NAKAMURA Takumi wrote: >> Modified: llvm/trunk/lib/Target/CMakeLists.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134795&r1=134794&r2=134795&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/CMakeLists.txt (original) >> +++ llvm/trunk/lib/Target/CMakeLists.txt Sat Jul 9 00:47:46 2011 >> @@ -54,3 +54,9 @@ >> ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in >> ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def >> ) >> + >> +# Produce llvm/Config/MCSubtargetInfos.def >> +configure_file( >> + ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in >> + ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def >> + ) > > Who needs MCSubtargetInfos.def? or Where is MCSubtargetInfos.def.in ? > > ...Takumi From geek4civic at gmail.com Sat Jul 9 02:19:50 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 09 Jul 2011 07:19:50 -0000 Subject: [llvm-commits] [llvm] r134809 - /llvm/trunk/utils/lit/lit/LitConfig.py Message-ID: <20110709071950.3DB782A6C12C@llvm.org> Author: chapuni Date: Sat Jul 9 02:19:50 2011 New Revision: 134809 URL: http://llvm.org/viewvc/llvm-project?rev=134809&view=rev Log: lit/LitConfig.py: Demote Win32 message "Unable to find 'bash.exe'" from Warning to Note. Modified: llvm/trunk/utils/lit/lit/LitConfig.py Modified: llvm/trunk/utils/lit/lit/LitConfig.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/LitConfig.py?rev=134809&r1=134808&r2=134809&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/LitConfig.py (original) +++ llvm/trunk/utils/lit/lit/LitConfig.py Sat Jul 9 02:19:50 2011 @@ -96,7 +96,7 @@ # bash self.bashPath = Util.which('bash', dir) if self.bashPath is None: - self.warning("Unable to find 'bash.exe'.") + self.note("Unable to find 'bash.exe'.") self.bashPath = '' return dir From geek4civic at gmail.com Sat Jul 9 03:41:21 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 09 Jul 2011 08:41:21 -0000 Subject: [llvm-commits] [llvm] r134812 - in /llvm/trunk/lib/Support/Windows: DynamicLibrary.inc explicit_symbols.inc Message-ID: <20110709084121.0DB672A6C12C@llvm.org> Author: chapuni Date: Sat Jul 9 03:41:20 2011 New Revision: 134812 URL: http://llvm.org/viewvc/llvm-project?rev=134812&view=rev Log: Windows/DynamicLibrary.inc: Fix trivial warnings. Thanks to John Myers! Modified: llvm/trunk/lib/Support/Windows/DynamicLibrary.inc llvm/trunk/lib/Support/Windows/explicit_symbols.inc Modified: llvm/trunk/lib/Support/Windows/DynamicLibrary.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/DynamicLibrary.inc?rev=134812&r1=134811&r2=134812&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/DynamicLibrary.inc (original) +++ llvm/trunk/lib/Support/Windows/DynamicLibrary.inc Sat Jul 9 03:41:20 2011 @@ -115,7 +115,7 @@ E = OpenedHandles.end(); I != E; ++I) { FARPROC ptr = GetProcAddress((HMODULE)*I, symbolName); if (ptr) { - return (void *) ptr; + return (void *)(intptr_t)ptr; } } Modified: llvm/trunk/lib/Support/Windows/explicit_symbols.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/explicit_symbols.inc?rev=134812&r1=134811&r2=134812&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/explicit_symbols.inc (original) +++ llvm/trunk/lib/Support/Windows/explicit_symbols.inc Sat Jul 9 03:41:20 2011 @@ -2,7 +2,7 @@ #ifdef HAVE__ALLOCA EXPLICIT_SYMBOL(_alloca) - EXPLICIT_SYMBOL2(alloca, _alloca); + EXPLICIT_SYMBOL2(alloca, _alloca) #endif #ifdef HAVE___ALLOCA EXPLICIT_SYMBOL(__alloca) @@ -62,5 +62,5 @@ /* msvcrt */ #if defined(_MSC_VER) - EXPLICIT_SYMBOL2(alloca, _alloca_probe); + EXPLICIT_SYMBOL2(alloca, _alloca_probe) #endif From geek4civic at gmail.com Sat Jul 9 03:42:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 9 Jul 2011 17:42:40 +0900 Subject: [llvm-commits] [PATCH] extra semicolon in lib/Support/Windows/explicit_symbols.inc In-Reply-To: References: Message-ID: 2011/6/15 John Myers : > There is an extra semicolon which needs to be removed in order for LLVM to > compile using cmake+mingw. > Visual Studio and mingw+configure compile fine even without the change. I am sorry to be too late. Applied in r134812. ...Takumi From geek4civic at gmail.com Sat Jul 9 05:22:28 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 09 Jul 2011 10:22:28 -0000 Subject: [llvm-commits] [llvm] r134814 - /llvm/trunk/test/CodeGen/X86/vector.ll Message-ID: <20110709102228.C47682A6C12C@llvm.org> Author: chapuni Date: Sat Jul 9 05:22:28 2011 New Revision: 134814 URL: http://llvm.org/viewvc/llvm-project?rev=134814&view=rev Log: test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts. With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t. It might work even if ">/dev/null" were used. Modified: llvm/trunk/test/CodeGen/X86/vector.ll Modified: llvm/trunk/test/CodeGen/X86/vector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector.ll?rev=134814&r1=134813&r2=134814&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vector.ll (original) +++ llvm/trunk/test/CodeGen/X86/vector.ll Sat Jul 9 05:22:28 2011 @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s -march=x86 -mcpu=i386 > %t -; RUN: llc < %s -march=x86 -mcpu=yonah > %t +; RUN: llc < %s -march=x86 -mcpu=yonah >> %t %d8 = type <8 x double> %f1 = type <1 x float> From joerg at britannica.bec.de Sat Jul 9 05:49:55 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Sat, 9 Jul 2011 12:49:55 +0200 Subject: [llvm-commits] [llvm] r134795 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/AsmParser/ lib/Target/X86/MCTargetDesc/ ... In-Reply-To: <20110709054747.65E8A2A6C12C@llvm.org> References: <20110709054747.65E8A2A6C12C@llvm.org> Message-ID: <20110709104955.GA12099@britannica.bec.de> On Sat, Jul 09, 2011 at 05:47:47AM -0000, Evan Cheng wrote: > Log: > Change createAsmParser to take a MCSubtargetInfo instead of triple, > CPU, and feature string. Parsing some asm directives can change > subtarget state (e.g. .code 16) and it must be reflected in other > modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance > must be shared. Are you sure that e.g. ".code XX" should effect anything outside the asm parser? I think for inline assembly, it should create a warning if the mode at the start and the mode at the end are different, but otherwise it seems like a typical setting that should be constrained to the assembler block. Joerg From sabre at nondot.org Sat Jul 9 11:52:42 2011 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Jul 2011 16:52:42 -0000 Subject: [llvm-commits] [llvm] r134818 - /llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll Message-ID: <20110709165242.477382A6C12C@llvm.org> Author: lattner Date: Sat Jul 9 11:52:42 2011 New Revision: 134818 URL: http://llvm.org/viewvc/llvm-project?rev=134818&view=rev Log: remove a test that doesn't make sense in the new world. Removed: llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll Removed: llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll?rev=134817&view=auto ============================================================================== --- llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll (original) +++ llvm/trunk/test/Linker/2003-10-21-ConflictingTypesTolerance.ll (removed) @@ -1,6 +0,0 @@ -; RUN: llvm-as < %s > %t.out1.bc -; RUN: echo { %M = type \[8 x i32\] external global %M } | llvm-as > %t.out2.bc -; RUN: llvm-link %t.out1.bc %t.out2.bc -S | grep %M | grep \\{ -%M = type { i32 } - - From sabre at nondot.org Sat Jul 9 11:55:16 2011 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Jul 2011 16:55:16 -0000 Subject: [llvm-commits] [llvm] r134819 - in /llvm/trunk/test/Assembler: 2002-01-24-BadSymbolTableAssert.ll 2002-01-24-ValueRefineAbsType.ll 2002-04-05-TypeParsing.ll 2002-05-02-ParseError.ll 2002-07-08-HugePerformanceProblem.ll 2002-07-25-ParserAssertionFailure.ll 2003-06-30-RecursiveTypeProblem.ll 2003-10-04-NotMergingGlobalConstants.ll 2003-12-30-TypeMapInvalidMemory.ll 2008-10-14-NamedTypeOnInteger.ll Message-ID: <20110709165516.BEB112A6C12C@llvm.org> Author: lattner Date: Sat Jul 9 11:55:16 2011 New Revision: 134819 URL: http://llvm.org/viewvc/llvm-project?rev=134819&view=rev Log: remove some crufy old tests that aren't adding much value Removed: llvm/trunk/test/Assembler/2002-01-24-BadSymbolTableAssert.ll llvm/trunk/test/Assembler/2002-01-24-ValueRefineAbsType.ll llvm/trunk/test/Assembler/2002-04-05-TypeParsing.ll llvm/trunk/test/Assembler/2002-05-02-ParseError.ll llvm/trunk/test/Assembler/2002-07-08-HugePerformanceProblem.ll llvm/trunk/test/Assembler/2002-07-25-ParserAssertionFailure.ll llvm/trunk/test/Assembler/2003-06-30-RecursiveTypeProblem.ll llvm/trunk/test/Assembler/2003-10-04-NotMergingGlobalConstants.ll llvm/trunk/test/Assembler/2003-12-30-TypeMapInvalidMemory.ll llvm/trunk/test/Assembler/2008-10-14-NamedTypeOnInteger.ll Removed: llvm/trunk/test/Assembler/2002-01-24-BadSymbolTableAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-01-24-BadSymbolTableAssert.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-01-24-BadSymbolTableAssert.ll (original) +++ llvm/trunk/test/Assembler/2002-01-24-BadSymbolTableAssert.ll (removed) @@ -1,11 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -; This testcase failed due to a bad assertion in SymbolTable.cpp, removed in -; the 1.20 revision. Basically the symbol table assumed that if there was an -; abstract type in the symbol table, [in this case for the entry %foo of type -; void(opaque)* ], that there should have also been named types by now. This -; was obviously not the case here, and this is valid. Assertion disabled. - -%bb = type i32 - -declare void @foo(i32) Removed: llvm/trunk/test/Assembler/2002-01-24-ValueRefineAbsType.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-01-24-ValueRefineAbsType.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-01-24-ValueRefineAbsType.ll (original) +++ llvm/trunk/test/Assembler/2002-01-24-ValueRefineAbsType.ll (removed) @@ -1,23 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -; This testcase used to fail due to a lack of this diff in Value.cpp: -; diff -r1.16 Value.cpp -; 11c11 -; < #include "llvm/Type.h" -; --- -; > #include "llvm/DerivedTypes.h" -; 74c74,76 -; < assert(Ty.get() == (const Type*)OldTy &&"Can't refine anything but my type!"); -; --- -; > assert(Ty.get() == OldTy &&"Can't refine anything but my type!"); -; > if (OldTy == NewTy && !OldTy->isAbstract()) -; > Ty.removeUserFromConcrete(); -; -; This was causing an assertion failure, due to the "foo" Method object never -; releasing it's reference to the opaque %bb value. -; - -%bb = type i32 -%exception_descriptor = type i32 - -declare void @foo(i32) Removed: llvm/trunk/test/Assembler/2002-04-05-TypeParsing.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-04-05-TypeParsing.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-04-05-TypeParsing.ll (original) +++ llvm/trunk/test/Assembler/2002-04-05-TypeParsing.ll (removed) @@ -1,3 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - - %Hosp = type { { \2*, { \2, %Hosp }* }, { \2*, { \2, %Hosp }* } } Removed: llvm/trunk/test/Assembler/2002-05-02-ParseError.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-05-02-ParseError.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-05-02-ParseError.ll (original) +++ llvm/trunk/test/Assembler/2002-05-02-ParseError.ll (removed) @@ -1,7 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -%T = type i32 * - -define %T @test() { - ret %T null -} Removed: llvm/trunk/test/Assembler/2002-07-08-HugePerformanceProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-07-08-HugePerformanceProblem.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-07-08-HugePerformanceProblem.ll (original) +++ llvm/trunk/test/Assembler/2002-07-08-HugePerformanceProblem.ll (removed) @@ -1,67 +0,0 @@ -; This file takes about 48 __MINUTES__ to assemble using as. This is WAY too -; long. The type resolution code needs to be sped up a lot. -; RUN: llvm-as %s -o /dev/null - %ALL_INTERSECTIONS_METHOD = type i32 (%OBJECT*, %RAY*, %ISTACK*)* - %BBOX = type { %BBOX_VECT, %BBOX_VECT } - %BBOX_TREE = type { i16, i16, %BBOX, %BBOX_TREE** } - %BBOX_VECT = type [3 x float] - %BLEND_MAP = type { i16, i16, i16, i32, %BLEND_MAP_ENTRY* } - %BLEND_MAP_ENTRY = type { float, i8, { %COLOUR, %PIGMENT*, %TNORMAL*, %TEXTURE*, %UV_VECT } } - %CAMERA = type { %VECTOR, %VECTOR, %VECTOR, %VECTOR, %VECTOR, %VECTOR, double, double, i32, double, double, i32, double, %TNORMAL* } - %COLOUR = type [5 x float] - %COPY_METHOD = type i8* (%OBJECT*)* - %COUNTER = type { i32, i32 } - %DENSITY_FILE = type { i32, %DENSITY_FILE_DATA* } - %DENSITY_FILE_DATA = type { i32, i8*, i32, i32, i32, i8*** } - %DESTROY_METHOD = type void (%OBJECT*)* - %FILE = type { i32, i8*, i8*, i8, i8, i32, i32, i32 } - %FILE_HANDLE = type { i8*, i32, i32, i32, i32, i8*, %FILE*, i32, i32 (%FILE_HANDLE*, i8*, i32*, i32*, i32, i32)*, void (%FILE_HANDLE*, %COLOUR*, i32)*, i32 (%FILE_HANDLE*, %COLOUR*, i32*)*, void (%IMAGE*, i8*)*, void (%FILE_HANDLE*)* } - %FINISH = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, %BBOX_VECT, %BBOX_VECT } - %FOG = type { i32, double, double, double, %COLOUR, %VECTOR, %TURB*, float, %FOG* } - %FRAME = type { %CAMERA*, i32, i32, i32, %LIGHT_SOURCE*, %OBJECT*, double, double, %COLOUR, %COLOUR, %COLOUR, %IMEDIA*, %FOG*, %RAINBOW*, %SKYSPHERE* } - %FRAMESEQ = type { i32, double, i32, i32, double, i32, i32, double, i32, double, i32, double, i32, i32 } - %IMAGE = type { i32, i32, i32, i32, i32, i16, i16, %VECTOR, float, float, i32, i32, i16, %IMAGE_COLOUR*, { %IMAGE_LINE*, i8** } } - %IMAGE_COLOUR = type { i16, i16, i16, i16, i16 } - %IMAGE_LINE = type { i8*, i8*, i8*, i8* } - %IMEDIA = type { i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, %COLOUR, %COLOUR, %COLOUR, %COLOUR, double, double, double, double*, %PIGMENT*, %IMEDIA* } - %INSIDE_METHOD = type i32 (double*, %OBJECT*)* - %INTERIOR = type { i32, i32, float, float, float, float, float, %IMEDIA* } - %INTERSECTION = type { double, %VECTOR, %VECTOR, %OBJECT*, i32, i32, double, double, i8* } - %INVERT_METHOD = type void (%OBJECT*)* - %ISTACK = type { %ISTACK*, %INTERSECTION*, i32 } - %LIGHT_SOURCE = type { %METHODS*, i32, %OBJECT*, %TEXTURE*, %INTERIOR*, %OBJECT*, %OBJECT*, %BBOX, i32, %OBJECT*, %COLOUR, %VECTOR, %VECTOR, %VECTOR, %VECTOR, %VECTOR, double, double, double, double, double, %LIGHT_SOURCE*, i8, i8, i8, i8, i32, i32, i32, i32, i32, %COLOUR**, %OBJECT*, [6 x %PROJECT_TREE_NODE*] } - %MATRIX = type [4 x %VECTOR_4D] - %METHODS = type { %ALL_INTERSECTIONS_METHOD, %INSIDE_METHOD, %NORMAL_METHOD, %COPY_METHOD, %ROTATE_METHOD, %ROTATE_METHOD, %ROTATE_METHOD, %TRANSFORM_METHOD, %DESTROY_METHOD, %DESTROY_METHOD } - %NORMAL_METHOD = type void (double*, %OBJECT*, %INTERSECTION*)* - %OBJECT = type { %METHODS*, i32, %OBJECT*, %TEXTURE*, %INTERIOR*, %OBJECT*, %OBJECT*, %BBOX, i32 } - %Opts = type { i32, i32, i8, i8, i8, i32, [150 x i8], [150 x i8], [150 x i8], [150 x i8], [150 x i8], double, double, i32, i32, double, double, i32, [25 x i8*], i32, i32, i32, double, double, i32, i32, double, double, double, i32, i32, i32, i32, i32, %FRAMESEQ, double, i32, double, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [150 x i8], %SHELLDATA*, [150 x i8], i32, i32 } - %PIGMENT = type { i16, i16, i16, i32, float, float, float, %WARP*, %TPATTERN*, %BLEND_MAP*, { %DENSITY_FILE*, %IMAGE*, %VECTOR, float, i16, i16, i16, { float, %VECTOR }, %complex.float }, %COLOUR } - %PRIORITY_QUEUE = type { i32, i32, %QELEM* } - %PROJECT = type { i32, i32, i32, i32 } - %PROJECT_QUEUE = type { i32, i32, %PROJECT_TREE_NODE** } - %PROJECT_TREE_NODE = type { i16, %BBOX_TREE*, %PROJECT, i16, %PROJECT_TREE_NODE** } - %QELEM = type { double, %BBOX_TREE* } - %RAINBOW = type { double, double, double, double, double, double, double, %VECTOR, %VECTOR, %VECTOR, %PIGMENT*, %RAINBOW* } - %RAY = type { %VECTOR, %VECTOR, i32, [100 x %INTERIOR*] } - %RAYINFO = type { %VECTOR, %VECTOR, %VECTORI, %VECTORI } - %RGB = type [3 x float] - %ROTATE_METHOD = type void (%OBJECT*, double*, %TRANSFORM*)* - %SCALE_METHOD = type void (%OBJECT*, double*, %TRANSFORM*)* - %SHELLDATA = type { i32, i32, [250 x i8] } - %SKYSPHERE = type { i32, %PIGMENT**, %TRANSFORM* } - %SNGL_VECT = type [3 x float] - %TEXTURE = type { i16, i16, i16, i32, float, float, float, %WARP*, %TPATTERN*, %BLEND_MAP*, { %DENSITY_FILE*, %IMAGE*, %VECTOR, float, i16, i16, i16, { float, %VECTOR }, %complex.float }, %TEXTURE*, %PIGMENT*, %TNORMAL*, %FINISH*, %TEXTURE*, i32 } - %TNORMAL = type { i16, i16, i16, i32, float, float, float, %WARP*, %TPATTERN*, %BLEND_MAP*, { %DENSITY_FILE*, %IMAGE*, %VECTOR, float, i16, i16, i16, { float, %VECTOR }, %complex.float }, float } - %TPATTERN = type { i16, i16, i16, i32, float, float, float, %WARP*, %TPATTERN*, %BLEND_MAP*, { %DENSITY_FILE*, %IMAGE*, %VECTOR, float, i16, i16, i16, { float, %VECTOR }, %complex.float } } - %TRANSFORM = type { %MATRIX, %MATRIX } - %TRANSFORM_METHOD = type void (%OBJECT*, %TRANSFORM*)* - %TRANSLATE_METHOD = type void (%OBJECT*, double*, %TRANSFORM*)* - %TURB = type { i16, %WARP*, %VECTOR, i32, float, float } - %UV_VECT = type [2 x double] - %VECTOR = type [3 x double] - %VECTORI = type [3 x i32] - %VECTOR_4D = type [4 x double] - %WARP = type { i16, %WARP* } - %__FILE = type { i32, i8*, i8*, i8, i8, i32, i32, i32 } - %_h_val = type { [2 x i32], double } - %complex.float = type { float, float } Removed: llvm/trunk/test/Assembler/2002-07-25-ParserAssertionFailure.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-07-25-ParserAssertionFailure.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-07-25-ParserAssertionFailure.ll (original) +++ llvm/trunk/test/Assembler/2002-07-25-ParserAssertionFailure.ll (removed) @@ -1,13 +0,0 @@ -; Make sure we don't get an assertion failure, even though this is a parse -; error -; RUN: not llvm-as %s -o /dev/null |& grep {'@foo' defined with} - -%ty = type void (i32) - -declare %ty* @foo() - -define void @test() { - call %ty* @foo( ) ; <%ty*>:0 [#uses=0] - ret void -} - Removed: llvm/trunk/test/Assembler/2003-06-30-RecursiveTypeProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2003-06-30-RecursiveTypeProblem.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2003-06-30-RecursiveTypeProblem.ll (original) +++ llvm/trunk/test/Assembler/2003-06-30-RecursiveTypeProblem.ll (removed) @@ -1,3 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -%MidFnTy = type void (%MidFnTy*) Removed: llvm/trunk/test/Assembler/2003-10-04-NotMergingGlobalConstants.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2003-10-04-NotMergingGlobalConstants.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2003-10-04-NotMergingGlobalConstants.ll (original) +++ llvm/trunk/test/Assembler/2003-10-04-NotMergingGlobalConstants.ll (removed) @@ -1,6 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -%T = type i32 - at X = global i32* null ; [#uses=0] - at Y = global i32* null ; [#uses=0] - Removed: llvm/trunk/test/Assembler/2003-12-30-TypeMapInvalidMemory.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2003-12-30-TypeMapInvalidMemory.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2003-12-30-TypeMapInvalidMemory.ll (original) +++ llvm/trunk/test/Assembler/2003-12-30-TypeMapInvalidMemory.ll (removed) @@ -1,55 +0,0 @@ -; RUN: not llvm-as %s -o /dev/null |& grep {use of undefined type named 'struct.D_Scope'} -; END. - - at d_reduction_0_dparser_gram = global { - i32 (i8*, i8**, i32, i32, { - %struct.Grammar*, void (\4, %struct.d_loc_t*, i8**)*, %struct.D_Scope*, - void (\4)*, { i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }* (\4, i32, { i32, %struct.d_loc_t, i8*, i8*, - %struct.D_Scope*, void (\9, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }**)*, - void ({ i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, - %struct.Grammar*, %struct.ParseNode_User }*)*, - %struct.d_loc_t, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, - i32 }*)*, - i32 (i8*, i8**, i32, i32, { %struct.Grammar*, - void (\4, %struct.d_loc_t*, i8**)*, %struct.D_Scope*, void (\4)*, { - i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }* (\4, i32, { i32, %struct.d_loc_t, i8*, i8*, - %struct.D_Scope*, void (\9, %struct.d_loc_t*, i8**)*, - %struct.Grammar*, %struct.ParseNode_User }**)*, - void ({ i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }*)*, %struct.d_loc_t, i32, i32, i32, i32, - i32, i32, i32, i32, i32, i32, i32, i32 }*)** } - - { i32 (i8*, i8**, i32, i32, { - %struct.Grammar*, void (\4, %struct.d_loc_t*, i8**)*, - %struct.D_Scope*, void (\4)*, { - i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User - }* (\4, i32, { i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\9, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }**)*, - void ({ i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }*)*, - %struct.d_loc_t, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, - i32, i32 }*)* null, - i32 (i8*, i8**, i32, i32, { - %struct.Grammar*, void (\4, %struct.d_loc_t*, i8**)*, - %struct.D_Scope*, void (\4)*, { i32, %struct.d_loc_t, i8*, i8*, - %struct.D_Scope*, void (\8, %struct.d_loc_t*, i8**)*, - %struct.Grammar*, %struct.ParseNode_User }* (\4, i32, { i32, - %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\9, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }**)*, - void ({ i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, - void (\8, %struct.d_loc_t*, i8**)*, %struct.Grammar*, - %struct.ParseNode_User }*)*, %struct.d_loc_t, i32, i32, i32, - i32, i32, i32, i32, i32, i32, i32, i32, i32 }*)** null - } Removed: llvm/trunk/test/Assembler/2008-10-14-NamedTypeOnInteger.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2008-10-14-NamedTypeOnInteger.ll?rev=134818&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2008-10-14-NamedTypeOnInteger.ll (original) +++ llvm/trunk/test/Assembler/2008-10-14-NamedTypeOnInteger.ll (removed) @@ -1,6 +0,0 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis -; PR2733 - -%t1 = type i32 -%t2 = type { %t1 } - at i1 = constant %t2 { %t1 15 } From sabre at nondot.org Sat Jul 9 11:57:10 2011 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Jul 2011 16:57:10 -0000 Subject: [llvm-commits] [llvm] r134820 - in /llvm/trunk/test: Assembler/ CodeGen/Blackfin/ CodeGen/CBackend/ CodeGen/Generic/ CodeGen/X86/ Feature/ Transforms/SimplifyCFG/ Verifier/ Message-ID: <20110709165710.D44C32A6C12C@llvm.org> Author: lattner Date: Sat Jul 9 11:57:10 2011 New Revision: 134820 URL: http://llvm.org/viewvc/llvm-project?rev=134820&view=rev Log: more tests not making the jump into the brave new world. Removed: llvm/trunk/test/Assembler/2002-02-19-TypeParsing.ll llvm/trunk/test/CodeGen/Blackfin/burg.ll llvm/trunk/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll llvm/trunk/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll llvm/trunk/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll llvm/trunk/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll llvm/trunk/test/CodeGen/Generic/BurgBadRegAlloc.ll llvm/trunk/test/CodeGen/Generic/spillccr.ll llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll llvm/trunk/test/CodeGen/X86/pr2623.ll llvm/trunk/test/CodeGen/X86/twoaddr-remat.ll llvm/trunk/test/Feature/opaquetypes.ll llvm/trunk/test/Transforms/SimplifyCFG/2005-08-03-PHIFactorCrash.ll llvm/trunk/test/Transforms/SimplifyCFG/2009-03-05-Speculative-Hoist-Dbg.ll llvm/trunk/test/Verifier/byval-2.ll Removed: llvm/trunk/test/Assembler/2002-02-19-TypeParsing.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-02-19-TypeParsing.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/Assembler/2002-02-19-TypeParsing.ll (original) +++ llvm/trunk/test/Assembler/2002-02-19-TypeParsing.ll (removed) @@ -1,3 +0,0 @@ -; RUN: llvm-as %s -o /dev/null - -%Hosp = type { i32, i32, i32, { \2*, { i32, i32, i32, { [4 x \3], \2, \5, %Hosp, i32, i32 }* }*, \2* }, { \2*, { i32, i32, i32, { [4 x \3], \2, \5, %Hosp, i32, i32 }* }*, \2* }, { \2*, { i32, i32, i32, { [4 x \3], \2, \5, %Hosp, i32, i32 }* }*, \2* }, { \2*, { i32, i32, i32, { [4 x \3], \2, \5, %Hosp, i32, i32 }* }*, \2* } } Removed: llvm/trunk/test/CodeGen/Blackfin/burg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Blackfin/burg.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Blackfin/burg.ll (original) +++ llvm/trunk/test/CodeGen/Blackfin/burg.ll (removed) @@ -1,19 +0,0 @@ -; RUN: llc < %s -march=bfin -verify-machineinstrs > %t - - %IntList = type %struct.intlist* - %ReadFn = type i32 ()* - %YYSTYPE = type { %IntList } - %struct.intlist = type { i32, %IntList } - at yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] - -define i32 @yyparse() { -bb0: - %reg254 = load i16* null ; [#uses=1] - %reg254-idxcast = sext i16 %reg254 to i64 ; [#uses=1] - %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; [#uses=1] - %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; [#uses=1] - %reg261.idx1 = getelementptr %YYSTYPE* null, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1] - %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1] - store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - unreachable -} Removed: llvm/trunk/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll (removed) @@ -1,3 +0,0 @@ -; RUN: llc < %s -march=c - - at MyIntList = external global { \2*, i32 } Removed: llvm/trunk/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll (removed) @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=c - -%MPI_Comm = type %struct.Comm* -%struct.Comm = type opaque - at thing = global %MPI_Comm* null ; <%MPI_Comm**> [#uses=0] - Removed: llvm/trunk/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll (removed) @@ -1,10 +0,0 @@ -; RUN: llc < %s -march=c - - %BitField = type i32 - %tokenptr = type i32* - -define void @test() { - %pmf1 = alloca %tokenptr (%tokenptr, i8*)* ; <%tokenptr (%tokenptr, i8*)**> [#uses=0] - ret void -} - Removed: llvm/trunk/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll (removed) @@ -1,5 +0,0 @@ -; RUN: llc < %s -march=c - - %JNIEnv = type %struct.JNINa* - %struct.JNINa = type { i8*, i8*, i8*, void (%JNIEnv*)* } - Removed: llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll (removed) @@ -1,11 +0,0 @@ -; PR918 -; RUN: llc < %s -march=c | not grep {l_structtype_s l_fixarray_array3} - -%structtype_s = type { i32 } -%fixarray_array3 = type [3 x %structtype_s] - -define i32 @witness(%fixarray_array3* %p) { - %q = getelementptr %fixarray_array3* %p, i32 0, i32 0, i32 0 - %v = load i32* %q - ret i32 %v -} Removed: llvm/trunk/test/CodeGen/Generic/BurgBadRegAlloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/BurgBadRegAlloc.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/BurgBadRegAlloc.ll (original) +++ llvm/trunk/test/CodeGen/Generic/BurgBadRegAlloc.ll (removed) @@ -1,829 +0,0 @@ -; RUN: llc < %s - -;; Register allocation is doing a very poor job on this routine from yyparse -;; in Burg: -;; -- at least two long-lived values are being allocated to %o? registers -;; -- even worse, those registers are being saved and restored repeatedly -;; at function calls, even though there are no intervening uses. -;; -- outgoing args of some function calls have to be swapped, causing -;; another write/read from stack to do the exchange (use -dregalloc=y). -;; -%Arity = type %struct.arity* - %Binding = type %struct.binding* - %DeltaCost = type [4 x i16] - %Dimension = type %struct.dimension* - %Index_Map = type { i32, %Item_Set* } - %IntList = type %struct.intlist* - %Item = type { %DeltaCost, %Rule } - %ItemArray = type %Item* - %Item_Set = type %struct.item_set* - %List = type %struct.list* - %Mapping = type %struct.mapping* - %NonTerminal = type %struct.nonterminal* - %Operator = type %struct.operator* - %Pattern = type %struct.pattern* - %PatternAST = type %struct.patternAST* - %Plank = type %struct.plank* - %PlankMap = type %struct.plankMap* - %ReadFn = type i32 ()* - %Rule = type %struct.rule* - %RuleAST = type %struct.ruleAST* - %StateMap = type %struct.stateMap* - %StrTableElement = type %struct.strTableElement* - %Symbol = type %struct.symbol* - %Table = type %struct.table* - %YYSTYPE = type { %IntList } - %struct.arity = type { i32, %List } - %struct.binding = type { i8*, i32 } - %struct.dimension = type { i16*, %Index_Map, %Mapping, i32, %PlankMap } - %struct.index_map = type { i32, %Item_Set* } - %struct.intlist = type { i32, %IntList } - %struct.item = type { %DeltaCost, %Rule } - %struct.item_set = type { i32, i32, %Operator, [2 x %Item_Set], %Item_Set, i16*, %ItemArray, %ItemArray } - %struct.list = type { i8*, %List } - %struct.mapping = type { %List*, i32, i32, i32, %Item_Set* } - %struct.nonterminal = type { i8*, i32, i32, i32, %PlankMap, %Rule } - %struct.operator = type { i8*, i32, i32, i32, i32, i32, %Table } - %struct.pattern = type { %NonTerminal, %Operator, [2 x %NonTerminal] } - %struct.patternAST = type { %Symbol, i8*, %List } - %struct.plank = type { i8*, %List, i32 } - %struct.plankMap = type { %List, i32, %StateMap } - %struct.rule = type { %DeltaCost, i32, i32, i32, %NonTerminal, %Pattern, i32 } - %struct.ruleAST = type { i8*, %PatternAST, i32, %IntList, %Rule, %StrTableElement, %StrTableElement } - %struct.stateMap = type { i8*, %Plank, i32, i16* } - %struct.strTableElement = type { i8*, %IntList, i8* } - %struct.symbol = type { i8*, i32, { %Operator } } - %struct.table = type { %Operator, %List, i16*, [2 x %Dimension], %Item_Set* } - at yylval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] - at yylhs = external global [25 x i16] ; <[25 x i16]*> [#uses=1] - at yylen = external global [25 x i16] ; <[25 x i16]*> [#uses=1] - at yydefred = external global [43 x i16] ; <[43 x i16]*> [#uses=1] - at yydgoto = external global [12 x i16] ; <[12 x i16]*> [#uses=1] - at yysindex = external global [43 x i16] ; <[43 x i16]*> [#uses=2] - at yyrindex = external global [43 x i16] ; <[43 x i16]*> [#uses=1] - at yygindex = external global [12 x i16] ; <[12 x i16]*> [#uses=1] - at yytable = external global [263 x i16] ; <[263 x i16]*> [#uses=4] - at yycheck = external global [263 x i16] ; <[263 x i16]*> [#uses=4] - at yynerrs = external global i32 ; [#uses=3] - at yyerrflag = external global i32 ; [#uses=6] - at yychar = external global i32 ; [#uses=15] - at yyssp = external global i16* ; [#uses=15] - at yyvsp = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=30] - at yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] - at yyss = external global i16* ; [#uses=3] - at yysslim = external global i16* ; [#uses=3] - at yyvs = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=1] - at .LC01 = external global [13 x i8] ; <[13 x i8]*> [#uses=1] - at .LC1 = external global [20 x i8] ; <[20 x i8]*> [#uses=1] - -define i32 @yyparse() { -bb0: - store i32 0, i32* @yynerrs - store i32 0, i32* @yyerrflag - store i32 -1, i32* @yychar - %reg113 = load i16** @yyss ; [#uses=1] - %cond581 = icmp ne i16* %reg113, null ; [#uses=1] - br i1 %cond581, label %bb3, label %bb2 - -bb2: ; preds = %bb0 - %reg584 = call i32 @yygrowstack( ) ; [#uses=1] - %cond584 = icmp ne i32 %reg584, 0 ; [#uses=1] - br i1 %cond584, label %bb113, label %bb3 - -bb3: ; preds = %bb2, %bb0 - %reg115 = load i16** @yyss ; [#uses=1] - store i16* %reg115, i16** @yyssp - %reg116 = load %YYSTYPE** @yyvs ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg116, %YYSTYPE** @yyvsp - %reg117 = load i16** @yyssp ; [#uses=1] - store i16 0, i16* %reg117 - br label %bb4 - -bb4: ; preds = %bb112, %bb102, %bb35, %bb31, %bb15, %bb14, %bb3 - %reg458 = phi i32 [ %reg476, %bb112 ], [ 1, %bb102 ], [ %reg458, %bb35 ], [ %cast768, %bb31 ], [ %cast658, %bb15 ], [ %cast658, %bb14 ], [ 0, %bb3 ] ; [#uses=2] - %reg458-idxcast = zext i32 %reg458 to i64 ; [#uses=3] - %reg594 = getelementptr [43 x i16]* @yydefred, i64 0, i64 %reg458-idxcast ; [#uses=1] - %reg125 = load i16* %reg594 ; [#uses=1] - %cast599 = sext i16 %reg125 to i32 ; [#uses=2] - %cond600 = icmp ne i32 %cast599, 0 ; [#uses=1] - br i1 %cond600, label %bb36, label %bb5 - -bb5: ; preds = %bb4 - %reg127 = load i32* @yychar ; [#uses=1] - %cond603 = icmp sge i32 %reg127, 0 ; [#uses=1] - br i1 %cond603, label %bb8, label %bb6 - -bb6: ; preds = %bb5 - %reg607 = call i32 @yylex( ) ; [#uses=1] - store i32 %reg607, i32* @yychar - %reg129 = load i32* @yychar ; [#uses=1] - %cond609 = icmp sge i32 %reg129, 0 ; [#uses=1] - br i1 %cond609, label %bb8, label %bb7 - -bb7: ; preds = %bb6 - store i32 0, i32* @yychar - br label %bb8 - -bb8: ; preds = %bb7, %bb6, %bb5 - %reg615 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg458-idxcast ; [#uses=1] - %reg137 = load i16* %reg615 ; [#uses=1] - %cast620 = sext i16 %reg137 to i32 ; [#uses=2] - %cond621 = icmp eq i32 %cast620, 0 ; [#uses=1] - br i1 %cond621, label %bb16, label %bb9 - -bb9: ; preds = %bb8 - %reg139 = load i32* @yychar ; [#uses=2] - %reg460 = add i32 %cast620, %reg139 ; [#uses=3] - %cond624 = icmp slt i32 %reg460, 0 ; [#uses=1] - br i1 %cond624, label %bb16, label %bb10 - -bb10: ; preds = %bb9 - %cond627 = icmp sgt i32 %reg460, 262 ; [#uses=1] - br i1 %cond627, label %bb16, label %bb11 - -bb11: ; preds = %bb10 - %reg460-idxcast = sext i32 %reg460 to i64 ; [#uses=2] - %reg632 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg460-idxcast ; [#uses=1] - %reg148 = load i16* %reg632 ; [#uses=1] - %cast637 = sext i16 %reg148 to i32 ; [#uses=1] - %cond639 = icmp ne i32 %cast637, %reg139 ; [#uses=1] - br i1 %cond639, label %bb16, label %bb12 - -bb12: ; preds = %bb11 - %reg150 = load i16** @yyssp ; [#uses=1] - %cast640 = bitcast i16* %reg150 to i8* ; [#uses=1] - %reg151 = load i16** @yysslim ; [#uses=1] - %cast641 = bitcast i16* %reg151 to i8* ; [#uses=1] - %cond642 = icmp ult i8* %cast640, %cast641 ; [#uses=1] - br i1 %cond642, label %bb14, label %bb13 - -bb13: ; preds = %bb12 - %reg644 = call i32 @yygrowstack( ) ; [#uses=1] - %cond644 = icmp ne i32 %reg644, 0 ; [#uses=1] - br i1 %cond644, label %bb113, label %bb14 - -bb14: ; preds = %bb13, %bb12 - %reg153 = load i16** @yyssp ; [#uses=1] - %reg647 = getelementptr i16* %reg153, i64 1 ; [#uses=2] - store i16* %reg647, i16** @yyssp - %reg653 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg460-idxcast ; [#uses=1] - %reg162 = load i16* %reg653 ; [#uses=2] - %cast658 = sext i16 %reg162 to i32 ; [#uses=2] - store i16 %reg162, i16* %reg647 - %reg164 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg661 = getelementptr %YYSTYPE* %reg164, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg661, %YYSTYPE** @yyvsp - %reg167 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg661.idx1 = getelementptr %YYSTYPE* %reg164, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg167, %IntList* %reg661.idx1 - store i32 -1, i32* @yychar - %reg169 = load i32* @yyerrflag ; [#uses=2] - %cond669 = icmp sle i32 %reg169, 0 ; [#uses=1] - br i1 %cond669, label %bb4, label %bb15 - -bb15: ; preds = %bb14 - %reg171 = add i32 %reg169, -1 ; [#uses=1] - store i32 %reg171, i32* @yyerrflag - br label %bb4 - -bb16: ; preds = %bb11, %bb10, %bb9, %bb8 - %reg677 = getelementptr [43 x i16]* @yyrindex, i64 0, i64 %reg458-idxcast ; [#uses=1] - %reg178 = load i16* %reg677 ; [#uses=1] - %cast682 = sext i16 %reg178 to i32 ; [#uses=2] - %cond683 = icmp eq i32 %cast682, 0 ; [#uses=1] - br i1 %cond683, label %bb21, label %bb17 - -bb17: ; preds = %bb16 - %reg180 = load i32* @yychar ; [#uses=2] - %reg463 = add i32 %cast682, %reg180 ; [#uses=3] - %cond686 = icmp slt i32 %reg463, 0 ; [#uses=1] - br i1 %cond686, label %bb21, label %bb18 - -bb18: ; preds = %bb17 - %cond689 = icmp sgt i32 %reg463, 262 ; [#uses=1] - br i1 %cond689, label %bb21, label %bb19 - -bb19: ; preds = %bb18 - %reg463-idxcast = sext i32 %reg463 to i64 ; [#uses=2] - %reg694 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg463-idxcast ; [#uses=1] - %reg189 = load i16* %reg694 ; [#uses=1] - %cast699 = sext i16 %reg189 to i32 ; [#uses=1] - %cond701 = icmp ne i32 %cast699, %reg180 ; [#uses=1] - br i1 %cond701, label %bb21, label %bb20 - -bb20: ; preds = %bb19 - %reg704 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg463-idxcast ; [#uses=1] - %reg197 = load i16* %reg704 ; [#uses=1] - %cast709 = sext i16 %reg197 to i32 ; [#uses=1] - br label %bb36 - -bb21: ; preds = %bb19, %bb18, %bb17, %bb16 - %reg198 = load i32* @yyerrflag ; [#uses=1] - %cond711 = icmp ne i32 %reg198, 0 ; [#uses=1] - br i1 %cond711, label %bb23, label %bb22 - -bb22: ; preds = %bb21 - call void @yyerror( i8* getelementptr ([13 x i8]* @.LC01, i64 0, i64 0) ) - %reg200 = load i32* @yynerrs ; [#uses=1] - %reg201 = add i32 %reg200, 1 ; [#uses=1] - store i32 %reg201, i32* @yynerrs - br label %bb23 - -bb23: ; preds = %bb22, %bb21 - %reg202 = load i32* @yyerrflag ; [#uses=1] - %cond719 = icmp sgt i32 %reg202, 2 ; [#uses=1] - br i1 %cond719, label %bb34, label %bb24 - -bb24: ; preds = %bb23 - store i32 3, i32* @yyerrflag - %reg241 = load i16** @yyss ; [#uses=1] - %cast778 = bitcast i16* %reg241 to i8* ; [#uses=1] - br label %bb25 - -bb25: ; preds = %bb33, %bb24 - %reg204 = load i16** @yyssp ; [#uses=4] - %reg206 = load i16* %reg204 ; [#uses=1] - %reg206-idxcast = sext i16 %reg206 to i64 ; [#uses=1] - %reg727 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg206-idxcast ; [#uses=1] - %reg212 = load i16* %reg727 ; [#uses=2] - %cast732 = sext i16 %reg212 to i32 ; [#uses=2] - %cond733 = icmp eq i32 %cast732, 0 ; [#uses=1] - br i1 %cond733, label %bb32, label %bb26 - -bb26: ; preds = %bb25 - %reg466 = add i32 %cast732, 256 ; [#uses=2] - %cond736 = icmp slt i32 %reg466, 0 ; [#uses=1] - br i1 %cond736, label %bb32, label %bb27 - -bb27: ; preds = %bb26 - %cond739 = icmp sgt i32 %reg466, 262 ; [#uses=1] - br i1 %cond739, label %bb32, label %bb28 - -bb28: ; preds = %bb27 - %reg212-idxcast = sext i16 %reg212 to i64 ; [#uses=1] - %reg212-idxcast-offset = add i64 %reg212-idxcast, 256 ; [#uses=2] - %reg744 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg212-idxcast-offset ; [#uses=1] - %reg221 = load i16* %reg744 ; [#uses=1] - %cond748 = icmp ne i16 %reg221, 256 ; [#uses=1] - br i1 %cond748, label %bb32, label %bb29 - -bb29: ; preds = %bb28 - %cast750 = bitcast i16* %reg204 to i8* ; [#uses=1] - %reg223 = load i16** @yysslim ; [#uses=1] - %cast751 = bitcast i16* %reg223 to i8* ; [#uses=1] - %cond752 = icmp ult i8* %cast750, %cast751 ; [#uses=1] - br i1 %cond752, label %bb31, label %bb30 - -bb30: ; preds = %bb29 - %reg754 = call i32 @yygrowstack( ) ; [#uses=1] - %cond754 = icmp ne i32 %reg754, 0 ; [#uses=1] - br i1 %cond754, label %bb113, label %bb31 - -bb31: ; preds = %bb30, %bb29 - %reg225 = load i16** @yyssp ; [#uses=1] - %reg757 = getelementptr i16* %reg225, i64 1 ; [#uses=2] - store i16* %reg757, i16** @yyssp - %reg763 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg212-idxcast-offset ; [#uses=1] - %reg234 = load i16* %reg763 ; [#uses=2] - %cast768 = sext i16 %reg234 to i32 ; [#uses=1] - store i16 %reg234, i16* %reg757 - %reg236 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg771 = getelementptr %YYSTYPE* %reg236, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg771, %YYSTYPE** @yyvsp - %reg239 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg771.idx1 = getelementptr %YYSTYPE* %reg236, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg239, %IntList* %reg771.idx1 - br label %bb4 - -bb32: ; preds = %bb28, %bb27, %bb26, %bb25 - %cast777 = bitcast i16* %reg204 to i8* ; [#uses=1] - %cond779 = icmp ule i8* %cast777, %cast778 ; [#uses=1] - br i1 %cond779, label %UnifiedExitNode, label %bb33 - -bb33: ; preds = %bb32 - %reg781 = getelementptr i16* %reg204, i64 -1 ; [#uses=1] - store i16* %reg781, i16** @yyssp - %reg244 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg786 = getelementptr %YYSTYPE* %reg244, i64 -1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg786, %YYSTYPE** @yyvsp - br label %bb25 - -bb34: ; preds = %bb23 - %reg246 = load i32* @yychar ; [#uses=1] - %cond791 = icmp eq i32 %reg246, 0 ; [#uses=1] - br i1 %cond791, label %UnifiedExitNode, label %bb35 - -bb35: ; preds = %bb34 - store i32 -1, i32* @yychar - br label %bb4 - -bb36: ; preds = %bb20, %bb4 - %reg468 = phi i32 [ %cast709, %bb20 ], [ %cast599, %bb4 ] ; [#uses=31] - %reg468-idxcast = sext i32 %reg468 to i64 ; [#uses=2] - %reg796 = getelementptr [25 x i16]* @yylen, i64 0, i64 %reg468-idxcast ; [#uses=1] - %reg254 = load i16* %reg796 ; [#uses=2] - %reg259 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg254-idxcast = sext i16 %reg254 to i64 ; [#uses=1] - %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; [#uses=1] - %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; [#uses=1] - %reg261.idx1 = getelementptr %YYSTYPE* %reg259, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1] - %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1] - store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %cond812 = icmp eq i32 %reg468, 13 ; [#uses=1] - br i1 %cond812, label %bb85, label %bb37 - -bb37: ; preds = %bb36 - %cond814 = icmp sgt i32 %reg468, 13 ; [#uses=1] - br i1 %cond814, label %bb56, label %bb38 - -bb38: ; preds = %bb37 - %cond817 = icmp eq i32 %reg468, 7 ; [#uses=1] - br i1 %cond817, label %bb79, label %bb39 - -bb39: ; preds = %bb38 - %cond819 = icmp sgt i32 %reg468, 7 ; [#uses=1] - br i1 %cond819, label %bb48, label %bb40 - -bb40: ; preds = %bb39 - %cond822 = icmp eq i32 %reg468, 4 ; [#uses=1] - br i1 %cond822, label %bb76, label %bb41 - -bb41: ; preds = %bb40 - %cond824 = icmp sgt i32 %reg468, 4 ; [#uses=1] - br i1 %cond824, label %bb45, label %bb42 - -bb42: ; preds = %bb41 - %cond827 = icmp eq i32 %reg468, 2 ; [#uses=1] - br i1 %cond827, label %bb74, label %bb43 - -bb43: ; preds = %bb42 - %cond829 = icmp eq i32 %reg468, 3 ; [#uses=1] - br i1 %cond829, label %bb75, label %bb97 - -bb45: ; preds = %bb41 - %cond831 = icmp eq i32 %reg468, 5 ; [#uses=1] - br i1 %cond831, label %bb77, label %bb46 - -bb46: ; preds = %bb45 - %cond833 = icmp eq i32 %reg468, 6 ; [#uses=1] - br i1 %cond833, label %bb78, label %bb97 - -bb48: ; preds = %bb39 - %cond835 = icmp eq i32 %reg468, 10 ; [#uses=1] - br i1 %cond835, label %bb82, label %bb49 - -bb49: ; preds = %bb48 - %cond837 = icmp sgt i32 %reg468, 10 ; [#uses=1] - br i1 %cond837, label %bb53, label %bb50 - -bb50: ; preds = %bb49 - %cond840 = icmp eq i32 %reg468, 8 ; [#uses=1] - br i1 %cond840, label %bb80, label %bb51 - -bb51: ; preds = %bb50 - %cond842 = icmp eq i32 %reg468, 9 ; [#uses=1] - br i1 %cond842, label %bb81, label %bb97 - -bb53: ; preds = %bb49 - %cond844 = icmp eq i32 %reg468, 11 ; [#uses=1] - br i1 %cond844, label %bb83, label %bb54 - -bb54: ; preds = %bb53 - %cond846 = icmp eq i32 %reg468, 12 ; [#uses=1] - br i1 %cond846, label %bb84, label %bb97 - -bb56: ; preds = %bb37 - %cond848 = icmp eq i32 %reg468, 19 ; [#uses=1] - br i1 %cond848, label %bb91, label %bb57 - -bb57: ; preds = %bb56 - %cond850 = icmp sgt i32 %reg468, 19 ; [#uses=1] - br i1 %cond850, label %bb66, label %bb58 - -bb58: ; preds = %bb57 - %cond853 = icmp eq i32 %reg468, 16 ; [#uses=1] - br i1 %cond853, label %bb88, label %bb59 - -bb59: ; preds = %bb58 - %cond855 = icmp sgt i32 %reg468, 16 ; [#uses=1] - br i1 %cond855, label %bb63, label %bb60 - -bb60: ; preds = %bb59 - %cond858 = icmp eq i32 %reg468, 14 ; [#uses=1] - br i1 %cond858, label %bb86, label %bb61 - -bb61: ; preds = %bb60 - %cond860 = icmp eq i32 %reg468, 15 ; [#uses=1] - br i1 %cond860, label %bb87, label %bb97 - -bb63: ; preds = %bb59 - %cond862 = icmp eq i32 %reg468, 17 ; [#uses=1] - br i1 %cond862, label %bb89, label %bb64 - -bb64: ; preds = %bb63 - %cond864 = icmp eq i32 %reg468, 18 ; [#uses=1] - br i1 %cond864, label %bb90, label %bb97 - -bb66: ; preds = %bb57 - %cond866 = icmp eq i32 %reg468, 22 ; [#uses=1] - br i1 %cond866, label %bb94, label %bb67 - -bb67: ; preds = %bb66 - %cond868 = icmp sgt i32 %reg468, 22 ; [#uses=1] - br i1 %cond868, label %bb71, label %bb68 - -bb68: ; preds = %bb67 - %cond871 = icmp eq i32 %reg468, 20 ; [#uses=1] - br i1 %cond871, label %bb92, label %bb69 - -bb69: ; preds = %bb68 - %cond873 = icmp eq i32 %reg468, 21 ; [#uses=1] - br i1 %cond873, label %bb93, label %bb97 - -bb71: ; preds = %bb67 - %cond875 = icmp eq i32 %reg468, 23 ; [#uses=1] - br i1 %cond875, label %bb95, label %bb72 - -bb72: ; preds = %bb71 - %cond877 = icmp eq i32 %reg468, 24 ; [#uses=1] - br i1 %cond877, label %bb96, label %bb97 - -bb74: ; preds = %bb42 - call void @yyfinished( ) - br label %bb97 - -bb75: ; preds = %bb43 - %reg262 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg264.idx1 = getelementptr %YYSTYPE* %reg262, i64 -2, i32 0 ; <%IntList*> [#uses=1] - %reg264 = load %IntList* %reg264.idx1 ; <%IntList> [#uses=1] - %reg265.idx = getelementptr %YYSTYPE* %reg262, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg265 = load %IntList* %reg265.idx ; <%IntList> [#uses=1] - %cast889 = bitcast %IntList %reg265 to %List ; <%List> [#uses=1] - %cast890 = bitcast %IntList %reg264 to %List ; <%List> [#uses=1] - call void @doSpec( %List %cast890, %List %cast889 ) - br label %bb97 - -bb76: ; preds = %bb40 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb77: ; preds = %bb45 - %reg269 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast894 = getelementptr %YYSTYPE* %reg269, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg271 = load %IntList* %cast894 ; <%IntList> [#uses=1] - %reg271.upgrd.1 = bitcast %IntList %reg271 to i8* ; [#uses=1] - %reg272.idx1 = getelementptr %YYSTYPE* %reg269, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg272 = load %IntList* %reg272.idx1 ; <%IntList> [#uses=1] - %cast901 = bitcast %IntList %reg272 to %List ; <%List> [#uses=1] - %reg901 = call %List @newList( i8* %reg271.upgrd.1, %List %cast901 ) ; <%List> [#uses=1] - bitcast %List %reg901 to %IntList ; <%IntList>:0 [#uses=1] - store %IntList %0, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb78: ; preds = %bb46 - %reg275 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg277.idx = getelementptr %YYSTYPE* %reg275, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg277 = load %IntList* %reg277.idx ; <%IntList> [#uses=1] - %cast907 = bitcast %IntList %reg277 to %List ; <%List> [#uses=1] - %reg907 = call %Arity @newArity( i32 -1, %List %cast907 ) ; <%Arity> [#uses=1] - bitcast %Arity %reg907 to %IntList ; <%IntList>:1 [#uses=1] - store %IntList %1, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb79: ; preds = %bb38 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %reg281 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast912 = getelementptr %YYSTYPE* %reg281, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg282 = load %IntList* %cast912 ; <%IntList> [#uses=1] - %reg282.upgrd.2 = bitcast %IntList %reg282 to %List ; <%List> [#uses=1] - call void @doGram( %List %reg282.upgrd.2 ) - br label %bb97 - -bb80: ; preds = %bb50 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %reg285 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast917 = getelementptr %YYSTYPE* %reg285, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg286 = load %IntList* %cast917 ; <%IntList> [#uses=1] - %reg286.upgrd.3 = bitcast %IntList %reg286 to i8* ; [#uses=1] - call void @doStart( i8* %reg286.upgrd.3 ) - br label %bb97 - -bb81: ; preds = %bb51 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb82: ; preds = %bb48 - %reg290 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast923 = getelementptr %YYSTYPE* %reg290, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg292 = load %IntList* %cast923 ; <%IntList> [#uses=1] - %reg292.upgrd.4 = bitcast %IntList %reg292 to i8* ; [#uses=1] - %reg293.idx1 = getelementptr %YYSTYPE* %reg290, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg293 = load %IntList* %reg293.idx1 ; <%IntList> [#uses=1] - %cast930 = bitcast %IntList %reg293 to %List ; <%List> [#uses=1] - %reg930 = call %List @newList( i8* %reg292.upgrd.4, %List %cast930 ) ; <%List> [#uses=1] - bitcast %List %reg930 to %IntList ; <%IntList>:2 [#uses=1] - store %IntList %2, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb83: ; preds = %bb53 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb84: ; preds = %bb54 - %reg298 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast936 = getelementptr %YYSTYPE* %reg298, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg300 = load %IntList* %cast936 ; <%IntList> [#uses=1] - %reg300.upgrd.5 = bitcast %IntList %reg300 to i8* ; [#uses=1] - %reg301.idx1 = getelementptr %YYSTYPE* %reg298, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg301 = load %IntList* %reg301.idx1 ; <%IntList> [#uses=1] - %cast943 = bitcast %IntList %reg301 to %List ; <%List> [#uses=1] - %reg943 = call %List @newList( i8* %reg300.upgrd.5, %List %cast943 ) ; <%List> [#uses=1] - bitcast %List %reg943 to %IntList ; <%IntList>:3 [#uses=1] - store %IntList %3, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb85: ; preds = %bb36 - %reg304 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast9521 = getelementptr %YYSTYPE* %reg304, i64 -2, i32 0 ; <%IntList*> [#uses=1] - %reg306 = load %IntList* %cast9521 ; <%IntList> [#uses=1] - %reg306.upgrd.6 = bitcast %IntList %reg306 to i8* ; [#uses=1] - %cast953 = bitcast %YYSTYPE* %reg304 to i32* ; [#uses=1] - %reg307 = load i32* %cast953 ; [#uses=1] - %reg955 = call %Binding @newBinding( i8* %reg306.upgrd.6, i32 %reg307 ) ; <%Binding> [#uses=1] - bitcast %Binding %reg955 to %IntList ; <%IntList>:4 [#uses=1] - store %IntList %4, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb86: ; preds = %bb60 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb87: ; preds = %bb61 - %reg312 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast961 = getelementptr %YYSTYPE* %reg312, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg314 = load %IntList* %cast961 ; <%IntList> [#uses=1] - %reg314.upgrd.7 = bitcast %IntList %reg314 to i8* ; [#uses=1] - %reg315.idx1 = getelementptr %YYSTYPE* %reg312, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg315 = load %IntList* %reg315.idx1 ; <%IntList> [#uses=1] - %cast968 = bitcast %IntList %reg315 to %List ; <%List> [#uses=1] - %reg968 = call %List @newList( i8* %reg314.upgrd.7, %List %cast968 ) ; <%List> [#uses=1] - bitcast %List %reg968 to %IntList ; <%IntList>:5 [#uses=1] - store %IntList %5, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb88: ; preds = %bb58 - %reg318 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=4] - %cast9791 = getelementptr %YYSTYPE* %reg318, i64 -6, i32 0 ; <%IntList*> [#uses=1] - %reg322 = load %IntList* %cast9791 ; <%IntList> [#uses=1] - %reg322.upgrd.8 = bitcast %IntList %reg322 to i8* ; [#uses=1] - %reg323.idx1 = getelementptr %YYSTYPE* %reg318, i64 -4, i32 0 ; <%IntList*> [#uses=1] - %reg323 = load %IntList* %reg323.idx1 ; <%IntList> [#uses=1] - %reg987 = getelementptr %YYSTYPE* %reg318, i64 -2 ; <%YYSTYPE*> [#uses=1] - %cast989 = bitcast %YYSTYPE* %reg987 to i32* ; [#uses=1] - %reg324 = load i32* %cast989 ; [#uses=1] - %reg325.idx1 = getelementptr %YYSTYPE* %reg318, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg325 = load %IntList* %reg325.idx1 ; <%IntList> [#uses=1] - %cast998 = bitcast %IntList %reg323 to %PatternAST ; <%PatternAST> [#uses=1] - %reg996 = call %RuleAST @newRuleAST( i8* %reg322.upgrd.8, %PatternAST %cast998, i32 %reg324, %IntList %reg325 ) ; <%RuleAST> [#uses=1] - bitcast %RuleAST %reg996 to %IntList ; <%IntList>:6 [#uses=1] - store %IntList %6, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb89: ; preds = %bb63 - %reg328 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast1002 = getelementptr %YYSTYPE* %reg328, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg329 = load %IntList* %cast1002 ; <%IntList> [#uses=1] - %reg329.upgrd.9 = bitcast %IntList %reg329 to i8* ; [#uses=1] - %reg1004 = call %PatternAST @newPatternAST( i8* %reg329.upgrd.9, %List null ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1004 to %IntList ; <%IntList>:7 [#uses=1] - store %IntList %7, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb90: ; preds = %bb64 - %reg333 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast10131 = getelementptr %YYSTYPE* %reg333, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg335 = load %IntList* %cast10131 ; <%IntList> [#uses=1] - %reg335.upgrd.10 = bitcast %IntList %reg335 to i8* ; [#uses=1] - %reg1015 = call %List @newList( i8* %reg335.upgrd.10, %List null ) ; <%List> [#uses=1] - %cast10211 = getelementptr %YYSTYPE* %reg333, i64 -3, i32 0 ; <%IntList*> [#uses=1] - %reg338 = load %IntList* %cast10211 ; <%IntList> [#uses=1] - %reg338.upgrd.11 = bitcast %IntList %reg338 to i8* ; [#uses=1] - %reg1023 = call %PatternAST @newPatternAST( i8* %reg338.upgrd.11, %List %reg1015 ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1023 to %IntList ; <%IntList>:8 [#uses=1] - store %IntList %8, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb91: ; preds = %bb56 - %reg341 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=3] - %cast10331 = getelementptr %YYSTYPE* %reg341, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg344 = load %IntList* %cast10331 ; <%IntList> [#uses=1] - %reg344.upgrd.12 = bitcast %IntList %reg344 to i8* ; [#uses=1] - %reg1035 = call %List @newList( i8* %reg344.upgrd.12, %List null ) ; <%List> [#uses=1] - %cast10411 = getelementptr %YYSTYPE* %reg341, i64 -3, i32 0 ; <%IntList*> [#uses=1] - %reg347 = load %IntList* %cast10411 ; <%IntList> [#uses=1] - %reg347.upgrd.13 = bitcast %IntList %reg347 to i8* ; [#uses=1] - %reg1043 = call %List @newList( i8* %reg347.upgrd.13, %List %reg1035 ) ; <%List> [#uses=1] - %cast10491 = getelementptr %YYSTYPE* %reg341, i64 -5, i32 0 ; <%IntList*> [#uses=1] - %reg349 = load %IntList* %cast10491 ; <%IntList> [#uses=1] - %reg349.upgrd.14 = bitcast %IntList %reg349 to i8* ; [#uses=1] - %reg1051 = call %PatternAST @newPatternAST( i8* %reg349.upgrd.14, %List %reg1043 ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1051 to %IntList ; <%IntList>:9 [#uses=1] - store %IntList %9, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb92: ; preds = %bb68 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb93: ; preds = %bb69 - %reg354 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1059 = getelementptr %YYSTYPE* %reg354, i64 -2 ; <%YYSTYPE*> [#uses=1] - %cast1061 = bitcast %YYSTYPE* %reg1059 to i32* ; [#uses=1] - %reg356 = load i32* %cast1061 ; [#uses=1] - %reg357.idx1 = getelementptr %YYSTYPE* %reg354, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg357 = load %IntList* %reg357.idx1 ; <%IntList> [#uses=1] - %reg1068 = call %IntList @newIntList( i32 %reg356, %IntList %reg357 ) ; <%IntList> [#uses=1] - store %IntList %reg1068, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb94: ; preds = %bb66 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb95: ; preds = %bb71 - %reg362 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1076 = getelementptr %YYSTYPE* %reg362, i64 -1 ; <%YYSTYPE*> [#uses=1] - %cast1078 = bitcast %YYSTYPE* %reg1076 to i32* ; [#uses=1] - %reg364 = load i32* %cast1078 ; [#uses=1] - %reg365.idx = getelementptr %YYSTYPE* %reg362, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg365 = load %IntList* %reg365.idx ; <%IntList> [#uses=1] - %reg1081 = call %IntList @newIntList( i32 %reg364, %IntList %reg365 ) ; <%IntList> [#uses=1] - store %IntList %reg1081, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb96: ; preds = %bb72 - %reg368 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1088 = getelementptr %YYSTYPE* %reg368, i64 -1 ; <%YYSTYPE*> [#uses=1] - %cast1090 = bitcast %YYSTYPE* %reg1088 to i32* ; [#uses=1] - %reg370 = load i32* %cast1090 ; [#uses=1] - %reg371.idx = getelementptr %YYSTYPE* %reg368, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg371 = load %IntList* %reg371.idx ; <%IntList> [#uses=1] - %reg1093 = call %IntList @newIntList( i32 %reg370, %IntList %reg371 ) ; <%IntList> [#uses=1] - store %IntList %reg1093, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb97: ; preds = %bb96, %bb95, %bb94, %bb93, %bb92, %bb91, %bb90, %bb89, %bb88, %bb87, %bb86, %bb85, %bb84, %bb83, %bb82, %bb81, %bb80, %bb79, %bb78, %bb77, %bb76, %bb75, %bb74, %bb72, %bb69, %bb64, %bb61, %bb54, %bb51, %bb46, %bb43 - %cast1097 = sext i16 %reg254 to i64 ; [#uses=3] - %reg375 = add i64 %cast1097, %cast1097 ; [#uses=1] - %reg377 = load i16** @yyssp ; [#uses=1] - %cast379 = ptrtoint i16* %reg377 to i64 ; [#uses=1] - %reg381 = sub i64 %cast379, %reg375 ; [#uses=1] - %cast1099 = inttoptr i64 %reg381 to i16* ; [#uses=1] - store i16* %cast1099, i16** @yyssp - %reg382 = load i16** @yyssp ; [#uses=3] - %reg383 = load i16* %reg382 ; [#uses=1] - %cast1103 = sext i16 %reg383 to i32 ; [#uses=3] - %reg385 = mul i64 %cast1097, 8 ; [#uses=1] - %reg387 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast389 = ptrtoint %YYSTYPE* %reg387 to i64 ; [#uses=1] - %reg391 = sub i64 %cast389, %reg385 ; [#uses=1] - %cast1108 = inttoptr i64 %reg391 to %YYSTYPE* ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %cast1108, %YYSTYPE** @yyvsp - %reg1111 = getelementptr [25 x i16]* @yylhs, i64 0, i64 %reg468-idxcast ; [#uses=1] - %reg398 = load i16* %reg1111 ; [#uses=2] - %cast1116 = sext i16 %reg398 to i32 ; [#uses=1] - %cond1117 = icmp ne i32 %cast1103, 0 ; [#uses=1] - br i1 %cond1117, label %bb104, label %bb98 - -bb98: ; preds = %bb97 - %cond1119 = icmp ne i32 %cast1116, 0 ; [#uses=1] - br i1 %cond1119, label %bb104, label %bb99 - -bb99: ; preds = %bb98 - %reg1122 = getelementptr i16* %reg382, i64 1 ; [#uses=2] - store i16* %reg1122, i16** @yyssp - store i16 1, i16* %reg1122 - %reg403 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1128 = getelementptr %YYSTYPE* %reg403, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg1128, %YYSTYPE** @yyvsp - %reg406 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg1128.idx1 = getelementptr %YYSTYPE* %reg403, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg406, %IntList* %reg1128.idx1 - %reg407 = load i32* @yychar ; [#uses=1] - %cond1135 = icmp sge i32 %reg407, 0 ; [#uses=1] - br i1 %cond1135, label %bb102, label %bb100 - -bb100: ; preds = %bb99 - %reg1139 = call i32 @yylex( ) ; [#uses=1] - store i32 %reg1139, i32* @yychar - %reg409 = load i32* @yychar ; [#uses=1] - %cond1141 = icmp sge i32 %reg409, 0 ; [#uses=1] - br i1 %cond1141, label %bb102, label %bb101 - -bb101: ; preds = %bb100 - store i32 0, i32* @yychar - br label %bb102 - -bb102: ; preds = %bb101, %bb100, %bb99 - %reg411 = load i32* @yychar ; [#uses=1] - %cond1146 = icmp ne i32 %reg411, 0 ; [#uses=1] - br i1 %cond1146, label %bb4, label %UnifiedExitNode - -bb104: ; preds = %bb98, %bb97 - %reg398-idxcast = sext i16 %reg398 to i64 ; [#uses=2] - %reg1150 = getelementptr [12 x i16]* @yygindex, i64 0, i64 %reg398-idxcast ; [#uses=1] - %reg418 = load i16* %reg1150 ; [#uses=1] - %cast1155 = sext i16 %reg418 to i32 ; [#uses=2] - %cond1156 = icmp eq i32 %cast1155, 0 ; [#uses=1] - br i1 %cond1156, label %bb109, label %bb105 - -bb105: ; preds = %bb104 - %reg473 = add i32 %cast1155, %cast1103 ; [#uses=3] - %cond1158 = icmp slt i32 %reg473, 0 ; [#uses=1] - br i1 %cond1158, label %bb109, label %bb106 - -bb106: ; preds = %bb105 - %cond1161 = icmp sgt i32 %reg473, 262 ; [#uses=1] - br i1 %cond1161, label %bb109, label %bb107 - -bb107: ; preds = %bb106 - %reg473-idxcast = sext i32 %reg473 to i64 ; [#uses=2] - %reg1166 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg473-idxcast ; [#uses=1] - %reg428 = load i16* %reg1166 ; [#uses=1] - %cast1171 = sext i16 %reg428 to i32 ; [#uses=1] - %cond1172 = icmp ne i32 %cast1171, %cast1103 ; [#uses=1] - br i1 %cond1172, label %bb109, label %bb108 - -bb108: ; preds = %bb107 - %reg1175 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg473-idxcast ; [#uses=1] - %reg435 = load i16* %reg1175 ; [#uses=1] - %cast1180 = sext i16 %reg435 to i32 ; [#uses=1] - br label %bb110 - -bb109: ; preds = %bb107, %bb106, %bb105, %bb104 - %reg1183 = getelementptr [12 x i16]* @yydgoto, i64 0, i64 %reg398-idxcast ; [#uses=1] - %reg442 = load i16* %reg1183 ; [#uses=1] - %cast1188 = sext i16 %reg442 to i32 ; [#uses=1] - br label %bb110 - -bb110: ; preds = %bb109, %bb108 - %reg476 = phi i32 [ %cast1188, %bb109 ], [ %cast1180, %bb108 ] ; [#uses=2] - %cast1189 = bitcast i16* %reg382 to i8* ; [#uses=1] - %reg444 = load i16** @yysslim ; [#uses=1] - %cast1190 = bitcast i16* %reg444 to i8* ; [#uses=1] - %cond1191 = icmp ult i8* %cast1189, %cast1190 ; [#uses=1] - br i1 %cond1191, label %bb112, label %bb111 - -bb111: ; preds = %bb110 - %reg1193 = call i32 @yygrowstack( ) ; [#uses=1] - %cond1193 = icmp ne i32 %reg1193, 0 ; [#uses=1] - br i1 %cond1193, label %bb113, label %bb112 - -bb112: ; preds = %bb111, %bb110 - %reg446 = load i16** @yyssp ; [#uses=1] - %reg1196 = getelementptr i16* %reg446, i64 1 ; [#uses=2] - store i16* %reg1196, i16** @yyssp - %cast1357 = trunc i32 %reg476 to i16 ; [#uses=1] - store i16 %cast1357, i16* %reg1196 - %reg449 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1202 = getelementptr %YYSTYPE* %reg449, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg1202, %YYSTYPE** @yyvsp - %reg452 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg1202.idx1 = getelementptr %YYSTYPE* %reg449, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg452, %IntList* %reg1202.idx1 - br label %bb4 - -bb113: ; preds = %bb111, %bb30, %bb13, %bb2 - call void @yyerror( i8* getelementptr ([20 x i8]* @.LC1, i64 0, i64 0) ) - br label %UnifiedExitNode - -UnifiedExitNode: ; preds = %bb113, %bb102, %bb34, %bb32 - %UnifiedRetVal = phi i32 [ 1, %bb113 ], [ 1, %bb34 ], [ 1, %bb32 ], [ 0, %bb102 ] ; [#uses=1] - ret i32 %UnifiedRetVal -} - -declare %List @newList(i8*, %List) - -declare %IntList @newIntList(i32, %IntList) - -declare void @doStart(i8*) - -declare void @yyerror(i8*) - -declare void @doSpec(%List, %List) - -declare %Arity @newArity(i32, %List) - -declare %Binding @newBinding(i8*, i32) - -declare %PatternAST @newPatternAST(i8*, %List) - -declare %RuleAST @newRuleAST(i8*, %PatternAST, i32, %IntList) - -declare void @yyfinished() - -declare i32 @yylex() - -declare void @doGram(%List) - -declare i32 @yygrowstack() Removed: llvm/trunk/test/CodeGen/Generic/spillccr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/spillccr.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/spillccr.ll (original) +++ llvm/trunk/test/CodeGen/Generic/spillccr.ll (removed) @@ -1,49 +0,0 @@ -; RUN: llc < %s - -; July 6, 2002 -- LLC Regression test -; This test case checks if the integer CC register %xcc (or %ccr) -; is correctly spilled. The code fragment came from function -; MakeGraph in Olden-mst. -; The original code made all comparisons with 0, so that the %xcc -; register is not needed for the branch in the first basic block. -; Replace 0 with 1 in the first comparson so that the -; branch-on-register instruction cannot be used directly, i.e., -; the %xcc register is needed for the first branch. -; - - %Graph = type %struct.graph_st* - %Hash = type %struct.hash* - %HashEntry = type %struct.hash_entry* - %Vertex = type %struct.vert_st* - %struct.graph_st = type { [1 x %Vertex] } - %struct.hash = type { %HashEntry*, i32 (i32)*, i32 } - %struct.hash_entry = type { i32, i8*, %HashEntry } - %struct.vert_st = type { i32, %Vertex, %Hash } - at HashRange = external global i32 ; [#uses=0] - at .LC0 = internal global [13 x i8] c"Make phase 2\00" ; <[13 x i8]*> [#uses=0] - at .LC1 = internal global [13 x i8] c"Make phase 3\00" ; <[13 x i8]*> [#uses=0] - at .LC2 = internal global [13 x i8] c"Make phase 4\00" ; <[13 x i8]*> [#uses=0] - at .LC3 = internal global [15 x i8] c"Make returning\00" ; <[15 x i8]*> [#uses=0] - -define %Graph @MakeGraph(i32 %numvert, i32 %numproc) { -bb1: - %reg111 = add i32 %numproc, -1 ; [#uses=2] - %cond275 = icmp slt i32 %reg111, 1 ; [#uses=1] - %cond276 = icmp sle i32 %reg111, 0 ; [#uses=1] - %cond277 = icmp sge i32 %numvert, 0 ; [#uses=1] - %reg162 = add i32 %numvert, 3 ; [#uses=0] - br i1 %cond275, label %bb7, label %bb4 - -bb4: ; preds = %bb1 - br i1 %cond276, label %bb7, label %bb5 - -bb5: ; preds = %bb4 - br i1 %cond277, label %bb7, label %bb6 - -bb6: ; preds = %bb5 - ret %Graph null - -bb7: ; preds = %bb5, %bb4, %bb1 - ret %Graph null -} - Removed: llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll (removed) @@ -1,237 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic - - %struct.XXActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } - %struct.XXAlphaTest = type { float, i16, i8, i8 } - %struct.XXArrayRange = type { i8, i8, i8, i8 } - %struct.XXBlendMode = type { i16, i16, i16, i16, %struct.ZZIColor4, i16, i16, i8, i8, i8, i8 } - %struct.XXBBRec = type opaque - %struct.XXBBstate = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, %struct.XXProgramLimits, %struct.XXProgramLimits, i8, i8, i8, i8, %struct.ZZSBB, %struct.ZZSBB, [4 x %struct.ZZSBB], %struct.ZZSBB, %struct.ZZSBB, %struct.ZZSBB, [8 x %struct.ZZSBB], %struct.ZZSBB } - %struct.XXClearColor = type { double, %struct.ZZIColor4, %struct.ZZIColor4, float, i32 } - %struct.XXClipPlane = type { i32, [6 x %struct.ZZIColor4] } - %struct.XXColorBB = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 } - %struct.XXColorMatrix = type { [16 x float]*, %struct.XXImagingColorScale } - %struct.XXConfig = type { i32, float, %struct.ZZGTransformKey, %struct.ZZGTransformKey, i8, i8, i8, i8, i8, i8, i16, i32, i32, i32, %struct.XXPixelFormatInfo, %struct.XXPointLineLimits, %struct.XXPointLineLimits, %struct.XXRenderFeatures, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.XXTextureLimits, [3 x %struct.XXPipelineProgramLimits], %struct.XXFragmentProgramLimits, %struct.XXVertexProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXVertexDescriptor*, %struct.XXVertexDescriptor*, [3 x i32], [4 x i32], [0 x i32] } - %struct.XXContextRec = type { float, float, float, float, float, float, float, float, %struct.ZZIColor4, %struct.ZZIColor4, %struct.YYFPContext, [16 x [2 x %struct.PPStreamToken]], %struct.ZZGProcessor, %struct._YYConstants*, void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)*, %struct._YYFunction*, %struct.PPStreamToken*, void (%struct.XXContextRec*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, %struct.XXVertex*)*, %struct._YYFunction*, %struct._YYFunction*, %struct._YYFunction*, [4 x i32], [3 x i32], [3 x i32], float, float, float, %struct.PPStreamToken, i32, %struct.ZZSDrawable, %struct.XXFramebufferRec*, %struct.XXFramebufferRec*, %struct.XXRect, %struct.XXFormat, %struct.XXFormat, %struct.XXFormat, %struct.XXConfig*, %struct.XXBBstate, %struct.XXBBstate, %struct.XXSharedRec*, %struct.XXState*, %struct.XXPluginSta te*, %struct.XXVertex*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.XXProgramRec*, %struct.XXPipelineProgramRec*, %struct.YYTextures, %struct.XXStippleData, i8, i16, i8, i32, i32, i32, %struct.XXQueryRec*, %struct.XXQueryRec*, %struct.XXFallback, { void (i8*, i8*, i32, i8*)* } } - %struct.XXConvolution = type { %struct.ZZIColor4, %struct.XXImagingColorScale, i16, i16, [0 x i32], float*, i32, i32 } - %struct.XXCurrent16A = type { [8 x %struct.ZZIColor4], [16 x %struct.ZZIColor4], %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, [4 x float], %struct.XXPointLineLimits, float, float, float, float, i8, i8, i8, i8 } - %struct.XXDepthTest = type { i16, i16, i8, i8, i8, i8, double, double } - %struct.XXDrawableWindow = type { i32, i32, i32 } - %struct.XXFallback = type { float*, %struct.XXRenderDispatch*, %struct.XXConfig*, i8*, i8*, i32, i32 } - %struct.XXFenceRec = type opaque - %struct.XXFixedFunction = type { %struct.PPStreamToken* } - %struct.XXFogMode = type { %struct.ZZIColor4, float, float, float, float, float, i16, i16, i16, i8, i8 } - %struct.XXFormat = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32 } - %struct.XXFragmentProgramLimits = type { i32, i32, i32, i16, i16, i32, i32 } - %struct.XXFramebufferAttachment = type { i16, i16, i32, i32, i32 } - %struct.XXFramebufferData = type { [10 x %struct.XXFramebufferAttachment], [8 x i16], i16, i16, i16, i8, i8, i32, i32 } - %struct.XXFramebufferRec = type { %struct.XXFramebufferData*, %struct.XXPluginFramebufferData*, %struct.XXFormat, i8, i8, i8, i8 } - %struct.XXGeometryShaderLimits = type { i32, i32, i32, i32, i32 } - %struct.XXHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } - %struct.XXHistogram = type { %struct.XXProgramLimits*, i32, i16, i8, i8 } - %struct.XXImagingColorScale = type { %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2 } - %struct.XXImagingSubset = type { %struct.XXConvolution, %struct.XXConvolution, %struct.XXConvolution, %struct.XXColorMatrix, %struct.XXMinmax, %struct.XXHistogram, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, i32, [0 x i32] } - %struct.XXLight = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, float, float, float, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, float, float, float, float } - %struct.XXLightModel = type { %struct.ZZIColor4, [8 x %struct.XXLight], [2 x %struct.XXMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 } - %struct.XXLightProduct = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 } - %struct.XXLogicOp = type { i16, i8, i8 } - %struct.XXMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXMaterial = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, float, float, float, float, [8 x %struct.XXLightProduct], %struct.ZZIColor4, [8 x i32] } - %struct.XXMinmax = type { %struct.XXMinmaxTable*, i16, i8, i8, [0 x i32] } - %struct.XXMinmaxTable = type { %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] } - %struct.XXMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPipelineProgramData = type { i16, i8, i8, i32, %struct.PPStreamToken*, i64, %struct.ZZIColor4*, i32, [0 x i32] } - %struct.XXPipelineProgramLimits = type { i32, i16, i16, i32, i16, i16, i32, i32 } - %struct.XXPipelineProgramRec = type { %struct.XXPipelineProgramData*, %struct.PPStreamToken*, %struct.XXContextRec*, { %struct._YYFunction*, \2, \2, [20 x i32], [64 x i32], i32, i32, i32 }*, i32, i32 } - %struct.XXPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.ZZIColor4* } - %struct.XXPixelFormatInfo = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.XXPixelMode = type { float, float, %struct.XXPixelStore, %struct.XXPixelTransfer, %struct.XXPixelMap, %struct.XXImagingSubset, i32, i32 } - %struct.XXPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 } - %struct.XXPixelStore = type { %struct.XXPixelPack, %struct.XXPixelPack } - %struct.XXPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float } - %struct.XXPluginFramebufferData = type { [10 x %struct.XXTextureRec*], i8, i8, i8, i8 } - %struct.XXPluginProgramData = type { [3 x %struct.XXPipelineProgramRec*], %struct.XXBBRec**, i32, [0 x i32] } - %struct.XXPluginState = type { [16 x [5 x %struct.XXTextureRec*]], [3 x %struct.XXTextureRec*], [3 x %struct.XXPipelineProgramRec*], [3 x %struct.XXPipelineProgramRec*], %struct.XXProgramRec*, %struct.XXVertexArrayRec*, [16 x %struct.XXBBRec*], %struct.XXFramebufferRec*, %struct.XXFramebufferRec* } - %struct.XXPointLineLimits = type { float, float, float } - %struct.XXPointMode = type { float, float, float, float, %struct.XXPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 } - %struct.XXPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXProgramData = type { i32, i32, i32, i32, %struct.PPStreamToken*, i32*, i32, i32, i32, i32, i8, i8, i8, i8, [0 x i32] } - %struct.XXProgramLimits = type { i32, i32, i32, i32 } - %struct.XXProgramRec = type { %struct.XXProgramData*, %struct.XXPluginProgramData*, %struct.ZZIColor4**, i32 } - %struct.XXQueryRec = type { i32, i32, %struct.XXQueryRec* } - %struct.XXRect = type { i32, i32, i32, i32, i32, i32 } - %struct.XXRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.ZZIColor4], [8 x %struct.XXRegisterCombinersPerStageState], %struct.XXRegisterCombinersFinalStageState } - %struct.XXRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXRegisterCombinersPerVariableState] } - %struct.XXRegisterCombinersPerPortionState = type { [4 x %struct.XXRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 } - %struct.XXRegisterCombinersPerStageState = type { [2 x %struct.XXRegisterCombinersPerPortionState], [2 x %struct.ZZIColor4] } - %struct.XXRegisterCombinersPerVariableState = type { i16, i16, i16, i16 } - %struct.XXRenderDispatch = type { void (%struct.XXContextRec*, i32, float)*, void (%struct.XXContextRec*, i32)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, float, float, i8*, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %st ruct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32*)*, void (%struct.XXContextRec*, i32, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, %struct.XXFenceRec*)*, void (%struct.XXContextRec*, i32, %struct.XXQueryRec*)*, void (%struct.XXContextRec*, %struct.XXQueryRec*)*, i32 (%struct.XXContextRec* , i32, i32, i32, i32, i32, i8*, %struct.ZZIColor4*, %struct.XXCurrent16A*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32)*, i32 (%struct.XXContextRec*, %struct.XXBBRec*, i32, i32, i8*)*, void (%struct.XXContextRec*, i32)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXQueryRec*)*, void (%struct.XXContextRec*)* } - %struct.XXRenderFeatures = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXSWRSurfaceRec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 } - %struct.XXScissorTest = type { %struct.XXProgramLimits, i8, i8, i8, i8 } - %struct.XXSharedData = type { } - %struct.XXSharedRec = type { %struct.__ZZarrayelementDrawInfoListType, %struct.XXSharedData*, i32, i8, i8, i8, i8 } - %struct.XXState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.ZZIColor4], [128 x %struct.ZZIColor4], %struct.XXViewport, %struct.XXTransform, %struct.XXLightModel, %struct.XXActiveTextureTargets, %struct.XXAlphaTest, %struct.XXBlendMode, %struct.XXClearColor, %struct.XXColorBB, %struct.XXDepthTest, %struct.XXArrayRange, %struct.XXFogMode, %struct.XXHintMode, %struct.XXLineMode, %struct.XXLogicOp, %struct.XXMaskMode, %struct.XXPixelMode, %struct.XXPointMode, %struct.XXPolygonMode, %struct.XXScissorTest, i32, %struct.XXStencilTest, [8 x %struct.XXTextureMode], [16 x %struct.XXTextureImageMode], %struct.XXArrayRange, [8 x %struct.XXTextureCoordGen], %struct.XXClipPlane, %struct.XXMultisample, %struct.XXRegisterCombiners, %struct.XXArrayRange, %struct.XXArrayRange, [3 x %struct.XXPipelineProgramState], %struct.XXArrayRange, %struct.XXTransformFeedback, i32*, %struct.XXFixedFunction, [1 x i32] }> - %struct.XXStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] } - %struct.XXStippleData = type { i32, i16, i16, [32 x [32 x i8]] } - %struct.XXTextureCoordGen = type { { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, i8, i8, i8, i8 } - %struct.XXTextureGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] } - %struct.XXTextureImageMode = type { float } - %struct.XXTextureLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* } - %struct.XXTextureLimits = type { float, float, i16, i16, i16, i16, i16, i16, i16, i16, i16, i8, i8, [16 x i16], i32 } - %struct.XXTextureMode = type { %struct.ZZIColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float } - %struct.XXTextureParamState = type { i16, i16, i16, i16, i16, i16, %struct.ZZIColor4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* } - %struct.XXTextureRec = type { [4 x float], %struct.XXTextureState*, %struct.XXMipmaplevel*, %struct.XXMipmaplevel*, float, float, float, float, i8, i8, i8, i8, i16, i16, i16, i16, i32, float, [2 x %struct.PPStreamToken] } - %struct.XXTextureState = type { i16, i8, i8, i16, i16, float, i32, %struct.XXSWRSurfaceRec*, %struct.XXTextureParamState, %struct.XXTextureGeomState, i16, i16, i8*, %struct.XXTextureLevel, [1 x [15 x %struct.XXTextureLevel]] } - %struct.XXTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }> - %struct.XXTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] } - %struct.XXVertex = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.ZZIColor4, float, i8, i8, i8, i8, float, float, i32, i32, i32, i32, [4 x float], [2 x %struct.XXMaterial*], [2 x i32], [8 x %struct.ZZIColor4] } - %struct.XXVertexArrayRec = type opaque - %struct.XXVertexDescriptor = type { i8, i8, i8, i8, [0 x i32] } - %struct.XXVertexProgramLimits = type { i16, i16, i32, i32 } - %struct.XXViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float } - %struct.ZZGColorTable = type { i32, i32, i32, i8* } - %struct.ZZGOperation = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, %struct.ZZGColorTable, %struct.ZZGColorTable, %struct.ZZGColorTable } - %struct.ZZGProcessor = type { void (%struct.XXPixelMode*, %struct.ZZGOperation*, %struct._ZZGProcessorData*, %union._ZZGFunctionKey*)*, %struct._YYFunction*, %union._ZZGFunctionKey*, %struct._ZZGProcessorData* } - %struct.ZZGTransformKey = type { i32, i32 } - %struct.ZZIColor4 = type { float, float, float, float } - %struct.ZZSBB = type { i8* } - %struct.ZZSDrawable = type { %struct.ZZSWindowRec* } - %struct.ZZSWindowRec = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, i32, i32, %struct.ZZSDrawable, i8*, i8*, i8*, i8*, i8*, [4 x i8*], i32, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, %struct.XXDrawableWindow, i32, i32, i8*, i8* } - %struct.ZZTCoord2 = type { float, float } - %struct.YYFPContext = type { float, i32, i32, i32, float, [3 x float] } - %struct.YYFragmentAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] } - %struct.YYTextures = type { [16 x %struct.XXTextureRec*] } - %struct.PPStreamToken = type { { i16, i16, i32 } } - %struct._ZZGProcessorData = type { void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, i8* (i32)*, void (i8*)* } - %struct._YYConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } } - %struct._YYFunction = type opaque - %struct.__ZZarrayelementDrawInfoListType = type { i32, [40 x i8] } - %union._ZZGFunctionKey = type opaque - at llvm.used = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define void @t(%struct.XXContextRec* %ctx, i32 %x, i32 %y, %struct.YYFragmentAttrib* %start, %struct.YYFragmentAttrib* %deriv, i32 %num_frags) nounwind { -entry: - %tmp7485.i.i.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp8382.i.i.i = extractelement <4 x i32> zeroinitializer, i32 1 ; [#uses=1] - %tmp8383.i.i.i = extractelement <4 x i32> zeroinitializer, i32 2 ; [#uses=2] - %tmp8384.i.i.i = extractelement <4 x i32> zeroinitializer, i32 3 ; [#uses=2] - br label %bb7551.i.i.i - -bb4426.i.i.i: ; preds = %bb7551.i.i.i - %0 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %1 = bitcast [4 x i32]* %0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %2 = load <4 x i32>* %1, align 16 ; <<4 x i32>> [#uses=1] - %3 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %4 = bitcast [4 x i32]* %3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] - %6 = shufflevector <4 x i32> %2, <4 x i32> %5, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1] - %7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1] - %8 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %7, <2 x i32> < i32 1, i32 3 > ; <<2 x i64>> [#uses=1] - %9 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8382.i.i.i, i32 6 ; [#uses=1] - %10 = load float** %9, align 4 ; [#uses=1] - %11 = bitcast float* %10 to i8* ; [#uses=1] - %12 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 6 ; [#uses=1] - %13 = load float** %12, align 4 ; [#uses=1] - %14 = bitcast float* %13 to i8* ; [#uses=1] - %15 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 6 ; [#uses=1] - %16 = load float** %15, align 4 ; [#uses=1] - %17 = bitcast float* %16 to i8* ; [#uses=1] - %tmp7308.i.i.i = and <2 x i64> zeroinitializer, %8 ; <<2 x i64>> [#uses=1] - %18 = bitcast <2 x i64> %tmp7308.i.i.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %19 = mul <4 x i32> %18, zeroinitializer ; <<4 x i32>> [#uses=1] - %20 = add <4 x i32> %19, zeroinitializer ; <<4 x i32>> [#uses=3] - %21 = load i32* null, align 4 ; [#uses=0] - %22 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind readnone ; <<4 x float>> [#uses=1] - %23 = fmul <4 x float> %22, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2114.i119.i.i = extractelement <4 x i32> %20, i32 1 ; [#uses=1] - %24 = shl i32 %tmp2114.i119.i.i, 2 ; [#uses=1] - %25 = getelementptr i8* %11, i32 %24 ; [#uses=1] - %26 = bitcast i8* %25 to i32* ; [#uses=1] - %27 = load i32* %26, align 4 ; [#uses=1] - %28 = or i32 %27, -16777216 ; [#uses=1] - %tmp1927.i120.i.i = insertelement <4 x i32> undef, i32 %28, i32 0 ; <<4 x i32>> [#uses=1] - %29 = bitcast <4 x i32> %tmp1927.i120.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %30 = shufflevector <16 x i8> %29, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %31 = bitcast <16 x i8> %30 to <8 x i16> ; <<8 x i16>> [#uses=1] - %32 = shufflevector <8 x i16> %31, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %33 = bitcast <8 x i16> %32 to <4 x i32> ; <<4 x i32>> [#uses=1] - %34 = shufflevector <4 x i32> %33, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %35 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %34) nounwind readnone ; <<4 x float>> [#uses=1] - %36 = fmul <4 x float> %35, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2113.i124.i.i = extractelement <4 x i32> %20, i32 2 ; [#uses=1] - %37 = shl i32 %tmp2113.i124.i.i, 2 ; [#uses=1] - %38 = getelementptr i8* %14, i32 %37 ; [#uses=1] - %39 = bitcast i8* %38 to i32* ; [#uses=1] - %40 = load i32* %39, align 4 ; [#uses=1] - %41 = or i32 %40, -16777216 ; [#uses=1] - %tmp1963.i125.i.i = insertelement <4 x i32> undef, i32 %41, i32 0 ; <<4 x i32>> [#uses=1] - %42 = bitcast <4 x i32> %tmp1963.i125.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %43 = shufflevector <16 x i8> %42, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %44 = bitcast <16 x i8> %43 to <8 x i16> ; <<8 x i16>> [#uses=1] - %45 = shufflevector <8 x i16> %44, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %46 = bitcast <8 x i16> %45 to <4 x i32> ; <<4 x i32>> [#uses=1] - %47 = shufflevector <4 x i32> %46, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %48 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %47) nounwind readnone ; <<4 x float>> [#uses=1] - %49 = fmul <4 x float> %48, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2112.i129.i.i = extractelement <4 x i32> %20, i32 3 ; [#uses=1] - %50 = shl i32 %tmp2112.i129.i.i, 2 ; [#uses=1] - %51 = getelementptr i8* %17, i32 %50 ; [#uses=1] - %52 = bitcast i8* %51 to i32* ; [#uses=1] - %53 = load i32* %52, align 4 ; [#uses=1] - %54 = or i32 %53, -16777216 ; [#uses=1] - %tmp1999.i130.i.i = insertelement <4 x i32> undef, i32 %54, i32 0 ; <<4 x i32>> [#uses=1] - %55 = bitcast <4 x i32> %tmp1999.i130.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %56 = shufflevector <16 x i8> %55, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %57 = bitcast <16 x i8> %56 to <8 x i16> ; <<8 x i16>> [#uses=1] - %58 = shufflevector <8 x i16> %57, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %59 = bitcast <8 x i16> %58 to <4 x i32> ; <<4 x i32>> [#uses=1] - %60 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %61 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %60) nounwind readnone ; <<4 x float>> [#uses=1] - %62 = fmul <4 x float> %61, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %63 = fmul <4 x float> %23, zeroinitializer ; <<4 x float>> [#uses=1] - %64 = fadd <4 x float> zeroinitializer, %63 ; <<4 x float>> [#uses=1] - %65 = fmul <4 x float> %36, zeroinitializer ; <<4 x float>> [#uses=1] - %66 = fadd <4 x float> zeroinitializer, %65 ; <<4 x float>> [#uses=1] - %67 = fmul <4 x float> %49, zeroinitializer ; <<4 x float>> [#uses=1] - %68 = fadd <4 x float> zeroinitializer, %67 ; <<4 x float>> [#uses=1] - %69 = fmul <4 x float> %62, zeroinitializer ; <<4 x float>> [#uses=1] - %70 = fadd <4 x float> zeroinitializer, %69 ; <<4 x float>> [#uses=1] - %tmp7452.i.i.i = bitcast <4 x float> %64 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7454.i.i.i = and <4 x i32> %tmp7452.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7459.i.i.i = or <4 x i32> %tmp7454.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7460.i.i.i = bitcast <4 x i32> %tmp7459.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7468.i.i.i = bitcast <4 x float> %66 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7470.i.i.i = and <4 x i32> %tmp7468.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7475.i.i.i = or <4 x i32> %tmp7470.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7476.i.i.i = bitcast <4 x i32> %tmp7475.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7479.i.i.i = bitcast <4 x float> %.279.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7480.i.i.i = and <4 x i32> zeroinitializer, %tmp7479.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7484.i.i.i = bitcast <4 x float> %68 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7486.i.i.i = and <4 x i32> %tmp7484.i.i.i, %tmp7485.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7491.i.i.i = or <4 x i32> %tmp7486.i.i.i, %tmp7480.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7492.i.i.i = bitcast <4 x i32> %tmp7491.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7495.i.i.i = bitcast <4 x float> %.380.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7496.i.i.i = and <4 x i32> zeroinitializer, %tmp7495.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7500.i.i.i = bitcast <4 x float> %70 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7502.i.i.i = and <4 x i32> %tmp7500.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7507.i.i.i = or <4 x i32> %tmp7502.i.i.i, %tmp7496.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7508.i.i.i = bitcast <4 x i32> %tmp7507.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %indvar.next.i.i.i = add i32 %aniso.0.i.i.i, 1 ; [#uses=1] - br label %bb7551.i.i.i - -bb7551.i.i.i: ; preds = %bb4426.i.i.i, %entry - %.077.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7460.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.178.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7476.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.279.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7492.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %.380.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7508.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %aniso.0.i.i.i = phi i32 [ 0, %entry ], [ %indvar.next.i.i.i, %bb4426.i.i.i ] ; [#uses=1] - br i1 false, label %glvmInterpretFPTransformFour6.exit, label %bb4426.i.i.i - -glvmInterpretFPTransformFour6.exit: ; preds = %bb7551.i.i.i - unreachable -} - -declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone Removed: llvm/trunk/test/CodeGen/X86/pr2623.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr2623.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr2623.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr2623.ll (removed) @@ -1,44 +0,0 @@ -; RUN: llc < %s -; PR2623 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-unknown-freebsd7.0" - %.objc_id = type { %.objc_id }* - %.objc_selector = type { i8*, i8* }* - at .objc_sel_ptr = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr13 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr14 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr15 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr16 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr17 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr18 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr19 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr20 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - at .objc_sel_ptr21 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - - at .objc_untyped_selector_alias = alias internal %.objc_selector* @.objc_sel_ptr15 ; <%.objc_selector*> [#uses=0] - at .objc_untyped_selector_alias1 = alias internal %.objc_selector* @.objc_sel_ptr ; <%.objc_selector*> [#uses=0] - at .objc_untyped_selector_alias2 = alias internal %.objc_selector* @.objc_sel_ptr17 ; <%.objc_selector*> [#uses=0] - at .objc_untyped_selector_alias3 = alias internal %.objc_selector* @.objc_sel_ptr16 ; <%.objc_selector*> [#uses=0] - at .objc_untyped_selector_alias4 = alias internal %.objc_selector* @.objc_sel_ptr13 ; <%.objc_selector*> [#uses=0] - at .objc_untyped_selector_alias7 = alias internal %.objc_selector* @.objc_sel_ptr14 ; <%.objc_selector*> [#uses=0] - at getRange = alias internal %.objc_selector* @.objc_sel_ptr18 ; <%.objc_selector*> [#uses=0] -@"valueWithRange:" = alias internal %.objc_selector* @.objc_sel_ptr21 ; <%.objc_selector*> [#uses=0] - at rangeValue = alias internal %.objc_selector* @.objc_sel_ptr20 ; <%.objc_selector*> [#uses=0] -@"printRange:" = alias internal %.objc_selector* @.objc_sel_ptr19 ; <%.objc_selector*> [#uses=0] - -define void @"._objc_method_SmalltalkTool()-run"(i8* %self, %.objc_selector %_cmd) { -entry: - br i1 false, label %small_int_messagerangeValue, label %real_object_messagerangeValue - -small_int_messagerangeValue: ; preds = %entry - br label %Continue - -real_object_messagerangeValue: ; preds = %entry - br label %Continue - -Continue: ; preds = %real_object_messagerangeValue, %small_int_messagerangeValue - %rangeValue = phi { i32, i32 } [ undef, %small_int_messagerangeValue ], [ undef, %real_object_messagerangeValue ] ; <{ i32, i32 }> [#uses=1] - call void (%.objc_id, %.objc_selector, ...)* null( %.objc_id null, %.objc_selector null, { i32, i32 } %rangeValue ) - ret void -} Removed: llvm/trunk/test/CodeGen/X86/twoaddr-remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/twoaddr-remat.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/twoaddr-remat.ll (original) +++ llvm/trunk/test/CodeGen/X86/twoaddr-remat.ll (removed) @@ -1,67 +0,0 @@ -; RUN: llc < %s -march=x86 | grep 59796 | count 3 - - %Args = type %Value* - %Exec = type opaque* - %Identifier = type opaque* - %JSFunction = type %Value (%Exec, %Scope, %Value, %Args) - %PropertyNameArray = type opaque* - %Scope = type opaque* - %Value = type opaque* - -declare i1 @X1(%Exec) readonly - -declare %Value @X2(%Exec) - -declare i32 @X3(%Exec, %Value) - -declare %Value @X4(i32) readnone - -define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind { -prologue: - %eh_check = tail call i1 @X1( %Exec %exec ) readonly ; [#uses=1] - br i1 %eh_check, label %exception, label %no_exception - -exception: ; preds = %no_exception, %prologue - %rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1] - ret %Value %rethrow_result - -no_exception: ; preds = %prologue - %args_intptr = bitcast %Args %args to i32* ; [#uses=1] - %argc_val = load i32* %args_intptr ; [#uses=1] - %cmpParamArgc = icmp sgt i32 %argc_val, 0 ; [#uses=1] - %arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1] - %arg_val = load %Args %arg_ptr ; <%Value> [#uses=1] - %ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1] - %toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; [#uses=3] - %eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; [#uses=1] - br i1 %eh_check6, label %exception, label %no_exception7 - -no_exception7: ; preds = %no_exception - %shl_tmp_result = shl i32 %toInt325, 1 ; [#uses=1] - %rhs_masked13 = and i32 %shl_tmp_result, 14 ; [#uses=1] - %ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; [#uses=1] - %and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; [#uses=1] - %ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; [#uses=1] - %rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; [#uses=1] - %ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; [#uses=1] - %and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; [#uses=1] - %addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; [#uses=1] - %ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; [#uses=1] - %rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; [#uses=1] - %ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; [#uses=1] - %and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; [#uses=1] - %addconv82 = add i32 %addconv, %and_tmp_result70 ; [#uses=3] - %rangetmp = add i32 %addconv82, 536870912 ; [#uses=1] - %rangecmp = icmp ult i32 %rangetmp, 1073741824 ; [#uses=1] - br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow - -NumberLiteralIntFast: ; preds = %no_exception7 - %imm_shift = shl i32 %addconv82, 2 ; [#uses=1] - %imm_or = or i32 %imm_shift, 3 ; [#uses=1] - %imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1] - ret %Value %imm_val - -NumberLiteralIntSlow: ; preds = %no_exception7 - %toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1] - ret %Value %toVal -} Removed: llvm/trunk/test/Feature/opaquetypes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/opaquetypes.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/Feature/opaquetypes.ll (original) +++ llvm/trunk/test/Feature/opaquetypes.ll (removed) @@ -1,52 +0,0 @@ -; RUN: llvm-as < %s | llvm-dis > %t1.ll -; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll -; RUN: diff %t1.ll %t2.ll - -; This test case is used to test opaque type processing, forward references, -; and recursive types. Oh my. -; - -%SQ1 = type { i32 } -%SQ2 = type { %ITy } -%ITy = type i32 - - -%CCC = type { \2* } -%BBB = type { \2*, \2 * } -%AAA = type { \2*, {\2*}, [12x{\2*}], {[1x{\2*}]} } - -; Test numbered types -%0 = type %CCC -%1 = type %BBB -%Composite = type { %0, %1 } - -; Perform a simple forward reference... -%ty1 = type { %ty2, i32 } -%ty2 = type float - -; Do a recursive type... -%list = type { %list * } -%listp = type { %listp } * - -; Do two mutually recursive types... -%TyA = type { %ty2, %TyB * } -%TyB = type { double, %TyA * } - -; A complex recursive type... -%Y = type { {%Y*}, %Y* } -%Z = type { { %Z * }, [12x%Z] *, {{{ %Z * }}} } - -; More ridiculous test cases... -%A = type [ 123x %A*] -%M = type %M (%M, %M) * -%P = type %P* - -; Recursive ptrs -%u = type %v* -%v = type %u* - -; Test the parser for unnamed recursive types... -%P1 = type \1 * -%Y1 = type { { \3 * }, \2 * } -%Z1 = type { { \3 * }, [12x\3] *, { { { \5 * } } } } - Removed: llvm/trunk/test/Transforms/SimplifyCFG/2005-08-03-PHIFactorCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2005-08-03-PHIFactorCrash.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2005-08-03-PHIFactorCrash.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2005-08-03-PHIFactorCrash.ll (removed) @@ -1,75 +0,0 @@ -; RUN: opt < %s -simplifycfg -disable-output -; END. - - %arraytype.1.Char = type { i32, [0 x i8] } - %arraytype.4.Signed = type { i32, [0 x i32] } - %functiontype.23 = type %structtype.Task* (%structtype.Task*, %structtype.Packet*, %structtype.FailedRun*) - %functiontype.27 = type %structtype.object* () - %functiontype.28 = type i1 (%structtype.object*, %structtype.object_vtable*) - %functiontype.39 = type i32 (%structtype.listiter*) - %opaquetype.RuntimeTypeInfo = type i8* (i8*) - %structtype.AssertionError_vtable = type { %structtype.FailedRun_vtable } - %structtype.DeviceTask = type { %structtype.Task } - %structtype.FailedRun = type { %structtype.object } - %structtype.FailedRun_vtable = type { %structtype.object_vtable } - %structtype.Packet = type { %structtype.object, %structtype.list.1*, i32, i32, i32, %structtype.Packet* } - %structtype.Task = type { %structtype.TaskState, %structtype.FailedRun*, i32, %structtype.Packet*, %structtype.Task*, i32 } - %structtype.TaskState = type { %structtype.object, i1, i1, i1 } - %structtype.list.1 = type { %arraytype.4.Signed* } - %structtype.listiter = type { %structtype.list.1*, i32 } - %structtype.object = type { %structtype.object_vtable* } - %structtype.object_vtable = type { %structtype.object_vtable*, %opaquetype.RuntimeTypeInfo*, %arraytype.1.Char*, %functiontype.27* } - at structinstance.59 = external global %structtype.AssertionError_vtable ; <%structtype.AssertionError_vtable*> [#uses=0] - -declare fastcc i1 @ll_isinstance__objectPtr_object_vtablePtr() - -declare fastcc void @ll_listnext__listiterPtr() - -define fastcc void @WorkTask.fn() { -block0: - br label %block1 -block1: ; preds = %block0 - %v2542 = call fastcc i1 @ll_isinstance__objectPtr_object_vtablePtr( ) ; [#uses=1] - br i1 %v2542, label %block4, label %block2 -block2: ; preds = %block1 - br label %block3 -block3: ; preds = %block2 - unwind -block4: ; preds = %block1 - br label %block5 -block5: ; preds = %block4 - %v2565 = icmp eq %structtype.Packet* null, null ; [#uses=1] - br i1 %v2565, label %block15, label %block6 -block6: ; preds = %block5 - %self_2575 = phi %structtype.DeviceTask* [ null, %block5 ] ; <%structtype.DeviceTask*> [#uses=1] - br i1 false, label %block14, label %block7 -block7: ; preds = %block14, %block6 - %self_2635 = phi %structtype.DeviceTask* [ %self_2575, %block6 ], [ null, %block14 ] ; <%structtype.DeviceTask*> [#uses=1] - %tmp.124 = getelementptr %structtype.Packet* null, i32 0, i32 2 ; [#uses=0] - br label %block8 -block8: ; preds = %block10, %block7 - %self_2672 = phi %structtype.DeviceTask* [ %self_2635, %block7 ], [ null, %block10 ] ; <%structtype.DeviceTask*> [#uses=0] - invoke fastcc void @ll_listnext__listiterPtr( ) - to label %block9 unwind label %block8_exception_handling -block8_exception_handling: ; preds = %block8 - br i1 false, label %block8_exception_found_branchto_block12, label %block8_not_exception_structinstance.10 -block8_not_exception_structinstance.10: ; preds = %block8_exception_handling - unwind -block8_exception_found_branchto_block12: ; preds = %block8_exception_handling - br label %block12 -block9: ; preds = %block8 - br i1 false, label %block11, label %block10 -block10: ; preds = %block11, %block9 - br label %block8 -block11: ; preds = %block9 - br label %block10 -block12: ; preds = %block8_exception_found_branchto_block12 - br label %block13 -block13: ; preds = %block15, %block12 - ret void -block14: ; preds = %block6 - br label %block7 -block15: ; preds = %block5 - %v2586 = phi %structtype.DeviceTask* [ null, %block5 ] ; <%structtype.DeviceTask*> [#uses=0] - br label %block13 -} Removed: llvm/trunk/test/Transforms/SimplifyCFG/2009-03-05-Speculative-Hoist-Dbg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2009-03-05-Speculative-Hoist-Dbg.ll?rev=134819&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2009-03-05-Speculative-Hoist-Dbg.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2009-03-05-Speculative-Hoist-Dbg.ll (removed) @@ -1,108 +0,0 @@ -; RUN: opt < %s -simplifycfg -S | grep select - %llvm.dbg.anchor.type = type { i32, i32 } - %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } - - at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" - - at .str = internal constant [4 x i8] c"a.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at .str1 = internal constant [6 x i8] c"/tmp/\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1] - at .str2 = internal constant [55 x i8] c"4.2.1 (Based on Apple Inc. build 5636) (LLVM build 00)\00", section "llvm.metadata" ; <[55 x i8]*> [#uses=1] - at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([55 x i8]* @.str2, i32 0, i32 0), i1 true, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] - -declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind - -external global <{ i8 }> ; <<{ i8 }>*>:0 [#uses=0] - at __dso_handle = external global i8* ; [#uses=0] - at _ZSt3cin = external global { i32 (...)**, i32, { { i32 (...)**, i32, i32, i32, i32, i32, { \2, void (i32, \6*, i32)*, i32, i32 }*, { i8*, i32 }, [8 x { i8*, i32 }], i32, { i8*, i32 }*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }, { i32 (...)**, \3 }*, i8, i8, { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }*, { { i32 (...)**, i32 }, i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }*, { { i32 (...)**, i32 } }*, { { i32 (...)**, i32 } }* } } ; <{ i32 (...)**, i32, { { i32 (...)**, i32, i32, i32, i32, i32, { \2, void (i32, \6*, i32)*, i32, i32 }*, { i8*, i32 }, [8 x { i8*, i32 }], i32, { i8*, i32 }*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }, { i32 (...)**, \3 }*, i8, i8, { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }*, { { i32 (...)**, i32 }, i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }*, { { i32 (...)**, i32 } }*, { { i32 (...)**, i32 } }* } }*> [#uses=1] - at _ZSt4cout = external global { i32 (...)**, { { i32 (...)**, i32, i32, i32, i32, i32, { \2, void (i32, \6*, i32)*, i32, i32 }*, { i8*, i32 }, [8 x { i8*, i32 }], i32, { i8*, i32 }*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }, \3*, i8, i8, { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }*, { { i32 (...)**, i32 }, i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }*, { { i32 (...)**, i32 } }*, { { i32 (...)**, i32 } }* } } ; <{ i32 (...)**, { { i32 (...)**, i32, i32, i32, i32, i32, { \2, void (i32, \6*, i32)*, i32, i32 }*, { i8*, i32 }, [8 x { i8*, i32 }], i32, { i8*, i32 }*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }, \3*, i8, i8, { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, { { i32, { i32 (...)**, i32 }**, i32, { i32 (...)**, i32 }**, i8** }* } }*, { { i32 (...)**, i32 }, i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }*, { { i32 (...)**, i32 } }*, { { i32 (...)**, i32 } }* } }*> [#uses=1] -external constant [2 x i8] ; <[2 x i8]*>:1 [#uses=1] - at llvm.global_ctors = external global [1 x { i32, void ()* }] ; <[1 x { i32, void ()* }]*> [#uses=0] - -define i32 @main(i32, i8**) { -;
  • Function Type
  • Pointer Type
  • -
  • Opaque Type
  • -
  • Type Up-references
  • Constants @@ -1535,7 +1533,6 @@ function, pointer, structure, - packed structure, vector, opaque. @@ -1703,7 +1700,9 @@ possible to have a two dimensional array, using an array as the element type of another array.

    - +
  • + +

    Aggregate Types @@ -1842,9 +1841,7 @@

    Overview:

    The structure type is used to represent a collection of data members together - in memory. The packing of the field types is defined to match the ABI of the - underlying processor. The elements of a structure may be any type that has a - size.

    + in memory. The elements of a structure may be any type that has a size.

    Structures in memory are accessed using 'load' and 'store' by getting a pointer to a field @@ -1852,66 +1849,76 @@ Structures in registers are accessed using the 'extractvalue' and 'insertvalue' instructions.

    + +

    Structures may optionally be "packed" structures, which indicate that the + alignment of the struct is one byte, and that there is no padding between + the elements. In non-packed structs, padding between field types is defined + by the target data string to match the underlying processor.

    + +

    Structures can either be "anonymous" or "named". An anonymous structure is + defined inline with other types (e.g. {i32, i32}*) and a named types + are always defined at the top level with a name. Anonmyous types are uniqued + by their contents and can never be recursive since there is no way to write + one. Named types can be recursive. +

    +
    Syntax:
    -  { <type list> }
    +  %T1 = type { <type list> }     ; Named normal struct type
    +  %T2 = type <{ <type list> }>   ; Named packed struct type
     
    - +
    Examples:
    - + + + + + +
    { i32, i32, i32 } A triple of three i32 values
    { float, i32 (i32) * } A pair, where the first element is a float and the second element is a pointer to a function that takes an i32, returning an i32.
    <{ i8, i32 }>A packed struct known to be 5 bytes in size.
    - +

    - Packed Structure Type + Opaque Type

    Overview:
    -

    The packed structure type is used to represent a collection of data members - together in memory. There is no padding between fields. Further, the - alignment of a packed structure is 1 byte. The elements of a packed - structure may be any type that has a size.

    - -

    Structures are accessed using 'load and - 'store' by getting a pointer to a field with - the 'getelementptr' instruction.

    +

    Opaque types are used to represent named structure types that do not have a + body specified. This corresponds (for example) to the C notion of a forward + declared structure.

    Syntax:
    -  < { <type list> } >
    +  %X = type opaque
    +  %52 = type opaque
     
    Examples:
    - - - - - + +
    < { i32, i32, i32 } >A triple of three i32 values
    -< { float, i32 (i32)* } >A pair, where the first element is a float and the - second element is a pointer to a - function that takes an i32, returning - an i32.opaqueAn opaque type.
    + +

    Pointer Type @@ -1999,86 +2006,6 @@ - -

    - Opaque Type -

    - -
    - -
    Overview:
    -

    Opaque types are used to represent unknown types in the system. This - corresponds (for example) to the C notion of a forward declared structure - type. In LLVM, opaque types can eventually be resolved to any type (not just - a structure type).

    - -
    Syntax:
    -
    -  opaque
    -
    - -
    Examples:
    - - - - - -
    opaqueAn opaque type.
    - -
    - - - - -

    - Type Up-references -

    - -
    - -
    Overview:
    -

    An "up reference" allows you to refer to a lexically enclosing type without - requiring it to have a name. For instance, a structure declaration may - contain a pointer to any of the types it is lexically a member of. Example - of up references (with their equivalent as named type declarations) - include:

    - -
    -   { \2 * }                %x = type { %x* }
    -   { \2 }*                 %y = type { %y }*
    -   \1*                     %z = type %z*
    -
    - -

    An up reference is needed by the asmprinter for printing out cyclic types - when there is no declared name for a type in the cycle. Because the - asmprinter does not want to print out an infinite type string, it needs a - syntax to handle recursive types that have no names (all names are optional - in llvm IR).

    - -
    Syntax:
    -
    -   \<level>
    -
    - -

    The level is the count of the lexical type that is being referred to.

    - -
    Examples:
    - - - - - - - - - -
    \1*Self-referential pointer.
    { { \3*, i8 }, i32 }Recursive structure where the upref refers to the out-most - structure.
    - -
    - - -

    Constants

    Modified: llvm/trunk/docs/ProgrammersManual.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/docs/ProgrammersManual.html (original) +++ llvm/trunk/docs/ProgrammersManual.html Sat Jul 9 12:41:24 2011 @@ -160,15 +160,8 @@
  • Advanced Topics
  • @@ -2645,173 +2638,10 @@ LLVM system, and only need to be accessed in unusual circumstances.

    +

    - LLVM Type Resolution -

    - -
    - -

    -The LLVM type system has a very simple goal: allow clients to compare types for -structural equality with a simple pointer comparison (aka a shallow compare). -This goal makes clients much simpler and faster, and is used throughout the LLVM -system. -

    - -

    -Unfortunately achieving this goal is not a simple matter. In particular, -recursive types and late resolution of opaque types makes the situation very -difficult to handle. Fortunately, for the most part, our implementation makes -most clients able to be completely unaware of the nasty internal details. The -primary case where clients are exposed to the inner workings of it are when -building a recursive type. In addition to this case, the LLVM bitcode reader, -assembly parser, and linker also have to be aware of the inner workings of this -system. -

    - -

    -For our purposes below, we need three concepts. First, an "Opaque Type" is -exactly as defined in the language -reference. Second an "Abstract Type" is any type which includes an -opaque type as part of its type graph (for example "{ opaque, i32 }"). -Third, a concrete type is a type that is not an abstract type (e.g. "{ i32, -float }"). -

    - - -

    - Basic Recursive Type Construction -

    - -
    - -

    -Because the most common question is "how do I build a recursive type with LLVM", -we answer it now and explain it as we go. Here we include enough to cause this -to be emitted to an output .ll file: -

    - -
    -
    -%mylist = type { %mylist*, i32 }
    -
    -
    - -

    -To build this, use the following LLVM APIs: -

    - -
    -
    -// Create the initial outer struct
    -PATypeHolder StructTy = OpaqueType::get();
    -std::vector<const Type*> Elts;
    -Elts.push_back(PointerType::getUnqual(StructTy));
    -Elts.push_back(Type::Int32Ty);
    -StructType *NewSTy = StructType::get(Elts);
    -
    -// At this point, NewSTy = "{ opaque*, i32 }". Tell VMCore that
    -// the struct and the opaque type are actually the same.
    -cast<OpaqueType>(StructTy.get())->refineAbstractTypeTo(NewSTy);
    -
    -// NewSTy is potentially invalidated, but StructTy (a PATypeHolder) is
    -// kept up-to-date
    -NewSTy = cast<StructType>(StructTy.get());
    -
    -// Add a name for the type to the module symbol table (optional)
    -MyModule->addTypeName("mylist", NewSTy);
    -
    -
    - -

    -This code shows the basic approach used to build recursive types: build a -non-recursive type using 'opaque', then use type unification to close the cycle. -The type unification step is performed by the refineAbstractTypeTo method, which is -described next. After that, we describe the PATypeHolder class. -

    - -
    - - -

    - The refineAbstractTypeTo method -

    - -
    -

    -The refineAbstractTypeTo method starts the type unification process. -While this method is actually a member of the DerivedType class, it is most -often used on OpaqueType instances. Type unification is actually a recursive -process. After unification, types can become structurally isomorphic to -existing types, and all duplicates are deleted (to preserve pointer equality). -

    - -

    -In the example above, the OpaqueType object is definitely deleted. -Additionally, if there is an "{ \2*, i32}" type already created in the system, -the pointer and struct type created are also deleted. Obviously whenever -a type is deleted, any "Type*" pointers in the program are invalidated. As -such, it is safest to avoid having any "Type*" pointers to abstract types -live across a call to refineAbstractTypeTo (note that non-abstract -types can never move or be deleted). To deal with this, the PATypeHolder class is used to maintain a stable -reference to a possibly refined type, and the AbstractTypeUser class is used to update more -complex datastructures. -

    - -
    - - -

    - The PATypeHolder Class -

    - -
    -

    -PATypeHolder is a form of a "smart pointer" for Type objects. When VMCore -happily goes about nuking types that become isomorphic to existing types, it -automatically updates all PATypeHolder objects to point to the new type. In the -example above, this allows the code to maintain a pointer to the resultant -resolved recursive type, even though the Type*'s are potentially invalidated. -

    - -

    -PATypeHolder is an extremely light-weight object that uses a lazy union-find -implementation to update pointers. For example the pointer from a Value to its -Type is maintained by PATypeHolder objects. -

    - -
    - - -

    - The AbstractTypeUser Class -

    - -
    - -

    -Some data structures need more to perform more complex updates when types get -resolved. To support this, a class can derive from the AbstractTypeUser class. -This class -allows it to get callbacks when certain types are resolved. To register to get -callbacks for a particular type, the DerivedType::{add/remove}AbstractTypeUser -methods can be called on a type. Note that these methods only work for - abstract types. Concrete types (those that do not include any opaque -objects) can never be refined. -

    -
    - -
    - - -

    - The ValueSymbolTable and - TypeSymbolTable classes + The ValueSymbolTable class

    @@ -2820,9 +2650,7 @@ href="#Function">Function and Module classes use for naming value definitions. The symbol table can provide a name for any Value. -The -TypeSymbolTable class is used by the Module class to store -names for types.

    +

    Note that the SymbolTable class should not be directly accessed by most clients. It should only be used when iteration over the symbol table @@ -2832,13 +2660,12 @@ an empty name) do not exist in the symbol table.

    -

    These symbol tables support iteration over the values/types in the symbol +

    Symbol tables support iteration over the values in the symbol table with begin/end/iterator and supports querying to see if a specific name is in the symbol table (with lookup). The ValueSymbolTable class exposes no public mutator methods, instead, simply call setName on a value, which will autoinsert it into the -appropriate symbol table. For types, use the Module::addTypeName method to -insert entries into the symbol table.

    +appropriate symbol table.

    @@ -3128,9 +2955,6 @@
  • bool isFloatingPointTy(): Return true if this is one of the five floating point types.
  • -
  • bool isAbstract(): Return true if the type is abstract (contains - an OpaqueType anywhere in its definition).
  • -
  • bool isSized(): Return true if the type has known size. Things that don't have a size are abstract types, labels and void.
  • @@ -3192,14 +3016,6 @@ number of formal parameters. -
    OpaqueType
    -
    Sublcass of DerivedType for abstract types. This class - defines no content and is used as a placeholder for some other type. Note - that OpaqueType is used (temporarily) during type resolution for forward - references of types. Once the referenced type is resolved, the OpaqueType - is replaced with the actual type. OpaqueType can also be used for data - abstraction. At link time opaque types can be resolved to actual types - of the same name.
    Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Sat Jul 9 12:41:24 2011 @@ -68,13 +68,6 @@ */ typedef struct LLVMOpaqueType *LLVMTypeRef; -/** - * When building recursive types using LLVMRefineType, LLVMTypeRef values may - * become invalid; use LLVMTypeHandleRef to resolve this problem. See the - * llvm::AbstractTypeHolder class. - */ -typedef struct LLVMOpaqueTypeHandle *LLVMTypeHandleRef; - typedef struct LLVMOpaqueValue *LLVMValueRef; typedef struct LLVMOpaqueBasicBlock *LLVMBasicBlockRef; typedef struct LLVMOpaqueBuilder *LLVMBuilderRef; @@ -206,7 +199,6 @@ LLVMStructTypeKind, /**< Structures */ LLVMArrayTypeKind, /**< Arrays */ LLVMPointerTypeKind, /**< Pointers */ - LLVMOpaqueTypeKind, /**< Opaque: type with unknown structure */ LLVMVectorTypeKind, /**< SIMD 'packed' format, or other vector type */ LLVMMetadataTypeKind, /**< Metadata */ LLVMX86_MMXTypeKind /**< X86 MMX */ @@ -320,12 +312,6 @@ const char *LLVMGetTarget(LLVMModuleRef M); void LLVMSetTarget(LLVMModuleRef M, const char *Triple); -/** See Module::addTypeName. */ -LLVMBool LLVMAddTypeName(LLVMModuleRef M, const char *Name, LLVMTypeRef Ty); -void LLVMDeleteTypeName(LLVMModuleRef M, const char *Name); -LLVMTypeRef LLVMGetTypeByName(LLVMModuleRef M, const char *Name); -const char *LLVMGetTypeName(LLVMModuleRef M, LLVMTypeRef Ty); - /** See Module::dump. */ void LLVMDumpModule(LLVMModuleRef M); @@ -418,7 +404,6 @@ /* Operations on other types */ LLVMTypeRef LLVMVoidTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C); -LLVMTypeRef LLVMOpaqueTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMX86MMXTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMVoidType(void); @@ -426,13 +411,6 @@ LLVMTypeRef LLVMOpaqueType(void); LLVMTypeRef LLVMX86MMXType(void); -/* Operations on type handles */ -LLVMTypeHandleRef LLVMCreateTypeHandle(LLVMTypeRef PotentiallyAbstractTy); -void LLVMRefineType(LLVMTypeRef AbstractTy, LLVMTypeRef ConcreteTy); -LLVMTypeRef LLVMResolveTypeHandle(LLVMTypeHandleRef TypeHandle); -void LLVMDisposeTypeHandle(LLVMTypeHandleRef TypeHandle); - - /*===-- Values ------------------------------------------------------------===*/ /* The bulk of LLVM's object model consists of values, which comprise a very @@ -1117,7 +1095,6 @@ DEFINE_SIMPLE_CONVERSION_FUNCTIONS(Module, LLVMModuleRef ) DEFINE_SIMPLE_CONVERSION_FUNCTIONS(BasicBlock, LLVMBasicBlockRef ) DEFINE_SIMPLE_CONVERSION_FUNCTIONS(IRBuilder<>, LLVMBuilderRef ) - DEFINE_SIMPLE_CONVERSION_FUNCTIONS(PATypeHolder, LLVMTypeHandleRef ) DEFINE_SIMPLE_CONVERSION_FUNCTIONS(MemoryBuffer, LLVMMemoryBufferRef ) DEFINE_SIMPLE_CONVERSION_FUNCTIONS(LLVMContext, LLVMContextRef ) DEFINE_SIMPLE_CONVERSION_FUNCTIONS(Use, LLVMUseRef ) Modified: llvm/trunk/include/llvm-c/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Transforms/IPO.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm-c/Transforms/IPO.h Sat Jul 9 12:41:24 2011 @@ -30,9 +30,6 @@ /** See llvm::createDeadArgEliminationPass function. */ void LLVMAddDeadArgEliminationPass(LLVMPassManagerRef PM); -/** See llvm::createDeadTypeEliminationPass function. */ -void LLVMAddDeadTypeEliminationPass(LLVMPassManagerRef PM); - /** See llvm::createFunctionAttrsPass function. */ void LLVMAddFunctionAttrsPass(LLVMPassManagerRef PM); Removed: llvm/trunk/include/llvm/AbstractTypeUser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/AbstractTypeUser.h?rev=134828&view=auto ============================================================================== --- llvm/trunk/include/llvm/AbstractTypeUser.h (original) +++ llvm/trunk/include/llvm/AbstractTypeUser.h (removed) @@ -1,205 +0,0 @@ -//===-- llvm/AbstractTypeUser.h - AbstractTypeUser Interface ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file declares the AbstractTypeUser class. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ABSTRACT_TYPE_USER_H -#define LLVM_ABSTRACT_TYPE_USER_H - -#if !defined(LLVM_TYPE_H) && !defined(LLVM_VALUE_H) -#error Do not include this file directly. Include Type.h instead. -#error Some versions of GCC (e.g. 3.4 and 4.1) can not handle the inlined method -#error PATypeHolder::dropRef() correctly otherwise. -#endif - -// This is the "master" include for Whether this file needs it or not, -// it must always include for the files which include -// llvm/AbstractTypeUser.h -// -// In this way, most every LLVM source file will have access to the assert() -// macro without having to #include directly. -// -#include - -namespace llvm { - -class Value; -class Type; -class DerivedType; -template struct simplify_type; - -/// The AbstractTypeUser class is an interface to be implemented by classes who -/// could possibly use an abstract type. Abstract types are denoted by the -/// isAbstract flag set to true in the Type class. These are classes that -/// contain an Opaque type in their structure somewhere. -/// -/// Classes must implement this interface so that they may be notified when an -/// abstract type is resolved. Abstract types may be resolved into more -/// concrete types through: linking, parsing, and bitcode reading. When this -/// happens, all of the users of the type must be updated to reference the new, -/// more concrete type. They are notified through the AbstractTypeUser -/// interface. -/// -/// In addition to this, AbstractTypeUsers must keep the use list of the -/// potentially abstract type that they reference up-to-date. To do this in a -/// nice, transparent way, the PATypeHandle class is used to hold "Potentially -/// Abstract Types", and keep the use list of the abstract types up-to-date. -/// @brief LLVM Abstract Type User Representation -class AbstractTypeUser { -protected: - virtual ~AbstractTypeUser(); // Derive from me - - /// setType - It's normally not possible to change a Value's type in place, - /// but an AbstractTypeUser subclass that knows what its doing can be - /// permitted to do so with care. - void setType(Value *V, const Type *NewTy); - -public: - - /// refineAbstractType - The callback method invoked when an abstract type is - /// resolved to another type. An object must override this method to update - /// its internal state to reference NewType instead of OldType. - /// - virtual void refineAbstractType(const DerivedType *OldTy, - const Type *NewTy) = 0; - - /// The other case which AbstractTypeUsers must be aware of is when a type - /// makes the transition from being abstract (where it has clients on its - /// AbstractTypeUsers list) to concrete (where it does not). This method - /// notifies ATU's when this occurs for a type. - /// - virtual void typeBecameConcrete(const DerivedType *AbsTy) = 0; - - // for debugging... - virtual void dump() const = 0; -}; - - -/// PATypeHandle - Handle to a Type subclass. This class is used to keep the -/// use list of abstract types up-to-date. -/// -class PATypeHandle { - const Type *Ty; - AbstractTypeUser * const User; - - // These functions are defined at the bottom of Type.h. See the comment there - // for justification. - void addUser(); - void removeUser(); -public: - // ctor - Add use to type if abstract. Note that Ty must not be null - inline PATypeHandle(const Type *ty, AbstractTypeUser *user) - : Ty(ty), User(user) { - addUser(); - } - - // ctor - Add use to type if abstract. - inline PATypeHandle(const PATypeHandle &T) : Ty(T.Ty), User(T.User) { - addUser(); - } - - // dtor - Remove reference to type... - inline ~PATypeHandle() { removeUser(); } - - // Automatic casting operator so that the handle may be used naturally - inline operator Type *() const { return const_cast(Ty); } - inline Type *get() const { return const_cast(Ty); } - - // operator= - Allow assignment to handle - inline Type *operator=(const Type *ty) { - if (Ty != ty) { // Ensure we don't accidentally drop last ref to Ty - removeUser(); - Ty = ty; - addUser(); - } - return get(); - } - - // operator= - Allow assignment to handle - inline const Type *operator=(const PATypeHandle &T) { - return operator=(T.Ty); - } - - inline bool operator==(const Type *ty) { - return Ty == ty; - } - - // operator-> - Allow user to dereference handle naturally... - inline const Type *operator->() const { return Ty; } -}; - - -/// PATypeHolder - Holder class for a potentially abstract type. This uses -/// efficient union-find techniques to handle dynamic type resolution. Unless -/// you need to do custom processing when types are resolved, you should always -/// use PATypeHolders in preference to PATypeHandles. -/// -class PATypeHolder { - mutable const Type *Ty; - void destroy(); -public: - PATypeHolder() : Ty(0) {} - PATypeHolder(const Type *ty) : Ty(ty) { - addRef(); - } - PATypeHolder(const PATypeHolder &T) : Ty(T.Ty) { - addRef(); - } - - ~PATypeHolder() { dropRef(); } - - operator Type *() const { return get(); } - Type *get() const; - - // operator-> - Allow user to dereference handle naturally... - Type *operator->() const { return get(); } - - // operator= - Allow assignment to handle - Type *operator=(const Type *ty) { - if (Ty != ty) { // Don't accidentally drop last ref to Ty. - dropRef(); - Ty = ty; - addRef(); - } - return get(); - } - Type *operator=(const PATypeHolder &H) { - return operator=(H.Ty); - } - - /// getRawType - This should only be used to implement the vmcore library. - /// - const Type *getRawType() const { return Ty; } - -private: - void addRef(); - void dropRef(); - friend class TypeMapBase; -}; - -// simplify_type - Allow clients to treat uses just like values when using -// casting operators. -template<> struct simplify_type { - typedef const Type* SimpleType; - static SimpleType getSimplifiedValue(const PATypeHolder &Val) { - return static_cast(Val.get()); - } -}; -template<> struct simplify_type { - typedef const Type* SimpleType; - static SimpleType getSimplifiedValue(const PATypeHolder &Val) { - return static_cast(Val.get()); - } -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Sat Jul 9 12:41:24 2011 @@ -29,13 +29,23 @@ // Module sub-block id's. PARAMATTR_BLOCK_ID, - TYPE_BLOCK_ID, + + /// TYPE_BLOCK_ID_OLD - This is the type descriptor block in LLVM 2.9 and + /// earlier, replaced with TYPE_BLOCK_ID2. FIXME: Remove in LLVM 3.1. + TYPE_BLOCK_ID_OLD, + CONSTANTS_BLOCK_ID, FUNCTION_BLOCK_ID, - TYPE_SYMTAB_BLOCK_ID, + + /// TYPE_SYMTAB_BLOCK_ID_OLD - This type descriptor is from LLVM 2.9 and + /// earlier bitcode files. FIXME: Remove in LLVM 3.1 + TYPE_SYMTAB_BLOCK_ID_OLD, + VALUE_SYMTAB_BLOCK_ID, METADATA_BLOCK_ID, - METADATA_ATTACHMENT_ID + METADATA_ATTACHMENT_ID, + + TYPE_BLOCK_ID_NEW }; @@ -72,31 +82,38 @@ /// TYPE blocks have codes for each type primitive they use. enum TypeCodes { - TYPE_CODE_NUMENTRY = 1, // NUMENTRY: [numentries] + TYPE_CODE_NUMENTRY = 1, // NUMENTRY: [numentries] // Type Codes - TYPE_CODE_VOID = 2, // VOID - TYPE_CODE_FLOAT = 3, // FLOAT - TYPE_CODE_DOUBLE = 4, // DOUBLE - TYPE_CODE_LABEL = 5, // LABEL - TYPE_CODE_OPAQUE = 6, // OPAQUE - TYPE_CODE_INTEGER = 7, // INTEGER: [width] - TYPE_CODE_POINTER = 8, // POINTER: [pointee type] - TYPE_CODE_FUNCTION = 9, // FUNCTION: [vararg, retty, paramty x N] - TYPE_CODE_STRUCT = 10, // STRUCT: [ispacked, eltty x N] - TYPE_CODE_ARRAY = 11, // ARRAY: [numelts, eltty] - TYPE_CODE_VECTOR = 12, // VECTOR: [numelts, eltty] + TYPE_CODE_VOID = 2, // VOID + TYPE_CODE_FLOAT = 3, // FLOAT + TYPE_CODE_DOUBLE = 4, // DOUBLE + TYPE_CODE_LABEL = 5, // LABEL + TYPE_CODE_OPAQUE = 6, // OPAQUE + TYPE_CODE_INTEGER = 7, // INTEGER: [width] + TYPE_CODE_POINTER = 8, // POINTER: [pointee type] + TYPE_CODE_FUNCTION = 9, // FUNCTION: [vararg, retty, paramty x N] + + // FIXME: This is the encoding used for structs in LLVM 2.9 and earlier. + // REMOVE this in LLVM 3.1 + TYPE_CODE_STRUCT_OLD = 10, // STRUCT: [ispacked, eltty x N] + TYPE_CODE_ARRAY = 11, // ARRAY: [numelts, eltty] + TYPE_CODE_VECTOR = 12, // VECTOR: [numelts, eltty] // These are not with the other floating point types because they're // a late addition, and putting them in the right place breaks // binary compatibility. - TYPE_CODE_X86_FP80 = 13, // X86 LONG DOUBLE - TYPE_CODE_FP128 = 14, // LONG DOUBLE (112 bit mantissa) - TYPE_CODE_PPC_FP128= 15, // PPC LONG DOUBLE (2 doubles) - - TYPE_CODE_METADATA = 16, // METADATA - - TYPE_CODE_X86_MMX = 17 // X86 MMX + TYPE_CODE_X86_FP80 = 13, // X86 LONG DOUBLE + TYPE_CODE_FP128 = 14, // LONG DOUBLE (112 bit mantissa) + TYPE_CODE_PPC_FP128= 15, // PPC LONG DOUBLE (2 doubles) + + TYPE_CODE_METADATA = 16, // METADATA + + TYPE_CODE_X86_MMX = 17, // X86 MMX + + TYPE_CODE_STRUCT_ANON = 18, // STRUCT_ANON: [ispacked, eltty x N] + TYPE_CODE_STRUCT_NAME = 19, // STRUCT_NAME: [strchr x N] + TYPE_CODE_STRUCT_NAMED = 20 // STRUCT_NAMED: [ispacked, eltty x N] }; // The type symbol table only has one code (TST_ENTRY_CODE). Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Sat Jul 9 12:41:24 2011 @@ -912,10 +912,18 @@ Constant *getWithOperandReplaced(unsigned OpNo, Constant *Op) const; /// getWithOperands - This returns the current constant expression with the - /// operands replaced with the specified values. The specified operands must - /// match count and type with the existing ones. - Constant *getWithOperands(ArrayRef Ops) const; - + /// operands replaced with the specified values. The specified array must + /// have the same number of operands as our current one. + Constant *getWithOperands(ArrayRef Ops) const { + return getWithOperands(Ops, getType()); + } + + /// getWithOperands - This returns the current constant expression with the + /// operands replaced with the specified values and with the specified result + /// type. The specified array must have the same number of operands as our + /// current one. + Constant *getWithOperands(ArrayRef Ops, const Type *Ty) const; + virtual void destroyConstant(); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); Modified: llvm/trunk/include/llvm/DefaultPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DefaultPasses.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/DefaultPasses.h (original) +++ llvm/trunk/include/llvm/DefaultPasses.h Sat Jul 9 12:41:24 2011 @@ -29,7 +29,6 @@ extern unsigned char CorrelatedValuePropagationID; extern unsigned char DeadArgEliminationID; extern unsigned char DeadStoreEliminationID; -extern unsigned char DeadTypeEliminationID; extern unsigned char EarlyCSEID; extern unsigned char FunctionAttrsID; extern unsigned char FunctionInliningID; Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Sat Jul 9 12:41:24 2011 @@ -24,51 +24,16 @@ namespace llvm { class Value; -template class TypeMap; -class FunctionValType; -class ArrayValType; -class StructValType; -class PointerValType; -class VectorValType; -class IntegerValType; class APInt; class LLVMContext; template class ArrayRef; +class StringRef; class DerivedType : public Type { - friend class Type; - protected: explicit DerivedType(LLVMContext &C, TypeID id) : Type(C, id) {} - - /// notifyUsesThatTypeBecameConcrete - Notify AbstractTypeUsers of this type - /// that the current type has transitioned from being abstract to being - /// concrete. - /// - void notifyUsesThatTypeBecameConcrete(); - - /// dropAllTypeUses - When this (abstract) type is resolved to be equal to - /// another (more concrete) type, we must eliminate all references to other - /// types, to avoid some circular reference problems. - /// - void dropAllTypeUses(); - public: - //===--------------------------------------------------------------------===// - // Abstract Type handling methods - These types have special lifetimes, which - // are managed by (add|remove)AbstractTypeUser. See comments in - // AbstractTypeUser.h for more information. - - /// refineAbstractTypeTo - This function is used to when it is discovered that - /// the 'this' abstract type is actually equivalent to the NewType specified. - /// This causes all users of 'this' to switch to reference the more concrete - /// type NewType and for 'this' to be deleted. - /// - void refineAbstractTypeTo(const Type *NewType); - - void dump() const { Type::dump(); } - // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const DerivedType *) { return true; } static inline bool classof(const Type *T) { @@ -88,7 +53,6 @@ DerivedType(C, IntegerTyID) { setSubclassData(NumBits); } - friend class TypeMap; public: /// This enum is just used to hold constants we need for IntegerType. enum { @@ -103,7 +67,7 @@ /// that instance will be returned. Otherwise a new one will be created. Only /// one instance with a given NumBits value is ever created. /// @brief Get or create an IntegerType instance. - static const IntegerType *get(LLVMContext &C, unsigned NumBits); + static IntegerType *get(LLVMContext &C, unsigned NumBits); /// @brief Get the number of bits in this IntegerType unsigned getBitWidth() const { return getSubclassData(); } @@ -143,11 +107,9 @@ /// FunctionType - Class to represent function types /// class FunctionType : public DerivedType { - friend class TypeMap; FunctionType(const FunctionType &); // Do not implement const FunctionType &operator=(const FunctionType &); // Do not implement - FunctionType(const Type *Result, ArrayRef Params, - bool IsVarArgs); + FunctionType(const Type *Result, ArrayRef Params, bool IsVarArgs); public: /// FunctionType::get - This static method is the primary way of constructing @@ -155,6 +117,8 @@ /// static FunctionType *get(const Type *Result, ArrayRef Params, bool isVarArg); + static FunctionType *get(const Type *Result, + ArrayRef Params, bool isVarArg); /// FunctionType::get - Create a FunctionType taking no parameters. /// @@ -169,24 +133,20 @@ static bool isValidArgumentType(const Type *ArgTy); bool isVarArg() const { return getSubclassData(); } - const Type *getReturnType() const { return ContainedTys[0]; } + Type *getReturnType() const { return ContainedTys[0]; } typedef Type::subtype_iterator param_iterator; param_iterator param_begin() const { return ContainedTys + 1; } param_iterator param_end() const { return &ContainedTys[NumContainedTys]; } // Parameter type accessors. - const Type *getParamType(unsigned i) const { return ContainedTys[i+1]; } + Type *getParamType(unsigned i) const { return ContainedTys[i+1]; } /// getNumParams - Return the number of fixed parameters this function type /// requires. This does not consider varargs. /// unsigned getNumParams() const { return NumContainedTys - 1; } - // Implement the AbstractTypeUser interface. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const FunctionType *) { return true; } static inline bool classof(const Type *T) { @@ -205,8 +165,8 @@ /// getTypeAtIndex - Given an index value into the type, return the type of /// the element. /// - const Type *getTypeAtIndex(const Value *V) const; - const Type *getTypeAtIndex(unsigned Idx) const; + Type *getTypeAtIndex(const Value *V) const; + Type *getTypeAtIndex(unsigned Idx) const; bool indexValid(const Value *V) const; bool indexValid(unsigned Idx) const; @@ -222,18 +182,49 @@ /// StructType - Class to represent struct types, both normal and packed. +/// Besides being optionally packed, structs can be either "anonymous" or may +/// have an identity. Anonymous structs are uniqued by structural equivalence, +/// but types are each unique when created, and optionally have a name. /// class StructType : public CompositeType { - friend class TypeMap; StructType(const StructType &); // Do not implement const StructType &operator=(const StructType &); // Do not implement - StructType(LLVMContext &C, ArrayRef Types, bool isPacked); + StructType(LLVMContext &C) + : CompositeType(C, StructTyID), SymbolTableEntry(0) {} + enum { + // This is the contents of the SubClassData field. + SCDB_HasBody = 1, + SCDB_Packed = 2, + SCDB_IsAnonymous = 4 + }; + + /// SymbolTableEntry - For a named struct that actually has a name, this is a + /// pointer to the symbol table entry (maintained by LLVMContext) for the + /// struct. This is null if the type is an anonymous struct or if it is + /// + void *SymbolTableEntry; public: + /// StructType::createNamed - This creates a named struct with no body + /// specified. If the name is empty, it creates an unnamed struct, which has + /// a unique identity but no actual name. + static StructType *createNamed(LLVMContext &Context, StringRef Name); + + static StructType *createNamed(StringRef Name, ArrayRef Elements, + bool isPacked = false); + static StructType *createNamed(LLVMContext &Context, StringRef Name, + ArrayRef Elements, + bool isPacked = false); + static StructType *createNamed(StringRef Name, Type *elt1, ...) END_WITH_NULL; + /// StructType::get - This static method is the primary way to create a /// StructType. /// + /// FIXME: Remove the 'const Type*' version of this when types are pervasively + /// de-constified. static StructType *get(LLVMContext &Context, ArrayRef Elements, bool isPacked = false); + static StructType *get(LLVMContext &Context, ArrayRef Elements, + bool isPacked = false); /// StructType::get - Create an empty structure type. /// @@ -245,11 +236,37 @@ /// element type. static StructType *get(const Type *elt1, ...) END_WITH_NULL; + bool isPacked() const { return (getSubclassData() & SCDB_Packed) != 0; } + + /// isAnonymous - Return true if this type is uniqued by structural + /// equivalence, false if it has an identity. + bool isAnonymous() const {return (getSubclassData() & SCDB_IsAnonymous) != 0;} + + /// isOpaque - Return true if this is a type with an identity that has no body + /// specified yet. These prints as 'opaque' in .ll files. + bool isOpaque() const { return (getSubclassData() & SCDB_HasBody) == 0; } + + /// hasName - Return true if this is a named struct that has a non-empty name. + bool hasName() const { return SymbolTableEntry != 0; } + + /// getName - Return the name for this struct type if it has an identity. + /// This may return an empty string for an unnamed struct type. Do not call + /// this on an anonymous type. + StringRef getName() const; + + /// setName - Change the name of this type to the specified name, or to a name + /// with a suffix if there is a collision. Do not call this on an anonymous + /// type. + void setName(StringRef Name); + + /// setBody - Specify a body for an opaque type. + void setBody(ArrayRef Elements, bool isPacked = false); + void setBody(Type *elt1, ...) END_WITH_NULL; + /// isValidElementType - Return true if the specified type is valid as a /// element type. static bool isValidElementType(const Type *ElemTy); - - bool isPacked() const { return getSubclassData() != 0 ? true : false; } + // Iterator access to the elements. typedef Type::subtype_iterator element_iterator; @@ -258,22 +275,15 @@ /// isLayoutIdentical - Return true if this is layout identical to the /// specified struct. - bool isLayoutIdentical(const StructType *Other) const { - return this == Other; - } - + bool isLayoutIdentical(const StructType *Other) const; // Random access to the elements unsigned getNumElements() const { return NumContainedTys; } - const Type *getElementType(unsigned N) const { + Type *getElementType(unsigned N) const { assert(N < NumContainedTys && "Element number out of range!"); return ContainedTys[N]; } - // Implement the AbstractTypeUser interface. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const StructType *) { return true; } static inline bool classof(const Type *T) { @@ -290,21 +300,19 @@ /// components out in memory identically. /// class SequentialType : public CompositeType { - PATypeHandle ContainedType; ///< Storage for the single contained type. + Type *ContainedType; ///< Storage for the single contained type. SequentialType(const SequentialType &); // Do not implement! const SequentialType &operator=(const SequentialType &); // Do not implement! - // avoiding warning: 'this' : used in base member initializer list - SequentialType *this_() { return this; } protected: - SequentialType(TypeID TID, const Type *ElType) - : CompositeType(ElType->getContext(), TID), ContainedType(ElType, this_()) { + SequentialType(TypeID TID, Type *ElType) + : CompositeType(ElType->getContext(), TID), ContainedType(ElType) { ContainedTys = &ContainedType; NumContainedTys = 1; } public: - const Type *getElementType() const { return ContainedTys[0]; } + Type *getElementType() const { return ContainedTys[0]; } // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const SequentialType *) { return true; } @@ -319,12 +327,11 @@ /// ArrayType - Class to represent array types. /// class ArrayType : public SequentialType { - friend class TypeMap; uint64_t NumElements; ArrayType(const ArrayType &); // Do not implement const ArrayType &operator=(const ArrayType &); // Do not implement - ArrayType(const Type *ElType, uint64_t NumEl); + ArrayType(Type *ElType, uint64_t NumEl); public: /// ArrayType::get - This static method is the primary way to construct an /// ArrayType @@ -337,10 +344,6 @@ uint64_t getNumElements() const { return NumElements; } - // Implement the AbstractTypeUser interface. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const ArrayType *) { return true; } static inline bool classof(const Type *T) { @@ -351,12 +354,11 @@ /// VectorType - Class to represent vector types. /// class VectorType : public SequentialType { - friend class TypeMap; unsigned NumElements; VectorType(const VectorType &); // Do not implement const VectorType &operator=(const VectorType &); // Do not implement - VectorType(const Type *ElType, unsigned NumEl); + VectorType(Type *ElType, unsigned NumEl); public: /// VectorType::get - This static method is the primary way to construct an /// VectorType. @@ -369,7 +371,7 @@ /// static VectorType *getInteger(const VectorType *VTy) { unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); - const Type *EltTy = IntegerType::get(VTy->getContext(), EltBits); + Type *EltTy = IntegerType::get(VTy->getContext(), EltBits); return VectorType::get(EltTy, VTy->getNumElements()); } @@ -379,7 +381,7 @@ /// static VectorType *getExtendedElementVectorType(const VectorType *VTy) { unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); - const Type *EltTy = IntegerType::get(VTy->getContext(), EltBits * 2); + Type *EltTy = IntegerType::get(VTy->getContext(), EltBits * 2); return VectorType::get(EltTy, VTy->getNumElements()); } @@ -391,7 +393,7 @@ unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits(); assert((EltBits & 1) == 0 && "Cannot truncate vector element with odd bit-width"); - const Type *EltTy = IntegerType::get(VTy->getContext(), EltBits / 2); + Type *EltTy = IntegerType::get(VTy->getContext(), EltBits / 2); return VectorType::get(EltTy, VTy->getNumElements()); } @@ -407,10 +409,6 @@ return NumElements * getElementType()->getPrimitiveSizeInBits(); } - // Implement the AbstractTypeUser interface. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - // Methods for support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const VectorType *) { return true; } static inline bool classof(const Type *T) { @@ -422,11 +420,9 @@ /// PointerType - Class to represent pointers. /// class PointerType : public SequentialType { - friend class TypeMap; - PointerType(const PointerType &); // Do not implement const PointerType &operator=(const PointerType &); // Do not implement - explicit PointerType(const Type *ElType, unsigned AddrSpace); + explicit PointerType(Type *ElType, unsigned AddrSpace); public: /// PointerType::get - This constructs a pointer to an object of the specified /// type in a numbered address space. @@ -445,10 +441,6 @@ /// @brief Return the address space of the Pointer type. inline unsigned getAddressSpace() const { return getSubclassData(); } - // Implement the AbstractTypeUser interface. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - // Implement support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const PointerType *) { return true; } static inline bool classof(const Type *T) { @@ -456,26 +448,6 @@ } }; - -/// OpaqueType - Class to represent opaque types. -/// -class OpaqueType : public DerivedType { - friend class LLVMContextImpl; - OpaqueType(const OpaqueType &); // DO NOT IMPLEMENT - const OpaqueType &operator=(const OpaqueType &); // DO NOT IMPLEMENT - OpaqueType(LLVMContext &C); -public: - /// OpaqueType::get - Static factory method for the OpaqueType class. - /// - static OpaqueType *get(LLVMContext &C); - - // Implement support for type inquiry through isa, cast, and dyn_cast. - static inline bool classof(const OpaqueType *) { return true; } - static inline bool classof(const Type *T) { - return T->getTypeID() == OpaqueTyID; - } -}; - } // End llvm namespace #endif Modified: llvm/trunk/include/llvm/Function.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Function.h (original) +++ llvm/trunk/include/llvm/Function.h Sat Jul 9 12:41:24 2011 @@ -128,8 +128,8 @@ ~Function(); - const Type *getReturnType() const; // Return the type of the ret val - const FunctionType *getFunctionType() const; // Return the FunctionType for me + Type *getReturnType() const; // Return the type of the ret val + FunctionType *getFunctionType() const; // Return the FunctionType for me /// getContext - Return a pointer to the LLVMContext associated with this /// function, or NULL if this function is not bound to a context yet. Modified: llvm/trunk/include/llvm/GlobalAlias.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalAlias.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalAlias.h (original) +++ llvm/trunk/include/llvm/GlobalAlias.h Sat Jul 9 12:41:24 2011 @@ -63,23 +63,23 @@ virtual void eraseFromParent(); /// set/getAliasee - These methods retrive and set alias target. - void setAliasee(Constant* GV); - const Constant* getAliasee() const { + void setAliasee(Constant *GV); + const Constant *getAliasee() const { return cast_or_null(getOperand(0)); } - Constant* getAliasee() { + Constant *getAliasee() { return cast_or_null(getOperand(0)); } /// getAliasedGlobal() - Aliasee can be either global or bitcast of /// global. This method retrives the global for both aliasee flavours. - const GlobalValue* getAliasedGlobal() const; + const GlobalValue *getAliasedGlobal() const; /// resolveAliasedGlobal() - This method tries to ultimately resolve the alias /// by going through the aliasing chain and trying to find the very last /// global. Returns NULL if a cycle was found. If stopOnWeak is false, then /// the whole chain aliasing chain is traversed, otherwise - only strong /// aliases. - const GlobalValue* resolveAliasedGlobal(bool stopOnWeak = true) const; + const GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true) const; // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const GlobalAlias *) { return true; } Modified: llvm/trunk/include/llvm/GlobalValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalValue.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalValue.h (original) +++ llvm/trunk/include/llvm/GlobalValue.h Sat Jul 9 12:41:24 2011 @@ -106,8 +106,8 @@ bool use_empty_except_constants(); /// getType - Global values are always pointers. - inline const PointerType *getType() const { - return reinterpret_cast(User::getType()); + inline PointerType *getType() const { + return reinterpret_cast(User::getType()); } static LinkageTypes getLinkOnceLinkage(bool ODR) { Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Sat Jul 9 12:41:24 2011 @@ -84,7 +84,6 @@ void initializeDAHPass(PassRegistry&); void initializeDCEPass(PassRegistry&); void initializeDSEPass(PassRegistry&); -void initializeDTEPass(PassRegistry&); void initializeDeadInstEliminationPass(PassRegistry&); void initializeDeadMachineInstructionElimPass(PassRegistry&); void initializeDomOnlyPrinterPass(PassRegistry&); Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Sat Jul 9 12:41:24 2011 @@ -76,7 +76,7 @@ /// getAllocatedType - Return the type that is being allocated by the /// instruction. /// - const Type *getAllocatedType() const; + Type *getAllocatedType() const; /// getAlignment - Return the alignment of the memory that is being allocated /// by the instruction. @@ -271,10 +271,10 @@ // GetElementPtrInst Class //===----------------------------------------------------------------------===// -// checkType - Simple wrapper function to give a better assertion failure +// checkGEPType - Simple wrapper function to give a better assertion failure // message on bad indexes for a gep instruction. // -static inline const Type *checkType(const Type *Ty) { +static inline const Type *checkGEPType(const Type *Ty) { assert(Ty && "Invalid GetElementPtrInst indices for type!"); return Ty; } @@ -315,13 +315,13 @@ /// pointer type. /// template - static const Type *getIndexedType(const Type *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - // This argument ensures that we - // have an iterator we can do - // arithmetic on in constant time - std::random_access_iterator_tag) { + static Type *getIndexedType(const Type *Ptr, + RandomAccessIterator IdxBegin, + RandomAccessIterator IdxEnd, + // This argument ensures that we + // have an iterator we can do + // arithmetic on in constant time + std::random_access_iterator_tag) { unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); if (NumIdx > 0) @@ -446,24 +446,22 @@ /// pointer type. /// template - static const Type *getIndexedType(const Type *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd) { + static Type *getIndexedType(const Type *Ptr, RandomAccessIterator IdxBegin, + RandomAccessIterator IdxEnd) { return getIndexedType(Ptr, IdxBegin, IdxEnd, typename std::iterator_traits:: iterator_category()); } - static const Type *getIndexedType(const Type *Ptr, - Value* const *Idx, unsigned NumIdx); - - static const Type *getIndexedType(const Type *Ptr, - Constant* const *Idx, unsigned NumIdx); - - static const Type *getIndexedType(const Type *Ptr, - uint64_t const *Idx, unsigned NumIdx); - - static const Type *getIndexedType(const Type *Ptr, Value *Idx); + // FIXME: Use ArrayRef + static Type *getIndexedType(const Type *Ptr, + Value* const *Idx, unsigned NumIdx); + static Type *getIndexedType(const Type *Ptr, + Constant* const *Idx, unsigned NumIdx); + + static Type *getIndexedType(const Type *Ptr, + uint64_t const *Idx, unsigned NumIdx); + static Type *getIndexedType(const Type *Ptr, Value *Idx); inline op_iterator idx_begin() { return op_begin()+1; } inline const_op_iterator idx_begin() const { return op_begin()+1; } @@ -538,7 +536,7 @@ unsigned Values, const Twine &NameStr, Instruction *InsertBefore) - : Instruction(PointerType::get(checkType( + : Instruction(PointerType::get(checkGEPType( getIndexedType(Ptr->getType(), IdxBegin, IdxEnd)), cast(Ptr->getType()) @@ -557,7 +555,7 @@ unsigned Values, const Twine &NameStr, BasicBlock *InsertAtEnd) - : Instruction(PointerType::get(checkType( + : Instruction(PointerType::get(checkGEPType( getIndexedType(Ptr->getType(), IdxBegin, IdxEnd)), cast(Ptr->getType()) @@ -1459,17 +1457,18 @@ /// /// Null is returned if the indices are invalid for the specified type. /// - static const Type *getIndexedType(const Type *Agg, - const unsigned *Idx, unsigned NumIdx); + /// FIXME: Use ArrayRef + static Type *getIndexedType(const Type *Agg, + const unsigned *Idx, unsigned NumIdx); template - static const Type *getIndexedType(const Type *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - // This argument ensures that we - // have an iterator we can do - // arithmetic on in constant time - std::random_access_iterator_tag) { + static Type *getIndexedType(const Type *Ptr, + RandomAccessIterator IdxBegin, + RandomAccessIterator IdxEnd, + // This argument ensures that we + // have an iterator we can do + // arithmetic on in constant time + std::random_access_iterator_tag) { unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); if (NumIdx > 0) @@ -1542,15 +1541,16 @@ /// /// Null is returned if the indices are invalid for the specified type. /// + /// FIXME: Remove the templates and just use ArrayRef. template - static const Type *getIndexedType(const Type *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd) { + static Type *getIndexedType(const Type *Ptr, + RandomAccessIterator IdxBegin, + RandomAccessIterator IdxEnd) { return getIndexedType(Ptr, IdxBegin, IdxEnd, typename std::iterator_traits:: iterator_category()); } - static const Type *getIndexedType(const Type *Ptr, unsigned Idx); + static Type *getIndexedType(const Type *Ptr, unsigned Idx); typedef const unsigned* idx_iterator; inline idx_iterator idx_begin() const { return Indices.begin(); } @@ -1590,8 +1590,8 @@ RandomAccessIterator IdxEnd, const Twine &NameStr, Instruction *InsertBefore) - : UnaryInstruction(checkType(getIndexedType(Agg->getType(), - IdxBegin, IdxEnd)), + : UnaryInstruction(checkGEPType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), ExtractValue, Agg, InsertBefore) { init(IdxBegin, IdxEnd, NameStr, typename std::iterator_traits @@ -1603,8 +1603,8 @@ RandomAccessIterator IdxEnd, const Twine &NameStr, BasicBlock *InsertAtEnd) - : UnaryInstruction(checkType(getIndexedType(Agg->getType(), - IdxBegin, IdxEnd)), + : UnaryInstruction(checkGEPType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), ExtractValue, Agg, InsertAtEnd) { init(IdxBegin, IdxEnd, NameStr, typename std::iterator_traits Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Sat Jul 9 12:41:24 2011 @@ -62,7 +62,6 @@ (void) llvm::createDeadCodeEliminationPass(); (void) llvm::createDeadInstEliminationPass(); (void) llvm::createDeadStoreEliminationPass(); - (void) llvm::createDeadTypeEliminationPass(); (void) llvm::createDomOnlyPrinterPass(); (void) llvm::createDomPrinterPass(); (void) llvm::createDomOnlyViewerPass(); Modified: llvm/trunk/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Module.h (original) +++ llvm/trunk/include/llvm/Module.h Sat Jul 9 12:41:24 2011 @@ -28,6 +28,10 @@ class FunctionType; class GVMaterializer; class LLVMContext; +class StructType; +template struct DenseMapInfo; +template class DenseMap; template<> struct ilist_traits : public SymbolTableListTraits { @@ -145,7 +149,6 @@ NamedMDListType NamedMDList; ///< The named metadata in the module std::string GlobalScopeAsm; ///< Inline Asm at global scope. ValueSymbolTable *ValSymTab; ///< Symbol table for values - TypeSymbolTable *TypeSymTab; ///< Symbol table for types OwningPtr Materializer; ///< Used to materialize GlobalValues std::string ModuleID; ///< Human readable identifier for the module std::string TargetTriple; ///< Platform target triple Module compiled on @@ -231,7 +234,7 @@ /// @name Generic Value Accessors /// @{ - /// getNamedValue - Return the first global value in the module with + /// getNamedValue - Return the global value in the module with /// the specified name, of arbitrary type. This method returns null /// if a global with the specified name is not found. GlobalValue *getNamedValue(StringRef Name) const; @@ -244,6 +247,18 @@ /// custom metadata IDs registered in this LLVMContext. void getMDKindNames(SmallVectorImpl &Result) const; + + typedef DenseMap, + DenseMapInfo > NumeredTypesMapTy; + + /// findUsedStructTypes - Walk the entire module and find all of the + /// struct types that are in use, returning them in a vector. + void findUsedStructTypes(std::vector &StructTypes) const; + + /// getTypeByName - Return the type with the specified name, or null if there + /// is none by that name. + StructType *getTypeByName(StringRef Name) const; + /// @} /// @name Function Accessors /// @{ @@ -296,7 +311,7 @@ GlobalVariable *getGlobalVariable(StringRef Name, bool AllowInternal = false) const; - /// getNamedGlobal - Return the first global variable in the module with the + /// getNamedGlobal - Return the global variable in the module with the /// specified name, of arbitrary type. This method returns null if a global /// with the specified name is not found. GlobalVariable *getNamedGlobal(StringRef Name) const { @@ -316,7 +331,7 @@ /// @name Global Alias Accessors /// @{ - /// getNamedAlias - Return the first global alias in the module with the + /// getNamedAlias - Return the global alias in the module with the /// specified name, of arbitrary type. This method returns null if a global /// with the specified name is not found. GlobalAlias *getNamedAlias(StringRef Name) const; @@ -325,12 +340,12 @@ /// @name Named Metadata Accessors /// @{ - /// getNamedMetadata - Return the first NamedMDNode in the module with the + /// getNamedMetadata - Return the NamedMDNode in the module with the /// specified name. This method returns null if a NamedMDNode with the /// specified name is not found. NamedMDNode *getNamedMetadata(const Twine &Name) const; - /// getOrInsertNamedMetadata - Return the first named MDNode in the module + /// getOrInsertNamedMetadata - Return the named MDNode in the module /// with the specified name. This method returns a new NamedMDNode if a /// NamedMDNode with the specified name is not found. NamedMDNode *getOrInsertNamedMetadata(StringRef Name); @@ -340,23 +355,6 @@ void eraseNamedMetadata(NamedMDNode *NMD); /// @} -/// @name Type Accessors -/// @{ - - /// addTypeName - Insert an entry in the symbol table mapping Str to Type. If - /// there is already an entry for this name, true is returned and the symbol - /// table is not modified. - bool addTypeName(StringRef Name, const Type *Ty); - - /// getTypeName - If there is at least one entry in the symbol table for the - /// specified type, return it. - std::string getTypeName(const Type *Ty) const; - - /// getTypeByName - Return the type with the specified name in this module, or - /// null if there is none by that name. - const Type *getTypeByName(StringRef Name) const; - -/// @} /// @name Materialization /// @{ @@ -429,41 +427,26 @@ const ValueSymbolTable &getValueSymbolTable() const { return *ValSymTab; } /// Get the Module's symbol table of global variable and function identifiers. ValueSymbolTable &getValueSymbolTable() { return *ValSymTab; } - /// Get the symbol table of types - const TypeSymbolTable &getTypeSymbolTable() const { return *TypeSymTab; } - /// Get the Module's symbol table of types - TypeSymbolTable &getTypeSymbolTable() { return *TypeSymTab; } /// @} /// @name Global Variable Iteration /// @{ - /// Get an iterator to the first global variable global_iterator global_begin() { return GlobalList.begin(); } - /// Get a constant iterator to the first global variable const_global_iterator global_begin() const { return GlobalList.begin(); } - /// Get an iterator to the last global variable global_iterator global_end () { return GlobalList.end(); } - /// Get a constant iterator to the last global variable const_global_iterator global_end () const { return GlobalList.end(); } - /// Determine if the list of globals is empty. bool global_empty() const { return GlobalList.empty(); } /// @} /// @name Function Iteration /// @{ - /// Get an iterator to the first function. iterator begin() { return FunctionList.begin(); } - /// Get a constant iterator to the first function. const_iterator begin() const { return FunctionList.begin(); } - /// Get an iterator to the last function. iterator end () { return FunctionList.end(); } - /// Get a constant iterator to the last function. const_iterator end () const { return FunctionList.end(); } - /// Determine how many functions are in the Module's list of functions. size_t size() const { return FunctionList.size(); } - /// Determine if the list of functions is empty. bool empty() const { return FunctionList.empty(); } /// @} @@ -487,17 +470,11 @@ /// @name Alias Iteration /// @{ - /// Get an iterator to the first alias. alias_iterator alias_begin() { return AliasList.begin(); } - /// Get a constant iterator to the first alias. const_alias_iterator alias_begin() const { return AliasList.begin(); } - /// Get an iterator to the last alias. alias_iterator alias_end () { return AliasList.end(); } - /// Get a constant iterator to the last alias. const_alias_iterator alias_end () const { return AliasList.end(); } - /// Determine how many aliases are in the Module's list of aliases. size_t alias_size () const { return AliasList.size(); } - /// Determine if the list of aliases is empty. bool alias_empty() const { return AliasList.empty(); } @@ -505,24 +482,17 @@ /// @name Named Metadata Iteration /// @{ - /// Get an iterator to the first named metadata. named_metadata_iterator named_metadata_begin() { return NamedMDList.begin(); } - /// Get a constant iterator to the first named metadata. const_named_metadata_iterator named_metadata_begin() const { return NamedMDList.begin(); } - /// Get an iterator to the last named metadata. named_metadata_iterator named_metadata_end() { return NamedMDList.end(); } - /// Get a constant iterator to the last named metadata. const_named_metadata_iterator named_metadata_end() const { return NamedMDList.end(); } - /// Determine how many NamedMDNodes are in the Module's list of named - /// metadata. size_t named_metadata_size() const { return NamedMDList.size(); } - /// Determine if the list of named metadata is empty. bool named_metadata_empty() const { return NamedMDList.empty(); } @@ -530,11 +500,13 @@ /// @name Utility functions for printing and dumping Module objects /// @{ - /// Print the module to an output stream with AssemblyAnnotationWriter. + /// Print the module to an output stream with an optional + /// AssemblyAnnotationWriter. void print(raw_ostream &OS, AssemblyAnnotationWriter *AAW) const; /// Dump the module to stderr (for debugging). void dump() const; + /// This function causes all the subinstructions to "let go" of all references /// that they are maintaining. This allows one to 'delete' a whole class at /// a time, even though there may be circular references... first all Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Sat Jul 9 12:41:24 2011 @@ -237,8 +237,8 @@ MPM.add(createInstructionCombiningPass()); // Clean up after everything. if (!DisableUnitAtATime) { + // FIXME: We shouldn't bother with this anymore. MPM.add(createStripDeadPrototypesPass()); // Get rid of dead prototypes - MPM.add(createDeadTypeEliminationPass()); // Eliminate dead types // GlobalOpt already deletes dead functions and globals, at -O3 try a // late pass of GlobalDCE. It is capable of deleting dead cycles. Modified: llvm/trunk/include/llvm/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm/Transforms/IPO.h Sat Jul 9 12:41:24 2011 @@ -74,13 +74,6 @@ //===----------------------------------------------------------------------===// -/// createDeadTypeEliminationPass - Return a new pass that eliminates symbol -/// table entries for types that are never used. -/// -ModulePass *createDeadTypeEliminationPass(); - - -//===----------------------------------------------------------------------===// /// createGlobalDCEPass - This transform is designed to eliminate unreachable /// internal globals (functions or global variables) /// Modified: llvm/trunk/include/llvm/Transforms/Utils/ValueMapper.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/ValueMapper.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/ValueMapper.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/ValueMapper.h Sat Jul 9 12:41:24 2011 @@ -22,6 +22,18 @@ class Instruction; typedef ValueMap > ValueToValueMapTy; + /// ValueMapTypeRemapper - This is a class that can be implemented by clients + /// to remap types when cloning constants and instructions. + class ValueMapTypeRemapper { + virtual void Anchor(); // Out of line method. + public: + ~ValueMapTypeRemapper() {} + + /// remapType - The client should implement this method if they want to + /// remap types while mapping values. + virtual Type *remapType(Type *SrcTy) = 0; + }; + /// RemapFlags - These are flags that the value mapping APIs allow. enum RemapFlags { RF_None = 0, @@ -42,9 +54,27 @@ } Value *MapValue(const Value *V, ValueToValueMapTy &VM, - RemapFlags Flags = RF_None); + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = 0); + void RemapInstruction(Instruction *I, ValueToValueMapTy &VM, - RemapFlags Flags = RF_None); + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = 0); + + /// MapValue - provide versions that preserve type safety for MDNode and + /// Constants. + inline MDNode *MapValue(const MDNode *V, ValueToValueMapTy &VM, + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = 0) { + return (MDNode*)MapValue((const Value*)V, VM, Flags, TypeMapper); + } + inline Constant *MapValue(const Constant *V, ValueToValueMapTy &VM, + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = 0) { + return (Constant*)MapValue((const Value*)V, VM, Flags, TypeMapper); + } + + } // End llvm namespace #endif Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Sat Jul 9 12:41:24 2011 @@ -15,19 +15,17 @@ #ifndef LLVM_TYPE_H #define LLVM_TYPE_H -#include "llvm/AbstractTypeUser.h" #include "llvm/Support/Casting.h" -#include namespace llvm { class DerivedType; class PointerType; class IntegerType; -class TypeMapBase; class raw_ostream; class Module; class LLVMContext; +class LLVMContextImpl; template struct GraphTraits; /// The instances of the Type class are immutable: once they are created, @@ -35,29 +33,10 @@ /// type is ever created. Thus seeing if two types are equal is a matter of /// doing a trivial pointer comparison. To enforce that no two equal instances /// are created, Type instances can only be created via static factory methods -/// in class Type and in derived classes. +/// in class Type and in derived classes. Once allocated, Types are never +/// free'd. /// -/// Once allocated, Types are never free'd, unless they are an abstract type -/// that is resolved to a more concrete type. -/// -/// Types themself don't have a name, and can be named either by: -/// - using SymbolTable instance, typically from some Module, -/// - using convenience methods in the Module class (which uses module's -/// SymbolTable too). -/// -/// Opaque types are simple derived types with no state. There may be many -/// different Opaque type objects floating around, but two are only considered -/// identical if they are pointer equals of each other. This allows us to have -/// two opaque types that end up resolving to different concrete types later. -/// -/// Opaque types are also kinda weird and scary and different because they have -/// to keep a list of uses of the type. When, through linking, parsing, or -/// bitcode reading, they become resolved, they need to find and update all -/// users of the unknown type, causing them to reference a new, more concrete -/// type. Opaque types are deleted when their use list dwindles to zero users. -/// -/// @brief Root of type hierarchy -class Type : public AbstractTypeUser { +class Type { public: //===--------------------------------------------------------------------===// /// Definitions of all of the base types for the Type system. Based on this @@ -85,8 +64,7 @@ StructTyID, ///< 11: Structures ArrayTyID, ///< 12: Arrays PointerTyID, ///< 13: Pointers - OpaqueTyID, ///< 14: Opaque: type with unknown structure - VectorTyID, ///< 15: SIMD 'packed' format, or other vector type + VectorTyID, ///< 14: SIMD 'packed' format, or other vector type NumTypeIDs, // Must remain as last defined ID LastPrimitiveTyID = X86_MMXTyID, @@ -94,86 +72,42 @@ }; private: - TypeID ID : 8; // The current base type of this type. - bool Abstract : 1; // True if type contains an OpaqueType - unsigned SubclassData : 23; //Space for subclasses to store data - - /// RefCount - This counts the number of PATypeHolders that are pointing to - /// this type. When this number falls to zero, if the type is abstract and - /// has no AbstractTypeUsers, the type is deleted. This is only sensical for - /// derived types. - /// - mutable unsigned RefCount; - /// Context - This refers to the LLVMContext in which this type was uniqued. LLVMContext &Context; - friend class LLVMContextImpl; - const Type *getForwardedTypeInternal() const; - - // When the last reference to a forwarded type is removed, it is destroyed. - void destroy() const; + TypeID ID : 8; // The current base type of this type. + unsigned SubclassData : 24; // Space for subclasses to store data protected: - explicit Type(LLVMContext &C, TypeID id) : - ID(id), Abstract(false), SubclassData(0), - RefCount(0), Context(C), - ForwardType(0), NumContainedTys(0), - ContainedTys(0) {} - virtual ~Type() { - assert(AbstractTypeUsers.empty() && "Abstract types remain"); - } - - /// Types can become nonabstract later, if they are refined. - /// - inline void setAbstract(bool Val) { Abstract = Val; } - - unsigned getRefCount() const { return RefCount; } + friend class LLVMContextImpl; + explicit Type(LLVMContext &C, TypeID tid) + : Context(C), ID(tid), SubclassData(0), + NumContainedTys(0), ContainedTys(0) {} + ~Type() {} unsigned getSubclassData() const { return SubclassData; } - void setSubclassData(unsigned val) { SubclassData = val; } - - /// ForwardType - This field is used to implement the union find scheme for - /// abstract types. When types are refined to other types, this field is set - /// to the more refined type. Only abstract types can be forwarded. - mutable const Type *ForwardType; - - - /// AbstractTypeUsers - Implement a list of the users that need to be notified - /// if I am a type, and I get resolved into a more concrete type. - /// - mutable std::vector AbstractTypeUsers; + void setSubclassData(unsigned val) { + SubclassData = val; + // Ensure we don't have any accidental truncation. + assert(SubclassData == val && "Subclass data too large for field"); + } - /// NumContainedTys - Keeps track of how many PATypeHandle instances there - /// are at the end of this type instance for the list of contained types. It - /// is the subclasses responsibility to set this up. Set to 0 if there are no - /// contained types in this type. + /// NumContainedTys - Keeps track of how many Type*'s there are in the + /// ContainedTys list. unsigned NumContainedTys; - /// ContainedTys - A pointer to the array of Types (PATypeHandle) contained - /// by this Type. For example, this includes the arguments of a function - /// type, the elements of a structure, the pointee of a pointer, the element - /// type of an array, etc. This pointer may be 0 for types that don't - /// contain other types (Integer, Double, Float). In general, the subclass - /// should arrange for space for the PATypeHandles to be included in the - /// allocation of the type object and set this pointer to the address of the - /// first element. This allows the Type class to manipulate the ContainedTys - /// without understanding the subclass's placement for this array. keeping - /// it here also allows the subtype_* members to be implemented MUCH more - /// efficiently, and dynamically very few types do not contain any elements. - PATypeHandle *ContainedTys; + /// ContainedTys - A pointer to the array of Types contained by this Type. + /// For example, this includes the arguments of a function type, the elements + /// of a structure, the pointee of a pointer, the element type of an array, + /// etc. This pointer may be 0 for types that don't contain other types + /// (Integer, Double, Float). + Type * const *ContainedTys; public: void print(raw_ostream &O) const; - - /// @brief Debugging support: print to stderr void dump() const; - /// @brief Debugging support: print to stderr (use type names from context - /// module). - void dump(const Module *Context) const; - - /// getContext - Fetch the LLVMContext in which this type was uniqued. + /// getContext - Return the LLVMContext in which this type was uniqued. LLVMContext &getContext() const { return Context; } //===--------------------------------------------------------------------===// @@ -205,8 +139,10 @@ /// isFloatingPointTy - Return true if this is one of the five floating point /// types - bool isFloatingPointTy() const { return ID == FloatTyID || ID == DoubleTyID || - ID == X86_FP80TyID || ID == FP128TyID || ID == PPC_FP128TyID; } + bool isFloatingPointTy() const { + return ID == FloatTyID || ID == DoubleTyID || + ID == X86_FP80TyID || ID == FP128TyID || ID == PPC_FP128TyID; + } /// isX86_MMXTy - Return true if this is X86 MMX. bool isX86_MMXTy() const { return ID == X86_MMXTyID; } @@ -249,19 +185,10 @@ /// bool isPointerTy() const { return ID == PointerTyID; } - /// isOpaqueTy - True if this is an instance of OpaqueType. - /// - bool isOpaqueTy() const { return ID == OpaqueTyID; } - /// isVectorTy - True if this is an instance of VectorType. /// bool isVectorTy() const { return ID == VectorTyID; } - /// isAbstract - True if the type is either an Opaque type, or is a derived - /// type that includes an opaque type somewhere in it. - /// - inline bool isAbstract() const { return Abstract; } - /// canLosslesslyBitCastTo - Return true if this type could be converted /// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCasts /// are valid for types of the same size only where no re-interpretation of @@ -276,24 +203,22 @@ /// Here are some useful little methods to query what type derived types are /// Note that all other types can just compare to see if this == Type::xxxTy; /// - inline bool isPrimitiveType() const { return ID <= LastPrimitiveTyID; } - inline bool isDerivedType() const { return ID >= FirstDerivedTyID; } + bool isPrimitiveType() const { return ID <= LastPrimitiveTyID; } + bool isDerivedType() const { return ID >= FirstDerivedTyID; } /// isFirstClassType - Return true if the type is "first class", meaning it /// is a valid type for a Value. /// - inline bool isFirstClassType() const { - // There are more first-class kinds than non-first-class kinds, so a - // negative test is simpler than a positive one. - return ID != FunctionTyID && ID != VoidTyID && ID != OpaqueTyID; + bool isFirstClassType() const { + return ID != FunctionTyID && ID != VoidTyID; } /// isSingleValueType - Return true if the type is a valid type for a - /// virtual register in codegen. This includes all first-class types - /// except struct and array types. + /// register in codegen. This includes all first-class types except struct + /// and array types. /// - inline bool isSingleValueType() const { - return (ID != VoidTyID && ID <= LastPrimitiveTyID) || + bool isSingleValueType() const { + return (ID != VoidTyID && isPrimitiveType()) || ID == IntegerTyID || ID == PointerTyID || ID == VectorTyID; } @@ -302,7 +227,7 @@ /// extractvalue instruction. This includes struct and array types, but /// does not include vector types. /// - inline bool isAggregateType() const { + bool isAggregateType() const { return ID == StructTyID || ID == ArrayTyID; } @@ -319,9 +244,8 @@ // it doesn't have a size. if (ID != StructTyID && ID != ArrayTyID && ID != VectorTyID) return false; - // If it is something that can have a size and it's concrete, it definitely - // has a size, otherwise we have to try harder to decide. - return !isAbstract() || isSizedDerivedType(); + // Otherwise we have to try harder to decide. + return isSizedDerivedType(); } /// getPrimitiveSizeInBits - Return the basic size of this type if it is a @@ -346,23 +270,14 @@ /// have a stable mantissa (e.g. ppc long double), this method returns -1. int getFPMantissaWidth() const; - /// getForwardedType - Return the type that this type has been resolved to if - /// it has been resolved to anything. This is used to implement the - /// union-find algorithm for type resolution, and shouldn't be used by general - /// purpose clients. - const Type *getForwardedType() const { - if (!ForwardType) return 0; - return getForwardedTypeInternal(); - } - /// getScalarType - If this is a vector type, return the element type, - /// otherwise return this. + /// otherwise return 'this'. const Type *getScalarType() const; //===--------------------------------------------------------------------===// - // Type Iteration support + // Type Iteration support. // - typedef PATypeHandle *subtype_iterator; + typedef Type * const *subtype_iterator; subtype_iterator subtype_begin() const { return ContainedTys; } subtype_iterator subtype_end() const { return &ContainedTys[NumContainedTys];} @@ -370,9 +285,9 @@ /// (defined a the end of the file). For derived types, this returns the /// types 'contained' in the derived type. /// - const Type *getContainedType(unsigned i) const { + Type *getContainedType(unsigned i) const { assert(i < NumContainedTys && "Index out of range!"); - return ContainedTys[i].get(); + return ContainedTys[i]; } /// getNumContainedTypes - Return the number of types in the derived type. @@ -385,140 +300,77 @@ // /// getPrimitiveType - Return a type based on an identifier. - static const Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber); + static Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber); //===--------------------------------------------------------------------===// - // These are the builtin types that are always available... + // These are the builtin types that are always available. // - static const Type *getVoidTy(LLVMContext &C); - static const Type *getLabelTy(LLVMContext &C); - static const Type *getFloatTy(LLVMContext &C); - static const Type *getDoubleTy(LLVMContext &C); - static const Type *getMetadataTy(LLVMContext &C); - static const Type *getX86_FP80Ty(LLVMContext &C); - static const Type *getFP128Ty(LLVMContext &C); - static const Type *getPPC_FP128Ty(LLVMContext &C); - static const Type *getX86_MMXTy(LLVMContext &C); - static const IntegerType *getIntNTy(LLVMContext &C, unsigned N); - static const IntegerType *getInt1Ty(LLVMContext &C); - static const IntegerType *getInt8Ty(LLVMContext &C); - static const IntegerType *getInt16Ty(LLVMContext &C); - static const IntegerType *getInt32Ty(LLVMContext &C); - static const IntegerType *getInt64Ty(LLVMContext &C); + static Type *getVoidTy(LLVMContext &C); + static Type *getLabelTy(LLVMContext &C); + static Type *getFloatTy(LLVMContext &C); + static Type *getDoubleTy(LLVMContext &C); + static Type *getMetadataTy(LLVMContext &C); + static Type *getX86_FP80Ty(LLVMContext &C); + static Type *getFP128Ty(LLVMContext &C); + static Type *getPPC_FP128Ty(LLVMContext &C); + static Type *getX86_MMXTy(LLVMContext &C); + static IntegerType *getIntNTy(LLVMContext &C, unsigned N); + static IntegerType *getInt1Ty(LLVMContext &C); + static IntegerType *getInt8Ty(LLVMContext &C); + static IntegerType *getInt16Ty(LLVMContext &C); + static IntegerType *getInt32Ty(LLVMContext &C); + static IntegerType *getInt64Ty(LLVMContext &C); //===--------------------------------------------------------------------===// // Convenience methods for getting pointer types with one of the above builtin // types as pointee. // - static const PointerType *getFloatPtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getDoublePtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getX86_FP80PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, - unsigned AS = 0); - static const PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getInt32PtrTy(LLVMContext &C, unsigned AS = 0); - static const PointerType *getInt64PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getFloatPtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getDoublePtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getX86_FP80PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0); + static PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getInt32PtrTy(LLVMContext &C, unsigned AS = 0); + static PointerType *getInt64PtrTy(LLVMContext &C, unsigned AS = 0); /// Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const Type *) { return true; } - void addRef() const { - assert(isAbstract() && "Cannot add a reference to a non-abstract type!"); - ++RefCount; - } - - void dropRef() const { - assert(isAbstract() && "Cannot drop a reference to a non-abstract type!"); - assert(RefCount && "No objects are currently referencing this object!"); - - // If this is the last PATypeHolder using this object, and there are no - // PATypeHandles using it, the type is dead, delete it now. - if (--RefCount == 0 && AbstractTypeUsers.empty()) - this->destroy(); - } - - /// addAbstractTypeUser - Notify an abstract type that there is a new user of - /// it. This function is called primarily by the PATypeHandle class. - /// - void addAbstractTypeUser(AbstractTypeUser *U) const; - - /// removeAbstractTypeUser - Notify an abstract type that a user of the class - /// no longer has a handle to the type. This function is called primarily by - /// the PATypeHandle class. When there are no users of the abstract type, it - /// is annihilated, because there is no way to get a reference to it ever - /// again. - /// - void removeAbstractTypeUser(AbstractTypeUser *U) const; - /// getPointerTo - Return a pointer to the current type. This is equivalent /// to PointerType::get(Foo, AddrSpace). - const PointerType *getPointerTo(unsigned AddrSpace = 0) const; + PointerType *getPointerTo(unsigned AddrSpace = 0) const; private: /// isSizedDerivedType - Derived types like structures and arrays are sized /// iff all of the members of the type are sized as well. Since asking for /// their size is relatively uncommon, move this operation out of line. bool isSizedDerivedType() const; - - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - virtual void typeBecameConcrete(const DerivedType *AbsTy); - -protected: - // PromoteAbstractToConcrete - This is an internal method used to calculate - // change "Abstract" from true to false when types are refined. - void PromoteAbstractToConcrete(); - friend class TypeMapBase; }; -//===----------------------------------------------------------------------===// -// Define some inline methods for the AbstractTypeUser.h:PATypeHandle class. -// These are defined here because they MUST be inlined, yet are dependent on -// the definition of the Type class. -// -inline void PATypeHandle::addUser() { - assert(Ty && "Type Handle has a null type!"); - if (Ty->isAbstract()) - Ty->addAbstractTypeUser(User); -} -inline void PATypeHandle::removeUser() { - if (Ty->isAbstract()) - Ty->removeAbstractTypeUser(User); -} - -// Define inline methods for PATypeHolder. - -/// get - This implements the forwarding part of the union-find algorithm for -/// abstract types. Before every access to the Type*, we check to see if the -/// type we are pointing to is forwarding to a new type. If so, we drop our -/// reference to the type. -/// -inline Type *PATypeHolder::get() const { - if (Ty == 0) return 0; - const Type *NewTy = Ty->getForwardedType(); - if (!NewTy) return const_cast(Ty); - return *const_cast(this) = NewTy; -} - -inline void PATypeHolder::addRef() { - if (Ty && Ty->isAbstract()) - Ty->addRef(); -} - -inline void PATypeHolder::dropRef() { - if (Ty && Ty->isAbstract()) - Ty->dropRef(); +// Printing of types. +static inline raw_ostream &operator<<(raw_ostream &OS, const Type &T) { + T.print(OS); + return OS; } +// allow isa(x) to work without DerivedTypes.h included. +template <> struct isa_impl { + static inline bool doit(const Type &Ty) { + return Ty.getTypeID() == Type::PointerTyID; + } +}; + //===----------------------------------------------------------------------===// // Provide specializations of GraphTraits to be able to treat a type as a // graph of sub types. + template <> struct GraphTraits { typedef Type NodeType; typedef Type::subtype_iterator ChildIteratorType; @@ -545,14 +397,6 @@ } }; -template <> struct isa_impl { - static inline bool doit(const Type &Ty) { - return Ty.getTypeID() == Type::PointerTyID; - } -}; - -raw_ostream &operator<<(raw_ostream &OS, const Type &T); - } // End llvm namespace #endif Removed: llvm/trunk/include/llvm/TypeSymbolTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/TypeSymbolTable.h?rev=134828&view=auto ============================================================================== --- llvm/trunk/include/llvm/TypeSymbolTable.h (original) +++ llvm/trunk/include/llvm/TypeSymbolTable.h (removed) @@ -1,152 +0,0 @@ -//===-- llvm/TypeSymbolTable.h - Implement a Type Symtab --------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the name/type symbol table for LLVM. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TYPE_SYMBOL_TABLE_H -#define LLVM_TYPE_SYMBOL_TABLE_H - -#include "llvm/Type.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/Support/DataTypes.h" -#include - -namespace llvm { - -/// This class provides a symbol table of name/type pairs with operations to -/// support constructing, searching and iterating over the symbol table. The -/// class derives from AbstractTypeUser so that the contents of the symbol -/// table can be updated when abstract types become concrete. -class TypeSymbolTable : public AbstractTypeUser { - -/// @name Types -/// @{ -public: - - /// @brief A mapping of names to types. - typedef std::map TypeMap; - - /// @brief An iterator over the TypeMap. - typedef TypeMap::iterator iterator; - - /// @brief A const_iterator over the TypeMap. - typedef TypeMap::const_iterator const_iterator; - -/// @} -/// @name Constructors -/// @{ -public: - - TypeSymbolTable():LastUnique(0) {} - ~TypeSymbolTable(); - -/// @} -/// @name Accessors -/// @{ -public: - - /// Generates a unique name for a type based on the \p BaseName by - /// incrementing an integer and appending it to the name, if necessary - /// @returns the unique name - /// @brief Get a unique name for a type - std::string getUniqueName(StringRef BaseName) const; - - /// This method finds the type with the given \p name in the type map - /// and returns it. - /// @returns null if the name is not found, otherwise the Type - /// associated with the \p name. - /// @brief Lookup a type by name. - Type *lookup(StringRef name) const; - - /// Lookup the type associated with name. - /// @returns end() if the name is not found, or an iterator at the entry for - /// Type. - iterator find(StringRef Name) { - return tmap.find(Name); - } - - /// Lookup the type associated with name. - /// @returns end() if the name is not found, or an iterator at the entry for - /// Type. - const_iterator find(StringRef Name) const { - return tmap.find(Name); - } - - /// @returns true iff the symbol table is empty. - /// @brief Determine if the symbol table is empty - inline bool empty() const { return tmap.empty(); } - - /// @returns the size of the symbol table - /// @brief The number of name/type pairs is returned. - inline unsigned size() const { return unsigned(tmap.size()); } - - /// This function can be used from the debugger to display the - /// content of the symbol table while debugging. - /// @brief Print out symbol table on stderr - void dump() const; - -/// @} -/// @name Iteration -/// @{ -public: - /// Get an iterator to the start of the symbol table - inline iterator begin() { return tmap.begin(); } - - /// @brief Get a const_iterator to the start of the symbol table - inline const_iterator begin() const { return tmap.begin(); } - - /// Get an iterator to the end of the symbol table. - inline iterator end() { return tmap.end(); } - - /// Get a const_iterator to the end of the symbol table. - inline const_iterator end() const { return tmap.end(); } - -/// @} -/// @name Mutators -/// @{ -public: - - /// Inserts a type into the symbol table with the specified name. There can be - /// a many-to-one mapping between names and types. This method allows a type - /// with an existing entry in the symbol table to get a new name. - /// @brief Insert a type under a new name. - void insert(StringRef Name, const Type *Typ); - - /// Remove a type at the specified position in the symbol table. - /// @returns the removed Type. - /// @returns the Type that was erased from the symbol table. - Type* remove(iterator TI); - -/// @} -/// @name AbstractTypeUser Methods -/// @{ -private: - /// This function is called when one of the types in the type plane - /// is refined. - virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy); - - /// This function marks a type as being concrete (defined). - virtual void typeBecameConcrete(const DerivedType *AbsTy); - -/// @} -/// @name Internal Data -/// @{ -private: - TypeMap tmap; ///< This is the mapping of names to types. - mutable uint32_t LastUnique; ///< Counter for tracking unique names - -/// @} - -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/include/llvm/Value.h (original) +++ llvm/trunk/include/llvm/Value.h Sat Jul 9 12:41:24 2011 @@ -14,7 +14,6 @@ #ifndef LLVM_VALUE_H #define LLVM_VALUE_H -#include "llvm/AbstractTypeUser.h" #include "llvm/Use.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Casting.h" @@ -32,7 +31,6 @@ class GlobalAlias; class InlineAsm; class ValueSymbolTable; -class TypeSymbolTable; template class StringMapEntry; template class AssertingVH; @@ -43,6 +41,7 @@ class LLVMContext; class Twine; class MDNode; +class Type; //===----------------------------------------------------------------------===// // Value Class @@ -77,12 +76,11 @@ /// This field is initialized to zero by the ctor. unsigned short SubclassData; - PATypeHolder VTy; + Type *VTy; Use *UseList; friend class ValueSymbolTable; // Allow ValueSymbolTable to directly mod Name. friend class ValueHandleBase; - friend class AbstractTypeUser; ValueName *Name; void operator=(const Value &); // Do not implement @@ -107,13 +105,13 @@ /// All values are typed, get the type of this value. /// - inline const Type *getType() const { return VTy; } + Type *getType() const { return VTy; } /// All values hold a context through their type. LLVMContext &getContext() const; // All values can potentially be named... - inline bool hasName() const { return Name != 0; } + bool hasName() const { return Name != 0; } ValueName *getValueName() const { return Name; } /// getName() - Return a constant reference to the value's name. This is cheap @@ -279,10 +277,6 @@ return true; // Values are always values. } - /// getRawType - This should only be used to implement the vmcore library. - /// - const Type *getRawType() const { return VTy.getRawType(); } - /// stripPointerCasts - This method strips off any unneeded pointer /// casts from the specified value, returning the original uncasted value. /// Note that the returned value has pointer type if the specified value does. @@ -310,6 +304,15 @@ /// load, store, and alloca instructions, and global values. static const unsigned MaximumAlignment = 1u << 29; + /// mutateType - Mutate the type of this Value to be of the specified type. + /// Note that this is an extremely dangerous operation which can create + /// completely invalid IR very easily. It is strongly recommended that you + /// recreate IR objects with the right types instead of mutating them in + /// place. + void mutateType(Type *Ty) { + VTy = Ty; + } + protected: unsigned short getSubclassDataFromValue() const { return SubclassData; } void setValueSubclassData(unsigned short D) { SubclassData = D; } Modified: llvm/trunk/lib/AsmParser/LLLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.h (original) +++ llvm/trunk/lib/AsmParser/LLLexer.h Sat Jul 9 12:41:24 2011 @@ -38,7 +38,7 @@ lltok::Kind CurKind; std::string StrVal; unsigned UIntVal; - const Type *TyVal; + Type *TyVal; APFloat APFloatVal; APSInt APSIntVal; @@ -56,7 +56,7 @@ LocTy getLoc() const { return SMLoc::getFromPointer(TokStart); } lltok::Kind getKind() const { return CurKind; } const std::string &getStrVal() const { return StrVal; } - const Type *getTyVal() const { return TyVal; } + Type *getTyVal() const { return TyVal; } unsigned getUIntVal() const { return UIntVal; } const APSInt &getAPSIntVal() const { return APSIntVal; } const APFloat &getAPFloatVal() const { return APFloatVal; } Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Sat Jul 9 12:41:24 2011 @@ -89,15 +89,16 @@ ForwardRefBlockAddresses.erase(ForwardRefBlockAddresses.begin()); } - - if (!ForwardRefTypes.empty()) - return Error(ForwardRefTypes.begin()->second.second, - "use of undefined type named '" + - ForwardRefTypes.begin()->first + "'"); - if (!ForwardRefTypeIDs.empty()) - return Error(ForwardRefTypeIDs.begin()->second.second, - "use of undefined type '%" + - Twine(ForwardRefTypeIDs.begin()->first) + "'"); + for (unsigned i = 0, e = NumberedTypes.size(); i != e; ++i) + if (NumberedTypes[i].second.isValid()) + return Error(NumberedTypes[i].second, + "use of undefined type '%" + Twine(i) + "'"); + + for (StringMap >::iterator I = + NamedTypes.begin(), E = NamedTypes.end(); I != E; ++I) + if (I->second.second.isValid()) + return Error(I->second.second, + "use of undefined type named '" + I->getKey() + "'"); if (!ForwardRefVals.empty()) return Error(ForwardRefVals.begin()->second.second, @@ -293,36 +294,32 @@ /// ::= LocalVarID '=' 'type' type bool LLParser::ParseUnnamedType() { LocTy TypeLoc = Lex.getLoc(); - unsigned TypeID = NumberedTypes.size(); - if (Lex.getUIntVal() != TypeID) - return Error(Lex.getLoc(), "type expected to be numbered '%" + - Twine(TypeID) + "'"); + unsigned TypeID = Lex.getUIntVal(); Lex.Lex(); // eat LocalVarID; if (ParseToken(lltok::equal, "expected '=' after name") || ParseToken(lltok::kw_type, "expected 'type' after '='")) return true; - PATypeHolder Ty(Type::getVoidTy(Context)); - if (ParseType(Ty)) return true; - - // See if this type was previously referenced. - std::map >::iterator - FI = ForwardRefTypeIDs.find(TypeID); - if (FI != ForwardRefTypeIDs.end()) { - if (FI->second.first.get() == Ty) - return Error(TypeLoc, "self referential type is invalid"); - - cast(FI->second.first.get())->refineAbstractTypeTo(Ty); - Ty = FI->second.first.get(); - ForwardRefTypeIDs.erase(FI); + if (TypeID >= NumberedTypes.size()) + NumberedTypes.resize(TypeID+1); + + Type *Result = 0; + if (ParseStructDefinition(TypeLoc, "", + NumberedTypes[TypeID], Result)) return true; + + if (!isa(Result)) { + std::pair &Entry = NumberedTypes[TypeID]; + if (Entry.first) + return Error(TypeLoc, "non-struct types may not be recursive"); + Entry.first = Result; + Entry.second = SMLoc(); } - NumberedTypes.push_back(Ty); - return false; } + /// toplevelentity /// ::= LocalVar '=' 'type' type bool LLParser::ParseNamedType() { @@ -330,37 +327,23 @@ LocTy NameLoc = Lex.getLoc(); Lex.Lex(); // eat LocalVar. - PATypeHolder Ty(Type::getVoidTy(Context)); - if (ParseToken(lltok::equal, "expected '=' after name") || - ParseToken(lltok::kw_type, "expected 'type' after name") || - ParseType(Ty)) + ParseToken(lltok::kw_type, "expected 'type' after name")) return true; - - // Set the type name, checking for conflicts as we do so. - bool AlreadyExists = M->addTypeName(Name, Ty); - if (!AlreadyExists) return false; - - // See if this type is a forward reference. We need to eagerly resolve - // types to allow recursive type redefinitions below. - std::map >::iterator - FI = ForwardRefTypes.find(Name); - if (FI != ForwardRefTypes.end()) { - if (FI->second.first.get() == Ty) - return Error(NameLoc, "self referential type is invalid"); - - cast(FI->second.first.get())->refineAbstractTypeTo(Ty); - Ty = FI->second.first.get(); - ForwardRefTypes.erase(FI); - return false; + + Type *Result = 0; + if (ParseStructDefinition(NameLoc, Name, + NamedTypes[Name], Result)) return true; + + if (!isa(Result)) { + std::pair &Entry = NamedTypes[Name]; + if (Entry.first) + return Error(NameLoc, "non-struct types may not be recursive"); + Entry.first = Result; + Entry.second = SMLoc(); } - - // Inserting a name that is already defined, get the existing name. - assert(M->getTypeByName(Name) && "Conflict but no matching type?!"); - - // Otherwise, this is an attempt to redefine a type, report the error. - return Error(NameLoc, "redefinition of type named '" + Name + "' of type '" + - getTypeString(Ty) + "'"); + + return false; } @@ -536,7 +519,7 @@ unsigned MetadataID = 0; LocTy TyLoc; - PATypeHolder Ty(Type::getVoidTy(Context)); + Type *Ty = 0; SmallVector Elts; if (ParseUInt32(MetadataID) || ParseToken(lltok::equal, "expected '=' here") || @@ -668,7 +651,7 @@ LocTy UnnamedAddrLoc; LocTy TyLoc; - PATypeHolder Ty(Type::getVoidTy(Context)); + Type *Ty = 0; if (ParseOptionalToken(lltok::kw_thread_local, ThreadLocal) || ParseOptionalAddrSpace(AddrSpace) || ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr, @@ -792,18 +775,11 @@ // Otherwise, create a new forward reference for this value and remember it. GlobalValue *FwdVal; - if (const FunctionType *FT = dyn_cast(PTy->getElementType())) { - // Function types can return opaque but functions can't. - if (FT->getReturnType()->isOpaqueTy()) { - Error(Loc, "function may not return opaque type"); - return 0; - } - + if (const FunctionType *FT = dyn_cast(PTy->getElementType())) FwdVal = Function::Create(FT, GlobalValue::ExternalWeakLinkage, Name, M); - } else { + else FwdVal = new GlobalVariable(*M, PTy->getElementType(), false, GlobalValue::ExternalWeakLinkage, 0, Name); - } ForwardRefVals[Name] = std::make_pair(FwdVal, Loc); return FwdVal; @@ -837,17 +813,11 @@ // Otherwise, create a new forward reference for this value and remember it. GlobalValue *FwdVal; - if (const FunctionType *FT = dyn_cast(PTy->getElementType())) { - // Function types can return opaque but functions can't. - if (FT->getReturnType()->isOpaqueTy()) { - Error(Loc, "function may not return opaque type"); - return 0; - } + if (const FunctionType *FT = dyn_cast(PTy->getElementType())) FwdVal = Function::Create(FT, GlobalValue::ExternalWeakLinkage, "", M); - } else { + else FwdVal = new GlobalVariable(*M, PTy->getElementType(), false, GlobalValue::ExternalWeakLinkage, 0, ""); - } ForwardRefValIDs[ID] = std::make_pair(FwdVal, Loc); return FwdVal; @@ -1228,165 +1198,68 @@ // Type Parsing. //===----------------------------------------------------------------------===// -/// ParseType - Parse and resolve a full type. -bool LLParser::ParseType(PATypeHolder &Result, bool AllowVoid) { - LocTy TypeLoc = Lex.getLoc(); - if (ParseTypeRec(Result)) return true; - - // Verify no unresolved uprefs. - if (!UpRefs.empty()) - return Error(UpRefs.back().Loc, "invalid unresolved type up reference"); - - if (!AllowVoid && Result.get()->isVoidTy()) - return Error(TypeLoc, "void type only allowed for function results"); - - return false; -} - -/// HandleUpRefs - Every time we finish a new layer of types, this function is -/// called. It loops through the UpRefs vector, which is a list of the -/// currently active types. For each type, if the up-reference is contained in -/// the newly completed type, we decrement the level count. When the level -/// count reaches zero, the up-referenced type is the type that is passed in: -/// thus we can complete the cycle. -/// -PATypeHolder LLParser::HandleUpRefs(const Type *ty) { - // If Ty isn't abstract, or if there are no up-references in it, then there is - // nothing to resolve here. - if (!ty->isAbstract() || UpRefs.empty()) return ty; - - PATypeHolder Ty(ty); -#if 0 - dbgs() << "Type '" << *Ty - << "' newly formed. Resolving upreferences.\n" - << UpRefs.size() << " upreferences active!\n"; -#endif - - // If we find any resolvable upreferences (i.e., those whose NestingLevel goes - // to zero), we resolve them all together before we resolve them to Ty. At - // the end of the loop, if there is anything to resolve to Ty, it will be in - // this variable. - OpaqueType *TypeToResolve = 0; - - for (unsigned i = 0; i != UpRefs.size(); ++i) { - // Determine if 'Ty' directly contains this up-references 'LastContainedTy'. - bool ContainsType = - std::find(Ty->subtype_begin(), Ty->subtype_end(), - UpRefs[i].LastContainedTy) != Ty->subtype_end(); - -#if 0 - dbgs() << " UR#" << i << " - TypeContains(" << *Ty << ", " - << *UpRefs[i].LastContainedTy << ") = " - << (ContainsType ? "true" : "false") - << " level=" << UpRefs[i].NestingLevel << "\n"; -#endif - if (!ContainsType) - continue; - - // Decrement level of upreference - unsigned Level = --UpRefs[i].NestingLevel; - UpRefs[i].LastContainedTy = Ty; - - // If the Up-reference has a non-zero level, it shouldn't be resolved yet. - if (Level != 0) - continue; - -#if 0 - dbgs() << " * Resolving upreference for " << UpRefs[i].UpRefTy << "\n"; -#endif - if (!TypeToResolve) - TypeToResolve = UpRefs[i].UpRefTy; - else - UpRefs[i].UpRefTy->refineAbstractTypeTo(TypeToResolve); - UpRefs.erase(UpRefs.begin()+i); // Remove from upreference list. - --i; // Do not skip the next element. - } - - if (TypeToResolve) - TypeToResolve->refineAbstractTypeTo(Ty); - - return Ty; -} - - -/// ParseTypeRec - The recursive function used to process the internal -/// implementation details of types. -bool LLParser::ParseTypeRec(PATypeHolder &Result) { +/// ParseType - Parse a type. +bool LLParser::ParseType(Type *&Result, bool AllowVoid) { + SMLoc TypeLoc = Lex.getLoc(); switch (Lex.getKind()) { default: return TokError("expected type"); case lltok::Type: - // TypeRec ::= 'float' | 'void' (etc) + // Type ::= 'float' | 'void' (etc) Result = Lex.getTyVal(); Lex.Lex(); break; - case lltok::kw_opaque: - // TypeRec ::= 'opaque' - Result = OpaqueType::get(Context); - Lex.Lex(); - break; case lltok::lbrace: - // TypeRec ::= '{' ... '}' - if (ParseStructType(Result, false)) + // Type ::= StructType + if (ParseAnonStructType(Result, false)) return true; break; case lltok::lsquare: - // TypeRec ::= '[' ... ']' + // Type ::= '[' ... ']' Lex.Lex(); // eat the lsquare. if (ParseArrayVectorType(Result, false)) return true; break; case lltok::less: // Either vector or packed struct. - // TypeRec ::= '<' ... '>' + // Type ::= '<' ... '>' Lex.Lex(); if (Lex.getKind() == lltok::lbrace) { - if (ParseStructType(Result, true) || + if (ParseAnonStructType(Result, true) || ParseToken(lltok::greater, "expected '>' at end of packed struct")) return true; } else if (ParseArrayVectorType(Result, true)) return true; break; - case lltok::LocalVar: - // TypeRec ::= %foo - if (const Type *T = M->getTypeByName(Lex.getStrVal())) { - Result = T; - } else { - Result = OpaqueType::get(Context); - ForwardRefTypes.insert(std::make_pair(Lex.getStrVal(), - std::make_pair(Result, - Lex.getLoc()))); - M->addTypeName(Lex.getStrVal(), Result.get()); + case lltok::LocalVar: { + // Type ::= %foo + std::pair &Entry = NamedTypes[Lex.getStrVal()]; + + // If the type hasn't been defined yet, create a forward definition and + // remember where that forward def'n was seen (in case it never is defined). + if (Entry.first == 0) { + Entry.first = StructType::createNamed(Context, Lex.getStrVal()); + Entry.second = Lex.getLoc(); } + Result = Entry.first; Lex.Lex(); break; + } - case lltok::LocalVarID: - // TypeRec ::= %4 - if (Lex.getUIntVal() < NumberedTypes.size()) - Result = NumberedTypes[Lex.getUIntVal()]; - else { - std::map >::iterator - I = ForwardRefTypeIDs.find(Lex.getUIntVal()); - if (I != ForwardRefTypeIDs.end()) - Result = I->second.first; - else { - Result = OpaqueType::get(Context); - ForwardRefTypeIDs.insert(std::make_pair(Lex.getUIntVal(), - std::make_pair(Result, - Lex.getLoc()))); - } + case lltok::LocalVarID: { + // Type ::= %4 + if (Lex.getUIntVal() >= NumberedTypes.size()) + NumberedTypes.resize(Lex.getUIntVal()+1); + std::pair &Entry = NumberedTypes[Lex.getUIntVal()]; + + // If the type hasn't been defined yet, create a forward definition and + // remember where that forward def'n was seen (in case it never is defined). + if (Entry.first == 0) { + Entry.first = StructType::createNamed(Context, ""); + Entry.second = Lex.getLoc(); } + Result = Entry.first; Lex.Lex(); break; - case lltok::backslash: { - // TypeRec ::= '\' 4 - Lex.Lex(); - unsigned Val; - if (ParseUInt32(Val)) return true; - OpaqueType *OT = OpaqueType::get(Context); //Use temporary placeholder. - UpRefs.push_back(UpRefRecord(Lex.getLoc(), Val, OT)); - Result = OT; - break; } } @@ -1394,34 +1267,37 @@ while (1) { switch (Lex.getKind()) { // End of type. - default: return false; + default: + if (!AllowVoid && Result->isVoidTy()) + return Error(TypeLoc, "void type only allowed for function results"); + return false; - // TypeRec ::= TypeRec '*' + // Type ::= Type '*' case lltok::star: - if (Result.get()->isLabelTy()) + if (Result->isLabelTy()) return TokError("basic block pointers are invalid"); - if (Result.get()->isVoidTy()) - return TokError("pointers to void are invalid; use i8* instead"); - if (!PointerType::isValidElementType(Result.get())) + if (Result->isVoidTy()) + return TokError("pointers to void are invalid - use i8* instead"); + if (!PointerType::isValidElementType(Result)) return TokError("pointer to this type is invalid"); - Result = HandleUpRefs(PointerType::getUnqual(Result.get())); + Result = PointerType::getUnqual(Result); Lex.Lex(); break; - // TypeRec ::= TypeRec 'addrspace' '(' uint32 ')' '*' + // Type ::= Type 'addrspace' '(' uint32 ')' '*' case lltok::kw_addrspace: { - if (Result.get()->isLabelTy()) + if (Result->isLabelTy()) return TokError("basic block pointers are invalid"); - if (Result.get()->isVoidTy()) + if (Result->isVoidTy()) return TokError("pointers to void are invalid; use i8* instead"); - if (!PointerType::isValidElementType(Result.get())) + if (!PointerType::isValidElementType(Result)) return TokError("pointer to this type is invalid"); unsigned AddrSpace; if (ParseOptionalAddrSpace(AddrSpace) || ParseToken(lltok::star, "expected '*' in address space")) return true; - Result = HandleUpRefs(PointerType::get(Result.get(), AddrSpace)); + Result = PointerType::get(Result, AddrSpace); break; } @@ -1452,7 +1328,7 @@ // Parse the argument. LocTy ArgLoc; - PATypeHolder ArgTy(Type::getVoidTy(Context)); + Type *ArgTy = 0; unsigned ArgAttrs1 = Attribute::None; unsigned ArgAttrs2 = Attribute::None; Value *V; @@ -1472,7 +1348,7 @@ /// ParseArgumentList - Parse the argument list for a function type or function -/// prototype. If 'inType' is true then we are parsing a FunctionType. +/// prototype. /// ::= '(' ArgTypeListI ')' /// ArgTypeListI /// ::= /*empty*/ @@ -1480,8 +1356,8 @@ /// ::= ArgTypeList ',' '...' /// ::= ArgType (',' ArgType)* /// -bool LLParser::ParseArgumentList(std::vector &ArgList, - bool &isVarArg, bool inType) { +bool LLParser::ParseArgumentList(SmallVectorImpl &ArgList, + bool &isVarArg){ isVarArg = false; assert(Lex.getKind() == lltok::lparen); Lex.Lex(); // eat the (. @@ -1493,14 +1369,11 @@ Lex.Lex(); } else { LocTy TypeLoc = Lex.getLoc(); - PATypeHolder ArgTy(Type::getVoidTy(Context)); + Type *ArgTy = 0; unsigned Attrs; std::string Name; - // If we're parsing a type, use ParseTypeRec, because we allow recursive - // types (such as a function returning a pointer to itself). If parsing a - // function prototype, we require fully resolved types. - if ((inType ? ParseTypeRec(ArgTy) : ParseType(ArgTy)) || + if (ParseType(ArgTy) || ParseOptionalAttrs(Attrs, 0)) return true; if (ArgTy->isVoidTy()) @@ -1525,8 +1398,7 @@ // Otherwise must be an argument type. TypeLoc = Lex.getLoc(); - if ((inType ? ParseTypeRec(ArgTy) : ParseType(ArgTy)) || - ParseOptionalAttrs(Attrs, 0)) return true; + if (ParseType(ArgTy) || ParseOptionalAttrs(Attrs, 0)) return true; if (ArgTy->isVoidTy()) return Error(TypeLoc, "argument can not have void type"); @@ -1538,7 +1410,7 @@ Name = ""; } - if (!ArgTy->isFirstClassType() && !ArgTy->isOpaqueTy()) + if (!ArgTy->isFirstClassType()) return Error(TypeLoc, "invalid type for function argument"); ArgList.push_back(ArgInfo(TypeLoc, ArgTy, Attrs, Name)); @@ -1550,15 +1422,15 @@ /// ParseFunctionType /// ::= Type ArgumentList OptionalAttrs -bool LLParser::ParseFunctionType(PATypeHolder &Result) { +bool LLParser::ParseFunctionType(Type *&Result) { assert(Lex.getKind() == lltok::lparen); if (!FunctionType::isValidReturnType(Result)) return TokError("invalid function return type"); - std::vector ArgList; + SmallVector ArgList; bool isVarArg; - if (ParseArgumentList(ArgList, isVarArg, true)) + if (ParseArgumentList(ArgList, isVarArg)) return true; // Reject names on the arguments lists. @@ -1570,68 +1442,122 @@ "argument attributes invalid in function type"); } - std::vector ArgListTy; + SmallVector ArgListTy; for (unsigned i = 0, e = ArgList.size(); i != e; ++i) - ArgListTy.push_back(ArgList[i].Type); + ArgListTy.push_back(ArgList[i].Ty); + + Result = FunctionType::get(Result, ArgListTy, isVarArg); + return false; +} - Result = HandleUpRefs(FunctionType::get(Result.get(), - ArgListTy, isVarArg)); +/// ParseAnonStructType - Parse an anonymous struct type, which is inlined into +/// other structs. +bool LLParser::ParseAnonStructType(Type *&Result, bool Packed) { + SmallVector Elts; + if (ParseStructBody(Elts)) return true; + + Result = StructType::get(Context, Elts, Packed); + return false; +} + +/// ParseStructDefinition - Parse a struct in a 'type' definition. +bool LLParser::ParseStructDefinition(SMLoc TypeLoc, StringRef Name, + std::pair &Entry, + Type *&ResultTy) { + // If the type was already defined, diagnose the redefinition. + if (Entry.first && !Entry.second.isValid()) + return Error(TypeLoc, "redefinition of type"); + + // If we have opaque, just return without filling in the definition for the + // struct. This counts as a definition as far as the .ll file goes. + if (EatIfPresent(lltok::kw_opaque)) { + // This type is being defined, so clear the location to indicate this. + Entry.second = SMLoc(); + + // If this type number has never been uttered, create it. + if (Entry.first == 0) + Entry.first = StructType::createNamed(Context, Name); + ResultTy = Entry.first; + return false; + } + + // If the type starts with '<', then it is either a packed struct or a vector. + bool isPacked = EatIfPresent(lltok::less); + + // If we don't have a struct, then we have a random type alias, which we + // accept for compatibility with old files. These types are not allowed to be + // forward referenced and not allowed to be recursive. + if (Lex.getKind() != lltok::lbrace) { + if (Entry.first) + return Error(TypeLoc, "forward references to non-struct type"); + + ResultTy = 0; + if (isPacked) + return ParseArrayVectorType(ResultTy, true); + return ParseType(ResultTy); + } + + // This type is being defined, so clear the location to indicate this. + Entry.second = SMLoc(); + + // If this type number has never been uttered, create it. + if (Entry.first == 0) + Entry.first = StructType::createNamed(Context, Name); + + StructType *STy = cast(Entry.first); + + SmallVector Body; + if (ParseStructBody(Body) || + (isPacked && ParseToken(lltok::greater, "expected '>' in packed struct"))) + return true; + + STy->setBody(Body, isPacked); + ResultTy = STy; return false; } + /// ParseStructType: Handles packed and unpacked types. parsed elsewhere. -/// TypeRec +/// StructType /// ::= '{' '}' -/// ::= '{' TypeRec (',' TypeRec)* '}' +/// ::= '{' Type (',' Type)* '}' /// ::= '<' '{' '}' '>' -/// ::= '<' '{' TypeRec (',' TypeRec)* '}' '>' -bool LLParser::ParseStructType(PATypeHolder &Result, bool Packed) { +/// ::= '<' '{' Type (',' Type)* '}' '>' +bool LLParser::ParseStructBody(SmallVectorImpl &Body) { assert(Lex.getKind() == lltok::lbrace); Lex.Lex(); // Consume the '{' - if (EatIfPresent(lltok::rbrace)) { - Result = StructType::get(Context, Packed); + // Handle the empty struct. + if (EatIfPresent(lltok::rbrace)) return false; - } - std::vector ParamsList; LocTy EltTyLoc = Lex.getLoc(); - if (ParseTypeRec(Result)) return true; - ParamsList.push_back(Result); + Type *Ty = 0; + if (ParseType(Ty)) return true; + Body.push_back(Ty); - if (Result->isVoidTy()) - return Error(EltTyLoc, "struct element can not have void type"); - if (!StructType::isValidElementType(Result)) + if (!StructType::isValidElementType(Ty)) return Error(EltTyLoc, "invalid element type for struct"); while (EatIfPresent(lltok::comma)) { EltTyLoc = Lex.getLoc(); - if (ParseTypeRec(Result)) return true; + if (ParseType(Ty)) return true; - if (Result->isVoidTy()) - return Error(EltTyLoc, "struct element can not have void type"); - if (!StructType::isValidElementType(Result)) + if (!StructType::isValidElementType(Ty)) return Error(EltTyLoc, "invalid element type for struct"); - ParamsList.push_back(Result); + Body.push_back(Ty); } - if (ParseToken(lltok::rbrace, "expected '}' at end of struct")) - return true; - - std::vector ParamsListTy; - for (unsigned i = 0, e = ParamsList.size(); i != e; ++i) - ParamsListTy.push_back(ParamsList[i].get()); - Result = HandleUpRefs(StructType::get(Context, ParamsListTy, Packed)); - return false; + return ParseToken(lltok::rbrace, "expected '}' at end of struct"); } /// ParseArrayVectorType - Parse an array or vector type, assuming the first /// token has already been consumed. -/// TypeRec +/// Type /// ::= '[' APSINTVAL 'x' Types ']' /// ::= '<' APSINTVAL 'x' Types '>' -bool LLParser::ParseArrayVectorType(PATypeHolder &Result, bool isVector) { +bool LLParser::ParseArrayVectorType(Type *&Result, bool isVector) { if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() || Lex.getAPSIntVal().getBitWidth() > 64) return TokError("expected number in address space"); @@ -1644,11 +1570,8 @@ return true; LocTy TypeLoc = Lex.getLoc(); - PATypeHolder EltTy(Type::getVoidTy(Context)); - if (ParseTypeRec(EltTy)) return true; - - if (EltTy->isVoidTy()) - return Error(TypeLoc, "array and vector element type cannot be void"); + Type *EltTy = 0; + if (ParseType(EltTy)) return true; if (ParseToken(isVector ? lltok::greater : lltok::rsquare, "expected end of sequential type")) @@ -1665,7 +1588,7 @@ } else { if (!ArrayType::isValidElementType(EltTy)) return Error(TypeLoc, "invalid array element type"); - Result = HandleUpRefs(ArrayType::get(EltTy, Size)); + Result = ArrayType::get(EltTy, Size); } return false; } @@ -1770,7 +1693,7 @@ } // Don't make placeholders with invalid type. - if (!Ty->isFirstClassType() && !Ty->isOpaqueTy() && !Ty->isLabelTy()) { + if (!Ty->isFirstClassType() && !Ty->isLabelTy()) { P.Error(Loc, "invalid use of a non-first-class type"); return 0; } @@ -1811,7 +1734,7 @@ return 0; } - if (!Ty->isFirstClassType() && !Ty->isOpaqueTy() && !Ty->isLabelTy()) { + if (!Ty->isFirstClassType() && !Ty->isLabelTy()) { P.Error(Loc, "invalid use of a non-first-class type"); return 0; } @@ -1987,9 +1910,10 @@ ParseToken(lltok::rbrace, "expected end of struct constant")) return true; - // FIXME: Get this type from context instead of reconstructing it! - ID.ConstantVal = ConstantStruct::getAnon(Context, Elts); - ID.Kind = ValID::t_Constant; + ID.ConstantStructElts = new Constant*[Elts.size()]; + ID.UIntVal = Elts.size(); + memcpy(ID.ConstantStructElts, Elts.data(), Elts.size()*sizeof(Elts[0])); + ID.Kind = ValID::t_ConstantStruct; return false; } case lltok::less: { @@ -2007,9 +1931,10 @@ return true; if (isPackedStruct) { - // FIXME: Get this type from context instead of reconstructing it! - ID.ConstantVal = ConstantStruct::getAnon(Context, Elts, true); - ID.Kind = ValID::t_Constant; + ID.ConstantStructElts = new Constant*[Elts.size()]; + memcpy(ID.ConstantStructElts, Elts.data(), Elts.size()*sizeof(Elts[0])); + ID.UIntVal = Elts.size(); + ID.Kind = ValID::t_PackedConstantStruct; return false; } @@ -2131,7 +2056,7 @@ case lltok::kw_inttoptr: case lltok::kw_ptrtoint: { unsigned Opc = Lex.getUIntVal(); - PATypeHolder DestTy(Type::getVoidTy(Context)); + Type *DestTy = 0; Constant *SrcVal; Lex.Lex(); if (ParseToken(lltok::lparen, "expected '(' after constantexpr cast") || @@ -2414,9 +2339,9 @@ } bool LLParser::ParseGlobalTypeAndValue(Constant *&V) { - PATypeHolder Type(Type::getVoidTy(Context)); - return ParseType(Type) || - ParseGlobalValue(Type, V); + Type *Ty = 0; + return ParseType(Ty) || + ParseGlobalValue(Ty, V); } /// ParseGlobalValueVector @@ -2562,8 +2487,7 @@ return false; case ValID::t_Undef: // FIXME: LabelTy should not be a first-class type. - if ((!Ty->isFirstClassType() || Ty->isLabelTy()) && - !Ty->isOpaqueTy()) + if (!Ty->isFirstClassType() || Ty->isLabelTy()) return Error(ID.Loc, "invalid type for undef constant"); V = UndefValue::get(Ty); return false; @@ -2584,20 +2508,40 @@ V = ID.ConstantVal; return false; + case ValID::t_ConstantStruct: + case ValID::t_PackedConstantStruct: + if (const StructType *ST = dyn_cast(Ty)) { + if (ST->getNumElements() != ID.UIntVal) + return Error(ID.Loc, + "initializer with struct type has wrong # elements"); + if (ST->isPacked() != (ID.Kind == ValID::t_PackedConstantStruct)) + return Error(ID.Loc, "packed'ness of initializer and type don't match"); + + // Verify that the elements are compatible with the structtype. + for (unsigned i = 0, e = ID.UIntVal; i != e; ++i) + if (ID.ConstantStructElts[i]->getType() != ST->getElementType(i)) + return Error(ID.Loc, "element " + Twine(i) + + " of struct initializer doesn't match struct element type"); + + V = ConstantStruct::get(ST, ArrayRef(ID.ConstantStructElts, + ID.UIntVal)); + } else + return Error(ID.Loc, "constant expression type mismatch"); + return false; } } -bool LLParser::ParseValue(const Type *Ty, Value *&V, PerFunctionState &PFS) { +bool LLParser::ParseValue(const Type *Ty, Value *&V, PerFunctionState *PFS) { V = 0; ValID ID; - return ParseValID(ID, &PFS) || - ConvertValIDToValue(Ty, ID, V, &PFS); + return ParseValID(ID, PFS) || + ConvertValIDToValue(Ty, ID, V, PFS); } -bool LLParser::ParseTypeAndValue(Value *&V, PerFunctionState &PFS) { - PATypeHolder T(Type::getVoidTy(Context)); - return ParseType(T) || - ParseValue(T, V, PFS); +bool LLParser::ParseTypeAndValue(Value *&V, PerFunctionState *PFS) { + Type *Ty = 0; + return ParseType(Ty) || + ParseValue(Ty, V, PFS); } bool LLParser::ParseTypeAndBasicBlock(BasicBlock *&BB, LocTy &Loc, @@ -2623,7 +2567,7 @@ unsigned Visibility, RetAttrs; CallingConv::ID CC; - PATypeHolder RetType(Type::getVoidTy(Context)); + Type *RetType = 0; LocTy RetTypeLoc = Lex.getLoc(); if (ParseOptionalLinkage(Linkage) || ParseOptionalVisibility(Visibility) || @@ -2660,8 +2604,7 @@ return Error(LinkageLoc, "invalid function linkage type"); } - if (!FunctionType::isValidReturnType(RetType) || - RetType->isOpaqueTy()) + if (!FunctionType::isValidReturnType(RetType)) return Error(RetTypeLoc, "invalid function return type"); LocTy NameLoc = Lex.getLoc(); @@ -2684,7 +2627,7 @@ if (Lex.getKind() != lltok::lparen) return TokError("expected '(' in function argument list"); - std::vector ArgList; + SmallVector ArgList; bool isVarArg; unsigned FuncAttrs; std::string Section; @@ -2693,7 +2636,7 @@ bool UnnamedAddr; LocTy UnnamedAddrLoc; - if (ParseArgumentList(ArgList, isVarArg, false) || + if (ParseArgumentList(ArgList, isVarArg) || ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr, &UnnamedAddrLoc) || ParseOptionalAttrs(FuncAttrs, 2) || @@ -2719,7 +2662,7 @@ Attrs.push_back(AttributeWithIndex::get(0, RetAttrs)); for (unsigned i = 0, e = ArgList.size(); i != e; ++i) { - ParamTypeList.push_back(ArgList[i].Type); + ParamTypeList.push_back(ArgList[i].Ty); if (ArgList[i].Attrs != Attribute::None) Attrs.push_back(AttributeWithIndex::get(i+1, ArgList[i].Attrs)); } @@ -3052,11 +2995,18 @@ /// ::= 'ret' void (',' !dbg, !1)* /// ::= 'ret' TypeAndValue (',' !dbg, !1)* bool LLParser::ParseRet(Instruction *&Inst, BasicBlock *BB, - PerFunctionState &PFS) { - PATypeHolder Ty(Type::getVoidTy(Context)); + PerFunctionState &PFS) { + SMLoc TypeLoc = Lex.getLoc(); + Type *Ty = 0; if (ParseType(Ty, true /*void allowed*/)) return true; + Type *ResType = PFS.getFunction().getReturnType(); + if (Ty->isVoidTy()) { + if (!ResType->isVoidTy()) + return Error(TypeLoc, "value doesn't match function result type '" + + getTypeString(ResType) + "'"); + Inst = ReturnInst::Create(Context); return false; } @@ -3064,6 +3014,10 @@ Value *RV; if (ParseValue(Ty, RV, PFS)) return true; + if (ResType != RV->getType()) + return Error(TypeLoc, "value doesn't match function result type '" + + getTypeString(ResType) + "'"); + Inst = ReturnInst::Create(Context, RV); return false; } @@ -3191,7 +3145,7 @@ LocTy CallLoc = Lex.getLoc(); unsigned RetAttrs, FnAttrs; CallingConv::ID CC; - PATypeHolder RetType(Type::getVoidTy(Context)); + Type *RetType = 0; LocTy RetTypeLoc; ValID CalleeID; SmallVector ArgList; @@ -3369,8 +3323,9 @@ /// ::= CastOpc TypeAndValue 'to' Type bool LLParser::ParseCast(Instruction *&Inst, PerFunctionState &PFS, unsigned Opc) { - LocTy Loc; Value *Op; - PATypeHolder DestTy(Type::getVoidTy(Context)); + LocTy Loc; + Value *Op; + Type *DestTy = 0; if (ParseTypeAndValue(Op, Loc, PFS) || ParseToken(lltok::kw_to, "expected 'to' after cast value") || ParseType(DestTy)) @@ -3409,7 +3364,7 @@ /// ::= 'va_arg' TypeAndValue ',' Type bool LLParser::ParseVA_Arg(Instruction *&Inst, PerFunctionState &PFS) { Value *Op; - PATypeHolder EltTy(Type::getVoidTy(Context)); + Type *EltTy = 0; LocTy TypeLoc; if (ParseTypeAndValue(Op, PFS) || ParseToken(lltok::comma, "expected ',' after vaarg operand") || @@ -3481,11 +3436,10 @@ /// ParsePHI /// ::= 'phi' Type '[' Value ',' Value ']' (',' '[' Value ',' Value ']')* int LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) { - PATypeHolder Ty(Type::getVoidTy(Context)); + Type *Ty = 0; LocTy TypeLoc; Value *Op0, *Op1; - LocTy TypeLoc = Lex.getLoc(); - if (ParseType(Ty) || + if (ParseType(Ty, TypeLoc) || ParseToken(lltok::lsquare, "expected '[' in phi value list") || ParseValue(Ty, Op0, PFS) || ParseToken(lltok::comma, "expected ',' after insertelement value") || @@ -3531,7 +3485,7 @@ bool isTail) { unsigned RetAttrs, FnAttrs; CallingConv::ID CC; - PATypeHolder RetType(Type::getVoidTy(Context)); + Type *RetType = 0; LocTy RetTypeLoc; ValID CalleeID; SmallVector ArgList; @@ -3620,10 +3574,10 @@ /// ParseAlloc /// ::= 'alloca' Type (',' TypeAndValue)? (',' OptionalInfo)? int LLParser::ParseAlloc(Instruction *&Inst, PerFunctionState &PFS) { - PATypeHolder Ty(Type::getVoidTy(Context)); Value *Size = 0; LocTy SizeLoc; unsigned Alignment = 0; + Type *Ty = 0; if (ParseType(Ty)) return true; bool AteExtraComma = false; @@ -3787,12 +3741,7 @@ } Value *V = 0; - PATypeHolder Ty(Type::getVoidTy(Context)); - ValID ID; - if (ParseType(Ty) || ParseValID(ID, PFS) || - ConvertValIDToValue(Ty, ID, V, PFS)) - return true; - + if (ParseTypeAndValue(V, PFS)) return true; Elts.push_back(V); } while (EatIfPresent(lltok::comma)); Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Sat Jul 9 12:41:24 2011 @@ -18,6 +18,7 @@ #include "llvm/Module.h" #include "llvm/Type.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/StringMap.h" #include "llvm/Support/ValueHandle.h" #include @@ -32,6 +33,7 @@ class GlobalValue; class MDString; class MDNode; + class StructType; /// ValID - Represents a reference of a definition of some sort with no type. /// There are several cases where we have to parse the value but where the @@ -47,7 +49,9 @@ t_Constant, // Value in ConstantVal. t_InlineAsm, // Value in StrVal/StrVal2/UIntVal. t_MDNode, // Value in MDNodeVal. - t_MDString // Value in MDStringVal. + t_MDString, // Value in MDStringVal. + t_ConstantStruct, // Value in ConstantStructElts. + t_PackedConstantStruct // Value in ConstantStructElts. } Kind; LLLexer::LocTy Loc; @@ -58,12 +62,19 @@ Constant *ConstantVal; MDNode *MDNodeVal; MDString *MDStringVal; - ValID() : APFloatVal(0.0) {} + Constant **ConstantStructElts; + + ValID() : Kind(t_LocalID), APFloatVal(0.0) {} + ~ValID() { + if (Kind == t_ConstantStruct || Kind == t_PackedConstantStruct) + delete [] ConstantStructElts; + } bool operator<(const ValID &RHS) const { if (Kind == t_LocalID || Kind == t_GlobalID) return UIntVal < RHS.UIntVal; - assert((Kind == t_LocalName || Kind == t_GlobalName) && + assert((Kind == t_LocalName || Kind == t_GlobalName || + Kind == t_ConstantStruct || Kind == t_PackedConstantStruct) && "Ordering not defined for this ValID kind yet"); return StrVal < RHS.StrVal; } @@ -93,33 +104,13 @@ }; DenseMap > ForwardRefInstMetadata; - // Type resolution handling data structures. - std::map > ForwardRefTypes; - std::map > ForwardRefTypeIDs; - std::vector NumberedTypes; + // Type resolution handling data structures. The location is set when we + // have processed a use of the type but not a definition yet. + StringMap > NamedTypes; + std::vector > NumberedTypes; + std::vector > NumberedMetadata; std::map, LocTy> > ForwardRefMDNodes; - struct UpRefRecord { - /// Loc - This is the location of the upref. - LocTy Loc; - - /// NestingLevel - The number of nesting levels that need to be popped - /// before this type is resolved. - unsigned NestingLevel; - - /// LastContainedTy - This is the type at the current binding level for - /// the type. Every time we reduce the nesting level, this gets updated. - const Type *LastContainedTy; - - /// UpRefTy - This is the actual opaque type that the upreference is - /// represented with. - OpaqueType *UpRefTy; - - UpRefRecord(LocTy L, unsigned NL, OpaqueType *URTy) - : Loc(L), NestingLevel(NL), LastContainedTy((Type*)URTy), - UpRefTy(URTy) {} - }; - std::vector UpRefs; // Global Value reference information. std::map > ForwardRefVals; @@ -137,7 +128,7 @@ M(m) {} bool Run(); - LLVMContext& getContext() { return Context; } + LLVMContext &getContext() { return Context; } private: @@ -222,16 +213,19 @@ bool ParseMDNodeID(MDNode *&Result, unsigned &SlotNo); // Type Parsing. - bool ParseType(PATypeHolder &Result, bool AllowVoid = false); - bool ParseType(PATypeHolder &Result, LocTy &Loc, bool AllowVoid = false) { + bool ParseType(Type *&Result, bool AllowVoid = false); + bool ParseType(Type *&Result, LocTy &Loc, bool AllowVoid = false) { Loc = Lex.getLoc(); return ParseType(Result, AllowVoid); } - bool ParseTypeRec(PATypeHolder &H); - bool ParseStructType(PATypeHolder &H, bool Packed); - bool ParseArrayVectorType(PATypeHolder &H, bool isVector); - bool ParseFunctionType(PATypeHolder &Result); - PATypeHolder HandleUpRefs(const Type *Ty); + bool ParseAnonStructType(Type *&Result, bool Packed); + bool ParseStructBody(SmallVectorImpl &Body); + bool ParseStructDefinition(SMLoc TypeLoc, StringRef Name, + std::pair &Entry, + Type *&ResultTy); + + bool ParseArrayVectorType(Type *&Result, bool isVector); + bool ParseFunctionType(Type *&Result); // Function Semantic Analysis. class PerFunctionState { @@ -278,14 +272,20 @@ bool ConvertValIDToValue(const Type *Ty, ValID &ID, Value *&V, PerFunctionState *PFS); - bool ParseValue(const Type *Ty, Value *&V, PerFunctionState &PFS); + bool ParseValue(const Type *Ty, Value *&V, PerFunctionState *PFS); + bool ParseValue(const Type *Ty, Value *&V, PerFunctionState &PFS) { + return ParseValue(Ty, V, &PFS); + } bool ParseValue(const Type *Ty, Value *&V, LocTy &Loc, PerFunctionState &PFS) { Loc = Lex.getLoc(); - return ParseValue(Ty, V, PFS); + return ParseValue(Ty, V, &PFS); } - bool ParseTypeAndValue(Value *&V, PerFunctionState &PFS); + bool ParseTypeAndValue(Value *&V, PerFunctionState *PFS); + bool ParseTypeAndValue(Value *&V, PerFunctionState &PFS) { + return ParseTypeAndValue(V, &PFS); + } bool ParseTypeAndValue(Value *&V, LocTy &Loc, PerFunctionState &PFS) { Loc = Lex.getLoc(); return ParseTypeAndValue(V, PFS); @@ -321,14 +321,13 @@ // Function Parsing. struct ArgInfo { LocTy Loc; - PATypeHolder Type; + Type *Ty; unsigned Attrs; std::string Name; - ArgInfo(LocTy L, PATypeHolder Ty, unsigned Attr, const std::string &N) - : Loc(L), Type(Ty), Attrs(Attr), Name(N) {} + ArgInfo(LocTy L, Type *ty, unsigned Attr, const std::string &N) + : Loc(L), Ty(ty), Attrs(Attr), Name(N) {} }; - bool ParseArgumentList(std::vector &ArgList, - bool &isVarArg, bool inType); + bool ParseArgumentList(SmallVectorImpl &ArgList, bool &isVarArg); bool ParseFunctionHeader(Function *&Fn, bool isDefine); bool ParseFunctionBody(Function &Fn); bool ParseBasicBlock(PerFunctionState &PFS); Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Sat Jul 9 12:41:24 2011 @@ -31,7 +31,7 @@ if (BufferOwned) delete Buffer; Buffer = 0; - std::vector().swap(TypeList); + std::vector().swap(TypeList); ValueList.clear(); MDValueList.clear(); @@ -352,19 +352,28 @@ return V; } -const Type *BitcodeReader::getTypeByID(unsigned ID, bool isTypeTable) { - // If the TypeID is in range, return it. - if (ID < TypeList.size()) - return TypeList[ID].get(); - if (!isTypeTable) return 0; - - // The type table allows forward references. Push as many Opaque types as - // needed to get up to ID. - while (TypeList.size() <= ID) - TypeList.push_back(OpaqueType::get(Context)); - return TypeList.back().get(); +Type *BitcodeReader::getTypeByID(unsigned ID) { + // The type table size is always specified correctly. + if (ID >= TypeList.size()) + return 0; + + if (Type *Ty = TypeList[ID]) + return Ty; + + // If we have a forward reference, the only possible case is when it is to a + // named struct. Just create a placeholder for now. + return TypeList[ID] = StructType::createNamed(Context, ""); +} + +/// FIXME: Remove in LLVM 3.1, only used by ParseOldTypeTable. +Type *BitcodeReader::getTypeByIDOrNull(unsigned ID) { + if (ID >= TypeList.size()) + TypeList.resize(ID+1); + + return TypeList[ID]; } + //===----------------------------------------------------------------------===// // Functions for parsing blocks from the bitcode file //===----------------------------------------------------------------------===// @@ -471,17 +480,22 @@ } } - bool BitcodeReader::ParseTypeTable() { - if (Stream.EnterSubBlock(bitc::TYPE_BLOCK_ID)) + if (Stream.EnterSubBlock(bitc::TYPE_BLOCK_ID_NEW)) return Error("Malformed block record"); + + return ParseTypeTableBody(); +} +bool BitcodeReader::ParseTypeTableBody() { if (!TypeList.empty()) return Error("Multiple TYPE_BLOCKs found!"); SmallVector Record; unsigned NumRecords = 0; + SmallString<64> TypeName; + // Read all the records for this type table. while (1) { unsigned Code = Stream.ReadCode(); @@ -508,17 +522,15 @@ // Read a record. Record.clear(); - const Type *ResultTy = 0; + Type *ResultTy = 0; switch (Stream.ReadRecord(Code, Record)) { - default: // Default behavior: unknown type. - ResultTy = 0; - break; + default: return Error("unknown type in type table"); case bitc::TYPE_CODE_NUMENTRY: // TYPE_CODE_NUMENTRY: [numentries] // TYPE_CODE_NUMENTRY contains a count of the number of types in the // type list. This allows us to reserve space. if (Record.size() < 1) return Error("Invalid TYPE_CODE_NUMENTRY record"); - TypeList.reserve(Record[0]); + TypeList.resize(Record[0]); continue; case bitc::TYPE_CODE_VOID: // VOID ResultTy = Type::getVoidTy(Context); @@ -541,9 +553,6 @@ case bitc::TYPE_CODE_LABEL: // LABEL ResultTy = Type::getLabelTy(Context); break; - case bitc::TYPE_CODE_OPAQUE: // OPAQUE - ResultTy = 0; - break; case bitc::TYPE_CODE_METADATA: // METADATA ResultTy = Type::getMetadataTy(Context); break; @@ -563,8 +572,9 @@ unsigned AddressSpace = 0; if (Record.size() == 2) AddressSpace = Record[1]; - ResultTy = PointerType::get(getTypeByID(Record[0], true), - AddressSpace); + ResultTy = getTypeByID(Record[0]); + if (ResultTy == 0) return Error("invalid element type in pointer type"); + ResultTy = PointerType::get(ResultTy, AddressSpace); break; } case bitc::TYPE_CODE_FUNCTION: { @@ -573,68 +583,305 @@ if (Record.size() < 3) return Error("Invalid FUNCTION type record"); std::vector ArgTys; - for (unsigned i = 3, e = Record.size(); i != e; ++i) - ArgTys.push_back(getTypeByID(Record[i], true)); + for (unsigned i = 3, e = Record.size(); i != e; ++i) { + if (Type *T = getTypeByID(Record[i])) + ArgTys.push_back(T); + else + break; + } + + ResultTy = getTypeByID(Record[2]); + if (ResultTy == 0 || ArgTys.size() < Record.size()-3) + return Error("invalid type in function type"); - ResultTy = FunctionType::get(getTypeByID(Record[2], true), ArgTys, - Record[0]); + ResultTy = FunctionType::get(ResultTy, ArgTys, Record[0]); break; } - case bitc::TYPE_CODE_STRUCT: { // STRUCT: [ispacked, eltty x N] + case bitc::TYPE_CODE_STRUCT_ANON: { // STRUCT: [ispacked, eltty x N] if (Record.size() < 1) return Error("Invalid STRUCT type record"); - std::vector EltTys; - for (unsigned i = 1, e = Record.size(); i != e; ++i) - EltTys.push_back(getTypeByID(Record[i], true)); + std::vector EltTys; + for (unsigned i = 1, e = Record.size(); i != e; ++i) { + if (Type *T = getTypeByID(Record[i])) + EltTys.push_back(T); + else + break; + } + if (EltTys.size() != Record.size()-1) + return Error("invalid type in struct type"); ResultTy = StructType::get(Context, EltTys, Record[0]); break; } + case bitc::TYPE_CODE_STRUCT_NAME: // STRUCT_NAME: [strchr x N] + if (ConvertToString(Record, 0, TypeName)) + return Error("Invalid STRUCT_NAME record"); + continue; + + case bitc::TYPE_CODE_STRUCT_NAMED: { // STRUCT: [ispacked, eltty x N] + if (Record.size() < 1) + return Error("Invalid STRUCT type record"); + + if (NumRecords >= TypeList.size()) + return Error("invalid TYPE table"); + + // Check to see if this was forward referenced, if so fill in the temp. + StructType *Res = cast_or_null(TypeList[NumRecords]); + if (Res) { + Res->setName(TypeName); + TypeList[NumRecords] = 0; + } else // Otherwise, create a new struct. + Res = StructType::createNamed(Context, TypeName); + TypeName.clear(); + + SmallVector EltTys; + for (unsigned i = 1, e = Record.size(); i != e; ++i) { + if (Type *T = getTypeByID(Record[i])) + EltTys.push_back(T); + else + break; + } + if (EltTys.size() != Record.size()-1) + return Error("invalid STRUCT type record"); + Res->setBody(EltTys, Record[0]); + ResultTy = Res; + break; + } + case bitc::TYPE_CODE_OPAQUE: { // OPAQUE: [] + if (Record.size() != 1) + return Error("Invalid OPAQUE type record"); + + if (NumRecords >= TypeList.size()) + return Error("invalid TYPE table"); + + // Check to see if this was forward referenced, if so fill in the temp. + StructType *Res = cast_or_null(TypeList[NumRecords]); + if (Res) { + Res->setName(TypeName); + TypeList[NumRecords] = 0; + } else // Otherwise, create a new struct with no body. + Res = StructType::createNamed(Context, TypeName); + TypeName.clear(); + ResultTy = Res; + break; + } case bitc::TYPE_CODE_ARRAY: // ARRAY: [numelts, eltty] if (Record.size() < 2) return Error("Invalid ARRAY type record"); - ResultTy = ArrayType::get(getTypeByID(Record[1], true), Record[0]); + if ((ResultTy = getTypeByID(Record[1]))) + ResultTy = ArrayType::get(ResultTy, Record[0]); + else + return Error("Invalid ARRAY type element"); break; case bitc::TYPE_CODE_VECTOR: // VECTOR: [numelts, eltty] if (Record.size() < 2) return Error("Invalid VECTOR type record"); - ResultTy = VectorType::get(getTypeByID(Record[1], true), Record[0]); + if ((ResultTy = getTypeByID(Record[1]))) + ResultTy = VectorType::get(ResultTy, Record[0]); + else + return Error("Invalid ARRAY type element"); break; } - if (NumRecords == TypeList.size()) { - // If this is a new type slot, just append it. - TypeList.push_back(ResultTy ? ResultTy : OpaqueType::get(Context)); - ++NumRecords; - } else if (ResultTy == 0) { - // Otherwise, this was forward referenced, so an opaque type was created, - // but the result type is actually just an opaque. Leave the one we - // created previously. - ++NumRecords; - } else { - // Otherwise, this was forward referenced, so an opaque type was created. - // Resolve the opaque type to the real type now. - assert(NumRecords < TypeList.size() && "Typelist imbalance"); - const OpaqueType *OldTy = cast(TypeList[NumRecords++].get()); + if (NumRecords >= TypeList.size()) + return Error("invalid TYPE table"); + assert(ResultTy && "Didn't read a type?"); + assert(TypeList[NumRecords] == 0 && "Already read type?"); + TypeList[NumRecords++] = ResultTy; + } +} - // Don't directly push the new type on the Tab. Instead we want to replace - // the opaque type we previously inserted with the new concrete value. The - // refinement from the abstract (opaque) type to the new type causes all - // uses of the abstract type to use the concrete type (NewTy). This will - // also cause the opaque type to be deleted. - const_cast(OldTy)->refineAbstractTypeTo(ResultTy); +// FIXME: Remove in LLVM 3.1 +bool BitcodeReader::ParseOldTypeTable() { + if (Stream.EnterSubBlock(bitc::TYPE_BLOCK_ID_OLD)) + return Error("Malformed block record"); - // This should have replaced the old opaque type with the new type in the - // value table... or with a preexisting type that was already in the - // system. Let's just make sure it did. - assert(TypeList[NumRecords-1].get() != OldTy && - "refineAbstractType didn't work!"); + if (!TypeList.empty()) + return Error("Multiple TYPE_BLOCKs found!"); + + + // While horrible, we have no good ordering of types in the bc file. Just + // iteratively parse types out of the bc file in multiple passes until we get + // them all. Do this by saving a cursor for the start of the type block. + BitstreamCursor StartOfTypeBlockCursor(Stream); + + unsigned NumTypesRead = 0; + + SmallVector Record; +RestartScan: + unsigned NextTypeID = 0; + bool ReadAnyTypes = false; + + // Read all the records for this type table. + while (1) { + unsigned Code = Stream.ReadCode(); + if (Code == bitc::END_BLOCK) { + if (NextTypeID != TypeList.size()) + return Error("Invalid type forward reference in TYPE_BLOCK_ID_OLD"); + + // If we haven't read all of the types yet, iterate again. + if (NumTypesRead != TypeList.size()) { + // If we didn't successfully read any types in this pass, then we must + // have an unhandled forward reference. + if (!ReadAnyTypes) + return Error("Obsolete bitcode contains unhandled recursive type"); + + Stream = StartOfTypeBlockCursor; + goto RestartScan; + } + + if (Stream.ReadBlockEnd()) + return Error("Error at end of type table block"); + return false; + } + + if (Code == bitc::ENTER_SUBBLOCK) { + // No known subblocks, always skip them. + Stream.ReadSubBlockID(); + if (Stream.SkipBlock()) + return Error("Malformed block record"); + continue; + } + + if (Code == bitc::DEFINE_ABBREV) { + Stream.ReadAbbrevRecord(); + continue; } + + // Read a record. + Record.clear(); + Type *ResultTy = 0; + switch (Stream.ReadRecord(Code, Record)) { + default: return Error("unknown type in type table"); + case bitc::TYPE_CODE_NUMENTRY: // TYPE_CODE_NUMENTRY: [numentries] + // TYPE_CODE_NUMENTRY contains a count of the number of types in the + // type list. This allows us to reserve space. + if (Record.size() < 1) + return Error("Invalid TYPE_CODE_NUMENTRY record"); + TypeList.resize(Record[0]); + continue; + case bitc::TYPE_CODE_VOID: // VOID + ResultTy = Type::getVoidTy(Context); + break; + case bitc::TYPE_CODE_FLOAT: // FLOAT + ResultTy = Type::getFloatTy(Context); + break; + case bitc::TYPE_CODE_DOUBLE: // DOUBLE + ResultTy = Type::getDoubleTy(Context); + break; + case bitc::TYPE_CODE_X86_FP80: // X86_FP80 + ResultTy = Type::getX86_FP80Ty(Context); + break; + case bitc::TYPE_CODE_FP128: // FP128 + ResultTy = Type::getFP128Ty(Context); + break; + case bitc::TYPE_CODE_PPC_FP128: // PPC_FP128 + ResultTy = Type::getPPC_FP128Ty(Context); + break; + case bitc::TYPE_CODE_LABEL: // LABEL + ResultTy = Type::getLabelTy(Context); + break; + case bitc::TYPE_CODE_METADATA: // METADATA + ResultTy = Type::getMetadataTy(Context); + break; + case bitc::TYPE_CODE_X86_MMX: // X86_MMX + ResultTy = Type::getX86_MMXTy(Context); + break; + case bitc::TYPE_CODE_INTEGER: // INTEGER: [width] + if (Record.size() < 1) + return Error("Invalid Integer type record"); + ResultTy = IntegerType::get(Context, Record[0]); + break; + case bitc::TYPE_CODE_OPAQUE: // OPAQUE + if (NextTypeID < TypeList.size() && TypeList[NextTypeID] == 0) + ResultTy = StructType::createNamed(Context, ""); + break; + case bitc::TYPE_CODE_STRUCT_OLD: {// STRUCT_OLD + if (NextTypeID >= TypeList.size()) break; + // If we already read it, don't reprocess. + if (TypeList[NextTypeID] && + !cast(TypeList[NextTypeID])->isOpaque()) + break; + + // Set a type. + if (TypeList[NextTypeID] == 0) + TypeList[NextTypeID] = StructType::createNamed(Context, ""); + + std::vector EltTys; + for (unsigned i = 1, e = Record.size(); i != e; ++i) { + if (Type *Elt = getTypeByIDOrNull(Record[i])) + EltTys.push_back(Elt); + else + break; + } + + if (EltTys.size() != Record.size()-1) + break; // Not all elements are ready. + + cast(TypeList[NextTypeID])->setBody(EltTys, Record[0]); + ResultTy = TypeList[NextTypeID]; + TypeList[NextTypeID] = 0; + break; + } + case bitc::TYPE_CODE_POINTER: { // POINTER: [pointee type] or + // [pointee type, address space] + if (Record.size() < 1) + return Error("Invalid POINTER type record"); + unsigned AddressSpace = 0; + if (Record.size() == 2) + AddressSpace = Record[1]; + if ((ResultTy = getTypeByIDOrNull(Record[0]))) + ResultTy = PointerType::get(ResultTy, AddressSpace); + break; + } + case bitc::TYPE_CODE_FUNCTION: { + // FIXME: attrid is dead, remove it in LLVM 3.0 + // FUNCTION: [vararg, attrid, retty, paramty x N] + if (Record.size() < 3) + return Error("Invalid FUNCTION type record"); + std::vector ArgTys; + for (unsigned i = 3, e = Record.size(); i != e; ++i) { + if (Type *Elt = getTypeByIDOrNull(Record[i])) + ArgTys.push_back(Elt); + else + break; + } + if (ArgTys.size()+3 != Record.size()) + break; // Something was null. + if ((ResultTy = getTypeByIDOrNull(Record[2]))) + ResultTy = FunctionType::get(ResultTy, ArgTys, Record[0]); + break; + } + case bitc::TYPE_CODE_ARRAY: // ARRAY: [numelts, eltty] + if (Record.size() < 2) + return Error("Invalid ARRAY type record"); + if ((ResultTy = getTypeByIDOrNull(Record[1]))) + ResultTy = ArrayType::get(ResultTy, Record[0]); + break; + case bitc::TYPE_CODE_VECTOR: // VECTOR: [numelts, eltty] + if (Record.size() < 2) + return Error("Invalid VECTOR type record"); + if ((ResultTy = getTypeByIDOrNull(Record[1]))) + ResultTy = VectorType::get(ResultTy, Record[0]); + break; + } + + if (NextTypeID >= TypeList.size()) + return Error("invalid TYPE table"); + + if (ResultTy && TypeList[NextTypeID] == 0) { + ++NumTypesRead; + ReadAnyTypes = true; + + TypeList[NextTypeID] = ResultTy; + } + + ++NextTypeID; } } -bool BitcodeReader::ParseTypeSymbolTable() { - if (Stream.EnterSubBlock(bitc::TYPE_SYMTAB_BLOCK_ID)) +bool BitcodeReader::ParseOldTypeSymbolTable() { + if (Stream.EnterSubBlock(bitc::TYPE_SYMTAB_BLOCK_ID_OLD)) return Error("Malformed block record"); SmallVector Record; @@ -674,7 +921,10 @@ if (TypeID >= TypeList.size()) return Error("Invalid Type ID in TST_ENTRY record"); - TheModule->addTypeName(TypeName, TypeList[TypeID].get()); + // Only apply the type name to a struct type with no name. + if (StructType *STy = dyn_cast(TypeList[TypeID])) + if (!STy->isAnonymous() && !STy->hasName()) + STy->setName(TypeName); TypeName.clear(); break; } @@ -1310,12 +1560,16 @@ if (ParseAttributeBlock()) return true; break; - case bitc::TYPE_BLOCK_ID: + case bitc::TYPE_BLOCK_ID_NEW: if (ParseTypeTable()) return true; break; - case bitc::TYPE_SYMTAB_BLOCK_ID: - if (ParseTypeSymbolTable()) + case bitc::TYPE_BLOCK_ID_OLD: + if (ParseOldTypeTable()) + return true; + break; + case bitc::TYPE_SYMTAB_BLOCK_ID_OLD: + if (ParseOldTypeSymbolTable()) return true; break; case bitc::VALUE_SYMTAB_BLOCK_ID: @@ -2307,7 +2561,7 @@ SmallVector Args; // Read the fixed params. for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) { - if (FTy->getParamType(i)->getTypeID()==Type::LabelTyID) + if (FTy->getParamType(i)->isLabelTy()) Args.push_back(getBasicBlock(Record[OpNum])); else Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i))); Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Sat Jul 9 12:41:24 2011 @@ -131,7 +131,7 @@ const char *ErrorString; - std::vector TypeList; + std::vector TypeList; BitcodeReaderValueList ValueList; BitcodeReaderMDValueList MDValueList; SmallVector InstructionList; @@ -210,7 +210,8 @@ /// @returns true if an error occurred. bool ParseTriple(std::string &Triple); private: - const Type *getTypeByID(unsigned ID, bool isTypeTable = false); + Type *getTypeByID(unsigned ID); + Type *getTypeByIDOrNull(unsigned ID); Value *getFnValueByID(unsigned ID, const Type *Ty) { if (Ty && Ty->isMetadataTy()) return MDValueList.getValueFwdRef(ID); @@ -258,7 +259,10 @@ bool ParseModule(); bool ParseAttributeBlock(); bool ParseTypeTable(); - bool ParseTypeSymbolTable(); + bool ParseOldTypeTable(); // FIXME: Remove in LLVM 3.1 + bool ParseTypeTableBody(); + + bool ParseOldTypeSymbolTable(); // FIXME: Remove in LLVM 3.1 bool ParseValueSymbolTable(); bool ParseConstants(); bool RememberAndSkipFunctionBody(); Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Sat Jul 9 12:41:24 2011 @@ -21,7 +21,6 @@ #include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Operator.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/ValueSymbolTable.h" #include "llvm/ADT/Triple.h" #include "llvm/Support/ErrorHandling.h" @@ -29,6 +28,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Program.h" #include +#include using namespace llvm; /// These are manifest constants used by the bitcode writer. They do not need to @@ -101,13 +101,16 @@ } } -static void WriteStringRecord(unsigned Code, const std::string &Str, +static void WriteStringRecord(unsigned Code, StringRef Str, unsigned AbbrevToUse, BitstreamWriter &Stream) { SmallVector Vals; // Code: [strchar x N] - for (unsigned i = 0, e = Str.size(); i != e; ++i) + for (unsigned i = 0, e = Str.size(); i != e; ++i) { + if (AbbrevToUse && !BitCodeAbbrevOp::isChar6(Str[i])) + AbbrevToUse = 0; Vals.push_back(Str[i]); + } // Emit the finished record. Stream.EmitRecord(Code, Vals, AbbrevToUse); @@ -151,7 +154,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) { const ValueEnumerator::TypeList &TypeList = VE.getTypes(); - Stream.EnterSubblock(bitc::TYPE_BLOCK_ID, 4 /*count from # abbrevs */); + Stream.EnterSubblock(bitc::TYPE_BLOCK_ID_NEW, 4 /*count from # abbrevs */); SmallVector TypeVals; // Abbrev for TYPE_CODE_POINTER. @@ -172,15 +175,32 @@ Log2_32_Ceil(VE.getTypes().size()+1))); unsigned FunctionAbbrev = Stream.EmitAbbrev(Abbv); - // Abbrev for TYPE_CODE_STRUCT. + // Abbrev for TYPE_CODE_STRUCT_ANON. + Abbv = new BitCodeAbbrev(); + Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT_ANON)); + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // ispacked + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, + Log2_32_Ceil(VE.getTypes().size()+1))); + unsigned StructAnonAbbrev = Stream.EmitAbbrev(Abbv); + + // Abbrev for TYPE_CODE_STRUCT_NAME. + Abbv = new BitCodeAbbrev(); + Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT_NAME)); + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6)); + unsigned StructNameAbbrev = Stream.EmitAbbrev(Abbv); + + // Abbrev for TYPE_CODE_STRUCT_NAMED. Abbv = new BitCodeAbbrev(); - Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT)); + Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT_NAMED)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // ispacked Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, Log2_32_Ceil(VE.getTypes().size()+1))); - unsigned StructAbbrev = Stream.EmitAbbrev(Abbv); + unsigned StructNamedAbbrev = Stream.EmitAbbrev(Abbv); + // Abbrev for TYPE_CODE_ARRAY. Abbv = new BitCodeAbbrev(); Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_ARRAY)); @@ -202,16 +222,15 @@ switch (T->getTypeID()) { default: llvm_unreachable("Unknown type!"); - case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break; - case Type::FloatTyID: Code = bitc::TYPE_CODE_FLOAT; break; - case Type::DoubleTyID: Code = bitc::TYPE_CODE_DOUBLE; break; - case Type::X86_FP80TyID: Code = bitc::TYPE_CODE_X86_FP80; break; - case Type::FP128TyID: Code = bitc::TYPE_CODE_FP128; break; + case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break; + case Type::FloatTyID: Code = bitc::TYPE_CODE_FLOAT; break; + case Type::DoubleTyID: Code = bitc::TYPE_CODE_DOUBLE; break; + case Type::X86_FP80TyID: Code = bitc::TYPE_CODE_X86_FP80; break; + case Type::FP128TyID: Code = bitc::TYPE_CODE_FP128; break; case Type::PPC_FP128TyID: Code = bitc::TYPE_CODE_PPC_FP128; break; - case Type::LabelTyID: Code = bitc::TYPE_CODE_LABEL; break; - case Type::OpaqueTyID: Code = bitc::TYPE_CODE_OPAQUE; break; - case Type::MetadataTyID: Code = bitc::TYPE_CODE_METADATA; break; - case Type::X86_MMXTyID: Code = bitc::TYPE_CODE_X86_MMX; break; + case Type::LabelTyID: Code = bitc::TYPE_CODE_LABEL; break; + case Type::MetadataTyID: Code = bitc::TYPE_CODE_METADATA; break; + case Type::X86_MMXTyID: Code = bitc::TYPE_CODE_X86_MMX; break; case Type::IntegerTyID: // INTEGER: [width] Code = bitc::TYPE_CODE_INTEGER; @@ -242,13 +261,28 @@ case Type::StructTyID: { const StructType *ST = cast(T); // STRUCT: [ispacked, eltty x N] - Code = bitc::TYPE_CODE_STRUCT; TypeVals.push_back(ST->isPacked()); // Output all of the element types. for (StructType::element_iterator I = ST->element_begin(), E = ST->element_end(); I != E; ++I) TypeVals.push_back(VE.getTypeID(*I)); - AbbrevToUse = StructAbbrev; + + if (ST->isAnonymous()) { + Code = bitc::TYPE_CODE_STRUCT_ANON; + AbbrevToUse = StructAnonAbbrev; + } else { + if (ST->isOpaque()) { + Code = bitc::TYPE_CODE_OPAQUE; + } else { + Code = bitc::TYPE_CODE_STRUCT_NAMED; + AbbrevToUse = StructNamedAbbrev; + } + + // Emit the name if it is present. + if (!ST->getName().empty()) + WriteStringRecord(bitc::TYPE_CODE_STRUCT_NAME, ST->getName(), + StructNameAbbrev, Stream); + } break; } case Type::ArrayTyID: { @@ -1278,46 +1312,6 @@ Stream.ExitBlock(); } -/// WriteTypeSymbolTable - Emit a block for the specified type symtab. -static void WriteTypeSymbolTable(const TypeSymbolTable &TST, - const ValueEnumerator &VE, - BitstreamWriter &Stream) { - if (TST.empty()) return; - - Stream.EnterSubblock(bitc::TYPE_SYMTAB_BLOCK_ID, 3); - - // 7-bit fixed width VST_CODE_ENTRY strings. - BitCodeAbbrev *Abbv = new BitCodeAbbrev(); - Abbv->Add(BitCodeAbbrevOp(bitc::VST_CODE_ENTRY)); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, - Log2_32_Ceil(VE.getTypes().size()+1))); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7)); - unsigned V7Abbrev = Stream.EmitAbbrev(Abbv); - - SmallVector NameVals; - - for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end(); - TI != TE; ++TI) { - // TST_ENTRY: [typeid, namechar x N] - NameVals.push_back(VE.getTypeID(TI->second)); - - const std::string &Str = TI->first; - bool is7Bit = true; - for (unsigned i = 0, e = Str.size(); i != e; ++i) { - NameVals.push_back((unsigned char)Str[i]); - if (Str[i] & 128) - is7Bit = false; - } - - // Emit the finished record. - Stream.EmitRecord(bitc::VST_CODE_ENTRY, NameVals, is7Bit ? V7Abbrev : 0); - NameVals.clear(); - } - - Stream.ExitBlock(); -} - // Emit blockinfo, which defines the standard abbreviations etc. static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) { // We only want to emit block info records for blocks that have multiple @@ -1521,9 +1515,6 @@ // Emit metadata. WriteModuleMetadataStore(M, Stream); - // Emit the type symbol table information. - WriteTypeSymbolTable(M->getTypeSymbolTable(), VE, Stream); - // Emit names for globals/functions etc. WriteValueSymbolTable(M->getValueSymbolTable(), VE, Stream); Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Sat Jul 9 12:41:24 2011 @@ -17,7 +17,6 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/ValueSymbolTable.h" #include "llvm/Instructions.h" #include @@ -59,9 +58,6 @@ I != E; ++I) EnumerateValue(I->getAliasee()); - // Enumerate types used by the type symbol table. - EnumerateTypeSymbolTable(M->getTypeSymbolTable()); - // Insert constants and metadata that are named at module level into the slot // pool so that the module symbol table can refer to them... EnumerateValueSymbolTable(M->getValueSymbolTable()); @@ -109,78 +105,12 @@ // Optimize constant ordering. OptimizeConstants(FirstConstant, Values.size()); - - OptimizeTypes(); - - // Now that we rearranged the type table, rebuild TypeMap. - for (unsigned i = 0, e = Types.size(); i != e; ++i) - TypeMap[Types[i]] = i+1; } -struct TypeAndDeps { - const Type *Ty; - unsigned NumDeps; -}; - -static int CompareByDeps(const void *a, const void *b) { - const TypeAndDeps &ta = *(const TypeAndDeps*) a; - const TypeAndDeps &tb = *(const TypeAndDeps*) b; - return ta.NumDeps - tb.NumDeps; -} - -static void VisitType(const Type *Ty, SmallPtrSet &Visited, - std::vector &Out) { - if (Visited.count(Ty)) - return; - - Visited.insert(Ty); - - for (Type::subtype_iterator I2 = Ty->subtype_begin(), - E2 = Ty->subtype_end(); I2 != E2; ++I2) { - const Type *InnerType = I2->get(); - VisitType(InnerType, Visited, Out); - } - - Out.push_back(Ty); -} - -void ValueEnumerator::OptimizeTypes(void) { - // If the types form a DAG, this will compute a topological sort and - // no forward references will be needed when reading them in. - // If there are cycles, this is a simple but reasonable heuristic for - // the minimum feedback arc set problem. - const unsigned NumTypes = Types.size(); - std::vector TypeDeps; - TypeDeps.resize(NumTypes); - - for (unsigned I = 0; I < NumTypes; ++I) { - const Type *Ty = Types[I]; - TypeDeps[I].Ty = Ty; - TypeDeps[I].NumDeps = 0; - } - - for (unsigned I = 0; I < NumTypes; ++I) { - const Type *Ty = TypeDeps[I].Ty; - for (Type::subtype_iterator I2 = Ty->subtype_begin(), - E2 = Ty->subtype_end(); I2 != E2; ++I2) { - const Type *InnerType = I2->get(); - unsigned InnerIndex = TypeMap.lookup(InnerType) - 1; - TypeDeps[InnerIndex].NumDeps++; - } - } - array_pod_sort(TypeDeps.begin(), TypeDeps.end(), CompareByDeps); - - SmallPtrSet Visited; - Types.clear(); - Types.reserve(NumTypes); - for (unsigned I = 0; I < NumTypes; ++I) { - VisitType(TypeDeps[I].Ty, Visited, Types); - } -} unsigned ValueEnumerator::getInstructionID(const Instruction *Inst) const { InstructionMapType::const_iterator I = InstructionMap.find(Inst); - assert (I != InstructionMap.end() && "Instruction is not mapped!"); + assert(I != InstructionMap.end() && "Instruction is not mapped!"); return I->second; } @@ -235,14 +165,6 @@ } -/// EnumerateTypeSymbolTable - Insert all of the types in the specified symbol -/// table. -void ValueEnumerator::EnumerateTypeSymbolTable(const TypeSymbolTable &TST) { - for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end(); - TI != TE; ++TI) - EnumerateType(TI->second); -} - /// EnumerateValueSymbolTable - Insert all of the values in the specified symbol /// table into the values table. void ValueEnumerator::EnumerateValueSymbolTable(const ValueSymbolTable &VST) { @@ -394,20 +316,40 @@ void ValueEnumerator::EnumerateType(const Type *Ty) { - unsigned &TypeID = TypeMap[Ty]; + unsigned *TypeID = &TypeMap[Ty]; // We've already seen this type. - if (TypeID) + if (*TypeID) return; - // First time we saw this type, add it. - Types.push_back(Ty); - TypeID = Types.size(); - - // Enumerate subtypes. + // If it is a non-anonymous struct, mark the type as being visited so that we + // don't recursively visit it. This is safe because we allow forward + // references of these in the bitcode reader. + if (const StructType *STy = dyn_cast(Ty)) + if (!STy->isAnonymous()) + *TypeID = ~0U; + + // Enumerate all of the subtypes before we enumerate this type. This ensures + // that the type will be enumerated in an order that can be directly built. for (Type::subtype_iterator I = Ty->subtype_begin(), E = Ty->subtype_end(); I != E; ++I) EnumerateType(*I); + + // Refresh the TypeID pointer in case the table rehashed. + TypeID = &TypeMap[Ty]; + + // Check to see if we got the pointer another way. This can happen when + // enumerating recursive types that hit the base case deeper than they start. + // + // If this is actually a struct that we are treating as forward ref'able, + // then emit the definition now that all of its contents are available. + if (*TypeID && *TypeID != ~0U) + return; + + // Add this type now that its contents are all happily enumerated. + Types.push_back(Ty); + + *TypeID = Types.size(); } // Enumerate the types for the specified value. If the value is a constant, Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Sat Jul 9 12:41:24 2011 @@ -30,7 +30,6 @@ class MDNode; class NamedMDNode; class AttrListPtr; -class TypeSymbolTable; class ValueSymbolTable; class MDSymbolTable; @@ -135,7 +134,6 @@ private: void OptimizeConstants(unsigned CstStart, unsigned CstEnd); - void OptimizeTypes(); void EnumerateMDNodeOperands(const MDNode *N); void EnumerateMetadata(const Value *MD); @@ -146,7 +144,6 @@ void EnumerateOperandType(const Value *V); void EnumerateAttributes(const AttrListPtr &PAL); - void EnumerateTypeSymbolTable(const TypeSymbolTable &ST); void EnumerateValueSymbolTable(const ValueSymbolTable &ST); void EnumerateNamedMetadata(const Module *M); }; Modified: llvm/trunk/lib/CodeGen/ShadowStackGC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShadowStackGC.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ShadowStackGC.cpp (original) +++ llvm/trunk/lib/CodeGen/ShadowStackGC.cpp Sat Jul 9 12:41:24 2011 @@ -45,7 +45,8 @@ /// StackEntryTy - Abstract type of a link in the shadow stack. /// - const StructType *StackEntryTy; + StructType *StackEntryTy; + StructType *FrameMapTy; /// Roots - GC roots in the current function. Each is a pair of the /// intrinsic call and its corresponding alloca. @@ -211,18 +212,14 @@ }; Constant *DescriptorElts[] = { - ConstantStruct::get(StructType::get(Int32Ty, Int32Ty, NULL), BaseElts), + ConstantStruct::get(FrameMapTy, BaseElts), ConstantArray::get(ArrayType::get(VoidPtr, NumMeta), Metadata) }; - Constant *FrameMap = - ConstantStruct::get(StructType::get(DescriptorElts[0]->getType(), - DescriptorElts[1]->getType(), NULL), - DescriptorElts); - - std::string TypeName("gc_map."); - TypeName += utostr(NumMeta); - F.getParent()->addTypeName(TypeName, FrameMap->getType()); + Type *EltTys[] = { DescriptorElts[0]->getType(),DescriptorElts[1]->getType()}; + StructType *STy = StructType::createNamed("gc_map."+utostr(NumMeta), EltTys); + + Constant *FrameMap = ConstantStruct::get(STy, DescriptorElts); // FIXME: Is this actually dangerous as WritingAnLLVMPass.html claims? Seems // that, short of multithreaded LLVM, it should be safe; all that is @@ -250,17 +247,12 @@ const Type* ShadowStackGC::GetConcreteStackEntryType(Function &F) { // doInitialization creates the generic version of this type. - std::vector EltTys; + std::vector EltTys; EltTys.push_back(StackEntryTy); for (size_t I = 0; I != Roots.size(); I++) EltTys.push_back(Roots[I].second->getAllocatedType()); - Type *Ty = StructType::get(F.getContext(), EltTys); - - std::string TypeName("gc_stackentry."); - TypeName += F.getName(); - F.getParent()->addTypeName(TypeName, Ty); - - return Ty; + + return StructType::createNamed("gc_stackentry."+F.getName().str(), EltTys); } /// doInitialization - If this module uses the GC intrinsics, find them now. If @@ -271,13 +263,12 @@ // int32_t NumMeta; // Number of metadata descriptors. May be < NumRoots. // void *Meta[]; // May be absent for roots without metadata. // }; - std::vector EltTys; + std::vector EltTys; // 32 bits is ok up to a 32GB stack frame. :) EltTys.push_back(Type::getInt32Ty(M.getContext())); // Specifies length of variable length array. EltTys.push_back(Type::getInt32Ty(M.getContext())); - StructType *FrameMapTy = StructType::get(M.getContext(), EltTys); - M.addTypeName("gc_map", FrameMapTy); + FrameMapTy = StructType::createNamed("gc_map", EltTys); PointerType *FrameMapPtrTy = PointerType::getUnqual(FrameMapTy); // struct StackEntry { @@ -285,18 +276,14 @@ // FrameMap *Map; // Pointer to constant FrameMap. // void *Roots[]; // Stack roots (in-place array, so we pretend). // }; - OpaqueType *RecursiveTy = OpaqueType::get(M.getContext()); - + + StackEntryTy = StructType::createNamed(M.getContext(), "gc_stackentry"); + EltTys.clear(); - EltTys.push_back(PointerType::getUnqual(RecursiveTy)); + EltTys.push_back(PointerType::getUnqual(StackEntryTy)); EltTys.push_back(FrameMapPtrTy); - PATypeHolder LinkTyH = StructType::get(M.getContext(), EltTys); - - RecursiveTy->refineAbstractTypeTo(LinkTyH.get()); - StackEntryTy = cast(LinkTyH.get()); + StackEntryTy->setBody(EltTys); const PointerType *StackEntryPtrTy = PointerType::getUnqual(StackEntryTy); - M.addTypeName("gc_stackentry", LinkTyH.get()); // FIXME: Is this safe from - // a FunctionPass? // Get the root chain if it already exists. Head = M.getGlobalVariable("llvm_gc_root_chain"); @@ -403,7 +390,7 @@ Instruction *CurrentHead = AtEntry.CreateLoad(Head, "gc_currhead"); Instruction *EntryMapPtr = CreateGEP(Context, AtEntry, StackEntry, 0,1,"gc_frame.map"); - AtEntry.CreateStore(FrameMap, EntryMapPtr); + AtEntry.CreateStore(FrameMap, EntryMapPtr); // After all the allocas... for (unsigned I = 0, E = Roots.size(); I != E; ++I) { Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Sat Jul 9 12:41:24 2011 @@ -78,7 +78,6 @@ case Type::FunctionTyID:return 'M'; case Type::StructTyID: return 'T'; case Type::ArrayTyID: return 'A'; - case Type::OpaqueTyID: return 'O'; default: return 'U'; } } Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Sat Jul 9 12:41:24 2011 @@ -9,337 +9,404 @@ // // This file implements the LLVM module linker. // -// Specifically, this: -// * Merges global variables between the two modules -// * Uninit + Uninit = Init, Init + Uninit = Init, Init + Init = Error if != -// * Merges functions between two modules -// //===----------------------------------------------------------------------===// #include "llvm/Linker.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/LLVMContext.h" #include "llvm/Module.h" -#include "llvm/TypeSymbolTable.h" -#include "llvm/ValueSymbolTable.h" -#include "llvm/Instructions.h" -#include "llvm/Assembly/Writer.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Path.h" #include "llvm/Transforms/Utils/ValueMapper.h" -#include "llvm/ADT/DenseMap.h" using namespace llvm; -// Error - Simple wrapper function to conditionally assign to E and return true. -// This just makes error return conditions a little bit simpler... -static inline bool Error(std::string *E, const Twine &Message) { - if (E) *E = Message.str(); - return true; -} - -// Function: ResolveTypes() -// -// Description: -// Attempt to link the two specified types together. -// -// Inputs: -// DestTy - The type to which we wish to resolve. -// SrcTy - The original type which we want to resolve. -// -// Outputs: -// DestST - The symbol table in which the new type should be placed. -// -// Return value: -// true - There is an error and the types cannot yet be linked. -// false - No errors. -// -static bool ResolveTypes(const Type *DestTy, const Type *SrcTy) { - if (DestTy == SrcTy) return false; // If already equal, noop - assert(DestTy && SrcTy && "Can't handle null types"); - - if (const OpaqueType *OT = dyn_cast(DestTy)) { - // Type _is_ in module, just opaque... - const_cast(OT)->refineAbstractTypeTo(SrcTy); - } else if (const OpaqueType *OT = dyn_cast(SrcTy)) { - const_cast(OT)->refineAbstractTypeTo(DestTy); - } else { - return true; // Cannot link types... not-equal and neither is opaque. - } - return false; -} +//===----------------------------------------------------------------------===// +// TypeMap implementation. +//===----------------------------------------------------------------------===// -/// LinkerTypeMap - This implements a map of types that is stable -/// even if types are resolved/refined to other types. This is not a general -/// purpose map, it is specific to the linker's use. namespace { -class LinkerTypeMap : public AbstractTypeUser { - typedef DenseMap TheMapTy; - TheMapTy TheMap; - - LinkerTypeMap(const LinkerTypeMap&); // DO NOT IMPLEMENT - void operator=(const LinkerTypeMap&); // DO NOT IMPLEMENT +class TypeMapTy : public ValueMapTypeRemapper { + /// MappedTypes - This is a mapping from a source type to a destination type + /// to use. + DenseMap MappedTypes; + + /// SpeculativeTypes - When checking to see if two subgraphs are isomorphic, + /// we speculatively add types to MappedTypes, but keep track of them here in + /// case we need to roll back. + SmallVector SpeculativeTypes; + + /// DefinitionsToResolve - This is a list of non-opaque structs in the source + /// module that are mapped to an opaque struct in the destination module. + SmallVector DefinitionsToResolve; public: - LinkerTypeMap() {} - ~LinkerTypeMap() { - for (DenseMap::iterator I = TheMap.begin(), - E = TheMap.end(); I != E; ++I) - I->first->removeAbstractTypeUser(this); - } - - /// lookup - Return the value for the specified type or null if it doesn't - /// exist. - const Type *lookup(const Type *Ty) const { - TheMapTy::const_iterator I = TheMap.find(Ty); - if (I != TheMap.end()) return I->second; - return 0; - } - - /// insert - This returns true if the pointer was new to the set, false if it - /// was already in the set. - bool insert(const Type *Src, const Type *Dst) { - if (!TheMap.insert(std::make_pair(Src, PATypeHolder(Dst))).second) - return false; // Already in map. - if (Src->isAbstract()) - Src->addAbstractTypeUser(this); - return true; - } - -protected: - /// refineAbstractType - The callback method invoked when an abstract type is - /// resolved to another type. An object must override this method to update - /// its internal state to reference NewType instead of OldType. - /// - virtual void refineAbstractType(const DerivedType *OldTy, - const Type *NewTy) { - TheMapTy::iterator I = TheMap.find(OldTy); - const Type *DstTy = I->second; - - TheMap.erase(I); - if (OldTy->isAbstract()) - OldTy->removeAbstractTypeUser(this); - - // Don't reinsert into the map if the key is concrete now. - if (NewTy->isAbstract()) - insert(NewTy, DstTy); - } - - /// The other case which AbstractTypeUsers must be aware of is when a type - /// makes the transition from being abstract (where it has clients on it's - /// AbstractTypeUsers list) to concrete (where it does not). This method - /// notifies ATU's when this occurs for a type. - virtual void typeBecameConcrete(const DerivedType *AbsTy) { - TheMap.erase(AbsTy); - AbsTy->removeAbstractTypeUser(this); - } - - // for debugging... - virtual void dump() const { - dbgs() << "AbstractTypeSet!\n"; + + /// addTypeMapping - Indicate that the specified type in the destination + /// module is conceptually equivalent to the specified type in the source + /// module. + void addTypeMapping(Type *DstTy, Type *SrcTy); + + /// linkDefinedTypeBodies - Produce a body for an opaque type in the dest + /// module from a type definition in the source module. + void linkDefinedTypeBodies(); + + /// get - Return the mapped type to use for the specified input type from the + /// source module. + Type *get(Type *SrcTy); + + FunctionType *get(FunctionType *T) {return cast(get((Type*)T));} + +private: + Type *getImpl(Type *T); + /// remapType - Implement the ValueMapTypeRemapper interface. + Type *remapType(Type *SrcTy) { + return get(SrcTy); } + + bool areTypesIsomorphic(Type *DstTy, Type *SrcTy); }; } - -// RecursiveResolveTypes - This is just like ResolveTypes, except that it -// recurses down into derived types, merging the used types if the parent types -// are compatible. -static bool RecursiveResolveTypesI(const Type *DstTy, const Type *SrcTy, - LinkerTypeMap &Pointers) { - if (DstTy == SrcTy) return false; // If already equal, noop - - // If we found our opaque type, resolve it now! - if (DstTy->isOpaqueTy() || SrcTy->isOpaqueTy()) - return ResolveTypes(DstTy, SrcTy); - - // Two types cannot be resolved together if they are of different primitive - // type. For example, we cannot resolve an int to a float. - if (DstTy->getTypeID() != SrcTy->getTypeID()) return true; - - // If neither type is abstract, then they really are just different types. - if (!DstTy->isAbstract() && !SrcTy->isAbstract()) +void TypeMapTy::addTypeMapping(Type *DstTy, Type *SrcTy) { + Type *&Entry = MappedTypes[SrcTy]; + if (Entry) return; + + if (DstTy == SrcTy) { + Entry = DstTy; + return; + } + + // Check to see if these types are recursively isomorphic and establish a + // mapping between them if so. + if (!areTypesIsomorphic(DstTy, SrcTy)) { + // Oops, they aren't isomorphic. Just discard this request by rolling out + // any speculative mappings we've established. + for (unsigned i = 0, e = SpeculativeTypes.size(); i != e; ++i) + MappedTypes.erase(SpeculativeTypes[i]); + } + SpeculativeTypes.clear(); +} + +/// areTypesIsomorphic - Recursively walk this pair of types, returning true +/// if they are isomorphic, false if they are not. +bool TypeMapTy::areTypesIsomorphic(Type *DstTy, Type *SrcTy) { + // Two types with differing kinds are clearly not isomorphic. + if (DstTy->getTypeID() != SrcTy->getTypeID()) return false; + + // If we have an entry in the MappedTypes table, then we have our answer. + Type *&Entry = MappedTypes[SrcTy]; + if (Entry) + return Entry == DstTy; + + // Two identical types are clearly isomorphic. Remember this + // non-speculatively. + if (DstTy == SrcTy) { + Entry = DstTy; return true; + } + + // Okay, we have two types with identical kinds that we haven't seen before. - // Otherwise, resolve the used type used by this derived type... - switch (DstTy->getTypeID()) { - default: - return true; - case Type::FunctionTyID: { - const FunctionType *DstFT = cast(DstTy); - const FunctionType *SrcFT = cast(SrcTy); - if (DstFT->isVarArg() != SrcFT->isVarArg() || - DstFT->getNumContainedTypes() != SrcFT->getNumContainedTypes()) + // If this is an opaque struct type, special case it. + if (StructType *SSTy = dyn_cast(SrcTy)) { + // Mapping an opaque type to any struct, just keep the dest struct. + if (SSTy->isOpaque()) { + Entry = DstTy; + SpeculativeTypes.push_back(SrcTy); return true; - - // Use TypeHolder's so recursive resolution won't break us. - PATypeHolder ST(SrcFT), DT(DstFT); - for (unsigned i = 0, e = DstFT->getNumContainedTypes(); i != e; ++i) { - const Type *SE = ST->getContainedType(i), *DE = DT->getContainedType(i); - if (SE != DE && RecursiveResolveTypesI(DE, SE, Pointers)) - return true; } - return false; - } - case Type::StructTyID: { - const StructType *DstST = cast(DstTy); - const StructType *SrcST = cast(SrcTy); - if (DstST->getNumContainedTypes() != SrcST->getNumContainedTypes()) - return true; - PATypeHolder ST(SrcST), DT(DstST); - for (unsigned i = 0, e = DstST->getNumContainedTypes(); i != e; ++i) { - const Type *SE = ST->getContainedType(i), *DE = DT->getContainedType(i); - if (SE != DE && RecursiveResolveTypesI(DE, SE, Pointers)) - return true; + // Mapping a non-opaque source type to an opaque dest. Keep the dest, but + // fill it in later. This doesn't need to be speculative. + if (cast(DstTy)->isOpaque()) { + Entry = DstTy; + DefinitionsToResolve.push_back(SSTy); + return true; } - return false; } - case Type::ArrayTyID: { - const ArrayType *DAT = cast(DstTy); - const ArrayType *SAT = cast(SrcTy); - if (DAT->getNumElements() != SAT->getNumElements()) return true; - return RecursiveResolveTypesI(DAT->getElementType(), SAT->getElementType(), - Pointers); - } - case Type::VectorTyID: { - const VectorType *DVT = cast(DstTy); - const VectorType *SVT = cast(SrcTy); - if (DVT->getNumElements() != SVT->getNumElements()) return true; - return RecursiveResolveTypesI(DVT->getElementType(), SVT->getElementType(), - Pointers); - } - case Type::PointerTyID: { - const PointerType *DstPT = cast(DstTy); - const PointerType *SrcPT = cast(SrcTy); - - if (DstPT->getAddressSpace() != SrcPT->getAddressSpace()) - return true; + + // If the number of subtypes disagree between the two types, then we fail. + if (SrcTy->getNumContainedTypes() != DstTy->getNumContainedTypes()) + return false; + + // Fail if any of the extra properties (e.g. array size) of the type disagree. + if (isa(DstTy)) + return false; // bitwidth disagrees. + if (PointerType *PT = dyn_cast(DstTy)) { + if (PT->getAddressSpace() != cast(SrcTy)->getAddressSpace()) + return false; + } else if (FunctionType *FT = dyn_cast(DstTy)) { + if (FT->isVarArg() != cast(SrcTy)->isVarArg()) + return false; + } else if (StructType *DSTy = dyn_cast(DstTy)) { + StructType *SSTy = cast(SrcTy); + if (DSTy->isAnonymous() != SSTy->isAnonymous() || + DSTy->isPacked() != SSTy->isPacked()) + return false; + } else if (ArrayType *DATy = dyn_cast(DstTy)) { + if (DATy->getNumElements() != cast(SrcTy)->getNumElements()) + return false; + } else if (VectorType *DVTy = dyn_cast(DstTy)) { + if (DVTy->getNumElements() != cast(SrcTy)->getNumElements()) + return false; + } + + // Otherwise, we speculate that these two types will line up and recursively + // check the subelements. + Entry = DstTy; + SpeculativeTypes.push_back(SrcTy); + + for (unsigned i = 0, e = SrcTy->getNumContainedTypes(); i != e; ++i) + if (!areTypesIsomorphic(DstTy->getContainedType(i), + SrcTy->getContainedType(i))) + return false; + + // If everything seems to have lined up, then everything is great. + return true; +} - // If this is a pointer type, check to see if we have already seen it. If - // so, we are in a recursive branch. Cut off the search now. We cannot use - // an associative container for this search, because the type pointers (keys - // in the container) change whenever types get resolved. - if (SrcPT->isAbstract()) - if (const Type *ExistingDestTy = Pointers.lookup(SrcPT)) - return ExistingDestTy != DstPT; - - if (DstPT->isAbstract()) - if (const Type *ExistingSrcTy = Pointers.lookup(DstPT)) - return ExistingSrcTy != SrcPT; - // Otherwise, add the current pointers to the vector to stop recursion on - // this pair. - if (DstPT->isAbstract()) - Pointers.insert(DstPT, SrcPT); - if (SrcPT->isAbstract()) - Pointers.insert(SrcPT, DstPT); - - return RecursiveResolveTypesI(DstPT->getElementType(), - SrcPT->getElementType(), Pointers); - } +/// linkDefinedTypeBodies - Produce a body for an opaque type in the dest +/// module from a type definition in the source module. +void TypeMapTy::linkDefinedTypeBodies() { + SmallVector Elements; + SmallString<16> TmpName; + + // Note that processing entries in this loop (calling 'get') can add new + // entries to the DefinitionsToResolve vector. + while (!DefinitionsToResolve.empty()) { + StructType *SrcSTy = DefinitionsToResolve.pop_back_val(); + StructType *DstSTy = cast(MappedTypes[SrcSTy]); + + // TypeMap is a many-to-one mapping, if there were multiple types that + // provide a body for DstSTy then previous iterations of this loop may have + // already handled it. Just ignore this case. + if (!DstSTy->isOpaque()) continue; + assert(!SrcSTy->isOpaque() && "Not resolving a definition?"); + + // Map the body of the source type over to a new body for the dest type. + Elements.resize(SrcSTy->getNumElements()); + for (unsigned i = 0, e = Elements.size(); i != e; ++i) + Elements[i] = getImpl(SrcSTy->getElementType(i)); + + DstSTy->setBody(Elements, SrcSTy->isPacked()); + + // If DstSTy has no name or has a longer name than STy, then viciously steal + // STy's name. + if (!SrcSTy->hasName()) continue; + StringRef SrcName = SrcSTy->getName(); + + if (!DstSTy->hasName() || DstSTy->getName().size() > SrcName.size()) { + TmpName.insert(TmpName.end(), SrcName.begin(), SrcName.end()); + SrcSTy->setName(""); + DstSTy->setName(TmpName.str()); + TmpName.clear(); + } } } -static bool RecursiveResolveTypes(const Type *DestTy, const Type *SrcTy) { - LinkerTypeMap PointerTypes; - return RecursiveResolveTypesI(DestTy, SrcTy, PointerTypes); + +/// get - Return the mapped type to use for the specified input type from the +/// source module. +Type *TypeMapTy::get(Type *Ty) { + Type *Result = getImpl(Ty); + + // If this caused a reference to any struct type, resolve it before returning. + if (!DefinitionsToResolve.empty()) + linkDefinedTypeBodies(); + return Result; +} + +/// getImpl - This is the recursive version of get(). +Type *TypeMapTy::getImpl(Type *Ty) { + // If we already have an entry for this type, return it. + Type **Entry = &MappedTypes[Ty]; + if (*Entry) return *Entry; + + // If this is not a named struct type, then just map all of the elements and + // then rebuild the type from inside out. + if (!isa(Ty) || cast(Ty)->isAnonymous()) { + // If there are no element types to map, then the type is itself. This is + // true for the anonymous {} struct, things like 'float', integers, etc. + if (Ty->getNumContainedTypes() == 0) + return *Entry = Ty; + + // Remap all of the elements, keeping track of whether any of them change. + bool AnyChange = false; + SmallVector ElementTypes; + ElementTypes.resize(Ty->getNumContainedTypes()); + for (unsigned i = 0, e = Ty->getNumContainedTypes(); i != e; ++i) { + ElementTypes[i] = getImpl(Ty->getContainedType(i)); + AnyChange |= ElementTypes[i] != Ty->getContainedType(i); + } + + // If we found our type while recursively processing stuff, just use it. + Entry = &MappedTypes[Ty]; + if (*Entry) return *Entry; + + // If all of the element types mapped directly over, then the type is usable + // as-is. + if (!AnyChange) + return *Entry = Ty; + + // Otherwise, rebuild a modified type. + switch (Ty->getTypeID()) { + default: assert(0 && "unknown derived type to remap"); + case Type::ArrayTyID: + return *Entry = ArrayType::get(ElementTypes[0], + cast(Ty)->getNumElements()); + case Type::VectorTyID: + return *Entry = VectorType::get(ElementTypes[0], + cast(Ty)->getNumElements()); + case Type::PointerTyID: + return *Entry = PointerType::get(ElementTypes[0], + cast(Ty)->getAddressSpace()); + case Type::FunctionTyID: + return *Entry = FunctionType::get(ElementTypes[0], + ArrayRef(ElementTypes).slice(1), + cast(Ty)->isVarArg()); + case Type::StructTyID: + // Note that this is only reached for anonymous structs. + return *Entry = StructType::get(Ty->getContext(), ElementTypes, + cast(Ty)->isPacked()); + } + } + + // Otherwise, this is an unmapped named struct. If the struct can be directly + // mapped over, just use it as-is. This happens in a case when the linked-in + // module has something like: + // %T = type {%T*, i32} + // @GV = global %T* null + // where T does not exist at all in the destination module. + // + // The other case we watch for is when the type is not in the destination + // module, but that it has to be rebuilt because it refers to something that + // is already mapped. For example, if the destination module has: + // %A = type { i32 } + // and the source module has something like + // %A' = type { i32 } + // %B = type { %A'* } + // @GV = global %B* null + // then we want to create a new type: "%B = type { %A*}" and have it take the + // pristine "%B" name from the source module. + // + // To determine which case this is, we have to recursively walk the type graph + // speculating that we'll be able to reuse it unmodified. Only if this is + // safe would we map the entire thing over. Because this is an optimization, + // and is not required for the prettiness of the linked module, we just skip + // it and always rebuild a type here. + StructType *STy = cast(Ty); + + // If the type is opaque, we can just use it directly. + if (STy->isOpaque()) + return *Entry = STy; + + // Otherwise we create a new type and resolve its body later. This will be + // resolved by the top level of get(). + DefinitionsToResolve.push_back(STy); + return *Entry = StructType::createNamed(STy->getContext(), ""); } -// LinkTypes - Go through the symbol table of the Src module and see if any -// types are named in the src module that are not named in the Dst module. -// Make sure there are no type name conflicts. -static bool LinkTypes(Module *Dest, const Module *Src, std::string *Err) { - TypeSymbolTable *DestST = &Dest->getTypeSymbolTable(); - const TypeSymbolTable *SrcST = &Src->getTypeSymbolTable(); - - // Look for a type plane for Type's... - TypeSymbolTable::const_iterator TI = SrcST->begin(); - TypeSymbolTable::const_iterator TE = SrcST->end(); - if (TI == TE) return false; // No named types, do nothing. - - // Some types cannot be resolved immediately because they depend on other - // types being resolved to each other first. This contains a list of types we - // are waiting to recheck. - std::vector DelayedTypesToResolve; - - for ( ; TI != TE; ++TI ) { - const std::string &Name = TI->first; - const Type *RHS = TI->second; - - // Check to see if this type name is already in the dest module. - Type *Entry = DestST->lookup(Name); - - // If the name is just in the source module, bring it over to the dest. - if (Entry == 0) { - if (!Name.empty()) - DestST->insert(Name, const_cast(RHS)); - } else if (ResolveTypes(Entry, RHS)) { - // They look different, save the types 'till later to resolve. - DelayedTypesToResolve.push_back(Name); - } - } - // Iteratively resolve types while we can... - while (!DelayedTypesToResolve.empty()) { - // Loop over all of the types, attempting to resolve them if possible... - unsigned OldSize = DelayedTypesToResolve.size(); - - // Try direct resolution by name... - for (unsigned i = 0; i != DelayedTypesToResolve.size(); ++i) { - const std::string &Name = DelayedTypesToResolve[i]; - Type *T1 = SrcST->lookup(Name); - Type *T2 = DestST->lookup(Name); - if (!ResolveTypes(T2, T1)) { - // We are making progress! - DelayedTypesToResolve.erase(DelayedTypesToResolve.begin()+i); - --i; - } - } - - // Did we not eliminate any types? - if (DelayedTypesToResolve.size() == OldSize) { - // Attempt to resolve subelements of types. This allows us to merge these - // two types: { int* } and { opaque* } - for (unsigned i = 0, e = DelayedTypesToResolve.size(); i != e; ++i) { - const std::string &Name = DelayedTypesToResolve[i]; - if (!RecursiveResolveTypes(SrcST->lookup(Name), DestST->lookup(Name))) { - // We are making progress! - DelayedTypesToResolve.erase(DelayedTypesToResolve.begin()+i); - - // Go back to the main loop, perhaps we can resolve directly by name - // now... - break; - } - } +//===----------------------------------------------------------------------===// +// ModuleLinker implementation. +//===----------------------------------------------------------------------===// - // If we STILL cannot resolve the types, then there is something wrong. - if (DelayedTypesToResolve.size() == OldSize) { - // Remove the symbol name from the destination. - DelayedTypesToResolve.pop_back(); - } +namespace { + /// ModuleLinker - This is an implementation class for the LinkModules + /// function, which is the entrypoint for this file. + class ModuleLinker { + Module *DstM, *SrcM; + + TypeMapTy TypeMap; + + /// ValueMap - Mapping of values from what they used to be in Src, to what + /// they are now in DstM. ValueToValueMapTy is a ValueMap, which involves + /// some overhead due to the use of Value handles which the Linker doesn't + /// actually need, but this allows us to reuse the ValueMapper code. + ValueToValueMapTy ValueMap; + + struct AppendingVarInfo { + GlobalVariable *NewGV; // New aggregate global in dest module. + Constant *DstInit; // Old initializer from dest module. + Constant *SrcInit; // Old initializer from src module. + }; + + std::vector AppendingVars; + + public: + std::string ErrorMsg; + + ModuleLinker(Module *dstM, Module *srcM) : DstM(dstM), SrcM(srcM) { } + + bool run(); + + private: + /// emitError - Helper method for setting a message and returning an error + /// code. + bool emitError(const Twine &Message) { + ErrorMsg = Message.str(); + return true; } - } + + /// getLinkageResult - This analyzes the two global values and determines + /// what the result will look like in the destination module. + bool getLinkageResult(GlobalValue *Dest, const GlobalValue *Src, + GlobalValue::LinkageTypes <, bool &LinkFromSrc); + + /// getLinkedToGlobal - Given a global in the source module, return the + /// global in the destination module that is being linked to, if any. + GlobalValue *getLinkedToGlobal(GlobalValue *SrcGV) { + // If the source has no name it can't link. If it has local linkage, + // there is no name match-up going on. + if (!SrcGV->hasName() || SrcGV->hasLocalLinkage()) + return 0; + + // Otherwise see if we have a match in the destination module's symtab. + GlobalValue *DGV = DstM->getNamedValue(SrcGV->getName()); + if (DGV == 0) return 0; + + // If we found a global with the same name in the dest module, but it has + // internal linkage, we are really not doing any linkage here. + if (DGV->hasLocalLinkage()) + return 0; + + // Otherwise, we do in fact link to the destination global. + return DGV; + } + + void computeTypeMapping(); + + bool linkAppendingVarProto(GlobalVariable *DstGV, GlobalVariable *SrcGV); + bool linkGlobalProto(GlobalVariable *SrcGV); + bool linkFunctionProto(Function *SrcF); + bool linkAliasProto(GlobalAlias *SrcA); + + void linkAppendingVarInit(const AppendingVarInfo &AVI); + void linkGlobalInits(); + void linkFunctionBody(Function *Dst, Function *Src); + void linkAliasBodies(); + void linkNamedMDNodes(); + }; +} - return false; -} -/// ForceRenaming - The LLVM SymbolTable class autorenames globals that conflict +/// forceRenaming - The LLVM SymbolTable class autorenames globals that conflict /// in the symbol table. This is good for all clients except for us. Go /// through the trouble to force this back. -static void ForceRenaming(GlobalValue *GV, const std::string &Name) { - assert(GV->getName() != Name && "Can't force rename to self"); - ValueSymbolTable &ST = GV->getParent()->getValueSymbolTable(); +static void forceRenaming(GlobalValue *GV, StringRef Name) { + // If the global doesn't force its name or if it already has the right name, + // there is nothing for us to do. + if (GV->hasLocalLinkage() || GV->getName() == Name) + return; + + Module *M = GV->getParent(); // If there is a conflict, rename the conflict. - if (GlobalValue *ConflictGV = cast_or_null(ST.lookup(Name))) { - assert(ConflictGV->hasLocalLinkage() && - "Not conflicting with a static global, should link instead!"); + if (GlobalValue *ConflictGV = M->getNamedValue(Name)) { GV->takeName(ConflictGV); ConflictGV->setName(Name); // This will cause ConflictGV to get renamed - assert(ConflictGV->getName() != Name && "ForceRenaming didn't work"); + assert(ConflictGV->getName() != Name && "forceRenaming didn't work"); } else { GV->setName(Name); // Force the name back } @@ -352,30 +419,35 @@ unsigned Alignment = std::max(DestGV->getAlignment(), SrcGV->getAlignment()); DestGV->copyAttributesFrom(SrcGV); DestGV->setAlignment(Alignment); + + forceRenaming(DestGV, SrcGV->getName()); } -/// GetLinkageResult - This analyzes the two global values and determines what +/// getLinkageResult - This analyzes the two global values and determines what /// the result will look like in the destination module. In particular, it /// computes the resultant linkage type, computes whether the global in the /// source should be copied over to the destination (replacing the existing /// one), and computes whether this linkage is an error or not. It also performs /// visibility checks: we cannot link together two symbols with different /// visibilities. -static bool GetLinkageResult(GlobalValue *Dest, const GlobalValue *Src, - GlobalValue::LinkageTypes <, bool &LinkFromSrc, - std::string *Err) { - assert((!Dest || !Src->hasLocalLinkage()) && +bool ModuleLinker::getLinkageResult(GlobalValue *Dest, const GlobalValue *Src, + GlobalValue::LinkageTypes <, + bool &LinkFromSrc) { + assert(Dest && "Must have two globals being queried"); + assert(!Src->hasLocalLinkage() && "If Src has internal linkage, Dest shouldn't be set!"); - if (!Dest) { - // Linking something to nothing. - LinkFromSrc = true; - LT = Src->getLinkage(); - } else if (Src->isDeclaration()) { + + // FIXME: GlobalAlias::isDeclaration is broken, should always be + // false. + bool SrcIsDeclaration = Src->isDeclaration() && !isa(Src); + bool DestIsDeclaration = Dest->isDeclaration() && !isa(Dest); + + if (SrcIsDeclaration) { // If Src is external or if both Src & Dest are external.. Just link the // external globals, we aren't adding anything. if (Src->hasDLLImportLinkage()) { // If one of GVs has DLLImport linkage, result should be dllimport'ed. - if (Dest->isDeclaration()) { + if (DestIsDeclaration) { LinkFromSrc = true; LT = Src->getLinkage(); } @@ -387,16 +459,10 @@ LinkFromSrc = false; LT = Dest->getLinkage(); } - } else if (Dest->isDeclaration() && !Dest->hasDLLImportLinkage()) { + } else if (DestIsDeclaration && !Dest->hasDLLImportLinkage()) { // If Dest is external but Src is not: LinkFromSrc = true; LT = Src->getLinkage(); - } else if (Src->hasAppendingLinkage() || Dest->hasAppendingLinkage()) { - if (Src->getLinkage() != Dest->getLinkage()) - return Error(Err, "Linking globals named '" + Src->getName() + - "': can only link appending global with another appending global!"); - LinkFromSrc = true; // Special cased. - LT = Src->getLinkage(); } else if (Src->isWeakForLinker()) { // At this point we know that Dest has LinkOnce, External*, Weak, Common, // or DLL* linkage. @@ -420,883 +486,485 @@ LT = GlobalValue::ExternalLinkage; } } else { - assert((Dest->hasExternalLinkage() || - Dest->hasDLLImportLinkage() || - Dest->hasDLLExportLinkage() || - Dest->hasExternalWeakLinkage()) && - (Src->hasExternalLinkage() || - Src->hasDLLImportLinkage() || - Src->hasDLLExportLinkage() || - Src->hasExternalWeakLinkage()) && + assert((Dest->hasExternalLinkage() || Dest->hasDLLImportLinkage() || + Dest->hasDLLExportLinkage() || Dest->hasExternalWeakLinkage()) && + (Src->hasExternalLinkage() || Src->hasDLLImportLinkage() || + Src->hasDLLExportLinkage() || Src->hasExternalWeakLinkage()) && "Unexpected linkage type!"); - return Error(Err, "Linking globals named '" + Src->getName() + + return emitError("Linking globals named '" + Src->getName() + "': symbol multiply defined!"); } // Check visibility - if (Dest && Src->getVisibility() != Dest->getVisibility() && - !Src->isDeclaration() && !Dest->isDeclaration() && + if (Src->getVisibility() != Dest->getVisibility() && + !SrcIsDeclaration && !DestIsDeclaration && !Src->hasAvailableExternallyLinkage() && !Dest->hasAvailableExternallyLinkage()) - return Error(Err, "Linking globals named '" + Src->getName() + + return emitError("Linking globals named '" + Src->getName() + "': symbols have different visibilities!"); return false; } -// Insert all of the named mdnoes in Src into the Dest module. -static void LinkNamedMDNodes(Module *Dest, Module *Src, - ValueToValueMapTy &ValueMap) { - for (Module::const_named_metadata_iterator I = Src->named_metadata_begin(), - E = Src->named_metadata_end(); I != E; ++I) { - const NamedMDNode *SrcNMD = I; - NamedMDNode *DestNMD = Dest->getOrInsertNamedMetadata(SrcNMD->getName()); - // Add Src elements into Dest node. - for (unsigned i = 0, e = SrcNMD->getNumOperands(); i != e; ++i) - DestNMD->addOperand(cast(MapValue(SrcNMD->getOperand(i), - ValueMap))); - } -} - -// LinkGlobals - Loop through the global variables in the src module and merge -// them into the dest module. -static bool LinkGlobals(Module *Dest, const Module *Src, - ValueToValueMapTy &ValueMap, - std::multimap &AppendingVars, - std::string *Err) { - ValueSymbolTable &DestSymTab = Dest->getValueSymbolTable(); - - // Loop over all of the globals in the src module, mapping them over as we go - for (Module::const_global_iterator I = Src->global_begin(), - E = Src->global_end(); I != E; ++I) { - const GlobalVariable *SGV = I; - GlobalValue *DGV = 0; - - // Check to see if may have to link the global with the global, alias or - // function. - if (SGV->hasName() && !SGV->hasLocalLinkage()) - DGV = cast_or_null(DestSymTab.lookup(SGV->getName())); - - // If we found a global with the same name in the dest module, but it has - // internal linkage, we are really not doing any linkage here. - if (DGV && DGV->hasLocalLinkage()) - DGV = 0; - - // If types don't agree due to opaque types, try to resolve them. - if (DGV && DGV->getType() != SGV->getType()) - RecursiveResolveTypes(SGV->getType(), DGV->getType()); - - assert((SGV->hasInitializer() || SGV->hasExternalWeakLinkage() || - SGV->hasExternalLinkage() || SGV->hasDLLImportLinkage()) && - "Global must either be external or have an initializer!"); - +/// computeTypeMapping - Loop over all of the linked values to compute type +/// mappings. For example, if we link "extern Foo *x" and "Foo *x = NULL", then +/// we have two struct types 'Foo' but one got renamed when the module was +/// loaded into the same LLVMContext. +void ModuleLinker::computeTypeMapping() { + // Incorporate globals. + for (Module::global_iterator I = SrcM->global_begin(), + E = SrcM->global_end(); I != E; ++I) { + GlobalValue *DGV = getLinkedToGlobal(I); + if (DGV == 0) continue; + + if (!DGV->hasAppendingLinkage() || !I->hasAppendingLinkage()) { + TypeMap.addTypeMapping(DGV->getType(), I->getType()); + continue; + } + + // Unify the element type of appending arrays. + ArrayType *DAT = cast(DGV->getType()->getElementType()); + ArrayType *SAT = cast(I->getType()->getElementType()); + TypeMap.addTypeMapping(DAT->getElementType(), SAT->getElementType()); + } + + // Incorporate functions. + for (Module::iterator I = SrcM->begin(), E = SrcM->end(); I != E; ++I) { + if (GlobalValue *DGV = getLinkedToGlobal(I)) + TypeMap.addTypeMapping(DGV->getType(), I->getType()); + } + + // Don't bother incorporating aliases, they aren't generally typed well. + + // Now that we have discovered all of the type equivalences, get a body for + // any 'opaque' types in the dest module that are now resolved. + TypeMap.linkDefinedTypeBodies(); +} + +/// linkAppendingVarProto - If there were any appending global variables, link +/// them together now. Return true on error. +bool ModuleLinker::linkAppendingVarProto(GlobalVariable *DstGV, + GlobalVariable *SrcGV) { + + if (!SrcGV->hasAppendingLinkage() || !DstGV->hasAppendingLinkage()) + return emitError("Linking globals named '" + SrcGV->getName() + + "': can only link appending global with another appending global!"); + + ArrayType *DstTy = cast(DstGV->getType()->getElementType()); + ArrayType *SrcTy = + cast(TypeMap.get(SrcGV->getType()->getElementType())); + Type *EltTy = DstTy->getElementType(); + + // Check to see that they two arrays agree on type. + if (EltTy != SrcTy->getElementType()) + return emitError("Appending variables with different element types!"); + if (DstGV->isConstant() != SrcGV->isConstant()) + return emitError("Appending variables linked with different const'ness!"); + + if (DstGV->getAlignment() != SrcGV->getAlignment()) + return emitError( + "Appending variables with different alignment need to be linked!"); + + if (DstGV->getVisibility() != SrcGV->getVisibility()) + return emitError( + "Appending variables with different visibility need to be linked!"); + + if (DstGV->getSection() != SrcGV->getSection()) + return emitError( + "Appending variables with different section name need to be linked!"); + + uint64_t NewSize = DstTy->getNumElements() + SrcTy->getNumElements(); + ArrayType *NewType = ArrayType::get(EltTy, NewSize); + + // Create the new global variable. + GlobalVariable *NG = + new GlobalVariable(*DstGV->getParent(), NewType, SrcGV->isConstant(), + DstGV->getLinkage(), /*init*/0, /*name*/"", DstGV, + DstGV->isThreadLocal(), + DstGV->getType()->getAddressSpace()); + + // Propagate alignment, visibility and section info. + CopyGVAttributes(NG, DstGV); + + AppendingVarInfo AVI; + AVI.NewGV = NG; + AVI.DstInit = DstGV->getInitializer(); + AVI.SrcInit = SrcGV->getInitializer(); + AppendingVars.push_back(AVI); + + // Replace any uses of the two global variables with uses of the new + // global. + ValueMap[SrcGV] = ConstantExpr::getBitCast(NG, TypeMap.get(SrcGV->getType())); + + DstGV->replaceAllUsesWith(ConstantExpr::getBitCast(NG, DstGV->getType())); + DstGV->eraseFromParent(); + + // Zap the initializer in the source variable so we don't try to link it. + SrcGV->setInitializer(0); + SrcGV->setLinkage(GlobalValue::ExternalLinkage); + return false; +} + +/// linkGlobalProto - Loop through the global variables in the src module and +/// merge them into the dest module. +bool ModuleLinker::linkGlobalProto(GlobalVariable *SGV) { + GlobalValue *DGV = getLinkedToGlobal(SGV); + + if (DGV) { + // Concatenation of appending linkage variables is magic and handled later. + if (DGV->hasAppendingLinkage() || SGV->hasAppendingLinkage()) + return linkAppendingVarProto(cast(DGV), SGV); + + // Determine whether linkage of these two globals follows the source + // module's definition or the destination module's definition. GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; bool LinkFromSrc = false; - if (GetLinkageResult(DGV, SGV, NewLinkage, LinkFromSrc, Err)) + if (getLinkageResult(DGV, SGV, NewLinkage, LinkFromSrc)) return true; - if (DGV == 0) { - // No linking to be performed, simply create an identical version of the - // symbol over in the dest module... the initializer will be filled in - // later by LinkGlobalInits. - GlobalVariable *NewDGV = - new GlobalVariable(*Dest, SGV->getType()->getElementType(), - SGV->isConstant(), SGV->getLinkage(), /*init*/0, - SGV->getName(), 0, false, - SGV->getType()->getAddressSpace()); - // Propagate alignment, visibility and section info. - CopyGVAttributes(NewDGV, SGV); - NewDGV->setUnnamedAddr(SGV->hasUnnamedAddr()); - - // If the LLVM runtime renamed the global, but it is an externally visible - // symbol, DGV must be an existing global with internal linkage. Rename - // it. - if (!NewDGV->hasLocalLinkage() && NewDGV->getName() != SGV->getName()) - ForceRenaming(NewDGV, SGV->getName()); - - // Make sure to remember this mapping. - ValueMap[SGV] = NewDGV; - - // Keep track that this is an appending variable. - if (SGV->hasAppendingLinkage()) - AppendingVars.insert(std::make_pair(SGV->getName(), NewDGV)); - continue; - } - - bool HasUnnamedAddr = SGV->hasUnnamedAddr() && DGV->hasUnnamedAddr(); - - // If the visibilities of the symbols disagree and the destination is a - // prototype, take the visibility of its input. - if (DGV->isDeclaration()) - DGV->setVisibility(SGV->getVisibility()); - - if (DGV->hasAppendingLinkage()) { - // No linking is performed yet. Just insert a new copy of the global, and - // keep track of the fact that it is an appending variable in the - // AppendingVars map. The name is cleared out so that no linkage is - // performed. - GlobalVariable *NewDGV = - new GlobalVariable(*Dest, SGV->getType()->getElementType(), - SGV->isConstant(), SGV->getLinkage(), /*init*/0, - "", 0, false, - SGV->getType()->getAddressSpace()); - - // Set alignment allowing CopyGVAttributes merge it with alignment of SGV. - NewDGV->setAlignment(DGV->getAlignment()); - // Propagate alignment, section and visibility info. - CopyGVAttributes(NewDGV, SGV); - - // Make sure to remember this mapping... - ValueMap[SGV] = NewDGV; - - // Keep track that this is an appending variable... - AppendingVars.insert(std::make_pair(SGV->getName(), NewDGV)); - continue; - } - - if (LinkFromSrc) { - if (isa(DGV)) - return Error(Err, "Global-Alias Collision on '" + SGV->getName() + - "': symbol multiple defined"); - - // If the types don't match, and if we are to link from the source, nuke - // DGV and create a new one of the appropriate type. Note that the thing - // we are replacing may be a function (if a prototype, weak, etc) or a - // global variable. - GlobalVariable *NewDGV = - new GlobalVariable(*Dest, SGV->getType()->getElementType(), - SGV->isConstant(), NewLinkage, /*init*/0, - DGV->getName(), 0, false, - SGV->getType()->getAddressSpace()); - - // Set the unnamed_addr. - NewDGV->setUnnamedAddr(HasUnnamedAddr); - - // Propagate alignment, section, and visibility info. - CopyGVAttributes(NewDGV, SGV); - DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDGV, - DGV->getType())); - - // DGV will conflict with NewDGV because they both had the same - // name. We must erase this now so ForceRenaming doesn't assert - // because DGV might not have internal linkage. - if (GlobalVariable *Var = dyn_cast(DGV)) - Var->eraseFromParent(); - else - cast(DGV)->eraseFromParent(); - - // If the symbol table renamed the global, but it is an externally visible - // symbol, DGV must be an existing global with internal linkage. Rename. - if (NewDGV->getName() != SGV->getName() && !NewDGV->hasLocalLinkage()) - ForceRenaming(NewDGV, SGV->getName()); - - // Inherit const as appropriate. - NewDGV->setConstant(SGV->isConstant()); - + // If we're not linking from the source, then keep the definition that we + // have. + if (!LinkFromSrc) { + // Special case for const propagation. + if (GlobalVariable *DGVar = dyn_cast(DGV)) + if (DGVar->isDeclaration() && SGV->isConstant() && !DGVar->isConstant()) + DGVar->setConstant(true); + + // Set calculated linkage. + DGV->setLinkage(NewLinkage); + // Make sure to remember this mapping. - ValueMap[SGV] = NewDGV; - continue; - } - - // Not "link from source", keep the one in the DestModule and remap the - // input onto it. - - // Special case for const propagation. - if (GlobalVariable *DGVar = dyn_cast(DGV)) - if (DGVar->isDeclaration() && SGV->isConstant() && !DGVar->isConstant()) - DGVar->setConstant(true); - - // SGV is global, but DGV is alias. - if (isa(DGV)) { - // The only valid mappings are: - // - SGV is external declaration, which is effectively a no-op. - // - SGV is weak, when we just need to throw SGV out. - if (!SGV->isDeclaration() && !SGV->isWeakForLinker()) - return Error(Err, "Global-Alias Collision on '" + SGV->getName() + - "': symbol multiple defined"); - } - - // Set calculated linkage and unnamed_addr - DGV->setLinkage(NewLinkage); - DGV->setUnnamedAddr(HasUnnamedAddr); - - // Make sure to remember this mapping... - ValueMap[SGV] = ConstantExpr::getBitCast(DGV, SGV->getType()); - } - return false; -} - -static GlobalValue::LinkageTypes -CalculateAliasLinkage(const GlobalValue *SGV, const GlobalValue *DGV) { - GlobalValue::LinkageTypes SL = SGV->getLinkage(); - GlobalValue::LinkageTypes DL = DGV->getLinkage(); - if (SL == GlobalValue::ExternalLinkage || DL == GlobalValue::ExternalLinkage) - return GlobalValue::ExternalLinkage; - else if (SL == GlobalValue::WeakAnyLinkage || - DL == GlobalValue::WeakAnyLinkage) - return GlobalValue::WeakAnyLinkage; - else if (SL == GlobalValue::WeakODRLinkage || - DL == GlobalValue::WeakODRLinkage) - return GlobalValue::WeakODRLinkage; - else if (SL == GlobalValue::InternalLinkage && - DL == GlobalValue::InternalLinkage) - return GlobalValue::InternalLinkage; - else if (SL == GlobalValue::LinkerPrivateLinkage && - DL == GlobalValue::LinkerPrivateLinkage) - return GlobalValue::LinkerPrivateLinkage; - else if (SL == GlobalValue::LinkerPrivateWeakLinkage && - DL == GlobalValue::LinkerPrivateWeakLinkage) - return GlobalValue::LinkerPrivateWeakLinkage; - else if (SL == GlobalValue::LinkerPrivateWeakDefAutoLinkage && - DL == GlobalValue::LinkerPrivateWeakDefAutoLinkage) - return GlobalValue::LinkerPrivateWeakDefAutoLinkage; - else { - assert (SL == GlobalValue::PrivateLinkage && - DL == GlobalValue::PrivateLinkage && "Unexpected linkage type"); - return GlobalValue::PrivateLinkage; - } -} - -// LinkAlias - Loop through the alias in the src module and link them into the -// dest module. We're assuming, that all functions/global variables were already -// linked in. -static bool LinkAlias(Module *Dest, const Module *Src, - ValueToValueMapTy &ValueMap, - std::string *Err) { - // Loop over all alias in the src module - for (Module::const_alias_iterator I = Src->alias_begin(), - E = Src->alias_end(); I != E; ++I) { - const GlobalAlias *SGA = I; - const GlobalValue *SAliasee = SGA->getAliasedGlobal(); - GlobalAlias *NewGA = NULL; - - // Globals were already linked, thus we can just query ValueMap for variant - // of SAliasee in Dest. - ValueToValueMapTy::const_iterator VMI = ValueMap.find(SAliasee); - assert(VMI != ValueMap.end() && "Aliasee not linked"); - GlobalValue* DAliasee = cast(VMI->second); - GlobalValue* DGV = NULL; - - // Fixup aliases to bitcasts. Note that aliases to GEPs are still broken - // by this, but aliases to GEPs are broken to a lot of other things, so - // it's less important. - Constant *DAliaseeConst = DAliasee; - if (SGA->getType() != DAliasee->getType()) - DAliaseeConst = ConstantExpr::getBitCast(DAliasee, SGA->getType()); - - // Try to find something 'similar' to SGA in destination module. - if (!DGV && !SGA->hasLocalLinkage()) { - DGV = Dest->getNamedAlias(SGA->getName()); - - // If types don't agree due to opaque types, try to resolve them. - if (DGV && DGV->getType() != SGA->getType()) - RecursiveResolveTypes(SGA->getType(), DGV->getType()); - } - - if (!DGV && !SGA->hasLocalLinkage()) { - DGV = Dest->getGlobalVariable(SGA->getName()); - - // If types don't agree due to opaque types, try to resolve them. - if (DGV && DGV->getType() != SGA->getType()) - RecursiveResolveTypes(SGA->getType(), DGV->getType()); - } - - if (!DGV && !SGA->hasLocalLinkage()) { - DGV = Dest->getFunction(SGA->getName()); - - // If types don't agree due to opaque types, try to resolve them. - if (DGV && DGV->getType() != SGA->getType()) - RecursiveResolveTypes(SGA->getType(), DGV->getType()); - } - - // No linking to be performed on internal stuff. - if (DGV && DGV->hasLocalLinkage()) - DGV = NULL; - - if (GlobalAlias *DGA = dyn_cast_or_null(DGV)) { - // Types are known to be the same, check whether aliasees equal. As - // globals are already linked we just need query ValueMap to find the - // mapping. - if (DAliasee == DGA->getAliasedGlobal()) { - // This is just two copies of the same alias. Propagate linkage, if - // necessary. - DGA->setLinkage(CalculateAliasLinkage(SGA, DGA)); - - NewGA = DGA; - // Proceed to 'common' steps - } else - return Error(Err, "Alias Collision on '" + SGA->getName()+ - "': aliases have different aliasees"); - } else if (GlobalVariable *DGVar = dyn_cast_or_null(DGV)) { - // The only allowed way is to link alias with external declaration or weak - // symbol.. - if (DGVar->isDeclaration() || DGVar->isWeakForLinker()) { - // But only if aliasee is global too... - if (!isa(DAliasee)) - return Error(Err, "Global-Alias Collision on '" + SGA->getName() + - "': aliasee is not global variable"); - - NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), - SGA->getName(), DAliaseeConst, Dest); - CopyGVAttributes(NewGA, SGA); - - // Any uses of DGV need to change to NewGA, with cast, if needed. - if (SGA->getType() != DGVar->getType()) - DGVar->replaceAllUsesWith(ConstantExpr::getBitCast(NewGA, - DGVar->getType())); - else - DGVar->replaceAllUsesWith(NewGA); - - // DGVar will conflict with NewGA because they both had the same - // name. We must erase this now so ForceRenaming doesn't assert - // because DGV might not have internal linkage. - DGVar->eraseFromParent(); - - // Proceed to 'common' steps - } else - return Error(Err, "Global-Alias Collision on '" + SGA->getName() + - "': symbol multiple defined"); - } else if (Function *DF = dyn_cast_or_null(DGV)) { - // The only allowed way is to link alias with external declaration or weak - // symbol... - if (DF->isDeclaration() || DF->isWeakForLinker()) { - // But only if aliasee is function too... - if (!isa(DAliasee)) - return Error(Err, "Function-Alias Collision on '" + SGA->getName() + - "': aliasee is not function"); - - NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), - SGA->getName(), DAliaseeConst, Dest); - CopyGVAttributes(NewGA, SGA); - - // Any uses of DF need to change to NewGA, with cast, if needed. - if (SGA->getType() != DF->getType()) - DF->replaceAllUsesWith(ConstantExpr::getBitCast(NewGA, - DF->getType())); - else - DF->replaceAllUsesWith(NewGA); - - // DF will conflict with NewGA because they both had the same - // name. We must erase this now so ForceRenaming doesn't assert - // because DF might not have internal linkage. - DF->eraseFromParent(); - - // Proceed to 'common' steps - } else - return Error(Err, "Function-Alias Collision on '" + SGA->getName() + - "': symbol multiple defined"); - } else { - // No linking to be performed, simply create an identical version of the - // alias over in the dest module... - NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), - SGA->getName(), DAliaseeConst, Dest); - CopyGVAttributes(NewGA, SGA); - - // Proceed to 'common' steps - } - - assert(NewGA && "No alias was created in destination module!"); - - // If the symbol table renamed the alias, but it is an externally visible - // symbol, DGA must be an global value with internal linkage. Rename it. - if (NewGA->getName() != SGA->getName() && - !NewGA->hasLocalLinkage()) - ForceRenaming(NewGA, SGA->getName()); - - // Remember this mapping so uses in the source module get remapped - // later by MapValue. - ValueMap[SGA] = NewGA; - } - + ValueMap[SGV] = ConstantExpr::getBitCast(DGV,TypeMap.get(SGV->getType())); + + // Destroy the source global's initializer (and convert it to a prototype) + // so that we don't attempt to copy it over when processing global + // initializers. + SGV->setInitializer(0); + SGV->setLinkage(GlobalValue::ExternalLinkage); + return false; + } + } + + // No linking to be performed or linking from the source: simply create an + // identical version of the symbol over in the dest module... the + // initializer will be filled in later by LinkGlobalInits. + GlobalVariable *NewDGV = + new GlobalVariable(*DstM, TypeMap.get(SGV->getType()->getElementType()), + SGV->isConstant(), SGV->getLinkage(), /*init*/0, + SGV->getName(), /*insertbefore*/0, + SGV->isThreadLocal(), + SGV->getType()->getAddressSpace()); + // Propagate alignment, visibility and section info. + CopyGVAttributes(NewDGV, SGV); + + if (DGV) { + DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDGV, DGV->getType())); + DGV->eraseFromParent(); + } + + // Make sure to remember this mapping. + ValueMap[SGV] = NewDGV; return false; } +/// linkFunctionProto - Link the function in the source module into the +/// destination module if needed, setting up mapping information. +bool ModuleLinker::linkFunctionProto(Function *SF) { + GlobalValue *DGV = getLinkedToGlobal(SF); -// LinkGlobalInits - Update the initializers in the Dest module now that all -// globals that may be referenced are in Dest. -static bool LinkGlobalInits(Module *Dest, const Module *Src, - ValueToValueMapTy &ValueMap, - std::string *Err) { - // Loop over all of the globals in the src module, mapping them over as we go - for (Module::const_global_iterator I = Src->global_begin(), - E = Src->global_end(); I != E; ++I) { - const GlobalVariable *SGV = I; - - if (SGV->hasInitializer()) { // Only process initialized GV's - // Figure out what the initializer looks like in the dest module. - Constant *SInit = - cast(MapValue(SGV->getInitializer(), ValueMap)); - // Grab destination global variable or alias. - GlobalValue *DGV = cast(ValueMap[SGV]->stripPointerCasts()); - - // If dest if global variable, check that initializers match. - if (GlobalVariable *DGVar = dyn_cast(DGV)) { - if (DGVar->hasInitializer()) { - if (SGV->hasExternalLinkage()) { - if (DGVar->getInitializer() != SInit) - return Error(Err, "Global Variable Collision on '" + - SGV->getName() + - "': global variables have different initializers"); - } else if (DGVar->isWeakForLinker()) { - // Nothing is required, mapped values will take the new global - // automatically. - } else if (SGV->isWeakForLinker()) { - // Nothing is required, mapped values will take the new global - // automatically. - } else if (DGVar->hasAppendingLinkage()) { - llvm_unreachable("Appending linkage unimplemented!"); - } else { - llvm_unreachable("Unknown linkage!"); - } - } else { - // Copy the initializer over now... - DGVar->setInitializer(SInit); - } - } else { - // Destination is alias, the only valid situation is when source is - // weak. Also, note, that we already checked linkage in LinkGlobals(), - // thus we assert here. - // FIXME: Should we weaken this assumption, 'dereference' alias and - // check for initializer of aliasee? - assert(SGV->isWeakForLinker()); - } - } - } + if (DGV) { + GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; + bool LinkFromSrc = false; + if (getLinkageResult(DGV, SF, NewLinkage, LinkFromSrc)) + return true; + + if (!LinkFromSrc) { + // Set calculated linkage + DGV->setLinkage(NewLinkage); + + // Make sure to remember this mapping. + ValueMap[SF] = ConstantExpr::getBitCast(DGV, TypeMap.get(SF->getType())); + + // Remove the body from the source module so we don't attempt to remap it. + SF->deleteBody(); + return false; + } + } + + // If there is no linkage to be performed or we are linking from the source, + // bring SF over. + Function *NewDF = Function::Create(TypeMap.get(SF->getFunctionType()), + SF->getLinkage(), SF->getName(), DstM); + CopyGVAttributes(NewDF, SF); + + if (DGV) { + // Any uses of DF need to change to NewDF, with cast. + DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDF, DGV->getType())); + DGV->eraseFromParent(); + } + + ValueMap[SF] = NewDF; return false; } -// LinkFunctionProtos - Link the functions together between the two modules, -// without doing function bodies... this just adds external function prototypes -// to the Dest function... -// -static bool LinkFunctionProtos(Module *Dest, const Module *Src, - ValueToValueMapTy &ValueMap, - std::string *Err) { - ValueSymbolTable &DestSymTab = Dest->getValueSymbolTable(); - - // Loop over all of the functions in the src module, mapping them over - for (Module::const_iterator I = Src->begin(), E = Src->end(); I != E; ++I) { - const Function *SF = I; // SrcFunction - GlobalValue *DGV = 0; - - // Check to see if may have to link the function with the global, alias or - // function. - if (SF->hasName() && !SF->hasLocalLinkage()) - DGV = cast_or_null(DestSymTab.lookup(SF->getName())); - - // If we found a global with the same name in the dest module, but it has - // internal linkage, we are really not doing any linkage here. - if (DGV && DGV->hasLocalLinkage()) - DGV = 0; - - // If types don't agree due to opaque types, try to resolve them. - if (DGV && DGV->getType() != SF->getType()) - RecursiveResolveTypes(SF->getType(), DGV->getType()); - +/// LinkAliasProto - Set up prototypes for any aliases that come over from the +/// source module. +bool ModuleLinker::linkAliasProto(GlobalAlias *SGA) { + GlobalValue *DGV = getLinkedToGlobal(SGA); + + if (DGV) { GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; bool LinkFromSrc = false; - if (GetLinkageResult(DGV, SF, NewLinkage, LinkFromSrc, Err)) + if (getLinkageResult(DGV, SGA, NewLinkage, LinkFromSrc)) return true; + + if (!LinkFromSrc) { + // Set calculated linkage. + DGV->setLinkage(NewLinkage); + + // Make sure to remember this mapping. + ValueMap[SGA] = ConstantExpr::getBitCast(DGV,TypeMap.get(SGA->getType())); + + // Remove the body from the source module so we don't attempt to remap it. + SGA->setAliasee(0); + return false; + } + } + + // If there is no linkage to be performed or we're linking from the source, + // bring over SGA. + GlobalAlias *NewDA = new GlobalAlias(TypeMap.get(SGA->getType()), + SGA->getLinkage(), SGA->getName(), + /*aliasee*/0, DstM); + CopyGVAttributes(NewDA, SGA); + + if (DGV) { + // Any uses of DGV need to change to NewDA, with cast. + DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDA, DGV->getType())); + DGV->eraseFromParent(); + } + + ValueMap[SGA] = NewDA; + return false; +} - // If there is no linkage to be performed, just bring over SF without - // modifying it. - if (DGV == 0) { - // Function does not already exist, simply insert an function signature - // identical to SF into the dest module. - Function *NewDF = Function::Create(SF->getFunctionType(), - SF->getLinkage(), - SF->getName(), Dest); - CopyGVAttributes(NewDF, SF); - - // If the LLVM runtime renamed the function, but it is an externally - // visible symbol, DF must be an existing function with internal linkage. - // Rename it. - if (!NewDF->hasLocalLinkage() && NewDF->getName() != SF->getName()) - ForceRenaming(NewDF, SF->getName()); - - // ... and remember this mapping... - ValueMap[SF] = NewDF; - continue; - } - - // If the visibilities of the symbols disagree and the destination is a - // prototype, take the visibility of its input. - if (DGV->isDeclaration()) - DGV->setVisibility(SF->getVisibility()); - - if (LinkFromSrc) { - if (isa(DGV)) - return Error(Err, "Function-Alias Collision on '" + SF->getName() + - "': symbol multiple defined"); - - // We have a definition of the same name but different type in the - // source module. Copy the prototype to the destination and replace - // uses of the destination's prototype with the new prototype. - Function *NewDF = Function::Create(SF->getFunctionType(), NewLinkage, - SF->getName(), Dest); - CopyGVAttributes(NewDF, SF); - - // Any uses of DF need to change to NewDF, with cast - DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDF, - DGV->getType())); - - // DF will conflict with NewDF because they both had the same. We must - // erase this now so ForceRenaming doesn't assert because DF might - // not have internal linkage. - if (GlobalVariable *Var = dyn_cast(DGV)) - Var->eraseFromParent(); - else - cast(DGV)->eraseFromParent(); - - // If the symbol table renamed the function, but it is an externally - // visible symbol, DF must be an existing function with internal - // linkage. Rename it. - if (NewDF->getName() != SF->getName() && !NewDF->hasLocalLinkage()) - ForceRenaming(NewDF, SF->getName()); - - // Remember this mapping so uses in the source module get remapped - // later by MapValue. - ValueMap[SF] = NewDF; - continue; - } - - // Not "link from source", keep the one in the DestModule and remap the - // input onto it. - - if (isa(DGV)) { - // The only valid mappings are: - // - SF is external declaration, which is effectively a no-op. - // - SF is weak, when we just need to throw SF out. - if (!SF->isDeclaration() && !SF->isWeakForLinker()) - return Error(Err, "Function-Alias Collision on '" + SF->getName() + - "': symbol multiple defined"); - } +void ModuleLinker::linkAppendingVarInit(const AppendingVarInfo &AVI) { + // Merge the initializer. + SmallVector Elements; + if (ConstantArray *I = dyn_cast(AVI.DstInit)) { + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) + Elements.push_back(I->getOperand(i)); + } else { + assert(isa(AVI.DstInit)); + ArrayType *DstAT = cast(AVI.DstInit->getType()); + Type *EltTy = DstAT->getElementType(); + Elements.append(DstAT->getNumElements(), Constant::getNullValue(EltTy)); + } + + Constant *SrcInit = MapValue(AVI.SrcInit, ValueMap, RF_None, &TypeMap); + if (const ConstantArray *I = dyn_cast(SrcInit)) { + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) + Elements.push_back(I->getOperand(i)); + } else { + assert(isa(SrcInit)); + ArrayType *SrcAT = cast(SrcInit->getType()); + Type *EltTy = SrcAT->getElementType(); + Elements.append(SrcAT->getNumElements(), Constant::getNullValue(EltTy)); + } + ArrayType *NewType = cast(AVI.NewGV->getType()->getElementType()); + AVI.NewGV->setInitializer(ConstantArray::get(NewType, Elements)); +} - // Set calculated linkage - DGV->setLinkage(NewLinkage); - // Make sure to remember this mapping. - ValueMap[SF] = ConstantExpr::getBitCast(DGV, SF->getType()); +// linkGlobalInits - Update the initializers in the Dest module now that all +// globals that may be referenced are in Dest. +void ModuleLinker::linkGlobalInits() { + // Loop over all of the globals in the src module, mapping them over as we go + for (Module::const_global_iterator I = SrcM->global_begin(), + E = SrcM->global_end(); I != E; ++I) { + if (!I->hasInitializer()) continue; // Only process initialized GV's. + + // Grab destination global variable. + GlobalVariable *DGV = cast(ValueMap[I]); + // Figure out what the initializer looks like in the dest module. + DGV->setInitializer(MapValue(I->getInitializer(), ValueMap, + RF_None, &TypeMap)); } - return false; } -// LinkFunctionBody - Copy the source function over into the dest function and +// linkFunctionBody - Copy the source function over into the dest function and // fix up references to values. At this point we know that Dest is an external // function, and that Src is not. -static bool LinkFunctionBody(Function *Dest, Function *Src, - ValueToValueMapTy &ValueMap, - std::string *Err) { - assert(Src && Dest && Dest->isDeclaration() && !Src->isDeclaration()); +void ModuleLinker::linkFunctionBody(Function *Dst, Function *Src) { + assert(Src && Dst && Dst->isDeclaration() && !Src->isDeclaration()); // Go through and convert function arguments over, remembering the mapping. - Function::arg_iterator DI = Dest->arg_begin(); + Function::arg_iterator DI = Dst->arg_begin(); for (Function::arg_iterator I = Src->arg_begin(), E = Src->arg_end(); I != E; ++I, ++DI) { - DI->setName(I->getName()); // Copy the name information over... + DI->setName(I->getName()); // Copy the name over. - // Add a mapping to our local map + // Add a mapping to our mapping. ValueMap[I] = DI; } // Splice the body of the source function into the dest function. - Dest->getBasicBlockList().splice(Dest->end(), Src->getBasicBlockList()); + Dst->getBasicBlockList().splice(Dst->end(), Src->getBasicBlockList()); // At this point, all of the instructions and values of the function are now // copied over. The only problem is that they are still referencing values in // the Source function as operands. Loop through all of the operands of the // functions and patch them up to point to the local versions. - for (Function::iterator BB = Dest->begin(), BE = Dest->end(); BB != BE; ++BB) + for (Function::iterator BB = Dst->begin(), BE = Dst->end(); BB != BE; ++BB) for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) - RemapInstruction(I, ValueMap, RF_IgnoreMissingEntries); + RemapInstruction(I, ValueMap, RF_IgnoreMissingEntries, &TypeMap); // There is no need to map the arguments anymore. for (Function::arg_iterator I = Src->arg_begin(), E = Src->arg_end(); I != E; ++I) ValueMap.erase(I); - - return false; } -// LinkFunctionBodies - Link in the function bodies that are defined in the -// source module into the DestModule. This consists basically of copying the -// function over and fixing up references to values. -static bool LinkFunctionBodies(Module *Dest, Module *Src, - ValueToValueMapTy &ValueMap, - std::string *Err) { - - // Loop over all of the functions in the src module, mapping them over as we - // go - for (Module::iterator SF = Src->begin(), E = Src->end(); SF != E; ++SF) { - if (!SF->isDeclaration()) { // No body if function is external - Function *DF = dyn_cast(ValueMap[SF]); // Destination function - - // DF not external SF external? - if (DF && DF->isDeclaration()) - // Only provide the function body if there isn't one already. - if (LinkFunctionBody(DF, SF, ValueMap, Err)) - return true; - } - } - return false; -} - -// LinkAppendingVars - If there were any appending global variables, link them -// together now. Return true on error. -static bool LinkAppendingVars(Module *M, - std::multimap &AppendingVars, - std::string *ErrorMsg) { - if (AppendingVars.empty()) return false; // Nothing to do. - - // Loop over the multimap of appending vars, processing any variables with the - // same name, forming a new appending global variable with both of the - // initializers merged together, then rewrite references to the old variables - // and delete them. - std::vector Inits; - while (AppendingVars.size() > 1) { - // Get the first two elements in the map... - std::multimap::iterator Second = AppendingVars.begin(), First=Second++; - - // If the first two elements are for different names, there is no pair... - // Otherwise there is a pair, so link them together... - if (First->first == Second->first) { - GlobalVariable *G1 = First->second, *G2 = Second->second; - const ArrayType *T1 = cast(G1->getType()->getElementType()); - const ArrayType *T2 = cast(G2->getType()->getElementType()); - - // Check to see that they two arrays agree on type... - if (T1->getElementType() != T2->getElementType()) - return Error(ErrorMsg, - "Appending variables with different element types need to be linked!"); - if (G1->isConstant() != G2->isConstant()) - return Error(ErrorMsg, - "Appending variables linked with different const'ness!"); - - if (G1->getAlignment() != G2->getAlignment()) - return Error(ErrorMsg, - "Appending variables with different alignment need to be linked!"); - - if (G1->getVisibility() != G2->getVisibility()) - return Error(ErrorMsg, - "Appending variables with different visibility need to be linked!"); - - if (G1->getSection() != G2->getSection()) - return Error(ErrorMsg, - "Appending variables with different section name need to be linked!"); - - unsigned NewSize = T1->getNumElements() + T2->getNumElements(); - ArrayType *NewType = ArrayType::get(T1->getElementType(), - NewSize); - - G1->setName(""); // Clear G1's name in case of a conflict! - - // Create the new global variable... - GlobalVariable *NG = - new GlobalVariable(*M, NewType, G1->isConstant(), G1->getLinkage(), - /*init*/0, First->first, 0, G1->isThreadLocal(), - G1->getType()->getAddressSpace()); - - // Propagate alignment, visibility and section info. - CopyGVAttributes(NG, G1); - - // Merge the initializer... - Inits.reserve(NewSize); - if (ConstantArray *I = dyn_cast(G1->getInitializer())) { - for (unsigned i = 0, e = T1->getNumElements(); i != e; ++i) - Inits.push_back(I->getOperand(i)); - } else { - assert(isa(G1->getInitializer())); - Constant *CV = Constant::getNullValue(T1->getElementType()); - for (unsigned i = 0, e = T1->getNumElements(); i != e; ++i) - Inits.push_back(CV); - } - if (ConstantArray *I = dyn_cast(G2->getInitializer())) { - for (unsigned i = 0, e = T2->getNumElements(); i != e; ++i) - Inits.push_back(I->getOperand(i)); - } else { - assert(isa(G2->getInitializer())); - Constant *CV = Constant::getNullValue(T2->getElementType()); - for (unsigned i = 0, e = T2->getNumElements(); i != e; ++i) - Inits.push_back(CV); - } - NG->setInitializer(ConstantArray::get(NewType, Inits)); - Inits.clear(); - - // Replace any uses of the two global variables with uses of the new - // global... - - // FIXME: This should rewrite simple/straight-forward uses such as - // getelementptr instructions to not use the Cast! - G1->replaceAllUsesWith(ConstantExpr::getBitCast(NG, - G1->getType())); - G2->replaceAllUsesWith(ConstantExpr::getBitCast(NG, - G2->getType())); - - // Remove the two globals from the module now... - M->getGlobalList().erase(G1); - M->getGlobalList().erase(G2); - - // Put the new global into the AppendingVars map so that we can handle - // linking of more than two vars... - Second->second = NG; - } - AppendingVars.erase(First); - } - - return false; -} - -static bool ResolveAliases(Module *Dest) { - for (Module::alias_iterator I = Dest->alias_begin(), E = Dest->alias_end(); +void ModuleLinker::linkAliasBodies() { + for (Module::alias_iterator I = SrcM->alias_begin(), E = SrcM->alias_end(); I != E; ++I) - // We can't sue resolveGlobalAlias here because we need to preserve - // bitcasts and GEPs. - if (const Constant *C = I->getAliasee()) { - while (dyn_cast(C)) - C = cast(C)->getAliasee(); - const GlobalValue *GV = dyn_cast(C); - if (C != I && !(GV && GV->isDeclaration())) - I->replaceAllUsesWith(const_cast(C)); + if (Constant *Aliasee = I->getAliasee()) { + GlobalAlias *DA = cast(ValueMap[I]); + DA->setAliasee(MapValue(Aliasee, ValueMap, RF_None, &TypeMap)); } - - return false; } -// LinkModules - This function links two modules together, with the resulting -// left module modified to be the composite of the two input modules. If an -// error occurs, true is returned and ErrorMsg (if not null) is set to indicate -// the problem. Upon failure, the Dest module could be in a modified state, and -// shouldn't be relied on to be consistent. -bool -Linker::LinkModules(Module *Dest, Module *Src, std::string *ErrorMsg) { - assert(Dest != 0 && "Invalid Destination module"); - assert(Src != 0 && "Invalid Source Module"); - - if (Dest->getDataLayout().empty()) { - if (!Src->getDataLayout().empty()) { - Dest->setDataLayout(Src->getDataLayout()); - } else { - std::string DataLayout; - - if (Dest->getEndianness() == Module::AnyEndianness) { - if (Src->getEndianness() == Module::BigEndian) - DataLayout.append("E"); - else if (Src->getEndianness() == Module::LittleEndian) - DataLayout.append("e"); - } - - if (Dest->getPointerSize() == Module::AnyPointerSize) { - if (Src->getPointerSize() == Module::Pointer64) - DataLayout.append(DataLayout.length() == 0 ? "p:64:64" : "-p:64:64"); - else if (Src->getPointerSize() == Module::Pointer32) - DataLayout.append(DataLayout.length() == 0 ? "p:32:32" : "-p:32:32"); - } - Dest->setDataLayout(DataLayout); - } +/// linkNamedMDNodes - Insert all of the named mdnodes in Src into the Dest +/// module. +void ModuleLinker::linkNamedMDNodes() { + for (Module::const_named_metadata_iterator I = SrcM->named_metadata_begin(), + E = SrcM->named_metadata_end(); I != E; ++I) { + NamedMDNode *DestNMD = DstM->getOrInsertNamedMetadata(I->getName()); + // Add Src elements into Dest node. + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) + DestNMD->addOperand(MapValue(I->getOperand(i), ValueMap, + RF_None, &TypeMap)); } +} + +bool ModuleLinker::run() { + assert(DstM && "Null Destination module"); + assert(SrcM && "Null Source Module"); + + // Inherit the target data from the source module if the destination module + // doesn't have one already. + if (DstM->getDataLayout().empty() && !SrcM->getDataLayout().empty()) + DstM->setDataLayout(SrcM->getDataLayout()); // Copy the target triple from the source to dest if the dest's is empty. - if (Dest->getTargetTriple().empty() && !Src->getTargetTriple().empty()) - Dest->setTargetTriple(Src->getTargetTriple()); + if (DstM->getTargetTriple().empty() && !SrcM->getTargetTriple().empty()) + DstM->setTargetTriple(SrcM->getTargetTriple()); - if (!Src->getDataLayout().empty() && !Dest->getDataLayout().empty() && - Src->getDataLayout() != Dest->getDataLayout()) + if (!SrcM->getDataLayout().empty() && !DstM->getDataLayout().empty() && + SrcM->getDataLayout() != DstM->getDataLayout()) errs() << "WARNING: Linking two modules of different data layouts!\n"; - if (!Src->getTargetTriple().empty() && - Dest->getTargetTriple() != Src->getTargetTriple()) { + if (!SrcM->getTargetTriple().empty() && + DstM->getTargetTriple() != SrcM->getTargetTriple()) { errs() << "WARNING: Linking two modules of different target triples: "; - if (!Src->getModuleIdentifier().empty()) - errs() << Src->getModuleIdentifier() << ": "; - errs() << "'" << Src->getTargetTriple() << "' and '" - << Dest->getTargetTriple() << "'\n"; + if (!SrcM->getModuleIdentifier().empty()) + errs() << SrcM->getModuleIdentifier() << ": "; + errs() << "'" << SrcM->getTargetTriple() << "' and '" + << DstM->getTargetTriple() << "'\n"; } // Append the module inline asm string. - if (!Src->getModuleInlineAsm().empty()) { - if (Dest->getModuleInlineAsm().empty()) - Dest->setModuleInlineAsm(Src->getModuleInlineAsm()); + if (!SrcM->getModuleInlineAsm().empty()) { + if (DstM->getModuleInlineAsm().empty()) + DstM->setModuleInlineAsm(SrcM->getModuleInlineAsm()); else - Dest->setModuleInlineAsm(Dest->getModuleInlineAsm()+"\n"+ - Src->getModuleInlineAsm()); + DstM->setModuleInlineAsm(DstM->getModuleInlineAsm()+"\n"+ + SrcM->getModuleInlineAsm()); } // Update the destination module's dependent libraries list with the libraries // from the source module. There's no opportunity for duplicates here as the // Module ensures that duplicate insertions are discarded. - for (Module::lib_iterator SI = Src->lib_begin(), SE = Src->lib_end(); + for (Module::lib_iterator SI = SrcM->lib_begin(), SE = SrcM->lib_end(); SI != SE; ++SI) - Dest->addLibrary(*SI); - - // LinkTypes - Go through the symbol table of the Src module and see if any - // types are named in the src module that are not named in the Dst module. - // Make sure there are no type name conflicts. - if (LinkTypes(Dest, Src, ErrorMsg)) - return true; - - // ValueMap - Mapping of values from what they used to be in Src, to what they - // are now in Dest. ValueToValueMapTy is a ValueMap, which involves some - // overhead due to the use of Value handles which the Linker doesn't actually - // need, but this allows us to reuse the ValueMapper code. - ValueToValueMapTy ValueMap; - - // AppendingVars - Keep track of global variables in the destination module - // with appending linkage. After the module is linked together, they are - // appended and the module is rewritten. - std::multimap AppendingVars; - for (Module::global_iterator I = Dest->global_begin(), E = Dest->global_end(); - I != E; ++I) { - // Add all of the appending globals already in the Dest module to - // AppendingVars. - if (I->hasAppendingLinkage()) - AppendingVars.insert(std::make_pair(I->getName(), I)); - } + DstM->addLibrary(*SI); + + // If the source library's module id is in the dependent library list of the + // destination library, remove it since that module is now linked in. + StringRef ModuleId = SrcM->getModuleIdentifier(); + if (!ModuleId.empty()) + DstM->removeLibrary(sys::path::stem(ModuleId)); + + + // Loop over all of the linked values to compute type mappings. + computeTypeMapping(); - // Insert all of the globals in src into the Dest module... without linking + // Insert all of the globals in src into the DstM module... without linking // initializers (which could refer to functions not yet mapped over). - if (LinkGlobals(Dest, Src, ValueMap, AppendingVars, ErrorMsg)) - return true; + for (Module::global_iterator I = SrcM->global_begin(), + E = SrcM->global_end(); I != E; ++I) + if (linkGlobalProto(I)) + return true; // Link the functions together between the two modules, without doing function - // bodies... this just adds external function prototypes to the Dest + // bodies... this just adds external function prototypes to the DstM // function... We do this so that when we begin processing function bodies, // all of the global values that may be referenced are available in our // ValueMap. - if (LinkFunctionProtos(Dest, Src, ValueMap, ErrorMsg)) - return true; + for (Module::iterator I = SrcM->begin(), E = SrcM->end(); I != E; ++I) + if (linkFunctionProto(I)) + return true; - // If there were any alias, link them now. We really need to do this now, - // because all of the aliases that may be referenced need to be available in - // ValueMap - if (LinkAlias(Dest, Src, ValueMap, ErrorMsg)) return true; - - // Update the initializers in the Dest module now that all globals that may - // be referenced are in Dest. - if (LinkGlobalInits(Dest, Src, ValueMap, ErrorMsg)) return true; - - // Link in the function bodies that are defined in the source module into the - // DestModule. This consists basically of copying the function over and - // fixing up references to values. - if (LinkFunctionBodies(Dest, Src, ValueMap, ErrorMsg)) return true; + // If there were any aliases, link them now. + for (Module::alias_iterator I = SrcM->alias_begin(), + E = SrcM->alias_end(); I != E; ++I) + if (linkAliasProto(I)) + return true; - // If there were any appending global variables, link them together now. - if (LinkAppendingVars(Dest, AppendingVars, ErrorMsg)) return true; + for (unsigned i = 0, e = AppendingVars.size(); i != e; ++i) + linkAppendingVarInit(AppendingVars[i]); + + // Update the initializers in the DstM module now that all globals that may + // be referenced are in DstM. + linkGlobalInits(); + + // Link in the function bodies that are defined in the source module into + // DstM. + for (Module::iterator SF = SrcM->begin(), E = SrcM->end(); SF != E; ++SF) { + if (SF->isDeclaration()) continue; // No body if function is external. + + linkFunctionBody(cast(ValueMap[SF]), SF); + } - // Resolve all uses of aliases with aliasees - if (ResolveAliases(Dest)) return true; + // Resolve all uses of aliases with aliasees. + linkAliasBodies(); - // Remap all of the named mdnoes in Src into the Dest module. We do this + // Remap all of the named mdnoes in Src into the DstM module. We do this // after linking GlobalValues so that MDNodes that reference GlobalValues // are properly remapped. - LinkNamedMDNodes(Dest, Src, ValueMap); - - // If the source library's module id is in the dependent library list of the - // destination library, remove it since that module is now linked in. - const std::string &modId = Src->getModuleIdentifier(); - if (!modId.empty()) - Dest->removeLibrary(sys::path::stem(modId)); + linkNamedMDNodes(); + // Now that all of the types from the source are used, resolve any structs + // copied over to the dest that didn't exist there. + TypeMap.linkDefinedTypeBodies(); + return false; } -// vim: sw=2 +//===----------------------------------------------------------------------===// +// LinkModules entrypoint. +//===----------------------------------------------------------------------===// + +// LinkModules - This function links two modules together, with the resulting +// left module modified to be the composite of the two input modules. If an +// error occurs, true is returned and ErrorMsg (if not null) is set to indicate +// the problem. Upon failure, the Dest module could be in a modified state, and +// shouldn't be relied on to be consistent. +bool Linker::LinkModules(Module *Dest, Module *Src, std::string *ErrorMsg) { + ModuleLinker TheLinker(Dest, Src); + if (TheLinker.run()) { + if (ErrorMsg) *ErrorMsg = TheLinker.ErrorMsg; + return true; + } + + return false; +} Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Sat Jul 9 12:41:24 2011 @@ -20,7 +20,6 @@ #include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/PassManager.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/Intrinsics.h" #include "llvm/IntrinsicInst.h" #include "llvm/InlineAsm.h" @@ -74,29 +73,6 @@ PrivateGlobalPrefix = ""; } }; - /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for - /// any unnamed structure types that are used by the program, and merges - /// external functions with the same name. - /// - class CBackendNameAllUsedStructsAndMergeFunctions : public ModulePass { - public: - static char ID; - CBackendNameAllUsedStructsAndMergeFunctions() - : ModulePass(ID) { - initializeFindUsedTypesPass(*PassRegistry::getPassRegistry()); - } - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - } - - virtual const char *getPassName() const { - return "C backend type canonicalizer"; - } - - virtual bool runOnModule(Module &M); - }; - - char CBackendNameAllUsedStructsAndMergeFunctions::ID = 0; /// CWriter - This class is the main chunk of code that converts an LLVM /// module to a C translation unit. @@ -109,7 +85,7 @@ const MCAsmInfo* TAsm; MCContext *TCtx; const TargetData* TD; - std::map TypeNames; + std::map FPConstantMap; std::set intrinsicPrototypesAlreadyGenerated; std::set ByValParams; @@ -118,6 +94,10 @@ DenseMap AnonValueNumbers; unsigned NextAnonValueNumber; + /// UnnamedStructIDs - This contains a unique ID for each struct that is + /// either anonymous or has no name. + DenseMap UnnamedStructIDs; + public: static char ID; explicit CWriter(formatted_raw_ostream &o) @@ -163,9 +143,9 @@ delete TCtx; delete TAsm; FPConstantMap.clear(); - TypeNames.clear(); ByValParams.clear(); intrinsicPrototypesAlreadyGenerated.clear(); + UnnamedStructIDs.clear(); return false; } @@ -182,6 +162,8 @@ const AttrListPtr &PAL, const PointerType *Ty); + std::string getStructName(const StructType *ST); + /// writeOperandDeref - Print the result of dereferencing the specified /// operand with '*'. This is equivalent to printing '*' then using /// writeOperand, but avoids excess syntax in some cases. @@ -214,8 +196,8 @@ /// intrinsics which need to be explicitly defined in the CBackend. void printIntrinsicDefinition(const Function &F, raw_ostream &Out); - void printModuleTypes(const TypeSymbolTable &ST); - void printContainedStructs(const Type *Ty, std::set &); + void printModuleTypes(); + void printContainedStructs(const Type *Ty, SmallPtrSet &); void printFloatingPointConstants(Function &F); void printFloatingPointConstants(const Constant *C); void printFunctionSignature(const Function *F, bool Prototype); @@ -359,6 +341,7 @@ char CWriter::ID = 0; + static std::string CBEMangle(const std::string &S) { std::string Result; @@ -374,90 +357,14 @@ return Result; } - -/// This method inserts names for any unnamed structure types that are used by -/// the program, and removes names from structure types that are not used by the -/// program. -/// -bool CBackendNameAllUsedStructsAndMergeFunctions::runOnModule(Module &M) { - // Get a set of types that are used by the program... - SetVector UT = getAnalysis().getTypes(); - - // Loop over the module symbol table, removing types from UT that are - // already named, and removing names for types that are not used. - // - TypeSymbolTable &TST = M.getTypeSymbolTable(); - for (TypeSymbolTable::iterator TI = TST.begin(), TE = TST.end(); - TI != TE; ) { - TypeSymbolTable::iterator I = TI++; - - // If this isn't a struct or array type, remove it from our set of types - // to name. This simplifies emission later. - if (!I->second->isStructTy() && !I->second->isOpaqueTy() && - !I->second->isArrayTy()) { - TST.remove(I); - } else { - // If this is not used, remove it from the symbol table. - if (!UT.count(I->second)) - TST.remove(I); - else - UT.remove(I->second); // Only keep one name for this type. - } - } - - // UT now contains types that are not named. Loop over it, naming - // structure types. - // - bool Changed = false; - unsigned RenameCounter = 0; - for (SetVector::const_iterator I = UT.begin(), E = UT.end(); - I != E; ++I) - if ((*I)->isStructTy() || (*I)->isArrayTy()) { - while (M.addTypeName("unnamed"+utostr(RenameCounter), *I)) - ++RenameCounter; - Changed = true; - } - - - // Loop over all external functions and globals. If we have two with - // identical names, merge them. - // FIXME: This code should disappear when we don't allow values with the same - // names when they have different types! - std::map ExtSymbols; - for (Module::iterator I = M.begin(), E = M.end(); I != E;) { - Function *GV = I++; - if (GV->isDeclaration() && GV->hasName()) { - std::pair::iterator, bool> X - = ExtSymbols.insert(std::make_pair(GV->getName(), GV)); - if (!X.second) { - // Found a conflict, replace this global with the previous one. - GlobalValue *OldGV = X.first->second; - GV->replaceAllUsesWith(ConstantExpr::getBitCast(OldGV, GV->getType())); - GV->eraseFromParent(); - Changed = true; - } - } - } - // Do the same for globals. - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E;) { - GlobalVariable *GV = I++; - if (GV->isDeclaration() && GV->hasName()) { - std::pair::iterator, bool> X - = ExtSymbols.insert(std::make_pair(GV->getName(), GV)); - if (!X.second) { - // Found a conflict, replace this global with the previous one. - GlobalValue *OldGV = X.first->second; - GV->replaceAllUsesWith(ConstantExpr::getBitCast(OldGV, GV->getType())); - GV->eraseFromParent(); - Changed = true; - } - } - } - - return Changed; +std::string CWriter::getStructName(const StructType *ST) { + if (!ST->isAnonymous() && !ST->getName().empty()) + return CBEMangle("l_"+ST->getName().str()); + + return "l_unnamed_" + utostr(UnnamedStructIDs[ST]); } + /// printStructReturnPointerFunctionType - This is like printType for a struct /// return type, except, instead of printing the type as void (*)(Struct*, ...) /// print it as "Struct (*)(...)", for struct return functions. @@ -471,7 +378,7 @@ bool PrintedType = false; FunctionType::param_iterator I = FTy->param_begin(), E = FTy->param_end(); - const Type *RetTy = cast(I->get())->getElementType(); + const Type *RetTy = cast(*I)->getElementType(); unsigned Idx = 1; for (++I, ++Idx; I != E; ++I, ++Idx) { if (PrintedType) @@ -559,12 +466,6 @@ return Out; } - // Check to see if the type is named. - if (!IgnoreName || Ty->isOpaqueTy()) { - std::map::iterator I = TypeNames.find(Ty); - if (I != TypeNames.end()) return Out << I->second << ' ' << NameSoFar; - } - switch (Ty->getTypeID()) { case Type::FunctionTyID: { const FunctionType *FTy = cast(Ty); @@ -599,6 +500,11 @@ } case Type::StructTyID: { const StructType *STy = cast(Ty); + + // Check to see if the type is named. + if (!IgnoreName) + return Out << getStructName(STy) << ' ' << NameSoFar; + Out << NameSoFar + " {\n"; unsigned Idx = 0; for (StructType::element_iterator I = STy->element_begin(), @@ -639,12 +545,6 @@ return Out << "; }"; } - case Type::OpaqueTyID: { - std::string TyName = "struct opaque_" + itostr(OpaqueCounter++); - assert(TypeNames.find(Ty) == TypeNames.end()); - TypeNames[Ty] = TyName; - return Out << TyName << ' ' << NameSoFar; - } default: llvm_unreachable("Unhandled case in getTypeProps!"); } @@ -1829,8 +1729,8 @@ << "/* End Module asm statements */\n"; } - // Loop over the symbol table, emitting all named constants... - printModuleTypes(M.getTypeSymbolTable()); + // Loop over the symbol table, emitting all named constants. + printModuleTypes(); // Global variable declarations... if (!M.global_empty()) { @@ -2119,11 +2019,10 @@ } - /// printSymbolTable - Run through symbol table looking for type names. If a /// type name is found, emit its declaration... /// -void CWriter::printModuleTypes(const TypeSymbolTable &TST) { +void CWriter::printModuleTypes() { Out << "/* Helper union for bitcasts */\n"; Out << "typedef union {\n"; Out << " unsigned int Int32;\n"; @@ -2132,46 +2031,42 @@ Out << " double Double;\n"; Out << "} llvmBitCastUnion;\n"; - // We are only interested in the type plane of the symbol table. - TypeSymbolTable::const_iterator I = TST.begin(); - TypeSymbolTable::const_iterator End = TST.end(); + // Get all of the struct types used in the module. + std::vector StructTypes; + TheModule->findUsedStructTypes(StructTypes); - // If there are no type names, exit early. - if (I == End) return; + if (StructTypes.empty()) return; - // Print out forward declarations for structure types before anything else! Out << "/* Structure forward decls */\n"; - for (; I != End; ++I) { - std::string Name = "struct " + CBEMangle("l_"+I->first); - Out << Name << ";\n"; - TypeNames.insert(std::make_pair(I->second, Name)); - } - Out << '\n'; + unsigned NextTypeID = 0; + + // If any of them are missing names, add a unique ID to UnnamedStructIDs. + // Print out forward declarations for structure types. + for (unsigned i = 0, e = StructTypes.size(); i != e; ++i) { + StructType *ST = StructTypes[i]; - // Now we can print out typedefs. Above, we guaranteed that this can only be - // for struct or opaque types. - Out << "/* Typedefs */\n"; - for (I = TST.begin(); I != End; ++I) { - std::string Name = CBEMangle("l_"+I->first); - Out << "typedef "; - printType(Out, I->second, false, Name); - Out << ";\n"; + if (ST->isAnonymous() || ST->getName().empty()) + UnnamedStructIDs[ST] = NextTypeID++; + + std::string Name = getStructName(ST); + + Out << "typedef struct " << Name << ' ' << Name << ";\n"; } Out << '\n'; - // Keep track of which structures have been printed so far... - std::set StructPrinted; + // Keep track of which structures have been printed so far. + SmallPtrSet StructPrinted; // Loop over all structures then push them into the stack so they are // printed in the correct order. // Out << "/* Structure contents */\n"; - for (I = TST.begin(); I != End; ++I) - if (I->second->isStructTy() || I->second->isArrayTy()) + for (unsigned i = 0, e = StructTypes.size(); i != e; ++i) + if (StructTypes[i]->isStructTy()) // Only print out used types! - printContainedStructs(I->second, StructPrinted); + printContainedStructs(StructTypes[i], StructPrinted); } // Push the struct onto the stack and recursively push all structs @@ -2180,7 +2075,7 @@ // TODO: Make this work properly with vector types // void CWriter::printContainedStructs(const Type *Ty, - std::set &StructPrinted) { + SmallPtrSet &StructPrinted) { // Don't walk through pointers. if (Ty->isPointerTy() || Ty->isPrimitiveType() || Ty->isIntegerTy()) return; @@ -2190,14 +2085,13 @@ E = Ty->subtype_end(); I != E; ++I) printContainedStructs(*I, StructPrinted); - if (Ty->isStructTy() || Ty->isArrayTy()) { + if (const StructType *ST = dyn_cast(Ty)) { // Check to see if we have already printed this struct. - if (StructPrinted.insert(Ty).second) { - // Print structure type out. - std::string Name = TypeNames[Ty]; - printType(Out, Ty, false, Name, true); - Out << ";\n\n"; - } + if (!StructPrinted.insert(Ty)) return; + + // Print structure type out. + printType(Out, ST, false, getStructName(ST), true); + Out << ";\n\n"; } } @@ -2847,10 +2741,12 @@ Out << "U" << type << (isMax ? "_MAX" : "0"); } +#ifndef NDEBUG static bool isSupportedIntegerSize(const IntegerType &T) { return T.getBitWidth() == 8 || T.getBitWidth() == 16 || T.getBitWidth() == 32 || T.getBitWidth() == 64; } +#endif void CWriter::printIntrinsicDefinition(const Function &F, raw_ostream &Out) { const FunctionType *funT = F.getFunctionType(); @@ -3704,7 +3600,6 @@ PM.add(createGCLoweringPass()); PM.add(createLowerInvokePass()); PM.add(createCFGSimplificationPass()); // clean up after lower invoke. - PM.add(new CBackendNameAllUsedStructsAndMergeFunctions()); PM.add(new CWriter(o)); PM.add(createGCInfoDeleter()); return false; Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Sat Jul 9 12:41:24 2011 @@ -22,7 +22,7 @@ #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/PassManager.h" -#include "llvm/TypeSymbolTable.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/CommandLine.h" @@ -33,7 +33,7 @@ #include "llvm/Config/config.h" #include #include - +#include using namespace llvm; static cl::opt @@ -193,26 +193,11 @@ case Type::ArrayTyID: return "array_"; case Type::PointerTyID: return "ptr_"; case Type::VectorTyID: return "packed_"; - case Type::OpaqueTyID: return "opaque_"; default: return "other_"; } return "unknown_"; } -// Looks up the type in the symbol table and returns a pointer to its name or -// a null pointer if it wasn't found. Note that this isn't the same as the -// Mode::getTypeName function which will return an empty string, not a null -// pointer if the name is not found. -static const std::string * -findTypeName(const TypeSymbolTable& ST, const Type* Ty) { - TypeSymbolTable::const_iterator TI = ST.begin(); - TypeSymbolTable::const_iterator TE = ST.end(); - for (;TI != TE; ++TI) - if (TI->second == Ty) - return &(TI->first); - return 0; -} - void CppWriter::error(const std::string& msg) { report_fatal_error(msg); } @@ -384,18 +369,20 @@ case Type::StructTyID: prefix = "StructTy_"; break; case Type::ArrayTyID: prefix = "ArrayTy_"; break; case Type::PointerTyID: prefix = "PointerTy_"; break; - case Type::OpaqueTyID: prefix = "OpaqueTy_"; break; case Type::VectorTyID: prefix = "VectorTy_"; break; default: prefix = "OtherTy_"; break; // prevent breakage } // See if the type has a name in the symboltable and build accordingly - const std::string* tName = findTypeName(TheModule->getTypeSymbolTable(), Ty); std::string name; - if (tName) - name = std::string(prefix) + *tName; - else - name = std::string(prefix) + utostr(uniqueNum++); + if (const StructType *STy = dyn_cast(Ty)) + if (STy->hasName()) + name = STy->getName(); + + if (name.empty()) + name = utostr(uniqueNum++); + + name = std::string(prefix) + name; sanitize(name); // Save the name @@ -590,8 +577,18 @@ Out << ");"; nl(Out); } - Out << "StructType* " << typeName << " = StructType::get(" - << typeName << "_fields, /*isPacked=*/" + + Out << "StructType *" << typeName << " = "; + if (ST->isAnonymous()) { + Out << "StructType::get(" << "mod->getContext(), "; + } else { + Out << "StructType::createNamed(mod->getContext(), \""; + printEscapedString(ST->getName()); + Out << "\");"; + nl(Out); + Out << typeName << "->setBody("; + } + Out << typeName << "_fields, /*isPacked=*/" << (ST->isPacked() ? "true" : "false") << ");"; nl(Out); break; @@ -629,25 +626,10 @@ nl(Out); break; } - case Type::OpaqueTyID: { - Out << "OpaqueType* " << typeName; - Out << " = OpaqueType::get(mod->getContext());"; - nl(Out); - break; - } default: error("Invalid TypeID"); } - // If the type had a name, make sure we recreate it. - const std::string* progTypeName = - findTypeName(TheModule->getTypeSymbolTable(),Ty); - if (progTypeName) { - Out << "mod->addTypeName(\"" << *progTypeName << "\", " - << typeName << ");"; - nl(Out); - } - // Pop us off the type stack TypeStack.pop_back(); @@ -670,7 +652,6 @@ case Type::StructTyID: Out << "StructType"; break; case Type::VectorTyID: Out << "VectorType"; break; case Type::PointerTyID: Out << "PointerType"; break; - case Type::OpaqueTyID: Out << "OpaqueType"; break; default: Out << "NoSuchDerivedType"; break; } Out << ">(" << I->second << "_fwd.get());"; @@ -695,26 +676,7 @@ } void CppWriter::printTypes(const Module* M) { - // Walk the symbol table and print out all its types - const TypeSymbolTable& symtab = M->getTypeSymbolTable(); - for (TypeSymbolTable::const_iterator TI = symtab.begin(), TE = symtab.end(); - TI != TE; ++TI) { - - // For primitive types and types already defined, just add a name - TypeMap::const_iterator TNI = TypeNames.find(TI->second); - if (TI->second->isIntegerTy() || TI->second->isPrimitiveType() || - TNI != TypeNames.end()) { - Out << "mod->addTypeName(\""; - printEscapedString(TI->first); - Out << "\", " << getCppName(TI->second) << ");"; - nl(Out); - // For everything else, define the type - } else { - printType(TI->second); - } - } - - // Add all of the global variables to the value table... + // Add all of the global variables to the value table. for (Module::const_global_iterator I = TheModule->global_begin(), E = TheModule->global_end(); I != E; ++I) { if (I->hasInitializer()) @@ -1959,8 +1921,8 @@ Out << "}\n"; } -void CppWriter::printType(const std::string& fname, - const std::string& typeName) { +void CppWriter::printType(const std::string &fname, + const std::string &typeName) { const Type* Ty = TheModule->getTypeByName(typeName); if (!Ty) { error(std::string("Type '") + typeName + "' not found in input module"); Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Sat Jul 9 12:41:24 2011 @@ -42,6 +42,7 @@ //===----------------------------------------------------------------------===// StructLayout::StructLayout(const StructType *ST, const TargetData &TD) { + assert(!ST->isOpaque() && "Cannot get layout of opaque structs"); StructAlignment = 0; StructSize = 0; NumElements = ST->getNumElements(); @@ -313,52 +314,16 @@ namespace { -class StructLayoutMap : public AbstractTypeUser { +class StructLayoutMap { typedef DenseMap LayoutInfoTy; LayoutInfoTy LayoutInfo; - void RemoveEntry(LayoutInfoTy::iterator I, bool WasAbstract) { - I->second->~StructLayout(); - free(I->second); - if (WasAbstract) - I->first->removeAbstractTypeUser(this); - LayoutInfo.erase(I); - } - - - /// refineAbstractType - The callback method invoked when an abstract type is - /// resolved to another type. An object must override this method to update - /// its internal state to reference NewType instead of OldType. - /// - virtual void refineAbstractType(const DerivedType *OldTy, - const Type *) { - LayoutInfoTy::iterator I = LayoutInfo.find(cast(OldTy)); - assert(I != LayoutInfo.end() && "Using type but not in map?"); - RemoveEntry(I, true); - } - - /// typeBecameConcrete - The other case which AbstractTypeUsers must be aware - /// of is when a type makes the transition from being abstract (where it has - /// clients on its AbstractTypeUsers list) to concrete (where it does not). - /// This method notifies ATU's when this occurs for a type. - /// - virtual void typeBecameConcrete(const DerivedType *AbsTy) { - LayoutInfoTy::iterator I = LayoutInfo.find(cast(AbsTy)); - assert(I != LayoutInfo.end() && "Using type but not in map?"); - RemoveEntry(I, true); - } - public: virtual ~StructLayoutMap() { // Remove any layouts. - for (LayoutInfoTy::iterator - I = LayoutInfo.begin(), E = LayoutInfo.end(); I != E; ++I) { - const Type *Key = I->first; + for (LayoutInfoTy::iterator I = LayoutInfo.begin(), E = LayoutInfo.end(); + I != E; ++I) { StructLayout *Value = I->second; - - if (Key->isAbstract()) - Key->removeAbstractTypeUser(this); - Value->~StructLayout(); free(Value); } @@ -367,7 +332,10 @@ void InvalidateEntry(const StructType *Ty) { LayoutInfoTy::iterator I = LayoutInfo.find(Ty); if (I == LayoutInfo.end()) return; - RemoveEntry(I, Ty->isAbstract()); + + I->second->~StructLayout(); + free(I->second); + LayoutInfo.erase(I); } StructLayout *&operator[](const StructType *STy) { @@ -404,9 +372,6 @@ new (L) StructLayout(Ty, *this); - if (Ty->isAbstract()) - Ty->addAbstractTypeUser(STM); - return L; } Modified: llvm/trunk/lib/Transforms/IPO/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/CMakeLists.txt?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/IPO/CMakeLists.txt Sat Jul 9 12:41:24 2011 @@ -2,7 +2,6 @@ ArgumentPromotion.cpp ConstantMerge.cpp DeadArgumentElimination.cpp - DeadTypeElimination.cpp ExtractGV.cpp FunctionAttrs.cpp GlobalDCE.cpp Removed: llvm/trunk/lib/Transforms/IPO/DeadTypeElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadTypeElimination.cpp?rev=134828&view=auto ============================================================================== --- llvm/trunk/lib/Transforms/IPO/DeadTypeElimination.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/DeadTypeElimination.cpp (removed) @@ -1,112 +0,0 @@ -//===- DeadTypeElimination.cpp - Eliminate unused types for symbol table --===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This pass is used to cleanup the output of GCC. It eliminate names for types -// that are unused in the entire translation unit, using the FindUsedTypes pass. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "deadtypeelim" -#include "llvm/Transforms/IPO.h" -#include "llvm/Analysis/FindUsedTypes.h" -#include "llvm/Module.h" -#include "llvm/TypeSymbolTable.h" -#include "llvm/DerivedTypes.h" -#include "llvm/ADT/Statistic.h" -using namespace llvm; - -STATISTIC(NumKilled, "Number of unused typenames removed from symtab"); - -namespace { - struct DTE : public ModulePass { - static char ID; // Pass identification, replacement for typeid - DTE() : ModulePass(ID) { - initializeDTEPass(*PassRegistry::getPassRegistry()); - } - - // doPassInitialization - For this pass, it removes global symbol table - // entries for primitive types. These are never used for linking in GCC and - // they make the output uglier to look at, so we nuke them. - // - // Also, initialize instance variables. - // - bool runOnModule(Module &M); - - // getAnalysisUsage - This function needs FindUsedTypes to do its job... - // - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - } - }; -} - -char DTE::ID = 0; -INITIALIZE_PASS_BEGIN(DTE, "deadtypeelim", "Dead Type Elimination", - false, false) -INITIALIZE_PASS_DEPENDENCY(FindUsedTypes) -INITIALIZE_PASS_END(DTE, "deadtypeelim", "Dead Type Elimination", false, false) - -ModulePass *llvm::createDeadTypeEliminationPass() { - return new DTE(); -} - - -// ShouldNukeSymtabEntry - Return true if this module level symbol table entry -// should be eliminated. -// -static inline bool ShouldNukeSymtabEntry(const Type *Ty){ - // Nuke all names for primitive types! - if (Ty->isPrimitiveType() || Ty->isIntegerTy()) - return true; - - // Nuke all pointers to primitive types as well... - if (const PointerType *PT = dyn_cast(Ty)) - if (PT->getElementType()->isPrimitiveType() || - PT->getElementType()->isIntegerTy()) - return true; - - return false; -} - -// run - For this pass, it removes global symbol table entries for primitive -// types. These are never used for linking in GCC and they make the output -// uglier to look at, so we nuke them. Also eliminate types that are never used -// in the entire program as indicated by FindUsedTypes. -// -bool DTE::runOnModule(Module &M) { - bool Changed = false; - - TypeSymbolTable &ST = M.getTypeSymbolTable(); - const SetVector &T = getAnalysis().getTypes(); - std::set UsedTypes(T.begin(), T.end()); - - // Check the symbol table for superfluous type entries... - // - // Grab the 'type' plane of the module symbol... - TypeSymbolTable::iterator TI = ST.begin(); - TypeSymbolTable::iterator TE = ST.end(); - while ( TI != TE ) { - // If this entry should be unconditionally removed, or if we detect that - // the type is not used, remove it. - const Type *RHS = TI->second; - if (ShouldNukeSymtabEntry(RHS) || !UsedTypes.count(RHS)) { - ST.remove(TI++); - ++NumKilled; - Changed = true; - } else { - ++TI; - // We only need to leave one name for each type. - UsedTypes.erase(RHS); - } - } - - return Changed; -} - -// vim: sw=2 Modified: llvm/trunk/lib/Transforms/IPO/IPO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPO.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/IPO.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/IPO.cpp Sat Jul 9 12:41:24 2011 @@ -25,7 +25,6 @@ initializeConstantMergePass(Registry); initializeDAEPass(Registry); initializeDAHPass(Registry); - initializeDTEPass(Registry); initializeFunctionAttrsPass(Registry); initializeGlobalDCEPass(Registry); initializeGlobalOptPass(Registry); @@ -63,10 +62,6 @@ unwrap(PM)->add(createDeadArgEliminationPass()); } -void LLVMAddDeadTypeEliminationPass(LLVMPassManagerRef PM) { - unwrap(PM)->add(createDeadTypeEliminationPass()); -} - void LLVMAddFunctionAttrsPass(LLVMPassManagerRef PM) { unwrap(PM)->add(createFunctionAttrsPass()); } Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Sat Jul 9 12:41:24 2011 @@ -218,7 +218,6 @@ llvm_unreachable("Unknown type!"); // Fall through in Release mode. case Type::IntegerTyID: - case Type::OpaqueTyID: case Type::VectorTyID: // Ty1 == Ty2 would have returned true earlier. return false; Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Sat Jul 9 12:41:24 2011 @@ -28,8 +28,8 @@ #include "llvm/Pass.h" #include "llvm/Analysis/DebugInfo.h" #include "llvm/ValueSymbolTable.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" using namespace llvm; @@ -174,13 +174,19 @@ } } -// Strip the symbol table of its names. -static void StripTypeSymtab(TypeSymbolTable &ST, bool PreserveDbgInfo) { - for (TypeSymbolTable::iterator TI = ST.begin(), E = ST.end(); TI != E; ) { - if (PreserveDbgInfo && StringRef(TI->first).startswith("llvm.dbg")) - ++TI; - else - ST.remove(TI++); +// Strip any named types of their names. +static void StripTypeNames(Module &M, bool PreserveDbgInfo) { + std::vector StructTypes; + M.findUsedStructTypes(StructTypes); + + for (unsigned i = 0, e = StructTypes.size(); i != e; ++i) { + StructType *STy = StructTypes[i]; + if (STy->isAnonymous() || STy->getName().empty()) continue; + + if (PreserveDbgInfo && STy->getName().startswith("llvm.dbg")) + continue; + + STy->setName(""); } } @@ -221,7 +227,7 @@ } // Remove all names from types. - StripTypeSymtab(M.getTypeSymbolTable(), PreserveDbgInfo); + StripTypeNames(M, PreserveDbgInfo); return true; } Modified: llvm/trunk/lib/Transforms/Utils/CloneModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneModule.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CloneModule.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CloneModule.cpp Sat Jul 9 12:41:24 2011 @@ -15,7 +15,6 @@ #include "llvm/Transforms/Utils/Cloning.h" #include "llvm/Module.h" #include "llvm/DerivedTypes.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/Constant.h" #include "llvm/Transforms/Utils/ValueMapper.h" using namespace llvm; @@ -32,20 +31,13 @@ return CloneModule(M, VMap); } -Module *llvm::CloneModule(const Module *M, - ValueToValueMapTy &VMap) { - // First off, we need to create the new module... +Module *llvm::CloneModule(const Module *M, ValueToValueMapTy &VMap) { + // First off, we need to create the new module. Module *New = new Module(M->getModuleIdentifier(), M->getContext()); New->setDataLayout(M->getDataLayout()); New->setTargetTriple(M->getTargetTriple()); New->setModuleInlineAsm(M->getModuleInlineAsm()); - - // Copy all of the type symbol table entries over. - const TypeSymbolTable &TST = M->getTypeSymbolTable(); - for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end(); - TI != TE; ++TI) - New->addTypeName(TI->first, TI->second); - + // Copy all of the dependent libraries over. for (Module::lib_iterator I = M->lib_begin(), E = M->lib_end(); I != E; ++I) New->addLibrary(*I); @@ -88,8 +80,7 @@ I != E; ++I) { GlobalVariable *GV = cast(VMap[I]); if (I->hasInitializer()) - GV->setInitializer(cast(MapValue(I->getInitializer(), - VMap, RF_None))); + GV->setInitializer(MapValue(I->getInitializer(), VMap)); GV->setLinkage(I->getLinkage()); GV->setThreadLocal(I->isThreadLocal()); GV->setConstant(I->isConstant()); @@ -119,8 +110,8 @@ I != E; ++I) { GlobalAlias *GA = cast(VMap[I]); GA->setLinkage(I->getLinkage()); - if (const Constant* C = I->getAliasee()) - GA->setAliasee(cast(MapValue(C, VMap, RF_None))); + if (const Constant *C = I->getAliasee()) + GA->setAliasee(MapValue(C, VMap)); } // And named metadata.... @@ -129,8 +120,7 @@ const NamedMDNode &NMD = *I; NamedMDNode *NewNMD = New->getOrInsertNamedMetadata(NMD.getName()); for (unsigned i = 0, e = NMD.getNumOperands(); i != e; ++i) - NewNMD->addOperand(cast(MapValue(NMD.getOperand(i), VMap, - RF_None))); + NewNMD->addOperand(MapValue(NMD.getOperand(i), VMap)); } return New; Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Sat Jul 9 12:41:24 2011 @@ -66,7 +66,7 @@ Constant *AbortFn; // Used for expensive EH support. - const Type *JBLinkTy; + StructType *JBLinkTy; GlobalVariable *JBListHead; Constant *SetJmpFn, *LongJmpFn, *StackSaveFn, *StackRestoreFn; bool useExpensiveEHSupport; @@ -120,24 +120,16 @@ // doInitialization - Make sure that there is a prototype for abort in the // current module. bool LowerInvoke::doInitialization(Module &M) { - const Type *VoidPtrTy = - Type::getInt8PtrTy(M.getContext()); + const Type *VoidPtrTy = Type::getInt8PtrTy(M.getContext()); if (useExpensiveEHSupport) { // Insert a type for the linked list of jump buffers. unsigned JBSize = TLI ? TLI->getJumpBufSize() : 0; JBSize = JBSize ? JBSize : 200; - const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JBSize); + Type *JmpBufTy = ArrayType::get(VoidPtrTy, JBSize); - { // The type is recursive, so use a type holder. - std::vector Elements; - Elements.push_back(JmpBufTy); - OpaqueType *OT = OpaqueType::get(M.getContext()); - Elements.push_back(PointerType::getUnqual(OT)); - PATypeHolder JBLType(StructType::get(M.getContext(), Elements)); - OT->refineAbstractTypeTo(JBLType.get()); // Complete the cycle. - JBLinkTy = JBLType.get(); - M.addTypeName("llvm.sjljeh.jmpbufty", JBLinkTy); - } + JBLinkTy = StructType::createNamed(M.getContext(), "llvm.sjljeh.jmpbufty"); + Type *Elts[] = { JmpBufTy, PointerType::getUnqual(JBLinkTy) }; + JBLinkTy->setBody(Elts); const Type *PtrJBList = PointerType::getUnqual(JBLinkTy); Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Sat Jul 9 12:41:24 2011 @@ -13,16 +13,17 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/Utils/ValueMapper.h" -#include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Instructions.h" #include "llvm/Metadata.h" -#include "llvm/ADT/SmallVector.h" using namespace llvm; -Value *llvm::MapValue(const Value *V, ValueToValueMapTy &VM, - RemapFlags Flags) { +// Out of line method to get vtable etc for class. +void ValueMapTypeRemapper::Anchor() {} + +Value *llvm::MapValue(const Value *V, ValueToValueMapTy &VM, RemapFlags Flags, + ValueMapTypeRemapper *TypeMapper) { ValueToValueMapTy::iterator I = VM.find(V); // If the value already exists in the map, use it. @@ -46,14 +47,14 @@ // Check all operands to see if any need to be remapped. for (unsigned i = 0, e = MD->getNumOperands(); i != e; ++i) { Value *OP = MD->getOperand(i); - if (OP == 0 || MapValue(OP, VM, Flags) == OP) continue; + if (OP == 0 || MapValue(OP, VM, Flags, TypeMapper) == OP) continue; // Ok, at least one operand needs remapping. SmallVector Elts; Elts.reserve(MD->getNumOperands()); for (i = 0; i != e; ++i) { Value *Op = MD->getOperand(i); - Elts.push_back(Op ? MapValue(Op, VM, Flags) : 0); + Elts.push_back(Op ? MapValue(Op, VM, Flags, TypeMapper) : 0); } MDNode *NewMD = MDNode::get(V->getContext(), Elts); Dummy->replaceAllUsesWith(NewMD); @@ -76,51 +77,75 @@ return 0; if (BlockAddress *BA = dyn_cast(C)) { - Function *F = cast(MapValue(BA->getFunction(), VM, Flags)); + Function *F = + cast(MapValue(BA->getFunction(), VM, Flags, TypeMapper)); BasicBlock *BB = cast_or_null(MapValue(BA->getBasicBlock(), VM, - Flags)); + Flags, TypeMapper)); return VM[V] = BlockAddress::get(F, BB ? BB : BA->getBasicBlock()); } - for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) { - Value *Op = C->getOperand(i); - Value *Mapped = MapValue(Op, VM, Flags); - if (Mapped == C) continue; - - // Okay, the operands don't all match. We've already processed some or all - // of the operands, set them up now. - std::vector Ops; - Ops.reserve(C->getNumOperands()); - for (unsigned j = 0; j != i; ++j) - Ops.push_back(cast(C->getOperand(i))); + // Otherwise, we have some other constant to remap. Start by checking to see + // if all operands have an identity remapping. + unsigned OpNo = 0, NumOperands = C->getNumOperands(); + Value *Mapped = 0; + for (; OpNo != NumOperands; ++OpNo) { + Value *Op = C->getOperand(OpNo); + Mapped = MapValue(Op, VM, Flags, TypeMapper); + if (Mapped != C) break; + } + + // See if the type mapper wants to remap the type as well. + Type *NewTy = C->getType(); + if (TypeMapper) + NewTy = TypeMapper->remapType(NewTy); + + // If the result type and all operands match up, then just insert an identity + // mapping. + if (OpNo == NumOperands && NewTy == C->getType()) + return VM[V] = C; + + // Okay, we need to create a new constant. We've already processed some or + // all of the operands, set them all up now. + SmallVector Ops; + Ops.reserve(NumOperands); + for (unsigned j = 0; j != OpNo; ++j) + Ops.push_back(cast(C->getOperand(j))); + + // If one of the operands mismatch, push it and the other mapped operands. + if (OpNo != NumOperands) { Ops.push_back(cast(Mapped)); - + // Map the rest of the operands that aren't processed yet. - for (++i; i != e; ++i) - Ops.push_back(cast(MapValue(C->getOperand(i), VM, Flags))); - - if (ConstantExpr *CE = dyn_cast(C)) - return VM[V] = CE->getWithOperands(Ops); - if (ConstantArray *CA = dyn_cast(C)) - return VM[V] = ConstantArray::get(CA->getType(), Ops); - if (ConstantStruct *CS = dyn_cast(C)) - return VM[V] = ConstantStruct::get(CS->getType(), Ops); - assert(isa(C) && "Unknown mapped constant type"); - return VM[V] = ConstantVector::get(Ops); + for (++OpNo; OpNo != NumOperands; ++OpNo) + Ops.push_back(MapValue(cast(C->getOperand(OpNo)), VM, + Flags, TypeMapper)); } - - // If we reach here, all of the operands of the constant match. - return VM[V] = C; + + if (ConstantExpr *CE = dyn_cast(C)) + return VM[V] = CE->getWithOperands(Ops, NewTy); + if (isa(C)) + return VM[V] = ConstantArray::get(cast(NewTy), Ops); + if (isa(C)) + return VM[V] = ConstantStruct::get(cast(NewTy), Ops); + if (isa(C)) + return VM[V] = ConstantVector::get(Ops); + // If this is a no-operand constant, it must be because the type was remapped. + if (isa(C)) + return VM[V] = UndefValue::get(NewTy); + if (isa(C)) + return VM[V] = ConstantAggregateZero::get(NewTy); + assert(isa(C)); + return VM[V] = ConstantPointerNull::get(cast(NewTy)); } /// RemapInstruction - Convert the instruction operands from referencing the /// current values into those specified by VMap. /// void llvm::RemapInstruction(Instruction *I, ValueToValueMapTy &VMap, - RemapFlags Flags) { + RemapFlags Flags, ValueMapTypeRemapper *TypeMapper){ // Remap operands. for (User::op_iterator op = I->op_begin(), E = I->op_end(); op != E; ++op) { - Value *V = MapValue(*op, VMap, Flags); + Value *V = MapValue(*op, VMap, Flags, TypeMapper); // If we aren't ignoring missing entries, assert that something happened. if (V != 0) *op = V; @@ -147,9 +172,13 @@ I->getAllMetadata(MDs); for (SmallVectorImpl >::iterator MI = MDs.begin(), ME = MDs.end(); MI != ME; ++MI) { - Value *Old = MI->second; - Value *New = MapValue(Old, VMap, Flags); + MDNode *Old = MI->second; + MDNode *New = MapValue(Old, VMap, Flags, TypeMapper); if (New != Old) - I->setMetadata(MI->first, cast(New)); + I->setMetadata(MI->first, New); } + + // If the instruction's type is being remapped, do so now. + if (TypeMapper) + I->mutateType(TypeMapper->remapType(I->getType())); } Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Sat Jul 9 12:41:24 2011 @@ -26,8 +26,7 @@ #include "llvm/Operator.h" #include "llvm/Module.h" #include "llvm/ValueSymbolTable.h" -#include "llvm/TypeSymbolTable.h" -#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/STLExtras.h" @@ -137,72 +136,57 @@ /// TypePrinting - Type printing machinery. namespace { class TypePrinting { - DenseMap TypeNames; TypePrinting(const TypePrinting &); // DO NOT IMPLEMENT void operator=(const TypePrinting&); // DO NOT IMPLEMENT public: - TypePrinting() {} - ~TypePrinting() {} - - void clear() { - TypeNames.clear(); - } - - void print(const Type *Ty, raw_ostream &OS, bool IgnoreTopLevelName = false); + + /// NamedTypes - The named types that are used by the current module. + std::vector NamedTypes; - void printAtLeastOneLevel(const Type *Ty, raw_ostream &OS) { - print(Ty, OS, true); - } + /// NumberedTypes - The numbered types, along with their value. + DenseMap NumberedTypes; - /// hasTypeName - Return true if the type has a name in TypeNames, false - /// otherwise. - bool hasTypeName(const Type *Ty) const { - return TypeNames.count(Ty); - } + TypePrinting() {} + ~TypePrinting() {} - /// addTypeName - Add a name for the specified type if it doesn't already have - /// one. This name will be printed instead of the structural version of the - /// type in order to make the output more concise. - void addTypeName(const Type *Ty, const std::string &N) { - TypeNames.insert(std::make_pair(Ty, N)); - } + void incorporateTypes(const Module &M); -private: - void CalcTypeName(const Type *Ty, SmallVectorImpl &TypeStack, - raw_ostream &OS, bool IgnoreTopLevelName = false); + void print(Type *Ty, raw_ostream &OS); + + void printStructBody(StructType *Ty, raw_ostream &OS); }; } // end anonymous namespace. -/// CalcTypeName - Write the specified type to the specified raw_ostream, making -/// use of type names or up references to shorten the type name where possible. -void TypePrinting::CalcTypeName(const Type *Ty, - SmallVectorImpl &TypeStack, - raw_ostream &OS, bool IgnoreTopLevelName) { - // Check to see if the type is named. - if (!IgnoreTopLevelName) { - DenseMap &TM = TypeNames; - DenseMap::iterator I = TM.find(Ty); - if (I != TM.end()) { - OS << I->second; - return; - } - } - - // Check to see if the Type is already on the stack... - unsigned Slot = 0, CurSize = TypeStack.size(); - while (Slot < CurSize && TypeStack[Slot] != Ty) ++Slot; // Scan for type - // This is another base case for the recursion. In this case, we know - // that we have looped back to a type that we have previously visited. - // Generate the appropriate upreference to handle this. - if (Slot < CurSize) { - OS << '\\' << unsigned(CurSize-Slot); // Here's the upreference - return; +void TypePrinting::incorporateTypes(const Module &M) { + M.findUsedStructTypes(NamedTypes); + + // The list of struct types we got back includes all the struct types, split + // the unnamed ones out to a numbering and remove the anonymous structs. + unsigned NextNumber = 0; + + std::vector::iterator NextToUse = NamedTypes.begin(), I, E; + for (I = NamedTypes.begin(), E = NamedTypes.end(); I != E; ++I) { + StructType *STy = *I; + + // Ignore anonymous types. + if (STy->isAnonymous()) + continue; + + if (STy->getName().empty()) + NumberedTypes[STy] = NextNumber++; + else + *NextToUse++ = STy; } + + NamedTypes.erase(NextToUse, NamedTypes.end()); +} - TypeStack.push_back(Ty); // Recursive case: Add us to the stack.. +/// CalcTypeName - Write the specified type to the specified raw_ostream, making +/// use of type names or up references to shorten the type name where possible. +void TypePrinting::print(Type *Ty, raw_ostream &OS) { switch (Ty->getTypeID()) { case Type::VoidTyID: OS << "void"; break; case Type::FloatTyID: OS << "float"; break; @@ -215,257 +199,100 @@ case Type::X86_MMXTyID: OS << "x86_mmx"; break; case Type::IntegerTyID: OS << 'i' << cast(Ty)->getBitWidth(); - break; + return; case Type::FunctionTyID: { - const FunctionType *FTy = cast(Ty); - CalcTypeName(FTy->getReturnType(), TypeStack, OS); + FunctionType *FTy = cast(Ty); + print(FTy->getReturnType(), OS); OS << " ("; for (FunctionType::param_iterator I = FTy->param_begin(), E = FTy->param_end(); I != E; ++I) { if (I != FTy->param_begin()) OS << ", "; - CalcTypeName(*I, TypeStack, OS); + print(*I, OS); } if (FTy->isVarArg()) { if (FTy->getNumParams()) OS << ", "; OS << "..."; } OS << ')'; - break; + return; } case Type::StructTyID: { - const StructType *STy = cast(Ty); - if (STy->isPacked()) - OS << '<'; - OS << '{'; - for (StructType::element_iterator I = STy->element_begin(), - E = STy->element_end(); I != E; ++I) { - OS << ' '; - CalcTypeName(*I, TypeStack, OS); - if (llvm::next(I) == STy->element_end()) - OS << ' '; - else - OS << ','; - } - OS << '}'; - if (STy->isPacked()) - OS << '>'; - break; + StructType *STy = cast(Ty); + + if (STy->isAnonymous()) + return printStructBody(STy, OS); + + if (!STy->getName().empty()) + return PrintLLVMName(OS, STy->getName(), LocalPrefix); + + DenseMap::iterator I = NumberedTypes.find(STy); + if (I != NumberedTypes.end()) + OS << '%' << I->second; + else // Not enumerated, print the hex address. + OS << "%\"type 0x" << STy << '\"'; + return; } case Type::PointerTyID: { - const PointerType *PTy = cast(Ty); - CalcTypeName(PTy->getElementType(), TypeStack, OS); + PointerType *PTy = cast(Ty); + print(PTy->getElementType(), OS); if (unsigned AddressSpace = PTy->getAddressSpace()) OS << " addrspace(" << AddressSpace << ')'; OS << '*'; - break; + return; } case Type::ArrayTyID: { - const ArrayType *ATy = cast(Ty); + ArrayType *ATy = cast(Ty); OS << '[' << ATy->getNumElements() << " x "; - CalcTypeName(ATy->getElementType(), TypeStack, OS); + print(ATy->getElementType(), OS); OS << ']'; - break; + return; } case Type::VectorTyID: { - const VectorType *PTy = cast(Ty); + VectorType *PTy = cast(Ty); OS << "<" << PTy->getNumElements() << " x "; - CalcTypeName(PTy->getElementType(), TypeStack, OS); + print(PTy->getElementType(), OS); OS << '>'; - break; + return; } - case Type::OpaqueTyID: - OS << "opaque"; - break; default: OS << ""; - break; + return; } - - TypeStack.pop_back(); // Remove self from stack. } -/// printTypeInt - The internal guts of printing out a type that has a -/// potentially named portion. -/// -void TypePrinting::print(const Type *Ty, raw_ostream &OS, - bool IgnoreTopLevelName) { - // Check to see if the type is named. - if (!IgnoreTopLevelName) { - DenseMap::iterator I = TypeNames.find(Ty); - if (I != TypeNames.end()) { - OS << I->second; - return; +void TypePrinting::printStructBody(StructType *STy, raw_ostream &OS) { + if (STy->isOpaque()) { + OS << "opaque"; + return; + } + + if (STy->isPacked()) + OS << '<'; + + if (STy->getNumElements() == 0) { + OS << "{}"; + } else { + StructType::element_iterator I = STy->element_begin(); + OS << "{ "; + print(*I++, OS); + for (StructType::element_iterator E = STy->element_end(); I != E; ++I) { + OS << ", "; + print(*I, OS); } + + OS << " }"; } - - // Otherwise we have a type that has not been named but is a derived type. - // Carefully recurse the type hierarchy to print out any contained symbolic - // names. - SmallVector TypeStack; - std::string TypeName; - - raw_string_ostream TypeOS(TypeName); - CalcTypeName(Ty, TypeStack, TypeOS, IgnoreTopLevelName); - OS << TypeOS.str(); - - // Cache type name for later use. - if (!IgnoreTopLevelName) - TypeNames.insert(std::make_pair(Ty, TypeOS.str())); + if (STy->isPacked()) + OS << '>'; } -namespace { - class TypeFinder { - // To avoid walking constant expressions multiple times and other IR - // objects, we keep several helper maps. - DenseSet VisitedConstants; - DenseSet VisitedTypes; - - TypePrinting &TP; - std::vector &NumberedTypes; - public: - TypeFinder(TypePrinting &tp, std::vector &numberedTypes) - : TP(tp), NumberedTypes(numberedTypes) {} - - void Run(const Module &M) { - // Get types from the type symbol table. This gets opaque types referened - // only through derived named types. - const TypeSymbolTable &ST = M.getTypeSymbolTable(); - for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end(); - TI != E; ++TI) - IncorporateType(TI->second); - - // Get types from global variables. - for (Module::const_global_iterator I = M.global_begin(), - E = M.global_end(); I != E; ++I) { - IncorporateType(I->getType()); - if (I->hasInitializer()) - IncorporateValue(I->getInitializer()); - } - - // Get types from aliases. - for (Module::const_alias_iterator I = M.alias_begin(), - E = M.alias_end(); I != E; ++I) { - IncorporateType(I->getType()); - IncorporateValue(I->getAliasee()); - } - - // Get types from functions. - for (Module::const_iterator FI = M.begin(), E = M.end(); FI != E; ++FI) { - IncorporateType(FI->getType()); - - for (Function::const_iterator BB = FI->begin(), E = FI->end(); - BB != E;++BB) - for (BasicBlock::const_iterator II = BB->begin(), - E = BB->end(); II != E; ++II) { - const Instruction &I = *II; - // Incorporate the type of the instruction and all its operands. - IncorporateType(I.getType()); - for (User::const_op_iterator OI = I.op_begin(), OE = I.op_end(); - OI != OE; ++OI) - IncorporateValue(*OI); - } - } - } - private: - void IncorporateType(const Type *Ty) { - // Check to see if we're already visited this type. - if (!VisitedTypes.insert(Ty).second) - return; - - // If this is a structure or opaque type, add a name for the type. - if (((Ty->isStructTy() && cast(Ty)->getNumElements()) - || Ty->isOpaqueTy()) && !TP.hasTypeName(Ty)) { - TP.addTypeName(Ty, "%"+utostr(unsigned(NumberedTypes.size()))); - NumberedTypes.push_back(Ty); - } - // Recursively walk all contained types. - for (Type::subtype_iterator I = Ty->subtype_begin(), - E = Ty->subtype_end(); I != E; ++I) - IncorporateType(*I); - } - - /// IncorporateValue - This method is used to walk operand lists finding - /// types hiding in constant expressions and other operands that won't be - /// walked in other ways. GlobalValues, basic blocks, instructions, and - /// inst operands are all explicitly enumerated. - void IncorporateValue(const Value *V) { - if (V == 0 || !isa(V) || isa(V)) return; - - // Already visited? - if (!VisitedConstants.insert(V).second) - return; - - // Check this type. - IncorporateType(V->getType()); - - // Look in operands for types. - const Constant *C = cast(V); - for (Constant::const_op_iterator I = C->op_begin(), - E = C->op_end(); I != E;++I) - IncorporateValue(*I); - } - }; -} // end anonymous namespace - - -/// AddModuleTypesToPrinter - Add all of the symbolic type names for types in -/// the specified module to the TypePrinter and all numbered types to it and the -/// NumberedTypes table. -static void AddModuleTypesToPrinter(TypePrinting &TP, - std::vector &NumberedTypes, - const Module *M) { - if (M == 0) return; - - // If the module has a symbol table, take all global types and stuff their - // names into the TypeNames map. - const TypeSymbolTable &ST = M->getTypeSymbolTable(); - for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end(); - TI != E; ++TI) { - const Type *Ty = cast(TI->second); - - // As a heuristic, don't insert pointer to primitive types, because - // they are used too often to have a single useful name. - if (const PointerType *PTy = dyn_cast(Ty)) { - const Type *PETy = PTy->getElementType(); - if ((PETy->isPrimitiveType() || PETy->isIntegerTy()) && - !PETy->isOpaqueTy()) - continue; - } - - // Likewise don't insert primitives either. - if (Ty->isIntegerTy() || Ty->isPrimitiveType()) - continue; - - // Get the name as a string and insert it into TypeNames. - std::string NameStr; - raw_string_ostream NameROS(NameStr); - formatted_raw_ostream NameOS(NameROS); - PrintLLVMName(NameOS, TI->first, LocalPrefix); - NameOS.flush(); - TP.addTypeName(Ty, NameStr); - } - - // Walk the entire module to find references to unnamed structure and opaque - // types. This is required for correctness by opaque types (because multiple - // uses of an unnamed opaque type needs to be referred to by the same ID) and - // it shrinks complex recursive structure types substantially in some cases. - TypeFinder(TP, NumberedTypes).Run(*M); -} - - -/// WriteTypeSymbolic - This attempts to write the specified type as a symbolic -/// type, iff there is an entry in the modules symbol table for the specified -/// type or one of it's component types. -/// void llvm::WriteTypeSymbolic(raw_ostream &OS, const Type *Ty, const Module *M) { - TypePrinting Printer; - std::vector NumberedTypes; - AddModuleTypesToPrinter(Printer, NumberedTypes, M); - Printer.print(Ty, OS); + // FIXME: remove this function. + OS << *Ty; } //===----------------------------------------------------------------------===// @@ -986,7 +813,7 @@ // As a special case, print the array as a string if it is an array of // i8 with ConstantInt values. // - const Type *ETy = CA->getType()->getElementType(); + Type *ETy = CA->getType()->getElementType(); if (CA->isString()) { Out << "c\""; PrintEscapedString(CA->getAsString(), Out); @@ -1043,7 +870,7 @@ } if (const ConstantVector *CP = dyn_cast(CV)) { - const Type *ETy = CP->getType()->getElementType(); + Type *ETy = CP->getType()->getElementType(); assert(CP->getNumOperands() > 0 && "Number of operands for a PackedConst must be > 0"); Out << '<'; @@ -1241,8 +1068,8 @@ if (Context == 0) Context = getModuleFromVal(V); TypePrinting TypePrinter; - std::vector NumberedTypes; - AddModuleTypesToPrinter(TypePrinter, NumberedTypes, Context); + if (Context) + TypePrinter.incorporateTypes(*Context); if (PrintType) { TypePrinter.print(V->getType(), Out); Out << ' '; @@ -1259,14 +1086,14 @@ const Module *TheModule; TypePrinting TypePrinter; AssemblyAnnotationWriter *AnnotationWriter; - std::vector NumberedTypes; public: inline AssemblyWriter(formatted_raw_ostream &o, SlotTracker &Mac, const Module *M, AssemblyAnnotationWriter *AAW) : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW) { - AddModuleTypesToPrinter(TypePrinter, NumberedTypes, M); + if (M) + TypePrinter.incorporateTypes(*M); } void printMDNodeBody(const MDNode *MD); @@ -1279,7 +1106,7 @@ void writeAllMDNodes(); - void printTypeSymbolTable(const TypeSymbolTable &ST); + void printTypeIdentities(); void printGlobal(const GlobalVariable *GV); void printAlias(const GlobalAlias *GV); void printFunction(const Function *F); @@ -1374,9 +1201,7 @@ Out << " ]"; } - // Loop over the symbol table, emitting all id'd types. - if (!M->getTypeSymbolTable().empty() || !NumberedTypes.empty()) Out << '\n'; - printTypeSymbolTable(M->getTypeSymbolTable()); + printTypeIdentities(); // Output all globals. if (!M->global_empty()) Out << '\n'; @@ -1534,7 +1359,10 @@ const Constant *Aliasee = GA->getAliasee(); - if (const GlobalVariable *GV = dyn_cast(Aliasee)) { + if (Aliasee == 0) { + TypePrinter.print(GA->getType(), Out); + Out << " <>"; + } else if (const GlobalVariable *GV = dyn_cast(Aliasee)) { TypePrinter.print(GV->getType(), Out); Out << ' '; PrintLLVMName(Out, GV); @@ -1560,26 +1388,40 @@ Out << '\n'; } -void AssemblyWriter::printTypeSymbolTable(const TypeSymbolTable &ST) { +void AssemblyWriter::printTypeIdentities() { + if (TypePrinter.NumberedTypes.empty() && + TypePrinter.NamedTypes.empty()) + return; + + Out << '\n'; + + // We know all the numbers that each type is used and we know that it is a + // dense assignment. Convert the map to an index table. + std::vector NumberedTypes(TypePrinter.NumberedTypes.size()); + for (DenseMap::iterator I = + TypePrinter.NumberedTypes.begin(), E = TypePrinter.NumberedTypes.end(); + I != E; ++I) { + assert(I->second < NumberedTypes.size() && "Didn't get a dense numbering?"); + NumberedTypes[I->second] = I->first; + } + // Emit all numbered types. for (unsigned i = 0, e = NumberedTypes.size(); i != e; ++i) { Out << '%' << i << " = type "; - + // Make sure we print out at least one level of the type structure, so // that we do not get %2 = type %2 - TypePrinter.printAtLeastOneLevel(NumberedTypes[i], Out); + TypePrinter.printStructBody(NumberedTypes[i], Out); Out << '\n'; } - - // Print the named types. - for (TypeSymbolTable::const_iterator TI = ST.begin(), TE = ST.end(); - TI != TE; ++TI) { - PrintLLVMName(Out, TI->first, LocalPrefix); + + for (unsigned i = 0, e = TypePrinter.NamedTypes.size(); i != e; ++i) { + PrintLLVMName(Out, TypePrinter.NamedTypes[i]->getName(), LocalPrefix); Out << " = type "; // Make sure we print out at least one level of the type structure, so // that we do not get %FILE = type %FILE - TypePrinter.printAtLeastOneLevel(TI->second, Out); + TypePrinter.printStructBody(TypePrinter.NamedTypes[i], Out); Out << '\n'; } } @@ -1893,9 +1735,9 @@ } Operand = CI->getCalledValue(); - const PointerType *PTy = cast(Operand->getType()); - const FunctionType *FTy = cast(PTy->getElementType()); - const Type *RetTy = FTy->getReturnType(); + PointerType *PTy = cast(Operand->getType()); + FunctionType *FTy = cast(PTy->getElementType()); + Type *RetTy = FTy->getReturnType(); const AttrListPtr &PAL = CI->getAttributes(); if (PAL.getRetAttributes() != Attribute::None) @@ -1926,9 +1768,9 @@ Out << ' ' << Attribute::getAsString(PAL.getFnAttributes()); } else if (const InvokeInst *II = dyn_cast(&I)) { Operand = II->getCalledValue(); - const PointerType *PTy = cast(Operand->getType()); - const FunctionType *FTy = cast(PTy->getElementType()); - const Type *RetTy = FTy->getReturnType(); + PointerType *PTy = cast(Operand->getType()); + FunctionType *FTy = cast(PTy->getElementType()); + Type *RetTy = FTy->getReturnType(); const AttrListPtr &PAL = II->getAttributes(); // Print the calling convention being used. @@ -2011,7 +1853,7 @@ // omit the type from all but the first operand. If the instruction has // different type operands (for example br), then they are all printed. bool PrintAllTypes = false; - const Type *TheType = Operand->getType(); + Type *TheType = Operand->getType(); // Select, Store and ShuffleVector always print all types. if (isa(I) || isa(I) || isa(I) @@ -2131,7 +1973,15 @@ OS << ""; return; } - TypePrinting().print(this, OS); + TypePrinting TP; + TP.print(const_cast(this), OS); + + // If the type is a named struct type, print the body as well. + if (StructType *STy = dyn_cast(const_cast(this))) + if (!STy->isAnonymous()) { + OS << " = type "; + TP.printStructBody(STy, OS); + } } void Value::print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW) const { @@ -2187,14 +2037,7 @@ void Value::dump() const { print(dbgs()); dbgs() << '\n'; } // Type::dump - allow easy printing of Types from the debugger. -// This one uses type names from the given context module -void Type::dump(const Module *Context) const { - WriteTypeSymbolic(dbgs(), this, Context); - dbgs() << '\n'; -} - -// Type::dump - allow easy printing of Types from the debugger. -void Type::dump() const { dump(0); } +void Type::dump() const { print(dbgs()); } // Module::dump() - Allow printing of Modules from the debugger. void Module::dump() const { print(dbgs(), 0); } Modified: llvm/trunk/lib/VMCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/CMakeLists.txt?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/CMakeLists.txt (original) +++ llvm/trunk/lib/VMCore/CMakeLists.txt Sat Jul 9 12:41:24 2011 @@ -29,7 +29,6 @@ PassRegistry.cpp PrintModulePass.cpp Type.cpp - TypeSymbolTable.cpp Use.cpp User.cpp Value.cpp Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Sat Jul 9 12:41:24 2011 @@ -1466,8 +1466,8 @@ /// isZeroSizedType - This type is zero sized if its an array or structure of /// zero sized types. The only leaf zero sized type is an empty structure. static bool isMaybeZeroSizedType(const Type *Ty) { - if (Ty->isOpaqueTy()) return true; // Can't say. if (const StructType *STy = dyn_cast(Ty)) { + if (STy->isOpaque()) return true; // Can't say. // If all of elements have zero size, this does too. for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Sat Jul 9 12:41:24 2011 @@ -31,6 +31,7 @@ #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include #include using namespace llvm; @@ -639,13 +640,13 @@ : Constant(T, ConstantStructVal, OperandTraits::op_end(this) - V.size(), V.size()) { - assert(V.size() == T->getNumElements() && + assert((T->isOpaque() || V.size() == T->getNumElements()) && "Invalid initializer vector for constant structure"); Use *OL = OperandList; for (std::vector::const_iterator I = V.begin(), E = V.end(); I != E; ++I, ++OL) { Constant *C = *I; - assert(C->getType() == T->getElementType(I-V.begin()) && + assert((T->isOpaque() || C->getType() == T->getElementType(I-V.begin())) && "Initializer for struct element doesn't match struct element type!"); *OL = C; } @@ -653,14 +654,13 @@ // ConstantStruct accessors. Constant *ConstantStruct::get(const StructType *ST, ArrayRef V) { - assert(ST->getNumElements() == V.size() && - "Incorrect # elements specified to ConstantStruct::get"); - // Create a ConstantAggregateZero value if all elements are zeros. for (unsigned i = 0, e = V.size(); i != e; ++i) if (!V[i]->isNullValue()) return ST->getContext().pImpl->StructConstants.getOrCreate(ST, V); + assert((ST->isOpaque() || ST->getNumElements() == V.size()) && + "Incorrect # elements specified to ConstantStruct::get"); return ConstantAggregateZero::get(ST); } @@ -839,17 +839,15 @@ } /// getWithOperands - This returns the current constant expression with the -/// operands replaced with the specified values. The specified operands must -/// match count and type with the existing ones. +/// operands replaced with the specified values. The specified array must +/// have the same number of operands as our current one. Constant *ConstantExpr:: -getWithOperands(ArrayRef Ops) const { +getWithOperands(ArrayRef Ops, const Type *Ty) const { assert(Ops.size() == getNumOperands() && "Operand count mismatch!"); - bool AnyChange = false; - for (unsigned i = 0; i != Ops.size(); ++i) { - assert(Ops[i]->getType() == getOperand(i)->getType() && - "Operand type mismatch!"); + bool AnyChange = Ty != getType(); + for (unsigned i = 0; i != Ops.size(); ++i) AnyChange |= Ops[i] != getOperand(i); - } + if (!AnyChange) // No operands changed, return self. return const_cast(this); @@ -866,7 +864,7 @@ case Instruction::PtrToInt: case Instruction::IntToPtr: case Instruction::BitCast: - return ConstantExpr::getCast(getOpcode(), Ops[0], getType()); + return ConstantExpr::getCast(getOpcode(), Ops[0], Ty); case Instruction::Select: return ConstantExpr::getSelect(Ops[0], Ops[1], Ops[2]); case Instruction::InsertElement: @@ -964,14 +962,14 @@ /// destroyConstant - Remove the constant from the constant table... /// void ConstantAggregateZero::destroyConstant() { - getRawType()->getContext().pImpl->AggZeroConstants.remove(this); + getType()->getContext().pImpl->AggZeroConstants.remove(this); destroyConstantImpl(); } /// destroyConstant - Remove the constant from the constant table... /// void ConstantArray::destroyConstant() { - getRawType()->getContext().pImpl->ArrayConstants.remove(this); + getType()->getContext().pImpl->ArrayConstants.remove(this); destroyConstantImpl(); } @@ -1050,14 +1048,14 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantStruct::destroyConstant() { - getRawType()->getContext().pImpl->StructConstants.remove(this); + getType()->getContext().pImpl->StructConstants.remove(this); destroyConstantImpl(); } // destroyConstant - Remove the constant from the constant table... // void ConstantVector::destroyConstant() { - getRawType()->getContext().pImpl->VectorConstants.remove(this); + getType()->getContext().pImpl->VectorConstants.remove(this); destroyConstantImpl(); } @@ -1098,7 +1096,7 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantPointerNull::destroyConstant() { - getRawType()->getContext().pImpl->NullPtrConstants.remove(this); + getType()->getContext().pImpl->NullPtrConstants.remove(this); destroyConstantImpl(); } @@ -1113,7 +1111,7 @@ // destroyConstant - Remove the constant from the constant table. // void UndefValue::destroyConstant() { - getRawType()->getContext().pImpl->UndefValueConstants.remove(this); + getType()->getContext().pImpl->UndefValueConstants.remove(this); destroyConstantImpl(); } @@ -1147,7 +1145,7 @@ // destroyConstant - Remove the constant from the constant table. // void BlockAddress::destroyConstant() { - getFunction()->getRawType()->getContext().pImpl + getFunction()->getType()->getContext().pImpl ->BlockAddresses.erase(std::make_pair(getFunction(), getBasicBlock())); getBasicBlock()->AdjustBlockAddressRefCount(-1); destroyConstantImpl(); @@ -1921,7 +1919,7 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantExpr::destroyConstant() { - getRawType()->getContext().pImpl->ExprConstants.remove(this); + getType()->getContext().pImpl->ExprConstants.remove(this); destroyConstantImpl(); } @@ -1962,10 +1960,10 @@ assert(isa(To) && "Cannot make Constant refer to non-constant!"); Constant *ToC = cast(To); - LLVMContextImpl *pImpl = getRawType()->getContext().pImpl; + LLVMContextImpl *pImpl = getType()->getContext().pImpl; std::pair Lookup; - Lookup.first.first = cast(getRawType()); + Lookup.first.first = cast(getType()); Lookup.second = this; std::vector &Values = Lookup.first.second; @@ -1999,7 +1997,7 @@ Constant *Replacement = 0; if (isAllZeros) { - Replacement = ConstantAggregateZero::get(getRawType()); + Replacement = ConstantAggregateZero::get(getType()); } else { // Check to see if we have this array type already. bool Exists; @@ -2050,7 +2048,7 @@ assert(getOperand(OperandToUpdate) == From && "ReplaceAllUsesWith broken!"); std::pair Lookup; - Lookup.first.first = cast(getRawType()); + Lookup.first.first = cast(getType()); Lookup.second = this; std::vector &Values = Lookup.first.second; Values.reserve(getNumOperands()); // Build replacement struct. @@ -2072,11 +2070,11 @@ } Values[OperandToUpdate] = ToC; - LLVMContextImpl *pImpl = getRawType()->getContext().pImpl; + LLVMContextImpl *pImpl = getContext().pImpl; Constant *Replacement = 0; if (isAllZeros) { - Replacement = ConstantAggregateZero::get(getRawType()); + Replacement = ConstantAggregateZero::get(getType()); } else { // Check to see if we have this struct type already. bool Exists; @@ -2167,7 +2165,7 @@ &Indices[0], Indices.size()); } else if (isCast()) { assert(getOperand(0) == From && "Cast only has one use!"); - Replacement = ConstantExpr::getCast(getOpcode(), To, getRawType()); + Replacement = ConstantExpr::getCast(getOpcode(), To, getType()); } else if (getOpcode() == Instruction::Select) { Constant *C1 = getOperand(0); Constant *C2 = getOperand(1); Modified: llvm/trunk/lib/VMCore/ConstantsContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantsContext.h?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantsContext.h (original) +++ llvm/trunk/lib/VMCore/ConstantsContext.h Sat Jul 9 12:41:24 2011 @@ -570,13 +570,11 @@ template -class ConstantUniqueMap : public AbstractTypeUser { +class ConstantUniqueMap { public: typedef std::pair MapKey; typedef std::map MapTy; typedef std::map InverseMapTy; - typedef std::map - AbstractTypeMapTy; private: /// Map - This is the main map from the element descriptor to the Constants. /// This is the primary way we avoid creating two of the same shape @@ -589,10 +587,6 @@ /// through the map with very large keys. InverseMapTy InverseMap; - /// AbstractTypeMap - Map for abstract type constants. - /// - AbstractTypeMapTy AbstractTypeMap; - public: typename MapTy::iterator map_begin() { return Map.begin(); } typename MapTy::iterator map_end() { return Map.end(); } @@ -629,7 +623,7 @@ } typename MapTy::iterator I = - Map.find(MapKey(static_cast(CP->getRawType()), + Map.find(MapKey(static_cast(CP->getType()), ConstantKeyData::getValType(CP))); if (I == Map.end() || I->second != CP) { // FIXME: This should not use a linear scan. If this gets to be a @@ -639,24 +633,8 @@ } return I; } - - void AddAbstractTypeUser(const Type *Ty, typename MapTy::iterator I) { - // If the type of the constant is abstract, make sure that an entry - // exists for it in the AbstractTypeMap. - if (Ty->isAbstract()) { - const DerivedType *DTy = static_cast(Ty); - typename AbstractTypeMapTy::iterator TI = AbstractTypeMap.find(DTy); - - if (TI == AbstractTypeMap.end()) { - // Add ourselves to the ATU list of the type. - cast(DTy)->addAbstractTypeUser(this); - - AbstractTypeMap.insert(TI, std::make_pair(DTy, I)); - } - } - } - ConstantClass* Create(const TypeClass *Ty, ValRefType V, + ConstantClass *Create(const TypeClass *Ty, ValRefType V, typename MapTy::iterator I) { ConstantClass* Result = ConstantCreator::create(Ty, V); @@ -667,8 +645,6 @@ if (HasLargeKey) // Remember the reverse mapping if needed. InverseMap.insert(std::make_pair(Result, I)); - AddAbstractTypeUser(Ty, I); - return Result; } public: @@ -692,43 +668,6 @@ return Result; } - void UpdateAbstractTypeMap(const DerivedType *Ty, - typename MapTy::iterator I) { - assert(AbstractTypeMap.count(Ty) && - "Abstract type not in AbstractTypeMap?"); - typename MapTy::iterator &ATMEntryIt = AbstractTypeMap[Ty]; - if (ATMEntryIt == I) { - // Yes, we are removing the representative entry for this type. - // See if there are any other entries of the same type. - typename MapTy::iterator TmpIt = ATMEntryIt; - - // First check the entry before this one... - if (TmpIt != Map.begin()) { - --TmpIt; - if (TmpIt->first.first != Ty) // Not the same type, move back... - ++TmpIt; - } - - // If we didn't find the same type, try to move forward... - if (TmpIt == ATMEntryIt) { - ++TmpIt; - if (TmpIt == Map.end() || TmpIt->first.first != Ty) - --TmpIt; // No entry afterwards with the same type - } - - // If there is another entry in the map of the same abstract type, - // update the AbstractTypeMap entry now. - if (TmpIt != ATMEntryIt) { - ATMEntryIt = TmpIt; - } else { - // Otherwise, we are removing the last instance of this type - // from the table. Remove from the ATM, and from user list. - cast(Ty)->removeAbstractTypeUser(this); - AbstractTypeMap.erase(Ty); - } - } - } - void remove(ConstantClass *CP) { typename MapTy::iterator I = FindExistingElement(CP); assert(I != Map.end() && "Constant not found in constant table!"); @@ -736,12 +675,6 @@ if (HasLargeKey) // Remember the reverse mapping if needed. InverseMap.erase(CP); - - // Now that we found the entry, make sure this isn't the entry that - // the AbstractTypeMap points to. - const TypeClass *Ty = I->first.first; - if (Ty->isAbstract()) - UpdateAbstractTypeMap(static_cast(Ty), I); Map.erase(I); } @@ -755,22 +688,7 @@ assert(OldI != Map.end() && "Constant not found in constant table!"); assert(OldI->second == C && "Didn't find correct element?"); - // If this constant is the representative element for its abstract type, - // update the AbstractTypeMap so that the representative element is I. - // - // This must use getRawType() because if the type is under refinement, we - // will get the refineAbstractType callback below, and we don't want to - // kick union find in on the constant. - if (C->getRawType()->isAbstract()) { - typename AbstractTypeMapTy::iterator ATI = - AbstractTypeMap.find(cast(C->getRawType())); - assert(ATI != AbstractTypeMap.end() && - "Abstract type not in AbstractTypeMap?"); - if (ATI->second == OldI) - ATI->second = I; - } - - // Remove the old entry from the map. + // Remove the old entry from the map. Map.erase(OldI); // Update the inverse map so that we know that this constant is now @@ -780,58 +698,6 @@ InverseMap[C] = I; } } - - void refineAbstractType(const DerivedType *OldTy, const Type *NewTy) { - typename AbstractTypeMapTy::iterator I = AbstractTypeMap.find(OldTy); - - assert(I != AbstractTypeMap.end() && - "Abstract type not in AbstractTypeMap?"); - - // Convert a constant at a time until the last one is gone. The last one - // leaving will remove() itself, causing the AbstractTypeMapEntry to be - // eliminated eventually. - do { - ConstantClass *C = I->second->second; - MapKey Key(cast(NewTy), - ConstantKeyData::getValType(C)); - - std::pair IP = - Map.insert(std::make_pair(Key, C)); - if (IP.second) { - // The map didn't previously have an appropriate constant in the - // new type. - - // Remove the old entry. - typename MapTy::iterator OldI = - Map.find(MapKey(cast(OldTy), IP.first->first.second)); - assert(OldI != Map.end() && "Constant not in map!"); - UpdateAbstractTypeMap(OldTy, OldI); - Map.erase(OldI); - - // Set the constant's type. This is done in place! - setType(C, NewTy); - - // Update the inverse map so that we know that this constant is now - // located at descriptor I. - if (HasLargeKey) - InverseMap[C] = IP.first; - - AddAbstractTypeUser(NewTy, IP.first); - } else { - // The map already had an appropriate constant in the new type, so - // there's no longer a need for the old constant. - C->uncheckedReplaceAllUsesWith(IP.first->second); - C->destroyConstant(); // This constant is now dead, destroy it. - } - I = AbstractTypeMap.find(OldTy); - } while (I != AbstractTypeMap.end()); - } - - // If the type became concrete without being refined to any other existing - // type, we just remove ourselves from the ATU list. - void typeBecameConcrete(const DerivedType *AbsTy) { - AbsTy->removeAbstractTypeUser(this); - } void dump() const { DEBUG(dbgs() << "Constant.cpp: ConstantUniqueMap\n"); Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Sat Jul 9 12:41:24 2011 @@ -19,7 +19,6 @@ #include "llvm/GlobalVariable.h" #include "llvm/GlobalAlias.h" #include "llvm/LLVMContext.h" -#include "llvm/TypeSymbolTable.h" #include "llvm/InlineAsm.h" #include "llvm/IntrinsicInst.h" #include "llvm/PassManager.h" @@ -111,27 +110,6 @@ unwrap(M)->setTargetTriple(Triple); } -/*--.. Type names ..........................................................--*/ -LLVMBool LLVMAddTypeName(LLVMModuleRef M, const char *Name, LLVMTypeRef Ty) { - return unwrap(M)->addTypeName(Name, unwrap(Ty)); -} - -void LLVMDeleteTypeName(LLVMModuleRef M, const char *Name) { - TypeSymbolTable &TST = unwrap(M)->getTypeSymbolTable(); - - TypeSymbolTable::iterator I = TST.find(Name); - if (I != TST.end()) - TST.remove(I); -} - -LLVMTypeRef LLVMGetTypeByName(LLVMModuleRef M, const char *Name) { - return wrap(unwrap(M)->getTypeByName(Name)); -} - -const char *LLVMGetTypeName(LLVMModuleRef M, LLVMTypeRef Ty) { - return unwrap(M)->getTypeName(unwrap(Ty)).c_str(); -} - void LLVMDumpModule(LLVMModuleRef M) { unwrap(M)->dump(); } @@ -182,8 +160,6 @@ return LLVMArrayTypeKind; case Type::PointerTyID: return LLVMPointerTypeKind; - case Type::OpaqueTyID: - return LLVMOpaqueTypeKind; case Type::VectorTyID: return LLVMVectorTypeKind; case Type::X86_MMXTyID: @@ -382,9 +358,6 @@ LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C) { return wrap(Type::getLabelTy(*unwrap(C))); } -LLVMTypeRef LLVMOpaqueTypeInContext(LLVMContextRef C) { - return wrap(OpaqueType::get(*unwrap(C))); -} LLVMTypeRef LLVMVoidType(void) { return LLVMVoidTypeInContext(LLVMGetGlobalContext()); @@ -392,28 +365,6 @@ LLVMTypeRef LLVMLabelType(void) { return LLVMLabelTypeInContext(LLVMGetGlobalContext()); } -LLVMTypeRef LLVMOpaqueType(void) { - return LLVMOpaqueTypeInContext(LLVMGetGlobalContext()); -} - -/*--.. Operations on type handles ..........................................--*/ - -LLVMTypeHandleRef LLVMCreateTypeHandle(LLVMTypeRef PotentiallyAbstractTy) { - return wrap(new PATypeHolder(unwrap(PotentiallyAbstractTy))); -} - -void LLVMDisposeTypeHandle(LLVMTypeHandleRef TypeHandle) { - delete unwrap(TypeHandle); -} - -LLVMTypeRef LLVMResolveTypeHandle(LLVMTypeHandleRef TypeHandle) { - return wrap(unwrap(TypeHandle)->get()); -} - -void LLVMRefineType(LLVMTypeRef AbstractTy, LLVMTypeRef ConcreteTy) { - unwrap(AbstractTy)->refineAbstractTypeTo(unwrap(ConcreteTy)); -} - /*===-- Operations on values ----------------------------------------------===*/ Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Sat Jul 9 12:41:24 2011 @@ -134,7 +134,7 @@ return getType()->getContext(); } -const FunctionType *Function::getFunctionType() const { +FunctionType *Function::getFunctionType() const { return cast(getType()->getElementType()); } @@ -142,7 +142,7 @@ return getFunctionType()->isVarArg(); } -const Type *Function::getReturnType() const { +Type *Function::getReturnType() const { return getFunctionType()->getReturnType(); } @@ -163,7 +163,7 @@ : GlobalValue(PointerType::getUnqual(Ty), Value::FunctionVal, 0, 0, Linkage, name) { assert(FunctionType::isValidReturnType(getReturnType()) && - !getReturnType()->isOpaqueTy() && "invalid return type"); + "invalid return type"); SymTab = new ValueSymbolTable(); // If the function has arguments, mark them as lazily built. Modified: llvm/trunk/lib/VMCore/Globals.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Globals.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Globals.cpp (original) +++ llvm/trunk/lib/VMCore/Globals.cpp Sat Jul 9 12:41:24 2011 @@ -51,6 +51,7 @@ setAlignment(Src->getAlignment()); setSection(Src->getSection()); setVisibility(Src->getVisibility()); + setUnnamedAddr(Src->hasUnnamedAddr()); } void GlobalValue::setAlignment(unsigned Align) { Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Sat Jul 9 12:41:24 2011 @@ -47,7 +47,7 @@ } void InlineAsm::destroyConstant() { - getRawType()->getContext().pImpl->InlineAsms.remove(this); + getType()->getContext().pImpl->InlineAsms.remove(this); delete this; } Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Sat Jul 9 12:41:24 2011 @@ -372,7 +372,7 @@ // Create the call to Malloc. BasicBlock* BB = InsertBefore ? InsertBefore->getParent() : InsertAtEnd; Module* M = BB->getParent()->getParent(); - const Type *BPTy = Type::getInt8PtrTy(BB->getContext()); + Type *BPTy = Type::getInt8PtrTy(BB->getContext()); Value *MallocFunc = MallocF; if (!MallocFunc) // prototype malloc as "void *malloc(size_t)" @@ -823,7 +823,7 @@ return true; } -const Type *AllocaInst::getAllocatedType() const { +Type *AllocaInst::getAllocatedType() const { return getType()->getElementType(); } @@ -1098,7 +1098,7 @@ GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx, const Twine &Name, Instruction *InBe) : Instruction(PointerType::get( - checkType(getIndexedType(Ptr->getType(),Idx)), retrieveAddrSpace(Ptr)), + checkGEPType(getIndexedType(Ptr->getType(),Idx)), retrieveAddrSpace(Ptr)), GetElementPtr, OperandTraits::op_end(this) - 2, 2, InBe) { @@ -1108,7 +1108,7 @@ GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx, const Twine &Name, BasicBlock *IAE) : Instruction(PointerType::get( - checkType(getIndexedType(Ptr->getType(),Idx)), + checkGEPType(getIndexedType(Ptr->getType(),Idx)), retrieveAddrSpace(Ptr)), GetElementPtr, OperandTraits::op_end(this) - 2, @@ -1126,60 +1126,50 @@ /// pointer type. /// template -static const Type* getIndexedTypeInternal(const Type *Ptr, IndexTy const *Idxs, - unsigned NumIdx) { +static Type *getIndexedTypeInternal(const Type *Ptr, IndexTy const *Idxs, + unsigned NumIdx) { const PointerType *PTy = dyn_cast(Ptr); if (!PTy) return 0; // Type isn't a pointer type! - const Type *Agg = PTy->getElementType(); + Type *Agg = PTy->getElementType(); // Handle the special case of the empty set index set, which is always valid. if (NumIdx == 0) return Agg; // If there is at least one index, the top level type must be sized, otherwise - // it cannot be 'stepped over'. We explicitly allow abstract types (those - // that contain opaque types) under the assumption that it will be resolved to - // a sane type later. - if (!Agg->isSized() && !Agg->isAbstract()) + // it cannot be 'stepped over'. + if (!Agg->isSized()) return 0; unsigned CurIdx = 1; for (; CurIdx != NumIdx; ++CurIdx) { - const CompositeType *CT = dyn_cast(Agg); + CompositeType *CT = dyn_cast(Agg); if (!CT || CT->isPointerTy()) return 0; IndexTy Index = Idxs[CurIdx]; if (!CT->indexValid(Index)) return 0; Agg = CT->getTypeAtIndex(Index); - - // If the new type forwards to another type, then it is in the middle - // of being refined to another type (and hence, may have dropped all - // references to what it was using before). So, use the new forwarded - // type. - if (const Type *Ty = Agg->getForwardedType()) - Agg = Ty; } return CurIdx == NumIdx ? Agg : 0; } -const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, - Value* const *Idxs, - unsigned NumIdx) { +Type *GetElementPtrInst::getIndexedType(const Type *Ptr, Value* const *Idxs, + unsigned NumIdx) { return getIndexedTypeInternal(Ptr, Idxs, NumIdx); } -const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, - Constant* const *Idxs, - unsigned NumIdx) { +Type *GetElementPtrInst::getIndexedType(const Type *Ptr, + Constant* const *Idxs, + unsigned NumIdx) { return getIndexedTypeInternal(Ptr, Idxs, NumIdx); } -const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, - uint64_t const *Idxs, - unsigned NumIdx) { +Type *GetElementPtrInst::getIndexedType(const Type *Ptr, + uint64_t const *Idxs, + unsigned NumIdx) { return getIndexedTypeInternal(Ptr, Idxs, NumIdx); } -const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, Value *Idx) { +Type *GetElementPtrInst::getIndexedType(const Type *Ptr, Value *Idx) { const PointerType *PTy = dyn_cast(Ptr); if (!PTy) return 0; // Type isn't a pointer type! @@ -1482,9 +1472,9 @@ // A null type is returned if the indices are invalid for the specified // pointer type. // -const Type* ExtractValueInst::getIndexedType(const Type *Agg, - const unsigned *Idxs, - unsigned NumIdx) { +Type *ExtractValueInst::getIndexedType(const Type *Agg, + const unsigned *Idxs, + unsigned NumIdx) { for (unsigned CurIdx = 0; CurIdx != NumIdx; ++CurIdx) { unsigned Index = Idxs[CurIdx]; // We can't use CompositeType::indexValid(Index) here. @@ -1505,19 +1495,11 @@ } Agg = cast(Agg)->getTypeAtIndex(Index); - - // If the new type forwards to another type, then it is in the middle - // of being refined to another type (and hence, may have dropped all - // references to what it was using before). So, use the new forwarded - // type. - if (const Type *Ty = Agg->getForwardedType()) - Agg = Ty; } - return Agg; + return const_cast(Agg); } -const Type* ExtractValueInst::getIndexedType(const Type *Agg, - unsigned Idx) { +Type *ExtractValueInst::getIndexedType(const Type *Agg, unsigned Idx) { return getIndexedType(Agg, &Idx, 1); } Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.cpp?rev=134829&r1=134828&r2=134829&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.cpp Sat Jul 9 12:41:24 2011 @@ -31,14 +31,10 @@ Int8Ty(C, 8), Int16Ty(C, 16), Int32Ty(C, 32), - Int64Ty(C, 64), - AlwaysOpaqueTy(new OpaqueType(C)) { + Int64Ty(C, 64) { InlineAsmDiagHandler = 0; InlineAsmDiagContext = 0; - - // Make sure the AlwaysOpaqueTy stays alive as long as the Context. - AlwaysOpaqueTy->addRef(); - OpaqueTypes.insert(AlwaysOpaqueTy); + NamedStructTypesUniqueID = 0; } namespace { @@ -86,12 +82,7 @@ I != E; ++I) { delete I->second; } - AlwaysOpaqueTy->dropRef(); - for (OpaqueTypesTy::iterator I = OpaqueTypes.begin(), E = OpaqueTypes.end(); - I != E; ++I) { - (*I)->AbstractTypeUsers.clear(); - delete *I; - } + // Destroy MDNodes. ~MDNode can move and remove nodes between the MDNodeSet // and the NonUniquedMDNodes sets, so copy the values out first. SmallVector MDNodes; @@ -109,7 +100,6 @@ "Destroying all MDNodes didn't empty the Context's sets."); // Destroy MDStrings. for (StringMap::iterator I = MDStringCache.begin(), - E = MDStringCache.end(); I != E; ++I) { + E = MDStringCache.end(); I != E; ++I) delete I->s