From stoklund at 2pi.dk Mon Jul 18 00:31:59 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 05:31:59 -0000 Subject: [llvm-commits] [llvm] r135378 - /llvm/trunk/lib/CodeGen/InlineSpiller.cpp Message-ID: <20110718053200.003BC2A6C12C@llvm.org> Author: stoklund Date: Mon Jul 18 00:31:59 2011 New Revision: 135378 URL: http://llvm.org/viewvc/llvm-project?rev=135378&view=rev Log: Fix PR10387. When trying to rematerialize a value before an instruction that has an early-clobber redefine of the virtual register, make sure to look up the correct value number. Early-clobber defs are moved one slot back, so getBaseIndex is needed to find the used value number. Bugpoint was unable to reduce the test case for this, see PR10388. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=135378&r1=135377&r2=135378&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Mon Jul 18 00:31:59 2011 @@ -637,7 +637,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineBasicBlock::iterator MI) { SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex(); - VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx); + VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); if (!ParentVNI) { DEBUG(dbgs() << "\tadding flags: "); From dblaikie at gmail.com Mon Jul 18 00:44:00 2011 From: dblaikie at gmail.com (David Blaikie) Date: Sun, 17 Jul 2011 22:44:00 -0700 Subject: [llvm-commits] [patch] universally transition to non-const llvm::Type In-Reply-To: References: <7DD58162-AB05-4C58-ABD1-64050456D495@apple.com> Message-ID: > > Applied in r135371, thanks! I'll apply your original patch as well after > fixing llvm-gcc. > Thanks for that. I see you skipped the change to PassAnalysisSupport... oh, I see, PassAnalysisSupport's VectorType isn't llvm::VectorType, it's AnalysisUsage::VectorType, which is completely unrelated. Thanks for catching that. Was there anything else you fixed up that I should look out for next time? (not that I expect to be making such sweeping patches on a regular basis - I think I'll work on StringRef-izing things next & see how that goes) - David -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110717/f9adb6a8/attachment.html From nicholas at mxc.ca Mon Jul 18 00:54:07 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 18 Jul 2011 05:54:07 -0000 Subject: [llvm-commits] [llvm] r135379 - /llvm/trunk/test/CodeGen/X86/avx-256-arith.s Message-ID: <20110718055407.19AF82A6C12C@llvm.org> Author: nicholas Date: Mon Jul 18 00:54:06 2011 New Revision: 135379 URL: http://llvm.org/viewvc/llvm-project?rev=135379&view=rev Log: Delete empty unused file. Removed: llvm/trunk/test/CodeGen/X86/avx-256-arith.s Removed: llvm/trunk/test/CodeGen/X86/avx-256-arith.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-arith.s?rev=135378&view=auto ============================================================================== (empty) From clattner at apple.com Mon Jul 18 01:39:55 2011 From: clattner at apple.com (Chris Lattner) Date: Sun, 17 Jul 2011 23:39:55 -0700 Subject: [llvm-commits] [patch] universally transition to non-const llvm::Type In-Reply-To: References: <7DD58162-AB05-4C58-ABD1-64050456D495@apple.com> Message-ID: On Jul 17, 2011, at 10:44 PM, David Blaikie wrote: > Applied in r135371, thanks! I'll apply your original patch as well after fixing llvm-gcc. > > Thanks for that. I see you skipped the change to PassAnalysisSupport... oh, I see, PassAnalysisSupport's VectorType isn't llvm::VectorType, it's AnalysisUsage::VectorType, which is completely unrelated. Thanks for catching that. Was there anything else you fixed up that I should look out for next time? (not that I expect to be making such sweeping patches on a regular basis - I think I'll work on StringRef-izing things next & see how that goes) The other thing that got missed were the llvm/examples, which aren't built by default and adding a note to the ReleaseNotes for the API change. I covered those in other commits. Thanks again, -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110717/317d4e85/attachment.html From fvbommel at gmail.com Mon Jul 18 02:05:55 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 09:05:55 +0200 Subject: [llvm-commits] [Review request] arrayRef helper function for explicit ArrayRef construction. In-Reply-To: References: Message-ID: On 18 July 2011 04:16, Chandler Carruth wrote: > On Sun, Jul 17, 2011 at 6:34 AM, Frits van Bommel > wrote: >> >> arrayRef(...) > > Any reason not to call these 'makeArrayRef'? That would seem more idiomatic > than a case difference, at least to my eyes. I wanted to keep it short, but okay. From fvbommel at gmail.com Mon Jul 18 03:25:00 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 10:25:00 +0200 Subject: [llvm-commits] [llvm] r135365 - in /llvm/trunk: docs/ProgrammersManual.html include/llvm/ADT/TinyPtrVector.h In-Reply-To: <20110718014002.5E44E2A6C12C@llvm.org> References: <20110718014002.5E44E2A6C12C@llvm.org> Message-ID: On 18 July 2011 03:40, Chris Lattner wrote: > Added: llvm/trunk/include/llvm/ADT/TinyPtrVector.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/TinyPtrVector.h?rev=135365&view=auto > ============================================================================== > --- llvm/trunk/include/llvm/ADT/TinyPtrVector.h (added) > +++ llvm/trunk/include/llvm/ADT/TinyPtrVector.h Sun Jul 17 20:40:02 2011 > @@ -0,0 +1,115 @@ > +//===- llvm/ADT/TinyPtrVector.h - 'Normally tiny' vectors -------*- C++ -*-===// > +// > +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file defines the Type class. s/Type/TinyPtrVector/ > +// > +//===----------------------------------------------------------------------===// > + > +#ifndef LLVM_ADT_TINYPTRVECTOR_H > +#define LLVM_ADT_TINYPTRVECTOR_H > + > +#include "llvm/ADT/SmallVector.h" > +#include "llvm/ADT/PointerUnion.h" > + > +namespace llvm { > + > +/// TinyPtrVector - This class is specialized for cases where there are > +/// normally 0 or 1 element in a vector, but is general enough to go beyond that > +/// when required. > +/// > +/// NOTE: This container doesn't allow you to store a null pointer into it. This restriction could be lifted by using a null VecTy* as the empty value instead of any null pointer (what empty() currently checks for) or a null EltTy (what can actually happen). Several changes would need to be made: * Swapping the ordering in the PointerUnion (so that default construction still makes it empty) or just explicitly initializing Val to (VecTy*)0. * The biggest change: reimplementing empty() as: bool empty() const { if (Val.template is()) return Val.template get(); if (VecTy *Vec = Val.template get() return Vec->empty(); return false; } * assigning (VectTy*)0 in the single-element case in clear(). * Using empty() to check for emptyness instead of Val.isNull() in operator[]. * Obviously, removing the assert that it's not null at the top of push_back(). * Using 'Val.isNull() && Val.template is()' instead of just 'Val.isNull()' in push_back() to check for 'no elements and no vector'. '!Val.getOpaqueValue()' would work too, if you swapped the element types of the PointerUnion as suggested above, but looks more fragile. Or maybe something nicer I haven't thought of. * Using is and get instead of dyn_cast in a few places because the dyn_cast can now return null even if there *is* an element but it happens to be null. * Anything I missed (?). But if none of the use cases you have in mind for this require it this might not be worth the added complexity. > +/// > +template > +class TinyPtrVector { > +public: > + ?typedef llvm::SmallVector VecTy; > + ?llvm::PointerUnion Val; > + > + ?TinyPtrVector() {} > + ?TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) { > + ? ?if (VecTy *V = Val.template dyn_cast()) > + ? ? ?Val = new VecTy(*V); > + ?} > + ?~TinyPtrVector() { > + ? ?if (VecTy *V = Val.template dyn_cast()) > + ? ? ?delete V; > + ?} > + > + ?/// empty() - This vector can be empty if it contains no element, or if it > + ?/// contains a pointer to an empty vector. This doesn't seem doc-comment worthy. It talks about implementation details the user shouldn't care about and which aren't mentioned in any of the other documentation. All other comments of this kind are inside the methods, which is where this one belongs too. > + ?bool empty() const { > + ? ?if (Val.isNull()) return true; > + ? ?if (VecTy *Vec = Val.template dyn_cast()) > + ? ? ?return Vec->empty(); > + ? ?return false; > + ?} > + > + ?unsigned size() const { > + ? ?if (empty()) > + ? ? ?return 0; > + ? ?if (Val. template is()) There's an extra space before 'template', which doesn't match the style used in most other cases in this file. > + ? ? ?return 1; > + ? ?return Val. template get()->size(); Ditto. > + ?} > + > + ?EltTy operator[](unsigned i) const { > + ? ?assert(!Val.isNull() && "can't index into an empty vector"); > + ? ?if (EltTy V = Val.template dyn_cast()) { > + ? ? ?assert(i == 0 && "tinyvector index out of range"); > + ? ? ?return V; > + ? ?} > + > + ? ?assert(i < Val. template get()->size() && Ditto. > + ? ? ? ? ? "tinyvector index out of range"); > + ? ?return (*Val. template get())[i]; Ditto. > + ?} > + > + ?EltTy front() const { > + ? ?assert(!empty() && "vector empty"); > + ? ?if (EltTy V = Val.template dyn_cast()) > + ? ? ?return V; > + ? ?return Val.template get()->front(); > + ?} > + > + ?void push_back(EltTy NewVal) { > + ? ?assert(NewVal != 0 && "Can't add a null value"); > + > + ? ?// If we have nothing, add something. > + ? ?if (Val.isNull()) { > + ? ? ?Val = NewVal; > + ? ? ?return; > + ? ?} > + > + ? ?// If we have a single value, convert to a vector. > + ? ?if (EltTy V = Val.template ?dyn_cast()) { There are two spaces in 'template dyn_cast'. > + ? ? ?Val = new VecTy(); > + ? ? ?Val.template get()->push_back(V); > + ? ?} > + > + ? ?// Add the new value, we know we have a vector. > + ? ?Val.template get()->push_back(NewVal); > + ?} > + > + ?void clear() { > + ? ?// If we have a single value, convert to empty. > + ? ?if (EltTy V = Val.template dyn_cast()) { > + ? ? ?Val = (EltTy)0; > + ? ?} else if (VecTy *Vec = Val.template dyn_cast()) { > + ? ? ?// If we have a vector form, just clear it. > + ? ? ?Vec->clear(); > + ? ?} > + ? ?// Otherwise, we're already empty. > + ?} > + > +private: > + ?void operator=(const TinyPtrVector&); // NOT IMPLEMENTED YET. > +}; > +} // end namespace llvm > + > +#endif From grosser at fim.uni-passau.de Mon Jul 18 03:38:59 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 08:38:59 -0000 Subject: [llvm-commits] [zorg] r135383 - in /zorg/trunk: buildbot/osuosl/master/config/builders.py buildbot/osuosl/master/master.cfg zorg/buildbot/builders/PollyBuilder.py Message-ID: <20110718083859.DC3582A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 03:38:59 2011 New Revision: 135383 URL: http://llvm.org/viewvc/llvm-project?rev=135383&view=rev Log: Add new Polly builder on Linux amd64. Added: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/buildbot/osuosl/master/master.cfg Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=135383&r1=135382&r2=135383&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Jul 18 03:38:59 2011 @@ -22,6 +22,10 @@ reload(ScriptedBuilder) from zorg.buildbot.builders import ScriptedBuilder +from zorg.buildbot.builders import PollyBuilder +reload(PollyBuilder) +from zorg.buildbot.builders import PollyBuilder + from buildbot.steps.source import SVN from zorg.buildbot.commands.ClangTestCommand import ClangTestCommand @@ -246,6 +250,15 @@ ] +# Polly builders. +def _get_polly_builders(): + return [ + {'name': "polly-amd64-linux", + 'slavenames':["grosser1"], + 'builddir':"polly-amd64-linux", + 'factory': PollyBuilder.getPollyBuildFactory()} + ] + def _get_experimental_builders(): return [ @@ -740,6 +753,10 @@ b['category'] = 'clang' yield b + for b in _get_polly_builders(): + b['category'] = 'polly' + yield b + for b in _get_experimental_builders(): yield b Modified: zorg/trunk/buildbot/osuosl/master/master.cfg URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/master.cfg?rev=135383&r1=135382&r2=135383&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/master.cfg (original) +++ zorg/trunk/buildbot/osuosl/master/master.cfg Mon Jul 18 03:38:59 2011 @@ -49,6 +49,7 @@ if True: c['change_source'].append(LLVMPoller("llvm/trunk")) c['change_source'].append(LLVMPoller("cfe/trunk")) + c['change_source'].append(LLVMPoller("polly/trunk")) c['change_source'].append(LLVMPoller("llvm-gcc-4.2/trunk")) c['change_source'].append(LLVMPoller("compiler-rt/trunk")) c['change_source'].append(LLVMPoller("dragonegg/trunk")) Added: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=135383&view=auto ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (added) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Mon Jul 18 03:38:59 2011 @@ -0,0 +1,129 @@ +import os + +import buildbot +import buildbot.process.factory +from buildbot.steps.source import SVN, Git +from buildbot.steps.shell import Configure, ShellCommand +from buildbot.process.properties import WithProperties + +f = buildbot.process.factory.BuildFactory() + +def installRequiredLibs(): + cloog_srcdir = "cloog.src" + isl_srcdir = "isl.src" + cloog_installdir = isl_installdir = "cloog.install" + + global f + # Get Cloog + f.addStep(Git(repourl='git://repo.or.cz/cloog.git', + mode='update', + workdir=cloog_srcdir)) + # Get isl + f.addStep(Git(repourl='git://repo.or.cz/isl.git', + mode='update', + workdir=isl_srcdir)) + # Build isl + f.addStep(ShellCommand(name="autogen-isl", + command=["./autogen.sh"], + haltOnFailure=True, + description=["autogen cloog"], + workdir=isl_srcdir)) + islconfargs = [] + islconfargs.append(WithProperties("%%(builddir)s/%s/configure" + % isl_srcdir)) + islconfargs.append(WithProperties("--prefix=%%(builddir)s/%s" + % isl_installdir)) + f.addStep(Configure(name="isl-configure", + command=islconfargs, + workdir=isl_srcdir, + description=['isl-configure'])) + f.addStep(ShellCommand(name="build-isl", + command=["make"], + haltOnFailure=True, + description=["build isl"], + workdir=isl_srcdir)) + f.addStep(ShellCommand(name="install-isl", + command=["make", "install"], + haltOnFailure=True, + description=["install isl"], + workdir=isl_srcdir)) + # Build Cloog + f.addStep(ShellCommand(name="autogen-cloog", + command=["./autogen.sh"], + haltOnFailure=True, + description=["autogen cloog"], + workdir=cloog_srcdir)) + confargs = [] + confargs.append(WithProperties("%%(builddir)s/%s/configure" + % cloog_srcdir)) + confargs.append(WithProperties("--prefix=%%(builddir)s/%s" + % cloog_installdir)) + confargs.append(WithProperties("--with-isl-prefix=%%(builddir)s/%s" + % cloog_installdir)) + confargs.append(WithProperties("--with-isl=system")) + f.addStep(Configure(name="cloog-configure", + command=confargs, + workdir=cloog_srcdir, + description=['cloog-configure'])) + f.addStep(ShellCommand(name="build-cloog", + command=["make"], + haltOnFailure=True, + description=["build cloog"], + workdir=cloog_srcdir)) + f.addStep(ShellCommand(name="install-cloog", + command=["make", "install"], + haltOnFailure=True, + description=["install cloog"], + workdir=cloog_srcdir)) + +def getPollyBuildFactory(): + llvm_srcdir = "llvm.src" + llvm_objdir = "llvm.obj" + cloog_installdir = "cloog.install" + + global f + # Determine the build directory. + f.addStep(buildbot.steps.shell.SetProperty(name="get_builddir", + command=["pwd"], + property="builddir", + description="set build dir", + workdir=".")) + # Install Prerequisites + installRequiredLibs() + # Get LLVM and Polly + f.addStep(SVN(name='svn-llvm', + mode='update', + baseURL='http://llvm.org/svn/llvm-project/llvm/', + defaultBranch='trunk', + workdir=llvm_srcdir)) + f.addStep(SVN(name='svn-polly', + mode='update', + baseURL='http://llvm.org/svn/llvm-project/polly/', + defaultBranch='trunk', + workdir='%s/tools/polly' % llvm_srcdir)) + # Create configuration files with cmake + f.addStep(ShellCommand(name="create-build-dir", + command=["mkdir", llvm_objdir], + haltOnFailure=False, + description=["create build dir"], + workdir=".")) + cloogpath = WithProperties("-DCMAKE_PREFIX_PATH=%%(builddir)s/%s" + % cloog_installdir) + f.addStep(ShellCommand(name="cmake-configure", + command=["cmake", "../%s" %llvm_srcdir, cloogpath], + haltOnFailure=False, + description=["cmake configure"], + workdir=llvm_objdir)) + # Build Polly + f.addStep(ShellCommand(name="build_polly", + command=["make"], + haltOnFailure=True, + description=["build polly"], + workdir=llvm_objdir)) + # Test Polly + f.addStep(ShellCommand(name="test_polly", + command=["make", "polly-test"], + haltOnFailure=True, + description=["test polly"], + workdir=llvm_objdir)) + return f From grosser at fim.uni-passau.de Mon Jul 18 04:53:32 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 09:53:32 -0000 Subject: [llvm-commits] [polly] r135384 - in /polly/trunk: include/polly/Support/AffineSCEVIterator.h lib/CodeGeneration.cpp Message-ID: <20110718095332.932322A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 04:53:32 2011 New Revision: 135384 URL: http://llvm.org/viewvc/llvm-project?rev=135384&view=rev Log: Use llvm::*Type without const Modified: polly/trunk/include/polly/Support/AffineSCEVIterator.h polly/trunk/lib/CodeGeneration.cpp Modified: polly/trunk/include/polly/Support/AffineSCEVIterator.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/AffineSCEVIterator.h?rev=135384&r1=135383&r2=135384&view=diff ============================================================================== --- polly/trunk/include/polly/Support/AffineSCEVIterator.h (original) +++ polly/trunk/include/polly/Support/AffineSCEVIterator.h Mon Jul 18 04:53:32 2011 @@ -28,7 +28,7 @@ namespace polly { /// @brief The itertor transform the scalar expressions to the form of sum of -/// (constant * varialbe)s, and return the variable/constant pairs one by one +/// (constant * variable)s, and return the variable/constant pairs one by one /// on the fly. /// /// For example, we can write SCEV: @@ -85,7 +85,7 @@ } value_type visitUnknown(const SCEVUnknown* S) { - const Type *AllocTy; + Type *AllocTy; Constant *FieldNo; // We treat these as constant. if (S->isSizeOf (AllocTy) || @@ -235,7 +235,7 @@ if (isa(S)) return; - const Type *Ty = S->getType(); + Type *Ty = S->getType(); // Init the constant component. visitStack.push_back(SE->getConstant(Ty, 0)); Modified: polly/trunk/lib/CodeGeneration.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=135384&r1=135383&r2=135384&view=diff ============================================================================== --- polly/trunk/lib/CodeGeneration.cpp (original) +++ polly/trunk/lib/CodeGeneration.cpp Mon Jul 18 04:53:32 2011 @@ -111,7 +111,7 @@ assert(LB->getType() == UB->getType() && "Different types for upper and lower bound."); - const IntegerType *LoopIVType = dyn_cast(UB->getType()); + IntegerType *LoopIVType = dyn_cast(UB->getType()); assert(LoopIVType && "UB is not integer?"); // IV @@ -211,11 +211,11 @@ return const_cast(OldOperand); } - const Type *getVectorPtrTy(const Value *V, int vectorWidth) { - const PointerType *pointerType = dyn_cast(V->getType()); + Type *getVectorPtrTy(const Value *V, int vectorWidth) { + PointerType *pointerType = dyn_cast(V->getType()); assert(pointerType && "PointerType expected"); - const Type *scalarType = pointerType->getElementType(); + Type *scalarType = pointerType->getElementType(); VectorType *vectorType = VectorType::get(scalarType, vectorWidth); return PointerType::getUnqual(vectorType); @@ -232,7 +232,7 @@ Value *generateStrideOneLoad(const LoadInst *load, ValueMapT &BBMap, int size) { const Value *pointer = load->getPointerOperand(); - const Type *vectorPtrType = getVectorPtrTy(pointer, size); + Type *vectorPtrType = getVectorPtrTy(pointer, size); Value *newPointer = getOperand(pointer, BBMap); Value *VectorPtr = Builder.CreateBitCast(newPointer, vectorPtrType, "vector_ptr"); @@ -258,7 +258,7 @@ Value *generateStrideZeroLoad(const LoadInst *load, ValueMapT &BBMap, int size) { const Value *pointer = load->getPointerOperand(); - const Type *vectorPtrType = getVectorPtrTy(pointer, 1); + Type *vectorPtrType = getVectorPtrTy(pointer, 1); Value *newPointer = getOperand(pointer, BBMap); Value *vectorPtr = Builder.CreateBitCast(newPointer, vectorPtrType, load->getNameStr() + "_p_vec_p"); @@ -417,7 +417,7 @@ Value *vector = getOperand(store->getValueOperand(), BBMap, &vectorMap); if (Access.isStrideOne(scatteringDomain)) { - const Type *vectorPtrType = getVectorPtrTy(pointer, vectorWidth); + Type *vectorPtrType = getVectorPtrTy(pointer, vectorWidth); Value *newPointer = getOperand(pointer, BBMap, &vectorMap); Value *VectorPtr = Builder.CreateBitCast(newPointer, vectorPtrType, @@ -528,7 +528,7 @@ IRBuilder<> &Builder; const CharMapT *IVS; - Value *codegen(const clast_name *e, const Type *Ty) { + Value *codegen(const clast_name *e, Type *Ty) { CharMapT::const_iterator I = IVS->find(e->name); if (I != IVS->end()) @@ -537,7 +537,7 @@ llvm_unreachable("Clast name not found"); } - Value *codegen(const clast_term *e, const Type *Ty) { + Value *codegen(const clast_term *e, Type *Ty) { APInt a = APInt_from_MPZ(e->val); Value *ConstOne = ConstantInt::get(Builder.getContext(), a); @@ -551,7 +551,7 @@ return ConstOne; } - Value *codegen(const clast_binary *e, const Type *Ty) { + Value *codegen(const clast_binary *e, Type *Ty) { Value *LHS = codegen(e->LHS, Ty); APInt RHS_AP = APInt_from_MPZ(e->RHS); @@ -595,7 +595,7 @@ }; } - Value *codegen(const clast_reduction *r, const Type *Ty) { + Value *codegen(const clast_reduction *r, Type *Ty) { assert(( r->type == clast_red_min || r->type == clast_red_max || r->type == clast_red_sum) @@ -644,7 +644,7 @@ // // @param e The expression to calculate. // @return The Value that holds the result. - Value *codegen(const clast_expr *e, const Type *Ty) { + Value *codegen(const clast_expr *e, Type *Ty) { switch(e->type) { case clast_expr_name: return codegen((const clast_name *)e, Ty); @@ -914,7 +914,7 @@ SetVector OMPDataVals) { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); LLVMContext &Context = FN->getContext(); - const IntegerType *intPtrTy = TD->getIntPtrType(Context); + IntegerType *intPtrTy = TD->getIntPtrType(Context); // Store the previous basic block. BasicBlock *PrevBB = Builder.GetInsertBlock(); @@ -994,7 +994,7 @@ /// statement. void codegenForOpenMP(const clast_for *f) { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); - const IntegerType *intPtrTy = TD->getIntPtrType(Builder.getContext()); + IntegerType *intPtrTy = TD->getIntPtrType(Builder.getContext()); Function *SubFunction = addOpenMPSubfunction(M); SetVector OMPDataVals = createOpenMPStructValues(); @@ -1099,7 +1099,7 @@ TD->getIntPtrType(Builder.getContext())); APInt Stride = APInt_from_MPZ(f->stride); - const IntegerType *LoopIVType = dyn_cast(LB->getType()); + IntegerType *LoopIVType = dyn_cast(LB->getType()); Stride = Stride.zext(LoopIVType->getBitWidth()); Value *StrideValue = ConstantInt::get(LoopIVType, Stride); @@ -1214,7 +1214,7 @@ assert(i < names->nb_parameters && "Not enough parameter names"); const SCEV *Param = *PI; - const Type *Ty = Param->getType(); + Type *Ty = Param->getType(); Instruction *insertLocation = --(Builder.GetInsertBlock()->end()); Value *V = Rewriter.expandCodeFor(Param, Ty, insertLocation); From grosser at fim.uni-passau.de Mon Jul 18 04:53:35 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 09:53:35 -0000 Subject: [llvm-commits] [polly] r135385 - /polly/trunk/www/todo.html Message-ID: <20110718095335.EBA952A6C12D@llvm.org> Author: grosser Date: Mon Jul 18 04:53:35 2011 New Revision: 135385 URL: http://llvm.org/viewvc/llvm-project?rev=135385&view=rev Log: www: Buildbot set up Modified: polly/trunk/www/todo.html Modified: polly/trunk/www/todo.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/todo.html?rev=135385&r1=135384&r2=135385&view=diff ============================================================================== --- polly/trunk/www/todo.html (original) +++ polly/trunk/www/todo.html Mon Jul 18 04:53:35 2011 @@ -60,8 +60,11 @@ Buildbot that runs 'make polly-test' - - Raghesh,
Andreas + +done
+http://google1.osuosl.org:8011/console + Tobias,
Raghesh,
Andreas Nightly performance/coverage tests
(with the llvm From grosser at fim.uni-passau.de Mon Jul 18 05:55:11 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 10:55:11 -0000 Subject: [llvm-commits] [zorg] r135386 - /zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Message-ID: <20110718105511.6347F2A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 05:55:11 2011 New Revision: 135386 URL: http://llvm.org/viewvc/llvm-project?rev=135386&view=rev Log: Some tweaks for new Polly Builder - Always check out the latest version of isl and CLooG (Otherwise we try to check out the svn revision numbers) - Take advantage of possible concurrency by using -j%jobs - Do not fail, if the builddir already exists. Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=135386&r1=135385&r2=135386&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Mon Jul 18 05:55:11 2011 @@ -17,11 +17,13 @@ # Get Cloog f.addStep(Git(repourl='git://repo.or.cz/cloog.git', mode='update', - workdir=cloog_srcdir)) + workdir=cloog_srcdir, + alwaysUseLatest=True)) # Get isl f.addStep(Git(repourl='git://repo.or.cz/isl.git', mode='update', - workdir=isl_srcdir)) + workdir=isl_srcdir, + alwaysUseLatest=True)) # Build isl f.addStep(ShellCommand(name="autogen-isl", command=["./autogen.sh"], @@ -38,7 +40,7 @@ workdir=isl_srcdir, description=['isl-configure'])) f.addStep(ShellCommand(name="build-isl", - command=["make"], + command=["make", WithProperties("-j%s" % jobs)], haltOnFailure=True, description=["build isl"], workdir=isl_srcdir)) @@ -66,7 +68,7 @@ workdir=cloog_srcdir, description=['cloog-configure'])) f.addStep(ShellCommand(name="build-cloog", - command=["make"], + command=["make", WithProperties("-j%s" % jobs)], haltOnFailure=True, description=["build cloog"], workdir=cloog_srcdir)) @@ -103,7 +105,7 @@ workdir='%s/tools/polly' % llvm_srcdir)) # Create configuration files with cmake f.addStep(ShellCommand(name="create-build-dir", - command=["mkdir", llvm_objdir], + command=["mkdir", "-p", llvm_objdir], haltOnFailure=False, description=["create build dir"], workdir=".")) @@ -116,7 +118,7 @@ workdir=llvm_objdir)) # Build Polly f.addStep(ShellCommand(name="build_polly", - command=["make"], + command=["make", WithProperties("-j%s" % jobs)], haltOnFailure=True, description=["build polly"], workdir=llvm_objdir)) From grosser at fim.uni-passau.de Mon Jul 18 06:00:13 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 11:00:13 -0000 Subject: [llvm-commits] [polly] r135387 - /polly/trunk/www/menu.html.incl Message-ID: <20110718110013.BDFD42A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 06:00:13 2011 New Revision: 135387 URL: http://llvm.org/viewvc/llvm-project?rev=135387&view=rev Log: www: Add link to buildbot into main menu Modified: polly/trunk/www/menu.html.incl Modified: polly/trunk/www/menu.html.incl URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/menu.html.incl?rev=135387&r1=135386&r2=135387&view=diff ============================================================================== --- polly/trunk/www/menu.html.incl (original) +++ polly/trunk/www/menu.html.incl Mon Jul 18 06:00:13 2011 @@ -15,12 +15,13 @@
- + - llvm-commits List + llvm-commits Mailing List - polly-dev List + polly-dev Mailing List Bug Reports + Buildbot
From fvbommel at gmail.com Mon Jul 18 06:58:53 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 11:58:53 -0000 Subject: [llvm-commits] [llvm] r135389 - /llvm/trunk/include/llvm/ADT/ArrayRef.h Message-ID: <20110718115853.751E12A6C12C@llvm.org> Author: fvbommel Date: Mon Jul 18 06:58:53 2011 New Revision: 135389 URL: http://llvm.org/viewvc/llvm-project?rev=135389&view=rev Log: Introduce the 'makeArrayRef(...)' family of functions, which fills a similar role for ArrayRef<> as std::make_pair() fills for std::pair<>: they return the right instantiation of ArrayRef based on the types of the parameters. They mostly mirror the ArrayRef constructors, with two exceptions: * There's no function mirroring the default constructor because it wouldn't have any parameters to deduce the right ArrayRef from. * There's an explicit SmallVector overload in addition to the SmallVectorImpl overload. Without it, the single-element overload would try to create an ArrayRef > because it's a better match according to the overloading rules. (And both overloads are used in the current tree, so neither is redundant) Modified: llvm/trunk/include/llvm/ADT/ArrayRef.h Modified: llvm/trunk/include/llvm/ADT/ArrayRef.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ArrayRef.h?rev=135389&r1=135388&r2=135389&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ArrayRef.h (original) +++ llvm/trunk/include/llvm/ADT/ArrayRef.h Mon Jul 18 06:58:53 2011 @@ -147,7 +147,53 @@ /// @} }; - + + /// @name ArrayRef Convenience constructors + /// @{ + + /// Construct an ArrayRef from a single element. + template + ArrayRef makeArrayRef(const T &OneElt) { + return OneElt; + } + + /// Construct an ArrayRef from a pointer and length. + template + ArrayRef makeArrayRef(const T *data, size_t length) { + return ArrayRef(data, length); + } + + /// Construct an ArrayRef from a range. + template + ArrayRef makeArrayRef(const T *begin, const T *end) { + return ArrayRef(begin, end); + } + + /// Construct an ArrayRef from a SmallVector. + template + ArrayRef makeArrayRef(const SmallVectorImpl &Vec) { + return Vec; + } + + /// Construct an ArrayRef from a SmallVector. + template + ArrayRef makeArrayRef(const SmallVector &Vec) { + return Vec; + } + + /// Construct an ArrayRef from a std::vector. + template + ArrayRef makeArrayRef(const std::vector &Vec) { + return Vec; + } + + /// Construct an ArrayRef from a C array. + template + ArrayRef makeArrayRef(const T (&Arr)[N]) { + return Arr; + } + + /// @} /// @name ArrayRef Comparison Operators /// @{ From fvbommel at gmail.com Mon Jul 18 07:00:32 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 12:00:32 -0000 Subject: [llvm-commits] [llvm] r135390 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/Analysis/ValueTracking.cpp lib/AsmParser/LLParser.cpp lib/CodeGen/LiveRangeEdit.h lib/CodeGen/RegAllocGreedy.cpp lib/CodeGen/RegisterClassInfo.h lib/Linker/LinkModules.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/CBackend/CBackend.cpp lib/Transforms/InstCombine/InstructionCombining.cpp lib/VMCore/Core.cpp utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110718120032.A6D1C2A6C124@llvm.org> Author: fvbommel Date: Mon Jul 18 07:00:32 2011 New Revision: 135390 URL: http://llvm.org/viewvc/llvm-project?rev=135390&view=rev Log: Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.h llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/RegisterClassInfo.h llvm/trunk/lib/Linker/LinkModules.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/lib/VMCore/Core.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Jul 18 07:00:32 2011 @@ -234,7 +234,7 @@ /// virtual ArrayRef getRawAllocationOrder(const MachineFunction &MF) const { - return ArrayRef(begin(), getNumRegs()); + return makeArrayRef(begin(), getNumRegs()); } /// getSize - Return the size of the register in bytes, which is also the size Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Mon Jul 18 07:00:32 2011 @@ -1358,8 +1358,7 @@ return NULL; // Insert the value in the new (sub) aggregrate - return llvm::InsertValueInst::Create(To, V, - ArrayRef(Idxs).slice(IdxSkip), + return llvm::InsertValueInst::Create(To, V, makeArrayRef(Idxs).slice(IdxSkip), "tmp", InsertBefore); } @@ -1435,9 +1434,7 @@ // %C = insertvalue {i32, i32 } %A, i32 11, 1 // which allows the unused 0,0 element from the nested struct to be // removed. - return BuildSubAggregate(V, - ArrayRef(idx_range.begin(), - req_idx), + return BuildSubAggregate(V, makeArrayRef(idx_range.begin(), req_idx), InsertBefore); else // We can't handle this without inserting insertvalues @@ -1455,7 +1452,7 @@ // requested (though possibly only partially). Now we recursively look at // the inserted value, passing any remaining indices. return FindInsertedValue(I->getInsertedValueOperand(), - ArrayRef(req_idx, idx_range.end()), + makeArrayRef(req_idx, idx_range.end()), InsertBefore); } else if (ExtractValueInst *I = dyn_cast(V)) { // If we're extracting a value from an aggregrate that was extracted from Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Jul 18 07:00:32 2011 @@ -2519,8 +2519,8 @@ return Error(ID.Loc, "element " + Twine(i) + " of struct initializer doesn't match struct element type"); - V = ConstantStruct::get(ST, ArrayRef(ID.ConstantStructElts, - ID.UIntVal)); + V = ConstantStruct::get(ST, makeArrayRef(ID.ConstantStructElts, + ID.UIntVal)); } else return Error(ID.Loc, "constant expression type mismatch"); return false; Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Mon Jul 18 07:00:32 2011 @@ -115,7 +115,7 @@ LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } ArrayRef regs() const { - return ArrayRef(newRegs_).slice(firstNew_); + return makeArrayRef(newRegs_).slice(firstNew_); } /// FIXME: Temporary accessors until we can get rid of Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Jul 18 07:00:32 2011 @@ -684,7 +684,7 @@ assert(T < GroupSize && "Array overflow"); TBS[T] = Number; if (++T == GroupSize) { - SpillPlacer->addLinks(ArrayRef(TBS, T)); + SpillPlacer->addLinks(makeArrayRef(TBS, T)); T = 0; } continue; @@ -714,7 +714,7 @@ ArrayRef Array(BCS, B); SpillPlacer->addConstraints(Array); - SpillPlacer->addLinks(ArrayRef(TBS, T)); + SpillPlacer->addLinks(makeArrayRef(TBS, T)); } void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { @@ -749,8 +749,7 @@ // Any new blocks to add? if (ActiveBlocks.size() == AddedTo) break; - addThroughConstraints(Cand.Intf, - ArrayRef(ActiveBlocks).slice(AddedTo)); + addThroughConstraints(Cand.Intf, makeArrayRef(ActiveBlocks).slice(AddedTo)); AddedTo = ActiveBlocks.size(); // Perhaps iterating can enable more bundles? Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.h?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.h (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.h Mon Jul 18 07:00:32 2011 @@ -32,7 +32,7 @@ RCInfo() : Tag(0), NumRegs(0) {} operator ArrayRef() const { - return ArrayRef(Order.get(), NumRegs); + return makeArrayRef(Order.get(), NumRegs); } }; Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Mon Jul 18 07:00:32 2011 @@ -261,7 +261,7 @@ cast(Ty)->getAddressSpace()); case Type::FunctionTyID: return *Entry = FunctionType::get(ElementTypes[0], - ArrayRef(ElementTypes).slice(1), + makeArrayRef(ElementTypes).slice(1), cast(Ty)->isVarArg()); case Type::StructTyID: // Note that this is only reached for anonymous structs. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jul 18 07:00:32 2011 @@ -487,19 +487,19 @@ if (!TFI->hasFP(MF)) { if (!STI.isR9Reserved()) - return ArrayRef(GPREven1); + return makeArrayRef(GPREven1); else - return ArrayRef(GPREven4); + return makeArrayRef(GPREven4); } else if (FramePtr == ARM::R7) { if (!STI.isR9Reserved()) - return ArrayRef(GPREven2); + return makeArrayRef(GPREven2); else - return ArrayRef(GPREven5); + return makeArrayRef(GPREven5); } else { // FramePtr == ARM::R11 if (!STI.isR9Reserved()) - return ArrayRef(GPREven3); + return makeArrayRef(GPREven3); else - return ArrayRef(GPREven6); + return makeArrayRef(GPREven6); } } else if (HintType == ARMRI::RegPairOdd) { if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) @@ -509,19 +509,19 @@ if (!TFI->hasFP(MF)) { if (!STI.isR9Reserved()) - return ArrayRef(GPROdd1); + return makeArrayRef(GPROdd1); else - return ArrayRef(GPROdd4); + return makeArrayRef(GPROdd4); } else if (FramePtr == ARM::R7) { if (!STI.isR9Reserved()) - return ArrayRef(GPROdd2); + return makeArrayRef(GPROdd2); else - return ArrayRef(GPROdd5); + return makeArrayRef(GPROdd5); } else { // FramePtr == ARM::R11 if (!STI.isR9Reserved()) - return ArrayRef(GPROdd3); + return makeArrayRef(GPROdd3); else - return ArrayRef(GPROdd6); + return makeArrayRef(GPROdd6); } } return RC->getRawAllocationOrder(MF); Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Jul 18 07:00:32 2011 @@ -3559,7 +3559,7 @@ i != e; ++i) { Type *IndexedTy = ExtractValueInst::getIndexedType(IVI.getOperand(0)->getType(), - ArrayRef(b, i+1)); + makeArrayRef(b, i+1)); if (IndexedTy->isArrayTy()) Out << ".array[" << *i << "]"; else @@ -3581,7 +3581,7 @@ i != e; ++i) { Type *IndexedTy = ExtractValueInst::getIndexedType(EVI.getOperand(0)->getType(), - ArrayRef(b, i+1)); + makeArrayRef(b, i+1)); if (IndexedTy->isArrayTy()) Out << ".array[" << *i << "]"; else Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Jul 18 07:00:32 2011 @@ -1242,7 +1242,7 @@ Value *NewEV = Builder->CreateExtractValue(IV->getAggregateOperand(), EV.getIndices()); return InsertValueInst::Create(NewEV, IV->getInsertedValueOperand(), - ArrayRef(insi, inse)); + makeArrayRef(insi, inse)); } if (insi == inse) // The insert list is a prefix of the extract list @@ -1254,7 +1254,7 @@ // with // %E extractvalue { i32 } { i32 42 }, 0 return ExtractValueInst::Create(IV->getInsertedValueOperand(), - ArrayRef(exti, exte)); + makeArrayRef(exti, exte)); } if (IntrinsicInst *II = dyn_cast(Agg)) { // We're extracting from an intrinsic, see if we're the only user, which Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Mon Jul 18 07:00:32 2011 @@ -506,7 +506,7 @@ LLVMValueRef LLVMMDNodeInContext(LLVMContextRef C, LLVMValueRef *Vals, unsigned Count) { return wrap(MDNode::get(*unwrap(C), - ArrayRef(unwrap(Vals, Count), Count))); + makeArrayRef(unwrap(Vals, Count), Count))); } LLVMValueRef LLVMMDNode(LLVMValueRef *Vals, unsigned Count) { @@ -575,8 +575,7 @@ LLVMValueRef *ConstantVals, unsigned Count, LLVMBool Packed) { Constant **Elements = unwrap(ConstantVals, Count); - return wrap(ConstantStruct::getAnon(*unwrap(C), - ArrayRef(Elements, Count), + return wrap(ConstantStruct::getAnon(*unwrap(C), makeArrayRef(Elements, Count), Packed != 0)); } @@ -602,11 +601,11 @@ Constant **Elements = unwrap(ConstantVals, Count); StructType *Ty = cast(unwrap(StructTy)); - return wrap(ConstantStruct::get(Ty, ArrayRef(Elements, Count))); + return wrap(ConstantStruct::get(Ty, makeArrayRef(Elements, Count))); } LLVMValueRef LLVMConstVector(LLVMValueRef *ScalarConstantVals, unsigned Size) { - return wrap(ConstantVector::get(ArrayRef( + return wrap(ConstantVector::get(makeArrayRef( unwrap(ScalarConstantVals, Size), Size))); } /*--.. Constant expressions ................................................--*/ @@ -934,8 +933,7 @@ LLVMValueRef LLVMConstExtractValue(LLVMValueRef AggConstant, unsigned *IdxList, unsigned NumIdx) { return wrap(ConstantExpr::getExtractValue(unwrap(AggConstant), - ArrayRef(IdxList, - NumIdx))); + makeArrayRef(IdxList, NumIdx))); } LLVMValueRef LLVMConstInsertValue(LLVMValueRef AggConstant, @@ -943,8 +941,7 @@ unsigned *IdxList, unsigned NumIdx) { return wrap(ConstantExpr::getInsertValue(unwrap(AggConstant), unwrap(ElementValueConstant), - ArrayRef(IdxList, - NumIdx))); + makeArrayRef(IdxList, NumIdx))); } LLVMValueRef LLVMConstInlineAsm(LLVMTypeRef Ty, const char *AsmString, @@ -1680,7 +1677,7 @@ LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch, const char *Name) { return wrap(unwrap(B)->CreateInvoke(unwrap(Fn), unwrap(Then), unwrap(Catch), - ArrayRef(unwrap(Args), NumArgs), + makeArrayRef(unwrap(Args), NumArgs), Name)); } @@ -2064,7 +2061,7 @@ LLVMValueRef *Args, unsigned NumArgs, const char *Name) { return wrap(unwrap(B)->CreateCall(unwrap(Fn), - ArrayRef(unwrap(Args), NumArgs), + makeArrayRef(unwrap(Args), NumArgs), Name)); } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=135390&r1=135389&r2=135390&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jul 18 07:00:32 2011 @@ -526,9 +526,9 @@ OS << " };\n"; } OS << " static const ArrayRef Order[] = {\n" - << " ArrayRef(" << RC.getName(); + << " makeArrayRef(" << RC.getName(); for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) - OS << "),\n ArrayRef(AltOrder" << oi; + OS << "),\n makeArrayRef(AltOrder" << oi; OS << ")\n };\n const unsigned Select = " << RC.getName() << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() << ");\n return Order[Select];\n}\n"; From fvbommel at gmail.com Mon Jul 18 07:31:03 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 12:31:03 -0000 Subject: [llvm-commits] [llvm] r135391 - /llvm/trunk/include/llvm/ADT/ArrayRef.h Message-ID: <20110718123103.E049A2A6C12C@llvm.org> Author: fvbommel Date: Mon Jul 18 07:31:03 2011 New Revision: 135391 URL: http://llvm.org/viewvc/llvm-project?rev=135391&view=rev Log: Hopefully fix some GCC-based buildbots. GCC apparently decays the array to a pointer here before overload resolution, so construct with an explicit length instead. Modified: llvm/trunk/include/llvm/ADT/ArrayRef.h Modified: llvm/trunk/include/llvm/ADT/ArrayRef.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ArrayRef.h?rev=135391&r1=135390&r2=135391&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ArrayRef.h (original) +++ llvm/trunk/include/llvm/ADT/ArrayRef.h Mon Jul 18 07:31:03 2011 @@ -190,7 +190,7 @@ /// Construct an ArrayRef from a C array. template ArrayRef makeArrayRef(const T (&Arr)[N]) { - return Arr; + return ArrayRef(Arr, N); } /// @} From dblaikie at gmail.com Mon Jul 18 09:28:04 2011 From: dblaikie at gmail.com (David Blaikie) Date: Mon, 18 Jul 2011 07:28:04 -0700 Subject: [llvm-commits] [llvm] r135391 - /llvm/trunk/include/llvm/ADT/ArrayRef.h In-Reply-To: <20110718123103.E049A2A6C12C@llvm.org> References: <20110718123103.E049A2A6C12C@llvm.org> Message-ID: > > template > ArrayRef makeArrayRef(const T (&Arr)[N]) { > - return Arr; > + return ArrayRef(Arr, N); > } > If you're going to implement this specialization this way you could probably just remove the ArrayRef(const T(&)[N]) ctor entirely since no one should/will ever use it. Alternatively would "return ArrayRef(Arr)" avoid the pointer degeneration? (& if that ctor doesn't work correctly (even if it's just because of a misimplementation* on a mainstream compiler) implicitly, should we just mark it explicit to be on the safe side?) * is this a bug in GCC? filed somewhere? -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/2acb5579/attachment.html From fvbommel at gmail.com Mon Jul 18 09:36:36 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 18 Jul 2011 16:36:36 +0200 Subject: [llvm-commits] [llvm] r135391 - /llvm/trunk/include/llvm/ADT/ArrayRef.h In-Reply-To: References: <20110718123103.E049A2A6C12C@llvm.org> Message-ID: 2011/7/18 David Blaikie : >> ? template >> ? ArrayRef makeArrayRef(const T (&Arr)[N]) { >> - ? ?return Arr; >> + ? ?return ArrayRef(Arr, N); >> ? } > > If you're going to implement this specialization this way you could probably > just remove the ArrayRef(const T(&)[N]) ctor entirely since no one > should/will ever use it. Alternatively would "return ArrayRef(Arr)" avoid > the pointer degeneration? (& if that ctor doesn't work correctly (even if Actually, the constructor will still be used for implicit conversions from arrays, which are used in man places in the tree still. I don't know if the version with an explicit constructor but implicit length will work, I just committed this blindly to fix it (I didn't have time to try it with GCC myself). > it's just because of a misimplementation* on a mainstream compiler) > implicitly, should we just mark it explicit to be on the safe side?) As I said, the constructor seems to work fine for the many implicit conversions from arrays, so there's no need to mark it explicit. The problem seems to be specific to array reference parameter --> ArrayRef conversion as in this function. > * is this a bug in GCC? filed somewhere? No idea, I've been a bit too busy today to investigate. From dblaikie at gmail.com Mon Jul 18 09:52:23 2011 From: dblaikie at gmail.com (David Blaikie) Date: Mon, 18 Jul 2011 07:52:23 -0700 Subject: [llvm-commits] [llvm] r135391 - /llvm/trunk/include/llvm/ADT/ArrayRef.h In-Reply-To: References: <20110718123103.E049A2A6C12C@llvm.org> Message-ID: > > Actually, the constructor will still be used for implicit conversions > from arrays > Oh, right, sorry to jump the gun. > The problem seems to be specific to array reference parameter --> ArrayRef > conversion as in this function. > In all other cases it's probably the case that it's used untemplated (the T is not being deduced from arguments, but explicitly specified in the function signature) so the compiler's not trying to guess. I'd probably pick the mapping straight through to the matching ctor, but I'm sure it doesn't matter either way (just passing one integer through an extra function call to a really simple inline function anyway). I might play around with GCC's behavior there at some point to see which compiler(s) are right, etc. Thanks for the explanation, - David -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/9d42f326/attachment.html From greened at obbligato.org Mon Jul 18 10:43:41 2011 From: greened at obbligato.org (David A. Greene) Date: Mon, 18 Jul 2011 10:43:41 -0500 Subject: [llvm-commits] [PATCH] Make Inits FoldingSetNodes In-Reply-To: <1B1170A1-81BE-4CD1-BC19-EE62ABB2E55F@2pi.dk> (Jakob Stoklund Olesen's message of "Fri, 15 Jul 2011 17:03:54 -0700") References: <1B1170A1-81BE-4CD1-BC19-EE62ABB2E55F@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: > Certainly. Let me clean it up a bit first ;-) > > Do you need all types to be unique? I have stuff like: > I could easily use a DenseMap to unique everything. Yeah, I would need them all to be unique. Thanks Jakob! -Dave From bob.wilson at apple.com Mon Jul 18 10:46:55 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 18 Jul 2011 15:46:55 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135392 - /llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Message-ID: <20110718154655.93C032A6C12C@llvm.org> Author: bwilson Date: Mon Jul 18 10:46:55 2011 New Revision: 135392 URL: http://llvm.org/viewvc/llvm-project?rev=135392&view=rev Log: Fix a build-breaking typo. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=135392&r1=135391&r2=135392&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Mon Jul 18 10:46:55 2011 @@ -1515,7 +1515,7 @@ intOpTypes[0] = ResultType; intOpTypes[1] = Ops[1]->getType(); - intFn = Intrinsic::getDeclaration(TheModule, intID, intOpTypes2); + intFn = Intrinsic::getDeclaration(TheModule, intID, intOpTypes); Result = Builder.CreateCall2(intFn, Ops[0], Ops[1]); break; From greened at obbligato.org Mon Jul 18 10:52:29 2011 From: greened at obbligato.org (David A. Greene) Date: Mon, 18 Jul 2011 10:52:29 -0500 Subject: [llvm-commits] [PATCH] Make Inits FoldingSetNodes In-Reply-To: <22224557-527C-4091-A2A9-0D5A4EA3449E@2pi.dk> (Jakob Stoklund Olesen's message of "Fri, 15 Jul 2011 18:04:07 -0700") References: <22224557-527C-4091-A2A9-0D5A4EA3449E@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: > The attached patch makes most RecTy subclasses into singletons with a get() factory method. > > It also uniques DefInit instances because of the Record-> DefInit -> RecordRecTy -> DefInit chicken and egg problem. > > Please review! Looks good to me. Your DefInit interning is much better than mine due to RecTys being unique. :) -Dave From sabre at nondot.org Mon Jul 18 11:04:11 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 18 Jul 2011 16:04:11 -0000 Subject: [llvm-commits] [llvm] r135394 - /llvm/trunk/include/llvm/ADT/TinyPtrVector.h Message-ID: <20110718160411.8A2692A6C130@llvm.org> Author: lattner Date: Mon Jul 18 11:04:11 2011 New Revision: 135394 URL: http://llvm.org/viewvc/llvm-project?rev=135394&view=rev Log: remove pasto Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/TinyPtrVector.h?rev=135394&r1=135393&r2=135394&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/TinyPtrVector.h (original) +++ llvm/trunk/include/llvm/ADT/TinyPtrVector.h Mon Jul 18 11:04:11 2011 @@ -6,10 +6,6 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// This file defines the Type class. -// -//===----------------------------------------------------------------------===// #ifndef LLVM_ADT_TINYPTRVECTOR_H #define LLVM_ADT_TINYPTRVECTOR_H From sabre at nondot.org Mon Jul 18 11:35:57 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 18 Jul 2011 16:35:57 -0000 Subject: [llvm-commits] [llvm] r135396 - /llvm/trunk/include/llvm/ADT/TinyPtrVector.h Message-ID: <20110718163557.D04C62A6C12C@llvm.org> Author: lattner Date: Mon Jul 18 11:35:57 2011 New Revision: 135396 URL: http://llvm.org/viewvc/llvm-project?rev=135396&view=rev Log: various cleanups noticed by Frits Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h Modified: llvm/trunk/include/llvm/ADT/TinyPtrVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/TinyPtrVector.h?rev=135396&r1=135395&r2=135396&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/TinyPtrVector.h (original) +++ llvm/trunk/include/llvm/ADT/TinyPtrVector.h Mon Jul 18 11:35:57 2011 @@ -37,9 +37,9 @@ delete V; } - /// empty() - This vector can be empty if it contains no element, or if it - /// contains a pointer to an empty vector. bool empty() const { + // This vector can be empty if it contains no element, or if it + // contains a pointer to an empty vector. if (Val.isNull()) return true; if (VecTy *Vec = Val.template dyn_cast()) return Vec->empty(); @@ -49,9 +49,9 @@ unsigned size() const { if (empty()) return 0; - if (Val. template is()) + if (Val.template is()) return 1; - return Val. template get()->size(); + return Val.template get()->size(); } typedef const EltTy *iterator; @@ -83,9 +83,9 @@ return V; } - assert(i < Val. template get()->size() && + assert(i < Val.template get()->size() && "tinyvector index out of range"); - return (*Val. template get())[i]; + return (*Val.template get())[i]; } EltTy front() const { @@ -105,7 +105,7 @@ } // If we have a single value, convert to a vector. - if (EltTy V = Val.template dyn_cast()) { + if (EltTy V = Val.template dyn_cast()) { Val = new VecTy(); Val.template get()->push_back(V); } From sabre at nondot.org Mon Jul 18 11:36:22 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 18 Jul 2011 09:36:22 -0700 Subject: [llvm-commits] [llvm] r135365 - in /llvm/trunk: docs/ProgrammersManual.html include/llvm/ADT/TinyPtrVector.h In-Reply-To: References: <20110718014002.5E44E2A6C12C@llvm.org> Message-ID: <24CF3FE9-76E3-4121-9BD1-B81A6BD3EEF3@nondot.org> On Jul 18, 2011, at 1:25 AM, Frits van Bommel wrote: >> +//===----------------------------------------------------------------------===// >> +// >> +// This file defines the Type class. > > s/Type/TinyPtrVector/ Zapped, thanks. Too many thoughts about types are something :) >> +/// TinyPtrVector - This class is specialized for cases where there are >> +/// normally 0 or 1 element in a vector, but is general enough to go beyond that >> +/// when required. >> +/// >> +/// NOTE: This container doesn't allow you to store a null pointer into it. > > This restriction could be lifted by using a null VecTy* as the empty > value instead of any null pointer (what empty() currently checks for) > or a null EltTy (what can actually happen). > > But if none of the use cases you have in mind for this require it this > might not be worth the added complexity. Interesting! This approach didn't occur to me. I think it would be useful to support null pointers: if nothing else, it takes away a gotcha that will bite people at runtime if they're unaware of it. One issue: if you swap the elements of the pointer union, you'll break begin/end, because they depend on being able to take the address of the single-pointer case and not have the low bit set. >> + /// empty() - This vector can be empty if it contains no element, or if it >> + /// contains a pointer to an empty vector. > > This doesn't seem doc-comment worthy. It talks about implementation > details the user shouldn't care about and which aren't mentioned in > any of the other documentation. > All other comments of this kind are inside the methods, which is where > this one belongs too. Fixed. >> + unsigned size() const { >> + if (empty()) >> + return 0; >> + if (Val. template is()) > > There's an extra space before 'template', which doesn't match the > style used in most other cases in this file. Fixed. Gotta love C++ :) Thanks for the review Frits! -Chris From greened at obbligato.org Mon Jul 18 11:42:06 2011 From: greened at obbligato.org (David A. Greene) Date: Mon, 18 Jul 2011 11:42:06 -0500 Subject: [llvm-commits] FW: [PATCH] Fix a bug in GenWidenVectorLoads In-Reply-To: <6594DDFF12B03D4E89690887C24869940296C41129@hasmsx504.ger.corp.intel.com> (Nadav Rotem's message of "Sat, 16 Jul 2011 13:37:25 +0300") References: <6594DDFF12B03D4E89690887C24869940296C41129@hasmsx504.ger.corp.intel.com> Message-ID: "Rotem, Nadav" writes: > Ping. > > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Rotem, Nadav > Sent: Wednesday, July 13, 2011 10:30 > To: llvm-commits at cs.uiuc.edu > Subject: [llvm-commits] [PATCH] Fix a bug in GenWidenVectorLoads > > On AVX, we can load 8xi32 at a time. The bug happens when two uneven loads are used: When we load the v12i32 type, the GenWidenVectorLoads method > generates two loads: v8xi32 and v4xi32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to fix the smaller > value. The test ?widen_load-2.ll? exposes this bug (if you implement wide loads?). Looks fine as far as I can tell. -Dave From jyasskin at google.com Mon Jul 18 11:57:39 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 18 Jul 2011 09:57:39 -0700 Subject: [llvm-commits] [PATCH] Add APInt(numBits, ArrayRef bigVal) constructor (issue4749046) In-Reply-To: <20cf301d427cfb2c4a04a83d7a52@google.com> References: <20cf301d427cfb2c4a04a83d7a52@google.com> Message-ID: Here's the patch. On Sat, Jul 16, 2011 at 10:51 PM, wrote: > Reviewers: eli.friedman_gmail.com, > > Message: > Initial diff at > http://codereview.appspot.com/download/issue4749046_1.diff > > Description: > Add APInt(numBits, ArrayRef bigVal) constructor to prevent > future ambiguity errors like the one corrected by r135261. ?Migrate all > LLVM callers of the old constructor to the new one. > > > Please review this at http://codereview.appspot.com/4749046/ > > Affected files: > ? M include/llvm/ADT/APInt.h > ? M lib/AsmParser/LLLexer.cpp > ? M lib/Bitcode/Reader/BitcodeReader.cpp > ? M lib/CodeGen/SelectionDAG/FastISel.cpp > ? M lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp > ? M lib/CodeGen/SelectionDAG/SelectionDAG.cpp > ? M lib/ExecutionEngine/ExecutionEngine.cpp > ? M lib/Support/APFloat.cpp > ? M lib/Support/APInt.cpp > ? M lib/VMCore/ConstantFold.cpp > ? M lib/VMCore/Core.cpp > ? M unittests/ADT/APIntTest.cpp > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: apint_array.diff Type: application/octet-stream Size: 15876 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/84553b40/attachment.obj From stoklund at 2pi.dk Mon Jul 18 12:02:57 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 17:02:57 -0000 Subject: [llvm-commits] [llvm] r135399 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenRegisters.cpp Record.cpp Record.h TGParser.cpp TGParser.h Message-ID: <20110718170257.80B252A6C12C@llvm.org> Author: stoklund Date: Mon Jul 18 12:02:57 2011 New Revision: 135399 URL: http://llvm.org/viewvc/llvm-project?rev=135399&view=rev Log: Intern all RecTy subclass instances to avoid duplicates. Make all of the RecTy constructors private, and use get() factory methods instead. Return singleton instances when it makes sense. ListTy instance pointers are stored in the element RecTy instance. BitsRecTy instance pointers, one per length, are stored in a static vector. Also unique DefInit instances. A Record has a unique DefInit which has a unique RecordRecTy instance. This saves some 200k-300k RecTy allocations when parsing ARM.td. It reduces TableGen's heap usage by almost 50%. Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenRegisters.cpp llvm/trunk/utils/TableGen/Record.cpp llvm/trunk/utils/TableGen/Record.h llvm/trunk/utils/TableGen/TGParser.cpp llvm/trunk/utils/TableGen/TGParser.h Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jul 18 12:02:57 2011 @@ -1771,7 +1771,7 @@ if (BitsInit *BI = dynamic_cast(TheInit)) { // Turn this into an IntInit. - Init *II = BI->convertInitializerTo(new IntRecTy()); + Init *II = BI->convertInitializerTo(IntRecTy::get()); if (II == 0 || !dynamic_cast(II)) error("Bits value must be constants!"); return ParseTreePattern(II, OpName); @@ -2180,7 +2180,7 @@ // Find some SDNode. assert(!SDNodes.empty() && "No SDNodes parsed?"); - Init *SomeSDNode = new DefInit(SDNodes.begin()->first); + Init *SomeSDNode = DefInit::get(SDNodes.begin()->first); for (unsigned iter = 0; iter != 2; ++iter) { for (unsigned i = 0, e = DefaultOps[iter].size(); i != e; ++i) { Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Mon Jul 18 12:02:57 2011 @@ -182,7 +182,7 @@ // Precompute some types. Record *RegisterCl = Def->getRecords().getClass("Register"); - RecTy *RegisterRecTy = new RecordRecTy(RegisterCl); + RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); StringInit *BlankName = new StringInit(""); // Zip them up. @@ -195,7 +195,7 @@ Record *Reg = Lists[i][n]; if (i) Name += '_'; Name += Reg->getName(); - Tuple.push_back(new DefInit(Reg)); + Tuple.push_back(DefInit::get(Reg)); CostPerUse = std::max(CostPerUse, unsigned(Reg->getValueAsInt("CostPerUse"))); } Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Mon Jul 18 12:02:57 2011 @@ -23,8 +23,20 @@ // Type implementations //===----------------------------------------------------------------------===// +BitRecTy BitRecTy::Shared; +IntRecTy IntRecTy::Shared; +StringRecTy StringRecTy::Shared; +CodeRecTy CodeRecTy::Shared; +DagRecTy DagRecTy::Shared; + void RecTy::dump() const { print(errs()); } +ListRecTy *RecTy::getListTy() { + if (!ListTy) + ListTy = new ListRecTy(this); + return ListTy; +} + Init *BitRecTy::convertValue(BitsInit *BI) { if (BI->getNumBits() != 1) return 0; // Only accept if just one bit! return BI->getBit(0); @@ -47,6 +59,16 @@ return 0; } +BitsRecTy *BitsRecTy::get(unsigned Sz) { + static std::vector Shared; + if (Sz >= Shared.size()) + Shared.resize(Sz + 1); + BitsRecTy *&Ty = Shared[Sz]; + if (!Ty) + Ty = new BitsRecTy(Sz); + return Ty; +} + std::string BitsRecTy::getAsString() const { return "bits<" + utostr(Size) + ">"; } @@ -231,7 +253,7 @@ return 0; } - return new ListInit(Elements, new ListRecTy(Ty)); + return new ListInit(Elements, this); } Init *ListRecTy::convertValue(TypedInit *TI) { @@ -277,6 +299,10 @@ return 0; } +RecordRecTy *RecordRecTy::get(Record *R) { + return &dynamic_cast(*R->getDefInit()->getType()); +} + std::string RecordRecTy::getAsString() const { return Rec->getName(); } @@ -326,7 +352,7 @@ iend = T1SuperClasses.end(); i != iend; ++i) { - RecordRecTy *SuperRecTy1 = new RecordRecTy(*i); + RecordRecTy *SuperRecTy1 = RecordRecTy::get(*i); RecTy *NewType1 = resolveTypes(SuperRecTy1, T2); if (NewType1 != 0) { if (NewType1 != SuperRecTy1) { @@ -345,7 +371,7 @@ iend = T2SuperClasses.end(); i != iend; ++i) { - RecordRecTy *SuperRecTy2 = new RecordRecTy(*i); + RecordRecTy *SuperRecTy2 = RecordRecTy::get(*i); RecTy *NewType2 = resolveTypes(T1, SuperRecTy2); if (NewType2 != 0) { if (NewType2 != SuperRecTy2) { @@ -577,7 +603,7 @@ } if (Record *D = (CurRec->getRecords()).getDef(Name)) - return new DefInit(D); + return DefInit::get(D); throw TGError(CurRec->getLoc(), "Undefined reference:'" + Name + "'\n"); } @@ -687,9 +713,9 @@ // try to fold eq comparison for 'bit' and 'int', otherwise fallback // to string objects. IntInit* L = - dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); + dynamic_cast(LHS->convertInitializerTo(IntRecTy::get())); IntInit* R = - dynamic_cast(RHS->convertInitializerTo(new IntRecTy())); + dynamic_cast(RHS->convertInitializerTo(IntRecTy::get())); if (L && R) return new IntInit(L->getValue() == R->getValue()); @@ -902,7 +928,7 @@ if (LHSd->getAsString() == RHSd->getAsString()) { Val = MHSd->getDef(); } - return new DefInit(Val); + return DefInit::get(Val); } if (RHSv) { std::string Val = RHSv->getName(); @@ -941,7 +967,7 @@ case IF: { IntInit *LHSi = dynamic_cast(LHS); - if (Init *I = LHS->convertInitializerTo(new IntRecTy())) + if (Init *I = LHS->convertInitializerTo(IntRecTy::get())) LHSi = dynamic_cast(I); if (LHSi) { if (LHSi->getValue()) { @@ -962,7 +988,7 @@ if (Opc == IF && lhs != LHS) { IntInit *Value = dynamic_cast(lhs); - if (Init *I = lhs->convertInitializerTo(new IntRecTy())) + if (Init *I = lhs->convertInitializerTo(IntRecTy::get())) Value = dynamic_cast(I); if (Value != 0) { // Short-circuit @@ -1156,6 +1182,10 @@ return 0; } +DefInit *DefInit::get(Record *R) { + return R->getDefInit(); +} + RecTy *DefInit::getFieldType(const std::string &FieldName) const { if (const RecordVal *RV = Def->getValue(FieldName)) return RV->getType(); @@ -1270,6 +1300,12 @@ unsigned Record::LastID = 0; +DefInit *Record::getDefInit() { + if (!TheInit) + TheInit = new DefInit(this, new RecordRecTy(this)); + return TheInit; +} + void Record::setName(const std::string &Name) { if (TrackedRecords.getDef(getName()) == this) { TrackedRecords.removeDef(getName()); Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Mon Jul 18 12:02:57 2011 @@ -63,7 +63,10 @@ // Type Classes //===----------------------------------------------------------------------===// -struct RecTy { +class RecTy { + ListRecTy *ListTy; +public: + RecTy() : ListTy(0) {} virtual ~RecTy() {} virtual std::string getAsString() const = 0; @@ -74,6 +77,9 @@ /// converted to the specified type. virtual bool typeIsConvertibleTo(const RecTy *RHS) const = 0; + /// getListTy - Returns the type representing list. + ListRecTy *getListTy(); + public: // These methods should only be called from subclasses of Init virtual Init *convertValue( UnsetInit *UI) { return 0; } virtual Init *convertValue( BitInit *BI) { return 0; } @@ -124,7 +130,11 @@ /// BitRecTy - 'bit' - Represent a single bit /// class BitRecTy : public RecTy { + static BitRecTy Shared; + BitRecTy() {} public: + static BitRecTy *get() { return &Shared; } + virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( BitInit *BI) { return (Init*)BI; } virtual Init *convertValue( BitsInit *BI); @@ -164,8 +174,9 @@ /// class BitsRecTy : public RecTy { unsigned Size; -public: explicit BitsRecTy(unsigned Sz) : Size(Sz) {} +public: + static BitsRecTy *get(unsigned Sz); unsigned getNumBits() const { return Size; } @@ -208,7 +219,11 @@ /// IntRecTy - 'int' - Represent an integer value of no particular size /// class IntRecTy : public RecTy { + static IntRecTy Shared; + IntRecTy() {} public: + static IntRecTy *get() { return &Shared; } + virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( BitInit *BI); virtual Init *convertValue( BitsInit *BI); @@ -246,7 +261,11 @@ /// StringRecTy - 'string' - Represent an string value /// class StringRecTy : public RecTy { + static StringRecTy Shared; + StringRecTy() {} public: + static StringRecTy *get() { return &Shared; } + virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; } @@ -288,9 +307,10 @@ /// class ListRecTy : public RecTy { RecTy *Ty; -public: explicit ListRecTy(RecTy *T) : Ty(T) {} - + friend ListRecTy *RecTy::getListTy(); +public: + static ListRecTy *get(RecTy *T) { return T->getListTy(); } RecTy *getElementType() const { return Ty; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } @@ -331,7 +351,11 @@ /// CodeRecTy - 'code' - Represent an code fragment, function or method. /// class CodeRecTy : public RecTy { + static CodeRecTy Shared; + CodeRecTy() {} public: + static CodeRecTy *get() { return &Shared; } + virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; } @@ -367,7 +391,11 @@ /// DagRecTy - 'dag' - Represent a dag fragment /// class DagRecTy : public RecTy { + static DagRecTy Shared; + DagRecTy() {} public: + static DagRecTy *get() { return &Shared; } + virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; } @@ -407,8 +435,10 @@ /// class RecordRecTy : public RecTy { Record *Rec; -public: explicit RecordRecTy(Record *R) : Rec(R) {} + friend class Record; +public: + static RecordRecTy *get(Record *R); Record *getRecord() const { return Rec; } @@ -633,7 +663,7 @@ class IntInit : public TypedInit { int64_t Value; public: - explicit IntInit(int64_t V) : TypedInit(new IntRecTy), Value(V) {} + explicit IntInit(int64_t V) : TypedInit(IntRecTy::get()), Value(V) {} int64_t getValue() const { return Value; } @@ -671,7 +701,7 @@ std::string Value; public: explicit StringInit(const std::string &V) - : TypedInit(new StringRecTy), Value(V) {} + : TypedInit(StringRecTy::get()), Value(V) {} const std::string &getValue() const { return Value; } @@ -726,11 +756,11 @@ typedef std::vector::const_iterator const_iterator; explicit ListInit(std::vector &Vs, RecTy *EltTy) - : TypedInit(new ListRecTy(EltTy)) { + : TypedInit(ListRecTy::get(EltTy)) { Values.swap(Vs); } explicit ListInit(iterator Start, iterator End, RecTy *EltTy) - : TypedInit(new ListRecTy(EltTy)), Values(Start, End) {} + : TypedInit(ListRecTy::get(EltTy)), Values(Start, End) {} unsigned getSize() const { return Values.size(); } Init *getElement(unsigned i) const { @@ -1034,8 +1064,10 @@ /// class DefInit : public TypedInit { Record *Def; + DefInit(Record *D, RecordRecTy *T) : TypedInit(T), Def(D) {} + friend class Record; public: - explicit DefInit(Record *D) : TypedInit(new RecordRecTy(D)), Def(D) {} + static DefInit *get(Record*); virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); @@ -1111,7 +1143,7 @@ public: DagInit(Init *V, std::string VN, const std::vector > &args) - : TypedInit(new DagRecTy), Val(V), ValName(VN) { + : TypedInit(DagRecTy::get()), Val(V), ValName(VN) { Args.reserve(args.size()); ArgNames.reserve(args.size()); for (unsigned i = 0, e = args.size(); i != e; ++i) { @@ -1121,7 +1153,7 @@ } DagInit(Init *V, std::string VN, const std::vector &args, const std::vector &argNames) - : TypedInit(new DagRecTy), Val(V), ValName(VN), Args(args), + : TypedInit(DagRecTy::get()), Val(V), ValName(VN), Args(args), ArgNames(argNames) { } virtual Init *convertInitializerTo(RecTy *Ty) { @@ -1235,11 +1267,13 @@ // Tracks Record instances. Not owned by Record. RecordKeeper &TrackedRecords; + DefInit *TheInit; + public: // Constructs a record. explicit Record(const std::string &N, SMLoc loc, RecordKeeper &records) : - ID(LastID++), Name(N), Loc(loc), TrackedRecords(records) {} + ID(LastID++), Name(N), Loc(loc), TrackedRecords(records), TheInit(0) {} ~Record() {} @@ -1253,6 +1287,9 @@ SMLoc getLoc() const { return Loc; } + /// get the corresponding DefInit. + DefInit *getDefInit(); + const std::vector &getTemplateArgs() const { return TemplateArgs; } Modified: llvm/trunk/utils/TableGen/TGParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.cpp?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGParser.cpp (original) +++ llvm/trunk/utils/TableGen/TGParser.cpp Mon Jul 18 12:02:57 2011 @@ -106,9 +106,9 @@ return Error(Loc, "Value '" + ValName + "' is not a bits type"); // Convert the incoming value to a bits type of the appropriate size... - Init *BI = V->convertInitializerTo(new BitsRecTy(BitList.size())); + Init *BI = V->convertInitializerTo(BitsRecTy::get(BitList.size())); if (BI == 0) { - V->convertInitializerTo(new BitsRecTy(BitList.size())); + V->convertInitializerTo(BitsRecTy::get(BitList.size())); return Error(Loc, "Initializer is not compatible with bit range"); } @@ -581,13 +581,13 @@ RecTy *TGParser::ParseType() { switch (Lex.getCode()) { default: TokError("Unknown token when expecting a type"); return 0; - case tgtok::String: Lex.Lex(); return new StringRecTy(); - case tgtok::Bit: Lex.Lex(); return new BitRecTy(); - case tgtok::Int: Lex.Lex(); return new IntRecTy(); - case tgtok::Code: Lex.Lex(); return new CodeRecTy(); - case tgtok::Dag: Lex.Lex(); return new DagRecTy(); + case tgtok::String: Lex.Lex(); return StringRecTy::get(); + case tgtok::Bit: Lex.Lex(); return BitRecTy::get(); + case tgtok::Int: Lex.Lex(); return IntRecTy::get(); + case tgtok::Code: Lex.Lex(); return CodeRecTy::get(); + case tgtok::Dag: Lex.Lex(); return DagRecTy::get(); case tgtok::Id: - if (Record *R = ParseClassID()) return new RecordRecTy(R); + if (Record *R = ParseClassID()) return RecordRecTy::get(R); return 0; case tgtok::Bits: { if (Lex.Lex() != tgtok::less) { // Eat 'bits' @@ -604,7 +604,7 @@ return 0; } Lex.Lex(); // Eat '>' - return new BitsRecTy(Val); + return BitsRecTy::get(Val); } case tgtok::List: { if (Lex.Lex() != tgtok::less) { // Eat 'bits' @@ -620,7 +620,7 @@ return 0; } Lex.Lex(); // Eat '>' - return new ListRecTy(SubType); + return ListRecTy::get(SubType); } } } @@ -667,7 +667,7 @@ } if (Record *D = Records.getDef(Name)) - return new DefInit(D); + return DefInit::get(D); Error(NameLoc, "Variable not defined: '" + Name + "'"); return 0; @@ -715,7 +715,7 @@ case tgtok::XEmpty: Lex.Lex(); // eat the operation Code = UnOpInit::EMPTY; - Type = new IntRecTy; + Type = IntRecTy::get(); break; } if (Lex.getCode() != tgtok::l_paren) { @@ -767,7 +767,7 @@ if (Code == UnOpInit::HEAD) { Type = Itemt->getType(); } else { - Type = new ListRecTy(Itemt->getType()); + Type = ListRecTy::get(Itemt->getType()); } } else { assert(LHSt && "expected list type argument in unary operator"); @@ -808,14 +808,14 @@ switch (OpTok) { default: assert(0 && "Unhandled code!"); - case tgtok::XConcat: Code = BinOpInit::CONCAT; Type = new DagRecTy(); break; - case tgtok::XSRA: Code = BinOpInit::SRA; Type = new IntRecTy(); break; - case tgtok::XSRL: Code = BinOpInit::SRL; Type = new IntRecTy(); break; - case tgtok::XSHL: Code = BinOpInit::SHL; Type = new IntRecTy(); break; - case tgtok::XEq: Code = BinOpInit::EQ; Type = new BitRecTy(); break; + case tgtok::XConcat: Code = BinOpInit::CONCAT;Type = DagRecTy::get(); break; + case tgtok::XSRA: Code = BinOpInit::SRA; Type = IntRecTy::get(); break; + case tgtok::XSRL: Code = BinOpInit::SRL; Type = IntRecTy::get(); break; + case tgtok::XSHL: Code = BinOpInit::SHL; Type = IntRecTy::get(); break; + case tgtok::XEq: Code = BinOpInit::EQ; Type = BitRecTy::get(); break; case tgtok::XStrConcat: Code = BinOpInit::STRCONCAT; - Type = new StringRecTy(); + Type = StringRecTy::get(); break; } @@ -932,14 +932,14 @@ if (MHSbits && RHSbits && MHSbits->getNumBits() == RHSbits->getNumBits()) { - Type = new BitRecTy(); + Type = BitRecTy::get(); break; } else { BitInit *MHSbit = dynamic_cast(MHS); BitInit *RHSbit = dynamic_cast(RHS); if (MHSbit && RHSbit) { - Type = new BitRecTy(); + Type = BitRecTy::get(); break; } } @@ -1110,7 +1110,7 @@ Records.addDef(NewRec); // The result of the expression is a reference to the new record. - return new DefInit(NewRec); + return DefInit::get(NewRec); } case tgtok::l_brace: { // Value ::= '{' ValueList '}' SMLoc BraceLoc = Lex.getLoc(); @@ -1129,7 +1129,7 @@ BitsInit *Result = new BitsInit(Vals.size()); for (unsigned i = 0, e = Vals.size(); i != e; ++i) { - Init *Bit = Vals[i]->convertInitializerTo(new BitRecTy()); + Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get()); if (Bit == 0) { Error(BraceLoc, "Element #" + utostr(i) + " (" + Vals[i]->getAsString()+ ") is not convertable to a bit"); Modified: llvm/trunk/utils/TableGen/TGParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.h?rev=135399&r1=135398&r2=135399&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGParser.h (original) +++ llvm/trunk/utils/TableGen/TGParser.h Mon Jul 18 12:02:57 2011 @@ -24,7 +24,7 @@ class Record; class RecordVal; class RecordKeeper; - struct RecTy; + class RecTy; class Init; struct MultiClass; struct SubClassReference; From stoklund at 2pi.dk Mon Jul 18 12:06:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 10:06:06 -0700 Subject: [llvm-commits] [PATCH] Make Inits FoldingSetNodes In-Reply-To: References: <22224557-527C-4091-A2A9-0D5A4EA3449E@2pi.dk> Message-ID: On Jul 18, 2011, at 8:52 AM, David A. Greene wrote: > Jakob Stoklund Olesen writes: > >> The attached patch makes most RecTy subclasses into singletons with a get() factory method. >> >> It also uniques DefInit instances because of the Record-> DefInit -> RecordRecTy -> DefInit chicken and egg problem. >> >> Please review! > > Looks good to me. Your DefInit interning is much better than mine due > to RecTys being unique. :) r135399. Note that I didn't change all of the RecTy pointers into const pointers. I don't think it is necessary since the RecTy classes don't have any public mutators. You could do the same for the Inits - It would require much fewer source changes. /jakob From bruno.cardoso at gmail.com Mon Jul 18 12:16:17 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 18 Jul 2011 10:16:17 -0700 Subject: [llvm-commits] [PATCH] Fix a bug in GenWidenVectorLoads In-Reply-To: <6594DDFF12B03D4E89690887C24869940296BDBBE7@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C24869940296BDBBE7@hasmsx504.ger.corp.intel.com> Message-ID: Nice. LGTM. Can you attach a testcase too? On Wed, Jul 13, 2011 at 12:30 AM, Rotem, Nadav wrote: > On AVX, we can load 8xi32 at a time. The bug happens when two uneven loads > are used: When we load the v12i32 type, the GenWidenVectorLoads method > generates two loads: v8xi32 and v4xi32 and attempts to use CONCAT_VECTORS to > join them. In this fix I concat undef values to fix the smaller value. The > test ?widen_load-2.ll? exposes this bug? (if you implement wide loads?). > > > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From ahatanak at gmail.com Mon Jul 18 12:44:27 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 18 Jul 2011 17:44:27 -0000 Subject: [llvm-commits] [llvm] r135403 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110718174427.B84812A6C12C@llvm.org> Author: ahatanak Date: Mon Jul 18 12:44:27 2011 New Revision: 135403 URL: http://llvm.org/viewvc/llvm-project?rev=135403&view=rev Log: Change destination register operands of SC instructions so that unique virtual registers are used. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135403&r1=135402&r2=135403&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 12:44:27 2011 @@ -740,6 +740,7 @@ unsigned Oldval = RegInfo.createVirtualRegister(RC); unsigned Tmp1 = RegInfo.createVirtualRegister(RC); unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp3 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -804,9 +805,9 @@ BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); } - BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB); + .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -852,6 +853,7 @@ unsigned Tmp10 = RegInfo.createVirtualRegister(RC); unsigned Tmp11 = RegInfo.createVirtualRegister(RC); unsigned Tmp12 = RegInfo.createVirtualRegister(RC); + unsigned Tmp13 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -947,9 +949,10 @@ BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addReg(Addr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp13) + .addReg(Tmp9).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB); + .addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -994,6 +997,7 @@ unsigned Tmp1 = RegInfo.createVirtualRegister(RC); unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp3 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -1051,9 +1055,9 @@ BB = loop2MBB; BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB); + .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); @@ -1097,6 +1101,7 @@ unsigned Tmp7 = RegInfo.createVirtualRegister(RC); unsigned Tmp8 = RegInfo.createVirtualRegister(RC); unsigned Tmp9 = RegInfo.createVirtualRegister(RC); + unsigned Tmp10 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -1161,10 +1166,10 @@ BB = loop2MBB; BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp7) + BuildMI(BB, dl, TII->get(Mips::SC), Tmp10) .addReg(Tmp7).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB); + .addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB); BB->addSuccessor(loop1MBB); BB->addSuccessor(exitMBB); From bruno.cardoso at gmail.com Mon Jul 18 12:51:40 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 18 Jul 2011 17:51:40 -0000 Subject: [llvm-commits] [llvm] r135404 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-128.ll Message-ID: <20110718175140.9B7EE2A6C12C@llvm.org> Author: bruno Date: Mon Jul 18 12:51:40 2011 New Revision: 135404 URL: http://llvm.org/viewvc/llvm-project?rev=135404&view=rev Log: Add AVX 128-bit sqrt versions Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-128.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135404&r1=135403&r2=135404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 18 12:51:40 2011 @@ -1894,6 +1894,17 @@ sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX; } +def : Pat<(f32 (fsqrt FR32:$src)), + (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>; +def : Pat<(f64 (fsqrt FR64:$src)), + (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>; +def : Pat<(f64 (fsqrt (load addr:$src))), + (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX, OptForSize]>; +def : Pat<(f32 (fsqrt (load addr:$src))), + (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>, + Requires<[HasAVX, OptForSize]>; + // Square root. defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>, sse1_fp_unop_p<0x51, "sqrt", fsqrt>, Modified: llvm/trunk/test/CodeGen/X86/avx-128.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-128.ll?rev=135404&r1=135403&r2=135404&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-128.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-128.ll Mon Jul 18 12:51:40 2011 @@ -52,3 +52,21 @@ %conv = sitofp i64 %tmp1 to float ret float %conv } + +; CHECK: vsqrtss +define float @sqrtA(float %a) nounwind uwtable readnone ssp { +entry: + %conv1 = tail call float @sqrtf(float %a) nounwind readnone + ret float %conv1 +} + +declare double @sqrt(double) readnone + +; CHECK: vsqrtsd +define double @sqrtB(double %a) nounwind uwtable readnone ssp { +entry: + %call = tail call double @sqrt(double %a) nounwind readnone + ret double %call +} + +declare float @sqrtf(float) readnone From bruno.cardoso at gmail.com Mon Jul 18 13:11:25 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 18 Jul 2011 18:11:25 -0000 Subject: [llvm-commits] [llvm] r135407 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110718181126.2074F2A6C12C@llvm.org> Author: bruno Date: Mon Jul 18 13:11:25 2011 New Revision: 135407 URL: http://llvm.org/viewvc/llvm-project?rev=135407&view=rev Log: Be more smart with VCVTSS2SD. Also place the patterns close to the definitions. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135407&r1=135406&r2=135407&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 18 13:11:25 2011 @@ -720,8 +720,15 @@ (ins FR32:$src1, f32mem:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>; -def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>, - Requires<[HasAVX]>; + +let Predicates = [HasAVX] in { + def : Pat<(f64 (fextend FR32:$src)), + (VCVTSS2SDrr FR32:$src, FR32:$src)>; + def : Pat<(fextend (loadf32 addr:$src)), + (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>; +} def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), "cvtss2sd\t{$src, $dst|$dst, $src}", @@ -2082,15 +2089,6 @@ def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; -// FIXME: According to the intel manual, DEST[127:64] <- SRC1[127:64], while -// in the non-AVX version bits 127:64 aren't touched. Find a better way to -// represent this instead of always zeroing SRC1. One possible solution is -// to represent the instruction w/ something similar as the "$src1 = $dst" -// constraint but without the tied operands. -def : Pat<(extloadf32 addr:$src), - (VCVTSS2SDrm (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)), addr:$src)>, - Requires<[HasAVX, OptForSpeed]>; - //===----------------------------------------------------------------------===// // SSE 1 & 2 - Load/Store XCSR register //===----------------------------------------------------------------------===// @@ -3633,15 +3631,7 @@ def : Pat<(fextend (loadf32 addr:$src)), (CVTSS2SDrm addr:$src)>; -// FIXME: According to the intel manual, DEST[127:64] <- SRC1[127:64], while -// in the non-AVX version bits 127:64 aren't touched. Find a better way to -// represent this instead of always zeroing SRC1. One possible solution is -// to represent the instruction w/ something similar as the "$src1 = $dst" -// constraint but without the tied operands. -let Predicates = [HasAVX] in - def : Pat<(fextend (loadf32 addr:$src)), - (VCVTSS2SDrm (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)), - addr:$src)>; + // bit_convert let Predicates = [HasXMMInt] in { From greened at obbligato.org Mon Jul 18 13:13:04 2011 From: greened at obbligato.org (David A. Greene) Date: Mon, 18 Jul 2011 13:13:04 -0500 Subject: [llvm-commits] [PATCH] Make Inits FoldingSetNodes In-Reply-To: (Jakob Stoklund Olesen's message of "Mon, 18 Jul 2011 10:06:06 -0700") References: <22224557-527C-4091-A2A9-0D5A4EA3449E@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: > Note that I didn't change all of the RecTy pointers into const > pointers. I don't think it is necessary since the RecTy classes don't > have any public mutators. Ok. > You could do the same for the Inits - It would require much fewer source changes. Having the "const" there helped catch a few bugs so I'm inclined to keep it. I've separated that bit of the patch out anyway. -Dave From atrick at apple.com Mon Jul 18 13:21:35 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 18 Jul 2011 18:21:35 -0000 Subject: [llvm-commits] [llvm] r135409 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110718182135.EEA4E2A6C12C@llvm.org> Author: atrick Date: Mon Jul 18 13:21:35 2011 New Revision: 135409 URL: http://llvm.org/viewvc/llvm-project?rev=135409&view=rev Log: indvars: Added isHighCostExpansion. Avoid generating extra ops in the preheader for the sole purpose of LFTR, since LFTR itself is usually not a clear optimization. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135409&r1=135408&r2=135409&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jul 18 13:21:35 2011 @@ -1448,6 +1448,54 @@ // LinearFunctionTestReplace and its kin. Rewrite the loop exit condition. //===----------------------------------------------------------------------===// +// Check for expressions that ScalarEvolution generates to compute +// BackedgeTakenInfo. If these expressions have not been reduced, then expanding +// them may incur additional cost (albeit in the loop preheader). +static bool isHighCostExpansion(const SCEV *S, BranchInst *BI, + ScalarEvolution *SE) { + // If the backedge-taken count is a UDiv, it's very likely a UDiv that + // ScalarEvolution's HowFarToZero or HowManyLessThans produced to compute a + // precise expression, rather than a UDiv from the user's code. If we can't + // find a UDiv in the code with some simple searching, assume the former and + // forego rewriting the loop. + if (isa(S)) { + ICmpInst *OrigCond = dyn_cast(BI->getCondition()); + if (!OrigCond) return true; + const SCEV *R = SE->getSCEV(OrigCond->getOperand(1)); + R = SE->getMinusSCEV(R, SE->getConstant(R->getType(), 1)); + if (R != S) { + const SCEV *L = SE->getSCEV(OrigCond->getOperand(0)); + L = SE->getMinusSCEV(L, SE->getConstant(L->getType(), 1)); + if (L != S) + return true; + } + } + + if (!DisableIVRewrite) + return false; + + // Recurse past add expressions, which commonly occur in the + // BackedgeTakenCount. They may already exist in program code, and if not, + // they are not too expensive rematerialize. + if (const SCEVAddExpr *Add = dyn_cast(S)) { + for (SCEVAddExpr::op_iterator I = Add->op_begin(), E = Add->op_end(); + I != E; ++I) { + if (isHighCostExpansion(*I, BI, SE)) + return true; + } + return false; + } + + // HowManyLessThans uses a Max expression whenever the loop is not guarded by + // the exit condition. + if (isa(S) || isa(S)) + return true; + + // If we haven't recognized an expensive SCEV patter, assume its an expression + // produced by program code. + return false; +} + /// canExpandBackedgeTakenCount - Return true if this loop's backedge taken /// count expression can be safely and cheaply expanded into an instruction /// sequence that can be used by LinearFunctionTestReplace. @@ -1465,23 +1513,9 @@ if (!BI) return false; - // Special case: If the backedge-taken count is a UDiv, it's very likely a - // UDiv that ScalarEvolution produced in order to compute a precise - // expression, rather than a UDiv from the user's code. If we can't find a - // UDiv in the code with some simple searching, assume the former and forego - // rewriting the loop. - if (isa(BackedgeTakenCount)) { - ICmpInst *OrigCond = dyn_cast(BI->getCondition()); - if (!OrigCond) return false; - const SCEV *R = SE->getSCEV(OrigCond->getOperand(1)); - R = SE->getMinusSCEV(R, SE->getConstant(R->getType(), 1)); - if (R != BackedgeTakenCount) { - const SCEV *L = SE->getSCEV(OrigCond->getOperand(0)); - L = SE->getMinusSCEV(L, SE->getConstant(L->getType(), 1)); - if (L != BackedgeTakenCount) - return false; - } - } + if (isHighCostExpansion(BackedgeTakenCount, BI, SE)) + return false; + return true; } From mailing-list at martin-whitaker.me.uk Mon Jul 18 13:22:33 2011 From: mailing-list at martin-whitaker.me.uk (Martin Whitaker) Date: Mon, 18 Jul 2011 19:22:33 +0100 Subject: [llvm-commits] [PATCH] Enable use of SPARC g2-g4 global registers In-Reply-To: <53BB11CC-A939-49B9-8495-7B7A8AC2AF29@2pi.dk> References: <4E1B4E07.3090408@martin-whitaker.me.uk> <53BB11CC-A939-49B9-8495-7B7A8AC2AF29@2pi.dk> Message-ID: <4E2479E9.1080505@martin-whitaker.me.uk> Ping. Could someone familiar with SPARC comment? Revised patch (following Jakob's comments and subsequent discussion) attached again. Martin Jakob Stoklund Olesen wrote: > > On Jul 11, 2011, at 12:24 PM, Martin Whitaker wrote: > >> This patch adds a SPARC code generator feature that allows the code generator to optionally use the global registers that are reserved for application use by the SPARC ABI (g2,g3,g4). >> >> It also changes the preferred register allocation order to give preference to the global and input registers, to increase the chances of being able to eliminate the frame save/restore in leaf functions (when that optimisation is added). I'm doing this now because it also makes the regression test for this patch simpler (and less likely to break in the future). >> >> Please review. > > There register stuff looks good to me, but someone who is familiar with SPARC should comment. > > +define void @test(i32* %ptr) nounwind { > +entry: > +; CHECK_N: ld [%i0], %i3 > +; CHECK_N: ld [%i0], %i2 > +; CHECK_N: ld [%i0], %i1 > +; CHECK_Y: ld [%i0], %g4 > +; CHECK_Y: ld [%i0], %g3 > +; CHECK_Y: ld [%i0], %g2 > > Please don't write tests that depend on the exact details of register allocation. There is no reason these registers would be allocated in exactly that order. > > Check for the absence or presence of frame save/restore code instead. > > /jakob > -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 0001-Enable-use-of-SPARC-g2-g4-global-registers.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/1315b4aa/attachment.pl From echristo at apple.com Mon Jul 18 13:27:44 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 18 Jul 2011 11:27:44 -0700 Subject: [llvm-commits] [llvm] r135289 - in /llvm/trunk: include/llvm/Object/ObjectFile.h tools/llvm-objdump/llvm-objdump.cpp In-Reply-To: <20110715183925.11AD4312800A@llvm.org> References: <20110715183925.11AD4312800A@llvm.org> Message-ID: On Jul 15, 2011, at 11:39 AM, Benjamin Kramer wrote: > + if (error(si->getName(Name))) break; I know it isn't your fault but this idiom pains me. The patches themselves look great. Thanks! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/94205ede/attachment.html From eli.friedman at gmail.com Mon Jul 18 13:33:16 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 18 Jul 2011 11:33:16 -0700 Subject: [llvm-commits] [PATCH] Add APInt(numBits, ArrayRef bigVal) constructor (issue4749046) In-Reply-To: References: <20cf301d427cfb2c4a04a83d7a52@google.com> Message-ID: On Mon, Jul 18, 2011 at 9:57 AM, Jeffrey Yasskin wrote: > Here's the patch. > > On Sat, Jul 16, 2011 at 10:51 PM, ? wrote: >> Reviewers: eli.friedman_gmail.com, >> >> Message: >> Initial diff at >> http://codereview.appspot.com/download/issue4749046_1.diff >> >> Description: >> Add APInt(numBits, ArrayRef bigVal) constructor to prevent >> future ambiguity errors like the one corrected by r135261. ?Migrate all >> LLVM callers of the old constructor to the new one. >> >> >> Please review this at http://codereview.appspot.com/4749046/ >> >> Affected files: >> ? M include/llvm/ADT/APInt.h >> ? M lib/AsmParser/LLLexer.cpp >> ? M lib/Bitcode/Reader/BitcodeReader.cpp >> ? M lib/CodeGen/SelectionDAG/FastISel.cpp >> ? M lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp >> ? M lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> ? M lib/ExecutionEngine/ExecutionEngine.cpp >> ? M lib/Support/APFloat.cpp >> ? M lib/Support/APInt.cpp >> ? M lib/VMCore/ConstantFold.cpp >> ? M lib/VMCore/Core.cpp >> ? M unittests/ADT/APIntTest.cpp @@ -342,7 +353,8 @@ public: if (isSingleWord()) return isUIntN(N, VAL); - return APInt(N, getNumWords(), pVal).zext(getBitWidth()) == (*this); + return APInt(N, ArrayRef(pVal, getNumWords())).zext(getBitWidth()) + == (*this); } /// @brief Check if this APInt has an N-bits signed integer value. makeArrayRef just landed; use it. :) Same in a couple other places. Otherwise, looks fine. As a followup, could you eliminate both the "APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[])" and the "APInt(unsigned numBits, uint64_t val, bool isSigned = false)" constructors? (It should just require ArrayRef-izing and adding an "APInt::getSigned(unsigned numBits, uint64_t val)" helper.) -Eli From jyasskin at google.com Mon Jul 18 13:42:34 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 18 Jul 2011 11:42:34 -0700 Subject: [llvm-commits] [PATCH] Add APInt(numBits, ArrayRef bigVal) constructor (issue4749046) In-Reply-To: References: <20cf301d427cfb2c4a04a83d7a52@google.com> Message-ID: On Mon, Jul 18, 2011 at 11:33 AM, Eli Friedman wrote: > On Mon, Jul 18, 2011 at 9:57 AM, Jeffrey Yasskin wrote: >> Here's the patch. >> >> On Sat, Jul 16, 2011 at 10:51 PM, ? wrote: >>> Reviewers: eli.friedman_gmail.com, >>> >>> Message: >>> Initial diff at >>> http://codereview.appspot.com/download/issue4749046_1.diff >>> >>> Description: >>> Add APInt(numBits, ArrayRef bigVal) constructor to prevent >>> future ambiguity errors like the one corrected by r135261. ?Migrate all >>> LLVM callers of the old constructor to the new one. >>> >>> >>> Please review this at http://codereview.appspot.com/4749046/ >>> >>> Affected files: >>> ? M include/llvm/ADT/APInt.h >>> ? M lib/AsmParser/LLLexer.cpp >>> ? M lib/Bitcode/Reader/BitcodeReader.cpp >>> ? M lib/CodeGen/SelectionDAG/FastISel.cpp >>> ? M lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp >>> ? M lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>> ? M lib/ExecutionEngine/ExecutionEngine.cpp >>> ? M lib/Support/APFloat.cpp >>> ? M lib/Support/APInt.cpp >>> ? M lib/VMCore/ConstantFold.cpp >>> ? M lib/VMCore/Core.cpp >>> ? M unittests/ADT/APIntTest.cpp > > @@ -342,7 +353,8 @@ public: > > ? ? if (isSingleWord()) > ? ? ? return isUIntN(N, VAL); > - ? ?return APInt(N, getNumWords(), pVal).zext(getBitWidth()) == (*this); > + ? ?return APInt(N, ArrayRef(pVal, > getNumWords())).zext(getBitWidth()) > + ? ? ?== (*this); > ? } > > ? /// @brief Check if this APInt has an N-bits signed integer value. > > makeArrayRef just landed; use it. :) ?Same in a couple other places. Silly codebase, changing out from under me. ;-) Will do. > Otherwise, looks fine. > > As a followup, could you eliminate both the "APInt(unsigned numBits, > unsigned numWords, const uint64_t bigVal[])" and the "APInt(unsigned > numBits, uint64_t val, bool isSigned = false)" constructors? ?(It > should just require ArrayRef-izing and adding an > "APInt::getSigned(unsigned numBits, uint64_t val)" helper.) How do you want to handle dependent codebases? I was thinking to leave APInt(...bigVal[]) in for a version to let people switch, but I guess LLVM does tend to remove things more aggressively than that. I'm only willing to commit to fixing clang myself if you want me to both fix things and remove the deprecated constructors. From grosser at fim.uni-passau.de Mon Jul 18 13:42:33 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 18:42:33 -0000 Subject: [llvm-commits] [zorg] r135411 - /zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Message-ID: <20110718184233.C9AC82A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 13:42:33 2011 New Revision: 135411 URL: http://llvm.org/viewvc/llvm-project?rev=135411&view=rev Log: Remove concurrent build from Polly builders. Lets get it working first. We will improve this later Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=135411&r1=135410&r2=135411&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Mon Jul 18 13:42:33 2011 @@ -40,7 +40,7 @@ workdir=isl_srcdir, description=['isl-configure'])) f.addStep(ShellCommand(name="build-isl", - command=["make", WithProperties("-j%s" % jobs)], + command=["make"], haltOnFailure=True, description=["build isl"], workdir=isl_srcdir)) @@ -68,7 +68,7 @@ workdir=cloog_srcdir, description=['cloog-configure'])) f.addStep(ShellCommand(name="build-cloog", - command=["make", WithProperties("-j%s" % jobs)], + command=["make"], haltOnFailure=True, description=["build cloog"], workdir=cloog_srcdir)) @@ -118,7 +118,7 @@ workdir=llvm_objdir)) # Build Polly f.addStep(ShellCommand(name="build_polly", - command=["make", WithProperties("-j%s" % jobs)], + command=["make"], haltOnFailure=True, description=["build polly"], workdir=llvm_objdir)) From atrick at apple.com Mon Jul 18 13:44:20 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 18 Jul 2011 18:44:20 -0000 Subject: [llvm-commits] [llvm] r135412 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110718184420.436E12A6C12C@llvm.org> Author: atrick Date: Mon Jul 18 13:44:20 2011 New Revision: 135412 URL: http://llvm.org/viewvc/llvm-project?rev=135412&view=rev Log: indvars: Added verification that LFTR and other indvars goodness does not interfere with BackedgeTakenCount computation. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135412&r1=135411&r2=135412&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jul 18 13:44:20 2011 @@ -1900,6 +1900,25 @@ // Clean up dead instructions. Changed |= DeleteDeadPHIs(L->getHeader()); // Check a post-condition. - assert(L->isLCSSAForm(*DT) && "Indvars did not leave the loop in lcssa form!"); + assert(L->isLCSSAForm(*DT) && + "Indvars did not leave the loop in lcssa form!"); + + // Verify that LFTR, and any other change have not interfered with SCEV's + // ability to compute trip count. +#ifndef NDEBUG + if (DisableIVRewrite && !isa(BackedgeTakenCount)) { + SE->forgetLoop(L); + const SCEV *NewBECount = SE->getBackedgeTakenCount(L); + if (SE->getTypeSizeInBits(BackedgeTakenCount->getType()) < + SE->getTypeSizeInBits(NewBECount->getType())) + NewBECount = SE->getTruncateOrNoop(NewBECount, + BackedgeTakenCount->getType()); + else + BackedgeTakenCount = SE->getTruncateOrNoop(BackedgeTakenCount, + NewBECount->getType()); + assert(BackedgeTakenCount == NewBECount && "indvars must preserve SCEV"); + } +#endif + return Changed; } From stoklund at 2pi.dk Mon Jul 18 13:47:14 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 18:47:14 -0000 Subject: [llvm-commits] [llvm] r135413 - in /llvm/trunk: lib/CodeGen/SplitKit.cpp test/CodeGen/ARM/crash-greedy-v6.ll Message-ID: <20110718184714.235862A6C12C@llvm.org> Author: stoklund Date: Mon Jul 18 13:47:13 2011 New Revision: 135413 URL: http://llvm.org/viewvc/llvm-project?rev=135413&view=rev Log: Fix a crash when building 177.mesa for armv6. When splitting a live range immediately before an LDR_POST instruction that redefines the address register, make sure to use the correct value number in leaveIntvBefore. We need the value number entering the instruction. Added: llvm/trunk/test/CodeGen/ARM/crash-greedy-v6.ll Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=135413&r1=135412&r2=135413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Jul 18 13:47:13 2011 @@ -730,7 +730,7 @@ DEBUG(dbgs() << " leaveIntvBefore " << Idx); // The interval must be live into the instruction at Idx. - Idx = Idx.getBoundaryIndex(); + Idx = Idx.getBaseIndex(); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); if (!ParentVNI) { DEBUG(dbgs() << ": not live\n"); Added: llvm/trunk/test/CodeGen/ARM/crash-greedy-v6.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/crash-greedy-v6.ll?rev=135413&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/crash-greedy-v6.ll (added) +++ llvm/trunk/test/CodeGen/ARM/crash-greedy-v6.ll Mon Jul 18 13:47:13 2011 @@ -0,0 +1,32 @@ +; RUN: llc -disable-fp-elim -relocation-model=pic < %s +target triple = "armv6-apple-ios" + +; Reduced from 177.mesa. This test causes a live range split before an LDR_POST instruction. +; That requires leaveIntvBefore to be very accurate about the redefined value number. +define internal void @sample_nearest_3d(i8* nocapture %tObj, i32 %n, float* nocapture %s, float* nocapture %t, float* nocapture %u, float* nocapture %lambda, i8* nocapture %red, i8* nocapture %green, i8* nocapture %blue, i8* nocapture %alpha) nounwind ssp { +entry: + br i1 undef, label %for.end, label %for.body.lr.ph + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph + %i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ] + %arrayidx11 = getelementptr float* %t, i32 %i.031 + %arrayidx15 = getelementptr float* %u, i32 %i.031 + %arrayidx19 = getelementptr i8* %red, i32 %i.031 + %arrayidx22 = getelementptr i8* %green, i32 %i.031 + %arrayidx25 = getelementptr i8* %blue, i32 %i.031 + %arrayidx28 = getelementptr i8* %alpha, i32 %i.031 + %tmp12 = load float* %arrayidx11, align 4 + tail call fastcc void @sample_3d_nearest(i8* %tObj, i8* undef, float undef, float %tmp12, float undef, i8* %arrayidx19, i8* %arrayidx22, i8* %arrayidx25, i8* %arrayidx28) + %0 = add i32 %i.031, 1 + %exitcond = icmp eq i32 %0, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +declare fastcc void @sample_3d_nearest(i8* nocapture, i8* nocapture, float, float, float, i8* nocapture, i8* nocapture, i8* nocapture, i8* nocapture) nounwind ssp + From resistor at mac.com Mon Jul 18 13:50:52 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 18 Jul 2011 18:50:52 -0000 Subject: [llvm-commits] [llvm] r135414 - in /llvm/trunk: lib/Target/ARM/ARMConstantIslandPass.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h utils/TableGen/ARMDecoderEmitter.cpp Message-ID: <20110718185053.167082A6C12C@llvm.org> Author: resistor Date: Mon Jul 18 13:50:52 2011 New Revision: 135414 URL: http://llvm.org/viewvc/llvm-project?rev=135414&view=rev Log: Re-apply r135319 with a fix for the constant island pass. Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=135414&r1=135413&r2=135414&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Jul 18 13:50:52 2011 @@ -1430,6 +1430,8 @@ // Use BL to implement far jump. Br.MaxDisp = (1 << 21) * 2; MI->setDesc(TII->get(ARM::tBfar)); + MI->addOperand(MachineOperand::CreateImm((int64_t)ARMCC::AL)); + MI->addOperand(MachineOperand::CreateReg(0, false)); BBSizes[MBB->getNumber()] += 2; AdjustBBOffsetsAfter(MBB, 2); HasFarJump = true; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=135414&r1=135413&r2=135414&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Jul 18 13:50:52 2011 @@ -390,8 +390,8 @@ Uses = [SP] in { // Also used for Thumb2 def tBL : TIx2<0b11110, 0b11, 1, - (outs), (ins t_bltarget:$func, variable_ops), IIC_Br, - "bl\t$func", + (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br, + "bl${p}\t$func", [(ARMtcall tglobaladdr:$func)]>, Requires<[IsThumb, IsNotDarwin]> { bits<21> func; @@ -403,8 +403,8 @@ // ARMv5T and above, also used for Thumb2 def tBLXi : TIx2<0b11110, 0b11, 0, - (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br, - "blx\t$func", + (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br, + "blx${p}\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsThumb, HasV5T, IsNotDarwin]> { bits<21> func; @@ -416,8 +416,8 @@ } // Also used for Thumb2 - def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, - "blx\t$func", + def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, + "blx${p}\t$func", [(ARMtcall GPR:$func)]>, Requires<[IsThumb, HasV5T, IsNotDarwin]>, T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; @@ -440,43 +440,22 @@ Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], Uses = [R7, SP] in { // Also used for Thumb2 - def tBLr9 : TIx2<0b11110, 0b11, 1, - (outs), (ins pred:$p, t_bltarget:$func, variable_ops), - IIC_Br, "bl${p}\t$func", - [(ARMtcall tglobaladdr:$func)]>, - Requires<[IsThumb, IsDarwin]> { - bits<21> func; - let Inst{25-16} = func{20-11}; - let Inst{13} = 1; - let Inst{11} = 1; - let Inst{10-0} = func{10-0}; - } + def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops), + 4, IIC_Br, [(ARMtcall tglobaladdr:$func)], + (tBL pred:$p, t_bltarget:$func)>, + Requires<[IsThumb, IsDarwin]>; // ARMv5T and above, also used for Thumb2 - def tBLXi_r9 : TIx2<0b11110, 0b11, 0, - (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), - IIC_Br, "blx${p}\t$func", - [(ARMcall tglobaladdr:$func)]>, - Requires<[IsThumb, HasV5T, IsDarwin]> { - bits<21> func; - let Inst{25-16} = func{20-11}; - let Inst{13} = 1; - let Inst{11} = 1; - let Inst{10-1} = func{10-1}; - let Inst{0} = 0; // func{0} is assumed zero - } + def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops), + 4, IIC_Br, [(ARMcall tglobaladdr:$func)], + (tBLXi pred:$p, t_blxtarget:$func)>, + Requires<[IsThumb, HasV5T, IsDarwin]>; // Also used for Thumb2 - def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, - "blx${p}\t$func", - [(ARMtcall GPR:$func)]>, - Requires<[IsThumb, HasV5T, IsDarwin]>, - T1Special<{1,1,1,?}> { - // A6.2.3 & A8.6.24 - bits<4> func; - let Inst{6-3} = func; - let Inst{2-0} = 0b000; - } + def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops), + 2, IIC_Br, [(ARMtcall GPR:$func)], + (tBLXr pred:$p, GPR:$func)>, + Requires<[IsThumb, HasV5T, IsDarwin]>; // ARMv4T def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), @@ -498,8 +477,8 @@ // Just a pseudo for a tBL instruction. Needed to let regalloc know about // the clobber of LR. let Defs = [LR] in - def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target), - 4, IIC_Br, [], (tBL t_bltarget:$target)>; + def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), + 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>; def tBR_JTr : tPseudoInst<(outs), (ins tGPR:$target, i32imm:$jt, i32imm:$id), Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=135414&r1=135413&r2=135414&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Mon Jul 18 13:50:52 2011 @@ -479,7 +479,7 @@ // tBX: Rm // tBX_RET: 0 operand // tBX_RET_vararg: Rm -// tBLXr_r9: Rm +// tBLXr: Rm // tBRIND: Rm static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -489,8 +489,8 @@ return true; // BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm. - if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) { - if (Opcode == ARM::tBLXr_r9) { + if (Opcode==ARM::tBLXr || Opcode==ARM::tBX || Opcode==ARM::tBRIND) { + if (Opcode == ARM::tBLXr) { // Handling the two predicate operands before the reg operand. if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps)) return false; @@ -1729,7 +1729,7 @@ // Branches: t2TPsoft -> no operand // // A8.6.23 BL, BLX (immediate) -// Branches (defined in ARMInstrThumb.td): tBLr9, tBLXi_r9 -> imm operand +// Branches (defined in ARMInstrThumb.td): tBL, tBLXi -> imm operand // // A8.6.26 // t2BXJ -> Rn @@ -1844,7 +1844,7 @@ } // Some instructions have predicate operands first before the immediate. - if (Opcode == ARM::tBLXi_r9 || Opcode == ARM::tBLr9) { + if (Opcode == ARM::tBLXi || Opcode == ARM::tBL) { // Handling the two predicate operands before the imm operand. if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) NumOpsAdded += 2; @@ -1867,10 +1867,10 @@ case ARM::t2Bcc: Offset = decodeImm32_B_EncodingT3(insn); break; - case ARM::tBLr9: + case ARM::tBL: Offset = decodeImm32_BL(insn); break; - case ARM::tBLXi_r9: + case ARM::tBLXi: Offset = decodeImm32_BLX(insn); break; } Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=135414&r1=135413&r2=135414&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Mon Jul 18 13:50:52 2011 @@ -1619,10 +1619,6 @@ if (Name == "tSTMIA") return false; - // On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts. - if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr") - return false; - // A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg. if (Name == "tBX_RET" || Name == "tBX_RET_vararg") return false; @@ -1654,14 +1650,12 @@ // Resolve conflicts: // - // tBfar conflicts with tBLr9 // t2LDMIA_RET conflict with t2LDM (ditto) // tMOVCCi conflicts with tMOVi8 // tMOVCCr conflicts with tMOVgpr2gpr // tLDRcp conflicts with tLDRspi // t2MOVCCi16 conflicts with tMOVi16 - if (Name == "tBfar" || - Name == "t2LDMIA_RET" || + if (Name == "t2LDMIA_RET" || Name == "tMOVCCi" || Name == "tMOVCCr" || Name == "tLDRcp" || Name == "t2MOVCCi16") From ahatanak at gmail.com Mon Jul 18 13:52:12 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 18 Jul 2011 18:52:12 -0000 Subject: [llvm-commits] [llvm] r135415 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsMachineFunction.h test/CodeGen/Mips/atomic.ll Message-ID: <20110718185212.EA3A72A6C12C@llvm.org> Author: ahatanak Date: Mon Jul 18 13:52:12 2011 New Revision: 135415 URL: http://llvm.org/viewvc/llvm-project?rev=135415&view=rev Log: Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsMachineFunction.h llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135415&r1=135414&r2=135415&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 13:52:12 2011 @@ -733,11 +733,10 @@ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); - unsigned Dest = MI->getOperand(0).getReg(); + unsigned Oldval = MI->getOperand(0).getReg(); unsigned Ptr = MI->getOperand(1).getReg(); unsigned Incr = MI->getOperand(2).getReg(); - unsigned Oldval = RegInfo.createVirtualRegister(RC); unsigned Tmp1 = RegInfo.createVirtualRegister(RC); unsigned Tmp2 = RegInfo.createVirtualRegister(RC); unsigned Tmp3 = RegInfo.createVirtualRegister(RC); @@ -759,38 +758,16 @@ // thisMBB: // ... - // sw incr, fi(sp) // store incr to stack (when BinOpcode == 0) // fallthrough --> loopMBB - - // Note: for atomic.swap (when BinOpcode == 0), storing incr to stack before - // the loop and then loading it from stack in block loopMBB is necessary to - // prevent MachineLICM pass to hoist "or" instruction out of the block - // loopMBB. - - int fi = 0; - if (BinOpcode == 0 && !Nand) { - // Get or create a temporary stack location. - MipsFunctionInfo *MipsFI = MF->getInfo(); - fi = MipsFI->getAtomicFrameIndex(); - if (fi == -1) { - fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); - MipsFI->setAtomicFrameIndex(fi); - } - - BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Incr).addFrameIndex(fi).addImm(0); - } BB->addSuccessor(loopMBB); // loopMBB: // ll oldval, 0(ptr) - // or dest, $0, oldval // tmp1, oldval, incr // sc tmp1, 0(ptr) // beq tmp1, $0, loopMBB BB = loopMBB; BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0); - BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval); if (Nand) { // and tmp2, oldval, incr // nor tmp1, $0, tmp2 @@ -800,10 +777,7 @@ // tmp1, oldval, incr BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr); } else { - // lw tmp2, fi(sp) // load incr from stack - // or tmp1, $zero, tmp2 - BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + Tmp1 = Incr; } BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) @@ -880,12 +854,6 @@ // nor mask2,$0,mask // andi tmp4,incr,255 // sll incr2,tmp4,shift - // sw incr2, fi(sp) // store incr2 to stack (when BinOpcode == 0) - - // Note: for atomic.swap (when BinOpcode == 0), storing incr2 to stack before - // the loop and then loading it from stack in block loopMBB is necessary to - // prevent MachineLICM pass to hoist "or" instruction out of the block - // loopMBB. int64_t MaskImm = (Size == 1) ? 255 : 65535; BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); @@ -904,21 +872,9 @@ BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift); } - int fi = 0; - if (BinOpcode == 0 && !Nand) { - // Get or create a temporary stack location. - MipsFunctionInfo *MipsFI = MF->getInfo(); - fi = MipsFI->getAtomicFrameIndex(); - if (fi == -1) { - fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); - MipsFI->setAtomicFrameIndex(fi); - } - - BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Incr2).addFrameIndex(fi).addImm(0); - } BB->addSuccessor(loopMBB); + // atomic.load.binop // loopMBB: // ll oldval,0(addr) // binop tmp7,oldval,incr2 @@ -927,6 +883,15 @@ // or tmp9,tmp8,newval // sc tmp9,0(addr) // beq tmp9,$0,loopMBB + + // atomic.swap + // loopMBB: + // ll oldval,0(addr) + // and tmp8,oldval,mask2 + // or tmp9,tmp8,incr2 + // sc tmp9,0(addr) + // beq tmp9,$0,loopMBB + BB = loopMBB; BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0); if (Nand) { @@ -940,15 +905,14 @@ } else if (BinOpcode) { // tmp7, oldval, incr2 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); - } else { - // lw tmp6, fi(sp) // load incr2 from stack - // or tmp7, $zero, tmp6 - BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addFrameIndex(fi).addImm(0); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); } - BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); + if (BinOpcode != 0 || Nand) + BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); + if (BinOpcode != 0 || Nand) + BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); + else + BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Incr2); BuildMI(BB, dl, TII->get(Mips::SC), Tmp13) .addReg(Tmp9).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) @@ -996,7 +960,6 @@ unsigned Newval = MI->getOperand(3).getReg(); unsigned Tmp1 = RegInfo.createVirtualRegister(RC); - unsigned Tmp2 = RegInfo.createVirtualRegister(RC); unsigned Tmp3 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block @@ -1016,25 +979,9 @@ BB->end()); exitMBB->transferSuccessorsAndUpdatePHIs(BB); - // Get or create a temporary stack location. - MipsFunctionInfo *MipsFI = MF->getInfo(); - int fi = MipsFI->getAtomicFrameIndex(); - if (fi == -1) { - fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); - MipsFI->setAtomicFrameIndex(fi); - } - // thisMBB: // ... - // sw newval, fi(sp) // store newval to stack // fallthrough --> loop1MBB - - // Note: storing newval to stack before the loop and then loading it from - // stack in block loop2MBB is necessary to prevent MachineLICM pass to - // hoist "or" instruction out of the block loop2MBB. - - BuildMI(BB, dl, TII->get(Mips::SW)) - .addReg(Newval).addFrameIndex(fi).addImm(0); BB->addSuccessor(loop1MBB); // loop1MBB: @@ -1048,13 +995,11 @@ BB->addSuccessor(loop2MBB); // loop2MBB: - // lw tmp2, fi(sp) // load newval from stack - // or tmp1, $0, tmp2 + // or tmp1, $0, newval // sc tmp1, 0(ptr) // beq tmp1, $0, loop1MBB BB = loop2MBB; - BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Newval); BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=135415&r1=135414&r2=135415&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Jul 18 13:52:12 2011 @@ -590,10 +590,10 @@ def SW : StoreM<0x2b, "sw", store>; /// Load-linked, Store-conditional -let hasDelaySlot = 1 in +let mayLoad = 1, hasDelaySlot = 1 in def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr), "ll\t$dst, $addr", [], IILoad>; -let Constraints = "$src = $dst" in +let mayStore = 1, Constraints = "$src = $dst" in def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr), "sc\t$src, $addr", [], IIStore>; Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=135415&r1=135414&r2=135415&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon Jul 18 13:52:12 2011 @@ -51,16 +51,12 @@ mutable int DynAllocFI; // Frame index of dynamically allocated stack area. unsigned MaxCallFrameSize; - /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap - /// intrinsics, it is necessary to use a temporary stack location. - /// This field holds the frame index of this location. - int AtomicFrameIndex; public: MipsFunctionInfo(MachineFunction& MF) : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0), - MaxCallFrameSize(0), AtomicFrameIndex(-1) + MaxCallFrameSize(0) {} bool isInArgFI(int FI) const { @@ -104,9 +100,6 @@ unsigned getMaxCallFrameSize() const { return MaxCallFrameSize; } void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; } - - int getAtomicFrameIndex() const { return AtomicFrameIndex; } - void setAtomicFrameIndex(int Index) { AtomicFrameIndex = Index; } }; } // end of namespace llvm Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135415&r1=135414&r2=135415&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Mon Jul 18 13:52:12 2011 @@ -24,7 +24,6 @@ ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 ; CHECK: sc $[[R2]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] @@ -39,43 +38,42 @@ ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] -; CHECK: and $[[R1]], $[[R1]], $4 -; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4 +; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; CHECK: sc $[[R2]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] } -define i32 @AtomicSwap32(i32 %oldval) nounwind { +define i32 @AtomicSwap32(i32 %newval) nounwind { entry: - %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval) + %newval.addr = alloca i32, align 4 + store i32 %newval, i32* %newval.addr, align 4 + %tmp = load i32* %newval.addr, align 4 + %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %tmp) ret i32 %0 ; CHECK: AtomicSwap32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) -; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: -; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] -; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]] -; CHECK: sc $[[R3]], 0($[[R0]]) -; CHECK: beq $[[R3]], $zero, $[[BB0]] +; CHECK: ll ${{[0-9]+}}, 0($[[R0]]) +; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] } define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind { entry: - %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval) + %newval.addr = alloca i32, align 4 + store i32 %newval, i32* %newval.addr, align 4 + %tmp = load i32* %newval.addr, align 4 + %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %tmp) ret i32 %0 ; CHECK: AtomicCmpSwap32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) -; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] -; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: or $[[R2:[0-9]+]], $zero, $5 ; CHECK: sc $[[R2]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] ; CHECK: $[[BB1]]: @@ -183,9 +181,9 @@ ; CHECK: sra $2, $[[R17]], 24 } -define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind { +define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { entry: - %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval) + %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %newval) ret i8 %0 ; CHECK: AtomicSwap8: @@ -199,15 +197,11 @@ ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] ; CHECK: andi $[[R8:[0-9]+]], $4, 255 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] -; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) -; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]] -; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] -; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]] ; CHECK: sc $[[R14]], 0($[[R2]]) ; CHECK: beq $[[R14]], $zero, $[[BB0]] From clattner at apple.com Mon Jul 18 14:07:36 2011 From: clattner at apple.com (Chris Lattner) Date: Mon, 18 Jul 2011 12:07:36 -0700 Subject: [llvm-commits] [PATCH] Enable use of SPARC g2-g4 global registers In-Reply-To: <4E2479E9.1080505@martin-whitaker.me.uk> References: <4E1B4E07.3090408@martin-whitaker.me.uk> <53BB11CC-A939-49B9-8495-7B7A8AC2AF29@2pi.dk> <4E2479E9.1080505@martin-whitaker.me.uk> Message-ID: <7B226FD3-6578-4364-99A4-92E0F0A8DB26@apple.com> On Jul 18, 2011, at 11:22 AM, Martin Whitaker wrote: > Ping. > > Could someone familiar with SPARC comment? > > Revised patch (following Jakob's comments and subsequent discussion) attached again. I guess I'm the closest thing to a sparc maintainer that we have, but I haven't used a sparc for ~8 years now. The patch is fine with me, would you like to be the new sparc maintainer? :) -Chris > > Martin > > Jakob Stoklund Olesen wrote: >> >> On Jul 11, 2011, at 12:24 PM, Martin Whitaker wrote: >> >>> This patch adds a SPARC code generator feature that allows the code generator to optionally use the global registers that are reserved for application use by the SPARC ABI (g2,g3,g4). >>> >>> It also changes the preferred register allocation order to give preference to the global and input registers, to increase the chances of being able to eliminate the frame save/restore in leaf functions (when that optimisation is added). I'm doing this now because it also makes the regression test for this patch simpler (and less likely to break in the future). >>> >>> Please review. >> >> There register stuff looks good to me, but someone who is familiar with SPARC should comment. >> >> +define void @test(i32* %ptr) nounwind { >> +entry: >> +; CHECK_N: ld [%i0], %i3 >> +; CHECK_N: ld [%i0], %i2 >> +; CHECK_N: ld [%i0], %i1 >> +; CHECK_Y: ld [%i0], %g4 >> +; CHECK_Y: ld [%i0], %g3 >> +; CHECK_Y: ld [%i0], %g2 >> >> Please don't write tests that depend on the exact details of register allocation. There is no reason these registers would be allocated in exactly that order. >> >> Check for the absence or presence of frame save/restore code instead. >> >> /jakob >> > > <0001-Enable-use-of-SPARC-g2-g4-global-registers.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ahatanak at gmail.com Mon Jul 18 14:58:59 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 18 Jul 2011 19:58:59 -0000 Subject: [llvm-commits] [llvm] r135418 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll Message-ID: <20110718195859.C2F702A6C12C@llvm.org> Author: ahatanak Date: Mon Jul 18 14:58:59 2011 New Revision: 135418 URL: http://llvm.org/viewvc/llvm-project?rev=135418&view=rev Log: Do not treat atomic.load.sub differently than other atomic binary intrinsics. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135418&r1=135417&r2=135418&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 14:58:59 2011 @@ -819,7 +819,6 @@ unsigned Tmp2 = RegInfo.createVirtualRegister(RC); unsigned Tmp3 = RegInfo.createVirtualRegister(RC); unsigned Tmp4 = RegInfo.createVirtualRegister(RC); - unsigned Tmp5 = RegInfo.createVirtualRegister(RC); unsigned Tmp6 = RegInfo.createVirtualRegister(RC); unsigned Tmp7 = RegInfo.createVirtualRegister(RC); unsigned Tmp8 = RegInfo.createVirtualRegister(RC); @@ -863,14 +862,8 @@ BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - if (BinOpcode != Mips::SUBu) { - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); - } else { - BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift); - } + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); BB->addSuccessor(loopMBB); @@ -899,9 +892,6 @@ // nor tmp7, $0, tmp6 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2); BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); - } else if (BinOpcode == Mips::SUBu) { - // addu tmp7, oldval, incr2 - BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2); } else if (BinOpcode) { // tmp7, oldval, incr2 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135418&r1=135417&r2=135418&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Mon Jul 18 14:58:59 2011 @@ -129,13 +129,12 @@ ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: subu $[[R18:[0-9]+]], $zero, $4 -; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255 +; CHECK: andi $[[R8:[0-9]+]], $4, 255 ; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) -; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] From stoklund at 2pi.dk Mon Jul 18 15:22:23 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 13:22:23 -0700 Subject: [llvm-commits] [llvm] r135418 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll In-Reply-To: <20110718195859.C2F702A6C12C@llvm.org> References: <20110718195859.C2F702A6C12C@llvm.org> Message-ID: On Jul 18, 2011, at 12:58 PM, Akira Hatanaka wrote: > @@ -819,7 +819,6 @@ > unsigned Tmp2 = RegInfo.createVirtualRegister(RC); > unsigned Tmp3 = RegInfo.createVirtualRegister(RC); > unsigned Tmp4 = RegInfo.createVirtualRegister(RC); > - unsigned Tmp5 = RegInfo.createVirtualRegister(RC); > unsigned Tmp6 = RegInfo.createVirtualRegister(RC); > unsigned Tmp7 = RegInfo.createVirtualRegister(RC); > unsigned Tmp8 = RegInfo.createVirtualRegister(RC); Interesting naming scheme. Please fix that. (I know you didn't do it.) http://llvm.org/docs/CodingStandards.html#ll_naming Thanks, /jakob From mailing-list at martin-whitaker.me.uk Mon Jul 18 15:28:16 2011 From: mailing-list at martin-whitaker.me.uk (Martin Whitaker) Date: Mon, 18 Jul 2011 21:28:16 +0100 Subject: [llvm-commits] [PATCH] Enable use of SPARC g2-g4 global registers In-Reply-To: <7B226FD3-6578-4364-99A4-92E0F0A8DB26@apple.com> References: <4E1B4E07.3090408@martin-whitaker.me.uk> <53BB11CC-A939-49B9-8495-7B7A8AC2AF29@2pi.dk> <4E2479E9.1080505@martin-whitaker.me.uk> <7B226FD3-6578-4364-99A4-92E0F0A8DB26@apple.com> Message-ID: <4E249760.2030900@martin-whitaker.me.uk> Chris Lattner wrote: > > On Jul 18, 2011, at 11:22 AM, Martin Whitaker wrote: > >> Ping. >> >> Could someone familiar with SPARC comment? >> >> Revised patch (following Jakob's comments and subsequent discussion) attached again. > > I guess I'm the closest thing to a sparc maintainer that we have, but I haven't used a sparc for ~8 years now. The patch is fine with me, would you like to be the new sparc maintainer? :) > > -Chris Well, at the moment I'm just evaluating clang/llvm as a potential replacement for GCC, so would hesitate to make such a commitment unless/until I start using it in earnest (and until I have a bit more familiarity with the LLVM codebase!). I'm filling in a few of the missing features in the SPARC code generator to allow a fairer comparison with GCC, which is why I'm contributing patches now. I see on the llvm-devel list that someone is looking at adding JIT support to the SPARC code generator, so there may be a better candidate for SPARC maintainer coming along... Martin From ahatanak at gmail.com Mon Jul 18 15:31:34 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 18 Jul 2011 13:31:34 -0700 Subject: [llvm-commits] [llvm] r135418 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll In-Reply-To: References: <20110718195859.C2F702A6C12C@llvm.org> Message-ID: Do you mean I should use vector or array instead? Or should I change the name "Tmp"? I understand "Tmp" is not very descriptive, but these registers are used as temporaries to store intermediate results. Thank you. On Mon, Jul 18, 2011 at 1:22 PM, Jakob Stoklund Olesen wrote: > > On Jul 18, 2011, at 12:58 PM, Akira Hatanaka wrote: > > > @@ -819,7 +819,6 @@ > > unsigned Tmp2 = RegInfo.createVirtualRegister(RC); > > unsigned Tmp3 = RegInfo.createVirtualRegister(RC); > > unsigned Tmp4 = RegInfo.createVirtualRegister(RC); > > - unsigned Tmp5 = RegInfo.createVirtualRegister(RC); > > unsigned Tmp6 = RegInfo.createVirtualRegister(RC); > > unsigned Tmp7 = RegInfo.createVirtualRegister(RC); > > unsigned Tmp8 = RegInfo.createVirtualRegister(RC); > > Interesting naming scheme. Please fix that. (I know you didn't do it.) > > http://llvm.org/docs/CodingStandards.html#ll_naming > > Thanks, > /jakob > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/25cbccac/attachment.html From atrick at apple.com Mon Jul 18 15:32:32 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 18 Jul 2011 20:32:32 -0000 Subject: [llvm-commits] [llvm] r135420 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/ada-loops.ll test/Transforms/IndVarSimplify/lftr-reuse.ll Message-ID: <20110718203232.13EA62A6C12C@llvm.org> Author: atrick Date: Mon Jul 18 15:32:31 2011 New Revision: 135420 URL: http://llvm.org/viewvc/llvm-project?rev=135420&view=rev Log: indvars: LinearFunctionTestReplace for non-canonical IVs. For -disable-iv-rewrite, perform LFTR without generating a new "canonical" induction variable. Instead find the "best" existing induction variable for use in the loop exit test and compute the final value of that IV for use in the new loop exit test. In short, convert to a simple eq/ne exit test as long as it's cheap to do so. Added: llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135420&r1=135419&r2=135420&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jul 18 15:32:31 2011 @@ -79,6 +79,12 @@ "disable-iv-rewrite", cl::Hidden, cl::desc("Disable canonical induction variable rewriting")); +// Temporary flag for use with -disable-iv-rewrite to force a canonical IV for +// LFTR purposes. +static cl::opt ForceLFTR( + "force-lftr", cl::Hidden, + cl::desc("Enable forced linear function test replacement")); + namespace { class IndVarSimplify : public LoopPass { IVUsers *IU; @@ -140,9 +146,8 @@ void RewriteIVExpressions(Loop *L, SCEVExpander &Rewriter); - ICmpInst *LinearFunctionTestReplace(Loop *L, const SCEV *BackedgeTakenCount, - PHINode *IndVar, - SCEVExpander &Rewriter); + Value *LinearFunctionTestReplace(Loop *L, const SCEV *BackedgeTakenCount, + PHINode *IndVar, SCEVExpander &Rewriter); void SinkUnusedInvariants(Loop *L); }; @@ -1014,7 +1019,7 @@ NarrowUse->replaceUsesOfWith(NarrowDef, Trunc); return 0; } - // We assume that block terminators are not SCEVable. We wouldn't want to + // Assume block terminators cannot evaluate to a recurrence. We can't to // insert a Trunc after a terminator if there happens to be a critical edge. assert(NarrowUse != NarrowUse->getParent()->getTerminator() && "SCEV is not expected to evaluate a block terminator"); @@ -1302,10 +1307,6 @@ // Get the symbolic expression for this instruction. const SCEV *S = SE->getSCEV(I); - // We assume that terminators are not SCEVable. - assert((!S || I != I->getParent()->getTerminator()) && - "can't fold terminators"); - // Only consider affine recurrences. const SCEVAddRecExpr *AR = dyn_cast(S); if (AR && AR->getLoop() == L) @@ -1471,7 +1472,7 @@ } } - if (!DisableIVRewrite) + if (!DisableIVRewrite || ForceLFTR) return false; // Recurse past add expressions, which commonly occur in the @@ -1522,7 +1523,7 @@ /// getBackedgeIVType - Get the widest type used by the loop test after peeking /// through Truncs. /// -/// TODO: Unnecessary if LFTR does not force a canonical IV. +/// TODO: Unnecessary when ForceLFTR is removed. static Type *getBackedgeIVType(Loop *L) { if (!L->getExitingBlock()) return 0; @@ -1549,12 +1550,198 @@ return Ty; } +/// isLoopInvariant - Perform a quick domtree based check for loop invariance +/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems +/// gratuitous for this purpose. +static bool isLoopInvariant(Value *V, Loop *L, DominatorTree *DT) { + Instruction *Inst = dyn_cast(V); + if (!Inst) + return true; + + return DT->properlyDominates(Inst->getParent(), L->getHeader()); +} + +/// getLoopPhiForCounter - Return the loop header phi IFF IncV adds a loop +/// invariant value to the phi. +static PHINode *getLoopPhiForCounter(Value *IncV, Loop *L, DominatorTree *DT) { + Instruction *IncI = dyn_cast(IncV); + if (!IncI) + return 0; + + switch (IncI->getOpcode()) { + case Instruction::Add: + case Instruction::Sub: + break; + case Instruction::GetElementPtr: + // An IV counter must preserve its type. + if (IncI->getNumOperands() == 2) + break; + default: + return 0; + } + + PHINode *Phi = dyn_cast(IncI->getOperand(0)); + if (Phi && Phi->getParent() == L->getHeader()) { + if (isLoopInvariant(IncI->getOperand(1), L, DT)) + return Phi; + return 0; + } + if (IncI->getOpcode() == Instruction::GetElementPtr) + return 0; + + // Allow add/sub to be commuted. + Phi = dyn_cast(IncI->getOperand(1)); + if (Phi && Phi->getParent() == L->getHeader()) { + if (isLoopInvariant(IncI->getOperand(0), L, DT)) + return Phi; + } + return 0; +} + +/// needsLFTR - LinearFunctionTestReplace policy. Return true unless we can show +/// that the current exit test is already sufficiently canonical. +static bool needsLFTR(Loop *L, DominatorTree *DT) { + assert(L->getExitingBlock() && "expected loop exit"); + + BasicBlock *LatchBlock = L->getLoopLatch(); + // Don't bother with LFTR if the loop is not properly simplified. + if (!LatchBlock) + return false; + + BranchInst *BI = dyn_cast(L->getExitingBlock()->getTerminator()); + assert(BI && "expected exit branch"); + + // Do LFTR to simplify the exit condition to an ICMP. + ICmpInst *Cond = dyn_cast(BI->getCondition()); + if (!Cond) + return true; + + // Do LFTR to simplify the exit ICMP to EQ/NE + ICmpInst::Predicate Pred = Cond->getPredicate(); + if (Pred != ICmpInst::ICMP_NE && Pred != ICmpInst::ICMP_EQ) + return true; + + // Look for a loop invariant RHS + Value *LHS = Cond->getOperand(0); + Value *RHS = Cond->getOperand(1); + if (!isLoopInvariant(RHS, L, DT)) { + if (!isLoopInvariant(LHS, L, DT)) + return true; + std::swap(LHS, RHS); + } + // Look for a simple IV counter LHS + PHINode *Phi = dyn_cast(LHS); + if (!Phi) + Phi = getLoopPhiForCounter(LHS, L, DT); + + if (!Phi) + return true; + + // Do LFTR if the exit condition's IV is *not* a simple counter. + Value *IncV = Phi->getIncomingValueForBlock(L->getLoopLatch()); + return Phi != getLoopPhiForCounter(IncV, L, DT); +} + +/// AlmostDeadIV - Return true if this IV has any uses other than the (soon to +/// be rewritten) loop exit test. +static bool AlmostDeadIV(PHINode *Phi, BasicBlock *LatchBlock, Value *Cond) { + int LatchIdx = Phi->getBasicBlockIndex(LatchBlock); + Value *IncV = Phi->getIncomingValue(LatchIdx); + + for (Value::use_iterator UI = Phi->use_begin(), UE = Phi->use_end(); + UI != UE; ++UI) { + if (*UI != Cond && *UI != IncV) return false; + } + + for (Value::use_iterator UI = IncV->use_begin(), UE = IncV->use_end(); + UI != UE; ++UI) { + if (*UI != Cond && *UI != Phi) return false; + } + return true; +} + +/// FindLoopCounter - Find an affine IV in canonical form. +/// +/// FIXME: Accept -1 stride and set IVLimit = IVInit - BECount +/// +/// FIXME: Accept non-unit stride as long as SCEV can reduce BECount * Stride. +/// This is difficult in general for SCEV because of potential overflow. But we +/// could at least handle constant BECounts. +static PHINode * +FindLoopCounter(Loop *L, const SCEV *BECount, + ScalarEvolution *SE, DominatorTree *DT, const TargetData *TD) { + // I'm not sure how BECount could be a pointer type, but we definitely don't + // want to LFTR that. + if (BECount->getType()->isPointerTy()) + return 0; + + uint64_t BCWidth = SE->getTypeSizeInBits(BECount->getType()); + + Value *Cond = + cast(L->getExitingBlock()->getTerminator())->getCondition(); + + // Loop over all of the PHI nodes, looking for a simple counter. + PHINode *BestPhi = 0; + const SCEV *BestInit = 0; + BasicBlock *LatchBlock = L->getLoopLatch(); + assert(LatchBlock && "needsLFTR should guarantee a loop latch"); + + for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) { + PHINode *Phi = cast(I); + if (!SE->isSCEVable(Phi->getType())) + continue; + + const SCEVAddRecExpr *AR = dyn_cast(SE->getSCEV(Phi)); + if (!AR || AR->getLoop() != L || !AR->isAffine()) + continue; + + // AR may be a pointer type, while BECount is an integer type. + // AR may be wider than BECount. With eq/ne tests overflow is immaterial. + // AR may not be a narrower type, or we may never exit. + uint64_t PhiWidth = SE->getTypeSizeInBits(AR->getType()); + if (PhiWidth < BCWidth || (TD && !TD->isLegalInteger(PhiWidth))) + continue; + + const SCEV *Step = dyn_cast(AR->getStepRecurrence(*SE)); + if (!Step || !Step->isOne()) + continue; + + int LatchIdx = Phi->getBasicBlockIndex(LatchBlock); + Value *IncV = Phi->getIncomingValue(LatchIdx); + if (getLoopPhiForCounter(IncV, L, DT) != Phi) + continue; + + const SCEV *Init = AR->getStart(); + + if (BestPhi && !AlmostDeadIV(BestPhi, LatchBlock, Cond)) { + // Don't force a live loop counter if another IV can be used. + if (AlmostDeadIV(Phi, LatchBlock, Cond)) + continue; + + // Prefer to count-from-zero. This is a more "canonical" counter form. It + // also prefers integer to pointer IVs. + if (BestInit->isZero() != Init->isZero()) { + if (BestInit->isZero()) + continue; + } + // If two IVs both count from zero or both count from nonzero then the + // narrower is likely a dead phi that has been widened. Use the wider phi + // to allow the other to be eliminated. + if (PhiWidth <= SE->getTypeSizeInBits(BestPhi->getType())) + continue; + } + BestPhi = Phi; + BestInit = Init; + } + return BestPhi; +} + /// LinearFunctionTestReplace - This method rewrites the exit condition of the /// loop to be a canonical != comparison against the incremented loop induction /// variable. This pass is able to rewrite the exit tests of any loop where the /// SCEV analysis can determine a loop-invariant trip count of the loop, which /// is actually a much broader range than just linear tests. -ICmpInst *IndVarSimplify:: +Value *IndVarSimplify:: LinearFunctionTestReplace(Loop *L, const SCEV *BackedgeTakenCount, PHINode *IndVar, @@ -1562,62 +1749,118 @@ assert(canExpandBackedgeTakenCount(L, SE) && "precondition"); BranchInst *BI = cast(L->getExitingBlock()->getTerminator()); + // In DisableIVRewrite mode, IndVar is not necessarily a canonical IV. In this + // mode, LFTR can ignore IV overflow and truncate to the width of + // BECount. This avoids materializing the add(zext(add)) expression. + Type *CntTy = DisableIVRewrite ? + BackedgeTakenCount->getType() : IndVar->getType(); + + const SCEV *IVLimit = BackedgeTakenCount; + // If the exiting block is not the same as the backedge block, we must compare // against the preincremented value, otherwise we prefer to compare against // the post-incremented value. Value *CmpIndVar; - const SCEV *RHS = BackedgeTakenCount; if (L->getExitingBlock() == L->getLoopLatch()) { // Add one to the "backedge-taken" count to get the trip count. // If this addition may overflow, we have to be more pessimistic and // cast the induction variable before doing the add. - const SCEV *Zero = SE->getConstant(BackedgeTakenCount->getType(), 0); const SCEV *N = - SE->getAddExpr(BackedgeTakenCount, - SE->getConstant(BackedgeTakenCount->getType(), 1)); - if ((isa(N) && !N->isZero()) || - SE->isLoopEntryGuardedByCond(L, ICmpInst::ICMP_NE, N, Zero)) { - // No overflow. Cast the sum. - RHS = SE->getTruncateOrZeroExtend(N, IndVar->getType()); - } else { - // Potential overflow. Cast before doing the add. - RHS = SE->getTruncateOrZeroExtend(BackedgeTakenCount, - IndVar->getType()); - RHS = SE->getAddExpr(RHS, - SE->getConstant(IndVar->getType(), 1)); + SE->getAddExpr(IVLimit, SE->getConstant(IVLimit->getType(), 1)); + if (CntTy == IVLimit->getType()) + IVLimit = N; + else { + const SCEV *Zero = SE->getConstant(IVLimit->getType(), 0); + if ((isa(N) && !N->isZero()) || + SE->isLoopEntryGuardedByCond(L, ICmpInst::ICMP_NE, N, Zero)) { + // No overflow. Cast the sum. + IVLimit = SE->getTruncateOrZeroExtend(N, CntTy); + } else { + // Potential overflow. Cast before doing the add. + IVLimit = SE->getTruncateOrZeroExtend(IVLimit, CntTy); + IVLimit = SE->getAddExpr(IVLimit, SE->getConstant(CntTy, 1)); + } } - // The BackedgeTaken expression contains the number of times that the // backedge branches to the loop header. This is one less than the // number of times the loop executes, so use the incremented indvar. CmpIndVar = IndVar->getIncomingValueForBlock(L->getExitingBlock()); } else { // We have to use the preincremented value... - RHS = SE->getTruncateOrZeroExtend(BackedgeTakenCount, - IndVar->getType()); + IVLimit = SE->getTruncateOrZeroExtend(IVLimit, CntTy); CmpIndVar = IndVar; } + // For unit stride, IVLimit = Start + BECount with 2's complement overflow. + // So for, non-zero start compute the IVLimit here. + bool isPtrIV = false; + Type *CmpTy = CntTy; + const SCEVAddRecExpr *AR = dyn_cast(SE->getSCEV(IndVar)); + assert(AR && AR->getLoop() == L && AR->isAffine() && "bad loop counter"); + if (!AR->getStart()->isZero()) { + assert(AR->getStepRecurrence(*SE)->isOne() && "only handles unit stride"); + const SCEV *IVInit = AR->getStart(); + + // For pointer types, sign extend BECount in order to materialize a GEP. + // Note that for DisableIVRewrite, we never run SCEVExpander on a + // pointer type, because we must preserve the existing GEPs. Instead we + // directly generate a GEP later. + if (IVInit->getType()->isPointerTy()) { + isPtrIV = true; + CmpTy = SE->getEffectiveSCEVType(IVInit->getType()); + IVLimit = SE->getTruncateOrSignExtend(IVLimit, CmpTy); + } + // For integer types, truncate the IV before computing IVInit + BECount. + else { + if (SE->getTypeSizeInBits(IVInit->getType()) + > SE->getTypeSizeInBits(CmpTy)) + IVInit = SE->getTruncateExpr(IVInit, CmpTy); + + IVLimit = SE->getAddExpr(IVInit, IVLimit); + } + } // Expand the code for the iteration count. - assert(SE->isLoopInvariant(RHS, L) && + IRBuilder<> Builder(BI); + + assert(SE->isLoopInvariant(IVLimit, L) && "Computed iteration count is not loop invariant!"); - Value *ExitCnt = Rewriter.expandCodeFor(RHS, IndVar->getType(), BI); + Value *ExitCnt = Rewriter.expandCodeFor(IVLimit, CmpTy, BI); + + // Create a gep for IVInit + IVLimit from on an existing pointer base. + assert(isPtrIV == IndVar->getType()->isPointerTy() && + "IndVar type must match IVInit type"); + if (isPtrIV) { + Value *IVStart = IndVar->getIncomingValueForBlock(L->getLoopPreheader()); + assert(AR->getStart() == SE->getSCEV(IVStart) && "bad loop counter"); + const PointerType *PointerTy = cast(IVStart->getType()); + assert(SE->getSizeOfExpr(PointerTy->getElementType())->isOne() && + "unit stride pointer IV must be i8*"); + + Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator()); + ExitCnt = Builder.CreateGEP(IVStart, ExitCnt, "lftr.limit"); + Builder.SetInsertPoint(BI); + } // Insert a new icmp_ne or icmp_eq instruction before the branch. - ICmpInst::Predicate Opcode; + ICmpInst::Predicate P; if (L->contains(BI->getSuccessor(0))) - Opcode = ICmpInst::ICMP_NE; + P = ICmpInst::ICMP_NE; else - Opcode = ICmpInst::ICMP_EQ; + P = ICmpInst::ICMP_EQ; DEBUG(dbgs() << "INDVARS: Rewriting loop exit condition to:\n" << " LHS:" << *CmpIndVar << '\n' << " op:\t" - << (Opcode == ICmpInst::ICMP_NE ? "!=" : "==") << "\n" - << " RHS:\t" << *RHS << "\n"); + << (P == ICmpInst::ICMP_NE ? "!=" : "==") << "\n" + << " RHS:\t" << *ExitCnt << "\n" + << " Expr:\t" << *IVLimit << "\n"); - ICmpInst *Cond = new ICmpInst(BI, Opcode, CmpIndVar, ExitCnt, "exitcond"); - Cond->setDebugLoc(BI->getDebugLoc()); + if (SE->getTypeSizeInBits(CmpIndVar->getType()) + > SE->getTypeSizeInBits(CmpTy)) { + CmpIndVar = Builder.CreateTrunc(CmpIndVar, CmpTy, "lftr.wideiv"); + } + + Value *Cond = Builder.CreateICmp(P, CmpIndVar, ExitCnt, "exitcond"); Value *OrigCond = BI->getCondition(); // It's tempting to use replaceAllUsesWith here to fully replace the old // comparison, but that's not immediately safe, since users of the old @@ -1784,8 +2027,9 @@ // a canonical induction variable should be inserted. Type *LargestType = 0; bool NeedCannIV = false; + bool ReuseIVForExit = DisableIVRewrite && !ForceLFTR; bool ExpandBECount = canExpandBackedgeTakenCount(L, SE); - if (ExpandBECount) { + if (ExpandBECount && !ReuseIVForExit) { // If we have a known trip count and a single exit block, we'll be // rewriting the loop exit test condition below, which requires a // canonical induction variable. @@ -1848,15 +2092,13 @@ OldCannIV->insertBefore(L->getHeader()->getFirstNonPHI()); } } - + else if (ExpandBECount && ReuseIVForExit && needsLFTR(L, DT)) { + IndVar = FindLoopCounter(L, BackedgeTakenCount, SE, DT, TD); + } // If we have a trip count expression, rewrite the loop's exit condition // using it. We can currently only handle loops with a single exit. - ICmpInst *NewICmp = 0; - if (ExpandBECount) { - assert(canExpandBackedgeTakenCount(L, SE) && - "canonical IV disrupted BackedgeTaken expansion"); - assert(NeedCannIV && - "LinearFunctionTestReplace requires a canonical induction variable"); + Value *NewICmp = 0; + if (ExpandBECount && IndVar) { // Check preconditions for proper SCEVExpander operation. SCEV does not // express SCEVExpander's dependencies, such as LoopSimplify. Instead any // pass that uses the SCEVExpander must do it. This does not work well for @@ -1894,9 +2136,11 @@ // For completeness, inform IVUsers of the IV use in the newly-created // loop exit test instruction. - if (NewICmp && IU) - IU->AddUsersIfInteresting(cast(NewICmp->getOperand(0))); - + if (IU && NewICmp) { + ICmpInst *NewICmpInst = dyn_cast(NewICmp); + if (NewICmpInst) + IU->AddUsersIfInteresting(cast(NewICmpInst->getOperand(0))); + } // Clean up dead instructions. Changed |= DeleteDeadPHIs(L->getHeader()); // Check a post-condition. Modified: llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll?rev=135420&r1=135419&r2=135420&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Mon Jul 18 15:32:31 2011 @@ -9,10 +9,9 @@ ; Note that all four functions should actually be converted to ; memset. However, this test case validates indvars behavior. We ; don't check that phis are "folded together" because that is a job -; for loop strength reduction. But indvars must remove sext, zext, -; trunc, and add i8. +; for loop strength reduction. But indvars must remove sext, zext, and add i8. ; -; CHECK-NOT: {{sext|zext|trunc|add i8}} +; CHECK-NOT: {{sext|zext|add i8}} ; ModuleID = 'ada.bc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-n:8:16:32" Added: llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll?rev=135420&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll Mon Jul 18 15:32:31 2011 @@ -0,0 +1,230 @@ +; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; +; Make sure that indvars can perform LFTR without a canonical IV. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +; Perform LFTR using the original pointer-type IV. + +; for(char* p = base; p < base + n; ++p) { +; *p = p-base; +; } +define void @ptriv(i8* %base, i32 %n) nounwind { +entry: + %idx.ext = sext i32 %n to i64 + %add.ptr = getelementptr inbounds i8* %base, i64 %idx.ext + %cmp1 = icmp ult i8* %base, %add.ptr + br i1 %cmp1, label %for.body, label %for.end + +; CHECK: for.body: +; CHECK: phi i8* +; CHECK-NOT: phi +; CHECK-NOT: add +; CHECK: icmp ne i8* +; CHECK: br i1 +for.body: + %p.02 = phi i8* [ %base, %entry ], [ %incdec.ptr, %for.body ] + ; cruft to make the IV useful + %sub.ptr.lhs.cast = ptrtoint i8* %p.02 to i64 + %sub.ptr.rhs.cast = ptrtoint i8* %base to i64 + %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast + %conv = trunc i64 %sub.ptr.sub to i8 + store i8 %conv, i8* %p.02 + %incdec.ptr = getelementptr inbounds i8* %p.02, i32 1 + %cmp = icmp ult i8* %incdec.ptr, %add.ptr + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +; It would be nice if SCEV and any loop analysis could assume that +; preheaders exist. Unfortunately it is not always the case. This test +; checks that SCEVExpander can handle an outer loop that has not yet +; been simplified. As a result, the inner loop's exit test will not be +; rewritten. +define void @expandOuterRecurrence(i32 %arg) nounwind { +entry: + %sub1 = sub nsw i32 %arg, 1 + %cmp1 = icmp slt i32 0, %sub1 + br i1 %cmp1, label %outer, label %exit + +outer: + %i = phi i32 [ 0, %entry ], [ %i.inc, %outer.inc ] + %sub2 = sub nsw i32 %arg, %i + %sub3 = sub nsw i32 %sub2, 1 + %cmp2 = icmp slt i32 0, %sub3 + br i1 %cmp2, label %inner.ph, label %outer.inc + +inner.ph: + br label %inner + +; CHECK: inner: +; CHECK: icmp slt +; CHECK: br i1 +inner: + %j = phi i32 [ 0, %inner.ph ], [ %j.inc, %inner ] + %j.inc = add nsw i32 %j, 1 + %cmp3 = icmp slt i32 %j.inc, %sub3 + br i1 %cmp3, label %inner, label %outer.inc + +; CHECK: outer.inc: +; CHECK: icmp ne +; CHECK: br i1 +outer.inc: + %i.inc = add nsw i32 %i, 1 + %cmp4 = icmp slt i32 %i.inc, %sub1 + br i1 %cmp4, label %outer, label %exit + +exit: + ret void +} + +; Force SCEVExpander to look for an existing well-formed phi. +; Perform LFTR without generating extra preheader code. +define void @guardedloop([0 x double]* %matrix, [0 x double]* %vector, + i32 %irow, i32 %ilead) nounwind { +; CHECK: entry: +; CHECK-NOT: zext +; CHECK-NOT: add +; CHECK: loop: +; CHECK: phi i64 +; CHECK: phi i64 +; CHECK-NOT: phi +; CHECK: icmp ne +; CHECK: br i1 +entry: + %cmp = icmp slt i32 1, %irow + br i1 %cmp, label %loop, label %return + +loop: + %rowidx = phi i32 [ 0, %entry ], [ %row.inc, %loop ] + %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ] + %diagidx = add nsw i32 %rowidx, %i + %diagidxw = sext i32 %diagidx to i64 + %matrixp = getelementptr inbounds [0 x double]* %matrix, i32 0, i64 %diagidxw + %v1 = load double* %matrixp + %iw = sext i32 %i to i64 + %vectorp = getelementptr inbounds [0 x double]* %vector, i32 0, i64 %iw + %v2 = load double* %vectorp + %row.inc = add nsw i32 %rowidx, %ilead + %i.inc = add nsw i32 %i, 1 + %cmp196 = icmp slt i32 %i.inc, %irow + br i1 %cmp196, label %loop, label %return + +return: + ret void +} + +; Avoid generating extra code to materialize a trip count. Skip LFTR. +define void @unguardedloop([0 x double]* %matrix, [0 x double]* %vector, + i32 %irow, i32 %ilead) nounwind { +entry: + br label %loop + +; CHECK: entry: +; CHECK-NOT: zext +; CHECK-NOT: add +; CHECK: loop: +; CHECK: phi i64 +; CHECK: phi i64 +; CHECK-NOT: phi +; CHECK: icmp slt +; CHECK: br i1 +loop: + %rowidx = phi i32 [ 0, %entry ], [ %row.inc, %loop ] + %i = phi i32 [ 0, %entry ], [ %i.inc, %loop ] + %diagidx = add nsw i32 %rowidx, %i + %diagidxw = sext i32 %diagidx to i64 + %matrixp = getelementptr inbounds [0 x double]* %matrix, i32 0, i64 %diagidxw + %v1 = load double* %matrixp + %iw = sext i32 %i to i64 + %vectorp = getelementptr inbounds [0 x double]* %vector, i32 0, i64 %iw + %v2 = load double* %vectorp + %row.inc = add nsw i32 %rowidx, %ilead + %i.inc = add nsw i32 %i, 1 + %cmp196 = icmp slt i32 %i.inc, %irow + br i1 %cmp196, label %loop, label %return + +return: + ret void +} + +; Remove %i which is only used by the exit test. +; Verify that SCEV can still compute a backedge count from the sign +; extended %n, used for pointer comparison by LFTR. +define void @geplftr(i8* %base, i32 %x, i32 %y, i32 %n) nounwind { +entry: + %x.ext = sext i32 %x to i64 + %add.ptr = getelementptr inbounds i8* %base, i64 %x.ext + %y.ext = sext i32 %y to i64 + %add.ptr10 = getelementptr inbounds i8* %add.ptr, i64 %y.ext + %lim = add i32 %x, %n + %cmp.ph = icmp ult i32 %x, %lim + br i1 %cmp.ph, label %loop, label %exit + +; CHECK: loop: +; CHECK: phi i8* +; CHECK-NOT: phi +; CHECK: getelementptr +; CHECK: store +; CHECK: icmp ne i8* +; CHECK: br i1 +loop: + %i = phi i32 [ %x, %entry ], [ %inc, %loop ] + %aptr = phi i8* [ %add.ptr10, %entry ], [ %incdec.ptr, %loop ] + %incdec.ptr = getelementptr inbounds i8* %aptr, i32 1 + store i8 3, i8* %aptr + %inc = add i32 %i, 1 + %cmp = icmp ult i32 %inc, %lim + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; Exercise backedge taken count verification with a never-taken loop. +define void @nevertaken() nounwind uwtable ssp { +entry: + br label %loop + +; CHECK: loop: +; CHECK-NOT: phi +; CHECK-NOT: add +; CHECK-NOT: icmp +; CHECK: exit: +loop: + %i = phi i32 [ 0, %entry ], [ %inc, %loop ] + %inc = add nsw i32 %i, 1 + %cmp = icmp sle i32 %inc, 0 + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; Test LFTR on an IV whose recurrence start is a non-unit pointer type. +define void @aryptriv([256 x i8]* %base, i32 %n) nounwind { +entry: + %ivstart = getelementptr inbounds [256 x i8]* %base, i32 0, i32 0 + %ivend = getelementptr inbounds [256 x i8]* %base, i32 0, i32 %n + %cmp.ph = icmp ult i8* %ivstart, %ivend + br i1 %cmp.ph, label %loop, label %exit + +; CHECK: loop: +; CHECK: phi i8* +; CHECK-NOT: phi +; CHECK: getelementptr +; CHECK: store +; CHECK: icmp ne i8* +; CHECK: br i1 +loop: + %aptr = phi i8* [ %ivstart, %entry ], [ %incdec.ptr, %loop ] + %incdec.ptr = getelementptr inbounds i8* %aptr, i32 1 + store i8 3, i8* %aptr + %cmp = icmp ult i8* %incdec.ptr, %ivend + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} From grosser at fim.uni-passau.de Mon Jul 18 15:34:42 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 18 Jul 2011 20:34:42 -0000 Subject: [llvm-commits] [polly] r135421 - /polly/trunk/www/index.html Message-ID: <20110718203442.14F0D2A6C12C@llvm.org> Author: grosser Date: Mon Jul 18 15:34:41 2011 New Revision: 135421 URL: http://llvm.org/viewvc/llvm-project?rev=135421&view=rev Log: www: Mention new Polly Builder in News Modified: polly/trunk/www/index.html Modified: polly/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/index.html?rev=135421&r1=135420&r2=135421&view=diff ============================================================================== --- polly/trunk/www/index.html (original) +++ polly/trunk/www/index.html Mon Jul 18 15:34:41 2011 @@ -36,6 +36,9 @@
From eli.friedman at gmail.com Mon Jul 18 21:24:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 19 Jul 2011 02:24:07 -0000 Subject: [llvm-commits] [llvm] r135462 - /llvm/trunk/include/llvm/Target/TargetLowering.h Message-ID: <20110719022407.4AC0A2A6C12C@llvm.org> Author: efriedma Date: Mon Jul 18 21:24:07 2011 New Revision: 135462 URL: http://llvm.org/viewvc/llvm-project?rev=135462&view=rev Log: Make isLoadExtLegal and isTruncStoreLegal check what the name says. :) This might have some minor effect on CellSPU, but all other targets should be unaffected. Fixing per report from Damien Vincent on llvmdev. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=135462&r1=135461&r2=135462&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Jul 18 21:24:07 2011 @@ -383,9 +383,7 @@ /// isLoadExtLegal - Return true if the specified load with extension is legal /// on this target. bool isLoadExtLegal(unsigned ExtType, EVT VT) const { - return VT.isSimple() && - (getLoadExtAction(ExtType, VT) == Legal || - getLoadExtAction(ExtType, VT) == Custom); + return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; } /// getTruncStoreAction - Return how this store with truncation should be @@ -404,8 +402,7 @@ /// legal on this target. bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { return isTypeLegal(ValVT) && MemVT.isSimple() && - (getTruncStoreAction(ValVT, MemVT) == Legal || - getTruncStoreAction(ValVT, MemVT) == Custom); + getTruncStoreAction(ValVT, MemVT) == Legal; } /// getIndexedLoadAction - Return how the indexed load should be treated: From ahatanak at gmail.com Mon Jul 18 22:14:58 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 03:14:58 -0000 Subject: [llvm-commits] [llvm] r135464 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719031458.B66302A6C12C@llvm.org> Author: ahatanak Date: Mon Jul 18 22:14:58 2011 New Revision: 135464 URL: http://llvm.org/viewvc/llvm-project?rev=135464&view=rev Log: Do not insert instructions in reverse order. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135464&r1=135463&r2=135464&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 22:14:58 2011 @@ -917,15 +917,16 @@ // sra dest,tmp12,24 BB = exitMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - // reverse order - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp12).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12) - .addReg(Tmp11).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11) - .addReg(Tmp10).addReg(Shift); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10) + + MachineBasicBlock::iterator II = BB->begin(); + BuildMI(*BB, II, dl, TII->get(Mips::AND), Tmp10) .addReg(Oldval).addReg(Mask); + BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp11) + .addReg(Tmp10).addReg(Shift); + BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp12) + .addReg(Tmp11).addImm(ShiftImm); + BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp12).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. @@ -1114,13 +1115,14 @@ // sra dest,tmp9,24 BB = exitMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - // reverse order - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp9).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9) - .addReg(Tmp8).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8) + + MachineBasicBlock::iterator II = BB->begin(); + BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp8) .addReg(Oldval4).addReg(Shift); + BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp9) + .addReg(Tmp8).addImm(ShiftImm); + BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp9).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. From ahatanak at gmail.com Mon Jul 18 22:42:13 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 03:42:13 -0000 Subject: [llvm-commits] [llvm] r135465 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719034214.069492A6C12C@llvm.org> Author: ahatanak Date: Mon Jul 18 22:42:13 2011 New Revision: 135465 URL: http://llvm.org/viewvc/llvm-project?rev=135465&view=rev Log: Make EmitAtomic functions return the correct MachineBasicBlocks so that ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135465&r1=135464&r2=135465&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 22:42:13 2011 @@ -787,7 +787,7 @@ MI->eraseFromParent(); // The instruction is gone now. - return BB; + return exitMBB; } MachineBasicBlock * @@ -831,10 +831,12 @@ // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineFunction::iterator It = BB; ++It; MF->insert(It, loopMBB); + MF->insert(It, sinkMBB); MF->insert(It, exitMBB); // Transfer the remainder of BB and its successor edges to exitMBB. @@ -908,29 +910,30 @@ BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB); BB->addSuccessor(loopMBB); - BB->addSuccessor(exitMBB); + BB->addSuccessor(sinkMBB); - // exitMBB: + // sinkMBB: // and tmp10,oldval,mask // srl tmp11,tmp10,shift // sll tmp12,tmp11,24 // sra dest,tmp12,24 - BB = exitMBB; + BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - MachineBasicBlock::iterator II = BB->begin(); - BuildMI(*BB, II, dl, TII->get(Mips::AND), Tmp10) + BuildMI(BB, dl, TII->get(Mips::AND), Tmp10) .addReg(Oldval).addReg(Mask); - BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp11) + BuildMI(BB, dl, TII->get(Mips::SRL), Tmp11) .addReg(Tmp10).addReg(Shift); - BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp12) + BuildMI(BB, dl, TII->get(Mips::SLL), Tmp12) .addReg(Tmp11).addImm(ShiftImm); - BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + BuildMI(BB, dl, TII->get(Mips::SRA), Dest) .addReg(Tmp12).addImm(ShiftImm); + sinkMBB->addSuccessor(exitMBB); + MI->eraseFromParent(); // The instruction is gone now. - return BB; + return exitMBB; } MachineBasicBlock * @@ -999,7 +1002,7 @@ MI->eraseFromParent(); // The instruction is gone now. - return BB; + return exitMBB; } MachineBasicBlock * @@ -1043,11 +1046,13 @@ const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineFunction::iterator It = BB; ++It; MF->insert(It, loop1MBB); MF->insert(It, loop2MBB); + MF->insert(It, sinkMBB); MF->insert(It, exitMBB); // Transfer the remainder of BB and its successor edges to exitMBB. @@ -1085,13 +1090,13 @@ // loop1MBB: // ll oldval3,0(addr) // and oldval4,oldval3,mask - // bne oldval4,oldval2,exitMBB + // bne oldval4,oldval2,sinkMBB BB = loop1MBB; BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::BNE)) - .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB); - BB->addSuccessor(exitMBB); + .addReg(Oldval4).addReg(Oldval2).addMBB(sinkMBB); + BB->addSuccessor(sinkMBB); BB->addSuccessor(loop2MBB); // loop2MBB: @@ -1107,26 +1112,27 @@ BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB); BB->addSuccessor(loop1MBB); - BB->addSuccessor(exitMBB); + BB->addSuccessor(sinkMBB); - // exitMBB: + // sinkMBB: // srl tmp8,oldval4,shift // sll tmp9,tmp8,24 // sra dest,tmp9,24 - BB = exitMBB; + BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - MachineBasicBlock::iterator II = BB->begin(); - BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp8) + BuildMI(BB, dl, TII->get(Mips::SRL), Tmp8) .addReg(Oldval4).addReg(Shift); - BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp9) + BuildMI(BB, dl, TII->get(Mips::SLL), Tmp9) .addReg(Tmp8).addImm(ShiftImm); - BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + BuildMI(BB, dl, TII->get(Mips::SRA), Dest) .addReg(Tmp9).addImm(ShiftImm); + sinkMBB->addSuccessor(exitMBB); + MI->eraseFromParent(); // The instruction is gone now. - return BB; + return exitMBB; } //===----------------------------------------------------------------------===// From geek4civic at gmail.com Mon Jul 18 22:42:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 19 Jul 2011 12:42:40 +0900 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: Jeffrey and Jakob, Thanks to work on the Git article! FYI, to prevent diversion between "git-pull" and "git-svn fetch git-svn rebase", "authorsfile" would be useful. Please refer to my instruction; http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040880.html In fact, I have not been using "git-svn rebase" for months. All I need are, "git pull (--rebase)", "git-cherry-pick (or git-rebase --onto)" and "git-svn dcommit". I will add comments to docs/GS.html if I would get a time. ...Takumi From stoklund at 2pi.dk Mon Jul 18 23:12:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 18 Jul 2011 21:12:21 -0700 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: On Jul 18, 2011, at 8:42 PM, NAKAMURA Takumi wrote: > Jeffrey and Jakob, > > Thanks to work on the Git article! > > FYI, to prevent diversion between "git-pull" and "git-svn fetch git-svn rebase", > "authorsfile" would be useful. That is not necessary. 'git svn rebase' figures it out the new time you fetch and rebase. I am not using an authors file, and I commit all the time. > Please refer to my instruction; > http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040880.html > > In fact, I have not been using "git-svn rebase" for months. > All I need are, "git pull (--rebase)", "git-cherry-pick (or git-rebase > --onto)" and "git-svn dcommit". > > I will add comments to docs/GS.html if I would get a time. There are many ways of doing things with Git, and I am sure yours works well, but we should keep the instructions as simple as possible. I think Jeffrey's notes are sufficient. People can add their own tricks depending on their git-fu. We should just provide the basics a newbie needs. Thanks, Takumi. /jakob From wdietz2 at illinois.edu Mon Jul 18 23:27:18 2011 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 19 Jul 2011 04:27:18 -0000 Subject: [llvm-commits] [poolalloc] r135467 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110719042718.5574C2A6C12C@llvm.org> Author: wdietz2 Date: Mon Jul 18 23:27:18 2011 New Revision: 135467 URL: http://llvm.org/viewvc/llvm-project?rev=135467&view=rev Log: TypeRuntime.cpp: (minor) Fix iostream include, and reference to cerr Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=135467&r1=135466&r2=135467&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Mon Jul 18 23:27:18 2011 @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include #include #include @@ -14,6 +14,8 @@ #include +using std::cerr; + #define DEBUG (0) /* Size of shadow memory. We're hoping everything fits in 46bits. */ From jyasskin at google.com Tue Jul 19 00:02:15 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 18 Jul 2011 22:02:15 -0700 Subject: [llvm-commits] [PATCH] Explicitly cast narrowing conversions inside {}s that will become errors in C++0x Message-ID: These were caught by my C++0x-narrowing-errors at http://codereview.appspot.com/4698047/, and they'll probably need to get fixed before turning the narrowing warnings on by default in C++98 mode, or they'll break the clang bootstrap. This is just the LLVM narrowings. Review here or at http://codereview.appspot.com/4773041. Jeffrey -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_narrowings.diff Type: application/octet-stream Size: 3790 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110718/88eefd8b/attachment.obj From echristo at apple.com Tue Jul 19 01:32:00 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 18 Jul 2011 23:32:00 -0700 Subject: [llvm-commits] [llvm] r135457 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Support/Dwarf.h lib/Analysis/DIBuilder.cpp lib/Analysis/DebugInfo.cpp In-Reply-To: <20110719010333.19CE52A6C12C@llvm.org> References: <20110719010333.19CE52A6C12C@llvm.org> Message-ID: On Jul 18, 2011, at 6:03 PM, Devang Patel wrote: > Author: dpatel > Date: Mon Jul 18 20:03:32 2011 > New Revision: 135457 > > URL: http://llvm.org/viewvc/llvm-project?rev=135457&view=rev > Log: > Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block. One of these patches broke bootstrap for llvm-gcc. Can you take a look please? -eric From evan.cheng at apple.com Tue Jul 19 01:37:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 19 Jul 2011 06:37:02 -0000 Subject: [llvm-commits] [llvm] r135468 - in /llvm/trunk: ./ autoconf/ cmake/ include/llvm-c/ include/llvm/Config/ include/llvm/ExecutionEngine/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/ExecutionEngine/ lib/ExecutionEngine/JIT/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ ... Message-ID: <20110719063703.69A062A6C12C@llvm.org> Author: evancheng Date: Tue Jul 19 01:37:02 2011 New Revision: 135468 URL: http://llvm.org/viewvc/llvm-project?rev=135468&view=rev Log: Introduce MCCodeGenInfo, which keeps information that can affect codegen (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. Added: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h llvm/trunk/lib/MC/MCCodeGenInfo.cpp Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/cmake/config-ix.cmake llvm/trunk/configure llvm/trunk/include/llvm-c/Target.h llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in llvm/trunk/include/llvm/Config/llvm-config.h.cmake llvm/trunk/include/llvm/Config/llvm-config.h.in llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/include/llvm/Target/TargetSelect.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CBackend/CTargetMachine.h llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.h llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.h llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/lli/lli.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Jul 19 01:37:02 2011 @@ -659,6 +659,7 @@ LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo" + LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo" LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser" @@ -669,6 +670,8 @@ [LLVM name for the native TargetInfo init function, if available]) AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCASMINFO, $LLVM_NATIVE_MCASMINFO, [LLVM name for the native MCAsmInfo init function, if available]) + AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCCODEGENINFO, $LLVM_NATIVE_MCCODEGENINFO, + [LLVM name for the native MCCodeGenInfo init function, if available]) AC_DEFINE_UNQUOTED(LLVM_NATIVE_ASMPRINTER, $LLVM_NATIVE_ASMPRINTER, [LLVM name for the native AsmPrinter init function, if available]) if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Tue Jul 19 01:37:02 2011 @@ -337,6 +337,7 @@ set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target) set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo) set(LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo) + set(LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCODEGENInfo) set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter) endif () Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Jul 19 01:37:02 2011 @@ -5121,6 +5121,7 @@ LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo" + LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo" LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser" @@ -5142,6 +5143,11 @@ cat >>confdefs.h <<_ACEOF +#define LLVM_NATIVE_MCCODEGENINFO $LLVM_NATIVE_MCCODEGENINFO +_ACEOF + + +cat >>confdefs.h <<_ACEOF #define LLVM_NATIVE_ASMPRINTER $LLVM_NATIVE_ASMPRINTER _ACEOF Modified: llvm/trunk/include/llvm-c/Target.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Target.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Target.h (original) +++ llvm/trunk/include/llvm-c/Target.h Tue Jul 19 01:37:02 2011 @@ -46,6 +46,11 @@ #include "llvm/Config/Targets.def" #undef LLVM_TARGET /* Explicit undef to make SWIG happier */ +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCCodeGenInfo(void); +#include "llvm/Config/Targets.def" +#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ + /** LLVMInitializeAllTargetInfos - The main program should call this function if it wants access to all available targets that LLVM is configured to support. */ @@ -73,6 +78,7 @@ LLVM_NATIVE_TARGETINFO(); LLVM_NATIVE_TARGET(); LLVM_NATIVE_MCASMINFO(); + LLVM_NATIVE_MCCODEGENINFO(); return 0; #else return 1; Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Tue Jul 19 01:37:02 2011 @@ -560,6 +560,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo + /* Define if this is Unixish platform */ #cmakedefine LLVM_ON_UNIX ${LLVM_ON_UNIX} Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Tue Jul 19 01:37:02 2011 @@ -576,6 +576,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #undef LLVM_NATIVE_MCASMINFO +/* LLVM name for the native MCCODEGENInfo init function, if available */ +#undef LLVM_NATIVE_MCCODEGENINFO + /* LLVM name for the native Target init function, if available */ #undef LLVM_NATIVE_TARGET Modified: llvm/trunk/include/llvm/Config/llvm-config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.cmake?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.cmake Tue Jul 19 01:37:02 2011 @@ -61,6 +61,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo + /* LLVM name for the native AsmPrinter init function, if available */ #cmakedefine LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter Modified: llvm/trunk/include/llvm/Config/llvm-config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/llvm-config.h.in?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/llvm-config.h.in (original) +++ llvm/trunk/include/llvm/Config/llvm-config.h.in Tue Jul 19 01:37:02 2011 @@ -61,6 +61,9 @@ /* LLVM name for the native MCAsmInfo init function, if available */ #undef LLVM_NATIVE_MCASMINFO +/* LLVM name for the native MCCodeGenInfo init function, if available */ +#undef LLVM_NATIVE_MCCODEGENINFO + /* LLVM name for the native AsmPrinter init function, if available */ #undef LLVM_NATIVE_ASMPRINTER Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Tue Jul 19 01:37:02 2011 @@ -18,6 +18,7 @@ #include #include #include +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/ValueMap.h" @@ -201,6 +202,7 @@ CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, + Reloc::Model RM = Reloc::Default, CodeModel::Model CMM = CodeModel::Default); @@ -463,6 +465,7 @@ CodeGenOpt::Level OptLevel; JITMemoryManager *JMM; bool AllocateGVsWithCode; + Reloc::Model RelocModel; CodeModel::Model CMModel; std::string MArch; std::string MCPU; @@ -476,6 +479,7 @@ OptLevel = CodeGenOpt::Default; JMM = NULL; AllocateGVsWithCode = false; + RelocModel = Reloc::Default; CMModel = CodeModel::Default; UseMCJIT = false; } @@ -517,6 +521,13 @@ return *this; } + /// setRelocationModel - Set the relocation model that the ExecutionEngine + /// target is using. Defaults to target specific default "Reloc::Default". + EngineBuilder &setRelocationModel(Reloc::Model RM) { + RelocModel = RM; + return *this; + } + /// setCodeModel - Set the CodeModel that the ExecutionEngine target /// data is using. Defaults to target specific default "CodeModel::Default". EngineBuilder &setCodeModel(CodeModel::Model M) { @@ -569,6 +580,7 @@ StringRef MArch, StringRef MCPU, const SmallVectorImpl& MAttrs, + Reloc::Model RM, std::string *Err); ExecutionEngine *create(); Added: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeGenInfo.h?rev=135468&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCCodeGenInfo.h (added) +++ llvm/trunk/include/llvm/MC/MCCodeGenInfo.h Tue Jul 19 01:37:02 2011 @@ -0,0 +1,36 @@ +//===-- llvm/MC/MCCodeGenInfo.h - Target CodeGen Info -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tracks information about the target which can affect codegen, +// asm parsing, and asm printing. For example, relocation model. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCCODEGENINFO_H +#define LLVM_MC_MCCODEGENINFO_H + +namespace llvm { + // Relocation model types. + namespace Reloc { + enum Model { Default, Static, PIC_, DynamicNoPIC }; + } + + class MCCodeGenInfo { + /// RelocationModel - Relocation model: statcic, pic, etc. + /// + Reloc::Model RelocationModel; + + public: + void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default); + + Reloc::Model getRelocationModel() const { return RelocationModel; } + }; +} // namespace llvm + +#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Tue Jul 19 01:37:02 2011 @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/StringRef.h" #include #include @@ -23,6 +24,7 @@ class InstrItineraryData; class JITCodeEmitter; class MCAsmInfo; +class MCCodeGenInfo; class MCContext; class Pass; class PassManager; @@ -41,16 +43,6 @@ class formatted_raw_ostream; class raw_ostream; -// Relocation model types. -namespace Reloc { - enum Model { - Default, - Static, - PIC_, // Cannot be named PIC due to collision with -DPIC - DynamicNoPIC - }; -} - // Code model types. namespace CodeModel { enum Model { @@ -108,6 +100,10 @@ std::string TargetCPU; std::string TargetFS; + /// CodeGenInfo - Low level target information such as relocation model. + /// + const MCCodeGenInfo *CodeGenInfo; + /// AsmInfo - Contains target specific asm information. /// const MCAsmInfo *AsmInfo; @@ -214,11 +210,7 @@ /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. - static Reloc::Model getRelocationModel(); - - /// setRelocationModel - Sets the code generation relocation model. - /// - static void setRelocationModel(Reloc::Model Model); + Reloc::Model getRelocationModel() const; /// getCodeModel - Returns the code model. The choices are small, kernel, /// medium, large, and target default. @@ -309,7 +301,7 @@ class LLVMTargetMachine : public TargetMachine { protected: // Can only create subclasses. LLVMTargetMachine(const Target &T, StringRef TargetTriple, - StringRef CPU, StringRef FS); + StringRef CPU, StringRef FS, Reloc::Model RM); private: /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Tue Jul 19 01:37:02 2011 @@ -19,6 +19,7 @@ #ifndef LLVM_TARGET_TARGETREGISTRY_H #define LLVM_TARGET_TARGETREGISTRY_H +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/ADT/Triple.h" #include #include @@ -37,6 +38,7 @@ class MCRegisterInfo; class MCStreamer; class MCSubtargetInfo; + class MCCodeGenInfo; class TargetAsmBackend; class TargetAsmLexer; class TargetAsmParser; @@ -68,15 +70,17 @@ typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T, StringRef TT); + typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, StringRef CPU, StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &Features); + StringRef TT, + StringRef CPU, + StringRef Features, + Reloc::Model RM); typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T, @@ -132,6 +136,10 @@ /// registered. MCAsmInfoCtorFnTy MCAsmInfoCtorFn; + /// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo, + /// if registered. + MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; + /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// if registered. MCInstrInfoCtorFnTy MCInstrInfoCtorFn; @@ -253,6 +261,14 @@ return MCAsmInfoCtorFn(*this, Triple); } + /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. + /// + MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const { + if (!MCCodeGenInfoCtorFn) + return 0; + return MCCodeGenInfoCtorFn(Triple, M); + } + /// createMCInstrInfo - Create a MCInstrInfo implementation. /// MCInstrInfo *createMCInstrInfo() const { @@ -292,12 +308,12 @@ /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - TargetMachine *createTargetMachine(const std::string &Triple, - const std::string &CPU, - const std::string &Features) const { + TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, + StringRef Features, + Reloc::Model RM = Reloc::Default) const { if (!TargetMachineCtorFn) return 0; - return TargetMachineCtorFn(*this, Triple, CPU, Features); + return TargetMachineCtorFn(*this, Triple, CPU, Features, RM); } /// createAsmBackend - Create a target specific assembly parser. @@ -500,6 +516,22 @@ T.MCAsmInfoCtorFn = Fn; } + /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the + /// given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCCodeGenInfo for the target. + static void RegisterMCCodeGenInfo(Target &T, + Target::MCCodeGenInfoCtorFnTy Fn) { + // Ignore duplicate registration. + if (!T.MCCodeGenInfoCtorFn) + T.MCCodeGenInfoCtorFn = Fn; + } + /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the /// given target. /// @@ -756,6 +788,39 @@ } }; + /// RegisterMCCodeGenInfo - Helper template for registering a target codegen info + /// implementation. This invokes the static "Create" method on the class + /// to actually do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCCodeGenInfo X(TheFooTarget); + /// } + template + struct RegisterMCCodeGenInfo { + RegisterMCCodeGenInfo(Target &T) { + TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); + } + private: + static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) { + return new MCCodeGenInfoImpl(); + } + }; + + /// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen + /// info implementation. This invokes the specified function to do the + /// construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCCodeGenInfoFn X(TheFooTarget, TheFunction); + /// } + struct RegisterMCCodeGenInfoFn { + RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) { + TargetRegistry::RegisterMCCodeGenInfo(T, Fn); + } + }; + /// RegisterMCInstrInfo - Helper template for registering a target instruction /// info implementation. This invokes the static "Create" method on the class /// to actually do the construction. Usage: @@ -871,10 +936,10 @@ } private: - static TargetMachine *Allocator(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) { - return new TargetMachineImpl(T, TT, CPU, FS); + static TargetMachine *Allocator(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) { + return new TargetMachineImpl(T, TT, CPU, FS, RM); } }; Modified: llvm/trunk/include/llvm/Target/TargetSelect.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Target/TargetSelect.h Tue Jul 19 01:37:02 2011 @@ -31,6 +31,10 @@ #include "llvm/Config/Targets.def" #define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCCodeGenInfo(); +#include "llvm/Config/Targets.def" + +#define LLVM_TARGET(TargetName) \ void LLVMInitialize##TargetName##MCInstrInfo(); #include "llvm/Config/Targets.def" @@ -91,6 +95,16 @@ #include "llvm/Config/Targets.def" } + /// InitializeAllMCCodeGenInfos - The main program should call this function + /// if it wants access to all targets machines that LLVM is configured to + /// support, to make them available via the TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCCodeGenInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCCodeGenInfo(); +#include "llvm/Config/Targets.def" + } + /// InitializeAllMCInstrInfos - The main program should call this function /// if it wants access to all available instruction infos for targets that /// LLVM is configured to support, to make them available via the @@ -164,6 +178,7 @@ LLVM_NATIVE_TARGETINFO(); LLVM_NATIVE_TARGET(); LLVM_NATIVE_MCASMINFO(); + LLVM_NATIVE_MCCODEGENINFO(); return false; #else return true; Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -103,8 +103,10 @@ cl::desc("Enable the \"fast\" instruction selector")); LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, - StringRef CPU, StringRef FS) + StringRef CPU, StringRef FS, + Reloc::Model RM) : TargetMachine(T, Triple, CPU, FS) { + CodeGenInfo = T.createMCCodeGenInfo(Triple, RM); AsmInfo = T.createMCAsmInfo(Triple); } Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Tue Jul 19 01:37:02 2011 @@ -422,6 +422,7 @@ JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, bool GVsWithCode, + Reloc::Model RM, CodeModel::Model CMM) { if (ExecutionEngine::JITCtor == 0) { if (ErrorStr) @@ -436,7 +437,7 @@ SmallVector MAttrs; TargetMachine *TM = - EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr); + EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr); if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; TM->setCodeModel(CMM); @@ -465,8 +466,8 @@ // Unless the interpreter was explicitly selected or the JIT is not linked, // try making a JIT. if (WhichEngine & EngineKind::JIT) { - if (TargetMachine *TM = - EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr)) { + if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, + RelocModel, ErrorStr)) { TM->setCodeModel(CMModel); if (UseMCJIT && ExecutionEngine::MCJITCtor) { Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Tue Jul 19 01:37:02 2011 @@ -100,9 +100,10 @@ CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, + Reloc::Model RM = Reloc::Default, CodeModel::Model CMM = CodeModel::Default) { return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode, - CMM); + RM, CMM); } virtual void addModule(Module *M); Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Tue Jul 19 01:37:02 2011 @@ -30,6 +30,7 @@ StringRef MArch, StringRef MCPU, const SmallVectorImpl& MAttrs, + Reloc::Model RM, std::string *ErrorStr) { Triple TheTriple(Mod->getTargetTriple()); if (TheTriple.getTriple().empty()) @@ -83,8 +84,8 @@ } // Allocate a target... - TargetMachine *Target = - TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr); + TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(), + MCPU, FeaturesStr, RM); assert(Target && "Could not allocate target machine!"); return Target; } Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Tue Jul 19 01:37:02 2011 @@ -6,6 +6,7 @@ MCAsmStreamer.cpp MCAssembler.cpp MCCodeEmitter.cpp + MCCodeGenInfo.cpp MCContext.cpp MCDisassembler.cpp MCELF.cpp Added: llvm/trunk/lib/MC/MCCodeGenInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCCodeGenInfo.cpp?rev=135468&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCCodeGenInfo.cpp (added) +++ llvm/trunk/lib/MC/MCCodeGenInfo.cpp Tue Jul 19 01:37:02 2011 @@ -0,0 +1,20 @@ +//===-- MCCodeGenInfo.cpp - Target CodeGen Info -----------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tracks information about the target which can affect codegen, +// asm parsing, and asm printing. For example, relocation model. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCCodeGenInfo.h" +using namespace llvm; + +void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) { + RelocationModel = RM; +} Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Tue Jul 19 01:37:02 2011 @@ -41,6 +41,7 @@ // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllMCRegisterInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Tue Jul 19 01:37:02 2011 @@ -108,6 +108,7 @@ InitializeAllTargetInfos(); InitializeAllTargets(); + InitializeAllMCCodeGenInfos(); InitializeAllMCAsmInfos(); InitializeAllMCRegisterInfos(); InitializeAllMCSubtargetInfos(); Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -62,25 +62,22 @@ /// TargetMachine ctor - Create an ARM architecture model. /// -ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { - DefRelocModel = getRelocationModel(); - // Default to soft float ABI if (FloatABIType == FloatABI::Default) FloatABIType = FloatABI::Soft; } -ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget), +ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -95,10 +92,10 @@ "support ARM mode execution!"); } -ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : ARMBaseTargetMachine(T, TT, CPU, FS), +ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), @@ -179,10 +176,6 @@ bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // FIXME: Move this to TargetJITInfo! - if (DefRelocModel == Reloc::Default) - setRelocationModel(Reloc::Static); - // Machine code emitter pass for ARM. PM.add(createARMJITCodeEmitterPass(*this, JCE)); return false; Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -37,11 +37,10 @@ private: ARMJITInfo JITInfo; InstrItineraryData InstrItins; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. public: - ARMBaseTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ARMBaseTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -69,8 +68,8 @@ ARMSelectionDAGInfo TSInfo; ARMFrameLowering FrameLowering; public: - ARMTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ARMTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -108,8 +107,8 @@ // Either Thumb1FrameLowering or ARMFrameLowering. OwningPtr FrameLowering; public: - ThumbTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + ThumbTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Tue Jul 19 01:37:02 2011 @@ -15,7 +15,7 @@ #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Target/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -142,3 +142,17 @@ RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo); RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo); } + +MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::DynamicNoPIC; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeARMMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo); +} + Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -22,19 +22,17 @@ RegisterTargetMachine X(TheAlphaTarget); } -AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), TLInfo(*this), TSInfo(*this) { - setRelocationModel(Reloc::PIC_); } - //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -36,8 +36,8 @@ AlphaSelectionDAGInfo TSInfo; public: - AlphaTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + AlphaTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -65,3 +65,15 @@ extern "C" void LLVMInitializeAlphaMCAsmInfo() { RegisterMCAsmInfo X(TheAlphaTarget); } + +MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(Reloc::PIC_); + return X; +} + +extern "C" void LLVMInitializeAlphaMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheAlphaTarget, + createAlphaMCCodeGenInfo); +} + Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -22,10 +22,10 @@ } BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -35,8 +35,8 @@ BlackfinFrameLowering FrameLowering; BlackfinIntrinsicInfo IntrinsicInfo; public: - BlackfinTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + BlackfinTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -68,3 +68,14 @@ extern "C" void LLVMInitializeBlackfinMCAsmInfo() { RegisterMCAsmInfo X(TheBlackfinTarget); } + +MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheBlackfinTarget, + createBlackfinMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Jul 19 01:37:02 2011 @@ -71,6 +71,8 @@ extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {} +extern "C" void LLVMInitializeCBackendMCCodeGenInfo() {} + namespace { class CBEMCAsmInfo : public MCAsmInfo { public: Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -20,8 +20,8 @@ namespace llvm { struct CTargetMachine : public TargetMachine { - CTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) + CTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -77,3 +77,16 @@ extern "C" void LLVMInitializeCellSPUMCAsmInfo() { RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo); } + +MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + // For the time being, use static relocations, since there's really no + // support for PIC yet. + X->InitMCCodeGenInfo(Reloc::Static); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheCellSPUTarget, + createSPUMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -31,9 +31,9 @@ return &LR[0]; } -SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU,const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, + StringRef CPU,StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), @@ -41,9 +41,6 @@ TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - // For the time being, use static relocations, since there's really no - // support for PIC yet. - setRelocationModel(Reloc::Static); } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -38,8 +38,8 @@ SPUSelectionDAGInfo TSInfo; InstrItineraryData InstrItins; public: - SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SPUTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jul 19 01:37:02 2011 @@ -85,6 +85,8 @@ extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {} +extern "C" void LLVMInitializeCppBackendMCCodeGenInfo() {} + namespace { typedef std::vector TypeList; typedef std::map TypeMap; Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -22,8 +22,8 @@ class formatted_raw_ostream; struct CPPTargetMachine : public TargetMachine { - CPPTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) + CPPTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Tue Jul 19 01:37:02 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Target/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -67,19 +67,15 @@ // offset from the stack/frame pointer, using StackGrowsUp enables // an easier handling. MBlazeTargetMachine:: -MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS): - LLVMTargetMachine(T, TT, CPU, FS), +MBlazeTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM): + LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - if (getRelocationModel() == Reloc::Default) { - setRelocationModel(Reloc::Static); - } - if (getCodeModel() == CodeModel::Default) setCodeModel(CodeModel::Small); } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -41,8 +41,8 @@ InstrItineraryData InstrItins; public: - MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MBlazeTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -74,3 +74,16 @@ extern "C" void LLVMInitializeMBlazeMCAsmInfo() { RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo); } + +MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::Static; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMBlazeTarget, + createMBlazeMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -66,3 +66,14 @@ extern "C" void LLVMInitializeMSP430MCAsmInfo() { RegisterMCAsmInfo X(TheMSP430Target); } + +MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMSP430MCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target, + createMSP430MCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -25,10 +25,10 @@ } MSP430TargetMachine::MSP430TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Tue Jul 19 01:37:02 2011 @@ -38,8 +38,8 @@ MSP430FrameLowering FrameLowering; public: - MSP430TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MSP430TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -77,3 +77,24 @@ RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo); RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo); } + +MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) { + // Abicall enables PIC by default + if (TT.find("mipsallegrex") != std::string::npos || + TT.find("psp") != std::string::npos) + RM = Reloc::Static; + else + RM = Reloc::PIC_; + } + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeMipsMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget, + createMipsMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget, + createMipsMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -31,10 +31,10 @@ // an easier handling. // Using CodeModel::Large enables different CALL behavior. MipsTargetMachine:: -MipsTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, +MipsTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM, bool isLittle=false): - LLVMTargetMachine(T, TT, CPU, FS), + LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : @@ -42,19 +42,12 @@ InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { - // Abicall enables PIC by default - if (getRelocationModel() == Reloc::Default) { - if (Subtarget.isABI_O32()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::Static); - } } MipselTargetMachine:: -MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS) : - MipsTargetMachine(T, TT, CPU, FS, true) {} +MipselTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM) : + MipsTargetMachine(T, TT, CPU, FS, RM, true) {} // Install an instruction selector pass using // the ISelDag to gen Mips code. Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -34,9 +34,9 @@ MipsTargetLowering TLInfo; MipsSelectionDAGInfo TSInfo; public: - MipsTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool isLittle); + MipsTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -73,8 +73,8 @@ /// class MipselTargetMachine : public MipsTargetMachine { public: - MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + MipselTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -70,3 +70,14 @@ RegisterMCAsmInfo X(ThePTX32Target); RegisterMCAsmInfo Y(ThePTX64Target); } + +MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializePTXMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(ThePTX32Target, createPTXMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(ThePTX64Target, createPTXMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -47,11 +47,11 @@ // DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS, - bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), @@ -59,18 +59,16 @@ TLInfo(*this) { } -PTX32TargetMachine::PTX32TargetMachine(const Target &T, - const std::string& TT, - const std::string& CPU, - const std::string& FS) - : PTXTargetMachine(T, TT, CPU, FS, false) { +PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : PTXTargetMachine(T, TT, CPU, FS, RM, false) { } -PTX64TargetMachine::PTX64TargetMachine(const Target &T, - const std::string& TT, - const std::string& CPU, - const std::string& FS) - : PTXTargetMachine(T, TT, CPU, FS, true) { +PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : PTXTargetMachine(T, TT, CPU, FS, RM, true) { } bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -32,8 +32,8 @@ PTXTargetLowering TLInfo; public: - PTXTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, + PTXTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM, bool is64Bit); virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -61,15 +61,15 @@ class PTX32TargetMachine : public PTXTargetMachine { public: - PTX32TargetMachine(const Target &T, const std::string &TT, - const std::string& CPU, const std::string& FS); + PTX32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; // class PTX32TargetMachine class PTX64TargetMachine : public PTXTargetMachine { public: - PTX64TargetMachine(const Target &T, const std::string &TT, - const std::string& CPU, const std::string& FS); + PTX64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; // class PTX32TargetMachine } // namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -93,3 +93,22 @@ RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo); RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo); } + +MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + + if (RM == Reloc::Default) { + Triple T(TT); + if (T.isOSDarwin()) + RM = Reloc::DynamicNoPIC; + else + RM = Reloc::Static; + } + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializePowerPCMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(ThePPC32Target, createPPCMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(ThePPC64Target, createPPCMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -52,40 +52,32 @@ TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); } - -PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), +PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - - if (getRelocationModel() == Reloc::Default) { - if (Subtarget.isDarwin()) - setRelocationModel(Reloc::DynamicNoPIC); - else - setRelocationModel(Reloc::Static); - } } /// Override this for PowerPC. Tail merging happily breaks up instruction issue /// groups, which typically degrades performance. bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } -PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : PPCTargetMachine(T, TT, CPU, FS, false) { +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : PPCTargetMachine(T, TT, CPU, FS, RM, false) { } -PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : PPCTargetMachine(T, TT, CPU, FS, true) { +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : PPCTargetMachine(T, TT, CPU, FS, RM, true) { } @@ -110,19 +102,11 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. // FIXME: This should be moved to TargetJITInfo!! - if (Subtarget.isPPC64()) { - // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many - // instructions to materialize arbitrary global variable + function + - // constant pool addresses. - setRelocationModel(Reloc::PIC_); + if (Subtarget.isPPC64()) // Temporary workaround for the inability of PPC64 JIT to handle jump // tables. DisableJumpTables = true; - } else { - setRelocationModel(Reloc::Static); - } // Inform the subtarget that we are in JIT mode. FIXME: does this break macho // writing? Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -40,9 +40,9 @@ InstrItineraryData InstrItins; public: - PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64Bit); + PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit); virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCFrameLowering *getFrameLowering() const { @@ -77,16 +77,16 @@ /// class PPC32TargetMachine : public PPCTargetMachine { public: - PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; /// PPC64TargetMachine - PowerPC 64-bit target machine. /// class PPC64TargetMachine : public PPCTargetMachine { public: - PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -65,3 +65,17 @@ RegisterMCAsmInfo X(TheSparcTarget); RegisterMCAsmInfo Y(TheSparcV9Target); } + +MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeSparcMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, + createSparcMCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, + createSparcMCCodeGenInfo); +} + Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -24,10 +24,10 @@ /// SparcTargetMachine ctor - Create an ILP32 architecture model /// -SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS), +SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), @@ -51,15 +51,15 @@ } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, false) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, true) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, true) { } Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -33,9 +33,9 @@ SparcInstrInfo InstrInfo; SparcFrameLowering FrameLowering; public: - SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64bit); + SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64bit); virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { @@ -62,16 +62,16 @@ /// class SparcV8TargetMachine : public SparcTargetMachine { public: - SparcV8TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SparcV8TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; /// SparcV9TargetMachine - Sparc 64-bit target machine /// class SparcV9TargetMachine : public SparcTargetMachine { public: - SparcV9TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SparcV9TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -67,3 +67,16 @@ extern "C" void LLVMInitializeSystemZMCAsmInfo() { RegisterMCAsmInfo X(TheSystemZTarget); } + +MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + if (RM == Reloc::Default) + RM = Reloc::Static; + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeSystemZMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget, + createSystemZMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -21,18 +21,15 @@ /// SystemZTargetMachine ctor - Create an ILP64 architecture model /// SystemZTargetMachine::SystemZTargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { - - if (getRelocationModel() == Reloc::Default) - setRelocationModel(Reloc::Static); } bool SystemZTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -37,8 +37,8 @@ SystemZSelectionDAGInfo TSInfo; SystemZFrameLowering FrameLowering; public: - SystemZTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + SystemZTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -40,7 +40,6 @@ bool JITExceptionHandling; bool JITEmitDebugInfo; bool JITEmitDebugInfoToDisk; - Reloc::Model RelocationModel; CodeModel::Model CMModel; bool GuaranteedTailCallOpt; unsigned StackAlignmentOverride; @@ -143,21 +142,6 @@ cl::location(JITEmitDebugInfoToDisk), cl::init(false)); -static cl::opt -DefRelocationModel("relocation-model", - cl::desc("Choose relocation model"), - cl::location(RelocationModel), - cl::init(Reloc::Default), - cl::values( - clEnumValN(Reloc::Default, "default", - "Target default relocation model"), - clEnumValN(Reloc::Static, "static", - "Non-relocatable code"), - clEnumValN(Reloc::PIC_, "pic", - "Fully relocatable, position independent code"), - clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", - "Relocatable external references, non-relocatable code"), - clEnumValEnd)); static cl::opt DefCodeModel("code-model", cl::desc("Choose code model"), @@ -236,13 +220,10 @@ /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. -Reloc::Model TargetMachine::getRelocationModel() { - return RelocationModel; -} - -/// setRelocationModel - Sets the code generation relocation model. -void TargetMachine::setRelocationModel(Reloc::Model Model) { - RelocationModel = Model; +Reloc::Model TargetMachine::getRelocationModel() const { + if (!CodeGenInfo) + return Reloc::Default; + return CodeGenInfo->getRelocationModel(); } /// getCodeModel - Returns the code model. The choices are small, kernel, Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -338,3 +338,50 @@ RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); } + +MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + + Triple T(TT); + bool is64Bit = T.getArch() == Triple::x86_64; + + if (RM == Reloc::Default) { + // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. + // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we + // use static relocation model by default. + if (T.isOSDarwin()) { + if (is64Bit) + RM = Reloc::PIC_; + else + RM = Reloc::DynamicNoPIC; + } else if (T.isOSWindows() && is64Bit) + RM = Reloc::PIC_; + else + RM = Reloc::Static; + } + + // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC + // is defined as a model for code which may be used in static or dynamic + // executables but not necessarily a shared library. On X86-32 we just + // compile in -static mode, in x86-64 we use PIC. + if (RM == Reloc::DynamicNoPIC) { + if (is64Bit) + RM = Reloc::PIC_; + else if (!T.isOSDarwin()) + RM = Reloc::Static; + } + + // If we are on Darwin, disallow static relocation model in X86-64 mode, since + // the Mach-O file format doesn't support it. + if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) + RM = Reloc::PIC_; + + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeX86MCCodeGenInfo() { + // Register the target asm info. + RegisterMCCodeGenInfoFn A(TheX86_32Target, createX86MCCodeGenInfo); + RegisterMCCodeGenInfoFn B(TheX86_64Target, createX86MCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -65,10 +65,10 @@ } -X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : X86TargetMachine(T, TT, CPU, FS, false), +X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : X86TargetMachine(T, TT, CPU, FS, RM, false), DataLayout(getSubtargetImpl()->isTargetDarwin() ? "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" : (getSubtargetImpl()->isTargetCygMing() || @@ -82,10 +82,10 @@ } -X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : X86TargetMachine(T, TT, CPU, FS, true), +X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM) + : X86TargetMachine(T, TT, CPU, FS, RM, true), DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"), InstrInfo(*this), TSInfo(*this), @@ -95,52 +95,13 @@ /// X86TargetMachine ctor - Create an X86 target. /// -X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS), +X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { - DefRelocModel = getRelocationModel(); - - // If no relocation model was picked, default as appropriate for the target. - if (getRelocationModel() == Reloc::Default) { - // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. - // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we - // use static relocation model by default. - if (Subtarget.isTargetDarwin()) { - if (Subtarget.is64Bit()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::DynamicNoPIC); - } else if (Subtarget.isTargetWin64()) - setRelocationModel(Reloc::PIC_); - else - setRelocationModel(Reloc::Static); - } - - assert(getRelocationModel() != Reloc::Default && - "Relocation mode not picked"); - - // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC - // is defined as a model for code which may be used in static or dynamic - // executables but not necessarily a shared library. On X86-32 we just - // compile in -static mode, in x86-64 we use PIC. - if (getRelocationModel() == Reloc::DynamicNoPIC) { - if (is64Bit) - setRelocationModel(Reloc::PIC_); - else if (!Subtarget.isTargetDarwin()) - setRelocationModel(Reloc::Static); - } - - // If we are on Darwin, disallow static relocation model in X86-64 mode, since - // the Mach-O file format doesn't support it. - if (getRelocationModel() == Reloc::Static && - Subtarget.isTargetDarwin() && - is64Bit) - setRelocationModel(Reloc::PIC_); - // Determine the PICStyle based on the target selected. if (getRelocationModel() == Reloc::Static) { // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. @@ -161,10 +122,6 @@ Subtarget.setPICStyle(PICStyles::GOT); } - // Finally, if we have "none" as our PIC style, force to static mode. - if (Subtarget.getPICStyle() == PICStyles::None) - setRelocationModel(Reloc::Static); - // default to hard float ABI if (FloatABIType == FloatABI::Default) FloatABIType = FloatABI::Hard; @@ -210,15 +167,6 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) { - // FIXME: Move this to TargetJITInfo! - // On Darwin, do not override 64-bit setting made in X86TargetMachine(). - if (DefRelocModel == Reloc::Default && - (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) { - setRelocationModel(Reloc::Static); - Subtarget.setPICStyle(PICStyles::None); - } - - PM.add(createX86JITCodeEmitterPass(*this, JCE)); return false; Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Tue Jul 19 01:37:02 2011 @@ -29,12 +29,12 @@ namespace llvm { class formatted_raw_ostream; +class StringRef; class X86TargetMachine : public LLVMTargetMachine { X86Subtarget Subtarget; X86FrameLowering FrameLowering; X86ELFWriterInfo ELFWriterInfo; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. private: // We have specific defaults for X86. @@ -42,9 +42,9 @@ virtual void setCodeModelForStatic(); public: - X86TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS, - bool is64Bit); + X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64Bit); virtual const X86InstrInfo *getInstrInfo() const { llvm_unreachable("getInstrInfo not implemented"); @@ -87,8 +87,8 @@ X86TargetLowering TLInfo; X86JITInfo JITInfo; public: - X86_32TargetMachine(const Target &T, const std::string &M, - const std::string &CPU, const std::string &FS); + X86_32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; @@ -113,8 +113,8 @@ X86TargetLowering TLInfo; X86JITInfo JITInfo; public: - X86_64TargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + X86_64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Tue Jul 19 01:37:02 2011 @@ -75,3 +75,14 @@ extern "C" void LLVMInitializeXCoreMCAsmInfo() { RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); } + +MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM); + return X; +} + +extern "C" void LLVMInitializeXCoreMCCodeGenInfo() { + TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget, + createXCoreMCCodeGenInfo); +} Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Tue Jul 19 01:37:02 2011 @@ -19,10 +19,10 @@ /// XCoreTargetMachine ctor - Create an ILP32 architecture model /// -XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS) - : LLVMTargetMachine(T, TT, CPU, FS), +XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Tue Jul 19 01:37:02 2011 @@ -32,8 +32,8 @@ XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; public: - XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, const std::string &FS); + XCoreTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, Reloc::Model RM); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll Tue Jul 19 01:37:02 2011 @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it ; If-conversion defeats the purpose of this test, which is to check CBZ ; generation, so use memory barrier instruction to make sure it doesn't ; happen and we get actual branches. Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Tue Jul 19 01:37:02 2011 @@ -76,6 +76,21 @@ cl::desc("Target specific attributes (-mattr=help for details)"), cl::value_desc("a1,+a2,-a3,...")); +static cl::opt +RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); + static cl::opt RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, " @@ -202,6 +217,7 @@ // Initialize targets first, so that --version shows registered targets. InitializeAllTargets(); InitializeAllMCAsmInfos(); + InitializeAllMCCodeGenInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); @@ -272,7 +288,7 @@ std::auto_ptr target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, - FeaturesStr)); + FeaturesStr, RelocModel)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); Modified: llvm/trunk/tools/lli/lli.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/lli/lli.cpp (original) +++ llvm/trunk/tools/lli/lli.cpp Tue Jul 19 01:37:02 2011 @@ -108,6 +108,21 @@ NoLazyCompilation("disable-lazy-compilation", cl::desc("Disable JIT lazy compilation"), cl::init(false)); + + cl::opt + RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); } static ExecutionEngine *EE = 0; @@ -164,6 +179,7 @@ builder.setMArch(MArch); builder.setMCPU(MCPU); builder.setMAttrs(MAttrs); + builder.setRelocationModel(RelocModel); builder.setErrorStr(&ErrorMsg); builder.setEngineKind(ForceInterpreter ? EngineKind::Interpreter Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jul 19 01:37:02 2011 @@ -111,6 +111,21 @@ cl::value_desc("cpu-name"), cl::init("")); +static cl::opt +RelocModel("relocation-model", + cl::desc("Choose relocation model"), + cl::init(Reloc::Default), + cl::values( + clEnumValN(Reloc::Default, "default", + "Target default relocation model"), + clEnumValN(Reloc::Static, "static", + "Non-relocatable code"), + clEnumValN(Reloc::PIC_, "pic", + "Fully relocatable, position independent code"), + clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", + "Relocatable external references, non-relocatable code"), + clEnumValEnd)); + static cl::opt NoInitialTextSection("n", cl::desc("Don't assume assembly file starts " "in the text section")); @@ -321,7 +336,8 @@ // the .cpu and .code16 directives). OwningPtr TM(TheTarget->createTargetMachine(TripleName, MCPU, - FeaturesStr)); + FeaturesStr, + RelocModel)); if (!TM) { errs() << ProgName << ": error: could not create target for triple '" @@ -440,6 +456,7 @@ // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllMCInstrInfos(); llvm::InitializeAllMCRegisterInfos(); llvm::InitializeAllMCSubtargetInfos(); Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Jul 19 01:37:02 2011 @@ -270,6 +270,7 @@ // FIXME: We shouldn't need to initialize the Target(Machine)s. llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); + llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Tue Jul 19 01:37:02 2011 @@ -75,6 +75,7 @@ { InitializeAllTargets(); InitializeAllMCAsmInfos(); + InitializeAllMCCodeGenInfos(); InitializeAllMCRegisterInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmPrinters(); @@ -252,15 +253,16 @@ // The relocation model is actually a static member of TargetMachine // and needs to be set before the TargetMachine is instantiated. + Reloc::Model RelocModel = Reloc::Default; switch( _codeModel ) { case LTO_CODEGEN_PIC_MODEL_STATIC: - TargetMachine::setRelocationModel(Reloc::Static); + RelocModel = Reloc::Static; break; case LTO_CODEGEN_PIC_MODEL_DYNAMIC: - TargetMachine::setRelocationModel(Reloc::PIC_); + RelocModel = Reloc::PIC_; break; case LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC: - TargetMachine::setRelocationModel(Reloc::DynamicNoPIC); + RelocModel = Reloc::DynamicNoPIC; break; } @@ -268,7 +270,8 @@ SubtargetFeatures Features; Features.getDefaultSubtargetFeatures(llvm::Triple(Triple)); std::string FeatureStr = Features.getString(); - _target = march->createTargetMachine(Triple, _mCpu, FeatureStr); + _target = march->createTargetMachine(Triple, _mCpu, FeatureStr, + RelocModel); } return false; } Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=135468&r1=135467&r2=135468&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jul 19 01:37:02 2011 @@ -136,6 +136,7 @@ static bool Initialized = false; if (!Initialized) { InitializeAllTargets(); + InitializeAllMCCodeGenInfos(); InitializeAllMCAsmInfos(); InitializeAllMCSubtargetInfos(); InitializeAllAsmParsers(); From evan.cheng at apple.com Tue Jul 19 01:38:44 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 19 Jul 2011 06:38:44 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135470 - in /llvm-gcc-4.2/trunk/gcc: Makefile.in config/darwin.h config/linux.h config/netbsd-elf.h config/openbsd.h config/sol2.h llvm-backend.cpp Message-ID: <20110719063844.D9C982A6C12C@llvm.org> Author: evancheng Date: Tue Jul 19 01:38:44 2011 New Revision: 135470 URL: http://llvm.org/viewvc/llvm-project?rev=135470&view=rev Log: Match createTargetMachine API change. Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/config/linux.h llvm-gcc-4.2/trunk/gcc/config/netbsd-elf.h llvm-gcc-4.2/trunk/gcc/config/openbsd.h llvm-gcc-4.2/trunk/gcc/config/sol2.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Tue Jul 19 01:38:44 2011 @@ -1188,9 +1188,9 @@ ## and asm printers actually get linked into libllvmgcc.dylib. LLVMTARGETSYMBOLS := \ _LLVMInitializeARMTarget _LLVMInitializeARMAsmPrinter \ - _LLVMInitializeARMMCAsmInfo \ + _LLVMInitializeARMMCAsmInfo _LLVMInitializeARMMCRegisterInfo \ _LLVMInitializeX86Target _LLVMInitializeX86AsmPrinter \ - _LLVMInitializeX86MCAsmInfo \ + _LLVMInitializeX86MCAsmInfo _LLVMInitializeX86MCRegisterInfo \ endif Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Tue Jul 19 01:38:44 2011 @@ -1486,17 +1486,27 @@ /* Darwin X86-64 only supports PIC code generation. */ #if defined (TARGET_386) -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if ((TARGET_64BIT) || flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static") + RelocModel = Reloc::Static; #elif defined (TARGET_ARM) -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static"); \ + RelocModel = Reloc::Static; +#else /* !TARGET_386 && !TARGET_ARM */ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else if (!MACHO_DYNAMIC_NO_PIC_P) \ + RelocModel = Reloc::Static; +#endif /* !TARGET_386 && !TARGET_ARM */ + +#if defined (TARGET_ARM) +#define LLVM_SET_TARGET_OPTIONS(argvec) \ if (darwin_iphoneos_version_min) \ { \ const char *p = darwin_iphoneos_version_min; \ @@ -1507,13 +1517,7 @@ argvec.push_back("--arm-reserve-r9"); \ } \ } -#else /* !TARGET_386 && !TARGET_ARM */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static") -#endif /* !TARGET_386 && !TARGET_ARM */ +#endif /* TARGET_ARM */ #endif /* LLVM LOCAL end */ Modified: llvm-gcc-4.2/trunk/gcc/config/linux.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/linux.h?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/linux.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/linux.h Tue Jul 19 01:38:44 2011 @@ -130,11 +130,11 @@ #ifdef ENABLE_LLVM /* Yes, we're supporting PIC codegen for linux targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else \ - argvec.push_back ("--relocation-model=static"); + RelocModel = Reloc::Static; #endif /* LLVM LOCAL end */ Modified: llvm-gcc-4.2/trunk/gcc/config/netbsd-elf.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/netbsd-elf.h?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/netbsd-elf.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/netbsd-elf.h Tue Jul 19 01:38:44 2011 @@ -97,11 +97,11 @@ #ifdef ENABLE_LLVM /* Yes, we're supporting PIC codegen for NetBSD targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else \ - argvec.push_back ("--relocation-model=static"); + RelocModel = Reloc::Static; #endif /* LLVM LOCAL end */ Modified: llvm-gcc-4.2/trunk/gcc/config/openbsd.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/openbsd.h?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/openbsd.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/openbsd.h Tue Jul 19 01:38:44 2011 @@ -343,11 +343,11 @@ #ifdef ENABLE_LLVM /* Yes, we're supporting PIC codegen for OpenBSD targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else \ - argvec.push_back ("--relocation-model=static"); + RelocModel = Reloc::Static; #endif Modified: llvm-gcc-4.2/trunk/gcc/config/sol2.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/sol2.h?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/sol2.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/sol2.h Tue Jul 19 01:38:44 2011 @@ -248,10 +248,11 @@ #ifdef ENABLE_LLVM /* Supporting PIC codegen for solaris targets */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ + RelocModel = Reloc::PIC_; \ else \ - argvec.push_back ("--relocation-model=static"); + RelocModel = Reloc::Static; + #endif /* LLVM LOCAL end */ Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=135470&r1=135469&r2=135470&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jul 19 01:38:44 2011 @@ -35,6 +35,7 @@ #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLibraryInfo.h" @@ -381,6 +382,7 @@ Declare(LLVM_TARGET_NAME, TargetInfo); Declare(LLVM_TARGET_NAME, Target); Declare(LLVM_TARGET_NAME, MCAsmInfo); + Declare(LLVM_TARGET_NAME, MCRegisterInfo); Declare(LLVM_TARGET_NAME, AsmPrinter); #undef Declare #undef Declare2 @@ -406,10 +408,13 @@ DoInit(LLVM_TARGET_NAME, TargetInfo); DoInit(LLVM_TARGET_NAME, Target); DoInit(LLVM_TARGET_NAME, MCAsmInfo); + DoInit(LLVM_TARGET_NAME, MCRegisterInfo); DoInit(LLVM_TARGET_NAME, AsmPrinter); #undef DoInit #undef DoInit2 + Reloc::Model RelocModel = Reloc::Default; + // Initialize LLVM options. std::vector Args; Args.push_back(progname); // program name @@ -428,6 +433,9 @@ #ifdef LLVM_SET_IMPLICIT_FLOAT LLVM_SET_IMPLICIT_FLOAT(flag_no_implicit_float) #endif +#ifdef LLVM_SET_RELOC_MODEL + LLVM_SET_RELOC_MODEL(RelocModel); +#endif if (time_report) Args.push_back("--time-passes"); @@ -552,7 +560,8 @@ Features.AddFeature(MAttrs[i]); FeatureStr = Features.getString(); - TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr); + TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr, + RelocModel); TheTarget->setMCUseLoc(false); TheTarget->setMCUseCFI(false); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); From jay.foad at gmail.com Tue Jul 19 02:46:39 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 08:46:39 +0100 Subject: [llvm-commits] [llvm] r135453 - /llvm/trunk/docs/GettingStarted.html In-Reply-To: <20110719002054.671CC2A6C12C@llvm.org> References: <20110719002054.671CC2A6C12C@llvm.org> Message-ID: > Document how to maintain a git-svn clone of the LLVM git repositories. Thanks for writing this up, Jeffrey! Jay. From tobias at grosser.es Tue Jul 19 02:59:31 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 19 Jul 2011 09:59:31 +0200 Subject: [llvm-commits] [llvm] r135453 - /llvm/trunk/docs/GettingStarted.html In-Reply-To: <20110719002054.671CC2A6C12C@llvm.org> References: <20110719002054.671CC2A6C12C@llvm.org> Message-ID: <4E253963.9090905@grosser.es> On 07/19/2011 02:20 AM, Jeffrey Yasskin wrote: > Author: jyasskin > Date: Mon Jul 18 19:20:54 2011 > New Revision: 135453 > > URL: http://llvm.org/viewvc/llvm-project?rev=135453&view=rev > Log: > Document how to maintain a git-svn clone of the LLVM git repositories. Hi Jeffrey, thanks for your work. I was too slow to review it on time, but as you got a nice version in this was not needed. Just two comments: > +

To set up clone from which you can submit code using To set up A clone ... ^ -> You miss an 'A' here. And furthermore, the text before the section you added might also need an update: > GIT mirrors are available for a number of LLVM subprojects. A list of the available mirrors may be nice. I think chapuni already cloned all available mirrors https://github.com/chapuni, so we can figure out from there which are available. > These > mirrors sync automatically with each Subversion commit and contain > all necessary git-svn marks (so, you can recreate git-svn metadata > locally). Note that right now mirrors reflect only trunk for each > project. This is not true anymore. E.g. the LLVM git mirror has: $ git branch -a * master remotes/origin/master remotes/origin/release_1 remotes/origin/release_16 remotes/origin/release_20 remotes/origin/release_21 remotes/origin/release_22 remotes/origin/release_23 remotes/origin/release_24 remotes/origin/release_25 remotes/origin/release_26 remotes/origin/release_27 remotes/origin/release_28 remotes/origin/release_29 remotes/origin/svn-tags/RELEASE_1 remotes/origin/svn-tags/RELEASE_20 remotes/origin/svn-tags/RELEASE_21 remotes/origin/svn-tags/RELEASE_22 remotes/origin/svn-tags/RELEASE_23 remotes/origin/svn-tags/RELEASE_24 remotes/origin/svn-tags/RELEASE_25 remotes/origin/svn-tags/RELEASE_26 remotes/origin/svn-tags/RELEASE_27 remotes/origin/svn-tags/RELEASE_28 remotes/origin/svn-tags/RELEASE_29 Cheers and thanks again for this nice work! Tobi From nicholas at mxc.ca Tue Jul 19 03:22:57 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 19 Jul 2011 08:22:57 -0000 Subject: [llvm-commits] [llvm] r135471 - /llvm/trunk/test/Transforms/InstSimplify/compare.ll Message-ID: <20110719082257.D4D482A6C12D@llvm.org> Author: nicholas Date: Tue Jul 19 03:22:57 2011 New Revision: 135471 URL: http://llvm.org/viewvc/llvm-project?rev=135471&view=rev Log: Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed to perform a signed wrap. Don't rely on any particular handling of that case. Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=135471&r1=135470&r2=135471&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original) +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Jul 19 03:22:57 2011 @@ -283,17 +283,6 @@ ret i1 %E } -; CHECK: @srem4 -; CHECK-NEXT: ret i1 false -define i1 @srem4(i16 %X, i32 %Y) { - %A = zext i16 %X to i32 - %B = or i32 2147483648, %A - %C = sub nsw i32 %A, %B - %D = srem i32 %C, %Y - %E = icmp slt i32 %D, 0 - ret i1 %E -} - define i1 @udiv1(i32 %X) { ; CHECK: @udiv1 %A = udiv i32 %X, 1000000 From jay.foad at gmail.com Tue Jul 19 03:43:11 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 08:43:11 -0000 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110719084312.0801E2A6C12C@llvm.org> Author: foad Date: Tue Jul 19 03:43:11 2011 New Revision: 135472 URL: http://llvm.org/viewvc/llvm-project?rev=135472&view=rev Log: Update for change in Intrinsic::getDeclaration API. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=135472&r1=135471&r2=135472&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue Jul 19 03:43:11 2011 @@ -426,7 +426,7 @@ Type *ArgTypes[3] = {SBP, SBP, IntPtr }; Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memcpy, - ArgTypes, 3), Ops); + ArgTypes), Ops); AI->setName(NameStack.back()); } @@ -1671,7 +1671,7 @@ Type *ArgTypes[3] = { SBP, SBP, IntPtr }; Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memcpy, - ArgTypes, 3), Ops); + ArgTypes), Ops); return Ops[0]; } @@ -1689,7 +1689,7 @@ Type *ArgTypes[3] = { SBP, SBP, IntPtr }; Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memmove, - ArgTypes, 3), Ops); + ArgTypes), Ops); return Ops[0]; } @@ -1707,7 +1707,7 @@ Type *ArgTypes[2] = { SBP, IntPtr }; Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memset, - ArgTypes, 2), Ops); + ArgTypes), Ops); return Ops[0]; } @@ -3739,9 +3739,7 @@ #endif Value *Result = - Builder.CreateCall(Intrinsic::getDeclaration(TheModule, id, - Ty, 2), - C); + Builder.CreateCall(Intrinsic::getDeclaration(TheModule, id, Ty), C); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -3787,7 +3785,7 @@ Value *Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_cmp_swap, - Ty, 2), Ops); + Ty), Ops); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -3949,8 +3947,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::objectsize, - &Ty, - 1), + Ty), Args); return true; } @@ -4349,7 +4346,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_add, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4397,7 +4394,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_sub, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4445,7 +4442,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_or, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4493,7 +4490,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_and, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4541,7 +4538,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_xor, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4589,7 +4586,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::atomic_load_nand, - Ty, 2), + Ty), C); // The gcc builtins are also full memory barriers. @@ -4694,7 +4691,7 @@ // by passing it as the 3rd and 4th parameters. This isn't needed for // most intrinsics, but is needed for ctpop, cttz, ctlz. Type *Ty = InVal->getType(); - Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, &Ty, 1), + Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, Ty), InVal); return true; } @@ -4704,7 +4701,7 @@ Type* Ty = Amt->getType(); return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, - Intrinsic::sqrt, &Ty, 1), + Intrinsic::sqrt, Ty), Amt); } @@ -4721,7 +4718,7 @@ Args.push_back(Val); Args.push_back(Pow); return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, - Intrinsic::powi, &Ty, 1), + Intrinsic::powi, Ty), Args); } @@ -4737,7 +4734,7 @@ Args.push_back(Val); Args.push_back(Pow); return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, - Intrinsic::pow, &Ty, 1), + Intrinsic::pow, Ty), Args); } @@ -5553,7 +5550,7 @@ Function *Fn = Intrinsic::getDeclaration(TheModule, Intrinsic::ptr_annotation, - &SBP, 1); + SBP); // Get file and line number. FIXME: Should this be for the decl or the // use. Is there a location info for the use? From geek4civic at gmail.com Tue Jul 19 04:54:15 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 19 Jul 2011 18:54:15 +0900 Subject: [llvm-commits] [llvm] r135453 - /llvm/trunk/docs/GettingStarted.html In-Reply-To: <4E253963.9090905@grosser.es> References: <20110719002054.671CC2A6C12C@llvm.org> <4E253963.9090905@grosser.es> Message-ID: Tobi, 2011/7/19 Tobias Grosser : >> GIT mirrors are available for a number of LLVM subprojects. > > A list of the available mirrors may be nice. I think chapuni already > cloned all available mirrors https://github.com/chapuni, so we can figure > out from there which are available. I don't know all git repos. I guess only Anton might know. At first, I had cloned them for my branches, but now, I am cloning them for the repo "llvm-project". >> These >> mirrors sync automatically with each Subversion commit and contain >> all necessary git-svn marks (so, you can recreate git-svn metadata >> locally). Note that right now mirrors reflect only trunk for each >> project. > > This is not true anymore. E.g. the LLVM git mirror has: (snip) > ? remotes/origin/svn-tags/RELEASE_29 llvm.org/svn-tags/RELEASE_XX(s) don't point useful commits. Each of them is orphan against master(trunk). It seems release branches would be fine. ...Takumi From tobias at grosser.es Tue Jul 19 04:56:34 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 19 Jul 2011 11:56:34 +0200 Subject: [llvm-commits] [llvm] r135453 - /llvm/trunk/docs/GettingStarted.html In-Reply-To: References: <20110719002054.671CC2A6C12C@llvm.org> <4E253963.9090905@grosser.es> Message-ID: <4E2554D2.6020300@grosser.es> On 07/19/2011 11:54 AM, NAKAMURA Takumi wrote: > Tobi, > > 2011/7/19 Tobias Grosser: >>> GIT mirrors are available for a number of LLVM subprojects. >> >> A list of the available mirrors may be nice. I think chapuni already >> cloned all available mirrors https://github.com/chapuni, so we can figure >> out from there which are available. > > I don't know all git repos. I guess only Anton might know. > At first, I had cloned them for my branches, but now, I am cloning > them for the repo "llvm-project". Anton will know. However, I think you already got the most important projects. We can just add these and add more projects as soon as we are aware of them. (Or Anton can add the missing ones, after the text is changed). >>> These >>> mirrors sync automatically with each Subversion commit and contain >>> all necessary git-svn marks (so, you can recreate git-svn metadata >>> locally). Note that right now mirrors reflect only trunk for each >>> project. >> >> This is not true anymore. E.g. the LLVM git mirror has: > (snip) >> remotes/origin/svn-tags/RELEASE_29 > > llvm.org/svn-tags/RELEASE_XX(s) don't point useful commits. Each of > them is orphan against master(trunk). This seems to be a bug. If they are wrong we either should fix them or they should be removed from the git repositories. Cheers Tobi From tobias at grosser.es Tue Jul 19 05:53:31 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 19 Jul 2011 12:53:31 +0200 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp In-Reply-To: <20110719084312.0801E2A6C12C@llvm.org> References: <20110719084312.0801E2A6C12C@llvm.org> Message-ID: <4E25622B.7020407@grosser.es> On 07/19/2011 10:43 AM, Jay Foad wrote: > Author: foad > Date: Tue Jul 19 03:43:11 2011 > New Revision: 135472 > > URL: http://llvm.org/viewvc/llvm-project?rev=135472&view=rev > Log: > Update for change in Intrinsic::getDeclaration API. > > Modified: > dragonegg/trunk/src/Convert.cpp > // The gcc builtins are also full memory barriers. > @@ -4694,7 +4691,7 @@ > // by passing it as the 3rd and 4th parameters. This isn't needed for > // most intrinsics, but is needed for ctpop, cttz, ctlz. > Type *Ty = InVal->getType(); > - Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id,&Ty, 1), > + Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, Ty), > InVal); > return true; > } > @@ -4704,7 +4701,7 @@ > Type* Ty = Amt->getType(); > > return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, > - Intrinsic::sqrt,&Ty, 1), > + Intrinsic::sqrt, Ty), > Amt); > } > > @@ -4721,7 +4718,7 @@ > Args.push_back(Val); > Args.push_back(Pow); > return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, > - Intrinsic::powi,&Ty, 1), > + Intrinsic::powi, Ty), > Args); > } > > @@ -4737,7 +4734,7 @@ > Args.push_back(Val); > Args.push_back(Pow); > return Builder.CreateCall(Intrinsic::getDeclaration(TheModule, > - Intrinsic::pow,&Ty, 1), > + Intrinsic::pow, Ty), > Args); > } > > @@ -5553,7 +5550,7 @@ > > Function *Fn = Intrinsic::getDeclaration(TheModule, > Intrinsic::ptr_annotation, > -&SBP, 1); > + SBP); Did you compile test these changes? I had the to use the following to make the calls with a single element work: - Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, &Ty, 1), + Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, + makeArrayRef(&Ty, 1)), Cheers Tobi From jay.foad at gmail.com Tue Jul 19 06:29:13 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 12:29:13 +0100 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp In-Reply-To: <4E25622B.7020407@grosser.es> References: <20110719084312.0801E2A6C12C@llvm.org> <4E25622B.7020407@grosser.es> Message-ID: > Did you compile test these changes? Yes. I got no errors in Convert.cpp, compiling with GCC 4.5.2 on Ubuntu Natty x86_64. > I had the to use the following to make > the calls with a single element work: > > - ?Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, &Ty, > 1), > + ?Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, > + makeArrayRef(&Ty, 1)), That's ugly. Why doesn't the implicit conversion from Type * to ArrayRef work? Jay. From tobias at grosser.es Tue Jul 19 07:19:37 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 19 Jul 2011 14:19:37 +0200 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp In-Reply-To: References: <20110719084312.0801E2A6C12C@llvm.org> <4E25622B.7020407@grosser.es> Message-ID: <4E257659.9080601@grosser.es> On 07/19/2011 01:29 PM, Jay Foad wrote: >> Did you compile test these changes? > > Yes. I got no errors in Convert.cpp, compiling with GCC 4.5.2 on > Ubuntu Natty x86_64. I have the same. >> I had the to use the following to make >> the calls with a single element work: >> >> - Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id,&Ty, >> 1), >> + Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, >> + makeArrayRef(&Ty, 1)), > > That's ugly. Why doesn't the implicit conversion from Type * to > ArrayRef work? OK. It seems I got it wrong. I used Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, &Ty) whereas you used Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, Ty) ^^ This makes the difference. Your code compiles for me without any problems. Tobi From jay.foad at gmail.com Tue Jul 19 07:25:48 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 13:25:48 +0100 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp In-Reply-To: <4E257659.9080601@grosser.es> References: <20110719084312.0801E2A6C12C@llvm.org> <4E25622B.7020407@grosser.es> <4E257659.9080601@grosser.es> Message-ID: > Your code compiles for me without any problems. Excellent! Jay. From richard at xmos.com Tue Jul 19 07:50:25 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 19 Jul 2011 12:50:25 -0000 Subject: [llvm-commits] [llvm] r135474 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/resources.ll Message-ID: <20110719125025.48BD82A6C12C@llvm.org> Author: friedgold Date: Tue Jul 19 07:50:25 2011 New Revision: 135474 URL: http://llvm.org/viewvc/llvm-project?rev=135474&view=rev Log: Add intrinsics for the peek and endin instructions. Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td llvm/trunk/test/CodeGen/XCore/resources.ll Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=135474&r1=135473&r2=135474&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue Jul 19 07:50:25 2011 @@ -65,6 +65,10 @@ [NoCapture<0>, NoCapture<1>]>; def int_xcore_setpsc : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], [NoCapture<0>]>; + def int_xcore_peek : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_endin : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; // Intrinsics for events. def int_xcore_waitevent : Intrinsic<[llvm_ptr_ty],[], [IntrReadMem]>; Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=135474&r1=135473&r2=135474&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Jul 19 07:50:25 2011 @@ -871,7 +871,6 @@ [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; // Two operand long -// TODO endin, peek, // getd, testlcl def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), "bitrev $dst, $src", @@ -917,6 +916,14 @@ "setpsc res[$src1], $src2", [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; +def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), + "peek $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; + +def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), + "endin $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; + // One operand short // TODO edu, eeu, waitet, waitef, tstart, clrtp // setdp, setcp, setev, kcall Modified: llvm/trunk/test/CodeGen/XCore/resources.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/resources.ll?rev=135474&r1=135473&r2=135474&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/resources.ll (original) +++ llvm/trunk/test/CodeGen/XCore/resources.ll Tue Jul 19 07:50:25 2011 @@ -22,6 +22,8 @@ declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) declare void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r) +declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r) define i8 addrspace(1)* @getr() { ; CHECK: getr: @@ -198,3 +200,17 @@ call void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } + +define i32 @peek(i8 addrspace(1)* %r) { +; CHECK: peek: +; CHECK: peek r0, res[r0] + %result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define i32 @endin(i8 addrspace(1)* %r) { +; CHECK: endin: +; CHECK: endin r0, res[r0] + %result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} From richard at xmos.com Tue Jul 19 08:00:40 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 19 Jul 2011 13:00:40 -0000 Subject: [llvm-commits] [llvm] r135475 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/resources.ll Message-ID: <20110719130040.D0AD22A6C12E@llvm.org> Author: friedgold Date: Tue Jul 19 08:00:40 2011 New Revision: 135475 URL: http://llvm.org/viewvc/llvm-project?rev=135475&view=rev Log: Add intrinsics for the testct, testwct instructions. Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td llvm/trunk/test/CodeGen/XCore/resources.ll Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=135475&r1=135474&r2=135475&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue Jul 19 08:00:40 2011 @@ -40,6 +40,10 @@ [NoCapture<0>]>; def int_xcore_chkct : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], [NoCapture<0>]>; + def int_xcore_testct : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_testwct : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; def int_xcore_setd : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], [NoCapture<0>]>; def int_xcore_setc : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=135475&r1=135474&r2=135475&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Jul 19 08:00:40 2011 @@ -754,7 +754,7 @@ } // Two operand short -// TODO eet, eef, testwct, tsetmr, sext (reg), zext (reg) +// TODO eet, eef, tsetmr, sext (reg), zext (reg) def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; @@ -846,6 +846,14 @@ "chkct res[$r], $val", [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; +def TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), + "testct $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; + +def TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), + "testwct $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; + def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), "setd res[$r], $val", [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; Modified: llvm/trunk/test/CodeGen/XCore/resources.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/resources.ll?rev=135475&r1=135474&r2=135475&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/resources.ll (original) +++ llvm/trunk/test/CodeGen/XCore/resources.ll Tue Jul 19 08:00:40 2011 @@ -9,6 +9,8 @@ declare void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r) +declare i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value) declare i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) @@ -214,3 +216,17 @@ %result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r) ret i32 %result } + +define i32 @testct(i8 addrspace(1)* %r) { +; CHECK: testct: +; CHECK: testct r0, res[r0] + %result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define i32 @testwct(i8 addrspace(1)* %r) { +; CHECK: testwct: +; CHECK: testwct r0, res[r0] + %result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} From richard at xmos.com Tue Jul 19 08:28:50 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 19 Jul 2011 13:28:50 -0000 Subject: [llvm-commits] [llvm] r135476 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/misc-intrinsics.ll Message-ID: <20110719132850.E97CB2A6C12D@llvm.org> Author: friedgold Date: Tue Jul 19 08:28:50 2011 New Revision: 135476 URL: http://llvm.org/viewvc/llvm-project?rev=135476&view=rev Log: Add intrinsics for the zext / sext instructions. Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=135476&r1=135475&r2=135476&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue Jul 19 08:28:50 2011 @@ -17,6 +17,10 @@ def int_xcore_crc32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], [IntrNoMem]>; + def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; + def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=135476&r1=135475&r2=135476&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Jul 19 08:28:50 2011 @@ -754,7 +754,7 @@ } // Two operand short -// TODO eet, eef, tsetmr, sext (reg), zext (reg) +// TODO eet, eef, tsetmr def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; @@ -764,15 +764,21 @@ [(set GRRegs:$dst, (ineg GRRegs:$b))]>; let Constraints = "$src1 = $dst" in { -let neverHasSideEffects = 1 in def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "sext $dst, $src2", - []>; + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>; + +def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; -let neverHasSideEffects = 1 in def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "zext $dst, $src2", - []>; + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>; + +def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "andnot $dst, $src2", Modified: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll?rev=135476&r1=135475&r2=135476&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll (original) +++ llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Tue Jul 19 08:28:50 2011 @@ -4,6 +4,8 @@ declare i32 @llvm.xcore.bitrev(i32) declare i32 @llvm.xcore.crc32(i32, i32, i32) declare %0 @llvm.xcore.crc8(i32, i32, i32) +declare i32 @llvm.xcore.zext(i32, i32) +declare i32 @llvm.xcore.sext(i32, i32) define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -25,3 +27,31 @@ %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) ret %0 %result } + +define i32 @zext(i32 %a, i32 %b) { +; CHECK: zext: +; CHECK: zext r0, r1 + %result = call i32 @llvm.xcore.zext(i32 %a, i32 %b) + ret i32 %result +} + +define i32 @zexti(i32 %a) { +; CHECK: zexti: +; CHECK: zext r0, 4 + %result = call i32 @llvm.xcore.zext(i32 %a, i32 4) + ret i32 %result +} + +define i32 @sext(i32 %a, i32 %b) { +; CHECK: sext: +; CHECK: sext r0, r1 + %result = call i32 @llvm.xcore.sext(i32 %a, i32 %b) + ret i32 %result +} + +define i32 @sexti(i32 %a) { +; CHECK: sexti: +; CHECK: sext r0, 4 + %result = call i32 @llvm.xcore.sext(i32 %a, i32 4) + ret i32 %result +} From jay.foad at gmail.com Tue Jul 19 08:32:40 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 13:32:40 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135477 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20110719133240.A684D2A6C12D@llvm.org> Author: foad Date: Tue Jul 19 08:32:40 2011 New Revision: 135477 URL: http://llvm.org/viewvc/llvm-project?rev=135477&view=rev Log: Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jul 19 08:32:40 2011 @@ -8901,7 +8901,7 @@ FieldPtr = TheFolder->CreateGetElementPtr(StructAddrLV, Ops+1, 2); FieldPtr = ConstantFoldInstOperands(Instruction::GetElementPtr, - FieldPtr->getType(), Ops, 3, &TD); + FieldPtr->getType(), Ops, &TD); // Now that we did an offset from the start of the struct, subtract off // the offset from BitStart. From jay.foad at gmail.com Tue Jul 19 08:32:40 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 13:32:40 -0000 Subject: [llvm-commits] [llvm] r135477 - in /llvm/trunk: docs/ReleaseNotes.html include/llvm/Analysis/ConstantFolding.h lib/Analysis/ConstantFolding.cpp lib/Analysis/InstructionSimplify.cpp lib/Analysis/ScalarEvolution.cpp lib/Transforms/IPO/GlobalOpt.cpp lib/Transforms/InstCombine/InstCombineSelect.cpp lib/Transforms/Scalar/SCCP.cpp lib/Transforms/Utils/CloneFunction.cpp Message-ID: <20110719133240.D7F542A6C12E@llvm.org> Author: foad Date: Tue Jul 19 08:32:40 2011 New Revision: 135477 URL: http://llvm.org/viewvc/llvm-project?rev=135477&view=rev Log: Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/Analysis/ConstantFolding.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp llvm/trunk/lib/Transforms/Scalar/SCCP.cpp llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Jul 19 08:32:40 2011 @@ -626,6 +626,8 @@

  • ConstantExpr::getIndices
  • ConstantExpr::getInsertElement
  • ConstantExpr::getWithOperands
    • +
  • ConstantFoldCall (in llvm/Analysis/ConstantFolding.h)
    • +
  • ConstantFoldInstOperands (in llvm/Analysis/ConstantFolding.h)
  • ConstantVector::get
  • DIBuilder::createComplexVariable
  • DIBuilder::getOrCreateArray
    • Modified: llvm/trunk/include/llvm/Analysis/ConstantFolding.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ConstantFolding.h?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ConstantFolding.h (original) +++ llvm/trunk/include/llvm/Analysis/ConstantFolding.h Tue Jul 19 08:32:40 2011 @@ -27,6 +27,8 @@ class TargetData; class Function; class Type; + template + class ArrayRef; /// ConstantFoldInstruction - Try to constant fold the specified instruction. /// If successful, the constant result is returned, if not, null is returned. @@ -48,7 +50,7 @@ /// form. /// Constant *ConstantFoldInstOperands(unsigned Opcode, Type *DestTy, - Constant *const *Ops, unsigned NumOps, + ArrayRef Ops, const TargetData *TD = 0); /// ConstantFoldCompareInstOperands - Attempt to constant fold a compare @@ -76,7 +78,7 @@ /// ConstantFoldCall - Attempt to constant fold a call to the specified function /// with the specified arguments, returning null if unsuccessful. Constant * -ConstantFoldCall(Function *F, Constant *const *Operands, unsigned NumOperands); +ConstantFoldCall(Function *F, ArrayRef Operands); } #endif Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jul 19 08:32:40 2011 @@ -536,7 +536,7 @@ /// CastGEPIndices - If array indices are not pointer-sized integers, /// explicitly cast them so that they aren't implicitly casted by the /// getelementptr. -static Constant *CastGEPIndices(Constant *const *Ops, unsigned NumOps, +static Constant *CastGEPIndices(ArrayRef Ops, Type *ResultTy, const TargetData *TD) { if (!TD) return 0; @@ -544,10 +544,10 @@ bool Any = false; SmallVector NewIdxs; - for (unsigned i = 1; i != NumOps; ++i) { + for (unsigned i = 1, e = Ops.size(); i != e; ++i) { if ((i == 1 || !isa(GetElementPtrInst::getIndexedType(Ops[0]->getType(), - reinterpret_cast(Ops+1), + Ops.data() + 1, i-1))) && Ops[i]->getType() != IntPtrTy) { Any = true; @@ -571,7 +571,7 @@ /// SymbolicallyEvaluateGEP - If we can symbolically evaluate the specified GEP /// constant expression, do so. -static Constant *SymbolicallyEvaluateGEP(Constant *const *Ops, unsigned NumOps, +static Constant *SymbolicallyEvaluateGEP(ArrayRef Ops, Type *ResultTy, const TargetData *TD) { Constant *Ptr = Ops[0]; @@ -582,12 +582,12 @@ // If this is a constant expr gep that is effectively computing an // "offsetof", fold it into 'cast int Size to T*' instead of 'gep 0, 0, 12' - for (unsigned i = 1; i != NumOps; ++i) + for (unsigned i = 1, e = Ops.size(); i != e; ++i) if (!isa(Ops[i])) { // If this is "gep i8* Ptr, (sub 0, V)", fold this as: // "inttoptr (sub (ptrtoint Ptr), V)" - if (NumOps == 2 && + if (Ops.size() == 2 && cast(ResultTy)->getElementType()->isIntegerTy(8)) { ConstantExpr *CE = dyn_cast(Ops[1]); assert((CE == 0 || CE->getType() == IntPtrTy) && @@ -608,7 +608,8 @@ unsigned BitWidth = TD->getTypeSizeInBits(IntPtrTy); APInt Offset = APInt(BitWidth, TD->getIndexedOffset(Ptr->getType(), - (Value**)Ops+1, NumOps-1)); + (Value**)Ops.data() + 1, + Ops.size() - 1)); Ptr = cast(Ptr->stripPointerCasts()); // If this is a GEP of a GEP, fold it all into a single GEP. @@ -778,8 +779,7 @@ cast(EVI->getAggregateOperand()), EVI->getIndices()); - return ConstantFoldInstOperands(I->getOpcode(), I->getType(), - Ops.data(), Ops.size(), TD); + return ConstantFoldInstOperands(I->getOpcode(), I->getType(), Ops, TD); } /// ConstantFoldConstantExpression - Attempt to fold the constant expression @@ -800,8 +800,7 @@ if (CE->isCompare()) return ConstantFoldCompareInstOperands(CE->getPredicate(), Ops[0], Ops[1], TD); - return ConstantFoldInstOperands(CE->getOpcode(), CE->getType(), - Ops.data(), Ops.size(), TD); + return ConstantFoldInstOperands(CE->getOpcode(), CE->getType(), Ops, TD); } /// ConstantFoldInstOperands - Attempt to constant fold an instruction with the @@ -815,7 +814,7 @@ /// folding using this function strips this information. /// Constant *llvm::ConstantFoldInstOperands(unsigned Opcode, Type *DestTy, - Constant* const* Ops, unsigned NumOps, + ArrayRef Ops, const TargetData *TD) { // Handle easy binops first. if (Instruction::isBinaryOp(Opcode)) { @@ -831,9 +830,9 @@ case Instruction::ICmp: case Instruction::FCmp: assert(0 && "Invalid for compares"); case Instruction::Call: - if (Function *F = dyn_cast(Ops[NumOps - 1])) + if (Function *F = dyn_cast(Ops.back())) if (canConstantFoldCallTo(F)) - return ConstantFoldCall(F, Ops, NumOps - 1); + return ConstantFoldCall(F, Ops.slice(0, Ops.size() - 1)); return 0; case Instruction::PtrToInt: // If the input is a inttoptr, eliminate the pair. This requires knowing @@ -887,12 +886,13 @@ case Instruction::ShuffleVector: return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]); case Instruction::GetElementPtr: - if (Constant *C = CastGEPIndices(Ops, NumOps, DestTy, TD)) + if (Constant *C = CastGEPIndices(Ops, DestTy, TD)) return C; - if (Constant *C = SymbolicallyEvaluateGEP(Ops, NumOps, DestTy, TD)) + if (Constant *C = SymbolicallyEvaluateGEP(Ops, DestTy, TD)) return C; - return ConstantExpr::getGetElementPtr(Ops[0], Ops+1, NumOps-1); + return ConstantExpr::getGetElementPtr(Ops[0], Ops.data() + 1, + Ops.size() - 1); } } @@ -967,7 +967,7 @@ unsigned OpC = Predicate == ICmpInst::ICMP_EQ ? Instruction::And : Instruction::Or; Constant *Ops[] = { LHS, RHS }; - return ConstantFoldInstOperands(OpC, LHS->getType(), Ops, 2, TD); + return ConstantFoldInstOperands(OpC, LHS->getType(), Ops, TD); } } @@ -1167,13 +1167,12 @@ /// ConstantFoldCall - Attempt to constant fold a call to the specified function /// with the specified arguments, returning null if unsuccessful. Constant * -llvm::ConstantFoldCall(Function *F, - Constant *const *Operands, unsigned NumOperands) { +llvm::ConstantFoldCall(Function *F, ArrayRef Operands) { if (!F->hasName()) return 0; StringRef Name = F->getName(); Type *Ty = F->getReturnType(); - if (NumOperands == 1) { + if (Operands.size() == 1) { if (ConstantFP *Op = dyn_cast(Operands[0])) { if (F->getIntrinsicID() == Intrinsic::convert_to_fp16) { APFloat Val(Op->getValueAPF()); @@ -1327,7 +1326,7 @@ return 0; } - if (NumOperands == 2) { + if (Operands.size() == 2) { if (ConstantFP *Op1 = dyn_cast(Operands[0])) { if (!Ty->isFloatTy() && !Ty->isDoubleTy()) return 0; Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Jul 19 08:32:40 2011 @@ -526,7 +526,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::Add, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // Canonicalize the constant to the RHS. @@ -595,7 +595,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::Sub, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // X - undef -> undef @@ -715,7 +715,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::Mul, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // Canonicalize the constant to the RHS. @@ -788,7 +788,7 @@ if (Constant *C0 = dyn_cast(Op0)) { if (Constant *C1 = dyn_cast(Op1)) { Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, 2, TD); + return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, TD); } } @@ -909,7 +909,7 @@ if (Constant *C0 = dyn_cast(Op0)) { if (Constant *C1 = dyn_cast(Op1)) { Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, 2, TD); + return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, TD); } } @@ -1012,7 +1012,7 @@ if (Constant *C0 = dyn_cast(Op0)) { if (Constant *C1 = dyn_cast(Op1)) { Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, 2, TD); + return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, TD); } } @@ -1138,7 +1138,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::And, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // Canonicalize the constant to the RHS. @@ -1227,7 +1227,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::Or, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // Canonicalize the constant to the RHS. @@ -1321,7 +1321,7 @@ if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; return ConstantFoldInstOperands(Instruction::Xor, CLHS->getType(), - Ops, 2, TD); + Ops, TD); } // Canonicalize the constant to the RHS. @@ -2328,7 +2328,7 @@ if (Constant *CLHS = dyn_cast(LHS)) if (Constant *CRHS = dyn_cast(RHS)) { Constant *COps[] = {CLHS, CRHS}; - return ConstantFoldInstOperands(Opcode, LHS->getType(), COps, 2, TD); + return ConstantFoldInstOperands(Opcode, LHS->getType(), COps, TD); } // If the operation is associative, try some generic simplifications. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jul 19 08:32:40 2011 @@ -4492,8 +4492,7 @@ if (const CmpInst *CI = dyn_cast(I)) return ConstantFoldCompareInstOperands(CI->getPredicate(), Operands[0], Operands[1], TD); - return ConstantFoldInstOperands(I->getOpcode(), I->getType(), - &Operands[0], Operands.size(), TD); + return ConstantFoldInstOperands(I->getOpcode(), I->getType(), Operands, TD); } /// getConstantEvolutionLoopExitValue - If we know that the specified Phi is @@ -4703,7 +4702,7 @@ Operands[0], Operands[1], TD); else C = ConstantFoldInstOperands(I->getOpcode(), I->getType(), - &Operands[0], Operands.size(), TD); + Operands, TD); if (!C) return V; return getSCEV(C); } Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Tue Jul 19 08:32:40 2011 @@ -2465,8 +2465,7 @@ if (Callee->isDeclaration()) { // If this is a function we can constant fold, do it. - if (Constant *C = ConstantFoldCall(Callee, Formals.data(), - Formals.size())) { + if (Constant *C = ConstantFoldCall(Callee, Formals)) { InstResult = C; } else { return false; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Tue Jul 19 08:32:40 2011 @@ -325,7 +325,7 @@ // All operands were constants, fold it. if (ConstOps.size() == I->getNumOperands()) return ConstantFoldInstOperands(I->getOpcode(), I->getType(), - ConstOps.data(), ConstOps.size(), TD); + ConstOps, TD); } return 0; Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Tue Jul 19 08:32:40 2011 @@ -1278,7 +1278,7 @@ // If we can constant fold this, mark the result of the call as a // constant. - if (Constant *C = ConstantFoldCall(F, Operands.data(), Operands.size())) + if (Constant *C = ConstantFoldCall(F, Operands)) return markConstant(I, C); } Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=135477&r1=135476&r2=135477&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Tue Jul 19 08:32:40 2011 @@ -338,8 +338,7 @@ return ConstantFoldLoadThroughGEPConstantExpr(GV->getInitializer(), CE); - return ConstantFoldInstOperands(I->getOpcode(), I->getType(), &Ops[0], - Ops.size(), TD); + return ConstantFoldInstOperands(I->getOpcode(), I->getType(), Ops, TD); } /// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto, From jay.foad at gmail.com Tue Jul 19 09:01:37 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 14:01:37 -0000 Subject: [llvm-commits] [llvm] r135478 - in /llvm/trunk: docs/ReleaseNotes.html include/llvm/Target/TargetData.h lib/Analysis/ConstantFolding.cpp lib/Analysis/Loads.cpp lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/ELFWriter.cpp lib/ExecutionEngine/ExecutionEngine.cpp lib/Target/TargetData.cpp lib/Transforms/IPO/MergeFunctions.cpp lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110719140137.90EFB2A6C12D@llvm.org> Author: foad Date: Tue Jul 19 09:01:37 2011 New Revision: 135478 URL: http://llvm.org/viewvc/llvm-project?rev=135478&view=rev Log: Convert TargetData::getIndexedOffset to use ArrayRef. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Analysis/Loads.cpp llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp llvm/trunk/lib/Target/TargetData.cpp llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Jul 19 09:01:37 2011 @@ -646,6 +646,7 @@
  • MDNode::getIfExists
  • MDNode::getTemporary
  • MDNode::getWhenValsUnresolved
    • +
  • TargetData::getIndexedOffset
  • All forms of StringMap::getOrCreateValue have been remove Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Tue Jul 19 09:01:37 2011 @@ -33,6 +33,8 @@ class StructLayout; class GlobalVariable; class LLVMContext; +template +class ArrayRef; /// Enum used to categorize the alignment types stored by TargetAlignElem enum AlignTypeEnum { @@ -264,8 +266,7 @@ /// getIndexedOffset - return the offset from the beginning of the type for /// the specified indices. This is used to implement getelementptr. /// - uint64_t getIndexedOffset(Type *Ty, - Value* const* Indices, unsigned NumIndices) const; + uint64_t getIndexedOffset(Type *Ty, ArrayRef Indices) const; /// getStructLayout - Return a StructLayout object, indicating the alignment /// of the struct, its size, and the offsets of its fields. Note that this Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jul 19 09:01:37 2011 @@ -606,10 +606,10 @@ } unsigned BitWidth = TD->getTypeSizeInBits(IntPtrTy); - APInt Offset = APInt(BitWidth, - TD->getIndexedOffset(Ptr->getType(), - (Value**)Ops.data() + 1, - Ops.size() - 1)); + APInt Offset = + APInt(BitWidth, TD->getIndexedOffset(Ptr->getType(), + makeArrayRef((Value **)Ops.data() + 1, + Ops.size() - 1))); Ptr = cast(Ptr->stripPointerCasts()); // If this is a GEP of a GEP, fold it all into a single GEP. @@ -628,9 +628,7 @@ Ptr = cast(GEP->getOperand(0)); Offset += APInt(BitWidth, - TD->getIndexedOffset(Ptr->getType(), - (Value**)NestedOps.data(), - NestedOps.size())); + TD->getIndexedOffset(Ptr->getType(), NestedOps)); Ptr = cast(Ptr->stripPointerCasts()); } Modified: llvm/trunk/lib/Analysis/Loads.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Loads.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Loads.cpp (original) +++ llvm/trunk/lib/Analysis/Loads.cpp Tue Jul 19 09:01:37 2011 @@ -63,7 +63,7 @@ return V; SmallVector Indices(GEP->op_begin() + 1, GEP->op_end()); ByteOffset += TD->getIndexedOffset(GEP->getPointerOperandType(), - &Indices[0], Indices.size()); + Indices); V = GEP->getPointerOperand(); } else if (Operator::getOpcode(V) == Instruction::BitCast) { V = cast(V)->getOperand(0); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jul 19 09:01:37 2011 @@ -1409,8 +1409,7 @@ // Generate a symbolic expression for the byte address const Constant *PtrVal = CE->getOperand(0); SmallVector IdxVec(CE->op_begin()+1, CE->op_end()); - int64_t Offset = TD.getIndexedOffset(PtrVal->getType(), &IdxVec[0], - IdxVec.size()); + int64_t Offset = TD.getIndexedOffset(PtrVal->getType(), IdxVec); const MCExpr *Base = LowerConstant(CE->getOperand(0), AP); if (Offset == 0) Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Tue Jul 19 09:01:37 2011 @@ -542,8 +542,7 @@ case Instruction::GetElementPtr: { const Constant *ptrVal = CE->getOperand(0); SmallVector idxVec(CE->op_begin()+1, CE->op_end()); - int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), &idxVec[0], - idxVec.size()); + int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), idxVec); return std::make_pair(ptrVal, Offset); } case Instruction::IntToPtr: { Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Tue Jul 19 09:01:37 2011 @@ -549,8 +549,7 @@ // Compute the index GenericValue Result = getConstantValue(Op0); SmallVector Indices(CE->op_begin()+1, CE->op_end()); - uint64_t Offset = - TD->getIndexedOffset(Op0->getType(), &Indices[0], Indices.size()); + uint64_t Offset = TD->getIndexedOffset(Op0->getType(), Indices); char* tmp = (char*) Result.PointerVal; Result = PTOGV(tmp + Offset); Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Tue Jul 19 09:01:37 2011 @@ -521,15 +521,16 @@ } -uint64_t TargetData::getIndexedOffset(Type *ptrTy, Value* const* Indices, - unsigned NumIndices) const { +uint64_t TargetData::getIndexedOffset(Type *ptrTy, + ArrayRef Indices) const { Type *Ty = ptrTy; assert(Ty->isPointerTy() && "Illegal argument for getIndexedOffset()"); uint64_t Result = 0; generic_gep_type_iterator - TI = gep_type_begin(ptrTy, Indices, Indices+NumIndices); - for (unsigned CurIDX = 0; CurIDX != NumIndices; ++CurIDX, ++TI) { + TI = gep_type_begin(ptrTy, Indices.begin(), Indices.end()); + for (unsigned CurIDX = 0, EndIDX = Indices.size(); CurIDX != EndIDX; + ++CurIDX, ++TI) { if (StructType *STy = dyn_cast(*TI)) { assert(Indices[CurIDX]->getType() == Type::getInt32Ty(ptrTy->getContext()) && Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Tue Jul 19 09:01:37 2011 @@ -346,9 +346,9 @@ SmallVector Indices1(GEP1->idx_begin(), GEP1->idx_end()); SmallVector Indices2(GEP2->idx_begin(), GEP2->idx_end()); uint64_t Offset1 = TD->getIndexedOffset(GEP1->getPointerOperandType(), - Indices1.data(), Indices1.size()); + Indices1); uint64_t Offset2 = TD->getIndexedOffset(GEP2->getPointerOperandType(), - Indices2.data(), Indices2.size()); + Indices2); return Offset1 == Offset2; } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue Jul 19 09:01:37 2011 @@ -266,8 +266,7 @@ // Get the current byte offset into the thing. Use the original // operand in case we're looking through a bitcast. SmallVector Ops(GEP->idx_begin(), GEP->idx_end()); - Offset = TD->getIndexedOffset(GEP->getPointerOperandType(), - Ops.data(), Ops.size()); + Offset = TD->getIndexedOffset(GEP->getPointerOperandType(), Ops); Op1 = GEP->getPointerOperand()->stripPointerCasts(); Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=135478&r1=135477&r2=135478&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Jul 19 09:01:37 2011 @@ -516,7 +516,7 @@ // Compute the offset that this GEP adds to the pointer. SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); uint64_t GEPOffset = TD.getIndexedOffset(GEP->getPointerOperandType(), - &Indices[0], Indices.size()); + Indices); // See if all uses can be converted. if (!CanConvertToScalar(GEP, Offset+GEPOffset)) return false; @@ -589,7 +589,7 @@ // Compute the offset that this GEP adds to the pointer. SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); uint64_t GEPOffset = TD.getIndexedOffset(GEP->getPointerOperandType(), - &Indices[0], Indices.size()); + Indices); ConvertUsesToScalar(GEP, NewAI, Offset+GEPOffset*8); GEP->eraseFromParent(); continue; @@ -1776,8 +1776,7 @@ // Compute the offset due to this GEP and check if the alloca has a // component element at that offset. SmallVector Indices(GEPI->op_begin() + 1, GEPI->op_end()); - Offset += TD->getIndexedOffset(GEPI->getPointerOperandType(), - &Indices[0], Indices.size()); + Offset += TD->getIndexedOffset(GEPI->getPointerOperandType(), Indices); if (!TypeHasComponent(Info.AI->getAllocatedType(), Offset, 0)) MarkUnsafe(Info, GEPI); } @@ -2053,8 +2052,7 @@ SmallVector &NewElts) { uint64_t OldOffset = Offset; SmallVector Indices(GEPI->op_begin() + 1, GEPI->op_end()); - Offset += TD->getIndexedOffset(GEPI->getPointerOperandType(), - &Indices[0], Indices.size()); + Offset += TD->getIndexedOffset(GEPI->getPointerOperandType(), Indices); RewriteForScalarRepl(GEPI, AI, Offset, NewElts); From jay.foad at gmail.com Tue Jul 19 09:42:50 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 14:42:50 -0000 Subject: [llvm-commits] [llvm] r135481 - in /llvm/trunk: docs/ReleaseNotes.html include/llvm/Support/GetElementPtrTypeIterator.h lib/Target/TargetData.cpp Message-ID: <20110719144251.135972A6C12D@llvm.org> Author: foad Date: Tue Jul 19 09:42:50 2011 New Revision: 135481 URL: http://llvm.org/viewvc/llvm-project?rev=135481&view=rev Log: Convert gep_type_begin and gep_type_end to use ArrayRef. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/Support/GetElementPtrTypeIterator.h llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135481&r1=135480&r2=135481&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Jul 19 09:42:50 2011 @@ -635,6 +635,8 @@
  • ExtractValueInst::getIndexedType
  • ExtractValueInst::getIndices
  • FindInsertedValue (in llvm/Analysis/ValueTracking.h)
    • +
  • gep_type_begin (in llvm/Support/GetElementPtrTypeIterator.h)
    • +
  • gep_type_end (in llvm/Support/GetElementPtrTypeIterator.h)
  • IRBuilder::CreateCall
  • IRBuilder::CreateExtractValue
  • IRBuilder::CreateInsertValue
    • Modified: llvm/trunk/include/llvm/Support/GetElementPtrTypeIterator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/GetElementPtrTypeIterator.h?rev=135481&r1=135480&r2=135481&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/GetElementPtrTypeIterator.h (original) +++ llvm/trunk/include/llvm/Support/GetElementPtrTypeIterator.h Tue Jul 19 09:42:50 2011 @@ -97,16 +97,16 @@ return gep_type_iterator::end(GEP.op_end()); } - template - inline generic_gep_type_iterator - gep_type_begin(Type *Op0, ItTy I, ItTy E) { - return generic_gep_type_iterator::begin(Op0, I); + template + inline generic_gep_type_iterator + gep_type_begin(Type *Op0, ArrayRef A) { + return generic_gep_type_iterator::begin(Op0, A.begin()); } - template - inline generic_gep_type_iterator - gep_type_end(Type *Op0, ItTy I, ItTy E) { - return generic_gep_type_iterator::end(E); + template + inline generic_gep_type_iterator + gep_type_end(Type *Op0, ArrayRef A) { + return generic_gep_type_iterator::end(A.end()); } } // end namespace llvm Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=135481&r1=135480&r2=135481&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Tue Jul 19 09:42:50 2011 @@ -528,7 +528,7 @@ uint64_t Result = 0; generic_gep_type_iterator - TI = gep_type_begin(ptrTy, Indices.begin(), Indices.end()); + TI = gep_type_begin(ptrTy, Indices); for (unsigned CurIDX = 0, EndIDX = Indices.size(); CurIDX != EndIDX; ++CurIDX, ++TI) { if (StructType *STy = dyn_cast(*TI)) { From jay.foad at gmail.com Tue Jul 19 10:07:52 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 15:07:52 -0000 Subject: [llvm-commits] [llvm] r135482 - in /llvm/trunk: docs/ReleaseNotes.html include/llvm/Analysis/InstructionSimplify.h lib/Analysis/InstructionSimplify.cpp lib/Analysis/PHITransAddr.cpp lib/Transforms/InstCombine/InstructionCombining.cpp Message-ID: <20110719150752.B1C9C2A6C12D@llvm.org> Author: foad Date: Tue Jul 19 10:07:52 2011 New Revision: 135482 URL: http://llvm.org/viewvc/llvm-project?rev=135482&view=rev Log: Convert SimplifyGEPInst to use ArrayRef. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/Analysis/InstructionSimplify.h llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/lib/Analysis/PHITransAddr.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135482&r1=135481&r2=135482&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Jul 19 10:07:52 2011 @@ -648,6 +648,7 @@
  • MDNode::getIfExists
  • MDNode::getTemporary
  • MDNode::getWhenValsUnresolved
    • +
  • SimplifyGEPInst (in llvm/Analysis/InstructionSimplify.h)
  • TargetData::getIndexedOffset
    • Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InstructionSimplify.h?rev=135482&r1=135481&r2=135482&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/InstructionSimplify.h (original) +++ llvm/trunk/include/llvm/Analysis/InstructionSimplify.h Tue Jul 19 10:07:52 2011 @@ -24,6 +24,8 @@ class Instruction; class Value; class TargetData; + template + class ArrayRef; /// SimplifyAddInst - Given operands for an Add, see if we can /// fold the result. If not, this returns null. @@ -121,7 +123,7 @@ /// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can /// fold the result. If not, this returns null. - Value *SimplifyGEPInst(Value * const *Ops, unsigned NumOps, + Value *SimplifyGEPInst(ArrayRef Ops, const TargetData *TD = 0, const DominatorTree *DT = 0); //=== Helper functions for higher up the class hierarchy. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=135482&r1=135481&r2=135482&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Jul 19 10:07:52 2011 @@ -2219,24 +2219,24 @@ /// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyGEPInst(Value *const *Ops, unsigned NumOps, +Value *llvm::SimplifyGEPInst(ArrayRef Ops, const TargetData *TD, const DominatorTree *) { // The type of the GEP pointer operand. PointerType *PtrTy = cast(Ops[0]->getType()); // getelementptr P -> P. - if (NumOps == 1) + if (Ops.size() == 1) return Ops[0]; if (isa(Ops[0])) { // Compute the (pointer) type returned by the GEP instruction. - Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, &Ops[1], - NumOps-1); + Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, Ops.data() + 1, + Ops.size() - 1); Type *GEPTy = PointerType::get(LastType, PtrTy->getAddressSpace()); return UndefValue::get(GEPTy); } - if (NumOps == 2) { + if (Ops.size() == 2) { // getelementptr P, 0 -> P. if (ConstantInt *C = dyn_cast(Ops[1])) if (C->isZero()) @@ -2250,12 +2250,13 @@ } // Check to see if this is constant foldable. - for (unsigned i = 0; i != NumOps; ++i) + for (unsigned i = 0, e = Ops.size(); i != e; ++i) if (!isa(Ops[i])) return 0; return ConstantExpr::getGetElementPtr(cast(Ops[0]), - (Constant *const*)Ops+1, NumOps-1); + (Constant *const*)Ops.data() + 1, + Ops.size() - 1); } /// SimplifyPHINode - See if we can fold the given phi. If not, returns null. @@ -2456,7 +2457,7 @@ break; case Instruction::GetElementPtr: { SmallVector Ops(I->op_begin(), I->op_end()); - Result = SimplifyGEPInst(&Ops[0], Ops.size(), TD, DT); + Result = SimplifyGEPInst(Ops, TD, DT); break; } case Instruction::PHI: Modified: llvm/trunk/lib/Analysis/PHITransAddr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/PHITransAddr.cpp?rev=135482&r1=135481&r2=135482&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/PHITransAddr.cpp (original) +++ llvm/trunk/lib/Analysis/PHITransAddr.cpp Tue Jul 19 10:07:52 2011 @@ -228,7 +228,7 @@ return GEP; // Simplify the GEP to handle 'gep x, 0' -> x etc. - if (Value *V = SimplifyGEPInst(&GEPOps[0], GEPOps.size(), TD, DT)) { + if (Value *V = SimplifyGEPInst(GEPOps, TD, DT)) { for (unsigned i = 0, e = GEPOps.size(); i != e; ++i) RemoveInstInputs(GEPOps[i], InstInputs); Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=135482&r1=135481&r2=135482&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue Jul 19 10:07:52 2011 @@ -742,7 +742,7 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) { SmallVector Ops(GEP.op_begin(), GEP.op_end()); - if (Value *V = SimplifyGEPInst(&Ops[0], Ops.size(), TD)) + if (Value *V = SimplifyGEPInst(Ops, TD)) return ReplaceInstUsesWith(GEP, V); Value *PtrOp = GEP.getOperand(0); From dblaikie at gmail.com Tue Jul 19 10:15:29 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 19 Jul 2011 08:15:29 -0700 Subject: [llvm-commits] [dragonegg] r135472 - /dragonegg/trunk/src/Convert.cpp In-Reply-To: <4E257659.9080601@grosser.es> References: <20110719084312.0801E2A6C12C@llvm.org> <4E25622B.7020407@grosser.es> <4E257659.9080601@grosser.es> Message-ID: > > >> + Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, > >> + makeArrayRef(&Ty, 1)), > > > > That's ugly. Why doesn't the implicit conversion from Type * to > > ArrayRef work? > > OK. It seems I got it wrong. I used > > Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, &Ty) > > whereas you used > > Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Id, Ty) > ^^ > > This makes the difference. Your code compiles for me without any problems. > If you're self hosting clang then perhaps Anna's work on "[sema++] clang should give a fixit for */& mismatch" might be, eventually, able to provide fixits for this situation. Though I assume this particular scenario won't be the first that's addressed when adding this feature, owing to the use of type conversions, etc, necessary to make the FixIt suggestion. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110719/b40b9042/attachment.html From jay.foad at gmail.com Tue Jul 19 10:30:30 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 19 Jul 2011 15:30:30 -0000 Subject: [llvm-commits] [llvm] r135483 - in /llvm/trunk/lib/VMCore: ConstantFold.cpp ConstantFold.h Constants.cpp Message-ID: <20110719153030.CE5372A6C12D@llvm.org> Author: foad Date: Tue Jul 19 10:30:30 2011 New Revision: 135483 URL: http://llvm.org/viewvc/llvm-project?rev=135483&view=rev Log: Convert ConstantFoldGetElementPtr to use ArrayRef. Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/lib/VMCore/ConstantFold.h llvm/trunk/lib/VMCore/Constants.cpp Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=135483&r1=135482&r2=135483&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Tue Jul 19 10:30:30 2011 @@ -2166,31 +2166,30 @@ template static Constant *ConstantFoldGetElementPtrImpl(Constant *C, bool inBounds, - IndexTy const *Idxs, - unsigned NumIdx) { - if (NumIdx == 0) return C; + ArrayRef Idxs) { + if (Idxs.empty()) return C; Constant *Idx0 = cast(Idxs[0]); - if ((NumIdx == 1 && Idx0->isNullValue())) + if ((Idxs.size() == 1 && Idx0->isNullValue())) return C; if (isa(C)) { PointerType *Ptr = cast(C->getType()); - Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs, Idxs+NumIdx); + Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(), Idxs.end()); assert(Ty != 0 && "Invalid indices for GEP!"); return UndefValue::get(PointerType::get(Ty, Ptr->getAddressSpace())); } if (C->isNullValue()) { bool isNull = true; - for (unsigned i = 0, e = NumIdx; i != e; ++i) + for (unsigned i = 0, e = Idxs.size(); i != e; ++i) if (!cast(Idxs[i])->isNullValue()) { isNull = false; break; } if (isNull) { PointerType *Ptr = cast(C->getType()); - Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs, - Idxs+NumIdx); + Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(), + Idxs.end()); assert(Ty != 0 && "Invalid indices for GEP!"); return ConstantPointerNull::get(PointerType::get(Ty, Ptr->getAddressSpace())); @@ -2210,7 +2209,7 @@ if ((LastTy && LastTy->isArrayTy()) || Idx0->isNullValue()) { SmallVector NewIndices; - NewIndices.reserve(NumIdx + CE->getNumOperands()); + NewIndices.reserve(Idxs.size() + CE->getNumOperands()); for (unsigned i = 1, e = CE->getNumOperands()-1; i != e; ++i) NewIndices.push_back(CE->getOperand(i)); @@ -2232,7 +2231,7 @@ } NewIndices.push_back(Combined); - NewIndices.append(Idxs+1, Idxs+NumIdx); + NewIndices.append(Idxs.begin() + 1, Idxs.end()); return (inBounds && cast(CE)->isInBounds()) ? ConstantExpr::getInBoundsGetElementPtr(CE->getOperand(0), &NewIndices[0], @@ -2248,7 +2247,7 @@ // i64 0, i64 0) // To: i32* getelementptr ([3 x i32]* %X, i64 0, i64 0) // - if (CE->isCast() && NumIdx > 1 && Idx0->isNullValue()) { + if (CE->isCast() && Idxs.size() > 1 && Idx0->isNullValue()) { if (PointerType *SPT = dyn_cast(CE->getOperand(0)->getType())) if (ArrayType *SAT = dyn_cast(SPT->getElementType())) @@ -2257,9 +2256,9 @@ if (CAT->getElementType() == SAT->getElementType()) return inBounds ? ConstantExpr::getInBoundsGetElementPtr( - (Constant*)CE->getOperand(0), Idxs, NumIdx) : + (Constant*)CE->getOperand(0), Idxs.data(), Idxs.size()) : ConstantExpr::getGetElementPtr( - (Constant*)CE->getOperand(0), Idxs, NumIdx); + (Constant*)CE->getOperand(0), Idxs.data(), Idxs.size()); } } @@ -2270,7 +2269,7 @@ SmallVector NewIdxs; Type *Ty = C->getType(); Type *Prev = 0; - for (unsigned i = 0; i != NumIdx; + for (unsigned i = 0, e = Idxs.size(); i != e; Prev = Ty, Ty = cast(Ty)->getTypeAtIndex(Idxs[i]), ++i) { if (ConstantInt *CI = dyn_cast(Idxs[i])) { if (ArrayType *ATy = dyn_cast(Ty)) @@ -2280,7 +2279,7 @@ if (isa(Prev)) { // It's out of range, but we can factor it into the prior // dimension. - NewIdxs.resize(NumIdx); + NewIdxs.resize(Idxs.size()); ConstantInt *Factor = ConstantInt::get(CI->getType(), ATy->getNumElements()); NewIdxs[i] = ConstantExpr::getSRem(CI, Factor); @@ -2312,7 +2311,7 @@ // If we did any factoring, start over with the adjusted indices. if (!NewIdxs.empty()) { - for (unsigned i = 0; i != NumIdx; ++i) + for (unsigned i = 0, e = Idxs.size(); i != e; ++i) if (!NewIdxs[i]) NewIdxs[i] = cast(Idxs[i]); return inBounds ? ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs.data(), @@ -2323,22 +2322,20 @@ // If all indices are known integers and normalized, we can do a simple // check for the "inbounds" property. if (!Unknown && !inBounds && - isa(C) && isInBoundsIndices(Idxs, NumIdx)) - return ConstantExpr::getInBoundsGetElementPtr(C, Idxs, NumIdx); + isa(C) && isInBoundsIndices(Idxs.data(), Idxs.size())) + return ConstantExpr::getInBoundsGetElementPtr(C, Idxs.data(), Idxs.size()); return 0; } Constant *llvm::ConstantFoldGetElementPtr(Constant *C, bool inBounds, - Constant* const *Idxs, - unsigned NumIdx) { - return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs, NumIdx); + ArrayRef Idxs) { + return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs); } Constant *llvm::ConstantFoldGetElementPtr(Constant *C, bool inBounds, - Value* const *Idxs, - unsigned NumIdx) { - return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs, NumIdx); + ArrayRef Idxs) { + return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs); } Modified: llvm/trunk/lib/VMCore/ConstantFold.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.h?rev=135483&r1=135482&r2=135483&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.h (original) +++ llvm/trunk/lib/VMCore/ConstantFold.h Tue Jul 19 10:30:30 2011 @@ -48,9 +48,9 @@ Constant *ConstantFoldCompareInstruction(unsigned short predicate, Constant *C1, Constant *C2); Constant *ConstantFoldGetElementPtr(Constant *C, bool inBounds, - Constant* const *Idxs, unsigned NumIdx); + ArrayRef Idxs); Constant *ConstantFoldGetElementPtr(Constant *C, bool inBounds, - Value* const *Idxs, unsigned NumIdx); + ArrayRef Idxs); } // End llvm namespace #endif Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=135483&r1=135482&r2=135483&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Jul 19 10:30:30 2011 @@ -1594,7 +1594,8 @@ Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs, unsigned NumIdx, bool InBounds) { - if (Constant *FC = ConstantFoldGetElementPtr(C, InBounds, Idxs, NumIdx)) + if (Constant *FC = ConstantFoldGetElementPtr(C, InBounds, + makeArrayRef(Idxs, NumIdx))) return FC; // Fold a few common cases. // Get the result type of the getelementptr! From jyasskin at google.com Tue Jul 19 11:08:03 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Tue, 19 Jul 2011 09:08:03 -0700 Subject: [llvm-commits] [llvm] r135453 - /llvm/trunk/docs/GettingStarted.html In-Reply-To: <4E253963.9090905@grosser.es> References: <20110719002054.671CC2A6C12C@llvm.org> <4E253963.9090905@grosser.es> Message-ID: On Tue, Jul 19, 2011 at 12:59 AM, Tobias Grosser wrote: > On 07/19/2011 02:20 AM, Jeffrey Yasskin wrote: >> >> Author: jyasskin >> Date: Mon Jul 18 19:20:54 2011 >> New Revision: 135453 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=135453&view=rev >> Log: >> Document how to maintain a git-svn clone of the LLVM git repositories. > > Hi Jeffrey, > > thanks for your work. I was too slow to review it on time, but as you got a > nice version in this was not needed. > > Just two comments: >> >> +

    To set up clone from which you can submit code using > > To set up A clone ... > ? ? ? ? ?^ > -> You miss an 'A' here. > > And furthermore, the text before the section you added might also need an > update: > >> GIT mirrors are available for a number of LLVM subprojects. > > A list of the available mirrors may be nice. I think chapuni already > cloned all available mirrors https://github.com/chapuni, so we can figure > out from there which are available. > >> These >> mirrors sync automatically with each Subversion commit and contain >> all necessary git-svn marks (so, you can recreate git-svn metadata >> locally). Note that right now mirrors reflect only trunk for each >> project. > > This is not true anymore. E.g. the LLVM git mirror has: > > $ git branch -a > * master > ?remotes/origin/master > ?remotes/origin/release_1 > ?remotes/origin/release_16 > ?remotes/origin/release_20 > ?remotes/origin/release_21 > ?remotes/origin/release_22 > ?remotes/origin/release_23 > ?remotes/origin/release_24 > ?remotes/origin/release_25 > ?remotes/origin/release_26 > ?remotes/origin/release_27 > ?remotes/origin/release_28 > ?remotes/origin/release_29 > ?remotes/origin/svn-tags/RELEASE_1 > ?remotes/origin/svn-tags/RELEASE_20 > ?remotes/origin/svn-tags/RELEASE_21 > ?remotes/origin/svn-tags/RELEASE_22 > ?remotes/origin/svn-tags/RELEASE_23 > ?remotes/origin/svn-tags/RELEASE_24 > ?remotes/origin/svn-tags/RELEASE_25 > ?remotes/origin/svn-tags/RELEASE_26 > ?remotes/origin/svn-tags/RELEASE_27 > ?remotes/origin/svn-tags/RELEASE_28 > ?remotes/origin/svn-tags/RELEASE_29 > > Cheers and thanks again for this nice work! I'm happy for the git experts to modify and improve this section. I just wanted to get something in here so us plain git users can work without having to search the mailing list every time. Thanks for sending the mailing list posts that I copied from. :) Jeffrey From bob.wilson at apple.com Tue Jul 19 11:31:59 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 19 Jul 2011 16:31:59 -0000 Subject: [llvm-commits] [llvm] r135485 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20110719163159.38D4B2A6C12D@llvm.org> Author: bwilson Date: Tue Jul 19 11:31:58 2011 New Revision: 135485 URL: http://llvm.org/viewvc/llvm-project?rev=135485&view=rev Log: Revert "Update docs to reflect r135457." This reverts commit ba034c0a2e71303c7cf3f43ca8e69dc8436b32e2. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=135485&r1=135484&r2=135485&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue Jul 19 11:31:58 2011 @@ -750,9 +750,7 @@ metadata, ;; Reference to file where defined i32, ;; 24 bit - Line number where defined ;; 8 bit - Argument number. 1 indicates 1st argument. - metadata, ;; Type descriptor - i32, ;; flags - metadata ;; (optional) Reference to inline location + metadata ;; Type descriptor } From bob.wilson at apple.com Tue Jul 19 11:32:50 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 19 Jul 2011 16:32:50 -0000 Subject: [llvm-commits] [llvm] r135486 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Support/Dwarf.h lib/Analysis/DIBuilder.cpp lib/Analysis/DebugInfo.cpp Message-ID: <20110719163250.B544C2A6C12D@llvm.org> Author: bwilson Date: Tue Jul 19 11:32:50 2011 New Revision: 135486 URL: http://llvm.org/viewvc/llvm-project?rev=135486&view=rev Log: Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/include/llvm/Support/Dwarf.h llvm/trunk/lib/Analysis/DIBuilder.cpp llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=135486&r1=135485&r2=135486&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jul 19 11:32:50 2011 @@ -628,9 +628,7 @@ uint64_t getAddrElement(unsigned Idx) const { if (getVersion() <= llvm::LLVMDebugVersion8) return getUInt64Field(Idx+6); - if (getVersion() == llvm::LLVMDebugVersion9) - return getUInt64Field(Idx+7); - return getUInt64Field(Idx+8); + return getUInt64Field(Idx+7); } /// isBlockByrefVariable - Return true if the variable was declared as @@ -718,13 +716,6 @@ /// suitable to hold function specific information. NamedMDNode *getFnSpecificMDNode(const Module &M, StringRef Name); - /// createInlinedVariable - Create a new inlined variable based on current - /// variable. - /// @param DV Current Variable. - /// @param InlinedScope Location at current variable is inlined. - DIVariable createInlinedVariable(MDNode *DV, MDNode *InlinedScope, - LLVMContext &VMContext); - class DebugInfoFinder { public: /// processModule - Process entire module and collect debug info Modified: llvm/trunk/include/llvm/Support/Dwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Dwarf.h?rev=135486&r1=135485&r2=135486&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Dwarf.h (original) +++ llvm/trunk/include/llvm/Support/Dwarf.h Tue Jul 19 11:32:50 2011 @@ -22,9 +22,8 @@ // Debug info constants. enum { - LLVMDebugVersion = (10 << 16), // Current version of debug information. - LLVMDebugVersion9 = (9 << 16), // Constant for version 9. - LLVMDebugVersion8 = (8 << 16), // Constant for version 8. + LLVMDebugVersion = (9 << 16), // Current version of debug information. + LLVMDebugVersion8 = (8 << 16), // Cconstant for version 8. LLVMDebugVersion7 = (7 << 16), // Constant for version 7. LLVMDebugVersion6 = (6 << 16), // Constant for version 6. LLVMDebugVersion5 = (5 << 16), // Constant for version 5. Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=135486&r1=135485&r2=135486&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Tue Jul 19 11:32:50 2011 @@ -626,8 +626,7 @@ File, ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24))), Ty, - ConstantInt::get(Type::getInt32Ty(VMContext), Flags), - Constant::getNullValue(Type::getInt32Ty(VMContext)), + ConstantInt::get(Type::getInt32Ty(VMContext), Flags) }; MDNode *Node = MDNode::get(VMContext, Elts); if (AlwaysPreserve) { @@ -662,7 +661,6 @@ Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24)))); Elts.push_back(Ty); Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); - Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); Elts.append(Addr.begin(), Addr.end()); return DIVariable(MDNode::get(VMContext, Elts)); Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=135486&r1=135485&r2=135486&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Jul 19 11:32:50 2011 @@ -111,9 +111,7 @@ unsigned DIVariable::getNumAddrElements() const { if (getVersion() <= llvm::LLVMDebugVersion8) return DbgNode->getNumOperands()-6; - if (getVersion() == llvm::LLVMDebugVersion9) - return DbgNode->getNumOperands()-7; - return DbgNode->getNumOperands()-8; + return DbgNode->getNumOperands()-7; } @@ -762,19 +760,6 @@ return M.getOrInsertNamedMetadata(Name.str()); } -/// createInlinedVariable - Create a new inlined variable based on current -/// variable. -/// @param DV Current Variable. -/// @param InlinedScope Location at current variable is inlined. -DIVariable llvm::createInlinedVariable(MDNode *DV, MDNode *InlinedScope, - LLVMContext &VMContext) { - SmallVector Elts; - // Insert inlined scope as 7th element. - for (unsigned i = 0, e = DV->getNumOperands(); i != e; ++i) - i == 7 ? Elts.push_back(InlinedScope) : - Elts.push_back(DV->getOperand(i)); - return DIVariable(MDNode::get(VMContext, Elts)); -} //===----------------------------------------------------------------------===// // DebugInfoFinder implementations. From grosbach at apple.com Tue Jul 19 11:50:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 16:50:30 -0000 Subject: [llvm-commits] [llvm] r135489 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td AsmParser/ARMAsmParser.cpp Message-ID: <20110719165030.8C7682A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 11:50:30 2011 New Revision: 135489 URL: http://llvm.org/viewvc/llvm-project?rev=135489&view=rev Log: ARM range checking for so_imm operands in assembly parsing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135489&r1=135488&r2=135489&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 19 11:50:30 2011 @@ -443,10 +443,12 @@ // so_imm - Match a 32-bit shifter_operand immediate operand, which is an // 8-bit immediate rotated by an arbitrary number of bits. +def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; } def so_imm : Operand, ImmLeaf { let EncoderMethod = "getSOImmOpValue"; + let ParserMatchClass = SOImmAsmOperand; } // Break so_imm's up into two pieces. This handles immediates with up to 16 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135489&r1=135488&r2=135489&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 11:50:30 2011 @@ -407,6 +407,14 @@ int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } + bool isARMSOImm() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return ARM_AM::getSOImmVal(Value) != -1; + } bool isT2SOImm() const { if (Kind != Immediate) return false; @@ -613,6 +621,11 @@ addExpr(Inst, getImm()); } + void addARMSOImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addT2SOImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); From ahatanak at gmail.com Tue Jul 19 12:09:53 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 17:09:53 -0000 Subject: [llvm-commits] [llvm] r135490 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719170953.BD19D2A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 12:09:53 2011 New Revision: 135490 URL: http://llvm.org/viewvc/llvm-project?rev=135490&view=rev Log: Separate code that modifies control flow from code that adds instruction to basic blocks. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135490&r1=135489&r2=135490&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 12:09:53 2011 @@ -760,6 +760,8 @@ // ... // fallthrough --> loopMBB BB->addSuccessor(loopMBB); + loopMBB->addSuccessor(loopMBB); + loopMBB->addSuccessor(exitMBB); // loopMBB: // ll oldval, 0(ptr) @@ -782,8 +784,6 @@ BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loopMBB); - BB->addSuccessor(loopMBB); - BB->addSuccessor(exitMBB); MI->eraseFromParent(); // The instruction is gone now. @@ -845,6 +845,11 @@ BB->end()); exitMBB->transferSuccessorsAndUpdatePHIs(BB); + BB->addSuccessor(loopMBB); + loopMBB->addSuccessor(loopMBB); + loopMBB->addSuccessor(sinkMBB); + sinkMBB->addSuccessor(exitMBB); + // thisMBB: // addiu tmp1,$0,-4 # 0xfffffffc // and addr,ptr,tmp1 @@ -867,7 +872,6 @@ BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); - BB->addSuccessor(loopMBB); // atomic.load.binop // loopMBB: @@ -909,8 +913,6 @@ .addReg(Tmp9).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB); - BB->addSuccessor(loopMBB); - BB->addSuccessor(sinkMBB); // sinkMBB: // and tmp10,oldval,mask @@ -929,8 +931,6 @@ BuildMI(BB, dl, TII->get(Mips::SRA), Dest) .addReg(Tmp12).addImm(ShiftImm); - sinkMBB->addSuccessor(exitMBB); - MI->eraseFromParent(); // The instruction is gone now. return exitMBB; @@ -977,6 +977,10 @@ // ... // fallthrough --> loop1MBB BB->addSuccessor(loop1MBB); + loop1MBB->addSuccessor(exitMBB); + loop1MBB->addSuccessor(loop2MBB); + loop2MBB->addSuccessor(loop1MBB); + loop2MBB->addSuccessor(exitMBB); // loop1MBB: // ll dest, 0(ptr) @@ -985,8 +989,6 @@ BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BNE)) .addReg(Dest).addReg(Oldval).addMBB(exitMBB); - BB->addSuccessor(exitMBB); - BB->addSuccessor(loop2MBB); // loop2MBB: // or tmp1, $0, newval @@ -997,8 +999,6 @@ BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); - BB->addSuccessor(loop1MBB); - BB->addSuccessor(exitMBB); MI->eraseFromParent(); // The instruction is gone now. @@ -1061,6 +1061,13 @@ BB->end()); exitMBB->transferSuccessorsAndUpdatePHIs(BB); + BB->addSuccessor(loop1MBB); + loop1MBB->addSuccessor(sinkMBB); + loop1MBB->addSuccessor(loop2MBB); + loop2MBB->addSuccessor(loop1MBB); + loop2MBB->addSuccessor(sinkMBB); + sinkMBB->addSuccessor(exitMBB); + // thisMBB: // addiu tmp1,$0,-4 # 0xfffffffc // and addr,ptr,tmp1 @@ -1085,7 +1092,6 @@ BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift); BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm); BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift); - BB->addSuccessor(loop1MBB); // loop1MBB: // ll oldval3,0(addr) @@ -1096,8 +1102,6 @@ BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::BNE)) .addReg(Oldval4).addReg(Oldval2).addMBB(sinkMBB); - BB->addSuccessor(sinkMBB); - BB->addSuccessor(loop2MBB); // loop2MBB: // and tmp6,oldval3,mask2 @@ -1111,8 +1115,6 @@ .addReg(Tmp7).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB); - BB->addSuccessor(loop1MBB); - BB->addSuccessor(sinkMBB); // sinkMBB: // srl tmp8,oldval4,shift @@ -1128,8 +1130,6 @@ BuildMI(BB, dl, TII->get(Mips::SRA), Dest) .addReg(Tmp9).addImm(ShiftImm); - sinkMBB->addSuccessor(exitMBB); - MI->eraseFromParent(); // The instruction is gone now. return exitMBB; From aggarwa4 at illinois.edu Tue Jul 19 12:27:53 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 19 Jul 2011 17:27:53 -0000 Subject: [llvm-commits] [poolalloc] r135493 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110719172753.AD0232A6C12D@llvm.org> Author: aggarwa4 Date: Tue Jul 19 12:27:53 2011 New Revision: 135493 URL: http://llvm.org/viewvc/llvm-project?rev=135493&view=rev Log: Use the correct tag argument. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=135493&r1=135492&r2=135493&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jul 19 12:27:53 2011 @@ -233,7 +233,7 @@ std::vector Args; Args.push_back(CI->getOperand(1)); Args.push_back(CI->getOperand(3)); // size - Args.push_back(CI->getOperand(5)); + Args.push_back(CI->getOperand(6)); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", CI); toDelete.push_back(CI); } From anton at korobeynikov.info Tue Jul 19 12:50:42 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 19 Jul 2011 21:50:42 +0400 Subject: [llvm-commits] [llvm] r135438 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/ExecutionEngine/JIT/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/Cel Message-ID: Hi Evan, > Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for > better location welcome). Any reasons for this? For me it seems that you're moving everything our of Target* stuff into MC* which does not look better :) PS: And yes, initial frame state definitely does not belong to asm info. Maybe there should be something like MCFrameInfo then? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From ahatanak at gmail.com Tue Jul 19 13:14:26 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 18:14:26 -0000 Subject: [llvm-commits] [llvm] r135495 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll Message-ID: <20110719181426.C75152A6C12E@llvm.org> Author: ahatanak Date: Tue Jul 19 13:14:26 2011 New Revision: 135495 URL: http://llvm.org/viewvc/llvm-project?rev=135495&view=rev Log: Remove redundant instructions. - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135495&r1=135494&r2=135495&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 13:14:26 2011 @@ -818,7 +818,6 @@ unsigned Tmp1 = RegInfo.createVirtualRegister(RC); unsigned Tmp2 = RegInfo.createVirtualRegister(RC); unsigned Tmp3 = RegInfo.createVirtualRegister(RC); - unsigned Tmp4 = RegInfo.createVirtualRegister(RC); unsigned Tmp6 = RegInfo.createVirtualRegister(RC); unsigned Tmp7 = RegInfo.createVirtualRegister(RC); unsigned Tmp8 = RegInfo.createVirtualRegister(RC); @@ -858,8 +857,7 @@ // ori tmp3,$0,255 # 0xff // sll mask,tmp3,shift // nor mask2,$0,mask - // andi tmp4,incr,255 - // sll incr2,tmp4,shift + // sll incr2,incr,shift int64_t MaskImm = (Size == 1) ? 255 : 65535; BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); @@ -869,8 +867,7 @@ BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(Shift); // atomic.load.binop @@ -886,8 +883,9 @@ // atomic.swap // loopMBB: // ll oldval,0(addr) + // and newval,incr2,mask // and tmp8,oldval,mask2 - // or tmp9,tmp8,incr2 + // or tmp9,tmp8,newval // sc tmp9,0(addr) // beq tmp9,$0,loopMBB @@ -898,17 +896,17 @@ // nor tmp7, $0, tmp6 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2); BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); + BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); } else if (BinOpcode) { // tmp7, oldval, incr2 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); - } - if (BinOpcode != 0 || Nand) BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); + } else {// atomic.swap + BuildMI(BB, dl, TII->get(Mips::ANDi), Newval).addReg(Incr2).addReg(Mask); + } + BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); - if (BinOpcode != 0 || Nand) - BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); - else - BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Incr2); + BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); BuildMI(BB, dl, TII->get(Mips::SC), Tmp13) .addReg(Tmp9).addReg(Addr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) @@ -953,7 +951,6 @@ unsigned Oldval = MI->getOperand(2).getReg(); unsigned Newval = MI->getOperand(3).getReg(); - unsigned Tmp1 = RegInfo.createVirtualRegister(RC); unsigned Tmp3 = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block @@ -991,12 +988,10 @@ .addReg(Dest).addReg(Oldval).addMBB(exitMBB); // loop2MBB: - // or tmp1, $0, newval // sc tmp1, 0(ptr) // beq tmp1, $0, loop1MBB BB = loop2MBB; - BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Newval); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); @@ -1068,6 +1063,7 @@ loop2MBB->addSuccessor(sinkMBB); sinkMBB->addSuccessor(exitMBB); + // FIXME: computation of newval2 can be moved to loop2MBB. // thisMBB: // addiu tmp1,$0,-4 # 0xfffffffc // and addr,ptr,tmp1 Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135495&r1=135494&r2=135495&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Tue Jul 19 13:14:26 2011 @@ -73,8 +73,7 @@ ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] -; CHECK: or $[[R2:[0-9]+]], $zero, $5 -; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] ; CHECK: $[[BB1]]: } @@ -97,8 +96,7 @@ ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -129,8 +127,7 @@ ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -161,8 +158,7 @@ ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -194,8 +190,7 @@ ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 ; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) From ahatanak at gmail.com Tue Jul 19 13:19:40 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 18:19:40 -0000 Subject: [llvm-commits] [llvm] r135496 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719181940.533782A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 13:19:40 2011 New Revision: 135496 URL: http://llvm.org/viewvc/llvm-project?rev=135496&view=rev Log: Fix comments. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135496&r1=135495&r2=135496&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 13:19:40 2011 @@ -766,8 +766,8 @@ // loopMBB: // ll oldval, 0(ptr) // tmp1, oldval, incr - // sc tmp1, 0(ptr) - // beq tmp1, $0, loopMBB + // sc tmp3, tmp1, 0(ptr) + // beq tmp3, $0, loopMBB BB = loopMBB; BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0); if (Nand) { @@ -877,8 +877,8 @@ // and newval,tmp7,mask // and tmp8,oldval,mask2 // or tmp9,tmp8,newval - // sc tmp9,0(addr) - // beq tmp9,$0,loopMBB + // sc tmp13,tmp9,0(addr) + // beq tmp13,$0,loopMBB // atomic.swap // loopMBB: @@ -886,8 +886,8 @@ // and newval,incr2,mask // and tmp8,oldval,mask2 // or tmp9,tmp8,newval - // sc tmp9,0(addr) - // beq tmp9,$0,loopMBB + // sc tmp13,tmp9,0(addr) + // beq tmp13,$0,loopMBB BB = loopMBB; BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0); @@ -988,8 +988,8 @@ .addReg(Dest).addReg(Oldval).addMBB(exitMBB); // loop2MBB: - // sc tmp1, 0(ptr) - // beq tmp1, $0, loop1MBB + // sc tmp3, tmp1, 0(ptr) + // beq tmp3, $0, loop1MBB BB = loop2MBB; BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) @@ -1102,8 +1102,8 @@ // loop2MBB: // and tmp6,oldval3,mask2 // or tmp7,tmp6,newval2 - // sc tmp7,0(addr) - // beq tmp7,$0,loop1MBB + // sc tmp10,tmp7,0(addr) + // beq tmp10,$0,loop1MBB BB = loop2MBB; BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); From evan.cheng at apple.com Tue Jul 19 13:24:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 19 Jul 2011 11:24:37 -0700 Subject: [llvm-commits] [llvm] r135438 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/ExecutionEngine/JIT/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/Cel In-Reply-To: References: Message-ID: <7E8C6640-B44F-40E3-92A8-264F9BEA5D3C@apple.com> On Jul 19, 2011, at 10:50 AM, Anton Korobeynikov wrote: > Hi Evan, > >> Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for >> better location welcome). > Any reasons for this? For me it seems that you're moving everything > our of Target* stuff into MC* which does not look better :) MC layer is not allowed to access CodeGen or Target. Currently we have a significant layering issue in MC. TargetAsmInfo is the worst offender. I'll moving stuff out one step at a time. There is another design issue in we are using virtual functions too freely when in fact a lot of target information can be initialized early. The Target layers are designed such a way where only one instance can be created at a time. By moving stuff into MC we can now create multiple instances and switch between them. This patch is obviously not a good example. See MCSubtargetInfo instead and how we are using it to implement .code directives. > > PS: And yes, initial frame state definitely does not belong to asm > info. Maybe there should be something like MCFrameInfo then? Later, if it's deemed necessary. We have a way to go still. Evan > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University From grosbach at apple.com Tue Jul 19 13:32:48 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 18:32:48 -0000 Subject: [llvm-commits] [llvm] r135497 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110719183248.EBA262A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 13:32:48 2011 New Revision: 135497 URL: http://llvm.org/viewvc/llvm-project?rev=135497&view=rev Log: Remove unused code. cc_out and pred operands are added during parsing via custom C++ now. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135497&r1=135496&r2=135497&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 13:32:48 2011 @@ -1959,12 +1959,12 @@ Mnemonic == "vcle" || (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || - Mnemonic == "vqdmlal" || Mnemonic == "bics")) + Mnemonic == "vqdmlal")) return Mnemonic; // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. - if (Mnemonic != "adcs") { + if (Mnemonic != "adcs" && Mnemonic != "bics") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) @@ -2167,59 +2167,8 @@ MCStreamer &Out) { MCInst Inst; unsigned ErrorInfo; - MatchResultTy MatchResult, MatchResult2; + MatchResultTy MatchResult; MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); - if (MatchResult != Match_Success) { - // If we get a Match_InvalidOperand it might be some arithmetic instruction - // that does not update the condition codes. So try adding a CCOut operand - // with a value of reg0. - if (MatchResult == Match_InvalidOperand) { - Operands.insert(Operands.begin() + 1, - ARMOperand::CreateCCOut(0, - ((ARMOperand*)Operands[0])->getStartLoc())); - MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo); - if (MatchResult2 == Match_Success) - MatchResult = Match_Success; - else { - ARMOperand *CCOut = ((ARMOperand*)Operands[1]); - Operands.erase(Operands.begin() + 1); - delete CCOut; - } - } - // If we get a Match_MnemonicFail it might be some arithmetic instruction - // that updates the condition codes if it ends in 's'. So see if the - // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut - // operand with a value of CPSR. - else if (MatchResult == Match_MnemonicFail) { - // Get the instruction mnemonic, which is the first token. - StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); - if (Mnemonic.substr(Mnemonic.size()-1) == "s") { - // removed the 's' from the mnemonic for matching. - StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1); - SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc(); - ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]); - Operands.erase(Operands.begin()); - delete OldMnemonic; - Operands.insert(Operands.begin(), - ARMOperand::CreateToken(MnemonicNoS, NameLoc)); - Operands.insert(Operands.begin() + 1, - ARMOperand::CreateCCOut(ARM::CPSR, NameLoc)); - MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo); - if (MatchResult2 == Match_Success) - MatchResult = Match_Success; - else { - ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]); - Operands.erase(Operands.begin()); - delete OldMnemonic; - Operands.insert(Operands.begin(), - ARMOperand::CreateToken(Mnemonic, NameLoc)); - ARMOperand *CCOut = ((ARMOperand*)Operands[1]); - Operands.erase(Operands.begin() + 1); - delete CCOut; - } - } - } - } switch (MatchResult) { case Match_Success: Out.EmitInstruction(Inst); From evan.cheng at apple.com Tue Jul 19 13:45:58 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 19 Jul 2011 18:45:58 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135498 - in /llvm-gcc-4.2/trunk/gcc: Makefile.in llvm-backend.cpp Message-ID: <20110719184558.62F422A6C12D@llvm.org> Author: evancheng Date: Tue Jul 19 13:45:58 2011 New Revision: 135498 URL: http://llvm.org/viewvc/llvm-project?rev=135498&view=rev Log: Fix my brain cramp. Initialize MCCodeGenInfo, not MCRegisterInfo. Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=135498&r1=135497&r2=135498&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Tue Jul 19 13:45:58 2011 @@ -1188,9 +1188,9 @@ ## and asm printers actually get linked into libllvmgcc.dylib. LLVMTARGETSYMBOLS := \ _LLVMInitializeARMTarget _LLVMInitializeARMAsmPrinter \ - _LLVMInitializeARMMCAsmInfo _LLVMInitializeARMMCRegisterInfo \ + _LLVMInitializeARMMCAsmInfo _LLVMInitializeARMMCCodeGenInfo \ _LLVMInitializeX86Target _LLVMInitializeX86AsmPrinter \ - _LLVMInitializeX86MCAsmInfo _LLVMInitializeX86MCRegisterInfo \ + _LLVMInitializeX86MCAsmInfo _LLVMInitializeX86MCCodeGenInfo \ endif Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=135498&r1=135497&r2=135498&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jul 19 13:45:58 2011 @@ -382,7 +382,7 @@ Declare(LLVM_TARGET_NAME, TargetInfo); Declare(LLVM_TARGET_NAME, Target); Declare(LLVM_TARGET_NAME, MCAsmInfo); - Declare(LLVM_TARGET_NAME, MCRegisterInfo); + Declare(LLVM_TARGET_NAME, MCCodeGenInfo); Declare(LLVM_TARGET_NAME, AsmPrinter); #undef Declare #undef Declare2 @@ -408,7 +408,7 @@ DoInit(LLVM_TARGET_NAME, TargetInfo); DoInit(LLVM_TARGET_NAME, Target); DoInit(LLVM_TARGET_NAME, MCAsmInfo); - DoInit(LLVM_TARGET_NAME, MCRegisterInfo); + DoInit(LLVM_TARGET_NAME, MCCodeGenInfo); DoInit(LLVM_TARGET_NAME, AsmPrinter); #undef DoInit #undef DoInit2 From grosbach at apple.com Tue Jul 19 14:02:39 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 19:02:39 -0000 Subject: [llvm-commits] [llvm] r135499 - /llvm/trunk/test/MC/ARM/arm_fixups.s Message-ID: <20110719190239.7DF8E2A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 14:02:39 2011 New Revision: 135499 URL: http://llvm.org/viewvc/llvm-project?rev=135499&view=rev Log: Whitespace. Modified: llvm/trunk/test/MC/ARM/arm_fixups.s Modified: llvm/trunk/test/MC/ARM/arm_fixups.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=135499&r1=135498&r2=135499&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_fixups.s (original) +++ llvm/trunk/test/MC/ARM/arm_fixups.s Tue Jul 19 14:02:39 2011 @@ -4,4 +4,4 @@ // CHECK: bl _printf @ encoding: [A,A,A,0xeb] // CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch bl _printf - \ No newline at end of file + From grosbach at apple.com Tue Jul 19 14:13:28 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 19:13:28 -0000 Subject: [llvm-commits] [llvm] r135500 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm_fixups.s test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s utils/TableGen/EDEmitter.cpp Message-ID: <20110719191328.743462A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 14:13:28 2011 New Revision: 135500 URL: http://llvm.org/viewvc/llvm-project?rev=135500&view=rev Log: ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/arm_fixups.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 19 14:13:28 2011 @@ -494,11 +494,16 @@ let EncoderMethod = "getImmMinusOneOpValue"; } -// i32imm_hilo16 - For movt/movw - sets the MC Encoder method. -// The imm is split into imm{15-12}, imm{11-0} +// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference +// a relocatable expression. // -def i32imm_hilo16 : Operand { +// FIXME: This really needs a Thumb version separate from the ARM version. +// While the range is the same, and can thus use the same match class, +// the encoding is different so it should have a different encoder method. +def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; } +def imm0_65535_expr : Operand { let EncoderMethod = "getHiLo16ImmOpValue"; + let ParserMatchClass = Imm0_65535ExprAsmOperand; } /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield @@ -2123,7 +2128,7 @@ } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in -def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm), +def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", [(set GPR:$Rd, imm0_65535:$imm)]>, @@ -2137,11 +2142,15 @@ let Inst{25} = 1; } +def : InstAlias<"mov${p} $Rd, $imm", + (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, + Requires<[IsARM]>; + def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; let Constraints = "$src = $Rd" in { -def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm), +def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, imm0_65535_expr:$imm), DPFrm, IIC_iMOVi, "movt", "\t$Rd, $imm", [(set GPR:$Rd, @@ -3260,7 +3269,7 @@ let isMoveImm = 1 in def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd), - (ins GPR:$false, i32imm_hilo16:$imm, pred:$p), + (ins GPR:$false, imm0_65535_expr:$imm, pred:$p), 4, IIC_iMOVi, []>, RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jul 19 14:13:28 2011 @@ -1615,7 +1615,7 @@ Requires<[IsThumb2]>; let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in -def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi, +def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, "movw", "\t$Rd, $imm", [(set rGPR:$Rd, imm0_65535:$imm)]> { let Inst{31-27} = 0b11110; @@ -1639,7 +1639,7 @@ let Constraints = "$src = $Rd" in { def t2MOVTi16 : T2I<(outs rGPR:$Rd), - (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi, + (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, "movt", "\t$Rd, $imm", [(set rGPR:$Rd, (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { @@ -2723,7 +2723,7 @@ // FIXME: Pseudo-ize these. For now, just mark codegen only. let isCodeGenOnly = 1 in { let isMoveImm = 1 in -def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm), +def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm), IIC_iCMOVi, "movw", "\t$Rd, $imm", []>, RegConstraint<"$false = $Rd"> { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 14:13:28 2011 @@ -407,6 +407,16 @@ int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } + bool isImm0_65535Expr() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // If it's not a constant expression, it'll generate a fixup and be + // handled later. + if (!CE) return true; + int64_t Value = CE->getValue(); + return Value >= 0 && Value < 65536; + } bool isARMSOImm() const { if (Kind != Immediate) return false; @@ -621,6 +631,11 @@ addExpr(Inst, getImm()); } + void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addARMSOImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); @@ -2063,16 +2078,19 @@ SmallVectorImpl &Operands) { // Create the leading tokens for the mnemonic, split by '.' characters. size_t Start = 0, Next = Name.find('.'); - StringRef Head = Name.slice(Start, Next); + StringRef Mnemonic = Name.slice(Start, Next); // Split out the predication code and carry setting flag from the mnemonic. unsigned PredicationCode; unsigned ProcessorIMod; bool CarrySetting; - Head = SplitMnemonic(Head, PredicationCode, CarrySetting, + Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting, ProcessorIMod); - Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); + Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); + + // FIXME: This is all a pretty gross hack. We should automatically handle + // optional operands like this via tblgen. // Next, add the CCOut and ConditionCode operands, if needed. // @@ -2082,13 +2100,13 @@ // the matcher deal with finding the right instruction or generating an // appropriate error. bool CanAcceptCarrySet, CanAcceptPredicationCode; - GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode); + GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); // If we had a carry-set on an instruction that can't do that, issue an // error. if (!CanAcceptCarrySet && CarrySetting) { Parser.EatToEndOfStatement(); - return Error(NameLoc, "instruction '" + Head + + return Error(NameLoc, "instruction '" + Mnemonic + "' can not set flags, but 's' suffix specified"); } @@ -2136,7 +2154,7 @@ // Read the remaining operands. if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. - if (ParseOperand(Operands, Head)) { + if (ParseOperand(Operands, Mnemonic)) { Parser.EatToEndOfStatement(); return true; } @@ -2145,7 +2163,7 @@ Parser.Lex(); // Eat the comma. // Parse and remember the operand. - if (ParseOperand(Operands, Head)) { + if (ParseOperand(Operands, Mnemonic)) { Parser.EatToEndOfStatement(); return true; } @@ -2158,6 +2176,26 @@ } Parser.Lex(); // Consume the EndOfStatement + + + // The 'mov' mnemonic is special. One variant has a cc_out operand, while + // another does not. Specifically, the MOVW instruction does not. So we + // special case it here and remove the defaulted (non-setting) cc_out + // operand if that's the instruction we're trying to match. + // + // We do this post-processing of the explicit operands rather than just + // conditionally adding the cc_out in the first place because we need + // to check the type of the parsed immediate operand. + if (Mnemonic == "mov" && Operands.size() > 4 && + !static_cast(Operands[4])->isARMSOImm() && + static_cast(Operands[4])->isImm0_65535Expr()) { + ARMOperand *Op = static_cast(Operands[1]); + Operands.erase(Operands.begin() + 1); + delete Op; + } + + + return false; } Modified: llvm/trunk/test/MC/ARM/arm_fixups.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_fixups.s (original) +++ llvm/trunk/test/MC/ARM/arm_fixups.s Tue Jul 19 14:13:28 2011 @@ -1,7 +1,17 @@ -// RUN: llvm-mc -triple arm-unknown-unknown %s --show-encoding > %t -// RUN: FileCheck < %t %s +@ RUN: llvm-mc -triple armv7-unknown-unknown %s --show-encoding > %t +@ RUN: FileCheck < %t %s -// CHECK: bl _printf @ encoding: [A,A,A,0xeb] -// CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch -bl _printf + bl _printf +@ CHECK: bl _printf @ encoding: [A,A,A,0xeb] +@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch + mov r9, :lower16:(_foo) + movw r9, :lower16:(_foo) + movt r9, :upper16:(_foo) + +@ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16 +@ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16 +@ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16 Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 14:13:28 2011 @@ -671,6 +671,21 @@ @ CHECK: mlsne r2, r5, r6, r3 @ encoding: [0x95,0x36,0x62,0x10] @------------------------------------------------------------------------------ +@ MOV (immediate) + at ------------------------------------------------------------------------------ + mov r3, #7 + mov r4, #0xff0 + mov r5, #0xff0000 + mov r6, #0xffff + movw r9, #0xffff + +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3] +@ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3] +@ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3] +@ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3] + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 19 14:13:28 2011 @@ -88,3 +88,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction + + + @ Out of range immediate for MOV + movw r9, 0x10000 +@ CHECK-ERRORS: error: invalid operand for instruction Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=135500&r1=135499&r2=135500&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Jul 19 14:13:28 2011 @@ -593,6 +593,7 @@ IMM("imm0_255"); IMM("imm0_4095"); IMM("imm0_65535"); + IMM("imm0_65535_expr"); IMM("jt2block_operand"); IMM("t_imm_s4"); IMM("pclabel"); From dpatel at apple.com Tue Jul 19 14:41:54 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 19 Jul 2011 19:41:54 -0000 Subject: [llvm-commits] [llvm] r135504 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Support/Dwarf.h lib/Analysis/DIBuilder.cpp lib/Analysis/DebugInfo.cpp Message-ID: <20110719194154.45FE32A6C12D@llvm.org> Author: dpatel Date: Tue Jul 19 14:41:54 2011 New Revision: 135504 URL: http://llvm.org/viewvc/llvm-project?rev=135504&view=rev Log: Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/include/llvm/Support/Dwarf.h llvm/trunk/lib/Analysis/DIBuilder.cpp llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=135504&r1=135503&r2=135504&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jul 19 14:41:54 2011 @@ -628,7 +628,9 @@ uint64_t getAddrElement(unsigned Idx) const { if (getVersion() <= llvm::LLVMDebugVersion8) return getUInt64Field(Idx+6); - return getUInt64Field(Idx+7); + if (getVersion() == llvm::LLVMDebugVersion9) + return getUInt64Field(Idx+7); + return getUInt64Field(Idx+8); } /// isBlockByrefVariable - Return true if the variable was declared as @@ -716,6 +718,13 @@ /// suitable to hold function specific information. NamedMDNode *getFnSpecificMDNode(const Module &M, StringRef Name); + /// createInlinedVariable - Create a new inlined variable based on current + /// variable. + /// @param DV Current Variable. + /// @param InlinedScope Location at current variable is inlined. + DIVariable createInlinedVariable(MDNode *DV, MDNode *InlinedScope, + LLVMContext &VMContext); + class DebugInfoFinder { public: /// processModule - Process entire module and collect debug info Modified: llvm/trunk/include/llvm/Support/Dwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Dwarf.h?rev=135504&r1=135503&r2=135504&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Dwarf.h (original) +++ llvm/trunk/include/llvm/Support/Dwarf.h Tue Jul 19 14:41:54 2011 @@ -22,8 +22,9 @@ // Debug info constants. enum { - LLVMDebugVersion = (9 << 16), // Current version of debug information. - LLVMDebugVersion8 = (8 << 16), // Cconstant for version 8. + LLVMDebugVersion = (10 << 16), // Current version of debug information. + LLVMDebugVersion9 = (9 << 16), // Constant for version 9. + LLVMDebugVersion8 = (8 << 16), // Constant for version 8. LLVMDebugVersion7 = (7 << 16), // Constant for version 7. LLVMDebugVersion6 = (6 << 16), // Constant for version 6. LLVMDebugVersion5 = (5 << 16), // Constant for version 5. Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=135504&r1=135503&r2=135504&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Tue Jul 19 14:41:54 2011 @@ -626,7 +626,8 @@ File, ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24))), Ty, - ConstantInt::get(Type::getInt32Ty(VMContext), Flags) + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), + Constant::getNullValue(Type::getInt32Ty(VMContext)), }; MDNode *Node = MDNode::get(VMContext, Elts); if (AlwaysPreserve) { @@ -661,6 +662,7 @@ Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24)))); Elts.push_back(Ty); Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); Elts.append(Addr.begin(), Addr.end()); return DIVariable(MDNode::get(VMContext, Elts)); Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=135504&r1=135503&r2=135504&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Jul 19 14:41:54 2011 @@ -111,7 +111,9 @@ unsigned DIVariable::getNumAddrElements() const { if (getVersion() <= llvm::LLVMDebugVersion8) return DbgNode->getNumOperands()-6; - return DbgNode->getNumOperands()-7; + if (getVersion() == llvm::LLVMDebugVersion9) + return DbgNode->getNumOperands()-7; + return DbgNode->getNumOperands()-8; } @@ -760,6 +762,19 @@ return M.getOrInsertNamedMetadata(Name.str()); } +/// createInlinedVariable - Create a new inlined variable based on current +/// variable. +/// @param DV Current Variable. +/// @param InlinedScope Location at current variable is inlined. +DIVariable llvm::createInlinedVariable(MDNode *DV, MDNode *InlinedScope, + LLVMContext &VMContext) { + SmallVector Elts; + // Insert inlined scope as 7th element. + for (unsigned i = 0, e = DV->getNumOperands(); i != e; ++i) + i == 7 ? Elts.push_back(InlinedScope) : + Elts.push_back(DV->getOperand(i)); + return DIVariable(MDNode::get(VMContext, Elts)); +} //===----------------------------------------------------------------------===// // DebugInfoFinder implementations. From dpatel at apple.com Tue Jul 19 14:42:14 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 19 Jul 2011 19:42:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135505 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Message-ID: <20110719194214.CB8E92A6C12D@llvm.org> Author: dpatel Date: Tue Jul 19 14:42:14 2011 New Revision: 135505 URL: http://llvm.org/viewvc/llvm-project?rev=135505&view=rev Log: Update DebugFactory to match r135504. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=135505&r1=135504&r2=135505&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Jul 19 14:42:14 2011 @@ -1954,7 +1954,8 @@ F, ConstantInt::get(Type::getInt32Ty(VMContext), LineNo), Ty, - ConstantInt::get(Type::getInt32Ty(VMContext), Flags) + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), + Constant::getNullValue(Type::getInt32Ty(VMContext)) }; MDNode *Node = MDNode::get(VMContext, Elts); if (AlwaysPreserve) { @@ -1991,6 +1992,8 @@ Elts.push_back(F); Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)); Elts.push_back(Ty); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); Elts.append(Addr, Addr+NumAddr); return DIVariable(MDNode::get(VMContext, Elts)); From dpatel at apple.com Tue Jul 19 14:45:04 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 19 Jul 2011 12:45:04 -0700 Subject: [llvm-commits] Fwd: [llvm-gcc-4.2] r135505 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp References: <20110719194214.CB8E92A6C12D@llvm.org> Message-ID: <01EF41C1-2E50-4202-A042-02AE98E12CE8@apple.com> Dragon-egg developers, Please apply this patch to dragon-egg also. This is required to match corresponding change in llvm. Thanks! - Devang Begin forwarded message: > From: Devang Patel > Subject: [llvm-commits] [llvm-gcc-4.2] r135505 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp > Date: July 19, 2011 12:42:14 PM PDT > To: llvm-commits at cs.uiuc.edu > > Author: dpatel > Date: Tue Jul 19 14:42:14 2011 > New Revision: 135505 > > URL: http://llvm.org/viewvc/llvm-project?rev=135505&view=rev > Log: > Update DebugFactory to match r135504. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=135505&r1=135504&r2=135505&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Jul 19 14:42:14 2011 > @@ -1954,7 +1954,8 @@ > F, > ConstantInt::get(Type::getInt32Ty(VMContext), LineNo), > Ty, > - ConstantInt::get(Type::getInt32Ty(VMContext), Flags) > + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), > + Constant::getNullValue(Type::getInt32Ty(VMContext)) > }; > MDNode *Node = MDNode::get(VMContext, Elts); > if (AlwaysPreserve) { > @@ -1991,6 +1992,8 @@ > Elts.push_back(F); > Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)); > Elts.push_back(Ty); > + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); > + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); > Elts.append(Addr, Addr+NumAddr); > > return DIVariable(MDNode::get(VMContext, Elts)); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110719/777731af/attachment.html From grosbach at apple.com Tue Jul 19 14:45:44 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 19:45:44 -0000 Subject: [llvm-commits] [llvm] r135506 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110719194544.B6B7D2A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 14:45:44 2011 New Revision: 135506 URL: http://llvm.org/viewvc/llvm-project?rev=135506&view=rev Log: Tighten conditional for 'mov' cc_out. Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135506&r1=135505&r2=135506&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 14:45:44 2011 @@ -2188,7 +2188,8 @@ // to check the type of the parsed immediate operand. if (Mnemonic == "mov" && Operands.size() > 4 && !static_cast(Operands[4])->isARMSOImm() && - static_cast(Operands[4])->isImm0_65535Expr()) { + static_cast(Operands[4])->isImm0_65535Expr() && + static_cast(Operands[1])->getReg() == 0) { ARMOperand *Op = static_cast(Operands[1]); Operands.erase(Operands.begin() + 1); delete Op; From grosbach at apple.com Tue Jul 19 14:47:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 19:47:11 -0000 Subject: [llvm-commits] [llvm] r135507 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110719194711.F21712A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 14:47:11 2011 New Revision: 135507 URL: http://llvm.org/viewvc/llvm-project?rev=135507&view=rev Log: Tidy up. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135507&r1=135506&r2=135507&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 14:47:11 2011 @@ -1963,18 +1963,14 @@ // Ignore some mnemonics we know aren't predicated forms. // // FIXME: Would be nice to autogen this. - if (Mnemonic == "teq" || Mnemonic == "vceq" || - Mnemonic == "movs" || - Mnemonic == "svc" || - (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || - Mnemonic == "vmls" || Mnemonic == "vnmls") || - Mnemonic == "vacge" || Mnemonic == "vcge" || - Mnemonic == "vclt" || - Mnemonic == "vacgt" || Mnemonic == "vcgt" || - Mnemonic == "vcle" || - (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || - Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || - Mnemonic == "vqdmlal")) + if (Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "movs" || + Mnemonic == "svc" || Mnemonic == "mls" || Mnemonic == "smmls" || + Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vnmls" || + Mnemonic == "vacge" || Mnemonic == "vcge" || Mnemonic == "vclt" || + Mnemonic == "vacgt" || Mnemonic == "vcgt" || Mnemonic == "vcle" || + Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || + Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || + Mnemonic == "vqdmlal") return Mnemonic; // First, split out any predication code. Ignore mnemonics we know aren't From grosbach at apple.com Tue Jul 19 15:10:31 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 20:10:31 -0000 Subject: [llvm-commits] [llvm] r135513 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s Message-ID: <20110719201031.4F91E2A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 15:10:31 2011 New Revision: 135513 URL: http://llvm.org/viewvc/llvm-project?rev=135513&view=rev Log: ARM assembly parsing for MOV (register). Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135513&r1=135512&r2=135513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 15:10:31 2011 @@ -79,6 +79,8 @@ bool MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, MCStreamer &Out); + StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, + bool &CarrySetting, unsigned &ProcessorIMod); void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode); @@ -1952,10 +1954,10 @@ /// setting letters to form a canonical mnemonic and flags. // // FIXME: Would be nice to autogen this. -static StringRef SplitMnemonic(StringRef Mnemonic, - unsigned &PredicationCode, - bool &CarrySetting, - unsigned &ProcessorIMod) { +StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic, + unsigned &PredicationCode, + bool &CarrySetting, + unsigned &ProcessorIMod) { PredicationCode = ARMCC::AL; CarrySetting = false; ProcessorIMod = 0; @@ -1963,19 +1965,19 @@ // Ignore some mnemonics we know aren't predicated forms. // // FIXME: Would be nice to autogen this. - if (Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "movs" || - Mnemonic == "svc" || Mnemonic == "mls" || Mnemonic == "smmls" || - Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vnmls" || - Mnemonic == "vacge" || Mnemonic == "vcge" || Mnemonic == "vclt" || - Mnemonic == "vacgt" || Mnemonic == "vcgt" || Mnemonic == "vcle" || - Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || - Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || - Mnemonic == "vqdmlal") + if ((Mnemonic == "movs" && isThumb()) || + Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || + Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || + Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || + Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || + Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || + Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || + Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") return Mnemonic; // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. - if (Mnemonic != "adcs" && Mnemonic != "bics") { + if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) @@ -2005,10 +2007,10 @@ // the instructions we know end in 's'. if (Mnemonic.endswith("s") && !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || - Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" || - Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" || - Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" || - Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) { + Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || + Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || + Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || + Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) { Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); CarrySetting = true; } @@ -2056,8 +2058,8 @@ Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || - Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" || - Mnemonic == "clrex" || Mnemonic.startswith("cps")) { + Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" || + Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) { CanAcceptPredicationCode = false; } else { CanAcceptPredicationCode = true; Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135513&r1=135512&r2=135513&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 15:10:31 2011 @@ -678,12 +678,31 @@ mov r5, #0xff0000 mov r6, #0xffff movw r9, #0xffff + movs r3, #7 + moveq r4, #0xff0 + movseq r5, #0xff0000 @ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] @ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3] @ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3] @ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3] @ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3] +@ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3] +@ CHECK: moveq r4, #4080 @ encoding: [0xff,0x4e,0xa0,0x03] +@ CHECK: movseq r5, #16711680 @ encoding: [0xff,0x58,0xb0,0x03] + + at ------------------------------------------------------------------------------ +@ MOV (register) + at ------------------------------------------------------------------------------ + mov r2, r3 + movs r2, r3 + moveq r2, r3 + movseq r2, r3 + +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: movs r2, r3 @ encoding: [0x03,0x20,0xb0,0xe1] +@ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01] +@ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01] @------------------------------------------------------------------------------ @ STM* Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135513&r1=135512&r2=135513&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 19 15:10:31 2011 @@ -93,3 +93,9 @@ @ Out of range immediate for MOV movw r9, 0x10000 @ CHECK-ERRORS: error: invalid operand for instruction + + @ Invalid 's' bit usage for MOVW + movs r6, #0xffff + movwseq r9, #0xffff +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified From ahatanak at gmail.com Tue Jul 19 15:11:17 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 20:11:17 -0000 Subject: [llvm-commits] [llvm] r135514 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719201117.8D6032A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 15:11:17 2011 New Revision: 135514 URL: http://llvm.org/viewvc/llvm-project?rev=135514&view=rev Log: Use descriptive variable names. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135514&r1=135513&r2=135514&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 15:11:17 2011 @@ -733,13 +733,13 @@ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); - unsigned Oldval = MI->getOperand(0).getReg(); + unsigned OldVal = MI->getOperand(0).getReg(); unsigned Ptr = MI->getOperand(1).getReg(); unsigned Incr = MI->getOperand(2).getReg(); - unsigned Tmp1 = RegInfo.createVirtualRegister(RC); - unsigned Tmp2 = RegInfo.createVirtualRegister(RC); - unsigned Tmp3 = RegInfo.createVirtualRegister(RC); + unsigned StoreVal = RegInfo.createVirtualRegister(RC); + unsigned AndRes = RegInfo.createVirtualRegister(RC); + unsigned Success = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -765,25 +765,27 @@ // loopMBB: // ll oldval, 0(ptr) - // tmp1, oldval, incr - // sc tmp3, tmp1, 0(ptr) - // beq tmp3, $0, loopMBB + // storeval, oldval, incr + // sc success, storeval, 0(ptr) + // beq success, $0, loopMBB BB = loopMBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); if (Nand) { - // and tmp2, oldval, incr - // nor tmp1, $0, tmp2 - BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr); - BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + // and andres, oldval, incr + // nor storeval, $0, andres + BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); + BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) + .addReg(Mips::ZERO).addReg(AndRes); } else if (BinOpcode) { - // tmp1, oldval, incr - BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr); + // storeval, oldval, incr + BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); } else { - Tmp1 = Incr; + StoreVal = Incr; } - BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Success) + .addReg(StoreVal).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loopMBB); + .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); MI->eraseFromParent(); // The instruction is gone now. @@ -808,24 +810,24 @@ unsigned Ptr = MI->getOperand(1).getReg(); unsigned Incr = MI->getOperand(2).getReg(); - unsigned Addr = RegInfo.createVirtualRegister(RC); - unsigned Shift = RegInfo.createVirtualRegister(RC); + unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); + unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); unsigned Mask = RegInfo.createVirtualRegister(RC); unsigned Mask2 = RegInfo.createVirtualRegister(RC); - unsigned Newval = RegInfo.createVirtualRegister(RC); - unsigned Oldval = RegInfo.createVirtualRegister(RC); + unsigned NewVal = RegInfo.createVirtualRegister(RC); + unsigned OldVal = RegInfo.createVirtualRegister(RC); unsigned Incr2 = RegInfo.createVirtualRegister(RC); - unsigned Tmp1 = RegInfo.createVirtualRegister(RC); - unsigned Tmp2 = RegInfo.createVirtualRegister(RC); - unsigned Tmp3 = RegInfo.createVirtualRegister(RC); - unsigned Tmp6 = RegInfo.createVirtualRegister(RC); - unsigned Tmp7 = RegInfo.createVirtualRegister(RC); - unsigned Tmp8 = RegInfo.createVirtualRegister(RC); - unsigned Tmp9 = RegInfo.createVirtualRegister(RC); - unsigned Tmp10 = RegInfo.createVirtualRegister(RC); - unsigned Tmp11 = RegInfo.createVirtualRegister(RC); - unsigned Tmp12 = RegInfo.createVirtualRegister(RC); - unsigned Tmp13 = RegInfo.createVirtualRegister(RC); + unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); + unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); + unsigned MaskUpper = RegInfo.createVirtualRegister(RC); + unsigned AndRes = RegInfo.createVirtualRegister(RC); + unsigned BinOpRes = RegInfo.createVirtualRegister(RC); + unsigned MaskOldVal0 = RegInfo.createVirtualRegister(RC); + unsigned StoreVal = RegInfo.createVirtualRegister(RC); + unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); + unsigned SrlRes = RegInfo.createVirtualRegister(RC); + unsigned SllRes = RegInfo.createVirtualRegister(RC); + unsigned Success = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -850,84 +852,93 @@ sinkMBB->addSuccessor(exitMBB); // thisMBB: - // addiu tmp1,$0,-4 # 0xfffffffc - // and addr,ptr,tmp1 - // andi tmp2,ptr,3 - // sll shift,tmp2,3 - // ori tmp3,$0,255 # 0xff - // sll mask,tmp3,shift + // addiu masklsb2,$0,-4 # 0xfffffffc + // and alignedaddr,ptr,masklsb2 + // andi ptrlsb2,ptr,3 + // sll shiftamt,ptrlsb2,3 + // ori maskupper,$0,255 # 0xff + // sll mask,maskupper,shiftamt // nor mask2,$0,mask - // sll incr2,incr,shift + // sll incr2,incr,shiftamt int64_t MaskImm = (Size == 1) ? 255 : 65535; - BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); - BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); - BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); - BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) + .addReg(Mips::ZERO).addImm(-4); + BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) + .addReg(Ptr).addReg(MaskLSB2); + BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); + BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); + BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) + .addReg(Mips::ZERO).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(MaskUpper).addReg(ShiftAmt); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(ShiftAmt); // atomic.load.binop // loopMBB: - // ll oldval,0(addr) - // binop tmp7,oldval,incr2 - // and newval,tmp7,mask - // and tmp8,oldval,mask2 - // or tmp9,tmp8,newval - // sc tmp13,tmp9,0(addr) - // beq tmp13,$0,loopMBB - + // ll oldval,0(alignedaddr) + // binop binopres,oldval,incr2 + // and newval,binopres,mask + // and maskedoldval0,oldval,mask2 + // or storeval,maskedoldval0,newval + // sc success,storeval,0(alignedaddr) + // beq success,$0,loopMBB + // atomic.swap // loopMBB: - // ll oldval,0(addr) + // ll oldval,0(alignedaddr) // and newval,incr2,mask - // and tmp8,oldval,mask2 - // or tmp9,tmp8,newval - // sc tmp13,tmp9,0(addr) - // beq tmp13,$0,loopMBB + // and maskedoldval0,oldval,mask2 + // or storeval,maskedoldval0,newval + // sc success,storeval,0(alignedaddr) + // beq success,$0,loopMBB BB = loopMBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); if (Nand) { - // and tmp6, oldval, incr2 - // nor tmp7, $0, tmp6 - BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2); - BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); - BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); + // and andres, oldval, incr2 + // nor binopres, $0, andres + // and newval, binopres, mask + BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); + BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) + .addReg(Mips::ZERO).addReg(AndRes); + BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); } else if (BinOpcode) { - // tmp7, oldval, incr2 - BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); - BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); + // binopres, oldval, incr2 + // and newval, binopres, mask + BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); + BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); } else {// atomic.swap - BuildMI(BB, dl, TII->get(Mips::ANDi), Newval).addReg(Incr2).addReg(Mask); + // and newval, incr2, mask + BuildMI(BB, dl, TII->get(Mips::ANDi), NewVal).addReg(Incr2).addReg(Mask); } - BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp13) - .addReg(Tmp9).addReg(Addr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0) + .addReg(OldVal).addReg(Mask2); + BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) + .addReg(MaskOldVal0).addReg(NewVal); + BuildMI(BB, dl, TII->get(Mips::SC), Success) + .addReg(StoreVal).addReg(AlignedAddr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB); + .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); // sinkMBB: - // and tmp10,oldval,mask - // srl tmp11,tmp10,shift - // sll tmp12,tmp11,24 - // sra dest,tmp12,24 + // and maskedoldval1,oldval,mask + // srl srlres,maskedoldval1,shiftamt + // sll sllres,srlres,24 + // sra dest,sllres,24 BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - BuildMI(BB, dl, TII->get(Mips::AND), Tmp10) - .addReg(Oldval).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SRL), Tmp11) - .addReg(Tmp10).addReg(Shift); - BuildMI(BB, dl, TII->get(Mips::SLL), Tmp12) - .addReg(Tmp11).addImm(ShiftImm); + BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) + .addReg(OldVal).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) + .addReg(MaskedOldVal1).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) + .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp12).addImm(ShiftImm); + .addReg(SllRes).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. @@ -948,10 +959,10 @@ unsigned Dest = MI->getOperand(0).getReg(); unsigned Ptr = MI->getOperand(1).getReg(); - unsigned Oldval = MI->getOperand(2).getReg(); - unsigned Newval = MI->getOperand(3).getReg(); + unsigned OldVal = MI->getOperand(2).getReg(); + unsigned NewVal = MI->getOperand(3).getReg(); - unsigned Tmp3 = RegInfo.createVirtualRegister(RC); + unsigned Success = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -985,15 +996,16 @@ BB = loop1MBB; BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BNE)) - .addReg(Dest).addReg(Oldval).addMBB(exitMBB); + .addReg(Dest).addReg(OldVal).addMBB(exitMBB); // loop2MBB: - // sc tmp3, tmp1, 0(ptr) - // beq tmp3, $0, loop1MBB + // sc success, newval, 0(ptr) + // beq success, $0, loop1MBB BB = loop2MBB; - BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::SC), Success) + .addReg(NewVal).addReg(Ptr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); + .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); MI->eraseFromParent(); // The instruction is gone now. @@ -1015,27 +1027,27 @@ unsigned Dest = MI->getOperand(0).getReg(); unsigned Ptr = MI->getOperand(1).getReg(); - unsigned Oldval = MI->getOperand(2).getReg(); - unsigned Newval = MI->getOperand(3).getReg(); + unsigned CmpVal = MI->getOperand(2).getReg(); + unsigned NewVal = MI->getOperand(3).getReg(); - unsigned Addr = RegInfo.createVirtualRegister(RC); - unsigned Shift = RegInfo.createVirtualRegister(RC); + unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); + unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); unsigned Mask = RegInfo.createVirtualRegister(RC); unsigned Mask2 = RegInfo.createVirtualRegister(RC); - unsigned Oldval2 = RegInfo.createVirtualRegister(RC); - unsigned Oldval3 = RegInfo.createVirtualRegister(RC); - unsigned Oldval4 = RegInfo.createVirtualRegister(RC); - unsigned Newval2 = RegInfo.createVirtualRegister(RC); - unsigned Tmp1 = RegInfo.createVirtualRegister(RC); - unsigned Tmp2 = RegInfo.createVirtualRegister(RC); - unsigned Tmp3 = RegInfo.createVirtualRegister(RC); - unsigned Tmp4 = RegInfo.createVirtualRegister(RC); - unsigned Tmp5 = RegInfo.createVirtualRegister(RC); - unsigned Tmp6 = RegInfo.createVirtualRegister(RC); - unsigned Tmp7 = RegInfo.createVirtualRegister(RC); - unsigned Tmp8 = RegInfo.createVirtualRegister(RC); - unsigned Tmp9 = RegInfo.createVirtualRegister(RC); - unsigned Tmp10 = RegInfo.createVirtualRegister(RC); + unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); + unsigned OldVal = RegInfo.createVirtualRegister(RC); + unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); + unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); + unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); + unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); + unsigned MaskUpper = RegInfo.createVirtualRegister(RC); + unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); + unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); + unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); + unsigned StoreVal = RegInfo.createVirtualRegister(RC); + unsigned SrlRes = RegInfo.createVirtualRegister(RC); + unsigned SllRes = RegInfo.createVirtualRegister(RC); + unsigned Success = RegInfo.createVirtualRegister(RC); // insert new blocks after the current block const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -1065,66 +1077,77 @@ // FIXME: computation of newval2 can be moved to loop2MBB. // thisMBB: - // addiu tmp1,$0,-4 # 0xfffffffc - // and addr,ptr,tmp1 - // andi tmp2,ptr,3 - // sll shift,tmp2,3 - // ori tmp3,$0,255 # 0xff - // sll mask,tmp3,shift + // addiu masklsb2,$0,-4 # 0xfffffffc + // and alignedaddr,ptr,masklsb2 + // andi ptrlsb2,ptr,3 + // sll shiftamt,ptrlsb2,3 + // ori maskupper,$0,255 # 0xff + // sll mask,maskupper,shiftamt // nor mask2,$0,mask - // andi tmp4,oldval,255 - // sll oldval2,tmp4,shift - // andi tmp5,newval,255 - // sll newval2,tmp5,shift + // andi maskedcmpval,cmpval,255 + // sll shiftedcmpval,maskedcmpval,shiftamt + // andi maskednewval,newval,255 + // sll shiftednewval,maskednewval,shiftamt int64_t MaskImm = (Size == 1) ? 255 : 65535; - BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); - BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); - BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); - BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) + .addReg(Mips::ZERO).addImm(-4); + BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) + .addReg(Ptr).addReg(MaskLSB2); + BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); + BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); + BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) + .addReg(Mips::ZERO).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Mask) + .addReg(MaskUpper).addReg(ShiftAmt); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift); - BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) + .addReg(CmpVal).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedCmpVal) + .addReg(MaskedCmpVal).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) + .addReg(NewVal).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedNewVal) + .addReg(MaskedNewVal).addReg(ShiftAmt); // loop1MBB: - // ll oldval3,0(addr) - // and oldval4,oldval3,mask - // bne oldval4,oldval2,sinkMBB + // ll oldval,0(alginedaddr) + // and maskedoldval0,oldval,mask + // bne maskedoldval0,shiftedcmpval,sinkMBB BB = loop1MBB; - BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0); - BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) + .addReg(OldVal).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::BNE)) - .addReg(Oldval4).addReg(Oldval2).addMBB(sinkMBB); + .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); // loop2MBB: - // and tmp6,oldval3,mask2 - // or tmp7,tmp6,newval2 - // sc tmp10,tmp7,0(addr) - // beq tmp10,$0,loop1MBB + // and maskedoldval1,oldval,mask2 + // or storeval,maskedoldval1,shiftednewval + // sc success,storeval,0(alignedaddr) + // beq success,$0,loop1MBB BB = loop2MBB; - BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); - BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); - BuildMI(BB, dl, TII->get(Mips::SC), Tmp10) - .addReg(Tmp7).addReg(Addr).addImm(0); + BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) + .addReg(OldVal).addReg(Mask2); + BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) + .addReg(MaskedOldVal1).addReg(ShiftedNewVal); + BuildMI(BB, dl, TII->get(Mips::SC), Success) + .addReg(StoreVal).addReg(AlignedAddr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) - .addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB); + .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); // sinkMBB: - // srl tmp8,oldval4,shift - // sll tmp9,tmp8,24 - // sra dest,tmp9,24 + // srl srlres,maskedoldval0,shiftamt + // sll sllres,srlres,24 + // sra dest,sllres,24 BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - BuildMI(BB, dl, TII->get(Mips::SRL), Tmp8) - .addReg(Oldval4).addReg(Shift); - BuildMI(BB, dl, TII->get(Mips::SLL), Tmp9) - .addReg(Tmp8).addImm(ShiftImm); + BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) + .addReg(MaskedOldVal0).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) + .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp9).addImm(ShiftImm); + .addReg(SllRes).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. From dag at cray.com Tue Jul 19 15:11:35 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:35 -0500 Subject: [llvm-commits] [PATCH 00/20] Make Inits Unique (Cover Letter) Message-ID: This is a patch series to make TableGen Inits unique. This patch supports some future work to make TableGen more dynamic and allow more code reuse in target specifications. The AVX/SIMD rewrite will take advantage of that to simplify the top-level instruction specification. Please review. Thanks! -Dave David Greene (20): Add DenseMapInfo for std::string [AVX] Remove Mutating Members from Inits [AVX] Remove non-const Iterators [AVX] Constify Inits [AVX] Create Inits Via Factory Method [AVX] Unique UnsetInit [AVX] Unique BitInit [AVX] Make BitsInit Unique [AVX] Make IntInit Unique [AVX] Make StringInit Unique [AVX] Make CodeInit Unique [AVX] Make ListInits Unique [AVX] Make UnOpInit Unique [AVX] Make BinOpInit Unique [AVX] Make TernOpInit Unique [AVX] Make VarInit Unique [AVX] Make VarBitInit Unique [AVX] Make VarListElementInit Unique [AVX] Make FieldInit Unique [AVX] Make DagInits Unique include/llvm/ADT/StringExtras.h | 19 + utils/TableGen/ARMDecoderEmitter.cpp | 20 +- utils/TableGen/AsmMatcherEmitter.cpp | 24 +- utils/TableGen/CallingConvEmitter.cpp | 10 +- utils/TableGen/ClangAttrEmitter.cpp | 10 +- utils/TableGen/ClangDiagnosticsEmitter.cpp | 6 +- utils/TableGen/ClangSACheckersEmitter.cpp | 24 +- utils/TableGen/CodeEmitterGen.cpp | 34 +- utils/TableGen/CodeEmitterGen.h | 4 +- utils/TableGen/CodeGenDAGPatterns.cpp | 119 ++-- utils/TableGen/CodeGenDAGPatterns.h | 18 +- utils/TableGen/CodeGenInstruction.cpp | 36 +- utils/TableGen/CodeGenInstruction.h | 8 +- utils/TableGen/CodeGenRegisters.cpp | 28 +- utils/TableGen/CodeGenTarget.cpp | 4 +- utils/TableGen/DAGISelMatcherGen.cpp | 12 +- utils/TableGen/FastISelEmitter.cpp | 8 +- utils/TableGen/FixedLenDecoderEmitter.cpp | 32 +- utils/TableGen/InstrInfoEmitter.cpp | 8 +- utils/TableGen/LLVMCConfigurationEmitter.cpp | 46 +- utils/TableGen/OptParserEmitter.cpp | 16 +- utils/TableGen/PseudoLoweringEmitter.cpp | 12 +- utils/TableGen/PseudoLoweringEmitter.h | 2 +- utils/TableGen/Record.cpp | 1005 ++++++++++++++++++-------- utils/TableGen/Record.h | 809 ++++++++++++--------- utils/TableGen/RegisterInfoEmitter.cpp | 2 +- utils/TableGen/SetTheory.cpp | 40 +- utils/TableGen/SetTheory.h | 4 +- utils/TableGen/TGParser.cpp | 161 ++-- utils/TableGen/TGParser.h | 20 +- utils/TableGen/X86RecognizableInstr.cpp | 6 +- 31 files changed, 1529 insertions(+), 1018 deletions(-) -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:36 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:36 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: References: Message-ID: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Add a DenseMapInfo implementation for std::string. This is useful when mapping pairs that include a string component. --- include/llvm/ADT/StringExtras.h | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git oldinclude/llvm/ADT/StringExtras.h newinclude/llvm/ADT/StringExtras.h index 5f5c041..d30e225 100644 --- oldinclude/llvm/ADT/StringExtras.h +++ newinclude/llvm/ADT/StringExtras.h @@ -16,6 +16,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/ADT/APFloat.h" +#include "llvm/ADT/DenseMapInfo.h" #include "llvm/ADT/StringRef.h" #include #include @@ -165,6 +166,24 @@ static inline unsigned HashString(StringRef Str, unsigned Result = 0) { return Result; } +// Provide DenseMapInfo for strings. +template<> struct DenseMapInfo { + static inline std::string getEmptyKey() { + std::string Empty("<<>>"); + return Empty; + } + static inline std::string getTombstoneKey() { + std::string Tombstone("<<>>"); + return Tombstone; + } + static unsigned getHashValue(const std::string& Val) { + return HashString(Val); + } + static bool isEqual(const std::string& LHS, const std::string& RHS) { + return LHS == RHS; + } +}; + } // End llvm namespace #endif -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:37 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:37 -0500 Subject: [llvm-commits] [PATCH 02/20] [AVX] Remove Mutating Members from Inits In-Reply-To: References: Message-ID: Delete all member functions that modify Init state. This is in preparation for making Inits const everywhere and finally, converting them to FoldingSetNodes. --- utils/TableGen/CodeEmitterGen.cpp | 12 +++-- utils/TableGen/Record.cpp | 98 ++++++++++++++++++------------------ utils/TableGen/Record.h | 12 +---- utils/TableGen/TGParser.cpp | 19 ++++--- 4 files changed, 69 insertions(+), 72 deletions(-) diff --git oldutils/TableGen/CodeEmitterGen.cpp newutils/TableGen/CodeEmitterGen.cpp index d828dfc..8b5cdda 100644 --- oldutils/TableGen/CodeEmitterGen.cpp +++ newutils/TableGen/CodeEmitterGen.cpp @@ -41,19 +41,23 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { BitsInit *BI = R->getValueAsBitsInit("Inst"); unsigned numBits = BI->getNumBits(); - BitsInit *NewBI = new BitsInit(numBits); + + SmallVector NewBits(numBits); + for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { unsigned bitSwapIdx = numBits - bit - 1; Init *OrigBit = BI->getBit(bit); Init *BitSwap = BI->getBit(bitSwapIdx); - NewBI->setBit(bit, BitSwap); - NewBI->setBit(bitSwapIdx, OrigBit); + NewBits[bit] = BitSwap; + NewBits[bitSwapIdx] = OrigBit; } if (numBits % 2) { unsigned middle = (numBits + 1) / 2; - NewBI->setBit(middle, BI->getBit(middle)); + NewBits[middle] = BI->getBit(middle); } + BitsInit *NewBI = new BitsInit(ArrayRef(NewBits)); + // Update the bits in reversed order so that emitInstrOpBits will get the // correct endianness. R->getValue("Inst")->setValue(NewBI); diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 3aaaa87..1a7f7e1 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -15,6 +15,8 @@ #include "Error.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/Format.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" using namespace llvm; @@ -74,18 +76,17 @@ std::string BitsRecTy::getAsString() const { } Init *BitsRecTy::convertValue(UnsetInit *UI) { - BitsInit *Ret = new BitsInit(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - Ret->setBit(i, new UnsetInit()); - return Ret; + NewBits[i] = new UnsetInit(); + + return new BitsInit(ArrayRef(NewBits)); } Init *BitsRecTy::convertValue(BitInit *UI) { if (Size != 1) return 0; // Can only convert single bit. - BitsInit *Ret = new BitsInit(1); - Ret->setBit(0, UI); - return Ret; + return new BitsInit(ArrayRef(UI)); } /// canFitInBitfield - Return true if the number of bits is large enough to hold @@ -105,11 +106,12 @@ Init *BitsRecTy::convertValue(IntInit *II) { if (!canFitInBitfield(Value, Size)) return 0; - BitsInit *Ret = new BitsInit(Size); + SmallVector NewBits(Size); + for (unsigned i = 0; i != Size; ++i) - Ret->setBit(i, new BitInit(Value & (1LL << i))); + NewBits[i] = new BitInit(Value & (1LL << i)); - return Ret; + return new BitsInit(ArrayRef(NewBits)); } Init *BitsRecTy::convertValue(BitsInit *BI) { @@ -122,16 +124,16 @@ Init *BitsRecTy::convertValue(BitsInit *BI) { Init *BitsRecTy::convertValue(TypedInit *VI) { if (BitsRecTy *BRT = dynamic_cast(VI->getType())) if (BRT->Size == Size) { - BitsInit *Ret = new BitsInit(Size); + SmallVector NewBits(Size); + for (unsigned i = 0; i != Size; ++i) - Ret->setBit(i, new VarBitInit(VI, i)); - return Ret; + NewBits[i] = new VarBitInit(VI, i); + return new BitsInit(ArrayRef(NewBits)); } if (Size == 1 && dynamic_cast(VI->getType())) { - BitsInit *Ret = new BitsInit(1); - Ret->setBit(0, VI); - return Ret; + Init *NewBits[1] = { VI }; + return new BitsInit(ArrayRef(NewBits)); } if (TernOpInit *Tern = dynamic_cast(VI)) { @@ -148,30 +150,31 @@ Init *BitsRecTy::convertValue(TypedInit *VI) { int64_t RHSVal = RHSi->getValue(); if (canFitInBitfield(MHSVal, Size) && canFitInBitfield(RHSVal, Size)) { - BitsInit *Ret = new BitsInit(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - Ret->setBit(i, new TernOpInit(TernOpInit::IF, LHS, - new IntInit((MHSVal & (1LL << i)) ? 1 : 0), - new IntInit((RHSVal & (1LL << i)) ? 1 : 0), - VI->getType())); + NewBits[i] = + new TernOpInit(TernOpInit::IF, LHS, + new IntInit((MHSVal & (1LL << i)) ? 1 : 0), + new IntInit((RHSVal & (1LL << i)) ? 1 : 0), + VI->getType()); - return Ret; + return new BitsInit(ArrayRef(NewBits)); } } else { BitsInit *MHSbs = dynamic_cast(MHS); BitsInit *RHSbs = dynamic_cast(RHS); if (MHSbs && RHSbs) { - BitsInit *Ret = new BitsInit(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - Ret->setBit(i, new TernOpInit(TernOpInit::IF, LHS, - MHSbs->getBit(i), - RHSbs->getBit(i), - VI->getType())); + NewBits[i] = new TernOpInit(TernOpInit::IF, LHS, + MHSbs->getBit(i), + RHSbs->getBit(i), + VI->getType()); - return Ret; + return new BitsInit(ArrayRef(NewBits)); } } } @@ -396,15 +399,14 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { void Init::dump() const { return print(errs()); } Init *BitsInit::convertInitializerBitRange(const std::vector &Bits) { - BitsInit *BI = new BitsInit(Bits.size()); + SmallVector NewBits(Bits.size()); + for (unsigned i = 0, e = Bits.size(); i != e; ++i) { - if (Bits[i] >= getNumBits()) { - delete BI; + if (Bits[i] >= getNumBits()) return 0; - } - BI->setBit(i, getBit(Bits[i])); + NewBits[i] = getBit(Bits[i]); } - return BI; + return new BitsInit(ArrayRef(NewBits)); } std::string BitsInit::getAsString() const { @@ -424,7 +426,7 @@ std::string BitsInit::getAsString() const { // Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) { bool Changed = false; - BitsInit *New = new BitsInit(getNumBits()); + SmallVector NewBits(getNumBits()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { Init *B; @@ -435,12 +437,12 @@ Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) { CurBit = CurBit->resolveReferences(R, RV); Changed |= B != CurBit; } while (B != CurBit); - New->setBit(i, CurBit); + NewBits[i] = CurBit; } if (Changed) - return New; - delete New; + return new BitsInit(ArrayRef(NewBits)); + return this; } @@ -449,16 +451,15 @@ std::string IntInit::getAsString() const { } Init *IntInit::convertInitializerBitRange(const std::vector &Bits) { - BitsInit *BI = new BitsInit(Bits.size()); + SmallVector NewBits(Bits.size()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { - if (Bits[i] >= 64) { - delete BI; + if (Bits[i] >= 64) return 0; - } - BI->setBit(i, new BitInit(Value & (INT64_C(1) << Bits[i]))); + + NewBits[i] = new BitInit(Value & (INT64_C(1) << Bits[i])); } - return BI; + return new BitsInit(ArrayRef(NewBits)); } Init *ListInit::convertInitListSlice(const std::vector &Elements) { @@ -1039,15 +1040,14 @@ Init *TypedInit::convertInitializerBitRange(const std::vector &Bits) { if (T == 0) return 0; // Cannot subscript a non-bits variable. unsigned NumBits = T->getNumBits(); - BitsInit *BI = new BitsInit(Bits.size()); + SmallVector NewBits(Bits.size()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { - if (Bits[i] >= NumBits) { - delete BI; + if (Bits[i] >= NumBits) return 0; - } - BI->setBit(i, new VarBitInit(this, Bits[i])); + + NewBits[i] = new VarBitInit(this, Bits[i]); } - return BI; + return new BitsInit(ArrayRef(NewBits)); } Init *TypedInit::convertInitListSlice(const std::vector &Elements) { diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index f4d0917..f300484 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -15,6 +15,7 @@ #ifndef RECORD_H #define RECORD_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/raw_ostream.h" @@ -624,6 +625,7 @@ class BitsInit : public Init { std::vector Bits; public: explicit BitsInit(unsigned Size) : Bits(Size) {} + BitsInit(ArrayRef Range) : Bits(Range.begin(), Range.end()) {} unsigned getNumBits() const { return Bits.size(); } @@ -631,11 +633,6 @@ public: assert(Bit < Bits.size() && "Bit index out of range!"); return Bits[Bit]; } - void setBit(unsigned Bit, Init *V) { - assert(Bit < Bits.size() && "Bit index out of range!"); - assert(Bits[Bit] == 0 && "Bit already set!"); - Bits[Bit] = V; - } virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); @@ -1174,11 +1171,6 @@ public: return ArgNames[Num]; } - void setArg(unsigned Num, Init *I) { - assert(Num < Args.size() && "Arg number out of range!"); - Args[Num] = I; - } - virtual Init *resolveReferences(Record &R, const RecordVal *RV); virtual std::string getAsString() const; diff --git oldutils/TableGen/TGParser.cpp newutils/TableGen/TGParser.cpp index 1b916b4..d8f5d63 100644 --- oldutils/TableGen/TGParser.cpp +++ newutils/TableGen/TGParser.cpp @@ -116,22 +116,22 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, BitsInit *BInit = dynamic_cast(BI); assert(BInit != 0); - BitsInit *NewVal = new BitsInit(CurVal->getNumBits()); + SmallVector NewBits(CurVal->getNumBits()); // Loop over bits, assigning values as appropriate. for (unsigned i = 0, e = BitList.size(); i != e; ++i) { unsigned Bit = BitList[i]; - if (NewVal->getBit(Bit)) + if (NewBits[Bit]) return Error(Loc, "Cannot set bit #" + utostr(Bit) + " of value '" + ValName + "' more than once"); - NewVal->setBit(Bit, BInit->getBit(i)); + NewBits[Bit] = BInit->getBit(i); } for (unsigned i = 0, e = CurVal->getNumBits(); i != e; ++i) - if (NewVal->getBit(i) == 0) - NewVal->setBit(i, CurVal->getBit(i)); + if (NewBits[i] == 0) + NewBits[i] = CurVal->getBit(i); - V = NewVal; + V = new BitsInit(ArrayRef(NewBits)); } if (RV->setValue(V)) @@ -1127,7 +1127,8 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { } Lex.Lex(); // eat the '}' - BitsInit *Result = new BitsInit(Vals.size()); + SmallVector NewBits(Vals.size()); + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get()); if (Bit == 0) { @@ -1135,9 +1136,9 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { ") is not convertable to a bit"); return 0; } - Result->setBit(Vals.size()-i-1, Bit); + NewBits[Vals.size()-i-1] = Bit; } - return Result; + return new BitsInit(ArrayRef(NewBits)); } case tgtok::l_square: { // Value ::= '[' ValueList ']' Lex.Lex(); // eat the '[' -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:38 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:38 -0500 Subject: [llvm-commits] [PATCH 03/20] [AVX] Remove non-const Iterators In-Reply-To: References: Message-ID: <354aba23155343587d71eb8b0b3425b5f0170702.1311100069.git.dag@cray.com> Remove all non-const iterators from Init classes. This is another step toward constifying Inits and ultimately turning them into FoldingSetNodes. --- utils/TableGen/ClangAttrEmitter.cpp | 4 +++- utils/TableGen/Record.cpp | 10 ++++++++-- utils/TableGen/Record.h | 13 ++----------- 3 files changed, 13 insertions(+), 14 deletions(-) diff --git oldutils/TableGen/ClangAttrEmitter.cpp newutils/TableGen/ClangAttrEmitter.cpp index 26bd878..4116ce6 100644 --- oldutils/TableGen/ClangAttrEmitter.cpp +++ newutils/TableGen/ClangAttrEmitter.cpp @@ -27,7 +27,9 @@ getValueAsListOfStrings(Record &R, StringRef FieldName) { std::vector Strings; Strings.reserve(List->getSize()); - for (ListInit::iterator i = List->begin(), e = List->end(); i != e; ++i) { + for (ListInit::const_iterator i = List->begin(), e = List->end(); + i != e; + ++i) { assert(*i && "Got a null element in a ListInit"); if (StringInit *S = dynamic_cast(*i)) Strings.push_back(S->getValue()); diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 1a7f7e1..f9ee89c 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -629,7 +629,13 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { assert(0 && "Empty list in cdr"); return 0; } - ListInit *Result = new ListInit(LHSl->begin()+1, LHSl->end(), + ListInit::const_iterator begin = LHSl->begin()+1; + ListInit::const_iterator end = LHSl->end(); + // We can't pass these iterators directly to ArrayRef because + // they are not convertible to Init **. Fortunately, + // RandomAccessIterator::operator * is guaranteed to return an + // lvalue. + ListInit *Result = new ListInit(ArrayRef(&*begin, end - begin), LHSl->getType()); return Result; } @@ -876,7 +882,7 @@ static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, std::vector NewOperands; std::vector NewList(MHSl->begin(), MHSl->end()); - for (ListInit::iterator li = NewList.begin(), + for (std::vector::iterator li = NewList.begin(), liend = NewList.end(); li != liend; ++li) { diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index f300484..6ec18fb 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -749,15 +749,14 @@ public: class ListInit : public TypedInit { std::vector Values; public: - typedef std::vector::iterator iterator; typedef std::vector::const_iterator const_iterator; explicit ListInit(std::vector &Vs, RecTy *EltTy) : TypedInit(ListRecTy::get(EltTy)) { Values.swap(Vs); } - explicit ListInit(iterator Start, iterator End, RecTy *EltTy) - : TypedInit(ListRecTy::get(EltTy)), Values(Start, End) {} + explicit ListInit(ArrayRef Range, RecTy *EltTy) + : TypedInit(ListRecTy::get(EltTy)), Values(Range.begin(), Range.end()) {} unsigned getSize() const { return Values.size(); } Init *getElement(unsigned i) const { @@ -782,9 +781,7 @@ public: virtual std::string getAsString() const; - inline iterator begin() { return Values.begin(); } inline const_iterator begin() const { return Values.begin(); } - inline iterator end () { return Values.end(); } inline const_iterator end () const { return Values.end(); } inline size_t size () const { return Values.size(); } @@ -1175,22 +1172,16 @@ public: virtual std::string getAsString() const; - typedef std::vector::iterator arg_iterator; typedef std::vector::const_iterator const_arg_iterator; - typedef std::vector::iterator name_iterator; typedef std::vector::const_iterator const_name_iterator; - inline arg_iterator arg_begin() { return Args.begin(); } inline const_arg_iterator arg_begin() const { return Args.begin(); } - inline arg_iterator arg_end () { return Args.end(); } inline const_arg_iterator arg_end () const { return Args.end(); } inline size_t arg_size () const { return Args.size(); } inline bool arg_empty() const { return Args.empty(); } - inline name_iterator name_begin() { return ArgNames.begin(); } inline const_name_iterator name_begin() const { return ArgNames.begin(); } - inline name_iterator name_end () { return ArgNames.end(); } inline const_name_iterator name_end () const { return ArgNames.end(); } inline size_t name_size () const { return ArgNames.size(); } -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:39 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:39 -0500 Subject: [llvm-commits] [PATCH 04/20] [AVX] Constify Inits In-Reply-To: References: Message-ID: Make references to Inits const everywhere. This is the final step before converting them to FoldingSetNodes. --- utils/TableGen/ARMDecoderEmitter.cpp | 20 +- utils/TableGen/AsmMatcherEmitter.cpp | 24 +- utils/TableGen/CallingConvEmitter.cpp | 10 +- utils/TableGen/ClangAttrEmitter.cpp | 6 +- utils/TableGen/ClangDiagnosticsEmitter.cpp | 6 +- utils/TableGen/ClangSACheckersEmitter.cpp | 24 +- utils/TableGen/CodeEmitterGen.cpp | 26 +- utils/TableGen/CodeEmitterGen.h | 4 +- utils/TableGen/CodeGenDAGPatterns.cpp | 112 +++--- utils/TableGen/CodeGenDAGPatterns.h | 18 +- utils/TableGen/CodeGenInstruction.cpp | 36 +- utils/TableGen/CodeGenInstruction.h | 8 +- utils/TableGen/CodeGenRegisters.cpp | 24 +- utils/TableGen/CodeGenTarget.cpp | 4 +- utils/TableGen/DAGISelMatcherGen.cpp | 12 +- utils/TableGen/FastISelEmitter.cpp | 8 +- utils/TableGen/FixedLenDecoderEmitter.cpp | 32 +- utils/TableGen/InstrInfoEmitter.cpp | 8 +- utils/TableGen/LLVMCConfigurationEmitter.cpp | 46 +- utils/TableGen/OptParserEmitter.cpp | 16 +- utils/TableGen/PseudoLoweringEmitter.cpp | 12 +- utils/TableGen/PseudoLoweringEmitter.h | 2 +- utils/TableGen/Record.cpp | 496 +++++++++++----------- utils/TableGen/Record.h | 582 +++++++++++++------------- utils/TableGen/RegisterInfoEmitter.cpp | 2 +- utils/TableGen/SetTheory.cpp | 40 +- utils/TableGen/SetTheory.h | 4 +- utils/TableGen/TGParser.cpp | 120 +++--- utils/TableGen/TGParser.h | 20 +- utils/TableGen/X86RecognizableInstr.cpp | 6 +- 30 files changed, 878 insertions(+), 850 deletions(-) diff --git oldutils/TableGen/ARMDecoderEmitter.cpp newutils/TableGen/ARMDecoderEmitter.cpp index 8a5dc8b..f29955a 100644 --- oldutils/TableGen/ARMDecoderEmitter.cpp +++ newutils/TableGen/ARMDecoderEmitter.cpp @@ -114,7 +114,7 @@ enum { /// byteFromBitsInit - Return the byte value from a BitsInit. /// Called from getByteField(). -static uint8_t byteFromBitsInit(BitsInit &init) { +static uint8_t byteFromBitsInit(const BitsInit &init) { int width = init.getNumBits(); assert(width <= 8 && "Field is too large for uint8_t!"); @@ -125,7 +125,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) { uint8_t ret = 0; for (index = 0; index < width; index++) { - if (static_cast(init.getBit(index))->getValue()) + if (static_cast(init.getBit(index))->getValue()) ret |= mask; mask <<= 1; @@ -135,12 +135,12 @@ static uint8_t byteFromBitsInit(BitsInit &init) { } static uint8_t getByteField(const Record &def, const char *str) { - BitsInit *bits = def.getValueAsBitsInit(str); + const BitsInit *bits = def.getValueAsBitsInit(str); return byteFromBitsInit(*bits); } -static BitsInit &getBitsField(const Record &def, const char *str) { - BitsInit *bits = def.getValueAsBitsInit(str); +static const BitsInit &getBitsField(const Record &def, const char *str) { + const BitsInit *bits = def.getValueAsBitsInit(str); return *bits; } @@ -183,15 +183,15 @@ static bool ValueNotSet(bit_value_t V) { static int Value(bit_value_t V) { return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1); } -static bit_value_t bitFromBits(BitsInit &bits, unsigned index) { - if (BitInit *bit = dynamic_cast(bits.getBit(index))) +static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { + if (const BitInit *bit = dynamic_cast(bits.getBit(index))) return bit->getValue() ? BIT_TRUE : BIT_FALSE; // The bit is uninitialized. return BIT_UNSET; } // Prints the bit value for each position. -static void dumpBits(raw_ostream &o, BitsInit &bits) { +static void dumpBits(raw_ostream &o, const BitsInit &bits) { unsigned index; for (index = bits.getNumBits(); index > 0; index--) { @@ -424,7 +424,7 @@ protected: if (AllInstructions[Opcode]->isPseudo) return; - BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); + const BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); for (unsigned i = 0; i < BIT_WIDTH; ++i) Insn[i] = bitFromBits(Bits, i); @@ -1558,7 +1558,7 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, const StringRef Name = Def.getName(); uint8_t Form = getByteField(Def, "Form"); - BitsInit &Bits = getBitsField(Def, "Inst"); + const BitsInit &Bits = getBitsField(Def, "Inst"); // If all the bit positions are not specified; do not decode this instruction. // We are bound to fail! For proper disassembly, the well-known encoding bits diff --git oldutils/TableGen/AsmMatcherEmitter.cpp newutils/TableGen/AsmMatcherEmitter.cpp index a6a4fec..ba7a9c2 100644 --- oldutils/TableGen/AsmMatcherEmitter.cpp +++ newutils/TableGen/AsmMatcherEmitter.cpp @@ -869,7 +869,7 @@ AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, int SubOpIdx) { Record *Rec = OI.Rec; if (SubOpIdx != -1) - Rec = dynamic_cast(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); + Rec = dynamic_cast(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); if (Rec->isSubClassOf("RegisterOperand")) { // RegisterOperand may have an associated ParserMatchClass. If it does, @@ -879,7 +879,7 @@ AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, throw "Record `" + Rec->getName() + "' does not have a ParserMatchClass!\n"; - if (DefInit *DI= dynamic_cast(R->getValue())) { + if (const DefInit *DI= dynamic_cast(R->getValue())) { Record *MatchClass = DI->getDef(); if (ClassInfo *CI = AsmOperandClasses[MatchClass]) return CI; @@ -1046,9 +1046,9 @@ void AsmMatcherInfo::BuildOperandClasses() { ClassInfo *CI = AsmOperandClasses[*it]; CI->Kind = ClassInfo::UserClass0 + Index; - ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); + const ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) { - DefInit *DI = dynamic_cast(Supers->getElement(i)); + const DefInit *DI = dynamic_cast(Supers->getElement(i)); if (!DI) { PrintError((*it)->getLoc(), "Invalid super class reference!"); continue; @@ -1065,28 +1065,28 @@ void AsmMatcherInfo::BuildOperandClasses() { CI->ValueName = (*it)->getName(); // Get or construct the predicate method name. - Init *PMName = (*it)->getValueInit("PredicateMethod"); - if (StringInit *SI = dynamic_cast(PMName)) { + const Init *PMName = (*it)->getValueInit("PredicateMethod"); + if (const StringInit *SI = dynamic_cast(PMName)) { CI->PredicateMethod = SI->getValue(); } else { - assert(dynamic_cast(PMName) && + assert(dynamic_cast(PMName) && "Unexpected PredicateMethod field!"); CI->PredicateMethod = "is" + CI->ClassName; } // Get or construct the render method name. - Init *RMName = (*it)->getValueInit("RenderMethod"); - if (StringInit *SI = dynamic_cast(RMName)) { + const Init *RMName = (*it)->getValueInit("RenderMethod"); + if (const StringInit *SI = dynamic_cast(RMName)) { CI->RenderMethod = SI->getValue(); } else { - assert(dynamic_cast(RMName) && + assert(dynamic_cast(RMName) && "Unexpected RenderMethod field!"); CI->RenderMethod = "add" + CI->ClassName + "Operands"; } // Get the parse method name or leave it as empty. - Init *PRMName = (*it)->getValueInit("ParserMethod"); - if (StringInit *SI = dynamic_cast(PRMName)) + const Init *PRMName = (*it)->getValueInit("ParserMethod"); + if (const StringInit *SI = dynamic_cast(PRMName)) CI->ParserMethod = SI->getValue(); AsmOperandClasses[*it] = CI; diff --git oldutils/TableGen/CallingConvEmitter.cpp newutils/TableGen/CallingConvEmitter.cpp index c51afd8..37758bc 100644 --- oldutils/TableGen/CallingConvEmitter.cpp +++ newutils/TableGen/CallingConvEmitter.cpp @@ -40,7 +40,7 @@ void CallingConvEmitter::run(raw_ostream &O) { void CallingConvEmitter::EmitCallingConv(Record *CC, raw_ostream &O) { - ListInit *CCActions = CC->getValueAsListInit("Actions"); + const ListInit *CCActions = CC->getValueAsListInit("Actions"); Counter = 0; O << "\n\nstatic bool " << CC->getName() @@ -67,7 +67,7 @@ void CallingConvEmitter::EmitAction(Record *Action, O << IndentStr << "if ("; if (Action->isSubClassOf("CCIfType")) { - ListInit *VTs = Action->getValueAsListInit("VTs"); + const ListInit *VTs = Action->getValueAsListInit("VTs"); for (unsigned i = 0, e = VTs->getSize(); i != e; ++i) { Record *VT = VTs->getElementAsRecord(i); if (i != 0) O << " ||\n " << IndentStr; @@ -91,7 +91,7 @@ void CallingConvEmitter::EmitAction(Record *Action, << "(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))\n" << IndentStr << " return false;\n"; } else if (Action->isSubClassOf("CCAssignToReg")) { - ListInit *RegList = Action->getValueAsListInit("RegList"); + const ListInit *RegList = Action->getValueAsListInit("RegList"); if (RegList->getSize() == 1) { O << IndentStr << "if (unsigned Reg = State.AllocateReg("; O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; @@ -112,8 +112,8 @@ void CallingConvEmitter::EmitAction(Record *Action, O << IndentStr << " return false;\n"; O << IndentStr << "}\n"; } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) { - ListInit *RegList = Action->getValueAsListInit("RegList"); - ListInit *ShadowRegList = Action->getValueAsListInit("ShadowRegList"); + const ListInit *RegList = Action->getValueAsListInit("RegList"); + const ListInit *ShadowRegList = Action->getValueAsListInit("ShadowRegList"); if (ShadowRegList->getSize() >0 && ShadowRegList->getSize() != RegList->getSize()) throw "Invalid length of list of shadowed registers"; diff --git oldutils/TableGen/ClangAttrEmitter.cpp newutils/TableGen/ClangAttrEmitter.cpp index 4116ce6..bca4bb6 100644 --- oldutils/TableGen/ClangAttrEmitter.cpp +++ newutils/TableGen/ClangAttrEmitter.cpp @@ -21,7 +21,7 @@ using namespace llvm; static const std::vector getValueAsListOfStrings(Record &R, StringRef FieldName) { - ListInit *List = R.getValueAsListInit(FieldName); + const ListInit *List = R.getValueAsListInit(FieldName); assert (List && "Got a null ListInit"); std::vector Strings; @@ -31,9 +31,9 @@ getValueAsListOfStrings(Record &R, StringRef FieldName) { i != e; ++i) { assert(*i && "Got a null element in a ListInit"); - if (StringInit *S = dynamic_cast(*i)) + if (const StringInit *S = dynamic_cast(*i)) Strings.push_back(S->getValue()); - else if (CodeInit *C = dynamic_cast(*i)) + else if (const CodeInit *C = dynamic_cast(*i)) Strings.push_back(C->getValue()); else assert(false && "Got a non-string, non-code element in a ListInit"); diff --git oldutils/TableGen/ClangDiagnosticsEmitter.cpp newutils/TableGen/ClangDiagnosticsEmitter.cpp index 0a48e75..2ef1e8b 100644 --- oldutils/TableGen/ClangDiagnosticsEmitter.cpp +++ newutils/TableGen/ClangDiagnosticsEmitter.cpp @@ -74,7 +74,7 @@ getCategoryFromDiagGroup(const Record *Group, static std::string getDiagnosticCategory(const Record *R, DiagGroupParentMap &DiagGroupParents) { // If the diagnostic is in a group, and that group has a category, use it. - if (DefInit *Group = dynamic_cast(R->getValueInit("Group"))) { + if (const DefInit *Group = dynamic_cast(R->getValueInit("Group"))) { // Check the diagnostic's diag group for a category. std::string CatName = getCategoryFromDiagGroup(Group->getDef(), DiagGroupParents); @@ -159,7 +159,7 @@ void ClangDiagsDefsEmitter::run(raw_ostream &OS) { OS.write_escaped(R.getValueAsString("Text")) << '"'; // Warning associated with the diagnostic. - if (DefInit *DI = dynamic_cast(R.getValueInit("Group"))) { + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) { OS << ", \""; OS.write_escaped(DI->getDef()->getValueAsString("GroupName")) << '"'; } else { @@ -225,7 +225,7 @@ void ClangDiagGroupsEmitter::run(raw_ostream &OS) { Records.getAllDerivedDefinitions("Diagnostic"); for (unsigned i = 0, e = Diags.size(); i != e; ++i) { const Record *R = Diags[i]; - DefInit *DI = dynamic_cast(R->getValueInit("Group")); + const DefInit *DI = dynamic_cast(R->getValueInit("Group")); if (DI == 0) continue; std::string GroupName = DI->getDef()->getValueAsString("GroupName"); DiagsInGroup[GroupName].DiagsInGroup.push_back(R); diff --git oldutils/TableGen/ClangSACheckersEmitter.cpp newutils/TableGen/ClangSACheckersEmitter.cpp index 97739c6..d509173 100644 --- oldutils/TableGen/ClangSACheckersEmitter.cpp +++ newutils/TableGen/ClangSACheckersEmitter.cpp @@ -28,7 +28,7 @@ static bool isHidden(const Record &R) { if (R.getValueAsBit("Hidden")) return true; // Not declared as hidden, check the parent package if it is hidden. - if (DefInit *DI = dynamic_cast(R.getValueInit("ParentPackage"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("ParentPackage"))) return isHidden(*DI->getDef()); return false; @@ -42,7 +42,7 @@ static std::string getPackageFullName(const Record *R); static std::string getParentPackageFullName(const Record *R) { std::string name; - if (DefInit *DI = dynamic_cast(R->getValueInit("ParentPackage"))) + if (const DefInit *DI = dynamic_cast(R->getValueInit("ParentPackage"))) name = getPackageFullName(DI->getDef()); return name; } @@ -63,8 +63,8 @@ static std::string getCheckerFullName(const Record *R) { } static std::string getStringValue(const Record &R, StringRef field) { - if (StringInit * - SI = dynamic_cast(R.getValueInit(field))) + if (const StringInit * + SI = dynamic_cast(R.getValueInit(field))) return SI->getValue(); return std::string(); } @@ -129,8 +129,8 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = checkers.size(); i != e; ++i) { Record *R = checkers[i]; Record *package = 0; - if (DefInit * - DI = dynamic_cast(R->getValueInit("ParentPackage"))) + if (const DefInit * + DI = dynamic_cast(R->getValueInit("ParentPackage"))) package = DI->getDef(); if (!isCheckerNamed(R) && !package) throw "Checker '" + R->getName() + "' is neither named, nor in a package!"; @@ -149,21 +149,21 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { Record *currR = isCheckerNamed(R) ? R : package; // Insert the checker and its parent packages into the subgroups set of // the corresponding parent package. - while (DefInit *DI - = dynamic_cast(currR->getValueInit("ParentPackage"))) { + while (const DefInit *DI + = dynamic_cast(currR->getValueInit("ParentPackage"))) { Record *parentPackage = DI->getDef(); recordGroupMap[parentPackage]->SubGroups.insert(currR); currR = parentPackage; } // Insert the checker into the set of its group. - if (DefInit *DI = dynamic_cast(R->getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(R->getValueInit("Group"))) recordGroupMap[DI->getDef()]->Checkers.insert(R); } // If a package is in group, add all its checkers and its sub-packages // checkers into the group. for (unsigned i = 0, e = packages.size(); i != e; ++i) - if (DefInit *DI = dynamic_cast(packages[i]->getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(packages[i]->getValueInit("Group"))) addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap); typedef std::map SortedRecords; @@ -204,7 +204,7 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { OS << "PACKAGE(" << "\""; OS.write_escaped(getPackageFullName(&R)) << "\", "; // Group index - if (DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) OS << groupToSortIndex[DI->getDef()] << ", "; else OS << "-1, "; @@ -232,7 +232,7 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { OS << "\""; OS.write_escaped(getStringValue(R, "HelpText")) << "\", "; // Group index - if (DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) OS << groupToSortIndex[DI->getDef()] << ", "; else OS << "-1, "; diff --git oldutils/TableGen/CodeEmitterGen.cpp newutils/TableGen/CodeEmitterGen.cpp index 8b5cdda..c11e4d0 100644 --- oldutils/TableGen/CodeEmitterGen.cpp +++ newutils/TableGen/CodeEmitterGen.cpp @@ -38,16 +38,16 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { R->getValueAsBit("isPseudo")) continue; - BitsInit *BI = R->getValueAsBitsInit("Inst"); + const BitsInit *BI = R->getValueAsBitsInit("Inst"); unsigned numBits = BI->getNumBits(); - SmallVector NewBits(numBits); + SmallVector NewBits(numBits); for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { unsigned bitSwapIdx = numBits - bit - 1; - Init *OrigBit = BI->getBit(bit); - Init *BitSwap = BI->getBit(bitSwapIdx); + const Init *OrigBit = BI->getBit(bit); + const Init *BitSwap = BI->getBit(bitSwapIdx); NewBits[bit] = BitSwap; NewBits[bitSwapIdx] = OrigBit; } @@ -56,7 +56,7 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { NewBits[middle] = BI->getBit(middle); } - BitsInit *NewBI = new BitsInit(ArrayRef(NewBits)); + BitsInit *NewBI = new BitsInit(ArrayRef(NewBits)); // Update the bits in reversed order so that emitInstrOpBits will get the // correct endianness. @@ -67,12 +67,12 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { // If the VarBitInit at position 'bit' matches the specified variable then // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, - BitsInit *BI, int bit) { - if (VarBitInit *VBI = dynamic_cast(BI->getBit(bit))) { - if (VarInit *VI = dynamic_cast(VBI->getVariable())) + const BitsInit *BI, int bit) { + if (const VarBitInit *VBI = dynamic_cast(BI->getBit(bit))) { + if (const VarInit *VI = dynamic_cast(VBI->getVariable())) if (VI->getName() == VarName) return VBI->getBitNum(); - } else if (VarInit *VI = dynamic_cast(BI->getBit(bit))) { + } else if (const VarInit *VI = dynamic_cast(BI->getBit(bit))) { if (VI->getName() == VarName) return 0; } @@ -81,7 +81,7 @@ int CodeEmitterGen::getVariableBit(const std::string &VarName, } void CodeEmitterGen:: -AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, +AddCodeToMergeInOperand(Record *R, const BitsInit *BI, const std::string &VarName, unsigned &NumberedOp, std::string &Case, CodeGenTarget &Target) { CodeGenInstruction &CGI = Target.getInstruction(R); @@ -185,7 +185,7 @@ std::string CodeEmitterGen::getInstructionCase(Record *R, CodeGenTarget &Target) { std::string Case; - BitsInit *BI = R->getValueAsBitsInit("Inst"); + const BitsInit *BI = R->getValueAsBitsInit("Inst"); const std::vector &Vals = R->getValues(); unsigned NumberedOp = 0; @@ -242,12 +242,12 @@ void CodeEmitterGen::run(raw_ostream &o) { continue; } - BitsInit *BI = R->getValueAsBitsInit("Inst"); + const BitsInit *BI = R->getValueAsBitsInit("Inst"); // Start by filling in fixed values. unsigned Value = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) + if (const BitInit *B = dynamic_cast(BI->getBit(e-i-1))) Value |= B->getValue() << (e-i-1); } o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n"; diff --git oldutils/TableGen/CodeEmitterGen.h newutils/TableGen/CodeEmitterGen.h index a874d97..1f841c3 100644 --- oldutils/TableGen/CodeEmitterGen.h +++ newutils/TableGen/CodeEmitterGen.h @@ -35,10 +35,10 @@ private: void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace); void emitGetValueBit(raw_ostream &o, const std::string &Namespace); void reverseBits(std::vector &Insts); - int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); + int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit); std::string getInstructionCase(Record *R, CodeGenTarget &Target); void - AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, + AddCodeToMergeInOperand(Record *R, const BitsInit *BI, const std::string &VarName, unsigned &NumberedOp, std::string &Case, CodeGenTarget &Target); diff --git oldutils/TableGen/CodeGenDAGPatterns.cpp newutils/TableGen/CodeGenDAGPatterns.cpp index 16585f7..2a75849 100644 --- oldutils/TableGen/CodeGenDAGPatterns.cpp +++ newutils/TableGen/CodeGenDAGPatterns.cpp @@ -583,7 +583,7 @@ typedef DepVarMap::const_iterator DepVarMap_citer; static void FindDepVarsOf(TreePatternNode *N, DepVarMap &DepMap) { if (N->isLeaf()) { - if (dynamic_cast(N->getLeafValue()) != NULL) + if (dynamic_cast(N->getLeafValue()) != NULL) DepMap[N->getName()]++; } else { for (size_t i = 0, e = N->getNumChildren(); i != e; ++i) @@ -692,7 +692,7 @@ static unsigned getPatternSize(const TreePatternNode *P, unsigned Size = 3; // The node itself. // If the root node is a ConstantSDNode, increases its size. // e.g. (set R32:$dst, 0). - if (P->isLeaf() && dynamic_cast(P->getLeafValue())) + if (P->isLeaf() && dynamic_cast(P->getLeafValue())) Size += 2; // FIXME: This is a hack to statically increase the priority of patterns @@ -716,7 +716,7 @@ static unsigned getPatternSize(const TreePatternNode *P, Child->getType(0) != MVT::Other) Size += getPatternSize(Child, CGP); else if (Child->isLeaf()) { - if (dynamic_cast(Child->getLeafValue())) + if (dynamic_cast(Child->getLeafValue())) Size += 5; // Matches a ConstantSDNode (+3) and a specific value (+2). else if (Child->getComplexPatternInfo(CGP)) Size += getPatternSize(Child, CGP); @@ -742,7 +742,7 @@ getPatternComplexity(const CodeGenDAGPatterns &CGP) const { std::string PatternToMatch::getPredicateCheck() const { std::string PredicateCheck; for (unsigned i = 0, e = Predicates->getSize(); i != e; ++i) { - if (DefInit *Pred = dynamic_cast(Predicates->getElement(i))) { + if (const DefInit *Pred = dynamic_cast(Predicates->getElement(i))) { Record *Def = Pred->getDef(); if (!Def->isSubClassOf("Predicate")) { #ifndef NDEBUG @@ -866,12 +866,12 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N, // The NodeToApply must be a leaf node that is a VT. OtherOperandNum must // have an integer type that is smaller than the VT. if (!NodeToApply->isLeaf() || - !dynamic_cast(NodeToApply->getLeafValue()) || - !static_cast(NodeToApply->getLeafValue())->getDef() + !dynamic_cast(NodeToApply->getLeafValue()) || + !static_cast(NodeToApply->getLeafValue())->getDef() ->isSubClassOf("ValueType")) TP.error(N->getOperator()->getName() + " expects a VT operand!"); MVT::SimpleValueType VT = - getValueType(static_cast(NodeToApply->getLeafValue())->getDef()); + getValueType(static_cast(NodeToApply->getLeafValue())->getDef()); EEVT::TypeSet TypeListTmp(VT, TP); @@ -1021,10 +1021,10 @@ static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) { return PFRec->getOnlyTree()->getNumTypes(); // Get the result tree. - DagInit *Tree = Operator->getValueAsDag("Fragment"); + const DagInit *Tree = Operator->getValueAsDag("Fragment"); Record *Op = 0; - if (Tree && dynamic_cast(Tree->getOperator())) - Op = dynamic_cast(Tree->getOperator())->getDef(); + if (Tree && dynamic_cast(Tree->getOperator())) + Op = dynamic_cast(Tree->getOperator())->getDef(); assert(Op && "Invalid Fragment"); return GetNumNodeResults(Op, CDP); } @@ -1098,8 +1098,8 @@ bool TreePatternNode::isIsomorphicTo(const TreePatternNode *N, return false; if (isLeaf()) { - if (DefInit *DI = dynamic_cast(getLeafValue())) { - if (DefInit *NDI = dynamic_cast(N->getLeafValue())) { + if (const DefInit *DI = dynamic_cast(getLeafValue())) { + if (const DefInit *NDI = dynamic_cast(N->getLeafValue())) { return ((DI->getDef() == NDI->getDef()) && (DepVars.find(getName()) == DepVars.end() || getName() == N->getName())); @@ -1155,9 +1155,9 @@ SubstituteFormalArguments(std::map &ArgMap) { for (unsigned i = 0, e = getNumChildren(); i != e; ++i) { TreePatternNode *Child = getChild(i); if (Child->isLeaf()) { - Init *Val = Child->getLeafValue(); - if (dynamic_cast(Val) && - static_cast(Val)->getDef()->getName() == "node") { + const Init *Val = Child->getLeafValue(); + if (dynamic_cast(Val) && + static_cast(Val)->getDef()->getName() == "node") { // We found a use of a formal argument, replace it with its value. TreePatternNode *NewChild = ArgMap[Child->getName()]; assert(NewChild && "Couldn't find formal argument!"); @@ -1319,7 +1319,7 @@ getIntrinsicInfo(const CodeGenDAGPatterns &CDP) const { return 0; unsigned IID = - dynamic_cast(getChild(0)->getLeafValue())->getValue(); + dynamic_cast(getChild(0)->getLeafValue())->getValue(); return &CDP.getIntrinsicInfo(IID); } @@ -1329,7 +1329,7 @@ const ComplexPattern * TreePatternNode::getComplexPatternInfo(const CodeGenDAGPatterns &CGP) const { if (!isLeaf()) return 0; - DefInit *DI = dynamic_cast(getLeafValue()); + const DefInit *DI = dynamic_cast(getLeafValue()); if (DI && DI->getDef()->isSubClassOf("ComplexPattern")) return &CGP.getComplexPattern(DI->getDef()); return 0; @@ -1382,7 +1382,7 @@ TreePatternNode::isCommutativeIntrinsic(const CodeGenDAGPatterns &CDP) const { bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { CodeGenDAGPatterns &CDP = TP.getDAGPatterns(); if (isLeaf()) { - if (DefInit *DI = dynamic_cast(getLeafValue())) { + if (const DefInit *DI = dynamic_cast(getLeafValue())) { // If it's a regclass or something else known, include the type. bool MadeChange = false; for (unsigned i = 0, e = Types.size(); i != e; ++i) @@ -1391,7 +1391,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { return MadeChange; } - if (IntInit *II = dynamic_cast(getLeafValue())) { + if (const IntInit *II = dynamic_cast(getLeafValue())) { assert(Types.size() == 1 && "Invalid IntInit"); // Int inits are always integers. :) @@ -1651,7 +1651,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { static bool OnlyOnRHSOfCommutative(TreePatternNode *N) { if (!N->isLeaf() && N->getOperator()->getName() == "imm") return true; - if (N->isLeaf() && dynamic_cast(N->getLeafValue())) + if (N->isLeaf() && dynamic_cast(N->getLeafValue())) return true; return false; } @@ -1701,14 +1701,14 @@ bool TreePatternNode::canPatternMatch(std::string &Reason, // TreePattern implementation // -TreePattern::TreePattern(Record *TheRec, ListInit *RawPat, bool isInput, +TreePattern::TreePattern(Record *TheRec, const ListInit *RawPat, bool isInput, CodeGenDAGPatterns &cdp) : TheRecord(TheRec), CDP(cdp){ isInputPattern = isInput; for (unsigned i = 0, e = RawPat->getSize(); i != e; ++i) Trees.push_back(ParseTreePattern(RawPat->getElement(i), "")); } -TreePattern::TreePattern(Record *TheRec, DagInit *Pat, bool isInput, +TreePattern::TreePattern(Record *TheRec, const DagInit *Pat, bool isInput, CodeGenDAGPatterns &cdp) : TheRecord(TheRec), CDP(cdp){ isInputPattern = isInput; Trees.push_back(ParseTreePattern(Pat, "")); @@ -1739,8 +1739,8 @@ void TreePattern::ComputeNamedNodes(TreePatternNode *N) { } -TreePatternNode *TreePattern::ParseTreePattern(Init *TheInit, StringRef OpName){ - if (DefInit *DI = dynamic_cast(TheInit)) { +TreePatternNode *TreePattern::ParseTreePattern(const Init *TheInit, StringRef OpName){ + if (const DefInit *DI = dynamic_cast(TheInit)) { Record *R = DI->getDef(); // Direct reference to a leaf DagNode or PatFrag? Turn it into a @@ -1748,7 +1748,7 @@ TreePatternNode *TreePattern::ParseTreePattern(Init *TheInit, StringRef OpName){ /// (foo GPR, imm) -> (foo GPR, (imm)) if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) return ParseTreePattern(new DagInit(DI, "", - std::vector >()), + std::vector >()), OpName); // Input argument? @@ -1763,26 +1763,26 @@ TreePatternNode *TreePattern::ParseTreePattern(Init *TheInit, StringRef OpName){ return Res; } - if (IntInit *II = dynamic_cast(TheInit)) { + if (const IntInit *II = dynamic_cast(TheInit)) { if (!OpName.empty()) error("Constant int argument should not have a name!"); return new TreePatternNode(II, 1); } - if (BitsInit *BI = dynamic_cast(TheInit)) { + if (const BitsInit *BI = dynamic_cast(TheInit)) { // Turn this into an IntInit. - Init *II = BI->convertInitializerTo(IntRecTy::get()); - if (II == 0 || !dynamic_cast(II)) + const Init *II = BI->convertInitializerTo(IntRecTy::get()); + if (II == 0 || !dynamic_cast(II)) error("Bits value must be constants!"); return ParseTreePattern(II, OpName); } - DagInit *Dag = dynamic_cast(TheInit); + const DagInit *Dag = dynamic_cast(TheInit); if (!Dag) { TheInit->dump(); error("Pattern has unexpected init kind!"); } - DefInit *OpDef = dynamic_cast(Dag->getOperator()); + const DefInit *OpDef = dynamic_cast(Dag->getOperator()); if (!OpDef) error("Pattern has unexpected operator type!"); Record *Operator = OpDef->getDef(); @@ -1947,7 +1947,7 @@ InferAllTypes(const StringMap > *InNamedTypes) { // us to match things like: // def : Pat<(v1i64 (bitconvert(v2i32 DPR:$src))), (v1i64 DPR:$src)>; if (Nodes[i] == Trees[0] && Nodes[i]->isLeaf()) { - DefInit *DI = dynamic_cast(Nodes[i]->getLeafValue()); + const DefInit *DI = dynamic_cast(Nodes[i]->getLeafValue()); if (DI && (DI->getDef()->isSubClassOf("RegisterClass") || DI->getDef()->isSubClassOf("RegisterOperand"))) continue; @@ -2096,7 +2096,7 @@ void CodeGenDAGPatterns::ParsePatternFragments() { // First step, parse all of the fragments. for (unsigned i = 0, e = Fragments.size(); i != e; ++i) { - DagInit *Tree = Fragments[i]->getValueAsDag("Fragment"); + const DagInit *Tree = Fragments[i]->getValueAsDag("Fragment"); TreePattern *P = new TreePattern(Fragments[i], Tree, true, *this); PatternFragments[Fragments[i]] = P; @@ -2108,8 +2108,8 @@ void CodeGenDAGPatterns::ParsePatternFragments() { P->error("Cannot have unnamed 'node' values in pattern fragment!"); // Parse the operands list. - DagInit *OpsList = Fragments[i]->getValueAsDag("Operands"); - DefInit *OpsOp = dynamic_cast(OpsList->getOperator()); + const DagInit *OpsList = Fragments[i]->getValueAsDag("Operands"); + const DefInit *OpsOp = dynamic_cast(OpsList->getOperator()); // Special cases: ops == outs == ins. Different names are used to // improve readability. if (!OpsOp || @@ -2121,8 +2121,8 @@ void CodeGenDAGPatterns::ParsePatternFragments() { // Copy over the arguments. Args.clear(); for (unsigned j = 0, e = OpsList->getNumArgs(); j != e; ++j) { - if (!dynamic_cast(OpsList->getArg(j)) || - static_cast(OpsList->getArg(j))-> + if (!dynamic_cast(OpsList->getArg(j)) || + static_cast(OpsList->getArg(j))-> getDef()->getName() != "node") P->error("Operands list should all be 'node' values."); if (OpsList->getArgName(j).empty()) @@ -2180,19 +2180,19 @@ void CodeGenDAGPatterns::ParseDefaultOperands() { // Find some SDNode. assert(!SDNodes.empty() && "No SDNodes parsed?"); - Init *SomeSDNode = DefInit::get(SDNodes.begin()->first); + const Init *SomeSDNode = DefInit::get(SDNodes.begin()->first); for (unsigned iter = 0; iter != 2; ++iter) { for (unsigned i = 0, e = DefaultOps[iter].size(); i != e; ++i) { - DagInit *DefaultInfo = DefaultOps[iter][i]->getValueAsDag("DefaultOps"); + const DagInit *DefaultInfo = DefaultOps[iter][i]->getValueAsDag("DefaultOps"); // Clone the DefaultInfo dag node, changing the operator from 'ops' to // SomeSDnode so that we can parse this. - std::vector > Ops; + std::vector > Ops; for (unsigned op = 0, e = DefaultInfo->getNumArgs(); op != e; ++op) Ops.push_back(std::make_pair(DefaultInfo->getArg(op), DefaultInfo->getArgName(op))); - DagInit *DI = new DagInit(SomeSDNode, "", Ops); + const DagInit *DI = new DagInit(SomeSDNode, "", Ops); // Create a TreePattern to parse this. TreePattern P(DefaultOps[iter][i], DI, false, *this); @@ -2231,7 +2231,7 @@ static bool HandleUse(TreePattern *I, TreePatternNode *Pat, // No name -> not interesting. if (Pat->getName().empty()) { if (Pat->isLeaf()) { - DefInit *DI = dynamic_cast(Pat->getLeafValue()); + const DefInit *DI = dynamic_cast(Pat->getLeafValue()); if (DI && (DI->getDef()->isSubClassOf("RegisterClass") || DI->getDef()->isSubClassOf("RegisterOperand"))) I->error("Input " + DI->getDef()->getName() + " must be named!"); @@ -2241,7 +2241,7 @@ static bool HandleUse(TreePattern *I, TreePatternNode *Pat, Record *Rec; if (Pat->isLeaf()) { - DefInit *DI = dynamic_cast(Pat->getLeafValue()); + const DefInit *DI = dynamic_cast(Pat->getLeafValue()); if (!DI) I->error("Input $" + Pat->getName() + " must be an identifier!"); Rec = DI->getDef(); } else { @@ -2259,7 +2259,7 @@ static bool HandleUse(TreePattern *I, TreePatternNode *Pat, } Record *SlotRec; if (Slot->isLeaf()) { - SlotRec = dynamic_cast(Slot->getLeafValue())->getDef(); + SlotRec = dynamic_cast(Slot->getLeafValue())->getDef(); } else { assert(Slot->getNumChildren() == 0 && "can't be a use with children!"); SlotRec = Slot->getOperator(); @@ -2294,7 +2294,7 @@ FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat, if (!Dest->isLeaf()) I->error("implicitly defined value should be a register!"); - DefInit *Val = dynamic_cast(Dest->getLeafValue()); + const DefInit *Val = dynamic_cast(Dest->getLeafValue()); if (!Val || !Val->getDef()->isSubClassOf("Register")) I->error("implicitly defined value should be a register!"); InstImpResults.push_back(Val->getDef()); @@ -2335,7 +2335,7 @@ FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat, if (!Dest->isLeaf()) I->error("set destination should be a register!"); - DefInit *Val = dynamic_cast(Dest->getLeafValue()); + const DefInit *Val = dynamic_cast(Dest->getLeafValue()); if (!Val) I->error("set destination should be a register!"); @@ -2401,7 +2401,7 @@ private: return false; const TreePatternNode *N0 = N->getChild(0); - if (!N0->isLeaf() || !dynamic_cast(N0->getLeafValue())) + if (!N0->isLeaf() || !dynamic_cast(N0->getLeafValue())) return false; const TreePatternNode *N1 = N->getChild(1); @@ -2418,7 +2418,7 @@ private: void AnalyzeNode(const TreePatternNode *N) { if (N->isLeaf()) { - if (DefInit *DI = dynamic_cast(N->getLeafValue())) { + if (const DefInit *DI = dynamic_cast(N->getLeafValue())) { Record *LeafRec = DI->getDef(); // Handle ComplexPattern leaves. if (LeafRec->isSubClassOf("ComplexPattern")) { @@ -2525,9 +2525,9 @@ void CodeGenDAGPatterns::ParseInstructions() { std::vector Instrs = Records.getAllDerivedDefinitions("Instruction"); for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { - ListInit *LI = 0; + const ListInit *LI = 0; - if (dynamic_cast(Instrs[i]->getValueInit("Pattern"))) + if (dynamic_cast(Instrs[i]->getValueInit("Pattern"))) LI = Instrs[i]->getValueAsListInit("Pattern"); // If there is no pattern, only collect minimal information about the @@ -2619,7 +2619,7 @@ void CodeGenDAGPatterns::ParseInstructions() { if (i == 0) Res0Node = RNode; - Record *R = dynamic_cast(RNode->getLeafValue())->getDef(); + Record *R = dynamic_cast(RNode->getLeafValue())->getDef(); if (R == 0) I->error("Operand $" + OpName + " should be a set destination: all " "outputs must occur before inputs in operand list!"); @@ -2664,8 +2664,8 @@ void CodeGenDAGPatterns::ParseInstructions() { InstInputsCheck.erase(OpName); // It occurred, remove from map. if (InVal->isLeaf() && - dynamic_cast(InVal->getLeafValue())) { - Record *InRec = static_cast(InVal->getLeafValue())->getDef(); + dynamic_cast(InVal->getLeafValue())) { + Record *InRec = static_cast(InVal->getLeafValue())->getDef(); if (Op.Rec != InRec && !InRec->isSubClassOf("ComplexPattern")) I->error("Operand $" + OpName + "'s register class disagrees" " between the operand and pattern"); @@ -2865,13 +2865,13 @@ void CodeGenDAGPatterns::ParsePatterns() { for (unsigned i = 0, e = Patterns.size(); i != e; ++i) { Record *CurPattern = Patterns[i]; - DagInit *Tree = CurPattern->getValueAsDag("PatternToMatch"); + const DagInit *Tree = CurPattern->getValueAsDag("PatternToMatch"); TreePattern *Pattern = new TreePattern(CurPattern, Tree, true, *this); // Inline pattern fragments into it. Pattern->InlinePatternFragments(); - ListInit *LI = CurPattern->getValueAsListInit("ResultInstrs"); + const ListInit *LI = CurPattern->getValueAsListInit("ResultInstrs"); if (LI->getSize() == 0) continue; // no pattern. // Parse the instruction. @@ -3183,7 +3183,7 @@ static void GenerateVariantsOf(TreePatternNode *N, for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) { TreePatternNode *Child = N->getChild(i); if (Child->isLeaf()) - if (DefInit *DI = dynamic_cast(Child->getLeafValue())) { + if (const DefInit *DI = dynamic_cast(Child->getLeafValue())) { Record *RR = DI->getDef(); if (RR->isSubClassOf("Register")) continue; diff --git oldutils/TableGen/CodeGenDAGPatterns.h newutils/TableGen/CodeGenDAGPatterns.h index 936fd01..833eef0 100644 --- oldutils/TableGen/CodeGenDAGPatterns.h +++ newutils/TableGen/CodeGenDAGPatterns.h @@ -306,7 +306,7 @@ class TreePatternNode { /// Val - The init value (e.g. the "GPRC" record, or "7") for a leaf. /// - Init *Val; + const Init *Val; /// Name - The name given to this node with the :$foo notation. /// @@ -327,7 +327,7 @@ public: : Operator(Op), Val(0), TransformFn(0), Children(Ch) { Types.resize(NumResults); } - TreePatternNode(Init *val, unsigned NumResults) // leaf ctor + TreePatternNode(const Init *val, unsigned NumResults) // leaf ctor : Operator(0), Val(val), TransformFn(0) { Types.resize(NumResults); } @@ -358,7 +358,7 @@ public: return Types[ResNo].isDynamicallyResolved(); } - Init *getLeafValue() const { assert(isLeaf()); return Val; } + const Init *getLeafValue() const { assert(isLeaf()); return Val; } Record *getOperator() const { assert(!isLeaf()); return Operator; } unsigned getNumChildren() const { return Children.size(); } @@ -517,9 +517,9 @@ public: /// TreePattern constructor - Parse the specified DagInits into the /// current record. - TreePattern(Record *TheRec, ListInit *RawPat, bool isInput, + TreePattern(Record *TheRec, const ListInit *RawPat, bool isInput, CodeGenDAGPatterns &ise); - TreePattern(Record *TheRec, DagInit *Pat, bool isInput, + TreePattern(Record *TheRec, const DagInit *Pat, bool isInput, CodeGenDAGPatterns &ise); TreePattern(Record *TheRec, TreePatternNode *Pat, bool isInput, CodeGenDAGPatterns &ise); @@ -576,7 +576,7 @@ public: void dump() const; private: - TreePatternNode *ParseTreePattern(Init *DI, StringRef OpName); + TreePatternNode *ParseTreePattern(const Init *DI, StringRef OpName); void ComputeNamedNodes(); void ComputeNamedNodes(TreePatternNode *N); }; @@ -631,7 +631,7 @@ public: /// processed to produce isel. class PatternToMatch { public: - PatternToMatch(Record *srcrecord, ListInit *preds, + PatternToMatch(Record *srcrecord, const ListInit *preds, TreePatternNode *src, TreePatternNode *dst, const std::vector &dstregs, unsigned complexity, unsigned uid) @@ -639,7 +639,7 @@ public: Dstregs(dstregs), AddedComplexity(complexity), ID(uid) {} Record *SrcRecord; // Originating Record for the pattern. - ListInit *Predicates; // Top level predicate conditions to match. + const ListInit *Predicates; // Top level predicate conditions to match. TreePatternNode *SrcPattern; // Source pattern to match. TreePatternNode *DstPattern; // Resulting pattern. std::vector Dstregs; // Physical register defs being matched. @@ -647,7 +647,7 @@ public: unsigned ID; // Unique ID for the record. Record *getSrcRecord() const { return SrcRecord; } - ListInit *getPredicates() const { return Predicates; } + const ListInit *getPredicates() const { return Predicates; } TreePatternNode *getSrcPattern() const { return SrcPattern; } TreePatternNode *getDstPattern() const { return DstPattern; } const std::vector &getDstRegs() const { return Dstregs; } diff --git oldutils/TableGen/CodeGenInstruction.cpp newutils/TableGen/CodeGenInstruction.cpp index a52ce86c..469e25b 100644 --- oldutils/TableGen/CodeGenInstruction.cpp +++ newutils/TableGen/CodeGenInstruction.cpp @@ -30,9 +30,9 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { hasOptionalDef = false; isVariadic = false; - DagInit *OutDI = R->getValueAsDag("OutOperandList"); + const DagInit *OutDI = R->getValueAsDag("OutOperandList"); - if (DefInit *Init = dynamic_cast(OutDI->getOperator())) { + if (const DefInit *Init = dynamic_cast(OutDI->getOperator())) { if (Init->getDef()->getName() != "outs") throw R->getName() + ": invalid def name for output list: use 'outs'"; } else @@ -40,8 +40,8 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { NumDefs = OutDI->getNumArgs(); - DagInit *InDI = R->getValueAsDag("InOperandList"); - if (DefInit *Init = dynamic_cast(InDI->getOperator())) { + const DagInit *InDI = R->getValueAsDag("InOperandList"); + if (const DefInit *Init = dynamic_cast(InDI->getOperator())) { if (Init->getDef()->getName() != "ins") throw R->getName() + ": invalid def name for input list: use 'ins'"; } else @@ -50,7 +50,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { unsigned MIOperandNo = 0; std::set OperandNames; for (unsigned i = 0, e = InDI->getNumArgs()+OutDI->getNumArgs(); i != e; ++i){ - Init *ArgInit; + const Init *ArgInit; std::string ArgName; if (i < NumDefs) { ArgInit = OutDI->getArg(i); @@ -60,7 +60,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { ArgName = InDI->getArgName(i-NumDefs); } - DefInit *Arg = dynamic_cast(ArgInit); + const DefInit *Arg = dynamic_cast(ArgInit); if (!Arg) throw "Illegal operand for the '" + R->getName() + "' instruction!"; @@ -69,7 +69,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { std::string EncoderMethod; std::string OperandType = "OPERAND_UNKNOWN"; unsigned NumOps = 1; - DagInit *MIOpInfo = 0; + const DagInit *MIOpInfo = 0; if (Rec->isSubClassOf("RegisterOperand")) { PrintMethod = Rec->getValueAsString("PrintMethod"); } else if (Rec->isSubClassOf("Operand")) { @@ -80,8 +80,8 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { MIOpInfo = Rec->getValueAsDag("MIOperandInfo"); // Verify that MIOpInfo has an 'ops' root value. - if (!dynamic_cast(MIOpInfo->getOperator()) || - dynamic_cast(MIOpInfo->getOperator()) + if (!dynamic_cast(MIOpInfo->getOperator()) || + dynamic_cast(MIOpInfo->getOperator()) ->getDef()->getName() != "ops") throw "Bad value for MIOperandInfo in operand '" + Rec->getName() + "'\n"; @@ -182,7 +182,7 @@ CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) { } // Find the suboperand number involved. - DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; + const DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; if (MIOpInfo == 0) throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'"; @@ -404,12 +404,12 @@ FlattenAsmStringVariants(StringRef Cur, unsigned Variant) { /// constructor. It checks if an argument in an InstAlias pattern matches /// the corresponding operand of the instruction. It returns true on a /// successful match, with ResOp set to the result operand to be used. -bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, +bool CodeGenInstAlias::tryAliasOpMatch(const DagInit *Result, unsigned AliasOpNo, Record *InstOpRec, bool hasSubOps, SMLoc Loc, CodeGenTarget &T, ResultOperand &ResOp) { - Init *Arg = Result->getArg(AliasOpNo); - DefInit *ADI = dynamic_cast(Arg); + const Init *Arg = Result->getArg(AliasOpNo); + const DefInit *ADI = dynamic_cast(Arg); if (ADI && ADI->getDef() == InstOpRec) { // If the operand is a record, it must have a name, and the record type @@ -455,7 +455,7 @@ bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, return true; } - if (IntInit *II = dynamic_cast(Arg)) { + if (const IntInit *II = dynamic_cast(Arg)) { if (hasSubOps || !InstOpRec->isSubClassOf("Operand")) return false; // Integer arguments can't have names. @@ -474,7 +474,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) { Result = R->getValueAsDag("ResultInst"); // Verify that the root of the result is an instruction. - DefInit *DI = dynamic_cast(Result->getOperator()); + const DefInit *DI = dynamic_cast(Result->getOperator()); if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction")) throw TGError(R->getLoc(), "result of inst alias should be an instruction"); @@ -484,7 +484,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) { // the same class. StringMap NameClass; for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) { - DefInit *ADI = dynamic_cast(Result->getArg(i)); + const DefInit *ADI = dynamic_cast(Result->getArg(i)); if (!ADI || Result->getArgName(i).empty()) continue; // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo) @@ -523,11 +523,11 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) { // If the argument did not match the instruction operand, and the operand // is composed of multiple suboperands, try matching the suboperands. if (NumSubOps > 1) { - DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo; + const DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo; for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { if (AliasOpNo >= Result->getNumArgs()) throw TGError(R->getLoc(), "not enough arguments for instruction!"); - Record *SubRec = dynamic_cast(MIOI->getArg(SubOp))->getDef(); + Record *SubRec = dynamic_cast(MIOI->getArg(SubOp))->getDef(); if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false, R->getLoc(), T, ResOp)) { ResultOperands.push_back(ResOp); diff --git oldutils/TableGen/CodeGenInstruction.h newutils/TableGen/CodeGenInstruction.h index 8d7669a..5cbe140 100644 --- oldutils/TableGen/CodeGenInstruction.h +++ newutils/TableGen/CodeGenInstruction.h @@ -98,7 +98,7 @@ namespace llvm { /// MIOperandInfo - Default MI operand type. Note an operand may be made /// up of multiple MI operands. - DagInit *MIOperandInfo; + const DagInit *MIOperandInfo; /// Constraint info for this operand. This operand can have pieces, so we /// track constraint info for each. @@ -106,7 +106,7 @@ namespace llvm { OperandInfo(Record *R, const std::string &N, const std::string &PMN, const std::string &EMN, const std::string &OT, unsigned MION, - unsigned MINO, DagInit *MIOI) + unsigned MINO, const DagInit *MIOI) : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN), OperandType(OT), MIOperandNo(MION), MINumOperands(MINO), MIOperandInfo(MIOI) {} @@ -270,7 +270,7 @@ namespace llvm { std::string AsmString; /// Result - The result instruction. - DagInit *Result; + const DagInit *Result; /// ResultInst - The instruction generated by the alias (decoded from /// Result). @@ -316,7 +316,7 @@ namespace llvm { CodeGenInstAlias(Record *R, CodeGenTarget &T); - bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, + bool tryAliasOpMatch(const DagInit *Result, unsigned AliasOpNo, Record *InstOpRec, bool hasSubOps, SMLoc Loc, CodeGenTarget &T, ResultOperand &ResOp); }; diff --git oldutils/TableGen/CodeGenRegisters.cpp newutils/TableGen/CodeGenRegisters.cpp index d7816c2..298009e 100644 --- oldutils/TableGen/CodeGenRegisters.cpp +++ newutils/TableGen/CodeGenRegisters.cpp @@ -91,14 +91,14 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { } // Process the composites. - ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices"); + const ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices"); for (unsigned i = 0, e = Comps->size(); i != e; ++i) { - DagInit *Pat = dynamic_cast(Comps->getElement(i)); + const DagInit *Pat = dynamic_cast(Comps->getElement(i)); if (!Pat) throw TGError(TheDef->getLoc(), "Invalid dag '" + Comps->getElement(i)->getAsString() + "' in CompositeIndices"); - DefInit *BaseIdxInit = dynamic_cast(Pat->getOperator()); + const DefInit *BaseIdxInit = dynamic_cast(Pat->getOperator()); if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); @@ -107,7 +107,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { CodeGenRegister *R2 = this; for (DagInit::const_arg_iterator di = Pat->arg_begin(), de = Pat->arg_end(); di != de; ++di) { - DefInit *IdxInit = dynamic_cast(*di); + const DefInit *IdxInit = dynamic_cast(*di); if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + Pat->getAsString()); @@ -163,7 +163,7 @@ struct TupleExpander : SetTheory::Expander { void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) { std::vector Indices = Def->getValueAsListOfDefs("SubRegIndices"); unsigned Dim = Indices.size(); - ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); + const ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); if (Dim != SubRegs->getSize()) throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); if (Dim < 2) @@ -183,13 +183,13 @@ struct TupleExpander : SetTheory::Expander { // Precompute some types. Record *RegisterCl = Def->getRecords().getClass("Register"); RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); - StringInit *BlankName = new StringInit(""); + const StringInit *BlankName = new StringInit(""); // Zip them up. for (unsigned n = 0; n != Length; ++n) { std::string Name; Record *Proto = Lists[0][n]; - std::vector Tuple; + std::vector Tuple; unsigned CostPerUse = 0; for (unsigned i = 0; i != Dim; ++i) { Record *Reg = Lists[i][n]; @@ -278,7 +278,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) Members.insert(RegBank.getReg((*Elements)[i])); // Alternative allocation orders may be subsets. - ListInit *Alts = R->getValueAsListInit("AltOrders"); + const ListInit *Alts = R->getValueAsListInit("AltOrders"); AltOrders.resize(Alts->size()); SetTheory::RecSet Order; for (unsigned i = 0, e = Alts->size(); i != e; ++i) { @@ -295,11 +295,11 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) } // SubRegClasses is a list containing (RC, subregindex, ...) dags. - ListInit *SRC = R->getValueAsListInit("SubRegClasses"); + const ListInit *SRC = R->getValueAsListInit("SubRegClasses"); for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { - DagInit *DAG = dynamic_cast(*i); + const DagInit *DAG = dynamic_cast(*i); if (!DAG) throw "SubRegClasses must contain DAGs"; - DefInit *DAGOp = dynamic_cast(DAG->getOperator()); + const DefInit *DAGOp = dynamic_cast(DAG->getOperator()); Record *RCRec; if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) throw "Operator '" + DAG->getOperator()->getAsString() + @@ -307,7 +307,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) // Iterate over args, all SubRegIndex instances. for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); ai != ae; ++ai) { - DefInit *Idx = dynamic_cast(*ai); + const DefInit *Idx = dynamic_cast(*ai); Record *IdxRec; if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) throw "Argument '" + (*ai)->getAsString() + diff --git oldutils/TableGen/CodeGenTarget.cpp newutils/TableGen/CodeGenTarget.cpp index 929791c..ceaa82f 100644 --- oldutils/TableGen/CodeGenTarget.cpp +++ newutils/TableGen/CodeGenTarget.cpp @@ -402,7 +402,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { // Parse the list of return types. std::vector OverloadedVTs; - ListInit *TypeList = R->getValueAsListInit("RetTypes"); + const ListInit *TypeList = R->getValueAsListInit("RetTypes"); for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { Record *TyEl = TypeList->getElementAsRecord(i); assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); @@ -470,7 +470,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { } // Parse the intrinsic properties. - ListInit *PropList = R->getValueAsListInit("Properties"); + const ListInit *PropList = R->getValueAsListInit("Properties"); for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { Record *Property = PropList->getElementAsRecord(i); assert(Property->isSubClassOf("IntrinsicProperty") && diff --git oldutils/TableGen/DAGISelMatcherGen.cpp newutils/TableGen/DAGISelMatcherGen.cpp index c5897c7..7e66c05 100644 --- oldutils/TableGen/DAGISelMatcherGen.cpp +++ newutils/TableGen/DAGISelMatcherGen.cpp @@ -203,7 +203,7 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) { assert(N->isLeaf() && "Not a leaf?"); // Direct match against an integer constant. - if (IntInit *II = dynamic_cast(N->getLeafValue())) { + if (const IntInit *II = dynamic_cast(N->getLeafValue())) { // If this is the root of the dag we're matching, we emit a redundant opcode // check to ensure that this gets folded into the normal top-level // OpcodeSwitch. @@ -215,7 +215,7 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) { return AddMatcher(new CheckIntegerMatcher(II->getValue())); } - DefInit *DI = dynamic_cast(N->getLeafValue()); + const DefInit *DI = dynamic_cast(N->getLeafValue()); if (DI == 0) { errs() << "Unknown leaf kind: " << *DI << "\n"; abort(); @@ -283,7 +283,7 @@ void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N, N->getOperator()->getName() == "or") && N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() && N->getPredicateFns().empty()) { - if (IntInit *II = dynamic_cast(N->getChild(1)->getLeafValue())) { + if (const IntInit *II = dynamic_cast(N->getChild(1)->getLeafValue())) { if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits. // If this is at the root of the pattern, we emit a redundant // CheckOpcode so that the following checks get factored properly under @@ -496,7 +496,7 @@ bool MatcherGen::EmitMatcherCode(unsigned Variant) { --RecNodeEntry; // Entries in VariableMap are biased. const ComplexPattern &CP = - CGP.getComplexPattern(((DefInit*)N->getLeafValue())->getDef()); + CGP.getComplexPattern(((const DefInit*)N->getLeafValue())->getDef()); // Emit a CheckComplexPat operation, which does the match (aborting if it // fails) and pushes the matched operands onto the recorded nodes list. @@ -572,14 +572,14 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N, SmallVectorImpl &ResultOps) { assert(N->isLeaf() && "Must be a leaf"); - if (IntInit *II = dynamic_cast(N->getLeafValue())) { + if (const IntInit *II = dynamic_cast(N->getLeafValue())) { AddMatcher(new EmitIntegerMatcher(II->getValue(), N->getType(0))); ResultOps.push_back(NextRecordedOperandNo++); return; } // If this is an explicit register reference, handle it. - if (DefInit *DI = dynamic_cast(N->getLeafValue())) { + if (const DefInit *DI = dynamic_cast(N->getLeafValue())) { Record *Def = DI->getDef(); if (Def->isSubClassOf("Register")) { const CodeGenRegister *Reg = diff --git oldutils/TableGen/FastISelEmitter.cpp newutils/TableGen/FastISelEmitter.cpp index f54e8df..2a86b89 100644 --- oldutils/TableGen/FastISelEmitter.cpp +++ newutils/TableGen/FastISelEmitter.cpp @@ -241,7 +241,7 @@ struct OperandsSignature { if (Op->getType(0) != VT) return false; - DefInit *OpDI = dynamic_cast(Op->getLeafValue()); + const DefInit *OpDI = dynamic_cast(Op->getLeafValue()); if (!OpDI) return false; Record *OpLeafRec = OpDI->getDef(); @@ -401,12 +401,12 @@ static std::string PhyRegForNode(TreePatternNode *Op, if (!Op->isLeaf()) return PhysReg; - DefInit *OpDI = dynamic_cast(Op->getLeafValue()); + const DefInit *OpDI = dynamic_cast(Op->getLeafValue()); Record *OpLeafRec = OpDI->getDef(); if (!OpLeafRec->isSubClassOf("Register")) return PhysReg; - PhysReg += static_cast(OpLeafRec->getValue( \ + PhysReg += static_cast(OpLeafRec->getValue( \ "Namespace")->getValue())->getValue(); PhysReg += "::"; PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); @@ -468,7 +468,7 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // a bit too complicated for now. if (!Dst->getChild(1)->isLeaf()) continue; - DefInit *SR = dynamic_cast(Dst->getChild(1)->getLeafValue()); + const DefInit *SR = dynamic_cast(Dst->getChild(1)->getLeafValue()); if (SR) SubRegNo = getQualifiedName(SR->getDef()); else diff --git oldutils/TableGen/FixedLenDecoderEmitter.cpp newutils/TableGen/FixedLenDecoderEmitter.cpp index c9dcb01..0cd4dd6 100644 --- oldutils/TableGen/FixedLenDecoderEmitter.cpp +++ newutils/TableGen/FixedLenDecoderEmitter.cpp @@ -48,15 +48,15 @@ static bool ValueNotSet(bit_value_t V) { static int Value(bit_value_t V) { return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1); } -static bit_value_t bitFromBits(BitsInit &bits, unsigned index) { - if (BitInit *bit = dynamic_cast(bits.getBit(index))) +static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { + if (const BitInit *bit = dynamic_cast(bits.getBit(index))) return bit->getValue() ? BIT_TRUE : BIT_FALSE; // The bit is uninitialized. return BIT_UNSET; } // Prints the bit value for each position. -static void dumpBits(raw_ostream &o, BitsInit &bits) { +static void dumpBits(raw_ostream &o, const BitsInit &bits) { unsigned index; for (index = bits.getNumBits(); index > 0; index--) { @@ -76,8 +76,8 @@ static void dumpBits(raw_ostream &o, BitsInit &bits) { } } -static BitsInit &getBitsField(const Record &def, const char *str) { - BitsInit *bits = def.getValueAsBitsInit(str); +static const BitsInit &getBitsField(const Record &def, const char *str) { + const BitsInit *bits = def.getValueAsBitsInit(str); return *bits; } @@ -279,7 +279,7 @@ public: protected: // Populates the insn given the uid. void insnWithID(insn_t &Insn, unsigned Opcode) const { - BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); + const BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); for (unsigned i = 0; i < BIT_WIDTH; ++i) Insn[i] = bitFromBits(Bits, i); @@ -1230,7 +1230,7 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, Def.getValueAsBit("isCodeGenOnly")) return false; - BitsInit &Bits = getBitsField(Def, "Inst"); + const BitsInit &Bits = getBitsField(Def, "Inst"); if (Bits.allInComplete()) return false; std::vector InsnOperands; @@ -1251,16 +1251,16 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, // Gather the outputs/inputs of the instruction, so we can find their // positions in the encoding. This assumes for now that they appear in the // MCInst in the order that they're listed. - std::vector > InOutOperands; - DagInit *Out = Def.getValueAsDag("OutOperandList"); - DagInit *In = Def.getValueAsDag("InOperandList"); + std::vector > InOutOperands; + const DagInit *Out = Def.getValueAsDag("OutOperandList"); + const DagInit *In = Def.getValueAsDag("InOperandList"); for (unsigned i = 0; i < Out->getNumArgs(); ++i) InOutOperands.push_back(std::make_pair(Out->getArg(i), Out->getArgName(i))); for (unsigned i = 0; i < In->getNumArgs(); ++i) InOutOperands.push_back(std::make_pair(In->getArg(i), In->getArgName(i))); // For each operand, see if we can figure out where it is encoded. - for (std::vector >::iterator + for (std::vector >::iterator NI = InOutOperands.begin(), NE = InOutOperands.end(); NI != NE; ++NI) { unsigned PrevBit = ~0; unsigned Base = ~0; @@ -1268,10 +1268,10 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, std::string Decoder = ""; for (unsigned bi = 0; bi < Bits.getNumBits(); ++bi) { - VarBitInit *BI = dynamic_cast(Bits.getBit(bi)); + const VarBitInit *BI = dynamic_cast(Bits.getBit(bi)); if (!BI) continue; - VarInit *Var = dynamic_cast(BI->getVariable()); + const VarInit *Var = dynamic_cast(BI->getVariable()); assert(Var); unsigned CurrBit = BI->getBitNum(); if (Var->getName() != NI->second) continue; @@ -1301,7 +1301,7 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, // for decoding register classes. // FIXME: This need to be extended to handle instructions with custom // decoder methods, and operands with (simple) MIOperandInfo's. - TypedInit *TI = dynamic_cast(NI->first); + const TypedInit *TI = dynamic_cast(NI->first); RecordRecTy *Type = dynamic_cast(TI->getType()); Record *TypeRecord = Type->getRecord(); bool isReg = false; @@ -1313,8 +1313,8 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, } RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod"); - StringInit *String = DecoderString ? - dynamic_cast(DecoderString->getValue()) : + const StringInit *String = DecoderString ? + dynamic_cast(DecoderString->getValue()) : 0; if (!isReg && String && String->getValue() != "") Decoder = String->getValue(); diff --git oldutils/TableGen/InstrInfoEmitter.cpp newutils/TableGen/InstrInfoEmitter.cpp index 5ebaf17..5004a99 100644 --- oldutils/TableGen/InstrInfoEmitter.cpp +++ newutils/TableGen/InstrInfoEmitter.cpp @@ -61,7 +61,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { // registers in their multi-operand operands. It may also be an anonymous // operand, which has a single operand, but no declared class for the // operand. - DagInit *MIOI = Inst.Operands[i].MIOperandInfo; + const DagInit *MIOI = Inst.Operands[i].MIOperandInfo; if (!MIOI || MIOI->getNumArgs() == 0) { // Single, anonymous, operand. @@ -70,7 +70,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { OperandList.push_back(Inst.Operands[i]); - Record *OpR = dynamic_cast(MIOI->getArg(j))->getDef(); + Record *OpR = dynamic_cast(MIOI->getArg(j))->getDef(); OperandList.back().Rec = OpR; } } @@ -295,11 +295,11 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.hasExtraDefRegAllocReq) OS << "|(1<getValueAsBitsInit("TSFlags"); + const BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); if (!TSF) throw "no TSFlags?"; uint64_t Value = 0; for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { - if (BitInit *Bit = dynamic_cast(TSF->getBit(i))) + if (const BitInit *Bit = dynamic_cast(TSF->getBit(i))) Value |= uint64_t(Bit->getValue()) << i; else throw "Invalid TSFlags bit in " + Inst.TheDef->getName(); diff --git oldutils/TableGen/LLVMCConfigurationEmitter.cpp newutils/TableGen/LLVMCConfigurationEmitter.cpp index cd0cbeb..563a727 100644 --- oldutils/TableGen/LLVMCConfigurationEmitter.cpp +++ newutils/TableGen/LLVMCConfigurationEmitter.cpp @@ -245,7 +245,7 @@ struct OptionDescription { unsigned Flags; std::string Help; unsigned MultiVal; - Init* InitVal; + const Init* InitVal; OptionDescription(OptionType::OptionType t = OptionType::Switch, const std::string& n = "", @@ -589,7 +589,7 @@ Handler GetHandler(FunctionObject* Obj, const DagInit& Dag) { } template -void InvokeDagInitHandler(FunctionObject* Obj, Init* I) { +void InvokeDagInitHandler(FunctionObject* Obj, const Init* I) { typedef void (FunctionObject::*Handler) (const DagInit&); const DagInit& Dag = InitPtrToDag(I); @@ -658,7 +658,7 @@ public: /// operator() - Just forwards to the corresponding property /// handler. - void operator() (Init* I) { + void operator() (const Init* I) { InvokeDagInitHandler(this, I); } @@ -705,10 +705,10 @@ private: void onInit (const DagInit& d) { CheckNumberOfArguments(d, 1); - Init* i = d.getArg(0); + const Init* i = d.getArg(0); const std::string& str = i->getAsString(); - bool correct = optDesc_.isParameter() && dynamic_cast(i); + bool correct = optDesc_.isParameter() && dynamic_cast(i); correct |= (optDesc_.isSwitch() && (str == "true" || str == "false")); if (!correct) @@ -821,7 +821,7 @@ void CollectOptionDescriptions (const RecordVector& V, for (RecordVector::const_iterator B = V.begin(), E = V.end(); B!=E; ++B) { // Throws an exception if the value does not exist. - ListInit* PropList = (*B)->getValueAsListInit("options"); + const ListInit* PropList = (*B)->getValueAsListInit("options"); // For every option description in this list: invoke AddOption. std::for_each(PropList->begin(), PropList->end(), AddOption(OptDescs)); @@ -836,8 +836,8 @@ namespace ToolFlags { struct ToolDescription : public RefCountedBase { std::string Name; - Init* CmdLine; - Init* Actions; + const Init* CmdLine; + const Init* Actions; StrVector InLanguage; std::string InFileOption; std::string OutFileOption; @@ -903,7 +903,7 @@ public: } } - void operator() (Init* I) { + void operator() (const Init* I) { InvokeDagInitHandler(this, I); } @@ -915,9 +915,9 @@ private: void onActions (const DagInit& d) { CheckNumberOfArguments(d, 1); - Init* Case = d.getArg(0); + const Init* Case = d.getArg(0); if (typeid(*Case) != typeid(DagInit) || - GetOperatorName(static_cast(*Case)) != "case") + GetOperatorName(static_cast(*Case)) != "case") throw "The argument to (actions) should be a 'case' construct!"; toolDesc_.Actions = Case; } @@ -954,7 +954,7 @@ private: isReallyJoin = true; } else { - Init* I = d.getArg(0); + const Init* I = d.getArg(0); isReallyJoin = InitPtrToBool(I); } @@ -1007,7 +1007,7 @@ void CollectToolDescriptions (const RecordVector& Tools, E = Tools.end(); B!=E; ++B) { const Record* T = *B; // Throws an exception if the value does not exist. - ListInit* PropList = T->getValueAsListInit("properties"); + const ListInit* PropList = T->getValueAsListInit("properties"); IntrusiveRefCntPtr ToolDesc(new ToolDescription(T->getName())); @@ -1163,7 +1163,7 @@ void WalkCase(const Init* Case, F1 TestCallback, F2 StatementCallback, unsigned i = 1; for (DagInit::const_arg_iterator B = d.arg_begin(), E = d.arg_end(); B != E; ++B) { - Init* arg = *B; + const Init* arg = *B; if (!even) { @@ -1181,8 +1181,8 @@ void WalkCase(const Init* Case, F1 TestCallback, F2 StatementCallback, } else { - if (dynamic_cast(arg) - && GetOperatorName(static_cast(*arg)) == "case") { + if (dynamic_cast(arg) + && GetOperatorName(static_cast(*arg)) == "case") { // Nested 'case'. WalkCase(arg, TestCallback, StatementCallback, IndentLevel + Indent1); } @@ -1210,7 +1210,7 @@ class ExtractOptionNames { ActionName == "parameter_equals" || ActionName == "element_in_list") { CheckNumberOfArguments(Stmt, 1); - Init* Arg = Stmt.getArg(0); + const Init* Arg = Stmt.getArg(0); if (typeid(*Arg) == typeid(StringInit)) OptionNames_.insert(InitPtrToString(Arg)); } @@ -1218,7 +1218,7 @@ class ExtractOptionNames { ActionName == "any_not_empty" || ActionName == "any_empty" || ActionName == "not_empty" || ActionName == "empty") { for (unsigned i = 0, NumArgs = Stmt.getNumArgs(); i < NumArgs; ++i) { - Init* Arg = Stmt.getArg(i); + const Init* Arg = Stmt.getArg(i); if (typeid(*Arg) == typeid(StringInit)) OptionNames_.insert(InitPtrToString(Arg)); } @@ -2613,7 +2613,7 @@ void EmitPreprocessOptions (const RecordKeeper& Records, for (RecordVector::const_iterator B = OptionPreprocessors.begin(), E = OptionPreprocessors.end(); B!=E; ++B) { - DagInit* Case = (*B)->getValueAsDag("preprocessor"); + const DagInit* Case = (*B)->getValueAsDag("preprocessor"); EmitCaseConstructHandler(Case, Indent1, EmitPreprocessOptionsCallback(OptDecs), false, OptDecs, O); @@ -2645,7 +2645,7 @@ public: } } - void operator() (Init* I) { + void operator() (const Init* I) { InvokeDagInitHandler(this, I); } @@ -2655,7 +2655,7 @@ private: CheckNumberOfArguments(d, 2); const std::string& Lang = InitPtrToString(d.getArg(0)); - Init* Suffixes = d.getArg(1); + const Init* Suffixes = d.getArg(1); // Second argument to lang_to_suffixes is either a single string... if (typeid(*Suffixes) == typeid(StringInit)) { @@ -2688,7 +2688,7 @@ void EmitPopulateLanguageMap (const RecordKeeper& Records, raw_ostream& O) // Call DoEmitPopulateLanguageMap. for (RecordVector::const_iterator B = LangMaps.begin(), E = LangMaps.end(); B!=E; ++B) { - ListInit* LangMap = (*B)->getValueAsListInit("map"); + const ListInit* LangMap = (*B)->getValueAsListInit("map"); std::for_each(LangMap->begin(), LangMap->end(), DoEmitPopulateLanguageMap(O)); } @@ -2947,7 +2947,7 @@ void FillInHookNames(const ToolDescriptions& ToolDescs, // Look for hook invocations in 'cmd_line'. if (!D.CmdLine) continue; - if (dynamic_cast(D.CmdLine)) + if (dynamic_cast(D.CmdLine)) // This is a string. ExtractHookNames(HookNames, OptDescs).operator()(D.CmdLine); else diff --git oldutils/TableGen/OptParserEmitter.cpp newutils/TableGen/OptParserEmitter.cpp index 431026c..f4d7be5 100644 --- oldutils/TableGen/OptParserEmitter.cpp +++ newutils/TableGen/OptParserEmitter.cpp @@ -56,7 +56,7 @@ static int CompareOptionRecords(const void *Av, const void *Bv) { static const std::string getOptionName(const Record &R) { // Use the record name unless EnumName is defined. - if (dynamic_cast(R.getValueInit("EnumName"))) + if (dynamic_cast(R.getValueInit("EnumName"))) return R.getName(); return R.getValueAsString("EnumName"); @@ -105,7 +105,7 @@ void OptParserEmitter::run(raw_ostream &OS) { // The containing option group (if any). OS << ", "; - if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) OS << getOptionName(*DI->getDef()); else OS << "INVALID"; @@ -114,7 +114,7 @@ void OptParserEmitter::run(raw_ostream &OS) { OS << ", INVALID, 0, 0"; // The option help text. - if (!dynamic_cast(R.getValueInit("HelpText"))) { + if (!dynamic_cast(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; write_cstring(OS, R.getValueAsString("HelpText")); @@ -145,14 +145,14 @@ void OptParserEmitter::run(raw_ostream &OS) { // The containing option group (if any). OS << ", "; - if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) OS << getOptionName(*DI->getDef()); else OS << "INVALID"; // The option alias (if any). OS << ", "; - if (const DefInit *DI = dynamic_cast(R.getValueInit("Alias"))) + if (const DefInit *DI = dynamic_cast(R.getValueInit("Alias"))) OS << getOptionName(*DI->getDef()); else OS << "INVALID"; @@ -166,7 +166,7 @@ void OptParserEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = LI->size(); i != e; ++i) { if (i) OS << " | "; - OS << dynamic_cast(LI->getElement(i))->getDef()->getName(); + OS << dynamic_cast(LI->getElement(i))->getDef()->getName(); } } @@ -174,7 +174,7 @@ void OptParserEmitter::run(raw_ostream &OS) { OS << ", " << R.getValueAsInt("NumArgs"); // The option help text. - if (!dynamic_cast(R.getValueInit("HelpText"))) { + if (!dynamic_cast(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; write_cstring(OS, R.getValueAsString("HelpText")); @@ -183,7 +183,7 @@ void OptParserEmitter::run(raw_ostream &OS) { // The option meta-variable name. OS << ", "; - if (!dynamic_cast(R.getValueInit("MetaVarName"))) + if (!dynamic_cast(R.getValueInit("MetaVarName"))) write_cstring(OS, R.getValueAsString("MetaVarName")); else OS << "0"; diff --git oldutils/TableGen/PseudoLoweringEmitter.cpp newutils/TableGen/PseudoLoweringEmitter.cpp index db33c1f..5cfa587 100644 --- oldutils/TableGen/PseudoLoweringEmitter.cpp +++ newutils/TableGen/PseudoLoweringEmitter.cpp @@ -24,11 +24,11 @@ using namespace llvm; // a single dag, so we can do fancier things. unsigned PseudoLoweringEmitter:: -addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, +addDagOperandMapping(Record *Rec, const DagInit *Dag, CodeGenInstruction &Insn, IndexedMap &OperandMap, unsigned BaseIdx) { unsigned OpsAdded = 0; for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { - if (DefInit *DI = dynamic_cast(Dag->getArg(i))) { + if (const DefInit *DI = dynamic_cast(Dag->getArg(i))) { // Physical register reference. Explicit check for the special case // "zero_reg" definition. if (DI->getDef()->isSubClassOf("Register") || @@ -54,11 +54,11 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) OperandMap[BaseIdx + i + I].Kind = OpData::Operand; OpsAdded += Insn.Operands[i].MINumOperands; - } else if (IntInit *II = dynamic_cast(Dag->getArg(i))) { + } else if (const IntInit *II = dynamic_cast(Dag->getArg(i))) { OperandMap[BaseIdx + i].Kind = OpData::Imm; OperandMap[BaseIdx + i].Data.Imm = II->getValue(); ++OpsAdded; - } else if (DagInit *SubDag = dynamic_cast(Dag->getArg(i))) { + } else if (const DagInit *SubDag = dynamic_cast(Dag->getArg(i))) { // Just add the operands recursively. This is almost certainly // a constant value for a complex operand (> 1 MI operand). unsigned NewOps = @@ -77,11 +77,11 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { // Validate that the result pattern has the corrent number and types // of arguments for the instruction it references. - DagInit *Dag = Rec->getValueAsDag("ResultInst"); + const DagInit *Dag = Rec->getValueAsDag("ResultInst"); assert(Dag && "Missing result instruction in pseudo expansion!"); DEBUG(dbgs() << " Result: " << *Dag << "\n"); - DefInit *OpDef = dynamic_cast(Dag->getOperator()); + const DefInit *OpDef = dynamic_cast(Dag->getOperator()); if (!OpDef) throw TGError(Rec->getLoc(), Rec->getName() + " has unexpected operator type!"); diff --git oldutils/TableGen/PseudoLoweringEmitter.h newutils/TableGen/PseudoLoweringEmitter.h index 2749280..6e52638 100644 --- oldutils/TableGen/PseudoLoweringEmitter.h +++ newutils/TableGen/PseudoLoweringEmitter.h @@ -47,7 +47,7 @@ class PseudoLoweringEmitter : public TableGenBackend { SmallVector Expansions; - unsigned addDagOperandMapping(Record *Rec, DagInit *Dag, + unsigned addDagOperandMapping(Record *Rec, const DagInit *Dag, CodeGenInstruction &Insn, IndexedMap &OperandMap, unsigned BaseIdx); diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index f9ee89c..d72a707 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -39,7 +39,7 @@ ListRecTy *RecTy::getListTy() { return ListTy; } -Init *BitRecTy::convertValue(BitsInit *BI) { +const Init *BitRecTy::convertValue(const BitsInit *BI) { if (BI->getNumBits() != 1) return 0; // Only accept if just one bit! return BI->getBit(0); } @@ -48,14 +48,14 @@ bool BitRecTy::baseClassOf(const BitsRecTy *RHS) const { return RHS->getNumBits() == 1; } -Init *BitRecTy::convertValue(IntInit *II) { +const Init *BitRecTy::convertValue(const IntInit *II) { int64_t Val = II->getValue(); if (Val != 0 && Val != 1) return 0; // Only accept 0 or 1 for a bit! return new BitInit(Val != 0); } -Init *BitRecTy::convertValue(TypedInit *VI) { +const Init *BitRecTy::convertValue(const TypedInit *VI) { if (dynamic_cast(VI->getType())) return VI; // Accept variable if it is already of bit type! return 0; @@ -75,18 +75,18 @@ std::string BitsRecTy::getAsString() const { return "bits<" + utostr(Size) + ">"; } -Init *BitsRecTy::convertValue(UnsetInit *UI) { - SmallVector NewBits(Size); +const Init *BitsRecTy::convertValue(const UnsetInit *UI) { + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) NewBits[i] = new UnsetInit(); - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } -Init *BitsRecTy::convertValue(BitInit *UI) { +const Init *BitsRecTy::convertValue(const BitInit *UI) { if (Size != 1) return 0; // Can only convert single bit. - return new BitsInit(ArrayRef(UI)); + return new BitsInit(ArrayRef(UI)); } /// canFitInBitfield - Return true if the number of bits is large enough to hold @@ -100,57 +100,55 @@ static bool canFitInBitfield(int64_t Value, unsigned NumBits) { /// convertValue from Int initializer to bits type: Split the integer up into the /// appropriate bits. /// -Init *BitsRecTy::convertValue(IntInit *II) { +const Init *BitsRecTy::convertValue(const IntInit *II) { int64_t Value = II->getValue(); // Make sure this bitfield is large enough to hold the integer value. if (!canFitInBitfield(Value, Size)) return 0; - SmallVector NewBits(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) NewBits[i] = new BitInit(Value & (1LL << i)); - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } -Init *BitsRecTy::convertValue(BitsInit *BI) { +const Init *BitsRecTy::convertValue(const BitsInit *BI) { // If the number of bits is right, return it. Otherwise we need to expand or // truncate. if (BI->getNumBits() == Size) return BI; return 0; } -Init *BitsRecTy::convertValue(TypedInit *VI) { +const Init *BitsRecTy::convertValue(const TypedInit *VI) { if (BitsRecTy *BRT = dynamic_cast(VI->getType())) if (BRT->Size == Size) { - SmallVector NewBits(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) NewBits[i] = new VarBitInit(VI, i); - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } - if (Size == 1 && dynamic_cast(VI->getType())) { - Init *NewBits[1] = { VI }; - return new BitsInit(ArrayRef(NewBits)); - } + if (Size == 1 && dynamic_cast(VI->getType())) + return new BitsInit(ArrayRef(VI)); - if (TernOpInit *Tern = dynamic_cast(VI)) { + if (const TernOpInit *Tern = dynamic_cast(VI)) { if (Tern->getOpcode() == TernOpInit::IF) { - Init *LHS = Tern->getLHS(); - Init *MHS = Tern->getMHS(); - Init *RHS = Tern->getRHS(); + const Init *LHS = Tern->getLHS(); + const Init *MHS = Tern->getMHS(); + const Init *RHS = Tern->getRHS(); - IntInit *MHSi = dynamic_cast(MHS); - IntInit *RHSi = dynamic_cast(RHS); + const IntInit *MHSi = dynamic_cast(MHS); + const IntInit *RHSi = dynamic_cast(RHS); if (MHSi && RHSi) { int64_t MHSVal = MHSi->getValue(); int64_t RHSVal = RHSi->getValue(); if (canFitInBitfield(MHSVal, Size) && canFitInBitfield(RHSVal, Size)) { - SmallVector NewBits(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) NewBits[i] = @@ -159,14 +157,14 @@ Init *BitsRecTy::convertValue(TypedInit *VI) { new IntInit((RHSVal & (1LL << i)) ? 1 : 0), VI->getType()); - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } } else { - BitsInit *MHSbs = dynamic_cast(MHS); - BitsInit *RHSbs = dynamic_cast(RHS); + const BitsInit *MHSbs = dynamic_cast(MHS); + const BitsInit *RHSbs = dynamic_cast(RHS); if (MHSbs && RHSbs) { - SmallVector NewBits(Size); + SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) NewBits[i] = new TernOpInit(TernOpInit::IF, LHS, @@ -174,7 +172,7 @@ Init *BitsRecTy::convertValue(TypedInit *VI) { RHSbs->getBit(i), VI->getType()); - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } } } @@ -183,14 +181,14 @@ Init *BitsRecTy::convertValue(TypedInit *VI) { return 0; } -Init *IntRecTy::convertValue(BitInit *BI) { +const Init *IntRecTy::convertValue(const BitInit *BI) { return new IntInit(BI->getValue()); } -Init *IntRecTy::convertValue(BitsInit *BI) { +const Init *IntRecTy::convertValue(const BitsInit *BI) { int64_t Result = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) - if (BitInit *Bit = dynamic_cast(BI->getBit(i))) { + if (const BitInit *Bit = dynamic_cast(BI->getBit(i))) { Result |= Bit->getValue() << i; } else { return 0; @@ -198,39 +196,39 @@ Init *IntRecTy::convertValue(BitsInit *BI) { return new IntInit(Result); } -Init *IntRecTy::convertValue(TypedInit *TI) { +const Init *IntRecTy::convertValue(const TypedInit *TI) { if (TI->getType()->typeIsConvertibleTo(this)) return TI; // Accept variable if already of the right type! return 0; } -Init *StringRecTy::convertValue(UnOpInit *BO) { +const Init *StringRecTy::convertValue(const UnOpInit *BO) { if (BO->getOpcode() == UnOpInit::CAST) { - Init *L = BO->getOperand()->convertInitializerTo(this); + const Init *L = BO->getOperand()->convertInitializerTo(this); if (L == 0) return 0; if (L != BO->getOperand()) return new UnOpInit(UnOpInit::CAST, L, new StringRecTy); return BO; } - return convertValue((TypedInit*)BO); + return convertValue((const TypedInit*)BO); } -Init *StringRecTy::convertValue(BinOpInit *BO) { +const Init *StringRecTy::convertValue(const BinOpInit *BO) { if (BO->getOpcode() == BinOpInit::STRCONCAT) { - Init *L = BO->getLHS()->convertInitializerTo(this); - Init *R = BO->getRHS()->convertInitializerTo(this); + const Init *L = BO->getLHS()->convertInitializerTo(this); + const Init *R = BO->getRHS()->convertInitializerTo(this); if (L == 0 || R == 0) return 0; if (L != BO->getLHS() || R != BO->getRHS()) return new BinOpInit(BinOpInit::STRCONCAT, L, R, new StringRecTy); return BO; } - return convertValue((TypedInit*)BO); + return convertValue((const TypedInit*)BO); } -Init *StringRecTy::convertValue(TypedInit *TI) { +const Init *StringRecTy::convertValue(const TypedInit *TI) { if (dynamic_cast(TI->getType())) return TI; // Accept variable if already of the right type! return 0; @@ -240,13 +238,13 @@ std::string ListRecTy::getAsString() const { return "list<" + Ty->getAsString() + ">"; } -Init *ListRecTy::convertValue(ListInit *LI) { - std::vector Elements; +const Init *ListRecTy::convertValue(const ListInit *LI) { + std::vector Elements; // Verify that all of the elements of the list are subclasses of the // appropriate class! for (unsigned i = 0, e = LI->getSize(); i != e; ++i) - if (Init *CI = LI->getElement(i)->convertInitializerTo(Ty)) + if (const Init *CI = LI->getElement(i)->convertInitializerTo(Ty)) Elements.push_back(CI); else return 0; @@ -259,7 +257,7 @@ Init *ListRecTy::convertValue(ListInit *LI) { return new ListInit(Elements, this); } -Init *ListRecTy::convertValue(TypedInit *TI) { +const Init *ListRecTy::convertValue(const TypedInit *TI) { // Ensure that TI is compatible with our class. if (ListRecTy *LRT = dynamic_cast(TI->getType())) if (LRT->getElementType()->typeIsConvertibleTo(getElementType())) @@ -267,21 +265,21 @@ Init *ListRecTy::convertValue(TypedInit *TI) { return 0; } -Init *CodeRecTy::convertValue(TypedInit *TI) { +const Init *CodeRecTy::convertValue(const TypedInit *TI) { if (TI->getType()->typeIsConvertibleTo(this)) return TI; return 0; } -Init *DagRecTy::convertValue(TypedInit *TI) { +const Init *DagRecTy::convertValue(const TypedInit *TI) { if (TI->getType()->typeIsConvertibleTo(this)) return TI; return 0; } -Init *DagRecTy::convertValue(UnOpInit *BO) { +const Init *DagRecTy::convertValue(const UnOpInit *BO) { if (BO->getOpcode() == UnOpInit::CAST) { - Init *L = BO->getOperand()->convertInitializerTo(this); + const Init *L = BO->getOperand()->convertInitializerTo(this); if (L == 0) return 0; if (L != BO->getOperand()) return new UnOpInit(UnOpInit::CAST, L, new DagRecTy); @@ -290,10 +288,10 @@ Init *DagRecTy::convertValue(UnOpInit *BO) { return 0; } -Init *DagRecTy::convertValue(BinOpInit *BO) { +const Init *DagRecTy::convertValue(const BinOpInit *BO) { if (BO->getOpcode() == BinOpInit::CONCAT) { - Init *L = BO->getLHS()->convertInitializerTo(this); - Init *R = BO->getRHS()->convertInitializerTo(this); + const Init *L = BO->getLHS()->convertInitializerTo(this); + const Init *R = BO->getRHS()->convertInitializerTo(this); if (L == 0 || R == 0) return 0; if (L != BO->getLHS() || R != BO->getRHS()) return new BinOpInit(BinOpInit::CONCAT, L, R, new DagRecTy); @@ -310,14 +308,14 @@ std::string RecordRecTy::getAsString() const { return Rec->getName(); } -Init *RecordRecTy::convertValue(DefInit *DI) { +const Init *RecordRecTy::convertValue(const DefInit *DI) { // Ensure that DI is a subclass of Rec. if (!DI->getDef()->isSubClassOf(Rec)) return 0; return DI; } -Init *RecordRecTy::convertValue(TypedInit *TI) { +const Init *RecordRecTy::convertValue(const TypedInit *TI) { // Ensure that TI is compatible with Rec. if (RecordRecTy *RRT = dynamic_cast(TI->getType())) if (RRT->getRecord()->isSubClassOf(getRecord()) || @@ -398,22 +396,23 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { void Init::dump() const { return print(errs()); } -Init *BitsInit::convertInitializerBitRange(const std::vector &Bits) { - SmallVector NewBits(Bits.size()); +const Init * +BitsInit::convertInitializerBitRange(const std::vector &Bits) const { + SmallVector NewBits(Bits.size()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { if (Bits[i] >= getNumBits()) return 0; NewBits[i] = getBit(Bits[i]); } - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } std::string BitsInit::getAsString() const { std::string Result = "{ "; for (unsigned i = 0, e = getNumBits(); i != e; ++i) { if (i) Result += ", "; - if (Init *Bit = getBit(e-i-1)) + if (const Init *Bit = getBit(e-i-1)) Result += Bit->getAsString(); else Result += "*"; @@ -424,13 +423,13 @@ std::string BitsInit::getAsString() const { // resolveReferences - If there are any field references that refer to fields // that have been filled in, we can propagate the values now. // -Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) { +const Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) const { bool Changed = false; - SmallVector NewBits(getNumBits()); + SmallVector NewBits(getNumBits()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { - Init *B; - Init *CurBit = getBit(i); + const Init *B; + const Init *CurBit = getBit(i); do { B = CurBit; @@ -441,7 +440,7 @@ Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) { } if (Changed) - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); return this; } @@ -450,8 +449,9 @@ std::string IntInit::getAsString() const { return itostr(Value); } -Init *IntInit::convertInitializerBitRange(const std::vector &Bits) { - SmallVector NewBits(Bits.size()); +const Init * +IntInit::convertInitializerBitRange(const std::vector &Bits) const { + SmallVector NewBits(Bits.size()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { if (Bits[i] >= 64) @@ -459,11 +459,12 @@ Init *IntInit::convertInitializerBitRange(const std::vector &Bits) { NewBits[i] = new BitInit(Value & (INT64_C(1) << Bits[i])); } - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } -Init *ListInit::convertInitListSlice(const std::vector &Elements) { - std::vector Vals; +const Init * +ListInit::convertInitListSlice(const std::vector &Elements) const { + std::vector Vals; for (unsigned i = 0, e = Elements.size(); i != e; ++i) { if (Elements[i] >= getSize()) return 0; @@ -474,19 +475,19 @@ Init *ListInit::convertInitListSlice(const std::vector &Elements) { Record *ListInit::getElementAsRecord(unsigned i) const { assert(i < Values.size() && "List element index out of range!"); - DefInit *DI = dynamic_cast(Values[i]); + const DefInit *DI = dynamic_cast(Values[i]); if (DI == 0) throw "Expected record in list!"; return DI->getDef(); } -Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) { - std::vector Resolved; +const Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) const { + std::vector Resolved; Resolved.reserve(getSize()); bool Changed = false; for (unsigned i = 0, e = getSize(); i != e; ++i) { - Init *E; - Init *CurElt = getElement(i); + const Init *E; + const Init *CurElt = getElement(i); do { E = CurElt; @@ -501,15 +502,16 @@ Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) { return this; } -Init *ListInit::resolveListElementReference(Record &R, const RecordVal *IRV, - unsigned Elt) { +const Init *ListInit::resolveListElementReference(Record &R, + const RecordVal *IRV, + unsigned Elt) const { if (Elt >= getSize()) return 0; // Out of range reference. - Init *E = getElement(Elt); + const Init *E = getElement(Elt); // If the element is set to some value, or if we are resolving a reference // to a specific variable and that variable is explicitly unset, then // replace the VarListElementInit with it. - if (IRV || !dynamic_cast(E)) + if (IRV || !dynamic_cast(E)) return E; return 0; } @@ -523,12 +525,12 @@ std::string ListInit::getAsString() const { return Result + "]"; } -Init *OpInit::resolveBitReference(Record &R, const RecordVal *IRV, - unsigned Bit) { - Init *Folded = Fold(&R, 0); +const Init *OpInit::resolveBitReference(Record &R, const RecordVal *IRV, + unsigned Bit) const { + const Init *Folded = Fold(&R, 0); if (Folded != this) { - TypedInit *Typed = dynamic_cast(Folded); + const TypedInit *Typed = dynamic_cast(Folded); if (Typed) { return Typed->resolveBitReference(R, IRV, Bit); } @@ -537,12 +539,12 @@ Init *OpInit::resolveBitReference(Record &R, const RecordVal *IRV, return 0; } -Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, - unsigned Elt) { - Init *Folded = Fold(&R, 0); +const Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, + unsigned Elt) const { + const Init *Folded = Fold(&R, 0); if (Folded != this) { - TypedInit *Typed = dynamic_cast(Folded); + const TypedInit *Typed = dynamic_cast(Folded); if (Typed) { return Typed->resolveListElementReference(R, IRV, Elt); } @@ -551,22 +553,22 @@ Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, return 0; } -Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { +const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { switch (getOpcode()) { default: assert(0 && "Unknown unop"); case CAST: { if (getType()->getAsString() == "string") { - StringInit *LHSs = dynamic_cast(LHS); + const StringInit *LHSs = dynamic_cast(LHS); if (LHSs) { return LHSs; } - DefInit *LHSd = dynamic_cast(LHS); + const DefInit *LHSd = dynamic_cast(LHS); if (LHSd) { return new StringInit(LHSd->getDef()->getName()); } } else { - StringInit *LHSs = dynamic_cast(LHS); + const StringInit *LHSs = dynamic_cast(LHS); if (LHSs) { std::string Name = LHSs->getValue(); @@ -612,7 +614,7 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { break; } case HEAD: { - ListInit *LHSl = dynamic_cast(LHS); + const ListInit *LHSl = dynamic_cast(LHS); if (LHSl) { if (LHSl->getSize() == 0) { assert(0 && "Empty list in car"); @@ -623,7 +625,7 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { break; } case TAIL: { - ListInit *LHSl = dynamic_cast(LHS); + const ListInit *LHSl = dynamic_cast(LHS); if (LHSl) { if (LHSl->getSize() == 0) { assert(0 && "Empty list in cdr"); @@ -635,14 +637,15 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { // they are not convertible to Init **. Fortunately, // RandomAccessIterator::operator * is guaranteed to return an // lvalue. - ListInit *Result = new ListInit(ArrayRef(&*begin, end - begin), - LHSl->getType()); + ListInit *Result = + new ListInit(ArrayRef(&*begin, end - begin), + LHSl->getType()); return Result; } break; } case EMPTY: { - ListInit *LHSl = dynamic_cast(LHS); + const ListInit *LHSl = dynamic_cast(LHS); if (LHSl) { if (LHSl->getSize() == 0) { return new IntInit(1); @@ -650,7 +653,7 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { return new IntInit(0); } } - StringInit *LHSs = dynamic_cast(LHS); + const StringInit *LHSs = dynamic_cast(LHS); if (LHSs) { if (LHSs->getValue().empty()) { return new IntInit(1); @@ -665,8 +668,8 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { return this; } -Init *UnOpInit::resolveReferences(Record &R, const RecordVal *RV) { - Init *lhs = LHS->resolveReferences(R, RV); +const Init *UnOpInit::resolveReferences(Record &R, const RecordVal *RV) const { + const Init *lhs = LHS->resolveReferences(R, RV); if (LHS != lhs) return (new UnOpInit(getOpcode(), lhs, getType()))->Fold(&R, 0); @@ -684,18 +687,18 @@ std::string UnOpInit::getAsString() const { return Result + "(" + LHS->getAsString() + ")"; } -Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { +const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { switch (getOpcode()) { default: assert(0 && "Unknown binop"); case CONCAT: { - DagInit *LHSs = dynamic_cast(LHS); - DagInit *RHSs = dynamic_cast(RHS); + const DagInit *LHSs = dynamic_cast(LHS); + const DagInit *RHSs = dynamic_cast(RHS); if (LHSs && RHSs) { - DefInit *LOp = dynamic_cast(LHSs->getOperator()); - DefInit *ROp = dynamic_cast(RHSs->getOperator()); + const DefInit *LOp = dynamic_cast(LHSs->getOperator()); + const DefInit *ROp = dynamic_cast(RHSs->getOperator()); if (LOp == 0 || ROp == 0 || LOp->getDef() != ROp->getDef()) throw "Concated Dag operators do not match!"; - std::vector Args; + std::vector Args; std::vector ArgNames; for (unsigned i = 0, e = LHSs->getNumArgs(); i != e; ++i) { Args.push_back(LHSs->getArg(i)); @@ -710,8 +713,8 @@ Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { break; } case STRCONCAT: { - StringInit *LHSs = dynamic_cast(LHS); - StringInit *RHSs = dynamic_cast(RHS); + const StringInit *LHSs = dynamic_cast(LHS); + const StringInit *RHSs = dynamic_cast(RHS); if (LHSs && RHSs) return new StringInit(LHSs->getValue() + RHSs->getValue()); break; @@ -719,16 +722,16 @@ Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { case EQ: { // try to fold eq comparison for 'bit' and 'int', otherwise fallback // to string objects. - IntInit* L = - dynamic_cast(LHS->convertInitializerTo(IntRecTy::get())); - IntInit* R = - dynamic_cast(RHS->convertInitializerTo(IntRecTy::get())); + const IntInit* L = + dynamic_cast(LHS->convertInitializerTo(IntRecTy::get())); + const IntInit* R = + dynamic_cast(RHS->convertInitializerTo(IntRecTy::get())); if (L && R) return new IntInit(L->getValue() == R->getValue()); - StringInit *LHSs = dynamic_cast(LHS); - StringInit *RHSs = dynamic_cast(RHS); + const StringInit *LHSs = dynamic_cast(LHS); + const StringInit *RHSs = dynamic_cast(RHS); // Make sure we've resolved if (LHSs && RHSs) @@ -739,8 +742,8 @@ Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { case SHL: case SRA: case SRL: { - IntInit *LHSi = dynamic_cast(LHS); - IntInit *RHSi = dynamic_cast(RHS); + const IntInit *LHSi = dynamic_cast(LHS); + const IntInit *RHSi = dynamic_cast(RHS); if (LHSi && RHSi) { int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue(); int64_t Result; @@ -758,9 +761,9 @@ Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { return this; } -Init *BinOpInit::resolveReferences(Record &R, const RecordVal *RV) { - Init *lhs = LHS->resolveReferences(R, RV); - Init *rhs = RHS->resolveReferences(R, RV); +const Init *BinOpInit::resolveReferences(Record &R, const RecordVal *RV) const { + const Init *lhs = LHS->resolveReferences(R, RV); + const Init *rhs = RHS->resolveReferences(R, RV); if (LHS != lhs || RHS != rhs) return (new BinOpInit(getOpcode(), lhs, rhs, getType()))->Fold(&R, 0); @@ -780,19 +783,21 @@ std::string BinOpInit::getAsString() const { return Result + "(" + LHS->getAsString() + ", " + RHS->getAsString() + ")"; } -static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, - Record *CurRec, MultiClass *CurMultiClass); +static const Init *ForeachHelper(const Init *LHS, const Init *MHS, + const Init *RHS, RecTy *Type, + Record *CurRec, MultiClass *CurMultiClass); -static Init *EvaluateOperation(OpInit *RHSo, Init *LHS, Init *Arg, - RecTy *Type, Record *CurRec, - MultiClass *CurMultiClass) { - std::vector NewOperands; +static const Init *EvaluateOperation(const OpInit *RHSo, const Init *LHS, + const Init *Arg, + RecTy *Type, Record *CurRec, + MultiClass *CurMultiClass) { + std::vector NewOperands; - TypedInit *TArg = dynamic_cast(Arg); + const TypedInit *TArg = dynamic_cast(Arg); // If this is a dag, recurse if (TArg && TArg->getType()->getAsString() == "dag") { - Init *Result = ForeachHelper(LHS, Arg, RHSo, Type, + const Init *Result = ForeachHelper(LHS, Arg, RHSo, Type, CurRec, CurMultiClass); if (Result != 0) { return Result; @@ -802,10 +807,10 @@ static Init *EvaluateOperation(OpInit *RHSo, Init *LHS, Init *Arg, } for (int i = 0; i < RHSo->getNumOperands(); ++i) { - OpInit *RHSoo = dynamic_cast(RHSo->getOperand(i)); + const OpInit *RHSoo = dynamic_cast(RHSo->getOperand(i)); if (RHSoo) { - Init *Result = EvaluateOperation(RHSoo, LHS, Arg, + const Init *Result = EvaluateOperation(RHSoo, LHS, Arg, Type, CurRec, CurMultiClass); if (Result != 0) { NewOperands.push_back(Result); @@ -820,8 +825,8 @@ static Init *EvaluateOperation(OpInit *RHSo, Init *LHS, Init *Arg, } // Now run the operator and use its result as the new leaf - OpInit *NewOp = RHSo->clone(NewOperands); - Init *NewVal = NewOp->Fold(CurRec, CurMultiClass); + const OpInit *NewOp = RHSo->clone(NewOperands); + const Init *NewVal = NewOp->Fold(CurRec, CurMultiClass); if (NewVal != NewOp) { delete NewOp; return NewVal; @@ -829,21 +834,23 @@ static Init *EvaluateOperation(OpInit *RHSo, Init *LHS, Init *Arg, return 0; } -static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, - Record *CurRec, MultiClass *CurMultiClass) { - DagInit *MHSd = dynamic_cast(MHS); - ListInit *MHSl = dynamic_cast(MHS); +static const Init *ForeachHelper(const Init *LHS, const Init *MHS, + const Init *RHS, RecTy *Type, + Record *CurRec, + MultiClass *CurMultiClass) { + const DagInit *MHSd = dynamic_cast(MHS); + const ListInit *MHSl = dynamic_cast(MHS); DagRecTy *DagType = dynamic_cast(Type); ListRecTy *ListType = dynamic_cast(Type); - OpInit *RHSo = dynamic_cast(RHS); + const OpInit *RHSo = dynamic_cast(RHS); if (!RHSo) { throw TGError(CurRec->getLoc(), "!foreach requires an operator\n"); } - TypedInit *LHSt = dynamic_cast(LHS); + const TypedInit *LHSt = dynamic_cast(LHS); if (!LHSt) { throw TGError(CurRec->getLoc(), "!foreach requires typed variable\n"); @@ -851,22 +858,22 @@ static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, if ((MHSd && DagType) || (MHSl && ListType)) { if (MHSd) { - Init *Val = MHSd->getOperator(); - Init *Result = EvaluateOperation(RHSo, LHS, Val, + const Init *Val = MHSd->getOperator(); + const Init *Result = EvaluateOperation(RHSo, LHS, Val, Type, CurRec, CurMultiClass); if (Result != 0) { Val = Result; } - std::vector > args; + std::vector > args; for (unsigned int i = 0; i < MHSd->getNumArgs(); ++i) { - Init *Arg; + const Init *Arg; std::string ArgName; Arg = MHSd->getArg(i); ArgName = MHSd->getArgName(i); // Process args - Init *Result = EvaluateOperation(RHSo, LHS, Arg, Type, + const Init *Result = EvaluateOperation(RHSo, LHS, Arg, Type, CurRec, CurMultiClass); if (Result != 0) { Arg = Result; @@ -879,14 +886,14 @@ static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, return new DagInit(Val, "", args); } if (MHSl) { - std::vector NewOperands; - std::vector NewList(MHSl->begin(), MHSl->end()); + std::vector NewOperands; + std::vector NewList(MHSl->begin(), MHSl->end()); - for (std::vector::iterator li = NewList.begin(), + for (std::vector::iterator li = NewList.begin(), liend = NewList.end(); li != liend; ++li) { - Init *Item = *li; + const Init *Item = *li; NewOperands.clear(); for(int i = 0; i < RHSo->getNumOperands(); ++i) { // First, replace the foreach variable with the list item @@ -898,8 +905,8 @@ static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, } // Now run the operator and use its result as the new list item - OpInit *NewOp = RHSo->clone(NewOperands); - Init *NewItem = NewOp->Fold(CurRec, CurMultiClass); + const OpInit *NewOp = RHSo->clone(NewOperands); + const Init *NewItem = NewOp->Fold(CurRec, CurMultiClass); if (NewItem != NewOp) { *li = NewItem; delete NewOp; @@ -911,21 +918,21 @@ static Init *ForeachHelper(Init *LHS, Init *MHS, Init *RHS, RecTy *Type, return 0; } -Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { +const Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { switch (getOpcode()) { default: assert(0 && "Unknown binop"); case SUBST: { - DefInit *LHSd = dynamic_cast(LHS); - VarInit *LHSv = dynamic_cast(LHS); - StringInit *LHSs = dynamic_cast(LHS); + const DefInit *LHSd = dynamic_cast(LHS); + const VarInit *LHSv = dynamic_cast(LHS); + const StringInit *LHSs = dynamic_cast(LHS); - DefInit *MHSd = dynamic_cast(MHS); - VarInit *MHSv = dynamic_cast(MHS); - StringInit *MHSs = dynamic_cast(MHS); + const DefInit *MHSd = dynamic_cast(MHS); + const VarInit *MHSv = dynamic_cast(MHS); + const StringInit *MHSs = dynamic_cast(MHS); - DefInit *RHSd = dynamic_cast(RHS); - VarInit *RHSv = dynamic_cast(RHS); - StringInit *RHSs = dynamic_cast(RHS); + const DefInit *RHSd = dynamic_cast(RHS); + const VarInit *RHSv = dynamic_cast(RHS); + const StringInit *RHSs = dynamic_cast(RHS); if ((LHSd && MHSd && RHSd) || (LHSv && MHSv && RHSv) @@ -964,7 +971,7 @@ Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { } case FOREACH: { - Init *Result = ForeachHelper(LHS, MHS, RHS, getType(), + const Init *Result = ForeachHelper(LHS, MHS, RHS, getType(), CurRec, CurMultiClass); if (Result != 0) { return Result; @@ -973,9 +980,9 @@ Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { } case IF: { - IntInit *LHSi = dynamic_cast(LHS); - if (Init *I = LHS->convertInitializerTo(IntRecTy::get())) - LHSi = dynamic_cast(I); + const IntInit *LHSi = dynamic_cast(LHS); + if (const Init *I = LHS->convertInitializerTo(IntRecTy::get())) + LHSi = dynamic_cast(I); if (LHSi) { if (LHSi->getValue()) { return MHS; @@ -990,29 +997,30 @@ Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { return this; } -Init *TernOpInit::resolveReferences(Record &R, const RecordVal *RV) { - Init *lhs = LHS->resolveReferences(R, RV); +const Init *TernOpInit::resolveReferences(Record &R, + const RecordVal *RV) const { + const Init *lhs = LHS->resolveReferences(R, RV); if (Opc == IF && lhs != LHS) { - IntInit *Value = dynamic_cast(lhs); - if (Init *I = lhs->convertInitializerTo(IntRecTy::get())) - Value = dynamic_cast(I); + const IntInit *Value = dynamic_cast(lhs); + if (const Init *I = lhs->convertInitializerTo(IntRecTy::get())) + Value = dynamic_cast(I); if (Value != 0) { // Short-circuit if (Value->getValue()) { - Init *mhs = MHS->resolveReferences(R, RV); + const Init *mhs = MHS->resolveReferences(R, RV); return (new TernOpInit(getOpcode(), lhs, mhs, RHS, getType()))->Fold(&R, 0); } else { - Init *rhs = RHS->resolveReferences(R, RV); + const Init *rhs = RHS->resolveReferences(R, RV); return (new TernOpInit(getOpcode(), lhs, MHS, rhs, getType()))->Fold(&R, 0); } } } - Init *mhs = MHS->resolveReferences(R, RV); - Init *rhs = RHS->resolveReferences(R, RV); + const Init *mhs = MHS->resolveReferences(R, RV); + const Init *rhs = RHS->resolveReferences(R, RV); if (LHS != lhs || MHS != mhs || RHS != rhs) return (new TernOpInit(getOpcode(), lhs, mhs, rhs, getType()))->Fold(&R, 0); @@ -1041,29 +1049,31 @@ RecTy *TypedInit::getFieldType(const std::string &FieldName) const { return 0; } -Init *TypedInit::convertInitializerBitRange(const std::vector &Bits) { +const Init * +TypedInit::convertInitializerBitRange(const std::vector &Bits) const { BitsRecTy *T = dynamic_cast(getType()); if (T == 0) return 0; // Cannot subscript a non-bits variable. unsigned NumBits = T->getNumBits(); - SmallVector NewBits(Bits.size()); + SmallVector NewBits(Bits.size()); for (unsigned i = 0, e = Bits.size(); i != e; ++i) { if (Bits[i] >= NumBits) return 0; NewBits[i] = new VarBitInit(this, Bits[i]); } - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } -Init *TypedInit::convertInitListSlice(const std::vector &Elements) { +const Init * +TypedInit::convertInitListSlice(const std::vector &Elements) const { ListRecTy *T = dynamic_cast(getType()); if (T == 0) return 0; // Cannot subscript a non-list variable. if (Elements.size() == 1) return new VarListElementInit(this, Elements[0]); - std::vector ListInits; + std::vector ListInits; ListInits.reserve(Elements.size()); for (unsigned i = 0, e = Elements.size(); i != e; ++i) ListInits.push_back(new VarListElementInit(this, Elements[i])); @@ -1071,48 +1081,49 @@ Init *TypedInit::convertInitListSlice(const std::vector &Elements) { } -Init *VarInit::resolveBitReference(Record &R, const RecordVal *IRV, - unsigned Bit) { +const Init *VarInit::resolveBitReference(Record &R, const RecordVal *IRV, + unsigned Bit) const { if (R.isTemplateArg(getName())) return 0; if (IRV && IRV->getName() != getName()) return 0; RecordVal *RV = R.getValue(getName()); assert(RV && "Reference to a non-existent variable?"); - assert(dynamic_cast(RV->getValue())); - BitsInit *BI = (BitsInit*)RV->getValue(); + assert(dynamic_cast(RV->getValue())); + const BitsInit *BI = (const BitsInit*)RV->getValue(); assert(Bit < BI->getNumBits() && "Bit reference out of range!"); - Init *B = BI->getBit(Bit); + const Init *B = BI->getBit(Bit); // If the bit is set to some value, or if we are resolving a reference to a // specific variable and that variable is explicitly unset, then replace the // VarBitInit with it. - if (IRV || !dynamic_cast(B)) + if (IRV || !dynamic_cast(B)) return B; return 0; } -Init *VarInit::resolveListElementReference(Record &R, const RecordVal *IRV, - unsigned Elt) { +const Init *VarInit::resolveListElementReference(Record &R, + const RecordVal *IRV, + unsigned Elt) const { if (R.isTemplateArg(getName())) return 0; if (IRV && IRV->getName() != getName()) return 0; RecordVal *RV = R.getValue(getName()); assert(RV && "Reference to a non-existent variable?"); - ListInit *LI = dynamic_cast(RV->getValue()); + const ListInit *LI = dynamic_cast(RV->getValue()); if (!LI) { - VarInit *VI = dynamic_cast(RV->getValue()); + const VarInit *VI = dynamic_cast(RV->getValue()); assert(VI && "Invalid list element!"); return new VarListElementInit(VI, Elt); } if (Elt >= LI->getSize()) return 0; // Out of range reference. - Init *E = LI->getElement(Elt); + const Init *E = LI->getElement(Elt); // If the element is set to some value, or if we are resolving a reference // to a specific variable and that variable is explicitly unset, then // replace the VarListElementInit with it. - if (IRV || !dynamic_cast(E)) + if (IRV || !dynamic_cast(E)) return E; return 0; } @@ -1125,15 +1136,15 @@ RecTy *VarInit::getFieldType(const std::string &FieldName) const { return 0; } -Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, - const std::string &FieldName) const { +const Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, + const std::string &FieldName) const { if (dynamic_cast(getType())) if (const RecordVal *Val = R.getValue(VarName)) { - if (RV != Val && (RV || dynamic_cast(Val->getValue()))) + if (RV != Val && (RV || dynamic_cast(Val->getValue()))) return 0; - Init *TheInit = Val->getValue(); + const Init *TheInit = Val->getValue(); assert(TheInit != this && "Infinite loop detected!"); - if (Init *I = TheInit->getFieldInit(R, RV, FieldName)) + if (const Init *I = TheInit->getFieldInit(R, RV, FieldName)) return I; else return 0; @@ -1146,9 +1157,9 @@ Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// -Init *VarInit::resolveReferences(Record &R, const RecordVal *RV) { +const Init *VarInit::resolveReferences(Record &R, const RecordVal *RV) const { if (RecordVal *Val = R.getValue(VarName)) - if (RV == Val || (RV == 0 && !dynamic_cast(Val->getValue()))) + if (RV == Val || (RV == 0 && !dynamic_cast(Val->getValue()))) return Val->getValue(); return this; } @@ -1157,8 +1168,9 @@ std::string VarBitInit::getAsString() const { return TI->getAsString() + "{" + utostr(Bit) + "}"; } -Init *VarBitInit::resolveReferences(Record &R, const RecordVal *RV) { - if (Init *I = getVariable()->resolveBitReference(R, RV, getBitNum())) +const Init *VarBitInit::resolveReferences(Record &R, + const RecordVal *RV) const { + if (const Init *I = getVariable()->resolveBitReference(R, RV, getBitNum())) return I; return this; } @@ -1167,22 +1179,25 @@ std::string VarListElementInit::getAsString() const { return TI->getAsString() + "[" + utostr(Element) + "]"; } -Init *VarListElementInit::resolveReferences(Record &R, const RecordVal *RV) { - if (Init *I = getVariable()->resolveListElementReference(R, RV, +const Init *VarListElementInit::resolveReferences(Record &R, + const RecordVal *RV) const { + if (const Init *I = getVariable()->resolveListElementReference(R, RV, getElementNum())) return I; return this; } -Init *VarListElementInit::resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { +const Init *VarListElementInit::resolveBitReference(Record &R, + const RecordVal *RV, + unsigned Bit) const { // FIXME: This should be implemented, to support references like: // bit B = AA[0]{1}; return 0; } -Init *VarListElementInit:: -resolveListElementReference(Record &R, const RecordVal *RV, unsigned Elt) { +const Init *VarListElementInit:: +resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const { // FIXME: This should be implemented, to support references like: // int B = AA[0][1]; return 0; @@ -1198,8 +1213,8 @@ RecTy *DefInit::getFieldType(const std::string &FieldName) const { return 0; } -Init *DefInit::getFieldInit(Record &R, const RecordVal *RV, - const std::string &FieldName) const { +const Init *DefInit::getFieldInit(Record &R, const RecordVal *RV, + const std::string &FieldName) const { return Def->getValue(FieldName)->getValue(); } @@ -1208,41 +1223,42 @@ std::string DefInit::getAsString() const { return Def->getName(); } -Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { - if (Init *BitsVal = Rec->getFieldInit(R, RV, FieldName)) - if (BitsInit *BI = dynamic_cast(BitsVal)) { +const Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { + if (const Init *BitsVal = Rec->getFieldInit(R, RV, FieldName)) + if (const BitsInit *BI = dynamic_cast(BitsVal)) { assert(Bit < BI->getNumBits() && "Bit reference out of range!"); - Init *B = BI->getBit(Bit); + const Init *B = BI->getBit(Bit); - if (dynamic_cast(B)) // If the bit is set. + if (dynamic_cast(B)) // If the bit is set. return B; // Replace the VarBitInit with it. } return 0; } -Init *FieldInit::resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) { - if (Init *ListVal = Rec->getFieldInit(R, RV, FieldName)) - if (ListInit *LI = dynamic_cast(ListVal)) { +const Init *FieldInit::resolveListElementReference(Record &R, + const RecordVal *RV, + unsigned Elt) const { + if (const Init *ListVal = Rec->getFieldInit(R, RV, FieldName)) + if (const ListInit *LI = dynamic_cast(ListVal)) { if (Elt >= LI->getSize()) return 0; - Init *E = LI->getElement(Elt); + const Init *E = LI->getElement(Elt); // If the element is set to some value, or if we are resolving a // reference to a specific variable and that variable is explicitly // unset, then replace the VarListElementInit with it. - if (RV || !dynamic_cast(E)) + if (RV || !dynamic_cast(E)) return E; } return 0; } -Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) { - Init *NewRec = RV ? Rec->resolveReferences(R, RV) : Rec; +const Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) const { + const Init *NewRec = RV ? Rec->resolveReferences(R, RV) : Rec; - Init *BitsVal = NewRec->getFieldInit(R, RV, FieldName); + const Init *BitsVal = NewRec->getFieldInit(R, RV, FieldName); if (BitsVal) { - Init *BVR = BitsVal->resolveReferences(R, RV); + const Init *BVR = BitsVal->resolveReferences(R, RV); return BVR->isComplete() ? BVR : this; } @@ -1252,12 +1268,12 @@ Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) { return this; } -Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) { - std::vector NewArgs; +const Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) const { + std::vector NewArgs; for (unsigned i = 0, e = Args.size(); i != e; ++i) NewArgs.push_back(Args[i]->resolveReferences(R, RV)); - Init *Op = Val->resolveReferences(R, RV); + const Init *Op = Val->resolveReferences(R, RV); if (Args != NewArgs || Op != Val) return new DagInit(Op, ValName, NewArgs, ArgNames); @@ -1329,7 +1345,7 @@ void Record::setName(const std::string &Name) { /// references. void Record::resolveReferencesTo(const RecordVal *RV) { for (unsigned i = 0, e = Values.size(); i != e; ++i) { - if (Init *V = Values[i].getValue()) + if (const Init *V = Values[i].getValue()) Values[i].setValue(V->resolveReferences(*this, RV)); } } @@ -1374,7 +1390,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const Record &R) { /// getValueInit - Return the initializer for a value with the specified name, /// or throw an exception if the field does not exist. /// -Init *Record::getValueInit(StringRef FieldName) const { +const Init *Record::getValueInit(StringRef FieldName) const { const RecordVal *R = getValue(FieldName); if (R == 0 || R->getValue() == 0) throw "Record `" + getName() + "' does not have a field named `" + @@ -1403,13 +1419,13 @@ std::string Record::getValueAsString(StringRef FieldName) const { /// its value as a BitsInit, throwing an exception if the field does not exist /// or if the value is not the right type. /// -BitsInit *Record::getValueAsBitsInit(StringRef FieldName) const { +const BitsInit *Record::getValueAsBitsInit(StringRef FieldName) const { const RecordVal *R = getValue(FieldName); if (R == 0 || R->getValue() == 0) throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (BitsInit *BI = dynamic_cast(R->getValue())) + if (const BitsInit *BI = dynamic_cast(R->getValue())) return BI; throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have a BitsInit initializer!"; @@ -1419,13 +1435,13 @@ BitsInit *Record::getValueAsBitsInit(StringRef FieldName) const { /// its value as a ListInit, throwing an exception if the field does not exist /// or if the value is not the right type. /// -ListInit *Record::getValueAsListInit(StringRef FieldName) const { +const ListInit *Record::getValueAsListInit(StringRef FieldName) const { const RecordVal *R = getValue(FieldName); if (R == 0 || R->getValue() == 0) throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (ListInit *LI = dynamic_cast(R->getValue())) + if (const ListInit *LI = dynamic_cast(R->getValue())) return LI; throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have a list initializer!"; @@ -1437,10 +1453,10 @@ ListInit *Record::getValueAsListInit(StringRef FieldName) const { /// std::vector Record::getValueAsListOfDefs(StringRef FieldName) const { - ListInit *List = getValueAsListInit(FieldName); + const ListInit *List = getValueAsListInit(FieldName); std::vector Defs; for (unsigned i = 0; i < List->getSize(); i++) { - if (DefInit *DI = dynamic_cast(List->getElement(i))) { + if (const DefInit *DI = dynamic_cast(List->getElement(i))) { Defs.push_back(DI->getDef()); } else { throw "Record `" + getName() + "', field `" + FieldName.str() + @@ -1460,7 +1476,7 @@ int64_t Record::getValueAsInt(StringRef FieldName) const { throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (IntInit *II = dynamic_cast(R->getValue())) + if (const IntInit *II = dynamic_cast(R->getValue())) return II->getValue(); throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have an int initializer!"; @@ -1472,10 +1488,10 @@ int64_t Record::getValueAsInt(StringRef FieldName) const { /// std::vector Record::getValueAsListOfInts(StringRef FieldName) const { - ListInit *List = getValueAsListInit(FieldName); + const ListInit *List = getValueAsListInit(FieldName); std::vector Ints; for (unsigned i = 0; i < List->getSize(); i++) { - if (IntInit *II = dynamic_cast(List->getElement(i))) { + if (const IntInit *II = dynamic_cast(List->getElement(i))) { Ints.push_back(II->getValue()); } else { throw "Record `" + getName() + "', field `" + FieldName.str() + @@ -1491,10 +1507,10 @@ Record::getValueAsListOfInts(StringRef FieldName) const { /// std::vector Record::getValueAsListOfStrings(StringRef FieldName) const { - ListInit *List = getValueAsListInit(FieldName); + const ListInit *List = getValueAsListInit(FieldName); std::vector Strings; for (unsigned i = 0; i < List->getSize(); i++) { - if (StringInit *II = dynamic_cast(List->getElement(i))) { + if (const StringInit *II = dynamic_cast(List->getElement(i))) { Strings.push_back(II->getValue()); } else { throw "Record `" + getName() + "', field `" + FieldName.str() + @@ -1514,7 +1530,7 @@ Record *Record::getValueAsDef(StringRef FieldName) const { throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (DefInit *DI = dynamic_cast(R->getValue())) + if (const DefInit *DI = dynamic_cast(R->getValue())) return DI->getDef(); throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have a def initializer!"; @@ -1530,7 +1546,7 @@ bool Record::getValueAsBit(StringRef FieldName) const { throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (BitInit *BI = dynamic_cast(R->getValue())) + if (const BitInit *BI = dynamic_cast(R->getValue())) return BI->getValue(); throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have a bit initializer!"; @@ -1540,13 +1556,13 @@ bool Record::getValueAsBit(StringRef FieldName) const { /// value as an Dag, throwing an exception if the field does not exist or if /// the value is not the right type. /// -DagInit *Record::getValueAsDag(StringRef FieldName) const { +const DagInit *Record::getValueAsDag(StringRef FieldName) const { const RecordVal *R = getValue(FieldName); if (R == 0 || R->getValue() == 0) throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - if (DagInit *DI = dynamic_cast(R->getValue())) + if (const DagInit *DI = dynamic_cast(R->getValue())) return DI; throw "Record `" + getName() + "', field `" + FieldName.str() + "' does not have a dag initializer!"; diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index 6ec18fb..0ba4aec 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -82,31 +82,31 @@ public: ListRecTy *getListTy(); public: // These methods should only be called from subclasses of Init - virtual Init *convertValue( UnsetInit *UI) { return 0; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { - return convertValue((TypedInit*)UI); + virtual const Init *convertValue( const UnsetInit *UI) { return 0; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { + return convertValue((const TypedInit*)UI); } - virtual Init *convertValue( BinOpInit *UI) { - return convertValue((TypedInit*)UI); + virtual const Init *convertValue( const BinOpInit *UI) { + return convertValue((const TypedInit*)UI); } - virtual Init *convertValue( TernOpInit *UI) { - return convertValue((TypedInit*)UI); + virtual const Init *convertValue( const TernOpInit *UI) { + return convertValue((const TypedInit*)UI); } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( TypedInit *TI) { return 0; } - virtual Init *convertValue( VarInit *VI) { - return convertValue((TypedInit*)VI); + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const TypedInit *TI) { return 0; } + virtual const Init *convertValue( const VarInit *VI) { + return convertValue((const TypedInit*)VI); } - virtual Init *convertValue( FieldInit *FI) { - return convertValue((TypedInit*)FI); + virtual const Init *convertValue( const FieldInit *FI) { + return convertValue((const TypedInit*)FI); } public: // These methods should only be called by subclasses of RecTy. @@ -136,22 +136,22 @@ class BitRecTy : public RecTy { public: static BitRecTy *get() { return &Shared; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return (Init*)BI; } - virtual Init *convertValue( BitsInit *BI); - virtual Init *convertValue( IntInit *II); - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return (Init*)VB; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return (const Init*)BI; } + virtual const Init *convertValue( const BitsInit *BI); + virtual const Init *convertValue( const IntInit *II); + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return (const Init*)VB; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const { return "bit"; } @@ -181,22 +181,22 @@ public: unsigned getNumBits() const { return Size; } - virtual Init *convertValue( UnsetInit *UI); - virtual Init *convertValue( BitInit *UI); - virtual Init *convertValue( BitsInit *BI); - virtual Init *convertValue( IntInit *II); - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI); + virtual const Init *convertValue( const BitInit *UI); + virtual const Init *convertValue( const BitsInit *BI); + virtual const Init *convertValue( const IntInit *II); + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const; @@ -225,22 +225,22 @@ class IntRecTy : public RecTy { public: static IntRecTy *get() { return &Shared; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI); - virtual Init *convertValue( BitsInit *BI); - virtual Init *convertValue( IntInit *II) { return (Init*)II; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI); + virtual const Init *convertValue( const BitsInit *BI); + virtual const Init *convertValue( const IntInit *II) { return (const Init*)II; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const { return "int"; } @@ -267,23 +267,23 @@ class StringRecTy : public RecTy { public: static StringRecTy *get() { return &Shared; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return (Init*)SI; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( UnOpInit *BO); - virtual Init *convertValue( BinOpInit *BO); - virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue(BO);} - - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return (const Init*)SI; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const UnOpInit *BO); + virtual const Init *convertValue( const BinOpInit *BO); + virtual const Init *convertValue( const TernOpInit *BO) { return RecTy::convertValue(BO);} + + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const { return "string"; } @@ -314,22 +314,22 @@ public: static ListRecTy *get(RecTy *T) { return T->getListTy(); } RecTy *getElementType() const { return Ty; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI); - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI); + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const; @@ -357,22 +357,22 @@ class CodeRecTy : public RecTy { public: static CodeRecTy *get() { return &Shared; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return (Init*)CI; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return (const Init*)CI; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const { return "code"; } @@ -397,22 +397,22 @@ class DagRecTy : public RecTy { public: static DagRecTy *get() { return &Shared; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( DefInit *DI) { return 0; } - virtual Init *convertValue( UnOpInit *BO); - virtual Init *convertValue( BinOpInit *BO); - virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue(BO);} - virtual Init *convertValue( DagInit *CI) { return (Init*)CI; } - virtual Init *convertValue( TypedInit *TI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const DefInit *DI) { return 0; } + virtual const Init *convertValue( const UnOpInit *BO); + virtual const Init *convertValue( const BinOpInit *BO); + virtual const Init *convertValue( const TernOpInit *BO) { return RecTy::convertValue(BO);} + virtual const Init *convertValue( const DagInit *CI) { return (const Init*)CI; } + virtual const Init *convertValue( const TypedInit *TI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const { return "dag"; } @@ -443,22 +443,22 @@ public: Record *getRecord() const { return Rec; } - virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } - virtual Init *convertValue( BitInit *BI) { return 0; } - virtual Init *convertValue( BitsInit *BI) { return 0; } - virtual Init *convertValue( IntInit *II) { return 0; } - virtual Init *convertValue(StringInit *SI) { return 0; } - virtual Init *convertValue( ListInit *LI) { return 0; } - virtual Init *convertValue( CodeInit *CI) { return 0; } - virtual Init *convertValue(VarBitInit *VB) { return 0; } - virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue(UI);} - virtual Init *convertValue( DefInit *DI); - virtual Init *convertValue( DagInit *DI) { return 0; } - virtual Init *convertValue( TypedInit *VI); - virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(VI);} - virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(FI);} + virtual const Init *convertValue( const UnsetInit *UI) { return (const Init*)UI; } + virtual const Init *convertValue( const BitInit *BI) { return 0; } + virtual const Init *convertValue( const BitsInit *BI) { return 0; } + virtual const Init *convertValue( const IntInit *II) { return 0; } + virtual const Init *convertValue(const StringInit *SI) { return 0; } + virtual const Init *convertValue( const ListInit *LI) { return 0; } + virtual const Init *convertValue( const CodeInit *CI) { return 0; } + virtual const Init *convertValue(const VarBitInit *VB) { return 0; } + virtual const Init *convertValue( const UnOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const BinOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const TernOpInit *UI) { return RecTy::convertValue(UI);} + virtual const Init *convertValue( const DefInit *DI); + virtual const Init *convertValue( const DagInit *DI) { return 0; } + virtual const Init *convertValue( const TypedInit *VI); + virtual const Init *convertValue( const VarInit *VI) { return RecTy::convertValue(VI);} + virtual const Init *convertValue( const FieldInit *FI) { return RecTy::convertValue(FI);} std::string getAsString() const; @@ -506,14 +506,15 @@ public: /// function that should be overridden to call the appropriate /// RecTy::convertValue method. /// - virtual Init *convertInitializerTo(RecTy *Ty) = 0; + virtual const Init *convertInitializerTo(RecTy *Ty) const = 0; /// convertInitializerBitRange - This method is used to implement the bitrange /// selection operator. Given an initializer, it selects the specified bits /// out, returning them as a new init of bits type. If it is not legal to use /// the bit subscript operator on this initializer, return null. /// - virtual Init *convertInitializerBitRange(const std::vector &Bits) { + virtual const Init * + convertInitializerBitRange(const std::vector &Bits) const { return 0; } @@ -522,7 +523,8 @@ public: /// elements, returning them as a new init of list type. If it is not legal /// to take a slice of this, return null. /// - virtual Init *convertInitListSlice(const std::vector &Elements) { + virtual const Init * + convertInitListSlice(const std::vector &Elements) const { return 0; } @@ -536,8 +538,8 @@ public: /// initializer for the specified field. If getFieldType returns non-null /// this method should return non-null, otherwise it returns null. /// - virtual Init *getFieldInit(Record &R, const RecordVal *RV, - const std::string &FieldName) const { + virtual const Init *getFieldInit(Record &R, const RecordVal *RV, + const std::string &FieldName) const { return 0; } @@ -546,7 +548,7 @@ public: /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// - virtual Init *resolveReferences(Record &R, const RecordVal *RV) { + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const { return this; } }; @@ -565,8 +567,10 @@ public: RecTy *getType() const { return Ty; } - virtual Init *convertInitializerBitRange(const std::vector &Bits); - virtual Init *convertInitListSlice(const std::vector &Elements); + virtual const Init * + convertInitializerBitRange(const std::vector &Bits) const; + virtual const Init * + convertInitListSlice(const std::vector &Elements) const; /// getFieldType - This method is used to implement the FieldInit class. /// Implementors of this method should return the type of the named field if @@ -578,14 +582,14 @@ public: /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. /// - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) = 0; + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const = 0; /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) = 0; + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const = 0; }; @@ -593,7 +597,7 @@ public: /// class UnsetInit : public Init { public: - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -611,7 +615,7 @@ public: bool getValue() const { return Value; } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -622,22 +626,23 @@ public: /// It contains a vector of bits, whose size is determined by the type. /// class BitsInit : public Init { - std::vector Bits; + std::vector Bits; public: explicit BitsInit(unsigned Size) : Bits(Size) {} - BitsInit(ArrayRef Range) : Bits(Range.begin(), Range.end()) {} + BitsInit(ArrayRef Range) : Bits(Range.begin(), Range.end()) {} unsigned getNumBits() const { return Bits.size(); } - Init *getBit(unsigned Bit) const { + const Init *getBit(unsigned Bit) const { assert(Bit < Bits.size() && "Bit index out of range!"); return Bits[Bit]; } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - virtual Init *convertInitializerBitRange(const std::vector &Bits); + virtual const Init * + convertInitializerBitRange(const std::vector &Bits) const; virtual bool isComplete() const { for (unsigned i = 0; i != getNumBits(); ++i) @@ -651,7 +656,7 @@ public: } virtual std::string getAsString() const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; }; @@ -664,10 +669,11 @@ public: int64_t getValue() const { return Value; } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - virtual Init *convertInitializerBitRange(const std::vector &Bits); + virtual const Init * + convertInitializerBitRange(const std::vector &Bits) const; virtual std::string getAsString() const; @@ -675,8 +681,8 @@ public: /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. /// - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { assert(0 && "Illegal bit reference off int"); return 0; } @@ -684,8 +690,8 @@ public: /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) { + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const { assert(0 && "Illegal element reference off int"); return 0; } @@ -702,7 +708,7 @@ public: const std::string &getValue() const { return Value; } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -712,8 +718,8 @@ public: /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. /// - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { assert(0 && "Illegal bit reference off string"); return 0; } @@ -721,8 +727,8 @@ public: /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) { + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const { assert(0 && "Illegal element reference off string"); return 0; } @@ -737,7 +743,7 @@ public: const std::string &getValue() const { return Value; } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -747,28 +753,28 @@ public: /// ListInit - [AL, AH, CL] - Represent a list of defs /// class ListInit : public TypedInit { - std::vector Values; + std::vector Values; public: - typedef std::vector::const_iterator const_iterator; + typedef std::vector::const_iterator const_iterator; - explicit ListInit(std::vector &Vs, RecTy *EltTy) + explicit ListInit(std::vector &Vs, RecTy *EltTy) : TypedInit(ListRecTy::get(EltTy)) { Values.swap(Vs); } - explicit ListInit(ArrayRef Range, RecTy *EltTy) + explicit ListInit(ArrayRef Range, RecTy *EltTy) : TypedInit(ListRecTy::get(EltTy)), Values(Range.begin(), Range.end()) {} unsigned getSize() const { return Values.size(); } - Init *getElement(unsigned i) const { + const Init *getElement(unsigned i) const { assert(i < Values.size() && "List element index out of range!"); return Values[i]; } Record *getElementAsRecord(unsigned i) const; - Init *convertInitListSlice(const std::vector &Elements); + const Init *convertInitListSlice(const std::vector &Elements) const; - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -777,7 +783,7 @@ public: /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const; @@ -791,8 +797,8 @@ public: /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. /// - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { assert(0 && "Illegal bit reference off list"); return 0; } @@ -800,8 +806,8 @@ public: /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt); + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const; }; @@ -812,23 +818,24 @@ public: OpInit(RecTy *Type) : TypedInit(Type) {} // Clone - Clone this operator, replacing arguments with the new list - virtual OpInit *clone(std::vector &Operands) = 0; + virtual const OpInit *clone(std::vector &Operands) const = 0; virtual int getNumOperands() const = 0; - virtual Init *getOperand(int i) = 0; + virtual const Init *getOperand(int i) const = 0; // Fold - If possible, fold this to a simpler init. Return this if not // possible to fold. - virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) = 0; + virtual const Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const = 0; - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit); - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt); + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const; + virtual const Init *resolveListElementReference(Record &R, + const RecordVal *RV, + unsigned Elt) const; }; @@ -839,33 +846,33 @@ public: enum UnaryOp { CAST, HEAD, TAIL, EMPTY }; private: UnaryOp Opc; - Init *LHS; + const Init *LHS; public: - UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type) : + UnOpInit(UnaryOp opc, const Init *lhs, RecTy *Type) : OpInit(Type), Opc(opc), LHS(lhs) { } // Clone - Clone this operator, replacing arguments with the new list - virtual OpInit *clone(std::vector &Operands) { + virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 1 && "Wrong number of operands for unary operation"); return new UnOpInit(getOpcode(), *Operands.begin(), getType()); } int getNumOperands() const { return 1; } - Init *getOperand(int i) { + const Init *getOperand(int i) const { assert(i == 0 && "Invalid operand id for unary operator"); return getOperand(); } UnaryOp getOpcode() const { return Opc; } - Init *getOperand() const { return LHS; } + const Init *getOperand() const { return LHS; } // Fold - If possible, fold this to a simpler init. Return this if not // possible to fold. - Init *Fold(Record *CurRec, MultiClass *CurMultiClass); + const Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const; }; @@ -877,21 +884,21 @@ public: enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; private: BinaryOp Opc; - Init *LHS, *RHS; + const Init *LHS, *RHS; public: - BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) : + BinOpInit(BinaryOp opc, const Init *lhs, const Init *rhs, RecTy *Type) : OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) { } // Clone - Clone this operator, replacing arguments with the new list - virtual OpInit *clone(std::vector &Operands) { + virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 2 && "Wrong number of operands for binary operation"); return new BinOpInit(getOpcode(), Operands[0], Operands[1], getType()); } int getNumOperands() const { return 2; } - Init *getOperand(int i) { + const Init *getOperand(int i) const { assert((i == 0 || i == 1) && "Invalid operand id for binary operator"); if (i == 0) { return getLHS(); @@ -901,14 +908,14 @@ public: } BinaryOp getOpcode() const { return Opc; } - Init *getLHS() const { return LHS; } - Init *getRHS() const { return RHS; } + const Init *getLHS() const { return LHS; } + const Init *getRHS() const { return RHS; } // Fold - If possible, fold this to a simpler init. Return this if not // possible to fold. - Init *Fold(Record *CurRec, MultiClass *CurMultiClass); + const Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const; }; @@ -920,14 +927,15 @@ public: enum TernaryOp { SUBST, FOREACH, IF }; private: TernaryOp Opc; - Init *LHS, *MHS, *RHS; + const Init *LHS, *MHS, *RHS; public: - TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs, RecTy *Type) : + TernOpInit(TernaryOp opc, const Init *lhs, const Init *mhs, const Init *rhs, + RecTy *Type) : OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) { } // Clone - Clone this operator, replacing arguments with the new list - virtual OpInit *clone(std::vector &Operands) { + virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 3 && "Wrong number of operands for ternary operation"); return new TernOpInit(getOpcode(), Operands[0], Operands[1], Operands[2], @@ -935,7 +943,7 @@ public: } int getNumOperands() const { return 3; } - Init *getOperand(int i) { + const Init *getOperand(int i) const { assert((i == 0 || i == 1 || i == 2) && "Invalid operand id for ternary operator"); if (i == 0) { @@ -948,17 +956,17 @@ public: } TernaryOp getOpcode() const { return Opc; } - Init *getLHS() const { return LHS; } - Init *getMHS() const { return MHS; } - Init *getRHS() const { return RHS; } + const Init *getLHS() const { return LHS; } + const Init *getMHS() const { return MHS; } + const Init *getRHS() const { return RHS; } // Fold - If possible, fold this to a simpler init. Return this if not // possible to fold. - Init *Fold(Record *CurRec, MultiClass *CurMultiClass); + const Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; virtual bool isComplete() const { return false; } - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const; }; @@ -972,27 +980,27 @@ public: explicit VarInit(const std::string &VN, RecTy *T) : TypedInit(T), VarName(VN) {} - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } const std::string &getName() const { return VarName; } - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit); - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt); + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const; + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const; virtual RecTy *getFieldType(const std::string &FieldName) const; - virtual Init *getFieldInit(Record &R, const RecordVal *RV, - const std::string &FieldName) const; + virtual const Init *getFieldInit(Record &R, const RecordVal *RV, + const std::string &FieldName) const; /// resolveReferences - This method is used by classes that refer to other /// variables which may not be defined at the time they expression is formed. /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const { return VarName; } }; @@ -1001,57 +1009,58 @@ public: /// VarBitInit - Opcode{0} - Represent access to one bit of a variable or field. /// class VarBitInit : public Init { - TypedInit *TI; + const TypedInit *TI; unsigned Bit; public: - VarBitInit(TypedInit *T, unsigned B) : TI(T), Bit(B) { + VarBitInit(const TypedInit *T, unsigned B) : TI(T), Bit(B) { assert(T->getType() && dynamic_cast(T->getType()) && ((BitsRecTy*)T->getType())->getNumBits() > B && "Illegal VarBitInit expression!"); } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - TypedInit *getVariable() const { return TI; } + const TypedInit *getVariable() const { return TI; } unsigned getBitNum() const { return Bit; } virtual std::string getAsString() const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; }; /// VarListElementInit - List[4] - Represent access to one element of a var or /// field. class VarListElementInit : public TypedInit { - TypedInit *TI; + const TypedInit *TI; unsigned Element; public: - VarListElementInit(TypedInit *T, unsigned E) + VarListElementInit(const TypedInit *T, unsigned E) : TypedInit(dynamic_cast(T->getType())->getElementType()), TI(T), Element(E) { assert(T->getType() && dynamic_cast(T->getType()) && "Illegal VarBitInit expression!"); } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - TypedInit *getVariable() const { return TI; } + const TypedInit *getVariable() const { return TI; } unsigned getElementNum() const { return Element; } - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit); + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const; /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt); + virtual const Init *resolveListElementReference(Record &R, + const RecordVal *RV, + unsigned Elt) const; virtual std::string getAsString() const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; }; /// DefInit - AL - Represent a reference to a 'def' in the description @@ -1063,17 +1072,18 @@ class DefInit : public TypedInit { public: static DefInit *get(Record*); - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } Record *getDef() const { return Def; } - //virtual Init *convertInitializerBitRange(const std::vector &Bits); + //virtual const Init * + //convertInitializerBitRange(const std::vector &Bits); virtual RecTy *getFieldType(const std::string &FieldName) const; - virtual Init *getFieldInit(Record &R, const RecordVal *RV, - const std::string &FieldName) const; + virtual const Init *getFieldInit(Record &R, const RecordVal *RV, + const std::string &FieldName) const; virtual std::string getAsString() const; @@ -1081,8 +1091,8 @@ public: /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. /// - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { assert(0 && "Illegal bit reference off def"); return 0; } @@ -1090,8 +1100,8 @@ public: /// resolveListElementReference - This method is used to implement /// VarListElementInit::resolveReferences. If the list element is resolvable /// now, we return the resolved value, otherwise we return null. - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) { + virtual const Init *resolveListElementReference(Record &R, const RecordVal *RV, + unsigned Elt) const { assert(0 && "Illegal element reference off def"); return 0; } @@ -1101,24 +1111,25 @@ public: /// FieldInit - X.Y - Represent a reference to a subfield of a variable /// class FieldInit : public TypedInit { - Init *Rec; // Record we are referring to + const Init *Rec; // Record we are referring to std::string FieldName; // Field we are accessing public: - FieldInit(Init *R, const std::string &FN) + FieldInit(const Init *R, const std::string &FN) : TypedInit(R->getFieldType(FN)), Rec(R), FieldName(FN) { assert(getType() && "FieldInit with non-record type!"); } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit); - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt); + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const; + virtual const Init *resolveListElementReference(Record &R, + const RecordVal *RV, + unsigned Elt) const; - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const { return Rec->getAsString() + "." + FieldName; @@ -1130,13 +1141,13 @@ public: /// argument can have a name associated with it. /// class DagInit : public TypedInit { - Init *Val; + const Init *Val; std::string ValName; - std::vector Args; + std::vector Args; std::vector ArgNames; public: - DagInit(Init *V, std::string VN, - const std::vector > &args) + DagInit(const Init *V, std::string VN, + const std::vector > &args) : TypedInit(DagRecTy::get()), Val(V), ValName(VN) { Args.reserve(args.size()); ArgNames.reserve(args.size()); @@ -1145,21 +1156,21 @@ public: ArgNames.push_back(args[i].second); } } - DagInit(Init *V, std::string VN, const std::vector &args, + DagInit(const Init *V, std::string VN, const std::vector &args, const std::vector &argNames) : TypedInit(DagRecTy::get()), Val(V), ValName(VN), Args(args), ArgNames(argNames) { } - virtual Init *convertInitializerTo(RecTy *Ty) { + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } - Init *getOperator() const { return Val; } + const Init *getOperator() const { return Val; } const std::string &getName() const { return ValName; } unsigned getNumArgs() const { return Args.size(); } - Init *getArg(unsigned Num) const { + const Init *getArg(unsigned Num) const { assert(Num < Args.size() && "Arg number out of range!"); return Args[Num]; } @@ -1168,11 +1179,11 @@ public: return ArgNames[Num]; } - virtual Init *resolveReferences(Record &R, const RecordVal *RV); + virtual const Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual std::string getAsString() const; - typedef std::vector::const_iterator const_arg_iterator; + typedef std::vector::const_iterator const_arg_iterator; typedef std::vector::const_iterator const_name_iterator; inline const_arg_iterator arg_begin() const { return Args.begin(); } @@ -1187,14 +1198,15 @@ public: inline size_t name_size () const { return ArgNames.size(); } inline bool name_empty() const { return ArgNames.empty(); } - virtual Init *resolveBitReference(Record &R, const RecordVal *RV, - unsigned Bit) { + virtual const Init *resolveBitReference(Record &R, const RecordVal *RV, + unsigned Bit) const { assert(0 && "Illegal bit reference off dag"); return 0; } - virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, - unsigned Elt) { + virtual const Init *resolveListElementReference(Record &R, + const RecordVal *RV, + unsigned Elt) const { assert(0 && "Illegal element reference off dag"); return 0; } @@ -1208,7 +1220,7 @@ class RecordVal { std::string Name; RecTy *Ty; unsigned Prefix; - Init *Value; + const Init *Value; public: RecordVal(const std::string &N, RecTy *T, unsigned P); @@ -1216,9 +1228,9 @@ public: unsigned getPrefix() const { return Prefix; } RecTy *getType() const { return Ty; } - Init *getValue() const { return Value; } + const Init *getValue() const { return Value; } - bool setValue(Init *V) { + bool setValue(const Init *V) { if (V) { Value = V->convertInitializerTo(Ty); return Value == 0; @@ -1357,7 +1369,7 @@ public: /// getValueInit - Return the initializer for a value with the specified name, /// or throw an exception if the field does not exist. /// - Init *getValueInit(StringRef FieldName) const; + const Init *getValueInit(StringRef FieldName) const; /// getValueAsString - This method looks up the specified field and returns /// its value as a string, throwing an exception if the field does not exist @@ -1369,13 +1381,13 @@ public: /// its value as a BitsInit, throwing an exception if the field does not exist /// or if the value is not the right type. /// - BitsInit *getValueAsBitsInit(StringRef FieldName) const; + const BitsInit *getValueAsBitsInit(StringRef FieldName) const; /// getValueAsListInit - This method looks up the specified field and returns /// its value as a ListInit, throwing an exception if the field does not exist /// or if the value is not the right type. /// - ListInit *getValueAsListInit(StringRef FieldName) const; + const ListInit *getValueAsListInit(StringRef FieldName) const; /// getValueAsListOfDefs - This method looks up the specified field and /// returns its value as a vector of records, throwing an exception if the @@ -1417,7 +1429,7 @@ public: /// value as an Dag, throwing an exception if the field does not exist or if /// the value is not the right type. /// - DagInit *getValueAsDag(StringRef FieldName) const; + const DagInit *getValueAsDag(StringRef FieldName) const; /// getValueAsCode - This method looks up the specified field and returns /// its value as the string data in a CodeInit, throwing an exception if the diff --git oldutils/TableGen/RegisterInfoEmitter.cpp newutils/TableGen/RegisterInfoEmitter.cpp index 6dad391..41c8829 100644 --- oldutils/TableGen/RegisterInfoEmitter.cpp +++ newutils/TableGen/RegisterInfoEmitter.cpp @@ -725,7 +725,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, if (!V || !V->getValue()) continue; - DefInit *DI = dynamic_cast(V->getValue()); + const DefInit *DI = dynamic_cast(V->getValue()); Record *Alias = DI->getDef(); DwarfRegNums[Reg] = DwarfRegNums[Alias]; } diff --git oldutils/TableGen/SetTheory.cpp newutils/TableGen/SetTheory.cpp index 21ac09c..0287269 100644 --- oldutils/TableGen/SetTheory.cpp +++ newutils/TableGen/SetTheory.cpp @@ -27,14 +27,14 @@ typedef SetTheory::RecVec RecVec; // (add a, b, ...) Evaluate and union all arguments. struct AddOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts) { ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts); } }; // (sub Add, Sub, ...) Set difference. struct SubOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts) { if (Expr->arg_size() < 2) throw "Set difference needs at least two arguments: " + Expr->getAsString(); @@ -49,7 +49,7 @@ struct SubOp : public SetTheory::Operator { // (and S1, S2) Set intersection. struct AndOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts) { if (Expr->arg_size() != 2) throw "Set intersection requires two arguments: " + Expr->getAsString(); RecSet S1, S2; @@ -63,16 +63,16 @@ struct AndOp : public SetTheory::Operator { // SetIntBinOp - Abstract base class for (Op S, N) operators. struct SetIntBinOp : public SetTheory::Operator { - virtual void apply2(SetTheory &ST, DagInit *Expr, + virtual void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) =0; - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts) { if (Expr->arg_size() != 2) throw "Operator requires (Op Set, Int) arguments: " + Expr->getAsString(); RecSet Set; ST.evaluate(Expr->arg_begin()[0], Set); - IntInit *II = dynamic_cast(Expr->arg_begin()[1]); + const IntInit *II = dynamic_cast(Expr->arg_begin()[1]); if (!II) throw "Second argument must be an integer: " + Expr->getAsString(); apply2(ST, Expr, Set, II->getValue(), Elts); @@ -81,7 +81,7 @@ struct SetIntBinOp : public SetTheory::Operator { // (shl S, N) Shift left, remove the first N elements. struct ShlOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N < 0) @@ -93,7 +93,7 @@ struct ShlOp : public SetIntBinOp { // (trunc S, N) Truncate after the first N elements. struct TruncOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N < 0) @@ -110,7 +110,7 @@ struct RotOp : public SetIntBinOp { RotOp(bool Rev) : Reverse(Rev) {} - void apply2(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (Reverse) @@ -129,7 +129,7 @@ struct RotOp : public SetIntBinOp { // (decimate S, N) Pick every N'th element of S. struct DecimateOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N <= 0) @@ -141,25 +141,25 @@ struct DecimateOp : public SetIntBinOp { // (sequence "Format", From, To) Generate a sequence of records by name. struct SequenceOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts) { if (Expr->arg_size() != 3) throw "Bad args to (sequence \"Format\", From, To): " + Expr->getAsString(); std::string Format; - if (StringInit *SI = dynamic_cast(Expr->arg_begin()[0])) + if (const StringInit *SI = dynamic_cast(Expr->arg_begin()[0])) Format = SI->getValue(); else throw "Format must be a string: " + Expr->getAsString(); int64_t From, To; - if (IntInit *II = dynamic_cast(Expr->arg_begin()[1])) + if (const IntInit *II = dynamic_cast(Expr->arg_begin()[1])) From = II->getValue(); else throw "From must be an integer: " + Expr->getAsString(); if (From < 0 || From >= (1 << 30)) throw "From out of range"; - if (IntInit *II = dynamic_cast(Expr->arg_begin()[2])) + if (const IntInit *II = dynamic_cast(Expr->arg_begin()[2])) To = II->getValue(); else throw "From must be an integer: " + Expr->getAsString(); @@ -167,7 +167,7 @@ struct SequenceOp : public SetTheory::Operator { throw "To out of range"; RecordKeeper &Records = - dynamic_cast(*Expr->getOperator()).getDef()->getRecords(); + dynamic_cast(*Expr->getOperator()).getDef()->getRecords(); int Step = From <= To ? 1 : -1; for (To += Step; From != To; From += Step) { @@ -222,9 +222,9 @@ void SetTheory::addFieldExpander(StringRef ClassName, StringRef FieldName) { addExpander(ClassName, new FieldExpander(FieldName)); } -void SetTheory::evaluate(Init *Expr, RecSet &Elts) { +void SetTheory::evaluate(const Init *Expr, RecSet &Elts) { // A def in a list can be a just an element, or it may expand. - if (DefInit *Def = dynamic_cast(Expr)) { + if (const DefInit *Def = dynamic_cast(Expr)) { if (const RecVec *Result = expand(Def->getDef())) return Elts.insert(Result->begin(), Result->end()); Elts.insert(Def->getDef()); @@ -232,14 +232,14 @@ void SetTheory::evaluate(Init *Expr, RecSet &Elts) { } // Lists simply expand. - if (ListInit *LI = dynamic_cast(Expr)) + if (const ListInit *LI = dynamic_cast(Expr)) return evaluate(LI->begin(), LI->end(), Elts); // Anything else must be a DAG. - DagInit *DagExpr = dynamic_cast(Expr); + const DagInit *DagExpr = dynamic_cast(Expr); if (!DagExpr) throw "Invalid set element: " + Expr->getAsString(); - DefInit *OpInit = dynamic_cast(DagExpr->getOperator()); + const DefInit *OpInit = dynamic_cast(DagExpr->getOperator()); if (!OpInit) throw "Bad set expression: " + Expr->getAsString(); Operator *Op = Operators.lookup(OpInit->getDef()->getName()); diff --git oldutils/TableGen/SetTheory.h newutils/TableGen/SetTheory.h index 6e8313b..f6123c7 100644 --- oldutils/TableGen/SetTheory.h +++ newutils/TableGen/SetTheory.h @@ -70,7 +70,7 @@ public: /// apply - Apply this operator to Expr's arguments and insert the result /// in Elts. - virtual void apply(SetTheory&, DagInit *Expr, RecSet &Elts) =0; + virtual void apply(SetTheory&, const DagInit *Expr, RecSet &Elts) =0; }; /// Expander - A callback function that can transform a Record representing a @@ -115,7 +115,7 @@ public: void addOperator(StringRef Name, Operator*); /// evaluate - Evaluate Expr and append the resulting set to Elts. - void evaluate(Init *Expr, RecSet &Elts); + void evaluate(const Init *Expr, RecSet &Elts); /// evaluate - Evaluate a sequence of Inits and append to Elts. template diff --git oldutils/TableGen/TGParser.cpp newutils/TableGen/TGParser.cpp index d8f5d63..1565959 100644 --- oldutils/TableGen/TGParser.cpp +++ newutils/TableGen/TGParser.cpp @@ -28,7 +28,7 @@ namespace llvm { struct SubClassReference { SMLoc RefLoc; Record *Rec; - std::vector TemplateArgs; + std::vector TemplateArgs; SubClassReference() : Rec(0) {} bool isInvalid() const { return Rec == 0; } @@ -37,7 +37,7 @@ struct SubClassReference { struct SubMultiClassReference { SMLoc RefLoc; MultiClass *MC; - std::vector TemplateArgs; + std::vector TemplateArgs; SubMultiClassReference() : MC(0) {} bool isInvalid() const { return MC == 0; } @@ -50,7 +50,7 @@ void SubMultiClassReference::dump() const { MC->dump(); errs() << "Template args:\n"; - for (std::vector::const_iterator i = TemplateArgs.begin(), + for (std::vector::const_iterator i = TemplateArgs.begin(), iend = TemplateArgs.end(); i != iend; ++i) { @@ -80,7 +80,7 @@ bool TGParser::AddValue(Record *CurRec, SMLoc Loc, const RecordVal &RV) { /// SetValue - /// Return true on error, false on success. bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, - const std::vector &BitList, Init *V) { + const std::vector &BitList, const Init *V) { if (!V) return false; if (CurRec == 0) CurRec = &CurMultiClass->Rec; @@ -92,7 +92,7 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, // Do not allow assignments like 'X = X'. This will just cause infinite loops // in the resolution machinery. if (BitList.empty()) - if (VarInit *VI = dynamic_cast(V)) + if (const VarInit *VI = dynamic_cast(V)) if (VI->getName() == ValName) return false; @@ -101,22 +101,22 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, // initializer. // if (!BitList.empty()) { - BitsInit *CurVal = dynamic_cast(RV->getValue()); + const BitsInit *CurVal = dynamic_cast(RV->getValue()); if (CurVal == 0) return Error(Loc, "Value '" + ValName + "' is not a bits type"); // Convert the incoming value to a bits type of the appropriate size... - Init *BI = V->convertInitializerTo(BitsRecTy::get(BitList.size())); + const Init *BI = V->convertInitializerTo(BitsRecTy::get(BitList.size())); if (BI == 0) { V->convertInitializerTo(BitsRecTy::get(BitList.size())); return Error(Loc, "Initializer is not compatible with bit range"); } // We should have a BitsInit type now. - BitsInit *BInit = dynamic_cast(BI); + const BitsInit *BInit = dynamic_cast(BI); assert(BInit != 0); - SmallVector NewBits(CurVal->getNumBits()); + SmallVector NewBits(CurVal->getNumBits()); // Loop over bits, assigning values as appropriate. for (unsigned i = 0, e = BitList.size(); i != e; ++i) { @@ -131,7 +131,7 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, if (NewBits[i] == 0) NewBits[i] = CurVal->getBit(i); - V = new BitsInit(ArrayRef(NewBits)); + V = new BitsInit(ArrayRef(NewBits)); } if (RV->setValue(V)) @@ -633,7 +633,7 @@ RecTy *TGParser::ParseType() { /// IDValue ::= ID [multiclass template argument] /// IDValue ::= ID [def name] /// -Init *TGParser::ParseIDValue(Record *CurRec) { +const Init *TGParser::ParseIDValue(Record *CurRec) { assert(Lex.getCode() == tgtok::Id && "Expected ID in ParseIDValue"); std::string Name = Lex.getCurStrVal(); SMLoc Loc = Lex.getLoc(); @@ -643,7 +643,7 @@ Init *TGParser::ParseIDValue(Record *CurRec) { /// ParseIDValue - This is just like ParseIDValue above, but it assumes the ID /// has already been read. -Init *TGParser::ParseIDValue(Record *CurRec, +const Init *TGParser::ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc) { if (CurRec) { if (const RecordVal *RV = CurRec->getValue(Name)) @@ -677,7 +677,7 @@ Init *TGParser::ParseIDValue(Record *CurRec, /// /// Operation ::= XOperator ['<' Type '>'] '(' Args ')' /// -Init *TGParser::ParseOperation(Record *CurRec) { +const Init *TGParser::ParseOperation(Record *CurRec) { switch (Lex.getCode()) { default: TokError("unknown operation"); @@ -724,15 +724,15 @@ Init *TGParser::ParseOperation(Record *CurRec) { } Lex.Lex(); // eat the '(' - Init *LHS = ParseValue(CurRec); + const Init *LHS = ParseValue(CurRec); if (LHS == 0) return 0; if (Code == UnOpInit::HEAD || Code == UnOpInit::TAIL || Code == UnOpInit::EMPTY) { - ListInit *LHSl = dynamic_cast(LHS); - StringInit *LHSs = dynamic_cast(LHS); - TypedInit *LHSt = dynamic_cast(LHS); + const ListInit *LHSl = dynamic_cast(LHS); + const StringInit *LHSs = dynamic_cast(LHS); + const TypedInit *LHSt = dynamic_cast(LHS); if (LHSl == 0 && LHSs == 0 && LHSt == 0) { TokError("expected list or string type argument in unary operator"); return 0; @@ -758,8 +758,8 @@ Init *TGParser::ParseOperation(Record *CurRec) { return 0; } if (LHSl) { - Init *Item = LHSl->getElement(0); - TypedInit *Itemt = dynamic_cast(Item); + const Init *Item = LHSl->getElement(0); + const TypedInit *Itemt = dynamic_cast(Item); if (Itemt == 0) { TokError("untyped list element in unary operator"); return 0; @@ -825,7 +825,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { } Lex.Lex(); // eat the '(' - SmallVector InitList; + SmallVector InitList; InitList.push_back(ParseValue(CurRec)); if (InitList.back() == 0) return 0; @@ -847,7 +847,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { // shorthand for nesting them. if (Code == BinOpInit::STRCONCAT) { while (InitList.size() > 2) { - Init *RHS = InitList.pop_back_val(); + const Init *RHS = InitList.pop_back_val(); RHS = (new BinOpInit(Code, InitList.back(), RHS, Type)) ->Fold(CurRec, CurMultiClass); InitList.back() = RHS; @@ -888,7 +888,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { } Lex.Lex(); // eat the '(' - Init *LHS = ParseValue(CurRec); + const Init *LHS = ParseValue(CurRec); if (LHS == 0) return 0; if (Lex.getCode() != tgtok::comma) { @@ -897,7 +897,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { } Lex.Lex(); // eat the ',' - Init *MHS = ParseValue(CurRec); + const Init *MHS = ParseValue(CurRec); if (MHS == 0) return 0; if (Lex.getCode() != tgtok::comma) { @@ -906,7 +906,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { } Lex.Lex(); // eat the ',' - Init *RHS = ParseValue(CurRec); + const Init *RHS = ParseValue(CurRec); if (RHS == 0) return 0; if (Lex.getCode() != tgtok::r_paren) { @@ -920,23 +920,23 @@ Init *TGParser::ParseOperation(Record *CurRec) { case tgtok::XIf: { // FIXME: The `!if' operator doesn't handle non-TypedInit well at // all. This can be made much more robust. - TypedInit *MHSt = dynamic_cast(MHS); - TypedInit *RHSt = dynamic_cast(RHS); + const TypedInit *MHSt = dynamic_cast(MHS); + const TypedInit *RHSt = dynamic_cast(RHS); RecTy *MHSTy = 0; RecTy *RHSTy = 0; if (MHSt == 0 && RHSt == 0) { - BitsInit *MHSbits = dynamic_cast(MHS); - BitsInit *RHSbits = dynamic_cast(RHS); + const BitsInit *MHSbits = dynamic_cast(MHS); + const BitsInit *RHSbits = dynamic_cast(RHS); if (MHSbits && RHSbits && MHSbits->getNumBits() == RHSbits->getNumBits()) { Type = BitRecTy::get(); break; } else { - BitInit *MHSbit = dynamic_cast(MHS); - BitInit *RHSbit = dynamic_cast(RHS); + const BitInit *MHSbit = dynamic_cast(MHS); + const BitInit *RHSbit = dynamic_cast(RHS); if (MHSbit && RHSbit) { Type = BitRecTy::get(); @@ -964,7 +964,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { break; } case tgtok::XForEach: { - TypedInit *MHSt = dynamic_cast(MHS); + const TypedInit *MHSt = dynamic_cast(MHS); if (MHSt == 0) { TokError("could not get type for !foreach"); return 0; @@ -973,7 +973,7 @@ Init *TGParser::ParseOperation(Record *CurRec) { break; } case tgtok::XSubst: { - TypedInit *RHSt = dynamic_cast(RHS); + const TypedInit *RHSt = dynamic_cast(RHS); if (RHSt == 0) { TokError("could not get type for !subst"); return 0; @@ -1038,8 +1038,8 @@ RecTy *TGParser::ParseOperatorType() { /// SimpleValue ::= SRLTOK '(' Value ',' Value ')' /// SimpleValue ::= STRCONCATTOK '(' Value ',' Value ')' /// -Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { - Init *R = 0; +const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { + const Init *R = 0; switch (Lex.getCode()) { default: TokError("Unknown token when parsing a value"); break; case tgtok::IntVal: R = new IntInit(Lex.getCurIntVal()); Lex.Lex(); break; @@ -1085,7 +1085,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { return 0; } - std::vector ValueList = ParseValueList(CurRec, Class); + std::vector ValueList = ParseValueList(CurRec, Class); if (ValueList.empty()) return 0; if (Lex.getCode() != tgtok::greater) { @@ -1115,7 +1115,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { case tgtok::l_brace: { // Value ::= '{' ValueList '}' SMLoc BraceLoc = Lex.getLoc(); Lex.Lex(); // eat the '{' - std::vector Vals; + std::vector Vals; if (Lex.getCode() != tgtok::r_brace) { Vals = ParseValueList(CurRec); @@ -1127,10 +1127,10 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { } Lex.Lex(); // eat the '}' - SmallVector NewBits(Vals.size()); + SmallVector NewBits(Vals.size()); for (unsigned i = 0, e = Vals.size(); i != e; ++i) { - Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get()); + const Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get()); if (Bit == 0) { Error(BraceLoc, "Element #" + utostr(i) + " (" + Vals[i]->getAsString()+ ") is not convertable to a bit"); @@ -1138,11 +1138,11 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { } NewBits[Vals.size()-i-1] = Bit; } - return new BitsInit(ArrayRef(NewBits)); + return new BitsInit(ArrayRef(NewBits)); } case tgtok::l_square: { // Value ::= '[' ValueList ']' Lex.Lex(); // eat the '[' - std::vector Vals; + std::vector Vals; RecTy *DeducedEltTy = 0; ListRecTy *GivenListTy = 0; @@ -1190,10 +1190,10 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { // Check elements RecTy *EltTy = 0; - for (std::vector::iterator i = Vals.begin(), ie = Vals.end(); + for (std::vector::iterator i = Vals.begin(), ie = Vals.end(); i != ie; ++i) { - TypedInit *TArg = dynamic_cast(*i); + const TypedInit *TArg = dynamic_cast(*i); if (TArg == 0) { TokError("Untyped list element"); return 0; @@ -1246,7 +1246,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { return 0; } - Init *Operator = ParseValue(CurRec); + const Init *Operator = ParseValue(CurRec); if (Operator == 0) return 0; // If the operator name is present, parse it. @@ -1260,7 +1260,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { Lex.Lex(); // eat the VarName. } - std::vector > DagArgs; + std::vector > DagArgs; if (Lex.getCode() != tgtok::r_paren) { DagArgs = ParseDagArgList(CurRec); if (DagArgs.empty()) return 0; @@ -1302,8 +1302,8 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { /// ValueSuffix ::= '[' BitList ']' /// ValueSuffix ::= '.' ID /// -Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType) { - Init *Result = ParseSimpleValue(CurRec, ItemType); +const Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType) { + const Init *Result = ParseSimpleValue(CurRec, ItemType); if (Result == 0) return 0; // Parse the suffixes now if present. @@ -1373,20 +1373,20 @@ Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType) { /// /// ParseDagArgList ::= Value (':' VARNAME)? /// ParseDagArgList ::= ParseDagArgList ',' Value (':' VARNAME)? -std::vector > +std::vector > TGParser::ParseDagArgList(Record *CurRec) { - std::vector > Result; + std::vector > Result; while (1) { - Init *Val = ParseValue(CurRec); - if (Val == 0) return std::vector >(); + const Init *Val = ParseValue(CurRec); + if (Val == 0) return std::vector >(); // If the variable name is present, add it. std::string VarName; if (Lex.getCode() == tgtok::colon) { if (Lex.Lex() != tgtok::VarName) { // eat the ':' TokError("expected variable name in dag literal"); - return std::vector >(); + return std::vector >(); } VarName = Lex.getCurStrVal(); Lex.Lex(); // eat the VarName. @@ -1408,9 +1408,9 @@ TGParser::ParseDagArgList(Record *CurRec) { /// /// ValueList ::= Value (',' Value) /// -std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, +std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, RecTy *EltTy) { - std::vector Result; + std::vector Result; RecTy *ItemType = EltTy; unsigned int ArgN = 0; if (ArgsRec != 0 && EltTy == 0) { @@ -1421,7 +1421,7 @@ std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, ++ArgN; } Result.push_back(ParseValue(CurRec, ItemType)); - if (Result.back() == 0) return std::vector(); + if (Result.back() == 0) return std::vector(); while (Lex.getCode() == tgtok::comma) { Lex.Lex(); // Eat the comma @@ -1430,7 +1430,7 @@ std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, const std::vector &TArgs = ArgsRec->getTemplateArgs(); if (ArgN >= TArgs.size()) { TokError("too many template arguments"); - return std::vector(); + return std::vector(); } const RecordVal *RV = ArgsRec->getValue(TArgs[ArgN]); assert(RV && "Template argument record not found??"); @@ -1438,7 +1438,7 @@ std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, ++ArgN; } Result.push_back(ParseValue(CurRec, ItemType)); - if (Result.back() == 0) return std::vector(); + if (Result.back() == 0) return std::vector(); } return Result; @@ -1491,7 +1491,7 @@ std::string TGParser::ParseDeclaration(Record *CurRec, if (Lex.getCode() == tgtok::equal) { Lex.Lex(); SMLoc ValLoc = Lex.getLoc(); - Init *Val = ParseValue(CurRec, Type); + const Init *Val = ParseValue(CurRec, Type); if (Val == 0 || SetValue(CurRec, ValLoc, DeclName, std::vector(), Val)) return ""; @@ -1575,7 +1575,7 @@ bool TGParser::ParseBodyItem(Record *CurRec) { RecTy *Type = Field->getType(); - Init *Val = ParseValue(CurRec, Type); + const Init *Val = ParseValue(CurRec, Type); if (Val == 0) return true; if (Lex.getCode() != tgtok::semi) @@ -1775,7 +1775,7 @@ std::vector TGParser::ParseLetList() { } Lex.Lex(); // eat the '='. - Init *Val = ParseValue(0); + const Init *Val = ParseValue(0); if (Val == 0) return std::vector(); // Now that we have everything, add the record. @@ -1949,7 +1949,7 @@ bool TGParser::ParseDefm(MultiClass *CurMultiClass) { // template parameters. MultiClass *MC = MultiClasses[Ref.Rec->getName()]; assert(MC && "Didn't lookup multiclass correctly?"); - std::vector &TemplateVals = Ref.TemplateArgs; + std::vector &TemplateVals = Ref.TemplateArgs; // Verify that the correct number of template arguments were specified. const std::vector &TArgs = MC->Rec.getTemplateArgs(); diff --git oldutils/TableGen/TGParser.h newutils/TableGen/TGParser.h index 8b56b8a..17de468 100644 --- oldutils/TableGen/TGParser.h +++ newutils/TableGen/TGParser.h @@ -33,9 +33,9 @@ namespace llvm { struct LetRecord { std::string Name; std::vector Bits; - Init *Value; + const Init *Value; SMLoc Loc; - LetRecord(const std::string &N, const std::vector &B, Init *V, + LetRecord(const std::string &N, const std::vector &B, const Init *V, SMLoc L) : Name(N), Bits(B), Value(V), Loc(L) { } @@ -73,7 +73,7 @@ public: private: // Semantic analysis methods. bool AddValue(Record *TheRec, SMLoc Loc, const RecordVal &RV); bool SetValue(Record *TheRec, SMLoc Loc, const std::string &ValName, - const std::vector &BitList, Init *V); + const std::vector &BitList, const Init *V); bool AddSubClass(Record *Rec, SubClassReference &SubClass); bool AddSubMultiClass(MultiClass *CurMC, SubMultiClassReference &SubMultiClass); @@ -98,18 +98,18 @@ private: // Parser methods. SubClassReference ParseSubClassReference(Record *CurRec, bool isDefm); SubMultiClassReference ParseSubMultiClassReference(MultiClass *CurMC); - Init *ParseIDValue(Record *CurRec); - Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc); - Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0); - Init *ParseValue(Record *CurRec, RecTy *ItemType = 0); - std::vector ParseValueList(Record *CurRec, Record *ArgsRec = 0, RecTy *EltTy = 0); - std::vector > ParseDagArgList(Record *); + const Init *ParseIDValue(Record *CurRec); + const Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc); + const Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0); + const Init *ParseValue(Record *CurRec, RecTy *ItemType = 0); + std::vector ParseValueList(Record *CurRec, Record *ArgsRec = 0, RecTy *EltTy = 0); + std::vector > ParseDagArgList(Record *); bool ParseOptionalRangeList(std::vector &Ranges); bool ParseOptionalBitList(std::vector &Ranges); std::vector ParseRangeList(); bool ParseRangePiece(std::vector &Ranges); RecTy *ParseType(); - Init *ParseOperation(Record *CurRec); + const Init *ParseOperation(Record *CurRec); RecTy *ParseOperatorType(); std::string ParseObjectName(); Record *ParseClassID(); diff --git oldutils/TableGen/X86RecognizableInstr.cpp newutils/TableGen/X86RecognizableInstr.cpp index ea3bb70..d4ed70a 100644 --- oldutils/TableGen/X86RecognizableInstr.cpp +++ newutils/TableGen/X86RecognizableInstr.cpp @@ -162,7 +162,7 @@ static bool isRegFormat(uint8_t form) { /// @param init - A reference to the BitsInit to be decoded. /// @return - The field, with the first bit in the BitsInit as the lowest /// order bit. -static uint8_t byteFromBitsInit(BitsInit &init) { +static uint8_t byteFromBitsInit(const BitsInit &init) { int width = init.getNumBits(); assert(width <= 8 && "Field is too large for uint8_t!"); @@ -173,7 +173,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) { uint8_t ret = 0; for (index = 0; index < width; index++) { - if (static_cast(init.getBit(index))->getValue()) + if (static_cast(init.getBit(index))->getValue()) ret |= mask; mask <<= 1; @@ -189,7 +189,7 @@ static uint8_t byteFromBitsInit(BitsInit &init) { /// @param name - The name of the field in the record. /// @return - The field, as translated by byteFromBitsInit(). static uint8_t byteFromRec(const Record* rec, const std::string &name) { - BitsInit* bits = rec->getValueAsBitsInit(name); + const BitsInit* bits = rec->getValueAsBitsInit(name); return byteFromBitsInit(*bits); } -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:40 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:40 -0500 Subject: [llvm-commits] [PATCH 05/20] [AVX] Create Inits Via Factory Method In-Reply-To: References: Message-ID: <3dea7b310178f95ca10cdcd160c96d6c999b8f94.1311100070.git.dag@cray.com> Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. --- utils/TableGen/CodeEmitterGen.cpp | 2 +- utils/TableGen/CodeGenDAGPatterns.cpp | 11 +- utils/TableGen/CodeGenRegisters.cpp | 6 +- utils/TableGen/Record.cpp | 225 ++++++++++++++++++++++----------- utils/TableGen/Record.h | 190 +++++++++++++++++++++++----- utils/TableGen/TGParser.cpp | 34 +++--- 6 files changed, 333 insertions(+), 135 deletions(-) diff --git oldutils/TableGen/CodeEmitterGen.cpp newutils/TableGen/CodeEmitterGen.cpp index c11e4d0..ff17df8 100644 --- oldutils/TableGen/CodeEmitterGen.cpp +++ newutils/TableGen/CodeEmitterGen.cpp @@ -56,7 +56,7 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { NewBits[middle] = BI->getBit(middle); } - BitsInit *NewBI = new BitsInit(ArrayRef(NewBits)); + const BitsInit *NewBI = BitsInit::get(ArrayRef(NewBits)); // Update the bits in reversed order so that emitInstrOpBits will get the // correct endianness. diff --git oldutils/TableGen/CodeGenDAGPatterns.cpp newutils/TableGen/CodeGenDAGPatterns.cpp index 2a75849..a1cf63f 100644 --- oldutils/TableGen/CodeGenDAGPatterns.cpp +++ newutils/TableGen/CodeGenDAGPatterns.cpp @@ -1747,9 +1747,10 @@ TreePatternNode *TreePattern::ParseTreePattern(const Init *TheInit, StringRef Op // TreePatternNode of its own. For example: /// (foo GPR, imm) -> (foo GPR, (imm)) if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) - return ParseTreePattern(new DagInit(DI, "", - std::vector >()), - OpName); + return ParseTreePattern( + DagInit::get(DI, "", + std::vector >()), + OpName); // Input argument? TreePatternNode *Res = new TreePatternNode(DI, 1); @@ -1860,7 +1861,7 @@ TreePatternNode *TreePattern::ParseTreePattern(const Init *TheInit, StringRef Op else // Otherwise, no chain. Operator = getDAGPatterns().get_intrinsic_wo_chain_sdnode(); - TreePatternNode *IIDNode = new TreePatternNode(new IntInit(IID), 1); + TreePatternNode *IIDNode = new TreePatternNode(IntInit::get(IID), 1); Children.insert(Children.begin(), IIDNode); } @@ -2192,7 +2193,7 @@ void CodeGenDAGPatterns::ParseDefaultOperands() { for (unsigned op = 0, e = DefaultInfo->getNumArgs(); op != e; ++op) Ops.push_back(std::make_pair(DefaultInfo->getArg(op), DefaultInfo->getArgName(op))); - const DagInit *DI = new DagInit(SomeSDNode, "", Ops); + const DagInit *DI = DagInit::get(SomeSDNode, "", Ops); // Create a TreePattern to parse this. TreePattern P(DefaultOps[iter][i], DI, false, *this); diff --git oldutils/TableGen/CodeGenRegisters.cpp newutils/TableGen/CodeGenRegisters.cpp index 298009e..8f4ebfb 100644 --- oldutils/TableGen/CodeGenRegisters.cpp +++ newutils/TableGen/CodeGenRegisters.cpp @@ -183,7 +183,7 @@ struct TupleExpander : SetTheory::Expander { // Precompute some types. Record *RegisterCl = Def->getRecords().getClass("Register"); RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); - const StringInit *BlankName = new StringInit(""); + const StringInit *BlankName = StringInit::get(""); // Zip them up. for (unsigned n = 0; n != Length; ++n) { @@ -216,7 +216,7 @@ struct TupleExpander : SetTheory::Expander { // Replace the sub-register list with Tuple. if (RV.getName() == "SubRegs") - RV.setValue(new ListInit(Tuple, RegisterRecTy)); + RV.setValue(ListInit::get(Tuple, RegisterRecTy)); // Provide a blank AsmName. MC hacks are required anyway. if (RV.getName() == "AsmName") @@ -224,7 +224,7 @@ struct TupleExpander : SetTheory::Expander { // CostPerUse is aggregated from all Tuple members. if (RV.getName() == "CostPerUse") - RV.setValue(new IntInit(CostPerUse)); + RV.setValue(IntInit::get(CostPerUse)); // Copy fields from the RegisterTuples def. if (RV.getName() == "SubRegIndices" || diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index d72a707..3339a22 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -52,7 +52,7 @@ const Init *BitRecTy::convertValue(const IntInit *II) { int64_t Val = II->getValue(); if (Val != 0 && Val != 1) return 0; // Only accept 0 or 1 for a bit! - return new BitInit(Val != 0); + return BitInit::get(Val != 0); } const Init *BitRecTy::convertValue(const TypedInit *VI) { @@ -79,14 +79,14 @@ const Init *BitsRecTy::convertValue(const UnsetInit *UI) { SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - NewBits[i] = new UnsetInit(); + NewBits[i] = UnsetInit::get(); - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } const Init *BitsRecTy::convertValue(const BitInit *UI) { if (Size != 1) return 0; // Can only convert single bit. - return new BitsInit(ArrayRef(UI)); + return BitsInit::get(ArrayRef(UI)); } /// canFitInBitfield - Return true if the number of bits is large enough to hold @@ -109,9 +109,9 @@ const Init *BitsRecTy::convertValue(const IntInit *II) { SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - NewBits[i] = new BitInit(Value & (1LL << i)); + NewBits[i] = BitInit::get(Value & (1LL << i)); - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } const Init *BitsRecTy::convertValue(const BitsInit *BI) { @@ -127,12 +127,12 @@ const Init *BitsRecTy::convertValue(const TypedInit *VI) { SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - NewBits[i] = new VarBitInit(VI, i); - return new BitsInit(ArrayRef(NewBits)); + NewBits[i] = VarBitInit::get(VI, i); + return BitsInit::get(ArrayRef(NewBits)); } if (Size == 1 && dynamic_cast(VI->getType())) - return new BitsInit(ArrayRef(VI)); + return BitsInit::get(ArrayRef(VI)); if (const TernOpInit *Tern = dynamic_cast(VI)) { if (Tern->getOpcode() == TernOpInit::IF) { @@ -152,12 +152,12 @@ const Init *BitsRecTy::convertValue(const TypedInit *VI) { for (unsigned i = 0; i != Size; ++i) NewBits[i] = - new TernOpInit(TernOpInit::IF, LHS, - new IntInit((MHSVal & (1LL << i)) ? 1 : 0), - new IntInit((RHSVal & (1LL << i)) ? 1 : 0), - VI->getType()); + TernOpInit::get(TernOpInit::IF, LHS, + IntInit::get((MHSVal & (1LL << i)) ? 1 : 0), + IntInit::get((RHSVal & (1LL << i)) ? 1 : 0), + VI->getType()); - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } } else { const BitsInit *MHSbs = dynamic_cast(MHS); @@ -167,12 +167,12 @@ const Init *BitsRecTy::convertValue(const TypedInit *VI) { SmallVector NewBits(Size); for (unsigned i = 0; i != Size; ++i) - NewBits[i] = new TernOpInit(TernOpInit::IF, LHS, - MHSbs->getBit(i), - RHSbs->getBit(i), - VI->getType()); + NewBits[i] = TernOpInit::get(TernOpInit::IF, LHS, + MHSbs->getBit(i), + RHSbs->getBit(i), + VI->getType()); - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } } } @@ -182,7 +182,7 @@ const Init *BitsRecTy::convertValue(const TypedInit *VI) { } const Init *IntRecTy::convertValue(const BitInit *BI) { - return new IntInit(BI->getValue()); + return IntInit::get(BI->getValue()); } const Init *IntRecTy::convertValue(const BitsInit *BI) { @@ -193,7 +193,7 @@ const Init *IntRecTy::convertValue(const BitsInit *BI) { } else { return 0; } - return new IntInit(Result); + return IntInit::get(Result); } const Init *IntRecTy::convertValue(const TypedInit *TI) { @@ -207,7 +207,7 @@ const Init *StringRecTy::convertValue(const UnOpInit *BO) { const Init *L = BO->getOperand()->convertInitializerTo(this); if (L == 0) return 0; if (L != BO->getOperand()) - return new UnOpInit(UnOpInit::CAST, L, new StringRecTy); + return UnOpInit::get(UnOpInit::CAST, L, new StringRecTy); return BO; } @@ -220,7 +220,7 @@ const Init *StringRecTy::convertValue(const BinOpInit *BO) { const Init *R = BO->getRHS()->convertInitializerTo(this); if (L == 0 || R == 0) return 0; if (L != BO->getLHS() || R != BO->getRHS()) - return new BinOpInit(BinOpInit::STRCONCAT, L, R, new StringRecTy); + return BinOpInit::get(BinOpInit::STRCONCAT, L, R, new StringRecTy); return BO; } @@ -254,7 +254,7 @@ const Init *ListRecTy::convertValue(const ListInit *LI) { return 0; } - return new ListInit(Elements, this); + return ListInit::get(Elements, this); } const Init *ListRecTy::convertValue(const TypedInit *TI) { @@ -282,7 +282,7 @@ const Init *DagRecTy::convertValue(const UnOpInit *BO) { const Init *L = BO->getOperand()->convertInitializerTo(this); if (L == 0) return 0; if (L != BO->getOperand()) - return new UnOpInit(UnOpInit::CAST, L, new DagRecTy); + return UnOpInit::get(UnOpInit::CAST, L, new DagRecTy); return BO; } return 0; @@ -294,7 +294,7 @@ const Init *DagRecTy::convertValue(const BinOpInit *BO) { const Init *R = BO->getRHS()->convertInitializerTo(this); if (L == 0 || R == 0) return 0; if (L != BO->getLHS() || R != BO->getRHS()) - return new BinOpInit(BinOpInit::CONCAT, L, R, new DagRecTy); + return BinOpInit::get(BinOpInit::CONCAT, L, R, new DagRecTy); return BO; } return 0; @@ -396,6 +396,18 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { void Init::dump() const { return print(errs()); } +const UnsetInit *UnsetInit::get() { + return new UnsetInit; +} + +const BitInit *BitInit::get(bool V) { + return new BitInit(V); +} + +const BitsInit *BitsInit::get(ArrayRef Range) { + return new BitsInit(Range); +} + const Init * BitsInit::convertInitializerBitRange(const std::vector &Bits) const { SmallVector NewBits(Bits.size()); @@ -405,7 +417,7 @@ BitsInit::convertInitializerBitRange(const std::vector &Bits) const { return 0; NewBits[i] = getBit(Bits[i]); } - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } std::string BitsInit::getAsString() const { @@ -440,11 +452,15 @@ const Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) const { } if (Changed) - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); return this; } +const IntInit *IntInit::get(int64_t V) { + return new IntInit(V); +} + std::string IntInit::getAsString() const { return itostr(Value); } @@ -457,9 +473,25 @@ IntInit::convertInitializerBitRange(const std::vector &Bits) const { if (Bits[i] >= 64) return 0; - NewBits[i] = new BitInit(Value & (INT64_C(1) << Bits[i])); + NewBits[i] = BitInit::get(Value & (INT64_C(1) << Bits[i])); } - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); +} + +const StringInit *StringInit::get(const std::string &V) { + return new StringInit(V); +} + +const CodeInit *CodeInit::get(const std::string &V) { + return new CodeInit(V); +} + +const ListInit *ListInit::get(std::vector &Vs, RecTy *EltTy) { + return new ListInit(Vs, EltTy); +} + +const ListInit *ListInit::get(ArrayRef Range, RecTy *EltTy) { + return new ListInit(Range, EltTy); } const Init * @@ -470,7 +502,7 @@ ListInit::convertInitListSlice(const std::vector &Elements) const { return 0; Vals.push_back(getElement(Elements[i])); } - return new ListInit(Vals, getType()); + return ListInit::get(Vals, getType()); } Record *ListInit::getElementAsRecord(unsigned i) const { @@ -498,7 +530,7 @@ const Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) const { } if (Changed) - return new ListInit(Resolved, getType()); + return ListInit::get(Resolved, getType()); return this; } @@ -553,6 +585,10 @@ const Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, return 0; } +const UnOpInit *UnOpInit::get(UnaryOp opc, const Init *lhs, RecTy *Type) { + return new UnOpInit(opc, lhs, Type); +} + const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { switch (getOpcode()) { default: assert(0 && "Unknown unop"); @@ -565,7 +601,7 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { const DefInit *LHSd = dynamic_cast(LHS); if (LHSd) { - return new StringInit(LHSd->getDef()->getName()); + return StringInit::get(LHSd->getDef()->getName()); } } else { const StringInit *LHSs = dynamic_cast(LHS); @@ -577,7 +613,7 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { if (const RecordVal *RV = CurRec->getValue(Name)) { if (RV->getType() != getType()) throw "type mismatch in cast"; - return new VarInit(Name, RV->getType()); + return VarInit::get(Name, RV->getType()); } std::string TemplateArgName = CurRec->getName()+":"+Name; @@ -588,7 +624,7 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { if (RV->getType() != getType()) throw "type mismatch in cast"; - return new VarInit(TemplateArgName, RV->getType()); + return VarInit::get(TemplateArgName, RV->getType()); } } @@ -601,7 +637,7 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { if (RV->getType() != getType()) throw "type mismatch in cast"; - return new VarInit(MCName, RV->getType()); + return VarInit::get(MCName, RV->getType()); } } @@ -637,9 +673,9 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { // they are not convertible to Init **. Fortunately, // RandomAccessIterator::operator * is guaranteed to return an // lvalue. - ListInit *Result = - new ListInit(ArrayRef(&*begin, end - begin), - LHSl->getType()); + const ListInit *Result = + ListInit::get(ArrayRef(&*begin, end - begin), + LHSl->getType()); return Result; } break; @@ -648,17 +684,17 @@ const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { const ListInit *LHSl = dynamic_cast(LHS); if (LHSl) { if (LHSl->getSize() == 0) { - return new IntInit(1); + return IntInit::get(1); } else { - return new IntInit(0); + return IntInit::get(0); } } const StringInit *LHSs = dynamic_cast(LHS); if (LHSs) { if (LHSs->getValue().empty()) { - return new IntInit(1); + return IntInit::get(1); } else { - return new IntInit(0); + return IntInit::get(0); } } @@ -672,7 +708,7 @@ const Init *UnOpInit::resolveReferences(Record &R, const RecordVal *RV) const { const Init *lhs = LHS->resolveReferences(R, RV); if (LHS != lhs) - return (new UnOpInit(getOpcode(), lhs, getType()))->Fold(&R, 0); + return (UnOpInit::get(getOpcode(), lhs, getType()))->Fold(&R, 0); return Fold(&R, 0); } @@ -687,6 +723,11 @@ std::string UnOpInit::getAsString() const { return Result + "(" + LHS->getAsString() + ")"; } +const BinOpInit *BinOpInit::get(BinaryOp opc, const Init *lhs, + const Init *rhs, RecTy *Type) { + return new BinOpInit(opc, lhs, rhs, Type); +} + const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { switch (getOpcode()) { default: assert(0 && "Unknown binop"); @@ -708,7 +749,7 @@ const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { Args.push_back(RHSs->getArg(i)); ArgNames.push_back(RHSs->getArgName(i)); } - return new DagInit(LHSs->getOperator(), "", Args, ArgNames); + return DagInit::get(LHSs->getOperator(), "", Args, ArgNames); } break; } @@ -716,7 +757,7 @@ const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { const StringInit *LHSs = dynamic_cast(LHS); const StringInit *RHSs = dynamic_cast(RHS); if (LHSs && RHSs) - return new StringInit(LHSs->getValue() + RHSs->getValue()); + return StringInit::get(LHSs->getValue() + RHSs->getValue()); break; } case EQ: { @@ -728,14 +769,14 @@ const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { dynamic_cast(RHS->convertInitializerTo(IntRecTy::get())); if (L && R) - return new IntInit(L->getValue() == R->getValue()); + return IntInit::get(L->getValue() == R->getValue()); const StringInit *LHSs = dynamic_cast(LHS); const StringInit *RHSs = dynamic_cast(RHS); // Make sure we've resolved if (LHSs && RHSs) - return new IntInit(LHSs->getValue() == RHSs->getValue()); + return IntInit::get(LHSs->getValue() == RHSs->getValue()); break; } @@ -753,7 +794,7 @@ const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { case SRA: Result = LHSv >> RHSv; break; case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break; } - return new IntInit(Result); + return IntInit::get(Result); } break; } @@ -766,7 +807,7 @@ const Init *BinOpInit::resolveReferences(Record &R, const RecordVal *RV) const { const Init *rhs = RHS->resolveReferences(R, RV); if (LHS != lhs || RHS != rhs) - return (new BinOpInit(getOpcode(), lhs, rhs, getType()))->Fold(&R, 0); + return (BinOpInit::get(getOpcode(), lhs, rhs, getType()))->Fold(&R, 0); return Fold(&R, 0); } @@ -783,6 +824,12 @@ std::string BinOpInit::getAsString() const { return Result + "(" + LHS->getAsString() + ", " + RHS->getAsString() + ")"; } +const TernOpInit *TernOpInit::get(TernaryOp opc, const Init *lhs, + const Init *mhs, const Init *rhs, + RecTy *Type) { + return new TernOpInit(opc, lhs, mhs, rhs, Type); +} + static const Init *ForeachHelper(const Init *LHS, const Init *MHS, const Init *RHS, RecTy *Type, Record *CurRec, MultiClass *CurMultiClass); @@ -827,10 +874,9 @@ static const Init *EvaluateOperation(const OpInit *RHSo, const Init *LHS, // Now run the operator and use its result as the new leaf const OpInit *NewOp = RHSo->clone(NewOperands); const Init *NewVal = NewOp->Fold(CurRec, CurMultiClass); - if (NewVal != NewOp) { - delete NewOp; + if (NewVal != NewOp) return NewVal; - } + return 0; } @@ -883,7 +929,7 @@ static const Init *ForeachHelper(const Init *LHS, const Init *MHS, args.push_back(std::make_pair(Arg, ArgName)); } - return new DagInit(Val, "", args); + return DagInit::get(Val, "", args); } if (MHSl) { std::vector NewOperands; @@ -907,12 +953,10 @@ static const Init *ForeachHelper(const Init *LHS, const Init *MHS, // Now run the operator and use its result as the new list item const OpInit *NewOp = RHSo->clone(NewOperands); const Init *NewItem = NewOp->Fold(CurRec, CurMultiClass); - if (NewItem != NewOp) { + if (NewItem != NewOp) *li = NewItem; - delete NewOp; - } } - return new ListInit(NewList, MHSl->getType()); + return ListInit::get(NewList, MHSl->getType()); } } return 0; @@ -949,7 +993,7 @@ const Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { if (LHSv->getAsString() == RHSv->getAsString()) { Val = MHSv->getName(); } - return new VarInit(Val, getType()); + return VarInit::get(Val, getType()); } if (RHSs) { std::string Val = RHSs->getValue(); @@ -964,7 +1008,7 @@ const Init *TernOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { idx = found + MHSs->getValue().size(); } while (found != std::string::npos); - return new StringInit(Val); + return StringInit::get(Val); } } break; @@ -1009,12 +1053,12 @@ const Init *TernOpInit::resolveReferences(Record &R, // Short-circuit if (Value->getValue()) { const Init *mhs = MHS->resolveReferences(R, RV); - return (new TernOpInit(getOpcode(), lhs, mhs, - RHS, getType()))->Fold(&R, 0); + return (TernOpInit::get(getOpcode(), lhs, mhs, + RHS, getType()))->Fold(&R, 0); } else { const Init *rhs = RHS->resolveReferences(R, RV); - return (new TernOpInit(getOpcode(), lhs, MHS, - rhs, getType()))->Fold(&R, 0); + return (TernOpInit::get(getOpcode(), lhs, MHS, + rhs, getType()))->Fold(&R, 0); } } } @@ -1023,7 +1067,8 @@ const Init *TernOpInit::resolveReferences(Record &R, const Init *rhs = RHS->resolveReferences(R, RV); if (LHS != lhs || MHS != mhs || RHS != rhs) - return (new TernOpInit(getOpcode(), lhs, mhs, rhs, getType()))->Fold(&R, 0); + return (TernOpInit::get(getOpcode(), lhs, mhs, rhs, + getType()))->Fold(&R, 0); return Fold(&R, 0); } @@ -1060,9 +1105,9 @@ TypedInit::convertInitializerBitRange(const std::vector &Bits) const { if (Bits[i] >= NumBits) return 0; - NewBits[i] = new VarBitInit(this, Bits[i]); + NewBits[i] = VarBitInit::get(this, Bits[i]); } - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } const Init * @@ -1071,16 +1116,20 @@ TypedInit::convertInitListSlice(const std::vector &Elements) const { if (T == 0) return 0; // Cannot subscript a non-list variable. if (Elements.size() == 1) - return new VarListElementInit(this, Elements[0]); + return VarListElementInit::get(this, Elements[0]); std::vector ListInits; ListInits.reserve(Elements.size()); for (unsigned i = 0, e = Elements.size(); i != e; ++i) - ListInits.push_back(new VarListElementInit(this, Elements[i])); - return new ListInit(ListInits, T); + ListInits.push_back(VarListElementInit::get(this, Elements[i])); + return ListInit::get(ListInits, T); } +const VarInit *VarInit::get(const std::string &VN, RecTy *T) { + return new VarInit(VN, T); +} + const Init *VarInit::resolveBitReference(Record &R, const RecordVal *IRV, unsigned Bit) const { if (R.isTemplateArg(getName())) return 0; @@ -1114,7 +1163,7 @@ const Init *VarInit::resolveListElementReference(Record &R, if (!LI) { const VarInit *VI = dynamic_cast(RV->getValue()); assert(VI && "Invalid list element!"); - return new VarListElementInit(VI, Elt); + return VarListElementInit::get(VI, Elt); } if (Elt >= LI->getSize()) @@ -1164,6 +1213,10 @@ const Init *VarInit::resolveReferences(Record &R, const RecordVal *RV) const { return this; } +const VarBitInit *VarBitInit::get(const TypedInit *T, unsigned B) { + return new VarBitInit(T, B); +} + std::string VarBitInit::getAsString() const { return TI->getAsString() + "{" + utostr(Bit) + "}"; } @@ -1175,6 +1228,11 @@ const Init *VarBitInit::resolveReferences(Record &R, return this; } +const VarListElementInit *VarListElementInit::get(const TypedInit *T, + unsigned E) { + return new VarListElementInit(T, E); +} + std::string VarListElementInit::getAsString() const { return TI->getAsString() + "[" + utostr(Element) + "]"; } @@ -1203,7 +1261,7 @@ resolveListElementReference(Record &R, const RecordVal *RV, return 0; } -DefInit *DefInit::get(Record *R) { +const DefInit *DefInit::get(Record *R) { return R->getDefInit(); } @@ -1223,6 +1281,10 @@ std::string DefInit::getAsString() const { return Def->getName(); } +const FieldInit *FieldInit::get(const Init *R, const std::string &FN) { + return new FieldInit(R, FN); +} + const Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV, unsigned Bit) const { if (const Init *BitsVal = Rec->getFieldInit(R, RV, FieldName)) @@ -1263,11 +1325,24 @@ const Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) const { } if (NewRec != Rec) { - return new FieldInit(NewRec, FieldName); + return FieldInit::get(NewRec, FieldName); } return this; } +const DagInit * +DagInit::get(const Init *V, const std::string &VN, + const std::vector > &args) { + return new DagInit(V, VN, args); +} + +const DagInit * +DagInit::get(const Init *V, const std::string &VN, + const std::vector &args, + const std::vector &argNames) { + return new DagInit(V, VN, args, argNames); +} + const Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) const { std::vector NewArgs; for (unsigned i = 0, e = Args.size(); i != e; ++i) @@ -1276,7 +1351,7 @@ const Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) const { const Init *Op = Val->resolveReferences(R, RV); if (Args != NewArgs || Op != Val) - return new DagInit(Op, ValName, NewArgs, ArgNames); + return DagInit::get(Op, ValName, NewArgs, ArgNames); return this; } @@ -1304,7 +1379,7 @@ std::string DagInit::getAsString() const { RecordVal::RecordVal(const std::string &N, RecTy *T, unsigned P) : Name(N), Ty(T), Prefix(P) { - Value = Ty->convertValue(new UnsetInit()); + Value = Ty->convertValue(UnsetInit::get()); assert(Value && "Cannot create unset value for current type!"); } diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index 0ba4aec..4b4a2c6 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -16,6 +16,7 @@ #define RECORD_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/Support/Allocator.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/raw_ostream.h" @@ -485,6 +486,12 @@ RecTy *resolveTypes(RecTy *T1, RecTy *T2); //===----------------------------------------------------------------------===// class Init { + Init(const Init &); // Do not define. + Init &operator=(const Init &); // Do not define. + +protected: + Init(void) {} + public: virtual ~Init() {} @@ -562,9 +569,14 @@ inline raw_ostream &operator<<(raw_ostream &OS, const Init &I) { /// class TypedInit : public Init { RecTy *Ty; -public: + + TypedInit(const TypedInit &Other); // Do not define. + TypedInit &operator=(const TypedInit &Other); // Do not define. + +protected: explicit TypedInit(RecTy *T) : Ty(T) {} +public: RecTy *getType() const { return Ty; } virtual const Init * @@ -596,7 +608,13 @@ public: /// UnsetInit - ? - Represents an uninitialized value /// class UnsetInit : public Init { + UnsetInit() : Init() {} + UnsetInit(const UnsetInit &); // Do not define. + UnsetInit &operator=(const UnsetInit &Other); // Do not define. + public: + static const UnsetInit *get(); + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -610,8 +628,13 @@ public: /// class BitInit : public Init { bool Value; -public: + explicit BitInit(bool V) : Value(V) {} + BitInit(const BitInit &Other); // Do not define. + BitInit &operator=(BitInit &Other); // Do not define. + +public: + static const BitInit *get(bool V); bool getValue() const { return Value; } @@ -627,10 +650,17 @@ public: /// class BitsInit : public Init { std::vector Bits; -public: - explicit BitsInit(unsigned Size) : Bits(Size) {} + + BitsInit(unsigned Size) : Bits(Size) {} + BitsInit(ArrayRef Range) : Bits(Range.begin(), Range.end()) {} + BitsInit(const BitsInit &Other); // Do not define. + BitsInit &operator=(const BitsInit &Other); // Do not define. + +public: + static const BitsInit *get(ArrayRef Range); + unsigned getNumBits() const { return Bits.size(); } const Init *getBit(unsigned Bit) const { @@ -664,9 +694,15 @@ public: /// class IntInit : public TypedInit { int64_t Value; -public: + explicit IntInit(int64_t V) : TypedInit(IntRecTy::get()), Value(V) {} + IntInit(const IntInit &Other); // Do not define. + IntInit &operator=(const IntInit &Other); // Do note define. + +public: + static const IntInit *get(int64_t V); + int64_t getValue() const { return Value; } virtual const Init *convertInitializerTo(RecTy *Ty) const { @@ -702,10 +738,16 @@ public: /// class StringInit : public TypedInit { std::string Value; -public: + explicit StringInit(const std::string &V) : TypedInit(StringRecTy::get()), Value(V) {} + StringInit(const StringInit &Other); // Do not define. + StringInit &operator=(const StringInit &Other); // Do not define. + +public: + static const StringInit *get(const std::string &V); + const std::string &getValue() const { return Value; } virtual const Init *convertInitializerTo(RecTy *Ty) const { @@ -738,9 +780,15 @@ public: /// class CodeInit : public Init { std::string Value; -public: + explicit CodeInit(const std::string &V) : Value(V) {} + CodeInit(const CodeInit &Other); // Do not define. + CodeInit &operator=(const CodeInit &Other); // Do not define. + +public: + static const CodeInit *get(const std::string &V); + const std::string &getValue() const { return Value; } virtual const Init *convertInitializerTo(RecTy *Ty) const { @@ -764,6 +812,13 @@ public: explicit ListInit(ArrayRef Range, RecTy *EltTy) : TypedInit(ListRecTy::get(EltTy)), Values(Range.begin(), Range.end()) {} + ListInit(const ListInit &Other); // Do not define. + ListInit &operator=(const ListInit &Other); // Do not define. + +public: + static const ListInit *get(std::vector &Vs, RecTy *EltTy); + static const ListInit *get(ArrayRef Range, RecTy *EltTy); + unsigned getSize() const { return Values.size(); } const Init *getElement(unsigned i) const { assert(i < Values.size() && "List element index out of range!"); @@ -814,9 +869,13 @@ public: /// OpInit - Base class for operators /// class OpInit : public TypedInit { -public: - OpInit(RecTy *Type) : TypedInit(Type) {} + OpInit(const OpInit &Other); // Do not define. + OpInit &operator=(OpInit &Other); // Do not define. +protected: + explicit OpInit(RecTy *Type) : TypedInit(Type) {} + +public: // Clone - Clone this operator, replacing arguments with the new list virtual const OpInit *clone(std::vector &Operands) const = 0; @@ -847,16 +906,21 @@ public: private: UnaryOp Opc; const Init *LHS; + + UnOpInit(UnaryOp opc, const Init *lhs, RecTy *Type) + : OpInit(Type), Opc(opc), LHS(lhs) {} + + UnOpInit(const UnOpInit &Other); // Do not define. + UnOpInit &operator=(const UnOpInit &Other); // Do not define. + public: - UnOpInit(UnaryOp opc, const Init *lhs, RecTy *Type) : - OpInit(Type), Opc(opc), LHS(lhs) { - } + static const UnOpInit *get(UnaryOp opc, const Init *lhs, RecTy *Type); // Clone - Clone this operator, replacing arguments with the new list virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 1 && "Wrong number of operands for unary operation"); - return new UnOpInit(getOpcode(), *Operands.begin(), getType()); + return UnOpInit::get(getOpcode(), *Operands.begin(), getType()); } int getNumOperands() const { return 1; } @@ -885,16 +949,22 @@ public: private: BinaryOp Opc; const Init *LHS, *RHS; -public: + BinOpInit(BinaryOp opc, const Init *lhs, const Init *rhs, RecTy *Type) : - OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) { - } + OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) {} + + BinOpInit(const BinOpInit &Other); // Do not define. + BinOpInit &operator=(const BinOpInit &Other); // Do not define. + +public: + static const BinOpInit *get(BinaryOp opc, const Init *lhs, const Init *rhs, + RecTy *Type); // Clone - Clone this operator, replacing arguments with the new list virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 2 && "Wrong number of operands for binary operation"); - return new BinOpInit(getOpcode(), Operands[0], Operands[1], getType()); + return BinOpInit::get(getOpcode(), Operands[0], Operands[1], getType()); } int getNumOperands() const { return 2; } @@ -928,18 +998,25 @@ public: private: TernaryOp Opc; const Init *LHS, *MHS, *RHS; -public: + TernOpInit(TernaryOp opc, const Init *lhs, const Init *mhs, const Init *rhs, RecTy *Type) : - OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) { - } + OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) {} + + TernOpInit(const TernOpInit &Other); // Do not define. + TernOpInit &operator=(const TernOpInit &Other); // Do not define. + +public: + static const TernOpInit *get(TernaryOp opc, const Init *lhs, + const Init *mhs, const Init *rhs, + RecTy *Type); // Clone - Clone this operator, replacing arguments with the new list virtual const OpInit *clone(std::vector &Operands) const { assert(Operands.size() == 3 && "Wrong number of operands for ternary operation"); - return new TernOpInit(getOpcode(), Operands[0], Operands[1], Operands[2], - getType()); + return TernOpInit::get(getOpcode(), Operands[0], Operands[1], Operands[2], + getType()); } int getNumOperands() const { return 3; } @@ -976,9 +1053,16 @@ public: /// class VarInit : public TypedInit { std::string VarName; -public: + explicit VarInit(const std::string &VN, RecTy *T) - : TypedInit(T), VarName(VN) {} + : TypedInit(T), VarName(VN) {} + + VarInit(const VarInit &Other); // Do not define. + VarInit &operator=(const VarInit &Other); // Do not define. + +public: + static const VarInit *get(const std::string &VN, RecTy *T); + static const VarInit *get(const Init *VN, RecTy *T); virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); @@ -1011,13 +1095,19 @@ public: class VarBitInit : public Init { const TypedInit *TI; unsigned Bit; -public: + VarBitInit(const TypedInit *T, unsigned B) : TI(T), Bit(B) { assert(T->getType() && dynamic_cast(T->getType()) && ((BitsRecTy*)T->getType())->getNumBits() > B && "Illegal VarBitInit expression!"); } + VarBitInit(const VarBitInit &Other); // Do not define. + VarBitInit &operator=(const VarBitInit &Other); // Do not define. + +public: + static const VarBitInit *get(const TypedInit *T, unsigned B); + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -1034,14 +1124,22 @@ public: class VarListElementInit : public TypedInit { const TypedInit *TI; unsigned Element; -public: + VarListElementInit(const TypedInit *T, unsigned E) - : TypedInit(dynamic_cast(T->getType())->getElementType()), - TI(T), Element(E) { + : TypedInit(dynamic_cast(T->getType())->getElementType()), + TI(T), Element(E) { assert(T->getType() && dynamic_cast(T->getType()) && "Illegal VarBitInit expression!"); } + VarListElementInit(const VarListElementInit &Other); // Do not define. + VarListElementInit &operator=(const VarListElementInit &Other); // Do + // not + // define. + +public: + static const VarListElementInit *get(const TypedInit *T, unsigned E); + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -1067,10 +1165,15 @@ public: /// class DefInit : public TypedInit { Record *Def; + DefInit(Record *D, RecordRecTy *T) : TypedInit(T), Def(D) {} friend class Record; + + DefInit(const DefInit &Other); // Do not define. + DefInit &operator=(const DefInit &Other); // Do not define. + public: - static DefInit *get(Record*); + static const DefInit *get(Record*); virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); @@ -1113,12 +1216,19 @@ public: class FieldInit : public TypedInit { const Init *Rec; // Record we are referring to std::string FieldName; // Field we are accessing -public: + FieldInit(const Init *R, const std::string &FN) - : TypedInit(R->getFieldType(FN)), Rec(R), FieldName(FN) { + : TypedInit(R->getFieldType(FN)), Rec(R), FieldName(FN) { assert(getType() && "FieldInit with non-record type!"); } + FieldInit(const FieldInit &Other); // Do not define. + FieldInit &operator=(const FieldInit &Other); // Do not define. + +public: + static const FieldInit *get(const Init *R, const std::string &FN); + static const FieldInit *get(const Init *R, const Init *FN); + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } @@ -1145,8 +1255,8 @@ class DagInit : public TypedInit { std::string ValName; std::vector Args; std::vector ArgNames; -public: - DagInit(const Init *V, std::string VN, + + DagInit(const Init *V, const std::string &VN, const std::vector > &args) : TypedInit(DagRecTy::get()), Val(V), ValName(VN) { Args.reserve(args.size()); @@ -1156,11 +1266,23 @@ public: ArgNames.push_back(args[i].second); } } - DagInit(const Init *V, std::string VN, const std::vector &args, + DagInit(const Init *V, const std::string &VN, + const std::vector &args, const std::vector &argNames) : TypedInit(DagRecTy::get()), Val(V), ValName(VN), Args(args), ArgNames(argNames) { } + DagInit(const DagInit &Other); // Do not define. + DagInit &operator=(const DagInit &Other); // Do not define. + +public: + static const DagInit *get(const Init *V, const std::string &VN, + const std::vector< + std::pair > &args); + static const DagInit *get(const Init *V, const std::string &VN, + const std::vector &args, + const std::vector &argNames); + virtual const Init *convertInitializerTo(RecTy *Ty) const { return Ty->convertValue(this); } diff --git oldutils/TableGen/TGParser.cpp newutils/TableGen/TGParser.cpp index 1565959..664a688 100644 --- oldutils/TableGen/TGParser.cpp +++ newutils/TableGen/TGParser.cpp @@ -131,7 +131,7 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, if (NewBits[i] == 0) NewBits[i] = CurVal->getBit(i); - V = new BitsInit(ArrayRef(NewBits)); + V = BitsInit::get(ArrayRef(NewBits)); } if (RV->setValue(V)) @@ -647,13 +647,13 @@ const Init *TGParser::ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc) { if (CurRec) { if (const RecordVal *RV = CurRec->getValue(Name)) - return new VarInit(Name, RV->getType()); + return VarInit::get(Name, RV->getType()); std::string TemplateArgName = CurRec->getName()+":"+Name; if (CurRec->isTemplateArg(TemplateArgName)) { const RecordVal *RV = CurRec->getValue(TemplateArgName); assert(RV && "Template arg doesn't exist??"); - return new VarInit(TemplateArgName, RV->getType()); + return VarInit::get(TemplateArgName, RV->getType()); } } @@ -662,7 +662,7 @@ const Init *TGParser::ParseIDValue(Record *CurRec, if (CurMultiClass->Rec.isTemplateArg(MCName)) { const RecordVal *RV = CurMultiClass->Rec.getValue(MCName); assert(RV && "Template arg doesn't exist??"); - return new VarInit(MCName, RV->getType()); + return VarInit::get(MCName, RV->getType()); } } @@ -790,7 +790,7 @@ const Init *TGParser::ParseOperation(Record *CurRec) { return 0; } Lex.Lex(); // eat the ')' - return (new UnOpInit(Code, LHS, Type))->Fold(CurRec, CurMultiClass); + return (UnOpInit::get(Code, LHS, Type))->Fold(CurRec, CurMultiClass); } case tgtok::XConcat: @@ -848,14 +848,14 @@ const Init *TGParser::ParseOperation(Record *CurRec) { if (Code == BinOpInit::STRCONCAT) { while (InitList.size() > 2) { const Init *RHS = InitList.pop_back_val(); - RHS = (new BinOpInit(Code, InitList.back(), RHS, Type)) - ->Fold(CurRec, CurMultiClass); + RHS = (BinOpInit::get(Code, InitList.back(), RHS, Type)) + ->Fold(CurRec, CurMultiClass); InitList.back() = RHS; } } if (InitList.size() == 2) - return (new BinOpInit(Code, InitList[0], InitList[1], Type)) + return (BinOpInit::get(Code, InitList[0], InitList[1], Type)) ->Fold(CurRec, CurMultiClass); Error(OpLoc, "expected two operands to operator"); @@ -982,7 +982,7 @@ const Init *TGParser::ParseOperation(Record *CurRec) { break; } } - return (new TernOpInit(Code, LHS, MHS, RHS, Type))->Fold(CurRec, + return (TernOpInit::get(Code, LHS, MHS, RHS, Type))->Fold(CurRec, CurMultiClass); } } @@ -1042,7 +1042,7 @@ const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { const Init *R = 0; switch (Lex.getCode()) { default: TokError("Unknown token when parsing a value"); break; - case tgtok::IntVal: R = new IntInit(Lex.getCurIntVal()); Lex.Lex(); break; + case tgtok::IntVal: R = IntInit::get(Lex.getCurIntVal()); Lex.Lex(); break; case tgtok::StrVal: { std::string Val = Lex.getCurStrVal(); Lex.Lex(); @@ -1053,15 +1053,15 @@ const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { Lex.Lex(); } - R = new StringInit(Val); + R = StringInit::get(Val); break; } case tgtok::CodeFragment: - R = new CodeInit(Lex.getCurStrVal()); + R = CodeInit::get(Lex.getCurStrVal()); Lex.Lex(); break; case tgtok::question: - R = new UnsetInit(); + R = UnsetInit::get(); Lex.Lex(); break; case tgtok::Id: { @@ -1138,7 +1138,7 @@ const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { } NewBits[Vals.size()-i-1] = Bit; } - return new BitsInit(ArrayRef(NewBits)); + return BitsInit::get(ArrayRef(NewBits)); } case tgtok::l_square: { // Value ::= '[' ValueList ']' Lex.Lex(); // eat the '[' @@ -1237,7 +1237,7 @@ const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { DeducedEltTy = EltTy; } - return new ListInit(Vals, DeducedEltTy); + return ListInit::get(Vals, DeducedEltTy); } case tgtok::l_paren: { // Value ::= '(' IDValue DagArgList ')' Lex.Lex(); // eat the '(' @@ -1272,7 +1272,7 @@ const Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { } Lex.Lex(); // eat the ')' - return new DagInit(Operator, OperatorName, DagArgs); + return DagInit::get(Operator, OperatorName, DagArgs); } case tgtok::XHead: @@ -1362,7 +1362,7 @@ const Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType) { Result->getAsString() + "'"); return 0; } - Result = new FieldInit(Result, Lex.getCurStrVal()); + Result = FieldInit::get(Result, Lex.getCurStrVal()); Lex.Lex(); // eat field name break; } -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:41 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:41 -0500 Subject: [llvm-commits] [PATCH 06/20] [AVX] Unique UnsetInit In-Reply-To: References: Message-ID: <7a8502122946b84eaa48a2c866d5ee9200c3f504.1311100070.git.dag@cray.com> Keep only one UnsetInit around. --- utils/TableGen/Record.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 3339a22..72b1f5f 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -397,7 +397,11 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { void Init::dump() const { return print(errs()); } const UnsetInit *UnsetInit::get() { - return new UnsetInit; + static const UnsetInit *TheInit = 0; + if (TheInit == 0) + TheInit = new UnsetInit(); + + return TheInit; } const BitInit *BitInit::get(bool V) { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:42 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:42 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: References: Message-ID: Keep only two copies of BitInit: one for true and one for false. --- utils/TableGen/Record.cpp | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 72b1f5f..68ac572 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -405,7 +405,15 @@ const UnsetInit *UnsetInit::get() { } const BitInit *BitInit::get(bool V) { - return new BitInit(V); + static const BitInit *True = 0; + static const BitInit *False = 0; + + const BitInit **Result = (V ? &True : &False); + + if (*Result == 0) + *Result = new BitInit(V); + + return *Result; } const BitsInit *BitsInit::get(ArrayRef Range) { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:44 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:44 -0500 Subject: [llvm-commits] [PATCH 09/20] [AVX] Make IntInit Unique In-Reply-To: References: Message-ID: Use a DenseMap to make sure only one IntInit of any value exists. --- utils/TableGen/Record.cpp | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 4c019d3..dda0b71 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -491,7 +491,19 @@ const Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) const { } const IntInit *IntInit::get(int64_t V) { - return new IntInit(V); + typedef DenseMap Pool; + static Pool ThePool; + + Pool::iterator Result = ThePool.find(V); + + if (Result == ThePool.end()) { + IntInit *New = new IntInit(V); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(V, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } std::string IntInit::getAsString() const { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:43 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:43 -0500 Subject: [llvm-commits] [PATCH 08/20] [AVX] Make BitsInit Unique In-Reply-To: References: Message-ID: Make BitsInit a FastFoldingSetNode so we can unique it. --- utils/TableGen/Record.cpp | 23 ++++++++++++++++++++++- utils/TableGen/Record.h | 8 ++++---- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 68ac572..4c019d3 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -15,6 +15,8 @@ #include "Error.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/Format.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" @@ -417,7 +419,26 @@ const BitInit *BitInit::get(bool V) { } const BitsInit *BitsInit::get(ArrayRef Range) { - return new BitsInit(Range); + typedef FoldingSet Pool; + static Pool ThePool; + + FoldingSetNodeID ID; + ID.AddInteger(Range.size()); + + for (ArrayRef::iterator i = Range.begin(), + iend = Range.end(); + i != iend; + ++i) + ID.AddPointer(*i); + + void *IP = 0; + if (const BitsInit *I = ThePool.FindNodeOrInsertPos(ID, IP)) + return I; + + BitsInit *I = new BitsInit(ID, Range); + ThePool.InsertNode(I, IP); + + return I; } const Init * diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index 4b4a2c6..468d31f 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -16,6 +16,7 @@ #define RECORD_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/FoldingSet.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/DataTypes.h" @@ -648,12 +649,11 @@ public: /// BitsInit - { a, b, c } - Represents an initializer for a BitsRecTy value. /// It contains a vector of bits, whose size is determined by the type. /// -class BitsInit : public Init { +class BitsInit : public Init, public FastFoldingSetNode { std::vector Bits; - BitsInit(unsigned Size) : Bits(Size) {} - - BitsInit(ArrayRef Range) : Bits(Range.begin(), Range.end()) {} + BitsInit(FoldingSetNodeID &ID, ArrayRef Range) + : FastFoldingSetNode(ID), Bits(Range.begin(), Range.end()) {} BitsInit(const BitsInit &Other); // Do not define. BitsInit &operator=(const BitsInit &Other); // Do not define. -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:45 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:45 -0500 Subject: [llvm-commits] [PATCH 10/20] [AVX] Make StringInit Unique In-Reply-To: References: Message-ID: <57a4bfee280f8231651d7aca9efb0d94a01a8f85.1311100070.git.dag@cray.com> Use a StringMap to ensure the StringInits are unique. This is especially important for AVX where we will have many smallish strings representing instruction prefixes, suffixes and the like. --- utils/TableGen/Record.cpp | 25 ++++++++++++++++++++++++- 1 files changed, 24 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index dda0b71..d1401c7 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -20,6 +20,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringMap.h" using namespace llvm; @@ -524,7 +525,29 @@ IntInit::convertInitializerBitRange(const std::vector &Bits) const { } const StringInit *StringInit::get(const std::string &V) { - return new StringInit(V); + typedef StringMap Pool; + static Pool ThePool; + + typedef StringMapEntry MapEntryTy; + + Pool::iterator i = ThePool.find(V); + + StringInit *Result = 0; + + if (i == ThePool.end()) { + Result = new StringInit(V); + + MapEntryTy *NewItem = MapEntryTy::Create(V.data(), V.data() + V.size(), + ThePool.getAllocator(), Result); + + bool Inserted = false; + Inserted = ThePool.insert(NewItem); + assert(Inserted && "Did not insert new Init into pool!"); + } + else + Result = i->second; + + return Result; } const CodeInit *CodeInit::get(const std::string &V) { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:46 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:46 -0500 Subject: [llvm-commits] [PATCH 11/20] [AVX] Make CodeInit Unique In-Reply-To: References: Message-ID: <63a8bf9c31dee8e811f78fef72e3014a10d84afd.1311100070.git.dag@cray.com> Use a StringMap to ensure CodeInits are unique and created only once. --- utils/TableGen/Record.cpp | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index d1401c7..726c86d 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -551,7 +551,29 @@ const StringInit *StringInit::get(const std::string &V) { } const CodeInit *CodeInit::get(const std::string &V) { - return new CodeInit(V); + typedef StringMap Pool; + static Pool ThePool; + + typedef StringMapEntry MapEntryTy; + + Pool::iterator i = ThePool.find(V); + + CodeInit *Result = 0; + + if (i == ThePool.end()) { + Result = new CodeInit(V); + + MapEntryTy *NewItem = MapEntryTy::Create(V.data(), V.data() + V.size(), + ThePool.getAllocator(), Result); + + bool Inserted = false; + Inserted = ThePool.insert(NewItem); + assert(Inserted && "Did not insert new Init into pool!"); + } + else + Result = i->second; + + return Result; } const ListInit *ListInit::get(std::vector &Vs, RecTy *EltTy) { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:47 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:47 -0500 Subject: [llvm-commits] [PATCH 12/20] [AVX] Make ListInits Unique In-Reply-To: References: Message-ID: Make ListInit a FastFoldingSetNode to ensure ListInits are unique and only created once. This will be important for AVX as lists will be used extensively to pass generic patterns, prefix information and other things to lower-level pattern-generation classes. --- utils/TableGen/Record.cpp | 25 +++++++++++++++++++++++-- utils/TableGen/Record.h | 14 +++++++------- 2 files changed, 30 insertions(+), 9 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 726c86d..5d1ec3a 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -577,11 +577,32 @@ const CodeInit *CodeInit::get(const std::string &V) { } const ListInit *ListInit::get(std::vector &Vs, RecTy *EltTy) { - return new ListInit(Vs, EltTy); + return ListInit::get(ArrayRef(Vs), EltTy); } const ListInit *ListInit::get(ArrayRef Range, RecTy *EltTy) { - return new ListInit(Range, EltTy); + typedef FoldingSet Pool; + static Pool ThePool; + + // Just use the FoldingSetNodeID to compute a hash. Use a DenseMap + // for actual storage. + FoldingSetNodeID ID; + ID.AddInteger(Range.size()); + ID.AddPointer(EltTy); + + for (ArrayRef::iterator i = Range.begin(), + iend = Range.end(); + i != iend; + ++i) + ID.AddPointer(*i); + + void *IP = 0; + if (const ListInit *I = ThePool.FindNodeOrInsertPos(ID, IP)) + return I; + + ListInit *I = new ListInit(ID, Range, EltTy); + ThePool.InsertNode(I, IP); + return I; } const Init * diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index 468d31f..ed8f678 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -1,3 +1,4 @@ + //===- Record.h - Classes to represent Table Records ------------*- C++ -*-===// // // The LLVM Compiler Infrastructure @@ -800,17 +801,16 @@ public: /// ListInit - [AL, AH, CL] - Represent a list of defs /// -class ListInit : public TypedInit { +class ListInit : public TypedInit, public FastFoldingSetNode { std::vector Values; public: typedef std::vector::const_iterator const_iterator; - explicit ListInit(std::vector &Vs, RecTy *EltTy) - : TypedInit(ListRecTy::get(EltTy)) { - Values.swap(Vs); - } - explicit ListInit(ArrayRef Range, RecTy *EltTy) - : TypedInit(ListRecTy::get(EltTy)), Values(Range.begin(), Range.end()) {} +private: + explicit ListInit(FoldingSetNodeID &ID, ArrayRef Range, + RecTy *EltTy) + : TypedInit(ListRecTy::get(EltTy)), FastFoldingSetNode(ID), + Values(Range.begin(), Range.end()) {} ListInit(const ListInit &Other); // Do not define. ListInit &operator=(const ListInit &Other); // Do not define. -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:48 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:48 -0500 Subject: [llvm-commits] [PATCH 13/20] [AVX] Make UnOpInit Unique In-Reply-To: References: Message-ID: <4754d9fc7e055f43b9eac1dac9edf1d2f3dd3616.1311100070.git.dag@cray.com> Make sure UnOpInits are unique and created only once. This will be important for AVX/SIMD as many operators will be used to generate patterns and other relevant data. --- utils/TableGen/Record.cpp | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 5d1ec3a..7adee3b 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -697,7 +697,22 @@ const Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, } const UnOpInit *UnOpInit::get(UnaryOp opc, const Init *lhs, RecTy *Type) { - return new UnOpInit(opc, lhs, Type); + typedef std::pair, RecTy *> Key; + + typedef DenseMap Pool; + static Pool ThePool; + + Key TheKey(std::make_pair(std::make_pair(opc, lhs), Type)); + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + UnOpInit *New = new UnOpInit(opc, lhs, Type); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } const Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:49 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:49 -0500 Subject: [llvm-commits] [PATCH 14/20] [AVX] Make BinOpInit Unique In-Reply-To: References: Message-ID: <0adf19305f988808d626ec0fd0ef36885231d38d.1311100070.git.dag@cray.com> Make sure BinOpInits are unique and created only once. This will be important for AVX/SIMD as many operators will be used to generate patterns and other relevant data. --- utils/TableGen/Record.cpp | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 7adee3b..d2ae02a 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -851,7 +851,27 @@ std::string UnOpInit::getAsString() const { const BinOpInit *BinOpInit::get(BinaryOp opc, const Init *lhs, const Init *rhs, RecTy *Type) { - return new BinOpInit(opc, lhs, rhs, Type); + typedef std::pair< + std::pair, const Init *>, + RecTy * + > Key; + + typedef DenseMap Pool; + static Pool ThePool; + + Key TheKey(std::make_pair(std::make_pair(std::make_pair(opc, lhs), rhs), + Type)); + + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + BinOpInit *New = new BinOpInit(opc, lhs, rhs, Type); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } const Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:50 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:50 -0500 Subject: [llvm-commits] [PATCH 15/20] [AVX] Make TernOpInit Unique In-Reply-To: References: Message-ID: Make sure TernOpInits are unique and created only once. This will be important for AVX/SIMD as many operators will be used to generate patterns and other relevant data. --- utils/TableGen/Record.cpp | 28 +++++++++++++++++++++++++++- 1 files changed, 27 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index d2ae02a..64ddced 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -973,7 +973,33 @@ std::string BinOpInit::getAsString() const { const TernOpInit *TernOpInit::get(TernaryOp opc, const Init *lhs, const Init *mhs, const Init *rhs, RecTy *Type) { - return new TernOpInit(opc, lhs, mhs, rhs, Type); + typedef std::pair< + std::pair< + std::pair, const Init *>, + const Init * + >, + const Init * + > Key; + + typedef DenseMap Pool; + static Pool ThePool; + + Key TheKey(std::make_pair(std::make_pair(std::make_pair(std::make_pair(opc, + Type), + lhs), + mhs), + rhs)); + + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + TernOpInit *New = new TernOpInit(opc, lhs, mhs, rhs, Type); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } static const Init *ForeachHelper(const Init *LHS, const Init *MHS, -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:51 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:51 -0500 Subject: [llvm-commits] [PATCH 16/20] [AVX] Make VarInit Unique In-Reply-To: References: Message-ID: <9f97409eda498199b415a2cb927684a76eb562bf.1311100070.git.dag@cray.com> Make sure VarInits are unique and created only once. --- utils/TableGen/Record.cpp | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 64ddced..6b37898 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -1299,7 +1299,21 @@ TypedInit::convertInitListSlice(const std::vector &Elements) const { const VarInit *VarInit::get(const std::string &VN, RecTy *T) { - return new VarInit(VN, T); + typedef std::pair Key; + typedef DenseMap Pool; + static Pool ThePool; + + Key TheKey(std::make_pair(T, VN)); + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + VarInit *New = new VarInit(VN, T); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } const Init *VarInit::resolveBitReference(Record &R, const RecordVal *IRV, -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:52 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:52 -0500 Subject: [llvm-commits] [PATCH 17/20] [AVX] Make VarBitInit Unique In-Reply-To: References: Message-ID: <1bf743f55ba81f87020564b97f049bf6b5bb1865.1311100070.git.dag@cray.com> Make sure VarBitInits are unique and created only once. --- utils/TableGen/Record.cpp | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 6b37898..6b51ac1 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -1400,7 +1400,23 @@ const Init *VarInit::resolveReferences(Record &R, const RecordVal *RV) const { } const VarBitInit *VarBitInit::get(const TypedInit *T, unsigned B) { - return new VarBitInit(T, B); + typedef std::pair Key; + typedef DenseMap Pool; + + static Pool ThePool; + + Key TheKey(std::make_pair(T, B)); + + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + VarBitInit *New = new VarBitInit(T, B); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } std::string VarBitInit::getAsString() const { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:53 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:53 -0500 Subject: [llvm-commits] [PATCH 18/20] [AVX] Make VarListElementInit Unique In-Reply-To: References: Message-ID: Make sure VarListElementInits are unique and created only once. --- utils/TableGen/Record.cpp | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index 6b51ac1..ef1601e 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -1432,7 +1432,22 @@ const Init *VarBitInit::resolveReferences(Record &R, const VarListElementInit *VarListElementInit::get(const TypedInit *T, unsigned E) { - return new VarListElementInit(T, E); + typedef std::pair Key; + typedef DenseMap Pool; + + static Pool ThePool; + + Key TheKey(std::make_pair(T, E)); + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + VarListElementInit *New = new VarListElementInit(T, E); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } std::string VarListElementInit::getAsString() const { -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:54 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:54 -0500 Subject: [llvm-commits] [PATCH 19/20] [AVX] Make FieldInit Unique In-Reply-To: References: Message-ID: <8ff659579962e4cdbee9901ebb63e6e804496665.1311100070.git.dag@cray.com> Make sure FieldInits are unique and created only once. --- utils/TableGen/Record.cpp | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index ef1601e..cf82255 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -1499,7 +1499,21 @@ std::string DefInit::getAsString() const { } const FieldInit *FieldInit::get(const Init *R, const std::string &FN) { - return new FieldInit(R, FN); + typedef std::pair Key; + typedef DenseMap Pool; + static Pool ThePool; + + Key TheKey(std::make_pair(R, FN)); + Pool::iterator Result = ThePool.find(TheKey); + + if (Result == ThePool.end()) { + FieldInit *New = new FieldInit(R, FN); + bool Inserted = false; + tie(Result, Inserted) = ThePool.insert(std::make_pair(TheKey, New)); + assert(Inserted && "Did not insert new Init into pool!"); + } + + return Result->second; } const Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV, -- 1.7.6 From dag at cray.com Tue Jul 19 15:11:55 2011 From: dag at cray.com (David Greene) Date: Tue, 19 Jul 2011 15:11:55 -0500 Subject: [llvm-commits] [PATCH 20/20] [AVX] Make DagInits Unique In-Reply-To: References: Message-ID: <200595c333d1f56a4cf28f9455ab39f4b5a63cb7.1311100070.git.dag@cray.com> Make sure DagInits are unique and created only once. Make DagInit a FastFoldingSetNode to accomplish this. --- utils/TableGen/Record.cpp | 49 +++++++++++++++++++++++++++++++++++++++++++- utils/TableGen/Record.h | 26 +++++++++-------------- 2 files changed, 57 insertions(+), 18 deletions(-) diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp index cf82255..2278b40 100644 --- oldutils/TableGen/Record.cpp +++ newutils/TableGen/Record.cpp @@ -1563,15 +1563,60 @@ const Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) const { const DagInit * DagInit::get(const Init *V, const std::string &VN, + ArrayRef ArgRange, + ArrayRef NameRange) { + typedef FoldingSet Pool; + static Pool ThePool; + + FoldingSetNodeID ID; + ID.AddPointer(V); + ID.AddString(VN); + + ArrayRef::iterator Arg = ArgRange.begin(); + ArrayRef::iterator Name = NameRange.begin(); + while (Arg != ArgRange.end()) { + assert(Name != NameRange.end() && "Arg name underflow!"); + ID.AddPointer(*Arg++); + ID.AddString(*Name++); + } + assert(Name == NameRange.end() && "Arg name overflow!"); + + void *IP = 0; + if (const DagInit *I = ThePool.FindNodeOrInsertPos(ID, IP)) + return I; + + DagInit *I = new DagInit(ID, V, VN, ArgRange, NameRange); + ThePool.InsertNode(I, IP); + + return I; +} + +const DagInit * +DagInit::get(const Init *V, const std::string &VN, const std::vector > &args) { - return new DagInit(V, VN, args); + typedef std::pair PairType; + + std::vector Args; + std::vector Names; + + for (std::vector::const_iterator i = args.begin(), + iend = args.end(); + i != iend; + ++i) { + Args.push_back(i->first); + Names.push_back(i->second); + } + + return DagInit::get(V, VN, ArrayRef(Args), + ArrayRef(Names)); } const DagInit * DagInit::get(const Init *V, const std::string &VN, const std::vector &args, const std::vector &argNames) { - return new DagInit(V, VN, args, argNames); + return DagInit::get(V, VN, ArrayRef(args), + ArrayRef(argNames)); } const Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) const { diff --git oldutils/TableGen/Record.h newutils/TableGen/Record.h index ed8f678..cdd08c4 100644 --- oldutils/TableGen/Record.h +++ newutils/TableGen/Record.h @@ -1250,33 +1250,27 @@ public: /// to have at least one value then a (possibly empty) list of arguments. Each /// argument can have a name associated with it. /// -class DagInit : public TypedInit { +class DagInit : public TypedInit, public FastFoldingSetNode { const Init *Val; std::string ValName; std::vector Args; std::vector ArgNames; - DagInit(const Init *V, const std::string &VN, - const std::vector > &args) - : TypedInit(DagRecTy::get()), Val(V), ValName(VN) { - Args.reserve(args.size()); - ArgNames.reserve(args.size()); - for (unsigned i = 0, e = args.size(); i != e; ++i) { - Args.push_back(args[i].first); - ArgNames.push_back(args[i].second); - } - } - DagInit(const Init *V, const std::string &VN, - const std::vector &args, - const std::vector &argNames) - : TypedInit(DagRecTy::get()), Val(V), ValName(VN), Args(args), - ArgNames(argNames) { } + DagInit(FoldingSetNodeID &ID, const Init *V, const std::string &VN, + ArrayRef ArgRange, + ArrayRef NameRange) + : TypedInit(DagRecTy::get()), FastFoldingSetNode(ID), Val(V), ValName(VN), + Args(ArgRange.begin(), ArgRange.end()), + ArgNames(NameRange.begin(), NameRange.end()) {} DagInit(const DagInit &Other); // Do not define. DagInit &operator=(const DagInit &Other); // Do not define. public: static const DagInit *get(const Init *V, const std::string &VN, + ArrayRef ArgRange, + ArrayRef NameRange); + static const DagInit *get(const Init *V, const std::string &VN, const std::vector< std::pair > &args); static const DagInit *get(const Init *V, const std::string &VN, -- 1.7.6 From stoklund at 2pi.dk Tue Jul 19 15:22:11 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 19 Jul 2011 13:22:11 -0700 Subject: [llvm-commits] [llvm] r135514 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp In-Reply-To: <20110719201117.8D6032A6C12D@llvm.org> References: <20110719201117.8D6032A6C12D@llvm.org> Message-ID: <2F290068-1F7A-44AD-8FA7-7F81B05B1E4A@2pi.dk> On Jul 19, 2011, at 1:11 PM, Akira Hatanaka wrote: > Author: ahatanak > Date: Tue Jul 19 15:11:17 2011 > New Revision: 135514 > > URL: http://llvm.org/viewvc/llvm-project?rev=135514&view=rev > Log: > Use descriptive variable names. > > > Modified: > llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thanks for doing this, Akira. This is so much better. /jakob From dblaikie at gmail.com Tue Jul 19 15:22:34 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 19 Jul 2011 13:22:34 -0700 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: References: Message-ID: > - ?return new BitInit(V); > + ?static const BitInit *True ?= 0; > + ?static const BitInit *False = 0; > + > + ?const BitInit **Result = (V ? &True : &False); > + > + ?if (*Result == 0) > + ? ?*Result = new BitInit(V); > + > + ?return *Result; You could use a reference here: const BitInit &*Result = (V ? True : False); if (Result == 0) Result = new BitINit(...); I'm not sure what LLVM's coding conventions are on the use of immediate static values rather than lazy initialization, but in this case is there a particular reason these are lazy? (if so, a comment explaining the necessity, if it's out of character/special, might be in order) - David From greened at obbligato.org Tue Jul 19 15:23:22 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 15:23:22 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> (David Greene's message of "Tue, 19 Jul 2011 15:11:36 -0500") References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: David Greene writes: > Add a DenseMapInfo implementation for std::string. This is useful > when mapping pairs that include a string component. > --- > include/llvm/ADT/StringExtras.h | 19 +++++++++++++++++++ > 1 files changed, 19 insertions(+), 0 deletions(-) > > diff --git oldinclude/llvm/ADT/StringExtras.h newinclude/llvm/ADT/StringExtras.h > index 5f5c041..d30e225 100644 > --- oldinclude/llvm/ADT/StringExtras.h > +++ newinclude/llvm/ADT/StringExtras.h Ah, shoot. My first experiment with git send-email is a big FAIL. Sorry about the bad path mangling. Hopefully these are still reviewable. I can easily re-send if necessary. -Dave From grosbach at apple.com Tue Jul 19 15:23:25 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 20:23:25 -0000 Subject: [llvm-commits] [llvm] r135516 - in /llvm/trunk/test/MC/ARM: basic-arm-instructions.s diagnostics.s Message-ID: <20110719202325.AE8622A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 15:23:25 2011 New Revision: 135516 URL: http://llvm.org/viewvc/llvm-project?rev=135516&view=rev Log: ARM testcases for MOVT. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135516&r1=135515&r2=135516&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 15:23:25 2011 @@ -705,6 +705,17 @@ @ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01] @------------------------------------------------------------------------------ +@ MOVT + at ------------------------------------------------------------------------------ + movt r3, #7 + movt r6, #0xffff + movteq r4, #0xff0 + +@ CHECK: movt r3, #7 @ encoding: [0x07,0x30,0x40,0xe3] +@ CHECK: movt r6, #65535 @ encoding: [0xff,0x6f,0x4f,0xe3] +@ CHECK: movteq r4, #4080 @ encoding: [0xf0,0x4f,0x40,0x03] + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135516&r1=135515&r2=135516&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 19 15:23:25 2011 @@ -99,3 +99,7 @@ movwseq r9, #0xffff @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified + + @ Out of range immediate for MOVT + movt r9, 0x10000 +@ CHECK-ERRORS: error: invalid operand for instruction From grosbach at apple.com Tue Jul 19 15:28:57 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 20:28:57 -0000 Subject: [llvm-commits] [llvm] r135517 - in /llvm/trunk/test/MC/ARM: arm_instructions.s basic-arm-instructions.s Message-ID: <20110719202857.172382A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 15:28:56 2011 New Revision: 135517 URL: http://llvm.org/viewvc/llvm-project?rev=135517&view=rev Log: Move mr[r]c[2] ARM tests and tidy up a bit. Modified: llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135517&r1=135516&r2=135517&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jul 19 15:28:56 2011 @@ -86,16 +86,6 @@ @ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] mrs r8, cpsr -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] - mrc p14, #0, r1, c1, c2, #4 -@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] - mrrc p7, #1, r5, r4, c1 - -@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] - mrc2 p14, #0, r1, c1, c2, #4 -@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] - mrrc2 p7, #1, r5, r4, c1 - @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] cdp p7, #1, c1, c1, c1, #4 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135517&r1=135516&r2=135517&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 15:28:56 2011 @@ -715,6 +715,25 @@ @ CHECK: movt r6, #65535 @ encoding: [0xff,0x6f,0x4f,0xe3] @ CHECK: movteq r4, #4080 @ encoding: [0xf0,0x4f,0x40,0x03] + + at ------------------------------------------------------------------------------ +@ MRC/MRC2 + at ------------------------------------------------------------------------------ + mrc p14, #0, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #4 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] + + at ------------------------------------------------------------------------------ +@ MRRC/MRRC2 + at ------------------------------------------------------------------------------ + mrrc p7, #1, r5, r4, c1 + mrrc2 p7, #1, r5, r4, c1 + +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] +@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ From greened at obbligato.org Tue Jul 19 15:32:12 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 15:32:12 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: (David Blaikie's message of "Tue, 19 Jul 2011 13:22:34 -0700") References: Message-ID: David Blaikie writes: >> - ?return new BitInit(V); >> + ?static const BitInit *True ?= 0; >> + ?static const BitInit *False = 0; >> + >> + ?const BitInit **Result = (V ? &True : &False); >> + >> + ?if (*Result == 0) >> + ? ?*Result = new BitInit(V); >> + >> + ?return *Result; > > You could use a reference here: > > const BitInit &*Result = (V ? True : False); > if (Result == 0) > Result = new BitINit(...); > > I'm not sure what LLVM's coding conventions are on the use of > immediate static values rather than lazy initialization, but in this > case is there a particular reason these are lazy? (if so, a comment > explaining the necessity, if it's out of character/special, might be > in order) I'm not sure what you mean by "lazy." Oh, you mean why aren't they initialized until needed? I suppose there is no good reason. I can certainly rework that. As for references, this is the old C guy in me creeping out. I try to keep him down as much as possible but he was too wily the other day. :) -Dave From eli.friedman at gmail.com Tue Jul 19 15:33:12 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 19 Jul 2011 13:33:12 -0700 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: On Tue, Jul 19, 2011 at 1:11 PM, David Greene wrote: > Add a DenseMapInfo implementation for std::string. ?This is useful > when mapping pairs that include a string component. > --- > ?include/llvm/ADT/StringExtras.h | ? 19 +++++++++++++++++++ > ?1 files changed, 19 insertions(+), 0 deletions(-) > > diff --git oldinclude/llvm/ADT/StringExtras.h newinclude/llvm/ADT/StringExtras.h > index 5f5c041..d30e225 100644 > --- oldinclude/llvm/ADT/StringExtras.h > +++ newinclude/llvm/ADT/StringExtras.h > @@ -16,6 +16,7 @@ > > ?#include "llvm/Support/DataTypes.h" > ?#include "llvm/ADT/APFloat.h" > +#include "llvm/ADT/DenseMapInfo.h" > ?#include "llvm/ADT/StringRef.h" > ?#include > ?#include > @@ -165,6 +166,24 @@ static inline unsigned HashString(StringRef Str, unsigned Result = 0) { > ? return Result; > ?} > > +// Provide DenseMapInfo for strings. > +template<> struct DenseMapInfo { > + ?static inline std::string getEmptyKey() { > + ? ?std::string Empty("<<>>"); > + ? ?return Empty; > + ?} > + ?static inline std::string getTombstoneKey() { > + ? ?std::string Tombstone("<<>>"); > + ? ?return Tombstone; > + ?} > + ?static unsigned getHashValue(const std::string& Val) { > + ? ?return HashString(Val); > + ?} > + ?static bool isEqual(const std::string& LHS, const std::string& RHS) { > + ? ?return LHS == RHS; > + ?} > +}; > + > ?} // End llvm namespace > > ?#endif > -- > 1.7.6 This is unsafe in general; TableGen might never see the string "<<>>", but you can't assume arbitrary code using this header will not see it. -Eli From ahatanak at gmail.com Tue Jul 19 15:34:00 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 20:34:00 -0000 Subject: [llvm-commits] [llvm] r135520 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll Message-ID: <20110719203400.936412A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 15:34:00 2011 New Revision: 135520 URL: http://llvm.org/viewvc/llvm-project?rev=135520&view=rev Log: Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135520&r1=135519&r2=135520&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 15:34:00 2011 @@ -870,9 +870,10 @@ BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) .addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(MaskUpper).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) + .addReg(ShiftAmt).addReg(MaskUpper); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); // atomic.load.binop @@ -911,7 +912,7 @@ BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); } else {// atomic.swap // and newval, incr2, mask - BuildMI(BB, dl, TII->get(Mips::ANDi), NewVal).addReg(Incr2).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); } BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0) @@ -933,8 +934,8 @@ BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) .addReg(OldVal).addReg(Mask); - BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) - .addReg(MaskedOldVal1).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) + .addReg(ShiftAmt).addReg(MaskedOldVal1); BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) @@ -1097,17 +1098,17 @@ BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) .addReg(Mips::ZERO).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), Mask) - .addReg(MaskUpper).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) + .addReg(ShiftAmt).addReg(MaskUpper); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) .addReg(CmpVal).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedCmpVal) - .addReg(MaskedCmpVal).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) + .addReg(ShiftAmt).addReg(MaskedCmpVal); BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) .addReg(NewVal).addImm(MaskImm); - BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedNewVal) - .addReg(MaskedNewVal).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) + .addReg(ShiftAmt).addReg(MaskedNewVal); // loop1MBB: // ll oldval,0(alginedaddr) @@ -1142,8 +1143,8 @@ BB = sinkMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes) - .addReg(MaskedOldVal0).addReg(ShiftAmt); + BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) + .addReg(ShiftAmt).addReg(MaskedOldVal0); BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) .addReg(SrlRes).addImm(ShiftImm); BuildMI(BB, dl, TII->get(Mips::SRA), Dest) Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135520&r1=135519&r2=135520&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Tue Jul 19 15:34:00 2011 @@ -94,9 +94,9 @@ ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -108,7 +108,7 @@ ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } @@ -125,9 +125,9 @@ ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -139,7 +139,7 @@ ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } @@ -156,9 +156,9 @@ ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -171,7 +171,7 @@ ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } @@ -188,9 +188,9 @@ ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -200,7 +200,7 @@ ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } @@ -217,12 +217,12 @@ ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] ; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]] ; CHECK: andi $[[R10:[0-9]+]], $5, 255 -; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]] +; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]]) @@ -235,7 +235,7 @@ ; CHECK: beq $[[R15]], $zero, $[[BB0]] ; CHECK: $[[BB1]]: -; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } From grosbach at apple.com Tue Jul 19 15:35:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 20:35:35 -0000 Subject: [llvm-commits] [llvm] r135521 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/diagnostics.s Message-ID: <20110719203535.402242A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 15:35:35 2011 New Revision: 135521 URL: http://llvm.org/viewvc/llvm-project?rev=135521&view=rev Log: ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. Add range checking to the immediate operands. Update tests accordingly. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135521&r1=135520&r2=135521&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 19 15:35:35 2011 @@ -3671,8 +3671,8 @@ imm:$CRm, imm:$opc2)]>; def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, (outs GPR:$Rt), - (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, - i32imm:$opc2), []>; + (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, + imm0_7:$opc2), []>; def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; @@ -3708,8 +3708,8 @@ imm:$CRm, imm:$opc2)]>; def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, (outs GPR:$Rt), - (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, - i32imm:$opc2), []>; + (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, + imm0_7:$opc2), []>; def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135521&r1=135520&r2=135521&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jul 19 15:35:35 2011 @@ -3389,13 +3389,12 @@ /* from coprocessor to ARM core register */ def t2MRC : t2MovRCopro<0b1110, "mrc", 1, - (outs GPR:$Rt), - (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), - []>; + (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, + c_imm:$CRm, imm0_7:$opc2), []>; def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, - (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, - c_imm:$CRm, i32imm:$opc2), []>; + (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, + c_imm:$CRm, imm0_7:$opc2), []>; def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135521&r1=135520&r2=135521&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 19 15:35:35 2011 @@ -103,3 +103,17 @@ @ Out of range immediate for MOVT movt r9, 0x10000 @ CHECK-ERRORS: error: invalid operand for instruction + + @ Out of range immediates for MRC/MRC2/MRRC/MRRC2 + mrc p14, #8, r1, c1, c2, #4 + mrc p14, #1, r1, c1, c2, #8 + mrc2 p14, #8, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #9 + mrrc p7, #16, r5, r4, c1 + mrrc2 p7, #17, r5, r4, c1 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction From dblaikie at gmail.com Tue Jul 19 15:54:11 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 19 Jul 2011 13:54:11 -0700 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: References: Message-ID: On Tue, Jul 19, 2011 at 1:32 PM, David A. Greene wrote: > David Blaikie writes: > >>> - ?return new BitInit(V); >>> + ?static const BitInit *True ?= 0; >>> + ?static const BitInit *False = 0; >>> + >>> + ?const BitInit **Result = (V ? &True : &False); >>> + >>> + ?if (*Result == 0) >>> + ? ?*Result = new BitInit(V); >>> + >>> + ?return *Result; >> >> You could use a reference here: >> >> const BitInit &*Result = (V ? True : False); >> if (Result == 0) >> ? Result = new BitINit(...); >> >> I'm not sure what LLVM's coding conventions are on the use of >> immediate static values rather than lazy initialization, but in this >> case is there a particular reason these are lazy? (if so, a comment >> explaining the necessity, if it's out of character/special, might be >> in order) > > I'm not sure what you mean by "lazy." ?Oh, you mean why aren't they > initialized until needed? ?I suppose there is no good reason. ?I > can certainly rework that. Yeah, just doing: static const BitInit True(true); static const BitInit False(false); return V ? True : False; I'd probably put these constants outside the function, just so the compiler doesn't emit its own lazy initializers (if it can prove that the construction order is irrelevant, then it could skip the lazy init, but otherwise it must init these local statics on the first call, not before) > As for references, this is the old C guy in me creeping out. ?I try to > keep him down as much as possible but he was too wily the other day. ?:) Yep, it happens - and in this case it's perhaps not strictly better (eh, it's a non-issue if you're removing the manual lazy init anyway), I was just reminded of another CR last week or the week before when someone went to fix some code that looked like it was broken (retrieved a reference to a pointer from a map, checked the pointer, inited the pointer if necessary, then did nothing else - the reader thought that the value hadn't been put back in the map, but it had via the reference) so it's certainly not the most obvious code, but in your case the scope of the reference would've been shorter (& thus more obvious) than in the other one I'm thinking of. Of course this lazy init feedback applies to your other CRs too - though I think only one other Init type has lazy init of a known set of values (the UnInit type, or similar). - David From ahatanak at gmail.com Tue Jul 19 15:56:53 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 20:56:53 -0000 Subject: [llvm-commits] [llvm] r135522 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110719205653.9D90A2A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 15:56:53 2011 New Revision: 135522 URL: http://llvm.org/viewvc/llvm-project?rev=135522&view=rev Log: Change variable name. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135522&r1=135521&r2=135522&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 15:56:53 2011 @@ -822,7 +822,7 @@ unsigned MaskUpper = RegInfo.createVirtualRegister(RC); unsigned AndRes = RegInfo.createVirtualRegister(RC); unsigned BinOpRes = RegInfo.createVirtualRegister(RC); - unsigned MaskOldVal0 = RegInfo.createVirtualRegister(RC); + unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); unsigned StoreVal = RegInfo.createVirtualRegister(RC); unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); unsigned SrlRes = RegInfo.createVirtualRegister(RC); @@ -915,10 +915,10 @@ BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); } - BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0) + BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) .addReg(OldVal).addReg(Mask2); BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) - .addReg(MaskOldVal0).addReg(NewVal); + .addReg(MaskedOldVal0).addReg(NewVal); BuildMI(BB, dl, TII->get(Mips::SC), Success) .addReg(StoreVal).addReg(AlignedAddr).addImm(0); BuildMI(BB, dl, TII->get(Mips::BEQ)) From resistor at mac.com Tue Jul 19 16:06:00 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 19 Jul 2011 21:06:00 -0000 Subject: [llvm-commits] [llvm] r135524 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/ARM/ARMInstrFormats.td utils/TableGen/FixedLenDecoderEmitter.cpp utils/TableGen/FixedLenDecoderEmitter.h Message-ID: <20110719210600.6CC622A6C12D@llvm.org> Author: resistor Date: Tue Jul 19 16:06:00 2011 New Revision: 135524 URL: http://llvm.org/viewvc/llvm-project?rev=135524&view=rev Log: Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=135524&r1=135523&r2=135524&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Tue Jul 19 16:06:00 2011 @@ -297,6 +297,10 @@ // from the opcode. int Size = 0; + // DecoderNamespace - The "namespace" in which this instruction exists, on + // targets like ARM which multiple ISA namespaces exist. + string DecoderNamespace = ""; + // Code size, for instruction selection. // FIXME: What does this actually mean? int CodeSize = 0; Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135524&r1=135523&r2=135524&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jul 19 16:06:00 2011 @@ -262,13 +262,17 @@ class InstARM - : InstTemplate, Encoding; + : InstTemplate, Encoding { + let DecoderNamespace = "ARM"; +} // This Encoding-less class is used by Thumb1 to specify the encoding bits later // on by adding flavors to specific instructions. class InstThumb - : InstTemplate; + : InstTemplate { + let DecoderNamespace = "Thumb"; +} class PseudoInst pattern> : InstTemplate Predicates = [IsThumb2]; + let DecoderNamespace = "Thumb2"; } // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an @@ -1091,6 +1096,7 @@ let AsmString = !strconcat(opc, "${s}${p}", asm); let Pattern = pattern; list Predicates = [IsThumb2]; + let DecoderNamespace = "Thumb2"; } // Special cases @@ -1103,6 +1109,7 @@ let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb2]; + let DecoderNamespace = "Thumb2"; } class ThumbXI Predicates = [IsThumb, IsThumb1Only]; + let DecoderNamespace = "Thumb"; } class T2I Predicates = [IsThumb2]; + let DecoderNamespace = "Thumb2"; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=135524&r1=135523&r2=135524&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Tue Jul 19 16:06:00 2011 @@ -84,11 +84,8 @@ // Forward declaration. class FilterChooser; -// FIXME: Possibly auto-detected? -#define BIT_WIDTH 32 - // Representation of the instruction to work on. -typedef bit_value_t insn_t[BIT_WIDTH]; +typedef std::vector insn_t; /// Filter - Filter works with FilterChooser to produce the decoding tree for /// the ISA. @@ -230,7 +227,7 @@ // Array of bit values passed down from our parent. // Set to all BIT_UNFILTERED's for Parent == NULL. - bit_value_t FilterBitValues[BIT_WIDTH]; + std::vector FilterBitValues; // Links to the FilterChooser above us in the decoding tree. FilterChooser *Parent; @@ -238,21 +235,24 @@ // Index of the best filter from Filters. int BestIndex; + // Width of instructions + unsigned BitWidth; + public: FilterChooser(const FilterChooser &FC) : AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes), - Operands(FC.Operands), Filters(FC.Filters), Parent(FC.Parent), - BestIndex(FC.BestIndex) { - memcpy(FilterBitValues, FC.FilterBitValues, sizeof(FilterBitValues)); - } + Operands(FC.Operands), Filters(FC.Filters), + FilterBitValues(FC.FilterBitValues), Parent(FC.Parent), + BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { } FilterChooser(const std::vector &Insts, const std::vector &IDs, - std::map > &Ops) : + std::map > &Ops, + unsigned BW) : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), - Parent(NULL), BestIndex(-1) { - for (unsigned i = 0; i < BIT_WIDTH; ++i) - FilterBitValues[i] = BIT_UNFILTERED; + Parent(NULL), BestIndex(-1), BitWidth(BW) { + for (unsigned i = 0; i < BitWidth; ++i) + FilterBitValues.push_back(BIT_UNFILTERED); doFilter(); } @@ -260,13 +260,11 @@ FilterChooser(const std::vector &Insts, const std::vector &IDs, std::map > &Ops, - bit_value_t (&ParentFilterBitValues)[BIT_WIDTH], + std::vector &ParentFilterBitValues, FilterChooser &parent) : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), - Filters(), Parent(&parent), BestIndex(-1) { - for (unsigned i = 0; i < BIT_WIDTH; ++i) - FilterBitValues[i] = ParentFilterBitValues[i]; - + Filters(), FilterBitValues(ParentFilterBitValues), + Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) { doFilter(); } @@ -274,15 +272,15 @@ bool isTopLevel() { return Parent == NULL; } // Emit the top level typedef and decodeInstruction() function. - void emitTop(raw_ostream &o, unsigned Indentation); + void emitTop(raw_ostream &o, unsigned Indentation, std::string Namespace); protected: // Populates the insn given the uid. void insnWithID(insn_t &Insn, unsigned Opcode) const { BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); - for (unsigned i = 0; i < BIT_WIDTH; ++i) - Insn[i] = bitFromBits(Bits, i); + for (unsigned i = 0; i < BitWidth; ++i) + Insn.push_back(bitFromBits(Bits, i)); } // Returns the record name. @@ -300,7 +298,7 @@ /// dumpFilterArray - dumpFilterArray prints out debugging info for the given /// filter array as a series of chars. - void dumpFilterArray(raw_ostream &o, bit_value_t (&filter)[BIT_WIDTH]); + void dumpFilterArray(raw_ostream &o, std::vector & filter); /// dumpStack - dumpStack traverses the filter chooser chain and calls /// dumpFilterArray on each filter chooser up to the top level one. @@ -375,7 +373,7 @@ Filter::Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed) : Owner(&owner), StartBit(startBit), NumBits(numBits), Mixed(mixed) { - assert(StartBit + NumBits - 1 < BIT_WIDTH); + assert(StartBit + NumBits - 1 < Owner->BitWidth); NumFiltered = 0; LastOpcFiltered = 0; @@ -427,9 +425,8 @@ void Filter::recurse() { std::map >::const_iterator mapIterator; - bit_value_t BitValueArray[BIT_WIDTH]; // Starts by inheriting our parent filter chooser's filter bit values. - memcpy(BitValueArray, Owner->FilterBitValues, sizeof(BitValueArray)); + std::vector BitValueArray(Owner->FilterBitValues); unsigned bitIndex; @@ -493,8 +490,9 @@ o << StartBit << "} ...\n"; - o.indent(Indentation) << "switch (fieldFromInstruction(insn, " - << StartBit << ", " << NumBits << ")) {\n"; + o.indent(Indentation) << "switch (fieldFromInstruction" << Owner->BitWidth + << "(insn, " << StartBit << ", " + << NumBits << ")) {\n"; std::map::iterator filterIterator; @@ -559,60 +557,12 @@ ////////////////////////////////// // Emit the top level typedef and decodeInstruction() function. -void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation) { - switch (BIT_WIDTH) { - case 8: - o.indent(Indentation) << "typedef uint8_t field_t;\n"; - break; - case 16: - o.indent(Indentation) << "typedef uint16_t field_t;\n"; - break; - case 32: - o.indent(Indentation) << "typedef uint32_t field_t;\n"; - break; - case 64: - o.indent(Indentation) << "typedef uint64_t field_t;\n"; - break; - default: - assert(0 && "Unexpected instruction size!"); - } - - o << '\n'; - - o.indent(Indentation) << "static field_t " << - "fieldFromInstruction(field_t insn, unsigned startBit, unsigned numBits)\n"; - - o.indent(Indentation) << "{\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "assert(startBit + numBits <= " << BIT_WIDTH - << " && \"Instruction field out of bounds!\");\n"; - o << '\n'; - o.indent(Indentation) << "field_t fieldMask;\n"; - o << '\n'; - o.indent(Indentation) << "if (numBits == " << BIT_WIDTH << ")\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "fieldMask = (field_t)-1;\n"; - --Indentation; --Indentation; - - o.indent(Indentation) << "else\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "fieldMask = ((1 << numBits) - 1) << startBit;\n"; - --Indentation; --Indentation; - - o << '\n'; - o.indent(Indentation) << "return (insn & fieldMask) >> startBit;\n"; - --Indentation; --Indentation; - - o.indent(Indentation) << "}\n"; - - o << '\n'; - +void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation, + std::string Namespace) { o.indent(Indentation) << - "static bool decodeInstruction(MCInst &MI, field_t insn, " - "uint64_t Address, const void *Decoder) {\n"; + "static bool decode" << Namespace << "Instruction" << BitWidth + << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, " + << "const void *Decoder) {\n"; o.indent(Indentation) << " unsigned tmp = 0;\n"; ++Indentation; ++Indentation; @@ -651,10 +601,10 @@ /// dumpFilterArray - dumpFilterArray prints out debugging info for the given /// filter array as a series of chars. void FilterChooser::dumpFilterArray(raw_ostream &o, - bit_value_t (&filter)[BIT_WIDTH]) { + std::vector &filter) { unsigned bitIndex; - for (bitIndex = BIT_WIDTH; bitIndex > 0; bitIndex--) { + for (bitIndex = BitWidth; bitIndex > 0; bitIndex--) { switch (filter[bitIndex - 1]) { case BIT_UNFILTERED: o << "."; @@ -727,7 +677,7 @@ int State = 0; int Val = -1; - for (unsigned i = 0; i < BIT_WIDTH; ++i) { + for (unsigned i = 0; i < BitWidth; ++i) { Val = Value(Insn[i]); bool Filtered = PositionFiltered(i); switch (State) { @@ -761,7 +711,7 @@ } // If we are still in Island after the loop, do some housekeeping. if (State == 2) { - EndBits.push_back(BIT_WIDTH - 1); + EndBits.push_back(BitWidth - 1); FieldVals.push_back(FieldVal); ++Num; } @@ -802,8 +752,8 @@ } o.indent(Indentation) - << " tmp = fieldFromInstruction(insn, " << I->FieldBase - << ", " << I->FieldLength << ");\n"; + << " tmp = fieldFromInstruction" << BitWidth + << "(insn, " << I->FieldBase << ", " << I->FieldLength << ");\n"; if (I->Decoder != "") { o.indent(Indentation) << " " << I->Decoder << "(MI, tmp, Address, Decoder);\n"; @@ -836,7 +786,8 @@ for (I = Size; I != 0; --I) { NumBits = EndBits[I-1] - StartBits[I-1] + 1; - o << "fieldFromInstruction(insn, " << StartBits[I-1] << ", " << NumBits + o << "fieldFromInstruction" << BitWidth << "(insn, " + << StartBits[I-1] << ", " << NumBits << ") == " << FieldVals[I-1]; if (I > 1) o << " && "; @@ -855,7 +806,8 @@ } o.indent(Indentation) - << " tmp = fieldFromInstruction(insn, " << I->FieldBase + << " tmp = fieldFromInstruction" << BitWidth + << "(insn, " << I->FieldBase << ", " << I->FieldLength << ");\n"; if (I->Decoder != "") { o.indent(Indentation) << " " << I->Decoder @@ -965,23 +917,23 @@ // (MIXED) ------ . ----> (MIXED) // (FILTERED)---- . ----> (FILTERED) - bitAttr_t bitAttrs[BIT_WIDTH]; + std::vector bitAttrs; // FILTERED bit positions provide no entropy and are not worthy of pursuing. // Filter::recurse() set either BIT_TRUE or BIT_FALSE for each position. - for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex) + for (BitIndex = 0; BitIndex < BitWidth; ++BitIndex) if (FilterBitValues[BitIndex] == BIT_TRUE || FilterBitValues[BitIndex] == BIT_FALSE) - bitAttrs[BitIndex] = ATTR_FILTERED; + bitAttrs.push_back(ATTR_FILTERED); else - bitAttrs[BitIndex] = ATTR_NONE; + bitAttrs.push_back(ATTR_NONE); for (InsnIndex = 0; InsnIndex < numInstructions; ++InsnIndex) { insn_t insn; insnWithID(insn, Opcodes[InsnIndex]); - for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex) { + for (BitIndex = 0; BitIndex < BitWidth; ++BitIndex) { switch (bitAttrs[BitIndex]) { case ATTR_NONE: if (insn[BitIndex] == BIT_UNSET) @@ -1027,7 +979,7 @@ bitAttr_t RA = ATTR_NONE; unsigned StartBit = 0; - for (BitIndex = 0; BitIndex < BIT_WIDTH; BitIndex++) { + for (BitIndex = 0; BitIndex < BitWidth; BitIndex++) { bitAttr_t bitAttr = bitAttrs[BitIndex]; assert(bitAttr != ATTR_NONE && "Bit without attributes"); @@ -1216,8 +1168,9 @@ return true; } -bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, - unsigned Opc){ +static bool populateInstruction(const CodeGenInstruction &CGI, + unsigned Opc, + std::map >& Operands){ const Record &Def = *CGI.TheDef; // If all the bit positions are not specified; do not decode this instruction. // We are bound to fail! For proper disassembly, the well-known encoding bits @@ -1351,16 +1304,43 @@ return true; } -void FixedLenDecoderEmitter::populateInstructions() { - for (unsigned i = 0, e = NumberedInstructions.size(); i < e; ++i) { - Record *R = NumberedInstructions[i]->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode" || - R->getValueAsBit("isPseudo")) - continue; +static void emitHelper(llvm::raw_ostream &o, unsigned BitWidth) { + unsigned Indentation = 0; + std::string WidthStr = "uint" + utostr(BitWidth) + "_t"; - if (populateInstruction(*NumberedInstructions[i], i)) - Opcodes.push_back(i); - } + o << '\n'; + + o.indent(Indentation) << "static " << WidthStr << + " fieldFromInstruction" << BitWidth << + "(" << WidthStr <<" insn, unsigned startBit, unsigned numBits)\n"; + + o.indent(Indentation) << "{\n"; + + ++Indentation; ++Indentation; + o.indent(Indentation) << "assert(startBit + numBits <= " << BitWidth + << " && \"Instruction field out of bounds!\");\n"; + o << '\n'; + o.indent(Indentation) << WidthStr << " fieldMask;\n"; + o << '\n'; + o.indent(Indentation) << "if (numBits == " << BitWidth << ")\n"; + + ++Indentation; ++Indentation; + o.indent(Indentation) << "fieldMask = (" << WidthStr << ")-1;\n"; + --Indentation; --Indentation; + + o.indent(Indentation) << "else\n"; + + ++Indentation; ++Indentation; + o.indent(Indentation) << "fieldMask = ((1 << numBits) - 1) << startBit;\n"; + --Indentation; --Indentation; + + o << '\n'; + o.indent(Indentation) << "return (insn & fieldMask) >> startBit;\n"; + --Indentation; --Indentation; + + o.indent(Indentation) << "}\n"; + + o << '\n'; } // Emits disassembler code for instruction decoding. @@ -1372,10 +1352,47 @@ o << '\n'; o << "namespace llvm {\n\n"; + // Parameterize the decoders based on namespace and instruction width. NumberedInstructions = Target.getInstructionsByEnumValue(); - populateInstructions(); - FilterChooser FC(NumberedInstructions, Opcodes, Operands); - FC.emitTop(o, 0); + std::map, + std::vector > OpcMap; + std::map > Operands; + + for (unsigned i = 0; i < NumberedInstructions.size(); ++i) { + const CodeGenInstruction *Inst = NumberedInstructions[i]; + Record *Def = Inst->TheDef; + unsigned Size = Def->getValueAsInt("Size"); + if (Def->getValueAsString("Namespace") == "TargetOpcode" || + Def->getValueAsBit("isPseudo") || + Def->getValueAsBit("isAsmParserOnly") || + Def->getValueAsBit("isCodeGenOnly")) + continue; + + std::string DecoderNamespace = Def->getValueAsString("DecoderNamespace"); + + if (Size) { + if (populateInstruction(*Inst, i, Operands)) { + OpcMap[std::make_pair(DecoderNamespace, Size)].push_back(i); + } + } + } + + std::set Sizes; + for (std::map, + std::vector >::iterator + I = OpcMap.begin(), E = OpcMap.end(); I != E; ++I) { + // If we haven't visited this instruction width before, emit the + // helper method to extract fields. + if (!Sizes.count(I->first.second)) { + emitHelper(o, 8*I->first.second); + Sizes.insert(I->first.second); + } + + // Emit the decoder for this namespace+width combination. + FilterChooser FC(NumberedInstructions, I->second, Operands, + 8*I->first.second); + FC.emitTop(o, 0, I->first.first); + } o << "\n} // End llvm namespace \n"; } Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=135524&r1=135523&r2=135524&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original) +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Tue Jul 19 16:06:00 2011 @@ -47,8 +47,6 @@ std::vector Opcodes; std::map > Operands; - bool populateInstruction(const CodeGenInstruction &CGI, unsigned Opc); - void populateInstructions(); }; } // end llvm namespace From greened at obbligato.org Tue Jul 19 16:11:40 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 16:11:40 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: (Eli Friedman's message of "Tue, 19 Jul 2011 13:33:12 -0700") References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: Eli Friedman writes: > On Tue, Jul 19, 2011 at 1:11 PM, David Greene wrote: > This is unsafe in general; TableGen might never see the string > "<<>>", but you can't assume arbitrary code using this > header will not see it. True, but it's highly unlikely. Do you have a better alternative? I certainly would like to do this the Right Way. -Dave From greened at obbligato.org Tue Jul 19 16:14:11 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 16:14:11 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: (David Blaikie's message of "Tue, 19 Jul 2011 13:54:11 -0700") References: Message-ID: David Blaikie writes: > I'd probably put these constants outside the function, just so the > compiler doesn't emit its own lazy initializers (if it can prove that > the construction order is irrelevant, then it could skip the lazy > init, but otherwise it must init these local statics on the first > call, not before) Well, there's a scoping issue there. It seems to me like not polluting the llvm namespace is more beneficial than avoiding some lazy initialization that might happen once and probably not ever because compiler's aren't that smart. :) > Of course this lazy init feedback applies to your other CRs too - > though I think only one other Init type has lazy init of a known set > of values (the UnInit type, or similar). UnsetInit is the only other one, I think. I've fixed both. -Dave From echristo at apple.com Tue Jul 19 16:26:22 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 19 Jul 2011 14:26:22 -0700 Subject: [llvm-commits] [llvm] r135342 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c In-Reply-To: <52725BD3-8C7A-41CE-98C1-B1A4FA90FC5E@apple.com> References: <20110716072835.BDAC72A6C12C@llvm.org> <219B41AE-4EC9-45A6-8014-E52311FD278A@apple.com> <04584A21-9481-4179-AB3D-B2E4A8D53123@apple.com> <443EBCCB-7E7F-4CA4-9924-043099FDFFAD@apple.com> <52725BD3-8C7A-41CE-98C1-B1A4FA90FC5E@apple.com> Message-ID: <56D1490B-E531-4904-8BD7-881C8A02D857@apple.com> On Jul 17, 2011, at 12:10 AM, Eric Christopher wrote: > > On Jul 16, 2011, at 6:41 PM, Chris Lattner wrote: > >>>> >>>> Hey Eric, >>>> >>>> Why is this test in test/FrontendC anyway, instead of in the clang testsuite? >>> >>> I don't know. Probably originally for llvm-gcc for tests? >> >> Hey, I hear that llvmgcc is dead, can we move these tests? If dragonegg wants them, they can be copied into it's repo too. > > The Frontend* tests? Totally. A few of them will need to be changed for the different codegen, but that's not a problem and will make running "make check" for llvm way less annoying. FWIW I'm doing this now. I'm removing (not migrating) the tests that seem to test gcc front end things instead of clang front end things or where I'm positive we have a clang test already. -eric From dblaikie at gmail.com Tue Jul 19 16:33:52 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 19 Jul 2011 14:33:52 -0700 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: References: Message-ID: > Well, there's a scoping issue there. ?It seems to me like not polluting > the llvm namespace is more beneficial than avoiding some lazy > initialization that might happen once and probably not ever because > compiler's aren't that smart. ?:) Actually it's the other way - compilers have to do the lazy init (though it doesn't have to be thread safe in C++03, probably does have to be thread safe in C++0x though I haven't checked - there's a fancy superfast way to do this thread safely, though) unless they're smart enough to prove it's not necessary (the "as if" clause - static locals must be initialized on the first call, but if the compiler can prove that initializing them at some other time will look "as if" it was the first call, they can do that) But yes, I'd put it in an anonymous namespace (C++ equivalent of a c-style file-scoped static, so it doesn't pollute any namespaces) if I were doing that. > UnsetInit is the only other one, I think. ?I've fixed both. Cool - David From greened at obbligato.org Tue Jul 19 16:45:47 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 16:45:47 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: (David Blaikie's message of "Tue, 19 Jul 2011 14:33:52 -0700") References: Message-ID: David Blaikie writes: >> Well, there's a scoping issue there. ?It seems to me like not polluting >> the llvm namespace is more beneficial than avoiding some lazy >> initialization that might happen once and probably not ever because >> compiler's aren't that smart. ?:) > > Actually it's the other way - compilers have to do the lazy init Of course. Duh. :) > But yes, I'd put it in an anonymous namespace (C++ equivalent of a > c-style file-scoped static, so it doesn't pollute any namespaces) if I > were doing that. It pollutes the namespace for the source file, just the same way a global "static" does. But in any case, I'll move it out as requested. -Dave From greened at obbligato.org Tue Jul 19 16:47:22 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 16:47:22 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: (David A. Greene's message of "Tue, 19 Jul 2011 16:45:47 -0500") References: Message-ID: greened at obbligato.org (David A. Greene) writes: > David Blaikie writes: > > It pollutes the namespace for the source file, just the same way a > global "static" does. But in any case, I'll move it out as requested. Urk. Forgot about the other reason it has to be function-scope: it needs access to the private constructor. :) -Dave From dblaikie at gmail.com Tue Jul 19 16:51:11 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 19 Jul 2011 14:51:11 -0700 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: References: Message-ID: > Urk. ?Forgot about the other reason it has to be function-scope: it > needs access to the private constructor. ?:) Oh, right - well then they could be private class statics if you wanted to avoid the lazy init. - David From grosbach at apple.com Tue Jul 19 16:59:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 21:59:30 -0000 Subject: [llvm-commits] [llvm] r135527 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMRegisterInfo.td test/MC/ARM/arm_instructions.s test/MC/ARM/basic-arm-instructions.s Message-ID: <20110719215930.23D272A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 16:59:29 2011 New Revision: 135527 URL: http://llvm.org/viewvc/llvm-project?rev=135527&view=rev Log: ARM assembly parsing of MRS instruction. Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135527&r1=135526&r2=135527&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 19 16:59:29 2011 @@ -3769,20 +3769,22 @@ def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; //===----------------------------------------------------------------------===// -// Move between special register and ARM core register -- for disassembly only +// Move between special register and ARM core register // // Move to ARM core register from Special Register -def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr", - [/* For disassembly only; pattern left blank */]> { +def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, + "mrs", "\t$Rd, apsr", []> { bits<4> Rd; let Inst{23-16} = 0b00001111; let Inst{15-12} = Rd; let Inst{7-4} = 0b0000; } -def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr", - [/* For disassembly only; pattern left blank */]> { +def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>; + +def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, + "mrs", "\t$Rd, spsr", []> { bits<4> Rd; let Inst{23-16} = 0b01001111; let Inst{15-12} = Rd; Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=135527&r1=135526&r2=135527&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Jul 19 16:59:29 2011 @@ -182,8 +182,10 @@ // Current Program Status Register. def CPSR : ARMReg<0, "cpsr">; -def FPSCR : ARMReg<1, "fpscr">; -def ITSTATE : ARMReg<2, "itstate">; +def APSR : ARMReg<1, "apsr">; +def SPSR : ARMReg<2, "spsr">; +def FPSCR : ARMReg<3, "fpscr">; +def ITSTATE : ARMReg<4, "itstate">; // Special Registers - only available in privileged mode. def FPSID : ARMReg<0, "fpsid">; Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135527&r1=135526&r2=135527&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jul 19 16:59:29 2011 @@ -83,9 +83,6 @@ @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] bkpt #10 -@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] - mrs r8, cpsr - @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] cdp p7, #1, c1, c1, c1, #4 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135527&r1=135526&r2=135527&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 16:59:29 2011 @@ -734,6 +734,19 @@ @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] + + at ------------------------------------------------------------------------------ +@ MRS + at ------------------------------------------------------------------------------ + mrs r8, apsr + mrs r8, cpsr + mrs r8, spsr +@ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1] +@ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1] +@ CHECK: mrs r8, spsr @ encoding: [0x00,0x80,0x4f,0xe1] + + + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ From eli.friedman at gmail.com Tue Jul 19 17:08:23 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 19 Jul 2011 15:08:23 -0700 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: On Tue, Jul 19, 2011 at 2:11 PM, David A. Greene wrote: > Eli Friedman writes: > >> On Tue, Jul 19, 2011 at 1:11 PM, David Greene wrote: >> This is unsafe in general; TableGen might never see the string >> "<<>>", but you can't assume arbitrary code using this >> header will not see it. > > True, but it's highly unlikely. ?Do you have a better alternative? ?I > certainly would like to do this the Right Way. Use std::map? It's not like performance matters here. -Eli From dpatel at apple.com Tue Jul 19 17:31:15 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 19 Jul 2011 22:31:15 -0000 Subject: [llvm-commits] [llvm] r135528 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110719223115.F1FAB2A6C12D@llvm.org> Author: dpatel Date: Tue Jul 19 17:31:15 2011 New Revision: 135528 URL: http://llvm.org/viewvc/llvm-project?rev=135528&view=rev Log: Distinguish between two copies of one inlined variable. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/Analysis/DebugInfo.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=135528&r1=135527&r2=135528&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jul 19 17:31:15 2011 @@ -725,6 +725,9 @@ DIVariable createInlinedVariable(MDNode *DV, MDNode *InlinedScope, LLVMContext &VMContext); + /// cleanseInlinedVariable - Remove inlined scope from the variable. + DIVariable cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext); + class DebugInfoFinder { public: /// processModule - Process entire module and collect debug info Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=135528&r1=135527&r2=135528&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Jul 19 17:31:15 2011 @@ -776,6 +776,17 @@ return DIVariable(MDNode::get(VMContext, Elts)); } +/// cleanseInlinedVariable - Remove inlined scope from the variable. +DIVariable llvm::cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext) { + SmallVector Elts; + // Insert inlined scope as 7th element. + for (unsigned i = 0, e = DV->getNumOperands(); i != e; ++i) + i == 7 ? + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))): + Elts.push_back(DV->getOperand(i)); + return DIVariable(MDNode::get(VMContext, Elts)); +} + //===----------------------------------------------------------------------===// // DebugInfoFinder implementations. //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=135528&r1=135527&r2=135528&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jul 19 17:31:15 2011 @@ -1268,14 +1268,18 @@ } /// findAbstractVariable - Find abstract variable, if any, associated with Var. -DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &Var, +DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &DV, DebugLoc ScopeLoc) { + LLVMContext &Ctx = DV->getContext(); + + // More then one inlined variable corresponds to one abstract variable. + DIVariable Var = cleanseInlinedVariable(DV, Ctx); DbgVariable *AbsDbgVariable = AbstractVariables.lookup(Var); if (AbsDbgVariable) return AbsDbgVariable; - LLVMContext &Ctx = Var->getContext(); + DbgScope *Scope = AbstractScopes.lookup(ScopeLoc.getScope(Ctx)); if (!Scope) return NULL; Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=135528&r1=135527&r2=135528&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Jul 19 17:31:15 2011 @@ -770,8 +770,15 @@ for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ++BI) { DebugLoc DL = BI->getDebugLoc(); - if (!DL.isUnknown()) + if (!DL.isUnknown()) { BI->setDebugLoc(updateInlinedAtInfo(DL, TheCallDL, BI->getContext())); + if (DbgValueInst *DVI = dyn_cast(BI)) { + LLVMContext &Ctx = BI->getContext(); + MDNode *InlinedAt = BI->getDebugLoc().getInlinedAt(Ctx); + DVI->setOperand(2, createInlinedVariable(DVI->getVariable(), + InlinedAt, Ctx)); + } + } } } } From criswell at illinois.edu Tue Jul 19 17:36:27 2011 From: criswell at illinois.edu (John Criswell) Date: Tue, 19 Jul 2011 17:36:27 -0500 Subject: [llvm-commits] Updated SAFECode Patch Message-ID: <4E2606EB.2070300@illinois.edu> Dear All, Attached is an updated version of the SAFECode patch. This patch: 1) Is updated to the new LLVM type API; and 2) Can just be applied using patch -p0 < scpatch instead of having to untar an archive of changes. 3) Perhaps I forgot it in previous posts, but using patch -p0 < testpatch in the test-suite directory will provide some test Makefiles which can be used by using "make TEST=sc report" 4) It includes a RewriteOOB pass which implements a feature called Out of Bounds Pointer rewriting. Basically, it allows SAFECode to permit out of bound pointers provided that such pointers are not dereferenced. It's an optional feature. -- John T. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: scpatch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110719/0a92b2b5/attachment-0002.pl -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: testpatch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110719/0a92b2b5/attachment-0003.pl From grosbach at apple.com Tue Jul 19 17:45:10 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 19 Jul 2011 22:45:10 -0000 Subject: [llvm-commits] [llvm] r135532 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/basic-arm-instructions.s test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110719224510.608B62A6C12D@llvm.org> Author: grosbach Date: Tue Jul 19 17:45:10 2011 New Revision: 135532 URL: http://llvm.org/viewvc/llvm-project?rev=135532&view=rev Log: Tweak ARM assembly parsing and printing of MSR instruction. The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 19 17:45:10 2011 @@ -3798,8 +3798,7 @@ // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains // the mask with the fields to be accessed in the special register. def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, - "msr", "\t$mask, $Rn", - [/* For disassembly only; pattern left blank */]> { + "msr", "\t$mask, $Rn", []> { bits<5> mask; bits<4> Rn; @@ -3813,8 +3812,7 @@ } def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, - "msr", "\t$mask, $a", - [/* For disassembly only; pattern left blank */]> { + "msr", "\t$mask, $a", []> { bits<5> mask; bits<12> a; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 19 17:45:10 2011 @@ -1430,7 +1430,7 @@ // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" size_t Start = 0, Next = Mask.find('_'); StringRef Flags = ""; - StringRef SpecReg = Mask.slice(Start, Next); + std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); if (Next != StringRef::npos) Flags = Mask.slice(Next+1, Mask.size()); @@ -1441,7 +1441,7 @@ if (SpecReg == "apsr") { FlagsVal = StringSwitch(Flags) - .Case("nzcvq", 0x8) // same as CPSR_c + .Case("nzcvq", 0x8) // same as CPSR_f .Case("g", 0x4) // same as CPSR_s .Case("nzcvqg", 0xc) // same as CPSR_fs .Default(~0U); Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Jul 19 17:45:10 2011 @@ -481,10 +481,23 @@ unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as + // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + O << "APSR_"; + switch (Mask) { + default: assert(0); + case 4: O << "g"; return; + case 8: O << "nzcvq"; return; + case 12: O << "nzcvqg"; return; + } + llvm_unreachable("Unexpected mask value!"); + } + if (SpecRegRBit) - O << "spsr"; + O << "SPSR"; else - O << "cpsr"; + O << "CPSR"; if (Mask) { O << '_'; Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jul 19 17:45:10 2011 @@ -121,45 +121,6 @@ @ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1] cpsie if, #10 -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr apsr, r0 - -@ CHECK: msr cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1] - msr apsr_g, r0 - -@ CHECK: msr cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1] - msr apsr_nzcvq, r0 - -@ CHECK: msr cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] - msr apsr_nzcvqg, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] - msr cpsr_c, r0 - -@ CHECK: msr cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] - msr cpsr_x, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_all, r0 - -@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] - msr cpsr_fsx, r0 - -@ CHECK: msr spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] - msr spsr_fc, r0 - -@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] - msr spsr_fsxc, r0 - -@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] - msr cpsr_fsxc, r0 - @ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] add r1, r2, r3, lsl r4 Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 19 17:45:10 2011 @@ -748,6 +748,70 @@ @------------------------------------------------------------------------------ +@ MSR + at ------------------------------------------------------------------------------ + + msr apsr, #5 + msr apsr_g, #5 + msr apsr_nzcvq, #5 + msr APSR_nzcvq, #5 + msr apsr_nzcvqg, #5 + msr cpsr_fc, #5 + msr cpsr_c, #5 + msr cpsr_x, #5 + msr cpsr_fc, #5 + msr cpsr_all, #5 + msr cpsr_fsx, #5 + msr spsr_fc, #5 + msr SPSR_fsxc, #5 + msr cpsr_fsxc, #5 + +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3] +@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3] +@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] +@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] +@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] + + msr apsr, r0 + msr apsr_g, r0 + msr apsr_nzcvq, r0 + msr APSR_nzcvq, r0 + msr apsr_nzcvqg, r0 + msr cpsr_fc, r0 + msr cpsr_c, r0 + msr cpsr_x, r0 + msr cpsr_fc, r0 + msr cpsr_all, r0 + msr cpsr_fsx, r0 + msr spsr_fc, r0 + msr SPSR_fsxc, r0 + msr cpsr_fsxc, r0 + +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] +@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] +@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] +@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Jul 19 17:45:10 2011 @@ -149,10 +149,10 @@ # CHECK: cpsie if, #10 0xca 0x00 0x0a 0xf1 -# CHECK: msr cpsr_fc, r0 +# CHECK: msr CPSR_fc, r0 0x00 0xf0 0x29 0xe1 -# CHECK: msrmi cpsr_c, #4043309056 +# CHECK: msrmi CPSR_c, #4043309056 0xf1 0xf4 0x21 0x43 # CHECK: rsbs r6, r7, r8 Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=135532&r1=135531&r2=135532&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Jul 19 17:45:10 2011 @@ -131,7 +131,7 @@ # CHECK: cpsie aif 0x67 0xb6 -# CHECK: msr cpsr_fc, r0 +# CHECK: msr CPSR_fc, r0 0x80 0xf3 0x00 0x89 # CHECK: blx #-4 From greened at obbligato.org Tue Jul 19 17:54:28 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 17:54:28 -0500 Subject: [llvm-commits] [PATCH 07/20] [AVX] Unique BitInit In-Reply-To: (David Blaikie's message of "Tue, 19 Jul 2011 14:51:11 -0700") References: Message-ID: David Blaikie writes: >> Urk. ?Forgot about the other reason it has to be function-scope: it >> needs access to the private constructor. ?:) > > Oh, right - well then they could be private class statics if you > wanted to avoid the lazy init. I was told not to do that by someone else. ;) -Dave From greened at obbligato.org Tue Jul 19 17:56:13 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 19 Jul 2011 17:56:13 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: (Eli Friedman's message of "Tue, 19 Jul 2011 15:08:23 -0700") References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: Eli Friedman writes: > On Tue, Jul 19, 2011 at 2:11 PM, David A. Greene wrote: >> Eli Friedman writes: >> >>> On Tue, Jul 19, 2011 at 1:11 PM, David Greene wrote: >>> This is unsafe in general; TableGen might never see the string >>> "<<>>", but you can't assume arbitrary code using this >>> header will not see it. >> >> True, but it's highly unlikely. ?Do you have a better alternative? ?I >> certainly would like to do this the Right Way. > > Use std::map? It's not like performance matters here. Well, Chris suggested using DenseMap with std::string and this is all I could come up with. Originally I used a FoldingSet but several people objected due to performance concerns. So I'm a bit stuck. :( -Dave From benny.kra at googlemail.com Tue Jul 19 17:59:25 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 19 Jul 2011 22:59:25 -0000 Subject: [llvm-commits] [llvm] r135533 - /llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Message-ID: <20110719225925.E773D2A6C12D@llvm.org> Author: d0k Date: Tue Jul 19 17:59:25 2011 New Revision: 135533 URL: http://llvm.org/viewvc/llvm-project?rev=135533&view=rev Log: Fix off-by-one. Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=135533&r1=135532&r2=135533&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Jul 19 17:59:25 2011 @@ -107,7 +107,7 @@ uint64_t getExtent() const { return Bytes.size(); } int readByte(uint64_t Addr, uint8_t *Byte) const { - if (Addr > getExtent()) + if (Addr >= getExtent()) return -1; *Byte = Bytes[Addr]; return 0; From eli.friedman at gmail.com Tue Jul 19 17:59:41 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 19 Jul 2011 22:59:41 -0000 Subject: [llvm-commits] [llvm] r135534 - in /llvm/trunk: lib/Transforms/Utils/BreakCriticalEdges.cpp test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll Message-ID: <20110719225941.C4A062A6C12D@llvm.org> Author: efriedma Date: Tue Jul 19 17:59:41 2011 New Revision: 135534 URL: http://llvm.org/viewvc/llvm-project?rev=135534&view=rev Log: PR10386: Don't try to split an edge from an indirectbr. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=135534&r1=135533&r2=135534&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Tue Jul 19 17:59:41 2011 @@ -337,6 +337,8 @@ } // For each unique exit block... + // FIXME: This code is functionally equivalent to the corresponding + // loop in LoopSimplify. SmallVector ExitBlocks; TIL->getExitBlocks(ExitBlocks); for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) { @@ -348,10 +350,15 @@ for (pred_iterator I = pred_begin(Exit), E = pred_end(Exit); I != E; ++I) { BasicBlock *P = *I; - if (TIL->contains(P)) + if (TIL->contains(P)) { + if (isa(P->getTerminator())) { + Preds.clear(); + break; + } Preds.push_back(P); - else + } else { HasPredOutsideOfLoop = true; + } } // If there are any preds not in the loop, we'll need to split // the edges. The Preds.empty() check is needed because a block Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll?rev=135534&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-19-CritEdgeBreakCrash.ll Tue Jul 19 17:59:41 2011 @@ -0,0 +1,52 @@ +; ModuleID = '' +; RUN: opt < %s -loop-reduce -S | FileCheck %s +; PR10386 + +declare i1 @foo() +declare i8* @bar(i8*,i8*,i8*,i8*) + +define void @f(i64* %a,i64* %b,i64* %c,i64* %d,i64* %e,i64* %f,i64* %g) nounwind uwtable { +entry: + br label %b_throw.preheader + +D_BREAK_LBL: ; preds = %indirectgoto + call i1 @foo() + br label %indirectgoto + +H_CONST_LBL: ; preds = %indirectgoto + call i1 @foo() + br label %body_failed + +H_MPZ_LBL: ; preds = %indirectgoto + %boo3 = call i1 @foo() + br i1 %boo3, label %body_failed, label %while.cond.i + +while.cond.i: ; preds = %while.body.i15795, %if.then.i15791 + %phi = phi i64 [ %tmp20916, %while.body.i15795 ], [ 0, %H_MPZ_LBL ] + %tmp20916 = add i64 %phi, 1 + %incdec.ptr.i15793 = getelementptr i64* %pc.0.lcssa.i1610719352, i64 %tmp20916 + %boo2 = call i1 @foo() + br i1 %boo2, label %indirectgoto, label %while.body.i15795 + +while.body.i15795: ; preds = %while.cond.i + %tmp20.i = load i64* %incdec.ptr.i15793, align 8 + %boo1 = call i1 @foo() + br i1 %boo1, label %while.cond.i, label %body_failed + +b_throw.preheader: ; preds = %body_failed, %entry + call i1 @foo() + br label %indirectgoto + +body_failed: + %pc.0.lcssa.i1610719364 = phi i64* [ %pc.0.lcssa.i1610719352, %indirectgoto ], [ %pc.0.lcssa.i1610719352, %H_MPZ_LBL ], [ %b, %H_CONST_LBL ], [ %pc.0.lcssa.i1610719352, %while.body.i15795 ] + call i1 @foo() + br label %b_throw.preheader + +indirectgoto: + %pc.0.lcssa.i1610719352 = phi i64* [ %pc.0.lcssa.i1610719352, %D_BREAK_LBL ], [ %a, %b_throw.preheader ], [ %d, %while.cond.i ] + %p = call i8* @bar(i8* blockaddress(@f, %D_BREAK_LBL), i8* blockaddress(@f, %H_CONST_LBL), i8* blockaddress(@f, %H_MPZ_LBL), i8* blockaddress(@f, %body_failed) ) + indirectbr i8* %p, [label %D_BREAK_LBL, label %H_CONST_LBL, label %H_MPZ_LBL, label %body_failed] +} + +; CHECK: %p = call i8* @bar(i8* blockaddress(@f, %D_BREAK_LBL), i8* blockaddress(@f, %H_CONST_LBL), i8* blockaddress(@f, %H_MPZ_LBL), i8* blockaddress(@f, %body_failed)) +; CHECK: indirectbr i8* %p, [label %D_BREAK_LBL, label %H_CONST_LBL, label %H_MPZ_LBL, label %body_failed] From evan.cheng at apple.com Tue Jul 19 18:14:32 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 19 Jul 2011 23:14:32 -0000 Subject: [llvm-commits] [llvm] r135535 - in /llvm/trunk: lib/CodeGen/TargetLoweringObjectFileImpl.cpp test/CodeGen/X86/global-sections.ll Message-ID: <20110719231432.40B5B2A6C12D@llvm.org> Author: evancheng Date: Tue Jul 19 18:14:32 2011 New Revision: 135535 URL: http://llvm.org/viewvc/llvm-project?rev=135535&view=rev Log: Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/test/CodeGen/X86/global-sections.ll Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=135535&r1=135534&r2=135535&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jul 19 18:14:32 2011 @@ -574,7 +574,7 @@ // to using it in -static mode. SixteenByteConstantSection = 0; if (TM.getRelocationModel() != Reloc::Static && - TM.getTargetData()->getPointerSize() == 32) + TM.getTargetData()->getPointerSizeInBits() == 32) SixteenByteConstantSection = // .literal16 getContext().getMachOSection("__TEXT", "__literal16", MCSectionMachO::S_16BYTE_LITERALS, Modified: llvm/trunk/test/CodeGen/X86/global-sections.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/global-sections.ll?rev=135535&r1=135534&r2=135535&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/global-sections.ll (original) +++ llvm/trunk/test/CodeGen/X86/global-sections.ll Tue Jul 19 18:14:32 2011 @@ -43,7 +43,7 @@ ; _Complex long long const G4 = 34; @G4 = unnamed_addr constant {i64,i64} { i64 34, i64 0 } -; DARWIN: .section __TEXT,__const +; DARWIN: .section __TEXT,__literal16,16byte_literals ; DARWIN: _G4: ; DARWIN: .long 34 From geek4civic at gmail.com Tue Jul 19 18:18:53 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 20 Jul 2011 08:18:53 +0900 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: Good morning, Jakob. 2011/7/19 Jakob Stoklund Olesen : > There are many ways of doing things with Git, and I am sure yours works well, but we should keep the instructions as simple as possible. > > I think Jeffrey's notes are sufficient. People can add their own tricks depending on their git-fu. We should just provide the basics a newbie needs. I don't think using "git-svn rebase -l" would be simple. git-svn stuff should be used to interact to svn repo. It would be enough "git pull" instead of "git fetch origin; git svn rebase -l". (.rev_map is not needed to be up-to-date unless git-svn command would be used) At committing, git-svn rebase could be used. $ git svn rebase -l $ git svn dcommit Also git-svn dcommit can update .rev_map, We can use "git pull --rebase" instead of "git svn rebase -l". BTW, setting up authorsfile might be pain, but it should reduce accidental undesirable committing by git-svn fetch. (Please consider, what would happen if "-l" were missed on executing "git-svn rebase"?) Happy hacking! ...Takumi From ahatanak at gmail.com Tue Jul 19 18:30:50 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 19 Jul 2011 23:30:50 -0000 Subject: [llvm-commits] [llvm] r135537 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/atomic.ll Message-ID: <20110719233050.A2F072A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 18:30:50 2011 New Revision: 135537 URL: http://llvm.org/viewvc/llvm-project?rev=135537&view=rev Log: Lower memory barriers to sync instructions. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135537&r1=135536&r2=135537&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 19 18:30:50 2011 @@ -61,6 +61,7 @@ case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; + case MipsISD::Sync: return "MipsISD::Sync"; default: return NULL; } } @@ -159,7 +160,7 @@ // Use the default for now setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); if (Subtarget->isSingleFloat()) setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); @@ -527,6 +528,7 @@ case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); + case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); } return SDValue(); } @@ -1525,6 +1527,15 @@ return FrameAddr; } +// TODO: set SType according to the desired memory barrier behavior. +SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, + SelectionDAG& DAG) const { + unsigned SType = 0; + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), + DAG.getConstant(SType, MVT::i32)); +} + //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=135537&r1=135536&r2=135537&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Jul 19 18:30:50 2011 @@ -81,7 +81,9 @@ WrapperPIC, - DynAlloc + DynAlloc, + + Sync }; } @@ -128,6 +130,7 @@ SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; virtual SDValue LowerFormalArguments(SDValue Chain, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=135537&r1=135536&r2=135537&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jul 19 18:30:50 2011 @@ -41,6 +41,7 @@ def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, iPTR>]>; +def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; // Call def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, @@ -106,6 +107,8 @@ def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, [SDNPHasChain, SDNPInGlue]>; +def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>; + //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// @@ -589,6 +592,15 @@ def SH : StoreM<0x29, "sh", truncstorei16>; def SW : StoreM<0x2b, "sw", store>; +let hasSideEffects = 1 in +def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", + [(MipsSync imm:$stype)], NoItinerary> +{ + let opcode = 0; + let Inst{25-11} = 0; + let Inst{5-0} = 15; +} + /// Load-linked, Store-conditional let mayLoad = 1, hasDelaySlot = 1 in def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr), Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135537&r1=135536&r2=135537&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Tue Jul 19 18:30:50 2011 @@ -12,6 +12,7 @@ declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind @x = common global i32 0, align 4 @@ -239,3 +240,21 @@ ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } + + at countsint = common global i32 0, align 4 + +define i32 @CheckSync(i32 %v) nounwind noinline { +entry: + tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* @countsint, i32 %v) + tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret i32 %0 + +; CHECK: CheckSync: +; CHECK: sync 0 +; CHECK: ll +; CHECK: sc +; CHECK: beq +; CHECK: sync 0 +} + From isanbard at gmail.com Tue Jul 19 18:33:42 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 19 Jul 2011 23:33:42 -0000 Subject: [llvm-commits] [llvm] r135538 - /llvm/trunk/runtime/libprofile/Makefile Message-ID: <20110719233342.CEEB42A6C12D@llvm.org> Author: void Date: Tue Jul 19 18:33:42 2011 New Revision: 135538 URL: http://llvm.org/viewvc/llvm-project?rev=135538&view=rev Log: Build and install the archive when building the Apple way. Modified: llvm/trunk/runtime/libprofile/Makefile Modified: llvm/trunk/runtime/libprofile/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/Makefile?rev=135538&r1=135537&r2=135538&view=diff ============================================================================== --- llvm/trunk/runtime/libprofile/Makefile (original) +++ llvm/trunk/runtime/libprofile/Makefile Tue Jul 19 18:33:42 2011 @@ -19,6 +19,10 @@ EXTRA_DIST = libprofile.exports EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/libprofile.exports +# Build and install this archive. +BUILD_ARCHIVE = 1 +override NO_INSTALL_ARCHIVES = + include $(LEVEL)/Makefile.common ifeq ($(HOST_OS),Darwin) From ahatanak at gmail.com Tue Jul 19 19:23:01 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 20 Jul 2011 00:23:01 -0000 Subject: [llvm-commits] [llvm] r135546 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20110720002301.614852A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 19:23:01 2011 New Revision: 135546 URL: http://llvm.org/viewvc/llvm-project?rev=135546&view=rev Log: Define classes for definitions of atomic instructions. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=135546&r1=135545&r2=135546&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jul 19 19:23:01 2011 @@ -396,6 +396,22 @@ let shamt = 0; } +// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). +class Atomic2 : + MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), + [(set CPURegs:$dst, + (Op CPURegs:$ptr, CPURegs:$incr))]>; + +// Atomic Compare & Swap. +class AtomicCmpSwap : + MipsPseudo<(outs CPURegs:$dst), + (ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap), + !strconcat("atomic_cmp_swap_", Width, + "\t$dst, $ptr, $cmp, $swap"), + [(set CPURegs:$dst, + (Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>; + //===----------------------------------------------------------------------===// // Pseudo instructions //===----------------------------------------------------------------------===// @@ -430,112 +446,32 @@ def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>; let usesCustomInserter = 1 in { - def ATOMIC_LOAD_ADD_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_add_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_add_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_ADD_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_add_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_add_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_ADD_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_add_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_add_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_LOAD_SUB_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_sub_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_sub_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_SUB_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_sub_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_sub_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_SUB_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_sub_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_sub_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_LOAD_AND_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_and_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_and_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_AND_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_and_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_and_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_AND_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_and_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_and_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_LOAD_OR_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_or_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_or_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_OR_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_or_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_or_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_OR_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_or_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_or_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_LOAD_XOR_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_xor_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_xor_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_XOR_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_xor_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_xor_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_XOR_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_xor_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_xor_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_LOAD_NAND_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_nand_8\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_nand_8 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_NAND_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_nand_16\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_nand_16 CPURegs:$ptr, CPURegs:$incr))]>; - def ATOMIC_LOAD_NAND_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), - "atomic_load_nand_32\t$dst, $ptr, $incr", - [(set CPURegs:$dst, (atomic_load_nand_32 CPURegs:$ptr, CPURegs:$incr))]>; - - def ATOMIC_SWAP_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), - "atomic_swap_8\t$dst, $ptr, $val", - [(set CPURegs:$dst, (atomic_swap_8 CPURegs:$ptr, CPURegs:$val))]>; - def ATOMIC_SWAP_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), - "atomic_swap_16\t$dst, $ptr, $val", - [(set CPURegs:$dst, (atomic_swap_16 CPURegs:$ptr, CPURegs:$val))]>; - def ATOMIC_SWAP_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), - "atomic_swap_32\t$dst, $ptr, $val", - [(set CPURegs:$dst, (atomic_swap_32 CPURegs:$ptr, CPURegs:$val))]>; - - def ATOMIC_CMP_SWAP_I8 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), - "atomic_cmp_swap_8\t$dst, $ptr, $oldval, $newval", - [(set CPURegs:$dst, - (atomic_cmp_swap_8 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; - def ATOMIC_CMP_SWAP_I16 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), - "atomic_cmp_swap_16\t$dst, $ptr, $oldval, $newval", - [(set CPURegs:$dst, - (atomic_cmp_swap_16 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; - def ATOMIC_CMP_SWAP_I32 : MipsPseudo< - (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), - "atomic_cmp_swap_32\t$dst, $ptr, $oldval, $newval", - [(set CPURegs:$dst, - (atomic_cmp_swap_32 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; + def ATOMIC_LOAD_ADD_I8 : Atomic2; + def ATOMIC_LOAD_ADD_I16 : Atomic2; + def ATOMIC_LOAD_ADD_I32 : Atomic2; + def ATOMIC_LOAD_SUB_I8 : Atomic2; + def ATOMIC_LOAD_SUB_I16 : Atomic2; + def ATOMIC_LOAD_SUB_I32 : Atomic2; + def ATOMIC_LOAD_AND_I8 : Atomic2; + def ATOMIC_LOAD_AND_I16 : Atomic2; + def ATOMIC_LOAD_AND_I32 : Atomic2; + def ATOMIC_LOAD_OR_I8 : Atomic2; + def ATOMIC_LOAD_OR_I16 : Atomic2; + def ATOMIC_LOAD_OR_I32 : Atomic2; + def ATOMIC_LOAD_XOR_I8 : Atomic2; + def ATOMIC_LOAD_XOR_I16 : Atomic2; + def ATOMIC_LOAD_XOR_I32 : Atomic2; + def ATOMIC_LOAD_NAND_I8 : Atomic2; + def ATOMIC_LOAD_NAND_I16 : Atomic2; + def ATOMIC_LOAD_NAND_I32 : Atomic2; + + def ATOMIC_SWAP_I8 : Atomic2; + def ATOMIC_SWAP_I16 : Atomic2; + def ATOMIC_SWAP_I32 : Atomic2; + + def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap; + def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap; + def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap; } //===----------------------------------------------------------------------===// From ahatanak at gmail.com Tue Jul 19 19:53:09 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 20 Jul 2011 00:53:09 -0000 Subject: [llvm-commits] [llvm] r135550 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20110720005309.9C5FD2A6C12D@llvm.org> Author: ahatanak Date: Tue Jul 19 19:53:09 2011 New Revision: 135550 URL: http://llvm.org/viewvc/llvm-project?rev=135550&view=rev Log: Change name of class. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=135550&r1=135549&r2=135550&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jul 19 19:53:09 2011 @@ -397,7 +397,7 @@ } // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). -class Atomic2 : +class Atomic2Ops : MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), [(set CPURegs:$dst, @@ -446,28 +446,28 @@ def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>; let usesCustomInserter = 1 in { - def ATOMIC_LOAD_ADD_I8 : Atomic2; - def ATOMIC_LOAD_ADD_I16 : Atomic2; - def ATOMIC_LOAD_ADD_I32 : Atomic2; - def ATOMIC_LOAD_SUB_I8 : Atomic2; - def ATOMIC_LOAD_SUB_I16 : Atomic2; - def ATOMIC_LOAD_SUB_I32 : Atomic2; - def ATOMIC_LOAD_AND_I8 : Atomic2; - def ATOMIC_LOAD_AND_I16 : Atomic2; - def ATOMIC_LOAD_AND_I32 : Atomic2; - def ATOMIC_LOAD_OR_I8 : Atomic2; - def ATOMIC_LOAD_OR_I16 : Atomic2; - def ATOMIC_LOAD_OR_I32 : Atomic2; - def ATOMIC_LOAD_XOR_I8 : Atomic2; - def ATOMIC_LOAD_XOR_I16 : Atomic2; - def ATOMIC_LOAD_XOR_I32 : Atomic2; - def ATOMIC_LOAD_NAND_I8 : Atomic2; - def ATOMIC_LOAD_NAND_I16 : Atomic2; - def ATOMIC_LOAD_NAND_I32 : Atomic2; - - def ATOMIC_SWAP_I8 : Atomic2; - def ATOMIC_SWAP_I16 : Atomic2; - def ATOMIC_SWAP_I32 : Atomic2; + def ATOMIC_LOAD_ADD_I8 : Atomic2Ops; + def ATOMIC_LOAD_ADD_I16 : Atomic2Ops; + def ATOMIC_LOAD_ADD_I32 : Atomic2Ops; + def ATOMIC_LOAD_SUB_I8 : Atomic2Ops; + def ATOMIC_LOAD_SUB_I16 : Atomic2Ops; + def ATOMIC_LOAD_SUB_I32 : Atomic2Ops; + def ATOMIC_LOAD_AND_I8 : Atomic2Ops; + def ATOMIC_LOAD_AND_I16 : Atomic2Ops; + def ATOMIC_LOAD_AND_I32 : Atomic2Ops; + def ATOMIC_LOAD_OR_I8 : Atomic2Ops; + def ATOMIC_LOAD_OR_I16 : Atomic2Ops; + def ATOMIC_LOAD_OR_I32 : Atomic2Ops; + def ATOMIC_LOAD_XOR_I8 : Atomic2Ops; + def ATOMIC_LOAD_XOR_I16 : Atomic2Ops; + def ATOMIC_LOAD_XOR_I32 : Atomic2Ops; + def ATOMIC_LOAD_NAND_I8 : Atomic2Ops; + def ATOMIC_LOAD_NAND_I16 : Atomic2Ops; + def ATOMIC_LOAD_NAND_I32 : Atomic2Ops; + + def ATOMIC_SWAP_I8 : Atomic2Ops; + def ATOMIC_SWAP_I16 : Atomic2Ops; + def ATOMIC_SWAP_I32 : Atomic2Ops; def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap; def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap; From benny.kra at googlemail.com Tue Jul 19 20:27:59 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 20 Jul 2011 01:27:59 -0000 Subject: [llvm-commits] [llvm] r135555 - /llvm/trunk/lib/Target/TargetMachine.cpp Message-ID: <20110720012759.10D262A6C12D@llvm.org> Author: d0k Date: Tue Jul 19 20:27:58 2011 New Revision: 135555 URL: http://llvm.org/viewvc/llvm-project?rev=135555&view=rev Log: Don't leak CodeGenInfos. Modified: llvm/trunk/lib/Target/TargetMachine.cpp Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=135555&r1=135554&r2=135555&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Tue Jul 19 20:27:58 2011 @@ -202,7 +202,8 @@ TargetMachine::TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS) - : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0), + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), + CodeGenInfo(0), AsmInfo(0), MCRelaxAll(false), MCNoExecStack(false), MCSaveTempLabels(false), @@ -215,6 +216,7 @@ } TargetMachine::~TargetMachine() { + delete CodeGenInfo; delete AsmInfo; } From clattner at apple.com Tue Jul 19 21:08:54 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 19 Jul 2011 19:08:54 -0700 Subject: [llvm-commits] [llvm] r135342 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c In-Reply-To: <56D1490B-E531-4904-8BD7-881C8A02D857@apple.com> References: <20110716072835.BDAC72A6C12C@llvm.org> <219B41AE-4EC9-45A6-8014-E52311FD278A@apple.com> <04584A21-9481-4179-AB3D-B2E4A8D53123@apple.com> <443EBCCB-7E7F-4CA4-9924-043099FDFFAD@apple.com> <52725BD3-8C7A-41CE-98C1-B1A4FA90FC5E@apple.com> <56D1490B-E531-4904-8BD7-881C8A02D857@apple.com> Message-ID: <0169808D-6F76-4047-8E4F-248D1CA56222@apple.com> On Jul 19, 2011, at 2:26 PM, Eric Christopher wrote: >> The Frontend* tests? Totally. A few of them will need to be changed for the different codegen, but that's not a problem and will make running "make check" for llvm way less annoying. > > FWIW I'm doing this now. I'm removing (not migrating) the tests that seem to test gcc front end things instead of clang front end things or where I'm positive we have a clang test already. Fantastic, thanks a lot Eric! -Chris From atrick at apple.com Tue Jul 19 21:08:58 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 20 Jul 2011 02:08:58 -0000 Subject: [llvm-commits] [llvm] r135558 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110720020858.BF9092A6C12D@llvm.org> Author: atrick Date: Tue Jul 19 21:08:58 2011 New Revision: 135558 URL: http://llvm.org/viewvc/llvm-project?rev=135558&view=rev Log: indvars -disable-iv-rewrite fix: derived GEP IVs Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135558&r1=135557&r2=135558&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jul 19 21:08:58 2011 @@ -1419,6 +1419,11 @@ if (Inserted) continue; PHINode *OrigPhi = Pos->second; + + // If one phi derives from the other via GEPs, types may differ. + if (OrigPhi->getType() != Phi->getType()) + continue; + // Replacing the congruent phi is sufficient because acyclic redundancy // elimination, CSE/GVN, should handle the rest. However, once SCEV proves // that a phi is congruent, it's almost certain to be the head of an IV @@ -1430,6 +1435,7 @@ Instruction *IsomorphicInc = cast(Phi->getIncomingValueForBlock(LatchBlock)); if (OrigInc != IsomorphicInc && + OrigInc->getType() == IsomorphicInc->getType() && SE->getSCEV(OrigInc) == SE->getSCEV(IsomorphicInc) && HoistStep(OrigInc, IsomorphicInc, DT)) { DEBUG(dbgs() << "INDVARS: Eliminated congruent iv.inc: " Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=135558&r1=135557&r2=135558&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Tue Jul 19 21:08:58 2011 @@ -125,9 +125,9 @@ ret void } -%struct = type { i32 } +%structI = type { i32 } -define void @bitcastiv(i32 %start, i32 %limit, i32 %step, %struct* %base) +define void @bitcastiv(i32 %start, i32 %limit, i32 %step, %structI* %base) nounwind { entry: @@ -142,12 +142,12 @@ ; CHECK: exit: loop: %iv = phi i32 [%start, %entry], [%next, %loop] - %p = phi %struct* [%base, %entry], [%pinc, %loop] - %adr = getelementptr %struct* %p, i32 0, i32 0 + %p = phi %structI* [%base, %entry], [%pinc, %loop] + %adr = getelementptr %structI* %p, i32 0, i32 0 store i32 3, i32* %adr - %pp = bitcast %struct* %p to i32* + %pp = bitcast %structI* %p to i32* store i32 4, i32* %pp - %pinc = getelementptr %struct* %p, i32 1 + %pinc = getelementptr %structI* %p, i32 1 %next = add i32 %iv, 1 %cond = icmp ne i32 %next, %limit br i1 %cond, label %loop, label %exit @@ -320,3 +320,26 @@ %sum4 = add i32 %sum1, %l.next ret i32 %sum4 } + +; Test a GEP IV that is derived from another GEP IV by a nop gep that +; lowers the type without changing the expression. +%structIF = type { i32, float } + +define void @congruentgepiv(%structIF* %base) nounwind uwtable ssp { +entry: + %first = getelementptr inbounds %structIF* %base, i64 0, i32 0 + br label %loop + +loop: + %ptr.iv = phi %structIF* [ %ptr.inc, %latch ], [ %base, %entry ] + %next = phi i32* [ %next.inc, %latch ], [ %first, %entry ] + br i1 undef, label %latch, label %exit + +latch: ; preds = %for.inc50.i + %ptr.inc = getelementptr inbounds %structIF* %ptr.iv, i64 1 + %next.inc = getelementptr inbounds %structIF* %ptr.inc, i64 0, i32 0 + br label %loop + +exit: + ret void +} From atrick at apple.com Tue Jul 19 21:14:37 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 20 Jul 2011 02:14:37 -0000 Subject: [llvm-commits] [llvm] r135559 - /llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110720021437.971AE2A6C12D@llvm.org> Author: atrick Date: Tue Jul 19 21:14:37 2011 New Revision: 135559 URL: http://llvm.org/viewvc/llvm-project?rev=135559&view=rev Log: indvars test case for r135558. Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=135559&r1=135558&r2=135559&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Tue Jul 19 21:14:37 2011 @@ -330,9 +330,16 @@ %first = getelementptr inbounds %structIF* %base, i64 0, i32 0 br label %loop +; CHECK: loop: +; CHECK: phi %structIF* +; CHECK: phi i32* +; CHECK: getelementptr inbounds +; CHECK: getelementptr inbounds +; CHECK: exit: loop: %ptr.iv = phi %structIF* [ %ptr.inc, %latch ], [ %base, %entry ] %next = phi i32* [ %next.inc, %latch ], [ %first, %entry ] + store i32 4, i32* %next br i1 undef, label %latch, label %exit latch: ; preds = %for.inc50.i From echristo at apple.com Tue Jul 19 21:44:39 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 20 Jul 2011 02:44:39 -0000 Subject: [llvm-commits] [llvm] r135561 - /llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h Message-ID: <20110720024439.DEBD32A6C12D@llvm.org> Author: echristo Date: Tue Jul 19 21:44:39 2011 New Revision: 135561 URL: http://llvm.org/viewvc/llvm-project?rev=135561&view=rev Log: Extra semi-colon. Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h?rev=135561&r1=135560&r2=135561&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h (original) +++ llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h Tue Jul 19 21:44:39 2011 @@ -143,7 +143,7 @@ bool isCompatibleFormat(const MemoryBuffer *InputBuffer) const { return isKnownFormat(InputBuffer); - }; + } }; } // end namespace llvm From echristo at apple.com Tue Jul 19 22:09:11 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 20 Jul 2011 03:09:11 -0000 Subject: [llvm-commits] [llvm] r135562 - /llvm/trunk/test/CodeGen/X86/ptr-rotate.ll Message-ID: <20110720030911.78DA92A6C12D@llvm.org> Author: echristo Date: Tue Jul 19 22:09:11 2011 New Revision: 135562 URL: http://llvm.org/viewvc/llvm-project?rev=135562&view=rev Log: New pointer rotate test. Added: llvm/trunk/test/CodeGen/X86/ptr-rotate.ll Added: llvm/trunk/test/CodeGen/X86/ptr-rotate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ptr-rotate.ll?rev=135562&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/ptr-rotate.ll (added) +++ llvm/trunk/test/CodeGen/X86/ptr-rotate.ll Tue Jul 19 22:09:11 2011 @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=i386-apple-darwin -o - < %s | FileCheck %s + +define i32 @func(i8* %A) nounwind readnone { +entry: + %tmp = ptrtoint i8* %A to i32 + %shr = lshr i32 %tmp, 5 + %shl = shl i32 %tmp, 27 + %or = or i32 %shr, %shl +; CHECK: roll $27 + ret i32 %or +} From rafael.espindola at gmail.com Tue Jul 19 22:56:54 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 19 Jul 2011 23:56:54 -0400 Subject: [llvm-commits] [patch] Add a pass for duplicating indirectbr at the IL level Message-ID: <4E265206.6040205@gmail.com> The attached patch adds a pass for duplicating indirectbr at the IL level. The motivation is to get better instruction selection. For example, with the current MI based duplication, we get leaq table(,%r11,8), %r8 jmpq *(%r8) with this patch we get jmpq *table(,%r11,8) The pass is mostly the current CodeGen TailDuplication with ideas taken from the old IL TailDuplication (it looks like this one is unused, should it be deleted?). With this patch in we can probably remove the bias for duplicating indirectbr in CodeGen. The two main points I would like a review are the two fixmes in the code: What it is the best place to factor the "isDefLiveOut" function and if SSAUpdate should be extended to handle the case mentioned by the other FIXME. Thanks, Rafael -------------- next part -------------- A non-text attachment was scrubbed... Name: indirectbr.patch Type: text/x-patch Size: 24460 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110719/55f7674c/attachment-0001.bin From geek4civic at gmail.com Tue Jul 19 23:02:21 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 20 Jul 2011 04:02:21 -0000 Subject: [llvm-commits] [llvm] r135564 - /llvm/trunk/lib/Target/X86/X86Subtarget.h Message-ID: <20110720040221.1355E2A6C12D@llvm.org> Author: chapuni Date: Tue Jul 19 23:02:20 2011 New Revision: 135564 URL: http://llvm.org/viewvc/llvm-project?rev=135564&view=rev Log: X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=135564&r1=135563&r2=135564&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Tue Jul 19 23:02:20 2011 @@ -199,7 +199,8 @@ } bool isTargetWin64() const { - return In64BitMode && (isTargetMingw() || isTargetWindows()); + // FIXME: x86_64-cygwin has not been released yet. + return In64BitMode && (isTargetCygMing() || isTargetWindows()); } bool isTargetEnvMacho() const { From atrick at apple.com Tue Jul 19 23:39:24 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 20 Jul 2011 04:39:24 -0000 Subject: [llvm-commits] [llvm] r135566 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110720043924.6A24D2A6C12D@llvm.org> Author: atrick Date: Tue Jul 19 23:39:24 2011 New Revision: 135566 URL: http://llvm.org/viewvc/llvm-project?rev=135566&view=rev Log: indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use info. Holding Use* pointers is bad form even though it happened to work in this case. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135566&r1=135565&r2=135566&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jul 19 23:39:24 2011 @@ -784,6 +784,21 @@ } namespace { + +/// NarrowIVDefUse - Record a link in the Narrow IV def-use chain along with the +/// WideIV that computes the same value as the Narrow IV def. This avoids +/// caching Use* pointers. +struct NarrowIVDefUse { + Instruction *NarrowDef; + Instruction *NarrowUse; + Instruction *WideDef; + + NarrowIVDefUse(): NarrowDef(0), NarrowUse(0), WideDef(0) {} + + NarrowIVDefUse(Instruction *ND, Instruction *NU, Instruction *WD): + NarrowDef(ND), NarrowUse(NU), WideDef(WD) {} +}; + /// WidenIV - The goal of this transform is to remove sign and zero extends /// without creating any new induction variables. To do this, it creates a new /// phi of the wider type and redirects all users, either removing extends or @@ -808,7 +823,7 @@ SmallVectorImpl &DeadInsts; SmallPtrSet Widened; - SmallVector, 8> NarrowIVUsers; + SmallVector NarrowIVUsers; public: WidenIV(PHINode *PN, const WideIVInfo &WI, LoopInfo *LInfo, @@ -831,14 +846,11 @@ PHINode *CreateWideIV(SCEVExpander &Rewriter); protected: - Instruction *CloneIVUser(Instruction *NarrowUse, - Instruction *NarrowDef, - Instruction *WideDef); + Instruction *CloneIVUser(NarrowIVDefUse DU); const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); - Instruction *WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, - Instruction *WideDef); + Instruction *WidenIVUse(NarrowIVDefUse DU); void pushNarrowIVUsers(Instruction *NarrowDef, Instruction *WideDef); }; @@ -853,10 +865,8 @@ /// CloneIVUser - Instantiate a wide operation to replace a narrow /// operation. This only needs to handle operations that can evaluation to /// SCEVAddRec. It can safely return 0 for any operation we decide not to clone. -Instruction *WidenIV::CloneIVUser(Instruction *NarrowUse, - Instruction *NarrowDef, - Instruction *WideDef) { - unsigned Opcode = NarrowUse->getOpcode(); +Instruction *WidenIV::CloneIVUser(NarrowIVDefUse DU) { + unsigned Opcode = DU.NarrowUse->getOpcode(); switch (Opcode) { default: return 0; @@ -870,21 +880,21 @@ case Instruction::Shl: case Instruction::LShr: case Instruction::AShr: - DEBUG(dbgs() << "Cloning IVUser: " << *NarrowUse << "\n"); + DEBUG(dbgs() << "Cloning IVUser: " << *DU.NarrowUse << "\n"); - IRBuilder<> Builder(NarrowUse); + IRBuilder<> Builder(DU.NarrowUse); // Replace NarrowDef operands with WideDef. Otherwise, we don't know // anything about the narrow operand yet so must insert a [sz]ext. It is // probably loop invariant and will be folded or hoisted. If it actually // comes from a widened IV, it should be removed during a future call to // WidenIVUse. - Value *LHS = (NarrowUse->getOperand(0) == NarrowDef) ? WideDef : - getExtend(NarrowUse->getOperand(0), WideType, IsSigned, Builder); - Value *RHS = (NarrowUse->getOperand(1) == NarrowDef) ? WideDef : - getExtend(NarrowUse->getOperand(1), WideType, IsSigned, Builder); + Value *LHS = (DU.NarrowUse->getOperand(0) == DU.NarrowDef) ? DU.WideDef : + getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, Builder); + Value *RHS = (DU.NarrowUse->getOperand(1) == DU.NarrowDef) ? DU.WideDef : + getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, Builder); - BinaryOperator *NarrowBO = cast(NarrowUse); + BinaryOperator *NarrowBO = cast(DU.NarrowUse); BinaryOperator *WideBO = BinaryOperator::Create(NarrowBO->getOpcode(), LHS, RHS, NarrowBO->getName()); @@ -962,41 +972,40 @@ /// WidenIVUse - Determine whether an individual user of the narrow IV can be /// widened. If so, return the wide clone of the user. -Instruction *WidenIV::WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, - Instruction *WideDef) { - Instruction *NarrowUse = cast(NarrowDefUse.getUser()); +Instruction *WidenIV::WidenIVUse(NarrowIVDefUse DU) { // Stop traversing the def-use chain at inner-loop phis or post-loop phis. - if (isa(NarrowUse) && LI->getLoopFor(NarrowUse->getParent()) != L) + if (isa(DU.NarrowUse) && + LI->getLoopFor(DU.NarrowUse->getParent()) != L) return 0; // Our raison d'etre! Eliminate sign and zero extension. - if (IsSigned ? isa(NarrowUse) : isa(NarrowUse)) { - Value *NewDef = WideDef; - if (NarrowUse->getType() != WideType) { - unsigned CastWidth = SE->getTypeSizeInBits(NarrowUse->getType()); + if (IsSigned ? isa(DU.NarrowUse) : isa(DU.NarrowUse)) { + Value *NewDef = DU.WideDef; + if (DU.NarrowUse->getType() != WideType) { + unsigned CastWidth = SE->getTypeSizeInBits(DU.NarrowUse->getType()); unsigned IVWidth = SE->getTypeSizeInBits(WideType); if (CastWidth < IVWidth) { // The cast isn't as wide as the IV, so insert a Trunc. - IRBuilder<> Builder(NarrowDefUse); - NewDef = Builder.CreateTrunc(WideDef, NarrowUse->getType()); + IRBuilder<> Builder(DU.NarrowUse); + NewDef = Builder.CreateTrunc(DU.WideDef, DU.NarrowUse->getType()); } else { // A wider extend was hidden behind a narrower one. This may induce // another round of IV widening in which the intermediate IV becomes // dead. It should be very rare. DEBUG(dbgs() << "INDVARS: New IV " << *WidePhi - << " not wide enough to subsume " << *NarrowUse << "\n"); - NarrowUse->replaceUsesOfWith(NarrowDef, WideDef); - NewDef = NarrowUse; + << " not wide enough to subsume " << *DU.NarrowUse << "\n"); + DU.NarrowUse->replaceUsesOfWith(DU.NarrowDef, DU.WideDef); + NewDef = DU.NarrowUse; } } - if (NewDef != NarrowUse) { - DEBUG(dbgs() << "INDVARS: eliminating " << *NarrowUse - << " replaced by " << *WideDef << "\n"); + if (NewDef != DU.NarrowUse) { + DEBUG(dbgs() << "INDVARS: eliminating " << *DU.NarrowUse + << " replaced by " << *DU.WideDef << "\n"); ++NumElimExt; - NarrowUse->replaceAllUsesWith(NewDef); - DeadInsts.push_back(NarrowUse); + DU.NarrowUse->replaceAllUsesWith(NewDef); + DeadInsts.push_back(DU.NarrowUse); } // Now that the extend is gone, we want to expose it's uses for potential // further simplification. We don't need to directly inform SimplifyIVUsers @@ -1009,29 +1018,31 @@ } // Does this user itself evaluate to a recurrence after widening? - const SCEVAddRecExpr *WideAddRec = GetWideRecurrence(NarrowUse); + const SCEVAddRecExpr *WideAddRec = GetWideRecurrence(DU.NarrowUse); if (!WideAddRec) { // This user does not evaluate to a recurence after widening, so don't // follow it. Instead insert a Trunc to kill off the original use, // eventually isolating the original narrow IV so it can be removed. - IRBuilder<> Builder(NarrowDefUse); - Value *Trunc = Builder.CreateTrunc(WideDef, NarrowDef->getType()); - NarrowUse->replaceUsesOfWith(NarrowDef, Trunc); + Use *U = std::find(DU.NarrowUse->op_begin(), DU.NarrowUse->op_end(), + DU.NarrowDef); + IRBuilder<> Builder(*U); + Value *Trunc = Builder.CreateTrunc(DU.WideDef, DU.NarrowDef->getType()); + DU.NarrowUse->replaceUsesOfWith(DU.NarrowDef, Trunc); return 0; } // Assume block terminators cannot evaluate to a recurrence. We can't to // insert a Trunc after a terminator if there happens to be a critical edge. - assert(NarrowUse != NarrowUse->getParent()->getTerminator() && + assert(DU.NarrowUse != DU.NarrowUse->getParent()->getTerminator() && "SCEV is not expected to evaluate a block terminator"); // Reuse the IV increment that SCEVExpander created as long as it dominates // NarrowUse. Instruction *WideUse = 0; - if (WideAddRec == WideIncExpr && HoistStep(WideInc, NarrowUse, DT)) { + if (WideAddRec == WideIncExpr && HoistStep(WideInc, DU.NarrowUse, DT)) { WideUse = WideInc; } else { - WideUse = CloneIVUser(NarrowUse, NarrowDef, WideDef); + WideUse = CloneIVUser(DU); if (!WideUse) return 0; } @@ -1056,13 +1067,13 @@ void WidenIV::pushNarrowIVUsers(Instruction *NarrowDef, Instruction *WideDef) { for (Value::use_iterator UI = NarrowDef->use_begin(), UE = NarrowDef->use_end(); UI != UE; ++UI) { - Use &U = UI.getUse(); + Instruction *NarrowUse = cast(*UI); // Handle data flow merges and bizarre phi cycles. - if (!Widened.insert(cast(U.getUser()))) + if (!Widened.insert(NarrowUse)) continue; - NarrowIVUsers.push_back(std::make_pair(&UI.getUse(), WideDef)); + NarrowIVUsers.push_back(NarrowIVDefUse(NarrowDef, NarrowUse, WideDef)); } } @@ -1129,23 +1140,19 @@ pushNarrowIVUsers(OrigPhi, WidePhi); while (!NarrowIVUsers.empty()) { - Use *UsePtr; - Instruction *WideDef; - tie(UsePtr, WideDef) = NarrowIVUsers.pop_back_val(); - Use &NarrowDefUse = *UsePtr; + NarrowIVDefUse DU = NarrowIVUsers.pop_back_val(); // Process a def-use edge. This may replace the use, so don't hold a // use_iterator across it. - Instruction *NarrowDef = cast(NarrowDefUse.get()); - Instruction *WideUse = WidenIVUse(NarrowDefUse, NarrowDef, WideDef); + Instruction *WideUse = WidenIVUse(DU); // Follow all def-use edges from the previous narrow use. if (WideUse) - pushNarrowIVUsers(cast(NarrowDefUse.getUser()), WideUse); + pushNarrowIVUsers(DU.NarrowUse, WideUse); // WidenIVUse may have removed the def-use edge. - if (NarrowDef->use_empty()) - DeadInsts.push_back(NarrowDef); + if (DU.NarrowDef->use_empty()) + DeadInsts.push_back(DU.NarrowDef); } return WidePhi; } From atrick at apple.com Wed Jul 20 00:32:06 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 20 Jul 2011 05:32:06 -0000 Subject: [llvm-commits] [llvm] r135568 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110720053206.51EBE2A6C12D@llvm.org> Author: atrick Date: Wed Jul 20 00:32:06 2011 New Revision: 135568 URL: http://llvm.org/viewvc/llvm-project?rev=135568&view=rev Log: indvars: Added getInsertPointForUses to find a valid place to truncate the IV. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135568&r1=135567&r2=135568&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jul 20 00:32:06 2011 @@ -216,6 +216,36 @@ return true; } +/// Determine the insertion point for this user. By default, insert immediately +/// before the user. SCEVExpander or LICM will hoist loop invariants out of the +/// loop. For PHI nodes, there may be multiple uses, so compute the nearest +/// common dominator for the incoming blocks. +static Instruction *getInsertPointForUses(Instruction *User, Value *Def, + DominatorTree *DT) { + PHINode *PHI = dyn_cast(User); + if (!PHI) + return User; + + Instruction *InsertPt = 0; + for (unsigned i = 0, e = PHI->getNumIncomingValues(); i != e; ++i) { + if (PHI->getIncomingValue(i) != Def) + continue; + + BasicBlock *InsertBB = PHI->getIncomingBlock(i); + if (!InsertPt) { + InsertPt = InsertBB->getTerminator(); + continue; + } + InsertBB = DT->findNearestCommonDominator(InsertPt->getParent(), InsertBB); + InsertPt = InsertBB->getTerminator(); + } + assert(InsertPt && "Missing phi operand"); + assert(!isa(Def) || + DT->dominates(cast(Def), InsertPt) && + "def does not dominate all uses"); + return InsertPt; +} + //===----------------------------------------------------------------------===// // RewriteNonIntegerIVs and helpers. Prefer integer IVs. //===----------------------------------------------------------------------===// @@ -697,18 +727,7 @@ // hoist loop invariants out of the loop. For PHI nodes, there may be // multiple uses, so compute the nearest common dominator for the // incoming blocks. - Instruction *InsertPt = User; - if (PHINode *PHI = dyn_cast(InsertPt)) - for (unsigned i = 0, e = PHI->getNumIncomingValues(); i != e; ++i) - if (PHI->getIncomingValue(i) == Op) { - if (InsertPt == User) - InsertPt = PHI->getIncomingBlock(i)->getTerminator(); - else - InsertPt = - DT->findNearestCommonDominator(InsertPt->getParent(), - PHI->getIncomingBlock(i)) - ->getTerminator(); - } + Instruction *InsertPt = getInsertPointForUses(User, Op, DT); // Now expand it into actual Instructions and patch it into place. Value *NewVal = Rewriter.expandCodeFor(AR, UseTy, InsertPt); @@ -1023,9 +1042,7 @@ // This user does not evaluate to a recurence after widening, so don't // follow it. Instead insert a Trunc to kill off the original use, // eventually isolating the original narrow IV so it can be removed. - Use *U = std::find(DU.NarrowUse->op_begin(), DU.NarrowUse->op_end(), - DU.NarrowDef); - IRBuilder<> Builder(*U); + IRBuilder<> Builder(getInsertPointForUses(DU.NarrowUse, DU.NarrowDef, DT)); Value *Trunc = Builder.CreateTrunc(DU.WideDef, DU.NarrowDef->getType()); DU.NarrowUse->replaceUsesOfWith(DU.NarrowDef, Trunc); return 0; Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=135568&r1=135567&r2=135568&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Wed Jul 20 00:32:06 2011 @@ -350,3 +350,42 @@ exit: ret void } + +; Test a widened IV that is used by a phi on different paths within the loop. +; +; CHECK: for.body: +; CHECK: phi i64 +; CHECK: trunc i64 +; CHECK: if.then: +; CHECK: for.inc: +; CHECK: phi i32 +; CHECK: for.end: +define void @phiUsesTrunc() nounwind { +entry: + br i1 undef, label %for.body, label %for.end + +for.body: + %iv = phi i32 [ %inc, %for.inc ], [ 1, %entry ] + br i1 undef, label %if.then, label %if.else + +if.then: + br i1 undef, label %if.then33, label %for.inc + +if.then33: + br label %for.inc + +if.else: + br i1 undef, label %if.then97, label %for.inc + +if.then97: + %idxprom100 = sext i32 %iv to i64 + br label %for.inc + +for.inc: + %kmin.1 = phi i32 [ %iv, %if.then33 ], [ 0, %if.then ], [ %iv, %if.then97 ], [ 0, %if.else ] + %inc = add nsw i32 %iv, 1 + br i1 undef, label %for.body, label %for.end + +for.end: + ret void +} From evan.cheng at apple.com Wed Jul 20 00:58:47 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 05:58:47 -0000 Subject: [llvm-commits] [llvm] r135569 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Target/ lib/Target/ARM/MCTargetDesc/ lib/Target/CBackend/ test/CodeGen/PowerPC/ tools/llvm-mc/ tools/lto/ Message-ID: <20110720055847.B1F6F2A6C12D@llvm.org> Author: evancheng Date: Wed Jul 20 00:58:47 2011 New Revision: 135569 URL: http://llvm.org/viewvc/llvm-project?rev=135569&view=rev Log: Add MCObjectFileInfo and sink the MCSections initialization code from TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! Added: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCWin64EH.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Wed Jul 20 00:58:47 2011 @@ -175,6 +175,7 @@ MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL. // Real constructor. MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, + const MCObjectFileInfo *MOFI, const TargetAsmInfo *TAI); ~MachineModuleInfo(); Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Wed Jul 20 00:58:47 2011 @@ -33,42 +33,13 @@ class TargetLoweringObjectFileELF : public TargetLoweringObjectFile { -protected: - /// TLSDataSection - Section directive for Thread Local data. - /// - const MCSection *TLSDataSection; // Defaults to ".tdata". - - /// TLSBSSSection - Section directive for Thread Local uninitialized data. - /// Null if this target doesn't support a BSS section. - /// - const MCSection *TLSBSSSection; // Defaults to ".tbss". - - const MCSection *DataRelSection; - const MCSection *DataRelLocalSection; - const MCSection *DataRelROSection; - const MCSection *DataRelROLocalSection; - - const MCSection *MergeableConst4Section; - const MCSection *MergeableConst8Section; - const MCSection *MergeableConst16Section; public: - TargetLoweringObjectFileELF(); - ~TargetLoweringObjectFileELF() {} - - virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); - - virtual const MCSection *getEHFrameSection() const; - virtual const MCSection *getWin64EHFuncTableSection(StringRef) const { - return NULL; - } - virtual const MCSection *getWin64EHTableSection(StringRef) const{return NULL;} + virtual ~TargetLoweringObjectFileELF() {} virtual void emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const; - const MCSection *getDataRelSection() const { return DataRelSection; } - /// getSectionForConstant - Given a constant with the SectionKind, return a /// section that it should be placed in. virtual const MCSection *getSectionForConstant(SectionKind Kind) const; @@ -99,48 +70,8 @@ class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile { - /// TLSDataSection - Section for thread local data. - /// - const MCSection *TLSDataSection; // Defaults to ".tdata". - - /// TLSBSSSection - Section for thread local uninitialized data. - /// - const MCSection *TLSBSSSection; // Defaults to ".tbss". - - /// TLSTLVSection - Section for thread local structure information. - /// Contains the source code name of the variable, visibility and a pointer - /// to the initial value (.tdata or .tbss). - const MCSection *TLSTLVSection; // Defaults to ".tlv". - - /// TLSThreadInitSection - Section for thread local data initialization - /// functions. - const MCSection *TLSThreadInitSection; // Defaults to ".thread_init_func". - - const MCSection *CStringSection; - const MCSection *UStringSection; - const MCSection *TextCoalSection; - const MCSection *ConstTextCoalSection; - const MCSection *ConstDataSection; - const MCSection *DataCoalSection; - const MCSection *DataCommonSection; - const MCSection *DataBSSSection; - const MCSection *FourByteConstantSection; - const MCSection *EightByteConstantSection; - const MCSection *SixteenByteConstantSection; - - const MCSection *LazySymbolPointerSection; - const MCSection *NonLazySymbolPointerSection; public: - TargetLoweringObjectFileMachO(); - ~TargetLoweringObjectFileMachO() {} - - virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); - - virtual const MCSection *getEHFrameSection() const; - virtual const MCSection *getWin64EHFuncTableSection(StringRef) const { - return NULL; - } - virtual const MCSection *getWin64EHTableSection(StringRef) const{return NULL;} + virtual ~TargetLoweringObjectFileMachO() {} virtual const MCSection * SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, @@ -158,30 +89,6 @@ virtual bool shouldEmitUsedDirectiveFor(const GlobalValue *GV, Mangler *) const; - /// getTextCoalSection - Return the "__TEXT,__textcoal_nt" section we put weak - /// text symbols into. - const MCSection *getTextCoalSection() const { - return TextCoalSection; - } - - /// getConstTextCoalSection - Return the "__TEXT,__const_coal" section - /// we put weak read-only symbols into. - const MCSection *getConstTextCoalSection() const { - return ConstTextCoalSection; - } - - /// getLazySymbolPointerSection - Return the section corresponding to - /// the .lazy_symbol_pointer directive. - const MCSection *getLazySymbolPointerSection() const { - return LazySymbolPointerSection; - } - - /// getNonLazySymbolPointerSection - Return the section corresponding to - /// the .non_lazy_symbol_pointer directive. - const MCSection *getNonLazySymbolPointerSection() const { - return NonLazySymbolPointerSection; - } - /// getExprForDwarfGlobalReference - The mach-o version of this method /// defaults to returning a stub reference. virtual const MCExpr * @@ -203,20 +110,8 @@ class TargetLoweringObjectFileCOFF : public TargetLoweringObjectFile { - const MCSection *DrectveSection; - const MCSection *PDataSection; - const MCSection *XDataSection; public: - TargetLoweringObjectFileCOFF(); - ~TargetLoweringObjectFileCOFF() {} - - virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); - - virtual const MCSection *getEHFrameSection() const; - virtual const MCSection *getWin64EHFuncTableSection(StringRef) const; - virtual const MCSection *getWin64EHTableSection(StringRef) const; - - virtual const MCSection *getDrectveSection() const { return DrectveSection; } + virtual ~TargetLoweringObjectFileCOFF() {} virtual const MCSection * getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind, Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Wed Jul 20 00:58:47 2011 @@ -26,6 +26,7 @@ class MCLabel; class MCDwarfFile; class MCDwarfLoc; + class MCObjectFileInfo; class MCRegisterInfo; class MCLineSection; class StringRef; @@ -50,6 +51,9 @@ /// The MCRegisterInfo for this target. const MCRegisterInfo &MRI; + /// The MCObjectFileInfo for this target. + const MCObjectFileInfo *MOFI; + const TargetAsmInfo *TAI; /// Allocator - Allocator object used for creating machine code objects. @@ -115,13 +119,15 @@ public: explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, - const TargetAsmInfo *TAI); + const MCObjectFileInfo *MOFI, const TargetAsmInfo *TAI); ~MCContext(); const MCAsmInfo &getAsmInfo() const { return MAI; } const MCRegisterInfo &getRegisterInfo() const { return MRI; } + const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } + const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; } void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; } Added: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectFileInfo.h?rev=135569&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectFileInfo.h (added) +++ llvm/trunk/include/llvm/MC/MCObjectFileInfo.h Wed Jul 20 00:58:47 2011 @@ -0,0 +1,278 @@ +//===-- llvm/MC/MCObjectFileInfo.h - Object File Info -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes common object file formats. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCBJECTFILEINFO_H +#define LLVM_MC_MCBJECTFILEINFO_H + +#include "llvm/MC/MCCodeGenInfo.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/MC/SectionKind.h" + +namespace llvm { +class MCContext; +class MCSection; +class Triple; + +class MCObjectFileInfo { +protected: + /// CommDirectiveSupportsAlignment - True if .comm supports alignment. This + /// is a hack for as long as we support 10.4 Tiger, whose assembler doesn't + /// support alignment on comm. + bool CommDirectiveSupportsAlignment; + + /// SupportsWeakEmptyEHFrame - True if target object file supports a + /// weak_definition of constant 0 for an omitted EH frame. + bool SupportsWeakOmittedEHFrame; + + /// IsFunctionEHFrameSymbolPrivate - This flag is set to true if the + /// "EH_frame" symbol for EH information should be an assembler temporary (aka + /// private linkage, aka an L or .L label) or false if it should be a normal + /// non-.globl label. This defaults to true. + bool IsFunctionEHFrameSymbolPrivate; + + + /// TextSection - Section directive for standard text. + /// + const MCSection *TextSection; + + /// DataSection - Section directive for standard data. + /// + const MCSection *DataSection; + + /// BSSSection - Section that is default initialized to zero. + const MCSection *BSSSection; + + /// ReadOnlySection - Section that is readonly and can contain arbitrary + /// initialized data. Targets are not required to have a readonly section. + /// If they don't, various bits of code will fall back to using the data + /// section for constants. + const MCSection *ReadOnlySection; + + /// StaticCtorSection - This section contains the static constructor pointer + /// list. + const MCSection *StaticCtorSection; + + /// StaticDtorSection - This section contains the static destructor pointer + /// list. + const MCSection *StaticDtorSection; + + /// LSDASection - If exception handling is supported by the target, this is + /// the section the Language Specific Data Area information is emitted to. + const MCSection *LSDASection; + + /// CompactUnwindSection - If exception handling is supported by the target + /// and the target can support a compact representation of the CIE and FDE, + /// this is the section to emit them into. + const MCSection *CompactUnwindSection; + + // Dwarf sections for debug info. If a target supports debug info, these must + // be set. + const MCSection *DwarfAbbrevSection; + const MCSection *DwarfInfoSection; + const MCSection *DwarfLineSection; + const MCSection *DwarfFrameSection; + const MCSection *DwarfPubNamesSection; + const MCSection *DwarfPubTypesSection; + const MCSection *DwarfDebugInlineSection; + const MCSection *DwarfStrSection; + const MCSection *DwarfLocSection; + const MCSection *DwarfARangesSection; + const MCSection *DwarfRangesSection; + const MCSection *DwarfMacroInfoSection; + + // Extra TLS Variable Data section. If the target needs to put additional + // information for a TLS variable, it'll go here. + const MCSection *TLSExtraDataSection; + + /// TLSDataSection - Section directive for Thread Local data. + /// ELF and MachO only. + const MCSection *TLSDataSection; // Defaults to ".tdata". + + /// TLSBSSSection - Section directive for Thread Local uninitialized data. + /// Null if this target doesn't support a BSS section. + /// ELF and MachO only. + const MCSection *TLSBSSSection; // Defaults to ".tbss". + + + /// EHFrameSection - EH frame section. It is initialized on demand so it + /// can be overwritten (with uniquing). + const MCSection *EHFrameSection; + + /// ELF specific sections. + /// + const MCSection *DataRelSection; + const MCSection *DataRelLocalSection; + const MCSection *DataRelROSection; + const MCSection *DataRelROLocalSection; + const MCSection *MergeableConst4Section; + const MCSection *MergeableConst8Section; + const MCSection *MergeableConst16Section; + + /// MachO specific sections. + /// + + /// TLSTLVSection - Section for thread local structure information. + /// Contains the source code name of the variable, visibility and a pointer + /// to the initial value (.tdata or .tbss). + const MCSection *TLSTLVSection; // Defaults to ".tlv". + + /// TLSThreadInitSection - Section for thread local data initialization + /// functions. + const MCSection *TLSThreadInitSection; // Defaults to ".thread_init_func". + + const MCSection *CStringSection; + const MCSection *UStringSection; + const MCSection *TextCoalSection; + const MCSection *ConstTextCoalSection; + const MCSection *ConstDataSection; + const MCSection *DataCoalSection; + const MCSection *DataCommonSection; + const MCSection *DataBSSSection; + const MCSection *FourByteConstantSection; + const MCSection *EightByteConstantSection; + const MCSection *SixteenByteConstantSection; + const MCSection *LazySymbolPointerSection; + const MCSection *NonLazySymbolPointerSection; + + /// COFF specific sections. + /// + const MCSection *DrectveSection; + const MCSection *PDataSection; + const MCSection *XDataSection; + +public: + void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, MCContext &ctx); + + bool isFunctionEHFrameSymbolPrivate() const { + return IsFunctionEHFrameSymbolPrivate; + } + bool getSupportsWeakOmittedEHFrame() const { + return SupportsWeakOmittedEHFrame; + } + bool getCommDirectiveSupportsAlignment() const { + return CommDirectiveSupportsAlignment; + } + + const MCSection *getTextSection() const { return TextSection; } + const MCSection *getDataSection() const { return DataSection; } + const MCSection *getBSSSection() const { return BSSSection; } + const MCSection *getStaticCtorSection() const { return StaticCtorSection; } + const MCSection *getStaticDtorSection() const { return StaticDtorSection; } + const MCSection *getLSDASection() const { return LSDASection; } + const MCSection *getCompactUnwindSection() const{ + return CompactUnwindSection; + } + const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSection; } + const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; } + const MCSection *getDwarfLineSection() const { return DwarfLineSection; } + const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; } + const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSection;} + const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSection;} + const MCSection *getDwarfDebugInlineSection() const { + return DwarfDebugInlineSection; + } + const MCSection *getDwarfStrSection() const { return DwarfStrSection; } + const MCSection *getDwarfLocSection() const { return DwarfLocSection; } + const MCSection *getDwarfARangesSection() const { return DwarfARangesSection;} + const MCSection *getDwarfRangesSection() const { return DwarfRangesSection; } + const MCSection *getDwarfMacroInfoSection() const { + return DwarfMacroInfoSection; + } + const MCSection *getTLSExtraDataSection() const { + return TLSExtraDataSection; + } + const MCSection *getTLSDataSection() const { return TLSDataSection; } + const MCSection *getTLSBSSSection() const { return TLSBSSSection; } + + /// ELF specific sections. + /// + const MCSection *getDataRelSection() const { return DataRelSection; } + const MCSection *getDataRelLocalSection() const { + return DataRelLocalSection; + } + const MCSection *getDataRelROSection() const { return DataRelROSection; } + const MCSection *getDataRelROLocalSection() const { + return DataRelROLocalSection; + } + const MCSection *getMergeableConst4Section() const { + return MergeableConst4Section; + } + const MCSection *getMergeableConst8Section() const { + return MergeableConst8Section; + } + const MCSection *getMergeableConst16Section() const { + return MergeableConst16Section; + } + + /// MachO specific sections. + /// + const MCSection *getTLSTLVSection() const { return TLSTLVSection; } + const MCSection *getTLSThreadInitSection() const { + return TLSThreadInitSection; + } + const MCSection *getCStringSection() const { return CStringSection; } + const MCSection *getUStringSection() const { return UStringSection; } + const MCSection *getTextCoalSection() const { return TextCoalSection; } + const MCSection *getConstTextCoalSection() const { + return ConstTextCoalSection; + } + const MCSection *getConstDataSection() const { return ConstDataSection; } + const MCSection *getDataCoalSection() const { return DataCoalSection; } + const MCSection *getDataCommonSection() const { return DataCommonSection; } + const MCSection *getDataBSSSection() const { return DataBSSSection; } + const MCSection *getFourByteConstantSection() const { + return FourByteConstantSection; + } + const MCSection *getEightByteConstantSection() const { + return EightByteConstantSection; + } + const MCSection *getSixteenByteConstantSection() const { + return SixteenByteConstantSection; + } + const MCSection *getLazySymbolPointerSection() const { + return LazySymbolPointerSection; + } + const MCSection *getNonLazySymbolPointerSection() const { + return NonLazySymbolPointerSection; + } + + /// COFF specific sections. + /// + const MCSection *getDrectveSection() const { return DrectveSection; } + const MCSection *getPDataSection() const { return PDataSection; } + const MCSection *getXDataSection() const { return XDataSection; } + + const MCSection *getEHFrameSection() { + if (!EHFrameSection) + InitEHFrameSection(); + return EHFrameSection; + } + +private: + enum Environment { IsMachO, IsELF, IsCOFF }; + Environment Env; + Reloc::Model RelocM; + MCContext *Ctx; + + void InitMachOMCObjectFileInfo(Triple T); + void InitELFMCObjectFileInfo(Triple T); + void InitCOFFMCObjectFileInfo(Triple T); + + /// InitEHFrameSection - Initialize EHFrameSection on demand. + /// + void InitEHFrameSection(); +}; + +} // end namespace llvm + +#endif Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jul 20 00:58:47 2011 @@ -15,11 +15,8 @@ #define LLVM_TARGET_TARGETASMINFO_H #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { - template class ArrayRef; - class MCSection; class TargetMachine; class TargetLoweringObjectFile; @@ -29,37 +26,9 @@ public: explicit TargetAsmInfo(const TargetMachine &TM); - const MCSection *getDwarfLineSection() const { - return TLOF->getDwarfLineSection(); - } - - const MCSection *getEHFrameSection() const { - return TLOF->getEHFrameSection(); - } - - const MCSection *getCompactUnwindSection() const { - return TLOF->getCompactUnwindSection(); - } - - const MCSection *getDwarfFrameSection() const { - return TLOF->getDwarfFrameSection(); - } - - const MCSection *getWin64EHFuncTableSection(StringRef Suffix) const { - return TLOF->getWin64EHFuncTableSection(Suffix); - } - - const MCSection *getWin64EHTableSection(StringRef Suffix) const { - return TLOF->getWin64EHTableSection(Suffix); - } - unsigned getFDEEncoding(bool CFI) const { return TLOF->getFDEEncoding(CFI); } - - bool isFunctionEHFrameSymbolPrivate() const { - return TLOF->isFunctionEHFrameSymbolPrivate(); - } }; } Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original) +++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Wed Jul 20 00:58:47 2011 @@ -16,6 +16,7 @@ #define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H #include "llvm/ADT/StringRef.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/SectionKind.h" namespace llvm { @@ -31,137 +32,27 @@ class GlobalValue; class TargetMachine; -class TargetLoweringObjectFile { +class TargetLoweringObjectFile : public MCObjectFileInfo { MCContext *Ctx; TargetLoweringObjectFile(const TargetLoweringObjectFile&); // DO NOT IMPLEMENT void operator=(const TargetLoweringObjectFile&); // DO NOT IMPLEMENT -protected: - - TargetLoweringObjectFile(); - /// TextSection - Section directive for standard text. - /// - const MCSection *TextSection; - - /// DataSection - Section directive for standard data. - /// - const MCSection *DataSection; - - /// BSSSection - Section that is default initialized to zero. - const MCSection *BSSSection; - - /// ReadOnlySection - Section that is readonly and can contain arbitrary - /// initialized data. Targets are not required to have a readonly section. - /// If they don't, various bits of code will fall back to using the data - /// section for constants. - const MCSection *ReadOnlySection; - - /// StaticCtorSection - This section contains the static constructor pointer - /// list. - const MCSection *StaticCtorSection; - - /// StaticDtorSection - This section contains the static destructor pointer - /// list. - const MCSection *StaticDtorSection; - - /// LSDASection - If exception handling is supported by the target, this is - /// the section the Language Specific Data Area information is emitted to. - const MCSection *LSDASection; - - /// CompactUnwindSection - If exception handling is supported by the target - /// and the target can support a compact representation of the CIE and FDE, - /// this is the section to emit them into. - const MCSection *CompactUnwindSection; - - // Dwarf sections for debug info. If a target supports debug info, these must - // be set. - const MCSection *DwarfAbbrevSection; - const MCSection *DwarfInfoSection; - const MCSection *DwarfLineSection; - const MCSection *DwarfFrameSection; - const MCSection *DwarfPubNamesSection; - const MCSection *DwarfPubTypesSection; - const MCSection *DwarfDebugInlineSection; - const MCSection *DwarfStrSection; - const MCSection *DwarfLocSection; - const MCSection *DwarfARangesSection; - const MCSection *DwarfRangesSection; - const MCSection *DwarfMacroInfoSection; - - // Extra TLS Variable Data section. If the target needs to put additional - // information for a TLS variable, it'll go here. - const MCSection *TLSExtraDataSection; - - /// CommDirectiveSupportsAlignment - True if .comm supports alignment. This - /// is a hack for as long as we support 10.4 Tiger, whose assembler doesn't - /// support alignment on comm. - bool CommDirectiveSupportsAlignment; - - /// SupportsWeakEmptyEHFrame - True if target object file supports a - /// weak_definition of constant 0 for an omitted EH frame. - bool SupportsWeakOmittedEHFrame; - - /// IsFunctionEHFrameSymbolPrivate - This flag is set to true if the - /// "EH_frame" symbol for EH information should be an assembler temporary (aka - /// private linkage, aka an L or .L label) or false if it should be a normal - /// non-.globl label. This defaults to true. - bool IsFunctionEHFrameSymbolPrivate; - public: MCContext &getContext() const { return *Ctx; } + + TargetLoweringObjectFile() : MCObjectFileInfo(), Ctx(0) {} virtual ~TargetLoweringObjectFile(); /// Initialize - this method must be called before any actual lowering is /// done. This specifies the current context for codegen, and gives the /// lowering implementations a chance to set up their default sections. - virtual void Initialize(MCContext &ctx, const TargetMachine &TM) { - Ctx = &ctx; - } + virtual void Initialize(MCContext &ctx, const TargetMachine &TM); - bool isFunctionEHFrameSymbolPrivate() const { - return IsFunctionEHFrameSymbolPrivate; - } - bool getSupportsWeakOmittedEHFrame() const { - return SupportsWeakOmittedEHFrame; - } - bool getCommDirectiveSupportsAlignment() const { - return CommDirectiveSupportsAlignment; - } - - const MCSection *getTextSection() const { return TextSection; } - const MCSection *getDataSection() const { return DataSection; } - const MCSection *getBSSSection() const { return BSSSection; } - const MCSection *getStaticCtorSection() const { return StaticCtorSection; } - const MCSection *getStaticDtorSection() const { return StaticDtorSection; } - const MCSection *getLSDASection() const { return LSDASection; } - const MCSection *getCompactUnwindSection() const{return CompactUnwindSection;} - virtual const MCSection *getEHFrameSection() const = 0; virtual void emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const; - const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSection; } - const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; } - const MCSection *getDwarfLineSection() const { return DwarfLineSection; } - const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; } - const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSection;} - const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSection;} - const MCSection *getDwarfDebugInlineSection() const { - return DwarfDebugInlineSection; - } - const MCSection *getDwarfStrSection() const { return DwarfStrSection; } - const MCSection *getDwarfLocSection() const { return DwarfLocSection; } - const MCSection *getDwarfARangesSection() const { return DwarfARangesSection;} - const MCSection *getDwarfRangesSection() const { return DwarfRangesSection; } - const MCSection *getDwarfMacroInfoSection() const { - return DwarfMacroInfoSection; - } - const MCSection *getTLSExtraDataSection() const { - return TLSExtraDataSection; - } - virtual const MCSection *getWin64EHFuncTableSection(StringRef suffix)const=0; - virtual const MCSection *getWin64EHTableSection(StringRef suffix) const = 0; /// shouldEmitUsedDirectiveFor - This hook allows targets to selectively /// decide not to emit the UsedDirective for some symbols in llvm.used. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/ARMException.cpp Wed Jul 20 00:58:47 2011 @@ -26,7 +26,6 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameLowering.h" -#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp Wed Jul 20 00:58:47 2011 @@ -77,7 +77,8 @@ // This is a temporary hack to keep sections in the same order they // were before. This lets us produce bit identical outputs while // transitioning to CFI. - Asm->OutStreamer.SwitchSection(TLOF.getEHFrameSection()); + Asm->OutStreamer.SwitchSection( + const_cast(TLOF).getEHFrameSection()); } } Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Wed Jul 20 00:58:47 2011 @@ -67,6 +67,7 @@ ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) : MachineFunctionPass(ID), O(o), TM(tm), OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(), + &TM.getTargetLowering()->getObjFileLowering(), new TargetAsmInfo(tm))), TLOF(TM.getTargetLowering()->getObjFileLowering()), is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64), Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jul 20 00:58:47 2011 @@ -30,6 +30,7 @@ #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Scalar.h" @@ -373,7 +374,9 @@ // all the per-module stuff we're generating, including MCContext. TargetAsmInfo *TAI = new TargetAsmInfo(*this); MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), - *getRegisterInfo(), TAI); + *getRegisterInfo(), + &getTargetLowering()->getObjFileLowering(), + TAI); PM.add(MMI); OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jul 20 00:58:47 2011 @@ -17,9 +17,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetAsmInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/Support/Dwarf.h" @@ -255,8 +254,9 @@ MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, + const MCObjectFileInfo *MOFI, const TargetAsmInfo *TAI) - : ImmutablePass(ID), Context(MAI, MRI, TAI), + : ImmutablePass(ID), Context(MAI, MRI, MOFI, TAI), ObjFileMMI(0), CompactUnwindEncoding(0), CurCallSite(0), CallsEHReturn(0), CallsUnwindInit(0), DbgInfoAvailable(false), CallsExternalVAFunctionWithFloatingPointArguments(false) { @@ -268,7 +268,8 @@ } MachineModuleInfo::MachineModuleInfo() - : ImmutablePass(ID), Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, NULL) { + : ImmutablePass(ID), + Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0, NULL) { assert(0 && "This MachineModuleInfo constructor should never be called, MMI " "should always be explicitly constructed by LLVMTargetMachine"); abort(); Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Jul 20 00:58:47 2011 @@ -43,153 +43,6 @@ // ELF //===----------------------------------------------------------------------===// -TargetLoweringObjectFileELF::TargetLoweringObjectFileELF() - : TargetLoweringObjectFile(), - TLSDataSection(0), - TLSBSSSection(0), - DataRelSection(0), - DataRelLocalSection(0), - DataRelROSection(0), - DataRelROLocalSection(0), - MergeableConst4Section(0), - MergeableConst8Section(0), - MergeableConst16Section(0) { -} - -void TargetLoweringObjectFileELF::Initialize(MCContext &Ctx, - const TargetMachine &TM) { - TargetLoweringObjectFile::Initialize(Ctx, TM); - - BSSSection = - getContext().getELFSection(".bss", ELF::SHT_NOBITS, - ELF::SHF_WRITE |ELF::SHF_ALLOC, - SectionKind::getBSS()); - - TextSection = - getContext().getELFSection(".text", ELF::SHT_PROGBITS, - ELF::SHF_EXECINSTR | - ELF::SHF_ALLOC, - SectionKind::getText()); - - DataSection = - getContext().getELFSection(".data", ELF::SHT_PROGBITS, - ELF::SHF_WRITE |ELF::SHF_ALLOC, - SectionKind::getDataRel()); - - ReadOnlySection = - getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC, - SectionKind::getReadOnly()); - - TLSDataSection = - getContext().getELFSection(".tdata", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC | ELF::SHF_TLS | - ELF::SHF_WRITE, - SectionKind::getThreadData()); - - TLSBSSSection = - getContext().getELFSection(".tbss", ELF::SHT_NOBITS, - ELF::SHF_ALLOC | ELF::SHF_TLS | - ELF::SHF_WRITE, - SectionKind::getThreadBSS()); - - DataRelSection = - getContext().getELFSection(".data.rel", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getDataRel()); - - DataRelLocalSection = - getContext().getELFSection(".data.rel.local", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getDataRelLocal()); - - DataRelROSection = - getContext().getELFSection(".data.rel.ro", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getReadOnlyWithRel()); - - DataRelROLocalSection = - getContext().getELFSection(".data.rel.ro.local", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getReadOnlyWithRelLocal()); - - MergeableConst4Section = - getContext().getELFSection(".rodata.cst4", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_MERGE, - SectionKind::getMergeableConst4()); - - MergeableConst8Section = - getContext().getELFSection(".rodata.cst8", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_MERGE, - SectionKind::getMergeableConst8()); - - MergeableConst16Section = - getContext().getELFSection(".rodata.cst16", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_MERGE, - SectionKind::getMergeableConst16()); - - StaticCtorSection = - getContext().getELFSection(".ctors", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getDataRel()); - - StaticDtorSection = - getContext().getELFSection(".dtors", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC |ELF::SHF_WRITE, - SectionKind::getDataRel()); - - // Exception Handling Sections. - - // FIXME: We're emitting LSDA info into a readonly section on ELF, even though - // it contains relocatable pointers. In PIC mode, this is probably a big - // runtime hit for C++ apps. Either the contents of the LSDA need to be - // adjusted or this should be a data section. - LSDASection = - getContext().getELFSection(".gcc_except_table", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC, - SectionKind::getReadOnly()); - // Debug Info Sections. - DwarfAbbrevSection = - getContext().getELFSection(".debug_abbrev", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfInfoSection = - getContext().getELFSection(".debug_info", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfLineSection = - getContext().getELFSection(".debug_line", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfFrameSection = - getContext().getELFSection(".debug_frame", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfPubNamesSection = - getContext().getELFSection(".debug_pubnames", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfPubTypesSection = - getContext().getELFSection(".debug_pubtypes", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfStrSection = - getContext().getELFSection(".debug_str", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfLocSection = - getContext().getELFSection(".debug_loc", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfARangesSection = - getContext().getELFSection(".debug_aranges", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfRangesSection = - getContext().getELFSection(".debug_ranges", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); - DwarfMacroInfoSection = - getContext().getELFSection(".debug_macinfo", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); -} - -const MCSection *TargetLoweringObjectFileELF::getEHFrameSection() const { - return getContext().getELFSection(".eh_frame", ELF::SHT_PROGBITS, - ELF::SHF_ALLOC, - SectionKind::getDataRel()); -} - MCSymbol * TargetLoweringObjectFileELF::getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, @@ -493,221 +346,6 @@ // MachO //===----------------------------------------------------------------------===// -TargetLoweringObjectFileMachO::TargetLoweringObjectFileMachO() - : TargetLoweringObjectFile(), - TLSDataSection(0), - TLSBSSSection(0), - TLSTLVSection(0), - TLSThreadInitSection(0), - CStringSection(0), - UStringSection(0), - TextCoalSection(0), - ConstTextCoalSection(0), - ConstDataSection(0), - DataCoalSection(0), - DataCommonSection(0), - DataBSSSection(0), - FourByteConstantSection(0), - EightByteConstantSection(0), - SixteenByteConstantSection(0), - LazySymbolPointerSection(0), - NonLazySymbolPointerSection(0) { -} - -void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx, - const TargetMachine &TM) { - IsFunctionEHFrameSymbolPrivate = false; - SupportsWeakOmittedEHFrame = false; - - // .comm doesn't support alignment before Leopard. - Triple T(((LLVMTargetMachine&)TM).getTargetTriple()); - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5)) - CommDirectiveSupportsAlignment = false; - - TargetLoweringObjectFile::Initialize(Ctx, TM); - - TextSection // .text - = getContext().getMachOSection("__TEXT", "__text", - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - SectionKind::getText()); - DataSection // .data - = getContext().getMachOSection("__DATA", "__data", 0, - SectionKind::getDataRel()); - - TLSDataSection // .tdata - = getContext().getMachOSection("__DATA", "__thread_data", - MCSectionMachO::S_THREAD_LOCAL_REGULAR, - SectionKind::getDataRel()); - TLSBSSSection // .tbss - = getContext().getMachOSection("__DATA", "__thread_bss", - MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, - SectionKind::getThreadBSS()); - - // TODO: Verify datarel below. - TLSTLVSection // .tlv - = getContext().getMachOSection("__DATA", "__thread_vars", - MCSectionMachO::S_THREAD_LOCAL_VARIABLES, - SectionKind::getDataRel()); - - TLSThreadInitSection - = getContext().getMachOSection("__DATA", "__thread_init", - MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS, - SectionKind::getDataRel()); - - CStringSection // .cstring - = getContext().getMachOSection("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS, - SectionKind::getMergeable1ByteCString()); - UStringSection - = getContext().getMachOSection("__TEXT","__ustring", 0, - SectionKind::getMergeable2ByteCString()); - FourByteConstantSection // .literal4 - = getContext().getMachOSection("__TEXT", "__literal4", - MCSectionMachO::S_4BYTE_LITERALS, - SectionKind::getMergeableConst4()); - EightByteConstantSection // .literal8 - = getContext().getMachOSection("__TEXT", "__literal8", - MCSectionMachO::S_8BYTE_LITERALS, - SectionKind::getMergeableConst8()); - - // ld_classic doesn't support .literal16 in 32-bit mode, and ld64 falls back - // to using it in -static mode. - SixteenByteConstantSection = 0; - if (TM.getRelocationModel() != Reloc::Static && - TM.getTargetData()->getPointerSizeInBits() == 32) - SixteenByteConstantSection = // .literal16 - getContext().getMachOSection("__TEXT", "__literal16", - MCSectionMachO::S_16BYTE_LITERALS, - SectionKind::getMergeableConst16()); - - ReadOnlySection // .const - = getContext().getMachOSection("__TEXT", "__const", 0, - SectionKind::getReadOnly()); - - TextCoalSection - = getContext().getMachOSection("__TEXT", "__textcoal_nt", - MCSectionMachO::S_COALESCED | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - SectionKind::getText()); - ConstTextCoalSection - = getContext().getMachOSection("__TEXT", "__const_coal", - MCSectionMachO::S_COALESCED, - SectionKind::getReadOnly()); - ConstDataSection // .const_data - = getContext().getMachOSection("__DATA", "__const", 0, - SectionKind::getReadOnlyWithRel()); - DataCoalSection - = getContext().getMachOSection("__DATA","__datacoal_nt", - MCSectionMachO::S_COALESCED, - SectionKind::getDataRel()); - DataCommonSection - = getContext().getMachOSection("__DATA","__common", - MCSectionMachO::S_ZEROFILL, - SectionKind::getBSS()); - DataBSSSection - = getContext().getMachOSection("__DATA","__bss", MCSectionMachO::S_ZEROFILL, - SectionKind::getBSS()); - - - LazySymbolPointerSection - = getContext().getMachOSection("__DATA", "__la_symbol_ptr", - MCSectionMachO::S_LAZY_SYMBOL_POINTERS, - SectionKind::getMetadata()); - NonLazySymbolPointerSection - = getContext().getMachOSection("__DATA", "__nl_symbol_ptr", - MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, - SectionKind::getMetadata()); - - if (TM.getRelocationModel() == Reloc::Static) { - StaticCtorSection - = getContext().getMachOSection("__TEXT", "__constructor", 0, - SectionKind::getDataRel()); - StaticDtorSection - = getContext().getMachOSection("__TEXT", "__destructor", 0, - SectionKind::getDataRel()); - } else { - StaticCtorSection - = getContext().getMachOSection("__DATA", "__mod_init_func", - MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, - SectionKind::getDataRel()); - StaticDtorSection - = getContext().getMachOSection("__DATA", "__mod_term_func", - MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, - SectionKind::getDataRel()); - } - - // Exception Handling. - LSDASection = getContext().getMachOSection("__TEXT", "__gcc_except_tab", 0, - SectionKind::getReadOnlyWithRel()); - - if (T.isMacOSX() && !T.isMacOSXVersionLT(10, 6)) - CompactUnwindSection = - getContext().getMachOSection("__LD", "__compact_unwind", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getReadOnly()); - - // Debug Information. - DwarfAbbrevSection = - getContext().getMachOSection("__DWARF", "__debug_abbrev", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfInfoSection = - getContext().getMachOSection("__DWARF", "__debug_info", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfLineSection = - getContext().getMachOSection("__DWARF", "__debug_line", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfFrameSection = - getContext().getMachOSection("__DWARF", "__debug_frame", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfPubNamesSection = - getContext().getMachOSection("__DWARF", "__debug_pubnames", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfPubTypesSection = - getContext().getMachOSection("__DWARF", "__debug_pubtypes", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfStrSection = - getContext().getMachOSection("__DWARF", "__debug_str", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfLocSection = - getContext().getMachOSection("__DWARF", "__debug_loc", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfARangesSection = - getContext().getMachOSection("__DWARF", "__debug_aranges", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfRangesSection = - getContext().getMachOSection("__DWARF", "__debug_ranges", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfMacroInfoSection = - getContext().getMachOSection("__DWARF", "__debug_macinfo", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - DwarfDebugInlineSection = - getContext().getMachOSection("__DWARF", "__debug_inlined", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); - - TLSExtraDataSection = TLSTLVSection; -} - -const MCSection *TargetLoweringObjectFileMachO::getEHFrameSection() const { - return getContext().getMachOSection("__TEXT", "__eh_frame", - MCSectionMachO::S_COALESCED | - MCSectionMachO::S_ATTR_NO_TOC | - MCSectionMachO::S_ATTR_STRIP_STATIC_SYMS | - MCSectionMachO::S_ATTR_LIVE_SUPPORT, - SectionKind::getReadOnly()); -} - const MCSection *TargetLoweringObjectFileMachO:: getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, const TargetMachine &TM) const { @@ -925,163 +563,6 @@ // COFF //===----------------------------------------------------------------------===// -TargetLoweringObjectFileCOFF::TargetLoweringObjectFileCOFF() - : TargetLoweringObjectFile(), - DrectveSection(0), - PDataSection(0), - XDataSection(0) { -} - -void TargetLoweringObjectFileCOFF::Initialize(MCContext &Ctx, - const TargetMachine &TM) { - TargetLoweringObjectFile::Initialize(Ctx, TM); - TextSection = - getContext().getCOFFSection(".text", - COFF::IMAGE_SCN_CNT_CODE | - COFF::IMAGE_SCN_MEM_EXECUTE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getText()); - DataSection = - getContext().getCOFFSection(".data", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); - ReadOnlySection = - getContext().getCOFFSection(".rdata", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getReadOnly()); - StaticCtorSection = - getContext().getCOFFSection(".ctors", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); - StaticDtorSection = - getContext().getCOFFSection(".dtors", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); - - // FIXME: We're emitting LSDA info into a readonly section on COFF, even - // though it contains relocatable pointers. In PIC mode, this is probably a - // big runtime hit for C++ apps. Either the contents of the LSDA need to be - // adjusted or this should be a data section. - LSDASection = - getContext().getCOFFSection(".gcc_except_table", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getReadOnly()); - // Debug info. - DwarfAbbrevSection = - getContext().getCOFFSection(".debug_abbrev", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfInfoSection = - getContext().getCOFFSection(".debug_info", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfLineSection = - getContext().getCOFFSection(".debug_line", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfFrameSection = - getContext().getCOFFSection(".debug_frame", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfPubNamesSection = - getContext().getCOFFSection(".debug_pubnames", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfPubTypesSection = - getContext().getCOFFSection(".debug_pubtypes", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfStrSection = - getContext().getCOFFSection(".debug_str", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfLocSection = - getContext().getCOFFSection(".debug_loc", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfARangesSection = - getContext().getCOFFSection(".debug_aranges", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfRangesSection = - getContext().getCOFFSection(".debug_ranges", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - DwarfMacroInfoSection = - getContext().getCOFFSection(".debug_macinfo", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); - - DrectveSection = - getContext().getCOFFSection(".drectve", - COFF::IMAGE_SCN_LNK_INFO, - SectionKind::getMetadata()); - - PDataSection = - getContext().getCOFFSection(".pdata", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); - - XDataSection = - getContext().getCOFFSection(".xdata", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); -} - -const MCSection *TargetLoweringObjectFileCOFF::getEHFrameSection() const { - return getContext().getCOFFSection(".eh_frame", - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); -} - -const MCSection *TargetLoweringObjectFileCOFF::getWin64EHFuncTableSection( - StringRef suffix) const { - if (suffix == "") - return PDataSection; - return getContext().getCOFFSection((".pdata"+suffix).str(), - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); -} - -const MCSection *TargetLoweringObjectFileCOFF::getWin64EHTableSection( - StringRef suffix) const { - if (suffix == "") - return XDataSection; - return getContext().getCOFFSection((".xdata"+suffix).str(), - COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | - COFF::IMAGE_SCN_MEM_READ | - COFF::IMAGE_SCN_MEM_WRITE, - SectionKind::getDataRel()); -} - - static unsigned getCOFFSectionFlags(SectionKind K) { unsigned Flags = 0; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jul 20 00:58:47 2011 @@ -16,6 +16,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSymbol.h" #include "llvm/ADT/OwningPtr.h" @@ -995,6 +996,19 @@ EmitEOL(); } +static const MCSection *getWin64EHTableSection(StringRef suffix, + MCContext &context) { + // FIXME: This doesn't belong in MCObjectFileInfo. However, + /// this duplicate code in MCWin64EH.cpp. + if (suffix == "") + return context.getObjectFileInfo()->getXDataSection(); + return context.getCOFFSection((".xdata"+suffix).str(), + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); +} + void MCAsmStreamer::EmitWin64EHHandlerData() { MCStreamer::EmitWin64EHHandlerData(); @@ -1004,8 +1018,7 @@ // data block is visible. MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); StringRef suffix=MCWin64EHUnwindEmitter::GetSectionSuffix(CurFrame->Function); - const MCSection *xdataSect = - getContext().getTargetAsmInfo().getWin64EHTableSection(suffix); + const MCSection *xdataSect = getWin64EHTableSection(suffix, getContext()); if (xdataSect) SwitchSectionNoChange(xdataSect); Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Wed Jul 20 00:58:47 2011 @@ -9,6 +9,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSectionELF.h" @@ -28,8 +29,8 @@ MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri, - const TargetAsmInfo *tai) : - MAI(mai), MRI(mri), TAI(tai), + const MCObjectFileInfo *mofi, const TargetAsmInfo *tai) : + MAI(mai), MRI(mri), MOFI(mofi), TAI(tai), Allocator(), Symbols(Allocator), UsedNames(Allocator), NextUniqueID(0), CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0), Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jul 20 00:58:47 2011 @@ -75,7 +75,7 @@ assert(tai && "Unable to create target assembler!"); // Set up the MCContext for creating symbols and MCExpr's. - MCContext *Ctx = new MCContext(*MAI, *MRI, tai); + MCContext *Ctx = new MCContext(*MAI, *MRI, 0, tai); assert(Ctx && "Unable to create MCContext!"); // Set up disassembler. Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Jul 20 00:58:47 2011 @@ -377,7 +377,7 @@ SourceMgr sourceMgr; sourceMgr.setDiagHandler(diag_handler, static_cast(this)); sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over - MCContext context(*AsmInfo, *MRI, NULL); + MCContext context(*AsmInfo, *MRI, NULL, NULL); OwningPtr streamer(createNullStreamer(context)); OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jul 20 00:58:47 2011 @@ -7,13 +7,15 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCDwarf.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCContext.h" -#include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -196,7 +198,7 @@ MCOS->EmitLabel(SectionEnd); // Switch back the the dwarf line section. - MCOS->SwitchSection(context.getTargetAsmInfo().getDwarfLineSection()); + MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfLineSection()); const MCAsmInfo &asmInfo = MCOS->getContext().getAsmInfo(); MCOS->EmitDwarfAdvanceLineAddr(INT64_MAX, LastLabel, SectionEnd, @@ -209,7 +211,7 @@ void MCDwarfFileTable::Emit(MCStreamer *MCOS) { MCContext &context = MCOS->getContext(); // Switch to the section where the table will be emitted into. - MCOS->SwitchSection(context.getTargetAsmInfo().getDwarfLineSection()); + MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfLineSection()); // Create a symbol at the beginning of this section. MCSymbol *LineStartSym = context.CreateTempSymbol(); @@ -688,6 +690,7 @@ bool FrameEmitterImpl::EmitCompactUnwind(MCStreamer &Streamer, const MCDwarfFrameInfo &Frame) { MCContext &Context = Streamer.getContext(); + const MCObjectFileInfo *MOFI = Context.getObjectFileInfo(); const TargetAsmInfo &TAI = Context.getTargetAsmInfo(); bool VerboseAsm = Streamer.isVerboseAsm(); @@ -720,7 +723,7 @@ if (Frame.Lsda) Encoding |= 0x40000000; - Streamer.SwitchSection(TAI.getCompactUnwindSection()); + Streamer.SwitchSection(MOFI->getCompactUnwindSection()); // Range Start unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI); @@ -767,11 +770,12 @@ unsigned lsdaEncoding) { MCContext &context = streamer.getContext(); const MCRegisterInfo &MRI = context.getRegisterInfo(); + const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); const TargetAsmInfo &TAI = context.getTargetAsmInfo(); bool verboseAsm = streamer.isVerboseAsm(); MCSymbol *sectionStart; - if (TAI.isFunctionEHFrameSymbolPrivate() || !IsEH) + if (MOFI->isFunctionEHFrameSymbolPrivate() || !IsEH) sectionStart = context.CreateTempSymbol(); else sectionStart = context.GetOrCreateSymbol(Twine("EH_frame") + Twine(CIENum)); @@ -890,10 +894,11 @@ MCContext &context = streamer.getContext(); MCSymbol *fdeStart = context.CreateTempSymbol(); MCSymbol *fdeEnd = context.CreateTempSymbol(); + const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); const TargetAsmInfo &TAI = context.getTargetAsmInfo(); bool verboseAsm = streamer.isVerboseAsm(); - if (!TAI.isFunctionEHFrameSymbolPrivate() && IsEH) { + if (!MOFI->isFunctionEHFrameSymbolPrivate() && IsEH) { MCSymbol *EHSym = context.GetOrCreateSymbol(frame.Function->getName() + Twine(".eh")); streamer.EmitEHSymAttributes(frame.Function, EHSym); @@ -1008,9 +1013,10 @@ bool UsingCFI, bool IsEH) { MCContext &Context = Streamer.getContext(); - const TargetAsmInfo &TAI = Context.getTargetAsmInfo(); - const MCSection &Section = IsEH ? *TAI.getEHFrameSection() : - *TAI.getDwarfFrameSection(); + MCObjectFileInfo *MOFI = + const_cast(Context.getObjectFileInfo()); + const MCSection &Section = IsEH ? *MOFI->getEHFrameSection() : + *MOFI->getDwarfFrameSection(); Streamer.SwitchSection(&Section); MCSymbol *SectionStart = Context.CreateTempSymbol(); Streamer.EmitLabel(SectionStart); @@ -1022,7 +1028,8 @@ const MCSymbol *DummyDebugKey = NULL; for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) { const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i); - if (IsEH && TAI.getCompactUnwindSection() && Frame.CompactUnwindEncoding && + if (IsEH && MOFI->getCompactUnwindSection() && + Frame.CompactUnwindEncoding && Emitter.EmitCompactUnwind(Streamer, Frame)) { FDEEnd = NULL; continue; Added: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=135569&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (added) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Jul 20 00:58:47 2011 @@ -0,0 +1,500 @@ +//===-- MObjectFileInfo.cpp - Object File Information ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSection.h" +#include "llvm/MC/MCSectionCOFF.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCSectionMachO.h" +#include "llvm/ADT/Triple.h" +using namespace llvm; + +void MCObjectFileInfo::InitMachOMCObjectFileInfo(Triple T) { + // MachO + IsFunctionEHFrameSymbolPrivate = false; + SupportsWeakOmittedEHFrame = false; + + // .comm doesn't support alignment before Leopard. + if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5)) + CommDirectiveSupportsAlignment = false; + + TextSection // .text + = Ctx->getMachOSection("__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + SectionKind::getText()); + DataSection // .data + = Ctx->getMachOSection("__DATA", "__data", 0, + SectionKind::getDataRel()); + + TLSDataSection // .tdata + = Ctx->getMachOSection("__DATA", "__thread_data", + MCSectionMachO::S_THREAD_LOCAL_REGULAR, + SectionKind::getDataRel()); + TLSBSSSection // .tbss + = Ctx->getMachOSection("__DATA", "__thread_bss", + MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, + SectionKind::getThreadBSS()); + + // TODO: Verify datarel below. + TLSTLVSection // .tlv + = Ctx->getMachOSection("__DATA", "__thread_vars", + MCSectionMachO::S_THREAD_LOCAL_VARIABLES, + SectionKind::getDataRel()); + + TLSThreadInitSection + = Ctx->getMachOSection("__DATA", "__thread_init", + MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS, + SectionKind::getDataRel()); + + CStringSection // .cstring + = Ctx->getMachOSection("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS, + SectionKind::getMergeable1ByteCString()); + UStringSection + = Ctx->getMachOSection("__TEXT","__ustring", 0, + SectionKind::getMergeable2ByteCString()); + FourByteConstantSection // .literal4 + = Ctx->getMachOSection("__TEXT", "__literal4", + MCSectionMachO::S_4BYTE_LITERALS, + SectionKind::getMergeableConst4()); + EightByteConstantSection // .literal8 + = Ctx->getMachOSection("__TEXT", "__literal8", + MCSectionMachO::S_8BYTE_LITERALS, + SectionKind::getMergeableConst8()); + + // ld_classic doesn't support .literal16 in 32-bit mode, and ld64 falls back + // to using it in -static mode. + SixteenByteConstantSection = 0; + if (RelocM != Reloc::Static && + T.getArch() != Triple::x86_64 && T.getArch() != Triple::ppc64) + SixteenByteConstantSection = // .literal16 + Ctx->getMachOSection("__TEXT", "__literal16", + MCSectionMachO::S_16BYTE_LITERALS, + SectionKind::getMergeableConst16()); + + ReadOnlySection // .const + = Ctx->getMachOSection("__TEXT", "__const", 0, + SectionKind::getReadOnly()); + + TextCoalSection + = Ctx->getMachOSection("__TEXT", "__textcoal_nt", + MCSectionMachO::S_COALESCED | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + SectionKind::getText()); + ConstTextCoalSection + = Ctx->getMachOSection("__TEXT", "__const_coal", + MCSectionMachO::S_COALESCED, + SectionKind::getReadOnly()); + ConstDataSection // .const_data + = Ctx->getMachOSection("__DATA", "__const", 0, + SectionKind::getReadOnlyWithRel()); + DataCoalSection + = Ctx->getMachOSection("__DATA","__datacoal_nt", + MCSectionMachO::S_COALESCED, + SectionKind::getDataRel()); + DataCommonSection + = Ctx->getMachOSection("__DATA","__common", + MCSectionMachO::S_ZEROFILL, + SectionKind::getBSS()); + DataBSSSection + = Ctx->getMachOSection("__DATA","__bss", MCSectionMachO::S_ZEROFILL, + SectionKind::getBSS()); + + + LazySymbolPointerSection + = Ctx->getMachOSection("__DATA", "__la_symbol_ptr", + MCSectionMachO::S_LAZY_SYMBOL_POINTERS, + SectionKind::getMetadata()); + NonLazySymbolPointerSection + = Ctx->getMachOSection("__DATA", "__nl_symbol_ptr", + MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, + SectionKind::getMetadata()); + + if (RelocM == Reloc::Static) { + StaticCtorSection + = Ctx->getMachOSection("__TEXT", "__constructor", 0, + SectionKind::getDataRel()); + StaticDtorSection + = Ctx->getMachOSection("__TEXT", "__destructor", 0, + SectionKind::getDataRel()); + } else { + StaticCtorSection + = Ctx->getMachOSection("__DATA", "__mod_init_func", + MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, + SectionKind::getDataRel()); + StaticDtorSection + = Ctx->getMachOSection("__DATA", "__mod_term_func", + MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, + SectionKind::getDataRel()); + } + + // Exception Handling. + LSDASection = Ctx->getMachOSection("__TEXT", "__gcc_except_tab", 0, + SectionKind::getReadOnlyWithRel()); + + if (T.isMacOSX() && !T.isMacOSXVersionLT(10, 6)) + CompactUnwindSection = + Ctx->getMachOSection("__LD", "__compact_unwind", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getReadOnly()); + + // Debug Information. + DwarfAbbrevSection = + Ctx->getMachOSection("__DWARF", "__debug_abbrev", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfInfoSection = + Ctx->getMachOSection("__DWARF", "__debug_info", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfLineSection = + Ctx->getMachOSection("__DWARF", "__debug_line", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfFrameSection = + Ctx->getMachOSection("__DWARF", "__debug_frame", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfPubNamesSection = + Ctx->getMachOSection("__DWARF", "__debug_pubnames", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfPubTypesSection = + Ctx->getMachOSection("__DWARF", "__debug_pubtypes", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfStrSection = + Ctx->getMachOSection("__DWARF", "__debug_str", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfLocSection = + Ctx->getMachOSection("__DWARF", "__debug_loc", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfARangesSection = + Ctx->getMachOSection("__DWARF", "__debug_aranges", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfRangesSection = + Ctx->getMachOSection("__DWARF", "__debug_ranges", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfMacroInfoSection = + Ctx->getMachOSection("__DWARF", "__debug_macinfo", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfDebugInlineSection = + Ctx->getMachOSection("__DWARF", "__debug_inlined", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + + TLSExtraDataSection = TLSTLVSection; +} + +void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) { + // ELF + BSSSection = + Ctx->getELFSection(".bss", ELF::SHT_NOBITS, + ELF::SHF_WRITE |ELF::SHF_ALLOC, + SectionKind::getBSS()); + + TextSection = + Ctx->getELFSection(".text", ELF::SHT_PROGBITS, + ELF::SHF_EXECINSTR | + ELF::SHF_ALLOC, + SectionKind::getText()); + + DataSection = + Ctx->getELFSection(".data", ELF::SHT_PROGBITS, + ELF::SHF_WRITE |ELF::SHF_ALLOC, + SectionKind::getDataRel()); + + ReadOnlySection = + Ctx->getELFSection(".rodata", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC, + SectionKind::getReadOnly()); + + TLSDataSection = + Ctx->getELFSection(".tdata", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC | ELF::SHF_TLS | + ELF::SHF_WRITE, + SectionKind::getThreadData()); + + TLSBSSSection = + Ctx->getELFSection(".tbss", ELF::SHT_NOBITS, + ELF::SHF_ALLOC | ELF::SHF_TLS | + ELF::SHF_WRITE, + SectionKind::getThreadBSS()); + + DataRelSection = + Ctx->getELFSection(".data.rel", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getDataRel()); + + DataRelLocalSection = + Ctx->getELFSection(".data.rel.local", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getDataRelLocal()); + + DataRelROSection = + Ctx->getELFSection(".data.rel.ro", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getReadOnlyWithRel()); + + DataRelROLocalSection = + Ctx->getELFSection(".data.rel.ro.local", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getReadOnlyWithRelLocal()); + + MergeableConst4Section = + Ctx->getELFSection(".rodata.cst4", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_MERGE, + SectionKind::getMergeableConst4()); + + MergeableConst8Section = + Ctx->getELFSection(".rodata.cst8", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_MERGE, + SectionKind::getMergeableConst8()); + + MergeableConst16Section = + Ctx->getELFSection(".rodata.cst16", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_MERGE, + SectionKind::getMergeableConst16()); + + StaticCtorSection = + Ctx->getELFSection(".ctors", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getDataRel()); + + StaticDtorSection = + Ctx->getELFSection(".dtors", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC |ELF::SHF_WRITE, + SectionKind::getDataRel()); + + // Exception Handling Sections. + + // FIXME: We're emitting LSDA info into a readonly section on ELF, even though + // it contains relocatable pointers. In PIC mode, this is probably a big + // runtime hit for C++ apps. Either the contents of the LSDA need to be + // adjusted or this should be a data section. + LSDASection = + Ctx->getELFSection(".gcc_except_table", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC, + SectionKind::getReadOnly()); + + // Debug Info Sections. + DwarfAbbrevSection = + Ctx->getELFSection(".debug_abbrev", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfInfoSection = + Ctx->getELFSection(".debug_info", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfLineSection = + Ctx->getELFSection(".debug_line", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfFrameSection = + Ctx->getELFSection(".debug_frame", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfPubNamesSection = + Ctx->getELFSection(".debug_pubnames", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfPubTypesSection = + Ctx->getELFSection(".debug_pubtypes", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfStrSection = + Ctx->getELFSection(".debug_str", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfLocSection = + Ctx->getELFSection(".debug_loc", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfARangesSection = + Ctx->getELFSection(".debug_aranges", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfRangesSection = + Ctx->getELFSection(".debug_ranges", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); + DwarfMacroInfoSection = + Ctx->getELFSection(".debug_macinfo", ELF::SHT_PROGBITS, 0, + SectionKind::getMetadata()); +} + + +void MCObjectFileInfo::InitCOFFMCObjectFileInfo(Triple T) { + // COFF + TextSection = + Ctx->getCOFFSection(".text", + COFF::IMAGE_SCN_CNT_CODE | + COFF::IMAGE_SCN_MEM_EXECUTE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getText()); + DataSection = + Ctx->getCOFFSection(".data", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); + ReadOnlySection = + Ctx->getCOFFSection(".rdata", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getReadOnly()); + StaticCtorSection = + Ctx->getCOFFSection(".ctors", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); + StaticDtorSection = + Ctx->getCOFFSection(".dtors", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); + + // FIXME: We're emitting LSDA info into a readonly section on COFF, even + // though it contains relocatable pointers. In PIC mode, this is probably a + // big runtime hit for C++ apps. Either the contents of the LSDA need to be + // adjusted or this should be a data section. + LSDASection = + Ctx->getCOFFSection(".gcc_except_table", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getReadOnly()); + + // Debug info. + DwarfAbbrevSection = + Ctx->getCOFFSection(".debug_abbrev", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfInfoSection = + Ctx->getCOFFSection(".debug_info", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfLineSection = + Ctx->getCOFFSection(".debug_line", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfFrameSection = + Ctx->getCOFFSection(".debug_frame", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfPubNamesSection = + Ctx->getCOFFSection(".debug_pubnames", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfPubTypesSection = + Ctx->getCOFFSection(".debug_pubtypes", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfStrSection = + Ctx->getCOFFSection(".debug_str", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfLocSection = + Ctx->getCOFFSection(".debug_loc", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfARangesSection = + Ctx->getCOFFSection(".debug_aranges", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfRangesSection = + Ctx->getCOFFSection(".debug_ranges", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + DwarfMacroInfoSection = + Ctx->getCOFFSection(".debug_macinfo", + COFF::IMAGE_SCN_MEM_DISCARDABLE | + COFF::IMAGE_SCN_MEM_READ, + SectionKind::getMetadata()); + + DrectveSection = + Ctx->getCOFFSection(".drectve", + COFF::IMAGE_SCN_LNK_INFO, + SectionKind::getMetadata()); + + PDataSection = + Ctx->getCOFFSection(".pdata", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); + + XDataSection = + Ctx->getCOFFSection(".xdata", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); +} + +void MCObjectFileInfo::InitMCObjectFileInfo(StringRef TT, Reloc::Model relocm, + MCContext &ctx) { + RelocM = relocm; + Ctx = &ctx; + + // Common. + CommDirectiveSupportsAlignment = true; + SupportsWeakOmittedEHFrame = true; + IsFunctionEHFrameSymbolPrivate = true; + + Triple T(TT); + Triple::ArchType Arch = T.getArch(); + // FIXME: Checking for Arch here to filter out bogus triples such as + // cellspu-apple-darwin. Perhaps we should fix in Triple? + if ((Arch == Triple::x86 || Arch == Triple::x86_64 || + Arch == Triple::arm || Arch == Triple::thumb || + Arch == Triple::ppc || Arch == Triple::ppc64 || + Arch == Triple::UnknownArch) && + (T.isOSDarwin() || T.getEnvironment() == Triple::MachO)) { + Env = IsMachO; + InitMachOMCObjectFileInfo(T); + } else if (T.getOS() == Triple::MinGW32 || T.getOS() == Triple::Cygwin || + T.getOS() == Triple::Win32) { + Env = IsCOFF; + InitCOFFMCObjectFileInfo(T); + } else { + Env = IsELF; + InitELFMCObjectFileInfo(T); + } +} + +void MCObjectFileInfo::InitEHFrameSection() { + if (Env == IsMachO) + EHFrameSection = + Ctx->getMachOSection("__TEXT", "__eh_frame", + MCSectionMachO::S_COALESCED | + MCSectionMachO::S_ATTR_NO_TOC | + MCSectionMachO::S_ATTR_STRIP_STATIC_SYMS | + MCSectionMachO::S_ATTR_LIVE_SUPPORT, + SectionKind::getReadOnly()); + else if (Env == IsELF) + EHFrameSection = + Ctx->getELFSection(".eh_frame", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC, + SectionKind::getDataRel()); + else + EHFrameSection = + Ctx->getCOFFSection(".eh_frame", + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); +} Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jul 20 00:58:47 2011 @@ -23,6 +23,7 @@ #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" Modified: llvm/trunk/lib/MC/MCWin64EH.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCWin64EH.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCWin64EH.cpp (original) +++ llvm/trunk/lib/MC/MCWin64EH.cpp Wed Jul 20 00:58:47 2011 @@ -10,10 +10,11 @@ #include "llvm/MC/MCWin64EH.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCExpr.h" -#include "llvm/Target/TargetAsmInfo.h" +#include "llvm/ADT/Twine.h" namespace llvm { @@ -220,14 +221,36 @@ return ""; } +static const MCSection *getWin64EHTableSection(StringRef suffix, + MCContext &context) { + if (suffix == "") + return context.getObjectFileInfo()->getXDataSection(); + + return context.getCOFFSection((".xdata"+suffix).str(), + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); +} + +static const MCSection *getWin64EHFuncTableSection(StringRef suffix, + MCContext &context) { + if (suffix == "") + return context.getObjectFileInfo()->getPDataSection(); + return context.getCOFFSection((".pdata"+suffix).str(), + COFF::IMAGE_SCN_CNT_INITIALIZED_DATA | + COFF::IMAGE_SCN_MEM_READ | + COFF::IMAGE_SCN_MEM_WRITE, + SectionKind::getDataRel()); +} + void MCWin64EHUnwindEmitter::EmitUnwindInfo(MCStreamer &streamer, MCWin64EHUnwindInfo *info) { // Switch sections (the static function above is meant to be called from // here and from Emit(). MCContext &context = streamer.getContext(); - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); const MCSection *xdataSect = - TAI.getWin64EHTableSection(GetSectionSuffix(info->Function)); + getWin64EHTableSection(GetSectionSuffix(info->Function), context); streamer.SwitchSection(xdataSect); llvm::EmitUnwindInfo(streamer, info); @@ -236,11 +259,10 @@ void MCWin64EHUnwindEmitter::Emit(MCStreamer &streamer) { MCContext &context = streamer.getContext(); // Emit the unwind info structs first. - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); for (unsigned i = 0; i < streamer.getNumW64UnwindInfos(); ++i) { MCWin64EHUnwindInfo &info = streamer.getW64UnwindInfo(i); const MCSection *xdataSect = - TAI.getWin64EHTableSection(GetSectionSuffix(info.Function)); + getWin64EHTableSection(GetSectionSuffix(info.Function), context); streamer.SwitchSection(xdataSect); llvm::EmitUnwindInfo(streamer, &info); } @@ -248,7 +270,7 @@ for (unsigned i = 0; i < streamer.getNumW64UnwindInfos(); ++i) { MCWin64EHUnwindInfo &info = streamer.getW64UnwindInfo(i); const MCSection *pdataSect = - TAI.getWin64EHFuncTableSection(GetSectionSuffix(info.Function)); + getWin64EHFuncTableSection(GetSectionSuffix(info.Function), context); streamer.SwitchSection(pdataSect); EmitRuntimeFunction(streamer, &info); } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 20 00:58:47 2011 @@ -155,4 +155,3 @@ TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo); TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo); } - Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Jul 20 00:58:47 2011 @@ -37,6 +37,7 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" @@ -92,6 +93,7 @@ const Module *TheModule; const MCAsmInfo* TAsm; const MCRegisterInfo *MRI; + const MCObjectFileInfo *MOFI; MCContext *TCtx; const TargetData* TD; @@ -111,8 +113,8 @@ static char ID; explicit CWriter(formatted_raw_ostream &o) : FunctionPass(ID), Out(o), IL(0), Mang(0), LI(0), - TheModule(0), TAsm(0), MRI(0), TCtx(0), TD(0), OpaqueCounter(0), - NextAnonValueNumber(0) { + TheModule(0), TAsm(0), MRI(0), MOFI(0), TCtx(0), TD(0), + OpaqueCounter(0), NextAnonValueNumber(0) { initializeLoopInfoPass(*PassRegistry::getPassRegistry()); FPCounter = 0; } @@ -152,6 +154,7 @@ delete TCtx; delete TAsm; delete MRI; + delete MOFI; FPConstantMap.clear(); ByValParams.clear(); intrinsicPrototypesAlreadyGenerated.clear(); @@ -1673,7 +1676,7 @@ #endif TAsm = new CBEMCAsmInfo(); MRI = new MCRegisterInfo(); - TCtx = new MCContext(*TAsm, *MRI, NULL); + TCtx = new MCContext(*TAsm, *MRI, NULL, NULL); Mang = new Mangler(*TCtx, *TD); // Keep track of which functions are static ctors/dtors so they can have Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Jul 20 00:58:47 2011 @@ -35,34 +35,15 @@ // Generic Code //===----------------------------------------------------------------------===// -TargetLoweringObjectFile::TargetLoweringObjectFile() : - Ctx(0), - TextSection(0), - DataSection(0), - BSSSection(0), - ReadOnlySection(0), - StaticCtorSection(0), - StaticDtorSection(0), - LSDASection(0), - CompactUnwindSection(0), - DwarfAbbrevSection(0), - DwarfInfoSection(0), - DwarfLineSection(0), - DwarfFrameSection(0), - DwarfPubNamesSection(0), - DwarfPubTypesSection(0), - DwarfDebugInlineSection(0), - DwarfStrSection(0), - DwarfLocSection(0), - DwarfARangesSection(0), - DwarfRangesSection(0), - DwarfMacroInfoSection(0), - TLSExtraDataSection(0), - CommDirectiveSupportsAlignment(true), - SupportsWeakOmittedEHFrame(true), - IsFunctionEHFrameSymbolPrivate(true) { +/// Initialize - this method must be called before any actual lowering is +/// done. This specifies the current context for codegen, and gives the +/// lowering implementations a chance to set up their default sections. +void TargetLoweringObjectFile::Initialize(MCContext &ctx, + const TargetMachine &TM) { + Ctx = &ctx; + InitMCObjectFileInfo(TM.getTargetTriple(), TM.getRelocationModel(), *Ctx); } - + TargetLoweringObjectFile::~TargetLoweringObjectFile() { } Modified: llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll Wed Jul 20 00:58:47 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -mtriple=ppc-apple-darwin | FileCheck %s +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jul 20 00:58:47 2011 @@ -18,6 +18,8 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -346,7 +348,12 @@ } const TargetAsmInfo *tai = new TargetAsmInfo(*TM); - MCContext Ctx(*MAI, *MRI, tai); + // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and + // MCObjectFileInfo needs a MCContext reference in order to initialize itself. + OwningPtr MOFI(new MCObjectFileInfo()); + MCContext Ctx(*MAI, *MRI, MOFI.get(), tai); + MOFI->InitMCObjectFileInfo(TripleName, RelocModel, Ctx); + if (SaveTempLabels) Ctx.setAllowTemporaryLabels(false); Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jul 20 00:58:47 2011 @@ -314,7 +314,7 @@ // mark which symbols can not be internalized MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), - NULL); + NULL, NULL); Mangler mangler(Context, *_target->getTargetData()); std::vector mustPreserveList; SmallPtrSet asmUsed; Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=135569&r1=135568&r2=135569&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Jul 20 00:58:47 2011 @@ -665,7 +665,7 @@ bool LTOModule::ParseSymbols() { // Use mangler to add GlobalPrefix to names to match linker names. MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), - NULL); + NULL, NULL); Mangler mangler(Context, *_target->getTargetData()); // add functions From pichet2000 at gmail.com Wed Jul 20 01:35:24 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 20 Jul 2011 06:35:24 -0000 Subject: [llvm-commits] [llvm] r135573 - /llvm/trunk/lib/MC/CMakeLists.txt Message-ID: <20110720063524.8A56D2A6C12D@llvm.org> Author: fpichet Date: Wed Jul 20 01:35:24 2011 New Revision: 135573 URL: http://llvm.org/viewvc/llvm-project?rev=135573&view=rev Log: Fix the CMake build. Modified: llvm/trunk/lib/MC/CMakeLists.txt Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=135573&r1=135572&r2=135573&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Wed Jul 20 01:35:24 2011 @@ -21,6 +21,7 @@ MCMachOStreamer.cpp MCMachObjectTargetWriter.cpp MCNullStreamer.cpp + MCObjectFileInfo.cpp MCObjectStreamer.cpp MCObjectWriter.cpp MCPureStreamer.cpp From evan.cheng at apple.com Wed Jul 20 01:54:19 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 06:54:19 -0000 Subject: [llvm-commits] [llvm] r135575 - /llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Message-ID: <20110720065419.DFD062A6C12D@llvm.org> Author: evancheng Date: Wed Jul 20 01:54:19 2011 New Revision: 135575 URL: http://llvm.org/viewvc/llvm-project?rev=135575&view=rev Log: Include MCRegisterInfo to eliminate a compilation warning. Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135575&r1=135574&r2=135575&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jul 20 01:54:19 2011 @@ -11,10 +11,11 @@ #include "llvm-c/Disassembler.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" -#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetAsmInfo.h" // FIXME. #include "llvm/Target/TargetMachine.h" // FIXME. From evan.cheng at apple.com Wed Jul 20 02:51:57 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 07:51:57 -0000 Subject: [llvm-commits] [llvm] r135580 - in /llvm/trunk: include/llvm/ExecutionEngine/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/ExecutionEngine/ lib/ExecutionEngine/JIT/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/MCTargetDesc/ lib/Target/MSP430/ lib/Target/MS... Message-ID: <20110720075158.298FC312800A@llvm.org> Author: evancheng Date: Wed Jul 20 02:51:56 2011 New Revision: 135580 URL: http://llvm.org/viewvc/llvm-project?rev=135580&view=rev Log: - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/include/llvm/MC/MCCodeGenInfo.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp llvm/trunk/lib/MC/MCCodeGenInfo.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp llvm/trunk/lib/Target/CBackend/CTargetMachine.h llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.h llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.h llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/lli/lli.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Jul 20 02:51:56 2011 @@ -480,7 +480,7 @@ JMM = NULL; AllocateGVsWithCode = false; RelocModel = Reloc::Default; - CMModel = CodeModel::Default; + CMModel = CodeModel::JITDefault; UseMCJIT = false; } @@ -529,7 +529,8 @@ } /// setCodeModel - Set the CodeModel that the ExecutionEngine target - /// data is using. Defaults to target specific default "CodeModel::Default". + /// data is using. Defaults to target specific default + /// "CodeModel::JITDefault". EngineBuilder &setCodeModel(CodeModel::Model M) { CMModel = M; return *this; @@ -581,6 +582,7 @@ StringRef MCPU, const SmallVectorImpl& MAttrs, Reloc::Model RM, + CodeModel::Model CM, std::string *Err); ExecutionEngine *create(); Modified: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeGenInfo.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCCodeGenInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCCodeGenInfo.h Wed Jul 20 02:51:56 2011 @@ -16,20 +16,33 @@ #define LLVM_MC_MCCODEGENINFO_H namespace llvm { + // Relocation model types. namespace Reloc { enum Model { Default, Static, PIC_, DynamicNoPIC }; } + // Code model types. + namespace CodeModel { + enum Model { Default, JITDefault, Small, Kernel, Medium, Large }; + } + class MCCodeGenInfo { /// RelocationModel - Relocation model: statcic, pic, etc. /// Reloc::Model RelocationModel; + /// CMModel - Code model. + /// + CodeModel::Model CMModel; + public: - void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default); + void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default, + CodeModel::Model CM = CodeModel::Default); Reloc::Model getRelocationModel() const { return RelocationModel; } + + CodeModel::Model getCodeModel() const { return CMModel; } }; } // namespace llvm Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Jul 20 02:51:56 2011 @@ -43,17 +43,6 @@ class formatted_raw_ostream; class raw_ostream; -// Code model types. -namespace CodeModel { - enum Model { - Default, - Small, - Kernel, - Medium, - Large - }; -} - // Code generation optimization level. namespace CodeGenOpt { enum Level { @@ -101,7 +90,6 @@ std::string TargetFS; /// CodeGenInfo - Low level target information such as relocation model. - /// const MCCodeGenInfo *CodeGenInfo; /// AsmInfo - Contains target specific asm information. @@ -214,11 +202,7 @@ /// getCodeModel - Returns the code model. The choices are small, kernel, /// medium, large, and target default. - static CodeModel::Model getCodeModel(); - - /// setCodeModel - Sets the code model. - /// - static void setCodeModel(CodeModel::Model Model); + CodeModel::Model getCodeModel() const; /// getAsmVerbosityDefault - Returns the default value of asm verbosity. /// @@ -301,7 +285,8 @@ class LLVMTargetMachine : public TargetMachine { protected: // Can only create subclasses. LLVMTargetMachine(const Target &T, StringRef TargetTriple, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); private: /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for @@ -310,9 +295,6 @@ bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, bool DisableVerify, MCContext *&OutCtx); - virtual void setCodeModelForJIT(); - virtual void setCodeModelForStatic(); - public: /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Jul 20 02:51:56 2011 @@ -70,7 +70,9 @@ typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T, StringRef TT); - typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M); + typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, + Reloc::Model RM, + CodeModel::Model CM); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, @@ -80,7 +82,8 @@ StringRef TT, StringRef CPU, StringRef Features, - Reloc::Model RM); + Reloc::Model RM, + CodeModel::Model CM); typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T, @@ -263,10 +266,11 @@ /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. /// - MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const { + MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM, + CodeModel::Model CM) const { if (!MCCodeGenInfoCtorFn) return 0; - return MCCodeGenInfoCtorFn(Triple, M); + return MCCodeGenInfoCtorFn(Triple, RM, CM); } /// createMCInstrInfo - Create a MCInstrInfo implementation. @@ -309,11 +313,12 @@ /// either the target triple from the module, or the target triple of the /// host if that does not exist. TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, - StringRef Features, - Reloc::Model RM = Reloc::Default) const { + StringRef Features, + Reloc::Model RM = Reloc::Default, + CodeModel::Model CM = CodeModel::Default) const { if (!TargetMachineCtorFn) return 0; - return TargetMachineCtorFn(*this, Triple, CPU, Features, RM); + return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM); } /// createAsmBackend - Create a target specific assembly parser. @@ -802,7 +807,8 @@ TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); } private: - static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) { + static MCCodeGenInfo *Allocator(StringRef TT, + Reloc::Model RM, CodeModel::Model CM) { return new MCCodeGenInfoImpl(); } }; @@ -938,8 +944,9 @@ private: static TargetMachine *Allocator(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) { - return new TargetMachineImpl(T, TT, CPU, FS, RM); + Reloc::Model RM, + CodeModel::Model CM) { + return new TargetMachineImpl(T, TT, CPU, FS, RM, CM); } }; Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -105,23 +105,12 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, - Reloc::Model RM) + Reloc::Model RM, CodeModel::Model CM) : TargetMachine(T, Triple, CPU, FS) { - CodeGenInfo = T.createMCCodeGenInfo(Triple, RM); + CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM); AsmInfo = T.createMCAsmInfo(Triple); } -// Set the default code model for the JIT for a generic target. -// FIXME: Is small right here? or .is64Bit() ? Large : Small? -void LLVMTargetMachine::setCodeModelForJIT() { - setCodeModel(CodeModel::Small); -} - -// Set the default code model for static compilation for a generic target. -void LLVMTargetMachine::setCodeModelForStatic() { - setCodeModel(CodeModel::Small); -} - bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, CodeGenFileType FileType, @@ -201,8 +190,6 @@ PM.add(Printer); - // Make sure the code model is set. - setCodeModelForStatic(); PM.add(createGCInfoDeleter()); return false; } @@ -217,9 +204,6 @@ JITCodeEmitter &JCE, CodeGenOpt::Level OptLevel, bool DisableVerify) { - // Make sure the code model is set. - setCodeModelForJIT(); - // Add common CodeGen passes. MCContext *Ctx = 0; if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx)) @@ -273,9 +257,6 @@ PM.add(Printer); - // Make sure the code model is set. - setCodeModelForJIT(); - return false; // success! } Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Jul 20 02:51:56 2011 @@ -437,9 +437,8 @@ SmallVector MAttrs; TargetMachine *TM = - EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr); + EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, CMM, ErrorStr); if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; - TM->setCodeModel(CMM); return ExecutionEngine::JITCtor(M, ErrorStr, JMM, OptLevel, GVsWithCode, TM); } @@ -467,9 +466,8 @@ // try making a JIT. if (WhichEngine & EngineKind::JIT) { if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, - RelocModel, ErrorStr)) { - TM->setCodeModel(CMModel); - + RelocModel, CMModel, + ErrorStr)) { if (UseMCJIT && ExecutionEngine::MCJITCtor) { ExecutionEngine *EE = ExecutionEngine::MCJITCtor(M, ErrorStr, JMM, OptLevel, Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Wed Jul 20 02:51:56 2011 @@ -101,7 +101,7 @@ CodeGenOpt::Default, bool GVsWithCode = true, Reloc::Model RM = Reloc::Default, - CodeModel::Model CMM = CodeModel::Default) { + CodeModel::Model CMM = CodeModel::JITDefault) { return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode, RM, CMM); } Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Wed Jul 20 02:51:56 2011 @@ -31,6 +31,7 @@ StringRef MCPU, const SmallVectorImpl& MAttrs, Reloc::Model RM, + CodeModel::Model CM, std::string *ErrorStr) { Triple TheTriple(Mod->getTargetTriple()); if (TheTriple.getTriple().empty()) @@ -85,7 +86,8 @@ // Allocate a target... TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(), - MCPU, FeaturesStr, RM); + MCPU, FeaturesStr, + RM, CM); assert(Target && "Could not allocate target machine!"); return Target; } Modified: llvm/trunk/lib/MC/MCCodeGenInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCCodeGenInfo.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCCodeGenInfo.cpp (original) +++ llvm/trunk/lib/MC/MCCodeGenInfo.cpp Wed Jul 20 02:51:56 2011 @@ -15,6 +15,7 @@ #include "llvm/MC/MCCodeGenInfo.h" using namespace llvm; -void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) { +void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) { RelocationModel = RM; + CMModel = CM; } Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -64,8 +64,8 @@ /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { @@ -76,8 +76,8 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget), + Reloc::Model RM, CodeModel::Model CM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -94,8 +94,8 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -40,7 +40,8 @@ public: ARMBaseTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -69,7 +70,8 @@ ARMFrameLowering FrameLowering; public: ARMTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -108,7 +110,8 @@ OwningPtr FrameLowering; public: ThumbTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -143,11 +143,12 @@ RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo); } -MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) RM = Reloc::DynamicNoPIC; - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -23,9 +23,9 @@ } AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -37,7 +37,8 @@ public: AlphaTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -66,9 +66,10 @@ RegisterMCAsmInfo X(TheAlphaTarget); } -MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(Reloc::PIC_); + X->InitMCCodeGenInfo(Reloc::PIC_, CM); return X; } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -24,8 +24,10 @@ BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, StringRef TT, StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef FS, + Reloc::Model RM, + CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -36,7 +36,8 @@ BlackfinIntrinsicInfo IntrinsicInfo; public: BlackfinTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -69,9 +69,10 @@ RegisterMCAsmInfo X(TheBlackfinTarget); } -MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -21,7 +21,8 @@ struct CTargetMachine : public TargetMachine { CTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -78,11 +78,12 @@ RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo); } -MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); // For the time being, use static relocations, since there's really no // support for PIC yet. - X->InitMCCodeGenInfo(Reloc::Static); + X->InitMCCodeGenInfo(Reloc::Static, CM); return X; } Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -32,8 +32,9 @@ } SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, - StringRef CPU,StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -39,7 +39,8 @@ InstrItineraryData InstrItins; public: SPUTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -23,7 +23,8 @@ struct CPPTargetMachine : public TargetMachine { CPPTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -68,16 +68,15 @@ // an easier handling. MBlazeTargetMachine:: MBlazeTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM): - LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM): + LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - if (getCodeModel() == CodeModel::Default) - setCodeModel(CodeModel::Small); } // Install an instruction selector pass using Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -42,7 +42,8 @@ public: MBlazeTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -75,11 +75,14 @@ RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo); } -MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) - RM = Reloc::Static; - X->InitMCCodeGenInfo(RM); + RM = Reloc::Static; + if (CM == CodeModel::Default) + CM = CodeModel::Small; + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -67,9 +67,10 @@ RegisterMCAsmInfo X(TheMSP430Target); } -MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -27,8 +27,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Wed Jul 20 02:51:56 2011 @@ -39,7 +39,8 @@ public: MSP430TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -78,7 +78,8 @@ RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo); } -MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) { // Abicall enables PIC by default @@ -88,7 +89,7 @@ else RM = Reloc::PIC_; } - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -32,9 +32,10 @@ // Using CodeModel::Large enables different CALL behavior. MipsTargetMachine:: MipsTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM, + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM, bool isLittle=false): - LLVMTargetMachine(T, TT, CPU, FS, RM), + LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : @@ -46,8 +47,9 @@ MipselTargetMachine:: MipselTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) : - MipsTargetMachine(T, TT, CPU, FS, RM, true) {} + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : + MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} // Install an instruction selector pass using // the ISelDag to gen Mips code. Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -36,7 +36,8 @@ public: MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool isLittle); + Reloc::Model RM, CodeModel::Model CM, + bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -74,7 +75,8 @@ class MipselTargetMachine : public MipsTargetMachine { public: MipselTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -71,9 +71,10 @@ RegisterMCAsmInfo Y(ThePTX64Target); } -MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -47,11 +47,10 @@ // DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, - Reloc::Model RM, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef TT, StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM, + bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), @@ -61,14 +60,14 @@ PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : PTXTargetMachine(T, TT, CPU, FS, RM, false) { + Reloc::Model RM, CodeModel::Model CM) + : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) { } PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : PTXTargetMachine(T, TT, CPU, FS, RM, true) { + Reloc::Model RM, CodeModel::Model CM) + : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) { } bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -33,7 +33,8 @@ public: PTXTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM, + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM, bool is64Bit); virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -62,14 +63,16 @@ public: PTX32TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; // class PTX32TargetMachine class PTX64TargetMachine : public PTXTargetMachine { public: PTX64TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; // class PTX32TargetMachine } // namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -94,7 +94,8 @@ RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo); } -MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) { @@ -104,7 +105,7 @@ else RM = Reloc::Static; } - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -54,8 +54,9 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM, + bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), @@ -68,16 +69,16 @@ bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : PPCTargetMachine(T, TT, CPU, FS, RM, false) { + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) { } PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : PPCTargetMachine(T, TT, CPU, FS, RM, true) { + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) { } Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -42,7 +42,7 @@ public: PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64Bit); + Reloc::Model RM, CodeModel::Model CM, bool is64Bit); virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCFrameLowering *getFrameLowering() const { @@ -78,7 +78,8 @@ class PPC32TargetMachine : public PPCTargetMachine { public: PPC32TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; /// PPC64TargetMachine - PowerPC 64-bit target machine. @@ -86,7 +87,8 @@ class PPC64TargetMachine : public PPCTargetMachine { public: PPC64TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -66,9 +66,10 @@ RegisterMCAsmInfo Y(TheSparcV9Target); } -MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -26,8 +26,9 @@ /// SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM, + bool is64bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), @@ -51,15 +52,15 @@ } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : SparcTargetMachine(T, TT, CPU, FS, RM, false) { + StringRef TT, StringRef CPU, + StringRef FS, Reloc::Model RM, + CodeModel::Model CM) + : SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : SparcTargetMachine(T, TT, CPU, FS, RM, true) { + StringRef TT, StringRef CPU, + StringRef FS, Reloc::Model RM, + CodeModel::Model CM) + : SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) { } Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -35,7 +35,7 @@ public: SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64bit); + Reloc::Model RM, CodeModel::Model CM, bool is64bit); virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { @@ -63,7 +63,8 @@ class SparcV8TargetMachine : public SparcTargetMachine { public: SparcV8TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; /// SparcV9TargetMachine - Sparc 64-bit target machine @@ -71,7 +72,8 @@ class SparcV9TargetMachine : public SparcTargetMachine { public: SparcV9TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -68,11 +68,12 @@ RegisterMCAsmInfo X(TheSystemZTarget); } -MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) RM = Reloc::Static; - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -21,10 +21,10 @@ /// SystemZTargetMachine ctor - Create an ILP64 architecture model /// SystemZTargetMachine::SystemZTargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef TT, StringRef CPU, + StringRef FS, Reloc::Model RM, + CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -38,7 +38,8 @@ SystemZFrameLowering FrameLowering; public: SystemZTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -40,7 +40,6 @@ bool JITExceptionHandling; bool JITEmitDebugInfo; bool JITEmitDebugInfoToDisk; - CodeModel::Model CMModel; bool GuaranteedTailCallOpt; unsigned StackAlignmentOverride; bool RealignStack; @@ -142,23 +141,6 @@ cl::location(JITEmitDebugInfoToDisk), cl::init(false)); -static cl::opt -DefCodeModel("code-model", - cl::desc("Choose code model"), - cl::location(CMModel), - cl::init(CodeModel::Default), - cl::values( - clEnumValN(CodeModel::Default, "default", - "Target default code model"), - clEnumValN(CodeModel::Small, "small", - "Small code model"), - clEnumValN(CodeModel::Kernel, "kernel", - "Kernel code model"), - clEnumValN(CodeModel::Medium, "medium", - "Medium code model"), - clEnumValN(CodeModel::Large, "large", - "Large code model"), - clEnumValEnd)); static cl::opt EnableGuaranteedTailCallOpt("tailcallopt", cl::desc("Turn fastcc calls into tail calls by (potentially) changing ABI."), @@ -230,13 +212,10 @@ /// getCodeModel - Returns the code model. The choices are small, kernel, /// medium, large, and target default. -CodeModel::Model TargetMachine::getCodeModel() { - return CMModel; -} - -/// setCodeModel - Sets the code model. -void TargetMachine::setCodeModel(CodeModel::Model Model) { - CMModel = Model; +CodeModel::Model TargetMachine::getCodeModel() const { + if (!CodeGenInfo) + return CodeModel::Default; + return CodeGenInfo->getCodeModel(); } bool TargetMachine::getAsmVerbosityDefault() { Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -339,7 +339,8 @@ RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); } -MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); Triple T(TT); @@ -376,7 +377,14 @@ if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) RM = Reloc::PIC_; - X->InitMCCodeGenInfo(RM); + // For static codegen, if we're not already set, use Small codegen. + if (CM == CodeModel::Default) + CM = CodeModel::Small; + else if (CM == CodeModel::JITDefault) + // 64-bit JIT places everything in the same buffer except external funcs. + CM = is64Bit ? CodeModel::Large : CodeModel::Small; + + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -67,8 +67,8 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : X86TargetMachine(T, TT, CPU, FS, RM, false), + Reloc::Model RM, CodeModel::Model CM) + : X86TargetMachine(T, TT, CPU, FS, RM, CM, false), DataLayout(getSubtargetImpl()->isTargetDarwin() ? "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" : (getSubtargetImpl()->isTargetCygMing() || @@ -84,8 +84,8 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : X86TargetMachine(T, TT, CPU, FS, RM, true), + Reloc::Model RM, CodeModel::Model CM) + : X86TargetMachine(T, TT, CPU, FS, RM, CM, true), DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"), InstrInfo(*this), TSInfo(*this), @@ -97,8 +97,9 @@ /// X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM, + bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { @@ -171,23 +172,3 @@ return false; } - -void X86TargetMachine::setCodeModelForStatic() { - - if (getCodeModel() != CodeModel::Default) return; - - // For static codegen, if we're not already set, use Small codegen. - setCodeModel(CodeModel::Small); -} - - -void X86TargetMachine::setCodeModelForJIT() { - - if (getCodeModel() != CodeModel::Default) return; - - // 64-bit JIT places everything in the same buffer except external functions. - if (Subtarget.is64Bit()) - setCodeModel(CodeModel::Large); - else - setCodeModel(CodeModel::Small); -} Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Wed Jul 20 02:51:56 2011 @@ -36,15 +36,11 @@ X86FrameLowering FrameLowering; X86ELFWriterInfo ELFWriterInfo; -private: - // We have specific defaults for X86. - virtual void setCodeModelForJIT(); - virtual void setCodeModelForStatic(); - public: X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64Bit); + Reloc::Model RM, CodeModel::Model CM, + bool is64Bit); virtual const X86InstrInfo *getInstrInfo() const { llvm_unreachable("getInstrInfo not implemented"); @@ -88,7 +84,8 @@ X86JITInfo JITInfo; public: X86_32TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; @@ -114,7 +111,8 @@ X86JITInfo JITInfo; public: X86_64TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Wed Jul 20 02:51:56 2011 @@ -76,9 +76,10 @@ RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); } -MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Jul 20 02:51:56 2011 @@ -20,9 +20,9 @@ /// XCoreTargetMachine ctor - Create an ILP32 architecture model /// XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Wed Jul 20 02:51:56 2011 @@ -33,7 +33,8 @@ XCoreSelectionDAGInfo TSInfo; public: XCoreTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Wed Jul 20 02:51:56 2011 @@ -91,6 +91,22 @@ "Relocatable external references, non-relocatable code"), clEnumValEnd)); +static cl::opt +CMModel("code-model", + cl::desc("Choose code model"), + cl::init(CodeModel::Default), + cl::values(clEnumValN(CodeModel::Default, "default", + "Target default code model"), + clEnumValN(CodeModel::Small, "small", + "Small code model"), + clEnumValN(CodeModel::Kernel, "kernel", + "Kernel code model"), + clEnumValN(CodeModel::Medium, "medium", + "Medium code model"), + clEnumValN(CodeModel::Large, "large", + "Large code model"), + clEnumValEnd)); + static cl::opt RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, " @@ -287,8 +303,9 @@ } std::auto_ptr - target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, - FeaturesStr, RelocModel)); + target(TheTarget->createTargetMachine(TheTriple.getTriple(), + MCPU, FeaturesStr, + RelocModel, CMModel)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); Modified: llvm/trunk/tools/lli/lli.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/tools/lli/lli.cpp (original) +++ llvm/trunk/tools/lli/lli.cpp Wed Jul 20 02:51:56 2011 @@ -123,6 +123,23 @@ clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", "Relocatable external references, non-relocatable code"), clEnumValEnd)); + + cl::opt + CMModel("code-model", + cl::desc("Choose code model"), + cl::init(CodeModel::JITDefault), + cl::values(clEnumValN(CodeModel::JITDefault, "default", + "Target default JIT code model"), + clEnumValN(CodeModel::Small, "small", + "Small code model"), + clEnumValN(CodeModel::Kernel, "kernel", + "Kernel code model"), + clEnumValN(CodeModel::Medium, "medium", + "Medium code model"), + clEnumValN(CodeModel::Large, "large", + "Large code model"), + clEnumValEnd)); + } static ExecutionEngine *EE = 0; @@ -180,6 +197,7 @@ builder.setMCPU(MCPU); builder.setMAttrs(MAttrs); builder.setRelocationModel(RelocModel); + builder.setCodeModel(CMModel); builder.setErrorStr(&ErrorMsg); builder.setEngineKind(ForceInterpreter ? EngineKind::Interpreter Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135580&r1=135579&r2=135580&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jul 20 02:51:56 2011 @@ -128,6 +128,22 @@ "Relocatable external references, non-relocatable code"), clEnumValEnd)); +static cl::opt +CMModel("code-model", + cl::desc("Choose code model"), + cl::init(CodeModel::Default), + cl::values(clEnumValN(CodeModel::Default, "default", + "Target default code model"), + clEnumValN(CodeModel::Small, "small", + "Small code model"), + clEnumValN(CodeModel::Kernel, "kernel", + "Kernel code model"), + clEnumValN(CodeModel::Medium, "medium", + "Medium code model"), + clEnumValN(CodeModel::Large, "large", + "Large code model"), + clEnumValEnd)); + static cl::opt NoInitialTextSection("n", cl::desc("Don't assume assembly file starts " "in the text section")); @@ -339,7 +355,8 @@ OwningPtr TM(TheTarget->createTargetMachine(TripleName, MCPU, FeaturesStr, - RelocModel)); + RelocModel, + CMModel)); if (!TM) { errs() << ProgName << ": error: could not create target for triple '" From jay.foad at gmail.com Wed Jul 20 03:15:21 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 20 Jul 2011 08:15:21 -0000 Subject: [llvm-commits] [llvm] r135581 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110720081521.8E1892A6C12E@llvm.org> Author: foad Date: Wed Jul 20 03:15:21 2011 New Revision: 135581 URL: http://llvm.org/viewvc/llvm-project?rev=135581&view=rev Log: Fix a GCC warning. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135581&r1=135580&r2=135581&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jul 20 03:15:21 2011 @@ -240,8 +240,8 @@ InsertPt = InsertBB->getTerminator(); } assert(InsertPt && "Missing phi operand"); - assert(!isa(Def) || - DT->dominates(cast(Def), InsertPt) && + assert((!isa(Def) || + DT->dominates(cast(Def), InsertPt)) && "def does not dominate all uses"); return InsertPt; } From grosser at fim.uni-passau.de Wed Jul 20 04:29:36 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 20 Jul 2011 09:29:36 -0000 Subject: [llvm-commits] [zorg] r135582 - /zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Message-ID: <20110720092936.AF0482A6C12D@llvm.org> Author: grosser Date: Wed Jul 20 04:29:36 2011 New Revision: 135582 URL: http://llvm.org/viewvc/llvm-project?rev=135582&view=rev Log: Retry if fetching from git fails. Fetching from the isl and cloog repositories hosted at repo.or.cz fails once in a while, because of random connection problems. Just retry. Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=135582&r1=135581&r2=135582&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Wed Jul 20 04:29:36 2011 @@ -18,12 +18,14 @@ f.addStep(Git(repourl='git://repo.or.cz/cloog.git', mode='update', workdir=cloog_srcdir, - alwaysUseLatest=True)) + alwaysUseLatest=True, + retry=(30, 10)) # Get isl f.addStep(Git(repourl='git://repo.or.cz/isl.git', mode='update', workdir=isl_srcdir, - alwaysUseLatest=True)) + alwaysUseLatest=True), + retry=(30, 10)) # Build isl f.addStep(ShellCommand(name="autogen-isl", command=["./autogen.sh"], From stoklund at 2pi.dk Wed Jul 20 10:12:17 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 08:12:17 -0700 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: On Jul 19, 2011, at 4:18 PM, NAKAMURA Takumi wrote: > I don't think using "git-svn rebase -l" would be simple. > git-svn stuff should be used to interact to svn repo. > > It would be enough "git pull" instead of "git fetch origin; git svn rebase -l". > (.rev_map is not needed to be up-to-date unless git-svn command would be used) Good point. If you can work with Jeffrey to come up with better instructions, that would be great. Just make sure they are newbie-proof. > At committing, git-svn rebase could be used. > $ git svn rebase -l > $ git svn dcommit > Also git-svn dcommit can update .rev_map, We can use "git pull > --rebase" instead of "git svn rebase -l". > > BTW, setting up authorsfile might be pain, but it should reduce > accidental undesirable committing by git-svn fetch. (Please consider, > what would happen if "-l" were missed on executing "git-svn rebase"?) For those who don't know, the problem is that 'git svn dcommit' will create a different local commit hash than the git mirror if the two log messages are not exactly identical. Since the log message includes the committer's name and email, those must be identical as well. After committing, you need to pull from the git mirror to get the canonical hash. I don't like any solution that depends on using an author file. It is simply too fragile to try to produce the same SHA-1 on the server and locally by having identical author files. Please make sure your instructions deal with that issue in a robust way. Thanks, /jakob From eli.friedman at gmail.com Wed Jul 20 10:19:08 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 08:19:08 -0700 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: On Tue, Jul 19, 2011 at 3:56 PM, David A. Greene wrote: > Eli Friedman writes: > >> On Tue, Jul 19, 2011 at 2:11 PM, David A. Greene wrote: >>> Eli Friedman writes: >>> >>>> On Tue, Jul 19, 2011 at 1:11 PM, David Greene wrote: >>>> This is unsafe in general; TableGen might never see the string >>>> "<<>>", but you can't assume arbitrary code using this >>>> header will not see it. >>> >>> True, but it's highly unlikely. ?Do you have a better alternative? ?I >>> certainly would like to do this the Right Way. >> >> Use std::map? ?It's not like performance matters here. > > Well, Chris suggested using DenseMap with std::string and this is all I > could come up with. ?Originally I used a FoldingSet but several people > objected due to performance concerns. ?So I'm a bit stuck. ?:( If you must, make a custom TableGenStringKey class (my name not really suggested) containing an std::string, and implement DenseMapInfo on that. -Eli From stoklund at 2pi.dk Wed Jul 20 10:26:25 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 08:26:25 -0700 Subject: [llvm-commits] [PATCH 02/20] [AVX] Remove Mutating Members from Inits In-Reply-To: References: Message-ID: <8CEDA0FF-6683-4ACE-95BB-10063A977150@2pi.dk> On Jul 19, 2011, at 1:11 PM, David Greene wrote: > Delete all member functions that modify Init state. This is in > preparation for making Inits const everywhere and finally, converting > them to FoldingSetNodes. Thanks, David. You have a lot of explicit ArrayRef constructor calls. That shouldn't be necessary. You should be getting implicit conversions. And please use the new makeArrayRef when that doesn't work. > + Init *NewBits[1] = { VI }; This should not be necessary, ArrayRef has a single-element constructor. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110720/0a655700/attachment-0001.html From stoklund at 2pi.dk Wed Jul 20 10:32:23 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 08:32:23 -0700 Subject: [llvm-commits] [PATCH 03/20] [AVX] Remove non-const Iterators In-Reply-To: <354aba23155343587d71eb8b0b3425b5f0170702.1311100069.git.dag@cray.com> References: <354aba23155343587d71eb8b0b3425b5f0170702.1311100069.git.dag@cray.com> Message-ID: On Jul 19, 2011, at 1:11 PM, David Greene wrote: > - ListInit *Result = new ListInit(LHSl->begin()+1, LHSl->end(), > + ListInit::const_iterator begin = LHSl->begin()+1; > + ListInit::const_iterator end = LHSl->end(); > + // We can't pass these iterators directly to ArrayRef because > + // they are not convertible to Init **. Fortunately, > + // RandomAccessIterator::operator * is guaranteed to return an > + // lvalue. > + ListInit *Result = new ListInit(ArrayRef(&*begin, end - begin), > LHSl->getType()); That comment is really scary. ArrayRef requires elements to be laid out continuously in memory. A random access iterator doesn't guarantee that. Think std::deque. How about adding a ListInit method that returns an ArrayRef instead? /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110720/f26786af/attachment.html From stoklund at 2pi.dk Wed Jul 20 10:37:16 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 08:37:16 -0700 Subject: [llvm-commits] [PATCH 06/20] [AVX] Unique UnsetInit In-Reply-To: <7a8502122946b84eaa48a2c866d5ee9200c3f504.1311100070.git.dag@cray.com> References: <7a8502122946b84eaa48a2c866d5ee9200c3f504.1311100070.git.dag@cray.com> Message-ID: <8E96158E-6258-466D-B7A6-16123E19B664@2pi.dk> On Jul 19, 2011, at 1:11 PM, David Greene wrote: > Keep only one UnsetInit around. > --- > utils/TableGen/Record.cpp | 6 +++++- > 1 files changed, 5 insertions(+), 1 deletions(-) > > diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp > index 3339a22..72b1f5f 100644 > --- oldutils/TableGen/Record.cpp > +++ newutils/TableGen/Record.cpp > @@ -397,7 +397,11 @@ RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { > void Init::dump() const { return print(errs()); } > > const UnsetInit *UnsetInit::get() { > - return new UnsetInit; > + static const UnsetInit *TheInit = 0; > + if (TheInit == 0) > + TheInit = new UnsetInit(); > + > + return TheInit; > } Why use a pointer instead of just a static object? /jakob From stoklund at 2pi.dk Wed Jul 20 10:43:43 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 08:43:43 -0700 Subject: [llvm-commits] [PATCH 09/20] [AVX] Make IntInit Unique In-Reply-To: References: Message-ID: <98D73C97-E711-4466-9A59-22327EFF7BA1@2pi.dk> On Jul 19, 2011, at 1:11 PM, David Greene wrote: > Use a DenseMap to make sure only one IntInit of any value exists. > --- > utils/TableGen/Record.cpp | 14 +++++++++++++- > 1 files changed, 13 insertions(+), 1 deletions(-) > > diff --git oldutils/TableGen/Record.cpp newutils/TableGen/Record.cpp > index 4c019d3..dda0b71 100644 > --- oldutils/TableGen/Record.cpp > +++ newutils/TableGen/Record.cpp > @@ -491,7 +491,19 @@ const Init *BitsInit::resolveReferences(Record &R, const RecordVal *RV) const { > } > > const IntInit *IntInit::get(int64_t V) { > - return new IntInit(V); > + typedef DenseMap Pool; > + static Pool ThePool; > + > + Pool::iterator Result = ThePool.find(V); > + > + if (Result == ThePool.end()) { > + IntInit *New = new IntInit(V); > + bool Inserted = false; > + tie(Result, Inserted) = ThePool.insert(std::make_pair(V, New)); > + assert(Inserted && "Did not insert new Init into pool!"); > + } > + > + return Result->second; > } This pattern is faster and simpler: const IntInit *&I = ThePool[V]; if (!I) I = new IntInit(V); return I; /jakob From dag at cray.com Wed Jul 20 10:59:34 2011 From: dag at cray.com (David A. Greene) Date: Wed, 20 Jul 2011 10:59:34 -0500 Subject: [llvm-commits] [PATCH 06/20] [AVX] Unique UnsetInit In-Reply-To: <8E96158E-6258-466D-B7A6-16123E19B664@2pi.dk> (Jakob Stoklund Olesen's message of "Wed, 20 Jul 2011 10:37:16 -0500") References: <7a8502122946b84eaa48a2c866d5ee9200c3f504.1311100070.git.dag@cray.com> <8E96158E-6258-466D-B7A6-16123E19B664@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: >> const UnsetInit *UnsetInit::get() { >> - return new UnsetInit; >> + static const UnsetInit *TheInit = 0; >> + if (TheInit == 0) >> + TheInit = new UnsetInit(); >> + >> + return TheInit; >> } > > Why use a pointer instead of just a static object? Already fixed. Someone beat you to it. :) -Dave From dag at cray.com Wed Jul 20 11:01:30 2011 From: dag at cray.com (David A. Greene) Date: Wed, 20 Jul 2011 11:01:30 -0500 Subject: [llvm-commits] [PATCH 09/20] [AVX] Make IntInit Unique In-Reply-To: <98D73C97-E711-4466-9A59-22327EFF7BA1@2pi.dk> (Jakob Stoklund Olesen's message of "Wed, 20 Jul 2011 10:43:43 -0500") References: <98D73C97-E711-4466-9A59-22327EFF7BA1@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: >> const IntInit *IntInit::get(int64_t V) { >> - return new IntInit(V); >> + typedef DenseMap Pool; >> + static Pool ThePool; >> + >> + Pool::iterator Result = ThePool.find(V); >> + >> + if (Result == ThePool.end()) { >> + IntInit *New = new IntInit(V); >> + bool Inserted = false; >> + tie(Result, Inserted) = ThePool.insert(std::make_pair(V, New)); >> + assert(Inserted && "Did not insert new Init into pool!"); >> + } >> + >> + return Result->second; >> } > > This pattern is faster and simpler: > > const IntInit *&I = ThePool[V]; > if (!I) I = new IntInit(V); > return I; Ok. -Dave From dag at cray.com Wed Jul 20 11:02:16 2011 From: dag at cray.com (David A. Greene) Date: Wed, 20 Jul 2011 11:02:16 -0500 Subject: [llvm-commits] [PATCH 02/20] [AVX] Remove Mutating Members from Inits In-Reply-To: <8CEDA0FF-6683-4ACE-95BB-10063A977150@2pi.dk> (Jakob Stoklund Olesen's message of "Wed, 20 Jul 2011 10:26:25 -0500") References: <8CEDA0FF-6683-4ACE-95BB-10063A977150@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: > On Jul 19, 2011, at 1:11 PM, David Greene wrote: > > Delete all member functions that modify Init state. This is in > preparation for making Inits const everywhere and finally, converting > them to FoldingSetNodes. > > Thanks, David. > > You have a lot of explicit ArrayRef constructor calls. That shouldn't be necessary. You should be getting implicit conversions. I'll check that out. Certainly I won't get implicit conversions for iterator pairs. :) > And please use the new makeArrayRef when that doesn't work. > > + Init *NewBits[1] = { VI }; > > This should not be necessary, ArrayRef has a single-element constructor. Urk. Missed that one. Thanks for the pointer. -Dave From dag at cray.com Wed Jul 20 11:02:31 2011 From: dag at cray.com (David A. Greene) Date: Wed, 20 Jul 2011 11:02:31 -0500 Subject: [llvm-commits] [PATCH 03/20] [AVX] Remove non-const Iterators In-Reply-To: (Jakob Stoklund Olesen's message of "Wed, 20 Jul 2011 10:32:23 -0500") References: <354aba23155343587d71eb8b0b3425b5f0170702.1311100069.git.dag@cray.com> Message-ID: Jakob Stoklund Olesen writes: > On Jul 19, 2011, at 1:11 PM, David Greene wrote: > > - ListInit *Result = new ListInit(LHSl->begin()+1, LHSl->end(), > + ListInit::const_iterator begin = LHSl->begin()+1; > + ListInit::const_iterator end = LHSl->end(); > + // We can't pass these iterators directly to ArrayRef because > + // they are not convertible to Init **. Fortunately, > + // RandomAccessIterator::operator * is guaranteed to return an > + // lvalue. > + ListInit *Result = new ListInit(ArrayRef(&*begin, end - begin), > LHSl->getType()); > > That comment is really scary. ArrayRef requires elements to be laid out continuously in memory. A random access iterator doesn't guarantee that. > Think std::deque. > > How about adding a ListInit method that returns an ArrayRef instead? Makes sense. Thanks! -Dave From greened at obbligato.org Wed Jul 20 11:03:57 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 11:03:57 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: (Eli Friedman's message of "Wed, 20 Jul 2011 08:19:08 -0700") References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: Eli Friedman writes: >> Well, Chris suggested using DenseMap with std::string and this is all I >> could come up with. ?Originally I used a FoldingSet but several people >> objected due to performance concerns. ?So I'm a bit stuck. ?:( > > If you must, make a custom TableGenStringKey class (my name not really > suggested) containing an std::string, and implement DenseMapInfo on > that. Ok, that's safer. Good idea. -Dave From evan.cheng at apple.com Wed Jul 20 11:03:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 16:03:49 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135588 - in /llvm-gcc-4.2/trunk/gcc: config/i386/i386.h llvm-backend.cpp Message-ID: <20110720160349.488DE2A6C12D@llvm.org> Author: evancheng Date: Wed Jul 20 11:03:49 2011 New Revision: 135588 URL: http://llvm.org/viewvc/llvm-project?rev=135588&view=rev Log: Unbreak llvm-c build. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=135588&r1=135587&r2=135588&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Wed Jul 20 11:03:49 2011 @@ -3938,28 +3938,30 @@ #define LLVM_CANONICAL_ADDRESS_CONSTRAINTS "im" /* Propagate code model setting to backend */ +#define LLVM_SET_CODE_MODEL(CMModel) \ + switch (ix86_cmodel) { \ + default: \ + sorry ("code model %<%s%> not supported yet", \ + ix86_cmodel_string); \ + break; \ + case CM_SMALL: \ + case CM_SMALL_PIC: \ + CMModel = llvm::CodeModel::Small; \ + break; \ + case CM_KERNEL: \ + CMModel = llvm::CodeModel::Kernel; \ + break; \ + case CM_MEDIUM: \ + case CM_MEDIUM_PIC: \ + CMModel = llvm::CodeModel::Medium; \ + break; \ + case CM_32: \ + CMModel = llvm::CodeModel::Large; \ + break; \ + } + #define LLVM_SET_MACHINE_OPTIONS(argvec) \ do { \ - switch (ix86_cmodel) { \ - default: \ - sorry ("code model %<%s%> not supported yet", \ - ix86_cmodel_string); \ - break; \ - case CM_SMALL: \ - case CM_SMALL_PIC: \ - argvec.push_back("--code-model=small"); \ - break; \ - case CM_KERNEL: \ - argvec.push_back("--code-model=kernel"); \ - break; \ - case CM_MEDIUM: \ - case CM_MEDIUM_PIC: \ - argvec.push_back("--code-model=medium"); \ - break; \ - case CM_32: \ - argvec.push_back("--code-model=default"); \ - break; \ - } \ /* A value of 3 in flag_omit_frame_pointer implies \ omitting leaf frame pointers only. */ \ if (flag_omit_frame_pointer == 3) \ Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=135588&r1=135587&r2=135588&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Jul 20 11:03:49 2011 @@ -414,6 +414,7 @@ #undef DoInit2 Reloc::Model RelocModel = Reloc::Default; + CodeModel::Model CMModel = CodeModel::Default; // Initialize LLVM options. std::vector Args; @@ -436,6 +437,9 @@ #ifdef LLVM_SET_RELOC_MODEL LLVM_SET_RELOC_MODEL(RelocModel); #endif +#ifdef LLVM_SET_CODE_MODEL + LLVM_SET_CODE_MODEL(CMModel); +#endif if (time_report) Args.push_back("--time-passes"); @@ -561,7 +565,7 @@ FeatureStr = Features.getString(); TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr, - RelocModel); + RelocModel, CMModel); TheTarget->setMCUseLoc(false); TheTarget->setMCUseCFI(false); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); From stoklund at 2pi.dk Wed Jul 20 11:28:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 09:28:21 -0700 Subject: [llvm-commits] [PATCH 12/20] [AVX] Make ListInits Unique In-Reply-To: References: Message-ID: <8D136665-E330-48F9-B7DA-D7A92E8A07ED@2pi.dk> On Jul 19, 2011, at 1:11 PM, David Greene wrote: > Make ListInit a FastFoldingSetNode to ensure ListInits are unique > and only created once. This will be important for AVX as lists > will be used extensively to pass generic patterns, prefix > information and other things to lower-level pattern-generation > classes. I don't really understand this approach. The FastFoldingSetNode base class adds 160 bytes of overhead, and it is guaranteed to at least double the memory used by a ListInit. Now that you have a FoldingSet per Init subclass, you can just provide a Profile method instead. That reduces the overhead to just a pointer. See APFloat for a simple example. /jakob From evan.cheng at apple.com Wed Jul 20 11:31:10 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 16:31:10 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135589 - /llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Message-ID: <20110720163110.43D562A6C12D@llvm.org> Author: evancheng Date: Wed Jul 20 11:31:10 2011 New Revision: 135589 URL: http://llvm.org/viewvc/llvm-project?rev=135589&view=rev Log: CM_32 means default code mode. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=135589&r1=135588&r2=135589&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Wed Jul 20 11:31:10 2011 @@ -3955,9 +3955,6 @@ case CM_MEDIUM_PIC: \ CMModel = llvm::CodeModel::Medium; \ break; \ - case CM_32: \ - CMModel = llvm::CodeModel::Large; \ - break; \ } #define LLVM_SET_MACHINE_OPTIONS(argvec) \ From greened at obbligato.org Wed Jul 20 11:58:25 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 11:58:25 -0500 Subject: [llvm-commits] [PATCH 01/20] Add DenseMapInfo for std::string In-Reply-To: (Eli Friedman's message of "Wed, 20 Jul 2011 08:19:08 -0700") References: <681f45456fda14bfa923356d33c2b52fbd2da25a.1311100069.git.dag@cray.com> Message-ID: Eli Friedman writes: > If you must, make a custom TableGenStringKey class (my name not really > suggested) containing an std::string, and implement DenseMapInfo on > that. Done. -Dave From echristo at apple.com Wed Jul 20 12:04:49 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 20 Jul 2011 17:04:49 -0000 Subject: [llvm-commits] [llvm] r135592 - in /llvm/trunk: configure include/llvm/Config/config.h.in Message-ID: <20110720170449.C746B2A6C12D@llvm.org> Author: echristo Date: Wed Jul 20 12:04:49 2011 New Revision: 135592 URL: http://llvm.org/viewvc/llvm-project?rev=135592&view=rev Log: Regenerate configure and friends for Chad. Modified: llvm/trunk/configure llvm/trunk/include/llvm/Config/config.h.in Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=135592&r1=135591&r2=135592&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Wed Jul 20 12:04:49 2011 @@ -1471,6 +1471,8 @@ 64 bit multilib directory. --with-binutils-include Specify path to binutils/include/ containing plugin-api.h file for gold plugin. + --with-bug-report-url Specify the URL where bug reports should be + submitted (default=http://llvm.org) --with-tclinclude directory where tcl headers are --with-llvmcc= Choose the LLVM capable compiler to use (llvm-gcc, clang, or none; default=check) @@ -5526,6 +5528,20 @@ fi fi + +# Check whether --with-bug-report-url was given. +if test "${with_bug_report_url+set}" = set; then + withval=$with_bug_report_url; +else + withval="http://llvm.org" +fi + + +cat >>confdefs.h <<_ACEOF +#define BUG_REPORT_URL "$withval" +_ACEOF + + # Check whether --enable-libffi was given. if test "${enable_libffi+set}" = set; then enableval=$enable_libffi; case "$enableval" in @@ -11602,7 +11618,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: Jakob, 2011/7/21 Jakob Stoklund Olesen : >> BTW, setting up authorsfile might be pain, but it should reduce >> accidental undesirable committing by git-svn fetch. (Please consider, >> what would happen if "-l" were missed on executing "git-svn rebase"?) > > For those who don't know, the problem is that 'git svn dcommit' will create a different local commit hash than the git mirror if the two log messages are not exactly identical. Since the log message includes the committer's name and email, those must be identical as well. After committing, you need to pull from the git mirror to get the canonical hash. > > I don't like any solution that depends on using an author file. It is simply too fragile to try to produce the same SHA-1 on the server and locally by having identical author files. > > Please make sure your instructions deal with that issue in a robust way. I don't assume the person should have the "authorsfile" identical to llvm.org/git. Simply, each authorsfile may have one line, his own entry. For example for me, chapuni = NAKAMURA Takumi git-svn fetch (and fetching triggered by git-svn dcommit) will reject (and stop) 3rd person's commits. Then, the person can know he would need "git-pull". I guess it could be also newbie-proof, ... as far as the line in authorsfile would be correct. As an option, it may be described in the document, I think. Still pain to us? Thank you. ...Takumi From mcrosier at apple.com Wed Jul 20 12:12:45 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 20 Jul 2011 10:12:45 -0700 Subject: [llvm-commits] [llvm] r135592 - in /llvm/trunk: configure include/llvm/Config/config.h.in In-Reply-To: <20110720170449.C746B2A6C12D@llvm.org> References: <20110720170449.C746B2A6C12D@llvm.org> Message-ID: <77C90345-94C3-407A-8C6B-972FCDD6B3C6@apple.com> Thanks Eric! Chad On Jul 20, 2011, at 10:04 AM, Eric Christopher wrote: > Author: echristo > Date: Wed Jul 20 12:04:49 2011 > New Revision: 135592 > > URL: http://llvm.org/viewvc/llvm-project?rev=135592&view=rev > Log: > Regenerate configure and friends for Chad. > > Modified: > llvm/trunk/configure > llvm/trunk/include/llvm/Config/config.h.in > > Modified: llvm/trunk/configure > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=135592&r1=135591&r2=135592&view=diff > ============================================================================== > --- llvm/trunk/configure (original) > +++ llvm/trunk/configure Wed Jul 20 12:04:49 2011 > @@ -1471,6 +1471,8 @@ > 64 bit multilib directory. > --with-binutils-include Specify path to binutils/include/ containing > plugin-api.h file for gold plugin. > + --with-bug-report-url Specify the URL where bug reports should be > + submitted (default=http://llvm.org) > --with-tclinclude directory where tcl headers are > --with-llvmcc= Choose the LLVM capable compiler to use (llvm-gcc, > clang, or none; default=check) > @@ -5526,6 +5528,20 @@ > fi > fi > > + > +# Check whether --with-bug-report-url was given. > +if test "${with_bug_report_url+set}" = set; then > + withval=$with_bug_report_url; > +else > + withval="http://llvm.org" > +fi > + > + > +cat >>confdefs.h <<_ACEOF > +#define BUG_REPORT_URL "$withval" > +_ACEOF > + > + > # Check whether --enable-libffi was given. > if test "${enable_libffi+set}" = set; then > enableval=$enable_libffi; case "$enableval" in > @@ -11602,7 +11618,7 @@ > lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 > lt_status=$lt_dlunknown > cat > conftest.$ac_ext < -#line 11591 "configure" > +#line 11621 "configure" > #include "confdefs.h" > > #if HAVE_DLFCN_H > > Modified: llvm/trunk/include/llvm/Config/config.h.in > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=135592&r1=135591&r2=135592&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Config/config.h.in (original) > +++ llvm/trunk/include/llvm/Config/config.h.in Wed Jul 20 12:04:49 2011 > @@ -3,6 +3,9 @@ > #ifndef CONFIG_H > #define CONFIG_H > > +/* Bug report URL. */ > +#undef BUG_REPORT_URL > + > /* Relative directory for resource files */ > #undef CLANG_RESOURCE_DIR > > @@ -576,7 +579,7 @@ > /* LLVM name for the native MCAsmInfo init function, if available */ > #undef LLVM_NATIVE_MCASMINFO > > -/* LLVM name for the native MCCODEGENInfo init function, if available */ > +/* LLVM name for the native MCCodeGenInfo init function, if available */ > #undef LLVM_NATIVE_MCCODEGENINFO > > /* LLVM name for the native Target init function, if available */ > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Wed Jul 20 13:07:58 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 20 Jul 2011 11:07:58 -0700 Subject: [llvm-commits] [llvm] r135580 - in /llvm/trunk: include/llvm/ExecutionEngine/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/ExecutionEngine/ lib/ExecutionEngine/JIT/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/MCTargetDesc/ lib/Target/MSP430/ lib/Target/MS... In-Reply-To: <20110720075158.298FC312800A@llvm.org> References: <20110720075158.298FC312800A@llvm.org> Message-ID: <216E3B20-82FE-4B0F-B9C5-FD4C76927C03@apple.com> On Jul 20, 2011, at 12:51 AM, Evan Cheng wrote: > - Introduce JITDefault code model. This tells targets to set different default > code model for JIT. This eliminates the ugly hack in TargetMachine where > code model is changed after construction. Yay. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110720/c50e4b9b/attachment.html From benny.kra at googlemail.com Wed Jul 20 13:13:23 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 20 Jul 2011 18:13:23 -0000 Subject: [llvm-commits] [llvm] r135594 - /llvm/trunk/lib/MC/MCObjectFileInfo.cpp Message-ID: <20110720181323.59C0F2A6C12D@llvm.org> Author: d0k Date: Wed Jul 20 13:13:23 2011 New Revision: 135594 URL: http://llvm.org/viewvc/llvm-project?rev=135594&view=rev Log: Initialize the EHFrameSection pointer to zero. This should fix the spurious buildbot errors. Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=135594&r1=135593&r2=135594&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Jul 20 13:13:23 2011 @@ -454,6 +454,7 @@ CommDirectiveSupportsAlignment = true; SupportsWeakOmittedEHFrame = true; IsFunctionEHFrameSymbolPrivate = true; + EHFrameSection = 0; Triple T(TT); Triple::ArchType Arch = T.getArch(); From eli.friedman at gmail.com Wed Jul 20 13:14:34 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 18:14:34 -0000 Subject: [llvm-commits] [llvm] r135595 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/X86/widen_shuffle-1.ll Message-ID: <20110720181434.3410C2A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 13:14:33 2011 New Revision: 135595 URL: http://llvm.org/viewvc/llvm-project?rev=135595&view=rev Log: PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=135595&r1=135594&r2=135595&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Jul 20 13:14:33 2011 @@ -1661,6 +1661,7 @@ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); unsigned WidenNumElts = WidenVT.getVectorNumElements(); + unsigned NumInElts = InVT.getVectorNumElements(); unsigned NumOperands = N->getNumOperands(); bool InputWidened = false; // Indicates we need to widen the input. @@ -1686,17 +1687,17 @@ if (N->getOperand(i).getOpcode() != ISD::UNDEF) break; - if (i > NumOperands) + if (i == NumOperands) // Everything but the first operand is an UNDEF so just return the // widened first operand. return GetWidenedVector(N->getOperand(0)); if (NumOperands == 2) { // Replace concat of two operands with a shuffle. - SmallVector MaskOps(WidenNumElts); - for (unsigned i=0; i < WidenNumElts/2; ++i) { + SmallVector MaskOps(WidenNumElts, -1); + for (unsigned i = 0; i < NumInElts; ++i) { MaskOps[i] = i; - MaskOps[i+WidenNumElts/2] = i+WidenNumElts; + MaskOps[i + NumInElts] = i + WidenNumElts; } return DAG.getVectorShuffle(WidenVT, dl, GetWidenedVector(N->getOperand(0)), @@ -1708,7 +1709,6 @@ // Fall back to use extracts and build vector. EVT EltVT = WidenVT.getVectorElementType(); - unsigned NumInElts = InVT.getVectorNumElements(); SmallVector Ops(WidenNumElts); unsigned Idx = 0; for (unsigned i=0; i < NumOperands; ++i) { Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=135595&r1=135594&r2=135595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Wed Jul 20 13:14:33 2011 @@ -30,6 +30,7 @@ ; opA with opB, the DAG will produce new operations with opA. define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind { entry: +; CHECK: shuf3: ; CHECK: pshufd %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> @@ -46,3 +47,10 @@ ret void } +; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS +define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone { +; CHECK: shuf4: +; CHECK: punpckldq + %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> + ret <8 x i8> %vshuf +} From stoklund at 2pi.dk Wed Jul 20 13:19:05 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 11:19:05 -0700 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: <20C4B91C-5F3E-4729-B6EA-A9AF55629AA9@2pi.dk> On Jul 20, 2011, at 10:08 AM, NAKAMURA Takumi wrote: > Jakob, > > 2011/7/21 Jakob Stoklund Olesen : >>> BTW, setting up authorsfile might be pain, but it should reduce >>> accidental undesirable committing by git-svn fetch. (Please consider, >>> what would happen if "-l" were missed on executing "git-svn rebase"?) >> >> For those who don't know, the problem is that 'git svn dcommit' will create a different local commit hash than the git mirror if the two log messages are not exactly identical. Since the log message includes the committer's name and email, those must be identical as well. After committing, you need to pull from the git mirror to get the canonical hash. >> >> I don't like any solution that depends on using an author file. It is simply too fragile to try to produce the same SHA-1 on the server and locally by having identical author files. >> >> Please make sure your instructions deal with that issue in a robust way. > > I don't assume the person should have the "authorsfile" identical to > llvm.org/git. > Simply, each authorsfile may have one line, his own entry. For example for me, > > chapuni = NAKAMURA Takumi > > git-svn fetch (and fetching triggered by git-svn dcommit) will reject > (and stop) 3rd person's commits. > Then, the person can know he would need "git-pull". What happens if your spell your name differently that the server does? From grosbach at apple.com Wed Jul 20 13:20:32 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 18:20:32 -0000 Subject: [llvm-commits] [llvm] r135596 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s Message-ID: <20110720182032.2C6B92A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 13:20:31 2011 New Revision: 135596 URL: http://llvm.org/viewvc/llvm-project?rev=135596&view=rev Log: ARM assembly parsing of MUL instruction. Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135596&r1=135595&r2=135596&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 20 13:20:31 2011 @@ -1977,7 +1977,8 @@ // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. - if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") { + if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && + Mnemonic != "muls") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135596&r1=135595&r2=135596&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 20 13:20:31 2011 @@ -812,6 +812,20 @@ @ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] @------------------------------------------------------------------------------ +@ MUL + at ------------------------------------------------------------------------------ + + mul r5, r6, r7 + muls r5, r6, r7 + mulgt r5, r6, r7 + mulsle r5, r6, r7 + +@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0] +@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] +@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] +@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} From grosbach at apple.com Wed Jul 20 13:37:08 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 18:37:08 -0000 Subject: [llvm-commits] [llvm] r135599 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110720183708.400722A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 13:37:08 2011 New Revision: 135599 URL: http://llvm.org/viewvc/llvm-project?rev=135599&view=rev Log: ARM parsing and encoding tests for MVN Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135599&r1=135598&r2=135599&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 20 13:37:08 2011 @@ -825,6 +825,63 @@ @ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] @ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] + + at ------------------------------------------------------------------------------ +@ MVN (immediate) + at ------------------------------------------------------------------------------ + mvn r3, #7 + mvn r4, #0xff0 + mvn r5, #0xff0000 + mvns r3, #7 + mvneq r4, #0xff0 + mvnseq r5, #0xff0000 + +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3] +@ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3] +@ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3] +@ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03] +@ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03] + + + at ------------------------------------------------------------------------------ +@ MVN (register) + at ------------------------------------------------------------------------------ + mvn r2, r3 + mvns r2, r3 + mvn r5, r6, lsl #19 + mvn r5, r6, lsr #9 + mvn r5, r6, asr #4 + mvn r5, r6, ror #6 + mvn r5, r6, rrx + mvneq r2, r3 + mvnseq r2, r3, lsl #10 + +@ CHECK: mvn r2, r3 @ encoding: [0x03,0x20,0xe0,0xe1] +@ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1] +@ CHECK: mvn r5, r6, lsl #19 @ encoding: [0x86,0x59,0xe0,0xe1] +@ CHECK: mvn r5, r6, lsr #9 @ encoding: [0xa6,0x54,0xe0,0xe1] +@ CHECK: mvn r5, r6, asr #4 @ encoding: [0x46,0x52,0xe0,0xe1] +@ CHECK: mvn r5, r6, ror #6 @ encoding: [0x66,0x53,0xe0,0xe1] +@ CHECK: mvn r5, r6, rrx @ encoding: [0x66,0x50,0xe0,0xe1] +@ CHECK: mvneq r2, r3 @ encoding: [0x03,0x20,0xe0,0x01] +@ CHECK: mvnseq r2, r3, lsl #10 @ encoding: [0x03,0x25,0xf0,0x01] + + + at ------------------------------------------------------------------------------ +@ MVN (shifted register) + at ------------------------------------------------------------------------------ + mvn r5, r6, lsl r7 + mvns r5, r6, lsr r7 + mvngt r5, r6, asr r7 + mvnslt r5, r6, ror r7 + +@ CHECK: mvn r5, r6, lsl r7 @ encoding: [0x16,0x57,0xe0,0xe1] +@ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1] +@ CHECK: mvngt r5, r6, asr r7 @ encoding: [0x56,0x57,0xe0,0xc1] +@ CHECK: mvnslt r5, r6, ror r7 @ encoding: [0x76,0x57,0xf0,0xb1] + + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ From grosbach at apple.com Wed Jul 20 13:39:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 18:39:38 -0000 Subject: [llvm-commits] [llvm] r135600 - in /llvm/trunk/test/MC/ARM: arm_instructions.s basic-arm-instructions.s Message-ID: <20110720183938.AC8532A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 13:39:38 2011 New Revision: 135600 URL: http://llvm.org/viewvc/llvm-project?rev=135600&view=rev Log: Consolidate ARM NOP encoding test. Modified: llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135600&r1=135599&r2=135600&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Wed Jul 20 13:39:38 2011 @@ -1,13 +1,5 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s -@ CHECK: nop -@ CHECK: encoding: [0x00,0xf0,0x20,0xe3] - nop - -@ CHECK: nopeq -@ CHECK: encoding: [0x00,0xf0,0x20,0x03] - nopeq - @ CHECK: trap @ CHECK: encoding: [0xfe,0xde,0xff,0xe7] trap @@ -109,9 +101,6 @@ @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] yield -@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] - nop - @ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1] cpsie aif Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135600&r1=135599&r2=135600&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 20 13:39:38 2011 @@ -881,6 +881,15 @@ @ CHECK: mvngt r5, r6, asr r7 @ encoding: [0x56,0x57,0xe0,0xc1] @ CHECK: mvnslt r5, r6, ror r7 @ encoding: [0x76,0x57,0xf0,0xb1] + at ------------------------------------------------------------------------------ +@ NOP + at ------------------------------------------------------------------------------ + nop + nopgt + +@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] +@ CHECK: nopgt @ encoding: [0x00,0xf0,0x20,0xc3] + @------------------------------------------------------------------------------ @ STM* From clattner at apple.com Wed Jul 20 13:44:52 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 20 Jul 2011 11:44:52 -0700 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: On Jul 20, 2011, at 8:12 AM, Jakob Stoklund Olesen wrote: > > On Jul 19, 2011, at 4:18 PM, NAKAMURA Takumi wrote: > >> I don't think using "git-svn rebase -l" would be simple. >> git-svn stuff should be used to interact to svn repo. >> >> It would be enough "git pull" instead of "git fetch origin; git svn rebase -l". >> (.rev_map is not needed to be up-to-date unless git-svn command would be used) > > Good point. > > If you can work with Jeffrey to come up with better instructions, that would be great. > > Just make sure they are newbie-proof. Wouldn't it be easier at some point to move llvm.org to git? -Chris From stoklund at 2pi.dk Wed Jul 20 13:47:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 20 Jul 2011 11:47:06 -0700 Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone of the LLVM git repositories In-Reply-To: References: <80718B42-483F-413F-A72D-067041C623E6@2pi.dk> Message-ID: <87D236DB-F1DB-490C-8044-7B02293996B6@2pi.dk> On Jul 20, 2011, at 11:44 AM, Chris Lattner wrote: > > On Jul 20, 2011, at 8:12 AM, Jakob Stoklund Olesen wrote: > >> >> On Jul 19, 2011, at 4:18 PM, NAKAMURA Takumi wrote: >> >>> I don't think using "git-svn rebase -l" would be simple. >>> git-svn stuff should be used to interact to svn repo. >>> >>> It would be enough "git pull" instead of "git fetch origin; git svn rebase -l". >>> (.rev_map is not needed to be up-to-date unless git-svn command would be used) >> >> Good point. >> >> If you can work with Jeffrey to come up with better instructions, that would be great. >> >> Just make sure they are newbie-proof. > > Wouldn't it be easier at some point to move llvm.org to git? Definitely. /jakob From grosbach at apple.com Wed Jul 20 13:48:53 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 18:48:53 -0000 Subject: [llvm-commits] [llvm] r135602 - in /llvm/trunk/test/MC/ARM: arm_instructions.s basic-arm-instructions.s Message-ID: <20110720184853.43ADB2A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 13:48:53 2011 New Revision: 135602 URL: http://llvm.org/viewvc/llvm-project?rev=135602&view=rev Log: Add parsing/encoding tests for ARM ORR instruction. Modified: llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135602&r1=135601&r2=135602&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Wed Jul 20 13:48:53 2011 @@ -42,12 +42,6 @@ @ CHECK: sbc r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0] sbc r1,r2,r3 -@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] - orr r1,r2,r3 - -@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] - orrs r1,r2,r3 - @ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] bic r1,r2,r3 Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135602&r1=135601&r2=135602&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 20 13:48:53 2011 @@ -892,6 +892,85 @@ @------------------------------------------------------------------------------ +@ ORR + at ------------------------------------------------------------------------------ + orr r4, r5, #0xf000 + orr r4, r5, r6 + orr r4, r5, r6, lsl #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, asr #5 + orr r4, r5, r6, ror #5 + orr r6, r7, r8, lsl r9 + orr r6, r7, r8, lsr r9 + orr r6, r7, r8, asr r9 + orr r6, r7, r8, ror r9 + orr r4, r5, r6, rrx + + @ destination register is optional + orr r5, #0xf000 + orr r4, r5 + orr r4, r5, lsl #5 + orr r4, r5, lsr #5 + orr r4, r5, lsr #5 + orr r4, r5, asr #5 + orr r4, r5, ror #5 + orr r6, r7, lsl r9 + orr r6, r7, lsr r9 + orr r6, r7, asr r9 + orr r6, r7, ror r9 + orr r4, r5, rrx + +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe1] +@ CHECK: orr r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe1] +@ CHECK: orr r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe1] + +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe1] +@ CHECK: orr r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe1] +@ CHECK: orr r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe1] + + orrseq r4, r5, #0xf000 + orrne r4, r5, r6 + orrseq r4, r5, r6, lsl #5 + orrlo r6, r7, r8, ror r9 + orrshi r4, r5, r6, rrx + orrcs r5, #0xf000 + orrseq r4, r5 + orrne r6, r7, asr r9 + orrslt r6, r7, ror r9 + orrsgt r4, r5, rrx + +@ CHECK: orrseq r4, r5, #61440 @ encoding: [0x0f,0x4a,0x95,0x03] +@ CHECK: orrne r4, r5, r6 @ encoding: [0x06,0x40,0x85,0x11] +@ CHECK: orrseq r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x95,0x01] +@ CHECK: orrlo r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0x31] +@ CHECK: orrshi r4, r5, r6, rrx @ encoding: [0x66,0x40,0x95,0x81] +@ CHECK: orrhs r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0x23] +@ CHECK: orrseq r4, r4, r5 @ encoding: [0x05,0x40,0x94,0x01] +@ CHECK: orrne r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0x11] +@ CHECK: orrslt r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x96,0xb1] +@ CHECK: orrsgt r4, r4, r5, rrx @ encoding: [0x65,0x40,0x94,0xc1] + + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} From dag at cray.com Wed Jul 20 13:51:46 2011 From: dag at cray.com (David A. Greene) Date: Wed, 20 Jul 2011 13:51:46 -0500 Subject: [llvm-commits] [PATCH 12/20] [AVX] Make ListInits Unique In-Reply-To: <8D136665-E330-48F9-B7DA-D7A92E8A07ED@2pi.dk> (Jakob Stoklund Olesen's message of "Wed, 20 Jul 2011 11:28:21 -0500") References: <8D136665-E330-48F9-B7DA-D7A92E8A07ED@2pi.dk> Message-ID: Jakob Stoklund Olesen writes: > Now that you have a FoldingSet per Init subclass, you can just provide > a Profile method instead. That reduces the overhead to just a pointer. Ok. Though it strikes me as a bit silly to worry about 160 bytes of overhead for a utility that never deletes anything. :) -Dave From aggarwa4 at illinois.edu Wed Jul 20 14:13:42 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 20 Jul 2011 19:13:42 -0000 Subject: [llvm-commits] [poolalloc] r135603 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110720191342.B8AA62A6C12D@llvm.org> Author: aggarwa4 Date: Wed Jul 20 14:13:42 2011 New Revision: 135603 URL: http://llvm.org/viewvc/llvm-project?rev=135603&view=rev Log: We must recompute I flags after StdLib pass as some DSNodes are no longer being used as arguments and should not be marked I any more. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=135603&r1=135602&r2=135603&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Jul 20 14:13:42 2011 @@ -344,9 +344,14 @@ {"trackgetcwd", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackgetpwuid", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackgethostname", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgethostbyname", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgetservbyname", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackgetaddrinfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgetsockname", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackaccept", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackpoll", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackpipe", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackReadLink", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, #if 0 {"wait", {false, false, false, false, true, false, false, false, false}}, @@ -584,6 +589,8 @@ // functions as External because, at that point, they were. However, they no // longer are necessarily External, and we need to update accordingly. // + GlobalsGraph->maskIncompleteMarkers(); + GlobalsGraph->computeExternalFlags(DSGraph::ResetExternal); for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) if (!I->isDeclaration()) { @@ -592,11 +599,25 @@ | DSGraph::ResetExternal | DSGraph::DontMarkFormalsExternal | DSGraph::ProcessCallSites; + G->maskIncompleteMarkers(); + G->markIncompleteNodes(DSGraph::MarkFormalArgs + |DSGraph::IgnoreGlobals); G->computeExternalFlags(EFlags); DEBUG(G->AssertGraphOK()); } + GlobalsGraph->markIncompleteNodes(DSGraph::MarkFormalArgs + |DSGraph::IgnoreGlobals); GlobalsGraph->computeExternalFlags(DSGraph::ProcessCallSites); DEBUG(GlobalsGraph->AssertGraphOK()); + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) + if (!I->isDeclaration()) { + DSGraph *Graph = getOrCreateGraph(I); + Graph->maskIncompleteMarkers(); + cloneGlobalsInto(Graph, DSGraph::DontCloneCallNodes | + DSGraph::DontCloneAuxCallNodes); + Graph->markIncompleteNodes(DSGraph::MarkFormalArgs + |DSGraph::IgnoreGlobals); + } return false; } From eli.friedman at gmail.com Wed Jul 20 14:36:11 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 19:36:11 -0000 Subject: [llvm-commits] [llvm] r135607 - in /llvm/trunk: lib/Target/X86/X86MCCodeEmitter.cpp test/MC/ELF/global-offset.s Message-ID: <20110720193611.366FB2A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 14:36:11 2011 New Revision: 135607 URL: http://llvm.org/viewvc/llvm-project?rev=135607&view=rev Log: Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/test/MC/ELF/global-offset.s Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=135607&r1=135606&r2=135607&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Wed Jul 20 14:36:11 2011 @@ -205,7 +205,9 @@ } // If we have an immoffset, add it to the expression. - if (FixupKind == FK_Data_4 && StartsWithGlobalOffsetTable(Expr)) { + if ((FixupKind == FK_Data_4 || + FixupKind == MCFixupKind(X86::reloc_signed_4byte)) && + StartsWithGlobalOffsetTable(Expr)) { assert(ImmOffset == 0); FixupKind = MCFixupKind(X86::reloc_global_offset_table); Modified: llvm/trunk/test/MC/ELF/global-offset.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/global-offset.s?rev=135607&r1=135606&r2=135607&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/global-offset.s (original) +++ llvm/trunk/test/MC/ELF/global-offset.s Wed Jul 20 14:36:11 2011 @@ -1,9 +1,10 @@ // RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s // We test that _GLOBAL_OFFSET_TABLE_ will account for the two bytes at the -// start of the addl. +// start of the addl/leal. addl $_GLOBAL_OFFSET_TABLE_, %ebx + leal _GLOBAL_OFFSET_TABLE_(%ebx), %ebx // CHECK: ('sh_name', 0x00000005) # '.text' // CHECK-NEXT: ('sh_type', @@ -15,4 +16,4 @@ // CHECK-NEXT: ('sh_info', // CHECK-NEXT: ('sh_addralign', // CHECK-NEXT: ('sh_entsize', -// CHECK-NEXT: ('_section_data', '81c30200 0000') +// CHECK-NEXT: ('_section_data', '81c30200 00008d9b 02000000') From benny.kra at googlemail.com Wed Jul 20 14:37:36 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 20 Jul 2011 19:37:36 -0000 Subject: [llvm-commits] [llvm] r135608 - in /llvm/trunk/tools/llvm-objdump: MCFunction.cpp MCFunction.h llvm-objdump.cpp Message-ID: <20110720193736.22FD12A6C12D@llvm.org> Author: d0k Date: Wed Jul 20 14:37:35 2011 New Revision: 135608 URL: http://llvm.org/viewvc/llvm-project?rev=135608&view=rev Log: Sketch out an CFG reconstruction mode for llvm-objdump. - Not great yet, but it's a start. - Requires an object file with a symbol table. (I really want to fix this, but it'll need a whole new algorithm) - ELF and COFF won't work at the moment due to libObject shortcomings. To try it out run $ llvm-objdump -d --cfg foo.o This will create a graphviz file for every symbol in the object file's text section containing a CFG. Added: llvm/trunk/tools/llvm-objdump/MCFunction.cpp llvm/trunk/tools/llvm-objdump/MCFunction.h Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Added: llvm/trunk/tools/llvm-objdump/MCFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MCFunction.cpp?rev=135608&view=auto ============================================================================== --- llvm/trunk/tools/llvm-objdump/MCFunction.cpp (added) +++ llvm/trunk/tools/llvm-objdump/MCFunction.cpp Wed Jul 20 14:37:35 2011 @@ -0,0 +1,113 @@ +//===-- MCFunction.cpp ----------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the algorithm to break down a region of machine code +// into basic blocks and try to reconstruct a CFG from it. +// +//===----------------------------------------------------------------------===// + +#include "MCFunction.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/system_error.h" +#include +using namespace llvm; + +MCFunction +MCFunction::createFunctionFromMC(StringRef Name, const MCDisassembler *DisAsm, + const MemoryObject &Region, uint64_t Start, + uint64_t End, const MCInstrInfo *InstrInfo, + raw_ostream &DebugOut) { + std::set Splits; + Splits.insert(Start); + std::vector Instructions; + uint64_t Size; + + // Disassemble code and gather basic block split points. + for (uint64_t Index = Start; Index < End; Index += Size) { + MCInst Inst; + + if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut)) { + const MCInstrDesc &Desc = InstrInfo->get(Inst.getOpcode()); + if (Desc.isBranch()) { + if (Desc.OpInfo[0].OperandType == MCOI::OPERAND_PCREL) { + int64_t Imm = Inst.getOperand(0).getImm(); + // FIXME: Distinguish relocations from nop jumps. + if (Imm != 0) { + assert(Index+Imm+Size < End && "Branch out of function."); + Splits.insert(Index+Imm+Size); + } + } + Splits.insert(Index+Size); + } + + Instructions.push_back(MCDecodedInst(Index, Size, Inst)); + } else { + errs() << "warning: invalid instruction encoding\n"; + if (Size == 0) + Size = 1; // skip illegible bytes + } + + } + + MCFunction f(Name); + + // Create basic blocks. + unsigned ii = 0, ie = Instructions.size(); + for (std::set::iterator spi = Splits.begin(), + spe = Splits.end(); spi != spe; ++spi) { + MCBasicBlock BB; + uint64_t BlockEnd = llvm::next(spi) == spe ? End : *llvm::next(spi); + // Add instructions to the BB. + for (; ii != ie; ++ii) { + if (Instructions[ii].Address < *spi || + Instructions[ii].Address >= BlockEnd) + break; + BB.addInst(Instructions[ii]); + } + f.addBlock(*spi, BB); + } + + // Calculate successors of each block. + for (MCFunction::iterator i = f.begin(), e = f.end(); i != e; ++i) { + MCBasicBlock &BB = i->second; + if (BB.getInsts().empty()) continue; + const MCDecodedInst &Inst = BB.getInsts().back(); + const MCInstrDesc &Desc = InstrInfo->get(Inst.Inst.getOpcode()); + + if (Desc.isBranch()) { + // PCRel branch, we know the destination. + if (Desc.OpInfo[0].OperandType == MCOI::OPERAND_PCREL) { + int64_t Imm = Inst.Inst.getOperand(0).getImm(); + if (Imm != 0) + BB.addSucc(&f.getBlockAtAddress(Inst.Address+Inst.Size+Imm)); + // Conditional branches can also fall through to the next block. + if (Desc.isConditionalBranch() && llvm::next(i) != e) + BB.addSucc(&next(i)->second); + } else { + // Indirect branch. Bail and add all blocks of the function as a + // successor. + for (MCFunction::iterator i = f.begin(), e = f.end(); i != e; ++i) + BB.addSucc(&i->second); + } + } else { + // No branch. Fall through to the next block. + if (!Desc.isReturn() && next(i) != e) + BB.addSucc(&next(i)->second); + } + } + + return f; +} Added: llvm/trunk/tools/llvm-objdump/MCFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MCFunction.h?rev=135608&view=auto ============================================================================== --- llvm/trunk/tools/llvm-objdump/MCFunction.h (added) +++ llvm/trunk/tools/llvm-objdump/MCFunction.h Wed Jul 20 14:37:35 2011 @@ -0,0 +1,88 @@ +//===-- MCFunction.h ------------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the data structures to hold a CFG reconstructed from +// machine code. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/MC/MCInst.h" +#include + +namespace llvm { + +class MCDisassembler; +class MCInstrInfo; +class MemoryObject; +class raw_ostream; + +/// MCDecodedInst - Small container to hold an MCInst and associated info like +/// address and size. +struct MCDecodedInst { + uint64_t Address; + uint64_t Size; + MCInst Inst; + + MCDecodedInst(uint64_t Address, uint64_t Size, MCInst Inst) + : Address(Address), Size(Size), Inst(Inst) {} +}; + +/// MCBasicBlock - Consists of multiple MCDecodedInsts and a list of successing +/// MCBasicBlocks. +class MCBasicBlock { + SmallVector Insts; + typedef SmallPtrSet SetTy; + SetTy Succs; +public: + ArrayRef getInsts() const { return Insts; } + + typedef SetTy::const_iterator succ_iterator; + succ_iterator succ_begin() const { return Succs.begin(); } + succ_iterator succ_end() const { return Succs.end(); } + + void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } + void addSucc(MCBasicBlock *BB) { Succs.insert(BB); } +}; + +/// MCFunction - Represents a named function in machine code, containing +/// multiple MCBasicBlocks. +class MCFunction { + const StringRef Name; + // Keep BBs sorted by address. + typedef std::map MapTy; + MapTy Blocks; +public: + MCFunction(StringRef Name) : Name(Name) {} + + // Create an MCFunction from a region of binary machine code. + static MCFunction + createFunctionFromMC(StringRef Name, const MCDisassembler *DisAsm, + const MemoryObject &Region, uint64_t Start, uint64_t End, + const MCInstrInfo *InstrInfo, raw_ostream &DebugOut); + + typedef MapTy::iterator iterator; + iterator begin() { return Blocks.begin(); } + iterator end() { return Blocks.end(); } + + StringRef getName() const { return Name; } + + MCBasicBlock &addBlock(uint64_t Address, const MCBasicBlock &BB) { + assert(!Blocks.count(Address) && "Already a BB at address."); + return Blocks[Address] = BB; + } + + MCBasicBlock &getBlockAtAddress(uint64_t Address) { + assert(Blocks.count(Address) && "No BB at address."); + return Blocks[Address]; + } +}; + +} Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=135608&r1=135607&r2=135608&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Jul 20 14:37:35 2011 @@ -13,6 +13,7 @@ // //===----------------------------------------------------------------------===// +#include "MCFunction.h" #include "llvm/Object/ObjectFile.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Triple.h" @@ -21,6 +22,8 @@ #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Format.h" @@ -52,6 +55,10 @@ Disassembled("d", cl::desc("Alias for --disassemble"), cl::aliasopt(Disassemble)); + cl::opt + CFG("cfg", cl::desc("Create a CFG for every symbol in the object file and" + "write it to a graphviz file")); + cl::opt TripleName("triple", cl::desc("Target triple to disassemble for, " "see -version for available targets")); @@ -156,6 +163,7 @@ // GetTarget prints out stuff. return; } + const MCInstrInfo *InstrInfo = TheTarget->createMCInstrInfo(); outs() << '\n'; outs() << Filename @@ -233,15 +241,14 @@ uint64_t End = si == se-1 ? SectSize : Symbols[si + 1].first - 1; outs() << '\n' << Symbols[si].second << ":\n"; - for (Index = Start; Index < End; Index += Size) { - MCInst Inst; - #ifndef NDEBUG raw_ostream &DebugOut = DebugFlag ? dbgs() : nulls(); #else raw_ostream &DebugOut = nulls(); #endif + for (Index = Start; Index < End; Index += Size) { + MCInst Inst; if (DisAsm->getInstruction(Inst, Size, memoryObject, Index, DebugOut)) { uint64_t addr; if (error(i->getAddress(addr))) break; @@ -255,6 +262,36 @@ Size = 1; // skip illegible bytes } } + + if (CFG) { + MCFunction f = + MCFunction::createFunctionFromMC(Symbols[si].second, DisAsm.get(), + memoryObject, Start, End, InstrInfo, + DebugOut); + + // Start a new dot file. + std::string Error; + raw_fd_ostream Out((f.getName().str() + ".dot").c_str(), Error); + + Out << "digraph " << f.getName() << " {\n"; + Out << "graph [ rankdir = \"LR\" ];\n"; + for (MCFunction::iterator i = f.begin(), e = f.end(); i != e; ++i) { + Out << '"' << (uintptr_t)&i->second << "\" [ label=\""; + // Print instructions. + for (unsigned ii = 0, ie = i->second.getInsts().size(); ii != ie; + ++ii) { + IP->printInst(&i->second.getInsts()[ii].Inst, Out); + Out << '|'; + } + Out << "\" shape=\"record\" ];\n"; + + // Add edges. + for (MCBasicBlock::succ_iterator si = i->second.succ_begin(), + se = i->second.succ_end(); si != se; ++si) + Out << (uintptr_t)&i->second << ":o -> " << (uintptr_t)*si <<":a\n"; + } + Out << "}\n"; + } } } } @@ -271,6 +308,7 @@ llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); llvm::InitializeAllMCCodeGenInfos(); + llvm::InitializeAllMCInstrInfos(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); From benny.kra at googlemail.com Wed Jul 20 14:43:38 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 20 Jul 2011 19:43:38 -0000 Subject: [llvm-commits] [llvm] r135609 - /llvm/trunk/tools/llvm-objdump/CMakeLists.txt Message-ID: <20110720194338.B97C42A6C12D@llvm.org> Author: d0k Date: Wed Jul 20 14:43:38 2011 New Revision: 135609 URL: http://llvm.org/viewvc/llvm-project?rev=135609&view=rev Log: Fix cmake. Modified: llvm/trunk/tools/llvm-objdump/CMakeLists.txt Modified: llvm/trunk/tools/llvm-objdump/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/CMakeLists.txt?rev=135609&r1=135608&r2=135609&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-objdump/CMakeLists.txt Wed Jul 20 14:43:38 2011 @@ -8,4 +8,5 @@ add_llvm_tool(llvm-objdump llvm-objdump.cpp + MCFunction.cpp ) From evan.cheng at apple.com Wed Jul 20 14:50:42 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jul 2011 19:50:42 -0000 Subject: [llvm-commits] [llvm] r135611 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Target/ lib/Target/CBackend/ lib/Target/X86/ tools/llvm-mc/ tools/lto/ Message-ID: <20110720195043.5D0102A6C12D@llvm.org> Author: evancheng Date: Wed Jul 20 14:50:42 2011 New Revision: 135611 URL: http://llvm.org/viewvc/llvm-project?rev=135611&view=rev Log: Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. Removed: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/lib/Target/TargetAsmInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCObjectFileInfo.h llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.h llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/MC/MCObjectFileInfo.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp llvm/trunk/lib/Target/X86/X86TargetObjectFile.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Wed Jul 20 14:50:42 2011 @@ -175,8 +175,7 @@ MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL. // Real constructor. MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, - const MCObjectFileInfo *MOFI, - const TargetAsmInfo *TAI); + const MCObjectFileInfo *MOFI); ~MachineModuleInfo(); bool doInitialization(); Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Wed Jul 20 14:50:42 2011 @@ -100,11 +100,6 @@ virtual MCSymbol * getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, MachineModuleInfo *MMI) const; - - virtual unsigned getPersonalityEncoding() const; - virtual unsigned getLSDAEncoding() const; - virtual unsigned getFDEEncoding(bool CFI) const; - virtual unsigned getTTypeEncoding() const; }; Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Wed Jul 20 14:50:42 2011 @@ -31,7 +31,6 @@ class MCLineSection; class StringRef; class Twine; - class TargetAsmInfo; class MCSectionMachO; class MCSectionELF; @@ -54,8 +53,6 @@ /// The MCObjectFileInfo for this target. const MCObjectFileInfo *MOFI; - const TargetAsmInfo *TAI; - /// Allocator - Allocator object used for creating machine code objects. /// /// We use a bump pointer allocator to avoid the need to track all allocated @@ -119,7 +116,7 @@ public: explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, - const MCObjectFileInfo *MOFI, const TargetAsmInfo *TAI); + const MCObjectFileInfo *MOFI); ~MCContext(); const MCAsmInfo &getAsmInfo() const { return MAI; } @@ -128,8 +125,6 @@ const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } - const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; } - void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; } /// @name Symbol Management Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectFileInfo.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectFileInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectFileInfo.h Wed Jul 20 14:50:42 2011 @@ -40,6 +40,13 @@ /// non-.globl label. This defaults to true. bool IsFunctionEHFrameSymbolPrivate; + /// PersonalityEncoding, LSDAEncoding, FDEEncoding, TTypeEncoding - Some + /// encoding values for EH. + unsigned PersonalityEncoding; + unsigned LSDAEncoding; + unsigned FDEEncoding; + unsigned FDECFIEncoding; + unsigned TTypeEncoding; /// TextSection - Section directive for standard text. /// @@ -151,7 +158,8 @@ const MCSection *XDataSection; public: - void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, MCContext &ctx); + void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, + MCContext &ctx); bool isFunctionEHFrameSymbolPrivate() const { return IsFunctionEHFrameSymbolPrivate; @@ -163,6 +171,13 @@ return CommDirectiveSupportsAlignment; } + unsigned getPersonalityEncoding() const { return PersonalityEncoding; } + unsigned getLSDAEncoding() const { return LSDAEncoding; } + unsigned getFDEEncoding(bool CFI) const { + return CFI ? FDECFIEncoding : FDEEncoding; + } + unsigned getTTypeEncoding() const { return TTypeEncoding; } + const MCSection *getTextSection() const { return TextSection; } const MCSection *getDataSection() const { return DataSection; } const MCSection *getBSSSection() const { return BSSSection; } @@ -262,6 +277,7 @@ enum Environment { IsMachO, IsELF, IsCOFF }; Environment Env; Reloc::Model RelocM; + CodeModel::Model CMModel; MCContext *Ctx; void InitMachOMCObjectFileInfo(Triple T); Removed: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=135610&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h (removed) @@ -1,35 +0,0 @@ -//===-- llvm/Target/TargetAsmInfo.h -----------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Interface to provide the information necessary for producing assembly files. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETASMINFO_H -#define LLVM_TARGET_TARGETASMINFO_H - -#include "llvm/Target/TargetLoweringObjectFile.h" - -namespace llvm { - class TargetMachine; - class TargetLoweringObjectFile; - -class TargetAsmInfo { - const TargetLoweringObjectFile *TLOF; - -public: - explicit TargetAsmInfo(const TargetMachine &TM); - - unsigned getFDEEncoding(bool CFI) const { - return TLOF->getFDEEncoding(CFI); - } -}; - -} -#endif Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original) +++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Wed Jul 20 14:50:42 2011 @@ -122,11 +122,6 @@ getExprForDwarfReference(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const; - virtual unsigned getPersonalityEncoding() const; - virtual unsigned getLSDAEncoding() const; - virtual unsigned getFDEEncoding(bool CFI) const; - virtual unsigned getTTypeEncoding() const; - protected: virtual const MCSection * SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jul 20 14:50:42 2011 @@ -33,7 +33,6 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLowering.h" Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Wed Jul 20 14:50:42 2011 @@ -45,7 +45,6 @@ #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetELFWriterInfo.h" #include "llvm/Target/TargetLowering.h" @@ -67,8 +66,7 @@ ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) : MachineFunctionPass(ID), O(o), TM(tm), OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(), - &TM.getTargetLowering()->getObjFileLowering(), - new TargetAsmInfo(tm))), + &TM.getTargetLowering()->getObjFileLowering())), TLOF(TM.getTargetLowering()->getObjFileLowering()), is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64), isLittleEndian(TM.getTargetData()->isLittleEndian()), Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jul 20 14:50:42 2011 @@ -27,9 +27,10 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSubtargetInfo.h" @@ -353,11 +354,9 @@ // Install a MachineModuleInfo class, which is an immutable pass that holds // all the per-module stuff we're generating, including MCContext. - TargetAsmInfo *TAI = new TargetAsmInfo(*this); MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), *getRegisterInfo(), - &getTargetLowering()->getObjFileLowering(), - TAI); + &getTargetLowering()->getObjFileLowering()); PM.add(MMI); OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jul 20 14:50:42 2011 @@ -17,7 +17,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/ADT/PointerUnion.h" @@ -254,9 +253,8 @@ MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, - const MCObjectFileInfo *MOFI, - const TargetAsmInfo *TAI) - : ImmutablePass(ID), Context(MAI, MRI, MOFI, TAI), + const MCObjectFileInfo *MOFI) + : ImmutablePass(ID), Context(MAI, MRI, MOFI), ObjFileMMI(0), CompactUnwindEncoding(0), CurCallSite(0), CallsEHReturn(0), CallsUnwindInit(0), DbgInfoAvailable(false), CallsExternalVAFunctionWithFloatingPointArguments(false) { @@ -269,7 +267,7 @@ MachineModuleInfo::MachineModuleInfo() : ImmutablePass(ID), - Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0, NULL) { + Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) { assert(0 && "This MachineModuleInfo constructor should never be called, MMI " "should always be explicitly constructed by LLVMTargetMachine"); abort(); Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Jul 20 14:50:42 2011 @@ -543,22 +543,6 @@ return SSym; } -unsigned TargetLoweringObjectFileMachO::getPersonalityEncoding() const { - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; -} - -unsigned TargetLoweringObjectFileMachO::getLSDAEncoding() const { - return DW_EH_PE_pcrel; -} - -unsigned TargetLoweringObjectFileMachO::getFDEEncoding(bool CFI) const { - return DW_EH_PE_pcrel; -} - -unsigned TargetLoweringObjectFileMachO::getTTypeEncoding() const { - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; -} - //===----------------------------------------------------------------------===// // COFF //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jul 20 14:50:42 2011 @@ -28,7 +28,6 @@ #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetAsmBackend.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include using namespace llvm; Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Wed Jul 20 14:50:42 2011 @@ -17,7 +17,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCLabel.h" #include "llvm/MC/MCDwarf.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/ELF.h" @@ -29,8 +28,8 @@ MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri, - const MCObjectFileInfo *mofi, const TargetAsmInfo *tai) : - MAI(mai), MRI(mri), MOFI(mofi), TAI(tai), + const MCObjectFileInfo *mofi) : + MAI(mai), MRI(mri), MOFI(mofi), Allocator(), Symbols(Allocator), UsedNames(Allocator), NextUniqueID(0), CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0), @@ -57,8 +56,6 @@ // If the stream for the .secure_log_unique directive was created free it. delete (raw_ostream*)SecureLog; - - delete TAI; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jul 20 14:50:42 2011 @@ -17,8 +17,6 @@ #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetAsmInfo.h" // FIXME. -#include "llvm/Target/TargetMachine.h" // FIXME. #include "llvm/Target/TargetSelect.h" #include "llvm/Support/MemoryObject.h" @@ -39,8 +37,6 @@ LLVMSymbolLookupCallback SymbolLookUp) { // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); - // FIXME: We shouldn't need to initialize the Target(Machine)s. - llvm::InitializeAllTargets(); llvm::InitializeAllMCAsmInfos(); llvm::InitializeAllMCCodeGenInfos(); llvm::InitializeAllMCRegisterInfos(); @@ -64,19 +60,8 @@ std::string FeaturesStr; std::string CPU; - // FIXME: We shouldn't need to do this (and link in codegen). - // When we split this out, we should do it in a way that makes - // it straightforward to switch subtargets on the fly. - TargetMachine *TM = TheTarget->createTargetMachine(TripleName, CPU, - FeaturesStr); - assert(TM && "Unable to create target machine!"); - - // Get the target assembler info needed to setup the context. - const TargetAsmInfo *tai = new TargetAsmInfo(*TM); - assert(tai && "Unable to create target assembler!"); - // Set up the MCContext for creating symbols and MCExpr's. - MCContext *Ctx = new MCContext(*MAI, *MRI, 0, tai); + MCContext *Ctx = new MCContext(*MAI, *MRI, 0); assert(Ctx && "Unable to create MCContext!"); // Set up disassembler. @@ -92,7 +77,7 @@ LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType, GetOpInfo, SymbolLookUp, - TheTarget, MAI, MRI, TM, tai, + TheTarget, MAI, MRI, Ctx, DisAsm, IP); assert(DC && "Allocation failure!"); return DC; Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.h Wed Jul 20 14:50:42 2011 @@ -22,14 +22,12 @@ #include "llvm/ADT/OwningPtr.h" namespace llvm { -class TargetAsmInfo; class MCContext; class MCAsmInfo; class MCDisassembler; class MCInstPrinter; class MCRegisterInfo; class Target; -class TargetMachine; // // This is the disassembler context returned by LLVMCreateDisasm(). @@ -61,12 +59,6 @@ llvm::OwningPtr MAI; // The register information for the target architecture. llvm::OwningPtr MRI; - // The target machine instance. - llvm::OwningPtr TM; - // The disassembler for the target architecture. - // FIXME: using llvm::OwningPtr causes a malloc - // error when this LLVMDisasmContext is deleted. - const TargetAsmInfo *Tai; // The assembly context for creating symbols and MCExprs. llvm::OwningPtr Ctx; // The disassembler for the target architecture. @@ -80,12 +72,10 @@ LLVMSymbolLookupCallback symbolLookUp, const Target *theTarget, const MCAsmInfo *mAI, const MCRegisterInfo *mRI, - llvm::TargetMachine *tM, const TargetAsmInfo *tai, llvm::MCContext *ctx, const MCDisassembler *disAsm, MCInstPrinter *iP) : TripleName(tripleName), DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo), - SymbolLookUp(symbolLookUp), TheTarget(theTarget), Tai(tai) { - TM.reset(tM); + SymbolLookUp(symbolLookUp), TheTarget(theTarget) { MAI.reset(mAI); MRI.reset(mRI); Ctx.reset(ctx); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Jul 20 14:50:42 2011 @@ -377,7 +377,7 @@ SourceMgr sourceMgr; sourceMgr.setDiagHandler(diag_handler, static_cast(this)); sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over - MCContext context(*AsmInfo, *MRI, NULL, NULL); + MCContext context(*AsmInfo, *MRI, NULL); OwningPtr streamer(createNullStreamer(context)); OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jul 20 14:50:42 2011 @@ -19,7 +19,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" @@ -691,7 +690,6 @@ const MCDwarfFrameInfo &Frame) { MCContext &Context = Streamer.getContext(); const MCObjectFileInfo *MOFI = Context.getObjectFileInfo(); - const TargetAsmInfo &TAI = Context.getTargetAsmInfo(); bool VerboseAsm = Streamer.isVerboseAsm(); // range-start range-length compact-unwind-enc personality-func lsda @@ -726,7 +724,7 @@ Streamer.SwitchSection(MOFI->getCompactUnwindSection()); // Range Start - unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI); + unsigned FDEEncoding = MOFI->getFDEEncoding(UsingCFI); unsigned Size = getSizeForEncoding(Streamer, FDEEncoding); if (VerboseAsm) Streamer.AddComment("Range Start"); Streamer.EmitSymbolValue(Frame.Function, Size); @@ -771,7 +769,6 @@ MCContext &context = streamer.getContext(); const MCRegisterInfo &MRI = context.getRegisterInfo(); const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); bool verboseAsm = streamer.isVerboseAsm(); MCSymbol *sectionStart; @@ -858,7 +855,7 @@ EmitEncodingByte(streamer, lsdaEncoding, "LSDA Encoding"); // Encoding of the FDE pointers - EmitEncodingByte(streamer, TAI.getFDEEncoding(UsingCFI), + EmitEncodingByte(streamer, MOFI->getFDEEncoding(UsingCFI), "FDE Encoding"); } @@ -895,7 +892,6 @@ MCSymbol *fdeStart = context.CreateTempSymbol(); MCSymbol *fdeEnd = context.CreateTempSymbol(); const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); bool verboseAsm = streamer.isVerboseAsm(); if (!MOFI->isFunctionEHFrameSymbolPrivate() && IsEH) { @@ -927,7 +923,7 @@ streamer.EmitSymbolValue(&cieStart, 4); } - unsigned fdeEncoding = TAI.getFDEEncoding(UsingCFI); + unsigned fdeEncoding = MOFI->getFDEEncoding(UsingCFI); unsigned size = getSizeForEncoding(streamer, fdeEncoding); // PC Begin Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Jul 20 14:50:42 2011 @@ -21,6 +21,12 @@ IsFunctionEHFrameSymbolPrivate = false; SupportsWeakOmittedEHFrame = false; + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel + | dwarf::DW_EH_PE_sdata4; + LSDAEncoding = FDEEncoding = FDECFIEncoding = dwarf::DW_EH_PE_pcrel; + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + dwarf::DW_EH_PE_sdata4; + // .comm doesn't support alignment before Leopard. if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5)) CommDirectiveSupportsAlignment = false; @@ -199,6 +205,45 @@ } void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) { + if (T.getArch() == Triple::x86) { + PersonalityEncoding = (RelocM == Reloc::PIC_) + ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 + : dwarf::DW_EH_PE_absptr; + LSDAEncoding = (RelocM == Reloc::PIC_) + ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 + : dwarf::DW_EH_PE_absptr; + FDEEncoding = FDECFIEncoding = (RelocM == Reloc::PIC_) + ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 + : dwarf::DW_EH_PE_absptr; + TTypeEncoding = (RelocM == Reloc::PIC_) + ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 + : dwarf::DW_EH_PE_absptr; + } else if (T.getArch() == Triple::x86_64) { + FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + + if (RelocM == Reloc::PIC_) { + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + ((CMModel == CodeModel::Small || CMModel == CodeModel::Medium) + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); + LSDAEncoding = dwarf::DW_EH_PE_pcrel | + (CMModel == CodeModel::Small + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); + FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + ((CMModel == CodeModel::Small || CMModel == CodeModel::Medium) + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); + } else { + PersonalityEncoding = + (CMModel == CodeModel::Small || CMModel == CodeModel::Medium) + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; + LSDAEncoding = (CMModel == CodeModel::Small) + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; + FDEEncoding = dwarf::DW_EH_PE_udata4; + TTypeEncoding = (CMModel == CodeModel::Small) + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; + } + } + // ELF BSSSection = Ctx->getELFSection(".bss", ELF::SHT_NOBITS, @@ -446,15 +491,21 @@ } void MCObjectFileInfo::InitMCObjectFileInfo(StringRef TT, Reloc::Model relocm, + CodeModel::Model cm, MCContext &ctx) { RelocM = relocm; + CMModel = cm; Ctx = &ctx; // Common. CommDirectiveSupportsAlignment = true; SupportsWeakOmittedEHFrame = true; IsFunctionEHFrameSymbolPrivate = true; - EHFrameSection = 0; + + PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = + TTypeEncoding = dwarf::DW_EH_PE_absptr; + + EHFrameSection = 0; // Created on demand. Triple T(TT); Triple::ArchType Arch = T.getArch(); Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jul 20 14:50:42 2011 @@ -33,7 +33,6 @@ #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetAsmParser.h" #include #include Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Jul 20 14:50:42 2011 @@ -1676,7 +1676,7 @@ #endif TAsm = new CBEMCAsmInfo(); MRI = new MCRegisterInfo(); - TCtx = new MCContext(*TAsm, *MRI, NULL, NULL); + TCtx = new MCContext(*TAsm, *MRI, NULL); Mang = new Mangler(*TCtx, *TD); // Keep track of which functions are static ctors/dtors so they can have Removed: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=135610&view=auto ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp (removed) @@ -1,18 +0,0 @@ -//===-- llvm/Target/TargetAsmInfo.cpp - Target Assembly Info --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetMachine.h" -using namespace llvm; - -TargetAsmInfo::TargetAsmInfo(const TargetMachine &TM) { - TLOF = &TM.getTargetLowering()->getObjFileLowering(); -} Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Jul 20 14:50:42 2011 @@ -41,7 +41,8 @@ void TargetLoweringObjectFile::Initialize(MCContext &ctx, const TargetMachine &TM) { Ctx = &ctx; - InitMCObjectFileInfo(TM.getTargetTriple(), TM.getRelocationModel(), *Ctx); + InitMCObjectFileInfo(TM.getTargetTriple(), + TM.getRelocationModel(), TM.getCodeModel(), *Ctx); } TargetLoweringObjectFile::~TargetLoweringObjectFile() { @@ -322,20 +323,3 @@ } } } - -unsigned TargetLoweringObjectFile::getPersonalityEncoding() const { - return dwarf::DW_EH_PE_absptr; -} - -unsigned TargetLoweringObjectFile::getLSDAEncoding() const { - return dwarf::DW_EH_PE_absptr; -} - -unsigned TargetLoweringObjectFile::getFDEEncoding(bool CFI) const { - return dwarf::DW_EH_PE_absptr; -} - -unsigned TargetLoweringObjectFile::getTTypeEncoding() const { - return dwarf::DW_EH_PE_absptr; -} - Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 14:50:42 2011 @@ -197,11 +197,8 @@ return new TargetLoweringObjectFileMachO(); } - if (Subtarget->isTargetELF()) { - if (is64Bit) - return new X8664_ELFTargetObjectFile(TM); - return new X8632_ELFTargetObjectFile(TM); - } + if (Subtarget->isTargetELF()) + return new TargetLoweringObjectFileELF(); if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) return new TargetLoweringObjectFileCOFF(); llvm_unreachable("unknown subtarget type"); Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp Wed Jul 20 14:50:42 2011 @@ -43,79 +43,3 @@ MachineModuleInfo *MMI) const { return Mang->getSymbol(GV); } - -unsigned X8632_ELFTargetObjectFile::getPersonalityEncoding() const { - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; - else - return DW_EH_PE_absptr; -} - -unsigned X8632_ELFTargetObjectFile::getLSDAEncoding() const { - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; - else - return DW_EH_PE_absptr; -} - -unsigned X8632_ELFTargetObjectFile::getFDEEncoding(bool FDE) const { - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; - else - return DW_EH_PE_absptr; -} - -unsigned X8632_ELFTargetObjectFile::getTTypeEncoding() const { - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; - else - return DW_EH_PE_absptr; -} - -unsigned X8664_ELFTargetObjectFile::getPersonalityEncoding() const { - CodeModel::Model Model = TM.getCodeModel(); - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_indirect | DW_EH_PE_pcrel | (Model == CodeModel::Small || - Model == CodeModel::Medium ? - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); - - if (Model == CodeModel::Small || Model == CodeModel::Medium) - return DW_EH_PE_udata4; - - return DW_EH_PE_absptr; -} - -unsigned X8664_ELFTargetObjectFile::getLSDAEncoding() const { - CodeModel::Model Model = TM.getCodeModel(); - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_pcrel | (Model == CodeModel::Small ? - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); - - if (Model == CodeModel::Small) - return DW_EH_PE_udata4; - - return DW_EH_PE_absptr; -} - -unsigned X8664_ELFTargetObjectFile::getFDEEncoding(bool CFI) const { - if (CFI) - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; - - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; - - return DW_EH_PE_udata4; -} - -unsigned X8664_ELFTargetObjectFile::getTTypeEncoding() const { - CodeModel::Model Model = TM.getCodeModel(); - if (TM.getRelocationModel() == Reloc::PIC_) - return DW_EH_PE_indirect | DW_EH_PE_pcrel | (Model == CodeModel::Small || - Model == CodeModel::Medium ? - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); - - if (Model == CodeModel::Small) - return DW_EH_PE_udata4; - - return DW_EH_PE_absptr; -} Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.h?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetObjectFile.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.h Wed Jul 20 14:50:42 2011 @@ -33,28 +33,6 @@ MachineModuleInfo *MMI) const; }; - class X8632_ELFTargetObjectFile : public TargetLoweringObjectFileELF { - const X86TargetMachine &TM; - public: - X8632_ELFTargetObjectFile(const X86TargetMachine &tm) - :TM(tm) { } - virtual unsigned getPersonalityEncoding() const; - virtual unsigned getLSDAEncoding() const; - virtual unsigned getFDEEncoding(bool CFI) const; - virtual unsigned getTTypeEncoding() const; - }; - - class X8664_ELFTargetObjectFile : public TargetLoweringObjectFileELF { - const X86TargetMachine &TM; - public: - X8664_ELFTargetObjectFile(const X86TargetMachine &tm) - :TM(tm) { } - virtual unsigned getPersonalityEncoding() const; - virtual unsigned getLSDAEncoding() const; - virtual unsigned getFDEEncoding(bool CFI) const; - virtual unsigned getTTypeEncoding() const; - }; - } // end namespace llvm #endif Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jul 20 14:50:42 2011 @@ -28,10 +28,6 @@ #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetAsmInfo.h" // FIXME. -#include "llvm/Target/TargetLowering.h" // FIXME. -#include "llvm/Target/TargetLoweringObjectFile.h" // FIXME. -#include "llvm/Target/TargetMachine.h" // FIXME. #include "llvm/Target/TargetSelect.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" @@ -348,28 +344,11 @@ // Package up features to be passed to target/subtarget std::string FeaturesStr; - // FIXME: We shouldn't need to do this (and link in codegen). - // When we split this out, we should do it in a way that makes - // it straightforward to switch subtargets on the fly (.e.g, - // the .cpu and .code16 directives). - OwningPtr TM(TheTarget->createTargetMachine(TripleName, - MCPU, - FeaturesStr, - RelocModel, - CMModel)); - - if (!TM) { - errs() << ProgName << ": error: could not create target for triple '" - << TripleName << "'.\n"; - return 1; - } - - const TargetAsmInfo *tai = new TargetAsmInfo(*TM); // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // MCObjectFileInfo needs a MCContext reference in order to initialize itself. OwningPtr MOFI(new MCObjectFileInfo()); - MCContext Ctx(*MAI, *MRI, MOFI.get(), tai); - MOFI->InitMCObjectFileInfo(TripleName, RelocModel, Ctx); + MCContext Ctx(*MAI, *MRI, MOFI.get()); + MOFI->InitMCObjectFileInfo(TripleName, RelocModel, CMModel, Ctx); if (SaveTempLabels) Ctx.setAllowTemporaryLabels(false); @@ -381,10 +360,6 @@ formatted_raw_ostream FOS(Out->os()); OwningPtr Str; - const TargetLoweringObjectFile &TLOF = - TM->getTargetLowering()->getObjFileLowering(); - const_cast(TLOF).Initialize(Ctx, *TM); - OwningPtr MCII(TheTarget->createMCInstrInfo()); OwningPtr STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jul 20 14:50:42 2011 @@ -313,8 +313,7 @@ passes.add(createVerifierPass()); // mark which symbols can not be internalized - MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), - NULL, NULL); + MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), NULL); Mangler mangler(Context, *_target->getTargetData()); std::vector mustPreserveList; SmallPtrSet asmUsed; Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=135611&r1=135610&r2=135611&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Jul 20 14:50:42 2011 @@ -664,8 +664,7 @@ bool LTOModule::ParseSymbols() { // Use mangler to add GlobalPrefix to names to match linker names. - MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), - NULL, NULL); + MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL); Mangler mangler(Context, *_target->getTargetData()); // add functions From grosbach at apple.com Wed Jul 20 14:57:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 12:57:35 -0700 Subject: [llvm-commits] [llvm] r135611 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Target/ lib/Target/CBackend/ lib/Target/X86/ tools/llvm-mc/ tools/lto/ In-Reply-To: <20110720195043.5D0102A6C12D@llvm.org> References: <20110720195043.5D0102A6C12D@llvm.org> Message-ID: Woot!! Very, very cool. -Jim On Jul 20, 2011, at 12:50 PM, Evan Cheng wrote: > Author: evancheng > Date: Wed Jul 20 14:50:42 2011 > New Revision: 135611 > > URL: http://llvm.org/viewvc/llvm-project?rev=135611&view=rev > Log: > Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. > > There is still a bit more refactoring left to do in Targets. But we are now very > close to fixing all the layering issues in MC. > > Removed: > llvm/trunk/include/llvm/Target/TargetAsmInfo.h > llvm/trunk/lib/Target/TargetAsmInfo.cpp > Modified: > llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h > llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h > llvm/trunk/include/llvm/MC/MCContext.h > llvm/trunk/include/llvm/MC/MCObjectFileInfo.h > llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > llvm/trunk/lib/CodeGen/ELFWriter.cpp > llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp > llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp > llvm/trunk/lib/MC/MCAsmStreamer.cpp > llvm/trunk/lib/MC/MCContext.cpp > llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp > llvm/trunk/lib/MC/MCDisassembler/Disassembler.h > llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > llvm/trunk/lib/MC/MCDwarf.cpp > llvm/trunk/lib/MC/MCObjectFileInfo.cpp > llvm/trunk/lib/MC/MCParser/AsmParser.cpp > llvm/trunk/lib/Target/CBackend/CBackend.cpp > llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp > llvm/trunk/lib/Target/X86/X86TargetObjectFile.h > llvm/trunk/tools/llvm-mc/llvm-mc.cpp > llvm/trunk/tools/lto/LTOCodeGenerator.cpp > llvm/trunk/tools/lto/LTOModule.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Wed Jul 20 14:50:42 2011 > @@ -175,8 +175,7 @@ > MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL. > // Real constructor. > MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, > - const MCObjectFileInfo *MOFI, > - const TargetAsmInfo *TAI); > + const MCObjectFileInfo *MOFI); > ~MachineModuleInfo(); > > bool doInitialization(); > > Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) > +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Wed Jul 20 14:50:42 2011 > @@ -100,11 +100,6 @@ > virtual MCSymbol * > getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, > MachineModuleInfo *MMI) const; > - > - virtual unsigned getPersonalityEncoding() const; > - virtual unsigned getLSDAEncoding() const; > - virtual unsigned getFDEEncoding(bool CFI) const; > - virtual unsigned getTTypeEncoding() const; > }; > > > > Modified: llvm/trunk/include/llvm/MC/MCContext.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCContext.h (original) > +++ llvm/trunk/include/llvm/MC/MCContext.h Wed Jul 20 14:50:42 2011 > @@ -31,7 +31,6 @@ > class MCLineSection; > class StringRef; > class Twine; > - class TargetAsmInfo; > class MCSectionMachO; > class MCSectionELF; > > @@ -54,8 +53,6 @@ > /// The MCObjectFileInfo for this target. > const MCObjectFileInfo *MOFI; > > - const TargetAsmInfo *TAI; > - > /// Allocator - Allocator object used for creating machine code objects. > /// > /// We use a bump pointer allocator to avoid the need to track all allocated > @@ -119,7 +116,7 @@ > > public: > explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, > - const MCObjectFileInfo *MOFI, const TargetAsmInfo *TAI); > + const MCObjectFileInfo *MOFI); > ~MCContext(); > > const MCAsmInfo &getAsmInfo() const { return MAI; } > @@ -128,8 +125,6 @@ > > const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } > > - const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; } > - > void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; } > > /// @name Symbol Management > > Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectFileInfo.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCObjectFileInfo.h (original) > +++ llvm/trunk/include/llvm/MC/MCObjectFileInfo.h Wed Jul 20 14:50:42 2011 > @@ -40,6 +40,13 @@ > /// non-.globl label. This defaults to true. > bool IsFunctionEHFrameSymbolPrivate; > > + /// PersonalityEncoding, LSDAEncoding, FDEEncoding, TTypeEncoding - Some > + /// encoding values for EH. > + unsigned PersonalityEncoding; > + unsigned LSDAEncoding; > + unsigned FDEEncoding; > + unsigned FDECFIEncoding; > + unsigned TTypeEncoding; > > /// TextSection - Section directive for standard text. > /// > @@ -151,7 +158,8 @@ > const MCSection *XDataSection; > > public: > - void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, MCContext &ctx); > + void InitMCObjectFileInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, > + MCContext &ctx); > > bool isFunctionEHFrameSymbolPrivate() const { > return IsFunctionEHFrameSymbolPrivate; > @@ -163,6 +171,13 @@ > return CommDirectiveSupportsAlignment; > } > > + unsigned getPersonalityEncoding() const { return PersonalityEncoding; } > + unsigned getLSDAEncoding() const { return LSDAEncoding; } > + unsigned getFDEEncoding(bool CFI) const { > + return CFI ? FDECFIEncoding : FDEEncoding; > + } > + unsigned getTTypeEncoding() const { return TTypeEncoding; } > + > const MCSection *getTextSection() const { return TextSection; } > const MCSection *getDataSection() const { return DataSection; } > const MCSection *getBSSSection() const { return BSSSection; } > @@ -262,6 +277,7 @@ > enum Environment { IsMachO, IsELF, IsCOFF }; > Environment Env; > Reloc::Model RelocM; > + CodeModel::Model CMModel; > MCContext *Ctx; > > void InitMachOMCObjectFileInfo(Triple T); > > Removed: llvm/trunk/include/llvm/Target/TargetAsmInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=135610&view=auto > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h (removed) > @@ -1,35 +0,0 @@ > -//===-- llvm/Target/TargetAsmInfo.h -----------------------------*- C++ -*-===// > -// > -// The LLVM Compiler Infrastructure > -// > -// This file is distributed under the University of Illinois Open Source > -// License. See LICENSE.TXT for details. > -// > -//===----------------------------------------------------------------------===// > -// > -// Interface to provide the information necessary for producing assembly files. > -// > -//===----------------------------------------------------------------------===// > - > -#ifndef LLVM_TARGET_TARGETASMINFO_H > -#define LLVM_TARGET_TARGETASMINFO_H > - > -#include "llvm/Target/TargetLoweringObjectFile.h" > - > -namespace llvm { > - class TargetMachine; > - class TargetLoweringObjectFile; > - > -class TargetAsmInfo { > - const TargetLoweringObjectFile *TLOF; > - > -public: > - explicit TargetAsmInfo(const TargetMachine &TM); > - > - unsigned getFDEEncoding(bool CFI) const { > - return TLOF->getFDEEncoding(CFI); > - } > -}; > - > -} > -#endif > > Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original) > +++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Wed Jul 20 14:50:42 2011 > @@ -122,11 +122,6 @@ > getExprForDwarfReference(const MCSymbol *Sym, unsigned Encoding, > MCStreamer &Streamer) const; > > - virtual unsigned getPersonalityEncoding() const; > - virtual unsigned getLSDAEncoding() const; > - virtual unsigned getFDEEncoding(bool CFI) const; > - virtual unsigned getTTypeEncoding() const; > - > protected: > virtual const MCSection * > SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jul 20 14:50:42 2011 > @@ -33,7 +33,6 @@ > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCSymbol.h" > #include "llvm/Target/Mangler.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetInstrInfo.h" > #include "llvm/Target/TargetLowering.h" > > Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) > +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Wed Jul 20 14:50:42 2011 > @@ -45,7 +45,6 @@ > #include "llvm/MC/MCSectionELF.h" > #include "llvm/MC/MCAsmInfo.h" > #include "llvm/Target/Mangler.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetELFWriterInfo.h" > #include "llvm/Target/TargetLowering.h" > @@ -67,8 +66,7 @@ > ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) > : MachineFunctionPass(ID), O(o), TM(tm), > OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(), > - &TM.getTargetLowering()->getObjFileLowering(), > - new TargetAsmInfo(tm))), > + &TM.getTargetLowering()->getObjFileLowering())), > TLOF(TM.getTargetLowering()->getObjFileLowering()), > is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64), > isLittleEndian(TM.getTargetData()->isLittleEndian()), > > Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) > +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jul 20 14:50:42 2011 > @@ -27,9 +27,10 @@ > #include "llvm/MC/MCInstrInfo.h" > #include "llvm/MC/MCStreamer.h" > #include "llvm/MC/MCSubtargetInfo.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetInstrInfo.h" > +#include "llvm/Target/TargetLowering.h" > +#include "llvm/Target/TargetLoweringObjectFile.h" > #include "llvm/Target/TargetRegisterInfo.h" > #include "llvm/Target/TargetRegistry.h" > #include "llvm/Target/TargetSubtargetInfo.h" > @@ -353,11 +354,9 @@ > > // Install a MachineModuleInfo class, which is an immutable pass that holds > // all the per-module stuff we're generating, including MCContext. > - TargetAsmInfo *TAI = new TargetAsmInfo(*this); > MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), > *getRegisterInfo(), > - &getTargetLowering()->getObjFileLowering(), > - TAI); > + &getTargetLowering()->getObjFileLowering()); > PM.add(MMI); > OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. > > > Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jul 20 14:50:42 2011 > @@ -17,7 +17,6 @@ > #include "llvm/CodeGen/MachineFunctionPass.h" > #include "llvm/CodeGen/MachineFunction.h" > #include "llvm/CodeGen/Passes.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/MC/MCObjectFileInfo.h" > #include "llvm/MC/MCSymbol.h" > #include "llvm/ADT/PointerUnion.h" > @@ -254,9 +253,8 @@ > > MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI, > const MCRegisterInfo &MRI, > - const MCObjectFileInfo *MOFI, > - const TargetAsmInfo *TAI) > - : ImmutablePass(ID), Context(MAI, MRI, MOFI, TAI), > + const MCObjectFileInfo *MOFI) > + : ImmutablePass(ID), Context(MAI, MRI, MOFI), > ObjFileMMI(0), CompactUnwindEncoding(0), CurCallSite(0), CallsEHReturn(0), > CallsUnwindInit(0), DbgInfoAvailable(false), > CallsExternalVAFunctionWithFloatingPointArguments(false) { > @@ -269,7 +267,7 @@ > > MachineModuleInfo::MachineModuleInfo() > : ImmutablePass(ID), > - Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0, NULL) { > + Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) { > assert(0 && "This MachineModuleInfo constructor should never be called, MMI " > "should always be explicitly constructed by LLVMTargetMachine"); > abort(); > > Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) > +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Jul 20 14:50:42 2011 > @@ -543,22 +543,6 @@ > return SSym; > } > > -unsigned TargetLoweringObjectFileMachO::getPersonalityEncoding() const { > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; > -} > - > -unsigned TargetLoweringObjectFileMachO::getLSDAEncoding() const { > - return DW_EH_PE_pcrel; > -} > - > -unsigned TargetLoweringObjectFileMachO::getFDEEncoding(bool CFI) const { > - return DW_EH_PE_pcrel; > -} > - > -unsigned TargetLoweringObjectFileMachO::getTTypeEncoding() const { > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; > -} > - > //===----------------------------------------------------------------------===// > // COFF > //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jul 20 14:50:42 2011 > @@ -28,7 +28,6 @@ > #include "llvm/Support/Format.h" > #include "llvm/Support/FormattedStream.h" > #include "llvm/Target/TargetAsmBackend.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/Target/TargetLoweringObjectFile.h" > #include > using namespace llvm; > > Modified: llvm/trunk/lib/MC/MCContext.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCContext.cpp (original) > +++ llvm/trunk/lib/MC/MCContext.cpp Wed Jul 20 14:50:42 2011 > @@ -17,7 +17,6 @@ > #include "llvm/MC/MCSymbol.h" > #include "llvm/MC/MCLabel.h" > #include "llvm/MC/MCDwarf.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/ADT/SmallString.h" > #include "llvm/ADT/Twine.h" > #include "llvm/Support/ELF.h" > @@ -29,8 +28,8 @@ > > > MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri, > - const MCObjectFileInfo *mofi, const TargetAsmInfo *tai) : > - MAI(mai), MRI(mri), MOFI(mofi), TAI(tai), > + const MCObjectFileInfo *mofi) : > + MAI(mai), MRI(mri), MOFI(mofi), > Allocator(), Symbols(Allocator), UsedNames(Allocator), > NextUniqueID(0), > CurrentDwarfLoc(0,0,0,DWARF2_FLAG_IS_STMT,0,0), > @@ -57,8 +56,6 @@ > > // If the stream for the .secure_log_unique directive was created free it. > delete (raw_ostream*)SecureLog; > - > - delete TAI; > } > > //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) > +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jul 20 14:50:42 2011 > @@ -17,8 +17,6 @@ > #include "llvm/MC/MCInstPrinter.h" > #include "llvm/MC/MCRegisterInfo.h" > #include "llvm/Target/TargetRegistry.h" > -#include "llvm/Target/TargetAsmInfo.h" // FIXME. > -#include "llvm/Target/TargetMachine.h" // FIXME. > #include "llvm/Target/TargetSelect.h" > #include "llvm/Support/MemoryObject.h" > > @@ -39,8 +37,6 @@ > LLVMSymbolLookupCallback SymbolLookUp) { > // Initialize targets and assembly printers/parsers. > llvm::InitializeAllTargetInfos(); > - // FIXME: We shouldn't need to initialize the Target(Machine)s. > - llvm::InitializeAllTargets(); > llvm::InitializeAllMCAsmInfos(); > llvm::InitializeAllMCCodeGenInfos(); > llvm::InitializeAllMCRegisterInfos(); > @@ -64,19 +60,8 @@ > std::string FeaturesStr; > std::string CPU; > > - // FIXME: We shouldn't need to do this (and link in codegen). > - // When we split this out, we should do it in a way that makes > - // it straightforward to switch subtargets on the fly. > - TargetMachine *TM = TheTarget->createTargetMachine(TripleName, CPU, > - FeaturesStr); > - assert(TM && "Unable to create target machine!"); > - > - // Get the target assembler info needed to setup the context. > - const TargetAsmInfo *tai = new TargetAsmInfo(*TM); > - assert(tai && "Unable to create target assembler!"); > - > // Set up the MCContext for creating symbols and MCExpr's. > - MCContext *Ctx = new MCContext(*MAI, *MRI, 0, tai); > + MCContext *Ctx = new MCContext(*MAI, *MRI, 0); > assert(Ctx && "Unable to create MCContext!"); > > // Set up disassembler. > @@ -92,7 +77,7 @@ > > LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType, > GetOpInfo, SymbolLookUp, > - TheTarget, MAI, MRI, TM, tai, > + TheTarget, MAI, MRI, > Ctx, DisAsm, IP); > assert(DC && "Allocation failure!"); > return DC; > > Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.h (original) > +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.h Wed Jul 20 14:50:42 2011 > @@ -22,14 +22,12 @@ > #include "llvm/ADT/OwningPtr.h" > > namespace llvm { > -class TargetAsmInfo; > class MCContext; > class MCAsmInfo; > class MCDisassembler; > class MCInstPrinter; > class MCRegisterInfo; > class Target; > -class TargetMachine; > > // > // This is the disassembler context returned by LLVMCreateDisasm(). > @@ -61,12 +59,6 @@ > llvm::OwningPtr MAI; > // The register information for the target architecture. > llvm::OwningPtr MRI; > - // The target machine instance. > - llvm::OwningPtr TM; > - // The disassembler for the target architecture. > - // FIXME: using llvm::OwningPtr causes a malloc > - // error when this LLVMDisasmContext is deleted. > - const TargetAsmInfo *Tai; > // The assembly context for creating symbols and MCExprs. > llvm::OwningPtr Ctx; > // The disassembler for the target architecture. > @@ -80,12 +72,10 @@ > LLVMSymbolLookupCallback symbolLookUp, > const Target *theTarget, const MCAsmInfo *mAI, > const MCRegisterInfo *mRI, > - llvm::TargetMachine *tM, const TargetAsmInfo *tai, > llvm::MCContext *ctx, const MCDisassembler *disAsm, > MCInstPrinter *iP) : TripleName(tripleName), > DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo), > - SymbolLookUp(symbolLookUp), TheTarget(theTarget), Tai(tai) { > - TM.reset(tM); > + SymbolLookUp(symbolLookUp), TheTarget(theTarget) { > MAI.reset(mAI); > MRI.reset(mRI); > Ctx.reset(ctx); > > Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) > +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Jul 20 14:50:42 2011 > @@ -377,7 +377,7 @@ > SourceMgr sourceMgr; > sourceMgr.setDiagHandler(diag_handler, static_cast(this)); > sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over > - MCContext context(*AsmInfo, *MRI, NULL, NULL); > + MCContext context(*AsmInfo, *MRI, NULL); > OwningPtr streamer(createNullStreamer(context)); > OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, > context, *streamer, > > Modified: llvm/trunk/lib/MC/MCDwarf.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCDwarf.cpp (original) > +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jul 20 14:50:42 2011 > @@ -19,7 +19,6 @@ > #include "llvm/Support/Debug.h" > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/raw_ostream.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/ADT/FoldingSet.h" > #include "llvm/ADT/SmallString.h" > #include "llvm/ADT/StringExtras.h" > @@ -691,7 +690,6 @@ > const MCDwarfFrameInfo &Frame) { > MCContext &Context = Streamer.getContext(); > const MCObjectFileInfo *MOFI = Context.getObjectFileInfo(); > - const TargetAsmInfo &TAI = Context.getTargetAsmInfo(); > bool VerboseAsm = Streamer.isVerboseAsm(); > > // range-start range-length compact-unwind-enc personality-func lsda > @@ -726,7 +724,7 @@ > Streamer.SwitchSection(MOFI->getCompactUnwindSection()); > > // Range Start > - unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI); > + unsigned FDEEncoding = MOFI->getFDEEncoding(UsingCFI); > unsigned Size = getSizeForEncoding(Streamer, FDEEncoding); > if (VerboseAsm) Streamer.AddComment("Range Start"); > Streamer.EmitSymbolValue(Frame.Function, Size); > @@ -771,7 +769,6 @@ > MCContext &context = streamer.getContext(); > const MCRegisterInfo &MRI = context.getRegisterInfo(); > const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); > - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); > bool verboseAsm = streamer.isVerboseAsm(); > > MCSymbol *sectionStart; > @@ -858,7 +855,7 @@ > EmitEncodingByte(streamer, lsdaEncoding, "LSDA Encoding"); > > // Encoding of the FDE pointers > - EmitEncodingByte(streamer, TAI.getFDEEncoding(UsingCFI), > + EmitEncodingByte(streamer, MOFI->getFDEEncoding(UsingCFI), > "FDE Encoding"); > } > > @@ -895,7 +892,6 @@ > MCSymbol *fdeStart = context.CreateTempSymbol(); > MCSymbol *fdeEnd = context.CreateTempSymbol(); > const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); > - const TargetAsmInfo &TAI = context.getTargetAsmInfo(); > bool verboseAsm = streamer.isVerboseAsm(); > > if (!MOFI->isFunctionEHFrameSymbolPrivate() && IsEH) { > @@ -927,7 +923,7 @@ > streamer.EmitSymbolValue(&cieStart, 4); > } > > - unsigned fdeEncoding = TAI.getFDEEncoding(UsingCFI); > + unsigned fdeEncoding = MOFI->getFDEEncoding(UsingCFI); > unsigned size = getSizeForEncoding(streamer, fdeEncoding); > > // PC Begin > > Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) > +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Jul 20 14:50:42 2011 > @@ -21,6 +21,12 @@ > IsFunctionEHFrameSymbolPrivate = false; > SupportsWeakOmittedEHFrame = false; > > + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel > + | dwarf::DW_EH_PE_sdata4; > + LSDAEncoding = FDEEncoding = FDECFIEncoding = dwarf::DW_EH_PE_pcrel; > + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | > + dwarf::DW_EH_PE_sdata4; > + > // .comm doesn't support alignment before Leopard. > if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5)) > CommDirectiveSupportsAlignment = false; > @@ -199,6 +205,45 @@ > } > > void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) { > + if (T.getArch() == Triple::x86) { > + PersonalityEncoding = (RelocM == Reloc::PIC_) > + ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 > + : dwarf::DW_EH_PE_absptr; > + LSDAEncoding = (RelocM == Reloc::PIC_) > + ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 > + : dwarf::DW_EH_PE_absptr; > + FDEEncoding = FDECFIEncoding = (RelocM == Reloc::PIC_) > + ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 > + : dwarf::DW_EH_PE_absptr; > + TTypeEncoding = (RelocM == Reloc::PIC_) > + ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 > + : dwarf::DW_EH_PE_absptr; > + } else if (T.getArch() == Triple::x86_64) { > + FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; > + > + if (RelocM == Reloc::PIC_) { > + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | > + ((CMModel == CodeModel::Small || CMModel == CodeModel::Medium) > + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); > + LSDAEncoding = dwarf::DW_EH_PE_pcrel | > + (CMModel == CodeModel::Small > + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); > + FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; > + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | > + ((CMModel == CodeModel::Small || CMModel == CodeModel::Medium) > + ? dwarf::DW_EH_PE_sdata4 : dwarf::DW_EH_PE_sdata8); > + } else { > + PersonalityEncoding = > + (CMModel == CodeModel::Small || CMModel == CodeModel::Medium) > + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; > + LSDAEncoding = (CMModel == CodeModel::Small) > + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; > + FDEEncoding = dwarf::DW_EH_PE_udata4; > + TTypeEncoding = (CMModel == CodeModel::Small) > + ? dwarf::DW_EH_PE_udata4 : dwarf::DW_EH_PE_absptr; > + } > + } > + > // ELF > BSSSection = > Ctx->getELFSection(".bss", ELF::SHT_NOBITS, > @@ -446,15 +491,21 @@ > } > > void MCObjectFileInfo::InitMCObjectFileInfo(StringRef TT, Reloc::Model relocm, > + CodeModel::Model cm, > MCContext &ctx) { > RelocM = relocm; > + CMModel = cm; > Ctx = &ctx; > > // Common. > CommDirectiveSupportsAlignment = true; > SupportsWeakOmittedEHFrame = true; > IsFunctionEHFrameSymbolPrivate = true; > - EHFrameSection = 0; > + > + PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = > + TTypeEncoding = dwarf::DW_EH_PE_absptr; > + > + EHFrameSection = 0; // Created on demand. > > Triple T(TT); > Triple::ArchType Arch = T.getArch(); > > Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) > +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jul 20 14:50:42 2011 > @@ -33,7 +33,6 @@ > #include "llvm/Support/MemoryBuffer.h" > #include "llvm/Support/SourceMgr.h" > #include "llvm/Support/raw_ostream.h" > -#include "llvm/Target/TargetAsmInfo.h" > #include "llvm/Target/TargetAsmParser.h" > #include > #include > > Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) > +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Jul 20 14:50:42 2011 > @@ -1676,7 +1676,7 @@ > #endif > TAsm = new CBEMCAsmInfo(); > MRI = new MCRegisterInfo(); > - TCtx = new MCContext(*TAsm, *MRI, NULL, NULL); > + TCtx = new MCContext(*TAsm, *MRI, NULL); > Mang = new Mangler(*TCtx, *TD); > > // Keep track of which functions are static ctors/dtors so they can have > > Removed: llvm/trunk/lib/Target/TargetAsmInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=135610&view=auto > ============================================================================== > --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) > +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp (removed) > @@ -1,18 +0,0 @@ > -//===-- llvm/Target/TargetAsmInfo.cpp - Target Assembly Info --------------===// > -// > -// The LLVM Compiler Infrastructure > -// > -// This file is distributed under the University of Illinois Open Source > -// License. See LICENSE.TXT for details. > -// > -//===----------------------------------------------------------------------===// > - > -#include "llvm/Target/TargetAsmInfo.h" > -#include "llvm/Target/TargetLowering.h" > -#include "llvm/Target/TargetLoweringObjectFile.h" > -#include "llvm/Target/TargetMachine.h" > -using namespace llvm; > - > -TargetAsmInfo::TargetAsmInfo(const TargetMachine &TM) { > - TLOF = &TM.getTargetLowering()->getObjFileLowering(); > -} > > Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) > +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Jul 20 14:50:42 2011 > @@ -41,7 +41,8 @@ > void TargetLoweringObjectFile::Initialize(MCContext &ctx, > const TargetMachine &TM) { > Ctx = &ctx; > - InitMCObjectFileInfo(TM.getTargetTriple(), TM.getRelocationModel(), *Ctx); > + InitMCObjectFileInfo(TM.getTargetTriple(), > + TM.getRelocationModel(), TM.getCodeModel(), *Ctx); > } > > TargetLoweringObjectFile::~TargetLoweringObjectFile() { > @@ -322,20 +323,3 @@ > } > } > } > - > -unsigned TargetLoweringObjectFile::getPersonalityEncoding() const { > - return dwarf::DW_EH_PE_absptr; > -} > - > -unsigned TargetLoweringObjectFile::getLSDAEncoding() const { > - return dwarf::DW_EH_PE_absptr; > -} > - > -unsigned TargetLoweringObjectFile::getFDEEncoding(bool CFI) const { > - return dwarf::DW_EH_PE_absptr; > -} > - > -unsigned TargetLoweringObjectFile::getTTypeEncoding() const { > - return dwarf::DW_EH_PE_absptr; > -} > - > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 14:50:42 2011 > @@ -197,11 +197,8 @@ > return new TargetLoweringObjectFileMachO(); > } > > - if (Subtarget->isTargetELF()) { > - if (is64Bit) > - return new X8664_ELFTargetObjectFile(TM); > - return new X8632_ELFTargetObjectFile(TM); > - } > + if (Subtarget->isTargetELF()) > + return new TargetLoweringObjectFileELF(); > if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) > return new TargetLoweringObjectFileCOFF(); > llvm_unreachable("unknown subtarget type"); > > Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.cpp Wed Jul 20 14:50:42 2011 > @@ -43,79 +43,3 @@ > MachineModuleInfo *MMI) const { > return Mang->getSymbol(GV); > } > - > -unsigned X8632_ELFTargetObjectFile::getPersonalityEncoding() const { > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - else > - return DW_EH_PE_absptr; > -} > - > -unsigned X8632_ELFTargetObjectFile::getLSDAEncoding() const { > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - else > - return DW_EH_PE_absptr; > -} > - > -unsigned X8632_ELFTargetObjectFile::getFDEEncoding(bool FDE) const { > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - else > - return DW_EH_PE_absptr; > -} > - > -unsigned X8632_ELFTargetObjectFile::getTTypeEncoding() const { > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - else > - return DW_EH_PE_absptr; > -} > - > -unsigned X8664_ELFTargetObjectFile::getPersonalityEncoding() const { > - CodeModel::Model Model = TM.getCodeModel(); > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | (Model == CodeModel::Small || > - Model == CodeModel::Medium ? > - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); > - > - if (Model == CodeModel::Small || Model == CodeModel::Medium) > - return DW_EH_PE_udata4; > - > - return DW_EH_PE_absptr; > -} > - > -unsigned X8664_ELFTargetObjectFile::getLSDAEncoding() const { > - CodeModel::Model Model = TM.getCodeModel(); > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_pcrel | (Model == CodeModel::Small ? > - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); > - > - if (Model == CodeModel::Small) > - return DW_EH_PE_udata4; > - > - return DW_EH_PE_absptr; > -} > - > -unsigned X8664_ELFTargetObjectFile::getFDEEncoding(bool CFI) const { > - if (CFI) > - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_pcrel | DW_EH_PE_sdata4; > - > - return DW_EH_PE_udata4; > -} > - > -unsigned X8664_ELFTargetObjectFile::getTTypeEncoding() const { > - CodeModel::Model Model = TM.getCodeModel(); > - if (TM.getRelocationModel() == Reloc::PIC_) > - return DW_EH_PE_indirect | DW_EH_PE_pcrel | (Model == CodeModel::Small || > - Model == CodeModel::Medium ? > - DW_EH_PE_sdata4 : DW_EH_PE_sdata8); > - > - if (Model == CodeModel::Small) > - return DW_EH_PE_udata4; > - > - return DW_EH_PE_absptr; > -} > > Modified: llvm/trunk/lib/Target/X86/X86TargetObjectFile.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetObjectFile.h?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86TargetObjectFile.h (original) > +++ llvm/trunk/lib/Target/X86/X86TargetObjectFile.h Wed Jul 20 14:50:42 2011 > @@ -33,28 +33,6 @@ > MachineModuleInfo *MMI) const; > }; > > - class X8632_ELFTargetObjectFile : public TargetLoweringObjectFileELF { > - const X86TargetMachine &TM; > - public: > - X8632_ELFTargetObjectFile(const X86TargetMachine &tm) > - :TM(tm) { } > - virtual unsigned getPersonalityEncoding() const; > - virtual unsigned getLSDAEncoding() const; > - virtual unsigned getFDEEncoding(bool CFI) const; > - virtual unsigned getTTypeEncoding() const; > - }; > - > - class X8664_ELFTargetObjectFile : public TargetLoweringObjectFileELF { > - const X86TargetMachine &TM; > - public: > - X8664_ELFTargetObjectFile(const X86TargetMachine &tm) > - :TM(tm) { } > - virtual unsigned getPersonalityEncoding() const; > - virtual unsigned getLSDAEncoding() const; > - virtual unsigned getFDEEncoding(bool CFI) const; > - virtual unsigned getTTypeEncoding() const; > - }; > - > } // end namespace llvm > > #endif > > Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) > +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jul 20 14:50:42 2011 > @@ -28,10 +28,6 @@ > #include "llvm/Target/TargetAsmParser.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetRegistry.h" > -#include "llvm/Target/TargetAsmInfo.h" // FIXME. > -#include "llvm/Target/TargetLowering.h" // FIXME. > -#include "llvm/Target/TargetLoweringObjectFile.h" // FIXME. > -#include "llvm/Target/TargetMachine.h" // FIXME. > #include "llvm/Target/TargetSelect.h" > #include "llvm/ADT/OwningPtr.h" > #include "llvm/Support/CommandLine.h" > @@ -348,28 +344,11 @@ > // Package up features to be passed to target/subtarget > std::string FeaturesStr; > > - // FIXME: We shouldn't need to do this (and link in codegen). > - // When we split this out, we should do it in a way that makes > - // it straightforward to switch subtargets on the fly (.e.g, > - // the .cpu and .code16 directives). > - OwningPtr TM(TheTarget->createTargetMachine(TripleName, > - MCPU, > - FeaturesStr, > - RelocModel, > - CMModel)); > - > - if (!TM) { > - errs() << ProgName << ": error: could not create target for triple '" > - << TripleName << "'.\n"; > - return 1; > - } > - > - const TargetAsmInfo *tai = new TargetAsmInfo(*TM); > // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and > // MCObjectFileInfo needs a MCContext reference in order to initialize itself. > OwningPtr MOFI(new MCObjectFileInfo()); > - MCContext Ctx(*MAI, *MRI, MOFI.get(), tai); > - MOFI->InitMCObjectFileInfo(TripleName, RelocModel, Ctx); > + MCContext Ctx(*MAI, *MRI, MOFI.get()); > + MOFI->InitMCObjectFileInfo(TripleName, RelocModel, CMModel, Ctx); > > if (SaveTempLabels) > Ctx.setAllowTemporaryLabels(false); > @@ -381,10 +360,6 @@ > formatted_raw_ostream FOS(Out->os()); > OwningPtr Str; > > - const TargetLoweringObjectFile &TLOF = > - TM->getTargetLowering()->getObjFileLowering(); > - const_cast(TLOF).Initialize(Ctx, *TM); > - > OwningPtr MCII(TheTarget->createMCInstrInfo()); > OwningPtr > STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); > > Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) > +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jul 20 14:50:42 2011 > @@ -313,8 +313,7 @@ > passes.add(createVerifierPass()); > > // mark which symbols can not be internalized > - MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), > - NULL, NULL); > + MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), NULL); > Mangler mangler(Context, *_target->getTargetData()); > std::vector mustPreserveList; > SmallPtrSet asmUsed; > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=135611&r1=135610&r2=135611&view=diff > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Jul 20 14:50:42 2011 > @@ -664,8 +664,7 @@ > > bool LTOModule::ParseSymbols() { > // Use mangler to add GlobalPrefix to names to match linker names. > - MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), > - NULL, NULL); > + MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL); > Mangler mangler(Context, *_target->getTargetData()); > > // add functions > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Wed Jul 20 15:00:06 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 20 Jul 2011 20:00:06 -0000 Subject: [llvm-commits] [llvm] r135613 - /llvm/trunk/lib/Target/CMakeLists.txt Message-ID: <20110720200006.31BDB2A6C12D@llvm.org> Author: d0k Date: Wed Jul 20 15:00:06 2011 New Revision: 135613 URL: http://llvm.org/viewvc/llvm-project?rev=135613&view=rev Log: Fix cmake again :) Modified: llvm/trunk/lib/Target/CMakeLists.txt Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=135613&r1=135612&r2=135613&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Wed Jul 20 15:00:06 2011 @@ -1,7 +1,6 @@ add_llvm_library(LLVMTarget Mangler.cpp Target.cpp - TargetAsmInfo.cpp TargetAsmLexer.cpp TargetData.cpp TargetELFWriterInfo.cpp From rafael.espindola at gmail.com Wed Jul 20 15:29:59 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 20 Jul 2011 16:29:59 -0400 Subject: [llvm-commits] [llvm] r135611 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Target/ lib/Target/CBackend/ lib/Target/X86/ tools/llvm-mc/ tools/lto/ In-Reply-To: <20110720195043.5D0102A6C12D@llvm.org> References: <20110720195043.5D0102A6C12D@llvm.org> Message-ID: <4E273AC7.1090709@gmail.com> Thanks! Cheers, Rafael From grosbach at apple.com Wed Jul 20 15:32:09 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 20:32:09 -0000 Subject: [llvm-commits] [llvm] r135616 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb2.td Disassembler/ARMDisassemblerCore.cpp Disassembler/ThumbDisassemblerCore.h Message-ID: <20110720203209.BFAF32A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 15:32:09 2011 New Revision: 135616 URL: http://llvm.org/viewvc/llvm-project?rev=135616&view=rev Log: ARM: Tidy up representation of PKH instruction. The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135616&r1=135615&r2=135616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 20 15:32:09 2011 @@ -854,11 +854,11 @@ bits<4> Rd; bits<4> Rn; bits<4> Rm; - bits<8> sh; + bits<5> sh; let Inst{27-20} = opcod; let Inst{19-16} = Rn; let Inst{15-12} = Rd; - let Inst{11-7} = sh{7-3}; + let Inst{11-7} = sh; let Inst{6} = tb; let Inst{5-4} = 0b01; let Inst{3-0} = Rm; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135616&r1=135615&r2=135616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 20 15:32:09 2011 @@ -3111,18 +3111,13 @@ (and (srl GPR:$Rm, (i32 8)), 0xFF)), (REVSH GPR:$Rm)>; -def lsl_shift_imm : SDNodeXFormgetZExtValue()); - return CurDAG->getTargetConstant(Sh, MVT::i32); -}]>; - def lsl_amt : ImmLeaf 0 && Imm < 32; -}], lsl_shift_imm>; + return Imm >= 0 && Imm < 32; +}]>; def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd), - (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh), - IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", + (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), + IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF), (and (shl GPR:$Rm, lsl_amt:$sh), 0xFFFF0000)))]>, @@ -3132,22 +3127,17 @@ def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)), (PKHBT GPR:$Rn, GPR:$Rm, 0)>; def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)), - (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>; - -def asr_shift_imm : SDNodeXFormgetZExtValue()); - return CurDAG->getTargetConstant(Sh, MVT::i32); -}]>; + (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>; def asr_amt : ImmLeaf 0 && Imm <= 32; -}], asr_shift_imm>; +}]>; // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd), - (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh), - IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", + (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), + IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000), (and (sra GPR:$Rm, asr_amt:$sh), 0xFFFF)))]>, @@ -3156,10 +3146,10 @@ // Alternate cases for PKHTB where identities eliminate some nodes. Note that // a shift amount of 0 is *not legal* here, it is PKHBT instead. def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)), - (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>; + (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>; def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)), - (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>; + (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>; //===----------------------------------------------------------------------===// // Comparison Instructions... Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135616&r1=135615&r2=135616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 20 15:32:09 2011 @@ -2613,8 +2613,8 @@ (t2REVSH rGPR:$Rm)>; def t2PKHBT : T2ThreeReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh), - IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", + (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), + IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), (and (shl rGPR:$Rm, lsl_amt:$sh), 0xFFFF0000)))]>, @@ -2625,9 +2625,9 @@ let Inst{5} = 0; // BT form let Inst{4} = 0; - bits<8> sh; - let Inst{14-12} = sh{7-5}; - let Inst{7-6} = sh{4-3}; + bits<5> sh; + let Inst{14-12} = sh{4-2}; + let Inst{7-6} = sh{1-0}; } // Alternate cases for PKHBT where identities eliminate some nodes. @@ -2635,14 +2635,14 @@ (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), - (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>, + (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, Requires<[HasT2ExtractPack, IsThumb2]>; // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def t2PKHTB : T2ThreeReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh), - IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", + (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), + IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), (and (sra rGPR:$Rm, asr_amt:$sh), 0xFFFF)))]>, @@ -2653,19 +2653,19 @@ let Inst{5} = 1; // TB form let Inst{4} = 0; - bits<8> sh; - let Inst{14-12} = sh{7-5}; - let Inst{7-6} = sh{4-3}; + bits<5> sh; + let Inst{14-12} = sh{4-2}; + let Inst{7-6} = sh{1-0}; } // Alternate cases for PKHTB where identities eliminate some nodes. Note that // a shift amount of 0 is *not legal* here, it is PKHBT instead. def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), - (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>, + (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), - (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>, + (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, Requires<[HasT2ExtractPack, IsThumb2]>; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135616&r1=135615&r2=135616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 20 15:32:09 2011 @@ -1638,7 +1638,10 @@ else if (Opcode == ARM::PKHTB) Opc = ARM_AM::asr; getImmShiftSE(Opc, ShiftAmt); - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); + if (Opcode == ARM::PKHBT || Opcode == ARM::PKHTB) + MI.addOperand(MCOperand::CreateImm(ShiftAmt)); + else + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=135616&r1=135615&r2=135616&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Jul 20 15:32:09 2011 @@ -1502,7 +1502,12 @@ unsigned imm5 = getShiftAmtBits(insn); ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift; unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp); - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt))); + // The PKHBT/PKHTB instructions have an implied shift type and so just + // use a plain immediate for the amount. + if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB) + MI.addOperand(MCOperand::CreateImm(ShAmt)); + else + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt))); } ++OpIdx; } From greened at obbligato.org Wed Jul 20 15:36:01 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 15:36:01 -0500 Subject: [llvm-commits] [PATCH 02/20] [AVX] Remove Mutating Members from Inits In-Reply-To: (David A. Greene's message of "Wed, 20 Jul 2011 11:02:16 -0500") References: <8CEDA0FF-6683-4ACE-95BB-10063A977150@2pi.dk> Message-ID: dag at cray.com (David A. Greene) writes: >> You have a lot of explicit ArrayRef constructor calls. That shouldn't be necessary. You should be getting implicit conversions. > > I'll check that out. Certainly I won't get implicit conversions for > iterator pairs. :) > >> And please use the new makeArrayRef when that doesn't work. >> >> + Init *NewBits[1] = { VI }; >> >> This should not be necessary, ArrayRef has a single-element constructor. > > Urk. Missed that one. Thanks for the pointer. Both done. Thanks! -Dave From grosbach at apple.com Wed Jul 20 15:49:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 20:49:03 -0000 Subject: [llvm-commits] [llvm] r135617 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb2.td Message-ID: <20110720204903.5C7E82A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 15:49:03 2011 New Revision: 135617 URL: http://llvm.org/viewvc/llvm-project?rev=135617&view=rev Log: Tidy up a bit. Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135617&r1=135616&r2=135617&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 20 15:49:03 2011 @@ -847,6 +847,9 @@ } // PKH instructions +def pkh_lsl_amt : ImmLeaf= 0 && Imm < 32; }]>; +def pkh_asr_amt : ImmLeaf 0 && Imm <= 32; }]>; + class APKHI opcod, bit tb, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I; -def lsl_amt : ImmLeaf= 0 && Imm < 32; -}]>; - def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF), - (and (shl GPR:$Rm, lsl_amt:$sh), + (and (shl GPR:$Rm, pkh_lsl_amt:$sh), 0xFFFF0000)))]>, Requires<[IsARM, HasV6]>; @@ -3129,17 +3125,13 @@ def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)), (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>; -def asr_amt : ImmLeaf 0 && Imm <= 32; -}]>; - // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000), - (and (sra GPR:$Rm, asr_amt:$sh), + (and (sra GPR:$Rm, pkh_asr_amt:$sh), 0xFFFF)))]>, Requires<[IsARM, HasV6]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135617&r1=135616&r2=135617&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 20 15:49:03 2011 @@ -2616,7 +2616,7 @@ (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), - (and (shl rGPR:$Rm, lsl_amt:$sh), + (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 0xFFFF0000)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11101; @@ -2644,7 +2644,7 @@ (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), - (and (sra rGPR:$Rm, asr_amt:$sh), + (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 0xFFFF)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11101; From greened at obbligato.org Wed Jul 20 15:52:51 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 15:52:51 -0500 Subject: [llvm-commits] [PATCH 03/20] [AVX] Remove non-const Iterators In-Reply-To: (David A. Greene's message of "Wed, 20 Jul 2011 11:02:31 -0500") References: <354aba23155343587d71eb8b0b3425b5f0170702.1311100069.git.dag@cray.com> Message-ID: dag at cray.com (David A. Greene) writes: > Jakob Stoklund Olesen writes: > >> How about adding a ListInit method that returns an ArrayRef instead? > > Makes sense. Thanks! Done! -Dave From eli.friedman at gmail.com Wed Jul 20 15:58:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 20:58:07 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r135618 - /llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Message-ID: <20110720205807.87C532A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 15:58:07 2011 New Revision: 135618 URL: http://llvm.org/viewvc/llvm-project?rev=135618&view=rev Log: Attempt to unbreak llvm-gcc. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=135618&r1=135617&r2=135618&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Wed Jul 20 15:58:07 2011 @@ -3955,6 +3955,9 @@ case CM_MEDIUM_PIC: \ CMModel = llvm::CodeModel::Medium; \ break; \ + case CM_32: \ + CMModel = llvm::CodeModel::Default; \ + break; \ } #define LLVM_SET_MACHINE_OPTIONS(argvec) \ From pichet2000 at gmail.com Wed Jul 20 16:35:29 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 20 Jul 2011 21:35:29 -0000 Subject: [llvm-commits] [llvm] r135623 - /llvm/trunk/tools/llvm-objdump/MCFunction.cpp Message-ID: <20110720213529.C32CF2A6C12D@llvm.org> Author: fpichet Date: Wed Jul 20 16:35:29 2011 New Revision: 135623 URL: http://llvm.org/viewvc/llvm-project?rev=135623&view=rev Log: Unbreak the MSVC build. Since the "next" function already exists in the MSVC headers, we need the explicit llvm:: qualifier to prevent a conflict. Modified: llvm/trunk/tools/llvm-objdump/MCFunction.cpp Modified: llvm/trunk/tools/llvm-objdump/MCFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MCFunction.cpp?rev=135623&r1=135622&r2=135623&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/MCFunction.cpp (original) +++ llvm/trunk/tools/llvm-objdump/MCFunction.cpp Wed Jul 20 16:35:29 2011 @@ -95,7 +95,7 @@ BB.addSucc(&f.getBlockAtAddress(Inst.Address+Inst.Size+Imm)); // Conditional branches can also fall through to the next block. if (Desc.isConditionalBranch() && llvm::next(i) != e) - BB.addSucc(&next(i)->second); + BB.addSucc(&llvm::next(i)->second); } else { // Indirect branch. Bail and add all blocks of the function as a // successor. @@ -104,8 +104,8 @@ } } else { // No branch. Fall through to the next block. - if (!Desc.isReturn() && next(i) != e) - BB.addSucc(&next(i)->second); + if (!Desc.isReturn() && llvm::next(i) != e) + BB.addSucc(&llvm::next(i)->second); } } From eli.friedman at gmail.com Wed Jul 20 16:35:53 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 21:35:53 -0000 Subject: [llvm-commits] [llvm] r135624 - /llvm/trunk/docs/LangRef.html Message-ID: <20110720213553.CC6D92A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 16:35:53 2011 New Revision: 135624 URL: http://llvm.org/viewvc/llvm-project?rev=135624&view=rev Log: Commit LangRef changes for LLVM concurrency model. Start of supporting C++0x memory model and atomics. See thread on llvmdev titled "Reviving the new LLVM concurrency model". Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=135624&r1=135623&r2=135624&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Jul 20 16:35:53 2011 @@ -53,6 +53,7 @@

  • Data Layout
  • Pointer Aliasing Rules
  • Volatile Memory Accesses
    • +
  • Memory Model for Concurrent Operations
  • Type System @@ -1470,6 +1471,91 @@ + +

    + Memory Model for Concurrent Operations +

    + +
    + +

    The LLVM IR does not define any way to start parallel threads of execution +or to register signal handlers. Nonetheless, there are platform-specific +ways to create them, and we define LLVM IR's behavior in their presence. This +model is inspired by the C++0x memory model.

    + +

    We define a happens-before partial order as the least partial order +that

    +
      +
    • Is a superset of single-thread program order, and
      • +
    • When a synchronizes-with b, includes an edge from + a to b. Synchronizes-with pairs are introduced + by platform-specific techniques, like pthread locks, thread + creation, thread joining, etc., and by the atomic operations described + in the Atomic intrinsics section.
      • +
    + +

    Note that program order does not introduce happens-before edges +between a thread and signals executing inside that thread.

    + +

    Every (defined) read operation (load instructions, memcpy, atomic +loads/read-modify-writes, etc.) R reads a series of bytes written by +(defined) write operations (store instructions, atomic +stores/read-modify-writes, memcpy, etc.). For each byte, R reads the +value written by some write that it may see, given any relevant +happens-before constraints. Rbyte may +see any write to the same byte, except:

    + +
      +
    • If write1 happens before + write2, and write2 happens + before Rbyte, then Rbyte + must not see write1. +
    • If Rbyte happens before write3, + then Rbyte must not see + write3. +
    + +

    Given that definition, Rbyte is defined as follows: +

      +
    • If there is no write to the same byte that happens before + Rbyte, Rbyte returns + undef for that byte. +
    • If Rbyte may see exactly one write, + Rbyte returns the value written by that + write.
      • +
    • If Rbyte and all the writes it may see are + atomic, it chooses one of those writes and returns it value. + Given any two bytes in a given read R, if the set of + writes Rbyte may see is the same as the set + of writes another byte may see, they will both choose the same write. +
    • Otherwise Rbyte returns undef.
      • +
    + +

    R returns the value composed of the series of bytes it read. +This implies that some bytes within the value may be undef +without the entire value being undef. Note that this only +defines the semantics of the operation; it doesn't mean that targets will +emit more than one instruction to read the series of bytes.

    + +

    Note that in cases where none of the atomic intrinsics are used, this model +places only one restriction on IR transformations on top of what is required +for single-threaded execution: introducing a store to a byte which might not +otherwise be stored to can introduce undefined behavior.

    + + + +
    + From eli.friedman at gmail.com Wed Jul 20 16:37:48 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 21:37:48 -0000 Subject: [llvm-commits] [llvm] r135625 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/scalar-promote-memmodel.ll Message-ID: <20110720213748.0D9962A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 16:37:47 2011 New Revision: 135625 URL: http://llvm.org/viewvc/llvm-project?rev=135625&view=rev Log: Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. Added: llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=135625&r1=135624&r2=135625&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 20 16:37:47 2011 @@ -151,6 +151,11 @@ /// bool isSafeToExecuteUnconditionally(Instruction &I); + /// isGuaranteedToExecute - Check that the instruction is guaranteed to + /// execute. + /// + bool isGuaranteedToExecute(Instruction &I); + /// pointerInvalidatedByLoop - Return true if the body of this loop may /// store into the memory location pointed to by V. /// @@ -577,6 +582,10 @@ if (Inst.isSafeToSpeculativelyExecute()) return true; + return isGuaranteedToExecute(Inst); +} + +bool LICM::isGuaranteedToExecute(Instruction &Inst) { // Otherwise we have to check to make sure that the instruction dominates all // of the exit blocks. If it doesn't, then there is a path out of the loop // which does not execute this instruction, so we can't hoist it. @@ -713,33 +722,36 @@ // If there is an non-load/store instruction in the loop, we can't promote // it. - unsigned InstAlignment; - if (LoadInst *load = dyn_cast(Use)) { + if (isa(Use)) { assert(!cast(Use)->isVolatile() && "AST broken"); - InstAlignment = load->getAlignment(); } else if (StoreInst *store = dyn_cast(Use)) { // Stores *of* the pointer are not interesting, only stores *to* the // pointer. if (Use->getOperand(1) != ASIV) continue; - InstAlignment = store->getAlignment(); + unsigned InstAlignment = store->getAlignment(); assert(!cast(Use)->isVolatile() && "AST broken"); - } else - return; // Not a load or store. - // If the alignment of this instruction allows us to specify a more - // restrictive (and performant) alignment and if we are sure this - // instruction will be executed, update the alignment. - // Larger is better, with the exception of 0 being the best alignment. - if ((InstAlignment > Alignment || InstAlignment == 0) - && (Alignment != 0)) - if (isSafeToExecuteUnconditionally(*Use)) { - GuaranteedToExecute = true; - Alignment = InstAlignment; - } + // Note that we only check GuaranteedToExecute inside the store case + // so that we do not introduce stores where they did not exist before + // (which would break the LLVM concurrency model). + + // If the alignment of this instruction allows us to specify a more + // restrictive (and performant) alignment and if we are sure this + // instruction will be executed, update the alignment. + // Larger is better, with the exception of 0 being the best alignment. + if ((InstAlignment > Alignment || InstAlignment == 0) + && (Alignment != 0)) + if (isGuaranteedToExecute(*Use)) { + GuaranteedToExecute = true; + Alignment = InstAlignment; + } + + if (!GuaranteedToExecute) + GuaranteedToExecute = isGuaranteedToExecute(*Use); - if (!GuaranteedToExecute) - GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use); + } else + return; // Not a load or store. LoopUses.push_back(Use); } Added: llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll?rev=135625&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll (added) +++ llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll Wed Jul 20 16:37:47 2011 @@ -0,0 +1,37 @@ +; RUN: opt < %s -basicaa -licm -S | FileCheck %s + +; Make sure we don't hoist a conditionally-executed store out of the loop; +; it would violate the concurrency memory model + + at g = common global i32 0, align 4 + +define void @bar(i32 %n, i32 %b) nounwind uwtable ssp { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %i.0 = phi i32 [ 0, %entry ], [ %inc5, %for.inc ] + %cmp = icmp slt i32 %i.0, %n + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %tobool = icmp eq i32 %b, 0 + br i1 %tobool, label %for.inc, label %if.then + +if.then: ; preds = %for.body + %tmp3 = load i32* @g, align 4 + %inc = add nsw i32 %tmp3, 1 + store i32 %inc, i32* @g, align 4 + br label %for.inc + +; CHECK: load i32* +; CHECK-NEXT: add +; CHECK-NEXT: store i32 + +for.inc: ; preds = %for.body, %if.then + %inc5 = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} From grosbach at apple.com Wed Jul 20 16:40:26 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 20 Jul 2011 21:40:26 -0000 Subject: [llvm-commits] [llvm] r135626 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h utils/TableGen/EDEmitter.cpp Message-ID: <20110720214026.E209D2A6C12D@llvm.org> Author: grosbach Date: Wed Jul 20 16:40:26 2011 New Revision: 135626 URL: http://llvm.org/viewvc/llvm-project?rev=135626&view=rev Log: ARM PKH shift ammount operand printing tweaks. Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 20 16:40:26 2011 @@ -847,8 +847,12 @@ } // PKH instructions -def pkh_lsl_amt : ImmLeaf= 0 && Imm < 32; }]>; -def pkh_asr_amt : ImmLeaf 0 && Imm <= 32; }]>; +def pkh_lsl_amt: Operand, ImmLeaf= 0 && Imm < 32; }]>{ + let PrintMethod = "printPKHLSLShiftImm"; +} +def pkh_asr_amt: Operand, ImmLeaf 0 && Imm <= 32; }]>{ + let PrintMethod = "printPKHASRShiftImm"; +} class APKHI opcod, bit tb, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 20 16:40:26 2011 @@ -3112,8 +3112,8 @@ (REVSH GPR:$Rm)>; def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd), - (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), - IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", + (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh), + IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF), (and (shl GPR:$Rm, pkh_lsl_amt:$sh), 0xFFFF0000)))]>, @@ -3128,8 +3128,8 @@ // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd), - (ins GPR:$Rn, GPR:$Rm, i32imm:$sh), - IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", + (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh), + IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000), (and (sra GPR:$Rm, pkh_asr_amt:$sh), 0xFFFF)))]>, Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 20 16:40:26 2011 @@ -1632,16 +1632,11 @@ && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Extract the 5-bit immediate field Inst{11-7}. unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F; - ARM_AM::ShiftOpc Opc = ARM_AM::no_shift; - if (Opcode == ARM::PKHBT) - Opc = ARM_AM::lsl; - else if (Opcode == ARM::PKHTB) - Opc = ARM_AM::asr; - getImmShiftSE(Opc, ShiftAmt); if (Opcode == ARM::PKHBT || Opcode == ARM::PKHTB) MI.addOperand(MCOperand::CreateImm(ShiftAmt)); else - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ARM_AM::no_shift, + ShiftAmt))); ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Jul 20 16:40:26 2011 @@ -1498,16 +1498,17 @@ MI.addOperand(MCOperand::CreateImm(Imm)); } else { // Build the constant shift specifier operand. - unsigned bits2 = getShiftTypeBits(insn); unsigned imm5 = getShiftAmtBits(insn); - ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift; - unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp); // The PKHBT/PKHTB instructions have an implied shift type and so just // use a plain immediate for the amount. if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB) - MI.addOperand(MCOperand::CreateImm(ShAmt)); - else + MI.addOperand(MCOperand::CreateImm(imm5)); + else { + ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift; + unsigned bits2 = getShiftTypeBits(insn); + unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp); MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt))); + } } ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jul 20 16:40:26 2011 @@ -441,6 +441,25 @@ O << ARM_AM::getSORegOffset(ShiftOp); } +void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNum).getImm(); + if (Imm == 0) + return; + assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); + O << ", lsl #" << Imm; +} + +void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNum).getImm(); + // A shift amount of 32 is encoded as 0. + if (Imm == 0) + Imm = 32; + assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); + O << ", asr #" << Imm; +} + void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O) { O << "{"; Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jul 20 16:40:26 2011 @@ -65,6 +65,8 @@ raw_ostream &O); void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O); Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=135626&r1=135625&r2=135626&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Jul 20 16:40:26 2011 @@ -594,6 +594,8 @@ IMM("imm0_4095"); IMM("imm0_65535"); IMM("imm0_65535_expr"); + IMM("pkh_lsl_amt"); + IMM("pkh_asr_amt"); IMM("jt2block_operand"); IMM("t_imm_s4"); IMM("pclabel"); From greened at obbligato.org Wed Jul 20 16:44:49 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 16:44:49 -0500 Subject: [llvm-commits] [PATCH 09/20] [AVX] Make IntInit Unique In-Reply-To: (David A. Greene's message of "Wed, 20 Jul 2011 11:01:30 -0500") References: <98D73C97-E711-4466-9A59-22327EFF7BA1@2pi.dk> Message-ID: dag at cray.com (David A. Greene) writes: > Jakob Stoklund Olesen writes: >> This pattern is faster and simpler: >> >> const IntInit *&I = ThePool[V]; >> if (!I) I = new IntInit(V); >> return I; > > Ok. Done! -Dave From dpatel at apple.com Wed Jul 20 16:57:04 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 20 Jul 2011 21:57:04 -0000 Subject: [llvm-commits] [llvm] r135627 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/CodeGen/X86/dbg-large-unsigned-const.ll Message-ID: <20110720215705.089FB2A6C12D@llvm.org> Author: dpatel Date: Wed Jul 20 16:57:04 2011 New Revision: 135627 URL: http://llvm.org/viewvc/llvm-project?rev=135627&view=rev Log: While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. Added: llvm/trunk/test/CodeGen/X86/dbg-large-unsigned-const.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=135627&r1=135626&r2=135627&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Wed Jul 20 16:57:04 2011 @@ -439,27 +439,36 @@ addBlock(Die, Attribute, 0, Block); } +/// isTypeSigned - Return true if the type is signed. +static bool isTypeSigned(DIType Ty, int *SizeInBits) { + if (Ty.isDerivedType()) + return isTypeSigned(DIDerivedType(Ty).getTypeDerivedFrom(), SizeInBits); + if (Ty.isBasicType()) + if (DIBasicType(Ty).getEncoding() == dwarf::DW_ATE_signed + || DIBasicType(Ty).getEncoding() == dwarf::DW_ATE_signed_char) { + *SizeInBits = Ty.getSizeInBits(); + return true; + } + return false; +} + /// addConstantValue - Add constant value entry in variable DIE. bool CompileUnit::addConstantValue(DIE *Die, const MachineOperand &MO, DIType Ty) { assert (MO.isImm() && "Invalid machine operand!"); DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); - unsigned form = dwarf::DW_FORM_udata; - switch (Ty.getSizeInBits()) { - case 8: form = dwarf::DW_FORM_data1; break; - case 16: form = dwarf::DW_FORM_data2; break; - case 32: form = dwarf::DW_FORM_data4; break; - case 64: form = dwarf::DW_FORM_data8; break; + int SizeInBits = -1; + bool SignedConstant = isTypeSigned(Ty, &SizeInBits); + unsigned Form = SignedConstant ? dwarf::DW_FORM_sdata : dwarf::DW_FORM_udata; + switch (SizeInBits) { + case 8: Form = dwarf::DW_FORM_data1; break; + case 16: Form = dwarf::DW_FORM_data2; break; + case 32: Form = dwarf::DW_FORM_data4; break; + case 64: Form = dwarf::DW_FORM_data8; break; default: break; } - - DIBasicType BTy(Ty); - if (BTy.Verify() && - (BTy.getEncoding() == dwarf::DW_ATE_signed - || BTy.getEncoding() == dwarf::DW_ATE_signed_char)) - addSInt(Block, 0, form, MO.getImm()); - else - addUInt(Block, 0, form, MO.getImm()); + SignedConstant ? addSInt(Block, 0, Form, MO.getImm()) + : addUInt(Block, 0, Form, MO.getImm()); addBlock(Die, dwarf::DW_AT_const_value, 0, Block); return true; Added: llvm/trunk/test/CodeGen/X86/dbg-large-unsigned-const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-large-unsigned-const.ll?rev=135627&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-large-unsigned-const.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-large-unsigned-const.ll Wed Jul 20 16:57:04 2011 @@ -0,0 +1,61 @@ +; RUN: llc -filetype=obj %s -o /dev/null +; Hanle large unsigned constant values. +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-macosx10.7.0" + +define zeroext i1 @_Z3iseRKxS0_(i64* nocapture %LHS, i64* nocapture %RHS) nounwind readonly optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i64* %LHS}, i64 0, metadata !7), !dbg !13 + tail call void @llvm.dbg.value(metadata !{i64* %RHS}, i64 0, metadata !11), !dbg !14 + %tmp1 = load i64* %LHS, align 4, !dbg !15, !tbaa !17 + %tmp3 = load i64* %RHS, align 4, !dbg !15, !tbaa !17 + %cmp = icmp eq i64 %tmp1, %tmp3, !dbg !15 + ret i1 %cmp, !dbg !15 +} + +define zeroext i1 @_Z2fnx(i64 %a) nounwind readnone optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i64 %a}, i64 0, metadata !12), !dbg !20 + tail call void @llvm.dbg.value(metadata !{i64 %a}, i64 0, metadata !12), !dbg !20 + tail call void @llvm.dbg.value(metadata !{i64 %a}, i64 0, metadata !21), !dbg !24 + tail call void @llvm.dbg.value(metadata !25, i64 0, metadata !26), !dbg !27 + %cmp.i = icmp eq i64 %a, 9223372036854775807, !dbg !28 + ret i1 %cmp.i, !dbg !22 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !6} +!llvm.dbg.lv._Z3iseRKxS0_ = !{!7, !11} +!llvm.dbg.lv._Z2fnx = !{!12} + +!0 = metadata !{i32 655377, i32 0, i32 4, metadata !"lli.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 135593)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 655406, i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !"_Z3iseRKxS0_", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 655401, metadata !"lli.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 655381, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 655396, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 655406, i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !"_Z2fnx", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 655617, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 655376, metadata !0, null, null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ] +!9 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_const_type ] +!10 = metadata !{i32 655396, metadata !0, metadata !"long long int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 655617, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 655617, metadata !6, metadata !"a", metadata !2, i32 16777222, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!13 = metadata !{i32 2, i32 27, metadata !1, null} +!14 = metadata !{i32 2, i32 49, metadata !1, null} +!15 = metadata !{i32 3, i32 3, metadata !16, null} +!16 = metadata !{i32 655371, metadata !1, i32 2, i32 54, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{metadata !"long long", metadata !18} +!18 = metadata !{metadata !"omnipotent char", metadata !19} +!19 = metadata !{metadata !"Simple C/C++ TBAA", null} +!20 = metadata !{i32 6, i32 19, metadata !6, null} +!21 = metadata !{i32 655617, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 7, i32 10, metadata !23, null} +!23 = metadata !{i32 655371, metadata !6, i32 6, i32 22, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 2, i32 27, metadata !1, metadata !22} +!25 = metadata !{i64 9223372036854775807} +!26 = metadata !{i32 655617, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] +!27 = metadata !{i32 2, i32 49, metadata !1, metadata !22} +!28 = metadata !{i32 3, i32 3, metadata !16, metadata !22} From eli.friedman at gmail.com Wed Jul 20 16:57:23 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 20 Jul 2011 21:57:23 -0000 Subject: [llvm-commits] [llvm] r135628 - in /llvm/trunk/lib/Transforms: InstCombine/InstCombineCasts.cpp InstCombine/InstCombineCompares.cpp InstCombine/InstCombineSelect.cpp InstCombine/InstCombineShifts.cpp Utils/Local.cpp Message-ID: <20110720215723.CB7E02A6C12D@llvm.org> Author: efriedma Date: Wed Jul 20 16:57:23 2011 New Revision: 135628 URL: http://llvm.org/viewvc/llvm-project?rev=135628&view=rev Log: Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=135628&r1=135627&r2=135628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Wed Jul 20 16:57:23 2011 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "InstCombine.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Target/TargetData.h" #include "llvm/Support/PatternMatch.h" using namespace llvm; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=135628&r1=135627&r2=135628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Jul 20 16:57:23 2011 @@ -13,6 +13,7 @@ #include "InstCombine.h" #include "llvm/IntrinsicInst.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/MemoryBuiltins.h" #include "llvm/Target/TargetData.h" Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=135628&r1=135627&r2=135628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Jul 20 16:57:23 2011 @@ -13,6 +13,7 @@ #include "InstCombine.h" #include "llvm/Support/PatternMatch.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" using namespace llvm; using namespace PatternMatch; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=135628&r1=135627&r2=135628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Wed Jul 20 16:57:23 2011 @@ -13,6 +13,7 @@ #include "InstCombine.h" #include "llvm/IntrinsicInst.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Support/PatternMatch.h" using namespace llvm; Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=135628&r1=135627&r2=135628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed Jul 20 16:57:23 2011 @@ -27,7 +27,6 @@ #include "llvm/Analysis/DebugInfo.h" #include "llvm/Analysis/DIBuilder.h" #include "llvm/Analysis/Dominators.h" -#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/ProfileInfo.h" #include "llvm/Analysis/ValueTracking.h" From dpatel at apple.com Wed Jul 20 17:18:50 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 20 Jul 2011 22:18:50 -0000 Subject: [llvm-commits] [llvm] r135629 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110720221850.9A4792A6C12D@llvm.org> Author: dpatel Date: Wed Jul 20 17:18:50 2011 New Revision: 135629 URL: http://llvm.org/viewvc/llvm-project?rev=135629&view=rev Log: There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/Analysis/DebugInfo.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=135629&r1=135628&r2=135629&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Jul 20 17:18:50 2011 @@ -614,6 +614,8 @@ return (getUnsignedField(6) & FlagArtificial) != 0; } + /// getInlinedAt - If this variable is inlined then return inline location. + MDNode *getInlinedAt(); /// Verify - Verify that a variable descriptor is well formed. bool Verify() const; Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=135629&r1=135628&r2=135629&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Jul 20 17:18:50 2011 @@ -116,6 +116,12 @@ return DbgNode->getNumOperands()-8; } +/// getInlinedAt - If this variable is inlined then return inline location. +MDNode *DIVariable::getInlinedAt() { + if (getVersion() <= llvm::LLVMDebugVersion9) + return NULL; + return dyn_cast_or_null(DbgNode->getOperand(7)); +} //===----------------------------------------------------------------------===// // Predicates Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=135629&r1=135628&r2=135629&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jul 20 17:18:50 2011 @@ -1410,8 +1410,16 @@ if (DV.getTag() == dwarf::DW_TAG_arg_variable && DISubprogram(DV.getContext()).describes(MF->getFunction())) Scope = CurrentFnDbgScope; - else - Scope = findDbgScope(MInsn->getDebugLoc()); + else { + if (DV.getVersion() <= LLVMDebugVersion9) + Scope = findDbgScope(MInsn->getDebugLoc()); + else { + if (MDNode *IA = DV.getInlinedAt()) + Scope = InlinedDbgScopeMap.lookup(DebugLoc::getFromDILocation(IA)); + else + Scope = DbgScopeMap.lookup(cast(DV->getOperand(1))); + } + } // If variable scope is not found then skip this variable. if (!Scope) continue; From zwarich at apple.com Wed Jul 20 17:20:29 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 20 Jul 2011 15:20:29 -0700 Subject: [llvm-commits] [llvm] r135625 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/scalar-promote-memmodel.ll In-Reply-To: <20110720213748.0D9962A6C12D@llvm.org> References: <20110720213748.0D9962A6C12D@llvm.org> Message-ID: <0B0781B7-6663-4BCA-8B72-A7E0D497F796@apple.com> Did you do any performance testing for this change? Cameron On Jul 20, 2011, at 2:37 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Jul 20 16:37:47 2011 > New Revision: 135625 > > URL: http://llvm.org/viewvc/llvm-project?rev=135625&view=rev > Log: > Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. > > > Added: > llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll > Modified: > llvm/trunk/lib/Transforms/Scalar/LICM.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=135625&r1=135624&r2=135625&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 20 16:37:47 2011 > @@ -151,6 +151,11 @@ > /// > bool isSafeToExecuteUnconditionally(Instruction &I); > > + /// isGuaranteedToExecute - Check that the instruction is guaranteed to > + /// execute. > + /// > + bool isGuaranteedToExecute(Instruction &I); > + > /// pointerInvalidatedByLoop - Return true if the body of this loop may > /// store into the memory location pointed to by V. > /// > @@ -577,6 +582,10 @@ > if (Inst.isSafeToSpeculativelyExecute()) > return true; > > + return isGuaranteedToExecute(Inst); > +} > + > +bool LICM::isGuaranteedToExecute(Instruction &Inst) { > // Otherwise we have to check to make sure that the instruction dominates all > // of the exit blocks. If it doesn't, then there is a path out of the loop > // which does not execute this instruction, so we can't hoist it. > @@ -713,33 +722,36 @@ > > // If there is an non-load/store instruction in the loop, we can't promote > // it. > - unsigned InstAlignment; > - if (LoadInst *load = dyn_cast(Use)) { > + if (isa(Use)) { > assert(!cast(Use)->isVolatile() && "AST broken"); > - InstAlignment = load->getAlignment(); > } else if (StoreInst *store = dyn_cast(Use)) { > // Stores *of* the pointer are not interesting, only stores *to* the > // pointer. > if (Use->getOperand(1) != ASIV) > continue; > - InstAlignment = store->getAlignment(); > + unsigned InstAlignment = store->getAlignment(); > assert(!cast(Use)->isVolatile() && "AST broken"); > - } else > - return; // Not a load or store. > > - // If the alignment of this instruction allows us to specify a more > - // restrictive (and performant) alignment and if we are sure this > - // instruction will be executed, update the alignment. > - // Larger is better, with the exception of 0 being the best alignment. > - if ((InstAlignment > Alignment || InstAlignment == 0) > - && (Alignment != 0)) > - if (isSafeToExecuteUnconditionally(*Use)) { > - GuaranteedToExecute = true; > - Alignment = InstAlignment; > - } > + // Note that we only check GuaranteedToExecute inside the store case > + // so that we do not introduce stores where they did not exist before > + // (which would break the LLVM concurrency model). > + > + // If the alignment of this instruction allows us to specify a more > + // restrictive (and performant) alignment and if we are sure this > + // instruction will be executed, update the alignment. > + // Larger is better, with the exception of 0 being the best alignment. > + if ((InstAlignment > Alignment || InstAlignment == 0) > + && (Alignment != 0)) > + if (isGuaranteedToExecute(*Use)) { > + GuaranteedToExecute = true; > + Alignment = InstAlignment; > + } > + > + if (!GuaranteedToExecute) > + GuaranteedToExecute = isGuaranteedToExecute(*Use); > > - if (!GuaranteedToExecute) > - GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use); > + } else > + return; // Not a load or store. > > LoopUses.push_back(Use); > } > > Added: llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll?rev=135625&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll (added) > +++ llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll Wed Jul 20 16:37:47 2011 > @@ -0,0 +1,37 @@ > +; RUN: opt < %s -basicaa -licm -S | FileCheck %s > + > +; Make sure we don't hoist a conditionally-executed store out of the loop; > +; it would violate the concurrency memory model > + > + at g = common global i32 0, align 4 > + > +define void @bar(i32 %n, i32 %b) nounwind uwtable ssp { > +entry: > + br label %for.cond > + > +for.cond: ; preds = %for.inc, %entry > + %i.0 = phi i32 [ 0, %entry ], [ %inc5, %for.inc ] > + %cmp = icmp slt i32 %i.0, %n > + br i1 %cmp, label %for.body, label %for.end > + > +for.body: ; preds = %for.cond > + %tobool = icmp eq i32 %b, 0 > + br i1 %tobool, label %for.inc, label %if.then > + > +if.then: ; preds = %for.body > + %tmp3 = load i32* @g, align 4 > + %inc = add nsw i32 %tmp3, 1 > + store i32 %inc, i32* @g, align 4 > + br label %for.inc > + > +; CHECK: load i32* > +; CHECK-NEXT: add > +; CHECK-NEXT: store i32 > + > +for.inc: ; preds = %for.body, %if.then > + %inc5 = add nsw i32 %i.0, 1 > + br label %for.cond > + > +for.end: ; preds = %for.cond > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From greened at obbligato.org Wed Jul 20 17:44:32 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 20 Jul 2011 17:44:32 -0500 Subject: [llvm-commits] [PATCH 12/20] [AVX] Make ListInits Unique In-Reply-To: (David A. Greene's message of "Wed, 20 Jul 2011 13:51:46 -0500") References: <8D136665-E330-48F9-B7DA-D7A92E8A07ED@2pi.dk> Message-ID: dag at cray.com (David A. Greene) writes: > Jakob Stoklund Olesen writes: > >> Now that you have a FoldingSet per Init subclass, you can just provide >> a Profile method instead. That reduces the overhead to just a pointer. > > Ok. Done! -Dave From geek4civic at gmail.com Wed Jul 20 17:58:28 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 20 Jul 2011 22:58:28 -0000 Subject: [llvm-commits] [llvm] r135632 - /llvm/trunk/docs/GettingStarted.html Message-ID: <20110720225828.5317D2A6C12D@llvm.org> Author: chapuni Date: Wed Jul 20 17:58:28 2011 New Revision: 135632 URL: http://llvm.org/viewvc/llvm-project?rev=135632&view=rev Log: docs/GettingStarted.html: Fix a typo and tweak a command line. Modified: llvm/trunk/docs/GettingStarted.html Modified: llvm/trunk/docs/GettingStarted.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=135632&r1=135631&r2=135632&view=diff ============================================================================== --- llvm/trunk/docs/GettingStarted.html (original) +++ llvm/trunk/docs/GettingStarted.html Wed Jul 20 17:58:28 2011 @@ -818,7 +818,7 @@ git-svn, run:

    -git clone http://llvm.org/git/llvm
+git clone http://llvm.org/git/llvm.git
 cd llvm
 git svn init https://llvm.org/svn/llvm-project/llvm/trunk --username=<username>
 git config svn-remote.svn.fetch :refs/remotes/origin/master
@@ -826,7 +826,7 @@
 
 # If you have clang too:
 cd tools
-git clone http://llvm.org/git/clang.git clang
+git clone http://llvm.org/git/clang.git
 cd clang
 git svn init https://llvm.org/svn/llvm-project/cfe/trunk --username=<username>
 git config svn-remote.svn.fetch :refs/remotes/origin/master



From dpatel at apple.com  Wed Jul 20 18:00:28 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 20 Jul 2011 23:00:28 -0000
Subject: [llvm-commits] [llvm] r135633 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110720230028.296842A6C12D@llvm.org>

Author: dpatel
Date: Wed Jul 20 18:00:27 2011
New Revision: 135633

URL: http://llvm.org/viewvc/llvm-project?rev=135633&view=rev
Log:
Refactor.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=135633&r1=135632&r2=135633&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jul 20 18:00:27 2011
@@ -1573,44 +1573,54 @@
   I->second = PrevLabel;
 }
 
+/// getOrCreateRegularScope - Create regular DbgScope.
+DbgScope *DwarfDebug::getOrCreateRegularScope(MDNode *Scope) {
+  DbgScope *WScope = DbgScopeMap.lookup(Scope);
+  if (WScope)
+    return WScope;
+  WScope = new DbgScope(NULL, DIDescriptor(Scope), NULL);
+  DbgScopeMap.insert(std::make_pair(Scope, WScope));
+  if (DIDescriptor(Scope).isLexicalBlock()) {
+    DbgScope *Parent =
+      getOrCreateDbgScope(DebugLoc::getFromDILexicalBlock(Scope));
+    WScope->setParent(Parent);
+    Parent->addScope(WScope);
+  } else if (DIDescriptor(Scope).isSubprogram()
+             && DISubprogram(Scope).describes(Asm->MF->getFunction()))
+    CurrentFnDbgScope = WScope;
+  
+  return WScope;
+}
+
+/// getOrCreateInlinedScope - Create inlined scope. 
+DbgScope *DwarfDebug::getOrCreateInlinedScope(MDNode *Scope, MDNode *InlinedAt){
+  DbgScope *InlinedScope = DbgScopeMap.lookup(InlinedAt);
+  if (InlinedScope)
+    return InlinedScope;
+
+  InlinedScope = new DbgScope(NULL, DIDescriptor(Scope), InlinedAt);
+  DebugLoc InlinedLoc = DebugLoc::getFromDILocation(InlinedAt);
+  InlinedDbgScopeMap[InlinedLoc] = InlinedScope;
+  DbgScopeMap[InlinedAt] = InlinedScope;
+  DbgScope *Parent = getOrCreateDbgScope(InlinedLoc);
+  InlinedScope->setParent(Parent);
+  Parent->addScope(InlinedScope);
+  return InlinedScope;
+}
+
 /// getOrCreateDbgScope - Create DbgScope for the scope.
 DbgScope *DwarfDebug::getOrCreateDbgScope(DebugLoc DL) {
   LLVMContext &Ctx = Asm->MF->getFunction()->getContext();
   MDNode *Scope = NULL;
   MDNode *InlinedAt = NULL;
   DL.getScopeAndInlinedAt(Scope, InlinedAt, Ctx);
+  if (!InlinedAt) 
+    return getOrCreateRegularScope(Scope);
 
-  if (!InlinedAt) {
-    DbgScope *WScope = DbgScopeMap.lookup(Scope);
-    if (WScope)
-      return WScope;
-    WScope = new DbgScope(NULL, DIDescriptor(Scope), NULL);
-    DbgScopeMap.insert(std::make_pair(Scope, WScope));
-    if (DIDescriptor(Scope).isLexicalBlock()) {
-      DbgScope *Parent =
-        getOrCreateDbgScope(DebugLoc::getFromDILexicalBlock(Scope));
-      WScope->setParent(Parent);
-      Parent->addScope(WScope);
-    } else if (DIDescriptor(Scope).isSubprogram()
-               && DISubprogram(Scope).describes(Asm->MF->getFunction()))
-      CurrentFnDbgScope = WScope;
-
-    return WScope;
-  }
-
+  // Create an abstract scope for inlined function.
   getOrCreateAbstractScope(Scope);
-  DbgScope *WScope = DbgScopeMap.lookup(InlinedAt);
-  if (WScope)
-    return WScope;
-
-  WScope = new DbgScope(NULL, DIDescriptor(Scope), InlinedAt);
-  DbgScopeMap.insert(std::make_pair(InlinedAt, WScope));
-  InlinedDbgScopeMap[DebugLoc::getFromDILocation(InlinedAt)] = WScope;
-  DbgScope *Parent =
-    getOrCreateDbgScope(DebugLoc::getFromDILocation(InlinedAt));
-  WScope->setParent(Parent);
-  Parent->addScope(WScope);
-  return WScope;
+  // Create an inlined scope for inlined function.
+  return getOrCreateInlinedScope(Scope, InlinedAt);
 }
 
 /// calculateDominanceGraph - Calculate dominance graph for DbgScope

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=135633&r1=135632&r2=135633&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Wed Jul 20 18:00:27 2011
@@ -318,7 +318,8 @@
 
   /// getOrCreateDbgScope - Create DbgScope for the scope.
   DbgScope *getOrCreateDbgScope(DebugLoc DL);
-
+  DbgScope *getOrCreateRegularScope(MDNode *Scope);
+  DbgScope *getOrCreateInlinedScope(MDNode *Scope, MDNode *InlinedAt);
   DbgScope *getOrCreateAbstractScope(const MDNode *N);
 
   /// findAbstractVariable - Find abstract variable associated with Var.



From isanbard at gmail.com  Wed Jul 20 18:04:10 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 20 Jul 2011 23:04:10 -0000
Subject: [llvm-commits] [llvm] r135634 - in /llvm/trunk:
 include/llvm/Target/TargetFrameLowering.h
 lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h
Message-ID: <20110720230410.23B8A2A6C12D@llvm.org>

Author: void
Date: Wed Jul 20 18:04:09 2011
New Revision: 135634

URL: http://llvm.org/viewvc/llvm-project?rev=135634&view=rev
Log:
Remove the now defunct getCompactUnwindEncoding method from the frame lowering code.

Modified:
    llvm/trunk/include/llvm/Target/TargetFrameLowering.h
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
    llvm/trunk/lib/Target/X86/X86FrameLowering.h

Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameLowering.h?rev=135634&r1=135633&r2=135634&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetFrameLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Wed Jul 20 18:04:09 2011
@@ -186,14 +186,6 @@
   ///
   virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
   }
-
-  /// getCompactUnwindEncoding - Get the compact unwind encoding for the
-  /// function. Return 0 if the compact unwind isn't available.
-  virtual uint32_t getCompactUnwindEncoding(ArrayRef Instrs,
-                                            int DataAlignmentFactor,
-                                            bool IsEH) const {
-    return 0;
-  }
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135634&r1=135633&r2=135634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Jul 20 18:04:09 2011
@@ -1076,118 +1076,3 @@
 
   return permutationEncoding;
 }
-
-uint32_t X86FrameLowering::
-getCompactUnwindEncoding(ArrayRef Instrs,
-                         int DataAlignmentFactor, bool IsEH) const {
-  uint32_t Encoding = 0;
-  int CFAOffset = 0;
-  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
-  unsigned SavedRegs[6] = { 0, 0, 0, 0, 0, 0 };
-  unsigned SavedRegIdx = 0;
-  int FramePointerReg = -1;
-
-  for (ArrayRef::const_iterator
-         I = Instrs.begin(), E = Instrs.end(); I != E; ++I) {
-    const MCCFIInstruction &Inst = *I;
-    MCSymbol *Label = Inst.getLabel();
-
-    // Ignore invalid labels.
-    if (Label && !Label->isDefined()) continue;
-
-    unsigned Operation = Inst.getOperation();
-    if (Operation != MCCFIInstruction::Move &&
-        Operation != MCCFIInstruction::RelMove)
-      // FIXME: We can't handle this frame just yet.
-      return 0;
-
-    const MachineLocation &Dst = Inst.getDestination();
-    const MachineLocation &Src = Inst.getSource();
-    const bool IsRelative = (Operation == MCCFIInstruction::RelMove);
-
-    if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
-      if (Src.getReg() != MachineLocation::VirtualFP) {
-        // DW_CFA_def_cfa
-        assert(FramePointerReg == -1 &&"Defining more than one frame pointer?");
-        if (TRI->getLLVMRegNum(Src.getReg(), IsEH) != X86::EBP &&
-            TRI->getLLVMRegNum(Src.getReg(), IsEH) != X86::RBP)
-          // The frame pointer isn't EBP/RBP. Cannot make unwind information
-          // compact.
-          return 0;
-        FramePointerReg = TRI->getCompactUnwindRegNum(Src.getReg(), IsEH);
-      } // else DW_CFA_def_cfa_offset
-
-      if (IsRelative)
-        CFAOffset += Src.getOffset();
-      else
-        CFAOffset -= Src.getOffset();
-
-      continue;
-    }
-
-    if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
-      // DW_CFA_def_cfa_register
-      assert(FramePointerReg == -1 && "Defining more than one frame pointer?");
-
-      if (TRI->getLLVMRegNum(Dst.getReg(), IsEH) != X86::EBP &&
-          TRI->getLLVMRegNum(Dst.getReg(), IsEH) != X86::RBP)
-        // The frame pointer isn't EBP/RBP. Cannot make unwind information
-        // compact.
-        return 0;
-
-      FramePointerReg = TRI->getCompactUnwindRegNum(Dst.getReg(), IsEH);
-      if (SavedRegIdx != 1 || SavedRegs[0] != unsigned(FramePointerReg))
-        return 0;
-
-      SavedRegs[0] = 0;
-      SavedRegIdx = 0;
-      continue;
-    }
-
-    unsigned Reg = Src.getReg();
-    int Offset = Dst.getOffset();
-    if (IsRelative)
-      Offset -= CFAOffset;
-    Offset /= DataAlignmentFactor;
-
-    if (Offset < 0) {
-      // FIXME: Handle?
-      // DW_CFA_offset_extended_sf
-      return 0;
-    } else if (Reg < 64) {
-      // DW_CFA_offset + Reg
-      if (SavedRegIdx >= 6) return 0;
-      int CURegNum = TRI->getCompactUnwindRegNum(Reg, IsEH);
-      if (CURegNum == -1) return 0;
-      SavedRegs[SavedRegIdx++] = CURegNum;
-    } else {
-      // FIXME: Handle?
-      // DW_CFA_offset_extended
-      return 0;
-    }
-  }
-
-  // Bail if there are too many registers to encode.
-  if (SavedRegIdx > 6) return 0;
-
-  // Check if the offset is too big.
-  CFAOffset /= 4;
-  if ((CFAOffset & 0xFF) != CFAOffset)
-    return 0;
-  Encoding |= (CFAOffset & 0xFF) << 16; // Size encoding.
-
-  if (FramePointerReg != -1) {
-    Encoding |= 0x01000000;     // EBP/RBP Unwind Frame
-    for (unsigned I = 0; I != SavedRegIdx; ++I) {
-      unsigned Reg = SavedRegs[I];
-      if (Reg == unsigned(FramePointerReg)) continue;
-      Encoding |= (Reg & 0x7) << (I * 3); // Register encoding
-    }
-  } else {
-    Encoding |= 0x02000000;     // Frameless unwind with small stack
-    Encoding |= (SavedRegIdx & 0x7) << 10;
-    Encoding |= permuteEncode(SavedRegIdx, SavedRegs);
-  }
-
-  return Encoding;
-}

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=135634&r1=135633&r2=135634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Wed Jul 20 18:04:09 2011
@@ -58,9 +58,6 @@
   bool hasReservedCallFrame(const MachineFunction &MF) const;
 
   int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
-
-  uint32_t getCompactUnwindEncoding(ArrayRef Instrs,
-                                    int DataAlignmentFactor, bool IsEH) const;
 };
 
 } // End llvm namespace



From isanbard at gmail.com  Wed Jul 20 18:07:42 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 20 Jul 2011 23:07:42 -0000
Subject: [llvm-commits] [llvm] r135635 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
Message-ID: <20110720230742.7808B2A6C12D@llvm.org>

Author: void
Date: Wed Jul 20 18:07:42 2011
New Revision: 135635

URL: http://llvm.org/viewvc/llvm-project?rev=135635&view=rev
Log:
Remove unused function.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135635&r1=135634&r2=135635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Jul 20 18:07:42 2011
@@ -370,7 +370,6 @@
   unsigned SlotSize = RegInfo->getSlotSize();
   unsigned FramePtr = RegInfo->getFrameRegister(MF);
   unsigned StackPtr = RegInfo->getStackRegister();
-
   DebugLoc DL;
 
   // If we're forcing a stack realignment we can't rely on just the frame
@@ -1013,66 +1012,3 @@
     FrameIdx = 0;
   }
 }
-
-/// permuteEncode - Create the permutation encoding used with frameless
-/// stacks. It is passed the number of registers to be saved and an array of the
-/// registers saved.
-static uint32_t permuteEncode(unsigned SavedCount, unsigned Registers[6]) {
-  // The saved registers are numbered from 1 to 6. In order to encode the order
-  // in which they were saved, we re-number them according to their place in the
-  // register order. The re-numbering is relative to the last re-numbered
-  // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
-  //
-  //    Orig  Re-Num
-  //    ----  ------
-  //     6       6
-  //     2       2
-  //     4       3
-  //     5       3
-  //
-  bool Used[7] = { false, false, false, false, false, false, false };
-  uint32_t RenumRegs[6];
-  for (unsigned I = 0; I < SavedCount; ++I) {
-    uint32_t Renum = 0;
-    for (unsigned U = 1; U < 7; ++U) {
-      if (U == Registers[I])
-        break;
-      if (!Used[U])
-        ++Renum;
-    }
-
-    Used[Registers[I]] = true;
-    RenumRegs[I] = Renum;
-  }
-
-  // Take the renumbered values and encode them into a 10-bit number.
-  uint32_t permutationEncoding = 0;
-  switch (SavedCount) {
-  case 6:
-    permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
-                           + 6 * RenumRegs[2] +  2 * RenumRegs[3]
-                           +     RenumRegs[4];
-    break;
-  case 5:
-    permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
-                           + 6 * RenumRegs[2] +  2 * RenumRegs[3]
-                           +     RenumRegs[4];
-    break;
-  case 4:
-    permutationEncoding |= 60 * RenumRegs[0] + 12 * RenumRegs[1]
-                          + 3 * RenumRegs[2] +      RenumRegs[3];
-    break;
-  case 3:
-    permutationEncoding |= 20 * RenumRegs[0] + 4 * RenumRegs[1]
-                              + RenumRegs[2];
-    break;
-  case 2:
-    permutationEncoding |=  5 * RenumRegs[0] +     RenumRegs[1];
-    break;
-  case 1:
-    permutationEncoding |=      RenumRegs[0];
-    break;
-  }
-
-  return permutationEncoding;
-}



From geek4civic at gmail.com  Wed Jul 20 18:15:08 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 21 Jul 2011 08:15:08 +0900
Subject: [llvm-commits] [llvm] r135569 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/
 lib/Target/ lib/Target/ARM/MCTargetDesc/ lib/Target/C
Message-ID: 

Evan,

2011/7/20 Evan Cheng :
> Author: evancheng
> Date: Wed Jul 20 00:58:47 2011
> New Revision: 135569
>
> URL: http://llvm.org/viewvc/llvm-project?rev=135569&view=rev
> Log:
> Add MCObjectFileInfo and sink the MCSections initialization code from
> TargetLoweringObjectFileImpl down to MCObjectFileInfo.
>
> TargetAsmInfo is done to one last method. It's *almost* gone!

A bad news. some of llvm/test/CodeGen/X86 have been failing since
r135569 on msvc10 and mingw.
Benjamin's r135594 did not help them. Investigating.

See also my buildbots; http://bb.pgr.jp/tgrid?length=50
(excuse me, they are still wip and it might be harder to read logs)

...Takumi

From evan.cheng at apple.com  Wed Jul 20 18:28:24 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 20 Jul 2011 16:28:24 -0700
Subject: [llvm-commits] [llvm] r135569 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/
 lib/Target/ lib/Target/ARM/MCTargetDesc/ lib/Target/C
In-Reply-To: 
References: 
Message-ID: <93997016-5CFB-4343-A45F-8924F27BFF9D@apple.com>

Sorry, I can't really read the logs. How are they failing?

Evan

On Jul 20, 2011, at 4:15 PM, NAKAMURA Takumi wrote:

> Evan,
> 
> 2011/7/20 Evan Cheng :
>> Author: evancheng
>> Date: Wed Jul 20 00:58:47 2011
>> New Revision: 135569
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=135569&view=rev
>> Log:
>> Add MCObjectFileInfo and sink the MCSections initialization code from
>> TargetLoweringObjectFileImpl down to MCObjectFileInfo.
>> 
>> TargetAsmInfo is done to one last method. It's *almost* gone!
> 
> A bad news. some of llvm/test/CodeGen/X86 have been failing since
> r135569 on msvc10 and mingw.
> Benjamin's r135594 did not help them. Investigating.
> 
> See also my buildbots; http://bb.pgr.jp/tgrid?length=50
> (excuse me, they are still wip and it might be harder to read logs)
> 
> ...Takumi


From evan.cheng at apple.com  Wed Jul 20 18:34:39 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 20 Jul 2011 23:34:39 -0000
Subject: [llvm-commits] [llvm] r135636 - in /llvm/trunk/lib/Target/ARM: ./
 AsmParser/ Disassembler/ InstPrinter/ MCTargetDesc/
Message-ID: <20110720233439.D7D202A6C12D@llvm.org>

Author: evancheng
Date: Wed Jul 20 18:34:39 2011
New Revision: 135636

URL: http://llvm.org/viewvc/llvm-project?rev=135636&view=rev
Log:
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

Added:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
      - copied, changed from r135597, llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
      - copied unchanged from r135597, llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
      - copied unchanged from r135597, llvm/trunk/lib/Target/ARM/ARMMCExpr.h
Removed:
    llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
    llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp
    llvm/trunk/lib/Target/ARM/ARMMCExpr.h
Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
    llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/CMakeLists.txt
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Removed: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=135635&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (removed)
@@ -1,595 +0,0 @@
-//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the ARM addressing mode implementation stuff.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
-#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
-
-#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/Support/MathExtras.h"
-#include 
-
-namespace llvm {
-
-/// ARM_AM - ARM Addressing Mode Stuff
-namespace ARM_AM {
-  enum ShiftOpc {
-    no_shift = 0,
-    asr,
-    lsl,
-    lsr,
-    ror,
-    rrx
-  };
-
-  enum AddrOpc {
-    add = '+', sub = '-'
-  };
-
-  static inline const char *getAddrOpcStr(AddrOpc Op) {
-    return Op == sub ? "-" : "";
-  }
-
-  static inline const char *getShiftOpcStr(ShiftOpc Op) {
-    switch (Op) {
-    default: assert(0 && "Unknown shift opc!");
-    case ARM_AM::asr: return "asr";
-    case ARM_AM::lsl: return "lsl";
-    case ARM_AM::lsr: return "lsr";
-    case ARM_AM::ror: return "ror";
-    case ARM_AM::rrx: return "rrx";
-    }
-  }
-
-  static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
-    switch (Op) {
-    default: assert(0 && "Unknown shift opc!");
-    case ARM_AM::asr: return 2;
-    case ARM_AM::lsl: return 0;
-    case ARM_AM::lsr: return 1;
-    case ARM_AM::ror: return 3;
-    }
-  }
-
-  static inline ShiftOpc getShiftOpcForNode(SDValue N) {
-    switch (N.getOpcode()) {
-    default:          return ARM_AM::no_shift;
-    case ISD::SHL:    return ARM_AM::lsl;
-    case ISD::SRL:    return ARM_AM::lsr;
-    case ISD::SRA:    return ARM_AM::asr;
-    case ISD::ROTR:   return ARM_AM::ror;
-    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
-    // Can't handle RRX here, because it would require folding a flag into
-    // the addressing mode.  :(  This causes us to miss certain things.
-    //case ARMISD::RRX: return ARM_AM::rrx;
-    }
-  }
-
-  enum AMSubMode {
-    bad_am_submode = 0,
-    ia,
-    ib,
-    da,
-    db
-  };
-
-  static inline const char *getAMSubModeStr(AMSubMode Mode) {
-    switch (Mode) {
-    default: assert(0 && "Unknown addressing sub-mode!");
-    case ARM_AM::ia: return "ia";
-    case ARM_AM::ib: return "ib";
-    case ARM_AM::da: return "da";
-    case ARM_AM::db: return "db";
-    }
-  }
-
-  /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
-  ///
-  static inline unsigned rotr32(unsigned Val, unsigned Amt) {
-    assert(Amt < 32 && "Invalid rotate amount");
-    return (Val >> Amt) | (Val << ((32-Amt)&31));
-  }
-
-  /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
-  ///
-  static inline unsigned rotl32(unsigned Val, unsigned Amt) {
-    assert(Amt < 32 && "Invalid rotate amount");
-    return (Val << Amt) | (Val >> ((32-Amt)&31));
-  }
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #1: shift_operand with registers
-  //===--------------------------------------------------------------------===//
-  //
-  // This 'addressing mode' is used for arithmetic instructions.  It can
-  // represent things like:
-  //   reg
-  //   reg [asr|lsl|lsr|ror|rrx] reg
-  //   reg [asr|lsl|lsr|ror|rrx] imm
-  //
-  // This is stored three operands [rega, regb, opc].  The first is the base
-  // reg, the second is the shift amount (or reg0 if not present or imm).  The
-  // third operand encodes the shift opcode and the imm if a reg isn't present.
-  //
-  static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
-    return ShOp | (Imm << 3);
-  }
-  static inline unsigned getSORegOffset(unsigned Op) {
-    return Op >> 3;
-  }
-  static inline ShiftOpc getSORegShOp(unsigned Op) {
-    return (ShiftOpc)(Op & 7);
-  }
-
-  /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
-  /// the 8-bit imm value.
-  static inline unsigned getSOImmValImm(unsigned Imm) {
-    return Imm & 0xFF;
-  }
-  /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
-  /// the rotate amount.
-  static inline unsigned getSOImmValRot(unsigned Imm) {
-    return (Imm >> 8) * 2;
-  }
-
-  /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
-  /// computing the rotate amount to use.  If this immediate value cannot be
-  /// handled with a single shifter-op, determine a good rotate amount that will
-  /// take a maximal chunk of bits out of the immediate.
-  static inline unsigned getSOImmValRotate(unsigned Imm) {
-    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
-    // of zero.
-    if ((Imm & ~255U) == 0) return 0;
-
-    // Use CTZ to compute the rotate amount.
-    unsigned TZ = CountTrailingZeros_32(Imm);
-
-    // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
-    // not 9.
-    unsigned RotAmt = TZ & ~1;
-
-    // If we can handle this spread, return it.
-    if ((rotr32(Imm, RotAmt) & ~255U) == 0)
-      return (32-RotAmt)&31;  // HW rotates right, not left.
-
-    // For values like 0xF000000F, we should ignore the low 6 bits, then
-    // retry the hunt.
-    if (Imm & 63U) {
-      unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
-      unsigned RotAmt2 = TZ2 & ~1;
-      if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
-        return (32-RotAmt2)&31;  // HW rotates right, not left.
-    }
-
-    // Otherwise, we have no way to cover this span of bits with a single
-    // shifter_op immediate.  Return a chunk of bits that will be useful to
-    // handle.
-    return (32-RotAmt)&31;  // HW rotates right, not left.
-  }
-
-  /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
-  /// into an shifter_operand immediate operand, return the 12-bit encoding for
-  /// it.  If not, return -1.
-  static inline int getSOImmVal(unsigned Arg) {
-    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
-    // of zero.
-    if ((Arg & ~255U) == 0) return Arg;
-
-    unsigned RotAmt = getSOImmValRotate(Arg);
-
-    // If this cannot be handled with a single shifter_op, bail out.
-    if (rotr32(~255U, RotAmt) & Arg)
-      return -1;
-
-    // Encode this correctly.
-    return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
-  }
-
-  /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
-  /// or'ing together two SOImmVal's.
-  static inline bool isSOImmTwoPartVal(unsigned V) {
-    // If this can be handled with a single shifter_op, bail out.
-    V = rotr32(~255U, getSOImmValRotate(V)) & V;
-    if (V == 0)
-      return false;
-
-    // If this can be handled with two shifter_op's, accept.
-    V = rotr32(~255U, getSOImmValRotate(V)) & V;
-    return V == 0;
-  }
-
-  /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
-  /// return the first chunk of it.
-  static inline unsigned getSOImmTwoPartFirst(unsigned V) {
-    return rotr32(255U, getSOImmValRotate(V)) & V;
-  }
-
-  /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
-  /// return the second chunk of it.
-  static inline unsigned getSOImmTwoPartSecond(unsigned V) {
-    // Mask out the first hunk.
-    V = rotr32(~255U, getSOImmValRotate(V)) & V;
-
-    // Take what's left.
-    assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
-    return V;
-  }
-
-  /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
-  /// by a left shift. Returns the shift amount to use.
-  static inline unsigned getThumbImmValShift(unsigned Imm) {
-    // 8-bit (or less) immediates are trivially immediate operand with a shift
-    // of zero.
-    if ((Imm & ~255U) == 0) return 0;
-
-    // Use CTZ to compute the shift amount.
-    return CountTrailingZeros_32(Imm);
-  }
-
-  /// isThumbImmShiftedVal - Return true if the specified value can be obtained
-  /// by left shifting a 8-bit immediate.
-  static inline bool isThumbImmShiftedVal(unsigned V) {
-    // If this can be handled with
-    V = (~255U << getThumbImmValShift(V)) & V;
-    return V == 0;
-  }
-
-  /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
-  /// by a left shift. Returns the shift amount to use.
-  static inline unsigned getThumbImm16ValShift(unsigned Imm) {
-    // 16-bit (or less) immediates are trivially immediate operand with a shift
-    // of zero.
-    if ((Imm & ~65535U) == 0) return 0;
-
-    // Use CTZ to compute the shift amount.
-    return CountTrailingZeros_32(Imm);
-  }
-
-  /// isThumbImm16ShiftedVal - Return true if the specified value can be
-  /// obtained by left shifting a 16-bit immediate.
-  static inline bool isThumbImm16ShiftedVal(unsigned V) {
-    // If this can be handled with
-    V = (~65535U << getThumbImm16ValShift(V)) & V;
-    return V == 0;
-  }
-
-  /// getThumbImmNonShiftedVal - If V is a value that satisfies
-  /// isThumbImmShiftedVal, return the non-shiftd value.
-  static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
-    return V >> getThumbImmValShift(V);
-  }
-
-
-  /// getT2SOImmValSplat - Return the 12-bit encoded representation
-  /// if the specified value can be obtained by splatting the low 8 bits
-  /// into every other byte or every byte of a 32-bit value. i.e.,
-  ///     00000000 00000000 00000000 abcdefgh    control = 0
-  ///     00000000 abcdefgh 00000000 abcdefgh    control = 1
-  ///     abcdefgh 00000000 abcdefgh 00000000    control = 2
-  ///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
-  /// Return -1 if none of the above apply.
-  /// See ARM Reference Manual A6.3.2.
-  static inline int getT2SOImmValSplatVal(unsigned V) {
-    unsigned u, Vs, Imm;
-    // control = 0
-    if ((V & 0xffffff00) == 0)
-      return V;
-
-    // If the value is zeroes in the first byte, just shift those off
-    Vs = ((V & 0xff) == 0) ? V >> 8 : V;
-    // Any passing value only has 8 bits of payload, splatted across the word
-    Imm = Vs & 0xff;
-    // Likewise, any passing values have the payload splatted into the 3rd byte
-    u = Imm | (Imm << 16);
-
-    // control = 1 or 2
-    if (Vs == u)
-      return (((Vs == V) ? 1 : 2) << 8) | Imm;
-
-    // control = 3
-    if (Vs == (u | (u << 8)))
-      return (3 << 8) | Imm;
-
-    return -1;
-  }
-
-  /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
-  /// specified value is a rotated 8-bit value. Return -1 if no rotation
-  /// encoding is possible.
-  /// See ARM Reference Manual A6.3.2.
-  static inline int getT2SOImmValRotateVal(unsigned V) {
-    unsigned RotAmt = CountLeadingZeros_32(V);
-    if (RotAmt >= 24)
-      return -1;
-
-    // If 'Arg' can be handled with a single shifter_op return the value.
-    if ((rotr32(0xff000000U, RotAmt) & V) == V)
-      return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
-
-    return -1;
-  }
-
-  /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
-  /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
-  /// encoding for it.  If not, return -1.
-  /// See ARM Reference Manual A6.3.2.
-  static inline int getT2SOImmVal(unsigned Arg) {
-    // If 'Arg' is an 8-bit splat, then get the encoded value.
-    int Splat = getT2SOImmValSplatVal(Arg);
-    if (Splat != -1)
-      return Splat;
-
-    // If 'Arg' can be handled with a single shifter_op return the value.
-    int Rot = getT2SOImmValRotateVal(Arg);
-    if (Rot != -1)
-      return Rot;
-
-    return -1;
-  }
-
-  static inline unsigned getT2SOImmValRotate(unsigned V) {
-    if ((V & ~255U) == 0) return 0;
-    // Use CTZ to compute the rotate amount.
-    unsigned RotAmt = CountTrailingZeros_32(V);
-    return (32 - RotAmt) & 31;
-  }
-
-  static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
-    unsigned V = Imm;
-    // Passing values can be any combination of splat values and shifter
-    // values. If this can be handled with a single shifter or splat, bail
-    // out. Those should be handled directly, not with a two-part val.
-    if (getT2SOImmValSplatVal(V) != -1)
-      return false;
-    V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
-    if (V == 0)
-      return false;
-
-    // If this can be handled as an immediate, accept.
-    if (getT2SOImmVal(V) != -1) return true;
-
-    // Likewise, try masking out a splat value first.
-    V = Imm;
-    if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
-      V &= ~0xff00ff00U;
-    else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
-      V &= ~0x00ff00ffU;
-    // If what's left can be handled as an immediate, accept.
-    if (getT2SOImmVal(V) != -1) return true;
-
-    // Otherwise, do not accept.
-    return false;
-  }
-
-  static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
-    assert (isT2SOImmTwoPartVal(Imm) &&
-            "Immedate cannot be encoded as two part immediate!");
-    // Try a shifter operand as one part
-    unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
-    // If the rest is encodable as an immediate, then return it.
-    if (getT2SOImmVal(V) != -1) return V;
-
-    // Try masking out a splat value first.
-    if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
-      return Imm & 0xff00ff00U;
-
-    // The other splat is all that's left as an option.
-    assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
-    return Imm & 0x00ff00ffU;
-  }
-
-  static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
-    // Mask out the first hunk
-    Imm ^= getT2SOImmTwoPartFirst(Imm);
-    // Return what's left
-    assert (getT2SOImmVal(Imm) != -1 &&
-            "Unable to encode second part of T2 two part SO immediate");
-    return Imm;
-  }
-
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #2
-  //===--------------------------------------------------------------------===//
-  //
-  // This is used for most simple load/store instructions.
-  //
-  // addrmode2 := reg +/- reg shop imm
-  // addrmode2 := reg +/- imm12
-  //
-  // The first operand is always a Reg.  The second operand is a reg if in
-  // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
-  // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
-  // fourth operand 16-17 encodes the index mode.
-  //
-  // If this addressing mode is a frame index (before prolog/epilog insertion
-  // and code rewriting), this operand will have the form:  FI#, reg0, 
-  // with no shift amount for the frame offset.
-  //
-  static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
-                                   unsigned IdxMode = 0) {
-    assert(Imm12 < (1 << 12) && "Imm too large!");
-    bool isSub = Opc == sub;
-    return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
-  }
-  static inline unsigned getAM2Offset(unsigned AM2Opc) {
-    return AM2Opc & ((1 << 12)-1);
-  }
-  static inline AddrOpc getAM2Op(unsigned AM2Opc) {
-    return ((AM2Opc >> 12) & 1) ? sub : add;
-  }
-  static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
-    return (ShiftOpc)((AM2Opc >> 13) & 7);
-  }
-  static inline unsigned getAM2IdxMode(unsigned AM2Opc) {
-    return (AM2Opc >> 16);
-  }
-
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #3
-  //===--------------------------------------------------------------------===//
-  //
-  // This is used for sign-extending loads, and load/store-pair instructions.
-  //
-  // addrmode3 := reg +/- reg
-  // addrmode3 := reg +/- imm8
-  //
-  // The first operand is always a Reg.  The second operand is a reg if in
-  // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
-  // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
-  // index mode.
-
-  /// getAM3Opc - This function encodes the addrmode3 opc field.
-  static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
-                                   unsigned IdxMode = 0) {
-    bool isSub = Opc == sub;
-    return ((int)isSub << 8) | Offset | (IdxMode << 9);
-  }
-  static inline unsigned char getAM3Offset(unsigned AM3Opc) {
-    return AM3Opc & 0xFF;
-  }
-  static inline AddrOpc getAM3Op(unsigned AM3Opc) {
-    return ((AM3Opc >> 8) & 1) ? sub : add;
-  }
-  static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
-    return (AM3Opc >> 9);
-  }
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #4
-  //===--------------------------------------------------------------------===//
-  //
-  // This is used for load / store multiple instructions.
-  //
-  // addrmode4 := reg, 
-  //
-  // The four modes are:
-  //    IA - Increment after
-  //    IB - Increment before
-  //    DA - Decrement after
-  //    DB - Decrement before
-  // For VFP instructions, only the IA and DB modes are valid.
-
-  static inline AMSubMode getAM4SubMode(unsigned Mode) {
-    return (AMSubMode)(Mode & 0x7);
-  }
-
-  static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
-    return (int)SubMode;
-  }
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #5
-  //===--------------------------------------------------------------------===//
-  //
-  // This is used for coprocessor instructions, such as FP load/stores.
-  //
-  // addrmode5 := reg +/- imm8*4
-  //
-  // The first operand is always a Reg.  The second operand encodes the
-  // operation in bit 8 and the immediate in bits 0-7.
-
-  /// getAM5Opc - This function encodes the addrmode5 opc field.
-  static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
-    bool isSub = Opc == sub;
-    return ((int)isSub << 8) | Offset;
-  }
-  static inline unsigned char getAM5Offset(unsigned AM5Opc) {
-    return AM5Opc & 0xFF;
-  }
-  static inline AddrOpc getAM5Op(unsigned AM5Opc) {
-    return ((AM5Opc >> 8) & 1) ? sub : add;
-  }
-
-  //===--------------------------------------------------------------------===//
-  // Addressing Mode #6
-  //===--------------------------------------------------------------------===//
-  //
-  // This is used for NEON load / store instructions.
-  //
-  // addrmode6 := reg with optional alignment
-  //
-  // This is stored in two operands [regaddr, align].  The first is the
-  // address register.  The second operand is the value of the alignment
-  // specifier in bytes or zero if no explicit alignment.
-  // Valid alignments depend on the specific instruction.
-
-  //===--------------------------------------------------------------------===//
-  // NEON Modified Immediates
-  //===--------------------------------------------------------------------===//
-  //
-  // Several NEON instructions (e.g., VMOV) take a "modified immediate"
-  // vector operand, where a small immediate encoded in the instruction
-  // specifies a full NEON vector value.  These modified immediates are
-  // represented here as encoded integers.  The low 8 bits hold the immediate
-  // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
-  // the "Cmode" field of the instruction.  The interfaces below treat the
-  // Op and Cmode values as a single 5-bit value.
-
-  static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
-    return (OpCmode << 8) | Val;
-  }
-  static inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
-    return (ModImm >> 8) & 0x1f;
-  }
-  static inline unsigned getNEONModImmVal(unsigned ModImm) {
-    return ModImm & 0xff;
-  }
-
-  /// decodeNEONModImm - Decode a NEON modified immediate value into the
-  /// element value and the element size in bits.  (If the element size is
-  /// smaller than the vector, it is splatted into all the elements.)
-  static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
-    unsigned OpCmode = getNEONModImmOpCmode(ModImm);
-    unsigned Imm8 = getNEONModImmVal(ModImm);
-    uint64_t Val = 0;
-
-    if (OpCmode == 0xe) {
-      // 8-bit vector elements
-      Val = Imm8;
-      EltBits = 8;
-    } else if ((OpCmode & 0xc) == 0x8) {
-      // 16-bit vector elements
-      unsigned ByteNum = (OpCmode & 0x6) >> 1;
-      Val = Imm8 << (8 * ByteNum);
-      EltBits = 16;
-    } else if ((OpCmode & 0x8) == 0) {
-      // 32-bit vector elements, zero with one byte set
-      unsigned ByteNum = (OpCmode & 0x6) >> 1;
-      Val = Imm8 << (8 * ByteNum);
-      EltBits = 32;
-    } else if ((OpCmode & 0xe) == 0xc) {
-      // 32-bit vector elements, one byte with low bits set
-      unsigned ByteNum = 1 + (OpCmode & 0x1);
-      Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
-      EltBits = 32;
-    } else if (OpCmode == 0x1e) {
-      // 64-bit vector elements
-      for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
-        if ((ModImm >> ByteNum) & 1)
-          Val |= (uint64_t)0xff << (8 * ByteNum);
-      }
-      EltBits = 64;
-    } else {
-      assert(false && "Unsupported NEON immediate");
-    }
-    return Val;
-  }
-
-  AMSubMode getLoadStoreMultipleSubMode(int Opcode);
-
-} // end namespace ARM_AM
-} // end namespace llvm
-
-#endif
-

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Jul 20 18:34:39 2011
@@ -8,8 +8,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMFixupKinds.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCDirectives.h"

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jul 20 18:34:39 2011
@@ -15,15 +15,15 @@
 #define DEBUG_TYPE "asm-printer"
 #include "ARM.h"
 #include "ARMAsmPrinter.h"
-#include "ARMAddressingModes.h"
 #include "ARMBuildAttrs.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMMachineFunctionInfo.h"
-#include "ARMMCExpr.h"
 #include "ARMTargetMachine.h"
 #include "ARMTargetObjectFile.h"
 #include "InstPrinter/ARMInstPrinter.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/Analysis/DebugInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Module.h"

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Jul 20 18:34:39 2011
@@ -191,6 +191,9 @@
   }
 }
 
+/// ARMII - This namespace holds all of the target specific flags that
+/// instruction info tracks.
+///
 namespace ARMII {
 
   /// ARM Index Modes
@@ -287,6 +290,142 @@
     /// call operand.
     MO_PLT
   };
+
+  enum {
+    //===------------------------------------------------------------------===//
+    // Instruction Flags.
+
+    //===------------------------------------------------------------------===//
+    // This four-bit field describes the addressing mode used.
+    AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+
+    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
+    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
+    // The index mode enums are declared in ARMBaseInfo.h
+    IndexModeShift = 5,
+    IndexModeMask  = 3 << IndexModeShift,
+
+    //===------------------------------------------------------------------===//
+    // Instruction encoding formats.
+    //
+    FormShift     = 7,
+    FormMask      = 0x3f << FormShift,
+
+    // Pseudo instructions
+    Pseudo        = 0  << FormShift,
+
+    // Multiply instructions
+    MulFrm        = 1  << FormShift,
+
+    // Branch instructions
+    BrFrm         = 2  << FormShift,
+    BrMiscFrm     = 3  << FormShift,
+
+    // Data Processing instructions
+    DPFrm         = 4  << FormShift,
+    DPSoRegFrm    = 5  << FormShift,
+
+    // Load and Store
+    LdFrm         = 6  << FormShift,
+    StFrm         = 7  << FormShift,
+    LdMiscFrm     = 8  << FormShift,
+    StMiscFrm     = 9  << FormShift,
+    LdStMulFrm    = 10 << FormShift,
+
+    LdStExFrm     = 11 << FormShift,
+
+    // Miscellaneous arithmetic instructions
+    ArithMiscFrm  = 12 << FormShift,
+    SatFrm        = 13 << FormShift,
+
+    // Extend instructions
+    ExtFrm        = 14 << FormShift,
+
+    // VFP formats
+    VFPUnaryFrm   = 15 << FormShift,
+    VFPBinaryFrm  = 16 << FormShift,
+    VFPConv1Frm   = 17 << FormShift,
+    VFPConv2Frm   = 18 << FormShift,
+    VFPConv3Frm   = 19 << FormShift,
+    VFPConv4Frm   = 20 << FormShift,
+    VFPConv5Frm   = 21 << FormShift,
+    VFPLdStFrm    = 22 << FormShift,
+    VFPLdStMulFrm = 23 << FormShift,
+    VFPMiscFrm    = 24 << FormShift,
+
+    // Thumb format
+    ThumbFrm      = 25 << FormShift,
+
+    // Miscelleaneous format
+    MiscFrm       = 26 << FormShift,
+
+    // NEON formats
+    NGetLnFrm     = 27 << FormShift,
+    NSetLnFrm     = 28 << FormShift,
+    NDupFrm       = 29 << FormShift,
+    NLdStFrm      = 30 << FormShift,
+    N1RegModImmFrm= 31 << FormShift,
+    N2RegFrm      = 32 << FormShift,
+    NVCVTFrm      = 33 << FormShift,
+    NVDupLnFrm    = 34 << FormShift,
+    N2RegVShLFrm  = 35 << FormShift,
+    N2RegVShRFrm  = 36 << FormShift,
+    N3RegFrm      = 37 << FormShift,
+    N3RegVShFrm   = 38 << FormShift,
+    NVExtFrm      = 39 << FormShift,
+    NVMulSLFrm    = 40 << FormShift,
+    NVTBLFrm      = 41 << FormShift,
+
+    //===------------------------------------------------------------------===//
+    // Misc flags.
+
+    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
+    // it doesn't have a Rn operand.
+    UnaryDP       = 1 << 13,
+
+    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
+    // a 16-bit Thumb instruction if certain conditions are met.
+    Xform16Bit    = 1 << 14,
+
+    //===------------------------------------------------------------------===//
+    // Code domain.
+    DomainShift   = 15,
+    DomainMask    = 7 << DomainShift,
+    DomainGeneral = 0 << DomainShift,
+    DomainVFP     = 1 << DomainShift,
+    DomainNEON    = 2 << DomainShift,
+    DomainNEONA8  = 4 << DomainShift,
+
+    //===------------------------------------------------------------------===//
+    // Field shifts - such shifts are used to set field while generating
+    // machine instructions.
+    //
+    // FIXME: This list will need adjusting/fixing as the MC code emitter
+    // takes shape and the ARMCodeEmitter.cpp bits go away.
+    ShiftTypeShift = 4,
+
+    M_BitShift     = 5,
+    ShiftImmShift  = 5,
+    ShiftShift     = 7,
+    N_BitShift     = 7,
+    ImmHiShift     = 8,
+    SoRotImmShift  = 8,
+    RegRsShift     = 8,
+    ExtRotImmShift = 10,
+    RegRdLoShift   = 12,
+    RegRdShift     = 12,
+    RegRdHiShift   = 16,
+    RegRnShift     = 16,
+    S_BitShift     = 20,
+    W_BitShift     = 21,
+    AM3_I_BitShift = 22,
+    D_BitShift     = 22,
+    U_BitShift     = 23,
+    P_BitShift     = 24,
+    I_BitShift     = 25,
+    CondShift      = 28
+  };
+
 } // end namespace ARMII
 
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jul 20 18:34:39 2011
@@ -13,11 +13,11 @@
 
 #include "ARMBaseInstrInfo.h"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMHazardRecognizer.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMRegisterInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/GlobalValue.h"
@@ -29,6 +29,7 @@
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/BranchProbability.h"
 #include "llvm/Support/CommandLine.h"

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Wed Jul 20 18:34:39 2011
@@ -27,146 +27,6 @@
   class ARMSubtarget;
   class ARMBaseRegisterInfo;
 
-/// ARMII - This namespace holds all of the target specific flags that
-/// instruction info tracks.
-///
-namespace ARMII {
-  enum {
-    //===------------------------------------------------------------------===//
-    // Instruction Flags.
-
-    //===------------------------------------------------------------------===//
-    // This four-bit field describes the addressing mode used.
-    AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
-
-    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
-    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
-    // The index mode enums are declared in ARMBaseInfo.h
-    IndexModeShift = 5,
-    IndexModeMask  = 3 << IndexModeShift,
-
-    //===------------------------------------------------------------------===//
-    // Instruction encoding formats.
-    //
-    FormShift     = 7,
-    FormMask      = 0x3f << FormShift,
-
-    // Pseudo instructions
-    Pseudo        = 0  << FormShift,
-
-    // Multiply instructions
-    MulFrm        = 1  << FormShift,
-
-    // Branch instructions
-    BrFrm         = 2  << FormShift,
-    BrMiscFrm     = 3  << FormShift,
-
-    // Data Processing instructions
-    DPFrm         = 4  << FormShift,
-    DPSoRegFrm    = 5  << FormShift,
-
-    // Load and Store
-    LdFrm         = 6  << FormShift,
-    StFrm         = 7  << FormShift,
-    LdMiscFrm     = 8  << FormShift,
-    StMiscFrm     = 9  << FormShift,
-    LdStMulFrm    = 10 << FormShift,
-
-    LdStExFrm     = 11 << FormShift,
-
-    // Miscellaneous arithmetic instructions
-    ArithMiscFrm  = 12 << FormShift,
-    SatFrm        = 13 << FormShift,
-
-    // Extend instructions
-    ExtFrm        = 14 << FormShift,
-
-    // VFP formats
-    VFPUnaryFrm   = 15 << FormShift,
-    VFPBinaryFrm  = 16 << FormShift,
-    VFPConv1Frm   = 17 << FormShift,
-    VFPConv2Frm   = 18 << FormShift,
-    VFPConv3Frm   = 19 << FormShift,
-    VFPConv4Frm   = 20 << FormShift,
-    VFPConv5Frm   = 21 << FormShift,
-    VFPLdStFrm    = 22 << FormShift,
-    VFPLdStMulFrm = 23 << FormShift,
-    VFPMiscFrm    = 24 << FormShift,
-
-    // Thumb format
-    ThumbFrm      = 25 << FormShift,
-
-    // Miscelleaneous format
-    MiscFrm       = 26 << FormShift,
-
-    // NEON formats
-    NGetLnFrm     = 27 << FormShift,
-    NSetLnFrm     = 28 << FormShift,
-    NDupFrm       = 29 << FormShift,
-    NLdStFrm      = 30 << FormShift,
-    N1RegModImmFrm= 31 << FormShift,
-    N2RegFrm      = 32 << FormShift,
-    NVCVTFrm      = 33 << FormShift,
-    NVDupLnFrm    = 34 << FormShift,
-    N2RegVShLFrm  = 35 << FormShift,
-    N2RegVShRFrm  = 36 << FormShift,
-    N3RegFrm      = 37 << FormShift,
-    N3RegVShFrm   = 38 << FormShift,
-    NVExtFrm      = 39 << FormShift,
-    NVMulSLFrm    = 40 << FormShift,
-    NVTBLFrm      = 41 << FormShift,
-
-    //===------------------------------------------------------------------===//
-    // Misc flags.
-
-    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
-    // it doesn't have a Rn operand.
-    UnaryDP       = 1 << 13,
-
-    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
-    // a 16-bit Thumb instruction if certain conditions are met.
-    Xform16Bit    = 1 << 14,
-
-    //===------------------------------------------------------------------===//
-    // Code domain.
-    DomainShift   = 15,
-    DomainMask    = 7 << DomainShift,
-    DomainGeneral = 0 << DomainShift,
-    DomainVFP     = 1 << DomainShift,
-    DomainNEON    = 2 << DomainShift,
-    DomainNEONA8  = 4 << DomainShift,
-
-    //===------------------------------------------------------------------===//
-    // Field shifts - such shifts are used to set field while generating
-    // machine instructions.
-    //
-    // FIXME: This list will need adjusting/fixing as the MC code emitter
-    // takes shape and the ARMCodeEmitter.cpp bits go away.
-    ShiftTypeShift = 4,
-
-    M_BitShift     = 5,
-    ShiftImmShift  = 5,
-    ShiftShift     = 7,
-    N_BitShift     = 7,
-    ImmHiShift     = 8,
-    SoRotImmShift  = 8,
-    RegRsShift     = 8,
-    ExtRotImmShift = 10,
-    RegRdLoShift   = 12,
-    RegRdShift     = 12,
-    RegRdHiShift   = 16,
-    RegRnShift     = 16,
-    S_BitShift     = 20,
-    W_BitShift     = 21,
-    AM3_I_BitShift = 22,
-    D_BitShift     = 22,
-    U_BitShift     = 23,
-    P_BitShift     = 24,
-    I_BitShift     = 25,
-    CondShift      = 28
-  };
-}
-
 class ARMBaseInstrInfo : public ARMGenInstrInfo {
   const ARMSubtarget &Subtarget;
 

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jul 20 18:34:39 2011
@@ -12,13 +12,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMFrameLowering.h"
 #include "ARMInstrInfo.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMSubtarget.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Jul 20 18:34:39 2011
@@ -14,12 +14,12 @@
 
 #define DEBUG_TYPE "jit"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMInstrInfo.h"
 #include "ARMRelocations.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Jul 20 18:34:39 2011
@@ -15,10 +15,10 @@
 
 #define DEBUG_TYPE "arm-cp-islands"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMInstrInfo.h"
 #include "Thumb2InstrInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Jul 20 18:34:39 2011
@@ -16,11 +16,11 @@
 
 #define DEBUG_TYPE "arm-pseudo"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMRegisterInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Jul 20 18:34:39 2011
@@ -14,13 +14,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMCallingConv.h"
 #include "ARMRegisterInfo.h"
 #include "ARMTargetMachine.h"
 #include "ARMSubtarget.h"
 #include "ARMConstantPoolValue.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CallingConv.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/GlobalVariable.h"

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed Jul 20 18:34:39 2011
@@ -12,10 +12,10 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMFrameLowering.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMMachineFunctionInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Jul 20 18:34:39 2011
@@ -14,8 +14,8 @@
 #define DEBUG_TYPE "arm-isel"
 #include "ARM.h"
 #include "ARMBaseInstrInfo.h"
-#include "ARMAddressingModes.h"
 #include "ARMTargetMachine.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CallingConv.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
@@ -373,7 +373,7 @@
   if (DisableShifterOp)
     return false;
 
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
 
   // Don't match base register only case. That is matched to a separate
   // lower complexity pattern with explicit register operand.
@@ -489,7 +489,8 @@
 
   // Otherwise this is R +/- [possibly shifted] R.
   ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
+  ARM_AM::ShiftOpc ShOpcVal =
+    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
   unsigned ShAmt = 0;
 
   Base   = N.getOperand(0);
@@ -515,7 +516,7 @@
   // Try matching (R shl C) + (R).
   if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
       !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
-    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
+    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
     if (ShOpcVal != ARM_AM::no_shift) {
       // Check to see if the RHS of the shift is a constant, if not, we can't
       // fold it.
@@ -630,7 +631,8 @@
 
   // Otherwise this is R +/- [possibly shifted] R.
   ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
+  ARM_AM::ShiftOpc ShOpcVal =
+    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
   unsigned ShAmt = 0;
 
   Base   = N.getOperand(0);
@@ -656,7 +658,7 @@
   // Try matching (R shl C) + (R).
   if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
       !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
-    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
+    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
     if (ShOpcVal != ARM_AM::no_shift) {
       // Check to see if the RHS of the shift is a constant, if not, we can't
       // fold it.
@@ -701,7 +703,7 @@
   }
 
   Offset = N;
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
   unsigned ShAmt = 0;
   if (ShOpcVal != ARM_AM::no_shift) {
     // Check to see if the RHS of the shift is a constant, if not, we can't fold
@@ -1079,7 +1081,7 @@
   if (DisableShifterOp)
     return false;
 
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
 
   // Don't match base register only case. That is matched to a separate
   // lower complexity pattern with explicit register operand.
@@ -1220,9 +1222,9 @@
   OffReg = N.getOperand(1);
 
   // Swap if it is ((R << c) + R).
-  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
   if (ShOpcVal != ARM_AM::lsl) {
-    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
+    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
     if (ShOpcVal == ARM_AM::lsl)
       std::swap(Base, OffReg);
   }

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 20 18:34:39 2011
@@ -14,7 +14,6 @@
 
 #define DEBUG_TYPE "arm-isel"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMCallingConv.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMISelLowering.h"
@@ -24,6 +23,7 @@
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "ARMTargetObjectFile.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CallingConv.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
@@ -7351,7 +7351,8 @@
 
     if (Ptr->getOpcode() == ISD::ADD) {
       isInc = true;
-      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
+      ARM_AM::ShiftOpc ShOpcVal=
+        ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
       if (ShOpcVal != ARM_AM::no_shift) {
         Base = Ptr->getOperand(1);
         Offset = Ptr->getOperand(0);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Wed Jul 20 18:34:39 2011
@@ -13,8 +13,8 @@
 
 #include "ARMInstrInfo.h"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMMachineFunctionInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jul 20 18:34:39 2011
@@ -14,10 +14,10 @@
 
 #define DEBUG_TYPE "arm-ldst-opt"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMRegisterInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -26,6 +26,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Jul 20 18:34:39 2011
@@ -13,16 +13,16 @@
 
 #define DEBUG_TYPE "mccodeemitter"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMFixupKinds.h"
 #include "ARMInstrInfo.h"
-#include "ARMMCExpr.h"
-#include "ARMSubtarget.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/raw_ostream.h"
 

Removed: llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp?rev=135635&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp (removed)
@@ -1,73 +0,0 @@
-//===-- ARMMCExpr.cpp - ARM specific MC expression classes ----------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "armmcexpr"
-#include "ARMMCExpr.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCAssembler.h"
-using namespace llvm;
-
-const ARMMCExpr*
-ARMMCExpr::Create(VariantKind Kind, const MCExpr *Expr,
-                       MCContext &Ctx) {
-  return new (Ctx) ARMMCExpr(Kind, Expr);
-}
-
-void ARMMCExpr::PrintImpl(raw_ostream &OS) const {
-  switch (Kind) {
-  default: assert(0 && "Invalid kind!");
-  case VK_ARM_HI16: OS << ":upper16:"; break;
-  case VK_ARM_LO16: OS << ":lower16:"; break;
-  }
-
-  const MCExpr *Expr = getSubExpr();
-  if (Expr->getKind() != MCExpr::SymbolRef)
-    OS << '(';
-  Expr->print(OS);
-  if (Expr->getKind() != MCExpr::SymbolRef)
-    OS << ')';
-}
-
-bool
-ARMMCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
-                                     const MCAsmLayout *Layout) const {
-  return false;
-}
-
-// FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps
-// that method should be made public?
-static void AddValueSymbols_(const MCExpr *Value, MCAssembler *Asm) {
-  switch (Value->getKind()) {
-  case MCExpr::Target:
-    assert(0 && "Can't handle nested target expr!");
-    break;
-
-  case MCExpr::Constant:
-    break;
-
-  case MCExpr::Binary: {
-    const MCBinaryExpr *BE = cast(Value);
-    AddValueSymbols_(BE->getLHS(), Asm);
-    AddValueSymbols_(BE->getRHS(), Asm);
-    break;
-  }
-
-  case MCExpr::SymbolRef:
-    Asm->getOrCreateSymbolData(cast(Value)->getSymbol());
-    break;
-
-  case MCExpr::Unary:
-    AddValueSymbols_(cast(Value)->getSubExpr(), Asm);
-    break;
-  }
-}
-
-void ARMMCExpr::AddValueSymbols(MCAssembler *Asm) const {
-  AddValueSymbols_(getSubExpr(), Asm);
-}

Removed: llvm/trunk/lib/Target/ARM/ARMMCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCExpr.h?rev=135635&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCExpr.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCExpr.h (removed)
@@ -1,76 +0,0 @@
-//===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARMMCEXPR_H
-#define ARMMCEXPR_H
-
-#include "llvm/MC/MCExpr.h"
-
-namespace llvm {
-
-class ARMMCExpr : public MCTargetExpr {
-public:
-  enum VariantKind {
-    VK_ARM_None,
-    VK_ARM_HI16,  // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
-    VK_ARM_LO16   // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
-  };
-
-private:
-  const VariantKind Kind;
-  const MCExpr *Expr;
-
-  explicit ARMMCExpr(VariantKind _Kind, const MCExpr *_Expr)
-    : Kind(_Kind), Expr(_Expr) {}
-  
-public:
-  /// @name Construction
-  /// @{
-
-  static const ARMMCExpr *Create(VariantKind Kind, const MCExpr *Expr,
-                                      MCContext &Ctx);
-
-  static const ARMMCExpr *CreateUpper16(const MCExpr *Expr, MCContext &Ctx) {
-    return Create(VK_ARM_HI16, Expr, Ctx);
-  }
-
-  static const ARMMCExpr *CreateLower16(const MCExpr *Expr, MCContext &Ctx) {
-    return Create(VK_ARM_LO16, Expr, Ctx);
-  }
-
-  /// @}
-  /// @name Accessors
-  /// @{
-
-  /// getOpcode - Get the kind of this expression.
-  VariantKind getKind() const { return Kind; }
-
-  /// getSubExpr - Get the child of this expression.
-  const MCExpr *getSubExpr() const { return Expr; }
-
-  /// @}
-
-  void PrintImpl(raw_ostream &OS) const;
-  bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const {
-    return getSubExpr()->FindAssociatedSection();
-  }
-
-  static bool classof(const MCExpr *E) {
-    return E->getKind() == MCExpr::Target;
-  }
-  
-  static bool classof(const ARMMCExpr *) { return true; }
-
-};
-} // end namespace llvm
-
-#endif

Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Jul 20 18:34:39 2011
@@ -14,7 +14,7 @@
 
 #include "ARM.h"
 #include "ARMAsmPrinter.h"
-#include "ARMMCExpr.h"
+#include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/Constants.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/MC/MCExpr.h"

Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h Wed Jul 20 18:34:39 2011
@@ -14,10 +14,27 @@
 #ifndef ARMSELECTIONDAGINFO_H
 #define ARMSELECTIONDAGINFO_H
 
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/Target/TargetSelectionDAGInfo.h"
 
 namespace llvm {
 
+namespace ARM_AM {
+  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
+    switch (Opcode) {
+    default:          return ARM_AM::no_shift;
+    case ISD::SHL:    return ARM_AM::lsl;
+    case ISD::SRL:    return ARM_AM::lsr;
+    case ISD::SRA:    return ARM_AM::asr;
+    case ISD::ROTR:   return ARM_AM::ror;
+    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
+    // Can't handle RRX here, because it would require folding a flag into
+    // the addressing mode.  :(  This causes us to miss certain things.
+    //case ARMISD::RRX: return ARM_AM::rrx;
+    }
+  }
+}  // end namespace ARM_AM
+
 class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
   /// make the right decision when generating code for different targets.

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 20 18:34:39 2011
@@ -8,10 +8,10 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
-#include "ARMAddressingModes.h"
-#include "ARMMCExpr.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMSubtarget.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"

Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jul 20 18:34:39 2011
@@ -34,7 +34,6 @@
   ARMJITInfo.cpp
   ARMMachObjectWriter.cpp
   ARMMCCodeEmitter.cpp
-  ARMMCExpr.cpp
   ARMLoadStoreOptimizer.cpp
   ARMMCInstLower.cpp
   ARMRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 20 18:34:39 2011
@@ -16,8 +16,10 @@
 #define DEBUG_TYPE "arm-disassembler"
 
 #include "ARMDisassemblerCore.h"
-#include "ARMAddressingModes.h"
-#include "ARMMCExpr.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMMCExpr.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/APFloat.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jul 20 18:34:39 2011
@@ -14,7 +14,7 @@
 #define DEBUG_TYPE "asm-printer"
 #include "ARMBaseInfo.h"
 #include "ARMInstPrinter.h"
-#include "ARMAddressingModes.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"

Copied: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (from r135597, llvm/trunk/lib/Target/ARM/ARMAddressingModes.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?p2=llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h&p1=llvm/trunk/lib/Target/ARM/ARMAddressingModes.h&r1=135597&r2=135636&rev=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h Wed Jul 20 18:34:39 2011
@@ -14,7 +14,6 @@
 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
 
-#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Support/MathExtras.h"
 #include 
 
@@ -60,20 +59,6 @@
     }
   }
 
-  static inline ShiftOpc getShiftOpcForNode(SDValue N) {
-    switch (N.getOpcode()) {
-    default:          return ARM_AM::no_shift;
-    case ISD::SHL:    return ARM_AM::lsl;
-    case ISD::SRL:    return ARM_AM::lsr;
-    case ISD::SRA:    return ARM_AM::asr;
-    case ISD::ROTR:   return ARM_AM::ror;
-    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
-    // Can't handle RRX here, because it would require folding a flag into
-    // the addressing mode.  :(  This causes us to miss certain things.
-    //case ARMISD::RRX: return ARM_AM::rrx;
-    }
-  }
-
   enum AMSubMode {
     bad_am_submode = 0,
     ia,

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Wed Jul 20 18:34:39 2011
@@ -1,6 +1,7 @@
 add_llvm_library(LLVMARMDesc
   ARMMCTargetDesc.cpp
   ARMMCAsmInfo.cpp
+  ARMMCExpr.cpp
   )
 
 # Hack: we need to include 'main' target directory to grab private headers

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Jul 20 18:34:39 2011
@@ -13,12 +13,12 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMSubtarget.h"
 #include "Thumb1InstrInfo.h"
 #include "Thumb1RegisterInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Jul 20 18:34:39 2011
@@ -14,9 +14,9 @@
 #include "Thumb2InstrInfo.h"
 #include "ARM.h"
 #include "ARMConstantPoolValue.h"
-#include "ARMAddressingModes.h"
 #include "ARMMachineFunctionInfo.h"
 #include "Thumb2InstrInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=135636&r1=135635&r2=135636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jul 20 18:34:39 2011
@@ -9,11 +9,11 @@
 
 #define DEBUG_TYPE "t2-reduce-size"
 #include "ARM.h"
-#include "ARMAddressingModes.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "Thumb2InstrInfo.h"
+#include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"



From geek4civic at gmail.com  Wed Jul 20 18:37:51 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 20 Jul 2011 23:37:51 -0000
Subject: [llvm-commits] [llvm] r135637 - /llvm/trunk/docs/GettingStarted.html
Message-ID: <20110720233751.ABF0F2A6C12D@llvm.org>

Author: chapuni
Date: Wed Jul 20 18:37:51 2011
New Revision: 135637

URL: http://llvm.org/viewvc/llvm-project?rev=135637&view=rev
Log:
docs/GettingStarted.html: Tweak style.

Modified:
    llvm/trunk/docs/GettingStarted.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=135637&r1=135636&r2=135637&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Wed Jul 20 18:37:51 2011
@@ -802,13 +802,13 @@
   now mirrors reflect only trunk for each project. You can do the
   read-only GIT clone of LLVM via:
    
 
-
    +
     git clone http://llvm.org/git/llvm.git
 
    
 
 
    If you want to check out clang too, run:
    
 
-
    +
     git clone http://llvm.org/git/llvm.git
 cd llvm/tools
 git clone http://llvm.org/git/clang.git
@@ -817,7 +817,7 @@
 
    To set up clone from which you can submit code using
    git-svn, run:
    
 
-
    +
     git clone http://llvm.org/git/llvm.git
 cd llvm
 git svn init https://llvm.org/svn/llvm-project/llvm/trunk --username=<username>
@@ -836,7 +836,7 @@
 
    To update this clone without generating git-svn tags that conflict
 with the upstream git repo, run:
    
 
-
    +
     git fetch && (cd tools/clang && git fetch)  # Get matching revisions of both trees.
 git checkout master
 git svn rebase -l
@@ -856,7 +856,7 @@
 dcommit stops working, complaining about files with uncommitted
 changes. The fix is to rebuild the metadata:
    
 
-
    +
     rm -rf .git/svn
 git svn rebase -l
 
    



From eli.friedman at gmail.com  Wed Jul 20 18:42:26 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 20 Jul 2011 16:42:26 -0700
Subject: [llvm-commits] [llvm] r135625 - in /llvm/trunk:
 lib/Transforms/Scalar/LICM.cpp
 test/Transforms/LICM/scalar-promote-memmodel.ll
In-Reply-To: <0B0781B7-6663-4BCA-8B72-A7E0D497F796@apple.com>
References: <20110720213748.0D9962A6C12D@llvm.org>
	<0B0781B7-6663-4BCA-8B72-A7E0D497F796@apple.com>
Message-ID: 

On Wed, Jul 20, 2011 at 3:20 PM, Cameron Zwarich  wrote:
> Did you do any performance testing for this change?

I don't have full performance results, but I took a brief look, and
this transformation triggers pretty rarely.

-Eli

> Cameron
>
> On Jul 20, 2011, at 2:37 PM, Eli Friedman wrote:
>
>> Author: efriedma
>> Date: Wed Jul 20 16:37:47 2011
>> New Revision: 135625
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=135625&view=rev
>> Log:
>> Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
>>
>>
>> Added:
>> ? ?llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll
>> Modified:
>> ? ?llvm/trunk/lib/Transforms/Scalar/LICM.cpp
>>
>> Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=135625&r1=135624&r2=135625&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Jul 20 16:37:47 2011
>> @@ -151,6 +151,11 @@
>> ? ? ///
>> ? ? bool isSafeToExecuteUnconditionally(Instruction &I);
>>
>> + ? ?/// isGuaranteedToExecute - Check that the instruction is guaranteed to
>> + ? ?/// execute.
>> + ? ?///
>> + ? ?bool isGuaranteedToExecute(Instruction &I);
>> +
>> ? ? /// pointerInvalidatedByLoop - Return true if the body of this loop may
>> ? ? /// store into the memory location pointed to by V.
>> ? ? ///
>> @@ -577,6 +582,10 @@
>> ? if (Inst.isSafeToSpeculativelyExecute())
>> ? ? return true;
>>
>> + ?return isGuaranteedToExecute(Inst);
>> +}
>> +
>> +bool LICM::isGuaranteedToExecute(Instruction &Inst) {
>> ? // Otherwise we have to check to make sure that the instruction dominates all
>> ? // of the exit blocks. ?If it doesn't, then there is a path out of the loop
>> ? // which does not execute this instruction, so we can't hoist it.
>> @@ -713,33 +722,36 @@
>>
>> ? ? ? // If there is an non-load/store instruction in the loop, we can't promote
>> ? ? ? // it.
>> - ? ? ?unsigned InstAlignment;
>> - ? ? ?if (LoadInst *load = dyn_cast(Use)) {
>> + ? ? ?if (isa(Use)) {
>> ? ? ? ? assert(!cast(Use)->isVolatile() && "AST broken");
>> - ? ? ? ?InstAlignment = load->getAlignment();
>> ? ? ? } else if (StoreInst *store = dyn_cast(Use)) {
>> ? ? ? ? // Stores *of* the pointer are not interesting, only stores *to* the
>> ? ? ? ? // pointer.
>> ? ? ? ? if (Use->getOperand(1) != ASIV)
>> ? ? ? ? ? continue;
>> - ? ? ? ?InstAlignment = store->getAlignment();
>> + ? ? ? ?unsigned InstAlignment = store->getAlignment();
>> ? ? ? ? assert(!cast(Use)->isVolatile() && "AST broken");
>> - ? ? ?} else
>> - ? ? ? ?return; // Not a load or store.
>>
>> - ? ? ?// If the alignment of this instruction allows us to specify a more
>> - ? ? ?// restrictive (and performant) alignment and if we are sure this
>> - ? ? ?// instruction will be executed, update the alignment.
>> - ? ? ?// Larger is better, with the exception of 0 being the best alignment.
>> - ? ? ?if ((InstAlignment > Alignment || InstAlignment == 0)
>> - ? ? ? ? ?&& (Alignment != 0))
>> - ? ? ? ?if (isSafeToExecuteUnconditionally(*Use)) {
>> - ? ? ? ? ?GuaranteedToExecute = true;
>> - ? ? ? ? ?Alignment = InstAlignment;
>> - ? ? ? ?}
>> + ? ? ? ?// Note that we only check GuaranteedToExecute inside the store case
>> + ? ? ? ?// so that we do not introduce stores where they did not exist before
>> + ? ? ? ?// (which would break the LLVM concurrency model).
>> +
>> + ? ? ? ?// If the alignment of this instruction allows us to specify a more
>> + ? ? ? ?// restrictive (and performant) alignment and if we are sure this
>> + ? ? ? ?// instruction will be executed, update the alignment.
>> + ? ? ? ?// Larger is better, with the exception of 0 being the best alignment.
>> + ? ? ? ?if ((InstAlignment > Alignment || InstAlignment == 0)
>> + ? ? ? ? ? ?&& (Alignment != 0))
>> + ? ? ? ? ?if (isGuaranteedToExecute(*Use)) {
>> + ? ? ? ? ? ?GuaranteedToExecute = true;
>> + ? ? ? ? ? ?Alignment = InstAlignment;
>> + ? ? ? ? ?}
>> +
>> + ? ? ? ?if (!GuaranteedToExecute)
>> + ? ? ? ? ?GuaranteedToExecute = isGuaranteedToExecute(*Use);
>>
>> - ? ? ?if (!GuaranteedToExecute)
>> - ? ? ? ?GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use);
>> + ? ? ?} else
>> + ? ? ? ?return; // Not a load or store.
>>
>> ? ? ? LoopUses.push_back(Use);
>> ? ? }
>>
>> Added: llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll?rev=135625&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll (added)
>> +++ llvm/trunk/test/Transforms/LICM/scalar-promote-memmodel.ll Wed Jul 20 16:37:47 2011
>> @@ -0,0 +1,37 @@
>> +; RUN: opt < %s -basicaa -licm -S | FileCheck %s
>> +
>> +; Make sure we don't hoist a conditionally-executed store out of the loop;
>> +; it would violate the concurrency memory model
>> +
>> + at g = common global i32 0, align 4
>> +
>> +define void @bar(i32 %n, i32 %b) nounwind uwtable ssp {
>> +entry:
>> + ?br label %for.cond
>> +
>> +for.cond: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.inc, %entry
>> + ?%i.0 = phi i32 [ 0, %entry ], [ %inc5, %for.inc ]
>> + ?%cmp = icmp slt i32 %i.0, %n
>> + ?br i1 %cmp, label %for.body, label %for.end
>> +
>> +for.body: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %for.cond
>> + ?%tobool = icmp eq i32 %b, 0
>> + ?br i1 %tobool, label %for.inc, label %if.then
>> +
>> +if.then: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.body
>> + ?%tmp3 = load i32* @g, align 4
>> + ?%inc = add nsw i32 %tmp3, 1
>> + ?store i32 %inc, i32* @g, align 4
>> + ?br label %for.inc
>> +
>> +; CHECK: load i32*
>> +; CHECK-NEXT: add
>> +; CHECK-NEXT: store i32
>> +
>> +for.inc: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.body, %if.then
>> + ?%inc5 = add nsw i32 %i.0, 1
>> + ?br label %for.cond
>> +
>> +for.end: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.cond
>> + ?ret void
>> +}
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From gohman at apple.com  Wed Jul 20 18:44:34 2011
From: gohman at apple.com (Dan Gohman)
Date: Wed, 20 Jul 2011 16:44:34 -0700
Subject: [llvm-commits] [llvm] r135624 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <20110720213553.CC6D92A6C12D@llvm.org>
References: <20110720213553.CC6D92A6C12D@llvm.org>
Message-ID: 

On Jul 20, 2011, at 2:35 PM, Eli Friedman wrote:
>  For each byte, R reads the
> +value written by some write that it may see, given any relevant
> +happens-before constraints.

This sentence seems confusing.

It mentions "relevant happens-before constraints", however it's not clear what
those are until the following sentance. And, it seems to suggest that R always
reads the value of a write, which isn't always true.

Actually, it seems you could just delete this sentance without loosing
anything essential.

>  Rbyte may
> +see any write to the same byte, except:
    

The implicit transition from talking about R to talking about R_{byte} here is
mildly mysterious.

> +
> +
      
> +  
    • If write1 happens before
> +      write2, and write2 happens
> +      before Rbyte, then Rbyte
> +      must not see write1.
> +  
    • If Rbyte happens before write3,
> +      then Rbyte must not see
> +      write3.

The use of the word "must" here is inconsistent with the rest of LangRef,
where it is used to constrain the IR producer, rather than the implementation.
Would "does" would convey the intended meaning better?

> +
    
> +
> +
    Given that definition, Rbyte is defined as follows:
> +
      
> +  
    • If there is no write to the same byte that happens before
> +    Rbyte, Rbyte returns 
> +    undef for that byte.

How do static initializers fit into this?

> +  
    • If Rbyte may see exactly one write,
> +      Rbyte returns the value written by that
> +      write.
      • 

What if there's exactly one write, but the read also may-see the memory
before any writes happen?

> +  
    • If Rbyte and all the writes it may see are
> +      atomic, it chooses one of those writes and returns it value.
> +      Given any two bytes in a given read R, if the set of
> +      writes Rbyte may see is the same as the set
> +      of writes another byte may see, they will both choose the same write.

What if there are two multi-byte reads, and both their may-see sets contain
only atomic writes, but the sets are different? Can bytes from atomic
multi-byte writes be interleaved in this case?

Also, does this rule apply even when R is non-atomic? Is it intended to
require that all multi-byte reads must read all of their bytes simultaneously?

> +  
    • Otherwise Rbyte returns undef.
      • 
> +
    
> +
> +
    R returns the value composed of the series of bytes it read.
> +This implies that some bytes within the value may be undef
> +without the entire value being undef. Note that this only
> +defines the semantics of the operation; it doesn't mean that targets will
> +emit more than one instruction to read the series of bytes.
    
> +
> +
    Note that in cases where none of the atomic intrinsics are used, this model
> +places only one restriction on IR transformations on top of what is required
> +for single-threaded execution: introducing a store to a byte which might not
> +otherwise be stored to can introduce undefined behavior.
    

Is it worth mentioning that this doesn't apply to pointers that
don't escape to other threads?

Dan


From evan.cheng at apple.com  Wed Jul 20 18:53:54 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 20 Jul 2011 23:53:54 -0000
Subject: [llvm-commits] [llvm] r135639 -
	/llvm/trunk/lib/MC/MCObjectFileInfo.cpp
Message-ID: <20110720235354.9E1C12A6C12D@llvm.org>

Author: evancheng
Date: Wed Jul 20 18:53:54 2011
New Revision: 135639

URL: http://llvm.org/viewvc/llvm-project?rev=135639&view=rev
Log:
X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts.

Modified:
    llvm/trunk/lib/MC/MCObjectFileInfo.cpp

Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=135639&r1=135638&r2=135639&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Jul 20 18:53:54 2011
@@ -518,8 +518,9 @@
       (T.isOSDarwin() || T.getEnvironment() == Triple::MachO)) {
     Env = IsMachO;
     InitMachOMCObjectFileInfo(T);
-  } else if (T.getOS() == Triple::MinGW32 || T.getOS() == Triple::Cygwin ||
-             T.getOS() == Triple::Win32) {
+  } else if ((Arch == Triple::x86 || Arch == Triple::x86_64) &&
+             (T.getOS() == Triple::MinGW32 || T.getOS() == Triple::Cygwin ||
+              T.getOS() == Triple::Win32)) {
     Env = IsCOFF;
     InitCOFFMCObjectFileInfo(T);
   } else {



From evan.cheng at apple.com  Wed Jul 20 18:54:39 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 20 Jul 2011 16:54:39 -0700
Subject: [llvm-commits] [llvm] r135569 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/
 lib/Target/ lib/Target/ARM/MCTargetDesc/ lib/Target/C
In-Reply-To: <93997016-5CFB-4343-A45F-8924F27BFF9D@apple.com>
References: 
	<93997016-5CFB-4343-A45F-8924F27BFF9D@apple.com>
Message-ID: <07340853-D521-4BD4-8ED9-DAC168EA0EFF@apple.com>

Try r135639.

Evan

On Jul 20, 2011, at 4:28 PM, Evan Cheng wrote:

> Sorry, I can't really read the logs. How are they failing?
> 
> Evan
> 
> On Jul 20, 2011, at 4:15 PM, NAKAMURA Takumi wrote:
> 
>> Evan,
>> 
>> 2011/7/20 Evan Cheng :
>>> Author: evancheng
>>> Date: Wed Jul 20 00:58:47 2011
>>> New Revision: 135569
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=135569&view=rev
>>> Log:
>>> Add MCObjectFileInfo and sink the MCSections initialization code from
>>> TargetLoweringObjectFileImpl down to MCObjectFileInfo.
>>> 
>>> TargetAsmInfo is done to one last method. It's *almost* gone!
>> 
>> A bad news. some of llvm/test/CodeGen/X86 have been failing since
>> r135569 on msvc10 and mingw.
>> Benjamin's r135594 did not help them. Investigating.
>> 
>> See also my buildbots; http://bb.pgr.jp/tgrid?length=50
>> (excuse me, they are still wip and it might be harder to read logs)
>> 
>> ...Takumi
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From eli.friedman at gmail.com  Wed Jul 20 19:17:31 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 20 Jul 2011 17:17:31 -0700
Subject: [llvm-commits] [llvm] r135624 - /llvm/trunk/docs/LangRef.html
In-Reply-To: 
References: <20110720213553.CC6D92A6C12D@llvm.org>
	
Message-ID: 

On Wed, Jul 20, 2011 at 4:44 PM, Dan Gohman  wrote:
>> +
>> +
>> +
    Given that definition, Rbyte is defined as follows:
>> +
      
>> + ?
    • If there is no write to the same byte that happens before
>> + ? ?Rbyte, Rbyte returns
>> + ? ?undef for that byte.
>
> How do static initializers fit into this?

An initializer acts like a write that happens before any read; I'll
add something explicit.

>> + ?
    • If Rbyte may see exactly one write,
>> + ? ? ?Rbyte returns the value written by that
>> + ? ? ?write.
      • 
>
> What if there's exactly one write, but the read also may-see the memory
> before any writes happen?

That's supposed to be covered by "If there is no write to the same
byte that happens before..."

>> + ?
    • If Rbyte and all the writes it may see are
>> + ? ? ?atomic, it chooses one of those writes and returns it value.
>> + ? ? ?Given any two bytes in a given read R, if the set of
>> + ? ? ?writes Rbyte may see is the same as the set
>> + ? ? ?of writes another byte may see, they will both choose the same write.
>
> What if there are two multi-byte reads, and both their may-see sets contain
> only atomic writes, but the sets are different? Can bytes from atomic
> multi-byte writes be interleaved in this case?

I'll try to make this clearer.  The intent is the obvious semantics
for multiple unordered atomic writes followed by an atomic read, but
it gets a little complicated because you can mix atomic writes of
differing sizes.

> Also, does this rule apply even when R is non-atomic? Is it intended to
> require that all multi-byte reads must read all of their bytes simultaneously?

No, it doesn't apply when R is not atomic ("if Rbyte and... are
atomic"); I suppose that could be made clearer.

>> + ?
    • Otherwise Rbyte returns undef.
      • 
>> +
    
>> +
>> +
    R returns the value composed of the series of bytes it read.
>> +This implies that some bytes within the value may be undef
>> +without the entire value being undef. Note that this only
>> +defines the semantics of the operation; it doesn't mean that targets will
>> +emit more than one instruction to read the series of bytes.
    
>> +
>> +
    Note that in cases where none of the atomic intrinsics are used, this model
>> +places only one restriction on IR transformations on top of what is required
>> +for single-threaded execution: introducing a store to a byte which might not
>> +otherwise be stored to can introduce undefined behavior.
    
>
> Is it worth mentioning that this doesn't apply to pointers that
> don't escape to other threads?

Possibly; I started out trying to write a sentence like that, but it
wasn't clear. I'll think about it a bit more.

I'll try to address the other issues you mentioned as well.

-Eli


From atrick at apple.com  Wed Jul 20 19:40:04 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 21 Jul 2011 00:40:04 -0000
Subject: [llvm-commits] [llvm] r135644 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
Message-ID: <20110721004004.C99682A6C12D@llvm.org>

Author: atrick
Date: Wed Jul 20 19:40:04 2011
New Revision: 135644

URL: http://llvm.org/viewvc/llvm-project?rev=135644&view=rev
Log:
LSR crashes on an empty IVUsers list.

rdar://9786536

Added:
    llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=135644&r1=135643&r2=135644&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Jul 20 19:40:04 2011
@@ -3740,6 +3740,9 @@
   OptimizeShadowIV();
   OptimizeLoopTermCond();
 
+  // If loop preparation eliminates all interesting IV users, bail.
+  if (IU.empty()) return;
+
   // Start collecting data and preparing for the solver.
   CollectInterestingTypesAndFactors();
   CollectFixupsAndInitialFormulae();

Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll?rev=135644&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll Wed Jul 20 19:40:04 2011
@@ -0,0 +1,24 @@
+; RUN: opt < %s -loop-reduce -S | FileCheck %s
+;
+; Test LSR's OptimizeShadowIV. Handle a floating-point IV with a
+; nonzero initial value.
+; rdar://9786536
+
+; First, make sure LSR doesn't crash on an empty IVUsers list.
+; CHECK: @dummyIV
+; CHECK-NOT: phi
+; CHECK-NOT: sitofp
+; CHECK: br
+define void @dummyIV() nounwind {
+entry:
+  br label %loop
+
+loop:
+  %i.01 = phi i32 [ -39, %entry ], [ %inc, %loop ]
+  %conv7 = sitofp i32 %i.01 to double
+  %inc = add nsw i32 %i.01, 1
+  br i1 undef, label %loop, label %for.end
+
+for.end:
+  unreachable
+}



From isanbard at gmail.com  Wed Jul 20 19:44:56 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 21 Jul 2011 00:44:56 -0000
Subject: [llvm-commits] [llvm] r135645 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
Message-ID: <20110721004456.EE90A2A6C12D@llvm.org>

Author: void
Date: Wed Jul 20 19:44:56 2011
New Revision: 135645

URL: http://llvm.org/viewvc/llvm-project?rev=135645&view=rev
Log:
Mark instructions which are part of the frame setup with the MachineInstr::FrameSetup flag.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135645&r1=135644&r2=135645&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Jul 20 19:44:56 2011
@@ -458,7 +458,8 @@
     if (needsFrameMoves) {
       // Mark the place where EBP/RBP was saved.
       MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
-      BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
+      BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
+        .addSym(FrameLabel);
 
       // Define the current CFA rule to use the provided offset.
       if (StackSize) {
@@ -486,7 +487,8 @@
     if (needsFrameMoves) {
       // Mark effective beginning of when frame pointer becomes valid.
       MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
-      BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
+      BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
+        .addSym(FrameLabel);
 
       // Define the current CFA to use the EBP/RBP register.
       MachineLocation FPDst(FramePtr);
@@ -503,8 +505,10 @@
     if (RegInfo->needsStackRealignment(MF)) {
       MachineInstr *MI =
         BuildMI(MBB, MBBI, DL,
-                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
-                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
+                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
+        .addReg(StackPtr)
+        .addImm(-MaxAlign)
+        .setMIFlag(MachineInstr::FrameSetup);
 
       // The EFLAGS implicit def is dead.
       MI->getOperand(3).setIsDead();
@@ -521,6 +525,7 @@
          (MBBI->getOpcode() == X86::PUSH32r ||
           MBBI->getOpcode() == X86::PUSH64r)) {
     PushedRegs = true;
+    MBBI->setFlag(MachineInstr::FrameSetup);
     ++MBBI;
 
     if (!HasFP && needsFrameMoves) {
@@ -585,26 +590,30 @@
 
       // Save EAX
       BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
-        .addReg(X86::EAX, RegState::Kill);
+        .addReg(X86::EAX, RegState::Kill)
+        .setMIFlag(MachineInstr::FrameSetup);
     }
 
     if (Is64Bit) {
       // Handle the 64-bit Windows ABI case where we need to call __chkstk.
       // Function prologue is responsible for adjusting the stack pointer.
       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
-        .addImm(NumBytes);
+        .addImm(NumBytes)
+        .setMIFlag(MachineInstr::FrameSetup);
     } else {
       // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
       // We'll also use 4 already allocated bytes for EAX.
       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
-        .addImm(isEAXAlive ? NumBytes - 4 : NumBytes);
+        .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
+        .setMIFlag(MachineInstr::FrameSetup);
     }
 
     BuildMI(MBB, MBBI, DL,
             TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
       .addExternalSymbol(StackProbeSymbol)
       .addReg(StackPtr,    RegState::Define | RegState::Implicit)
-      .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
+      .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
+      .setMIFlag(MachineInstr::FrameSetup);
 
     // MSVC x64's __chkstk needs to adjust %rsp.
     // FIXME: %rax preserves the offset and should be available.
@@ -617,6 +626,7 @@
         MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
                                                 X86::EAX),
                                         StackPtr, false, NumBytes - 4);
+        MI->setFlag(MachineInstr::FrameSetup);
         MBB.insert(MBBI, MI);
     }
   } else if (NumBytes)
@@ -626,7 +636,8 @@
   if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
     // Mark end of stack pointer adjustment.
     MCSymbol *Label = MMI.getContext().CreateTempSymbol();
-    BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
+    BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
+      .addSym(Label);
 
     if (!HasFP && NumBytes) {
       // Define the current CFA rule to use the provided offset.



From atrick at apple.com  Wed Jul 20 20:05:01 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 21 Jul 2011 01:05:01 -0000
Subject: [llvm-commits] [llvm] r135650 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
Message-ID: <20110721010501.AD7F32A6C12D@llvm.org>

Author: atrick
Date: Wed Jul 20 20:05:01 2011
New Revision: 135650

URL: http://llvm.org/viewvc/llvm-project?rev=135650&view=rev
Log:
LSR must sometimes sign-extend before generating double constants.

rdar://9786536

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=135650&r1=135649&r2=135650&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Jul 20 20:05:01 2011
@@ -1427,6 +1427,7 @@
     ++UI;
     Instruction *ShadowUse = CandidateUI->getUser();
     Type *DestTy = NULL;
+    bool IsSigned = false;
 
     /* If shadow use is a int->float cast then insert a second IV
        to eliminate this cast.
@@ -1440,10 +1441,14 @@
          for (unsigned i = 0; i < n; ++i, ++d)
            foo(d);
     */
-    if (UIToFPInst *UCast = dyn_cast(CandidateUI->getUser()))
+    if (UIToFPInst *UCast = dyn_cast(CandidateUI->getUser())) {
+      IsSigned = false;
       DestTy = UCast->getDestTy();
-    else if (SIToFPInst *SCast = dyn_cast(CandidateUI->getUser()))
+    }
+    else if (SIToFPInst *SCast = dyn_cast(CandidateUI->getUser())) {
+      IsSigned = true;
       DestTy = SCast->getDestTy();
+    }
     if (!DestTy) continue;
 
     if (TLI) {
@@ -1474,7 +1479,9 @@
 
     ConstantInt *Init = dyn_cast(PH->getIncomingValue(Entry));
     if (!Init) continue;
-    Constant *NewInit = ConstantFP::get(DestTy, Init->getZExtValue());
+    Constant *NewInit = ConstantFP::get(DestTy, IsSigned ?
+                                        Init->getSExtValue() :
+                                        Init->getZExtValue());
 
     BinaryOperator *Incr =
       dyn_cast(PH->getIncomingValue(Latch));

Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll?rev=135650&r1=135649&r2=135650&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll Wed Jul 20 20:05:01 2011
@@ -15,7 +15,26 @@
 
 loop:
   %i.01 = phi i32 [ -39, %entry ], [ %inc, %loop ]
-  %conv7 = sitofp i32 %i.01 to double
+  %conv = sitofp i32 %i.01 to double
+  %inc = add nsw i32 %i.01, 1
+  br i1 undef, label %loop, label %for.end
+
+for.end:
+  unreachable
+}
+
+; Now check that the computed double constant is correct.
+; CHECK: @doubleIV
+; CHECK: phi double [ 0x43F0000000000000, %entry ]
+; CHECK: br
+define void @doubleIV() nounwind {
+entry:
+  br label %loop
+
+loop:
+  %i.01 = phi i32 [ -39, %entry ], [ %inc, %loop ]
+  %conv = sitofp i32 %i.01 to double
+  %div = fdiv double %conv, 4.000000e+01
   %inc = add nsw i32 %i.01, 1
   br i1 undef, label %loop, label %for.end
 



From atrick at apple.com  Wed Jul 20 20:45:54 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 21 Jul 2011 01:45:54 -0000
Subject: [llvm-commits] [llvm] r135654 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
Message-ID: <20110721014554.801AE2A6C12D@llvm.org>

Author: atrick
Date: Wed Jul 20 20:45:54 2011
New Revision: 135654

URL: http://llvm.org/viewvc/llvm-project?rev=135654&view=rev
Log:
LSR, correct fix for rdar://9786536. Silly casting bug.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=135654&r1=135653&r2=135654&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Jul 20 20:45:54 2011
@@ -1480,8 +1480,8 @@
     ConstantInt *Init = dyn_cast(PH->getIncomingValue(Entry));
     if (!Init) continue;
     Constant *NewInit = ConstantFP::get(DestTy, IsSigned ?
-                                        Init->getSExtValue() :
-                                        Init->getZExtValue());
+                                        (double)Init->getSExtValue() :
+                                        (double)Init->getZExtValue());
 
     BinaryOperator *Incr =
       dyn_cast(PH->getIncomingValue(Latch));

Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll?rev=135654&r1=135653&r2=135654&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-07-20-DoubleIV.ll Wed Jul 20 20:45:54 2011
@@ -25,7 +25,7 @@
 
 ; Now check that the computed double constant is correct.
 ; CHECK: @doubleIV
-; CHECK: phi double [ 0x43F0000000000000, %entry ]
+; CHECK: phi double [ -3.900000e+01, %entry ]
 ; CHECK: br
 define void @doubleIV() nounwind {
 entry:



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:27 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:27 -0000
Subject: [llvm-commits] [llvm] r135656 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110721015527.CAE542A6C12D@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:27 2011
New Revision: 135656

URL: http://llvm.org/viewvc/llvm-project?rev=135656&view=rev
Log:
Tidy up code

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135656&r1=135655&r2=135656&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 20:55:27 2011
@@ -85,14 +85,10 @@
                                    DebugLoc dl) {
   EVT VT = Vec.getValueType();
   assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
-
   EVT ElVT = VT.getVectorElementType();
-
-  int Factor = VT.getSizeInBits() / 128;
-
-  EVT ResultVT = EVT::getVectorVT(*DAG.getContext(),
-                                  ElVT,
-                                  VT.getVectorNumElements() / Factor);
+  int Factor = VT.getSizeInBits()/128;
+  EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
+                                  VT.getVectorNumElements()/Factor);
 
   // Extract from UNDEF is UNDEF.
   if (Vec.getOpcode() == ISD::UNDEF)
@@ -111,7 +107,6 @@
                                  * ElemsPerChunk);
 
     SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
-
     SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
                                  VecIdx);
 
@@ -136,21 +131,18 @@
     assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
 
     EVT ElVT = VT.getVectorElementType();
-
     unsigned IdxVal = cast(Idx)->getZExtValue();
-
     EVT ResultVT = Result.getValueType();
 
     // Insert the relevant 128 bits.
-    unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
+    unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
 
     // This is the index of the first element of the 128-bit chunk
     // we want.
-    unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
+    unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
                                  * ElemsPerChunk);
 
     SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
-
     Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
                          VecIdx);
     return Result;
@@ -3641,7 +3633,6 @@
   EVT ElVT = VecVT.getVectorElementType();
 
   unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
-
   return Index / NumElemsPerChunk;
 }
 
@@ -3659,7 +3650,6 @@
   EVT ElVT = VecVT.getVectorElementType();
 
   unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
-
   return Index / NumElemsPerChunk;
 }
 



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:30 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:30 -0000
Subject: [llvm-commits] [llvm] r135657 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20110721015530.9CD882A6C12E@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:30 2011
New Revision: 135657

URL: http://llvm.org/viewvc/llvm-project?rev=135657&view=rev
Log:
Move code around. No functionality changes

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135657&r1=135656&r2=135657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 20 20:55:30 2011
@@ -5289,8 +5289,10 @@
 // AVX Instructions
 //===----------------------------------------------------------------------===//
 
-
-// Load from memory and broadcast to all elements of the destination operand
+//===----------------------------------------------------------------------===//
+// VBROADCAST - Load from memory and broadcast to all elements of the
+//              destination operand
+//
 class avx_broadcast opc, string OpcodeStr, RegisterClass RC,
                     X86MemOperand x86memop, Intrinsic Int> :
   AVX8I;
 
-// Insert packed floating-point values
+def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
+          (VBROADCASTF128 addr:$src)>;
+
+//===----------------------------------------------------------------------===//
+// VINSERTF128 - Insert packed floating-point values
+//
 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
           (ins VR256:$src1, VR128:$src2, i8imm:$src3),
           "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
@@ -5316,7 +5323,33 @@
           "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
           []>, VEX_4V;
 
-// Extract packed floating-point values
+def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
+          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
+def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
+          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
+def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
+          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
+
+def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
+def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
+def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
+def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
+
+//===----------------------------------------------------------------------===//
+// VEXTRACTF128 - Extract packed floating-point values
+//
 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
           (ins VR256:$src1, i8imm:$src2),
           "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -5326,7 +5359,33 @@
           "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
           []>, VEX;
 
-// Conditional SIMD Packed Loads and Stores
+def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
+          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
+def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
+          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
+def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
+          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
+
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v4f32 (VEXTRACTF128rr
+                    (v8f32 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v2f64 (VEXTRACTF128rr
+                    (v4f64 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v4i32 (VEXTRACTF128rr
+                    (v8i32 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v2i64 (VEXTRACTF128rr
+                    (v4i64 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+
+//===----------------------------------------------------------------------===//
+// VMASKMOV - Conditional SIMD Packed Loads and Stores
+//
 multiclass avx_movmask_rm opc_rm, bits<8> opc_mr, string OpcodeStr,
                           Intrinsic IntLd, Intrinsic IntLd256,
                           Intrinsic IntSt, Intrinsic IntSt256,
@@ -5364,7 +5423,9 @@
                                  int_x86_avx_maskstore_pd_256,
                                  memopv2f64, memopv4f64>;
 
-// Permute Floating-Point Values
+//===----------------------------------------------------------------------===//
+// VPERM - Permute Floating-Point Values
+//
 multiclass avx_permil opc_rm, bits<8> opc_rmi, string OpcodeStr,
                       RegisterClass RC, X86MemOperand x86memop_f,
                       X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
@@ -5414,65 +5475,6 @@
           "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
           []>, VEX_4V;
 
-// Zero All YMM registers
-def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
-                 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
-
-// Zero Upper bits of YMM registers
-def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
-                   [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
-
-def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
-          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
-def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
-          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
-def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
-          (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
-
-def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
-                                   (i32 imm)),
-          (VINSERTF128rr VR256:$src1, VR128:$src2,
-                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
-def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
-                                   (i32 imm)),
-          (VINSERTF128rr VR256:$src1, VR128:$src2,
-                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
-def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
-                                   (i32 imm)),
-          (VINSERTF128rr VR256:$src1, VR128:$src2,
-                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
-def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
-                                   (i32 imm)),
-          (VINSERTF128rr VR256:$src1, VR128:$src2,
-                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
-
-def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
-          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
-def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
-          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
-def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
-          (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
-
-def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
-          (v4f32 (VEXTRACTF128rr
-                    (v8f32 VR256:$src1),
-                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
-def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
-          (v2f64 (VEXTRACTF128rr
-                    (v4f64 VR256:$src1),
-                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
-def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
-          (v4i32 (VEXTRACTF128rr
-                    (v8i32 VR256:$src1),
-                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
-def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
-          (v2i64 (VEXTRACTF128rr
-                    (v4i64 VR256:$src1),
-                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
-
-def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
-          (VBROADCASTF128 addr:$src)>;
-
 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
           (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
@@ -5491,6 +5493,17 @@
           (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
 
 //===----------------------------------------------------------------------===//
+// VZERO - Zero YMM registers
+//
+// Zero All YMM registers
+def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
+                 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
+
+// Zero Upper bits of YMM registers
+def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
+                   [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
+
+//===----------------------------------------------------------------------===//
 // SSE Shuffle pattern fragments
 //===----------------------------------------------------------------------===//
 



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:33 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:33 -0000
Subject: [llvm-commits] [llvm] r135658 -
	/llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Message-ID: <20110721015533.8C2BB2A6C12F@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:33 2011
New Revision: 135658

URL: http://llvm.org/viewvc/llvm-project?rev=135658&view=rev
Log:
Add v16i16 type to VR256 class

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=135658&r1=135657&r2=135658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Wed Jul 20 20:55:33 2011
@@ -455,8 +455,8 @@
   let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
 }
 
-def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
-                          (sequence "YMM%u", 0, 15)> {
+def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
+                          256, (sequence "YMM%u", 0, 15)> {
   let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
 }
 



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:36 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:36 -0000
Subject: [llvm-commits] [llvm] r135659 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20110721015536.64A9F2A6C12D@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:36 2011
New Revision: 135659

URL: http://llvm.org/viewvc/llvm-project?rev=135659&view=rev
Log:
Add aditional patterns for vinsertf128 instruction

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135659&r1=135658&r2=135659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 20 20:55:36 2011
@@ -5346,6 +5346,14 @@
                                    (i32 imm)),
           (VINSERTF128rr VR256:$src1, VR128:$src2,
                          (INSERT_get_vinsertf128_imm VR256:$ins))>;
+def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
+def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
+                                   (i32 imm)),
+          (VINSERTF128rr VR256:$src1, VR128:$src2,
+                         (INSERT_get_vinsertf128_imm VR256:$ins))>;
 
 //===----------------------------------------------------------------------===//
 // VEXTRACTF128 - Extract packed floating-point values



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:39 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:39 -0000
Subject: [llvm-commits] [llvm] r135660 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20110721015539.7315A2A6C12E@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:39 2011
New Revision: 135660

URL: http://llvm.org/viewvc/llvm-project?rev=135660&view=rev
Log:
Add aditional patterns for vextractf128 instruction

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135660&r1=135659&r2=135660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 20 20:55:39 2011
@@ -5390,6 +5390,14 @@
           (v2i64 (VEXTRACTF128rr
                     (v4i64 VR256:$src1),
                     (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v8i16 (VEXTRACTF128rr
+                    (v16i16 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
+def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
+          (v16i8 (VEXTRACTF128rr
+                    (v32i8 VR256:$src1),
+                    (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
 
 //===----------------------------------------------------------------------===//
 // VMASKMOV - Conditional SIMD Packed Loads and Stores



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:42 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:42 -0000
Subject: [llvm-commits] [llvm] r135661 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110721015542.53AD52A6C12F@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:42 2011
New Revision: 135661

URL: http://llvm.org/viewvc/llvm-project?rev=135661&view=rev
Log:
Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135661&r1=135660&r2=135661&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 20:55:42 2011
@@ -3889,7 +3889,7 @@
   return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
 }
 
-/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
+/// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
                           SDValue V2) {
   unsigned NumElems = VT.getVectorNumElements();
@@ -3902,31 +3902,89 @@
   return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
 }
 
-/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
-static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
-  EVT PVT = MVT::v4f32;
-  EVT VT = SV->getValueType(0);
-  DebugLoc dl = SV->getDebugLoc();
-  SDValue V1 = SV->getOperand(0);
+// PromoteSplatv8v16 - All i16 and i8 vector types can't be used directly by
+// a generic shuffle instruction because the target has no such instructions.
+// Generate shuffles which repeat i16 and i8 several times until they can be
+// represented by v4f32 and then be manipulated by target suported shuffles.
+static SDValue PromoteSplatv8v16(SDValue V, SelectionDAG &DAG, int &EltNo) {
+  EVT VT = V.getValueType();
   int NumElems = VT.getVectorNumElements();
-  int EltNo = SV->getSplatIndex();
+  DebugLoc dl = V.getDebugLoc();
 
-  // unpack elements to the correct location
   while (NumElems > 4) {
     if (EltNo < NumElems/2) {
-      V1 = getUnpackl(DAG, dl, VT, V1, V1);
+      V = getUnpackl(DAG, dl, VT, V, V);
     } else {
-      V1 = getUnpackh(DAG, dl, VT, V1, V1);
+      V = getUnpackh(DAG, dl, VT, V, V);
       EltNo -= NumElems/2;
     }
     NumElems >>= 1;
   }
+  return V;
+}
+
+/// getLegalSplat - Generate a legal splat with supported x86 shuffles
+static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
+  EVT VT = V.getValueType();
+  DebugLoc dl = V.getDebugLoc();
+  assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
+         && "Vector size not supported");
+
+  bool Is128 = VT.getSizeInBits() == 128;
+  EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32;
+  V = DAG.getNode(ISD::BITCAST, dl, NVT, V);
+
+  if (Is128) {
+    int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
+    V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
+  } else {
+    // The second half of indicies refer to the higher part, which is a
+    // duplication of the lower one. This makes this shuffle a perfect match
+    // for the VPERM instruction.
+    int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
+                         EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
+    V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
+  }
+
+  return DAG.getNode(ISD::BITCAST, dl, VT, V);
+}
+
+/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
+/// v8i32, v16i16 or v32i8 to v8f32.
+static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
+  EVT SrcVT = SV->getValueType(0);
+  SDValue V1 = SV->getOperand(0);
+  DebugLoc dl = SV->getDebugLoc();
+
+  int EltNo = SV->getSplatIndex();
+  int NumElems = SrcVT.getVectorNumElements();
+  unsigned Size = SrcVT.getSizeInBits();
+
+  // Extract the 128-bit part containing the splat element and update
+  // the splat element index when it refers to the higher register.
+  if (Size == 256) {
+    unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
+    V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
+    if (Idx > 0)
+      EltNo -= NumElems/2;
+  }
+
+  // Make this 128-bit vector duplicate i8 and i16 elements
+  if (NumElems > 4)
+    V1 = PromoteSplatv8v16(V1, DAG, EltNo);
+
+  // Recreate the 256-bit vector and place the same 128-bit vector
+  // into the low and high part. This is necessary because we want
+  // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles
+  // inside each separate v4f32 lane.
+  if (Size == 256) {
+    SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
+                         DAG.getConstant(0, MVT::i32), DAG, dl);
+    V1 = Insert128BitVector(InsV, V1,
+               DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
+  }
 
-  // Perform the splat.
-  int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
-  V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
-  V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
-  return DAG.getNode(ISD::BITCAST, dl, VT, V1);
+  return getLegalSplat(DAG, V1, EltNo);
 }
 
 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
@@ -5663,19 +5721,24 @@
 
   // Handle splat operations
   if (SVOp->isSplat()) {
-    // Special case, this is the only place now where it's
-    // allowed to return a vector_shuffle operation without
-    // using a target specific node, because *hopefully* it
-    // will be optimized away by the dag combiner.
-    if (VT.getVectorNumElements() <= 4 &&
-        CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
+    unsigned NumElem = VT.getVectorNumElements();
+    // Special case, this is the only place now where it's allowed to return
+    // a vector_shuffle operation without using a target specific node, because
+    // *hopefully* it will be optimized away by the dag combiner. FIXME: should
+    // this be moved to DAGCombine instead?
+    if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
       return Op;
 
     // Handle splats by matching through known masks
-    if (VT.getVectorNumElements() <= 4)
+    if ((VT.is128BitVector() && NumElem <= 4) ||
+        (VT.is256BitVector() && NumElem <= 8))
       return SDValue();
 
-    // Canonicalize all of the remaining to v4f32.
+    // All i16 and i8 vector types can't be used directly by a generic shuffle
+    // instruction because the target has no such instruction. Generate shuffles
+    // which repeat i16 and i8 several times until they fit in i32, and then can
+    // be manipulated by target suported shuffles. After the insertion of the
+    // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
     return PromoteSplat(SVOp, DAG);
   }
 



From bruno.cardoso at gmail.com  Wed Jul 20 20:55:47 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 01:55:47 -0000
Subject: [llvm-commits] [llvm] r135662 - in /llvm/trunk:
 lib/Target/X86/InstPrinter/X86InstComments.cpp
 lib/Target/X86/Utils/X86ShuffleDecode.cpp
 lib/Target/X86/Utils/X86ShuffleDecode.h lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-256-splat.ll
Message-ID: <20110721015547.C1D342A6C12D@llvm.org>

Author: bruno
Date: Wed Jul 20 20:55:47 2011
New Revision: 135662

URL: http://llvm.org/viewvc/llvm-project?rev=135662&view=rev
Log:
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

Added:
    llvm/trunk/test/CodeGen/X86/avx-256-splat.ll
Modified:
    llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
    llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp
    llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Wed Jul 20 20:55:47 2011
@@ -205,6 +205,16 @@
     DecodeUNPCKHPMask(4, ShuffleMask);
     Src1Name = getRegName(MI->getOperand(0).getReg());
     break;
+  case X86::VPERMILPSYri:
+    DecodeVPERMILPSMask(8, MI->getOperand(2).getImm(),
+                        ShuffleMask);
+    Src1Name = getRegName(MI->getOperand(0).getReg());
+    break;
+  case X86::VPERMILPDYri:
+    DecodeVPERMILPSMask(4, MI->getOperand(2).getImm(),
+                        ShuffleMask);
+    Src1Name = getRegName(MI->getOperand(0).getReg());
+    break;
   }
 
 

Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp (original)
+++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp Wed Jul 20 20:55:47 2011
@@ -187,4 +187,31 @@
   }
 }
 
+void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
+                        SmallVectorImpl &ShuffleMask) {
+  DecodeVPERMILMask(MVT::getVectorVT(MVT::i32, NElts), Imm, ShuffleMask);
+}
+
+void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
+                        SmallVectorImpl &ShuffleMask) {
+  DecodeVPERMILMask(MVT::getVectorVT(MVT::i64, NElts), Imm, ShuffleMask);
+}
+
+// DecodeVPERMILMask - Decodes VPERMIL permutes for any 128-bit
+// with 32/64-bit elements. For 256-bit vectors, it's considered
+// as two 128 lanes and the mask of the first lane should be
+// identical of the second one.
+void DecodeVPERMILMask(EVT VT, unsigned Imm,
+                       SmallVectorImpl &ShuffleMask) {
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned NumLanes = VT.getSizeInBits()/128;
+
+  for (unsigned l = 0; l != NumLanes; ++l) {
+    for (unsigned i = 0; i != NumElts/NumLanes; ++i) {
+      unsigned Idx = (Imm >> (i*2)) & 0x3 ;
+      ShuffleMask.push_back(Idx+(l*NumElts/NumLanes));
+    }
+  }
+}
+
 } // llvm namespace

Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h (original)
+++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.h Wed Jul 20 20:55:47 2011
@@ -82,6 +82,20 @@
 void DecodeUNPCKLPMask(EVT VT,
                        SmallVectorImpl &ShuffleMask);
 
+
+void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
+                        SmallVectorImpl &ShuffleMask);
+
+void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
+                        SmallVectorImpl &ShuffleMask);
+
+// DecodeVPERMILMask - Decodes VPERMIL permutes for any 128-bit
+// with 32/64-bit elements. For 256-bit vectors, it's considered
+// as two 128 lanes and the mask of the first lane should be
+// identical of the second one.
+void DecodeVPERMILMask(EVT VT, unsigned Imm,
+                       SmallVectorImpl &ShuffleMask);
+
 } // llvm namespace
 
 #endif

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 20:55:47 2011
@@ -2747,6 +2747,7 @@
   case X86ISD::PUNPCKHBW:
   case X86ISD::PUNPCKHDQ:
   case X86ISD::PUNPCKHQDQ:
+  case X86ISD::VPERMIL:
     return true;
   }
   return false;
@@ -2772,6 +2773,7 @@
   case X86ISD::PSHUFD:
   case X86ISD::PSHUFHW:
   case X86ISD::PSHUFLW:
+  case X86ISD::VPERMIL:
     return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
   }
 
@@ -3422,6 +3424,54 @@
   return ::isMOVLMask(M, N->getValueType(0));
 }
 
+/// isVPERMILMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to VPERMIL*.
+static bool isVPERMILMask(const SmallVectorImpl &Mask, EVT VT) {
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned NumLanes = VT.getSizeInBits()/128;
+
+  // Match any permutation of 128-bit vector with 32/64-bit types
+  if (NumLanes == 1) {
+    if (NumElts == 4 || NumElts == 2)
+      return true;
+    return false;
+  }
+
+  // Only match 256-bit with 32/64-bit types
+  if (NumElts != 8 && NumElts != 4)
+    return false;
+
+  // The mask on the high lane should be the same as the low. Actually,
+  // they can differ if any of the corresponding index in a lane is undef.
+  int LaneSize = NumElts/NumLanes;
+  for (int i = 0; i < LaneSize; ++i) {
+    int HighElt = i+LaneSize;
+    if (Mask[i] < 0 || Mask[HighElt] < 0)
+      continue;
+
+    if (Mask[HighElt]-Mask[i] != LaneSize)
+      return false;
+  }
+
+  return true;
+}
+
+/// getShuffleVPERMILImmediateediate - Return the appropriate immediate to shuffle
+/// the specified VECTOR_MASK mask with VPERMIL* instructions.
+static unsigned getShuffleVPERMILImmediate(SDNode *N) {
+  ShuffleVectorSDNode *SVOp = cast(N);
+  EVT VT = SVOp->getValueType(0);
+
+  int NumElts = VT.getVectorNumElements();
+  int NumLanes = VT.getSizeInBits()/128;
+
+  unsigned Mask = 0;
+  for (int i = 0; i < NumElts/NumLanes /* lane size */; ++i)
+    Mask |= SVOp->getMaskElt(i) << (i*2);
+
+  return Mask;
+}
+
 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
 /// of what x86 movss want. X86 movs requires the lowest  element to be lowest
 /// element of vector 2 and the other elements to come from vector 1 in order.
@@ -4097,6 +4147,10 @@
       return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
                                  Depth+1);
     }
+    case X86ISD::VPERMIL:
+      ImmN = N->getOperand(N->getNumOperands()-1);
+      DecodeVPERMILMask(VT, cast(ImmN)->getZExtValue(),
+                        ShuffleMask);
     default:
       assert("not implemented for target shuffle node");
       return SDValue();
@@ -6043,6 +6097,13 @@
   if (NumElems == 4)
     return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
 
+  // Handle VPERMIL permutations
+  if (isVPERMILMask(M, VT)) {
+    unsigned TargetMask = getShuffleVPERMILImmediate(SVOp);
+    if (VT == MVT::v8f32)
+      return getTargetShuffleNode(X86ISD::VPERMIL, dl, VT, V1, TargetMask, DAG);
+  }
+
   return SDValue();
 }
 
@@ -9660,6 +9721,7 @@
   case X86ISD::PUNPCKHWD:          return "X86ISD::PUNPCKHWD";
   case X86ISD::PUNPCKHDQ:          return "X86ISD::PUNPCKHDQ";
   case X86ISD::PUNPCKHQDQ:         return "X86ISD::PUNPCKHQDQ";
+  case X86ISD::VPERMIL:            return "X86ISD::VPERMIL";
   case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
   case X86ISD::VAARG_64:           return "X86ISD::VAARG_64";
   case X86ISD::WIN_ALLOCA:         return "X86ISD::WIN_ALLOCA";
@@ -12465,6 +12527,7 @@
   case X86ISD::PSHUFLW:
   case X86ISD::MOVSS:
   case X86ISD::MOVSD:
+  case X86ISD::VPERMIL:
   case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
   }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jul 20 20:55:47 2011
@@ -271,6 +271,7 @@
       PUNPCKHWD,
       PUNPCKHDQ,
       PUNPCKHQDQ,
+      VPERMIL,
 
       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
       // according to %al. An operator is needed so that this can be expanded

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Jul 20 20:55:47 2011
@@ -150,6 +150,8 @@
 def X86Punpckhdq  : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>;
 def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>;
 
+def X86VPermil : SDNode<"X86ISD::VPERMIL", SDTShuff2OpI>;
+
 //===----------------------------------------------------------------------===//
 // SSE Complex Patterns
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135662&r1=135661&r2=135662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 20 20:55:47 2011
@@ -5529,6 +5529,10 @@
 // The AVX version of some but not all of them are described here, and more
 // should come in a near future.
 
+// Shuffle with VPERMIL instructions
+def : Pat<(v8f32 (X86VPermil VR256:$src1, (i8 imm:$imm))),
+          (VPERMILPSYri VR256:$src1, imm:$imm)>;
+
 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
 // SSE2 loads, which are always promoted to v2i64. The last one should match
 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD

Added: llvm/trunk/test/CodeGen/X86/avx-256-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-splat.ll?rev=135662&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-256-splat.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx-256-splat.ll Wed Jul 20 20:55:47 2011
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+
+; FIXME: use avx versions for punpcklbw and punpckhbw
+
+; CHECK: vextractf128 $0
+; CHECK-NEXT: punpcklbw
+; CHECK-NEXT: punpckhbw
+; CHECK-NEXT: vinsertf128 $0
+; CHECK-NEXT: vinsertf128 $1
+; CHECK-NEXT: vpermilps $85
+define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> 
+  ret <32 x i8> %shuffle
+}
+



From bruno.cardoso at gmail.com  Wed Jul 20 21:24:08 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 02:24:08 -0000
Subject: [llvm-commits] [llvm] r135663 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx-256-splat.ll
Message-ID: <20110721022408.D0A9D2A6C12D@llvm.org>

Author: bruno
Date: Wed Jul 20 21:24:08 2011
New Revision: 135663

URL: http://llvm.org/viewvc/llvm-project?rev=135663&view=rev
Log:
- Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx-256-splat.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135663&r1=135662&r2=135663&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 20 21:24:08 2011
@@ -970,11 +970,12 @@
     setOperationAction(ISD::VSETCC,             MVT::v2i64, Custom);
 
   if (!UseSoftFloat && Subtarget->hasAVX()) {
-    addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
-    addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
-    addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
-    addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
-    addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
+    addRegisterClass(MVT::v32i8,  X86::VR256RegisterClass);
+    addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
+    addRegisterClass(MVT::v8i32,  X86::VR256RegisterClass);
+    addRegisterClass(MVT::v8f32,  X86::VR256RegisterClass);
+    addRegisterClass(MVT::v4i64,  X86::VR256RegisterClass);
+    addRegisterClass(MVT::v4f64,  X86::VR256RegisterClass);
 
     setOperationAction(ISD::LOAD,               MVT::v8f32, Legal);
     setOperationAction(ISD::LOAD,               MVT::v4f64, Legal);

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=135663&r1=135662&r2=135663&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 20 21:24:08 2011
@@ -3668,20 +3668,22 @@
 }
 
 let Predicates = [HasAVX] in {
-  def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
-  def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
-  def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
-  def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
-  def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
-  def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
-  def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
-  def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
-  def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
-  def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
-  def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
-  def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
-  def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
-  def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
+  def : Pat<(v4f64  (bitconvert (v8f32 VR256:$src))),  (v4f64 VR256:$src)>;
+  def : Pat<(v4f64  (bitconvert (v4i64 VR256:$src))),  (v4f64 VR256:$src)>;
+  def : Pat<(v4f64  (bitconvert (v32i8 VR256:$src))),  (v4f64 VR256:$src)>;
+  def : Pat<(v8f32  (bitconvert (v4i64 VR256:$src))),  (v8f32 VR256:$src)>;
+  def : Pat<(v8f32  (bitconvert (v4f64 VR256:$src))),  (v8f32 VR256:$src)>;
+  def : Pat<(v8f32  (bitconvert (v32i8 VR256:$src))),  (v8f32 VR256:$src)>;
+  def : Pat<(v8f32  (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
+  def : Pat<(v4i64  (bitconvert (v8f32 VR256:$src))),  (v4i64 VR256:$src)>;
+  def : Pat<(v4i64  (bitconvert (v4f64 VR256:$src))),  (v4i64 VR256:$src)>;
+  def : Pat<(v4i64  (bitconvert (v32i8 VR256:$src))),  (v4i64 VR256:$src)>;
+  def : Pat<(v32i8  (bitconvert (v4f64 VR256:$src))),  (v32i8 VR256:$src)>;
+  def : Pat<(v32i8  (bitconvert (v4i64 VR256:$src))),  (v32i8 VR256:$src)>;
+  def : Pat<(v32i8  (bitconvert (v8f32 VR256:$src))),  (v32i8 VR256:$src)>;
+  def : Pat<(v32i8  (bitconvert (v8i32 VR256:$src))),  (v32i8 VR256:$src)>;
+  def : Pat<(v8i32  (bitconvert (v32i8 VR256:$src))),  (v8i32 VR256:$src)>;
+  def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))),  (v16i16 VR256:$src)>;
 }
 
 // Move scalar to XMM zero-extended

Modified: llvm/trunk/test/CodeGen/X86/avx-256-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-splat.ll?rev=135663&r1=135662&r2=135663&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-256-splat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-256-splat.ll Wed Jul 20 21:24:08 2011
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
-; FIXME: use avx versions for punpcklbw and punpckhbw
+; FIXME: use avx versions for punpcklbw, punpckhbw and punpckhwd
 
 ; CHECK: vextractf128 $0
 ; CHECK-NEXT: punpcklbw
@@ -14,3 +14,14 @@
   ret <32 x i8> %shuffle
 }
 
+; CHECK: vextractf128 $0
+; CHECK-NEXT: punpckhwd
+; CHECK-NEXT: vinsertf128 $0
+; CHECK-NEXT: vinsertf128 $1
+; CHECK-NEXT: vpermilps $85
+define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> 
+  ret <16 x i16> %shuffle
+}
+



From grosser at fim.uni-passau.de  Wed Jul 20 16:02:48 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 20 Jul 2011 21:02:48 -0000
Subject: [llvm-commits] [zorg] r135620 -
	/zorg/trunk/buildbot/osuosl/master/config/status.py
Message-ID: <20110720210248.C59D42A6C12D@llvm.org>

Author: grosser
Date: Wed Jul 20 16:02:48 2011
New Revision: 135620

URL: http://llvm.org/viewvc/llvm-project?rev=135620&view=rev
Log:
Send myself mails, if the Polly buildbot fails

Modified:
    zorg/trunk/buildbot/osuosl/master/config/status.py

Modified: zorg/trunk/buildbot/osuosl/master/config/status.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/status.py?rev=135620&r1=135619&r2=135620&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/status.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/status.py Wed Jul 20 16:02:48 2011
@@ -34,4 +34,13 @@
             builders = ["dragonegg-i386-linux", "dragonegg-x86_64-linux"],
             addLogs=False,
             num_lines = 15),
+        InformativeMailNotifier(
+            fromaddr = "buildbot at google1.osuosl.org",
+            sendToInterestedUsers= False,
+            extraRecipients = ["tobias at grosser.es"],
+            subject="Build %(builder)s Failure",
+            mode = "failing",
+            builders = ["polly-amd64-linux"],
+            addLogs=False,
+            num_lines = 15),
         ]



From raghesh.a at gmail.com  Wed Jul 20 19:08:23 2011
From: raghesh.a at gmail.com (Raghesh Aloor)
Date: Thu, 21 Jul 2011 00:08:23 -0000
Subject: [llvm-commits] [polly] r135641 -
	/polly/trunk/www/documentation/memaccess.html
Message-ID: <20110721000823.353362A6C12D@llvm.org>

Author: raghesh
Date: Wed Jul 20 19:08:23 2011
New Revision: 135641

URL: http://llvm.org/viewvc/llvm-project?rev=135641&view=rev
Log:
www: Memory Access Documentation Update


Modified:
    polly/trunk/www/documentation/memaccess.html

Modified: polly/trunk/www/documentation/memaccess.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=135641&r1=135640&r2=135641&view=diff
==============================================================================
--- polly/trunk/www/documentation/memaccess.html (original)
+++ polly/trunk/www/documentation/memaccess.html Wed Jul 20 19:08:23 2011
@@ -81,6 +81,10 @@
 }]
 
    
 We need to detect this access function change.
+
+
    Step 2
    
+Update the code generation module to reflect the access function change made
+in Step 1.
 
 
 



From geek4civic at gmail.com  Wed Jul 20 22:43:21 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 21 Jul 2011 12:43:21 +0900
Subject: [llvm-commits] [llvm] r135639 -
	/llvm/trunk/lib/MC/MCObjectFileInfo.cpp
In-Reply-To: <20110720235354.9E1C12A6C12D@llvm.org>
References: <20110720235354.9E1C12A6C12D@llvm.org>
Message-ID: 

2011/7/21 Evan Cheng :
> Author: evancheng
> Date: Wed Jul 20 18:53:54 2011
> New Revision: 135639
>
> URL: http://llvm.org/viewvc/llvm-project?rev=135639&view=rev
> Log:
> X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts.

Evan, it resolved test/CodeGen/X86 passed on win32 hosts, thanks.

Still I have weird failures, (why in powerpc?) gzip-ed logs attached.

On mingw,
Failing Tests (1):
    LLVM :: CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll

On msvc10(Release),
Failing Tests (8):
    LLVM :: CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
    LLVM :: CodeGen/PowerPC/fp-branch.ll
    LLVM :: CodeGen/PowerPC/ppcf128-4.ll
    LLVM :: CodeGen/PowerPC/select-cc.ll
    LLVM :: CodeGen/PowerPC/unsafe-math.ll
    LLVM :: CodeGen/PowerPC/vec_insert.ll
    LLVM :: CodeGen/PowerPC/vec_shift.ll
    LLVM :: CodeGen/PowerPC/vector.ll

...Takumi
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From geek4civic at gmail.com  Wed Jul 20 22:52:02 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 21 Jul 2011 12:52:02 +0900
Subject: [llvm-commits] [PATCH] Document how to maintain a git-svn clone
 of the LLVM git repositories
In-Reply-To: <20C4B91C-5F3E-4729-B6EA-A9AF55629AA9@2pi.dk>
References: 
	
	
	<80718B42-483F-413F-A72D-067041C623E6@2pi.dk>
	
	
	
	
	
	
	
	<20C4B91C-5F3E-4729-B6EA-A9AF55629AA9@2pi.dk>
Message-ID: 

2011/7/21 Jakob Stoklund Olesen :
> What happens if your spell your name differently that the server does?

As far as I tried, "partial reconstruction of rev_map" occur in the
next "git-svn dcommit".
It was just similar to dcommit w/o authorsfile.
I was afraid full reconstruction might run..., I won't trigger full
reconstruction.

As expected, git-svn dcommit makes an undesired commit (and the commit
is marked in rev_map).
After upstream commit was made, git-pull --rebase can cancel the undesired one.
(Then, rev_map points on undesired one)

It might be "better than nothing" to use oneline authorsfile.
I will add authorsfile topic when we will create docs/Git.html ;)

...Takumi

From geek4civic at gmail.com  Wed Jul 20 22:57:24 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 21 Jul 2011 12:57:24 +0900
Subject: [llvm-commits] [llvm] r135639 -
	/llvm/trunk/lib/MC/MCObjectFileInfo.cpp
In-Reply-To: <20110720235354.9E1C12A6C12D@llvm.org>
References: <20110720235354.9E1C12A6C12D@llvm.org>
Message-ID: 

FYI, stack trace by Debug build on vs10.

FAIL: LLVM :: CodeGen/PowerPC/vec_shift.ll (1502 of 6050)
******************** TEST 'LLVM :: CodeGen/PowerPC/vec_shift.ll'
FAILED ********************
Script:
--
E:/llvm/build/cmake-vs10/bin/Debug/llc.EXE <
E:/llvm/llvm-project/llvm/test/CodeGen/PowerPC/vec_shift.ll
-march=ppc32 -mcpu=g5
--
Exit Code: None
Command Output (stdout):
--
Command 0: "E:/llvm/build/cmake-vs10/bin/Debug/llc.EXE" "-march=ppc32"
"-mcpu=g5"
Command 0 Result: -3
Command 0 Output:


Command 0 Stderr:
Stack dump:
0.        Program arguments:
E:/llvm/build/cmake-vs10/bin/Debug/llc.EXE -march=ppc32 -mcpu=g5
1.    Running pass 'Function Pass Manager' on module ''.
2.    Running pass 'Linux PPC Assembly Printer' on function '@update'
01A76DA2 (0xCDCDCDCD 0x00C6F19C 0x00000000 0x0017DDB0), `anonymous
namespace'::MCAsmStreamer::ChangeSection()+0082 bytes(s),
e:\llvm\llvm-project\llvm\lib\mc\mcasmstreamer.cpp, line 307+0019
byte(s)
0109D654 (0xCDCDCDCD 0x00C6F3C4 0x00C6F32C 0x00000000),
llvm::MCStreamer::SwitchSection()+0148 bytes(s),
e:\llvm\llvm-project\llvm\include\llvm\mc\mcstreamer.h, line 194+0019
byte(s)
0138E29D (0x00C6F454 0x00C6F3DC 0xCCCCCCCC 0xCCCCCCCC),
llvm::AsmPrinter::EmitConstantPool()+0941 bytes(s),
e:\llvm\llvm-project\llvm\lib\codegen\asmprinter\asmprinter.cpp, line
1002
0138B9F1 (0x0017DF28 0x00C6F3E8 0x015B9B90 0x00181828),
llvm::AsmPrinter::EmitFunctionHeader()+0049 bytes(s),
e:\llvm\llvm-project\llvm\lib\codegen\asmprinter\asmprinter.cpp, line
416+0015 byte(s)
00F9EB22 (0x00181828 0x00C6F3F4 0x00181828 0x0017DF28),
llvm::AsmPrinter::runOnMachineFunction()+0034 bytes(s),
e:\llvm\llvm-project\llvm\include\llvm\codegen\asmprinter.h, line 166
015B9B90 (0x00140770 0x00C6F53C 0x00C6F490 0x00000000),
llvm::MachineFunctionPass::runOnFunction()+0080 bytes(s),
e:\llvm\llvm-project\llvm\lib\codegen\machinefunctionpass.cpp, line
33+0019 byte(s)
01933360 (0x00140770 0xCCCCCCCC 0xCCCCCCCC 0x0013D76C),
llvm::FPPassManager::runOnFunction()+0304 bytes(s),
e:\llvm\llvm-project\llvm\lib\vmcore\passmanager.cpp, line 1513+0023
byte(s)
0193350E (0x0013D7A0 0x00C6F838 0x00C6F548 0x00000000),
llvm::FPPassManager::runOnModule()+0126 bytes(s),
e:\llvm\llvm-project\llvm\lib\vmcore\passmanager.cpp, line 1535+0017
byte(s)
01933838 (0x0013D7A0 0x00C6F578 0x7EFDE000 0x00000000),
llvm::MPPassManager::runOnModule()+0360 bytes(s),
e:\llvm\llvm-project\llvm\lib\vmcore\passmanager.cpp, line 1589+0023
byte(s)
01933D69 (0x0013D7A0 0x00C6F62C 0x00C6F838 0x00F847C3),
llvm::PassManagerImpl::run()+0169 bytes(s),
e:\llvm\llvm-project\llvm\lib\vmcore\passmanager.cpp,line 1671+0027
byte(s)
019340CD (0x0013D7A0 0x00000000 0x00000000 0xCCCCCCCC),
llvm::PassManager::run()+0029 bytes(s),
e:\llvm\llvm-project\llvm\lib\vmcore\passmanager.cpp, line 1716
00F847C3 (0x00000003 0x00DC34E0 0x00DC1FC0 0x171BEB6A), main()+2819
bytes(s), e:\llvm\llvm-project\llvm\tools\llc\llc.cpp, line 374
01B0F92F (0x00C6F89C 0x751D33CA 0x7EFDE000 0x00C6F8DC),
__tmainCRTStartup()+0447 bytes(s),
f:\dd\vctools\crt_bld\self_x86\crt\src\crtexe.c, line 555+0025 byte(s)
01B0F75F (0x7EFDE000 0x00C6F8DC 0x77519ED2 0x7EFDE000),
mainCRTStartup()+0015 bytes(s),
f:\dd\vctools\crt_bld\self_x86\crt\src\crtexe.c, line 371
751D33CA (0x7EFDE000 0x13F52BB8 0x00000000 0x00000000),
BaseThreadInitThunk()+0018 bytes(s)
77519ED2 (0x01B0F750 0x7EFDE000 0x00000000 0x00000000),
RtlInitializeExceptionChain()+0099 bytes(s)
77519EA5 (0x01B0F750 0x7EFDE000 0x00000000 0x00000000),
RtlInitializeExceptionChain()+0054 bytes(s)

From sabre at nondot.org  Thu Jul 21 01:21:31 2011
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 21 Jul 2011 06:21:31 -0000
Subject: [llvm-commits] [llvm] r135669 - in /llvm/trunk:
 include/llvm/ADT/STLExtras.h lib/Support/StringExtras.cpp
 lib/Transforms/IPO/GlobalOpt.cpp lib/Transforms/Scalar/IndVarSimplify.cpp
 lib/Transforms/Scalar/SCCP.cpp lib/VMCore/Module.cpp
 utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20110721062131.BADE12A6C12D@llvm.org>

Author: lattner
Date: Thu Jul 21 01:21:31 2011
New Revision: 135669

URL: http://llvm.org/viewvc/llvm-project?rev=135669&view=rev
Log:
move tier out of an anonymous namespace, it doesn't make sense
to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.

Modified:
    llvm/trunk/include/llvm/ADT/STLExtras.h
    llvm/trunk/lib/Support/StringExtras.cpp
    llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/lib/VMCore/Module.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/include/llvm/ADT/STLExtras.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/STLExtras.h?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/STLExtras.h (original)
+++ llvm/trunk/include/llvm/ADT/STLExtras.h Thu Jul 21 01:21:31 2011
@@ -186,25 +186,21 @@
 //   // do stuff
 // else
 //   // do other stuff
-
-namespace
-{
-  template 
-  struct tier {
-    typedef T1 &first_type;
-    typedef T2 &second_type;
-
-    first_type first;
-    second_type second;
-
-    tier(first_type f, second_type s) : first(f), second(s) { }
-    tier& operator=(const std::pair& p) {
-      first = p.first;
-      second = p.second;
-      return *this;
-    }
-  };
-}
+template 
+struct tier {
+  typedef T1 &first_type;
+  typedef T2 &second_type;
+
+  first_type first;
+  second_type second;
+
+  tier(first_type f, second_type s) : first(f), second(s) { }
+  tier& operator=(const std::pair& p) {
+    first = p.first;
+    second = p.second;
+    return *this;
+  }
+};
 
 template 
 inline tier tie(T1& f, T2& s) {

Modified: llvm/trunk/lib/Support/StringExtras.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringExtras.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/lib/Support/StringExtras.cpp (original)
+++ llvm/trunk/lib/Support/StringExtras.cpp Thu Jul 21 01:21:31 2011
@@ -51,11 +51,10 @@
 void llvm::SplitString(StringRef Source,
                        SmallVectorImpl &OutFragments,
                        StringRef Delimiters) {
-  StringRef S2, S;
-  tie(S2, S) = getToken(Source, Delimiters);
-  while (!S2.empty()) {
-    OutFragments.push_back(S2);
-    tie(S2, S) = getToken(S, Delimiters);
+  std::pair S = getToken(Source, Delimiters);
+  while (!S.first.empty()) {
+    OutFragments.push_back(S.first);
+    S = getToken(S.second, Delimiters);
   }
 }
 

Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Thu Jul 21 01:21:31 2011
@@ -1260,11 +1260,9 @@
   // already been seen first by another load, so its uses have already been
   // processed.
   PHINode *PN = cast(LoadUser);
-  bool Inserted;
-  DenseMap >::iterator InsertPos;
-  tie(InsertPos, Inserted) =
-    InsertedScalarizedValues.insert(std::make_pair(PN, std::vector()));
-  if (!Inserted) return;
+  if (!InsertedScalarizedValues.insert(std::make_pair(PN,
+                                              std::vector())).second)
+    return;
 
   // If this is the first time we've seen this PHI, recursively process all
   // users.

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jul 21 01:21:31 2011
@@ -1389,24 +1389,23 @@
       pushIVUsers(CurrIV, Simplified, SimpleIVUsers);
 
       while (!SimpleIVUsers.empty()) {
-        Instruction *UseInst, *Operand;
-        tie(UseInst, Operand) = SimpleIVUsers.pop_back_val();
+        std::pair Use =SimpleIVUsers.pop_back_val();
         // Bypass back edges to avoid extra work.
-        if (UseInst == CurrIV) continue;
+        if (Use.first == CurrIV) continue;
 
-        if (EliminateIVUser(UseInst, Operand)) {
-          pushIVUsers(Operand, Simplified, SimpleIVUsers);
+        if (EliminateIVUser(Use.first, Use.second)) {
+          pushIVUsers(Use.second, Simplified, SimpleIVUsers);
           continue;
         }
-        if (CastInst *Cast = dyn_cast(UseInst)) {
+        if (CastInst *Cast = dyn_cast(Use.first)) {
           bool IsSigned = Cast->getOpcode() == Instruction::SExt;
           if (IsSigned || Cast->getOpcode() == Instruction::ZExt) {
             CollectExtend(Cast, IsSigned, WI, SE, TD);
           }
           continue;
         }
-        if (isSimpleIVUser(UseInst, L, SE)) {
-          pushIVUsers(UseInst, Simplified, SimpleIVUsers);
+        if (isSimpleIVUser(Use.first, L, SE)) {
+          pushIVUsers(Use.first, Simplified, SimpleIVUsers);
         }
       }
       if (WI.WidestNativeType) {
@@ -1437,12 +1436,11 @@
       continue;
 
     const SCEV *S = SE->getSCEV(Phi);
-    DenseMap::const_iterator Pos;
-    bool Inserted;
-    tie(Pos, Inserted) = ExprToIVMap.insert(std::make_pair(S, Phi));
-    if (Inserted)
+    std::pair::const_iterator, bool> Tmp =
+      ExprToIVMap.insert(std::make_pair(S, Phi));
+    if (Tmp.second)
       continue;
-    PHINode *OrigPhi = Pos->second;
+    PHINode *OrigPhi = Tmp.first->second;
 
     // If one phi derives from the other via GEPs, types may differ.
     if (OrigPhi->getType() != Phi->getType())

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Thu Jul 21 01:21:31 2011
@@ -471,9 +471,9 @@
   /// UsersOfOverdefinedPHIs map for PN, remove them now.
   void RemoveFromOverdefinedPHIs(Instruction *I, PHINode *PN) {
     if (UsersOfOverdefinedPHIs.empty()) return;
-    std::multimap::iterator It, E;
-    tie(It, E) = UsersOfOverdefinedPHIs.equal_range(PN);
-    while (It != E) {
+    typedef std::multimap::iterator ItTy;
+    std::pair Range = UsersOfOverdefinedPHIs.equal_range(PN);
+    for (ItTy It = Range.first, E = Range.second; It != E;) {
       if (It->second == I)
         UsersOfOverdefinedPHIs.erase(It++);
       else
@@ -486,9 +486,9 @@
   /// (Duplicate entries do not break anything directly, but can lead to
   /// exponential growth of the table in rare cases.)
   void InsertInOverdefinedPHIs(Instruction *I, PHINode *PN) {
-    std::multimap::iterator J, E;
-    tie(J, E) = UsersOfOverdefinedPHIs.equal_range(PN);
-    for (; J != E; ++J)
+    typedef std::multimap::iterator ItTy;
+    std::pair Range = UsersOfOverdefinedPHIs.equal_range(PN);
+    for (ItTy J = Range.first, E = Range.second; J != E; ++J)
       if (J->second == I)
         return;
     UsersOfOverdefinedPHIs.insert(std::make_pair(PN, I));
@@ -692,13 +692,14 @@
     // There may be instructions using this PHI node that are not overdefined
     // themselves.  If so, make sure that they know that the PHI node operand
     // changed.
-    std::multimap::iterator I, E;
-    tie(I, E) = UsersOfOverdefinedPHIs.equal_range(&PN);
-    if (I == E)
+    typedef std::multimap::iterator ItTy;
+    std::pair Range = UsersOfOverdefinedPHIs.equal_range(&PN);
+    
+    if (Range.first == Range.second)
       return;
     
     SmallVector Users;
-    for (; I != E; ++I)
+    for (ItTy I = Range.first, E = Range.second; I != E; ++I)
       Users.push_back(I->second);
     while (!Users.empty())
       visit(Users.pop_back_val());

Modified: llvm/trunk/lib/VMCore/Module.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Module.cpp (original)
+++ llvm/trunk/lib/VMCore/Module.cpp Thu Jul 21 01:21:31 2011
@@ -82,8 +82,10 @@
   Module::Endianness ret = AnyEndianness;
   
   while (!temp.empty()) {
-    StringRef token = DataLayout;
-    tie(token, temp) = getToken(temp, "-");
+    std::pair P = getToken(temp, "-");
+    
+    StringRef token = P.first;
+    temp = P.second;
     
     if (token[0] == 'e') {
       ret = LittleEndian;
@@ -95,15 +97,16 @@
   return ret;
 }
 
-/// Target Pointer Size information...
+/// Target Pointer Size information.
 Module::PointerSize Module::getPointerSize() const {
   StringRef temp = DataLayout;
   Module::PointerSize ret = AnyPointerSize;
   
   while (!temp.empty()) {
-    StringRef token, signalToken;
-    tie(token, temp) = getToken(temp, "-");
-    tie(signalToken, token) = getToken(token, ":");
+    std::pair TmpP = getToken(temp, "-");
+    temp = TmpP.second;
+    TmpP = getToken(TmpP.first, ":");
+    StringRef token = TmpP.second, signalToken = TmpP.first;
     
     if (signalToken[0] == 'p') {
       int size = 0;

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=135669&r1=135668&r2=135669&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Thu Jul 21 01:21:31 2011
@@ -267,8 +267,9 @@
 
 void CGIOperandList::ProcessDisableEncoding(std::string DisableEncoding) {
   while (1) {
-    std::string OpName;
-    tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t");
+    std::pair P = getToken(DisableEncoding, " ,\t");
+    std::string OpName = P.first;
+    DisableEncoding = P.second;
     if (OpName.empty()) break;
 
     // Figure out which operand this is.



From dblaikie at gmail.com  Thu Jul 21 01:35:20 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Wed, 20 Jul 2011 23:35:20 -0700
Subject: [llvm-commits] [llvm] r135669 - in /llvm/trunk:
 include/llvm/ADT/STLExtras.h lib/Support/StringExtras.cpp
 lib/Transforms/IPO/GlobalOpt.cpp lib/Transforms/Scalar/IndVarSimplify.cpp
 lib/Transforms/Scalar/SCCP.cpp lib/VMCore/Module.cpp utils/TableGe
Message-ID: 

> move tier out of an anonymous namespace, it doesn't make sense
> to for it to be an an anon namespace and be in a header.

Thanks!

> Eliminate some extraenous uses of tie.

Just curious - which usage do you consider to be appropriate use of
tie & which is extraneous? Several of the cases seem like the help
readability by naming the variables & aren't much/any longer than the
version using the pair directly. And the example below seems like what
I would consider a canonical use case for tie. I take it you'd only
consider tie appropriate when both variables are not coming into
existence at the point of the tie, but instead are both coming from
broader scopes?

> - ? ?std::string OpName;
> - ? ?tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t");
> + ? ?std::pair P = getToken(DisableEncoding, " ,\t");
> + ? ?std::string OpName = P.first;
> + ? ?DisableEncoding = P.second;
> ? ? if (OpName.empty()) break;
>
> ? ? // Figure out which operand this is.


From sabre at nondot.org  Thu Jul 21 01:37:58 2011
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 20 Jul 2011 23:37:58 -0700
Subject: [llvm-commits] [llvm] r135669 - in /llvm/trunk:
	include/llvm/ADT/STLExtras.h lib/Support/StringExtras.cpp
	lib/Transforms/IPO/GlobalOpt.cpp
	lib/Transforms/Scalar/IndVarSimplify.cpp
	lib/Transforms/Scalar/SCCP.cpp lib/VMCore/Module.cpp utils/TableGe
In-Reply-To: 
References: 
Message-ID: 


On Jul 20, 2011, at 11:35 PM, David Blaikie wrote:

>> move tier out of an anonymous namespace, it doesn't make sense
>> to for it to be an an anon namespace and be in a header.
> 
> Thanks!
> 
>> Eliminate some extraenous uses of tie.
> 
> Just curious - which usage do you consider to be appropriate use of
> tie & which is extraneous? Several of the cases seem like the help
> readability by naming the variables & aren't much/any longer than the
> version using the pair directly. And the example below seems like what
> I would consider a canonical use case for tie. I take it you'd only
> consider tie appropriate when both variables are not coming into
> existence at the point of the tie, but instead are both coming from
> broader scopes?

I don't really like tie and would like it to go away.  I actually was scrubbing the code base when I ran into many legit uses in lib/CodeGen.  While I'd prefer the APIs involved to be changed to not return a pair (e.g. there are things that return pairs of bools, they could return the bools by-ref) keeping it around for now seems reasonable.

With C++'0x features like auto, the need for it would go away completely IMO.

-Chris

From clattner at apple.com  Thu Jul 21 02:38:25 2011
From: clattner at apple.com (Chris Lattner)
Date: Thu, 21 Jul 2011 00:38:25 -0700
Subject: [llvm-commits] Updated SAFECode Patch
In-Reply-To: <4E2606EB.2070300@illinois.edu>
References: <4E2606EB.2070300@illinois.edu>
Message-ID: <2FD8FC55-2374-4A6A-B021-AC81F65579B9@apple.com>

On Jul 19, 2011, at 3:36 PM, John Criswell wrote:
> Dear All,
> 
> Attached is an updated version of the SAFECode patch.  This patch:
> 
> 1) Is updated to the new LLVM type API; and
> 2) Can just be applied using patch -p0 < scpatch instead of having to untar an archive of changes.
> 3) Perhaps I forgot it in previous posts, but using patch -p0 < testpatch  in the test-suite directory will provide some test Makefiles which can be used by using "make TEST=sc report"
> 4) It includes a RewriteOOB pass which implements a feature called Out of Bounds Pointer rewriting.  Basically, it allows SAFECode to permit out of bound pointers provided that such pointers are not dereferenced.  It's an optional feature.

Hi John,

Thanks for updating this and I apologize again 10x for the delay reviewing this.  This is a *lot* of code to wade through.  Overall, the code is well structured and well commented.

Here are a few micro-level comments:

* Passes like InsertGEPChecks should be in a .cpp file that matches the pass name, and don't need the class to be exposed in a public header file (for the same reason the SCCP class (for example) is private to its own .cpp file).

* There is some '#if 0' code that should be removed.

* Did you guys actually write the asm blob in strncpy_asm?  Are you sure the code is not GPL?  It looks dead anyway, dead code should be zapped.

* Found a bug! :)

+  Constant * GAVConst = M->getOrInsertFunction ("pchk_getActualValue",
+                                                VoidPtrTy,
+                                                VoidPtrTy,
+                                                VoidPtrTy,
+                                                NULL);
+  Function * GetActualValue = dyn_cast(GAVConst);
...
+ use(GetActualValue)

The dyn_cast should be a cast<> or check for null.


* The code isn't fully detangled from the other projects in the research group, there are still references to llva, declarations but no definition of things like pool_rindex, etc.

* There are lots of minor coding style issues, such as the extra spaces in the code, some 80 col violations etc:

+static inline Value *
+peelCasts (Value * PointerOperand, std::set & Chain) {
+  Value * SourcePointer = PointerOperand;

* Inefficient containers like std::set and std::map are used pervasively, as are verboten classes like std::ostream.

* There are linux-system specific details in the code, I suspect it's not portable to other systems.  I also see various uses of unistd.h, errno.h etc.

* Why do you have an implementation of a SplayTree?  Why is it better than a hash table or other data structure?

* The files have the old LLVM copyright header on them.

* I see that the runtime library contains a bunch of pool allocation related stuff, is that used by the transformation patches or used by other parts of safecode that can't be included because they depend on DSA?

* Where is the documentation on how to use this? :-)  What are the features and limitations of this work in the absence of DSA and the other pieces?  You've made claims that this is generally useful for partial applications and other code, is this really true how does it work?



Anyway, those are some thoughts on the first pass through the code.  As it is, the code isn't ready to go in, and even if it were, it would be impossible to really review as a monolith.  Beyond that, I have my concerns about who is going to maintain and push forward this code going forward.  I'm not accusing you guys of it, but I have a general concerned about "abandonware" in the codebase, and do routinely purge apparently dead passes from the codebase.  Do you have particular clients that are actively using this and will defend against me not purging it in a future release?

If you're driven to get this better integrated into LLVM and available to a wider community, there are two routes you can take:

1. The work can be decomposed into small and incremental pieces that each deliver specific value, and you can propose and integrate these one piece at a time.  For example, start with one of the passes and a minimal runtime library that will catch some subset of the bugs.  Once that is in, rinse and repeat for the next piece and the next piece etc.  This is a really long road for this much code, but particularly if it is delivering concrete value and there is a client that will be using it, it is the right way to get it into the project.

2. You can rework the high level hooks of this to use the new PassManagerBuilder.h interface to "hook into" extension points in the standard pass manager, rework this code to be a clang plugin, and keep the code available in the safecode.llvm.org repo.  Doing this engineering work (to make it trivial to turn on with a stock clang) is really required for #1 anyway.  This will make it much easier for people to try safecode out, and we're pushing to split other parts of the codebase out into plugins as well (e.g. the clang static analyzer and the ARC migration tool), so hopefully that plugin infrastructure will continue to develop.

I guess option #3 is to maintain the status quo and keep safecode in its own repo right now.  Depending on what your goals are, this is actually a very attractive option for the same reasons that LLDB being in its own repo is: you can choose when and how to synch up to llvm (lldb just uses a "current recommend revision # of llvm), being a subproject allows you to move more quickly and make changes when it makes sense to you.


Anyway, I guess my message is that the route forward depends on what your goals are.  If your goal is to get it into mainline LLVM to get more users, then I think that things are backwards: we really want there to be end users driving things into the compiler, not the other way around.  If you're looking to reduce the cost of merging mainline API changes, there are *many* opportunities to adopt the C API in these passes, which would greatly reduce the amount of churn required to keep stuff working.  Even though there isn't C API for everything, there is for the most volatile stuff.

I hope this helps,

-Chris






From jay.foad at gmail.com  Thu Jul 21 02:52:17 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 07:52:17 -0000
Subject: [llvm-commits] [llvm] r135671 - in
 /llvm/trunk/include/llvm/Support: ConstantFolder.h IRBuilder.h NoFolder.h
 TargetFolder.h
Message-ID: <20110721075217.F38932A6C12E@llvm.org>

Author: foad
Date: Thu Jul 21 02:52:17 2011
New Revision: 135671

URL: http://llvm.org/viewvc/llvm-project?rev=135671&view=rev
Log:
Convert ConstantFolder APIs to use ArrayRef.

Modified:
    llvm/trunk/include/llvm/Support/ConstantFolder.h
    llvm/trunk/include/llvm/Support/IRBuilder.h
    llvm/trunk/include/llvm/Support/NoFolder.h
    llvm/trunk/include/llvm/Support/TargetFolder.h

Modified: llvm/trunk/include/llvm/Support/ConstantFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantFolder.h?rev=135671&r1=135670&r2=135671&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ConstantFolder.h (original)
+++ llvm/trunk/include/llvm/Support/ConstantFolder.h Thu Jul 21 02:52:17 2011
@@ -118,22 +118,36 @@
   // Memory Instructions
   //===--------------------------------------------------------------------===//
 
-  Constant *CreateGetElementPtr(Constant *C, Constant* const *IdxList,
-                                unsigned NumIdx) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList, NumIdx);
-  }
-  Constant *CreateGetElementPtr(Constant *C, Value* const *IdxList,
-                                unsigned NumIdx) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList, NumIdx);
-  }
-
-  Constant *CreateInBoundsGetElementPtr(Constant *C, Constant* const *IdxList,
-                                        unsigned NumIdx) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList, NumIdx);
-  }
-  Constant *CreateInBoundsGetElementPtr(Constant *C, Value* const *IdxList,
-                                        unsigned NumIdx) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList, NumIdx);
+  Constant *CreateGetElementPtr(Constant *C,
+                                ArrayRef IdxList) const {
+    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+  }
+  Constant *CreateGetElementPtr(Constant *C, Constant *Idx) const {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return ConstantExpr::getGetElementPtr(C, &Idx, 1);
+  }
+  Constant *CreateGetElementPtr(Constant *C,
+                                ArrayRef IdxList) const {
+    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+  }
+
+  Constant *CreateInBoundsGetElementPtr(Constant *C,
+                                        ArrayRef IdxList) const {
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
+                                                  IdxList.size());
+  }
+  Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *Idx) const {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return ConstantExpr::getInBoundsGetElementPtr(C, &Idx, 1);
+  }
+  Constant *CreateInBoundsGetElementPtr(Constant *C,
+                                        ArrayRef IdxList) const {
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
+                                                  IdxList.size());
   }
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=135671&r1=135670&r2=135671&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Thu Jul 21 02:52:17 2011
@@ -774,8 +774,8 @@
         if (!isa(*i))
           break;
       if (i == IdxEnd)
-        return Insert(Folder.CreateGetElementPtr(PC, &IdxBegin[0],
-                                                 IdxEnd - IdxBegin),
+        return Insert(Folder.CreateGetElementPtr(PC, makeArrayRef(IdxBegin,
+                                                                  IdxEnd)),
                       Name);
     }
     return Insert(GetElementPtrInst::Create(Ptr, IdxBegin, IdxEnd), Name);
@@ -792,8 +792,8 @@
           break;
       if (i == IdxEnd)
         return Insert(Folder.CreateInBoundsGetElementPtr(PC,
-                                                         &IdxBegin[0],
-                                                         IdxEnd - IdxBegin),
+                                                         makeArrayRef(IdxBegin,
+                                                                      IdxEnd)),
                       Name);
     }
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, IdxBegin, IdxEnd),
@@ -802,20 +802,20 @@
   Value *CreateGEP(Value *Ptr, Value *Idx, const Twine &Name = "") {
     if (Constant *PC = dyn_cast(Ptr))
       if (Constant *IC = dyn_cast(Idx))
-        return Insert(Folder.CreateGetElementPtr(PC, &IC, 1), Name);
+        return Insert(Folder.CreateGetElementPtr(PC, IC), Name);
     return Insert(GetElementPtrInst::Create(Ptr, Idx), Name);
   }
   Value *CreateInBoundsGEP(Value *Ptr, Value *Idx, const Twine &Name = "") {
     if (Constant *PC = dyn_cast(Ptr))
       if (Constant *IC = dyn_cast(Idx))
-        return Insert(Folder.CreateInBoundsGetElementPtr(PC, &IC, 1), Name);
+        return Insert(Folder.CreateInBoundsGetElementPtr(PC, IC), Name);
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idx), Name);
   }
   Value *CreateConstGEP1_32(Value *Ptr, unsigned Idx0, const Twine &Name = "") {
     Value *Idx = ConstantInt::get(Type::getInt32Ty(Context), Idx0);
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateGetElementPtr(PC, &Idx, 1), Name);
+      return Insert(Folder.CreateGetElementPtr(PC, Idx), Name);
 
     return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
   }
@@ -824,7 +824,7 @@
     Value *Idx = ConstantInt::get(Type::getInt32Ty(Context), Idx0);
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateInBoundsGetElementPtr(PC, &Idx, 1), Name);
+      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idx), Name);
 
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, &Idx, &Idx+1), Name);
   }
@@ -836,7 +836,7 @@
     };
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateGetElementPtr(PC, Idxs, 2), Name);
+      return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name);
 
     return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
   }
@@ -848,7 +848,7 @@
     };
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs, 2), Name);
+      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name);
 
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name);
   }
@@ -856,7 +856,7 @@
     Value *Idx = ConstantInt::get(Type::getInt64Ty(Context), Idx0);
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateGetElementPtr(PC, &Idx, 1), Name);
+      return Insert(Folder.CreateGetElementPtr(PC, Idx), Name);
 
     return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
   }
@@ -865,7 +865,7 @@
     Value *Idx = ConstantInt::get(Type::getInt64Ty(Context), Idx0);
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateInBoundsGetElementPtr(PC, &Idx, 1), Name);
+      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idx), Name);
 
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, &Idx, &Idx+1), Name);
   }
@@ -877,7 +877,7 @@
     };
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateGetElementPtr(PC, Idxs, 2), Name);
+      return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name);
 
     return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
   }
@@ -889,7 +889,7 @@
     };
 
     if (Constant *PC = dyn_cast(Ptr))
-      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs, 2), Name);
+      return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name);
 
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name);
   }

Modified: llvm/trunk/include/llvm/Support/NoFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/NoFolder.h?rev=135671&r1=135670&r2=135671&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/NoFolder.h (original)
+++ llvm/trunk/include/llvm/Support/NoFolder.h Thu Jul 21 02:52:17 2011
@@ -177,22 +177,23 @@
   // Memory Instructions
   //===--------------------------------------------------------------------===//
 
-  Constant *CreateGetElementPtr(Constant *C, Constant* const *IdxList,
-                                unsigned NumIdx) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList, NumIdx);
-  }
-  Instruction *CreateGetElementPtr(Constant *C, Value* const *IdxList,
-                                   unsigned NumIdx) const {
-    return GetElementPtrInst::Create(C, IdxList, IdxList+NumIdx);
-  }
-
-  Constant *CreateInBoundsGetElementPtr(Constant *C, Constant* const *IdxList,
-                                        unsigned NumIdx) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList, NumIdx);
-  }
-  Instruction *CreateInBoundsGetElementPtr(Constant *C, Value* const *IdxList,
-                                           unsigned NumIdx) const {
-    return GetElementPtrInst::CreateInBounds(C, IdxList, IdxList+NumIdx);
+  Constant *CreateGetElementPtr(Constant *C,
+                                ArrayRef IdxList) const {
+    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+  }
+  Instruction *CreateGetElementPtr(Constant *C,
+                                   ArrayRef IdxList) const {
+    return GetElementPtrInst::Create(C, IdxList.begin(), IdxList.end());
+  }
+
+  Constant *CreateInBoundsGetElementPtr(Constant *C,
+                                        ArrayRef IdxList) const {
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
+                                                  IdxList.size());
+  }
+  Instruction *CreateInBoundsGetElementPtr(Constant *C,
+                                           ArrayRef IdxList) const {
+    return GetElementPtrInst::CreateInBounds(C, IdxList.begin(), IdxList.end());
   }
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/Support/TargetFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetFolder.h?rev=135671&r1=135670&r2=135671&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetFolder.h (original)
+++ llvm/trunk/include/llvm/Support/TargetFolder.h Thu Jul 21 02:52:17 2011
@@ -130,22 +130,32 @@
   // Memory Instructions
   //===--------------------------------------------------------------------===//
 
-  Constant *CreateGetElementPtr(Constant *C, Constant* const *IdxList,
-                                unsigned NumIdx) const {
-    return Fold(ConstantExpr::getGetElementPtr(C, IdxList, NumIdx));
-  }
-  Constant *CreateGetElementPtr(Constant *C, Value* const *IdxList,
-                                unsigned NumIdx) const {
-    return Fold(ConstantExpr::getGetElementPtr(C, IdxList, NumIdx));
-  }
-
-  Constant *CreateInBoundsGetElementPtr(Constant *C, Constant* const *IdxList,
-                                        unsigned NumIdx) const {
-    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList, NumIdx));
-  }
-  Constant *CreateInBoundsGetElementPtr(Constant *C, Value* const *IdxList,
-                                        unsigned NumIdx) const {
-    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList, NumIdx));
+  Constant *CreateGetElementPtr(Constant *C,
+                                ArrayRef IdxList) const {
+    return Fold(ConstantExpr::getGetElementPtr(C, IdxList.data(),
+                                               IdxList.size()));
+  }
+  Constant *CreateGetElementPtr(Constant *C, Constant *Idx) const {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return Fold(ConstantExpr::getGetElementPtr(C, &Idx, 1));
+  }
+  Constant *CreateGetElementPtr(Constant *C,
+                                ArrayRef IdxList) const {
+    return Fold(ConstantExpr::getGetElementPtr(C, IdxList.data(),
+                                               IdxList.size()));
+  }
+
+  Constant *CreateInBoundsGetElementPtr(Constant *C,
+                                        ArrayRef IdxList) const {
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
+                                                       IdxList.size()));
+  }
+  Constant *CreateInBoundsGetElementPtr(Constant *C,
+                                        ArrayRef IdxList) const {
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
+                                                       IdxList.size()));
   }
 
   //===--------------------------------------------------------------------===//



From nicholas at mxc.ca  Thu Jul 21 03:06:32 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 21 Jul 2011 01:06:32 -0700
Subject: [llvm-commits] patch: go crazy,
 compute bits for an entire add instruction
In-Reply-To: 
References: <4E14001E.1040801@mxc.ca>	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>		<4E1EAFF1.1050809@mxc.ca>
	
Message-ID: <4E27DE08.2090308@mxc.ca>

Jay Foad wrote:
>> In general though, will I be
>> allowed to use an O(n) loop in ComputeMaskedBits if needed? I don't think
>> we'll be able to solve multiply without it--though we can try!
>
> I'd be very surprised if you get any real world benefit from trying to
> calculate the middle bits of the result of a multiply. Surely it's
> good enough to calculate just the low bits and the high bits?

No, I do want middle bits, but ...

> Or maybe you do want the middle bits, but only in the special case
> where one operand is a completely known constant. That might be easier
> to solve than the completely general case, but I haven't thought about
> it much.

... all the cases I care about right now have a constant RHS.

Jay, would you be willing to review this updated patch, now for add+sub? 
I think I'd like to do the rest (overflow intrinsics and bswap) next 
before moving on to mul, actually. I have piles of missed optz'ns of due 
to overflow intrinsics that I haven't solved.

In previous review over IRC, Chris complained that the change to 
InstSimplify was unclear and I promised to add comments. I have 
reconsidered, and consider the code clear enough with the same comments 
it had before (but with a bugfix). In particular the 'and' analysis only 
requests masked bits because we knows that if the whole result is 
constant than the result bits not in the mask must be zero, while an 
'or' could be setting all the unknown bits to one, but we still need 
ComputeMaskedBits to tell us what the other bits actually are. In 
addition, I've added four tests, one for each "return" statement in 
InstSimplify (another one of Chris' comments was that one of the returns 
was unreachable).

Nick
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From nicholas at mxc.ca  Thu Jul 21 03:32:34 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 21 Jul 2011 01:32:34 -0700
Subject: [llvm-commits] patch: teach sroa to scalarize lifetime
	intrinsics
In-Reply-To: <4E1C1409.1010207@mxc.ca>
References: <4E1C1409.1010207@mxc.ca>
Message-ID: <4E27E422.9050004@mxc.ca>

Ping!

The main thing I'm worried about is that isSafeForScalarRepl will now 
return true for values used by lifetime intrinsics, while only 
RewriteForScalarRepl knows how to rewrite them, not ConvertToScalarInfo. 
That's okay, right?

The other thing is the possible loss of performance due to chasing 
bitcasts to i8* in order to look for the intrinsics, but I don't see any 
obvious inefficiencies.

Updated for the type branch merge patch attached!

Nick

Nick Lewycky wrote:
> The attached patch extends sroa's ability to handle lifetime intrinsics.
> Despite the tests, I'm still not really confident that all the corner
> cases are handled properly and would appreciate a thorough review. I'm
> also unhappy with the innards of RewriteLifetimeIntrinsic() itself, but
> I don't see a way to straighten out the logic. Suggestions appreciated.
>
> Please review! This is another in the series of patches that should help
> PR10121, but there is still more to do in sroa.
>
> Nick
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From nicholas at mxc.ca  Thu Jul 21 03:35:18 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 21 Jul 2011 01:35:18 -0700
Subject: [llvm-commits] patch: go crazy,
 compute bits for an entire add instruction
In-Reply-To: <4E27DE08.2090308@mxc.ca>
References: <4E14001E.1040801@mxc.ca>	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>		<4E1EAFF1.1050809@mxc.ca>	
	<4E27DE08.2090308@mxc.ca>
Message-ID: <4E27E4C6.3040305@mxc.ca>

Pardon me, fixed patch attached. I had a buggy test.

Nick

Nick Lewycky wrote:
> Jay Foad wrote:
>>> In general though, will I be
>>> allowed to use an O(n) loop in ComputeMaskedBits if needed? I don't
>>> think
>>> we'll be able to solve multiply without it--though we can try!
>>
>> I'd be very surprised if you get any real world benefit from trying to
>> calculate the middle bits of the result of a multiply. Surely it's
>> good enough to calculate just the low bits and the high bits?
>
> No, I do want middle bits, but ...
>
>> Or maybe you do want the middle bits, but only in the special case
>> where one operand is a completely known constant. That might be easier
>> to solve than the completely general case, but I haven't thought about
>> it much.
>
> ... all the cases I care about right now have a constant RHS.
>
> Jay, would you be willing to review this updated patch, now for add+sub?
> I think I'd like to do the rest (overflow intrinsics and bswap) next
> before moving on to mul, actually. I have piles of missed optz'ns of due
> to overflow intrinsics that I haven't solved.
>
> In previous review over IRC, Chris complained that the change to
> InstSimplify was unclear and I promised to add comments. I have
> reconsidered, and consider the code clear enough with the same comments
> it had before (but with a bugfix). In particular the 'and' analysis only
> requests masked bits because we knows that if the whole result is
> constant than the result bits not in the mask must be zero, while an
> 'or' could be setting all the unknown bits to one, but we still need
> ComputeMaskedBits to tell us what the other bits actually are. In
> addition, I've added four tests, one for each "return" statement in
> InstSimplify (another one of Chris' comments was that one of the returns
> was unreachable).
>
> Nick
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From jay.foad at gmail.com  Thu Jul 21 03:48:59 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 09:48:59 +0100
Subject: [llvm-commits] patch: go crazy,
	compute bits for an entire add instruction
In-Reply-To: <4E27DE08.2090308@mxc.ca>
References: <4E14001E.1040801@mxc.ca>
	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>
	
	<4E1EAFF1.1050809@mxc.ca>
	
	<4E27DE08.2090308@mxc.ca>
Message-ID: 

> Jay, would you be willing to review this updated patch, now for add+sub?

OK, first some comments on the and/or parts:

> Index: lib/Analysis/InstructionSimplify.cpp
> ===================================================================
> --- lib/Analysis/InstructionSimplify.cpp	(revision 135567)
> +++ lib/Analysis/InstructionSimplify.cpp	(working copy)
> @@ -1211,6 +1211,21 @@
>                                        MaxRecurse))
>        return V;
>
> +  // Check whether the and instruction can be solved through bitwise analysis.
> +  if (ConstantInt *CI = dyn_cast(Op1)) {

I'd find it easier to read if CI was renamed to C1, or CI1, or COp1,
or *anything* that makes it clear that it's Op1.

> +    unsigned BitWidth = cast(Op0->getType())->getBitWidth();
> +    APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
> +    ComputeMaskedBits(Op0, CI->getValue(), KnownZero, KnownOne, TD, 0);
> +
> +    // Are the bits being and'd away already known to be zero?
> +    if ((CI->getValue() | KnownZero).isMaxValue())
> +      return Op0;
> +
> +    // Are all of the bits left after masking known?
> +    if ((KnownZero | KnownOne) == CI->getValue())

Does ComputeMaskedBits guarantee not to return with any bits set in
KnownZero/KnownOne outside of the bits you specified in the mask? If
not (i.e. if it treats the mask just as an optimisation, which it can
ignore if it chooses) you want something like:

  if ((CI->getValue() & ~(KnownZero | KnownOne)) == 0)

> +      return ConstantInt::get(Op0->getType(), KnownOne);
> +  }
> +
>    return 0;
>  }
>
> @@ -1305,6 +1320,23 @@
>                                        MaxRecurse))
>        return V;
>
> +  // Check whether the or instruction can be solved through bitwise analysis.
> +  if (ConstantInt *CI = dyn_cast(Op1)) {
> +    unsigned BitWidth = cast(Op0->getType())->getBitWidth();
> +    APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
> +    ComputeMaskedBits(Op0, APInt::getAllOnesValue(BitWidth),
> +                      KnownZero, KnownOne, TD, 0);

Surely you can specify ~CI->getValue() as the mask? Maybe this is the
asymmetry that it sounds like Chris complained about.

> +
> +    // Are the bits being or'd in already known to be one?
> +    if ((CI->getValue() & KnownOne) == CI->getValue())
> +      return Op0;
> +
> +    // Are all of the unknown bits being set to true by the or?
> +    if ((KnownZero | KnownOne | CI->getValue()).isMaxValue())
> +      return ConstantInt::get(Op0->getType(),
> +                              (KnownOne | CI->getValue()));
> +  }
> +
>    return 0;
>  }


Overall I think this is all reasonably clear.

But, couldn't you easily extend it to cover the case where Op1 isn't a
constant? Something like:

// for AND
ComputeMaskedBits(Op1, AllOnes, Op1KnownZero, Op1KnownOne);
ComputeMaskedBits(Op0, ~Op1KnownZero, Op0KnownZero, Op0KnownOne);

ResKnownZero = Op0KnownZero | Op1KnownZero;
ResKnownOne = Op0KnownOne & Op1KnownOne;
if ((ResKnownZero | ResKnownOne).isMaxValue())
  // All result bits known
  return ConstantInt::get(Op0KnownOne & Op1KnownOne);

if ((Op0KnownZero | Op1KnownOne).isMaxValue())
  // Op0 won't be changed by ANDing with Op1
  return Op0;

if ((Op0KnownOne | Op1KnownZero).isMaxValue())
  // Op1 won't be changed by ANDing with Op0
  return Op1;

However, this duplicates some of the logic from ComputeMaskedBits()
itself: the case where we return a constant here is exactly the case
where, if we called ComputeMaskedBits on the result of the AND
operation, it would tell us that all the bits are known. So why are we
getting this duplication in the first place? Isn't there some common
place where we can call ComputeMaskedBits on every expression, and if
all the bits are known, replace the operation with a constant?

Jay.

From nicholas at mxc.ca  Thu Jul 21 04:09:25 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 21 Jul 2011 02:09:25 -0700
Subject: [llvm-commits] patch: go crazy,
 compute bits for an entire add instruction
In-Reply-To: 
References: <4E14001E.1040801@mxc.ca>	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>		<4E1EAFF1.1050809@mxc.ca>		<4E27DE08.2090308@mxc.ca>
	
Message-ID: <4E27ECC5.7080704@mxc.ca>

Jay Foad wrote:
>> Jay, would you be willing to review this updated patch, now for add+sub?
>
> OK, first some comments on the and/or parts:
>
>> Index: lib/Analysis/InstructionSimplify.cpp
>> ===================================================================
>> --- lib/Analysis/InstructionSimplify.cpp	(revision 135567)
>> +++ lib/Analysis/InstructionSimplify.cpp	(working copy)
>> @@ -1211,6 +1211,21 @@
>>                                         MaxRecurse))
>>         return V;
>>
>> +  // Check whether the and instruction can be solved through bitwise analysis.
>> +  if (ConstantInt *CI = dyn_cast(Op1)) {
>
> I'd find it easier to read if CI was renamed to C1, or CI1, or COp1,
> or *anything* that makes it clear that it's Op1.

Ok, Op1CI then.

>
>> +    unsigned BitWidth = cast(Op0->getType())->getBitWidth();
>> +    APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
>> +    ComputeMaskedBits(Op0, CI->getValue(), KnownZero, KnownOne, TD, 0);
>> +
>> +    // Are the bits being and'd away already known to be zero?
>> +    if ((CI->getValue() | KnownZero).isMaxValue())
>> +      return Op0;
>> +
>> +    // Are all of the bits left after masking known?
>> +    if ((KnownZero | KnownOne) == CI->getValue())
>
> Does ComputeMaskedBits guarantee not to return with any bits set in
> KnownZero/KnownOne outside of the bits you specified in the mask?

Yep.

  If
> not (i.e. if it treats the mask just as an optimisation, which it can
> ignore if it chooses) you want something like:
>
>    if ((CI->getValue()&  ~(KnownZero | KnownOne)) == 0)
>
>> +      return ConstantInt::get(Op0->getType(), KnownOne);
>> +  }
>> +
>>     return 0;
>>   }
>>
>> @@ -1305,6 +1320,23 @@
>>                                         MaxRecurse))
>>         return V;
>>
>> +  // Check whether the or instruction can be solved through bitwise analysis.
>> +  if (ConstantInt *CI = dyn_cast(Op1)) {
>> +    unsigned BitWidth = cast(Op0->getType())->getBitWidth();
>> +    APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
>> +    ComputeMaskedBits(Op0, APInt::getAllOnesValue(BitWidth),
>> +                      KnownZero, KnownOne, TD, 0);
>
> Surely you can specify ~CI->getValue() as the mask? Maybe this is the
> asymmetry that it sounds like Chris complained about.
>
>> +
>> +    // Are the bits being or'd in already known to be one?
>> +    if ((CI->getValue()&  KnownOne) == CI->getValue())
>> +      return Op0;
>> +
>> +    // Are all of the unknown bits being set to true by the or?
>> +    if ((KnownZero | KnownOne | CI->getValue()).isMaxValue())
>> +      return ConstantInt::get(Op0->getType(),
>> +                              (KnownOne | CI->getValue()));
>> +  }
>> +
>>     return 0;
>>   }
>
>
> Overall I think this is all reasonably clear.
>
> But, couldn't you easily extend it to cover the case where Op1 isn't a
> constant? Something like:
>
> // for AND
> ComputeMaskedBits(Op1, AllOnes, Op1KnownZero, Op1KnownOne);
> ComputeMaskedBits(Op0, ~Op1KnownZero, Op0KnownZero, Op0KnownOne);
>
> ResKnownZero = Op0KnownZero | Op1KnownZero;
> ResKnownOne = Op0KnownOne&  Op1KnownOne;
> if ((ResKnownZero | ResKnownOne).isMaxValue())
>    // All result bits known
>    return ConstantInt::get(Op0KnownOne&  Op1KnownOne);
>
> if ((Op0KnownZero | Op1KnownOne).isMaxValue())
>    // Op0 won't be changed by ANDing with Op1
>    return Op0;
>
> if ((Op0KnownOne | Op1KnownZero).isMaxValue())
>    // Op1 won't be changed by ANDing with Op0
>    return Op1;
>
> However, this duplicates some of the logic from ComputeMaskedBits()
> itself: the case where we return a constant here is exactly the case
> where, if we called ComputeMaskedBits on the result of the AND
> operation, it would tell us that all the bits are known. So why are we
> getting this duplication in the first place? Isn't there some common
> place where we can call ComputeMaskedBits on every expression, and if
> all the bits are known, replace the operation with a constant?

That's a great point.

We don't want to put ourselves in a situation where we do an iteration 
over every instruction calling a method that does a walk over all uses. 
For an n-instruction long chain of computation, that would give us 
O(n^2) time.

ComputeMaskedBits has a partner in crime, SimplifyDemandedBits which is 
used by the instruction combiner. SimplifyDemandedBits is similar to 
ComputeMaskedBits but also modifies a chain of computation that touches 
irrelevant (masked) bits. Its best trick is deleting irrelevant 
and/xor/or instructions. I suppose it could also try to replace a more 
complex instruction with a simpler one (add -> or) knowing that the bits 
which come out different are going to be ignored anyway.

This time, I left SimplifyDemandedBits alone, because for accuracy in 
ComputeMaskedBits the new mask is actually all-one bits, which is the 
most useless possible mask for SimplifyDemandedBits.

But perhaps I should revisit that and see if we can't come up with a way 
to calculate the "demanded" bits in an add, based on the known bits on 
the lhs and rhs and the mask of which bits of output are relevant.

Nick

From jay.foad at gmail.com  Thu Jul 21 04:19:11 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 09:19:11 -0000
Subject: [llvm-commits] [dragonegg] r135672 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110721091911.C971E2A6C12D@llvm.org>

Author: foad
Date: Thu Jul 21 04:19:11 2011
New Revision: 135672

URL: http://llvm.org/viewvc/llvm-project?rev=135672&view=rev
Log:
Update llvm-gcc-4.2 and dragonegg after converting ConstantFolder APIs
to use ArrayRef.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=135672&r1=135671&r2=135672&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Thu Jul 21 04:19:11 2011
@@ -1257,8 +1257,8 @@
   // Convert the pointer into an i8* and add the offset to it.
   Ptr = Folder.CreateBitCast(Ptr, GetUnitPointerType(Context));
   Constant *Result = POINTER_TYPE_OVERFLOW_UNDEFINED ?
-    Folder.CreateInBoundsGetElementPtr(Ptr, &Idx, 1) :
-    Folder.CreateGetElementPtr(Ptr, &Idx, 1);
+    Folder.CreateInBoundsGetElementPtr(Ptr, Idx) :
+    Folder.CreateGetElementPtr(Ptr, Idx);
 
   // The result may be of a different pointer type.
   Result = Folder.CreateBitCast(Result, getRegType(TREE_TYPE(exp)));
@@ -1418,8 +1418,8 @@
   ArrayAddr = Folder.CreateBitCast(ArrayAddr, EltTy->getPointerTo());
 
   return POINTER_TYPE_OVERFLOW_UNDEFINED ?
-    Folder.CreateInBoundsGetElementPtr(ArrayAddr, &IndexVal, 1) :
-    Folder.CreateGetElementPtr(ArrayAddr, &IndexVal, 1);
+    Folder.CreateInBoundsGetElementPtr(ArrayAddr, IndexVal) :
+    Folder.CreateGetElementPtr(ArrayAddr, IndexVal);
 }
 
 /// AddressOfCOMPONENT_REF - Return the address of a field in a record.
@@ -1456,7 +1456,7 @@
   Type *UnitPtrTy = GetUnitPointerType(Context);
   Constant *StructAddr = AddressOfImpl(TREE_OPERAND(exp, 0), Folder);
   Constant *FieldPtr = Folder.CreateBitCast(StructAddr, UnitPtrTy);
-  FieldPtr = Folder.CreateInBoundsGetElementPtr(FieldPtr, &Offset, 1);
+  FieldPtr = Folder.CreateInBoundsGetElementPtr(FieldPtr, Offset);
 
   return FieldPtr;
 }



From jay.foad at gmail.com  Thu Jul 21 04:19:11 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 09:19:11 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r135672 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20110721091911.D7F572A6C124@llvm.org>

Author: foad
Date: Thu Jul 21 04:19:11 2011
New Revision: 135672

URL: http://llvm.org/viewvc/llvm-project?rev=135672&view=rev
Log:
Update llvm-gcc-4.2 and dragonegg after converting ConstantFolder APIs
to use ArrayRef.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=135672&r1=135671&r2=135672&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jul 21 04:19:11 2011
@@ -8866,7 +8866,7 @@
     Idx.push_back(ConstantInt::get(IntPtrTy, 0));
   Idx.push_back(IndexVal);
 
-  return TheFolder->CreateGetElementPtr(ArrayAddr, &Idx[0], Idx.size());
+  return TheFolder->CreateGetElementPtr(ArrayAddr, Idx);
 }
 
 Constant *TreeConstantToLLVM::EmitLV_COMPONENT_REF(tree exp) {
@@ -8898,7 +8898,8 @@
       Constant::getNullValue(Type::getInt32Ty(Context)),
       ConstantInt::get(Type::getInt32Ty(Context), MemberIndex)
     };
-    FieldPtr = TheFolder->CreateGetElementPtr(StructAddrLV, Ops+1, 2);
+    FieldPtr = TheFolder->CreateGetElementPtr(StructAddrLV,
+                                              makeArrayRef(Ops + 1, 2));
 
     FieldPtr = ConstantFoldInstOperands(Instruction::GetElementPtr,
                                         FieldPtr->getType(), Ops, &TD);



From jay.foad at gmail.com  Thu Jul 21 04:19:11 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 09:19:11 -0000
Subject: [llvm-commits] [llvm] r135672 -
	/llvm/trunk/include/llvm/Support/TargetFolder.h
Message-ID: <20110721091911.E10D02A6C12E@llvm.org>

Author: foad
Date: Thu Jul 21 04:19:11 2011
New Revision: 135672

URL: http://llvm.org/viewvc/llvm-project?rev=135672&view=rev
Log:
Update llvm-gcc-4.2 and dragonegg after converting ConstantFolder APIs
to use ArrayRef.

Modified:
    llvm/trunk/include/llvm/Support/TargetFolder.h

Modified: llvm/trunk/include/llvm/Support/TargetFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetFolder.h?rev=135672&r1=135671&r2=135672&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetFolder.h (original)
+++ llvm/trunk/include/llvm/Support/TargetFolder.h Thu Jul 21 04:19:11 2011
@@ -152,6 +152,12 @@
     return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
                                                        IdxList.size()));
   }
+  Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *Idx) const {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, &Idx, 1));
+  }
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
     return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),



From anton at korobeynikov.info  Thu Jul 21 04:28:39 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Thu, 21 Jul 2011 13:28:39 +0400
Subject: [llvm-commits] [llvm] r135645 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
In-Reply-To: <20110721004456.EE90A2A6C12D@llvm.org>
References: <20110721004456.EE90A2A6C12D@llvm.org>
Message-ID: 

Hi Bill,

> - ? ? ? ? ? ? ? ?TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
> - ? ? ? ? ? ? ? ?StackPtr).addReg(StackPtr).addImm(-MaxAlign);
> + ? ? ? ? ? ? ? ?TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
> + ? ? ? ?.addReg(StackPtr)
> + ? ? ? ?.addImm(-MaxAlign)
> + ? ? ? ?.setMIFlag(MachineInstr::FrameSetup);
What do you think - maybe we'll introduce the BuildFrameSetupMI helper
method? Just to make sure we won't miss .setMIFlag calls in such
cases?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From jay.foad at gmail.com  Thu Jul 21 04:34:14 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 10:34:14 +0100
Subject: [llvm-commits] patch: go crazy,
	compute bits for an entire add instruction
In-Reply-To: <4E27ECC5.7080704@mxc.ca>
References: <4E14001E.1040801@mxc.ca>
	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>
	
	<4E1EAFF1.1050809@mxc.ca>
	
	<4E27DE08.2090308@mxc.ca>
	
	<4E27ECC5.7080704@mxc.ca>
Message-ID: 

> We don't want to put ourselves in a situation where we do an iteration over
> every instruction calling a method that does a walk over all uses. For an
> n-instruction long chain of computation, that would give us O(n^2) time.

It should be possible to fix the O(n^2) behaviour by memo-ising the
results of ComputeMaskedBits.

I don't have a high-level understanding of how all these bits of
analysis and simplification fit together, so I can't really offer any
constructive opinions.

> But perhaps I should revisit that and see if we can't come up with a way to
> calculate the "demanded" bits in an add, based on the known bits on the lhs
> and rhs and the mask of which bits of output are relevant.

Sounds like a fun bit twiddling problem! I've never thought about this
one so I don't have any ideas to offer.

Jay.

From jay.foad at gmail.com  Thu Jul 21 05:00:18 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 11:00:18 +0100
Subject: [llvm-commits] patch: go crazy,
	compute bits for an entire add instruction
In-Reply-To: <4E27DE08.2090308@mxc.ca>
References: <4E14001E.1040801@mxc.ca>
	<92A7EBDD-201D-47B1-8792-CB08DB9B9E40@apple.com>
	
	<4E1EAFF1.1050809@mxc.ca>
	
	<4E27DE08.2090308@mxc.ca>
Message-ID: 

On 21 July 2011 09:06, Nick Lewycky  wrote:
> Jay, would you be willing to review this updated patch, now for add+sub?

Now the add/sub bits. (As a unified diff fan I hate to say it, but I
think a context diff would be much easier to read for this bit!)

> Index: lib/Analysis/ValueTracking.cpp
> ===================================================================
> --- lib/Analysis/ValueTracking.cpp	(revision 135567)
> +++ lib/Analysis/ValueTracking.cpp	(working copy)
> @@ -377,86 +377,66 @@
>        return;
>      }
>      break;
> +  case Instruction::Add:  // fall-through
>    case Instruction::Sub: {
> -    if (ConstantInt *CLHS = dyn_cast(I->getOperand(0))) {
> -      // We know that the top bits of C-X are clear if X contains less bits
> -      // than C (i.e. no wrap-around can happen).  For example, 20-X is
> -      // positive if we can prove that X is >= 0 and < 16.
> -      if (!CLHS->getValue().isNegative()) {
> -        unsigned NLZ = (CLHS->getValue()+1).countLeadingZeros();
> -        // NLZ can't be BitWidth with no sign bit
> -        APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
> -        ComputeMaskedBits(I->getOperand(1), MaskV, KnownZero2, KnownOne2,
> -                          TD, Depth+1);
> -
> -        // If all of the MaskV bits are known to be zero, then we know the
> -        // output top bits are zero, because we now know that the output is
> -        // from [0-C].
> -        if ((KnownZero2 & MaskV) == MaskV) {
> -          unsigned NLZ2 = CLHS->getValue().countLeadingZeros();
> -          // Top bits known zero.
> -          KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask;
> -        }
> -      }
> -    }
> -  }
> -  // fall through
> -  case Instruction::Add: {
> -    // If one of the operands has trailing zeros, then the bits that the
> -    // other operand has in those bit positions will be preserved in the
> -    // result. For an add, this works with either operand. For a subtract,
> -    // this only works if the known zeros are in the right operand.
> +    APInt Mask2 = APInt::getAllOnesValue(BitWidth);
>      APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
> -    APInt Mask2 = APInt::getLowBitsSet(BitWidth,
> -                                       BitWidth - Mask.countLeadingZeros());
>      ComputeMaskedBits(I->getOperand(0), Mask2, LHSKnownZero, LHSKnownOne, TD,
>                        Depth+1);
> -    assert((LHSKnownZero & LHSKnownOne) == 0 &&
> -           "Bits known to be one AND zero?");
> -    unsigned LHSKnownZeroOut = LHSKnownZero.countTrailingOnes();
> +    if (LHSKnownZero.isMinValue() && LHSKnownOne.isMinValue())
> +      return;

If I ruled the world, ComputeMaskedBits(UndefValue) would return with
both KnownZero and KnownOne set to an all-ones value. But I don't, so
it probably doesn't.

>
> -    ComputeMaskedBits(I->getOperand(1), Mask2, KnownZero2, KnownOne2, TD,
> +    APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0);
> +    ComputeMaskedBits(I->getOperand(1), Mask2, RHSKnownZero, RHSKnownOne, TD,
>                        Depth+1);
> -    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
> -    unsigned RHSKnownZeroOut = KnownZero2.countTrailingOnes();
> +    if (RHSKnownZero.isMinValue() && RHSKnownOne.isMinValue())
> +      return;
>
> -    // Determine which operand has more trailing zeros, and use that
> -    // many bits from the other operand.
> -    if (LHSKnownZeroOut > RHSKnownZeroOut) {
> -      if (I->getOpcode() == Instruction::Add) {
> -        APInt Mask = APInt::getLowBitsSet(BitWidth, LHSKnownZeroOut);
> -        KnownZero |= KnownZero2 & Mask;
> -        KnownOne  |= KnownOne2 & Mask;
> -      } else {
> -        // If the known zeros are in the left operand for a subtract,
> -        // fall back to the minimum known zeros in both operands.
> -        KnownZero |= APInt::getLowBitsSet(BitWidth,
> -                                          std::min(LHSKnownZeroOut,
> -                                                   RHSKnownZeroOut));
> -      }
> -    } else if (RHSKnownZeroOut >= LHSKnownZeroOut) {
> -      APInt Mask = APInt::getLowBitsSet(BitWidth, RHSKnownZeroOut);
> -      KnownZero |= LHSKnownZero & Mask;
> -      KnownOne  |= LHSKnownOne & Mask;
> +    // Calculate the sum/difference as if the unknown bits were all zeros, and
> +    // another as if the unknown bits were all ones.
> +    APInt OpWithZeros;
> +    APInt OpWithOnes;
> +    if (I->getOpcode() == Instruction::Add) {
> +      OpWithZeros = LHSKnownOne + RHSKnownOne;
> +      OpWithOnes = ~LHSKnownZero + ~RHSKnownZero;
> +    } else {
> +      OpWithZeros = LHSKnownOne - RHSKnownOne;
> +      OpWithOnes = ~LHSKnownZero - ~RHSKnownZero;
>      }

I think this is wrong for subtract. An example with 2-bit values,
using x for unknown bits:

  LHS = 1x // i.e. 10 or 11, two or three
  RHS = 0x // i.e. 00 or 01, zero or one
  // therefore LHS - RHS is one, two or three

  your OpWithZeroes = 10
  your OpWithOnes = 10
  your CarryMask = 11

  you would conclude that the result is 1x, which is wrong

A better attempt would be:

  OpWithMinimalBorrows = ~LHSKnownZero - RHSKnownOne;
  OpWithMaximalBorrows = LHSKnownOne - ~RHSKnownZero;

... but I'd have to think about this some more to be 100% convinced
that it is correct.

(An alternative way of coding this is to write a general
SolveAdd(Value *LHS, Value *RHS, unsigned CarryIn), and then handle
ADD with SolveAdd(LHR, RHS, 0), and SUB with SolveAdd(LHS, ~RHS, 1).)

>
> +    // At a bit position where OpWithZeros and OpWithOne agree, the carry
> +    // value is the same regardless of the unknown bits.
> +    APInt CarryMask = ~(OpWithZeros ^ OpWithOnes);
> +
> +    // We can only know the result of the subtraction when we know the values
> +    // for the left, right and carry inputs.
> +    APInt KnownMask = (LHSKnownZero | LHSKnownOne) &
> +                      (RHSKnownZero | RHSKnownOne) &
> +                      CarryMask &
> +                      Mask;
> +
> +    // At this stage, for every bit position where KnownMask is true, exactly
> +    // one of either OpWithZeros or OpWithOnes is set.
> +    KnownZero = ~OpWithZeros & KnownMask;
> +    KnownOne = OpWithOnes & KnownMask;

The comment is wrong. For every bit position where KnownMask is 1,
OpWithZeros == OpWithOnes.

> +
>      // Are we still trying to solve for the sign bit?
> -    if (Mask.isNegative() && !KnownZero.isNegative() && !KnownOne.isNegative()){
> +    if (Mask.isNegative() && !KnownMask.isNegative()) {
>        OverflowingBinaryOperator *OBO = cast(I);
>        if (OBO->hasNoSignedWrap()) {
>          if (I->getOpcode() == Instruction::Add) {
>            // Adding two positive numbers can't wrap into negative
> -          if (LHSKnownZero.isNegative() && KnownZero2.isNegative())
> +          if (LHSKnownZero.isNegative() && RHSKnownZero.isNegative())
>              KnownZero |= APInt::getSignBit(BitWidth);
>            // and adding two negative numbers can't wrap into positive.
> -          else if (LHSKnownOne.isNegative() && KnownOne2.isNegative())
> +          else if (LHSKnownOne.isNegative() && RHSKnownOne.isNegative())
>              KnownOne |= APInt::getSignBit(BitWidth);
>          } else {
>            // Subtracting a negative number from a positive one can't wrap
> -          if (LHSKnownZero.isNegative() && KnownOne2.isNegative())
> +          if (LHSKnownZero.isNegative() && RHSKnownOne.isNegative())
>              KnownZero |= APInt::getSignBit(BitWidth);
>            // neither can subtracting a positive number from a negative one.
> -          else if (LHSKnownOne.isNegative() && KnownZero2.isNegative())
> +          else if (LHSKnownOne.isNegative() && RHSKnownZero.isNegative())
>              KnownOne |= APInt::getSignBit(BitWidth);
>          }
>        }

The rest looks good to me.

Jay.

From jay.foad at gmail.com  Thu Jul 21 09:31:17 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 14:31:17 -0000
Subject: [llvm-commits] [llvm] r135673 - in /llvm/trunk: docs/
 examples/BrainF/ include/llvm/ include/llvm/Support/ lib/Analysis/
 lib/AsmParser/ lib/Bitcode/Reader/ lib/Target/ARM/ lib/Transforms/IPO/
 lib/Transforms/Instrumentation/ lib/Transforms/Scalar/ lib/VMCore/
 tools/bugpoint/
Message-ID: <20110721143118.300382A6C12E@llvm.org>

Author: foad
Date: Thu Jul 21 09:31:17 2011
New Revision: 135673

URL: http://llvm.org/viewvc/llvm-project?rev=135673&view=rev
Log:
Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.

Modified:
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/examples/BrainF/BrainF.cpp
    llvm/trunk/include/llvm/Constants.h
    llvm/trunk/include/llvm/Support/ConstantFolder.h
    llvm/trunk/include/llvm/Support/NoFolder.h
    llvm/trunk/include/llvm/Support/TargetFolder.h
    llvm/trunk/lib/Analysis/ConstantFolding.cpp
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp
    llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
    llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/lib/VMCore/ConstantFold.cpp
    llvm/trunk/lib/VMCore/Constants.cpp
    llvm/trunk/lib/VMCore/Core.cpp
    llvm/trunk/tools/bugpoint/Miscompilation.cpp

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Thu Jul 21 09:31:17 2011
@@ -623,6 +623,8 @@
 
  • ComputeLinearIndex (in llvm/CodeGen/Analysis.h)
    • 
 
  • ConstantArray::get
    • 
 
  • ConstantExpr::getExtractElement
    • 
+
  • ConstantExpr::getGetElementPtr
    • 
+
  • ConstantExpr::getInBoundsGetElementPtr
    • 
 
  • ConstantExpr::getIndices
    • 
 
  • ConstantExpr::getInsertElement
    • 
 
  • ConstantExpr::getWithOperands
    • 

Modified: llvm/trunk/examples/BrainF/BrainF.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/BrainF/BrainF.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/examples/BrainF/BrainF.cpp (original)
+++ llvm/trunk/examples/BrainF/BrainF.cpp Thu Jul 21 09:31:17 2011
@@ -162,8 +162,7 @@
       };
 
       Constant *msgptr = ConstantExpr::
-        getGetElementPtr(aberrormsg, gep_params,
-                         array_lengthof(gep_params));
+        getGetElementPtr(aberrormsg, gep_params);
 
       Value *puts_params[] = {
         msgptr

Modified: llvm/trunk/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Constants.h (original)
+++ llvm/trunk/include/llvm/Constants.h Thu Jul 21 09:31:17 2011
@@ -788,25 +788,40 @@
   /// all elements must be Constant's.
   ///
   static Constant *getGetElementPtr(Constant *C,
-                                    Constant *const *IdxList, unsigned NumIdx,
+                                    ArrayRef IdxList,
                                     bool InBounds = false) {
-    return getGetElementPtr(C, (Value**)IdxList, NumIdx, InBounds);
+    return getGetElementPtr(C, makeArrayRef((Value * const *)IdxList.data(),
+                                            IdxList.size()),
+                            InBounds);
   }
   static Constant *getGetElementPtr(Constant *C,
-                                    Value *const *IdxList, unsigned NumIdx,
+                                    Constant *Idx,
+                                    bool InBounds = false) {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return getGetElementPtr(C, cast(Idx), InBounds);
+  }
+  static Constant *getGetElementPtr(Constant *C,
+                                    ArrayRef IdxList,
                                     bool InBounds = false);
 
   /// Create an "inbounds" getelementptr. See the documentation for the
   /// "inbounds" flag in LangRef.html for details.
   static Constant *getInBoundsGetElementPtr(Constant *C,
-                                            Constant *const *IdxList,
-                                            unsigned NumIdx) {
-    return getGetElementPtr(C, IdxList, NumIdx, true);
+                                            ArrayRef IdxList) {
+    return getGetElementPtr(C, IdxList, true);
+  }
+  static Constant *getInBoundsGetElementPtr(Constant *C,
+                                            Constant *Idx) {
+    // This form of the function only exists to avoid ambiguous overload
+    // warnings about whether to convert Idx to ArrayRef or
+    // ArrayRef.
+    return getGetElementPtr(C, Idx, true);
   }
   static Constant *getInBoundsGetElementPtr(Constant *C,
-                                            Value* const *IdxList,
-                                            unsigned NumIdx) {
-    return getGetElementPtr(C, IdxList, NumIdx, true);
+                                            ArrayRef IdxList) {
+    return getGetElementPtr(C, IdxList, true);
   }
 
   static Constant *getExtractElement(Constant *Vec, Constant *Idx);

Modified: llvm/trunk/include/llvm/Support/ConstantFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantFolder.h?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ConstantFolder.h (original)
+++ llvm/trunk/include/llvm/Support/ConstantFolder.h Thu Jul 21 09:31:17 2011
@@ -120,34 +120,32 @@
 
   Constant *CreateGetElementPtr(Constant *C,
                                 ArrayRef IdxList) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+    return ConstantExpr::getGetElementPtr(C, IdxList);
   }
   Constant *CreateGetElementPtr(Constant *C, Constant *Idx) const {
     // This form of the function only exists to avoid ambiguous overload
     // warnings about whether to convert Idx to ArrayRef or
     // ArrayRef.
-    return ConstantExpr::getGetElementPtr(C, &Idx, 1);
+    return ConstantExpr::getGetElementPtr(C, Idx);
   }
   Constant *CreateGetElementPtr(Constant *C,
                                 ArrayRef IdxList) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+    return ConstantExpr::getGetElementPtr(C, IdxList);
   }
 
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
-                                                  IdxList.size());
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList);
   }
   Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *Idx) const {
     // This form of the function only exists to avoid ambiguous overload
     // warnings about whether to convert Idx to ArrayRef or
     // ArrayRef.
-    return ConstantExpr::getInBoundsGetElementPtr(C, &Idx, 1);
+    return ConstantExpr::getInBoundsGetElementPtr(C, Idx);
   }
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
-                                                  IdxList.size());
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList);
   }
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/Support/NoFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/NoFolder.h?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/NoFolder.h (original)
+++ llvm/trunk/include/llvm/Support/NoFolder.h Thu Jul 21 09:31:17 2011
@@ -179,7 +179,7 @@
 
   Constant *CreateGetElementPtr(Constant *C,
                                 ArrayRef IdxList) const {
-    return ConstantExpr::getGetElementPtr(C, IdxList.data(), IdxList.size());
+    return ConstantExpr::getGetElementPtr(C, IdxList);
   }
   Instruction *CreateGetElementPtr(Constant *C,
                                    ArrayRef IdxList) const {
@@ -188,8 +188,7 @@
 
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
-    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
-                                                  IdxList.size());
+    return ConstantExpr::getInBoundsGetElementPtr(C, IdxList);
   }
   Instruction *CreateInBoundsGetElementPtr(Constant *C,
                                            ArrayRef IdxList) const {

Modified: llvm/trunk/include/llvm/Support/TargetFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetFolder.h?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetFolder.h (original)
+++ llvm/trunk/include/llvm/Support/TargetFolder.h Thu Jul 21 09:31:17 2011
@@ -132,36 +132,32 @@
 
   Constant *CreateGetElementPtr(Constant *C,
                                 ArrayRef IdxList) const {
-    return Fold(ConstantExpr::getGetElementPtr(C, IdxList.data(),
-                                               IdxList.size()));
+    return Fold(ConstantExpr::getGetElementPtr(C, IdxList));
   }
   Constant *CreateGetElementPtr(Constant *C, Constant *Idx) const {
     // This form of the function only exists to avoid ambiguous overload
     // warnings about whether to convert Idx to ArrayRef or
     // ArrayRef.
-    return Fold(ConstantExpr::getGetElementPtr(C, &Idx, 1));
+    return Fold(ConstantExpr::getGetElementPtr(C, Idx));
   }
   Constant *CreateGetElementPtr(Constant *C,
                                 ArrayRef IdxList) const {
-    return Fold(ConstantExpr::getGetElementPtr(C, IdxList.data(),
-                                               IdxList.size()));
+    return Fold(ConstantExpr::getGetElementPtr(C, IdxList));
   }
 
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
-    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
-                                                       IdxList.size()));
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList));
   }
   Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *Idx) const {
     // This form of the function only exists to avoid ambiguous overload
     // warnings about whether to convert Idx to ArrayRef or
     // ArrayRef.
-    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, &Idx, 1));
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, Idx));
   }
   Constant *CreateInBoundsGetElementPtr(Constant *C,
                                         ArrayRef IdxList) const {
-    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList.data(),
-                                                       IdxList.size()));
+    return Fold(ConstantExpr::getInBoundsGetElementPtr(C, IdxList));
   }
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jul 21 09:31:17 2011
@@ -562,7 +562,7 @@
   if (!Any) return 0;
 
   Constant *C =
-    ConstantExpr::getGetElementPtr(Ops[0], &NewIdxs[0], NewIdxs.size());
+    ConstantExpr::getGetElementPtr(Ops[0], NewIdxs);
   if (ConstantExpr *CE = dyn_cast(C))
     if (Constant *Folded = ConstantFoldConstantExpression(CE, TD))
       C = Folded;
@@ -702,7 +702,7 @@
 
   // Create a GEP.
   Constant *C =
-    ConstantExpr::getGetElementPtr(Ptr, &NewIdxs[0], NewIdxs.size());
+    ConstantExpr::getGetElementPtr(Ptr, NewIdxs);
   assert(cast(C->getType())->getElementType() == Ty &&
          "Computed GetElementPtr has unexpected type!");
 
@@ -889,8 +889,7 @@
     if (Constant *C = SymbolicallyEvaluateGEP(Ops, DestTy, TD))
       return C;
     
-    return ConstantExpr::getGetElementPtr(Ops[0], Ops.data() + 1,
-                                          Ops.size() - 1);
+    return ConstantExpr::getGetElementPtr(Ops[0], Ops.slice(1));
   }
 }
 

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jul 21 09:31:17 2011
@@ -2254,9 +2254,7 @@
     if (!isa(Ops[i]))
       return 0;
 
-  return ConstantExpr::getGetElementPtr(cast(Ops[0]),
-                                        (Constant *const*)Ops.data() + 1,
-                                        Ops.size() - 1);
+  return ConstantExpr::getGetElementPtr(cast(Ops[0]), Ops.slice(1));
 }
 
 /// SimplifyPHINode - See if we can fold the given phi.  If not, returns null.

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Thu Jul 21 09:31:17 2011
@@ -494,7 +494,7 @@
     // Fold a GEP with constant operands.
     if (Constant *CLHS = dyn_cast(V))
       if (Constant *CRHS = dyn_cast(Idx))
-        return ConstantExpr::getGetElementPtr(CLHS, &CRHS, 1);
+        return ConstantExpr::getGetElementPtr(CLHS, CRHS);
 
     // Do a quick scan to see if we have this GEP nearby.  If so, reuse it.
     unsigned ScanLimit = 6;

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Jul 21 09:31:17 2011
@@ -2273,16 +2273,14 @@
       if (Elts.size() == 0 || !Elts[0]->getType()->isPointerTy())
         return Error(ID.Loc, "getelementptr requires pointer operand");
 
+      ArrayRef Indices(Elts.begin() + 1, Elts.end());
       if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(),
                                              (Value**)(Elts.data() + 1),
                                              Elts.size() - 1))
         return Error(ID.Loc, "invalid indices for getelementptr");
       ID.ConstantVal = InBounds ?
-        ConstantExpr::getInBoundsGetElementPtr(Elts[0],
-                                               Elts.data() + 1,
-                                               Elts.size() - 1) :
-        ConstantExpr::getGetElementPtr(Elts[0],
-                                       Elts.data() + 1, Elts.size() - 1);
+        ConstantExpr::getInBoundsGetElementPtr(Elts[0], Indices) :
+        ConstantExpr::getGetElementPtr(Elts[0], Indices);
     } else if (Opc == Instruction::Select) {
       if (Elts.size() != 3)
         return Error(ID.Loc, "expected three operands to select");

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Jul 21 09:31:17 2011
@@ -1351,12 +1351,11 @@
         if (!ElTy) return Error("Invalid CE_GEP record");
         Elts.push_back(ValueList.getConstantFwdRef(Record[i+1], ElTy));
       }
+      ArrayRef Indices(Elts.begin() + 1, Elts.end());
       if (BitCode == bitc::CST_CODE_CE_INBOUNDS_GEP)
-        V = ConstantExpr::getInBoundsGetElementPtr(Elts[0], &Elts[1],
-                                                   Elts.size()-1);
+        V = ConstantExpr::getInBoundsGetElementPtr(Elts[0], Indices);
       else
-        V = ConstantExpr::getGetElementPtr(Elts[0], &Elts[1],
-                                           Elts.size()-1);
+        V = ConstantExpr::getGetElementPtr(Elts[0], Indices);
       break;
     }
     case bitc::CST_CODE_CE_SELECT:  // CE_SELECT: [opval#, opval#, opval#]

Modified: llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Thu Jul 21 09:31:17 2011
@@ -150,7 +150,7 @@
         ConstantInt::get(Int32Ty, 0),
         ConstantInt::get(Int32Ty, k-i)
       };
-      Constant *GEP = ConstantExpr::getInBoundsGetElementPtr(MergedGV, Idx, 2);
+      Constant *GEP = ConstantExpr::getInBoundsGetElementPtr(MergedGV, Idx);
       Globals[k]->replaceAllUsesWith(GEP);
       Globals[k]->eraseFromParent();
     }

Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Thu Jul 21 09:31:17 2011
@@ -596,8 +596,7 @@
         Idxs.push_back(NullInt);
         for (unsigned i = 3, e = CE->getNumOperands(); i != e; ++i)
           Idxs.push_back(CE->getOperand(i));
-        NewPtr = ConstantExpr::getGetElementPtr(cast(NewPtr),
-                                                &Idxs[0], Idxs.size());
+        NewPtr = ConstantExpr::getGetElementPtr(cast(NewPtr), Idxs);
       } else {
         GetElementPtrInst *GEPI = cast(GEP);
         SmallVector Idxs;
@@ -753,8 +752,7 @@
           break;
       if (Idxs.size() == GEPI->getNumOperands()-1)
         Changed |= OptimizeAwayTrappingUsesOfValue(GEPI,
-                          ConstantExpr::getGetElementPtr(NewV, &Idxs[0],
-                                                        Idxs.size()));
+                          ConstantExpr::getGetElementPtr(NewV, Idxs));
       if (GEPI->use_empty()) {
         Changed = true;
         GEPI->eraseFromParent();
@@ -2410,8 +2408,8 @@
            i != e; ++i)
         GEPOps.push_back(getVal(Values, *i));
       InstResult = cast(GEP)->isInBounds() ?
-          ConstantExpr::getInBoundsGetElementPtr(P, &GEPOps[0], GEPOps.size()) :
-          ConstantExpr::getGetElementPtr(P, &GEPOps[0], GEPOps.size());
+          ConstantExpr::getInBoundsGetElementPtr(P, GEPOps) :
+          ConstantExpr::getGetElementPtr(P, GEPOps);
     } else if (LoadInst *LI = dyn_cast(CurInst)) {
       if (LI->isVolatile()) return false;  // no volatile accesses.
       InstResult = ComputeLoadResult(getVal(Values, LI->getOperand(0)),

Modified: llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp Thu Jul 21 09:31:17 2011
@@ -51,8 +51,7 @@
                              Constant::getNullValue(Type::getInt32Ty(Context)));
   unsigned NumElements = 0;
   if (Array) {
-    Args[2] = ConstantExpr::getGetElementPtr(Array, &GEPIndices[0],
-                                             GEPIndices.size());
+    Args[2] = ConstantExpr::getGetElementPtr(Array, GEPIndices);
     NumElements =
       cast(Array->getType()->getElementType())->getNumElements();
   } else {
@@ -120,7 +119,7 @@
   Indices[0] = Constant::getNullValue(Type::getInt32Ty(Context));
   Indices[1] = ConstantInt::get(Type::getInt32Ty(Context), CounterNum);
   Constant *ElementPtr =
-    ConstantExpr::getGetElementPtr(CounterArray, &Indices[0], Indices.size());
+    ConstantExpr::getGetElementPtr(CounterArray, Indices);
 
   // Load, increment and store the value back.
   Value *OldVal = new LoadInst(ElementPtr, "OldFuncCounter", InsertPos);

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Jul 21 09:31:17 2011
@@ -920,7 +920,7 @@
                                  llvm::Type::getInt8PtrTy(Src->getContext()));
   Constant *OffsetCst = 
     ConstantInt::get(Type::getInt64Ty(Src->getContext()), (unsigned)Offset);
-  Src = ConstantExpr::getGetElementPtr(Src, &OffsetCst, 1);
+  Src = ConstantExpr::getGetElementPtr(Src, OffsetCst);
   Src = ConstantExpr::getBitCast(Src, PointerType::getUnqual(LoadTy));
   if (ConstantFoldLoadFromConstPtr(Src, &TD))
     return Offset;
@@ -1081,7 +1081,7 @@
                                  llvm::Type::getInt8PtrTy(Src->getContext()));
   Constant *OffsetCst = 
   ConstantInt::get(Type::getInt64Ty(Src->getContext()), (unsigned)Offset);
-  Src = ConstantExpr::getGetElementPtr(Src, &OffsetCst, 1);
+  Src = ConstantExpr::getGetElementPtr(Src, OffsetCst);
   Src = ConstantExpr::getBitCast(Src, PointerType::getUnqual(LoadTy));
   return ConstantFoldLoadFromConstPtr(Src, &TD);
 }

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Thu Jul 21 09:31:17 2011
@@ -1180,8 +1180,8 @@
   }
 
   Constant *Ptr = Operands[0];
-  markConstant(&I, ConstantExpr::getGetElementPtr(Ptr, &Operands[0]+1,
-                                                  Operands.size()-1));
+  ArrayRef Indices(Operands.begin() + 1, Operands.end());
+  markConstant(&I, ConstantExpr::getGetElementPtr(Ptr, Indices));
 }
 
 void SCCPSolver::visitStoreInst(StoreInst &SI) {

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jul 21 09:31:17 2011
@@ -127,8 +127,7 @@
 
         if (ElTy == DPTy->getElementType())
           // This GEP is inbounds because all indices are zero.
-          return ConstantExpr::getInBoundsGetElementPtr(V, &IdxList[0],
-                                                        IdxList.size());
+          return ConstantExpr::getInBoundsGetElementPtr(V, IdxList);
       }
 
   // Handle casts from one vector constant to another.  We know that the src 
@@ -2146,9 +2145,9 @@
 /// isInBoundsIndices - Test whether the given sequence of *normalized* indices
 /// is "inbounds".
 template
-static bool isInBoundsIndices(IndexTy const *Idxs, size_t NumIdx) {
+static bool isInBoundsIndices(ArrayRef Idxs) {
   // No indices means nothing that could be out of bounds.
-  if (NumIdx == 0) return true;
+  if (Idxs.empty()) return true;
 
   // If the first index is zero, it's in bounds.
   if (cast(Idxs[0])->isNullValue()) return true;
@@ -2157,7 +2156,7 @@
   // by the one-past-the-end rule.
   if (!cast(Idxs[0])->isOne())
     return false;
-  for (unsigned i = 1, e = NumIdx; i != e; ++i)
+  for (unsigned i = 1, e = Idxs.size(); i != e; ++i)
     if (!cast(Idxs[i])->isNullValue())
       return false;
   return true;
@@ -2234,11 +2233,8 @@
         NewIndices.append(Idxs.begin() + 1, Idxs.end());
         return (inBounds && cast(CE)->isInBounds()) ?
           ConstantExpr::getInBoundsGetElementPtr(CE->getOperand(0),
-                                                 &NewIndices[0],
-                                                 NewIndices.size()) :
-          ConstantExpr::getGetElementPtr(CE->getOperand(0),
-                                         &NewIndices[0],
-                                         NewIndices.size());
+                                                 NewIndices) :
+          ConstantExpr::getGetElementPtr(CE->getOperand(0), NewIndices);
       }
     }
 
@@ -2256,9 +2252,9 @@
             if (CAT->getElementType() == SAT->getElementType())
               return inBounds ?
                 ConstantExpr::getInBoundsGetElementPtr(
-                      (Constant*)CE->getOperand(0), Idxs.data(), Idxs.size()) :
+                      (Constant*)CE->getOperand(0), Idxs) :
                 ConstantExpr::getGetElementPtr(
-                      (Constant*)CE->getOperand(0), Idxs.data(), Idxs.size());
+                      (Constant*)CE->getOperand(0), Idxs);
     }
   }
 
@@ -2314,16 +2310,15 @@
     for (unsigned i = 0, e = Idxs.size(); i != e; ++i)
       if (!NewIdxs[i]) NewIdxs[i] = cast(Idxs[i]);
     return inBounds ?
-      ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs.data(),
-                                             NewIdxs.size()) :
-      ConstantExpr::getGetElementPtr(C, NewIdxs.data(), NewIdxs.size());
+      ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs) :
+      ConstantExpr::getGetElementPtr(C, NewIdxs);
   }
 
   // If all indices are known integers and normalized, we can do a simple
   // check for the "inbounds" property.
   if (!Unknown && !inBounds &&
-      isa(C) && isInBoundsIndices(Idxs.data(), Idxs.size()))
-    return ConstantExpr::getInBoundsGetElementPtr(C, Idxs.data(), Idxs.size());
+      isa(C) && isInBoundsIndices(Idxs))
+    return ConstantExpr::getInBoundsGetElementPtr(C, Idxs);
 
   return 0;
 }

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Thu Jul 21 09:31:17 2011
@@ -840,12 +840,12 @@
       Ops[i-1] = getOperand(i);
     if (OpNo == 0)
       return cast(this)->isInBounds() ?
-        ConstantExpr::getInBoundsGetElementPtr(Op, &Ops[0], Ops.size()) :
-        ConstantExpr::getGetElementPtr(Op, &Ops[0], Ops.size());
+        ConstantExpr::getInBoundsGetElementPtr(Op, Ops) :
+        ConstantExpr::getGetElementPtr(Op, Ops);
     Ops[OpNo-1] = Op;
     return cast(this)->isInBounds() ?
-      ConstantExpr::getInBoundsGetElementPtr(getOperand(0), &Ops[0],Ops.size()):
-      ConstantExpr::getGetElementPtr(getOperand(0), &Ops[0], Ops.size());
+      ConstantExpr::getInBoundsGetElementPtr(getOperand(0), Ops) :
+      ConstantExpr::getGetElementPtr(getOperand(0), Ops);
   }
   default:
     assert(getNumOperands() == 2 && "Must be binary operator?");
@@ -892,8 +892,8 @@
     return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
   case Instruction::GetElementPtr:
     return cast(this)->isInBounds() ?
-      ConstantExpr::getInBoundsGetElementPtr(Ops[0], &Ops[1], Ops.size()-1) :
-      ConstantExpr::getGetElementPtr(Ops[0], &Ops[1], Ops.size()-1);
+      ConstantExpr::getInBoundsGetElementPtr(Ops[0], Ops.slice(1)) :
+      ConstantExpr::getGetElementPtr(Ops[0], Ops.slice(1));
   case Instruction::ICmp:
   case Instruction::FCmp:
     return ConstantExpr::getCompare(getPredicate(), Ops[0], Ops[1]);
@@ -1518,7 +1518,7 @@
   // Note that a non-inbounds gep is used, as null isn't within any object.
   Constant *GEPIdx = ConstantInt::get(Type::getInt32Ty(Ty->getContext()), 1);
   Constant *GEP = getGetElementPtr(
-                 Constant::getNullValue(PointerType::getUnqual(Ty)), &GEPIdx, 1);
+                 Constant::getNullValue(PointerType::getUnqual(Ty)), GEPIdx);
   return getPtrToInt(GEP, 
                      Type::getInt64Ty(Ty->getContext()));
 }
@@ -1532,7 +1532,7 @@
   Constant *Zero = ConstantInt::get(Type::getInt64Ty(Ty->getContext()), 0);
   Constant *One = ConstantInt::get(Type::getInt32Ty(Ty->getContext()), 1);
   Constant *Indices[2] = { Zero, One };
-  Constant *GEP = getGetElementPtr(NullPtr, Indices, 2);
+  Constant *GEP = getGetElementPtr(NullPtr, Indices);
   return getPtrToInt(GEP,
                      Type::getInt64Ty(Ty->getContext()));
 }
@@ -1550,7 +1550,7 @@
     FieldNo
   };
   Constant *GEP = getGetElementPtr(
-                Constant::getNullValue(PointerType::getUnqual(Ty)), GEPIdx, 2);
+                Constant::getNullValue(PointerType::getUnqual(Ty)), GEPIdx);
   return getPtrToInt(GEP,
                      Type::getInt64Ty(Ty->getContext()));
 }
@@ -1592,15 +1592,14 @@
   return pImpl->ExprConstants.getOrCreate(V1->getType(), Key);
 }
 
-Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs,
-                                         unsigned NumIdx, bool InBounds) {
-  if (Constant *FC = ConstantFoldGetElementPtr(C, InBounds,
-                                               makeArrayRef(Idxs, NumIdx)))
+Constant *ConstantExpr::getGetElementPtr(Constant *C, ArrayRef Idxs,
+                                         bool InBounds) {
+  if (Constant *FC = ConstantFoldGetElementPtr(C, InBounds, Idxs))
     return FC;          // Fold a few common cases.
 
   // Get the result type of the getelementptr!
-  Type *Ty = 
-    GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx);
+  Type *Ty =
+    GetElementPtrInst::getIndexedType(C->getType(), Idxs.begin(), Idxs.end());
   assert(Ty && "GEP indices invalid!");
   unsigned AS = cast(C->getType())->getAddressSpace();
   Type *ReqTy = Ty->getPointerTo(AS);
@@ -1609,9 +1608,9 @@
          "Non-pointer type for constant GetElementPtr expression");
   // Look up the constant in the table first to ensure uniqueness
   std::vector ArgVec;
-  ArgVec.reserve(NumIdx+1);
+  ArgVec.reserve(1 + Idxs.size());
   ArgVec.push_back(C);
-  for (unsigned i = 0; i != NumIdx; ++i)
+  for (unsigned i = 0, e = Idxs.size(); i != e; ++i)
     ArgVec.push_back(cast(Idxs[i]));
   const ExprMapKeyType Key(Instruction::GetElementPtr, ArgVec, 0,
                            InBounds ? GEPOperator::IsInBounds : 0);
@@ -2092,8 +2091,7 @@
       if (Val == From) Val = To;
       Indices.push_back(Val);
     }
-    Replacement = ConstantExpr::getGetElementPtr(Pointer,
-                                                 &Indices[0], Indices.size(),
+    Replacement = ConstantExpr::getGetElementPtr(Pointer, Indices,
                                          cast(this)->isInBounds());
   } else if (getOpcode() == Instruction::ExtractValue) {
     Constant *Agg = getOperand(0);

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Thu Jul 21 09:31:17 2011
@@ -792,18 +792,19 @@
 
 LLVMValueRef LLVMConstGEP(LLVMValueRef ConstantVal,
                           LLVMValueRef *ConstantIndices, unsigned NumIndices) {
+  ArrayRef IdxList(unwrap(ConstantIndices, NumIndices),
+                               NumIndices);
   return wrap(ConstantExpr::getGetElementPtr(unwrap(ConstantVal),
-                                             unwrap(ConstantIndices, 
-                                                              NumIndices),
-                                             NumIndices));
+                                             IdxList));
 }
 
 LLVMValueRef LLVMConstInBoundsGEP(LLVMValueRef ConstantVal,
                                   LLVMValueRef *ConstantIndices,
                                   unsigned NumIndices) {
   Constant* Val = unwrap(ConstantVal);
-  Constant** Idxs = unwrap(ConstantIndices, NumIndices);
-  return wrap(ConstantExpr::getInBoundsGetElementPtr(Val, Idxs, NumIndices));
+  ArrayRef IdxList(unwrap(ConstantIndices, NumIndices),
+                               NumIndices);
+  return wrap(ConstantExpr::getInBoundsGetElementPtr(Val, IdxList));
 }
 
 LLVMValueRef LLVMConstTrunc(LLVMValueRef ConstantVal, LLVMTypeRef ToType) {

Modified: llvm/trunk/tools/bugpoint/Miscompilation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/Miscompilation.cpp?rev=135673&r1=135672&r2=135673&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/Miscompilation.cpp (original)
+++ llvm/trunk/tools/bugpoint/Miscompilation.cpp Thu Jul 21 09:31:17 2011
@@ -834,8 +834,7 @@
         // GetElementPtr *funcName, ulong 0, ulong 0
         std::vector GEPargs(2,
                      Constant::getNullValue(Type::getInt32Ty(F->getContext())));
-        Value *GEP =
-                ConstantExpr::getGetElementPtr(funcName, &GEPargs[0], 2);
+        Value *GEP = ConstantExpr::getGetElementPtr(funcName, GEPargs);
         std::vector ResolverArgs;
         ResolverArgs.push_back(GEP);
 



From jay.foad at gmail.com  Thu Jul 21 09:42:51 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 14:42:51 -0000
Subject: [llvm-commits] [llvm] r135674 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110721144251.603962A6C12D@llvm.org>

Author: foad
Date: Thu Jul 21 09:42:51 2011
New Revision: 135674

URL: http://llvm.org/viewvc/llvm-project?rev=135674&view=rev
Log:
Sort case-insensitively.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135674&r1=135673&r2=135674&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Thu Jul 21 09:42:51 2011
@@ -639,13 +639,13 @@
 
  • FindInsertedValue (in llvm/Analysis/ValueTracking.h)
    • 
 
  • gep_type_begin (in llvm/Support/GetElementPtrTypeIterator.h)
    • 
 
  • gep_type_end (in llvm/Support/GetElementPtrTypeIterator.h)
    • 
+
  • InsertValueInst::Create
    • 
+
  • InsertValueInst::getIndices
    • 
+
  • InvokeInst::Create
    • 
 
  • IRBuilder::CreateCall
    • 
 
  • IRBuilder::CreateExtractValue
    • 
 
  • IRBuilder::CreateInsertValue
    • 
 
  • IRBuilder::CreateInvoke
    • 
-
  • InsertValueInst::Create
    • 
-
  • InsertValueInst::getIndices
    • 
-
  • InvokeInst::Create
    • 
 
  • MDNode::get
    • 
 
  • MDNode::getIfExists
    • 
 
  • MDNode::getTemporary
    • 



From jay.foad at gmail.com  Thu Jul 21 10:15:37 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 21 Jul 2011 15:15:37 -0000
Subject: [llvm-commits] [llvm] r135676 - in /llvm/trunk/lib:
 AsmParser/LLParser.cpp Bitcode/Reader/BitcodeReader.cpp
 Transforms/IPO/GlobalOpt.cpp VMCore/ConstantFold.cpp VMCore/Constants.cpp
Message-ID: <20110721151537.9B6CE2A6C12D@llvm.org>

Author: foad
Date: Thu Jul 21 10:15:37 2011
New Revision: 135676

URL: http://llvm.org/viewvc/llvm-project?rev=135676&view=rev
Log:
Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.

Modified:
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
    llvm/trunk/lib/VMCore/ConstantFold.cpp
    llvm/trunk/lib/VMCore/Constants.cpp

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=135676&r1=135675&r2=135676&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Jul 21 10:15:37 2011
@@ -2278,9 +2278,8 @@
                                              (Value**)(Elts.data() + 1),
                                              Elts.size() - 1))
         return Error(ID.Loc, "invalid indices for getelementptr");
-      ID.ConstantVal = InBounds ?
-        ConstantExpr::getInBoundsGetElementPtr(Elts[0], Indices) :
-        ConstantExpr::getGetElementPtr(Elts[0], Indices);
+      ID.ConstantVal = ConstantExpr::getGetElementPtr(Elts[0], Indices,
+                                                      InBounds);
     } else if (Opc == Instruction::Select) {
       if (Elts.size() != 3)
         return Error(ID.Loc, "expected three operands to select");

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=135676&r1=135675&r2=135676&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Jul 21 10:15:37 2011
@@ -1352,10 +1352,9 @@
         Elts.push_back(ValueList.getConstantFwdRef(Record[i+1], ElTy));
       }
       ArrayRef Indices(Elts.begin() + 1, Elts.end());
-      if (BitCode == bitc::CST_CODE_CE_INBOUNDS_GEP)
-        V = ConstantExpr::getInBoundsGetElementPtr(Elts[0], Indices);
-      else
-        V = ConstantExpr::getGetElementPtr(Elts[0], Indices);
+      V = ConstantExpr::getGetElementPtr(Elts[0], Indices,
+                                         BitCode ==
+                                           bitc::CST_CODE_CE_INBOUNDS_GEP);
       break;
     }
     case bitc::CST_CODE_CE_SELECT:  // CE_SELECT: [opval#, opval#, opval#]

Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=135676&r1=135675&r2=135676&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Thu Jul 21 10:15:37 2011
@@ -2407,9 +2407,9 @@
       for (User::op_iterator i = GEP->op_begin() + 1, e = GEP->op_end();
            i != e; ++i)
         GEPOps.push_back(getVal(Values, *i));
-      InstResult = cast(GEP)->isInBounds() ?
-          ConstantExpr::getInBoundsGetElementPtr(P, GEPOps) :
-          ConstantExpr::getGetElementPtr(P, GEPOps);
+      InstResult =
+        ConstantExpr::getGetElementPtr(P, GEPOps,
+                                       cast(GEP)->isInBounds());
     } else if (LoadInst *LI = dyn_cast(CurInst)) {
       if (LI->isVolatile()) return false;  // no volatile accesses.
       InstResult = ComputeLoadResult(getVal(Values, LI->getOperand(0)),

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=135676&r1=135675&r2=135676&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jul 21 10:15:37 2011
@@ -2231,10 +2231,10 @@
 
         NewIndices.push_back(Combined);
         NewIndices.append(Idxs.begin() + 1, Idxs.end());
-        return (inBounds && cast(CE)->isInBounds()) ?
-          ConstantExpr::getInBoundsGetElementPtr(CE->getOperand(0),
-                                                 NewIndices) :
-          ConstantExpr::getGetElementPtr(CE->getOperand(0), NewIndices);
+        return
+          ConstantExpr::getGetElementPtr(CE->getOperand(0), NewIndices,
+                                         inBounds &&
+                                           cast(CE)->isInBounds());
       }
     }
 
@@ -2250,11 +2250,9 @@
           if (ArrayType *CAT =
         dyn_cast(cast(C->getType())->getElementType()))
             if (CAT->getElementType() == SAT->getElementType())
-              return inBounds ?
-                ConstantExpr::getInBoundsGetElementPtr(
-                      (Constant*)CE->getOperand(0), Idxs) :
-                ConstantExpr::getGetElementPtr(
-                      (Constant*)CE->getOperand(0), Idxs);
+              return
+                ConstantExpr::getGetElementPtr((Constant*)CE->getOperand(0),
+                                               Idxs, inBounds);
     }
   }
 
@@ -2309,9 +2307,7 @@
   if (!NewIdxs.empty()) {
     for (unsigned i = 0, e = Idxs.size(); i != e; ++i)
       if (!NewIdxs[i]) NewIdxs[i] = cast(Idxs[i]);
-    return inBounds ?
-      ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs) :
-      ConstantExpr::getGetElementPtr(C, NewIdxs);
+    return ConstantExpr::getGetElementPtr(C, NewIdxs, inBounds);
   }
 
   // If all indices are known integers and normalized, we can do a simple

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=135676&r1=135675&r2=135676&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Thu Jul 21 10:15:37 2011
@@ -839,13 +839,13 @@
     for (unsigned i = 1, e = getNumOperands(); i != e; ++i)
       Ops[i-1] = getOperand(i);
     if (OpNo == 0)
-      return cast(this)->isInBounds() ?
-        ConstantExpr::getInBoundsGetElementPtr(Op, Ops) :
-        ConstantExpr::getGetElementPtr(Op, Ops);
+      return
+        ConstantExpr::getGetElementPtr(Op, Ops,
+                                       cast(this)->isInBounds());
     Ops[OpNo-1] = Op;
-    return cast(this)->isInBounds() ?
-      ConstantExpr::getInBoundsGetElementPtr(getOperand(0), Ops) :
-      ConstantExpr::getGetElementPtr(getOperand(0), Ops);
+    return
+      ConstantExpr::getGetElementPtr(getOperand(0), Ops,
+                                     cast(this)->isInBounds());
   }
   default:
     assert(getNumOperands() == 2 && "Must be binary operator?");
@@ -891,9 +891,9 @@
   case Instruction::ShuffleVector:
     return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
   case Instruction::GetElementPtr:
-    return cast(this)->isInBounds() ?
-      ConstantExpr::getInBoundsGetElementPtr(Ops[0], Ops.slice(1)) :
-      ConstantExpr::getGetElementPtr(Ops[0], Ops.slice(1));
+    return
+      ConstantExpr::getGetElementPtr(Ops[0], Ops.slice(1),
+                                     cast(this)->isInBounds());
   case Instruction::ICmp:
   case Instruction::FCmp:
     return ConstantExpr::getCompare(getPredicate(), Ops[0], Ops[1]);



From bruno.cardoso at gmail.com  Thu Jul 21 11:28:51 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 16:28:51 -0000
Subject: [llvm-commits] [llvm] r135678 - in /llvm/trunk: CMakeLists.txt
 autoconf/configure.ac configure lib/Target/Mips/CMakeLists.txt
 lib/Target/Mips/Mips.h lib/Target/Mips/MipsCodeEmitter.cpp
 lib/Target/Mips/MipsJITInfo.cpp lib/Target/Mips/MipsJITInfo.h
 lib/Target/Mips/MipsRelocations.h lib/Target/Mips/MipsTargetMachine.cpp
 lib/Target/Mips/MipsTargetMachine.h
 lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
Message-ID: <20110721162851.AF03C2A6C12D@llvm.org>

Author: bruno
Date: Thu Jul 21 11:28:51 2011
New Revision: 135678

URL: http://llvm.org/viewvc/llvm-project?rev=135678&view=rev
Log:
Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

Added:
    llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
    llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsJITInfo.h
    llvm/trunk/lib/Target/Mips/MipsRelocations.h
Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure
    llvm/trunk/lib/Target/Mips/CMakeLists.txt
    llvm/trunk/lib/Target/Mips/Mips.h
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Jul 21 11:28:51 2011
@@ -82,7 +82,7 @@
   )
 
 # List of targets with JIT support:
-set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM)
+set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM Mips)
 
 if( MSVC )
   set(LLVM_TARGETS_TO_BUILD X86

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Thu Jul 21 11:28:51 2011
@@ -484,7 +484,7 @@
     x86_64)      AC_SUBST(TARGET_HAS_JIT,1) ;;
     Alpha)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     ARM)         AC_SUBST(TARGET_HAS_JIT,1) ;;
-    Mips)        AC_SUBST(TARGET_HAS_JIT,0) ;;
+    Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
     SystemZ)     AC_SUBST(TARGET_HAS_JIT,0) ;;

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Thu Jul 21 11:28:51 2011
@@ -4865,7 +4865,7 @@
  ;;
     ARM)         TARGET_HAS_JIT=1
  ;;
-    Mips)        TARGET_HAS_JIT=0
+    Mips)        TARGET_HAS_JIT=1
  ;;
     XCore)       TARGET_HAS_JIT=0
  ;;

Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jul 21 11:28:51 2011
@@ -9,6 +9,7 @@
 
 add_llvm_target(MipsCodeGen
   MipsAsmPrinter.cpp
+  MipsCodeEmitter.cpp
   MipsDelaySlotFiller.cpp
   MipsEmitGPRestore.cpp
   MipsExpandPseudo.cpp

Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Thu Jul 21 11:28:51 2011
@@ -29,6 +29,9 @@
   FunctionPass *createMipsExpandPseudoPass(MipsTargetMachine &TM);
   FunctionPass *createMipsEmitGPRestorePass(MipsTargetMachine &TM);
 
+  FunctionPass *createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
+                                             JITCodeEmitter &JCE);
+
 } // end namespace llvm;
 
 #endif

Added: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=135678&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (added)
+++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Thu Jul 21 11:28:51 2011
@@ -0,0 +1,193 @@
+//===-- Mips/MipsCodeEmitter.cpp - Convert Mips code to machine code -----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+//
+// This file contains the pass that transforms the Mips machine instructions
+// into relocatable machine code.
+//
+//===---------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "jit"
+#include "Mips.h"
+#include "MipsInstrInfo.h"
+#include "MipsRelocations.h"
+#include "MipsSubtarget.h"
+#include "MipsTargetMachine.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/PassManager.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#ifndef NDEBUG
+#include 
+#endif
+
+#include "llvm/CodeGen/MachineOperand.h"
+
+using namespace llvm;
+
+namespace {
+
+class MipsCodeEmitter : public MachineFunctionPass {
+  MipsJITInfo *JTI;
+  const MipsInstrInfo *II;
+  const TargetData *TD;
+  const MipsSubtarget *Subtarget;
+  TargetMachine &TM;
+  JITCodeEmitter &MCE;
+  const std::vector *MCPEs;
+  const std::vector *MJTEs;
+  bool IsPIC;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const {
+    AU.addRequired ();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  static char ID;
+
+  public:
+    MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) :
+      MachineFunctionPass(ID), JTI(0),
+        II((const MipsInstrInfo *) tm.getInstrInfo()),
+        TD(tm.getTargetData()), TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
+        IsPIC(TM.getRelocationModel() == Reloc::PIC_) {
+    }
+
+    bool runOnMachineFunction(MachineFunction &MF);
+
+    virtual const char *getPassName() const {
+      return "Mips Machine Code Emitter";
+    }
+
+    void emitInstruction(const MachineInstr &MI);
+
+    unsigned getOperandValue(const MachineOperand &MO,
+        unsigned relocType = -1);
+
+    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
+        bool MayNeedFarStub = true);
+
+    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
+        intptr_t JTBase = 0);
+
+    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
+    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
+    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
+};
+}
+
+void MipsCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
+    bool mayNeedFarStub) {
+  MachineRelocation MR = MachineRelocation::getGV(MCE.getCurrentPCOffset(),
+                  Reloc, const_cast (GV), 0, mayNeedFarStub);
+  MCE.addRelocation(MR);
+}
+
+/// emitMachineBasicBlock - Emit the specified address basic block.
+void MipsCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
+    unsigned Reloc, intptr_t JTBase) {
+  MCE.addRelocation(
+      MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, BB, JTBase));
+}
+
+void MipsCodeEmitter::emitExternalSymbolAddress(const char *ES,
+    unsigned Reloc) {
+  MCE.addRelocation(
+      MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES, 0, 0,
+          false));
+}
+
+void MipsCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc)
+    const {
+  MCE.addRelocation(
+      MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTIndex,
+          0, false));
+}
+
+void MipsCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
+  MCE.addRelocation(
+      MachineRelocation::getConstPool
+        (MCE.getCurrentPCOffset(), Reloc, CPI, 0));
+}
+
+/// createMipsJITCodeEmitterPass - Return a pass that emits the collected Mips
+/// code to the specified MCE object.
+FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
+    JITCodeEmitter &JCE) {
+  return new MipsCodeEmitter(TM, JCE);
+}
+
+char MipsCodeEmitter::ID = 10;
+
+bool MipsCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+  JTI = ((MipsTargetMachine&) MF.getTarget()).getJITInfo();
+  II = ((const MipsTargetMachine&) MF.getTarget()).getInstrInfo();
+  TD = ((const MipsTargetMachine&) MF.getTarget()).getTargetData();
+  Subtarget = &TM.getSubtarget ();
+  MCPEs = &MF.getConstantPool()->getConstants();
+  MJTEs = 0;
+  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
+  JTI->Initialize(MF, IsPIC);
+  MCE.setModuleInfo(&getAnalysis ());
+
+  do {
+    DEBUG(errs() << "JITTing function '"
+        << MF.getFunction()->getName() << "'\n");
+    MCE.startFunction(MF);
+
+    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
+        MBB != E; ++MBB){
+      MCE.StartMachineBasicBlock(MBB);
+      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
+          I != E; ++I)
+        emitInstruction(*I);
+    }
+  } while (MCE.finishFunction(MF));
+
+  return false;
+}
+
+void MipsCodeEmitter::emitInstruction(const MachineInstr &MI) {}
+
+unsigned MipsCodeEmitter::getOperandValue(const MachineOperand &MO,
+    unsigned relocType) {
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate:
+    return MO.getImm();
+  case MachineOperand::MO_GlobalAddress:
+    emitGlobalAddress(MO.getGlobal(), relocType, false);
+    return 0;
+  case MachineOperand::MO_ExternalSymbol:
+    emitExternalSymbolAddress(MO.getSymbolName(), relocType);
+    return 0;
+  case MachineOperand::MO_MachineBasicBlock:
+    emitMachineBasicBlock(MO.getMBB(), relocType, MCE.getCurrentPCValue());
+    return 0;
+  case MachineOperand::MO_Register:
+    return MipsRegisterInfo::getRegisterNumbering(MO.getReg());
+  case MachineOperand::MO_JumpTableIndex:
+    emitJumpTableAddress(MO.getIndex(), relocType);
+    return 0;
+  case MachineOperand::MO_ConstantPoolIndex:
+    emitConstPoolAddress(MO.getIndex(), relocType);
+    return 0;
+  default: return 0;
+  }
+}
+

Added: llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp?rev=135678&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp (added)
+++ llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp Thu Jul 21 11:28:51 2011
@@ -0,0 +1,195 @@
+//===- MipsJITInfo.cpp - Implement the JIT interfaces for the Mips target -===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the JIT interfaces for the Mips target.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "jit"
+#include "MipsJITInfo.h"
+#include "MipsInstrInfo.h"
+#include "MipsRelocations.h"
+#include "MipsSubtarget.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Memory.h"
+#include 
+using namespace llvm;
+
+
+void MipsJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
+  report_fatal_error("MipsJITInfo::replaceMachineCodeForFunction");
+}
+
+/// JITCompilerFunction - This contains the address of the JIT function used to
+/// compile a function lazily.
+static TargetJITInfo::JITCompilerFn JITCompilerFunction;
+
+// Get the ASMPREFIX for the current host.  This is often '_'.
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+#define GETASMPREFIX2(X) #X
+#define GETASMPREFIX(X) GETASMPREFIX2(X)
+#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
+
+// save registers, call MipsCompilationCallbackC, restore registers
+extern "C" {
+#if defined (__mips__)
+void MipsCompilationCallback();
+
+  asm(
+    ".text\n"
+    ".align 2\n"
+    ".globl " ASMPREFIX "MipsCompilationCallback\n"
+    ASMPREFIX "MipsCompilationCallback:\n"
+    ".ent " ASMPREFIX "MipsCompilationCallback\n"
+    ".set  noreorder\n"
+    ".cpload $t9\n"
+    ".frame  $29, 32, $31\n"
+
+    "addiu $sp, $sp, -40\n"
+    "sw $a0, 4($sp)\n"
+    "sw $a1, 8($sp)\n"
+    "sw $a2, 12($sp)\n"
+    "sw $a3, 20($sp)\n"
+    "sw $ra, 24($sp)\n"
+    "sw $v0, 28($sp)\n"
+    "sw $v1, 32($sp)\n"
+    "sw $t8, 36($sp)\n"
+    ".cprestore 16\n"
+
+    "addiu $a0, $t8, -16\n"
+    "jal   " ASMPREFIX "MipsCompilationCallbackC\n"
+    "nop\n"
+
+    "lw $a0, 4($sp)\n"
+    "lw $a1, 8($sp)\n"
+    "lw $a2, 12($sp)\n"
+    "lw $a3, 20($sp)\n"
+    "lw $ra, 24($sp)\n"
+    "lw $v0, 28($sp)\n"
+    "lw $v1, 32($sp)\n"
+    "lw $t8, 36($sp)\n"
+    "addiu $sp, $sp, 40\n"
+
+    "addiu $t8, $t8, -16\n"
+    "jr $t8\n"
+    "nop\n"
+
+    ".set  reorder\n"
+    ".end " ASMPREFIX "MipsCompilationCallback\n"
+      );
+#else  // host != Mips
+  void MipsCompilationCallback() {
+    llvm_unreachable(
+      "Cannot call MipsCompilationCallback() on a non-Mips arch!");
+  }
+#endif
+}
+
+/// MipsCompilationCallbackC - This is the target-specific function invoked
+/// by the function stub when we did not know the real target of a call.
+/// This function must locate the start of the stub or call site and pass
+/// it into the JIT compiler function.
+extern "C" void MipsCompilationCallbackC(intptr_t StubAddr) {
+
+  // Get the address of the compiled code for this function.
+  intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
+
+  *(intptr_t *) (StubAddr) = 2 << 26 | ((NewVal & 0x0fffffff) >> 2); // J NewVal
+  *(intptr_t *) (StubAddr + 4) = 0; // NOP
+  *(intptr_t *) (StubAddr + 8) = 0; // NOP
+  *(intptr_t *) (StubAddr + 12) = 0; // NOP
+
+  sys::Memory::InvalidateInstructionCache((void*) StubAddr, 16);
+}
+
+TargetJITInfo::LazyResolverFn MipsJITInfo::getLazyResolverFunction(
+    JITCompilerFn F) {
+  JITCompilerFunction = F;
+  return MipsCompilationCallback;
+}
+
+TargetJITInfo::StubLayout MipsJITInfo::getStubLayout() {
+  StubLayout Result = { 24, 4 }; // {Size. Alignment} (of FunctionStub)
+  return Result;
+}
+
+void *MipsJITInfo::emitFunctionStub(const Function* F, void *Fn,
+    JITCodeEmitter &JCE) {
+  JCE.emitAlignment(4);
+  void *Addr = (void*) (JCE.getCurrentPCValue());
+
+  unsigned arg0 = ((intptr_t) MipsCompilationCallback >> 16);
+  if ((((intptr_t) MipsCompilationCallback & 0xffff) >> 15) == 1) {
+    arg0 += 1;  // same hack as in relocate()
+  }
+
+  // LUI t9, %hi(MipsCompilationCallback)
+  JCE.emitWordLE(0xf << 26 | 25 << 16 | arg0);
+  // ADDiu t9, t9, %lo(MipsCompilationCallback)
+  JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16
+          | ((intptr_t) MipsCompilationCallback & 0xffff));
+  // JALR t8, t9
+  JCE.emitWordLE(25 << 21 | 24 << 11 | 9);
+  JCE.emitWordLE(0);  // NOP
+
+  sys::Memory::InvalidateInstructionCache((void*) Addr, 16);
+
+  return Addr;
+}
+
+/// relocate - Before the JIT can run a block of code that has been emitted,
+/// it must rewrite the code to contain the actual addresses of any
+/// referenced global symbols.
+void MipsJITInfo::relocate(void *Function, MachineRelocation *MR,
+    unsigned NumRelocs, unsigned char* GOTBase) {
+  for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
+
+    void *RelocPos = (char*) Function + MR->getMachineCodeOffset();
+    intptr_t ResultPtr = (intptr_t) MR->getResultPointer();
+
+    switch ((Mips::RelocationType) MR->getRelocationType()) {
+    case Mips::reloc_mips_pcrel:
+      ResultPtr = (((ResultPtr - (intptr_t) RelocPos) - 4) >> 2) & 0xffff;
+      *((unsigned*) RelocPos) |= (unsigned) ResultPtr;
+      break;
+
+    case Mips::reloc_mips_j_jal: {
+      ResultPtr = (ResultPtr & 0x0fffffff) >> 2;
+      *((unsigned*) RelocPos) |= (unsigned) ResultPtr;
+    }
+      break;
+
+    case Mips::reloc_mips_hi: {
+      ResultPtr = ResultPtr >> 16;
+
+      // see See MIPS Run Linux, chapter 9.4
+      if ((((intptr_t) (MR->getResultPointer()) & 0xffff) >> 15) == 1) {
+        ResultPtr += 1;
+      }
+
+      *((unsigned*) RelocPos) |= (unsigned) ResultPtr;
+    }
+      break;
+
+    case Mips::reloc_mips_lo:
+      ResultPtr = ResultPtr & 0xffff;
+      *((unsigned*) RelocPos) |= (unsigned) ResultPtr;
+      break;
+
+    default:
+      assert(0 && "MipsJITInfo.unknown relocation;");
+    }
+  }
+}

Added: llvm/trunk/lib/Target/Mips/MipsJITInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.h?rev=135678&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsJITInfo.h (added)
+++ llvm/trunk/lib/Target/Mips/MipsJITInfo.h Thu Jul 21 11:28:51 2011
@@ -0,0 +1,70 @@
+//===- MipsJITInfo.h - Mips implementation of the JIT interface -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MipsJITInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MIPSJITINFO_H
+#define MIPSJITINFO_H
+
+#include "MipsMachineFunction.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/Target/TargetJITInfo.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+
+namespace llvm {
+class MipsTargetMachine;
+
+class MipsJITInfo : public TargetJITInfo {
+
+  bool IsPIC;
+
+  public:
+    explicit MipsJITInfo() :
+      IsPIC(false) {}
+
+    /// replaceMachineCodeForFunction - Make it so that calling the function
+    /// whose machine code is at OLD turns into a call to NEW, perhaps by
+    /// overwriting OLD with a branch to NEW.  This is used for self-modifying
+    /// code.
+    ///
+    virtual void replaceMachineCodeForFunction(void *Old, void *New);
+
+    // getStubLayout - Returns the size and alignment of the largest call stub
+    // on Mips.
+    virtual StubLayout getStubLayout();
+
+    /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
+    /// small native function that simply calls the function at the specified
+    /// address.
+    virtual void *emitFunctionStub(const Function* F, void *Fn,
+        JITCodeEmitter &JCE);
+
+    /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
+    virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
+
+    /// relocate - Before the JIT can run a block of code that has been emitted,
+    /// it must rewrite the code to contain the actual addresses of any
+    /// referenced global symbols.
+    virtual void relocate(void *Function, MachineRelocation *MR,
+        unsigned NumRelocs, unsigned char* GOTBase);
+
+    /// Initialize - Initialize internal stage for the function being JITted.
+    void Initialize(const MachineFunction &MF, bool isPIC) {
+      IsPIC = isPIC;
+    }
+
+};
+}
+
+#endif

Added: llvm/trunk/lib/Target/Mips/MipsRelocations.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRelocations.h?rev=135678&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRelocations.h (added)
+++ llvm/trunk/lib/Target/Mips/MipsRelocations.h Thu Jul 21 11:28:51 2011
@@ -0,0 +1,32 @@
+//===- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+//
+// This file defines the Mips target-specific relocation types
+// (for relocation-model=static).
+//
+//===---------------------------------------------------------------------===//
+
+#ifndef MIPSRELOCATIONS_H_
+#define MIPSRELOCATIONS_H_
+
+#include "llvm/CodeGen/MachineRelocation.h"
+
+namespace llvm {
+  namespace Mips{
+    enum RelocationType {
+      reloc_mips_pcrel = 1,
+      reloc_mips_hi = 3,
+      reloc_mips_lo = 4,
+      reloc_mips_j_jal = 5
+    };
+  }
+}
+
+#endif /* MIPSRELOCATIONS_H_ */
+

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 21 11:28:51 2011
@@ -42,7 +42,7 @@
              std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
   InstrInfo(*this),
   FrameLowering(Subtarget),
-  TLInfo(*this), TSInfo(*this) {
+  TLInfo(*this), TSInfo(*this), JITInfo() {
 }
 
 MipselTargetMachine::
@@ -81,3 +81,12 @@
   PM.add(createMipsExpandPseudoPass(*this));
   return true;
 }
+
+bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                          CodeGenOpt::Level OptLevel,
+                                          JITCodeEmitter &JCE) {
+  // Machine code emitter pass for Mips.
+  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
+  return false;
+}
+

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Thu Jul 21 11:28:51 2011
@@ -22,6 +22,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetFrameLowering.h"
+#include "MipsJITInfo.h"
 
 namespace llvm {
   class formatted_raw_ostream;
@@ -33,6 +34,9 @@
     MipsFrameLowering   FrameLowering;
     MipsTargetLowering  TLInfo;
     MipsSelectionDAGInfo TSInfo;
+    MipsJITInfo JITInfo;
+    Reloc::Model DefRelocModel; // Reloc model before it's overridden.
+
   public:
     MipsTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
@@ -47,6 +51,9 @@
     { return &Subtarget; }
     virtual const TargetData      *getTargetData()    const
     { return &DataLayout;}
+    virtual MipsJITInfo *getJITInfo()
+    { return &JITInfo; }
+
 
     virtual const MipsRegisterInfo *getRegisterInfo()  const {
       return &InstrInfo.getRegisterInfo();
@@ -68,6 +75,10 @@
     virtual bool addPreRegAlloc(PassManagerBase &PM,
                                 CodeGenOpt::Level OptLevel);
     virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
+    virtual bool addCodeEmitter(PassManagerBase &PM,
+				 CodeGenOpt::Level OptLevel,
+				 JITCodeEmitter &JCE);
+
   };
 
 /// MipselTargetMachine - Mipsel target machine.

Modified: llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp?rev=135678&r1=135677&r2=135678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp Thu Jul 21 11:28:51 2011
@@ -15,7 +15,9 @@
 Target llvm::TheMipsTarget, llvm::TheMipselTarget;
 
 extern "C" void LLVMInitializeMipsTargetInfo() {
-  RegisterTarget X(TheMipsTarget, "mips", "Mips");
+  RegisterTarget X(TheMipsTarget, "mips", "Mips");
 
-  RegisterTarget Y(TheMipselTarget, "mipsel", "Mipsel");
+  RegisterTarget Y(TheMipselTarget, "mipsel", "Mipsel");
 }



From bruno.cardoso at gmail.com  Thu Jul 21 11:31:27 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 21 Jul 2011 09:31:27 -0700
Subject: [llvm-commits] [llvm] [PATCH] Mips JIT implementation
In-Reply-To: <4DFA0C63.3030103@rt-rk.com>
References: <4DC18677.20706@rt-rk.com>
	
	<4DFA0C63.3030103@rt-rk.com>
Message-ID: 

Hi Vladimir,
Sorry again for the late reply.

> thanks a lot for the review.
> Here's the modified version, with emitInstruction relying on TSFlags.

I commited the first chunk in r135678. We still need to improve the
TSFlags part before integrating. Here are a couple of things:

1) There's no need to add this amount of bits for the TSFlags. We
should heavily rely on auto-generated stuff. So, the first step is to
get automatic encoding from getBinaryCodeForInstr(MI). If you apply
the attached mips00.patch, you will make llvm autogenerate several
encoding functions, and to use it all you need is to include the .inc
file in the end of MipsCodeEmitter.cpp (see ARM for details). It's
important that we go this path because we want a really easy migration
to the MC JIT later, so is important that we handle as much as
possible of the encoding in the tablegen files. When you apply this
patch, it will break tblgen, so you need to find out what is going
wrong with the actual descriptions in the first place.

2) After doing that, you will need more bits in TSFlags to describe
additional stuff, to do that, follow the style and enum as in
mips01.patch, don't apply this patch, it's just an example of how to
do stuff.

3) After 1) let's work in small pieces, in the following patches, send
only the JIT handling for class FR for example, easier to review, and
will apply and get feedback to you faster. And then we move to the
next patch! Mips is simple enough that the implementation should be
easy to understand.

Thanks again for working on this,

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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From grosbach at apple.com  Thu Jul 21 12:23:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 21 Jul 2011 17:23:04 -0000
Subject: [llvm-commits] [llvm] r135682 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrInfo.td AsmParser/ARMAsmParser.cpp
Message-ID: <20110721172304.5E69C2A6C12D@llvm.org>

Author: grosbach
Date: Thu Jul 21 12:23:04 2011
New Revision: 135682

URL: http://llvm.org/viewvc/llvm-project?rev=135682&view=rev
Log:
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135682&r1=135681&r2=135682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Jul 21 12:23:04 2011
@@ -847,11 +847,21 @@
 }
 
 // PKH instructions
+def PKHLSLAsmOperand : AsmOperandClass {
+  let Name = "PKHLSLImm";
+  let ParserMethod = "parsePKHLSLImm";
+}
 def pkh_lsl_amt: Operand, ImmLeaf= 0 && Imm < 32; }]>{
   let PrintMethod = "printPKHLSLShiftImm";
+  let ParserMatchClass = PKHLSLAsmOperand;
+}
+def PKHASRAsmOperand : AsmOperandClass {
+  let Name = "PKHASRImm";
+  let ParserMethod = "parsePKHASRImm";
 }
 def pkh_asr_amt: Operand, ImmLeaf 0 && Imm <= 32; }]>{
   let PrintMethod = "printPKHASRShiftImm";
+  let ParserMatchClass = PKHASRAsmOperand;
 }
 
 class APKHI opcod, bit tb, dag oops, dag iops, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135682&r1=135681&r2=135682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 21 12:23:04 2011
@@ -4067,3 +4067,9 @@
 def : MnemonicAlias<"stmia", "stm">;
 def : MnemonicAlias<"stmea", "stm">;
 
+// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
+// shift amount is zero (i.e., unspecified).
+def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
+                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
+def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
+                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135682&r1=135681&r2=135682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 21 12:23:04 2011
@@ -118,6 +118,14 @@
     SmallVectorImpl&);
   OperandMatchResultTy tryParseMemMode3Operand(
     SmallVectorImpl&);
+  OperandMatchResultTy parsePKHImm(SmallVectorImpl &O,
+                                   StringRef Op, int Low, int High);
+  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl &O) {
+    return parsePKHImm(O, "lsl", 0, 31);
+  }
+  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl &O) {
+    return parsePKHImm(O, "asr", 1, 32);
+  }
 
   // Asm Match Converter Methods
   bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
@@ -419,6 +427,22 @@
     int64_t Value = CE->getValue();
     return Value >= 0 && Value < 65536;
   }
+  bool isPKHLSLImm() const {
+    if (Kind != Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value >= 0 && Value < 32;
+  }
+  bool isPKHASRImm() const {
+    if (Kind != Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value > 0 && Value <= 32;
+  }
   bool isARMSOImm() const {
     if (Kind != Immediate)
       return false;
@@ -638,6 +662,20 @@
     addExpr(Inst, getImm());
   }
 
+  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    addExpr(Inst, getImm());
+  }
+
+  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // An ASR value of 32 encodes as 0, so that's how we want to add it to
+    // the instruction as well.
+    const MCConstantExpr *CE = dyn_cast(getImm());
+    int Val = CE->getValue();
+    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
+  }
+
   void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
@@ -1507,6 +1545,52 @@
   return MatchOperand_Success;
 }
 
+ARMAsmParser::OperandMatchResultTy ARMAsmParser::
+parsePKHImm(SmallVectorImpl &Operands, StringRef Op,
+            int Low, int High) {
+  const AsmToken &Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier)) {
+    Error(Parser.getTok().getLoc(), Op + " operand expected.");
+    return MatchOperand_ParseFail;
+  }
+  StringRef ShiftName = Tok.getString();
+  std::string LowerOp = LowercaseString(Op);
+  std::string UpperOp = UppercaseString(Op);
+  if (ShiftName != LowerOp && ShiftName != UpperOp) {
+    Error(Parser.getTok().getLoc(), Op + " operand expected.");
+    return MatchOperand_ParseFail;
+  }
+  Parser.Lex(); // Eat shift type token.
+
+  // There must be a '#' and a shift amount.
+  if (Parser.getTok().isNot(AsmToken::Hash)) {
+    Error(Parser.getTok().getLoc(), "'#' expected");
+    return MatchOperand_ParseFail;
+  }
+  Parser.Lex(); // Eat hash token.
+
+  const MCExpr *ShiftAmount;
+  SMLoc Loc = Parser.getTok().getLoc();
+  if (getParser().ParseExpression(ShiftAmount)) {
+    Error(Loc, "illegal expression");
+    return MatchOperand_ParseFail;
+  }
+  const MCConstantExpr *CE = dyn_cast(ShiftAmount);
+  if (!CE) {
+    Error(Loc, "constant expression expected");
+    return MatchOperand_ParseFail;
+  }
+  int Val = CE->getValue();
+  if (Val < Low || Val > High) {
+    Error(Loc, "immediate value out of range");
+    return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
+
+  return MatchOperand_Success;
+}
+
 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
 /// when they refer multiple MIOperands inside a single one.



From benny.kra at googlemail.com  Thu Jul 21 12:26:51 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 21 Jul 2011 17:26:51 -0000
Subject: [llvm-commits] [llvm] r135683 - in /llvm/trunk/include/llvm:
 MC/MCRegisterInfo.h Target/TargetRegisterInfo.h
Message-ID: <20110721172651.100AC2A6C12D@llvm.org>

Author: d0k
Date: Thu Jul 21 12:26:50 2011
New Revision: 135683

URL: http://llvm.org/viewvc/llvm-project?rev=135683&view=rev
Log:
Sink parts of TargetRegisterClass into MCRegisterClass.

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=135683&r1=135682&r2=135683&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Jul 21 12:26:50 2011
@@ -17,10 +17,87 @@
 #define LLVM_MC_MCREGISTERINFO_H
 
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
 #include 
 
 namespace llvm {
 
+/// MCRegisterClass - Base class of TargetRegisterClass.
+class MCRegisterClass {
+public:
+  typedef const unsigned* iterator;
+  typedef const unsigned* const_iterator;
+private:
+  unsigned ID;
+  const char *Name;
+  const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
+  const int CopyCost;
+  const bool Allocatable;
+  const iterator RegsBegin, RegsEnd;
+  DenseSet RegSet;
+public:
+  MCRegisterClass(unsigned id, const char *name,
+                  unsigned RS, unsigned Al, int CC, bool Allocable,
+                  iterator RB, iterator RE)
+    : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
+      Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {
+      for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
+        RegSet.insert(*I);
+    }
+
+  /// getID() - Return the register class ID number.
+  ///
+  unsigned getID() const { return ID; }
+
+  /// getName() - Return the register class name for debugging.
+  ///
+  const char *getName() const { return Name; }
+
+  /// begin/end - Return all of the registers in this class.
+  ///
+  iterator       begin() const { return RegsBegin; }
+  iterator         end() const { return RegsEnd; }
+
+  /// getNumRegs - Return the number of registers in this class.
+  ///
+  unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
+
+  /// getRegister - Return the specified register in the class.
+  ///
+  unsigned getRegister(unsigned i) const {
+    assert(i < getNumRegs() && "Register number out of range!");
+    return RegsBegin[i];
+  }
+
+  /// contains - Return true if the specified register is included in this
+  /// register class.  This does not include virtual registers.
+  bool contains(unsigned Reg) const {
+    return RegSet.count(Reg);
+  }
+
+  /// contains - Return true if both registers are in this class.
+  bool contains(unsigned Reg1, unsigned Reg2) const {
+    return contains(Reg1) && contains(Reg2);
+  }
+
+  /// getSize - Return the size of the register in bytes, which is also the size
+  /// of a stack slot allocated to hold a spilled copy of this register.
+  unsigned getSize() const { return RegSize; }
+
+  /// getAlignment - Return the minimum required alignment for a register of
+  /// this class.
+  unsigned getAlignment() const { return Alignment; }
+
+  /// getCopyCost - Return the cost of copying a value between two registers in
+  /// this class. A negative number means the register class is very expensive
+  /// to copy e.g. status flag register classes.
+  int getCopyCost() const { return CopyCost; }
+
+  /// isAllocatable - Return true if this register class may be used to create
+  /// virtual registers.
+  bool isAllocatable() const { return Allocatable; }
+};
+
 /// MCRegisterDesc - This record contains all of the information known about
 /// a particular register.  The Overlaps field contains a pointer to a zero
 /// terminated array of registers that this register aliases, starting with

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=135683&r1=135682&r2=135683&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jul 21 12:26:50 2011
@@ -32,79 +32,29 @@
 template class SmallVectorImpl;
 class raw_ostream;
 
-class TargetRegisterClass {
+class TargetRegisterClass : public MCRegisterClass {
 public:
-  typedef const unsigned* iterator;
-  typedef const unsigned* const_iterator;
-
   typedef const EVT* vt_iterator;
   typedef const TargetRegisterClass* const * sc_iterator;
 private:
-  unsigned ID;
-  const char *Name;
   const vt_iterator VTs;
   const sc_iterator SubClasses;
   const sc_iterator SuperClasses;
   const sc_iterator SubRegClasses;
   const sc_iterator SuperRegClasses;
-  const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
-  const int CopyCost;
-  const bool Allocatable;
-  const iterator RegsBegin, RegsEnd;
-  DenseSet RegSet;
 public:
-  TargetRegisterClass(unsigned id,
-                      const char *name,
-                      const EVT *vts,
+  TargetRegisterClass(unsigned id, const char *name, const EVT *vts,
                       const TargetRegisterClass * const *subcs,
                       const TargetRegisterClass * const *supcs,
                       const TargetRegisterClass * const *subregcs,
                       const TargetRegisterClass * const *superregcs,
                       unsigned RS, unsigned Al, int CC, bool Allocable,
                       iterator RB, iterator RE)
-    : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
-    SubRegClasses(subregcs), SuperRegClasses(superregcs),
-    RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable),
-    RegsBegin(RB), RegsEnd(RE) {
-      for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
-        RegSet.insert(*I);
-    }
-  virtual ~TargetRegisterClass() {}     // Allow subclasses
-
-  /// getID() - Return the register class ID number.
-  ///
-  unsigned getID() const { return ID; }
+    : MCRegisterClass(id, name, RS, Al, CC, Allocable, RB, RE),
+      VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs),
+      SuperRegClasses(superregcs) {}
 
-  /// getName() - Return the register class name for debugging.
-  ///
-  const char *getName() const { return Name; }
-
-  /// begin/end - Return all of the registers in this class.
-  ///
-  iterator       begin() const { return RegsBegin; }
-  iterator         end() const { return RegsEnd; }
-
-  /// getNumRegs - Return the number of registers in this class.
-  ///
-  unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
-
-  /// getRegister - Return the specified register in the class.
-  ///
-  unsigned getRegister(unsigned i) const {
-    assert(i < getNumRegs() && "Register number out of range!");
-    return RegsBegin[i];
-  }
-
-  /// contains - Return true if the specified register is included in this
-  /// register class.  This does not include virtual registers.
-  bool contains(unsigned Reg) const {
-    return RegSet.count(Reg);
-  }
-
-  /// contains - Return true if both registers are in this class.
-  bool contains(unsigned Reg1, unsigned Reg2) const {
-    return contains(Reg1) && contains(Reg2);
-  }
+  virtual ~TargetRegisterClass() {}     // Allow subclasses
 
   /// hasType - return true if this TargetRegisterClass has the ValueType vt.
   ///
@@ -236,23 +186,6 @@
   ArrayRef getRawAllocationOrder(const MachineFunction &MF) const {
     return makeArrayRef(begin(), getNumRegs());
   }
-
-  /// getSize - Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return RegSize; }
-
-  /// getAlignment - Return the minimum required alignment for a register of
-  /// this class.
-  unsigned getAlignment() const { return Alignment; }
-
-  /// getCopyCost - Return the cost of copying a value between two registers in
-  /// this class. A negative number means the register class is very expensive
-  /// to copy e.g. status flag register classes.
-  int getCopyCost() const { return CopyCost; }
-
-  /// isAllocatable - Return true if this register class may be used to create
-  /// virtual registers.
-  bool isAllocatable() const { return Allocatable; }
 };
 
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about



From atrick at apple.com  Thu Jul 21 12:37:39 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 21 Jul 2011 17:37:39 -0000
Subject: [llvm-commits] [llvm] r135684 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20110721173739.ED0CA2A6C12D@llvm.org>

Author: atrick
Date: Thu Jul 21 12:37:39 2011
New Revision: 135684

URL: http://llvm.org/viewvc/llvm-project?rev=135684&view=rev
Log:
Cleanup: make std::pair usage slightly less indecipherable without actually naming variables!

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=135684&r1=135683&r2=135684&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jul 21 12:37:39 2011
@@ -1389,23 +1389,24 @@
       pushIVUsers(CurrIV, Simplified, SimpleIVUsers);
 
       while (!SimpleIVUsers.empty()) {
-        std::pair Use =SimpleIVUsers.pop_back_val();
+        std::pair UseOper =
+          SimpleIVUsers.pop_back_val();
         // Bypass back edges to avoid extra work.
-        if (Use.first == CurrIV) continue;
+        if (UseOper.first == CurrIV) continue;
 
-        if (EliminateIVUser(Use.first, Use.second)) {
-          pushIVUsers(Use.second, Simplified, SimpleIVUsers);
+        if (EliminateIVUser(UseOper.first, UseOper.second)) {
+          pushIVUsers(UseOper.second, Simplified, SimpleIVUsers);
           continue;
         }
-        if (CastInst *Cast = dyn_cast(Use.first)) {
+        if (CastInst *Cast = dyn_cast(UseOper.first)) {
           bool IsSigned = Cast->getOpcode() == Instruction::SExt;
           if (IsSigned || Cast->getOpcode() == Instruction::ZExt) {
             CollectExtend(Cast, IsSigned, WI, SE, TD);
           }
           continue;
         }
-        if (isSimpleIVUser(Use.first, L, SE)) {
-          pushIVUsers(Use.first, Simplified, SimpleIVUsers);
+        if (isSimpleIVUser(UseOper.first, L, SE)) {
+          pushIVUsers(UseOper.first, Simplified, SimpleIVUsers);
         }
       }
       if (WI.WidestNativeType) {



From isanbard at gmail.com  Thu Jul 21 12:44:50 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 21 Jul 2011 10:44:50 -0700
Subject: [llvm-commits] [llvm] r135645 -
 /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
In-Reply-To: 
References: <20110721004456.EE90A2A6C12D@llvm.org>
	
Message-ID: 

On Jul 21, 2011, at 2:28 AM, Anton Korobeynikov wrote:

> Hi Bill,
> 
>> -                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
>> -                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
>> +                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
>> +        .addReg(StackPtr)
>> +        .addImm(-MaxAlign)
>> +        .setMIFlag(MachineInstr::FrameSetup);
> What do you think - maybe we'll introduce the BuildFrameSetupMI helper
> method? Just to make sure we won't miss .setMIFlag calls in such
> cases?
> 
It might not be a bad idea. :-)

-bw


From jyasskin at google.com  Thu Jul 21 12:45:44 2011
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Thu, 21 Jul 2011 10:45:44 -0700
Subject: [llvm-commits] [llvm] r135678 - in /llvm/trunk: CMakeLists.txt
 autoconf/configure.ac configure lib/Target/Mips/CMakeLists.txt
 lib/Target/Mips/Mips.h lib/Target/Mips/MipsCodeEmitter.cpp
 lib/Target/Mips/MipsJITInfo.cpp lib/Target/Mips/MipsJITInfo.h
Message-ID: 

This appears to have broken the cmake build with the following error:

CMake Error at cmake/modules/LLVMProcessSources.cmake:86 (message):
  Found unknown source file
  /Users/jyasskin/src/llvm/git/src/lib/Target/Mips/MipsJITInfo.cpp

  Please update
  /Users/jyasskin/src/llvm/git/src/lib/Target/Mips/CMakeLists.txt

Call Stack (most recent call first):
  cmake/modules/LLVMProcessSources.cmake:42 (llvm_check_source_file_list)
  cmake/modules/AddLLVM.cmake:5 (llvm_process_sources)
  cmake/modules/AddLLVM.cmake:133 (add_llvm_library)
  lib/Target/Mips/CMakeLists.txt:10 (add_llvm_target)


The following patch fixes it for me:

--- a/lib/Target/Mips/CMakeLists.txt
+++ b/lib/Target/Mips/CMakeLists.txt
@@ -17,6 +17,7 @@ add_llvm_target(MipsCodeGen
   MipsISelDAGToDAG.cpp
   MipsISelLowering.cpp
   MipsFrameLowering.cpp
+  MipsJITInfo.cpp
   MipsMCInstLower.cpp
   MipsMCSymbolRefExpr.cpp
   MipsRegisterInfo.cpp


Is there a reason you omitted MipsJITInfo.cpp from CMakeLists.txt, or
should I commit this patch?

On Thu, Jul 21, 2011 at 9:28 AM, Bruno Cardoso Lopes
 wrote:
> Author: bruno
> Date: Thu Jul 21 11:28:51 2011
> New Revision: 135678
>
> URL: http://llvm.org/viewvc/llvm-project?rev=135678&view=rev
> Log:
> Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
> Stefanovic. I removed the part that actually emits the instructions cause
> I want that to get in better shape first and in incremental steps. This
> also makes it easier to review the upcoming parts.
>
> Added:
> ? ?llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsJITInfo.h
> ? ?llvm/trunk/lib/Target/Mips/MipsRelocations.h
> Modified:
> ? ?llvm/trunk/CMakeLists.txt
> ? ?llvm/trunk/autoconf/configure.ac
> ? ?llvm/trunk/configure
> ? ?llvm/trunk/lib/Target/Mips/CMakeLists.txt
> ? ?llvm/trunk/lib/Target/Mips/Mips.h
> ? ?llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> ? ?llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
>
> Modified: llvm/trunk/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/CMakeLists.txt (original)
> +++ llvm/trunk/CMakeLists.txt Thu Jul 21 11:28:51 2011
> @@ -82,7 +82,7 @@
> ? )
>
> ?# List of targets with JIT support:
> -set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM)
> +set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM Mips)
>
> ?if( MSVC )
> ? set(LLVM_TARGETS_TO_BUILD X86
>
> Modified: llvm/trunk/autoconf/configure.ac
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/autoconf/configure.ac (original)
> +++ llvm/trunk/autoconf/configure.ac Thu Jul 21 11:28:51 2011
> @@ -484,7 +484,7 @@
> ? ? x86_64) ? ? ?AC_SUBST(TARGET_HAS_JIT,1) ;;
> ? ? Alpha) ? ? ? AC_SUBST(TARGET_HAS_JIT,0) ;;
> ? ? ARM) ? ? ? ? AC_SUBST(TARGET_HAS_JIT,1) ;;
> - ? ?Mips) ? ? ? ?AC_SUBST(TARGET_HAS_JIT,0) ;;
> + ? ?Mips) ? ? ? ?AC_SUBST(TARGET_HAS_JIT,1) ;;
> ? ? XCore) ? ? ? AC_SUBST(TARGET_HAS_JIT,0) ;;
> ? ? MSP430) ? ? ?AC_SUBST(TARGET_HAS_JIT,0) ;;
> ? ? SystemZ) ? ? AC_SUBST(TARGET_HAS_JIT,0) ;;
>
> Modified: llvm/trunk/configure
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/configure (original)
> +++ llvm/trunk/configure Thu Jul 21 11:28:51 2011
> @@ -4865,7 +4865,7 @@
> ?;;
> ? ? ARM) ? ? ? ? TARGET_HAS_JIT=1
> ?;;
> - ? ?Mips) ? ? ? ?TARGET_HAS_JIT=0
> + ? ?Mips) ? ? ? ?TARGET_HAS_JIT=1
> ?;;
> ? ? XCore) ? ? ? TARGET_HAS_JIT=0
> ?;;
>
> Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jul 21 11:28:51 2011
> @@ -9,6 +9,7 @@
>
> ?add_llvm_target(MipsCodeGen
> ? MipsAsmPrinter.cpp
> + ?MipsCodeEmitter.cpp
> ? MipsDelaySlotFiller.cpp
> ? MipsEmitGPRestore.cpp
> ? MipsExpandPseudo.cpp
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.h Thu Jul 21 11:28:51 2011
> @@ -29,6 +29,9 @@
> ? FunctionPass *createMipsExpandPseudoPass(MipsTargetMachine &TM);
> ? FunctionPass *createMipsEmitGPRestorePass(MipsTargetMachine &TM);
>
> + ?FunctionPass *createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JITCodeEmitter &JCE);
> +
> ?} // end namespace llvm;
>
> ?#endif
>
> Added: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=135678&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (added)
> +++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Thu Jul 21 11:28:51 2011
> @@ -0,0 +1,193 @@
> +//===-- Mips/MipsCodeEmitter.cpp - Convert Mips code to machine code -----===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===---------------------------------------------------------------------===//
> +//
> +// This file contains the pass that transforms the Mips machine instructions
> +// into relocatable machine code.
> +//
> +//===---------------------------------------------------------------------===//
> +
> +#define DEBUG_TYPE "jit"
> +#include "Mips.h"
> +#include "MipsInstrInfo.h"
> +#include "MipsRelocations.h"
> +#include "MipsSubtarget.h"
> +#include "MipsTargetMachine.h"
> +#include "llvm/Constants.h"
> +#include "llvm/DerivedTypes.h"
> +#include "llvm/Function.h"
> +#include "llvm/PassManager.h"
> +#include "llvm/CodeGen/JITCodeEmitter.h"
> +#include "llvm/CodeGen/MachineConstantPool.h"
> +#include "llvm/CodeGen/MachineFunctionPass.h"
> +#include "llvm/CodeGen/MachineInstr.h"
> +#include "llvm/CodeGen/MachineJumpTableInfo.h"
> +#include "llvm/CodeGen/MachineModuleInfo.h"
> +#include "llvm/CodeGen/Passes.h"
> +#include "llvm/ADT/Statistic.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Support/raw_ostream.h"
> +#ifndef NDEBUG
> +#include 
> +#endif
> +
> +#include "llvm/CodeGen/MachineOperand.h"
> +
> +using namespace llvm;
> +
> +namespace {
> +
> +class MipsCodeEmitter : public MachineFunctionPass {
> + ?MipsJITInfo *JTI;
> + ?const MipsInstrInfo *II;
> + ?const TargetData *TD;
> + ?const MipsSubtarget *Subtarget;
> + ?TargetMachine &TM;
> + ?JITCodeEmitter &MCE;
> + ?const std::vector *MCPEs;
> + ?const std::vector *MJTEs;
> + ?bool IsPIC;
> +
> + ?void getAnalysisUsage(AnalysisUsage &AU) const {
> + ? ?AU.addRequired ();
> + ? ?MachineFunctionPass::getAnalysisUsage(AU);
> + ?}
> +
> + ?static char ID;
> +
> + ?public:
> + ? ?MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) :
> + ? ? ?MachineFunctionPass(ID), JTI(0),
> + ? ? ? ?II((const MipsInstrInfo *) tm.getInstrInfo()),
> + ? ? ? ?TD(tm.getTargetData()), TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
> + ? ? ? ?IsPIC(TM.getRelocationModel() == Reloc::PIC_) {
> + ? ?}
> +
> + ? ?bool runOnMachineFunction(MachineFunction &MF);
> +
> + ? ?virtual const char *getPassName() const {
> + ? ? ?return "Mips Machine Code Emitter";
> + ? ?}
> +
> + ? ?void emitInstruction(const MachineInstr &MI);
> +
> + ? ?unsigned getOperandValue(const MachineOperand &MO,
> + ? ? ? ?unsigned relocType = -1);
> +
> + ? ?void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
> + ? ? ? ?bool MayNeedFarStub = true);
> +
> + ? ?void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
> + ? ? ? ?intptr_t JTBase = 0);
> +
> + ? ?void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
> + ? ?void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
> + ? ?void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
> +};
> +}
> +
> +void MipsCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
> + ? ?bool mayNeedFarStub) {
> + ?MachineRelocation MR = MachineRelocation::getGV(MCE.getCurrentPCOffset(),
> + ? ? ? ? ? ? ? ? ?Reloc, const_cast (GV), 0, mayNeedFarStub);
> + ?MCE.addRelocation(MR);
> +}
> +
> +/// emitMachineBasicBlock - Emit the specified address basic block.
> +void MipsCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
> + ? ?unsigned Reloc, intptr_t JTBase) {
> + ?MCE.addRelocation(
> + ? ? ?MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, BB, JTBase));
> +}
> +
> +void MipsCodeEmitter::emitExternalSymbolAddress(const char *ES,
> + ? ?unsigned Reloc) {
> + ?MCE.addRelocation(
> + ? ? ?MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES, 0, 0,
> + ? ? ? ? ?false));
> +}
> +
> +void MipsCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc)
> + ? ?const {
> + ?MCE.addRelocation(
> + ? ? ?MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTIndex,
> + ? ? ? ? ?0, false));
> +}
> +
> +void MipsCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
> + ?MCE.addRelocation(
> + ? ? ?MachineRelocation::getConstPool
> + ? ? ? ?(MCE.getCurrentPCOffset(), Reloc, CPI, 0));
> +}
> +
> +/// createMipsJITCodeEmitterPass - Return a pass that emits the collected Mips
> +/// code to the specified MCE object.
> +FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
> + ? ?JITCodeEmitter &JCE) {
> + ?return new MipsCodeEmitter(TM, JCE);
> +}
> +
> +char MipsCodeEmitter::ID = 10;
> +
> +bool MipsCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
> + ?JTI = ((MipsTargetMachine&) MF.getTarget()).getJITInfo();
> + ?II = ((const MipsTargetMachine&) MF.getTarget()).getInstrInfo();
> + ?TD = ((const MipsTargetMachine&) MF.getTarget()).getTargetData();
> + ?Subtarget = &TM.getSubtarget ();
> + ?MCPEs = &MF.getConstantPool()->getConstants();
> + ?MJTEs = 0;
> + ?if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
> + ?JTI->Initialize(MF, IsPIC);
> + ?MCE.setModuleInfo(&getAnalysis ());
> +
> + ?do {
> + ? ?DEBUG(errs() << "JITTing function '"
> + ? ? ? ?<< MF.getFunction()->getName() << "'\n");
> + ? ?MCE.startFunction(MF);
> +
> + ? ?for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
> + ? ? ? ?MBB != E; ++MBB){
> + ? ? ?MCE.StartMachineBasicBlock(MBB);
> + ? ? ?for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
> + ? ? ? ? ?I != E; ++I)
> + ? ? ? ?emitInstruction(*I);
> + ? ?}
> + ?} while (MCE.finishFunction(MF));
> +
> + ?return false;
> +}
> +
> +void MipsCodeEmitter::emitInstruction(const MachineInstr &MI) {}
> +
> +unsigned MipsCodeEmitter::getOperandValue(const MachineOperand &MO,
> + ? ?unsigned relocType) {
> + ?switch (MO.getType()) {
> + ?case MachineOperand::MO_Immediate:
> + ? ?return MO.getImm();
> + ?case MachineOperand::MO_GlobalAddress:
> + ? ?emitGlobalAddress(MO.getGlobal(), relocType, false);
> + ? ?return 0;
> + ?case MachineOperand::MO_ExternalSymbol:
> + ? ?emitExternalSymbolAddress(MO.getSymbolName(), relocType);
> + ? ?return 0;
> + ?case MachineOperand::MO_MachineBasicBlock:
> + ? ?emitMachineBasicBlock(MO.getMBB(), relocType, MCE.getCurrentPCValue());
> + ? ?return 0;
> + ?case MachineOperand::MO_Register:
> + ? ?return MipsRegisterInfo::getRegisterNumbering(MO.getReg());
> + ?case MachineOperand::MO_JumpTableIndex:
> + ? ?emitJumpTableAddress(MO.getIndex(), relocType);
> + ? ?return 0;
> + ?case MachineOperand::MO_ConstantPoolIndex:
> + ? ?emitConstPoolAddress(MO.getIndex(), relocType);
> + ? ?return 0;
> + ?default: return 0;
> + ?}
> +}
> +
>
> Added: llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp?rev=135678&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp (added)
> +++ llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp Thu Jul 21 11:28:51 2011
> @@ -0,0 +1,195 @@
> +//===- MipsJITInfo.cpp - Implement the JIT interfaces for the Mips target -===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements the JIT interfaces for the Mips target.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#define DEBUG_TYPE "jit"
> +#include "MipsJITInfo.h"
> +#include "MipsInstrInfo.h"
> +#include "MipsRelocations.h"
> +#include "MipsSubtarget.h"
> +#include "llvm/Function.h"
> +#include "llvm/CodeGen/JITCodeEmitter.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Support/raw_ostream.h"
> +#include "llvm/Support/Memory.h"
> +#include 
> +using namespace llvm;
> +
> +
> +void MipsJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
> + ?report_fatal_error("MipsJITInfo::replaceMachineCodeForFunction");
> +}
> +
> +/// JITCompilerFunction - This contains the address of the JIT function used to
> +/// compile a function lazily.
> +static TargetJITInfo::JITCompilerFn JITCompilerFunction;
> +
> +// Get the ASMPREFIX for the current host. ?This is often '_'.
> +#ifndef __USER_LABEL_PREFIX__
> +#define __USER_LABEL_PREFIX__
> +#endif
> +#define GETASMPREFIX2(X) #X
> +#define GETASMPREFIX(X) GETASMPREFIX2(X)
> +#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
> +
> +// save registers, call MipsCompilationCallbackC, restore registers
> +extern "C" {
> +#if defined (__mips__)
> +void MipsCompilationCallback();
> +
> + ?asm(
> + ? ?".text\n"
> + ? ?".align 2\n"
> + ? ?".globl " ASMPREFIX "MipsCompilationCallback\n"
> + ? ?ASMPREFIX "MipsCompilationCallback:\n"
> + ? ?".ent " ASMPREFIX "MipsCompilationCallback\n"
> + ? ?".set ?noreorder\n"
> + ? ?".cpload $t9\n"
> + ? ?".frame ?$29, 32, $31\n"
> +
> + ? ?"addiu $sp, $sp, -40\n"
> + ? ?"sw $a0, 4($sp)\n"
> + ? ?"sw $a1, 8($sp)\n"
> + ? ?"sw $a2, 12($sp)\n"
> + ? ?"sw $a3, 20($sp)\n"
> + ? ?"sw $ra, 24($sp)\n"
> + ? ?"sw $v0, 28($sp)\n"
> + ? ?"sw $v1, 32($sp)\n"
> + ? ?"sw $t8, 36($sp)\n"
> + ? ?".cprestore 16\n"
> +
> + ? ?"addiu $a0, $t8, -16\n"
> + ? ?"jal ? " ASMPREFIX "MipsCompilationCallbackC\n"
> + ? ?"nop\n"
> +
> + ? ?"lw $a0, 4($sp)\n"
> + ? ?"lw $a1, 8($sp)\n"
> + ? ?"lw $a2, 12($sp)\n"
> + ? ?"lw $a3, 20($sp)\n"
> + ? ?"lw $ra, 24($sp)\n"
> + ? ?"lw $v0, 28($sp)\n"
> + ? ?"lw $v1, 32($sp)\n"
> + ? ?"lw $t8, 36($sp)\n"
> + ? ?"addiu $sp, $sp, 40\n"
> +
> + ? ?"addiu $t8, $t8, -16\n"
> + ? ?"jr $t8\n"
> + ? ?"nop\n"
> +
> + ? ?".set ?reorder\n"
> + ? ?".end " ASMPREFIX "MipsCompilationCallback\n"
> + ? ? ?);
> +#else ?// host != Mips
> + ?void MipsCompilationCallback() {
> + ? ?llvm_unreachable(
> + ? ? ?"Cannot call MipsCompilationCallback() on a non-Mips arch!");
> + ?}
> +#endif
> +}
> +
> +/// MipsCompilationCallbackC - This is the target-specific function invoked
> +/// by the function stub when we did not know the real target of a call.
> +/// This function must locate the start of the stub or call site and pass
> +/// it into the JIT compiler function.
> +extern "C" void MipsCompilationCallbackC(intptr_t StubAddr) {
> +
> + ?// Get the address of the compiled code for this function.
> + ?intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
> +
> + ?*(intptr_t *) (StubAddr) = 2 << 26 | ((NewVal & 0x0fffffff) >> 2); // J NewVal
> + ?*(intptr_t *) (StubAddr + 4) = 0; // NOP
> + ?*(intptr_t *) (StubAddr + 8) = 0; // NOP
> + ?*(intptr_t *) (StubAddr + 12) = 0; // NOP
> +
> + ?sys::Memory::InvalidateInstructionCache((void*) StubAddr, 16);
> +}
> +
> +TargetJITInfo::LazyResolverFn MipsJITInfo::getLazyResolverFunction(
> + ? ?JITCompilerFn F) {
> + ?JITCompilerFunction = F;
> + ?return MipsCompilationCallback;
> +}
> +
> +TargetJITInfo::StubLayout MipsJITInfo::getStubLayout() {
> + ?StubLayout Result = { 24, 4 }; // {Size. Alignment} (of FunctionStub)
> + ?return Result;
> +}
> +
> +void *MipsJITInfo::emitFunctionStub(const Function* F, void *Fn,
> + ? ?JITCodeEmitter &JCE) {
> + ?JCE.emitAlignment(4);
> + ?void *Addr = (void*) (JCE.getCurrentPCValue());
> +
> + ?unsigned arg0 = ((intptr_t) MipsCompilationCallback >> 16);
> + ?if ((((intptr_t) MipsCompilationCallback & 0xffff) >> 15) == 1) {
> + ? ?arg0 += 1; ?// same hack as in relocate()
> + ?}
> +
> + ?// LUI t9, %hi(MipsCompilationCallback)
> + ?JCE.emitWordLE(0xf << 26 | 25 << 16 | arg0);
> + ?// ADDiu t9, t9, %lo(MipsCompilationCallback)
> + ?JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16
> + ? ? ? ? ?| ((intptr_t) MipsCompilationCallback & 0xffff));
> + ?// JALR t8, t9
> + ?JCE.emitWordLE(25 << 21 | 24 << 11 | 9);
> + ?JCE.emitWordLE(0); ?// NOP
> +
> + ?sys::Memory::InvalidateInstructionCache((void*) Addr, 16);
> +
> + ?return Addr;
> +}
> +
> +/// relocate - Before the JIT can run a block of code that has been emitted,
> +/// it must rewrite the code to contain the actual addresses of any
> +/// referenced global symbols.
> +void MipsJITInfo::relocate(void *Function, MachineRelocation *MR,
> + ? ?unsigned NumRelocs, unsigned char* GOTBase) {
> + ?for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
> +
> + ? ?void *RelocPos = (char*) Function + MR->getMachineCodeOffset();
> + ? ?intptr_t ResultPtr = (intptr_t) MR->getResultPointer();
> +
> + ? ?switch ((Mips::RelocationType) MR->getRelocationType()) {
> + ? ?case Mips::reloc_mips_pcrel:
> + ? ? ?ResultPtr = (((ResultPtr - (intptr_t) RelocPos) - 4) >> 2) & 0xffff;
> + ? ? ?*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
> + ? ? ?break;
> +
> + ? ?case Mips::reloc_mips_j_jal: {
> + ? ? ?ResultPtr = (ResultPtr & 0x0fffffff) >> 2;
> + ? ? ?*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
> + ? ?}
> + ? ? ?break;
> +
> + ? ?case Mips::reloc_mips_hi: {
> + ? ? ?ResultPtr = ResultPtr >> 16;
> +
> + ? ? ?// see See MIPS Run Linux, chapter 9.4
> + ? ? ?if ((((intptr_t) (MR->getResultPointer()) & 0xffff) >> 15) == 1) {
> + ? ? ? ?ResultPtr += 1;
> + ? ? ?}
> +
> + ? ? ?*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
> + ? ?}
> + ? ? ?break;
> +
> + ? ?case Mips::reloc_mips_lo:
> + ? ? ?ResultPtr = ResultPtr & 0xffff;
> + ? ? ?*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
> + ? ? ?break;
> +
> + ? ?default:
> + ? ? ?assert(0 && "MipsJITInfo.unknown relocation;");
> + ? ?}
> + ?}
> +}
>
> Added: llvm/trunk/lib/Target/Mips/MipsJITInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.h?rev=135678&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsJITInfo.h (added)
> +++ llvm/trunk/lib/Target/Mips/MipsJITInfo.h Thu Jul 21 11:28:51 2011
> @@ -0,0 +1,70 @@
> +//===- MipsJITInfo.h - Mips implementation of the JIT interface -*- C++ -*-===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file contains the declaration of the MipsJITInfo class.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef MIPSJITINFO_H
> +#define MIPSJITINFO_H
> +
> +#include "MipsMachineFunction.h"
> +#include "llvm/CodeGen/MachineConstantPool.h"
> +#include "llvm/CodeGen/MachineFunction.h"
> +#include "llvm/CodeGen/MachineJumpTableInfo.h"
> +#include "llvm/Target/TargetJITInfo.h"
> +#include "llvm/ADT/DenseMap.h"
> +#include "llvm/ADT/SmallVector.h"
> +
> +namespace llvm {
> +class MipsTargetMachine;
> +
> +class MipsJITInfo : public TargetJITInfo {
> +
> + ?bool IsPIC;
> +
> + ?public:
> + ? ?explicit MipsJITInfo() :
> + ? ? ?IsPIC(false) {}
> +
> + ? ?/// replaceMachineCodeForFunction - Make it so that calling the function
> + ? ?/// whose machine code is at OLD turns into a call to NEW, perhaps by
> + ? ?/// overwriting OLD with a branch to NEW. ?This is used for self-modifying
> + ? ?/// code.
> + ? ?///
> + ? ?virtual void replaceMachineCodeForFunction(void *Old, void *New);
> +
> + ? ?// getStubLayout - Returns the size and alignment of the largest call stub
> + ? ?// on Mips.
> + ? ?virtual StubLayout getStubLayout();
> +
> + ? ?/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
> + ? ?/// small native function that simply calls the function at the specified
> + ? ?/// address.
> + ? ?virtual void *emitFunctionStub(const Function* F, void *Fn,
> + ? ? ? ?JITCodeEmitter &JCE);
> +
> + ? ?/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
> + ? ?virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
> +
> + ? ?/// relocate - Before the JIT can run a block of code that has been emitted,
> + ? ?/// it must rewrite the code to contain the actual addresses of any
> + ? ?/// referenced global symbols.
> + ? ?virtual void relocate(void *Function, MachineRelocation *MR,
> + ? ? ? ?unsigned NumRelocs, unsigned char* GOTBase);
> +
> + ? ?/// Initialize - Initialize internal stage for the function being JITted.
> + ? ?void Initialize(const MachineFunction &MF, bool isPIC) {
> + ? ? ?IsPIC = isPIC;
> + ? ?}
> +
> +};
> +}
> +
> +#endif
>
> Added: llvm/trunk/lib/Target/Mips/MipsRelocations.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRelocations.h?rev=135678&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRelocations.h (added)
> +++ llvm/trunk/lib/Target/Mips/MipsRelocations.h Thu Jul 21 11:28:51 2011
> @@ -0,0 +1,32 @@
> +//===- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===---------------------------------------------------------------------===//
> +//
> +// This file defines the Mips target-specific relocation types
> +// (for relocation-model=static).
> +//
> +//===---------------------------------------------------------------------===//
> +
> +#ifndef MIPSRELOCATIONS_H_
> +#define MIPSRELOCATIONS_H_
> +
> +#include "llvm/CodeGen/MachineRelocation.h"
> +
> +namespace llvm {
> + ?namespace Mips{
> + ? ?enum RelocationType {
> + ? ? ?reloc_mips_pcrel = 1,
> + ? ? ?reloc_mips_hi = 3,
> + ? ? ?reloc_mips_lo = 4,
> + ? ? ?reloc_mips_j_jal = 5
> + ? ?};
> + ?}
> +}
> +
> +#endif /* MIPSRELOCATIONS_H_ */
> +
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 21 11:28:51 2011
> @@ -42,7 +42,7 @@
> ? ? ? ? ? ? ?std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
> ? InstrInfo(*this),
> ? FrameLowering(Subtarget),
> - ?TLInfo(*this), TSInfo(*this) {
> + ?TLInfo(*this), TSInfo(*this), JITInfo() {
> ?}
>
> ?MipselTargetMachine::
> @@ -81,3 +81,12 @@
> ? PM.add(createMipsExpandPseudoPass(*this));
> ? return true;
> ?}
> +
> +bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenOpt::Level OptLevel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?JITCodeEmitter &JCE) {
> + ?// Machine code emitter pass for Mips.
> + ?PM.add(createMipsJITCodeEmitterPass(*this, JCE));
> + ?return false;
> +}
> +
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Thu Jul 21 11:28:51 2011
> @@ -22,6 +22,7 @@
> ?#include "llvm/Target/TargetMachine.h"
> ?#include "llvm/Target/TargetData.h"
> ?#include "llvm/Target/TargetFrameLowering.h"
> +#include "MipsJITInfo.h"
>
> ?namespace llvm {
> ? class formatted_raw_ostream;
> @@ -33,6 +34,9 @@
> ? ? MipsFrameLowering ? FrameLowering;
> ? ? MipsTargetLowering ?TLInfo;
> ? ? MipsSelectionDAGInfo TSInfo;
> + ? ?MipsJITInfo JITInfo;
> + ? ?Reloc::Model DefRelocModel; // Reloc model before it's overridden.
> +
> ? public:
> ? ? MipsTargetMachine(const Target &T, StringRef TT,
> ? ? ? ? ? ? ? ? ? ? ? StringRef CPU, StringRef FS,
> @@ -47,6 +51,9 @@
> ? ? { return &Subtarget; }
> ? ? virtual const TargetData ? ? ?*getTargetData() ? ?const
> ? ? { return &DataLayout;}
> + ? ?virtual MipsJITInfo *getJITInfo()
> + ? ?{ return &JITInfo; }
> +
>
> ? ? virtual const MipsRegisterInfo *getRegisterInfo() ?const {
> ? ? ? return &InstrInfo.getRegisterInfo();
> @@ -68,6 +75,10 @@
> ? ? virtual bool addPreRegAlloc(PassManagerBase &PM,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenOpt::Level OptLevel);
> ? ? virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
> + ? ?virtual bool addCodeEmitter(PassManagerBase &PM,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenOpt::Level OptLevel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?JITCodeEmitter &JCE);
> +
> ? };
>
> ?/// MipselTargetMachine - Mipsel target machine.
>
> Modified: llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp?rev=135678&r1=135677&r2=135678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp Thu Jul 21 11:28:51 2011
> @@ -15,7 +15,9 @@
> ?Target llvm::TheMipsTarget, llvm::TheMipselTarget;
>
> ?extern "C" void LLVMInitializeMipsTargetInfo() {
> - ?RegisterTarget X(TheMipsTarget, "mips", "Mips");
> + ?RegisterTarget + ? ? ? ?/*HasJIT=*/true> X(TheMipsTarget, "mips", "Mips");
>
> - ?RegisterTarget Y(TheMipselTarget, "mipsel", "Mipsel");
> + ?RegisterTarget + ? ? ? ?/*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
> ?}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From aggarwa4 at illinois.edu  Thu Jul 21 12:48:53 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 21 Jul 2011 17:48:53 -0000
Subject: [llvm-commits] [poolalloc] r135688 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp
Message-ID: <20110721174853.8F35F2A6C12D@llvm.org>

Author: aggarwa4
Date: Thu Jul 21 12:48:53 2011
New Revision: 135688

URL: http://llvm.org/viewvc/llvm-project?rev=135688&view=rev
Log:
Visit Instructions in dominator tree order.
Keep track of the PHI instructions added by the pass,
so as to not instrument those.


Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=135688&r1=135687&r2=135688&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jul 21 12:48:53 2011
@@ -40,6 +40,7 @@
   std::list ByValFunctions;
   std::list AddressTakenFunctions;
   std::set IndCalls;
+  std::set InsertedPHINodes;
   std::map SelectInst_MD_Map;
   std::map SelectInst_BasePtr_Map;
   std::map PHINode_MD_Map;

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=135688&r1=135687&r2=135688&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jul 21 12:48:53 2011
@@ -235,14 +235,38 @@
     Function &F = *MI;
     if(F.isDeclaration())
       continue;
+    DominatorTree & DT = getAnalysis(F);
+    std::deque Worklist;
+    Worklist.push_back (DT.getRootNode());
+    while(Worklist.size()) {
+      DomTreeNode * Node = Worklist.front();
+      Worklist.pop_front();
+      BasicBlock *BB = Node->getBlock();
+      for (BasicBlock::iterator bi = BB->begin(); bi != BB->end(); ++bi) {
+        Instruction &I = *bi;
+        if (StoreInst *SI = dyn_cast(&I)) {
+          modified |= visitStoreInst(M, *SI);
+        } else if (LoadInst *LI = dyn_cast(&I)) {
+          modified |= visitLoadInst(M, *LI);
+        } else if (CallInst *CI = dyn_cast(&I)) {
+          modified |= visitCallInst(M, *CI);
+        } else if (InvokeInst *II = dyn_cast(&I)) {
+          modified |= visitInvokeInst(M, *II);
+        } else if (AllocaInst *AI = dyn_cast(&I)) {
+          modified |= visitAllocaInst(M, *AI);
+        } else if (VAArgInst *VI = dyn_cast(&I)) {
+          modified |= visitVAArgInst(M, *VI);
+        }
+      }
+      Worklist.insert(Worklist.end(), Node->begin(), Node->end());
+    }
 
     // Loop over all of the instructions in the function,
     // adding instrumentation where needed.
-    for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE;++II) {
+    /*for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE;++II) {
       Instruction &I = *II;
       if (StoreInst *SI = dyn_cast(&I)) {
-        if(!isa(SI->getOperand(0)))
-          modified |= visitStoreInst(M, *SI);
+        modified |= visitStoreInst(M, *SI);
       } else if (LoadInst *LI = dyn_cast(&I)) {
         modified |= visitLoadInst(M, *LI);
       } else if (CallInst *CI = dyn_cast(&I)) {
@@ -254,7 +278,7 @@
       } else if (VAArgInst *VI = dyn_cast(&I)) {
         modified |= visitVAArgInst(M, *VI);
       }
-    }
+    }*/
   }
 
   // visit all the indirect call sites
@@ -2128,11 +2152,17 @@
         Prev = PHINode_MD_Map[PH];
         PrevBasePtr = PHINode_BasePtr_Map[PH];
       }
+      if(InsertedPHINodes.find(PH) != InsertedPHINodes.end())
+        continue;
+      /*if(isa(I)) {
+        std::string name = PH->getName();
+        if (strncmp(name.c_str(), "baseptr.", 8) == 0) continue;
+      }*/
       PHINode *AI_New;
       PHINode *BCI_New;
       if(!Prev) {
         AI_New = PHINode::Create(AI->getType(),  PH->getNameStr() + ".md", PH);
-        BCI_New = PHINode::Create(BCI->getType(),  PH->getNameStr() + ".baseptr", PH);
+        BCI_New = PHINode::Create(BCI->getType(),PH->getNameStr() + ".baseptr", PH);
         for(unsigned c = 0; c < PH->getNumIncomingValues(); c++) {
           if(PH->getIncomingValue(c) == I) {
             AI_New->addIncoming(AI, PH->getIncomingBlock(c));
@@ -2142,9 +2172,11 @@
             AI_New->addIncoming(Constant::getNullValue(AI->getType()), PH->getIncomingBlock(c));
             BCI_New->addIncoming(Constant::getNullValue(BCI->getType()), PH->getIncomingBlock(c));
           }
-          PHINode_MD_Map[PH] = AI_New;
-          PHINode_BasePtr_Map[PH] = BCI_New;
         }
+        PHINode_MD_Map[PH] = AI_New;
+        PHINode_BasePtr_Map[PH] = BCI_New;
+        InsertedPHINodes.insert(AI_New);
+        InsertedPHINodes.insert(BCI_New);
         visitUses(PH, AI_New, BCI_New);
       }
       else {
@@ -2172,6 +2204,9 @@
 
 // Insert runtime checks before all store instructions.
 bool TypeChecks::visitStoreInst(Module &M, StoreInst &SI) {
+  if(isa(SI.getOperand(0)->stripPointerCasts())) {
+    return false;
+  }
   if(PHINode *PH = dyn_cast(SI.getOperand(0)->stripPointerCasts())) {
     if(PHINode_MD_Map.find(PH) != PHINode_MD_Map.end())
       return false;



From resistor at mac.com  Thu Jul 21 13:54:16 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 21 Jul 2011 18:54:16 -0000
Subject: [llvm-commits] [llvm] r135693 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp
 lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 utils/TableGen/EDEmitter.cpp
Message-ID: <20110721185416.DAA6E2A6C12D@llvm.org>

Author: resistor
Date: Thu Jul 21 13:54:16 2011
New Revision: 135693

URL: http://llvm.org/viewvc/llvm-project?rev=135693&view=rev
Log:
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates.  This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=135693&r1=135692&r2=135693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul 21 13:54:16 2011
@@ -172,7 +172,7 @@
       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
+                         get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
         .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
         .addImm(Pred).addReg(0).addReg(0);
     } else

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=135693&r1=135692&r2=135693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Jul 21 13:54:16 2011
@@ -741,7 +741,8 @@
       MI.eraseFromParent();
       return true;
     }
-    case ARM::MOVCCs: {
+    case ARM::MOVCCsi:
+    case ARM::MOVCCsr: {
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
               (MI.getOperand(1).getReg()))
         .addReg(MI.getOperand(2).getReg(),

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=135693&r1=135692&r2=135693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Jul 21 13:54:16 2011
@@ -90,13 +90,20 @@
   bool hasNoVMLxHazardUse(SDNode *N) const;
   bool isShifterOpProfitable(const SDValue &Shift,
                              ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
-  bool SelectShifterOperandReg(SDValue N, SDValue &A,
+  bool SelectRegShifterOperand(SDValue N, SDValue &A,
+                               SDValue &B, SDValue &C,
+                               bool CheckProfitability = true);
+  bool SelectImmShifterOperand(SDValue N, SDValue &A,
                                SDValue &B, SDValue &C,
                                bool CheckProfitability = true);
   bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
                                     SDValue &B, SDValue &C) {
     // Don't apply the profitability check
-    return SelectShifterOperandReg(N, A, B, C, false);
+    if (SelectImmShifterOperand(N, A, B, C, false))
+      return true;
+    else if (SelectRegShifterOperand(N, A, B, C, false))
+      return true;
+    return false;
   }
 
   bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
@@ -365,7 +372,7 @@
   return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
 }
 
-bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
+bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
                                               SDValue &BaseReg,
                                               SDValue &ShReg,
                                               SDValue &Opc,
@@ -381,19 +388,43 @@
 
   BaseReg = N.getOperand(0);
   unsigned ShImmVal = 0;
-  if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) {
-    ShReg = CurDAG->getRegister(0, MVT::i32);
-    ShImmVal = RHS->getZExtValue() & 31;
-  } else {
-    ShReg = N.getOperand(1);
-    if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
-      return false;
-  }
+  ConstantSDNode *RHS = dyn_cast(N.getOperand(1));
+  if (!RHS) return false;
+  ShReg = CurDAG->getRegister(0, MVT::i32);
+  ShImmVal = RHS->getZExtValue() & 31;
   Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
                                   MVT::i32);
   return true;
 }
 
+bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
+                                              SDValue &BaseReg,
+                                              SDValue &ShReg,
+                                              SDValue &Opc,
+                                              bool CheckProfitability) {
+  if (DisableShifterOp)
+    return false;
+
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
+
+  // Don't match base register only case. That is matched to a separate
+  // lower complexity pattern with explicit register operand.
+  if (ShOpcVal == ARM_AM::no_shift) return false;
+
+  BaseReg = N.getOperand(0);
+  unsigned ShImmVal = 0;
+  ConstantSDNode *RHS = dyn_cast(N.getOperand(1));
+  if (RHS) return false;
+
+  ShReg = N.getOperand(1);
+  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
+    return false;
+  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
+                                  MVT::i32);
+  return true;
+}
+
+
 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
                                           SDValue &Base,
                                           SDValue &OffImm) {
@@ -2036,10 +2067,16 @@
   SDValue CPTmp0;
   SDValue CPTmp1;
   SDValue CPTmp2;
-  if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
+  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
+    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
+    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
+    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 7);
+  }
+
+  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
     SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
     SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
-    return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
+    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
   }
   return 0;
 }
@@ -2309,7 +2346,7 @@
           return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
         } else {
           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
-          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
+          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
         }
       }
       if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
@@ -2325,7 +2362,7 @@
           return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
         } else {
           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
-          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
+          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
         }
       }
     }

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=135693&r1=135692&r2=135693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jul 21 13:54:16 2011
@@ -5224,15 +5224,19 @@
 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
   {ARM::ADCSri, ARM::ADCri},
   {ARM::ADCSrr, ARM::ADCrr},
-  {ARM::ADCSrs, ARM::ADCrs},
+  {ARM::ADCSrsi, ARM::ADCrsi},
+  {ARM::ADCSrsr, ARM::ADCrsr},
   {ARM::SBCSri, ARM::SBCri},
   {ARM::SBCSrr, ARM::SBCrr},
-  {ARM::SBCSrs, ARM::SBCrs},
+  {ARM::SBCSrsi, ARM::SBCrsi},
+  {ARM::SBCSrsr, ARM::SBCrsr},
   {ARM::RSBSri, ARM::RSBri},
   {ARM::RSBSrr, ARM::RSBrr},
-  {ARM::RSBSrs, ARM::RSBrs},
+  {ARM::RSBSrsi, ARM::RSBrsi},
+  {ARM::RSBSrsr, ARM::RSBrsr},
   {ARM::RSCSri, ARM::RSCri},
-  {ARM::RSCSrs, ARM::RSCrs},
+  {ARM::RSCSrsi, ARM::RSCrsi},
+  {ARM::RSCSrsr, ARM::RSCrsr},
   {ARM::t2ADCSri, ARM::t2ADCri},
   {ARM::t2ADCSrr, ARM::t2ADCrr},
   {ARM::t2ADCSrs, ARM::t2ADCrs},

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135693&r1=135692&r2=135693&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 21 13:54:16 2011
@@ -423,15 +423,29 @@
   let Name = "ShiftedReg";
 }
 
-// shifter_operand operands: so_reg and so_imm.
-def so_reg : Operand,    // reg reg imm
-             ComplexPattern {
+def ShiftedImmAsmOperand : AsmOperandClass {
+  let Name = "ShiftedImm";
+}
+
+// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
+def so_reg_reg : Operand,  // reg reg imm
+                 ComplexPattern {
   let EncoderMethod = "getSORegOpValue";
   let PrintMethod = "printSORegOperand";
   let ParserMatchClass = ShiftedRegAsmOperand;
   let MIOperandInfo = (ops GPR, GPR, shift_imm);
 }
+
+def so_reg_imm : Operand, // reg imm
+                 ComplexPattern {
+  let EncoderMethod = "getSORegOpValue";
+  let PrintMethod = "printSORegOperand";
+  let ParserMatchClass = ShiftedImmAsmOperand;
+  let MIOperandInfo = (ops GPR, GPR, shift_imm);
+}
+
 // FIXME: Does this need to be distinct from so_reg?
 def shift_so_reg : Operand,    // reg reg imm
                    ComplexPattern {
+    bits<4> Rd;
+    bits<4> Rn;
+    bits<12> shift;
+    let Inst{25} = 0;
+    let Inst{19-16} = Rn;
+    let Inst{15-12} = Rd;
+    let Inst{11-5} = shift{11-5};
+    let Inst{4} = 0;
+    let Inst{3-0} = shift{3-0};
+  }
+
+  def rsr : AsI1 {
+               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> shift;
     let Inst{25} = 0;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
-    let Inst{11-0} = shift;
+    let Inst{11-8} = shift{11-8};
+    let Inst{7} = 0;
+    let Inst{6-5} = shift{6-5};
+    let Inst{4} = 1;
+    let Inst{3-0} = shift{3-0};
   }
 
   // Assembly aliases for optional destination operand when it's the same
@@ -780,10 +815,16 @@
                                                     cc_out:$s)>,
      Requires<[IsARM]>;
   def : InstAlias(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
-                                                    so_reg:$shift, pred:$p,
+     (!cast(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
+                                                    so_reg_imm:$shift, pred:$p,
                                                     cc_out:$s)>,
      Requires<[IsARM]>;
+  def : InstAlias(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
+                                                    so_reg_reg:$shift, pred:$p,
+                                                    cc_out:$s)>,
+     Requires<[IsARM]>;
+
 }
 
 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
@@ -818,9 +859,10 @@
     let Inst{11-4} = 0b00000000;
     let Inst{3-0} = Rm;
   }
-  def rs : AI1 {
+               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> shift;
@@ -828,7 +870,27 @@
     let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
-    let Inst{11-0} = shift;
+    let Inst{11-5} = shift{11-5};
+    let Inst{4} = 0;
+    let Inst{3-0} = shift{3-0};
+  }
+
+    def rsr : AI1 {
+    bits<4> Rd;
+    bits<4> Rn;
+    bits<12> shift;
+    let Inst{25} = 0;
+    let Inst{20} = 1;
+    let Inst{19-16} = Rn;
+    let Inst{15-12} = Rd;
+    let Inst{11-8} = shift{11-8};
+    let Inst{7} = 0;
+    let Inst{6-5} = shift{6-5};
+    let Inst{4} = 1;
+    let Inst{3-0} = shift{3-0};
   }
 }
 }
@@ -864,17 +926,37 @@
     let Inst{11-4} = 0b00000000;
     let Inst{3-0} = Rm;
   }
-  def rs : AI1 {
+    bits<4> Rn;
+    bits<12> shift;
+    let Inst{25} = 0;
+    let Inst{20} = 1;
+    let Inst{19-16} = Rn;
+    let Inst{15-12} = 0b0000;
+    let Inst{11-5} = shift{11-5};
+    let Inst{4} = 0;
+    let Inst{3-0} = shift{3-0};
+  }
+  def rsr : AI1 {
+               [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
     bits<4> Rn;
     bits<12> shift;
     let Inst{25} = 0;
     let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = 0b0000;
-    let Inst{11-0} = shift;
+    let Inst{11-8} = shift{11-8};
+    let Inst{7} = 0;
+    let Inst{6-5} = shift{6-5};
+    let Inst{4} = 1;
+    let Inst{3-0} = shift{3-0};
   }
+
 }
 }
 
@@ -1009,17 +1091,37 @@
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
   }
-  def rs : AsI1,
+               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
                Requires<[IsARM]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> shift;
     let Inst{25} = 0;
-    let Inst{11-0} = shift;
+    let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
+    let Inst{11-5} = shift{11-5};
+    let Inst{4} = 0;
+    let Inst{3-0} = shift{3-0};
+  }
+  def rsr : AsI1,
+               Requires<[IsARM]> {
+    bits<4> Rd;
+    bits<4> Rn;
+    bits<12> shift;
+    let Inst{25} = 0;
     let Inst{19-16} = Rn;
+    let Inst{15-12} = Rd;
+    let Inst{11-8} = shift{11-8};
+    let Inst{7} = 0;
+    let Inst{6-5} = shift{6-5};
+    let Inst{4} = 1;
+    let Inst{3-0} = shift{3-0};
   }
   }
   // Assembly aliases for optional destination operand when it's the same
@@ -1035,8 +1137,13 @@
                                                     cc_out:$s)>,
      Requires<[IsARM]>;
   def : InstAlias(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
-                                                    so_reg:$shift, pred:$p,
+     (!cast(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
+                                                    so_reg_imm:$shift, pred:$p,
+                                                    cc_out:$s)>,
+     Requires<[IsARM]>;
+  def : InstAlias(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
+                                                    so_reg_reg:$shift, pred:$p,
                                                     cc_out:$s)>,
      Requires<[IsARM]>;
 }
@@ -1053,9 +1160,12 @@
                [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
     let isCommutable = Commutable;
   }
-  def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+  def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
                4, IIC_iALUsr,
-               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
+               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
+  def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
+               4, IIC_iALUsr,
+               [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
 }
 }
 
@@ -2338,16 +2448,34 @@
   let Inst{19-16} = Rn;
 }
 
-def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
                  DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
-                 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
+                 [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<12> shift;
   let Inst{25} = 0;
-  let Inst{11-0} = shift;
+  let Inst{19-16} = Rn;
   let Inst{15-12} = Rd;
+  let Inst{11-5} = shift{11-5};
+  let Inst{4} = 0;
+  let Inst{3-0} = shift{3-0};
+}
+
+def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
+                 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
+                 [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> shift;
+  let Inst{25} = 0;
   let Inst{19-16} = Rn;
+  let Inst{15-12} = Rd;
+  let Inst{11-8} = shift{11-8};
+  let Inst{7} = 0;
+  let Inst{6-5} = shift{6-5};
+  let Inst{4} = 1;
+  let Inst{3-0} = shift{3-0};
 }
 
 // RSB with 's' bit set.
@@ -2359,9 +2487,12 @@
 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
                  4, IIC_iALUr,
                  [/* For disassembly only; pattern left blank */]>;
-def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
                  4, IIC_iALUsr,
-                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
+                 [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>;
+def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
+                 4, IIC_iALUsr,
+                 [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>;
 }
 
 let Uses = [CPSR] in {
@@ -2391,28 +2522,50 @@
   let Inst{15-12} = Rd;
   let Inst{19-16} = Rn;
 }
-def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
                  DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
-                 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
+                 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>,
                  Requires<[IsARM]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<12> shift;
   let Inst{25} = 0;
-  let Inst{11-0} = shift;
+  let Inst{19-16} = Rn;
   let Inst{15-12} = Rd;
+  let Inst{11-5} = shift{11-5};
+  let Inst{4} = 0;
+  let Inst{3-0} = shift{3-0};
+}
+def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
+                 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
+                 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>,
+                 Requires<[IsARM]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> shift;
+  let Inst{25} = 0;
   let Inst{19-16} = Rn;
+  let Inst{15-12} = Rd;
+  let Inst{11-8} = shift{11-8};
+  let Inst{7} = 0;
+  let Inst{6-5} = shift{6-5};
+  let Inst{4} = 1;
+  let Inst{3-0} = shift{3-0};
 }
 }
 
+
 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
 let usesCustomInserter = 1, Uses = [CPSR] in {
 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
                   4, IIC_iALUi,
                   [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
-def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
+                  4, IIC_iALUsr,
+                [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>;
+def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
                   4, IIC_iALUsr,
-                  [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
+                [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>;
 }
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
@@ -2684,15 +2837,31 @@
   let Inst{15-12} = Rd;
   let Inst{3-0} = Rm;
 }
-def  MVNs  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
+def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), DPSoRegFrm,
                   IIC_iMVNsr, "mvn", "\t$Rd, $shift",
-                  [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
+                  [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
   bits<4> Rd;
   bits<12> shift;
   let Inst{25} = 0;
   let Inst{19-16} = 0b0000;
   let Inst{15-12} = Rd;
-  let Inst{11-0} = shift;
+  let Inst{11-5} = shift{11-5};
+  let Inst{4} = 0;
+  le