From baldrick at free.fr Mon Jul 25 02:56:56 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 07:56:56 -0000 Subject: [llvm-commits] [dragonegg] r135900 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110725075656.4100E2A6C12F@llvm.org> Author: baldrick Date: Mon Jul 25 02:56:56 2011 New Revision: 135900 URL: http://llvm.org/viewvc/llvm-project?rev=135900&view=rev Log: Port commits 135235 and 135814 (evancheng) from llvm-gcc. Original changelog entries: Initialize MCAsmInfo. Match LLVM API change. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=135900&r1=135899&r2=135900&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Mon Jul 25 02:56:56 2011 @@ -268,6 +268,7 @@ #define Declare(T, M) Declare2(T, M) Declare(LLVM_TARGET_NAME, TargetInfo); Declare(LLVM_TARGET_NAME, Target); + Declare(LLVM_TARGET_NAME, TargetMC); Declare(LLVM_TARGET_NAME, AsmPrinter); #undef Declare #undef Declare2 @@ -280,6 +281,7 @@ #define DoInit(T, M) DoInit2(T, M) DoInit(LLVM_TARGET_NAME, TargetInfo); DoInit(LLVM_TARGET_NAME, Target); + DoInit(LLVM_TARGET_NAME, TargetMC); DoInit(LLVM_TARGET_NAME, AsmPrinter); #undef DoInit #undef DoInit2 From baldrick at free.fr Mon Jul 25 03:25:12 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 08:25:12 -0000 Subject: [llvm-commits] [dragonegg] r135901 - in /dragonegg/trunk: include/darwin/dragonegg/OS.h include/freebsd/dragonegg/OS.h include/linux/dragonegg/OS.h include/openbsd/dragonegg/OS.h src/Backend.cpp Message-ID: <20110725082512.2B8E22A6C12C@llvm.org> Author: baldrick Date: Mon Jul 25 03:25:11 2011 New Revision: 135901 URL: http://llvm.org/viewvc/llvm-project?rev=135901&view=rev Log: Port commit 135470 (evancheng) from llvm-gcc. Original changelog entry: Match createTargetMachine API change. Modified: dragonegg/trunk/include/darwin/dragonegg/OS.h dragonegg/trunk/include/freebsd/dragonegg/OS.h dragonegg/trunk/include/linux/dragonegg/OS.h dragonegg/trunk/include/openbsd/dragonegg/OS.h dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/include/darwin/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/darwin/dragonegg/OS.h?rev=135901&r1=135900&r2=135901&view=diff ============================================================================== --- dragonegg/trunk/include/darwin/dragonegg/OS.h (original) +++ dragonegg/trunk/include/darwin/dragonegg/OS.h Mon Jul 25 03:25:11 2011 @@ -25,23 +25,23 @@ /* Darwin X86-64 only supports PIC code generation. */ #if defined (TARGET_386) -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if ((TARGET_64BIT) || flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static") +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if ((TARGET_64BIT) || flag_pic) \ + RelocModel = Reloc::PIC_; \ + else if (!MACHO_DYNAMIC_NO_PIC_P) \ + RelocModel = Reloc::Static; #elif defined (TARGET_ARM) -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static"); \ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else if (!MACHO_DYNAMIC_NO_PIC_P) \ + RelocModel = Reloc::Static; \ #else /* !TARGET_386 && !TARGET_ARM */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else if (!MACHO_DYNAMIC_NO_PIC_P) \ - argvec.push_back ("--relocation-model=static") +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else if (!MACHO_DYNAMIC_NO_PIC_P) \ + RelocModel = Reloc::Static; #endif /* !TARGET_386 && !TARGET_ARM */ /* Give a constant string a sufficient alignment for the platform. */ Modified: dragonegg/trunk/include/freebsd/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/freebsd/dragonegg/OS.h?rev=135901&r1=135900&r2=135901&view=diff ============================================================================== --- dragonegg/trunk/include/freebsd/dragonegg/OS.h (original) +++ dragonegg/trunk/include/freebsd/dragonegg/OS.h Mon Jul 25 03:25:11 2011 @@ -24,10 +24,10 @@ #define DRAGONEGG_OS_H /* Yes, we support PIC codegen for FreeBSD targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else \ - argvec.push_back ("--relocation-model=static"); +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else \ + RelocModel = Reloc::Static; #endif /* DRAGONEGG_OS_H */ Modified: dragonegg/trunk/include/linux/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/linux/dragonegg/OS.h?rev=135901&r1=135900&r2=135901&view=diff ============================================================================== --- dragonegg/trunk/include/linux/dragonegg/OS.h (original) +++ dragonegg/trunk/include/linux/dragonegg/OS.h Mon Jul 25 03:25:11 2011 @@ -24,10 +24,10 @@ #define DRAGONEGG_OS_H /* Yes, we support PIC codegen for linux targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else \ - argvec.push_back ("--relocation-model=static"); +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else \ + RelocModel = Reloc::Static; #endif /* DRAGONEGG_OS_H */ Modified: dragonegg/trunk/include/openbsd/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/openbsd/dragonegg/OS.h?rev=135901&r1=135900&r2=135901&view=diff ============================================================================== --- dragonegg/trunk/include/openbsd/dragonegg/OS.h (original) +++ dragonegg/trunk/include/openbsd/dragonegg/OS.h Mon Jul 25 03:25:11 2011 @@ -24,10 +24,10 @@ #define DRAGONEGG_OS_H /* Yes, we support PIC codegen for OpenBSD targets! */ -#define LLVM_SET_TARGET_OPTIONS(argvec) \ - if (flag_pic) \ - argvec.push_back ("--relocation-model=pic"); \ - else \ - argvec.push_back ("--relocation-model=static"); +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else \ + RelocModel = Reloc::Static; #endif /* DRAGONEGG_OS_H */ Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=135901&r1=135900&r2=135901&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Mon Jul 25 03:25:11 2011 @@ -39,6 +39,7 @@ #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/PassManagerBuilder.h" @@ -413,7 +414,15 @@ LLVM_SET_SUBTARGET_FEATURES(CPU, Features); FeatureStr = Features.getString(); #endif - TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr); + + // The target can set LLVM_SET_RELOC_MODEL to configure the relocation + // model used by the LLVM backend. + Reloc::Model RelocModel = Reloc::Default; +#ifdef LLVM_SET_RELOC_MODEL + LLVM_SET_RELOC_MODEL(RelocModel); +#endif + TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr, + RelocModel); TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); } From baldrick at free.fr Mon Jul 25 03:30:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 08:30:44 -0000 Subject: [llvm-commits] [dragonegg] r135902 - /dragonegg/trunk/src/Debug.cpp Message-ID: <20110725083044.8A23D2A6C12C@llvm.org> Author: baldrick Date: Mon Jul 25 03:30:44 2011 New Revision: 135902 URL: http://llvm.org/viewvc/llvm-project?rev=135902&view=rev Log: Port commit 135505 (dpatel) from llvm-gcc. Original changelog entry: Update DebugFactory to match r135504. Modified: dragonegg/trunk/src/Debug.cpp Modified: dragonegg/trunk/src/Debug.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=135902&r1=135901&r2=135902&view=diff ============================================================================== --- dragonegg/trunk/src/Debug.cpp (original) +++ dragonegg/trunk/src/Debug.cpp Mon Jul 25 03:30:44 2011 @@ -1645,7 +1645,8 @@ F, ConstantInt::get(Type::getInt32Ty(VMContext), LineNo), Ty, - ConstantInt::get(Type::getInt32Ty(VMContext), Flags) + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), + Constant::getNullValue(Type::getInt32Ty(VMContext)) }; MDNode *Node = MDNode::get(VMContext, Elts); if (AlwaysPreserve) { @@ -1682,6 +1683,8 @@ Elts.push_back(F); Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)); Elts.push_back(Ty); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); Elts.append(Addr, Addr+NumAddr); return DIVariable(MDNode::get(VMContext, Elts)); From baldrick at free.fr Mon Jul 25 03:49:56 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 08:49:56 -0000 Subject: [llvm-commits] [dragonegg] r135903 - in /dragonegg/trunk: include/x86/dragonegg/Target.h src/Backend.cpp Message-ID: <20110725084956.373512A6C12C@llvm.org> Author: baldrick Date: Mon Jul 25 03:49:56 2011 New Revision: 135903 URL: http://llvm.org/viewvc/llvm-project?rev=135903&view=rev Log: Port commits 135588 (evancheng), 135589 (evancheng) and 135618 (efriedma) from llvm-gcc. Original changelog entries: Unbreak llvm-c build. CM_32 means default code mode. Attempt to unbreak llvm-gcc. Modified: dragonegg/trunk/include/x86/dragonegg/Target.h dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/include/x86/dragonegg/Target.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/x86/dragonegg/Target.h?rev=135903&r1=135902&r2=135903&view=diff ============================================================================== --- dragonegg/trunk/include/x86/dragonegg/Target.h (original) +++ dragonegg/trunk/include/x86/dragonegg/Target.h Mon Jul 25 03:49:56 2011 @@ -371,33 +371,39 @@ #define LLVM_CANONICAL_ADDRESS_CONSTRAINTS "im" /* Propagate code model setting to backend */ -#define LLVM_SET_MACHINE_OPTIONS(argvec) \ - do { \ - switch (ix86_cmodel) { \ - default: \ - sorry ("code model %<%s%> not supported yet", \ - ix86_cmodel_string); \ - break; \ - case CM_SMALL: \ - case CM_SMALL_PIC: \ - argvec.push_back("--code-model=small"); \ - break; \ - case CM_KERNEL: \ - argvec.push_back("--code-model=kernel"); \ - break; \ - case CM_MEDIUM: \ - case CM_MEDIUM_PIC: \ - argvec.push_back("--code-model=medium"); \ - break; \ - case CM_32: \ - argvec.push_back("--code-model=default"); \ - break; \ - } \ - if (TARGET_OMIT_LEAF_FRAME_POINTER) \ - argvec.push_back("--disable-non-leaf-fp-elim"); \ - \ - if (ix86_force_align_arg_pointer) \ - argvec.push_back("-force-align-stack"); \ +#define LLVM_SET_CODE_MODEL(CMModel) \ + switch (ix86_cmodel) { \ + default: \ + sorry ("code model %<%s%> not supported yet", \ + ix86_cmodel_string); \ + break; \ + case CM_32: \ + CMModel = CodeModel::Default; \ + break; \ + case CM_SMALL: \ + case CM_SMALL_PIC: \ + CMModel = CodeModel::Small; \ + break; \ + case CM_KERNEL: \ + CMModel = CodeModel::Kernel; \ + break; \ + case CM_MEDIUM: \ + case CM_MEDIUM_PIC: \ + CMModel = CodeModel::Medium; \ + break; \ + case CM_LARGE: \ + case CM_LARGE_PIC: \ + CMModel = CodeModel::Large; \ + break; \ + } + +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ + do { \ + if (TARGET_OMIT_LEAF_FRAME_POINTER) \ + argvec.push_back("--disable-non-leaf-fp-elim"); \ + \ + if (ix86_force_align_arg_pointer) \ + argvec.push_back("-force-align-stack"); \ } while (0) #endif /* DRAGONEGG_TARGET_H */ Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=135903&r1=135902&r2=135903&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Mon Jul 25 03:49:56 2011 @@ -415,14 +415,22 @@ FeatureStr = Features.getString(); #endif - // The target can set LLVM_SET_RELOC_MODEL to configure the relocation - // model used by the LLVM backend. + // The target can set LLVM_SET_RELOC_MODEL to configure the relocation model + // used by the LLVM backend. Reloc::Model RelocModel = Reloc::Default; #ifdef LLVM_SET_RELOC_MODEL LLVM_SET_RELOC_MODEL(RelocModel); #endif + + // The target can set LLVM_SET_CODE_MODEL to configure the code model used + // used by the LLVM backend. + CodeModel::Model CMModel = CodeModel::Default; +#ifdef LLVM_SET_CODE_MODEL + LLVM_SET_CODE_MODEL(CMModel); +#endif + TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr, - RelocModel); + RelocModel, CMModel); TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); } From baldrick at free.fr Mon Jul 25 03:58:59 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 10:58:59 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r134830 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386.cpp llvm-backend.cpp llvm-convert.cpp llvm-internal.h llvm-linker-hack.cpp llvm-types.cpp In-Reply-To: <6C807505-3D89-4D8A-BE78-312737C0A76D@apple.com> References: <20110709174147.53C2E2A6C12C@llvm.org> <4E2C4BEF.3000503@free.fr> <6C807505-3D89-4D8A-BE78-312737C0A76D@apple.com> Message-ID: <4E2D3053.6000403@free.fr> Hi Chris, ... >> do you remember what this is about? Do you have a testcase? > > I don't have a testcase. IIRC, the ObjC frontend was making metadata whose initializer had a different type than the global variable backing it. I think it must have been more complicated than that, since that case should already be handled. Probably the dragonegg testsuite will allow me to reproduce the problem if it still exists. If it doesn't I don't care enough about ObjC to do anything more :) Ciao, Duncan. From baldrick at free.fr Mon Jul 25 03:59:39 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 10:59:39 +0200 Subject: [llvm-commits] Fwd: [llvm-gcc-4.2] r135505 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp In-Reply-To: <01EF41C1-2E50-4202-A042-02AE98E12CE8@apple.com> References: <20110719194214.CB8E92A6C12D@llvm.org> <01EF41C1-2E50-4202-A042-02AE98E12CE8@apple.com> Message-ID: <4E2D307B.2050802@free.fr> Hi Devang, > Please apply this patch to dragon-egg also. This is required to match > corresponding change in llvm. I did, thanks! Ciao, Duncan. From jay.foad at gmail.com Mon Jul 25 04:48:08 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 25 Jul 2011 09:48:08 -0000 Subject: [llvm-commits] [llvm] r135904 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Support/ lib/Analysis/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Instrumentation/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ unittests/Transforms/Utils/ Message-ID: <20110725094809.6199A2A6C12C@llvm.org> Author: foad Date: Mon Jul 25 04:48:08 2011 New Revision: 135904 URL: http://llvm.org/viewvc/llvm-project?rev=135904&view=rev Log: Convert GetElementPtrInst to use ArrayRef. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/Support/IRBuilder.h llvm/trunk/include/llvm/Support/NoFolder.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/lib/Analysis/PHITransAddr.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/unittests/Transforms/Utils/Cloning.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Jul 25 04:48:08 2011 @@ -639,6 +639,9 @@
  • FindInsertedValue (in llvm/Analysis/ValueTracking.h)
  • gep_type_begin (in llvm/Support/GetElementPtrTypeIterator.h)
  • gep_type_end (in llvm/Support/GetElementPtrTypeIterator.h)
    • +
  • GetElementPtrInst::Create
    • +
  • GetElementPtrInst::CreateInBounds
    • +
  • GetElementPtrInst::getIndexedType
  • InsertValueInst::Create
  • InsertValueInst::getIndices
  • InvokeInst::Create
    • Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Jul 25 04:48:08 2011 @@ -285,149 +285,51 @@ /// class GetElementPtrInst : public Instruction { GetElementPtrInst(const GetElementPtrInst &GEPI); - void init(Value *Ptr, Value* const *Idx, unsigned NumIdx, - const Twine &NameStr); - void init(Value *Ptr, Value *Idx, const Twine &NameStr); - - template - void init(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - const Twine &NameStr, - // This argument ensures that we have an iterator we can - // do arithmetic on in constant time - std::random_access_iterator_tag) { - unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); - - if (NumIdx > 0) { - // This requires that the iterator points to contiguous memory. - init(Ptr, &*IdxBegin, NumIdx, NameStr); // FIXME: for the general case - // we have to build an array here - } - else { - init(Ptr, 0, NumIdx, NameStr); - } - } - - /// getIndexedType - Returns the type of the element that would be loaded with - /// a load instruction with the specified parameters. - /// - /// Null is returned if the indices are invalid for the specified - /// pointer type. - /// - template - static Type *getIndexedType(Type *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - // This argument ensures that we - // have an iterator we can do - // arithmetic on in constant time - std::random_access_iterator_tag) { - unsigned NumIdx = static_cast(std::distance(IdxBegin, IdxEnd)); - - if (NumIdx > 0) - // This requires that the iterator points to contiguous memory. - return getIndexedType(Ptr, &*IdxBegin, NumIdx); - else - return getIndexedType(Ptr, (Value *const*)0, NumIdx); - } + void init(Value *Ptr, ArrayRef IdxList, const Twine &NameStr); /// Constructors - Create a getelementptr instruction with a base pointer an /// list of indices. The first ctor can optionally insert before an existing /// instruction, the second appends the new instruction to the specified /// BasicBlock. - template - inline GetElementPtrInst(Value *Ptr, RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - unsigned Values, - const Twine &NameStr, + inline GetElementPtrInst(Value *Ptr, ArrayRef IdxList, + unsigned Values, const Twine &NameStr, Instruction *InsertBefore); - template - inline GetElementPtrInst(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - unsigned Values, - const Twine &NameStr, BasicBlock *InsertAtEnd); - - /// Constructors - These two constructors are convenience methods because one - /// and two index getelementptr instructions are so common. - GetElementPtrInst(Value *Ptr, Value *Idx, const Twine &NameStr = "", - Instruction *InsertBefore = 0); - GetElementPtrInst(Value *Ptr, Value *Idx, - const Twine &NameStr, BasicBlock *InsertAtEnd); + inline GetElementPtrInst(Value *Ptr, ArrayRef IdxList, + unsigned Values, const Twine &NameStr, + BasicBlock *InsertAtEnd); protected: virtual GetElementPtrInst *clone_impl() const; public: - template - static GetElementPtrInst *Create(Value *Ptr, RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, + static GetElementPtrInst *Create(Value *Ptr, ArrayRef IdxList, const Twine &NameStr = "", Instruction *InsertBefore = 0) { - typename std::iterator_traits::difference_type - Values = 1 + std::distance(IdxBegin, IdxEnd); + unsigned Values = 1 + unsigned(IdxList.size()); return new(Values) - GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertBefore); + GetElementPtrInst(Ptr, IdxList, Values, NameStr, InsertBefore); } - template - static GetElementPtrInst *Create(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, + static GetElementPtrInst *Create(Value *Ptr, ArrayRef IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) { - typename std::iterator_traits::difference_type - Values = 1 + std::distance(IdxBegin, IdxEnd); + unsigned Values = 1 + unsigned(IdxList.size()); return new(Values) - GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertAtEnd); - } - - /// Constructors - These two creators are convenience methods because one - /// index getelementptr instructions are so common. - static GetElementPtrInst *Create(Value *Ptr, Value *Idx, - const Twine &NameStr = "", - Instruction *InsertBefore = 0) { - return new(2) GetElementPtrInst(Ptr, Idx, NameStr, InsertBefore); - } - static GetElementPtrInst *Create(Value *Ptr, Value *Idx, - const Twine &NameStr, - BasicBlock *InsertAtEnd) { - return new(2) GetElementPtrInst(Ptr, Idx, NameStr, InsertAtEnd); + GetElementPtrInst(Ptr, IdxList, Values, NameStr, InsertAtEnd); } /// Create an "inbounds" getelementptr. See the documentation for the /// "inbounds" flag in LangRef.html for details. - template static GetElementPtrInst *CreateInBounds(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, + ArrayRef IdxList, const Twine &NameStr = "", Instruction *InsertBefore = 0) { - GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd, - NameStr, InsertBefore); + GetElementPtrInst *GEP = Create(Ptr, IdxList, NameStr, InsertBefore); GEP->setIsInBounds(true); return GEP; } - template static GetElementPtrInst *CreateInBounds(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, - const Twine &NameStr, - BasicBlock *InsertAtEnd) { - GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd, - NameStr, InsertAtEnd); - GEP->setIsInBounds(true); - return GEP; - } - static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx, - const Twine &NameStr = "", - Instruction *InsertBefore = 0) { - GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertBefore); - GEP->setIsInBounds(true); - return GEP; - } - static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx, + ArrayRef IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) { - GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertAtEnd); + GetElementPtrInst *GEP = Create(Ptr, IdxList, NameStr, InsertAtEnd); GEP->setIsInBounds(true); return GEP; } @@ -446,23 +348,9 @@ /// Null is returned if the indices are invalid for the specified /// pointer type. /// - template - static Type *getIndexedType(Type *Ptr, RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd) { - return getIndexedType(Ptr, IdxBegin, IdxEnd, - typename std::iterator_traits:: - iterator_category()); - } - - // FIXME: Use ArrayRef - static Type *getIndexedType(Type *Ptr, - Value* const *Idx, unsigned NumIdx); - static Type *getIndexedType(Type *Ptr, - Constant* const *Idx, unsigned NumIdx); - - static Type *getIndexedType(Type *Ptr, - uint64_t const *Idx, unsigned NumIdx); - static Type *getIndexedType(Type *Ptr, Value *Idx); + static Type *getIndexedType(Type *Ptr, ArrayRef IdxList); + static Type *getIndexedType(Type *Ptr, ArrayRef IdxList); + static Type *getIndexedType(Type *Ptr, ArrayRef IdxList); inline op_iterator idx_begin() { return op_begin()+1; } inline const_op_iterator idx_begin() const { return op_begin()+1; } @@ -530,43 +418,33 @@ public VariadicOperandTraits { }; -template GetElementPtrInst::GetElementPtrInst(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, + ArrayRef IdxList, unsigned Values, const Twine &NameStr, Instruction *InsertBefore) : Instruction(PointerType::get(checkGEPType( - getIndexedType(Ptr->getType(), - IdxBegin, IdxEnd)), + getIndexedType(Ptr->getType(), IdxList)), cast(Ptr->getType()) ->getAddressSpace()), GetElementPtr, OperandTraits::op_end(this) - Values, Values, InsertBefore) { - init(Ptr, IdxBegin, IdxEnd, NameStr, - typename std::iterator_traits - ::iterator_category()); + init(Ptr, IdxList, NameStr); } -template GetElementPtrInst::GetElementPtrInst(Value *Ptr, - RandomAccessIterator IdxBegin, - RandomAccessIterator IdxEnd, + ArrayRef IdxList, unsigned Values, const Twine &NameStr, BasicBlock *InsertAtEnd) : Instruction(PointerType::get(checkGEPType( - getIndexedType(Ptr->getType(), - IdxBegin, IdxEnd)), + getIndexedType(Ptr->getType(), IdxList)), cast(Ptr->getType()) ->getAddressSpace()), GetElementPtr, OperandTraits::op_end(this) - Values, Values, InsertAtEnd) { - init(Ptr, IdxBegin, IdxEnd, NameStr, - typename std::iterator_traits - ::iterator_category()); + init(Ptr, IdxList, NameStr); } Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Mon Jul 25 04:48:08 2011 @@ -773,9 +773,7 @@ if (i == e) return Insert(Folder.CreateGetElementPtr(PC, IdxList), Name); } - return Insert(GetElementPtrInst::Create(Ptr, IdxList.begin(), - IdxList.end()), - Name); + return Insert(GetElementPtrInst::Create(Ptr, IdxList), Name); } Value *CreateInBoundsGEP(Value *Ptr, ArrayRef IdxList, const Twine &Name = "") { @@ -788,9 +786,7 @@ if (i == e) return Insert(Folder.CreateInBoundsGetElementPtr(PC, IdxList), Name); } - return Insert(GetElementPtrInst::CreateInBounds(Ptr, IdxList.begin(), - IdxList.end()), - Name); + return Insert(GetElementPtrInst::CreateInBounds(Ptr, IdxList), Name); } Value *CreateGEP(Value *Ptr, Value *Idx, const Twine &Name = "") { if (Constant *PC = dyn_cast(Ptr)) @@ -831,7 +827,7 @@ if (Constant *PC = dyn_cast(Ptr)) return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name); - return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name); + return Insert(GetElementPtrInst::Create(Ptr, Idxs), Name); } Value *CreateConstInBoundsGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1, const Twine &Name = "") { @@ -843,7 +839,7 @@ if (Constant *PC = dyn_cast(Ptr)) return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name); - return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name); + return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs), Name); } Value *CreateConstGEP1_64(Value *Ptr, uint64_t Idx0, const Twine &Name = "") { Value *Idx = ConstantInt::get(Type::getInt64Ty(Context), Idx0); @@ -872,7 +868,7 @@ if (Constant *PC = dyn_cast(Ptr)) return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name); - return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name); + return Insert(GetElementPtrInst::Create(Ptr, Idxs), Name); } Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1, const Twine &Name = "") { @@ -884,7 +880,7 @@ if (Constant *PC = dyn_cast(Ptr)) return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name); - return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name); + return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs), Name); } Value *CreateStructGEP(Value *Ptr, unsigned Idx, const Twine &Name = "") { return CreateConstInBoundsGEP2_32(Ptr, 0, Idx, Name); Modified: llvm/trunk/include/llvm/Support/NoFolder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/NoFolder.h?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/NoFolder.h (original) +++ llvm/trunk/include/llvm/Support/NoFolder.h Mon Jul 25 04:48:08 2011 @@ -183,7 +183,7 @@ } Instruction *CreateGetElementPtr(Constant *C, ArrayRef IdxList) const { - return GetElementPtrInst::Create(C, IdxList.begin(), IdxList.end()); + return GetElementPtrInst::Create(C, IdxList); } Constant *CreateInBoundsGetElementPtr(Constant *C, @@ -192,7 +192,7 @@ } Instruction *CreateInBoundsGetElementPtr(Constant *C, ArrayRef IdxList) const { - return GetElementPtrInst::CreateInBounds(C, IdxList.begin(), IdxList.end()); + return GetElementPtrInst::CreateInBounds(C, IdxList); } //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Jul 25 04:48:08 2011 @@ -547,8 +547,7 @@ for (unsigned i = 1, e = Ops.size(); i != e; ++i) { if ((i == 1 || !isa(GetElementPtrInst::getIndexedType(Ops[0]->getType(), - Ops.data() + 1, - i-1))) && + Ops.slice(1, i-1)))) && Ops[i]->getType() != IntPtrTy) { Any = true; NewIdxs.push_back(ConstantExpr::getCast(CastInst::getCastOpcode(Ops[i], Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Mon Jul 25 04:48:08 2011 @@ -2230,8 +2230,7 @@ if (isa(Ops[0])) { // Compute the (pointer) type returned by the GEP instruction. - Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, Ops.data() + 1, - Ops.size() - 1); + Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, Ops.slice(1)); Type *GEPTy = PointerType::get(LastType, PtrTy->getAddressSpace()); return UndefValue::get(GEPTy); } Modified: llvm/trunk/lib/Analysis/PHITransAddr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/PHITransAddr.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/PHITransAddr.cpp (original) +++ llvm/trunk/lib/Analysis/PHITransAddr.cpp Mon Jul 25 04:48:08 2011 @@ -407,9 +407,10 @@ } GetElementPtrInst *Result = - GetElementPtrInst::Create(GEPOps[0], GEPOps.begin()+1, GEPOps.end(), - InVal->getName()+".phi.trans.insert", - PredBB->getTerminator()); + GetElementPtrInst::Create(GEPOps[0], + makeArrayRef(GEPOps.begin() + 1, GEPOps.end()), + InVal->getName()+".phi.trans.insert", + PredBB->getTerminator()); Result->setIsInBounds(GEP->isInBounds()); NewInsts.push_back(Result); return Result; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Jul 25 04:48:08 2011 @@ -2274,9 +2274,7 @@ return Error(ID.Loc, "getelementptr requires pointer operand"); ArrayRef Indices(Elts.begin() + 1, Elts.end()); - if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(), - (Value**)(Elts.data() + 1), - Elts.size() - 1)) + if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(), Indices)) return Error(ID.Loc, "invalid indices for getelementptr"); ID.ConstantVal = ConstantExpr::getGetElementPtr(Elts[0], Indices, InBounds); @@ -3660,10 +3658,9 @@ Indices.push_back(Val); } - if (!GetElementPtrInst::getIndexedType(Ptr->getType(), - Indices.begin(), Indices.end())) + if (!GetElementPtrInst::getIndexedType(Ptr->getType(), Indices)) return Error(Loc, "invalid getelementptr indices"); - Inst = GetElementPtrInst::Create(Ptr, Indices.begin(), Indices.end()); + Inst = GetElementPtrInst::Create(Ptr, Indices); if (InBounds) cast(Inst)->setIsInBounds(true); return AteExtraComma ? InstExtraComma : InstNormal; Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Jul 25 04:48:08 2011 @@ -2181,7 +2181,7 @@ GEPIdx.push_back(Op); } - I = GetElementPtrInst::Create(BasePtr, GEPIdx.begin(), GEPIdx.end()); + I = GetElementPtrInst::Create(BasePtr, GEPIdx); InstructionList.push_back(I); if (BitCode == bitc::FUNC_CODE_INST_INBOUNDS_GEP) cast(I)->setIsInBounds(true); Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Jul 25 04:48:08 2011 @@ -386,22 +386,20 @@ // We need to also keep around a reference to the call_site field Idxs[0] = Zero; Idxs[1] = ConstantInt::get(Int32Ty, 1); - CallSite = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2, - "call_site", + CallSite = GetElementPtrInst::Create(FunctionContext, Idxs, "call_site", EntryBB->getTerminator()); // The exception selector comes back in context->data[1] Idxs[1] = ConstantInt::get(Int32Ty, 2); - Value *FCData = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2, - "fc_data", + Value *FCData = GetElementPtrInst::Create(FunctionContext, Idxs, "fc_data", EntryBB->getTerminator()); Idxs[1] = ConstantInt::get(Int32Ty, 1); - Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs, Idxs+2, + Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs, "exc_selector_gep", EntryBB->getTerminator()); // The exception value comes back in context->data[0] Idxs[1] = Zero; - Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs, Idxs+2, + Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs, "exception_gep", EntryBB->getTerminator()); @@ -466,8 +464,7 @@ Idxs[0] = Zero; Idxs[1] = ConstantInt::get(Int32Ty, 4); Value *LSDAFieldPtr = - GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2, - "lsda_gep", + GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep", EntryBB->getTerminator()); Value *LSDA = CallInst::Create(LSDAAddrFn, "lsda_addr", EntryBB->getTerminator()); @@ -475,8 +472,7 @@ Idxs[1] = ConstantInt::get(Int32Ty, 3); Value *PersonalityFieldPtr = - GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2, - "lsda_gep", + GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep", EntryBB->getTerminator()); new StoreInst(PersonalityFn, PersonalityFieldPtr, true, EntryBB->getTerminator()); @@ -484,12 +480,11 @@ // Save the frame pointer. Idxs[1] = ConstantInt::get(Int32Ty, 5); Value *JBufPtr - = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2, - "jbuf_gep", + = GetElementPtrInst::Create(FunctionContext, Idxs, "jbuf_gep", EntryBB->getTerminator()); Idxs[1] = ConstantInt::get(Int32Ty, 0); Value *FramePtr = - GetElementPtrInst::Create(JBufPtr, Idxs, Idxs+2, "jbuf_fp_gep", + GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep", EntryBB->getTerminator()); Value *Val = CallInst::Create(FrameAddrFn, @@ -501,7 +496,7 @@ // Save the stack pointer. Idxs[1] = ConstantInt::get(Int32Ty, 2); Value *StackPtr = - GetElementPtrInst::Create(JBufPtr, Idxs, Idxs+2, "jbuf_sp_gep", + GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep", EntryBB->getTerminator()); Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator()); Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Mon Jul 25 04:48:08 2011 @@ -576,9 +576,7 @@ for (ScalarizeTable::iterator SI = ArgIndices.begin(), E = ArgIndices.end(); SI != E; ++SI) { // not allowed to dereference ->begin() if size() is 0 - Params.push_back(GetElementPtrInst::getIndexedType(I->getType(), - SI->begin(), - SI->end())); + Params.push_back(GetElementPtrInst::getIndexedType(I->getType(), *SI)); assert(Params.back()); } @@ -668,7 +666,7 @@ ConstantInt::get(Type::getInt32Ty(F->getContext()), 0), 0 }; for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { Idxs[1] = ConstantInt::get(Type::getInt32Ty(F->getContext()), i); - Value *Idx = GetElementPtrInst::Create(*AI, Idxs, Idxs+2, + Value *Idx = GetElementPtrInst::Create(*AI, Idxs, (*AI)->getName()+"."+utostr(i), Call); // TODO: Tell AA about the new values? @@ -699,8 +697,7 @@ ElTy = cast(ElTy)->getTypeAtIndex(*II); } // And create a GEP to extract those indices. - V = GetElementPtrInst::Create(V, Ops.begin(), Ops.end(), - V->getName()+".idx", Call); + V = GetElementPtrInst::Create(V, Ops, V->getName()+".idx", Call); Ops.clear(); AA.copyValue(OrigLoad->getOperand(0), V); } @@ -801,7 +798,7 @@ for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { Idxs[1] = ConstantInt::get(Type::getInt32Ty(F->getContext()), i); Value *Idx = - GetElementPtrInst::Create(TheAlloca, Idxs, Idxs+2, + GetElementPtrInst::Create(TheAlloca, Idxs, TheAlloca->getName()+"."+Twine(i), InsertPt); I2->setName(I->getName()+"."+Twine(i)); Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Mon Jul 25 04:48:08 2011 @@ -603,7 +603,7 @@ Idxs.push_back(NullInt); for (unsigned i = 3, e = GEPI->getNumOperands(); i != e; ++i) Idxs.push_back(GEPI->getOperand(i)); - NewPtr = GetElementPtrInst::Create(NewPtr, Idxs.begin(), Idxs.end(), + NewPtr = GetElementPtrInst::Create(NewPtr, Idxs, GEPI->getName()+"."+Twine(Val),GEPI); } } @@ -1243,8 +1243,7 @@ GEPIdx.push_back(GEPI->getOperand(1)); GEPIdx.append(GEPI->op_begin()+3, GEPI->op_end()); - Value *NGEPI = GetElementPtrInst::Create(NewPtr, - GEPIdx.begin(), GEPIdx.end(), + Value *NGEPI = GetElementPtrInst::Create(NewPtr, GEPIdx, GEPI->getName(), GEPI); GEPI->replaceAllUsesWith(NGEPI); GEPI->eraseFromParent(); Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Mon Jul 25 04:48:08 2011 @@ -1693,7 +1693,7 @@ // If we found a path from the src to dest, create the getelementptr now. if (SrcElTy == DstElTy) { SmallVector Idxs(NumZeros+1, ZeroUInt); - return GetElementPtrInst::CreateInBounds(Src, Idxs.begin(), Idxs.end()); + return GetElementPtrInst::CreateInBounds(Src, Idxs); } } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Jul 25 04:48:08 2011 @@ -58,8 +58,7 @@ Idx[0] = NullIdx; Idx[1] = NullIdx; Instruction *GEP = - GetElementPtrInst::CreateInBounds(New, Idx, Idx + 2, - New->getName()+".sub"); + GetElementPtrInst::CreateInBounds(New, Idx, New->getName()+".sub"); InsertNewInstBefore(GEP, *It); // Now make everything use the getelementptr instead of the original Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Jul 25 04:48:08 2011 @@ -229,8 +229,8 @@ Value *Base = FixedOperands[0]; GetElementPtrInst *NewGEP = - GetElementPtrInst::Create(Base, FixedOperands.begin()+1, - FixedOperands.end()); + GetElementPtrInst::Create(Base, makeArrayRef(FixedOperands.begin() + 1, + FixedOperands.end())); if (AllInBounds) NewGEP->setIsInBounds(); NewGEP->setDebugLoc(FirstInst->getDebugLoc()); return NewGEP; Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Jul 25 04:48:08 2011 @@ -851,10 +851,9 @@ if (!Indices.empty()) return (GEP.isInBounds() && Src->isInBounds()) ? - GetElementPtrInst::CreateInBounds(Src->getOperand(0), Indices.begin(), - Indices.end(), GEP.getName()) : - GetElementPtrInst::Create(Src->getOperand(0), Indices.begin(), - Indices.end(), GEP.getName()); + GetElementPtrInst::CreateInBounds(Src->getOperand(0), Indices, + GEP.getName()) : + GetElementPtrInst::Create(Src->getOperand(0), Indices, GEP.getName()); } // Handle gep(bitcast x) and gep(gep x, 0, 0, 0). @@ -883,8 +882,7 @@ // -> GEP i8* X, ... SmallVector Idx(GEP.idx_begin()+1, GEP.idx_end()); GetElementPtrInst *Res = - GetElementPtrInst::Create(StrippedPtr, Idx.begin(), - Idx.end(), GEP.getName()); + GetElementPtrInst::Create(StrippedPtr, Idx, GEP.getName()); Res->setIsInBounds(GEP.isInBounds()); return Res; } Modified: llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp Mon Jul 25 04:48:08 2011 @@ -1029,8 +1029,7 @@ gepIndices[1] = incValue; GetElementPtrInst* pcPointer = - GetElementPtrInst::Create(dag->getCounterArray(), - gepIndices.begin(), gepIndices.end(), + GetElementPtrInst::Create(dag->getCounterArray(), gepIndices, "counterInc", insertPoint); // Load from the array - call it oldPC Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jul 25 04:48:08 2011 @@ -2086,8 +2086,7 @@ } Instruction *Val = NewElts[Idx]; if (NewArgs.size() > 1) { - Val = GetElementPtrInst::CreateInBounds(Val, NewArgs.begin(), - NewArgs.end(), "", GEPI); + Val = GetElementPtrInst::CreateInBounds(Val, NewArgs, "", GEPI); Val->takeName(GEPI); } if (Val->getType() != GEPI->getType()) @@ -2163,7 +2162,7 @@ if (OtherPtr) { Value *Idx[2] = { Zero, ConstantInt::get(Type::getInt32Ty(MI->getContext()), i) }; - OtherElt = GetElementPtrInst::CreateInBounds(OtherPtr, Idx, Idx + 2, + OtherElt = GetElementPtrInst::CreateInBounds(OtherPtr, Idx, OtherPtr->getName()+"."+Twine(i), MI); uint64_t EltOffset; Modified: llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp Mon Jul 25 04:48:08 2011 @@ -317,8 +317,7 @@ Idx[1] = ConstantInt::get(Type::getInt32Ty(header->getContext()), i); TerminatorInst *TI = newFunction->begin()->getTerminator(); GetElementPtrInst *GEP = - GetElementPtrInst::Create(AI, Idx, Idx+2, - "gep_" + inputs[i]->getName(), TI); + GetElementPtrInst::Create(AI, Idx, "gep_" + inputs[i]->getName(), TI); RewriteVal = new LoadInst(GEP, "loadgep_" + inputs[i]->getName(), TI); } else RewriteVal = AI++; @@ -420,7 +419,7 @@ Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context)); Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), i); GetElementPtrInst *GEP = - GetElementPtrInst::Create(Struct, Idx, Idx + 2, + GetElementPtrInst::Create(Struct, Idx, "gep_" + StructValues[i]->getName()); codeReplacer->getInstList().push_back(GEP); StoreInst *SI = new StoreInst(StructValues[i], GEP); @@ -446,7 +445,7 @@ Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context)); Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), FirstOut + i); GetElementPtrInst *GEP - = GetElementPtrInst::Create(Struct, Idx, Idx + 2, + = GetElementPtrInst::Create(Struct, Idx, "gep_reload_" + outputs[i]->getName()); codeReplacer->getInstList().push_back(GEP); Output = GEP; @@ -561,7 +560,7 @@ Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), FirstOut+out); GetElementPtrInst *GEP = - GetElementPtrInst::Create(OAI, Idx, Idx + 2, + GetElementPtrInst::Create(OAI, Idx, "gep_" + outputs[out]->getName(), NTRet); new StoreInst(outputs[out], GEP, NTRet); Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Mon Jul 25 04:48:08 2011 @@ -455,8 +455,7 @@ Value *Idx[] = { Constant::getNullValue(Type::getInt32Ty(F.getContext())), ConstantInt::get(Type::getInt32Ty(F.getContext()), 1) }; - OldJmpBufPtr = GetElementPtrInst::Create(JmpBuf, &Idx[0], &Idx[2], - "OldBuf", + OldJmpBufPtr = GetElementPtrInst::Create(JmpBuf, Idx, "OldBuf", EntryBB->getTerminator()); // Copy the JBListHead to the alloca. @@ -502,8 +501,7 @@ "setjmp.cont"); Idx[1] = ConstantInt::get(Type::getInt32Ty(F.getContext()), 0); - Value *JmpBufPtr = GetElementPtrInst::Create(JmpBuf, &Idx[0], &Idx[2], - "TheJmpBuf", + Value *JmpBufPtr = GetElementPtrInst::Create(JmpBuf, Idx, "TheJmpBuf", EntryBB->getTerminator()); JmpBufPtr = new BitCastInst(JmpBufPtr, Type::getInt8PtrTy(F.getContext()), @@ -557,8 +555,7 @@ // Get a pointer to the jmpbuf and longjmp. Value *Idx[] = { Constant::getNullValue(Type::getInt32Ty(F.getContext())), ConstantInt::get(Type::getInt32Ty(F.getContext()), 0) }; - Idx[0] = GetElementPtrInst::Create(BufPtr, &Idx[0], &Idx[2], "JmpBuf", - UnwindBlock); + Idx[0] = GetElementPtrInst::Create(BufPtr, Idx, "JmpBuf", UnwindBlock); Idx[0] = new BitCastInst(Idx[0], Type::getInt8PtrTy(F.getContext()), "tmp", UnwindBlock); Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Mon Jul 25 04:48:08 2011 @@ -2173,7 +2173,7 @@ if (isa(C)) { PointerType *Ptr = cast(C->getType()); - Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(), Idxs.end()); + Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs); assert(Ty != 0 && "Invalid indices for GEP!"); return UndefValue::get(PointerType::get(Ty, Ptr->getAddressSpace())); } @@ -2187,8 +2187,7 @@ } if (isNull) { PointerType *Ptr = cast(C->getType()); - Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(), - Idxs.end()); + Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs); assert(Ty != 0 && "Invalid indices for GEP!"); return ConstantPointerNull::get(PointerType::get(Ty, Ptr->getAddressSpace())); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Mon Jul 25 04:48:08 2011 @@ -1598,8 +1598,7 @@ return FC; // Fold a few common cases. // Get the result type of the getelementptr! - Type *Ty = - GetElementPtrInst::getIndexedType(C->getType(), Idxs.begin(), Idxs.end()); + Type *Ty = GetElementPtrInst::getIndexedType(C->getType(), Idxs); assert(Ty && "GEP indices invalid!"); unsigned AS = cast(C->getType())->getAddressSpace(); Type *ReqTy = Ty->getPointerTo(AS); Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jul 25 04:48:08 2011 @@ -999,28 +999,11 @@ // GetElementPtrInst Implementation //===----------------------------------------------------------------------===// -static unsigned retrieveAddrSpace(const Value *Val) { - return cast(Val->getType())->getAddressSpace(); -} - -void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, +void GetElementPtrInst::init(Value *Ptr, ArrayRef IdxList, const Twine &Name) { - assert(NumOperands == 1+NumIdx && "NumOperands not initialized?"); - Use *OL = OperandList; - OL[0] = Ptr; - - for (unsigned i = 0; i != NumIdx; ++i) - OL[i+1] = Idx[i]; - - setName(Name); -} - -void GetElementPtrInst::init(Value *Ptr, Value *Idx, const Twine &Name) { - assert(NumOperands == 2 && "NumOperands not initialized?"); - Use *OL = OperandList; - OL[0] = Ptr; - OL[1] = Idx; - + assert(NumOperands == 1 + IdxList.size() && "NumOperands not initialized?"); + OperandList[0] = Ptr; + std::copy(IdxList.begin(), IdxList.end(), op_begin() + 1); setName(Name); } @@ -1029,34 +1012,10 @@ OperandTraits::op_end(this) - GEPI.getNumOperands(), GEPI.getNumOperands()) { - Use *OL = OperandList; - Use *GEPIOL = GEPI.OperandList; - for (unsigned i = 0, E = NumOperands; i != E; ++i) - OL[i] = GEPIOL[i]; + std::copy(GEPI.op_begin(), GEPI.op_end(), op_begin()); SubclassOptionalData = GEPI.SubclassOptionalData; } -GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx, - const Twine &Name, Instruction *InBe) - : Instruction(PointerType::get( - checkGEPType(getIndexedType(Ptr->getType(),Idx)), retrieveAddrSpace(Ptr)), - GetElementPtr, - OperandTraits::op_end(this) - 2, - 2, InBe) { - init(Ptr, Idx, Name); -} - -GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx, - const Twine &Name, BasicBlock *IAE) - : Instruction(PointerType::get( - checkGEPType(getIndexedType(Ptr->getType(),Idx)), - retrieveAddrSpace(Ptr)), - GetElementPtr, - OperandTraits::op_end(this) - 2, - 2, IAE) { - init(Ptr, Idx, Name); -} - /// getIndexedType - Returns the type of the element that would be accessed with /// a gep instruction with the specified parameters. /// @@ -1067,14 +1026,13 @@ /// pointer type. /// template -static Type *getIndexedTypeInternal(Type *Ptr, IndexTy const *Idxs, - unsigned NumIdx) { +static Type *getIndexedTypeInternal(Type *Ptr, ArrayRef IdxList) { PointerType *PTy = dyn_cast(Ptr); if (!PTy) return 0; // Type isn't a pointer type! Type *Agg = PTy->getElementType(); // Handle the special case of the empty set index set, which is always valid. - if (NumIdx == 0) + if (IdxList.empty()) return Agg; // If there is at least one index, the top level type must be sized, otherwise @@ -1083,44 +1041,29 @@ return 0; unsigned CurIdx = 1; - for (; CurIdx != NumIdx; ++CurIdx) { + for (; CurIdx != IdxList.size(); ++CurIdx) { CompositeType *CT = dyn_cast(Agg); if (!CT || CT->isPointerTy()) return 0; - IndexTy Index = Idxs[CurIdx]; + IndexTy Index = IdxList[CurIdx]; if (!CT->indexValid(Index)) return 0; Agg = CT->getTypeAtIndex(Index); } - return CurIdx == NumIdx ? Agg : 0; + return CurIdx == IdxList.size() ? Agg : 0; } -Type *GetElementPtrInst::getIndexedType(Type *Ptr, Value* const *Idxs, - unsigned NumIdx) { - return getIndexedTypeInternal(Ptr, Idxs, NumIdx); +Type *GetElementPtrInst::getIndexedType(Type *Ptr, ArrayRef IdxList) { + return getIndexedTypeInternal(Ptr, IdxList); } Type *GetElementPtrInst::getIndexedType(Type *Ptr, - Constant* const *Idxs, - unsigned NumIdx) { - return getIndexedTypeInternal(Ptr, Idxs, NumIdx); + ArrayRef IdxList) { + return getIndexedTypeInternal(Ptr, IdxList); } -Type *GetElementPtrInst::getIndexedType(Type *Ptr, - uint64_t const *Idxs, - unsigned NumIdx) { - return getIndexedTypeInternal(Ptr, Idxs, NumIdx); +Type *GetElementPtrInst::getIndexedType(Type *Ptr, ArrayRef IdxList) { + return getIndexedTypeInternal(Ptr, IdxList); } -Type *GetElementPtrInst::getIndexedType(Type *Ptr, Value *Idx) { - PointerType *PTy = dyn_cast(Ptr); - if (!PTy) return 0; // Type isn't a pointer type! - - // Check the pointer index. - if (!PTy->indexValid(Idx)) return 0; - - return PTy->getElementType(); -} - - /// hasAllZeroIndices - Return true if all of the indices of this GEP are /// zeros. If so, the result pointer and the first operand have the same /// value, just potentially different types. Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jul 25 04:48:08 2011 @@ -1276,8 +1276,7 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { SmallVector Idxs(GEP.idx_begin(), GEP.idx_end()); Type *ElTy = - GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(), - Idxs.begin(), Idxs.end()); + GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(), Idxs); Assert1(ElTy, "Invalid indices for GEP pointer type!", &GEP); Assert2(GEP.getType()->isPointerTy() && cast(GEP.getType())->getElementType() == ElTy, Modified: llvm/trunk/unittests/Transforms/Utils/Cloning.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Transforms/Utils/Cloning.cpp?rev=135904&r1=135903&r2=135904&view=diff ============================================================================== --- llvm/trunk/unittests/Transforms/Utils/Cloning.cpp (original) +++ llvm/trunk/unittests/Transforms/Utils/Cloning.cpp Mon Jul 25 04:48:08 2011 @@ -124,7 +124,7 @@ Constant *Z = Constant::getNullValue(Type::getInt32Ty(context)); std::vector ops; ops.push_back(Z); - GetElementPtrInst *GEP = GetElementPtrInst::Create(V, ops.begin(), ops.end()); + GetElementPtrInst *GEP = GetElementPtrInst::Create(V, ops); EXPECT_FALSE(this->clone(GEP)->isInBounds()); GEP->setIsInBounds(); From jay.foad at gmail.com Mon Jul 25 05:14:44 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 25 Jul 2011 10:14:44 -0000 Subject: [llvm-commits] [llvm] r135905 - in /llvm/trunk: include/llvm/Constants.h lib/VMCore/Constants.cpp Message-ID: <20110725101444.E384B2A6C12C@llvm.org> Author: foad Date: Mon Jul 25 05:14:44 2011 New Revision: 135905 URL: http://llvm.org/viewvc/llvm-project?rev=135905&view=rev Log: Use ArrayRef in the (protected) constructors of ConstantArray, ConstantStruct and ConstantVector. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/lib/VMCore/Constants.cpp Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=135905&r1=135904&r2=135905&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Mon Jul 25 05:14:44 2011 @@ -329,7 +329,7 @@ std::vector >; ConstantArray(const ConstantArray &); // DO NOT IMPLEMENT protected: - ConstantArray(ArrayType *T, const std::vector &Val); + ConstantArray(ArrayType *T, ArrayRef Val); public: // ConstantArray accessors static Constant *get(ArrayType *T, ArrayRef V); @@ -400,7 +400,7 @@ std::vector >; ConstantStruct(const ConstantStruct &); // DO NOT IMPLEMENT protected: - ConstantStruct(StructType *T, const std::vector &Val); + ConstantStruct(StructType *T, ArrayRef Val); public: // ConstantStruct accessors static Constant *get(StructType *T, ArrayRef V); @@ -461,7 +461,7 @@ std::vector >; ConstantVector(const ConstantVector &); // DO NOT IMPLEMENT protected: - ConstantVector(VectorType *T, const std::vector &Val); + ConstantVector(VectorType *T, ArrayRef Val); public: // ConstantVector accessors static Constant *get(ArrayRef V); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=135905&r1=135904&r2=135905&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Mon Jul 25 05:14:44 2011 @@ -573,21 +573,16 @@ //===----------------------------------------------------------------------===// -ConstantArray::ConstantArray(ArrayType *T, - const std::vector &V) +ConstantArray::ConstantArray(ArrayType *T, ArrayRef V) : Constant(T, ConstantArrayVal, OperandTraits::op_end(this) - V.size(), V.size()) { assert(V.size() == T->getNumElements() && "Invalid initializer vector for constant array"); - Use *OL = OperandList; - for (std::vector::const_iterator I = V.begin(), E = V.end(); - I != E; ++I, ++OL) { - Constant *C = *I; - assert(C->getType() == T->getElementType() && + for (unsigned i = 0, e = V.size(); i != e; ++i) + assert(V[i]->getType() == T->getElementType() && "Initializer for array element doesn't match array element type!"); - *OL = C; - } + std::copy(V.begin(), V.end(), op_begin()); } Constant *ConstantArray::get(ArrayType *Ty, ArrayRef V) { @@ -653,21 +648,16 @@ } -ConstantStruct::ConstantStruct(StructType *T, - const std::vector &V) +ConstantStruct::ConstantStruct(StructType *T, ArrayRef V) : Constant(T, ConstantStructVal, OperandTraits::op_end(this) - V.size(), V.size()) { assert((T->isOpaque() || V.size() == T->getNumElements()) && "Invalid initializer vector for constant structure"); - Use *OL = OperandList; - for (std::vector::const_iterator I = V.begin(), E = V.end(); - I != E; ++I, ++OL) { - Constant *C = *I; - assert((T->isOpaque() || C->getType() == T->getElementType(I-V.begin())) && + for (unsigned i = 0, e = V.size(); i != e; ++i) + assert((T->isOpaque() || V[i]->getType() == T->getElementType(i)) && "Initializer for struct element doesn't match struct element type!"); - *OL = C; - } + std::copy(V.begin(), V.end(), op_begin()); } // ConstantStruct accessors. @@ -692,19 +682,14 @@ return get(T, Values); } -ConstantVector::ConstantVector(VectorType *T, - const std::vector &V) +ConstantVector::ConstantVector(VectorType *T, ArrayRef V) : Constant(T, ConstantVectorVal, OperandTraits::op_end(this) - V.size(), V.size()) { - Use *OL = OperandList; - for (std::vector::const_iterator I = V.begin(), E = V.end(); - I != E; ++I, ++OL) { - Constant *C = *I; - assert(C->getType() == T->getElementType() && + for (size_t i = 0, e = V.size(); i != e; i++) + assert(V[i]->getType() == T->getElementType() && "Initializer for vector element doesn't match vector element type!"); - *OL = C; - } + std::copy(V.begin(), V.end(), op_begin()); } // ConstantVector accessors. From jay.foad at gmail.com Mon Jul 25 05:32:27 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 25 Jul 2011 10:32:27 -0000 Subject: [llvm-commits] [llvm] r135906 - /llvm/trunk/include/llvm/Support/TypeBuilder.h Message-ID: <20110725103227.81B6E2A6C12C@llvm.org> Author: foad Date: Mon Jul 25 05:32:27 2011 New Revision: 135906 URL: http://llvm.org/viewvc/llvm-project?rev=135906&view=rev Log: Remove uses of std::vector from TypeBuilder. Modified: llvm/trunk/include/llvm/Support/TypeBuilder.h Modified: llvm/trunk/include/llvm/Support/TypeBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TypeBuilder.h?rev=135906&r1=135905&r2=135906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/TypeBuilder.h (original) +++ llvm/trunk/include/llvm/Support/TypeBuilder.h Mon Jul 25 05:32:27 2011 @@ -18,7 +18,6 @@ #include "llvm/DerivedTypes.h" #include "llvm/LLVMContext.h" #include -#include namespace llvm { @@ -254,9 +253,9 @@ template class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(1); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, false); } @@ -265,10 +264,10 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(2); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, false); } @@ -277,11 +276,11 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(3); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, false); } @@ -292,12 +291,12 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(4); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, false); } @@ -308,13 +307,13 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(5); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, false); } @@ -330,9 +329,9 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(1); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, true); } }; @@ -340,10 +339,10 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(2); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, true); } @@ -352,11 +351,11 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(3); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, true); } @@ -367,12 +366,12 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(4); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, true); } @@ -383,13 +382,13 @@ class TypeBuilder { public: static FunctionType *get(LLVMContext &Context) { - std::vector params; - params.reserve(5); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); - params.push_back(TypeBuilder::get(Context)); + Type *params[] = { + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + TypeBuilder::get(Context), + }; return FunctionType::get(TypeBuilder::get(Context), params, true); } From 6yearold at gmail.com Mon Jul 25 06:40:35 2011 From: 6yearold at gmail.com (arrowdodger) Date: Mon, 25 Jul 2011 15:40:35 +0400 Subject: [llvm-commits] [PATCH][CMake] Connect llvmc tool to the build. Message-ID: I've wrote this by looking on according Makefiles. I haven't done anything in doc/, since Makefiles do nothing there too. The only thing i'm unsure is how do determine LLVM{GCC,GXX}COMMAND, so i just hardcoded them to clang/clang++. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/ebc0e702/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvmc.cmake.patch Type: text/x-patch Size: 4340 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/ebc0e702/attachment.bin From baldrick at free.fr Mon Jul 25 07:48:41 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 14:48:41 +0200 Subject: [llvm-commits] [llvm] r135362 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp In-Reply-To: <20110717190500.7CE192A6C12C@llvm.org> References: <20110717190500.7CE192A6C12C@llvm.org> Message-ID: <4E2D6629.3080000@free.fr> Hi Nadav, > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Jul 17 14:05:00 2011 > @@ -2775,7 +2775,6 @@ > > > SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { > - > ShuffleVectorSDNode *SV = cast(N); > EVT VT = N->getValueType(0); > DebugLoc dl = N->getDebugLoc(); > @@ -2838,13 +2837,12 @@ > EVT NOutVTElem = NOutVT.getVectorElementType(); > > DebugLoc dl = N->getDebugLoc(); > - > - SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, > - N->getOperand(0)); > + SDValue V0 = GetPromotedInteger(N->getOperand(0)); > + SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, V0); > > SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, > NOutVTElem, N->getOperand(1)); > - return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT, > + return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, > ConvertedVector, ConvElem, N->getOperand(2)); > } since the input and output vector types are the same, as the output type is promoted you know that the input type is promoted to the same type. Thus the ANY_EXTEND of V0 must be a no-op and can be removed. Ciao, Duncan. From baldrick at free.fr Mon Jul 25 08:01:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 25 Jul 2011 15:01:44 +0200 Subject: [llvm-commits] [llvm] r135471 - /llvm/trunk/test/Transforms/InstSimplify/compare.ll In-Reply-To: <20110719082257.D4D482A6C12D@llvm.org> References: <20110719082257.D4D482A6C12D@llvm.org> Message-ID: <4E2D6938.6080800@free.fr> Hi Nick, > Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed > to perform a signed wrap. Don't rely on any particular handling of that case. I don't understand what you are saying. "sub nsw" never does a signed wrap (if it does the program performs undefined behaviour). In the testcase, %A is positive while %B is negative. Thus %C is positive because there is no signed wrap. Thus %D is positive or zero and %E is false. Ciao, Duncan. > > Modified: > llvm/trunk/test/Transforms/InstSimplify/compare.ll > > Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=135471&r1=135470&r2=135471&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original) > +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Jul 19 03:22:57 2011 > @@ -283,17 +283,6 @@ > ret i1 %E > } > > -; CHECK: @srem4 > -; CHECK-NEXT: ret i1 false > -define i1 @srem4(i16 %X, i32 %Y) { > - %A = zext i16 %X to i32 > - %B = or i32 2147483648, %A > - %C = sub nsw i32 %A, %B > - %D = srem i32 %C, %Y > - %E = icmp slt i32 %D, 0 > - ret i1 %E > -} > - > define i1 @udiv1(i32 %X) { > ; CHECK: @udiv1 > %A = udiv i32 %X, 1000000 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ofv at wanadoo.es Mon Jul 25 09:10:24 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Mon, 25 Jul 2011 16:10:24 +0200 Subject: [llvm-commits] [PATCH][CMake] Connect llvmc tool to the build. References: Message-ID: <87mxg2ih7z.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > I've wrote this by looking on according Makefiles. I haven't done anything > in doc/, since Makefiles do nothing there too. > > The only thing i'm unsure is how do determine LLVM{GCC,GXX}COMMAND, so i > just hardcoded them to clang/clang++. > > Index: tools/llvmc/src/CMakeLists.txt > =================================================================== > --- tools/llvmc/src/CMakeLists.txt (revision 0) > +++ tools/llvmc/src/CMakeLists.txt (revision 0) > @@ -0,0 +1,25 @@ > +set(LLVMGCCCOMMAND ${CMAKE_BINARY_DIR}/bin/clang) > +set(LLVMGXXCOMMAND ${CMAKE_BINARY_DIR}/bin/clang++) The above will stop working once LLVM is installed and the build directory removed, or when clang is not included in the build. Maybe set(LLVMGCCCOMMAND "${CMAKE_C_COMPILER}") set(LLVMGCCCOMMAND "${CMAKE_CXX_COMPILER}") ? > +configure_file( > + ${CMAKE_CURRENT_SOURCE_DIR}/Base.td.in > + ${CMAKE_CURRENT_BINARY_DIR}/Base.td > + ) Please use the @ONLY option in that configure_file, just in case. > +set(LLVM_TARGET_DEFINITIONS AutoGenerated.td) > + > +tablegen(AutoGenerated.inc -gen-llvmc) > + > +set(LLVM_USED_LIBS CompilerDriver) > +set(LLVM_LINK_COMPONENTS support) > + > +add_llvm_tool(llvmc > + Hooks.cpp > + Main.cpp > + ) The chunks of code like this: > +add_custom_target(llvmc_gen ALL > + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/AutoGenerated.inc) > +set_target_properties(llvmc_gen PROPERTIES FOLDER "Tablegenning") > + > +set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} llvmc_gen PARENT_SCOPE) ... are now unnecessary. I've just added support in add_llvm_executable for automatically doing that. > \ No newline at end of file Please end the CMakeLists.txt files with a newline. [snip] > +set(LLVM_USED_LIBS CompilerDriver) Why do you neeed CompilerDriver ? [snip] From ofv at wanadoo.es Mon Jul 25 09:11:55 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 25 Jul 2011 14:11:55 -0000 Subject: [llvm-commits] [llvm] r135908 - in /llvm/trunk/cmake/modules: AddLLVM.cmake TableGen.cmake Message-ID: <20110725141155.3C2422A6C12C@llvm.org> Author: ofv Date: Mon Jul 25 09:11:55 2011 New Revision: 135908 URL: http://llvm.org/viewvc/llvm-project?rev=135908&view=rev Log: CMake: generalize the system that creates custom targets for tablegenning to all libraries and executables. Modified: llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/cmake/modules/TableGen.cmake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=135908&r1=135907&r2=135908&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Mon Jul 25 09:11:55 2011 @@ -2,6 +2,7 @@ include(LLVM-Config) macro(add_llvm_library name) + create_tablegenning_custom_target( ${name} ) llvm_process_sources( ALL_FILES ${ARGN} ) add_library( ${name} ${ALL_FILES} ) set_property( GLOBAL APPEND PROPERTY LLVM_LIBS ${name} ) @@ -32,6 +33,7 @@ add_dependencies(${name} ${CURRENT_LLVM_TARGET}) endif() set_target_properties(${name} PROPERTIES FOLDER "Libraries") + add_tablegenning_dependency( ${name} ) endmacro(add_llvm_library name) @@ -75,6 +77,7 @@ macro(add_llvm_executable name) + create_tablegenning_custom_target( ${name} ) llvm_process_sources( ALL_FILES ${ARGN} ) if( EXCLUDE_FROM_ALL ) add_executable(${name} EXCLUDE_FROM_ALL ${ALL_FILES}) @@ -88,6 +91,7 @@ add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) link_system_libs( ${name} ) + add_tablegenning_dependency( ${name} ) endmacro(add_llvm_executable name) @@ -124,16 +128,7 @@ macro(add_llvm_target target_name) - if( TABLEGEN_OUTPUT ) - add_custom_target(${target_name}Table_gen - DEPENDS ${TABLEGEN_OUTPUT}) - add_dependencies(${target_name}Table_gen ${LLVM_COMMON_DEPENDS}) - endif( TABLEGEN_OUTPUT ) include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}) add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT}) - if ( TABLEGEN_OUTPUT ) - add_dependencies(LLVM${target_name} ${target_name}Table_gen) - set_target_properties(${target_name}Table_gen PROPERTIES FOLDER "Tablegenning") - endif (TABLEGEN_OUTPUT) set( CURRENT_LLVM_TARGET LLVM${target_name} ) endmacro(add_llvm_target) Modified: llvm/trunk/cmake/modules/TableGen.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/TableGen.cmake?rev=135908&r1=135907&r2=135908&view=diff ============================================================================== --- llvm/trunk/cmake/modules/TableGen.cmake (original) +++ llvm/trunk/cmake/modules/TableGen.cmake Mon Jul 25 09:11:55 2011 @@ -44,3 +44,24 @@ set_source_files_properties(${CMAKE_CURRENT_BINARY_DIR}/${ofn} PROPERTIES GENERATED 1) endmacro(tablegen) + + +function(create_tablegenning_custom_target target) + # Creates the global target that runs the file-level dependencies + # for tablegenning. + if( TABLEGEN_OUTPUT ) + add_custom_target(${target}Table_gen + DEPENDS ${TABLEGEN_OUTPUT}) + add_dependencies(${target}Table_gen ${LLVM_COMMON_DEPENDS}) + endif( TABLEGEN_OUTPUT ) +endfunction() + +function(add_tablegenning_dependency target) + # Makes the tablegenning step created with + # create_tablegenning_custom_target dependent on `target'. + if ( TABLEGEN_OUTPUT ) + add_dependencies(${target} ${target}Table_gen) + set_target_properties(${target}Table_gen PROPERTIES FOLDER "Tablegenning") + endif (TABLEGEN_OUTPUT) +endfunction() + From nadav.rotem at intel.com Mon Jul 25 09:33:32 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 25 Jul 2011 17:33:32 +0300 Subject: [llvm-commits] [PATCH] Vector-select patch Message-ID: <6594DDFF12B03D4E89690887C24869940296D9096B@hasmsx504.ger.corp.intel.com> Hi, Please review the attached file. The type legalization changes are mostly complete, and it is possible to match vector instructions. This patch contains the code-independent parts of the vector select. Thanks, Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/99d7a37f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: vector_select_list.diff Type: application/octet-stream Size: 18597 bytes Desc: vector_select_list.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/99d7a37f/attachment.obj From fvbommel at gmail.com Mon Jul 25 09:36:23 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 25 Jul 2011 16:36:23 +0200 Subject: [llvm-commits] [llvm] r135904 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Support/ lib/Analysis/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Instrumentation/ lib/Transforms Message-ID: On 25 July 2011 11:48, Jay Foad wrote: > --- llvm/trunk/lib/Analysis/PHITransAddr.cpp (original) > +++ llvm/trunk/lib/Analysis/PHITransAddr.cpp Mon Jul 25 04:48:08 2011 > @@ -407,9 +407,10 @@ > ? ? } > > ? ? GetElementPtrInst *Result = > - ? ?GetElementPtrInst::Create(GEPOps[0], GEPOps.begin()+1, GEPOps.end(), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?InVal->getName()+".phi.trans.insert", > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?PredBB->getTerminator()); > + ? ? ?GetElementPtrInst::Create(GEPOps[0], > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?makeArrayRef(GEPOps.begin() + 1, GEPOps.end()), 'makeArrayRef(GEPOps).slice(1)' is nicer, and is the idiom used in several other places. > --- llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Jul 25 04:48:08 2011 > @@ -229,8 +229,8 @@ > > ? Value *Base = FixedOperands[0]; > ? GetElementPtrInst *NewGEP = > - ? ?GetElementPtrInst::Create(Base, FixedOperands.begin()+1, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?FixedOperands.end()); > + ? ?GetElementPtrInst::Create(Base, makeArrayRef(FixedOperands.begin() + 1, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? FixedOperands.end())); makeArrayRef(FixedOperands).slice(1) From jay.foad at gmail.com Mon Jul 25 09:49:09 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 25 Jul 2011 15:49:09 +0100 Subject: [llvm-commits] [llvm] r135904 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Support/ lib/Analysis/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Instrumentation/ lib/Transforms In-Reply-To: References: Message-ID: On 25 July 2011 15:36, Frits van Bommel wrote: > On 25 July 2011 11:48, Jay Foad wrote: >> --- llvm/trunk/lib/Analysis/PHITransAddr.cpp (original) >> +++ llvm/trunk/lib/Analysis/PHITransAddr.cpp Mon Jul 25 04:48:08 2011 >> @@ -407,9 +407,10 @@ >> ? ? } >> >> ? ? GetElementPtrInst *Result = >> - ? ?GetElementPtrInst::Create(GEPOps[0], GEPOps.begin()+1, GEPOps.end(), >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?InVal->getName()+".phi.trans.insert", >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?PredBB->getTerminator()); >> + ? ? ?GetElementPtrInst::Create(GEPOps[0], >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?makeArrayRef(GEPOps.begin() + 1, GEPOps.end()), > > 'makeArrayRef(GEPOps).slice(1)' is nicer, and is the idiom used in > several other places. I considered both versions and chose this one. Why? Because I'm not very familiar with slice(). It isn't in the STL (is it?) and it's not immediately obvious to me, as a reader, what slice(a) and slice(a,b) mean. Feel free to change it if you want. Jay. From 6yearold at gmail.com Mon Jul 25 10:00:30 2011 From: 6yearold at gmail.com (arrowdodger) Date: Mon, 25 Jul 2011 19:00:30 +0400 Subject: [llvm-commits] [PATCH][CMake] Connect llvmc tool to the build. In-Reply-To: <87mxg2ih7z.fsf@wanadoo.es> References: <87mxg2ih7z.fsf@wanadoo.es> Message-ID: On Mon, Jul 25, 2011 at 6:10 PM, ?scar Fuentes wrote: > > Index: tools/llvmc/src/CMakeLists.txt > > =================================================================== > > --- tools/llvmc/src/CMakeLists.txt (revision 0) > > +++ tools/llvmc/src/CMakeLists.txt (revision 0) > > @@ -0,0 +1,25 @@ > > +set(LLVMGCCCOMMAND ${CMAKE_BINARY_DIR}/bin/clang) > > +set(LLVMGXXCOMMAND ${CMAKE_BINARY_DIR}/bin/clang++) > > The above will stop working once LLVM is installed and the build > directory removed, or when clang is not included in the build. > > Maybe > > set(LLVMGCCCOMMAND "${CMAKE_C_COMPILER}") > set(LLVMGCCCOMMAND "${CMAKE_CXX_COMPILER}") > > ? > CMAKE_C_COMPILER is not guaranteed to be able to -emit-llvm. As i've understand, LLVM{GCC,GXX}COMMAND should point to clang, llvm-gcc or dragonegg. I've built LLVM with autotools and ran llvmc. It seems, LLVM{GCC,GXX}COMMAND aren't contain absolute path, but just defaults to llvm-g{cc,++}. And there is -clang option for llvmc, which changes llvm-g{cc,++} to clang{++}. So, the soultion here is just set(LLVMGCCCOMMAND llvm-gcc) set(LLVMGCCCOMMAND llvm-g++) But since llvm-gcc is almost dead, isn't it better to make clang default? Of course, this would require changes in Makefiles for consistency and in llvmc itself for option update. > +set(LLVM_USED_LIBS CompilerDriver) > > Why do you neeed CompilerDriver ? > Because llvmc depends on it. In llvmc/src/Makefile there is line LLVMC_BASED_DRIVER = llvmc and in Makefile.rules there are following lines ifdef LLVMC_BASED_DRIVER LLVMLIBS = CompilerDriver.a At last, removing set(LLVM_USED_LIBS CompilerDriver) causes linking failures. I've adressed your notes in updated patch. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/495f3089/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvmc.cmake.patch Type: text/x-patch Size: 3154 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/495f3089/attachment.bin From fvbommel at gmail.com Mon Jul 25 10:13:01 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 25 Jul 2011 15:13:01 -0000 Subject: [llvm-commits] [llvm] r135910 - in /llvm/trunk/lib: Analysis/PHITransAddr.cpp Transforms/InstCombine/InstCombinePHI.cpp Message-ID: <20110725151301.CBA102A6C124@llvm.org> Author: fvbommel Date: Mon Jul 25 10:13:01 2011 New Revision: 135910 URL: http://llvm.org/viewvc/llvm-project?rev=135910&view=rev Log: Shorten some expressions by using ArrayRef::slice(). Modified: llvm/trunk/lib/Analysis/PHITransAddr.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Modified: llvm/trunk/lib/Analysis/PHITransAddr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/PHITransAddr.cpp?rev=135910&r1=135909&r2=135910&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/PHITransAddr.cpp (original) +++ llvm/trunk/lib/Analysis/PHITransAddr.cpp Mon Jul 25 10:13:01 2011 @@ -407,8 +407,7 @@ } GetElementPtrInst *Result = - GetElementPtrInst::Create(GEPOps[0], - makeArrayRef(GEPOps.begin() + 1, GEPOps.end()), + GetElementPtrInst::Create(GEPOps[0], makeArrayRef(GEPOps).slice(1), InVal->getName()+".phi.trans.insert", PredBB->getTerminator()); Result->setIsInBounds(GEP->isInBounds()); Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=135910&r1=135909&r2=135910&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Jul 25 10:13:01 2011 @@ -229,8 +229,7 @@ Value *Base = FixedOperands[0]; GetElementPtrInst *NewGEP = - GetElementPtrInst::Create(Base, makeArrayRef(FixedOperands.begin() + 1, - FixedOperands.end())); + GetElementPtrInst::Create(Base, makeArrayRef(FixedOperands).slice(1)); if (AllInBounds) NewGEP->setIsInBounds(); NewGEP->setDebugLoc(FirstInst->getDebugLoc()); return NewGEP; From ofv at wanadoo.es Mon Jul 25 10:24:48 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Mon, 25 Jul 2011 17:24:48 +0200 Subject: [llvm-commits] [PATCH][CMake] Connect llvmc tool to the build. In-Reply-To: (arrowdodger's message of "Mon, 25 Jul 2011 19:00:30 +0400") References: <87mxg2ih7z.fsf@wanadoo.es> Message-ID: <87hb6aidrz.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: [snip] Okay. Have you tested the build in Visual Studio? (with LLVM_BUILD_EXAMPLES=ON) From stoklund at 2pi.dk Mon Jul 25 10:25:43 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 25 Jul 2011 15:25:43 -0000 Subject: [llvm-commits] [llvm] r135912 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110725152543.90ACE2A6C12D@llvm.org> Author: stoklund Date: Mon Jul 25 10:25:43 2011 New Revision: 135912 URL: http://llvm.org/viewvc/llvm-project?rev=135912&view=rev Log: Add an RS_Split2 stage used for loop prevention. This mechanism already exists, but the RS_Split2 stage makes it clearer. When live range splitting creates ranges that may not be making progress, they are marked RS_Split2 instead of RS_New. These ranges may be split again, but only in a way that can be proven to make progress. For local ranges, that means they must be split into ranges used by strictly fewer instructions. For global ranges, region splitting is bypassed and the RS_Split2 ranges go straight to per-block splitting. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=135912&r1=135911&r2=135912&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Jul 25 10:25:43 2011 @@ -99,6 +99,11 @@ /// Attempt live range splitting if assignment is impossible. RS_Split, + /// Attempt more aggressive live range splitting that is guaranteed to make + /// progress. This is used for split products that may not be making + /// progress. + RS_Split2, + /// Live range will be spilled. No more splitting will be attempted. RS_Spill, @@ -246,6 +251,7 @@ "RS_New", "RS_Assign", "RS_Split", + "RS_Split2", "RS_Spill", "RS_Done" }; @@ -451,7 +457,7 @@ /// @param BreaksHint True when B is already assigned to its preferred register. bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, LiveInterval &B, bool BreaksHint) { - bool CanSplit = getStage(B) <= RS_Split; + bool CanSplit = getStage(B) < RS_Spill; // Be fairly aggressive about following hints as long as the evictee can be // split. @@ -987,13 +993,13 @@ } // Main interval. Allow repeated splitting as long as the number of live - // blocks is strictly decreasing. + // blocks is strictly decreasing. Otherwise force per-block splitting. if (IntvMap[i] == MainIntv) { if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks << " blocks as original.\n"); // Don't allow repeated splitting as a safe guard against looping. - setStage(Reg, RS_Spill); + setStage(Reg, RS_Split2); } continue; } @@ -1180,17 +1186,17 @@ // // Instead we use these rules: // - // 1. Allow any split for ranges with getStage() < RS_Spill. (Except for the + // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the // noop split, of course). - // 2. Require progress be made for ranges with getStage() >= RS_Spill. All + // 2. Require progress be made for ranges with getStage() == RS_Split2. All // the new ranges must have fewer instructions than before the split. - // 3. New ranges with the same number of instructions are marked RS_Spill, + // 3. New ranges with the same number of instructions are marked RS_Split2, // smaller ranges are marked RS_New. // // These rules allow a 3 -> 2+3 split once, which we need. They also prevent // excessive splitting and infinite loops. // - bool ProgressRequired = getStage(VirtReg) >= RS_Spill; + bool ProgressRequired = getStage(VirtReg) >= RS_Split2; // Best split candidate. unsigned BestBefore = NumGaps; @@ -1309,7 +1315,7 @@ DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); // If the new range has the same number of instructions as before, mark it as - // RS_Spill so the next split will be forced to make progress. Otherwise, + // RS_Split2 so the next split will be forced to make progress. Otherwise, // leave the new intervals as RS_New so they can compete. bool LiveBefore = BestBefore != 0 || BI.LiveIn; bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; @@ -1319,7 +1325,7 @@ assert(!ProgressRequired && "Didn't make progress when it was required."); for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) if (IntvMap[i] == 1) { - setStage(*LREdit.get(i), RS_Spill); + setStage(*LREdit.get(i), RS_Split2); DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg)); } DEBUG(dbgs() << '\n'); @@ -1347,8 +1353,7 @@ NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled); - // Don't iterate global splitting. - // Move straight to spilling if this range was produced by a global split. + // Ranges must be Split2 or less. if (getStage(VirtReg) >= RS_Spill) return 0; @@ -1365,10 +1370,14 @@ return PhysReg; } - // First try to split around a region spanning multiple blocks. - unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); - if (PhysReg || !NewVRegs.empty()) - return PhysReg; + // First try to split around a region spanning multiple blocks. RS_Split2 + // ranges already made dubious progress with region splitting, so they go + // straight to single block splitting. + if (getStage(VirtReg) < RS_Split2) { + unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); + if (PhysReg || !NewVRegs.empty()) + return PhysReg; + } // Then isolate blocks with multiple uses. SplitAnalysis::BlockPtrSet Blocks; From stoklund at 2pi.dk Mon Jul 25 10:25:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 25 Jul 2011 15:25:41 -0000 Subject: [llvm-commits] [llvm] r135911 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110725152541.379752A6C12C@llvm.org> Author: stoklund Date: Mon Jul 25 10:25:41 2011 New Revision: 135911 URL: http://llvm.org/viewvc/llvm-project?rev=135911&view=rev Log: Rename live range stages to better reflect how they are used. The stage is used to control where a live range is going, not where it is coming from. Live ranges created by splitting will usually be marked RS_New, but some are marked RS_Spill to avoid wasting time trying to split them again. The old RS_Global and RS_Local stages are merged - they are really the same thing for local and global live ranges. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=135911&r1=135910&r2=135911&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Jul 25 10:25:41 2011 @@ -90,12 +90,21 @@ // range splitting algorithm terminates, something that is otherwise hard to // ensure. enum LiveRangeStage { - RS_New, ///< Never seen before. - RS_First, ///< First time in the queue. - RS_Second, ///< Second time in the queue. - RS_Global, ///< Produced by global splitting. - RS_Local, ///< Produced by local splitting. - RS_Spill ///< Produced by spilling. + /// Newly created live range that has never been queued. + RS_New, + + /// Only attempt assignment and eviction. Then requeue as RS_Split. + RS_Assign, + + /// Attempt live range splitting if assignment is impossible. + RS_Split, + + /// Live range will be spilled. No more splitting will be attempted. + RS_Spill, + + /// There is nothing more we can do to this live range. Abort compilation + /// if it can't be assigned. + RS_Done }; static const char *const StageName[]; @@ -234,12 +243,11 @@ #ifndef NDEBUG const char *const RAGreedy::StageName[] = { - "RS_New", - "RS_First", - "RS_Second", - "RS_Global", - "RS_Local", - "RS_Spill" + "RS_New", + "RS_Assign", + "RS_Split", + "RS_Spill", + "RS_Done" }; #endif @@ -351,9 +359,9 @@ ExtraRegInfo.grow(Reg); if (ExtraRegInfo[Reg].Stage == RS_New) - ExtraRegInfo[Reg].Stage = RS_First; + ExtraRegInfo[Reg].Stage = RS_Assign; - if (ExtraRegInfo[Reg].Stage == RS_Second) + if (ExtraRegInfo[Reg].Stage == RS_Split) // Unsplit ranges that couldn't be allocated immediately are deferred until // everything else has been allocated. Long ranges are allocated last so // they are split against realistic interference. @@ -443,7 +451,7 @@ /// @param BreaksHint True when B is already assigned to its preferred register. bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, LiveInterval &B, bool BreaksHint) { - bool CanSplit = getStage(B) <= RS_Second; + bool CanSplit = getStage(B) <= RS_Split; // Be fairly aggressive about following hints as long as the evictee can be // split. @@ -488,7 +496,7 @@ if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) return false; // Never evict spill products. They cannot split or spill. - if (getStage(*Intf) == RS_Spill) + if (getStage(*Intf) == RS_Done) return false; // Once a live range becomes small enough, it is urgent that we find a // register for it. This is indicated by an infinite spill weight. These @@ -974,7 +982,7 @@ // Remainder interval. Don't try splitting again, spill if it doesn't // allocate. if (IntvMap[i] == 0) { - setStage(Reg, RS_Global); + setStage(Reg, RS_Spill); continue; } @@ -985,7 +993,7 @@ DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks << " blocks as original.\n"); // Don't allow repeated splitting as a safe guard against looping. - setStage(Reg, RS_Global); + setStage(Reg, RS_Spill); } continue; } @@ -1172,17 +1180,17 @@ // // Instead we use these rules: // - // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the + // 1. Allow any split for ranges with getStage() < RS_Spill. (Except for the // noop split, of course). - // 2. Require progress be made for ranges with getStage() >= RS_Local. All + // 2. Require progress be made for ranges with getStage() >= RS_Spill. All // the new ranges must have fewer instructions than before the split. - // 3. New ranges with the same number of instructions are marked RS_Local, + // 3. New ranges with the same number of instructions are marked RS_Spill, // smaller ranges are marked RS_New. // // These rules allow a 3 -> 2+3 split once, which we need. They also prevent // excessive splitting and infinite loops. // - bool ProgressRequired = getStage(VirtReg) >= RS_Local; + bool ProgressRequired = getStage(VirtReg) >= RS_Spill; // Best split candidate. unsigned BestBefore = NumGaps; @@ -1301,7 +1309,7 @@ DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); // If the new range has the same number of instructions as before, mark it as - // RS_Local so the next split will be forced to make progress. Otherwise, + // RS_Spill so the next split will be forced to make progress. Otherwise, // leave the new intervals as RS_New so they can compete. bool LiveBefore = BestBefore != 0 || BI.LiveIn; bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; @@ -1311,7 +1319,7 @@ assert(!ProgressRequired && "Didn't make progress when it was required."); for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) if (IntvMap[i] == 1) { - setStage(*LREdit.get(i), RS_Local); + setStage(*LREdit.get(i), RS_Spill); DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg)); } DEBUG(dbgs() << '\n'); @@ -1341,7 +1349,7 @@ // Don't iterate global splitting. // Move straight to spilling if this range was produced by a global split. - if (getStage(VirtReg) >= RS_Global) + if (getStage(VirtReg) >= RS_Spill) return 0; SA->analyze(&VirtReg); @@ -1368,7 +1376,7 @@ LiveRangeEdit LREdit(VirtReg, NewVRegs, this); SE->reset(LREdit); SE->splitSingleBlocks(Blocks); - setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global); + setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill); if (VerifyEnabled) MF->verify(this, "After splitting live range around basic blocks"); } @@ -1394,9 +1402,9 @@ << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); // Try to evict a less worthy live range, but only for ranges from the primary - // queue. The RS_Second ranges already failed to do this, and they should not + // queue. The RS_Split ranges already failed to do this, and they should not // get a second chance until they have been split. - if (Stage != RS_Second) + if (Stage != RS_Split) if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) return PhysReg; @@ -1405,8 +1413,8 @@ // The first time we see a live range, don't try to split or spill. // Wait until the second time, when all smaller ranges have been allocated. // This gives a better picture of the interference to split around. - if (Stage == RS_First) { - setStage(VirtReg, RS_Second); + if (Stage < RS_Split) { + setStage(VirtReg, RS_Split); DEBUG(dbgs() << "wait for second round\n"); NewVRegs.push_back(&VirtReg); return 0; @@ -1414,7 +1422,7 @@ // If we couldn't allocate a register from spilling, there is probably some // invalid inline assembly. The base class wil report it. - if (Stage >= RS_Spill || !VirtReg.isSpillable()) + if (Stage >= RS_Done || !VirtReg.isSpillable()) return ~0u; // Try splitting VirtReg or interferences. @@ -1426,7 +1434,7 @@ NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled); LiveRangeEdit LRE(VirtReg, NewVRegs, this); spiller().spill(LRE); - setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill); + setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done); if (VerifyEnabled) MF->verify(this, "After spilling"); From rafael.espindola at gmail.com Mon Jul 25 10:28:00 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 25 Jul 2011 15:28:00 -0000 Subject: [llvm-commits] [llvm] r135913 - /llvm/trunk/docs/LangRef.html Message-ID: <20110725152800.526952A6C12C@llvm.org> Author: rafael Date: Mon Jul 25 10:27:59 2011 New Revision: 135913 URL: http://llvm.org/viewvc/llvm-project?rev=135913&view=rev Log: Add uwtable to the langref. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=135913&r1=135912&r2=135913&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Jul 25 10:27:59 2011 @@ -1247,6 +1247,14 @@ function that doesn't have an sspreq attribute or which has an ssp attribute, then the resulting function will have an sspreq attribute. + +
    uwtable
    +
    This attribute indicates that the ABI being targeted requires that + an unwind table entry be produce for this function even if we can + show that no exceptions passes by it. This is normally the case for + the ELF x86-64 abi, but it can be disabled for some compilation + units.
    + From grosbach at apple.com Mon Jul 25 12:11:29 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 17:11:29 -0000 Subject: [llvm-commits] [llvm] r135917 - /llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Message-ID: <20110725171129.A6AAC2A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 12:11:29 2011 New Revision: 135917 URL: http://llvm.org/viewvc/llvm-project?rev=135917&view=rev Log: Tidy up. 80 columns. Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=135917&r1=135916&r2=135917&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Mon Jul 25 12:11:29 2011 @@ -47,12 +47,17 @@ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveRoData>(".rodata"); AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTData>(".tdata"); AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTBSS>(".tbss"); - AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRel>(".data.rel"); - AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRo>(".data.rel.ro"); - AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRoLocal>(".data.rel.ro.local"); - AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame"); + AddDirectiveHandler< + &ELFAsmParser::ParseSectionDirectiveDataRel>(".data.rel"); + AddDirectiveHandler< + &ELFAsmParser::ParseSectionDirectiveDataRelRo>(".data.rel.ro"); + AddDirectiveHandler< + &ELFAsmParser::ParseSectionDirectiveDataRelRoLocal>(".data.rel.ro.local"); + AddDirectiveHandler< + &ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSection>(".section"); - AddDirectiveHandler<&ELFAsmParser::ParseDirectivePushSection>(".pushsection"); + AddDirectiveHandler< + &ELFAsmParser::ParseDirectivePushSection>(".pushsection"); AddDirectiveHandler<&ELFAsmParser::ParseDirectivePopSection>(".popsection"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size"); AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous"); From ofv at wanadoo.es Mon Jul 25 12:24:54 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 25 Jul 2011 17:24:54 -0000 Subject: [llvm-commits] [llvm] r135918 - /llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp Message-ID: <20110725172454.3780C2A6C12C@llvm.org> Author: ofv Date: Mon Jul 25 12:24:54 2011 New Revision: 135918 URL: http://llvm.org/viewvc/llvm-project?rev=135918&view=rev Log: Fixes VS support for llvmc mcc16 llvmc example. Patch by arrowdodger! Modified: llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp Modified: llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp?rev=135918&r1=135917&r2=135918&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp (original) +++ llvm/trunk/tools/llvmc/examples/mcc16/Hooks.cpp Mon Jul 25 12:24:54 2011 @@ -3,9 +3,10 @@ #include "llvm/Support/raw_ostream.h" #include +#include namespace llvmc { - extern char *ProgramName; + extern const char *ProgramName; namespace autogenerated { extern llvm::cl::opt Parameter_p; @@ -31,6 +32,7 @@ // It is __partname format in lower case. std::string GetLowerCasePartDefine(void) { + std::locale loc; std::string Partname; if (autogenerated::Parameter_p.empty()) { Partname = "16f1xxx"; @@ -40,7 +42,7 @@ std::string LowerCase; for (unsigned i = 0; i < Partname.size(); i++) { - LowerCase.push_back(std::tolower(Partname[i])); + LowerCase.push_back(std::tolower(Partname[i], loc)); } return "__" + LowerCase; @@ -48,6 +50,7 @@ std::string GetUpperCasePartDefine(void) { + std::locale loc; std::string Partname; if (autogenerated::Parameter_p.empty()) { Partname = "16f1xxx"; @@ -57,7 +60,7 @@ std::string UpperCase; for (unsigned i = 0; i < Partname.size(); i++) { - UpperCase.push_back(std::toupper(Partname[i])); + UpperCase.push_back(std::toupper(Partname[i], loc)); } return "__" + UpperCase; From ofv at wanadoo.es Mon Jul 25 12:25:10 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 25 Jul 2011 17:25:10 -0000 Subject: [llvm-commits] [llvm] r135919 - in /llvm/trunk/tools/llvmc: CMakeLists.txt examples/CMakeLists.txt examples/Hello/CMakeLists.txt examples/Simple/CMakeLists.txt examples/Skeleton/CMakeLists.txt examples/mcc16/CMakeLists.txt src/CMakeLists.txt Message-ID: <20110725172510.935312A6C12C@llvm.org> Author: ofv Date: Mon Jul 25 12:25:10 2011 New Revision: 135919 URL: http://llvm.org/viewvc/llvm-project?rev=135919&view=rev Log: Builds llvmc and its examples with CMake. Patch by arrowdodger! Added: llvm/trunk/tools/llvmc/examples/CMakeLists.txt llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt llvm/trunk/tools/llvmc/src/CMakeLists.txt Modified: llvm/trunk/tools/llvmc/CMakeLists.txt Modified: llvm/trunk/tools/llvmc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/CMakeLists.txt?rev=135919&r1=135918&r2=135919&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/CMakeLists.txt (original) +++ llvm/trunk/tools/llvmc/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -1,4 +1,8 @@ -# add_subdirectory(src) +add_subdirectory(src) # TODO: support plugins and user-configured builds. # See ./doc/LLVMC-Reference.rst "Customizing LLVMC: the compilation graph" + +if( LLVM_INCLUDE_EXAMPLES ) + add_subdirectory(examples) +endif() Added: llvm/trunk/tools/llvmc/examples/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/examples/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/examples/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,4 @@ +add_subdirectory(Hello) +add_subdirectory(Simple) +add_subdirectory(mcc16) +add_subdirectory(Skeleton) Added: llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,4 @@ +set(LLVM_USED_LIBS CompilerDriver) +set(LLVM_LINK_COMPONENTS support) + +add_llvm_example(Hello Hello.cpp) Added: llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,10 @@ +set(LLVM_TARGET_DEFINITIONS Simple.td) + +tablegen(Simple.inc -gen-llvmc) + +set(LLVM_USED_LIBS CompilerDriver) +set(LLVM_LINK_COMPONENTS support) + +add_llvm_example(Simple + Simple.cpp + ) Added: llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,11 @@ +set(LLVM_TARGET_DEFINITIONS AutoGenerated.td) + +tablegen(AutoGenerated.inc -gen-llvmc) + +set(LLVM_USED_LIBS CompilerDriver) +set(LLVM_LINK_COMPONENTS support) + +add_llvm_example(llvmc-skeleton + Hooks.cpp + Main.cpp + ) Added: llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,11 @@ +set(LLVM_TARGET_DEFINITIONS PIC16.td) + +tablegen(PIC16.inc -gen-llvmc) + +set(LLVM_USED_LIBS CompilerDriver) +set(LLVM_LINK_COMPONENTS support) + +add_llvm_example(mcc16 + Hooks.cpp + Main.cpp + ) Added: llvm/trunk/tools/llvmc/src/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/CMakeLists.txt?rev=135919&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/src/CMakeLists.txt (added) +++ llvm/trunk/tools/llvmc/src/CMakeLists.txt Mon Jul 25 12:25:10 2011 @@ -0,0 +1,19 @@ +set(LLVMGCCCOMMAND llvm-gcc) +set(LLVMGXXCOMMAND llvm-g++) + +configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/Base.td.in + ${CMAKE_CURRENT_BINARY_DIR}/Base.td + @ONLY) + +set(LLVM_TARGET_DEFINITIONS AutoGenerated.td) + +tablegen(AutoGenerated.inc -gen-llvmc) + +set(LLVM_USED_LIBS CompilerDriver) +set(LLVM_LINK_COMPONENTS support) + +add_llvm_tool(llvmc + Hooks.cpp + Main.cpp + ) From ofv at wanadoo.es Mon Jul 25 12:26:48 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Mon, 25 Jul 2011 19:26:48 +0200 Subject: [llvm-commits] [PATCH][CMake] Connect llvmc tool to the build. In-Reply-To: (arrowdodger's message of "Mon, 25 Jul 2011 21:14:32 +0400") References: <87mxg2ih7z.fsf@wanadoo.es> <87hb6aidrz.fsf@wanadoo.es> <87d3gyicms.fsf@wanadoo.es> Message-ID: <8739hui84n.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > 2011/7/25 ?scar Fuentes > >> Absolutely. We don't want to break the build for the VS users. CMake is >> the only method they have for building LLVM. >> > > Build on Windows unveiled fex bugs. After fixing them, i've successfully > built llvmc and it's examples on Windows XP SP3 with VS2008. > Updated patch attached. Committed. Thanks! From bruno.cardoso at gmail.com Mon Jul 25 12:55:41 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 25 Jul 2011 10:55:41 -0700 Subject: [llvm-commits] [PATCH] Vector-select patch In-Reply-To: <6594DDFF12B03D4E89690887C24869940296D9096B@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C24869940296D9096B@hasmsx504.ger.corp.intel.com> Message-ID: Hi Nadav, > Please review the attached file. The type legalization changes are mostly > complete, and it is possible to match vector instructions. ?This patch > contains the code-independent parts of the vector select. MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { - return MVT::i8; + if (!VT.isVector()) return MVT::i8; + switch (VT.getVectorNumElements()) { + default: + assert(false && "unknown vector size"); + case 2: return MVT::v2i64; + case 4: return MVT::v4i32; + case 8: return MVT::v8i16; + case 16: return MVT::v16i8; + } } Could you please add the 256-bit AVX types here? -- Bruno Cardoso Lopes http://www.brunocardoso.cc From grosbach at apple.com Mon Jul 25 12:55:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 17:55:35 -0000 Subject: [llvm-commits] [llvm] r135921 - in /llvm/trunk: lib/MC/MCMachOStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/COFFAsmParser.cpp lib/MC/MCParser/ELFAsmParser.cpp test/MC/AsmParser/labels.s Message-ID: <20110725175535.B63DD2A6C12D@llvm.org> Author: grosbach Date: Mon Jul 25 12:55:35 2011 New Revision: 135921 URL: http://llvm.org/viewvc/llvm-project?rev=135921&view=rev Log: Move some ELF directives into ELF asm parser. The .local, .hidden, .internal, and .protected are not legal for all supported file formats (in particular, they're invalid for MachO). Move the parsing for them into the ELF assembly parser since that's the format they're for. Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing to the COFF and ELF asm parsers. Previously, using any of these directives on Darwin would result in an assertion failure in the parser; now we get a diagnostic as we should. rdar://9827089 Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/test/MC/AsmParser/labels.s Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=135921&r1=135920&r2=135921&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Jul 25 12:55:35 2011 @@ -207,7 +207,6 @@ case MCSA_ELF_TypeCommon: case MCSA_ELF_TypeNoType: case MCSA_ELF_TypeGnuUniqueObject: - case MCSA_IndirectSymbol: case MCSA_Hidden: case MCSA_Internal: case MCSA_Protected: Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=135921&r1=135920&r2=135921&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 25 12:55:35 2011 @@ -1117,15 +1117,8 @@ if (IDVal == ".globl" || IDVal == ".global") return ParseDirectiveSymbolAttribute(MCSA_Global); - // ELF only? Should it be here? - if (IDVal == ".local") - return ParseDirectiveSymbolAttribute(MCSA_Local); - if (IDVal == ".hidden") - return ParseDirectiveSymbolAttribute(MCSA_Hidden); if (IDVal == ".indirect_symbol") return ParseDirectiveSymbolAttribute(MCSA_IndirectSymbol); - if (IDVal == ".internal") - return ParseDirectiveSymbolAttribute(MCSA_Internal); if (IDVal == ".lazy_reference") return ParseDirectiveSymbolAttribute(MCSA_LazyReference); if (IDVal == ".no_dead_strip") @@ -1134,12 +1127,8 @@ return ParseDirectiveSymbolAttribute(MCSA_SymbolResolver); if (IDVal == ".private_extern") return ParseDirectiveSymbolAttribute(MCSA_PrivateExtern); - if (IDVal == ".protected") - return ParseDirectiveSymbolAttribute(MCSA_Protected); if (IDVal == ".reference") return ParseDirectiveSymbolAttribute(MCSA_Reference); - if (IDVal == ".weak") - return ParseDirectiveSymbolAttribute(MCSA_Weak); if (IDVal == ".weak_definition") return ParseDirectiveSymbolAttribute(MCSA_WeakDefinition); if (IDVal == ".weak_reference") Modified: llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp?rev=135921&r1=135920&r2=135921&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp Mon Jul 25 12:55:35 2011 @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/MCParser/MCAsmParserExtension.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" @@ -72,6 +73,7 @@ ".seh_pushframe"); AddDirectiveHandler<&COFFAsmParser::ParseSEHDirectiveEndProlog>( ".seh_endprologue"); + AddDirectiveHandler<&COFFAsmParser::ParseDirectiveSymbolAttribute>(".weak"); } bool ParseSectionDirectiveText(StringRef, SMLoc) { @@ -118,12 +120,44 @@ bool ParseAtUnwindOrAtExcept(bool &unwind, bool &except); bool ParseSEHRegisterNumber(unsigned &RegNo); + bool ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc); public: COFFAsmParser() {} }; } // end annonomous namespace. +/// ParseDirectiveSymbolAttribute +/// ::= { ".weak", ... } [ identifier ( , identifier )* ] +bool COFFAsmParser::ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc) { + MCSymbolAttr Attr = StringSwitch(Directive) + .Case(".weak", MCSA_Weak) + .Default(MCSA_Invalid); + assert(Attr != MCSA_Invalid && "unexpected symbol attribute directive!"); + if (getLexer().isNot(AsmToken::EndOfStatement)) { + for (;;) { + StringRef Name; + + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + getStreamer().EmitSymbolAttribute(Sym, Attr); + + if (getLexer().is(AsmToken::EndOfStatement)) + break; + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + } + } + + Lex(); + return false; +} + bool COFFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Characteristics, SectionKind Kind) { Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=135921&r1=135920&r2=135921&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Mon Jul 25 12:55:35 2011 @@ -65,6 +65,14 @@ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymver>(".symver"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveWeakref>(".weakref"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymbolAttribute>(".weak"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymbolAttribute>(".local"); + AddDirectiveHandler< + &ELFAsmParser::ParseDirectiveSymbolAttribute>(".protected"); + AddDirectiveHandler< + &ELFAsmParser::ParseDirectiveSymbolAttribute>(".internal"); + AddDirectiveHandler< + &ELFAsmParser::ParseDirectiveSymbolAttribute>(".hidden"); } // FIXME: Part of this logic is duplicated in the MCELFStreamer. What is @@ -134,6 +142,7 @@ bool ParseDirectiveIdent(StringRef, SMLoc); bool ParseDirectiveSymver(StringRef, SMLoc); bool ParseDirectiveWeakref(StringRef, SMLoc); + bool ParseDirectiveSymbolAttribute(StringRef, SMLoc); private: bool ParseSectionName(StringRef &SectionName); @@ -141,6 +150,41 @@ } +/// ParseDirectiveSymbolAttribute +/// ::= { ".local", ".weak", ... } [ identifier ( , identifier )* ] +bool ELFAsmParser::ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc) { + MCSymbolAttr Attr = StringSwitch(Directive) + .Case(".weak", MCSA_Weak) + .Case(".local", MCSA_Local) + .Case(".hidden", MCSA_Hidden) + .Case(".internal", MCSA_Internal) + .Case(".protected", MCSA_Protected) + .Default(MCSA_Invalid); + assert(Attr != MCSA_Invalid && "unexpected symbol attribute directive!"); + if (getLexer().isNot(AsmToken::EndOfStatement)) { + for (;;) { + StringRef Name; + + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + getStreamer().EmitSymbolAttribute(Sym, Attr); + + if (getLexer().is(AsmToken::EndOfStatement)) + break; + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + } + } + + Lex(); + return false; +} + bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind) { if (getLexer().isNot(AsmToken::EndOfStatement)) Modified: llvm/trunk/test/MC/AsmParser/labels.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/labels.s?rev=135921&r1=135920&r2=135921&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/labels.s (original) +++ llvm/trunk/test/MC/AsmParser/labels.s Mon Jul 25 12:55:35 2011 @@ -35,9 +35,6 @@ // CHECK: .globl "a 3" .globl "a 3" -// CHECK: .weak "a 4" - .weak "a 4" - // CHECK: .desc "a 5",1 .desc "a 5", 1 From isanbard at gmail.com Mon Jul 25 13:00:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 18:00:28 -0000 Subject: [llvm-commits] [llvm] r135922 - in /llvm/trunk/lib/Target/X86: X86FrameLowering.cpp X86FrameLowering.h Message-ID: <20110725180028.BC32C2A6C12C@llvm.org> Author: void Date: Mon Jul 25 13:00:28 2011 New Revision: 135922 URL: http://llvm.org/viewvc/llvm-project?rev=135922&view=rev Log: After we've modified the prolog to save volatile registers, generate the compact unwind encoding for that function. This simply crawls through the prolog looking for machine instrs marked as "frame setup". It can calculate from these what the compact unwind should look like. This is currently disabled because of needed linker support. But initial tests look good. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.h Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135922&r1=135921&r2=135922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Jul 25 13:00:28 2011 @@ -283,8 +283,8 @@ } void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, - MCSymbol *Label, - unsigned FramePtr) const { + MCSymbol *Label, + unsigned FramePtr) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); @@ -346,6 +346,245 @@ } } +/// getCompactUnwindRegNum - Get the compact unwind number for a given +/// register. The number corresponds to the enum lists in +/// compact_unwind_encoding.h. +static int getCompactUnwindRegNum(const unsigned *CURegs, unsigned Reg) { + int Idx = 1; + for (; *CURegs; ++CURegs, ++Idx) + if (*CURegs == Reg) + return Idx; + + return -1; +} + +/// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding +/// used with frameless stacks. It is passed the number of registers to be saved +/// and an array of the registers saved. +static uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[6], + unsigned RegCount, + bool Is64Bit) { + // The saved registers are numbered from 1 to 6. In order to encode the order + // in which they were saved, we re-number them according to their place in the + // register order. The re-numbering is relative to the last re-numbered + // register. E.g., if we have registers {6, 2, 4, 5} saved in that order: + // + // Orig Re-Num + // ---- ------ + // 6 6 + // 2 2 + // 4 3 + // 5 3 + // + static const unsigned CU32BitRegs[] = { + X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 + }; + static const unsigned CU64BitRegs[] = { + X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 + }; + const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); + + uint32_t RenumRegs[6]; + for (unsigned i = 6 - RegCount; i < 6; ++i) { + int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]); + if (CUReg == -1) return ~0U; + SavedRegs[i] = CUReg; + + unsigned Countless = 0; + for (unsigned j = 6 - RegCount; j < i; ++j) + if (SavedRegs[j] < SavedRegs[i]) + ++Countless; + + RenumRegs[i] = SavedRegs[i] - Countless - 1; + } + + // Take the renumbered values and encode them into a 10-bit number. + uint32_t permutationEncoding = 0; + switch (RegCount) { + case 6: + permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] + + 6 * RenumRegs[2] + 2 * RenumRegs[3] + + RenumRegs[4]; + break; + case 5: + permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] + + 6 * RenumRegs[3] + 2 * RenumRegs[4] + + RenumRegs[5]; + break; + case 4: + permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] + + 3 * RenumRegs[4] + RenumRegs[5]; + break; + case 3: + permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] + + RenumRegs[5]; + break; + case 2: + permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; + break; + case 1: + permutationEncoding |= RenumRegs[5]; + break; + } + + assert((permutationEncoding & 0x3FF) == permutationEncoding && + "Invalid compact register encoding!"); + return permutationEncoding; +} + +/// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a +/// compact encoding with a frame pointer. +static uint32_t encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[6], + bool Is64Bit) { + static const unsigned CU32BitRegs[] = { + X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 + }; + static const unsigned CU64BitRegs[] = { + X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 + }; + const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); + + // Encode the registers in the order they were saved, 3-bits per register. The + // registers are numbered from 1 to 6. + uint32_t RegEnc = 0; + for (int I = 5; I >= 0; --I) { + unsigned Reg = SavedRegs[I]; + if (Reg == 0) break; + int CURegNum = getCompactUnwindRegNum(CURegs, Reg); + if (CURegNum == -1) + return ~0U; + RegEnc |= (CURegNum & 0x7) << (5 - I); + } + + assert((RegEnc & 0x7FFF) == RegEnc && "Invalid compact register encoding!"); + return RegEnc; +} + +uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const { + const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); + unsigned FramePtr = RegInfo->getFrameRegister(MF); + unsigned StackPtr = RegInfo->getStackRegister(); + + X86MachineFunctionInfo *X86FI = MF.getInfo(); + int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); + + bool Is64Bit = STI.is64Bit(); + bool HasFP = hasFP(MF); + + unsigned SavedRegs[6] = { 0, 0, 0, 0, 0, 0 }; + int SavedRegIdx = 6; + + unsigned OffsetSize = (Is64Bit ? 8 : 4); + + unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r); + unsigned PushInstrSize = 1; + unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); + unsigned MoveInstrSize = (Is64Bit ? 3 : 2); + unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta); + unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); + + unsigned InstrOffset = 0; + unsigned CFAOffset = 0; + unsigned StackAdjust = 0; + + MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB. + bool ExpectEnd = false; + for (MachineBasicBlock::iterator + MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) { + MachineInstr &MI = *MBBI; + unsigned Opc = MI.getOpcode(); + if (Opc == X86::PROLOG_LABEL) continue; + if (!MI.getFlag(MachineInstr::FrameSetup)) break; + + // We don't exect any more prolog instructions. + if (ExpectEnd) return 0; + + if (Opc == PushInstr) { + // If there are too many saved registers, we cannot use compact encoding. + if (--SavedRegIdx < 0) return 0; + + SavedRegs[SavedRegIdx] = MI.getOperand(0).getReg(); + CFAOffset += OffsetSize; + InstrOffset += PushInstrSize; + } else if (Opc == MoveInstr) { + unsigned SrcReg = MI.getOperand(1).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); + + if (DstReg != FramePtr || SrcReg != StackPtr) + return 0; + + CFAOffset = 0; + memset(SavedRegs, 0, sizeof(SavedRegs)); + InstrOffset += MoveInstrSize; + } else if (Opc == SubtractInstr) { + if (StackAdjust) + // We all ready have a stack pointer adjustment. + return 0; + + if (!MI.getOperand(0).isReg() || + MI.getOperand(0).getReg() != MI.getOperand(1).getReg() || + MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm()) + // We need this to be a stack adjustment pointer. Something like: + // + // %RSP = SUB64ri8 %RSP, 48 + return 0; + + StackAdjust = MI.getOperand(2).getImm() / 4; + SubtractInstrIdx += InstrOffset; + ExpectEnd = true; + } + } + + // Encode that we are using EBP/RBP as the frame pointer. + uint32_t CompactUnwindEncoding = 0; + CFAOffset /= 4; + if (HasFP) { + if ((CFAOffset & 0xFF) != CFAOffset) + // Offset was too big for compact encoding. + return 0; + + // Get the encoding of the saved registers when we have a frame pointer. + uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit); + if (RegEnc == ~0U) + return 0; + + CompactUnwindEncoding |= 0x01000000; + CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16; + CompactUnwindEncoding |= RegEnc & 0x7FFF; + } else { + unsigned FullOffset = CFAOffset + StackAdjust; + if ((FullOffset & 0xFF) == FullOffset) { + // Frameless stack. + CompactUnwindEncoding |= 0x02000000; + CompactUnwindEncoding |= (FullOffset & 0xFF) << 16; + } else { + if ((CFAOffset & 0x7) != CFAOffset) + // The extra stack adjustments are too big for us to handle. + return 0; + + // Frameless stack with an offset too large for us to encode compactly. + CompactUnwindEncoding |= 0x03000000; + + // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' + // instruction. + CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; + + // Encode any extra stack stack changes (done via push instructions). + CompactUnwindEncoding |= (CFAOffset & 0x7) << 13; + } + + // Get the encoding of the saved registers when we don't have a frame + // pointer. + uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegs, + 6 - SavedRegIdx, + Is64Bit); + if (RegEnc == ~0U) return 0; + CompactUnwindEncoding |= RegEnc & 0x3FF; + } + + return CompactUnwindEncoding; +} + /// emitPrologue - Push callee-saved registers onto the stack, which /// automatically adjust the stack pointer. Adjust the stack pointer to allocate /// space for local variables. Also emit labels used by the exception handler to @@ -478,7 +717,7 @@ Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); } - // Update EBP with the new base value... + // Update EBP with the new base value. BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) .addReg(StackPtr) @@ -520,6 +759,7 @@ // Skip the callee-saved push instructions. bool PushedRegs = false; int StackOffset = 2 * stackGrowth; + SmallVector SavedRegs; while (MBBI != MBB.end() && (MBBI->getOpcode() == X86::PUSH32r || @@ -534,8 +774,7 @@ BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); // Define the current CFA rule to use the provided offset. - unsigned Ptr = StackSize ? - MachineLocation::VirtualFP : StackPtr; + unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr; MachineLocation SPDst(Ptr); MachineLocation SPSrc(Ptr, StackOffset); Moves.push_back(MachineMove(Label, SPDst, SPSrc)); @@ -657,6 +896,11 @@ if (PushedRegs) emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr); } + + // Darwin 10.7 and greater has support for compact unwind encoding. + if (false && // FIXME: Enable once linker support is available. + STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) + MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); } void X86FrameLowering::emitEpilogue(MachineFunction &MF, Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=135922&r1=135921&r2=135922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Mon Jul 25 13:00:28 2011 @@ -58,6 +58,7 @@ bool hasReservedCallFrame(const MachineFunction &MF) const; int getFrameIndexOffset(const MachineFunction &MF, int FI) const; + uint32_t getCompactUnwindEncoding(MachineFunction &MF) const; }; } // End llvm namespace From isanbard at gmail.com Mon Jul 25 13:01:27 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 18:01:27 -0000 Subject: [llvm-commits] [llvm] r135923 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110725180127.44AC72A6C12C@llvm.org> Author: void Date: Mon Jul 25 13:01:27 2011 New Revision: 135923 URL: http://llvm.org/viewvc/llvm-project?rev=135923&view=rev Log: Remove dead variable. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135923&r1=135922&r2=135923&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Jul 25 13:01:27 2011 @@ -759,7 +759,6 @@ // Skip the callee-saved push instructions. bool PushedRegs = false; int StackOffset = 2 * stackGrowth; - SmallVector SavedRegs; while (MBBI != MBB.end() && (MBBI->getOpcode() == X86::PUSH32r || From isanbard at gmail.com Mon Jul 25 13:04:49 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 18:04:49 -0000 Subject: [llvm-commits] [llvm] r135924 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110725180449.585D12A6C12C@llvm.org> Author: void Date: Mon Jul 25 13:04:49 2011 New Revision: 135924 URL: http://llvm.org/viewvc/llvm-project?rev=135924&view=rev Log: Changed disabled code into a flag. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135924&r1=135923&r2=135924&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Jul 25 13:04:49 2011 @@ -34,6 +34,12 @@ // FIXME: completely move here. extern cl::opt ForceStackAlign; +// FIXME: Remove once linker support is available. +static cl::opt +GenerateCompactUnwind("gen-compact-unwind", + cl::desc("Generate compact unwind encoding"), + cl::Hidden); + bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { return !MF.getFrameInfo()->hasVarSizedObjects(); } @@ -897,7 +903,7 @@ } // Darwin 10.7 and greater has support for compact unwind encoding. - if (false && // FIXME: Enable once linker support is available. + if (GenerateCompactUnwind && STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); } From criswell at uiuc.edu Mon Jul 25 13:06:52 2011 From: criswell at uiuc.edu (John Criswell) Date: Mon, 25 Jul 2011 18:06:52 -0000 Subject: [llvm-commits] [poolalloc] r135926 - /poolalloc/branches/release_27/ Message-ID: <20110725180652.E270E2A6C12C@llvm.org> Author: criswell Date: Mon Jul 25 13:06:52 2011 New Revision: 135926 URL: http://llvm.org/viewvc/llvm-project?rev=135926&view=rev Log: Creating the release_27 branch of poolalloc. Added: poolalloc/branches/release_27/ (props changed) - copied from r135925, poolalloc/trunk/ Propchange: poolalloc/branches/release_27/ ------------------------------------------------------------------------------ svn:mergeinfo = /poolalloc/branches/release_26:97820-104253 From evan.cheng at apple.com Mon Jul 25 13:43:53 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 18:43:53 -0000 Subject: [llvm-commits] [llvm] r135930 - in /llvm/trunk/lib: MC/ELFObjectWriter.cpp MC/WinCOFFObjectWriter.cpp Target/X86/MCTargetDesc/X86BaseInfo.h Target/X86/MCTargetDesc/X86FixupKinds.h Target/X86/MCTargetDesc/X86MCTargetDesc.h Target/X86/X86.h Target/X86/X86AsmBackend.cpp Target/X86/X86CodeEmitter.cpp Target/X86/X86FixupKinds.h Target/X86/X86InstrInfo.cpp Target/X86/X86InstrInfo.h Target/X86/X86MCCodeEmitter.cpp Target/X86/X86MachObjectWriter.cpp Message-ID: <20110725184353.94E452A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 13:43:53 2011 New Revision: 135930 URL: http://llvm.org/viewvc/llvm-project?rev=135930&view=rev Log: Refactor X86 target to separate MC code from Target code. Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h llvm/trunk/lib/Target/X86/MCTargetDesc/X86FixupKinds.h - copied unchanged from r135824, llvm/trunk/lib/Target/X86/X86FixupKinds.h Removed: llvm/trunk/lib/Target/X86/X86FixupKinds.h Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Jul 25 13:43:53 2011 @@ -28,7 +28,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringSwitch.h" -#include "../Target/X86/X86FixupKinds.h" +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" #include "../Target/ARM/MCTargetDesc/ARMFixupKinds.h" #include Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Mon Jul 25 13:43:53 2011 @@ -33,7 +33,7 @@ #include "llvm/Support/TimeValue.h" -#include "../Target/X86/X86FixupKinds.h" +#include "../Target/X86/MCTargetDesc/X86FixupKinds.h" #include Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=135930&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (added) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Mon Jul 25 13:43:53 2011 @@ -0,0 +1,544 @@ +//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the X86 target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef X86BASEINFO_H +#define X86BASEINFO_H + +#include "X86MCTargetDesc.h" +#include "llvm/Support/DataTypes.h" +#include + +namespace llvm { + +namespace X86 { + // Enums for memory operand decoding. Each memory operand is represented with + // a 5 operand sequence in the form: + // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] + // These enums help decode this. + enum { + AddrBaseReg = 0, + AddrScaleAmt = 1, + AddrIndexReg = 2, + AddrDisp = 3, + + /// AddrSegmentReg - The operand # of the segment in the memory operand. + AddrSegmentReg = 4, + + /// AddrNumOperands - Total number of operands in a memory reference. + AddrNumOperands = 5 + }; +} // end namespace X86; + + +/// X86II - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +namespace X86II { + /// Target Operand Flag enum. + enum TOF { + //===------------------------------------------------------------------===// + // X86 Specific MachineOperand flags. + + MO_NO_FLAG, + + /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a + /// relocation of: + /// SYMBOL_LABEL + [. - PICBASELABEL] + MO_GOT_ABSOLUTE_ADDRESS, + + /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the + /// immediate should get the value of the symbol minus the PIC base label: + /// SYMBOL_LABEL - PICBASELABEL + MO_PIC_BASE_OFFSET, + + /// MO_GOT - On a symbol operand this indicates that the immediate is the + /// offset to the GOT entry for the symbol name from the base of the GOT. + /// + /// See the X86-64 ELF ABI supplement for more details. + /// SYMBOL_LABEL @GOT + MO_GOT, + + /// MO_GOTOFF - On a symbol operand this indicates that the immediate is + /// the offset to the location of the symbol name from the base of the GOT. + /// + /// See the X86-64 ELF ABI supplement for more details. + /// SYMBOL_LABEL @GOTOFF + MO_GOTOFF, + + /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is + /// offset to the GOT entry for the symbol name from the current code + /// location. + /// + /// See the X86-64 ELF ABI supplement for more details. + /// SYMBOL_LABEL @GOTPCREL + MO_GOTPCREL, + + /// MO_PLT - On a symbol operand this indicates that the immediate is + /// offset to the PLT entry of symbol name from the current code location. + /// + /// See the X86-64 ELF ABI supplement for more details. + /// SYMBOL_LABEL @PLT + MO_PLT, + + /// MO_TLSGD - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// See 'ELF Handling for Thread-Local Storage' for more details. + /// SYMBOL_LABEL @TLSGD + MO_TLSGD, + + /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// See 'ELF Handling for Thread-Local Storage' for more details. + /// SYMBOL_LABEL @GOTTPOFF + MO_GOTTPOFF, + + /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// See 'ELF Handling for Thread-Local Storage' for more details. + /// SYMBOL_LABEL @INDNTPOFF + MO_INDNTPOFF, + + /// MO_TPOFF - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// See 'ELF Handling for Thread-Local Storage' for more details. + /// SYMBOL_LABEL @TPOFF + MO_TPOFF, + + /// MO_NTPOFF - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// See 'ELF Handling for Thread-Local Storage' for more details. + /// SYMBOL_LABEL @NTPOFF + MO_NTPOFF, + + /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the + /// reference is actually to the "__imp_FOO" symbol. This is used for + /// dllimport linkage on windows. + MO_DLLIMPORT, + + /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the + /// reference is actually to the "FOO$stub" symbol. This is used for calls + /// and jumps to external functions on Tiger and earlier. + MO_DARWIN_STUB, + + /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the + /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a + /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. + MO_DARWIN_NONLAZY, + + /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates + /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is + /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. + MO_DARWIN_NONLAZY_PIC_BASE, + + /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this + /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", + /// which is a PIC-base-relative reference to a hidden dyld lazy pointer + /// stub. + MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, + + /// MO_TLVP - On a symbol operand this indicates that the immediate is + /// some TLS offset. + /// + /// This is the TLS offset for the Darwin TLS mechanism. + MO_TLVP, + + /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate + /// is some TLS offset from the picbase. + /// + /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. + MO_TLVP_PIC_BASE + }; + + enum { + //===------------------------------------------------------------------===// + // Instruction encodings. These are the standard/most common forms for X86 + // instructions. + // + + // PseudoFrm - This represents an instruction that is a pseudo instruction + // or one that has not been implemented yet. It is illegal to code generate + // it, but tolerated for intermediate implementation stages. + Pseudo = 0, + + /// Raw - This form is for instructions that don't have any operands, so + /// they are just a fixed opcode value, like 'leave'. + RawFrm = 1, + + /// AddRegFrm - This form is used for instructions like 'push r32' that have + /// their one register operand added to their opcode. + AddRegFrm = 2, + + /// MRMDestReg - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is a register. + /// + MRMDestReg = 3, + + /// MRMDestMem - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is memory. + /// + MRMDestMem = 4, + + /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is a register. + /// + MRMSrcReg = 5, + + /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is memory. + /// + MRMSrcMem = 6, + + /// MRM[0-7][rm] - These forms are used to represent instructions that use + /// a Mod/RM byte, and use the middle field to hold extended opcode + /// information. In the intel manual these are represented as /0, /1, ... + /// + + // First, instructions that operate on a register r/m operand... + MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 + MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 + + // Next, instructions that operate on a memory r/m operand... + MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 + MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 + + // MRMInitReg - This form is used for instructions whose source and + // destinations are the same register. + MRMInitReg = 32, + + //// MRM_C1 - A mod/rm byte of exactly 0xC1. + MRM_C1 = 33, + MRM_C2 = 34, + MRM_C3 = 35, + MRM_C4 = 36, + MRM_C8 = 37, + MRM_C9 = 38, + MRM_E8 = 39, + MRM_F0 = 40, + MRM_F8 = 41, + MRM_F9 = 42, + MRM_D0 = 45, + MRM_D1 = 46, + + /// RawFrmImm8 - This is used for the ENTER instruction, which has two + /// immediates, the first of which is a 16-bit immediate (specified by + /// the imm encoding) and the second is a 8-bit fixed value. + RawFrmImm8 = 43, + + /// RawFrmImm16 - This is used for CALL FAR instructions, which have two + /// immediates, the first of which is a 16 or 32-bit immediate (specified by + /// the imm encoding) and the second is a 16-bit fixed value. In the AMD + /// manual, this operand is described as pntr16:32 and pntr16:16 + RawFrmImm16 = 44, + + FormMask = 63, + + //===------------------------------------------------------------------===// + // Actual flags... + + // OpSize - Set if this instruction requires an operand size prefix (0x66), + // which most often indicates that the instruction operates on 16 bit data + // instead of 32 bit data. + OpSize = 1 << 6, + + // AsSize - Set if this instruction requires an operand size prefix (0x67), + // which most often indicates that the instruction address 16 bit address + // instead of 32 bit address (or 32 bit address in 64 bit mode). + AdSize = 1 << 7, + + //===------------------------------------------------------------------===// + // Op0Mask - There are several prefix bytes that are used to form two byte + // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is + // used to obtain the setting of this field. If no bits in this field is + // set, there is no prefix byte for obtaining a multibyte opcode. + // + Op0Shift = 8, + Op0Mask = 0x1F << Op0Shift, + + // TB - TwoByte - Set if this instruction has a two byte opcode, which + // starts with a 0x0F byte before the real opcode. + TB = 1 << Op0Shift, + + // REP - The 0xF3 prefix byte indicating repetition of the following + // instruction. + REP = 2 << Op0Shift, + + // D8-DF - These escape opcodes are used by the floating point unit. These + // values must remain sequential. + D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, + DA = 5 << Op0Shift, DB = 6 << Op0Shift, + DC = 7 << Op0Shift, DD = 8 << Op0Shift, + DE = 9 << Op0Shift, DF = 10 << Op0Shift, + + // XS, XD - These prefix codes are for single and double precision scalar + // floating point operations performed in the SSE registers. + XD = 11 << Op0Shift, XS = 12 << Op0Shift, + + // T8, TA, A6, A7 - Prefix after the 0x0F prefix. + T8 = 13 << Op0Shift, TA = 14 << Op0Shift, + A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, + + // TF - Prefix before and after 0x0F + TF = 17 << Op0Shift, + + //===------------------------------------------------------------------===// + // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. + // They are used to specify GPRs and SSE registers, 64-bit operand size, + // etc. We only cares about REX.W and REX.R bits and only the former is + // statically determined. + // + REXShift = Op0Shift + 5, + REX_W = 1 << REXShift, + + //===------------------------------------------------------------------===// + // This three-bit field describes the size of an immediate operand. Zero is + // unused so that we can tell if we forgot to set a value. + ImmShift = REXShift + 1, + ImmMask = 7 << ImmShift, + Imm8 = 1 << ImmShift, + Imm8PCRel = 2 << ImmShift, + Imm16 = 3 << ImmShift, + Imm16PCRel = 4 << ImmShift, + Imm32 = 5 << ImmShift, + Imm32PCRel = 6 << ImmShift, + Imm64 = 7 << ImmShift, + + //===------------------------------------------------------------------===// + // FP Instruction Classification... Zero is non-fp instruction. + + // FPTypeMask - Mask for all of the FP types... + FPTypeShift = ImmShift + 3, + FPTypeMask = 7 << FPTypeShift, + + // NotFP - The default, set for instructions that do not use FP registers. + NotFP = 0 << FPTypeShift, + + // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 + ZeroArgFP = 1 << FPTypeShift, + + // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst + OneArgFP = 2 << FPTypeShift, + + // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a + // result back to ST(0). For example, fcos, fsqrt, etc. + // + OneArgFPRW = 3 << FPTypeShift, + + // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an + // explicit argument, storing the result to either ST(0) or the implicit + // argument. For example: fadd, fsub, fmul, etc... + TwoArgFP = 4 << FPTypeShift, + + // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an + // explicit argument, but have no destination. Example: fucom, fucomi, ... + CompareFP = 5 << FPTypeShift, + + // CondMovFP - "2 operand" floating point conditional move instructions. + CondMovFP = 6 << FPTypeShift, + + // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. + SpecialFP = 7 << FPTypeShift, + + // Lock prefix + LOCKShift = FPTypeShift + 3, + LOCK = 1 << LOCKShift, + + // Segment override prefixes. Currently we just need ability to address + // stuff in gs and fs segments. + SegOvrShift = LOCKShift + 1, + SegOvrMask = 3 << SegOvrShift, + FS = 1 << SegOvrShift, + GS = 2 << SegOvrShift, + + // Execution domain for SSE instructions in bits 23, 24. + // 0 in bits 23-24 means normal, non-SSE instruction. + SSEDomainShift = SegOvrShift + 2, + + OpcodeShift = SSEDomainShift + 2, + + //===------------------------------------------------------------------===// + /// VEX - The opcode prefix used by AVX instructions + VEXShift = OpcodeShift + 8, + VEX = 1U << 0, + + /// VEX_W - Has a opcode specific functionality, but is used in the same + /// way as REX_W is for regular SSE instructions. + VEX_W = 1U << 1, + + /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 + /// address instructions in SSE are represented as 3 address ones in AVX + /// and the additional register is encoded in VEX_VVVV prefix. + VEX_4V = 1U << 2, + + /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, + /// must be encoded in the i8 immediate field. This usually happens in + /// instructions with 4 operands. + VEX_I8IMM = 1U << 3, + + /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current + /// instruction uses 256-bit wide registers. This is usually auto detected + /// if a VR256 register is used, but some AVX instructions also have this + /// field marked when using a f256 memory references. + VEX_L = 1U << 4, + + /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the + /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents + /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction + /// storing a classifier in the imm8 field. To simplify our implementation, + /// we handle this by storeing the classifier in the opcode field and using + /// this flag to indicate that the encoder should do the wacky 3DNow! thing. + Has3DNow0F0FOpcode = 1U << 5 + }; + + // getBaseOpcodeFor - This function returns the "base" X86 opcode for the + // specified machine instruction. + // + static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { + return TSFlags >> X86II::OpcodeShift; + } + + static inline bool hasImm(uint64_t TSFlags) { + return (TSFlags & X86II::ImmMask) != 0; + } + + /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field + /// of the specified instruction. + static inline unsigned getSizeOfImm(uint64_t TSFlags) { + switch (TSFlags & X86II::ImmMask) { + default: assert(0 && "Unknown immediate size"); + case X86II::Imm8: + case X86II::Imm8PCRel: return 1; + case X86II::Imm16: + case X86II::Imm16PCRel: return 2; + case X86II::Imm32: + case X86II::Imm32PCRel: return 4; + case X86II::Imm64: return 8; + } + } + + /// isImmPCRel - Return true if the immediate of the specified instruction's + /// TSFlags indicates that it is pc relative. + static inline unsigned isImmPCRel(uint64_t TSFlags) { + switch (TSFlags & X86II::ImmMask) { + default: assert(0 && "Unknown immediate size"); + case X86II::Imm8PCRel: + case X86II::Imm16PCRel: + case X86II::Imm32PCRel: + return true; + case X86II::Imm8: + case X86II::Imm16: + case X86II::Imm32: + case X86II::Imm64: + return false; + } + } + + /// getMemoryOperandNo - The function returns the MCInst operand # for the + /// first field of the memory operand. If the instruction doesn't have a + /// memory operand, this returns -1. + /// + /// Note that this ignores tied operands. If there is a tied register which + /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only + /// counted as one operand. + /// + static inline int getMemoryOperandNo(uint64_t TSFlags) { + switch (TSFlags & X86II::FormMask) { + case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); + default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); + case X86II::Pseudo: + case X86II::RawFrm: + case X86II::AddRegFrm: + case X86II::MRMDestReg: + case X86II::MRMSrcReg: + case X86II::RawFrmImm8: + case X86II::RawFrmImm16: + return -1; + case X86II::MRMDestMem: + return 0; + case X86II::MRMSrcMem: { + bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; + unsigned FirstMemOp = 1; + if (HasVEX_4V) + ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). + + // FIXME: Maybe lea should have its own form? This is a horrible hack. + //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || + // Opcode == X86::LEA16r || Opcode == X86::LEA32r) + return FirstMemOp; + } + case X86II::MRM0r: case X86II::MRM1r: + case X86II::MRM2r: case X86II::MRM3r: + case X86II::MRM4r: case X86II::MRM5r: + case X86II::MRM6r: case X86II::MRM7r: + return -1; + case X86II::MRM0m: case X86II::MRM1m: + case X86II::MRM2m: case X86II::MRM3m: + case X86II::MRM4m: case X86II::MRM5m: + case X86II::MRM6m: case X86II::MRM7m: + return 0; + case X86II::MRM_C1: + case X86II::MRM_C2: + case X86II::MRM_C3: + case X86II::MRM_C4: + case X86II::MRM_C8: + case X86II::MRM_C9: + case X86II::MRM_E8: + case X86II::MRM_F0: + case X86II::MRM_F8: + case X86II::MRM_F9: + case X86II::MRM_D0: + case X86II::MRM_D1: + return -1; + } + } + + /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or + /// higher) register? e.g. r8, xmm8, xmm13, etc. + static inline bool isX86_64ExtendedReg(unsigned RegNo) { + switch (RegNo) { + default: break; + case X86::R8: case X86::R9: case X86::R10: case X86::R11: + case X86::R12: case X86::R13: case X86::R14: case X86::R15: + case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: + case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: + case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: + case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: + case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: + case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: + case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: + case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: + case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: + case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: + case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: + case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: + return true; + } + return false; + } + + static inline bool isX86_64NonExtLowByteReg(unsigned reg) { + return (reg == X86::SPL || reg == X86::BPL || + reg == X86::SIL || reg == X86::DIL); + } +} + +} // end namespace llvm; + +#endif Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Mon Jul 25 13:43:53 2011 @@ -17,6 +17,9 @@ #include namespace llvm { +class MCCodeEmitter; +class MCContext; +class MCInstrInfo; class MCRegisterInfo; class MCSubtargetInfo; class Target; @@ -63,6 +66,11 @@ StringRef FS); } +MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, + MCContext &Ctx); + + } // End llvm namespace Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Mon Jul 25 13:43:53 2011 @@ -15,6 +15,7 @@ #ifndef TARGET_X86_H #define TARGET_X86_H +#include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/Support/DataTypes.h" #include "llvm/Target/TargetMachine.h" @@ -60,10 +61,6 @@ FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, JITCodeEmitter &JCE); -MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx); - TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &); TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &); Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Mon Jul 25 13:43:53 2011 @@ -9,7 +9,7 @@ #include "llvm/MC/TargetAsmBackend.h" #include "X86.h" -#include "X86FixupKinds.h" +#include "MCTargetDesc/X86FixupKinds.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCELFObjectWriter.h" Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Jul 25 13:43:53 2011 @@ -167,7 +167,7 @@ const MachineOperand& MO = MI.getOperand(i); if (MO.isReg()) { unsigned Reg = MO.getReg(); - if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) + if (X86II::isX86_64NonExtLowByteReg(Reg)) REX |= 0x40; } } Removed: llvm/trunk/lib/Target/X86/X86FixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupKinds.h?rev=135929&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86FixupKinds.h (original) +++ llvm/trunk/lib/Target/X86/X86FixupKinds.h (removed) @@ -1,33 +0,0 @@ -//===-- X86/X86FixupKinds.h - X86 Specific Fixup Entries --------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_X86_X86FIXUPKINDS_H -#define LLVM_X86_X86FIXUPKINDS_H - -#include "llvm/MC/MCFixup.h" - -namespace llvm { -namespace X86 { -enum Fixups { - reloc_riprel_4byte = FirstTargetFixupKind, // 32-bit rip-relative - reloc_riprel_4byte_movq_load, // 32-bit rip-relative in movq - reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4 - // this will be sign extended at - // runtime. - reloc_global_offset_table, // 32-bit, relative to the start - // of the instruction. Used only - // for _GLOBAL_OFFSET_TABLE_. - // Marker - LastTargetFixupKind, - NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind -}; -} -} - -#endif Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jul 25 13:43:53 2011 @@ -3013,31 +3013,6 @@ RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); } - -/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) -/// register? e.g. r8, xmm8, xmm13, etc. -bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { - switch (RegNo) { - default: break; - case X86::R8: case X86::R9: case X86::R10: case X86::R11: - case X86::R12: case X86::R13: case X86::R14: case X86::R15: - case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: - case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: - case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: - case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: - case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: - case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: - case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: - case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: - case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: - case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: - case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: - case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: - return true; - } - return false; -} - /// getGlobalBaseReg - Return a virtual register initialized with the /// the global base register value. Output instructions required to /// initialize the register in the function entry block, if necessary. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Jul 25 13:43:53 2011 @@ -27,24 +27,6 @@ class X86TargetMachine; namespace X86 { - // Enums for memory operand decoding. Each memory operand is represented with - // a 5 operand sequence in the form: - // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] - // These enums help decode this. - enum { - AddrBaseReg = 0, - AddrScaleAmt = 1, - AddrIndexReg = 2, - AddrDisp = 3, - - /// AddrSegmentReg - The operand # of the segment in the memory operand. - AddrSegmentReg = 4, - - /// AddrNumOperands - Total number of operands in a memory reference. - AddrNumOperands = 5 - }; - - // X86 specific condition code. These correspond to X86_*_COND in // X86InstrInfo.td. They must be kept in synch. enum CondCode { @@ -82,133 +64,8 @@ /// GetOppositeBranchCondition - Return the inverse of the specified cond, /// e.g. turning COND_E to COND_NE. CondCode GetOppositeBranchCondition(X86::CondCode CC); +} // end namespace X86; -} - -/// X86II - This namespace holds all of the target specific flags that -/// instruction info tracks. -/// -namespace X86II { - /// Target Operand Flag enum. - enum TOF { - //===------------------------------------------------------------------===// - // X86 Specific MachineOperand flags. - - MO_NO_FLAG, - - /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a - /// relocation of: - /// SYMBOL_LABEL + [. - PICBASELABEL] - MO_GOT_ABSOLUTE_ADDRESS, - - /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the - /// immediate should get the value of the symbol minus the PIC base label: - /// SYMBOL_LABEL - PICBASELABEL - MO_PIC_BASE_OFFSET, - - /// MO_GOT - On a symbol operand this indicates that the immediate is the - /// offset to the GOT entry for the symbol name from the base of the GOT. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOT - MO_GOT, - - /// MO_GOTOFF - On a symbol operand this indicates that the immediate is - /// the offset to the location of the symbol name from the base of the GOT. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOTOFF - MO_GOTOFF, - - /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is - /// offset to the GOT entry for the symbol name from the current code - /// location. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOTPCREL - MO_GOTPCREL, - - /// MO_PLT - On a symbol operand this indicates that the immediate is - /// offset to the PLT entry of symbol name from the current code location. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @PLT - MO_PLT, - - /// MO_TLSGD - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @TLSGD - MO_TLSGD, - - /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @GOTTPOFF - MO_GOTTPOFF, - - /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @INDNTPOFF - MO_INDNTPOFF, - - /// MO_TPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @TPOFF - MO_TPOFF, - - /// MO_NTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @NTPOFF - MO_NTPOFF, - - /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "__imp_FOO" symbol. This is used for - /// dllimport linkage on windows. - MO_DLLIMPORT, - - /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "FOO$stub" symbol. This is used for calls - /// and jumps to external functions on Tiger and earlier. - MO_DARWIN_STUB, - - /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a - /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. - MO_DARWIN_NONLAZY, - - /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates - /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is - /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. - MO_DARWIN_NONLAZY_PIC_BASE, - - /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this - /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", - /// which is a PIC-base-relative reference to a hidden dyld lazy pointer - /// stub. - MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, - - /// MO_TLVP - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// This is the TLS offset for the Darwin TLS mechanism. - MO_TLVP, - - /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate - /// is some TLS offset from the picbase. - /// - /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. - MO_TLVP_PIC_BASE - }; -} /// isGlobalStubReference - Return true if the specified TargetFlag operand is /// a reference to a stub for a global, not the global itself. @@ -243,353 +100,6 @@ } } -/// X86II - This namespace holds all of the target specific flags that -/// instruction info tracks. -/// -namespace X86II { - enum { - //===------------------------------------------------------------------===// - // Instruction encodings. These are the standard/most common forms for X86 - // instructions. - // - - // PseudoFrm - This represents an instruction that is a pseudo instruction - // or one that has not been implemented yet. It is illegal to code generate - // it, but tolerated for intermediate implementation stages. - Pseudo = 0, - - /// Raw - This form is for instructions that don't have any operands, so - /// they are just a fixed opcode value, like 'leave'. - RawFrm = 1, - - /// AddRegFrm - This form is used for instructions like 'push r32' that have - /// their one register operand added to their opcode. - AddRegFrm = 2, - - /// MRMDestReg - This form is used for instructions that use the Mod/RM byte - /// to specify a destination, which in this case is a register. - /// - MRMDestReg = 3, - - /// MRMDestMem - This form is used for instructions that use the Mod/RM byte - /// to specify a destination, which in this case is memory. - /// - MRMDestMem = 4, - - /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte - /// to specify a source, which in this case is a register. - /// - MRMSrcReg = 5, - - /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte - /// to specify a source, which in this case is memory. - /// - MRMSrcMem = 6, - - /// MRM[0-7][rm] - These forms are used to represent instructions that use - /// a Mod/RM byte, and use the middle field to hold extended opcode - /// information. In the intel manual these are represented as /0, /1, ... - /// - - // First, instructions that operate on a register r/m operand... - MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 - MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 - - // Next, instructions that operate on a memory r/m operand... - MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 - MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 - - // MRMInitReg - This form is used for instructions whose source and - // destinations are the same register. - MRMInitReg = 32, - - //// MRM_C1 - A mod/rm byte of exactly 0xC1. - MRM_C1 = 33, - MRM_C2 = 34, - MRM_C3 = 35, - MRM_C4 = 36, - MRM_C8 = 37, - MRM_C9 = 38, - MRM_E8 = 39, - MRM_F0 = 40, - MRM_F8 = 41, - MRM_F9 = 42, - MRM_D0 = 45, - MRM_D1 = 46, - - /// RawFrmImm8 - This is used for the ENTER instruction, which has two - /// immediates, the first of which is a 16-bit immediate (specified by - /// the imm encoding) and the second is a 8-bit fixed value. - RawFrmImm8 = 43, - - /// RawFrmImm16 - This is used for CALL FAR instructions, which have two - /// immediates, the first of which is a 16 or 32-bit immediate (specified by - /// the imm encoding) and the second is a 16-bit fixed value. In the AMD - /// manual, this operand is described as pntr16:32 and pntr16:16 - RawFrmImm16 = 44, - - FormMask = 63, - - //===------------------------------------------------------------------===// - // Actual flags... - - // OpSize - Set if this instruction requires an operand size prefix (0x66), - // which most often indicates that the instruction operates on 16 bit data - // instead of 32 bit data. - OpSize = 1 << 6, - - // AsSize - Set if this instruction requires an operand size prefix (0x67), - // which most often indicates that the instruction address 16 bit address - // instead of 32 bit address (or 32 bit address in 64 bit mode). - AdSize = 1 << 7, - - //===------------------------------------------------------------------===// - // Op0Mask - There are several prefix bytes that are used to form two byte - // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is - // used to obtain the setting of this field. If no bits in this field is - // set, there is no prefix byte for obtaining a multibyte opcode. - // - Op0Shift = 8, - Op0Mask = 0x1F << Op0Shift, - - // TB - TwoByte - Set if this instruction has a two byte opcode, which - // starts with a 0x0F byte before the real opcode. - TB = 1 << Op0Shift, - - // REP - The 0xF3 prefix byte indicating repetition of the following - // instruction. - REP = 2 << Op0Shift, - - // D8-DF - These escape opcodes are used by the floating point unit. These - // values must remain sequential. - D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, - DA = 5 << Op0Shift, DB = 6 << Op0Shift, - DC = 7 << Op0Shift, DD = 8 << Op0Shift, - DE = 9 << Op0Shift, DF = 10 << Op0Shift, - - // XS, XD - These prefix codes are for single and double precision scalar - // floating point operations performed in the SSE registers. - XD = 11 << Op0Shift, XS = 12 << Op0Shift, - - // T8, TA, A6, A7 - Prefix after the 0x0F prefix. - T8 = 13 << Op0Shift, TA = 14 << Op0Shift, - A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, - - // TF - Prefix before and after 0x0F - TF = 17 << Op0Shift, - - //===------------------------------------------------------------------===// - // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. - // They are used to specify GPRs and SSE registers, 64-bit operand size, - // etc. We only cares about REX.W and REX.R bits and only the former is - // statically determined. - // - REXShift = Op0Shift + 5, - REX_W = 1 << REXShift, - - //===------------------------------------------------------------------===// - // This three-bit field describes the size of an immediate operand. Zero is - // unused so that we can tell if we forgot to set a value. - ImmShift = REXShift + 1, - ImmMask = 7 << ImmShift, - Imm8 = 1 << ImmShift, - Imm8PCRel = 2 << ImmShift, - Imm16 = 3 << ImmShift, - Imm16PCRel = 4 << ImmShift, - Imm32 = 5 << ImmShift, - Imm32PCRel = 6 << ImmShift, - Imm64 = 7 << ImmShift, - - //===------------------------------------------------------------------===// - // FP Instruction Classification... Zero is non-fp instruction. - - // FPTypeMask - Mask for all of the FP types... - FPTypeShift = ImmShift + 3, - FPTypeMask = 7 << FPTypeShift, - - // NotFP - The default, set for instructions that do not use FP registers. - NotFP = 0 << FPTypeShift, - - // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 - ZeroArgFP = 1 << FPTypeShift, - - // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst - OneArgFP = 2 << FPTypeShift, - - // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a - // result back to ST(0). For example, fcos, fsqrt, etc. - // - OneArgFPRW = 3 << FPTypeShift, - - // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an - // explicit argument, storing the result to either ST(0) or the implicit - // argument. For example: fadd, fsub, fmul, etc... - TwoArgFP = 4 << FPTypeShift, - - // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an - // explicit argument, but have no destination. Example: fucom, fucomi, ... - CompareFP = 5 << FPTypeShift, - - // CondMovFP - "2 operand" floating point conditional move instructions. - CondMovFP = 6 << FPTypeShift, - - // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. - SpecialFP = 7 << FPTypeShift, - - // Lock prefix - LOCKShift = FPTypeShift + 3, - LOCK = 1 << LOCKShift, - - // Segment override prefixes. Currently we just need ability to address - // stuff in gs and fs segments. - SegOvrShift = LOCKShift + 1, - SegOvrMask = 3 << SegOvrShift, - FS = 1 << SegOvrShift, - GS = 2 << SegOvrShift, - - // Execution domain for SSE instructions in bits 23, 24. - // 0 in bits 23-24 means normal, non-SSE instruction. - SSEDomainShift = SegOvrShift + 2, - - OpcodeShift = SSEDomainShift + 2, - - //===------------------------------------------------------------------===// - /// VEX - The opcode prefix used by AVX instructions - VEXShift = OpcodeShift + 8, - VEX = 1U << 0, - - /// VEX_W - Has a opcode specific functionality, but is used in the same - /// way as REX_W is for regular SSE instructions. - VEX_W = 1U << 1, - - /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 - /// address instructions in SSE are represented as 3 address ones in AVX - /// and the additional register is encoded in VEX_VVVV prefix. - VEX_4V = 1U << 2, - - /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, - /// must be encoded in the i8 immediate field. This usually happens in - /// instructions with 4 operands. - VEX_I8IMM = 1U << 3, - - /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current - /// instruction uses 256-bit wide registers. This is usually auto detected - /// if a VR256 register is used, but some AVX instructions also have this - /// field marked when using a f256 memory references. - VEX_L = 1U << 4, - - /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the - /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents - /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction - /// storing a classifier in the imm8 field. To simplify our implementation, - /// we handle this by storeing the classifier in the opcode field and using - /// this flag to indicate that the encoder should do the wacky 3DNow! thing. - Has3DNow0F0FOpcode = 1U << 5 - }; - - // getBaseOpcodeFor - This function returns the "base" X86 opcode for the - // specified machine instruction. - // - static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { - return TSFlags >> X86II::OpcodeShift; - } - - static inline bool hasImm(uint64_t TSFlags) { - return (TSFlags & X86II::ImmMask) != 0; - } - - /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field - /// of the specified instruction. - static inline unsigned getSizeOfImm(uint64_t TSFlags) { - switch (TSFlags & X86II::ImmMask) { - default: assert(0 && "Unknown immediate size"); - case X86II::Imm8: - case X86II::Imm8PCRel: return 1; - case X86II::Imm16: - case X86II::Imm16PCRel: return 2; - case X86II::Imm32: - case X86II::Imm32PCRel: return 4; - case X86II::Imm64: return 8; - } - } - - /// isImmPCRel - Return true if the immediate of the specified instruction's - /// TSFlags indicates that it is pc relative. - static inline unsigned isImmPCRel(uint64_t TSFlags) { - switch (TSFlags & X86II::ImmMask) { - default: assert(0 && "Unknown immediate size"); - case X86II::Imm8PCRel: - case X86II::Imm16PCRel: - case X86II::Imm32PCRel: - return true; - case X86II::Imm8: - case X86II::Imm16: - case X86II::Imm32: - case X86II::Imm64: - return false; - } - } - - /// getMemoryOperandNo - The function returns the MCInst operand # for the - /// first field of the memory operand. If the instruction doesn't have a - /// memory operand, this returns -1. - /// - /// Note that this ignores tied operands. If there is a tied register which - /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only - /// counted as one operand. - /// - static inline int getMemoryOperandNo(uint64_t TSFlags) { - switch (TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); - default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); - case X86II::Pseudo: - case X86II::RawFrm: - case X86II::AddRegFrm: - case X86II::MRMDestReg: - case X86II::MRMSrcReg: - case X86II::RawFrmImm8: - case X86II::RawFrmImm16: - return -1; - case X86II::MRMDestMem: - return 0; - case X86II::MRMSrcMem: { - bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; - unsigned FirstMemOp = 1; - if (HasVEX_4V) - ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). - - // FIXME: Maybe lea should have its own form? This is a horrible hack. - //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || - // Opcode == X86::LEA16r || Opcode == X86::LEA32r) - return FirstMemOp; - } - case X86II::MRM0r: case X86II::MRM1r: - case X86II::MRM2r: case X86II::MRM3r: - case X86II::MRM4r: case X86II::MRM5r: - case X86II::MRM6r: case X86II::MRM7r: - return -1; - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - return 0; - case X86II::MRM_C1: - case X86II::MRM_C2: - case X86II::MRM_C3: - case X86II::MRM_C4: - case X86II::MRM_C8: - case X86II::MRM_C9: - case X86II::MRM_E8: - case X86II::MRM_F0: - case X86II::MRM_F8: - case X86II::MRM_F9: - case X86II::MRM_D0: - case X86II::MRM_D1: - return -1; - } - } -} - inline static bool isScale(const MachineOperand &MO) { return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || @@ -829,20 +339,11 @@ /// instruction that defines the specified register class. bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; - static bool isX86_64NonExtLowByteReg(unsigned reg) { - return (reg == X86::SPL || reg == X86::BPL || - reg == X86::SIL || reg == X86::DIL); - } - static bool isX86_64ExtendedReg(const MachineOperand &MO) { if (!MO.isReg()) return false; - return isX86_64ExtendedReg(MO.getReg()); + return X86II::isX86_64ExtendedReg(MO.getReg()); } - /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or - /// higher) register? e.g. r8, xmm8, xmm13, etc. - static bool isX86_64ExtendedReg(unsigned RegNo); - /// getGlobalBaseReg - Return a virtual register initialized with the /// the global base register value. Output instructions required to /// initialize the register in the function entry block, if necessary. Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Mon Jul 25 13:43:53 2011 @@ -12,12 +12,14 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mccodeemitter" -#include "X86.h" -#include "X86InstrInfo.h" -#include "X86FixupKinds.h" +#include "MCTargetDesc/X86MCTargetDesc.h" +#include "MCTargetDesc/X86BaseInfo.h" +#include "MCTargetDesc/X86FixupKinds.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Support/raw_ostream.h" @@ -153,6 +155,11 @@ return MCFixup::getKindForSize(Size, isPCRel); } +namespace llvm { + // FIXME: TableGen this? + extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc. +} + /// Is32BitMemOperand - Return true if the specified instruction with a memory /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit /// memory operand. Op specifies the operand # of the memoperand. @@ -160,8 +167,10 @@ const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); - if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) || - (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg()))) + if ((BaseReg.getReg() != 0 && + X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || + (IndexReg.getReg() != 0 && + X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) return true; return false; } @@ -506,7 +515,7 @@ case X86II::MRMSrcMem: case X86II::MRMSrcReg: if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) VEX_R = 0x0; CurOp++; @@ -527,11 +536,11 @@ for (; CurOp != NumOps; ++CurOp) { const MCOperand &MO = MI.getOperand(CurOp); - if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) VEX_B = 0x0; if (!VEX_B && MO.isReg() && ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) && - X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + X86II::isX86_64ExtendedReg(MO.getReg())) VEX_X = 0x0; } break; @@ -540,7 +549,7 @@ break; if (MI.getOperand(CurOp).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) VEX_B = 0; if (HasVEX_4V) @@ -550,7 +559,7 @@ for (; CurOp != NumOps; ++CurOp) { const MCOperand &MO = MI.getOperand(CurOp); if (MO.isReg() && !HasVEX_4V && - X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + X86II::isX86_64ExtendedReg(MO.getReg())) VEX_R = 0x0; } break; @@ -606,7 +615,7 @@ const MCOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); - if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue; + if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything // that returns non-zero. REX |= 0x40; // REX fixed encoding prefix @@ -617,25 +626,25 @@ case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!"); case X86II::MRMSrcReg: if (MI.getOperand(0).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) REX |= 1 << 2; // set REX.R i = isTwoAddr ? 2 : 1; for (; i != NumOps; ++i) { const MCOperand &MO = MI.getOperand(i); - if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) REX |= 1 << 0; // set REX.B } break; case X86II::MRMSrcMem: { if (MI.getOperand(0).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) REX |= 1 << 2; // set REX.R unsigned Bit = 0; i = isTwoAddr ? 2 : 1; for (; i != NumOps; ++i) { const MCOperand &MO = MI.getOperand(i); if (MO.isReg()) { - if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + if (X86II::isX86_64ExtendedReg(MO.getReg())) REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) Bit++; } @@ -650,13 +659,13 @@ unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); i = isTwoAddr ? 1 : 0; if (NumOps > e && MI.getOperand(e).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) REX |= 1 << 2; // set REX.R unsigned Bit = 0; for (; i != e; ++i) { const MCOperand &MO = MI.getOperand(i); if (MO.isReg()) { - if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + if (X86II::isX86_64ExtendedReg(MO.getReg())) REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) Bit++; } @@ -665,12 +674,12 @@ } default: if (MI.getOperand(0).isReg() && - X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg())) + X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) REX |= 1 << 0; // set REX.B i = isTwoAddr ? 2 : 1; for (unsigned e = NumOps; i != e; ++i) { const MCOperand &MO = MI.getOperand(i); - if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) + if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) REX |= 1 << 2; // set REX.R } break; @@ -1009,7 +1018,7 @@ if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { const MCOperand &MO = MI.getOperand(CurOp++); bool IsExtReg = - X86InstrInfo::isX86_64ExtendedReg(MO.getReg()); + X86II::isX86_64ExtendedReg(MO.getReg()); unsigned RegNum = (IsExtReg ? (1 << 7) : 0); RegNum |= GetX86RegNum(MO) << 4; EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS, Modified: llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp?rev=135930&r1=135929&r2=135930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp Mon Jul 25 13:43:53 2011 @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "X86.h" -#include "X86FixupKinds.h" +#include "MCTargetDesc/X86FixupKinds.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmLayout.h" From jstaszak at apple.com Mon Jul 25 14:25:40 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 25 Jul 2011 19:25:40 -0000 Subject: [llvm-commits] [llvm] r135937 - in /llvm/trunk: include/llvm/ include/llvm/Analysis/ include/llvm/CodeGen/ lib/Analysis/ lib/CodeGen/ Message-ID: <20110725192540.B84F42A6C12C@llvm.org> Author: kuba Date: Mon Jul 25 14:25:40 2011 New Revision: 135937 URL: http://llvm.org/viewvc/llvm-project?rev=135937&view=rev Log: Rename BlockFrequency to BlockFrequencyInfo and MachineBlockFrequency to MachineBlockFrequencyInfo. Added: llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h - copied, changed from r135924, llvm/trunk/include/llvm/Analysis/BlockFrequency.h llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h - copied, changed from r135924, llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp - copied, changed from r135924, llvm/trunk/lib/Analysis/BlockFrequency.cpp llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp - copied, changed from r135924, llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp Removed: llvm/trunk/include/llvm/Analysis/BlockFrequency.h llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h llvm/trunk/lib/Analysis/BlockFrequency.cpp llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/lib/Analysis/Analysis.cpp llvm/trunk/lib/Analysis/CMakeLists.txt llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/CodeGen/CodeGen.cpp Removed: llvm/trunk/include/llvm/Analysis/BlockFrequency.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequency.h?rev=135936&view=auto ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequency.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequency.h (removed) @@ -1,53 +0,0 @@ -//========-------- BlockFrequency.h - Block Frequency Analysis -------========// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Loops should be simplified before this analysis. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ANALYSIS_BLOCKFREQUENCY_H -#define LLVM_ANALYSIS_BLOCKFREQUENCY_H - -#include "llvm/Pass.h" -#include - -namespace llvm { - -class BranchProbabilityInfo; -template -class BlockFrequencyImpl; - -/// BlockFrequency pass uses BlockFrequencyImpl implementation to estimate -/// IR basic block frequencies. -class BlockFrequency : public FunctionPass { - - BlockFrequencyImpl *BFI; - -public: - static char ID; - - BlockFrequency(); - - ~BlockFrequency(); - - void getAnalysisUsage(AnalysisUsage &AU) const; - - bool runOnFunction(Function &F); - - /// getblockFreq - Return block frequency. Return 0 if we don't have the - /// information. Please note that initial frequency is equal to 1024. It means - /// that we should not rely on the value itself, but only on the comparison to - /// the other block frequencies. We do this to avoid using of floating points. - /// - uint32_t getBlockFreq(BasicBlock *BB); -}; - -} - -#endif Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Mon Jul 25 14:25:40 2011 @@ -29,8 +29,8 @@ namespace llvm { -class BlockFrequency; -class MachineBlockFrequency; +class BlockFrequencyInfo; +class MachineBlockFrequencyInfo; /// BlockFrequencyImpl implements block frequency algorithm for IR and /// Machine Instructions. Algorithm starts with value 1024 (START_FREQ) @@ -263,8 +263,8 @@ } } - friend class BlockFrequency; - friend class MachineBlockFrequency; + friend class BlockFrequencyInfo; + friend class MachineBlockFrequencyInfo; void doFunction(FunctionT *fn, BlockProbInfoT *bpi) { Fn = fn; Copied: llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h (from r135924, llvm/trunk/include/llvm/Analysis/BlockFrequency.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h?p2=llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h&p1=llvm/trunk/include/llvm/Analysis/BlockFrequency.h&r1=135924&r2=135937&rev=135937&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequency.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h Mon Jul 25 14:25:40 2011 @@ -1,4 +1,4 @@ -//========-------- BlockFrequency.h - Block Frequency Analysis -------========// +//========-------- BlockFrequencyInfo.h - Block Frequency Analysis -------========// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_ANALYSIS_BLOCKFREQUENCY_H -#define LLVM_ANALYSIS_BLOCKFREQUENCY_H +#ifndef LLVM_ANALYSIS_BLOCKFREQUENCYINFO_H +#define LLVM_ANALYSIS_BLOCKFREQUENCYINFO_H #include "llvm/Pass.h" #include @@ -23,18 +23,18 @@ template class BlockFrequencyImpl; -/// BlockFrequency pass uses BlockFrequencyImpl implementation to estimate +/// BlockFrequencyInfo pass uses BlockFrequencyImpl implementation to estimate /// IR basic block frequencies. -class BlockFrequency : public FunctionPass { +class BlockFrequencyInfo : public FunctionPass { BlockFrequencyImpl *BFI; public: static char ID; - BlockFrequency(); + BlockFrequencyInfo(); - ~BlockFrequency(); + ~BlockFrequencyInfo(); void getAnalysisUsage(AnalysisUsage &AU) const; Removed: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h?rev=135936&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h (removed) @@ -1,53 +0,0 @@ -//====----- MachineBlockFrequency.h - MachineBlock Frequency Analysis ----====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Loops should be simplified before this analysis. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H -#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H - -#include "llvm/CodeGen/MachineFunctionPass.h" -#include - -namespace llvm { - -class MachineBranchProbabilityInfo; -template -class BlockFrequencyImpl; - -/// MachineBlockFrequency pass uses BlockFrequencyImpl implementation to estimate -/// machine basic block frequencies. -class MachineBlockFrequency : public MachineFunctionPass { - - BlockFrequencyImpl *MBFI; - -public: - static char ID; - - MachineBlockFrequency(); - - ~MachineBlockFrequency(); - - void getAnalysisUsage(AnalysisUsage &AU) const; - - bool runOnMachineFunction(MachineFunction &F); - - /// getblockFreq - Return block frequency. Return 0 if we don't have the - /// information. Please note that initial frequency is equal to 1024. It means - /// that we should not rely on the value itself, but only on the comparison to - /// the other block frequencies. We do this to avoid using of floating points. - /// - uint32_t getBlockFreq(MachineBasicBlock *MBB); -}; - -} - -#endif Copied: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (from r135924, llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?p2=llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h&p1=llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h&r1=135924&r2=135937&rev=135937&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequency.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Mon Jul 25 14:25:40 2011 @@ -1,4 +1,4 @@ -//====----- MachineBlockFrequency.h - MachineBlock Frequency Analysis ----====// +//====----- MachineBlockFrequencyInfo.h - MachineBlock Frequency Analysis ----====// // // The LLVM Compiler Infrastructure // @@ -23,18 +23,18 @@ template class BlockFrequencyImpl; -/// MachineBlockFrequency pass uses BlockFrequencyImpl implementation to estimate +/// MachineBlockFrequencyInfo pass uses BlockFrequencyImpl implementation to estimate /// machine basic block frequencies. -class MachineBlockFrequency : public MachineFunctionPass { +class MachineBlockFrequencyInfo : public MachineFunctionPass { BlockFrequencyImpl *MBFI; public: static char ID; - MachineBlockFrequency(); + MachineBlockFrequencyInfo(); - ~MachineBlockFrequency(); + ~MachineBlockFrequencyInfo(); void getAnalysisUsage(AnalysisUsage &AU) const; Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Mon Jul 25 14:25:40 2011 @@ -65,7 +65,7 @@ void initializeBasicAliasAnalysisPass(PassRegistry&); void initializeBasicCallGraphPass(PassRegistry&); void initializeBlockExtractorPassPass(PassRegistry&); -void initializeBlockFrequencyPass(PassRegistry&); +void initializeBlockFrequencyInfoPass(PassRegistry&); void initializeBlockPlacementPass(PassRegistry&); void initializeBranchProbabilityInfoPass(PassRegistry&); void initializeBreakCriticalEdgesPass(PassRegistry&); @@ -145,7 +145,7 @@ void initializeLowerInvokePass(PassRegistry&); void initializeLowerSetJmpPass(PassRegistry&); void initializeLowerSwitchPass(PassRegistry&); -void initializeMachineBlockFrequencyPass(PassRegistry&); +void initializeMachineBlockFrequencyInfoPass(PassRegistry&); void initializeMachineBranchProbabilityInfoPass(PassRegistry&); void initializeMachineCSEPass(PassRegistry&); void initializeMachineDominatorTreePass(PassRegistry&); Modified: llvm/trunk/lib/Analysis/Analysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Analysis.cpp (original) +++ llvm/trunk/lib/Analysis/Analysis.cpp Mon Jul 25 14:25:40 2011 @@ -23,7 +23,7 @@ initializeAliasSetPrinterPass(Registry); initializeNoAAPass(Registry); initializeBasicAliasAnalysisPass(Registry); - initializeBlockFrequencyPass(Registry); + initializeBlockFrequencyInfoPass(Registry); initializeBranchProbabilityInfoPass(Registry); initializeCFGViewerPass(Registry); initializeCFGPrinterPass(Registry); Removed: llvm/trunk/lib/Analysis/BlockFrequency.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequency.cpp?rev=135936&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/BlockFrequency.cpp (original) +++ llvm/trunk/lib/Analysis/BlockFrequency.cpp (removed) @@ -1,59 +0,0 @@ -//=======-------- BlockFrequency.cpp - Block Frequency Analysis -------=======// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Loops should be simplified before this analysis. -// -//===----------------------------------------------------------------------===// - -#include "llvm/InitializePasses.h" -#include "llvm/Analysis/BlockFrequencyImpl.h" -#include "llvm/Analysis/BlockFrequency.h" -#include "llvm/Analysis/LoopInfo.h" -#include "llvm/Analysis/Passes.h" -#include "llvm/Analysis/BranchProbabilityInfo.h" - -using namespace llvm; - -INITIALIZE_PASS_BEGIN(BlockFrequency, "block-freq", "Block Frequency Analysis", - true, true) -INITIALIZE_PASS_DEPENDENCY(BranchProbabilityInfo) -INITIALIZE_PASS_END(BlockFrequency, "block-freq", "Block Frequency Analysis", - true, true) - -char BlockFrequency::ID = 0; - - -BlockFrequency::BlockFrequency() : FunctionPass(ID) { - initializeBlockFrequencyPass(*PassRegistry::getPassRegistry()); - BFI = new BlockFrequencyImpl(); -} - -BlockFrequency::~BlockFrequency() { - delete BFI; -} - -void BlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.setPreservesAll(); -} - -bool BlockFrequency::runOnFunction(Function &F) { - BranchProbabilityInfo &BPI = getAnalysis(); - BFI->doFunction(&F, &BPI); - return false; -} - -/// getblockFreq - Return block frequency. Return 0 if we don't have the -/// information. Please note that initial frequency is equal to 1024. It means -/// that we should not rely on the value itself, but only on the comparison to -/// the other block frequencies. We do this to avoid using of floating points. -/// -uint32_t BlockFrequency::getBlockFreq(BasicBlock *BB) { - return BFI->getBlockFreq(BB); -} Copied: llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp (from r135924, llvm/trunk/lib/Analysis/BlockFrequency.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp?p2=llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp&p1=llvm/trunk/lib/Analysis/BlockFrequency.cpp&r1=135924&r2=135937&rev=135937&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BlockFrequency.cpp (original) +++ llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp Mon Jul 25 14:25:40 2011 @@ -1,4 +1,4 @@ -//=======-------- BlockFrequency.cpp - Block Frequency Analysis -------=======// +//=======-------- BlockFrequencyInfo.cpp - Block Frequency Analysis -------=======// // // The LLVM Compiler Infrastructure // @@ -13,37 +13,37 @@ #include "llvm/InitializePasses.h" #include "llvm/Analysis/BlockFrequencyImpl.h" -#include "llvm/Analysis/BlockFrequency.h" +#include "llvm/Analysis/BlockFrequencyInfo.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/BranchProbabilityInfo.h" using namespace llvm; -INITIALIZE_PASS_BEGIN(BlockFrequency, "block-freq", "Block Frequency Analysis", +INITIALIZE_PASS_BEGIN(BlockFrequencyInfo, "block-freq", "Block Frequency Analysis", true, true) INITIALIZE_PASS_DEPENDENCY(BranchProbabilityInfo) -INITIALIZE_PASS_END(BlockFrequency, "block-freq", "Block Frequency Analysis", +INITIALIZE_PASS_END(BlockFrequencyInfo, "block-freq", "Block Frequency Analysis", true, true) -char BlockFrequency::ID = 0; +char BlockFrequencyInfo::ID = 0; -BlockFrequency::BlockFrequency() : FunctionPass(ID) { - initializeBlockFrequencyPass(*PassRegistry::getPassRegistry()); +BlockFrequencyInfo::BlockFrequencyInfo() : FunctionPass(ID) { + initializeBlockFrequencyInfoPass(*PassRegistry::getPassRegistry()); BFI = new BlockFrequencyImpl(); } -BlockFrequency::~BlockFrequency() { +BlockFrequencyInfo::~BlockFrequencyInfo() { delete BFI; } -void BlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const { +void BlockFrequencyInfo::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesAll(); } -bool BlockFrequency::runOnFunction(Function &F) { +bool BlockFrequencyInfo::runOnFunction(Function &F) { BranchProbabilityInfo &BPI = getAnalysis(); BFI->doFunction(&F, &BPI); return false; @@ -54,6 +54,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -uint32_t BlockFrequency::getBlockFreq(BasicBlock *BB) { +uint32_t BlockFrequencyInfo::getBlockFreq(BasicBlock *BB) { return BFI->getBlockFreq(BB); } Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Mon Jul 25 14:25:40 2011 @@ -6,7 +6,7 @@ AliasSetTracker.cpp Analysis.cpp BasicAliasAnalysis.cpp - BlockFrequency.cpp + BlockFrequencyInfo.cpp BranchProbabilityInfo.cpp CFGPrinter.cpp CaptureTracking.cpp Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Mon Jul 25 14:25:40 2011 @@ -33,7 +33,7 @@ LocalStackSlotAllocation.cpp LowerSubregs.cpp MachineBasicBlock.cpp - MachineBlockFrequency.cpp + MachineBlockFrequencyInfo.cpp MachineBranchProbabilityInfo.cpp MachineCSE.cpp MachineDominators.cpp Modified: llvm/trunk/lib/CodeGen/CodeGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=135937&r1=135936&r2=135937&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CodeGen.cpp (original) +++ llvm/trunk/lib/CodeGen/CodeGen.cpp Mon Jul 25 14:25:40 2011 @@ -27,6 +27,7 @@ initializeLiveIntervalsPass(Registry); initializeLiveStacksPass(Registry); initializeLiveVariablesPass(Registry); + initializeMachineBlockFrequencyInfoPass(Registry); initializeMachineCSEPass(Registry); initializeMachineDominatorTreePass(Registry); initializeMachineLICMPass(Registry); Removed: llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp?rev=135936&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp (removed) @@ -1,60 +0,0 @@ -//====----- MachineBlockFrequency.cpp - Machine Block Frequency Analysis ----====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Loops should be simplified before this analysis. -// -//===----------------------------------------------------------------------===// - -#include "llvm/InitializePasses.h" -#include "llvm/Analysis/BlockFrequencyImpl.h" -#include "llvm/CodeGen/MachineBlockFrequency.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" - -using namespace llvm; - -INITIALIZE_PASS_BEGIN(MachineBlockFrequency, "machine-block-freq", - "Machine Block Frequency Analysis", true, true) -INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) -INITIALIZE_PASS_END(MachineBlockFrequency, "machine-block-freq", - "Machine Block Frequency Analysis", true, true) - -char MachineBlockFrequency::ID = 0; - - -MachineBlockFrequency::MachineBlockFrequency() : MachineFunctionPass(ID) { - initializeMachineBlockFrequencyPass(*PassRegistry::getPassRegistry()); - MBFI = new BlockFrequencyImpl(); -} - -MachineBlockFrequency::~MachineBlockFrequency() { - delete MBFI; -} - -void MachineBlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.setPreservesAll(); - MachineFunctionPass::getAnalysisUsage(AU); -} - -bool MachineBlockFrequency::runOnMachineFunction(MachineFunction &F) { - MachineBranchProbabilityInfo &MBPI = getAnalysis(); - MBFI->doFunction(&F, &MBPI); - return false; -} - -/// getblockFreq - Return block frequency. Return 0 if we don't have the -/// information. Please note that initial frequency is equal to 1024. It means -/// that we should not rely on the value itself, but only on the comparison to -/// the other block frequencies. We do this to avoid using of floating points. -/// -uint32_t MachineBlockFrequency::getBlockFreq(MachineBasicBlock *MBB) { - return MBFI->getBlockFreq(MBB); -} Copied: llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp (from r135924, llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp?p2=llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp&p1=llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp&r1=135924&r2=135937&rev=135937&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockFrequency.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp Mon Jul 25 14:25:40 2011 @@ -1,4 +1,4 @@ -//====----- MachineBlockFrequency.cpp - Machine Block Frequency Analysis ----====// +//====----- MachineBlockFrequencyInfo.cpp - Machine Block Frequency Analysis ----====// // // The LLVM Compiler Infrastructure // @@ -13,38 +13,38 @@ #include "llvm/InitializePasses.h" #include "llvm/Analysis/BlockFrequencyImpl.h" -#include "llvm/CodeGen/MachineBlockFrequency.h" +#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" using namespace llvm; -INITIALIZE_PASS_BEGIN(MachineBlockFrequency, "machine-block-freq", +INITIALIZE_PASS_BEGIN(MachineBlockFrequencyInfo, "machine-block-freq", "Machine Block Frequency Analysis", true, true) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) -INITIALIZE_PASS_END(MachineBlockFrequency, "machine-block-freq", +INITIALIZE_PASS_END(MachineBlockFrequencyInfo, "machine-block-freq", "Machine Block Frequency Analysis", true, true) -char MachineBlockFrequency::ID = 0; +char MachineBlockFrequencyInfo::ID = 0; -MachineBlockFrequency::MachineBlockFrequency() : MachineFunctionPass(ID) { - initializeMachineBlockFrequencyPass(*PassRegistry::getPassRegistry()); +MachineBlockFrequencyInfo::MachineBlockFrequencyInfo() : MachineFunctionPass(ID) { + initializeMachineBlockFrequencyInfoPass(*PassRegistry::getPassRegistry()); MBFI = new BlockFrequencyImpl(); } -MachineBlockFrequency::~MachineBlockFrequency() { +MachineBlockFrequencyInfo::~MachineBlockFrequencyInfo() { delete MBFI; } -void MachineBlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const { +void MachineBlockFrequencyInfo::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } -bool MachineBlockFrequency::runOnMachineFunction(MachineFunction &F) { +bool MachineBlockFrequencyInfo::runOnMachineFunction(MachineFunction &F) { MachineBranchProbabilityInfo &MBPI = getAnalysis(); MBFI->doFunction(&F, &MBPI); return false; @@ -55,6 +55,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -uint32_t MachineBlockFrequency::getBlockFreq(MachineBasicBlock *MBB) { +uint32_t MachineBlockFrequencyInfo::getBlockFreq(MachineBasicBlock *MBB) { return MBFI->getBlockFreq(MBB); } From evan.cheng at apple.com Mon Jul 25 14:33:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 19:33:48 -0000 Subject: [llvm-commits] [llvm] r135939 - in /llvm/trunk/lib/Target/X86: CMakeLists.txt MCTargetDesc/CMakeLists.txt MCTargetDesc/X86AsmBackend.cpp MCTargetDesc/X86MCCodeEmitter.cpp MCTargetDesc/X86MCTargetDesc.cpp MCTargetDesc/X86MCTargetDesc.h MCTargetDesc/X86MachObjectWriter.cpp X86.h X86AsmBackend.cpp X86MCCodeEmitter.cpp X86MachObjectWriter.cpp X86TargetMachine.cpp Message-ID: <20110725193349.1900E2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 14:33:48 2011 New Revision: 135939 URL: http://llvm.org/viewvc/llvm-project?rev=135939&view=rev Log: More refactoring. Added: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp - copied, changed from r135930, llvm/trunk/lib/Target/X86/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp - copied unchanged from r135930, llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp - copied, changed from r135930, llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp Removed: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Jul 25 14:33:48 2011 @@ -14,7 +14,6 @@ set(sources SSEDomainFix.cpp - X86AsmBackend.cpp X86AsmPrinter.cpp X86COFFMachineModuleInfo.cpp X86CodeEmitter.cpp @@ -26,8 +25,6 @@ X86ISelLowering.cpp X86InstrInfo.cpp X86JITInfo.cpp - X86MachObjectWriter.cpp - X86MCCodeEmitter.cpp X86MCInstLower.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Mon Jul 25 14:33:48 2011 @@ -1,6 +1,9 @@ add_llvm_library(LLVMX86Desc + X86AsmBackend.cpp X86MCTargetDesc.cpp X86MCAsmInfo.cpp + X86MCCodeEmitter.cpp + X86MachObjectWriter.cpp ) # Hack: we need to include 'main' target directory to grab private headers Copied: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (from r135930, llvm/trunk/lib/Target/X86/X86AsmBackend.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?p2=llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp&p1=llvm/trunk/lib/Target/X86/X86AsmBackend.cpp&r1=135930&r2=135939&rev=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon Jul 25 14:33:48 2011 @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/TargetAsmBackend.h" -#include "X86.h" +#include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86FixupKinds.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAssembler.h" Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Jul 25 14:33:48 2011 @@ -16,6 +16,7 @@ #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/Triple.h" @@ -363,6 +364,23 @@ return X; } +static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, + MCContext &Ctx, TargetAsmBackend &TAB, + raw_ostream &_OS, + MCCodeEmitter *_Emitter, + bool RelaxAll, + bool NoExecStack) { + Triple TheTriple(TT); + + if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) + return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll); + + if (TheTriple.isOSWindows()) + return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll); + + return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); +} + // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { // Register the MC asm info. @@ -386,4 +404,22 @@ X86_MC::createX86MCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, X86_MC::createX86MCSubtargetInfo); + + // Register the code emitter. + TargetRegistry::RegisterCodeEmitter(TheX86_32Target, + createX86MCCodeEmitter); + TargetRegistry::RegisterCodeEmitter(TheX86_64Target, + createX86MCCodeEmitter); + + // Register the asm backend. + TargetRegistry::RegisterAsmBackend(TheX86_32Target, + createX86_32AsmBackend); + TargetRegistry::RegisterAsmBackend(TheX86_64Target, + createX86_64AsmBackend); + + // Register the object streamer. + TargetRegistry::RegisterObjectStreamer(TheX86_32Target, + createMCStreamer); + TargetRegistry::RegisterObjectStreamer(TheX86_64Target, + createMCStreamer); } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Mon Jul 25 14:33:48 2011 @@ -20,10 +20,13 @@ class MCCodeEmitter; class MCContext; class MCInstrInfo; +class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; +class TargetAsmBackend; class StringRef; +class raw_ostream; extern Target TheX86_32Target, TheX86_64Target; @@ -70,6 +73,14 @@ const MCSubtargetInfo &STI, MCContext &Ctx); +TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &); +TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &); + +/// createX86MachObjectWriter - Construct an X86 Mach-O object writer. +MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint32_t CPUType, + uint32_t CPUSubtype); } // End llvm namespace Copied: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp (from r135930, llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp?p2=llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp&p1=llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp&r1=135930&r2=135939&rev=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp Mon Jul 25 14:33:48 2011 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// -#include "X86.h" #include "MCTargetDesc/X86FixupKinds.h" -#include "llvm/ADT/Twine.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCMachObjectWriter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCValue.h" +#include "llvm/ADT/Twine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Object/MachOFormat.h" Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Mon Jul 25 14:33:48 2011 @@ -61,9 +61,6 @@ FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, JITCodeEmitter &JCE); -TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &); -TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &); - /// createX86EmitCodeToMemory - Returns a pass that converts a register /// allocated function into raw machine code in a dynamically /// allocated chunk of memory. @@ -76,13 +73,6 @@ /// FunctionPass *createX86MaxStackAlignmentHeuristicPass(); - -/// createX86MachObjectWriter - Construct an X86 Mach-O object writer. -MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, - bool Is64Bit, - uint32_t CPUType, - uint32_t CPUSubtype); - } // End llvm namespace #endif Removed: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=135938&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (removed) @@ -1,452 +0,0 @@ -//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmBackend.h" -#include "X86.h" -#include "MCTargetDesc/X86FixupKinds.h" -#include "llvm/ADT/Twine.h" -#include "llvm/MC/MCAssembler.h" -#include "llvm/MC/MCELFObjectWriter.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCFixupKindInfo.h" -#include "llvm/MC/MCMachObjectWriter.h" -#include "llvm/MC/MCObjectWriter.h" -#include "llvm/MC/MCSectionCOFF.h" -#include "llvm/MC/MCSectionELF.h" -#include "llvm/MC/MCSectionMachO.h" -#include "llvm/Object/MachOFormat.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/ELF.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetRegistry.h" -using namespace llvm; - -// Option to allow disabling arithmetic relaxation to workaround PR9807, which -// is useful when running bitwise comparison experiments on Darwin. We should be -// able to remove this once PR9807 is resolved. -static cl::opt -MCDisableArithRelaxation("mc-x86-disable-arith-relaxation", - cl::desc("Disable relaxation of arithmetic instruction for X86")); - -static unsigned getFixupKindLog2Size(unsigned Kind) { - switch (Kind) { - default: assert(0 && "invalid fixup kind!"); - case FK_PCRel_1: - case FK_Data_1: return 0; - case FK_PCRel_2: - case FK_Data_2: return 1; - case FK_PCRel_4: - case X86::reloc_riprel_4byte: - case X86::reloc_riprel_4byte_movq_load: - case X86::reloc_signed_4byte: - case X86::reloc_global_offset_table: - case FK_Data_4: return 2; - case FK_PCRel_8: - case FK_Data_8: return 3; - } -} - -namespace { - -class X86ELFObjectWriter : public MCELFObjectTargetWriter { -public: - X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine, - bool HasRelocationAddend) - : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {} -}; - -class X86AsmBackend : public TargetAsmBackend { -public: - X86AsmBackend(const Target &T) - : TargetAsmBackend() {} - - unsigned getNumFixupKinds() const { - return X86::NumTargetFixupKinds; - } - - const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { - const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { - { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }, - { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel}, - { "reloc_signed_4byte", 0, 4 * 8, 0}, - { "reloc_global_offset_table", 0, 4 * 8, 0} - }; - - if (Kind < FirstTargetFixupKind) - return TargetAsmBackend::getFixupKindInfo(Kind); - - assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && - "Invalid kind!"); - return Infos[Kind - FirstTargetFixupKind]; - } - - void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const { - unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); - - assert(Fixup.getOffset() + Size <= DataSize && - "Invalid fixup offset!"); - for (unsigned i = 0; i != Size; ++i) - Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); - } - - bool MayNeedRelaxation(const MCInst &Inst) const; - - void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; - - bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; -}; -} // end anonymous namespace - -static unsigned getRelaxedOpcodeBranch(unsigned Op) { - switch (Op) { - default: - return Op; - - case X86::JAE_1: return X86::JAE_4; - case X86::JA_1: return X86::JA_4; - case X86::JBE_1: return X86::JBE_4; - case X86::JB_1: return X86::JB_4; - case X86::JE_1: return X86::JE_4; - case X86::JGE_1: return X86::JGE_4; - case X86::JG_1: return X86::JG_4; - case X86::JLE_1: return X86::JLE_4; - case X86::JL_1: return X86::JL_4; - case X86::JMP_1: return X86::JMP_4; - case X86::JNE_1: return X86::JNE_4; - case X86::JNO_1: return X86::JNO_4; - case X86::JNP_1: return X86::JNP_4; - case X86::JNS_1: return X86::JNS_4; - case X86::JO_1: return X86::JO_4; - case X86::JP_1: return X86::JP_4; - case X86::JS_1: return X86::JS_4; - } -} - -static unsigned getRelaxedOpcodeArith(unsigned Op) { - switch (Op) { - default: - return Op; - - // IMUL - case X86::IMUL16rri8: return X86::IMUL16rri; - case X86::IMUL16rmi8: return X86::IMUL16rmi; - case X86::IMUL32rri8: return X86::IMUL32rri; - case X86::IMUL32rmi8: return X86::IMUL32rmi; - case X86::IMUL64rri8: return X86::IMUL64rri32; - case X86::IMUL64rmi8: return X86::IMUL64rmi32; - - // AND - case X86::AND16ri8: return X86::AND16ri; - case X86::AND16mi8: return X86::AND16mi; - case X86::AND32ri8: return X86::AND32ri; - case X86::AND32mi8: return X86::AND32mi; - case X86::AND64ri8: return X86::AND64ri32; - case X86::AND64mi8: return X86::AND64mi32; - - // OR - case X86::OR16ri8: return X86::OR16ri; - case X86::OR16mi8: return X86::OR16mi; - case X86::OR32ri8: return X86::OR32ri; - case X86::OR32mi8: return X86::OR32mi; - case X86::OR64ri8: return X86::OR64ri32; - case X86::OR64mi8: return X86::OR64mi32; - - // XOR - case X86::XOR16ri8: return X86::XOR16ri; - case X86::XOR16mi8: return X86::XOR16mi; - case X86::XOR32ri8: return X86::XOR32ri; - case X86::XOR32mi8: return X86::XOR32mi; - case X86::XOR64ri8: return X86::XOR64ri32; - case X86::XOR64mi8: return X86::XOR64mi32; - - // ADD - case X86::ADD16ri8: return X86::ADD16ri; - case X86::ADD16mi8: return X86::ADD16mi; - case X86::ADD32ri8: return X86::ADD32ri; - case X86::ADD32mi8: return X86::ADD32mi; - case X86::ADD64ri8: return X86::ADD64ri32; - case X86::ADD64mi8: return X86::ADD64mi32; - - // SUB - case X86::SUB16ri8: return X86::SUB16ri; - case X86::SUB16mi8: return X86::SUB16mi; - case X86::SUB32ri8: return X86::SUB32ri; - case X86::SUB32mi8: return X86::SUB32mi; - case X86::SUB64ri8: return X86::SUB64ri32; - case X86::SUB64mi8: return X86::SUB64mi32; - - // CMP - case X86::CMP16ri8: return X86::CMP16ri; - case X86::CMP16mi8: return X86::CMP16mi; - case X86::CMP32ri8: return X86::CMP32ri; - case X86::CMP32mi8: return X86::CMP32mi; - case X86::CMP64ri8: return X86::CMP64ri32; - case X86::CMP64mi8: return X86::CMP64mi32; - - // PUSH - case X86::PUSHi8: return X86::PUSHi32; - case X86::PUSHi16: return X86::PUSHi32; - case X86::PUSH64i8: return X86::PUSH64i32; - case X86::PUSH64i16: return X86::PUSH64i32; - } -} - -static unsigned getRelaxedOpcode(unsigned Op) { - unsigned R = getRelaxedOpcodeArith(Op); - if (R != Op) - return R; - return getRelaxedOpcodeBranch(Op); -} - -bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const { - // Branches can always be relaxed. - if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode()) - return true; - - if (MCDisableArithRelaxation) - return false; - - // Check if this instruction is ever relaxable. - if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode()) - return false; - - - // Check if it has an expression and is not RIP relative. - bool hasExp = false; - bool hasRIP = false; - for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { - const MCOperand &Op = Inst.getOperand(i); - if (Op.isExpr()) - hasExp = true; - - if (Op.isReg() && Op.getReg() == X86::RIP) - hasRIP = true; - } - - // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on - // how we do relaxations? - return hasExp && !hasRIP; -} - -// FIXME: Can tblgen help at all here to verify there aren't other instructions -// we can relax? -void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { - // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. - unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); - - if (RelaxedOp == Inst.getOpcode()) { - SmallString<256> Tmp; - raw_svector_ostream OS(Tmp); - Inst.dump_pretty(OS); - OS << "\n"; - report_fatal_error("unexpected instruction to relax: " + OS.str()); - } - - Res = Inst; - Res.setOpcode(RelaxedOp); -} - -/// WriteNopData - Write optimal nops to the output file for the \arg Count -/// bytes. This returns the number of bytes written. It may return 0 if -/// the \arg Count is more than the maximum optimal nops. -bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { - static const uint8_t Nops[10][10] = { - // nop - {0x90}, - // xchg %ax,%ax - {0x66, 0x90}, - // nopl (%[re]ax) - {0x0f, 0x1f, 0x00}, - // nopl 0(%[re]ax) - {0x0f, 0x1f, 0x40, 0x00}, - // nopl 0(%[re]ax,%[re]ax,1) - {0x0f, 0x1f, 0x44, 0x00, 0x00}, - // nopw 0(%[re]ax,%[re]ax,1) - {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, - // nopl 0L(%[re]ax) - {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, - // nopl 0L(%[re]ax,%[re]ax,1) - {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - // nopw 0L(%[re]ax,%[re]ax,1) - {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - // nopw %cs:0L(%[re]ax,%[re]ax,1) - {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - }; - - // Write an optimal sequence for the first 15 bytes. - const uint64_t OptimalCount = (Count < 16) ? Count : 15; - const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10; - for (uint64_t i = 0, e = Prefixes; i != e; i++) - OW->Write8(0x66); - const uint64_t Rest = OptimalCount - Prefixes; - for (uint64_t i = 0, e = Rest; i != e; i++) - OW->Write8(Nops[Rest - 1][i]); - - // Finish with single byte nops. - for (uint64_t i = OptimalCount, e = Count; i != e; ++i) - OW->Write8(0x90); - - return true; -} - -/* *** */ - -namespace { -class ELFX86AsmBackend : public X86AsmBackend { -public: - Triple::OSType OSType; - ELFX86AsmBackend(const Target &T, Triple::OSType _OSType) - : X86AsmBackend(T), OSType(_OSType) { - HasReliableSymbolDifference = true; - } - - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { - const MCSectionELF &ES = static_cast(Section); - return ES.getFlags() & ELF::SHF_MERGE; - } -}; - -class ELFX86_32AsmBackend : public ELFX86AsmBackend { -public: - ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType) - : ELFX86AsmBackend(T, OSType) {} - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ true); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false); - } -}; - -class ELFX86_64AsmBackend : public ELFX86AsmBackend { -public: - ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType) - : ELFX86AsmBackend(T, OSType) {} - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(createELFObjectTargetWriter(), - OS, /*IsLittleEndian*/ true); - } - - MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true); - } -}; - -class WindowsX86AsmBackend : public X86AsmBackend { - bool Is64Bit; - -public: - WindowsX86AsmBackend(const Target &T, bool is64Bit) - : X86AsmBackend(T) - , Is64Bit(is64Bit) { - } - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createWinCOFFObjectWriter(OS, Is64Bit); - } -}; - -class DarwinX86AsmBackend : public X86AsmBackend { -public: - DarwinX86AsmBackend(const Target &T) - : X86AsmBackend(T) { } -}; - -class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { -public: - DarwinX86_32AsmBackend(const Target &T) - : DarwinX86AsmBackend(T) {} - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createX86MachObjectWriter(OS, /*Is64Bit=*/false, - object::mach::CTM_i386, - object::mach::CSX86_ALL); - } -}; - -class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { -public: - DarwinX86_64AsmBackend(const Target &T) - : DarwinX86AsmBackend(T) { - HasReliableSymbolDifference = true; - } - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createX86MachObjectWriter(OS, /*Is64Bit=*/true, - object::mach::CTM_x86_64, - object::mach::CSX86_ALL); - } - - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { - // Temporary labels in the string literals sections require symbols. The - // issue is that the x86_64 relocation format does not allow symbol + - // offset, and so the linker does not have enough information to resolve the - // access to the appropriate atom unless an external relocation is used. For - // non-cstring sections, we expect the compiler to use a non-temporary label - // for anything that could have an addend pointing outside the symbol. - // - // See . - const MCSectionMachO &SMO = static_cast(Section); - return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS; - } - - virtual bool isSectionAtomizable(const MCSection &Section) const { - const MCSectionMachO &SMO = static_cast(Section); - // Fixed sized data sections are uniqued, they cannot be diced into atoms. - switch (SMO.getType()) { - default: - return true; - - case MCSectionMachO::S_4BYTE_LITERALS: - case MCSectionMachO::S_8BYTE_LITERALS: - case MCSectionMachO::S_16BYTE_LITERALS: - case MCSectionMachO::S_LITERAL_POINTERS: - case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS: - case MCSectionMachO::S_LAZY_SYMBOL_POINTERS: - case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS: - case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS: - case MCSectionMachO::S_INTERPOSING: - return false; - } - } -}; - -} // end anonymous namespace - -TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T, - const std::string &TT) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) - return new DarwinX86_32AsmBackend(T); - - if (TheTriple.isOSWindows()) - return new WindowsX86AsmBackend(T, false); - - return new ELFX86_32AsmBackend(T, TheTriple.getOS()); -} - -TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T, - const std::string &TT) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) - return new DarwinX86_64AsmBackend(T); - - if (TheTriple.isOSWindows()) - return new WindowsX86AsmBackend(T, true); - - return new ELFX86_64AsmBackend(T, TheTriple.getOS()); -} Removed: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=135938&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (removed) @@ -1,1055 +0,0 @@ -//===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the X86MCCodeEmitter class. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "mccodeemitter" -#include "MCTargetDesc/X86MCTargetDesc.h" -#include "MCTargetDesc/X86BaseInfo.h" -#include "MCTargetDesc/X86FixupKinds.h" -#include "llvm/MC/MCCodeEmitter.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -namespace { -class X86MCCodeEmitter : public MCCodeEmitter { - X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT - void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT - const MCInstrInfo &MCII; - const MCSubtargetInfo &STI; - MCContext &Ctx; -public: - X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, - MCContext &ctx) - : MCII(mcii), STI(sti), Ctx(ctx) { - } - - ~X86MCCodeEmitter() {} - - bool is64BitMode() const { - // FIXME: Can tablegen auto-generate this? - return (STI.getFeatureBits() & X86::Mode64Bit) != 0; - } - - static unsigned GetX86RegNum(const MCOperand &MO) { - return X86_MC::getX86RegNum(MO.getReg()); - } - - // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range - // 0-7 and the difference between the 2 groups is given by the REX prefix. - // In the VEX prefix, registers are seen sequencially from 0-15 and encoded - // in 1's complement form, example: - // - // ModRM field => XMM9 => 1 - // VEX.VVVV => XMM9 => ~9 - // - // See table 4-35 of Intel AVX Programming Reference for details. - static unsigned char getVEXRegisterEncoding(const MCInst &MI, - unsigned OpNum) { - unsigned SrcReg = MI.getOperand(OpNum).getReg(); - unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); - if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) || - (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15)) - SrcRegNum += 8; - - // The registers represented through VEX_VVVV should - // be encoded in 1's complement form. - return (~SrcRegNum) & 0xf; - } - - void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { - OS << (char)C; - ++CurByte; - } - - void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, - raw_ostream &OS) const { - // Output the constant in little endian byte order. - for (unsigned i = 0; i != Size; ++i) { - EmitByte(Val & 255, CurByte, OS); - Val >>= 8; - } - } - - void EmitImmediate(const MCOperand &Disp, - unsigned ImmSize, MCFixupKind FixupKind, - unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups, - int ImmOffset = 0) const; - - inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, - unsigned RM) { - assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); - return RM | (RegOpcode << 3) | (Mod << 6); - } - - void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, - unsigned &CurByte, raw_ostream &OS) const { - EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); - } - - void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, - unsigned &CurByte, raw_ostream &OS) const { - // SIB byte is in the same format as the ModRMByte. - EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); - } - - - void EmitMemModRMByte(const MCInst &MI, unsigned Op, - unsigned RegOpcodeField, - uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups) const; - - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const; - - void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, - const MCInst &MI, const MCInstrDesc &Desc, - raw_ostream &OS) const; - - void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, - int MemOperand, const MCInst &MI, - raw_ostream &OS) const; - - void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, - const MCInst &MI, const MCInstrDesc &Desc, - raw_ostream &OS) const; -}; - -} // end anonymous namespace - - -MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new X86MCCodeEmitter(MCII, STI, Ctx); -} - -/// isDisp8 - Return true if this signed displacement fits in a 8-bit -/// sign-extended field. -static bool isDisp8(int Value) { - return Value == (signed char)Value; -} - -/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate -/// in an instruction with the specified TSFlags. -static MCFixupKind getImmFixupKind(uint64_t TSFlags) { - unsigned Size = X86II::getSizeOfImm(TSFlags); - bool isPCRel = X86II::isImmPCRel(TSFlags); - - return MCFixup::getKindForSize(Size, isPCRel); -} - -namespace llvm { - // FIXME: TableGen this? - extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc. -} - -/// Is32BitMemOperand - Return true if the specified instruction with a memory -/// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit -/// memory operand. Op specifies the operand # of the memoperand. -static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { - const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); - const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); - - if ((BaseReg.getReg() != 0 && - X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || - (IndexReg.getReg() != 0 && - X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) - return true; - return false; -} - -/// StartsWithGlobalOffsetTable - Return true for the simple cases where this -/// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support -/// PIC on ELF i386 as that symbol is magic. We check only simple case that -/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start -/// of a binary expression. -static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) { - if (Expr->getKind() == MCExpr::Binary) { - const MCBinaryExpr *BE = static_cast(Expr); - Expr = BE->getLHS(); - } - - if (Expr->getKind() != MCExpr::SymbolRef) - return false; - - const MCSymbolRefExpr *Ref = static_cast(Expr); - const MCSymbol &S = Ref->getSymbol(); - return S.getName() == "_GLOBAL_OFFSET_TABLE_"; -} - -void X86MCCodeEmitter:: -EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, - unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups, int ImmOffset) const { - const MCExpr *Expr = NULL; - if (DispOp.isImm()) { - // If this is a simple integer displacement that doesn't require a relocation, - // emit it now. - if (FixupKind != FK_PCRel_1 && - FixupKind != FK_PCRel_2 && - FixupKind != FK_PCRel_4) { - EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); - return; - } - Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); - } else { - Expr = DispOp.getExpr(); - } - - // If we have an immoffset, add it to the expression. - if ((FixupKind == FK_Data_4 || - FixupKind == MCFixupKind(X86::reloc_signed_4byte)) && - StartsWithGlobalOffsetTable(Expr)) { - assert(ImmOffset == 0); - - FixupKind = MCFixupKind(X86::reloc_global_offset_table); - ImmOffset = CurByte; - } - - // If the fixup is pc-relative, we need to bias the value to be relative to - // the start of the field, not the end of the field. - if (FixupKind == FK_PCRel_4 || - FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || - FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) - ImmOffset -= 4; - if (FixupKind == FK_PCRel_2) - ImmOffset -= 2; - if (FixupKind == FK_PCRel_1) - ImmOffset -= 1; - - if (ImmOffset) - Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), - Ctx); - - // Emit a symbolic constant as a fixup and 4 zeros. - Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind)); - EmitConstant(0, Size, CurByte, OS); -} - -void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, - unsigned RegOpcodeField, - uint64_t TSFlags, unsigned &CurByte, - raw_ostream &OS, - SmallVectorImpl &Fixups) const{ - const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); - const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); - const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); - const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); - unsigned BaseReg = Base.getReg(); - - // Handle %rip relative addressing. - if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode - assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); - assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); - EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); - - unsigned FixupKind = X86::reloc_riprel_4byte; - - // movq loads are handled with a special relocation form which allows the - // linker to eliminate some loads for GOT references which end up in the - // same linkage unit. - if (MI.getOpcode() == X86::MOV64rm) - FixupKind = X86::reloc_riprel_4byte_movq_load; - - // rip-relative addressing is actually relative to the *next* instruction. - // Since an immediate can follow the mod/rm byte for an instruction, this - // means that we need to bias the immediate field of the instruction with - // the size of the immediate field. If we have this case, add it into the - // expression to emit. - int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; - - EmitImmediate(Disp, 4, MCFixupKind(FixupKind), - CurByte, OS, Fixups, -ImmSize); - return; - } - - unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; - - // Determine whether a SIB byte is needed. - // If no BaseReg, issue a RIP relative instruction only if the MCE can - // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table - // 2-7) and absolute references. - - if (// The SIB byte must be used if there is an index register. - IndexReg.getReg() == 0 && - // The SIB byte must be used if the base is ESP/RSP/R12, all of which - // encode to an R/M value of 4, which indicates that a SIB byte is - // present. - BaseRegNo != N86::ESP && - // If there is no base register and we're in 64-bit mode, we need a SIB - // byte to emit an addr that is just 'disp32' (the non-RIP relative form). - (!is64BitMode() || BaseReg != 0)) { - - if (BaseReg == 0) { // [disp32] in X86-32 mode - EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); - EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups); - return; - } - - // If the base is not EBP/ESP and there is no displacement, use simple - // indirect register encoding, this handles addresses like [EAX]. The - // encoding for [EBP] with no displacement means [disp32] so we handle it - // by emitting a displacement of 0 below. - if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { - EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); - return; - } - - // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. - if (Disp.isImm() && isDisp8(Disp.getImm())) { - EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); - EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups); - return; - } - - // Otherwise, emit the most general non-SIB encoding: [REG+disp32] - EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); - EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, - Fixups); - return; - } - - // We need a SIB byte, so start by outputting the ModR/M byte first - assert(IndexReg.getReg() != X86::ESP && - IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); - - bool ForceDisp32 = false; - bool ForceDisp8 = false; - if (BaseReg == 0) { - // If there is no base register, we emit the special case SIB byte with - // MOD=0, BASE=5, to JUST get the index, scale, and displacement. - EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); - ForceDisp32 = true; - } else if (!Disp.isImm()) { - // Emit the normal disp32 encoding. - EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); - ForceDisp32 = true; - } else if (Disp.getImm() == 0 && - // Base reg can't be anything that ends up with '5' as the base - // reg, it is the magic [*] nomenclature that indicates no base. - BaseRegNo != N86::EBP) { - // Emit no displacement ModR/M byte - EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); - } else if (isDisp8(Disp.getImm())) { - // Emit the disp8 encoding. - EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); - ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP - } else { - // Emit the normal disp32 encoding. - EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); - } - - // Calculate what the SS field value should be... - static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 }; - unsigned SS = SSTable[Scale.getImm()]; - - if (BaseReg == 0) { - // Handle the SIB byte for the case where there is no base, see Intel - // Manual 2A, table 2-7. The displacement has already been output. - unsigned IndexRegNo; - if (IndexReg.getReg()) - IndexRegNo = GetX86RegNum(IndexReg); - else // Examples: [ESP+1*+4] or [scaled idx]+disp32 (MOD=0,BASE=5) - IndexRegNo = 4; - EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); - } else { - unsigned IndexRegNo; - if (IndexReg.getReg()) - IndexRegNo = GetX86RegNum(IndexReg); - else - IndexRegNo = 4; // For example [ESP+1*+4] - EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); - } - - // Do we need to output a displacement? - if (ForceDisp8) - EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups); - else if (ForceDisp32 || Disp.getImm() != 0) - EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, - Fixups); -} - -/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix -/// called VEX. -void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, - int MemOperand, const MCInst &MI, - const MCInstrDesc &Desc, - raw_ostream &OS) const { - bool HasVEX_4V = false; - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V) - HasVEX_4V = true; - - // VEX_R: opcode externsion equivalent to REX.R in - // 1's complement (inverted) form - // - // 1: Same as REX_R=0 (must be 1 in 32-bit mode) - // 0: Same as REX_R=1 (64 bit mode only) - // - unsigned char VEX_R = 0x1; - - // VEX_X: equivalent to REX.X, only used when a - // register is used for index in SIB Byte. - // - // 1: Same as REX.X=0 (must be 1 in 32-bit mode) - // 0: Same as REX.X=1 (64-bit mode only) - unsigned char VEX_X = 0x1; - - // VEX_B: - // - // 1: Same as REX_B=0 (ignored in 32-bit mode) - // 0: Same as REX_B=1 (64 bit mode only) - // - unsigned char VEX_B = 0x1; - - // VEX_W: opcode specific (use like REX.W, or used for - // opcode extension, or ignored, depending on the opcode byte) - unsigned char VEX_W = 0; - - // VEX_5M (VEX m-mmmmm field): - // - // 0b00000: Reserved for future use - // 0b00001: implied 0F leading opcode - // 0b00010: implied 0F 38 leading opcode bytes - // 0b00011: implied 0F 3A leading opcode bytes - // 0b00100-0b11111: Reserved for future use - // - unsigned char VEX_5M = 0x1; - - // VEX_4V (VEX vvvv field): a register specifier - // (in 1's complement form) or 1111 if unused. - unsigned char VEX_4V = 0xf; - - // VEX_L (Vector Length): - // - // 0: scalar or 128-bit vector - // 1: 256-bit vector - // - unsigned char VEX_L = 0; - - // VEX_PP: opcode extension providing equivalent - // functionality of a SIMD prefix - // - // 0b00: None - // 0b01: 66 - // 0b10: F3 - // 0b11: F2 - // - unsigned char VEX_PP = 0; - - // Encode the operand size opcode prefix as needed. - if (TSFlags & X86II::OpSize) - VEX_PP = 0x01; - - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) - VEX_W = 1; - - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) - VEX_L = 1; - - switch (TSFlags & X86II::Op0Mask) { - default: assert(0 && "Invalid prefix!"); - case X86II::T8: // 0F 38 - VEX_5M = 0x2; - break; - case X86II::TA: // 0F 3A - VEX_5M = 0x3; - break; - case X86II::TF: // F2 0F 38 - VEX_PP = 0x3; - VEX_5M = 0x2; - break; - case X86II::XS: // F3 0F - VEX_PP = 0x2; - break; - case X86II::XD: // F2 0F - VEX_PP = 0x3; - break; - case X86II::A6: // Bypass: Not used by VEX - case X86II::A7: // Bypass: Not used by VEX - case X86II::TB: // Bypass: Not used by VEX - case 0: - break; // No prefix! - } - - // Set the vector length to 256-bit if YMM0-YMM15 is used - for (unsigned i = 0; i != MI.getNumOperands(); ++i) { - if (!MI.getOperand(i).isReg()) - continue; - unsigned SrcReg = MI.getOperand(i).getReg(); - if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15) - VEX_L = 1; - } - - unsigned NumOps = MI.getNumOperands(); - unsigned CurOp = 0; - bool IsDestMem = false; - - switch (TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!"); - case X86II::MRMDestMem: - IsDestMem = true; - // The important info for the VEX prefix is never beyond the address - // registers. Don't check beyond that. - NumOps = CurOp = X86::AddrNumOperands; - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - case X86II::MRMSrcMem: - case X86II::MRMSrcReg: - if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) - VEX_R = 0x0; - CurOp++; - - if (HasVEX_4V) { - VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp); - CurOp++; - } - - // To only check operands before the memory address ones, start - // the search from the beginning - if (IsDestMem) - CurOp = 0; - - // If the last register should be encoded in the immediate field - // do not use any bit from VEX prefix to this register, ignore it - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) - NumOps--; - - for (; CurOp != NumOps; ++CurOp) { - const MCOperand &MO = MI.getOperand(CurOp); - if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) - VEX_B = 0x0; - if (!VEX_B && MO.isReg() && - ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) && - X86II::isX86_64ExtendedReg(MO.getReg())) - VEX_X = 0x0; - } - break; - default: // MRMDestReg, MRM0r-MRM7r, RawFrm - if (!MI.getNumOperands()) - break; - - if (MI.getOperand(CurOp).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) - VEX_B = 0; - - if (HasVEX_4V) - VEX_4V = getVEXRegisterEncoding(MI, CurOp); - - CurOp++; - for (; CurOp != NumOps; ++CurOp) { - const MCOperand &MO = MI.getOperand(CurOp); - if (MO.isReg() && !HasVEX_4V && - X86II::isX86_64ExtendedReg(MO.getReg())) - VEX_R = 0x0; - } - break; - } - - // Emit segment override opcode prefix as needed. - EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); - - // VEX opcode prefix can have 2 or 3 bytes - // - // 3 bytes: - // +-----+ +--------------+ +-------------------+ - // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | - // +-----+ +--------------+ +-------------------+ - // 2 bytes: - // +-----+ +-------------------+ - // | C5h | | R | vvvv | L | pp | - // +-----+ +-------------------+ - // - unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); - - if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix - EmitByte(0xC5, CurByte, OS); - EmitByte(LastByte | (VEX_R << 7), CurByte, OS); - return; - } - - // 3 byte VEX prefix - EmitByte(0xC4, CurByte, OS); - EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); - EmitByte(LastByte | (VEX_W << 7), CurByte, OS); -} - -/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 -/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand -/// size, and 3) use of X86-64 extended registers. -static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, - const MCInstrDesc &Desc) { - unsigned REX = 0; - if (TSFlags & X86II::REX_W) - REX |= 1 << 3; // set REX.W - - if (MI.getNumOperands() == 0) return REX; - - unsigned NumOps = MI.getNumOperands(); - // FIXME: MCInst should explicitize the two-addrness. - bool isTwoAddr = NumOps > 1 && - Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; - - // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. - unsigned i = isTwoAddr ? 1 : 0; - for (; i != NumOps; ++i) { - const MCOperand &MO = MI.getOperand(i); - if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; - // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything - // that returns non-zero. - REX |= 0x40; // REX fixed encoding prefix - break; - } - - switch (TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!"); - case X86II::MRMSrcReg: - if (MI.getOperand(0).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) - REX |= 1 << 2; // set REX.R - i = isTwoAddr ? 2 : 1; - for (; i != NumOps; ++i) { - const MCOperand &MO = MI.getOperand(i); - if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) - REX |= 1 << 0; // set REX.B - } - break; - case X86II::MRMSrcMem: { - if (MI.getOperand(0).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) - REX |= 1 << 2; // set REX.R - unsigned Bit = 0; - i = isTwoAddr ? 2 : 1; - for (; i != NumOps; ++i) { - const MCOperand &MO = MI.getOperand(i); - if (MO.isReg()) { - if (X86II::isX86_64ExtendedReg(MO.getReg())) - REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) - Bit++; - } - } - break; - } - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - case X86II::MRMDestMem: { - unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); - i = isTwoAddr ? 1 : 0; - if (NumOps > e && MI.getOperand(e).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) - REX |= 1 << 2; // set REX.R - unsigned Bit = 0; - for (; i != e; ++i) { - const MCOperand &MO = MI.getOperand(i); - if (MO.isReg()) { - if (X86II::isX86_64ExtendedReg(MO.getReg())) - REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) - Bit++; - } - } - break; - } - default: - if (MI.getOperand(0).isReg() && - X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) - REX |= 1 << 0; // set REX.B - i = isTwoAddr ? 2 : 1; - for (unsigned e = NumOps; i != e; ++i) { - const MCOperand &MO = MI.getOperand(i); - if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) - REX |= 1 << 2; // set REX.R - } - break; - } - return REX; -} - -/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed -void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, - unsigned &CurByte, int MemOperand, - const MCInst &MI, - raw_ostream &OS) const { - switch (TSFlags & X86II::SegOvrMask) { - default: assert(0 && "Invalid segment!"); - case 0: - // No segment override, check for explicit one on memory operand. - if (MemOperand != -1) { // If the instruction has a memory operand. - switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { - default: assert(0 && "Unknown segment register!"); - case 0: break; - case X86::CS: EmitByte(0x2E, CurByte, OS); break; - case X86::SS: EmitByte(0x36, CurByte, OS); break; - case X86::DS: EmitByte(0x3E, CurByte, OS); break; - case X86::ES: EmitByte(0x26, CurByte, OS); break; - case X86::FS: EmitByte(0x64, CurByte, OS); break; - case X86::GS: EmitByte(0x65, CurByte, OS); break; - } - } - break; - case X86II::FS: - EmitByte(0x64, CurByte, OS); - break; - case X86II::GS: - EmitByte(0x65, CurByte, OS); - break; - } -} - -/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. -/// -/// MemOperand is the operand # of the start of a memory operand if present. If -/// Not present, it is -1. -void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, - int MemOperand, const MCInst &MI, - const MCInstrDesc &Desc, - raw_ostream &OS) const { - - // Emit the lock opcode prefix as needed. - if (TSFlags & X86II::LOCK) - EmitByte(0xF0, CurByte, OS); - - // Emit segment override opcode prefix as needed. - EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); - - // Emit the repeat opcode prefix as needed. - if ((TSFlags & X86II::Op0Mask) == X86II::REP) - EmitByte(0xF3, CurByte, OS); - - // Emit the address size opcode prefix as needed. - if ((TSFlags & X86II::AdSize) || - (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand))) - EmitByte(0x67, CurByte, OS); - - // Emit the operand size opcode prefix as needed. - if (TSFlags & X86II::OpSize) - EmitByte(0x66, CurByte, OS); - - bool Need0FPrefix = false; - switch (TSFlags & X86II::Op0Mask) { - default: assert(0 && "Invalid prefix!"); - case 0: break; // No prefix! - case X86II::REP: break; // already handled. - case X86II::TB: // Two-byte opcode prefix - case X86II::T8: // 0F 38 - case X86II::TA: // 0F 3A - case X86II::A6: // 0F A6 - case X86II::A7: // 0F A7 - Need0FPrefix = true; - break; - case X86II::TF: // F2 0F 38 - EmitByte(0xF2, CurByte, OS); - Need0FPrefix = true; - break; - case X86II::XS: // F3 0F - EmitByte(0xF3, CurByte, OS); - Need0FPrefix = true; - break; - case X86II::XD: // F2 0F - EmitByte(0xF2, CurByte, OS); - Need0FPrefix = true; - break; - case X86II::D8: EmitByte(0xD8, CurByte, OS); break; - case X86II::D9: EmitByte(0xD9, CurByte, OS); break; - case X86II::DA: EmitByte(0xDA, CurByte, OS); break; - case X86II::DB: EmitByte(0xDB, CurByte, OS); break; - case X86II::DC: EmitByte(0xDC, CurByte, OS); break; - case X86II::DD: EmitByte(0xDD, CurByte, OS); break; - case X86II::DE: EmitByte(0xDE, CurByte, OS); break; - case X86II::DF: EmitByte(0xDF, CurByte, OS); break; - } - - // Handle REX prefix. - // FIXME: Can this come before F2 etc to simplify emission? - if (is64BitMode()) { - if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) - EmitByte(0x40 | REX, CurByte, OS); - } - - // 0x0F escape code must be emitted just before the opcode. - if (Need0FPrefix) - EmitByte(0x0F, CurByte, OS); - - // FIXME: Pull this up into previous switch if REX can be moved earlier. - switch (TSFlags & X86II::Op0Mask) { - case X86II::TF: // F2 0F 38 - case X86II::T8: // 0F 38 - EmitByte(0x38, CurByte, OS); - break; - case X86II::TA: // 0F 3A - EmitByte(0x3A, CurByte, OS); - break; - case X86II::A6: // 0F A6 - EmitByte(0xA6, CurByte, OS); - break; - case X86II::A7: // 0F A7 - EmitByte(0xA7, CurByte, OS); - break; - } -} - -void X86MCCodeEmitter:: -EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const { - unsigned Opcode = MI.getOpcode(); - const MCInstrDesc &Desc = MCII.get(Opcode); - uint64_t TSFlags = Desc.TSFlags; - - // Pseudo instructions don't get encoded. - if ((TSFlags & X86II::FormMask) == X86II::Pseudo) - return; - - // If this is a two-address instruction, skip one of the register operands. - // FIXME: This should be handled during MCInst lowering. - unsigned NumOps = Desc.getNumOperands(); - unsigned CurOp = 0; - if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) - ++CurOp; - else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) - // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 - --NumOps; - - // Keep track of the current byte being emitted. - unsigned CurByte = 0; - - // Is this instruction encoded using the AVX VEX prefix? - bool HasVEXPrefix = false; - - // It uses the VEX.VVVV field? - bool HasVEX_4V = false; - - if ((TSFlags >> X86II::VEXShift) & X86II::VEX) - HasVEXPrefix = true; - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V) - HasVEX_4V = true; - - - // Determine where the memory operand starts, if present. - int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); - if (MemoryOperand != -1) MemoryOperand += CurOp; - - if (!HasVEXPrefix) - EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); - else - EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); - - - unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); - - if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) - BaseOpcode = 0x0F; // Weird 3DNow! encoding. - - unsigned SrcRegNum = 0; - switch (TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: - assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); - default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; - assert(0 && "Unknown FormMask value in X86MCCodeEmitter!"); - case X86II::Pseudo: - assert(0 && "Pseudo instruction shouldn't be emitted"); - case X86II::RawFrm: - EmitByte(BaseOpcode, CurByte, OS); - break; - - case X86II::RawFrmImm8: - EmitByte(BaseOpcode, CurByte, OS); - EmitImmediate(MI.getOperand(CurOp++), - X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), - CurByte, OS, Fixups); - EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups); - break; - case X86II::RawFrmImm16: - EmitByte(BaseOpcode, CurByte, OS); - EmitImmediate(MI.getOperand(CurOp++), - X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), - CurByte, OS, Fixups); - EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups); - break; - - case X86II::AddRegFrm: - EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); - break; - - case X86II::MRMDestReg: - EmitByte(BaseOpcode, CurByte, OS); - EmitRegModRMByte(MI.getOperand(CurOp), - GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS); - CurOp += 2; - break; - - case X86II::MRMDestMem: - EmitByte(BaseOpcode, CurByte, OS); - SrcRegNum = CurOp + X86::AddrNumOperands; - - if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) - SrcRegNum++; - - EmitMemModRMByte(MI, CurOp, - GetX86RegNum(MI.getOperand(SrcRegNum)), - TSFlags, CurByte, OS, Fixups); - CurOp = SrcRegNum + 1; - break; - - case X86II::MRMSrcReg: - EmitByte(BaseOpcode, CurByte, OS); - SrcRegNum = CurOp + 1; - - if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) - SrcRegNum++; - - EmitRegModRMByte(MI.getOperand(SrcRegNum), - GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); - CurOp = SrcRegNum + 1; - break; - - case X86II::MRMSrcMem: { - int AddrOperands = X86::AddrNumOperands; - unsigned FirstMemOp = CurOp+1; - if (HasVEX_4V) { - ++AddrOperands; - ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). - } - - EmitByte(BaseOpcode, CurByte, OS); - - EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), - TSFlags, CurByte, OS, Fixups); - CurOp += AddrOperands + 1; - break; - } - - case X86II::MRM0r: case X86II::MRM1r: - case X86II::MRM2r: case X86II::MRM3r: - case X86II::MRM4r: case X86II::MRM5r: - case X86II::MRM6r: case X86II::MRM7r: - if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). - CurOp++; - EmitByte(BaseOpcode, CurByte, OS); - EmitRegModRMByte(MI.getOperand(CurOp++), - (TSFlags & X86II::FormMask)-X86II::MRM0r, - CurByte, OS); - break; - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - EmitByte(BaseOpcode, CurByte, OS); - EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, - TSFlags, CurByte, OS, Fixups); - CurOp += X86::AddrNumOperands; - break; - case X86II::MRM_C1: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC1, CurByte, OS); - break; - case X86II::MRM_C2: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC2, CurByte, OS); - break; - case X86II::MRM_C3: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC3, CurByte, OS); - break; - case X86II::MRM_C4: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC4, CurByte, OS); - break; - case X86II::MRM_C8: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC8, CurByte, OS); - break; - case X86II::MRM_C9: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xC9, CurByte, OS); - break; - case X86II::MRM_E8: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xE8, CurByte, OS); - break; - case X86II::MRM_F0: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xF0, CurByte, OS); - break; - case X86II::MRM_F8: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xF8, CurByte, OS); - break; - case X86II::MRM_F9: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xF9, CurByte, OS); - break; - case X86II::MRM_D0: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xD0, CurByte, OS); - break; - case X86II::MRM_D1: - EmitByte(BaseOpcode, CurByte, OS); - EmitByte(0xD1, CurByte, OS); - break; - } - - // If there is a remaining operand, it must be a trailing immediate. Emit it - // according to the right size for the instruction. - if (CurOp != NumOps) { - // The last source register of a 4 operand instruction in AVX is encoded - // in bits[7:4] of a immediate byte, and bits[3:0] are ignored. - if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { - const MCOperand &MO = MI.getOperand(CurOp++); - bool IsExtReg = - X86II::isX86_64ExtendedReg(MO.getReg()); - unsigned RegNum = (IsExtReg ? (1 << 7) : 0); - RegNum |= GetX86RegNum(MO) << 4; - EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS, - Fixups); - } else { - unsigned FixupKind; - // FIXME: Is there a better way to know that we need a signed relocation? - if (MI.getOpcode() == X86::ADD64ri32 || - MI.getOpcode() == X86::MOV64ri32 || - MI.getOpcode() == X86::MOV64mi32 || - MI.getOpcode() == X86::PUSH64i32) - FixupKind = X86::reloc_signed_4byte; - else - FixupKind = getImmFixupKind(TSFlags); - EmitImmediate(MI.getOperand(CurOp++), - X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), - CurByte, OS, Fixups); - } - } - - if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) - EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); - - -#ifndef NDEBUG - // FIXME: Verify. - if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { - errs() << "Cannot encode all operands of: "; - MI.dump(); - errs() << '\n'; - abort(); - } -#endif -} Removed: llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp?rev=135938&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp (removed) @@ -1,554 +0,0 @@ -//===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "X86.h" -#include "MCTargetDesc/X86FixupKinds.h" -#include "llvm/ADT/Twine.h" -#include "llvm/MC/MCAssembler.h" -#include "llvm/MC/MCAsmLayout.h" -#include "llvm/MC/MCMachObjectWriter.h" -#include "llvm/MC/MCSectionMachO.h" -#include "llvm/MC/MCValue.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Object/MachOFormat.h" - -using namespace llvm; -using namespace llvm::object; - -namespace { -class X86MachObjectWriter : public MCMachObjectTargetWriter { - void RecordScatteredRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - unsigned Log2Size, - uint64_t &FixedValue); - void RecordTLVPRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue); - - void RecordX86Relocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue); - void RecordX86_64Relocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue); -public: - X86MachObjectWriter(bool Is64Bit, uint32_t CPUType, - uint32_t CPUSubtype) - : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype, - /*UseAggressiveSymbolFolding=*/Is64Bit) {} - - void RecordRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, const MCAsmLayout &Layout, - const MCFragment *Fragment, const MCFixup &Fixup, - MCValue Target, uint64_t &FixedValue) { - if (Writer->is64Bit()) - RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, - FixedValue); - else - RecordX86Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, - FixedValue); - } -}; -} - -static bool isFixupKindRIPRel(unsigned Kind) { - return Kind == X86::reloc_riprel_4byte || - Kind == X86::reloc_riprel_4byte_movq_load; -} - -static unsigned getFixupKindLog2Size(unsigned Kind) { - switch (Kind) { - default: - llvm_unreachable("invalid fixup kind!"); - case FK_PCRel_1: - case FK_Data_1: return 0; - case FK_PCRel_2: - case FK_Data_2: return 1; - case FK_PCRel_4: - // FIXME: Remove these!!! - case X86::reloc_riprel_4byte: - case X86::reloc_riprel_4byte_movq_load: - case X86::reloc_signed_4byte: - case FK_Data_4: return 2; - case FK_Data_8: return 3; - } -} - -void X86MachObjectWriter::RecordX86_64Relocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue) { - unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind()); - unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind()); - unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); - - // See . - uint32_t FixupOffset = - Layout.getFragmentOffset(Fragment) + Fixup.getOffset(); - uint32_t FixupAddress = - Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset(); - int64_t Value = 0; - unsigned Index = 0; - unsigned IsExtern = 0; - unsigned Type = 0; - - Value = Target.getConstant(); - - if (IsPCRel) { - // Compensate for the relocation offset, Darwin x86_64 relocations only have - // the addend and appear to have attempted to define it to be the actual - // expression addend without the PCrel bias. However, instructions with data - // following the relocation are not accommodated for (see comment below - // regarding SIGNED{1,2,4}), so it isn't exactly that either. - Value += 1LL << Log2Size; - } - - if (Target.isAbsolute()) { // constant - // SymbolNum of 0 indicates the absolute section. - Type = macho::RIT_X86_64_Unsigned; - Index = 0; - - // FIXME: I believe this is broken, I don't think the linker can understand - // it. I think it would require a local relocation, but I'm not sure if that - // would work either. The official way to get an absolute PCrel relocation - // is to use an absolute symbol (which we don't support yet). - if (IsPCRel) { - IsExtern = 1; - Type = macho::RIT_X86_64_Branch; - } - } else if (Target.getSymB()) { // A - B + constant - const MCSymbol *A = &Target.getSymA()->getSymbol(); - MCSymbolData &A_SD = Asm.getSymbolData(*A); - const MCSymbolData *A_Base = Asm.getAtom(&A_SD); - - const MCSymbol *B = &Target.getSymB()->getSymbol(); - MCSymbolData &B_SD = Asm.getSymbolData(*B); - const MCSymbolData *B_Base = Asm.getAtom(&B_SD); - - // Neither symbol can be modified. - if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None || - Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None) - report_fatal_error("unsupported relocation of modified symbol"); - - // We don't support PCrel relocations of differences. Darwin 'as' doesn't - // implement most of these correctly. - if (IsPCRel) - report_fatal_error("unsupported pc-relative relocation of difference"); - - // The support for the situation where one or both of the symbols would - // require a local relocation is handled just like if the symbols were - // external. This is certainly used in the case of debug sections where the - // section has only temporary symbols and thus the symbols don't have base - // symbols. This is encoded using the section ordinal and non-extern - // relocation entries. - - // Darwin 'as' doesn't emit correct relocations for this (it ends up with a - // single SIGNED relocation); reject it for now. Except the case where both - // symbols don't have a base, equal but both NULL. - if (A_Base == B_Base && A_Base) - report_fatal_error("unsupported relocation with identical base"); - - Value += Writer->getSymbolAddress(&A_SD, Layout) - - (A_Base == NULL ? 0 : Writer->getSymbolAddress(A_Base, Layout)); - Value -= Writer->getSymbolAddress(&B_SD, Layout) - - (B_Base == NULL ? 0 : Writer->getSymbolAddress(B_Base, Layout)); - - if (A_Base) { - Index = A_Base->getIndex(); - IsExtern = 1; - } - else { - Index = A_SD.getFragment()->getParent()->getOrdinal() + 1; - IsExtern = 0; - } - Type = macho::RIT_X86_64_Unsigned; - - macho::RelocationEntry MRE; - MRE.Word0 = FixupOffset; - MRE.Word1 = ((Index << 0) | - (IsPCRel << 24) | - (Log2Size << 25) | - (IsExtern << 27) | - (Type << 28)); - Writer->addRelocation(Fragment->getParent(), MRE); - - if (B_Base) { - Index = B_Base->getIndex(); - IsExtern = 1; - } - else { - Index = B_SD.getFragment()->getParent()->getOrdinal() + 1; - IsExtern = 0; - } - Type = macho::RIT_X86_64_Subtractor; - } else { - const MCSymbol *Symbol = &Target.getSymA()->getSymbol(); - MCSymbolData &SD = Asm.getSymbolData(*Symbol); - const MCSymbolData *Base = Asm.getAtom(&SD); - - // Relocations inside debug sections always use local relocations when - // possible. This seems to be done because the debugger doesn't fully - // understand x86_64 relocation entries, and expects to find values that - // have already been fixed up. - if (Symbol->isInSection()) { - const MCSectionMachO &Section = static_cast( - Fragment->getParent()->getSection()); - if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG)) - Base = 0; - } - - // x86_64 almost always uses external relocations, except when there is no - // symbol to use as a base address (a local symbol with no preceding - // non-local symbol). - if (Base) { - Index = Base->getIndex(); - IsExtern = 1; - - // Add the local offset, if needed. - if (Base != &SD) - Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base); - } else if (Symbol->isInSection() && !Symbol->isVariable()) { - // The index is the section ordinal (1-based). - Index = SD.getFragment()->getParent()->getOrdinal() + 1; - IsExtern = 0; - Value += Writer->getSymbolAddress(&SD, Layout); - - if (IsPCRel) - Value -= FixupAddress + (1 << Log2Size); - } else if (Symbol->isVariable()) { - const MCExpr *Value = Symbol->getVariableValue(); - int64_t Res; - bool isAbs = Value->EvaluateAsAbsolute(Res, Layout, - Writer->getSectionAddressMap()); - if (isAbs) { - FixedValue = Res; - return; - } else { - report_fatal_error("unsupported relocation of variable '" + - Symbol->getName() + "'"); - } - } else { - report_fatal_error("unsupported relocation of undefined symbol '" + - Symbol->getName() + "'"); - } - - MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind(); - if (IsPCRel) { - if (IsRIPRel) { - if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) { - // x86_64 distinguishes movq foo at GOTPCREL so that the linker can - // rewrite the movq to an leaq at link time if the symbol ends up in - // the same linkage unit. - if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load) - Type = macho::RIT_X86_64_GOTLoad; - else - Type = macho::RIT_X86_64_GOT; - } else if (Modifier == MCSymbolRefExpr::VK_TLVP) { - Type = macho::RIT_X86_64_TLV; - } else if (Modifier != MCSymbolRefExpr::VK_None) { - report_fatal_error("unsupported symbol modifier in relocation"); - } else { - Type = macho::RIT_X86_64_Signed; - - // The Darwin x86_64 relocation format has a problem where it cannot - // encode an address (L + ) which is outside the atom - // containing L. Generally, this shouldn't occur but it does - // happen when we have a RIPrel instruction with data following the - // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel - // adjustment Darwin x86_64 uses, the offset is still negative and the - // linker has no way to recognize this. - // - // To work around this, Darwin uses several special relocation types - // to indicate the offsets. However, the specification or - // implementation of these seems to also be incomplete; they should - // adjust the addend as well based on the actual encoded instruction - // (the additional bias), but instead appear to just look at the final - // offset. - switch (-(Target.getConstant() + (1LL << Log2Size))) { - case 1: Type = macho::RIT_X86_64_Signed1; break; - case 2: Type = macho::RIT_X86_64_Signed2; break; - case 4: Type = macho::RIT_X86_64_Signed4; break; - } - } - } else { - if (Modifier != MCSymbolRefExpr::VK_None) - report_fatal_error("unsupported symbol modifier in branch " - "relocation"); - - Type = macho::RIT_X86_64_Branch; - } - } else { - if (Modifier == MCSymbolRefExpr::VK_GOT) { - Type = macho::RIT_X86_64_GOT; - } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) { - // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which - // case all we do is set the PCrel bit in the relocation entry; this is - // used with exception handling, for example. The source is required to - // include any necessary offset directly. - Type = macho::RIT_X86_64_GOT; - IsPCRel = 1; - } else if (Modifier == MCSymbolRefExpr::VK_TLVP) { - report_fatal_error("TLVP symbol modifier should have been rip-rel"); - } else if (Modifier != MCSymbolRefExpr::VK_None) - report_fatal_error("unsupported symbol modifier in relocation"); - else - Type = macho::RIT_X86_64_Unsigned; - } - } - - // x86_64 always writes custom values into the fixups. - FixedValue = Value; - - // struct relocation_info (8 bytes) - macho::RelocationEntry MRE; - MRE.Word0 = FixupOffset; - MRE.Word1 = ((Index << 0) | - (IsPCRel << 24) | - (Log2Size << 25) | - (IsExtern << 27) | - (Type << 28)); - Writer->addRelocation(Fragment->getParent(), MRE); -} - -void X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - unsigned Log2Size, - uint64_t &FixedValue) { - uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); - unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind()); - unsigned Type = macho::RIT_Vanilla; - - // See . - const MCSymbol *A = &Target.getSymA()->getSymbol(); - MCSymbolData *A_SD = &Asm.getSymbolData(*A); - - if (!A_SD->getFragment()) - report_fatal_error("symbol '" + A->getName() + - "' can not be undefined in a subtraction expression"); - - uint32_t Value = Writer->getSymbolAddress(A_SD, Layout); - uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent()); - FixedValue += SecAddr; - uint32_t Value2 = 0; - - if (const MCSymbolRefExpr *B = Target.getSymB()) { - MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol()); - - if (!B_SD->getFragment()) - report_fatal_error("symbol '" + B->getSymbol().getName() + - "' can not be undefined in a subtraction expression"); - - // Select the appropriate difference relocation type. - // - // Note that there is no longer any semantic difference between these two - // relocation types from the linkers point of view, this is done solely for - // pedantic compatibility with 'as'. - Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference : - (unsigned)macho::RIT_Generic_LocalDifference; - Value2 = Writer->getSymbolAddress(B_SD, Layout); - FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent()); - } - - // Relocations are written out in reverse order, so the PAIR comes first. - if (Type == macho::RIT_Difference || - Type == macho::RIT_Generic_LocalDifference) { - macho::RelocationEntry MRE; - MRE.Word0 = ((0 << 0) | - (macho::RIT_Pair << 24) | - (Log2Size << 28) | - (IsPCRel << 30) | - macho::RF_Scattered); - MRE.Word1 = Value2; - Writer->addRelocation(Fragment->getParent(), MRE); - } - - macho::RelocationEntry MRE; - MRE.Word0 = ((FixupOffset << 0) | - (Type << 24) | - (Log2Size << 28) | - (IsPCRel << 30) | - macho::RF_Scattered); - MRE.Word1 = Value; - Writer->addRelocation(Fragment->getParent(), MRE); -} - -void X86MachObjectWriter::RecordTLVPRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue) { - assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP && - !is64Bit() && - "Should only be called with a 32-bit TLVP relocation!"); - - unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); - uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); - unsigned IsPCRel = 0; - - // Get the symbol data. - MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol()); - unsigned Index = SD_A->getIndex(); - - // We're only going to have a second symbol in pic mode and it'll be a - // subtraction from the picbase. For 32-bit pic the addend is the difference - // between the picbase and the next address. For 32-bit static the addend is - // zero. - if (Target.getSymB()) { - // If this is a subtraction then we're pcrel. - uint32_t FixupAddress = - Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset(); - MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol()); - IsPCRel = 1; - FixedValue = (FixupAddress - Writer->getSymbolAddress(SD_B, Layout) + - Target.getConstant()); - FixedValue += 1ULL << Log2Size; - } else { - FixedValue = 0; - } - - // struct relocation_info (8 bytes) - macho::RelocationEntry MRE; - MRE.Word0 = Value; - MRE.Word1 = ((Index << 0) | - (IsPCRel << 24) | - (Log2Size << 25) | - (1 << 27) | // Extern - (macho::RIT_Generic_TLV << 28)); // Type - Writer->addRelocation(Fragment->getParent(), MRE); -} - -void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer, - const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, - MCValue Target, - uint64_t &FixedValue) { - unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind()); - unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); - - // If this is a 32-bit TLVP reloc it's handled a bit differently. - if (Target.getSymA() && - Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) { - RecordTLVPRelocation(Writer, Asm, Layout, Fragment, Fixup, Target, - FixedValue); - return; - } - - // If this is a difference or a defined symbol plus an offset, then we need a - // scattered relocation entry. Differences always require scattered - // relocations. - if (Target.getSymB()) - return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup, - Target, Log2Size, FixedValue); - - // Get the symbol data, if any. - MCSymbolData *SD = 0; - if (Target.getSymA()) - SD = &Asm.getSymbolData(Target.getSymA()->getSymbol()); - - // If this is an internal relocation with an offset, it also needs a scattered - // relocation entry. - uint32_t Offset = Target.getConstant(); - if (IsPCRel) - Offset += 1 << Log2Size; - if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD)) - return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup, - Target, Log2Size, FixedValue); - - // See . - uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); - unsigned Index = 0; - unsigned IsExtern = 0; - unsigned Type = 0; - - if (Target.isAbsolute()) { // constant - // SymbolNum of 0 indicates the absolute section. - // - // FIXME: Currently, these are never generated (see code below). I cannot - // find a case where they are actually emitted. - Type = macho::RIT_Vanilla; - } else { - // Resolve constant variables. - if (SD->getSymbol().isVariable()) { - int64_t Res; - if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute( - Res, Layout, Writer->getSectionAddressMap())) { - FixedValue = Res; - return; - } - } - - // Check whether we need an external or internal relocation. - if (Writer->doesSymbolRequireExternRelocation(SD)) { - IsExtern = 1; - Index = SD->getIndex(); - // For external relocations, make sure to offset the fixup value to - // compensate for the addend of the symbol address, if it was - // undefined. This occurs with weak definitions, for example. - if (!SD->Symbol->isUndefined()) - FixedValue -= Layout.getSymbolOffset(SD); - } else { - // The index is the section ordinal (1-based). - const MCSectionData &SymSD = Asm.getSectionData( - SD->getSymbol().getSection()); - Index = SymSD.getOrdinal() + 1; - FixedValue += Writer->getSectionAddress(&SymSD); - } - if (IsPCRel) - FixedValue -= Writer->getSectionAddress(Fragment->getParent()); - - Type = macho::RIT_Vanilla; - } - - // struct relocation_info (8 bytes) - macho::RelocationEntry MRE; - MRE.Word0 = FixupOffset; - MRE.Word1 = ((Index << 0) | - (IsPCRel << 24) | - (Log2Size << 25) | - (IsExtern << 27) | - (Type << 28)); - Writer->addRelocation(Fragment->getParent(), MRE); -} - -MCObjectWriter *llvm::createX86MachObjectWriter(raw_ostream &OS, - bool Is64Bit, - uint32_t CPUType, - uint32_t CPUSubtype) { - return createMachObjectWriter(new X86MachObjectWriter(Is64Bit, - CPUType, - CPUSubtype), - OS, /*IsLittleEndian=*/true); -} Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=135939&r1=135938&r2=135939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Jul 25 14:33:48 2011 @@ -16,52 +16,15 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/MC/MCCodeEmitter.h" -#include "llvm/MC/MCStreamer.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) - return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll); - - if (TheTriple.isOSWindows()) - return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll); - - return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); -} - extern "C" void LLVMInitializeX86Target() { // Register the target. RegisterTargetMachine X(TheX86_32Target); RegisterTargetMachine Y(TheX86_64Target); - - // Register the code emitter. - TargetRegistry::RegisterCodeEmitter(TheX86_32Target, - createX86MCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(TheX86_64Target, - createX86MCCodeEmitter); - - // Register the asm backend. - TargetRegistry::RegisterAsmBackend(TheX86_32Target, - createX86_32AsmBackend); - TargetRegistry::RegisterAsmBackend(TheX86_64Target, - createX86_64AsmBackend); - - // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(TheX86_32Target, - createMCStreamer); - TargetRegistry::RegisterObjectStreamer(TheX86_64Target, - createMCStreamer); } From evan.cheng at apple.com Mon Jul 25 14:53:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 19:53:23 -0000 Subject: [llvm-commits] [llvm] r135942 - in /llvm/trunk/lib/Target/PowerPC: CMakeLists.txt MCTargetDesc/CMakeLists.txt MCTargetDesc/PPCAsmBackend.cpp MCTargetDesc/PPCFixupKinds.h MCTargetDesc/PPCMCCodeEmitter.cpp MCTargetDesc/PPCMCTargetDesc.cpp MCTargetDesc/PPCMCTargetDesc.h PPC.h PPCAsmBackend.cpp PPCCodeEmitter.cpp PPCFixupKinds.h PPCFrameLowering.cpp PPCInstrInfo.cpp PPCMCCodeEmitter.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h PPCTargetMachine.cpp Message-ID: <20110725195324.129102A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 14:53:23 2011 New Revision: 135942 URL: http://llvm.org/viewvc/llvm-project?rev=135942&view=rev Log: Refactor PPC target to separate MC routines from Target routines. Added: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp - copied, changed from r135928, llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h - copied unchanged from r135928, llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp - copied, changed from r135928, llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp Removed: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h llvm/trunk/lib/Target/PowerPC/PPC.h llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jul 25 14:53:23 2011 @@ -10,7 +10,6 @@ tablegen(PPCGenSubtargetInfo.inc -gen-subtarget) add_llvm_target(PowerPCCodeGen - PPCAsmBackend.cpp PPCAsmPrinter.cpp PPCBranchSelector.cpp PPCCodeEmitter.cpp @@ -20,7 +19,6 @@ PPCISelLowering.cpp PPCFrameLowering.cpp PPCJITInfo.cpp - PPCMCCodeEmitter.cpp PPCMCInstLower.cpp PPCPredicates.cpp PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Mon Jul 25 14:53:23 2011 @@ -1,4 +1,6 @@ add_llvm_library(LLVMPowerPCDesc + PPCAsmBackend.cpp PPCMCTargetDesc.cpp PPCMCAsmInfo.cpp + PPCMCCodeEmitter.cpp ) Copied: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (from r135928, llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?p2=llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp&p1=llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp&r1=135928&r2=135942&rev=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Jul 25 14:53:23 2011 @@ -8,8 +8,8 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/TargetAsmBackend.h" -#include "PPC.h" -#include "PPCFixupKinds.h" +#include "MCTargetDesc/PPCMCTargetDesc.h" +#include "MCTargetDesc/PPCFixupKinds.h" #include "llvm/MC/MCMachObjectWriter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCObjectWriter.h" Copied: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (from r135928, llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?p2=llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp&p1=llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp&r1=135928&r2=135942&rev=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Mon Jul 25 14:53:23 2011 @@ -12,9 +12,8 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mccodeemitter" -#include "PPC.h" -#include "PPCRegisterInfo.h" -#include "PPCFixupKinds.h" +#include "MCTargetDesc/PPCBaseInfo.h" +#include "MCTargetDesc/PPCFixupKinds.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInst.h" #include "llvm/ADT/Statistic.h" @@ -170,7 +169,7 @@ const MCOperand &MO = MI.getOperand(OpNo); assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); - return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg()); + return 0x80 >> getPPCRegisterNumbering(MO.getReg()); } @@ -182,7 +181,7 @@ // The GPR operand should come through here though. assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); - return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); + return getPPCRegisterNumbering(MO.getReg()); } assert(MO.isImm() && Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Mon Jul 25 14:53:23 2011 @@ -16,6 +16,7 @@ #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" @@ -87,6 +88,19 @@ return X; } +// This is duplicated code. Refactor this. +static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, + MCContext &Ctx, TargetAsmBackend &TAB, + raw_ostream &OS, + MCCodeEmitter *Emitter, + bool RelaxAll, + bool NoExecStack) { + if (Triple(TT).isOSDarwin()) + return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); + + return NULL; +} + extern "C" void LLVMInitializePowerPCTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo); @@ -109,4 +123,16 @@ createPPCMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target, createPPCMCSubtargetInfo); + + // Register the MC Code Emitter + TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); + TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); + + // Register the asm backend. + TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend); + TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend); + + // Register the object streamer. + TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer); + TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); } Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Mon Jul 25 14:53:23 2011 @@ -14,14 +14,26 @@ #ifndef PPCMCTARGETDESC_H #define PPCMCTARGETDESC_H +#include + namespace llvm { +class MCCodeEmitter; +class MCContext; +class MCInstrInfo; class MCSubtargetInfo; class Target; +class TargetAsmBackend; class StringRef; extern Target ThePPC32Target; extern Target ThePPC64Target; +MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, + MCContext &Ctx); + +TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &); + } // End llvm namespace // Defines symbolic names for PowerPC registers. This defines a mapping from Modified: llvm/trunk/lib/Target/PowerPC/PPC.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPC.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Jul 25 14:53:23 2011 @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_POWERPC_H #define LLVM_TARGET_POWERPC_H +#include "MCTargetDesc/PPCBaseInfo.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include @@ -41,11 +42,6 @@ FunctionPass *createPPCISelDag(PPCTargetMachine &TM); FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM, JITCodeEmitter &MCE); - MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx); - TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &); - void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP, bool isDarwin); Removed: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=135941&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (removed) @@ -1,123 +0,0 @@ -//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmBackend.h" -#include "PPC.h" -#include "PPCFixupKinds.h" -#include "llvm/MC/MCMachObjectWriter.h" -#include "llvm/MC/MCSectionMachO.h" -#include "llvm/MC/MCObjectWriter.h" -#include "llvm/MC/MCValue.h" -#include "llvm/Object/MachOFormat.h" -#include "llvm/Target/TargetRegistry.h" -using namespace llvm; - -namespace { -class PPCMachObjectWriter : public MCMachObjectTargetWriter { -public: - PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, - uint32_t CPUSubtype) - : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {} - - void RecordRelocation(MachObjectWriter *Writer, - const MCAssembler &Asm, const MCAsmLayout &Layout, - const MCFragment *Fragment, const MCFixup &Fixup, - MCValue Target, uint64_t &FixedValue) {} -}; - -class PPCAsmBackend : public TargetAsmBackend { -const Target &TheTarget; -public: - PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {} - - unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; } - - const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { - const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = { - // name offset bits flags - { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_ppc_lo16", 16, 16, 0 }, - { "fixup_ppc_ha16", 16, 16, 0 }, - { "fixup_ppc_lo14", 16, 14, 0 } - }; - - if (Kind < FirstTargetFixupKind) - return TargetAsmBackend::getFixupKindInfo(Kind); - - assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && - "Invalid kind!"); - return Infos[Kind - FirstTargetFixupKind]; - } - - bool MayNeedRelaxation(const MCInst &Inst) const { - // FIXME. - return false; - } - - void RelaxInstruction(const MCInst &Inst, MCInst &Res) const { - // FIXME. - assert(0 && "RelaxInstruction() unimplemented"); - } - - bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const { - // FIXME: Zero fill for now. That's not right, but at least will get the - // section size right. - for (uint64_t i = 0; i != Count; ++i) - OW->Write8(0); - return true; - } - - unsigned getPointerSize() const { - StringRef Name = TheTarget.getName(); - if (Name == "ppc64") return 8; - assert(Name == "ppc32" && "Unknown target name!"); - return 4; - } -}; -} // end anonymous namespace - - -// FIXME: This should be in a separate file. -namespace { - class DarwinPPCAsmBackend : public PPCAsmBackend { - public: - DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { } - - void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const { - assert(0 && "UNIMP"); - } - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - bool is64 = getPointerSize() == 8; - return createMachObjectWriter(new PPCMachObjectWriter( - /*Is64Bit=*/is64, - (is64 ? object::mach::CTM_PowerPC64 : - object::mach::CTM_PowerPC), - object::mach::CSPPC_ALL), - OS, /*IsLittleEndian=*/false); - } - - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { - return false; - } - }; -} // end anonymous namespace - - - - -TargetAsmBackend *llvm::createPPCAsmBackend(const Target &T, - const std::string &TT) { - if (Triple(TT).isOSDarwin()) - return new DarwinPPCAsmBackend(T); - - return 0; -} Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Jul 25 14:53:23 2011 @@ -140,7 +140,7 @@ const MachineOperand &MO = MI.getOperand(OpNo); assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); - return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg()); + return 0x80 >> getPPCRegisterNumbering(MO.getReg()); } MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO, @@ -250,7 +250,7 @@ // The GPR operand should come through here though. assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); - return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); + return getPPCRegisterNumbering(MO.getReg()); } assert(MO.isImm() && Removed: llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h?rev=135941&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFixupKinds.h (removed) @@ -1,45 +0,0 @@ -//===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_PPC_PPCFIXUPKINDS_H -#define LLVM_PPC_PPCFIXUPKINDS_H - -#include "llvm/MC/MCFixup.h" - -namespace llvm { -namespace PPC { -enum Fixups { - // fixup_ppc_br24 - 24-bit PC relative relocation for direct branches like 'b' - // and 'bl'. - fixup_ppc_br24 = FirstTargetFixupKind, - - /// fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional - /// branches. - fixup_ppc_brcond14, - - /// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs - /// like 'li'. - fixup_ppc_lo16, - - /// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs - /// like 'lis'. - fixup_ppc_ha16, - - /// fixup_ppc_lo14 - A 14-bit fixup corresponding to lo16(_foo) for instrs - /// like 'std'. - fixup_ppc_lo14, - - // Marker - LastTargetFixupKind, - NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind -}; -} -} - -#endif Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon Jul 25 14:53:23 2011 @@ -109,14 +109,14 @@ for (MachineRegisterInfo::livein_iterator I = MF->getRegInfo().livein_begin(), E = MF->getRegInfo().livein_end(); I != E; ++I) { - unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); + unsigned RegNo = getPPCRegisterNumbering(I->first); if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. } for (MachineRegisterInfo::liveout_iterator I = MF->getRegInfo().liveout_begin(), E = MF->getRegInfo().liveout_end(); I != E; ++I) { - unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); + unsigned RegNo = getPPCRegisterNumbering(*I); if (VRRegNo[RegNo] == *I) // If this really is a vector reg. UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. } @@ -878,7 +878,7 @@ FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); } - LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8; + LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; } // Check whether the frame pointer register is allocated. If so, make sure it @@ -912,8 +912,8 @@ } unsigned MinReg = - std::min(PPCRegisterInfo::getRegisterNumbering(MinGPR), - PPCRegisterInfo::getRegisterNumbering(MinG8R)); + std::min(getPPCRegisterNumbering(MinGPR), + getPPCRegisterNumbering(MinG8R)); if (Subtarget.isPPC64()) { LowerBound -= (31 - MinReg + 1) * 8; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Jul 25 14:53:23 2011 @@ -402,7 +402,7 @@ // If the saved register wasn't CR0, shift the bits left so that they are // in CR0's slot. if (SrcReg != PPC::CR0) { - unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; + unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; // rlwinm scratch, scratch, ShiftBits, 0, 31. NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) .addReg(ScratchReg).addImm(ShiftBits) @@ -537,7 +537,7 @@ // If the reloaded register isn't CR0, shift the bits right so that they are // in the right CR's slot. if (DestReg != PPC::CR0) { - unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; + unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) Removed: llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp?rev=135941&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (removed) @@ -1,194 +0,0 @@ -//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the PPCMCCodeEmitter class. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "mccodeemitter" -#include "PPC.h" -#include "PPCRegisterInfo.h" -#include "PPCFixupKinds.h" -#include "llvm/MC/MCCodeEmitter.h" -#include "llvm/MC/MCInst.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Support/ErrorHandling.h" -using namespace llvm; - -STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); - -namespace { -class PPCMCCodeEmitter : public MCCodeEmitter { - PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT - void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT - -public: - PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, - MCContext &ctx) { - } - - ~PPCMCCodeEmitter() {} - - unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; - - /// getMachineOpValue - Return binary encoding of operand. If the machine - /// operand requires relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, - SmallVectorImpl &Fixups) const; - - // getBinaryCodeForInstr - TableGen'erated function for getting the - // binary encoding for an instruction. - unsigned getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const { - unsigned Bits = getBinaryCodeForInstr(MI, Fixups); - - // Output the constant in big endian byte order. - for (unsigned i = 0; i != 4; ++i) { - OS << (char)(Bits >> 24); - Bits <<= 8; - } - - ++MCNumEmitted; // Keep track of the # of mi's emitted. - } - -}; - -} // end anonymous namespace - -MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new PPCMCCodeEmitter(MCII, STI, Ctx); -} - -unsigned PPCMCCodeEmitter:: -getDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_br24)); - return 0; -} - -unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_brcond14)); - return 0; -} - -unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_ha16)); - return 0; -} - -unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo16)); - return 0; -} - -unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - // Encode (imm, reg) as a memri, which has the low 16-bits as the - // displacement and the next 5 bits as the register #. - assert(MI.getOperand(OpNo+1).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; - - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isImm()) - return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; - - // Add a fixup for the displacement field. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo16)); - return RegBits; -} - - -unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - // Encode (imm, reg) as a memrix, which has the low 14-bits as the - // displacement and the next 5 bits as the register #. - assert(MI.getOperand(OpNo+1).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; - - const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isImm()) - return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits; - - // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_lo14)); - return RegBits; -} - - -unsigned PPCMCCodeEmitter:: -get_crbitm_encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpNo); - assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) && - (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); - return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg()); -} - - -unsigned PPCMCCodeEmitter:: -getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { - if (MO.isReg()) { - // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. - // The GPR operand should come through here though. - assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || - MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); - return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); - } - - assert(MO.isImm() && - "Relocation required in an instruction that we cannot encode!"); - return MO.getImm(); -} - - -#include "PPCGenMCCodeEmitter.inc" Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jul 25 14:53:23 2011 @@ -67,49 +67,6 @@ (EnablePPC64RS && Subtarget.isPPC64())); } -/// getRegisterNumbering - Given the enum value for some register, e.g. -/// PPC::F14, return the number that it corresponds to (e.g. 14). -unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { - using namespace PPC; - switch (RegEnum) { - case 0: return 0; - case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; - case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; - case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; - case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; - case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; - case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; - case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; - case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; - case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; - case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; - case R10: case X10: case F10: case V10: case CR2EQ: return 10; - case R11: case X11: case F11: case V11: case CR2UN: return 11; - case R12: case X12: case F12: case V12: case CR3LT: return 12; - case R13: case X13: case F13: case V13: case CR3GT: return 13; - case R14: case X14: case F14: case V14: case CR3EQ: return 14; - case R15: case X15: case F15: case V15: case CR3UN: return 15; - case R16: case X16: case F16: case V16: case CR4LT: return 16; - case R17: case X17: case F17: case V17: case CR4GT: return 17; - case R18: case X18: case F18: case V18: case CR4EQ: return 18; - case R19: case X19: case F19: case V19: case CR4UN: return 19; - case R20: case X20: case F20: case V20: case CR5LT: return 20; - case R21: case X21: case F21: case V21: case CR5GT: return 21; - case R22: case X22: case F22: case V22: case CR5EQ: return 22; - case R23: case X23: case F23: case V23: case CR5UN: return 23; - case R24: case X24: case F24: case V24: case CR6LT: return 24; - case R25: case X25: case F25: case V25: case CR6GT: return 25; - case R26: case X26: case F26: case V26: case CR6EQ: return 26; - case R27: case X27: case F27: case V27: case CR6UN: return 27; - case R28: case X28: case F28: case V28: case CR7LT: return 28; - case R29: case X29: case F29: case V29: case CR7GT: return 29; - case R30: case X30: case F30: case V30: case CR7EQ: return 30; - case R31: case X31: case F31: case V31: case CR7UN: return 31; - default: - llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); - } -} - PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, const TargetInstrInfo &tii) : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, @@ -521,7 +478,7 @@ // rlwinm rA, rA, ShiftBits, 0, 31. BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) .addReg(Reg, RegState::Kill) - .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) + .addImm(getPPCRegisterNumbering(SrcReg) * 4) .addImm(0) .addImm(31); Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon Jul 25 14:53:23 2011 @@ -33,10 +33,6 @@ public: PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii); - /// getRegisterNumbering - Given the enum value for some register, e.g. - /// PPC::F14, return the number that it corresponds to (e.g. 14). - static unsigned getRegisterNumbering(unsigned RegEnum); - /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const; Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=135942&r1=135941&r2=135942&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Jul 25 14:53:23 2011 @@ -20,36 +20,10 @@ #include "llvm/Support/FormattedStream.h" using namespace llvm; -// This is duplicated code. Refactor this. -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, - raw_ostream &OS, - MCCodeEmitter *Emitter, - bool RelaxAll, - bool NoExecStack) { - if (Triple(TT).isOSDarwin()) - return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); - - return NULL; -} - extern "C" void LLVMInitializePowerPCTarget() { // Register the targets RegisterTargetMachine A(ThePPC32Target); RegisterTargetMachine B(ThePPC64Target); - - // Register the MC Code Emitter - TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); - - - // Register the asm backend. - TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend); - TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend); - - // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer); - TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); } PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, From evan.cheng at apple.com Mon Jul 25 14:55:33 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 19:55:33 -0000 Subject: [llvm-commits] [llvm] r135943 - /llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h Message-ID: <20110725195533.540452A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 14:55:33 2011 New Revision: 135943 URL: http://llvm.org/viewvc/llvm-project?rev=135943&view=rev Log: Missed a file. Added: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h Added: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h?rev=135943&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h (added) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h Mon Jul 25 14:55:33 2011 @@ -0,0 +1,70 @@ +//===-- PPCBaseInfo.h - Top level definitions for PPC -------- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the PPC target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef PPCBASEINFO_H +#define PPCBASEINFO_H + +#include "PPCMCTargetDesc.h" +#include "llvm/Support/ErrorHandling.h" + +namespace llvm { + +/// getRegisterNumbering - Given the enum value for some register, e.g. +/// PPC::F14, return the number that it corresponds to (e.g. 14). +inline static unsigned getPPCRegisterNumbering(unsigned RegEnum) { + using namespace PPC; + switch (RegEnum) { + case 0: return 0; + case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; + case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; + case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; + case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; + case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; + case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; + case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; + case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; + case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; + case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; + case R10: case X10: case F10: case V10: case CR2EQ: return 10; + case R11: case X11: case F11: case V11: case CR2UN: return 11; + case R12: case X12: case F12: case V12: case CR3LT: return 12; + case R13: case X13: case F13: case V13: case CR3GT: return 13; + case R14: case X14: case F14: case V14: case CR3EQ: return 14; + case R15: case X15: case F15: case V15: case CR3UN: return 15; + case R16: case X16: case F16: case V16: case CR4LT: return 16; + case R17: case X17: case F17: case V17: case CR4GT: return 17; + case R18: case X18: case F18: case V18: case CR4EQ: return 18; + case R19: case X19: case F19: case V19: case CR4UN: return 19; + case R20: case X20: case F20: case V20: case CR5LT: return 20; + case R21: case X21: case F21: case V21: case CR5GT: return 21; + case R22: case X22: case F22: case V22: case CR5EQ: return 22; + case R23: case X23: case F23: case V23: case CR5UN: return 23; + case R24: case X24: case F24: case V24: case CR6LT: return 24; + case R25: case X25: case F25: case V25: case CR6GT: return 25; + case R26: case X26: case F26: case V26: case CR6EQ: return 26; + case R27: case X27: case F27: case V27: case CR6UN: return 27; + case R28: case X28: case F28: case V28: case CR7LT: return 28; + case R29: case X29: case F29: case V29: case CR7GT: return 29; + case R30: case X30: case F30: case V30: case CR7EQ: return 30; + case R31: case X31: case F31: case V31: case CR7UN: return 31; + default: + llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); + } +} + +} // end namespace llvm; + +#endif From grosbach at apple.com Mon Jul 25 15:00:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 20:00:33 -0000 Subject: [llvm-commits] [llvm] r135945 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110725200033.1F5662A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 15:00:32 2011 New Revision: 135945 URL: http://llvm.org/viewvc/llvm-project?rev=135945&view=rev Log: Tidy up a bit. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135945&r1=135944&r2=135945&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 15:00:32 2011 @@ -419,15 +419,8 @@ let ParserMatchClass = ShifterAsmOperand; } -def ShiftedRegAsmOperand : AsmOperandClass { - let Name = "ShiftedReg"; -} - -def ShiftedImmAsmOperand : AsmOperandClass { - let Name = "ShiftedImm"; -} - // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. +def ShiftedRegAsmOperand : AsmOperandClass { let Name = "ShiftedReg"; } def so_reg_reg : Operand, // reg reg imm ComplexPattern { @@ -437,6 +430,7 @@ let MIOperandInfo = (ops GPR, GPR, shift_imm); } +def ShiftedImmAsmOperand : AsmOperandClass { let Name = "ShiftedImm"; } def so_reg_imm : Operand, // reg imm ComplexPattern { From grosbach at apple.com Mon Jul 25 15:06:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 20:06:30 -0000 Subject: [llvm-commits] [llvm] r135946 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110725200630.9F1782A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 15:06:30 2011 New Revision: 135946 URL: http://llvm.org/viewvc/llvm-project?rev=135946&view=rev Log: Tidy up formatting. Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135946&r1=135945&r2=135946&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 15:06:30 2011 @@ -347,33 +347,21 @@ // A list of registers separated by comma. Used by load/store multiple. -def RegListAsmOperand : AsmOperandClass { - let Name = "RegList"; - let SuperClasses = []; -} - -def DPRRegListAsmOperand : AsmOperandClass { - let Name = "DPRRegList"; - let SuperClasses = []; -} - -def SPRRegListAsmOperand : AsmOperandClass { - let Name = "SPRRegList"; - let SuperClasses = []; -} - +def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } def reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = RegListAsmOperand; let PrintMethod = "printRegisterList"; } +def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } def dpr_reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = DPRRegListAsmOperand; let PrintMethod = "printRegisterList"; } +def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } def spr_reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = SPRRegListAsmOperand; @@ -406,14 +394,11 @@ let EncoderMethod = "getRotImmOpValue"; } -def ShifterAsmOperand : AsmOperandClass { - let Name = "Shifter"; - let SuperClasses = []; -} // shift_imm: An integer that encodes a shift amount and the type of shift // (currently either asr or lsl) using the same encoding used for the // immediates in so_reg operands. +def ShifterAsmOperand : AsmOperandClass { let Name = "Shifter"; } def shift_imm : Operand { let PrintMethod = "printShiftImmOperand"; let ParserMatchClass = ShifterAsmOperand; @@ -558,19 +543,6 @@ } // Define ARM specific addressing modes. - -def MemMode2AsmOperand : AsmOperandClass { - let Name = "MemMode2"; - let SuperClasses = []; - let ParserMethod = "tryParseMemMode2Operand"; -} - -def MemMode3AsmOperand : AsmOperandClass { - let Name = "MemMode3"; - let SuperClasses = []; - let ParserMethod = "tryParseMemMode3Operand"; -} - // addrmode_imm12 := reg +/- imm12 // def addrmode_imm12 : Operand, @@ -596,6 +568,10 @@ // addrmode2 := reg +/- imm12 // := reg +/- reg shop imm // +def MemMode2AsmOperand : AsmOperandClass { + let Name = "MemMode2"; + let ParserMethod = "tryParseMemMode2Operand"; +} def addrmode2 : Operand, ComplexPattern { let EncoderMethod = "getAddrMode2OpValue"; @@ -615,6 +591,10 @@ // addrmode3 := reg +/- reg // addrmode3 := reg +/- imm8 // +def MemMode3AsmOperand : AsmOperandClass { + let Name = "MemMode3"; + let ParserMethod = "tryParseMemMode3Operand"; +} def addrmode3 : Operand, ComplexPattern { let EncoderMethod = "getAddrMode3OpValue"; @@ -638,13 +618,9 @@ let PrintMethod = "printLdStmModeOperand"; } -def MemMode5AsmOperand : AsmOperandClass { - let Name = "MemMode5"; - let SuperClasses = []; -} - // addrmode5 := reg +/- imm8*4 // +def MemMode5AsmOperand : AsmOperandClass { let Name = "MemMode5"; } def addrmode5 : Operand, ComplexPattern { let PrintMethod = "printAddrMode5Operand"; @@ -696,15 +672,11 @@ let MIOperandInfo = (ops GPR, i32imm); } -def MemMode7AsmOperand : AsmOperandClass { - let Name = "MemMode7"; - let SuperClasses = []; -} - // addrmode7 := reg // Used by load/store exclusive instructions. Useful to enable right assembly // parsing and printing. Not used for any codegen matching. // +def MemMode7AsmOperand : AsmOperandClass { let Name = "MemMode7"; } def addrmode7 : Operand { let PrintMethod = "printAddrMode7Operand"; let MIOperandInfo = (ops GPR); @@ -717,21 +689,17 @@ def CoprocNumAsmOperand : AsmOperandClass { let Name = "CoprocNum"; - let SuperClasses = []; let ParserMethod = "tryParseCoprocNumOperand"; } - -def CoprocRegAsmOperand : AsmOperandClass { - let Name = "CoprocReg"; - let SuperClasses = []; - let ParserMethod = "tryParseCoprocRegOperand"; -} - def p_imm : Operand { let PrintMethod = "printPImmediate"; let ParserMatchClass = CoprocNumAsmOperand; } +def CoprocRegAsmOperand : AsmOperandClass { + let Name = "CoprocReg"; + let ParserMethod = "tryParseCoprocRegOperand"; +} def c_imm : Operand { let PrintMethod = "printCImmediate"; let ParserMatchClass = CoprocRegAsmOperand; From jstaszak at apple.com Mon Jul 25 15:08:00 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 25 Jul 2011 20:08:00 -0000 Subject: [llvm-commits] [llvm] r135947 - /llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Message-ID: <20110725200800.B2F572A6C12C@llvm.org> Author: kuba Date: Mon Jul 25 15:08:00 2011 New Revision: 135947 URL: http://llvm.org/viewvc/llvm-project?rev=135947&view=rev Log: Fix #include guard directive. Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?rev=135947&r1=135946&r2=135947&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Mon Jul 25 15:08:00 2011 @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H -#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H +#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H +#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H #include "llvm/CodeGen/MachineFunctionPass.h" #include From jstaszak at apple.com Mon Jul 25 15:08:58 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 25 Jul 2011 20:08:58 -0000 Subject: [llvm-commits] [llvm] r135948 - /llvm/trunk/include/llvm/Support/BranchProbability.h Message-ID: <20110725200858.498212A6C12C@llvm.org> Author: kuba Date: Mon Jul 25 15:08:58 2011 New Revision: 135948 URL: http://llvm.org/viewvc/llvm-project?rev=135948&view=rev Log: Fix class description. Modified: llvm/trunk/include/llvm/Support/BranchProbability.h Modified: llvm/trunk/include/llvm/Support/BranchProbability.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=135948&r1=135947&r2=135948&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/BranchProbability.h (original) +++ llvm/trunk/include/llvm/Support/BranchProbability.h Mon Jul 25 15:08:58 2011 @@ -1,4 +1,4 @@ -//===- BranchProbability.h - Branch Probability Analysis --------*- C++ -*-===// +//===- BranchProbability.h - Branch Probability Wrapper ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -34,7 +34,7 @@ uint32_t getNumerator() const { return N; } uint32_t getDenominator() const { return D; } - + // Return (1 - Probability). BranchProbability getCompl() { return BranchProbability(D - N, D); From ofv at wanadoo.es Mon Jul 25 15:13:36 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 25 Jul 2011 20:13:36 -0000 Subject: [llvm-commits] [llvm] r135949 - /llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Message-ID: <20110725201337.08CFB2A6C12C@llvm.org> Author: ofv Date: Mon Jul 25 15:13:36 2011 New Revision: 135949 URL: http://llvm.org/viewvc/llvm-project?rev=135949&view=rev Log: Unbreak the build. Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=135949&r1=135948&r2=135949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Mon Jul 25 15:13:36 2011 @@ -14,6 +14,7 @@ #ifndef X86MCTARGETDESC_H #define X86MCTARGETDESC_H +#include "llvm/Support/DataTypes.h" #include namespace llvm { From grosbach at apple.com Mon Jul 25 15:14:50 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 20:14:50 -0000 Subject: [llvm-commits] [llvm] r135950 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td AsmParser/ARMAsmParser.cpp Message-ID: <20110725201450.D86692A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 15:14:50 2011 New Revision: 135950 URL: http://llvm.org/viewvc/llvm-project?rev=135950&view=rev Log: Make assembly parser method names more consistent. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135950&r1=135949&r2=135950&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Jul 25 15:14:50 2011 @@ -144,19 +144,19 @@ def MemBarrierOptOperand : AsmOperandClass { let Name = "MemBarrierOpt"; let SuperClasses = []; - let ParserMethod = "tryParseMemBarrierOptOperand"; + let ParserMethod = "parseMemBarrierOptOperand"; } def ProcIFlagsOperand : AsmOperandClass { let Name = "ProcIFlags"; let SuperClasses = []; - let ParserMethod = "tryParseProcIFlagsOperand"; + let ParserMethod = "parseProcIFlagsOperand"; } def MSRMaskOperand : AsmOperandClass { let Name = "MSRMask"; let SuperClasses = []; - let ParserMethod = "tryParseMSRMaskOperand"; + let ParserMethod = "parseMSRMaskOperand"; } // ARM imod and iflag operands, used only by the CPS instruction. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135950&r1=135949&r2=135950&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 15:14:50 2011 @@ -570,7 +570,7 @@ // def MemMode2AsmOperand : AsmOperandClass { let Name = "MemMode2"; - let ParserMethod = "tryParseMemMode2Operand"; + let ParserMethod = "parseMemMode2Operand"; } def addrmode2 : Operand, ComplexPattern { @@ -593,7 +593,7 @@ // def MemMode3AsmOperand : AsmOperandClass { let Name = "MemMode3"; - let ParserMethod = "tryParseMemMode3Operand"; + let ParserMethod = "parseMemMode3Operand"; } def addrmode3 : Operand, ComplexPattern { @@ -689,7 +689,7 @@ def CoprocNumAsmOperand : AsmOperandClass { let Name = "CoprocNum"; - let ParserMethod = "tryParseCoprocNumOperand"; + let ParserMethod = "parseCoprocNumOperand"; } def p_imm : Operand { let PrintMethod = "printPImmediate"; @@ -698,7 +698,7 @@ def CoprocRegAsmOperand : AsmOperandClass { let Name = "CoprocReg"; - let ParserMethod = "tryParseCoprocRegOperand"; + let ParserMethod = "parseCoprocRegOperand"; } def c_imm : Operand { let PrintMethod = "printCImmediate"; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135950&r1=135949&r2=135950&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 15:14:50 2011 @@ -104,19 +104,19 @@ /// } - OperandMatchResultTy tryParseCoprocNumOperand( + OperandMatchResultTy parseCoprocNumOperand( SmallVectorImpl&); - OperandMatchResultTy tryParseCoprocRegOperand( + OperandMatchResultTy parseCoprocRegOperand( SmallVectorImpl&); - OperandMatchResultTy tryParseMemBarrierOptOperand( + OperandMatchResultTy parseMemBarrierOptOperand( SmallVectorImpl&); - OperandMatchResultTy tryParseProcIFlagsOperand( + OperandMatchResultTy parseProcIFlagsOperand( SmallVectorImpl&); - OperandMatchResultTy tryParseMSRMaskOperand( + OperandMatchResultTy parseMSRMaskOperand( SmallVectorImpl&); - OperandMatchResultTy tryParseMemMode2Operand( + OperandMatchResultTy parseMemMode2Operand( SmallVectorImpl&); - OperandMatchResultTy tryParseMemMode3Operand( + OperandMatchResultTy parseMemMode3Operand( SmallVectorImpl&); OperandMatchResultTy parsePKHImm(SmallVectorImpl &O, StringRef Op, int Low, int High); @@ -1360,11 +1360,11 @@ return -1; } -/// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The +/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseCoprocNumOperand(SmallVectorImpl &Operands) { +parseCoprocNumOperand(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1378,11 +1378,11 @@ return MatchOperand_Success; } -/// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The +/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseCoprocRegOperand(SmallVectorImpl &Operands) { +parseCoprocRegOperand(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1480,9 +1480,9 @@ return false; } -/// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. +/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseMemBarrierOptOperand(SmallVectorImpl &Operands) { +parseMemBarrierOptOperand(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1511,9 +1511,9 @@ return MatchOperand_Success; } -/// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction. +/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseProcIFlagsOperand(SmallVectorImpl &Operands) { +parseProcIFlagsOperand(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1540,9 +1540,9 @@ return MatchOperand_Success; } -/// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction. +/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseMSRMaskOperand(SmallVectorImpl &Operands) { +parseMSRMaskOperand(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1606,9 +1606,9 @@ return MatchOperand_Success; } -/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand. +/// parseMemMode2Operand - Try to parse memory addressing mode 2 operand. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseMemMode2Operand(SmallVectorImpl &Operands) { +parseMemMode2Operand(SmallVectorImpl &Operands) { assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); if (ParseMemory(Operands, ARMII::AddrMode2)) @@ -1617,9 +1617,9 @@ return MatchOperand_Success; } -/// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand. +/// parseMemMode3Operand - Try to parse memory addressing mode 3 operand. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: -tryParseMemMode3Operand(SmallVectorImpl &Operands) { +parseMemMode3Operand(SmallVectorImpl &Operands) { assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); if (ParseMemory(Operands, ARMII::AddrMode3)) From isanbard at gmail.com Mon Jul 25 15:15:15 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 20:15:15 -0000 Subject: [llvm-commits] [llvm] r135951 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110725201515.AB5B82A6C12C@llvm.org> Author: void Date: Mon Jul 25 15:15:15 2011 New Revision: 135951 URL: http://llvm.org/viewvc/llvm-project?rev=135951&view=rev Log: Update the comment. This feature is available only on Darwin at the moment. Though it's not Darwin-specific. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=135951&r1=135950&r2=135951&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Jul 25 15:15:15 2011 @@ -34,7 +34,8 @@ // FIXME: completely move here. extern cl::opt ForceStackAlign; -// FIXME: Remove once linker support is available. +// FIXME: Remove once linker support is available. The feature exists only on +// Darwin at the moment. static cl::opt GenerateCompactUnwind("gen-compact-unwind", cl::desc("Generate compact unwind encoding"), From ofv at wanadoo.es Mon Jul 25 15:17:01 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 25 Jul 2011 20:17:01 -0000 Subject: [llvm-commits] [llvm] r135952 - /llvm/trunk/cmake/modules/AddLLVM.cmake Message-ID: <20110725201701.B86F52A6C12C@llvm.org> Author: ofv Date: Mon Jul 25 15:17:01 2011 New Revision: 135952 URL: http://llvm.org/viewvc/llvm-project?rev=135952&view=rev Log: While building a LLVM target, put the current source directory on the header search path. Modified: llvm/trunk/cmake/modules/AddLLVM.cmake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=135952&r1=135951&r2=135952&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Mon Jul 25 15:17:01 2011 @@ -128,7 +128,9 @@ macro(add_llvm_target target_name) - include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}) + include_directories(BEFORE + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}) add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT}) set( CURRENT_LLVM_TARGET LLVM${target_name} ) endmacro(add_llvm_target) From evan.cheng at apple.com Mon Jul 25 15:18:18 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 20:18:18 -0000 Subject: [llvm-commits] [llvm] r135953 - in /llvm/trunk/lib/Target/MBlaze: AsmParser/MBlazeAsmParser.cpp CMakeLists.txt MBlaze.h MBlazeAsmBackend.cpp MBlazeAsmPrinter.cpp MBlazeISelLowering.cpp MBlazeInstrInfo.h MBlazeMCCodeEmitter.cpp MBlazeRegisterInfo.cpp MBlazeRegisterInfo.h MBlazeTargetMachine.cpp MCTargetDesc/CMakeLists.txt MCTargetDesc/MBlazeAsmBackend.cpp MCTargetDesc/MBlazeBaseInfo.h MCTargetDesc/MBlazeMCCodeEmitter.cpp MCTargetDesc/MBlazeMCTargetDesc.cpp MCTargetDesc/MBlazeMCTargetDesc.h Message-ID: <20110725201818.B2CBA2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 15:18:18 2011 New Revision: 135953 URL: http://llvm.org/viewvc/llvm-project?rev=135953&view=rev Log: Refactor MBlaze target to separate MC routines from Target routines. Added: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp - copied, changed from r135928, llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp - copied, changed from r135928, llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Removed: llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MBlaze.h llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Mon Jul 25 15:18:18 2011 @@ -286,19 +286,19 @@ break; case Register: OS << ""; + OS << getMBlazeRegisterNumbering(getReg()) << ">"; break; case Token: OS << "'" << getToken() << "'"; break; case Memory: { OS << ""; Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jul 25 15:18:18 2011 @@ -24,10 +24,8 @@ MBlazeIntrinsicInfo.cpp MBlazeSelectionDAGInfo.cpp MBlazeAsmPrinter.cpp - MBlazeAsmBackend.cpp MBlazeMCInstLower.cpp MBlazeELFWriterInfo.cpp - MBlazeMCCodeEmitter.cpp ) add_subdirectory(AsmParser) Modified: llvm/trunk/lib/Target/MBlaze/MBlaze.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlaze.h?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlaze.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlaze.h Mon Jul 25 15:18:18 2011 @@ -15,6 +15,7 @@ #ifndef TARGET_MBLAZE_H #define TARGET_MBLAZE_H +#include "MCTargetDesc/MBlazeBaseInfo.h" #include "MCTargetDesc/MBlazeMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" @@ -22,17 +23,6 @@ class MBlazeTargetMachine; class FunctionPass; class MachineCodeEmitter; - class MCCodeEmitter; - class MCInstrInfo; - class MCSubtargetInfo; - class TargetAsmBackend; - class formatted_raw_ostream; - - MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx); - - TargetAsmBackend *createMBlazeAsmBackend(const Target &, const std::string &); FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM); FunctionPass *createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &TM); Removed: llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp?rev=135952&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (removed) @@ -1,161 +0,0 @@ -//===-- MBlazeAsmBackend.cpp - MBlaze Assembler Backend -------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmBackend.h" -#include "MBlaze.h" -#include "MBlazeELFWriterInfo.h" -#include "llvm/ADT/Twine.h" -#include "llvm/MC/MCAssembler.h" -#include "llvm/MC/MCAsmLayout.h" -#include "llvm/MC/MCELFObjectWriter.h" -#include "llvm/MC/MCELFSymbolFlags.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCObjectWriter.h" -#include "llvm/MC/MCSectionELF.h" -#include "llvm/MC/MCSectionMachO.h" -#include "llvm/MC/MCValue.h" -#include "llvm/Support/ELF.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetRegistry.h" -using namespace llvm; - -static unsigned getFixupKindSize(unsigned Kind) { - switch (Kind) { - default: assert(0 && "invalid fixup kind!"); - case FK_Data_1: return 1; - case FK_PCRel_2: - case FK_Data_2: return 2; - case FK_PCRel_4: - case FK_Data_4: return 4; - case FK_Data_8: return 8; - } -} - - -namespace { -class MBlazeELFObjectWriter : public MCELFObjectTargetWriter { -public: - MBlazeELFObjectWriter(Triple::OSType OSType) - : MCELFObjectTargetWriter(/*is64Bit*/ false, OSType, ELF::EM_MBLAZE, - /*HasRelocationAddend*/ true) {} -}; - -class MBlazeAsmBackend : public TargetAsmBackend { -public: - MBlazeAsmBackend(const Target &T) - : TargetAsmBackend() { - } - - unsigned getNumFixupKinds() const { - return 2; - } - - bool MayNeedRelaxation(const MCInst &Inst) const; - - void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; - - bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; - - unsigned getPointerSize() const { - return 4; - } -}; - -static unsigned getRelaxedOpcode(unsigned Op) { - switch (Op) { - default: return Op; - case MBlaze::ADDIK: return MBlaze::ADDIK32; - case MBlaze::ORI: return MBlaze::ORI32; - case MBlaze::BRLID: return MBlaze::BRLID32; - } -} - -bool MBlazeAsmBackend::MayNeedRelaxation(const MCInst &Inst) const { - if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode()) - return false; - - bool hasExprOrImm = false; - for (unsigned i = 0; i < Inst.getNumOperands(); ++i) - hasExprOrImm |= Inst.getOperand(i).isExpr(); - - return hasExprOrImm; -} - -void MBlazeAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { - Res = Inst; - Res.setOpcode(getRelaxedOpcode(Inst.getOpcode())); -} - -bool MBlazeAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { - if ((Count % 4) != 0) - return false; - - for (uint64_t i = 0; i < Count; i += 4) - OW->Write32(0x00000000); - - return true; -} -} // end anonymous namespace - -namespace { -class ELFMBlazeAsmBackend : public MBlazeAsmBackend { -public: - Triple::OSType OSType; - ELFMBlazeAsmBackend(const Target &T, Triple::OSType _OSType) - : MBlazeAsmBackend(T), OSType(_OSType) { } - - void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const; - - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createELFObjectWriter(new MBlazeELFObjectWriter(OSType), OS, - /*IsLittleEndian*/ false); - } -}; - -void ELFMBlazeAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, - unsigned DataSize, uint64_t Value) const { - unsigned Size = getFixupKindSize(Fixup.getKind()); - - assert(Fixup.getOffset() + Size <= DataSize && - "Invalid fixup offset!"); - - char *data = Data + Fixup.getOffset(); - switch (Size) { - default: llvm_unreachable("Cannot fixup unknown value."); - case 1: llvm_unreachable("Cannot fixup 1 byte value."); - case 8: llvm_unreachable("Cannot fixup 8 byte value."); - - case 4: - *(data+7) = uint8_t(Value); - *(data+6) = uint8_t(Value >> 8); - *(data+3) = uint8_t(Value >> 16); - *(data+2) = uint8_t(Value >> 24); - break; - - case 2: - *(data+3) = uint8_t(Value >> 0); - *(data+2) = uint8_t(Value >> 8); - } -} -} // end anonymous namespace - -TargetAsmBackend *llvm::createMBlazeAsmBackend(const Target &T, - const std::string &TT) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin()) - assert(0 && "Mac not supported on MBlaze"); - - if (TheTriple.isOSWindows()) - assert(0 && "Windows not supported on MBlaze"); - - return new ELFMBlazeAsmBackend(T, TheTriple.getOS()); -} Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Jul 25 15:18:18 2011 @@ -136,19 +136,17 @@ const std::vector &CSI = MFI->getCalleeSavedInfo(); for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(Reg); + unsigned RegNum = getMBlazeRegisterNumbering(Reg); if (MBlaze::GPRRegisterClass->contains(Reg)) CPUBitmask |= (1 << RegNum); } // Return Address and Frame registers must also be set in CPUBitmask. if (TFI->hasFP(*MF)) - CPUBitmask |= (1 << MBlazeRegisterInfo:: - getRegisterNumbering(RI.getFrameRegister(*MF))); + CPUBitmask |= (1 << getMBlazeRegisterNumbering(RI.getFrameRegister(*MF))); if (MFI->adjustsStack()) - CPUBitmask |= (1 << MBlazeRegisterInfo:: - getRegisterNumbering(RI.getRARegister())); + CPUBitmask |= (1 << getMBlazeRegisterNumbering(RI.getRARegister())); // Print CPUBitmask OutStreamer.EmitRawText("\t.mask\t0x" + Twine::utohexstr(CPUBitmask)); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Mon Jul 25 15:18:18 2011 @@ -964,9 +964,9 @@ // The last register argument that must be saved is MBlaze::R10 TargetRegisterClass *RC = MBlaze::GPRRegisterClass; - unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5); - unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1); - unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10); + unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5); + unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1); + unsigned End = getMBlazeRegisterNumbering(MBlaze::R10); unsigned StackLoc = Start - Begin + 1; for (; Start <= End; ++Start, ++StackLoc) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Mon Jul 25 15:18:18 2011 @@ -166,62 +166,6 @@ } } -/// MBlazeII - This namespace holds all of the target specific flags that -/// instruction info tracks. -/// -namespace MBlazeII { - enum { - // PseudoFrm - This represents an instruction that is a pseudo instruction - // or one that has not been implemented yet. It is illegal to code generate - // it, but tolerated for intermediate implementation stages. - FPseudo = 0, - FRRR, - FRRI, - FCRR, - FCRI, - FRCR, - FRCI, - FCCR, - FCCI, - FRRCI, - FRRC, - FRCX, - FRCS, - FCRCS, - FCRCX, - FCX, - FCR, - FRIR, - FRRRR, - FRI, - FC, - FormMask = 63 - - //===------------------------------------------------------------------===// - // MBlaze Specific MachineOperand flags. - // MO_NO_FLAG, - - /// MO_GOT - Represents the offset into the global offset table at which - /// the address the relocation entry symbol resides during execution. - // MO_GOT, - - /// MO_GOT_CALL - Represents the offset into the global offset table at - /// which the address of a call site relocation entry symbol resides - /// during execution. This is different from the above since this flag - /// can only be present in call instructions. - // MO_GOT_CALL, - - /// MO_GPREL - Represents the offset from the current gp value to be used - /// for the relocatable object file being produced. - // MO_GPREL, - - /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol - /// address. - // MO_ABS_HILO - - }; -} - class MBlazeInstrInfo : public MBlazeGenInstrInfo { MBlazeTargetMachine &TM; const MBlazeRegisterInfo RI; Removed: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=135952&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (removed) @@ -1,222 +0,0 @@ -//===-- MBlazeMCCodeEmitter.cpp - Convert MBlaze code to machine code -----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the MBlazeMCCodeEmitter class. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "mccodeemitter" -#include "MBlaze.h" -#include "MBlazeInstrInfo.h" -#include "llvm/MC/MCCodeEmitter.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCFixup.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); - -namespace { -class MBlazeMCCodeEmitter : public MCCodeEmitter { - MBlazeMCCodeEmitter(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT - void operator=(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT - const MCInstrInfo &MCII; - -public: - MBlazeMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, - MCContext &ctx) - : MCII(mcii) { - } - - ~MBlazeMCCodeEmitter() {} - - // getBinaryCodeForInstr - TableGen'erated function for getting the - // binary encoding for an instruction. - unsigned getBinaryCodeForInstr(const MCInst &MI) const; - - /// getMachineOpValue - Return binary encoding of operand. If the machine - /// operand requires relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; - unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { - return getMachineOpValue(MI, MI.getOperand(OpIdx)); - } - - static unsigned GetMBlazeRegNum(const MCOperand &MO) { - // FIXME: getMBlazeRegisterNumbering() is sufficient? - assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented."); - return 0; - } - - void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { - // The MicroBlaze uses a bit reversed format so we need to reverse the - // order of the bits. Taken from: - // http://graphics.stanford.edu/~seander/bithacks.html - C = ((C * 0x80200802ULL) & 0x0884422110ULL) * 0x0101010101ULL >> 32; - - OS << (char)C; - ++CurByte; - } - - void EmitRawByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { - OS << (char)C; - ++CurByte; - } - - void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, - raw_ostream &OS) const { - assert(Size <= 8 && "size too big in emit constant"); - - for (unsigned i = 0; i != Size; ++i) { - EmitByte(Val & 255, CurByte, OS); - Val >>= 8; - } - } - - void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const; - void EmitIMM(const MCInst &MI, unsigned &CurByte, raw_ostream &OS) const; - - void EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel, - unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups) const; - - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const; -}; - -} // end anonymous namespace - - -MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new MBlazeMCCodeEmitter(MCII, STI, Ctx); -} - -/// getMachineOpValue - Return binary encoding of operand. If the machine -/// operand requires relocation, record the relocation and return zero. -unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI, - const MCOperand &MO) const { - if (MO.isReg()) - return MBlazeRegisterInfo::getRegisterNumbering(MO.getReg()); - else if (MO.isImm()) - return static_cast(MO.getImm()); - else if (MO.isExpr()) - return 0; // The relocation has already been recorded at this point. - else { -#ifndef NDEBUG - errs() << MO; -#endif - llvm_unreachable(0); - } - return 0; -} - -void MBlazeMCCodeEmitter:: -EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const { - int32_t val = (int32_t)imm.getImm(); - if (val > 32767 || val < -32768) { - EmitByte(0x0D, CurByte, OS); - EmitByte(0x00, CurByte, OS); - EmitRawByte((val >> 24) & 0xFF, CurByte, OS); - EmitRawByte((val >> 16) & 0xFF, CurByte, OS); - } -} - -void MBlazeMCCodeEmitter:: -EmitIMM(const MCInst &MI, unsigned &CurByte,raw_ostream &OS) const { - switch (MI.getOpcode()) { - default: break; - - case MBlaze::ADDIK32: - case MBlaze::ORI32: - case MBlaze::BRLID32: - EmitByte(0x0D, CurByte, OS); - EmitByte(0x00, CurByte, OS); - EmitRawByte(0, CurByte, OS); - EmitRawByte(0, CurByte, OS); - } -} - -void MBlazeMCCodeEmitter:: -EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel, unsigned &CurByte, - raw_ostream &OS, SmallVectorImpl &Fixups) const { - assert(MI.getNumOperands()>opNo && "Not enought operands for instruction"); - - MCOperand oper = MI.getOperand(opNo); - - if (oper.isImm()) { - EmitIMM(oper, CurByte, OS); - } else if (oper.isExpr()) { - MCFixupKind FixupKind; - switch (MI.getOpcode()) { - default: - FixupKind = pcrel ? FK_PCRel_2 : FK_Data_2; - Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind)); - break; - case MBlaze::ORI32: - case MBlaze::ADDIK32: - case MBlaze::BRLID32: - FixupKind = pcrel ? FK_PCRel_4 : FK_Data_4; - Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind)); - break; - } - } -} - - - -void MBlazeMCCodeEmitter:: -EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const { - unsigned Opcode = MI.getOpcode(); - const MCInstrDesc &Desc = MCII.get(Opcode); - uint64_t TSFlags = Desc.TSFlags; - // Keep track of the current byte being emitted. - unsigned CurByte = 0; - - // Emit an IMM instruction if the instruction we are encoding requires it - EmitIMM(MI,CurByte,OS); - - switch ((TSFlags & MBlazeII::FormMask)) { - default: break; - case MBlazeII::FPseudo: - // Pseudo instructions don't get encoded. - return; - case MBlazeII::FRRI: - EmitImmediate(MI, 2, false, CurByte, OS, Fixups); - break; - case MBlazeII::FRIR: - EmitImmediate(MI, 1, false, CurByte, OS, Fixups); - break; - case MBlazeII::FCRI: - EmitImmediate(MI, 1, true, CurByte, OS, Fixups); - break; - case MBlazeII::FRCI: - EmitImmediate(MI, 1, true, CurByte, OS, Fixups); - case MBlazeII::FCCI: - EmitImmediate(MI, 0, true, CurByte, OS, Fixups); - break; - } - - ++MCNumEmitted; // Keep track of the # of mi's emitted - unsigned Value = getBinaryCodeForInstr(MI); - EmitConstant(Value, 4, CurByte, OS); -} - -// FIXME: These #defines shouldn't be necessary. Instead, tblgen should -// be able to generate code emitter helpers for either variant, like it -// does for the AsmWriter. -#define MBlazeCodeEmitter MBlazeMCCodeEmitter -#define MachineInstr MCInst -#include "MBlazeGenCodeEmitter.inc" -#undef MBlazeCodeEmitter -#undef MachineInstr Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jul 25 15:18:18 2011 @@ -45,71 +45,6 @@ MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {} -/// getRegisterNumbering - Given the enum value for some register, e.g. -/// MBlaze::R0, return the number that it corresponds to (e.g. 0). -unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) { - switch (RegEnum) { - case MBlaze::R0 : return 0; - case MBlaze::R1 : return 1; - case MBlaze::R2 : return 2; - case MBlaze::R3 : return 3; - case MBlaze::R4 : return 4; - case MBlaze::R5 : return 5; - case MBlaze::R6 : return 6; - case MBlaze::R7 : return 7; - case MBlaze::R8 : return 8; - case MBlaze::R9 : return 9; - case MBlaze::R10 : return 10; - case MBlaze::R11 : return 11; - case MBlaze::R12 : return 12; - case MBlaze::R13 : return 13; - case MBlaze::R14 : return 14; - case MBlaze::R15 : return 15; - case MBlaze::R16 : return 16; - case MBlaze::R17 : return 17; - case MBlaze::R18 : return 18; - case MBlaze::R19 : return 19; - case MBlaze::R20 : return 20; - case MBlaze::R21 : return 21; - case MBlaze::R22 : return 22; - case MBlaze::R23 : return 23; - case MBlaze::R24 : return 24; - case MBlaze::R25 : return 25; - case MBlaze::R26 : return 26; - case MBlaze::R27 : return 27; - case MBlaze::R28 : return 28; - case MBlaze::R29 : return 29; - case MBlaze::R30 : return 30; - case MBlaze::R31 : return 31; - case MBlaze::RPC : return 0x0000; - case MBlaze::RMSR : return 0x0001; - case MBlaze::REAR : return 0x0003; - case MBlaze::RESR : return 0x0005; - case MBlaze::RFSR : return 0x0007; - case MBlaze::RBTR : return 0x000B; - case MBlaze::REDR : return 0x000D; - case MBlaze::RPID : return 0x1000; - case MBlaze::RZPR : return 0x1001; - case MBlaze::RTLBX : return 0x1002; - case MBlaze::RTLBLO : return 0x1003; - case MBlaze::RTLBHI : return 0x1004; - case MBlaze::RPVR0 : return 0x2000; - case MBlaze::RPVR1 : return 0x2001; - case MBlaze::RPVR2 : return 0x2002; - case MBlaze::RPVR3 : return 0x2003; - case MBlaze::RPVR4 : return 0x2004; - case MBlaze::RPVR5 : return 0x2005; - case MBlaze::RPVR6 : return 0x2006; - case MBlaze::RPVR7 : return 0x2007; - case MBlaze::RPVR8 : return 0x2008; - case MBlaze::RPVR9 : return 0x2009; - case MBlaze::RPVR10 : return 0x200A; - case MBlaze::RPVR11 : return 0x200B; - default: llvm_unreachable("Unknown register number!"); - } - return 0; // Not reached -} - /// getRegisterFromNumbering - Given the enum value for some register, e.g. /// MBlaze::R0, return the number that it corresponds to (e.g. 0). unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jul 25 15:18:18 2011 @@ -42,9 +42,6 @@ MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget, const TargetInstrInfo &tii); - /// getRegisterNumbering - Given the enum value for some register, e.g. - /// MBlaze::RA, return the number that it corresponds to (e.g. 31). - static unsigned getRegisterNumbering(unsigned RegEnum); static unsigned getRegisterFromNumbering(unsigned RegEnum); static unsigned getSpecialRegisterFromNumbering(unsigned RegEnum); static bool isRegister(unsigned RegEnum); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Mon Jul 25 15:18:18 2011 @@ -20,44 +20,9 @@ #include "llvm/Target/TargetRegistry.h" using namespace llvm; -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin()) { - llvm_unreachable("MBlaze does not support Darwin MACH-O format"); - return NULL; - } - - if (TheTriple.isOSWindows()) { - llvm_unreachable("MBlaze does not support Windows COFF format"); - return NULL; - } - - return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); -} - - extern "C" void LLVMInitializeMBlazeTarget() { // Register the target. RegisterTargetMachine X(TheMBlazeTarget); - - // Register the MC code emitter - TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget, - llvm::createMBlazeMCCodeEmitter); - - // Register the asm backend - TargetRegistry::RegisterAsmBackend(TheMBlazeTarget, - createMBlazeAsmBackend); - - // Register the object streamer - TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget, - createMCStreamer); - } // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Mon Jul 25 15:18:18 2011 @@ -1,4 +1,6 @@ add_llvm_library(LLVMMBlazeDesc - MBlazeMCTargetDesc.cpp + MBlazeAsmBackend.cpp MBlazeMCAsmInfo.cpp + MBlazeMCCodeEmitter.cpp + MBlazeMCTargetDesc.cpp ) Copied: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (from r135928, llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?p2=llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp&p1=llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp&r1=135928&r2=135953&rev=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Mon Jul 25 15:18:18 2011 @@ -7,10 +7,8 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/MBlazeMCTargetDesc.h" #include "llvm/MC/TargetAsmBackend.h" -#include "MBlaze.h" -#include "MBlazeELFWriterInfo.h" -#include "llvm/ADT/Twine.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCELFObjectWriter.h" @@ -20,6 +18,7 @@ #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCValue.h" +#include "llvm/ADT/Twine.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" Added: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h?rev=135953&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h (added) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h Mon Jul 25 15:18:18 2011 @@ -0,0 +1,148 @@ +//===-- MBlazeBaseInfo.h - Top level definitions for MBlaze -- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the MBlaze target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef MBlazeBASEINFO_H +#define MBlazeBASEINFO_H + +#include "MBlazeMCTargetDesc.h" +#include "llvm/Support/ErrorHandling.h" + +namespace llvm { + +/// MBlazeII - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +namespace MBlazeII { + enum { + // PseudoFrm - This represents an instruction that is a pseudo instruction + // or one that has not been implemented yet. It is illegal to code generate + // it, but tolerated for intermediate implementation stages. + FPseudo = 0, + FRRR, + FRRI, + FCRR, + FCRI, + FRCR, + FRCI, + FCCR, + FCCI, + FRRCI, + FRRC, + FRCX, + FRCS, + FCRCS, + FCRCX, + FCX, + FCR, + FRIR, + FRRRR, + FRI, + FC, + FormMask = 63 + + //===------------------------------------------------------------------===// + // MBlaze Specific MachineOperand flags. + // MO_NO_FLAG, + + /// MO_GOT - Represents the offset into the global offset table at which + /// the address the relocation entry symbol resides during execution. + // MO_GOT, + + /// MO_GOT_CALL - Represents the offset into the global offset table at + /// which the address of a call site relocation entry symbol resides + /// during execution. This is different from the above since this flag + /// can only be present in call instructions. + // MO_GOT_CALL, + + /// MO_GPREL - Represents the offset from the current gp value to be used + /// for the relocatable object file being produced. + // MO_GPREL, + + /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol + /// address. + // MO_ABS_HILO + + }; +} + +/// getMBlazeRegisterNumbering - Given the enum value for some register, e.g. +/// MBlaze::R0, return the number that it corresponds to (e.g. 0). +static inline unsigned getMBlazeRegisterNumbering(unsigned RegEnum) { + switch (RegEnum) { + case MBlaze::R0 : return 0; + case MBlaze::R1 : return 1; + case MBlaze::R2 : return 2; + case MBlaze::R3 : return 3; + case MBlaze::R4 : return 4; + case MBlaze::R5 : return 5; + case MBlaze::R6 : return 6; + case MBlaze::R7 : return 7; + case MBlaze::R8 : return 8; + case MBlaze::R9 : return 9; + case MBlaze::R10 : return 10; + case MBlaze::R11 : return 11; + case MBlaze::R12 : return 12; + case MBlaze::R13 : return 13; + case MBlaze::R14 : return 14; + case MBlaze::R15 : return 15; + case MBlaze::R16 : return 16; + case MBlaze::R17 : return 17; + case MBlaze::R18 : return 18; + case MBlaze::R19 : return 19; + case MBlaze::R20 : return 20; + case MBlaze::R21 : return 21; + case MBlaze::R22 : return 22; + case MBlaze::R23 : return 23; + case MBlaze::R24 : return 24; + case MBlaze::R25 : return 25; + case MBlaze::R26 : return 26; + case MBlaze::R27 : return 27; + case MBlaze::R28 : return 28; + case MBlaze::R29 : return 29; + case MBlaze::R30 : return 30; + case MBlaze::R31 : return 31; + case MBlaze::RPC : return 0x0000; + case MBlaze::RMSR : return 0x0001; + case MBlaze::REAR : return 0x0003; + case MBlaze::RESR : return 0x0005; + case MBlaze::RFSR : return 0x0007; + case MBlaze::RBTR : return 0x000B; + case MBlaze::REDR : return 0x000D; + case MBlaze::RPID : return 0x1000; + case MBlaze::RZPR : return 0x1001; + case MBlaze::RTLBX : return 0x1002; + case MBlaze::RTLBLO : return 0x1003; + case MBlaze::RTLBHI : return 0x1004; + case MBlaze::RPVR0 : return 0x2000; + case MBlaze::RPVR1 : return 0x2001; + case MBlaze::RPVR2 : return 0x2002; + case MBlaze::RPVR3 : return 0x2003; + case MBlaze::RPVR4 : return 0x2004; + case MBlaze::RPVR5 : return 0x2005; + case MBlaze::RPVR6 : return 0x2006; + case MBlaze::RPVR7 : return 0x2007; + case MBlaze::RPVR8 : return 0x2008; + case MBlaze::RPVR9 : return 0x2009; + case MBlaze::RPVR10 : return 0x200A; + case MBlaze::RPVR11 : return 0x200B; + default: llvm_unreachable("Unknown register number!"); + } + return 0; // Not reached +} + +} // end namespace llvm; + +#endif Copied: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp (from r135928, llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp?p2=llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp&p1=llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp&r1=135928&r2=135953&rev=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp Mon Jul 25 15:18:18 2011 @@ -12,11 +12,13 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mccodeemitter" -#include "MBlaze.h" -#include "MBlazeInstrInfo.h" +#include "MCTargetDesc/MBlazeBaseInfo.h" +#include "MCTargetDesc/MBlazeMCTargetDesc.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCFixup.h" #include "llvm/ADT/Statistic.h" @@ -106,7 +108,7 @@ unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO) const { if (MO.isReg()) - return MBlazeRegisterInfo::getRegisterNumbering(MO.getReg()); + return getMBlazeRegisterNumbering(MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); else if (MO.isExpr()) Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Mon Jul 25 15:18:18 2011 @@ -15,8 +15,10 @@ #include "MBlazeMCAsmInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_MC_DESC #include "MBlazeGenInstrInfo.inc" @@ -68,6 +70,27 @@ return X; } +static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, + MCContext &Ctx, TargetAsmBackend &TAB, + raw_ostream &_OS, + MCCodeEmitter *_Emitter, + bool RelaxAll, + bool NoExecStack) { + Triple TheTriple(TT); + + if (TheTriple.isOSDarwin()) { + llvm_unreachable("MBlaze does not support Darwin MACH-O format"); + return NULL; + } + + if (TheTriple.isOSWindows()) { + llvm_unreachable("MBlaze does not support Windows COFF format"); + return NULL; + } + + return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); +} + // Force static initialization. extern "C" void LLVMInitializeMBlazeTargetMC() { // Register the MC asm info. @@ -87,4 +110,16 @@ // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget, createMBlazeMCSubtargetInfo); + + // Register the MC code emitter + TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget, + llvm::createMBlazeMCCodeEmitter); + + // Register the asm backend + TargetRegistry::RegisterAsmBackend(TheMBlazeTarget, + createMBlazeAsmBackend); + + // Register the object streamer + TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget, + createMCStreamer); } Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h?rev=135953&r1=135952&r2=135953&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Mon Jul 25 15:18:18 2011 @@ -14,13 +14,26 @@ #ifndef MBLAZEMCTARGETDESC_H #define MBLAZEMCTARGETDESC_H +#include + namespace llvm { +class MCContext; +class MCCodeEmitter; +class MCInstrInfo; class MCSubtargetInfo; class Target; +class TargetAsmBackend; class StringRef; +class formatted_raw_ostream; extern Target TheMBlazeTarget; +MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, + const MCSubtargetInfo &STI, + MCContext &Ctx); + +TargetAsmBackend *createMBlazeAsmBackend(const Target &, const std::string &); + } // End llvm namespace // Defines symbolic names for MBlaze registers. This defines a mapping from From evan.cheng at apple.com Mon Jul 25 15:18:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 20:18:49 -0000 Subject: [llvm-commits] [llvm] r135954 - in /llvm/trunk/lib/Target: ARM/ARM.h ARM/MCTargetDesc/ARMBaseInfo.h PowerPC/MCTargetDesc/PPCBaseInfo.h PowerPC/PPC.h X86/X86.h Message-ID: <20110725201849.2D6AA2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 15:18:48 2011 New Revision: 135954 URL: http://llvm.org/viewvc/llvm-project?rev=135954&view=rev Log: Code clean up. Modified: llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h llvm/trunk/lib/Target/PowerPC/PPC.h llvm/trunk/lib/Target/X86/X86.h Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=135954&r1=135953&r2=135954&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Jul 25 15:18:48 2011 @@ -29,13 +29,7 @@ class FunctionPass; class JITCodeEmitter; class MachineInstr; -class MCCodeEmitter; class MCInst; -class MCInstrInfo; -class MCObjectWriter; -class MCSubtargetInfo; -class TargetAsmBackend; -class formatted_raw_ostream; FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel); Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=135954&r1=135953&r2=135954&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Mon Jul 25 15:18:48 2011 @@ -20,9 +20,6 @@ #include "ARMMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" -// Note that the following auto-generated files only defined enum types, and -// so are safe to include here. - namespace llvm { // Enums corresponding to ARM condition codes Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h?rev=135954&r1=135953&r2=135954&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h Mon Jul 25 15:18:48 2011 @@ -22,7 +22,7 @@ namespace llvm { -/// getRegisterNumbering - Given the enum value for some register, e.g. +/// getPPCRegisterNumbering - Given the enum value for some register, e.g. /// PPC::F14, return the number that it corresponds to (e.g. 14). inline static unsigned getPPCRegisterNumbering(unsigned RegEnum) { using namespace PPC; Modified: llvm/trunk/lib/Target/PowerPC/PPC.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=135954&r1=135953&r2=135954&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPC.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Jul 25 15:18:48 2011 @@ -31,12 +31,7 @@ class MachineInstr; class AsmPrinter; class MCInst; - class MCCodeEmitter; - class MCContext; - class MCInstrInfo; - class MCSubtargetInfo; class TargetMachine; - class TargetAsmBackend; FunctionPass *createPPCBranchSelectionPass(); FunctionPass *createPPCISelDag(PPCTargetMachine &TM); Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=135954&r1=135953&r2=135954&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Mon Jul 25 15:18:48 2011 @@ -25,16 +25,8 @@ class FunctionPass; class JITCodeEmitter; class MachineCodeEmitter; -class MCCodeEmitter; -class MCContext; -class MCInstrInfo; -class MCObjectWriter; -class MCSubtargetInfo; class Target; -class TargetAsmBackend; class X86TargetMachine; -class formatted_raw_ostream; -class raw_ostream; /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. From isanbard at gmail.com Mon Jul 25 15:19:48 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 20:19:48 -0000 Subject: [llvm-commits] [llvm] r135955 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20110725201948.D18642A6C12C@llvm.org> Author: void Date: Mon Jul 25 15:19:48 2011 New Revision: 135955 URL: http://llvm.org/viewvc/llvm-project?rev=135955&view=rev Log: An initial description of the compact unwind encoding. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=135955&r1=135954&r2=135955&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Mon Jul 25 15:19:48 2011 @@ -1805,7 +1805,115 @@

    Prolog/Epilog Code Insertion

    -

    To Be Written

    + + +

    + Compact Unwind +

    + +
    + +

    Unwinding out of a function is done virually via DWARF encodings. These + encodings exist in two forms: a Common Information Entry (CIE) and a Frame + Description Entry (FDE). These two tables contain the information necessary + for the unwinder to restore the state of the computer to before the function + was called. However, the tables themselves are rather large. LLVM can use a + "compact unwind" encoding to represent the virtual unwinding.

    + +

    The compact unwind encoding is a 32-bit value, which is encoded in an + architecture-specific way. It specifies which registers to restore and from + where, and how to unwind out of the funciton. When the linker creates a final + linked image, it will create a __TEXT,__unwind_info + section. This section is a small and fast way for the runtime to access + unwind info for any given function. If we emit compact unwind info for the + function, that compact unwind info will be encoded in + the __TEXT,__unwind_info section. If we emit DWARF unwind info, + the __TEXT,__unwind_info section will contain the offset of the + FDE in the __TEXT,__eh_frame section in the final linked + image.

    + +

    For X86, there are three modes for the compact unwind encoding:

    + +
      +
      Function with a Frame Pointer (EBP or RBP)
      +

      EBP/RBP-based frame, where EBP/RBP is pushed + onto the stack immediately after the return address, + then ESP/RSP is moved to EBP/RBP. Thus to + unwind, ESP/RSP is restored with the + current EBP/RBP value, then EBP/RBP is restored + by popping the stack, and the return is done by popping the stack once + more into the PC. All non-volatile registers that need to be restored must + have been saved in a small range on the stack that + starts EBP-4 to EBP-1020 (RBP-8 + to RBP-1020). The offset (divided by 4) is encoded in bits + 16-23 (mask: 0x00FF0000). The registers saved are encoded in + bits 0-14 (mask: 0x00007FFF) as five 3-bit entries from the + following table:

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      Compact Numberi386 Registerx86-64 Regiser
      1EBXRBX
      2ECXR12
      3EDXR13
      4EDIR14
      5ESIR15
      6EBPRBP
      + +
      + +
      Frameless with a Small Constant Stack Size (EBP or RBP is not used as a frame pointer)
      +

      To return, a constant (encoded in the compact unwind encoding) is added + to the ESP/RSP. Then the return is done by popping the stack + into the PC. All non-volatile registers that need to be restored must have + been saved on the stack immediately after the return address. The stack + size (divided by 4) is encoded in bits 16-23 + (mask: 0x00FF0000). There is a maximum stack size of 1024 + bytes. The number of registers saved is encoded in bits 9-12 + (mask: 0x00001C00). Bits 0-9 (mask: + 0x000003FF) contain which registers were saved and their + order. (See the encodeCompactUnwindRegistersWithoutFrame() + function in lib/Target/X86FrameLowering.cpp for the encoding + algorithm.)

      + +
      Frameless with a Large Constant Stack Size (EBP or RBP is not used as a frame pointer)
      +

      This case is like the "Frameless with a Small Constant Stack Size" + case, but the stack size is too larget to encode in the compact unwind + encoding. Instead it requires that the function contains "subl + $nnnnnn, %esp" in its prolog. The compact encoding contains the + offset to the $nnnnnn value in the funciton in bits 9-12 + (mask: 0x00001C00).

      +
    + +
    +

    Late Machine Code Optimizations From isanbard at gmail.com Mon Jul 25 15:25:03 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 25 Jul 2011 20:25:03 -0000 Subject: [llvm-commits] [llvm] r135956 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20110725202503.5D6282A6C12C@llvm.org> Author: void Date: Mon Jul 25 15:25:03 2011 New Revision: 135956 URL: http://llvm.org/viewvc/llvm-project?rev=135956&view=rev Log: Fix some typos. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=135956&r1=135955&r2=135956&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Mon Jul 25 15:25:03 2011 @@ -1889,7 +1889,8 @@ -
    Frameless with a Small Constant Stack Size (EBP or RBP is not used as a frame pointer)
    +
    Frameless with a Small Constant Stack Size (EBP + or RBP is not used as a frame pointer)

    To return, a constant (encoded in the compact unwind encoding) is added to the ESP/RSP. Then the return is done by popping the stack into the PC. All non-volatile registers that need to be restored must have @@ -1903,12 +1904,13 @@ function in lib/Target/X86FrameLowering.cpp for the encoding algorithm.)

    -
    Frameless with a Large Constant Stack Size (EBP or RBP is not used as a frame pointer)
    +
    Frameless with a Large Constant Stack Size (EBP + or RBP is not used as a frame pointer)

    This case is like the "Frameless with a Small Constant Stack Size" - case, but the stack size is too larget to encode in the compact unwind + case, but the stack size is too large to encode in the compact unwind encoding. Instead it requires that the function contains "subl $nnnnnn, %esp" in its prolog. The compact encoding contains the - offset to the $nnnnnn value in the funciton in bits 9-12 + offset to the $nnnnnn value in the function in bits 9-12 (mask: 0x00001C00).

    From grosbach at apple.com Mon Jul 25 15:38:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 20:38:19 -0000 Subject: [llvm-commits] [llvm] r135958 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20110725203819.2A6D42A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 15:38:18 2011 New Revision: 135958 URL: http://llvm.org/viewvc/llvm-project?rev=135958&view=rev Log: More simple cleanup of ARM asm operand definitions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135958&r1=135957&r2=135958&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Jul 25 15:38:18 2011 @@ -131,39 +131,15 @@ // ARM special operands. // -def CondCodeOperand : AsmOperandClass { - let Name = "CondCode"; - let SuperClasses = []; -} - -def CCOutOperand : AsmOperandClass { - let Name = "CCOut"; - let SuperClasses = []; -} - -def MemBarrierOptOperand : AsmOperandClass { - let Name = "MemBarrierOpt"; - let SuperClasses = []; - let ParserMethod = "parseMemBarrierOptOperand"; +// ARM imod and iflag operands, used only by the CPS instruction. +def imod_op : Operand { + let PrintMethod = "printCPSIMod"; } def ProcIFlagsOperand : AsmOperandClass { let Name = "ProcIFlags"; - let SuperClasses = []; let ParserMethod = "parseProcIFlagsOperand"; } - -def MSRMaskOperand : AsmOperandClass { - let Name = "MSRMask"; - let SuperClasses = []; - let ParserMethod = "parseMSRMaskOperand"; -} - -// ARM imod and iflag operands, used only by the CPS instruction. -def imod_op : Operand { - let PrintMethod = "printCPSIMod"; -} - def iflags_op : Operand { let PrintMethod = "printCPSIFlag"; let ParserMatchClass = ProcIFlagsOperand; @@ -171,6 +147,7 @@ // ARM Predicate operand. Default to 14 = always (AL). Second part is CC // register whose default is 0 (no register). +def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand { let PrintMethod = "printPredicateOperand"; @@ -178,6 +155,7 @@ } // Conditional code result for instructions whose 's' bit is set, e.g. subs. +def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } def cc_out : OptionalDefOperand { let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; @@ -202,6 +180,10 @@ let ParserMatchClass = SetEndAsmOperand; } +def MSRMaskOperand : AsmOperandClass { + let Name = "MSRMask"; + let ParserMethod = "parseMSRMaskOperand"; +} def msr_mask : Operand { let PrintMethod = "printMSRMaskOperand"; let ParserMatchClass = MSRMaskOperand; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135958&r1=135957&r2=135958&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 15:38:18 2011 @@ -394,7 +394,6 @@ let EncoderMethod = "getRotImmOpValue"; } - // shift_imm: An integer that encodes a shift amount and the type of shift // (currently either asr or lsl) using the same encoding used for the // immediates in so_reg operands. @@ -3450,6 +3449,10 @@ // Atomic operations intrinsics // +def MemBarrierOptOperand : AsmOperandClass { + let Name = "MemBarrierOpt"; + let ParserMethod = "parseMemBarrierOptOperand"; +} def memb_opt : Operand { let PrintMethod = "printMemBOption"; let ParserMatchClass = MemBarrierOptOperand; From grosbach at apple.com Mon Jul 25 15:49:51 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 20:49:51 -0000 Subject: [llvm-commits] [llvm] r135959 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td AsmParser/ARMAsmParser.cpp Message-ID: <20110725204951.CBFF42A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 15:49:51 2011 New Revision: 135959 URL: http://llvm.org/viewvc/llvm-project?rev=135959&view=rev Log: ARM asm operand renaming. Make things a bit more explicit. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135959&r1=135958&r2=135959&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 15:49:51 2011 @@ -404,7 +404,7 @@ } // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. -def ShiftedRegAsmOperand : AsmOperandClass { let Name = "ShiftedReg"; } +def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } def so_reg_reg : Operand, // reg reg imm ComplexPattern { @@ -414,7 +414,7 @@ let MIOperandInfo = (ops GPR, GPR, shift_imm); } -def ShiftedImmAsmOperand : AsmOperandClass { let Name = "ShiftedImm"; } +def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } def so_reg_imm : Operand, // reg imm ComplexPattern { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135959&r1=135958&r2=135959&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 15:49:51 2011 @@ -242,12 +242,12 @@ unsigned SrcReg; unsigned ShiftReg; unsigned ShiftImm; - } ShiftedReg; + } RegShiftedReg; struct { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; unsigned ShiftImm; - } ShiftedImm; + } RegShiftedImm; }; ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -295,10 +295,10 @@ Shift = o.Shift; break; case ShiftedRegister: - ShiftedReg = o.ShiftedReg; + RegShiftedReg = o.RegShiftedReg; break; case ShiftedImmediate: - ShiftedImm = o.ShiftedImm; + RegShiftedImm = o.RegShiftedImm; break; } } @@ -501,8 +501,8 @@ bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } bool isMemory() const { return Kind == Memory; } bool isShifter() const { return Kind == Shifter; } - bool isShiftedReg() const { return Kind == ShiftedRegister; } - bool isShiftedImm() const { return Kind == ShiftedImmediate; } + bool isRegShiftedReg() const { return Kind == ShiftedRegister; } + bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } bool isMemMode2() const { if (getMemAddrMode() != ARMII::AddrMode2) return false; @@ -633,21 +633,21 @@ Inst.addOperand(MCOperand::CreateReg(getReg())); } - void addShiftedRegOperands(MCInst &Inst, unsigned N) const { + void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); - assert(isShiftedReg() && "addShiftedRegOperands() on non ShiftedReg!"); - Inst.addOperand(MCOperand::CreateReg(ShiftedReg.SrcReg)); - Inst.addOperand(MCOperand::CreateReg(ShiftedReg.ShiftReg)); + assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); + Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); + Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); Inst.addOperand(MCOperand::CreateImm( - ARM_AM::getSORegOpc(ShiftedReg.ShiftTy, ShiftedReg.ShiftImm))); + ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); } - void addShiftedImmOperands(MCInst &Inst, unsigned N) const { + void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); - assert(isShiftedImm() && "addShiftedImmOperands() on non ShiftedImm!"); - Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg)); + assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); + Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); Inst.addOperand(MCOperand::CreateImm( - ARM_AM::getSORegOpc(ShiftedImm.ShiftTy, ShiftedImm.ShiftImm))); + ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); } @@ -935,10 +935,10 @@ unsigned ShiftImm, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(ShiftedRegister); - Op->ShiftedReg.ShiftTy = ShTy; - Op->ShiftedReg.SrcReg = SrcReg; - Op->ShiftedReg.ShiftReg = ShiftReg; - Op->ShiftedReg.ShiftImm = ShiftImm; + Op->RegShiftedReg.ShiftTy = ShTy; + Op->RegShiftedReg.SrcReg = SrcReg; + Op->RegShiftedReg.ShiftReg = ShiftReg; + Op->RegShiftedReg.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -949,9 +949,9 @@ unsigned ShiftImm, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(ShiftedImmediate); - Op->ShiftedImm.ShiftTy = ShTy; - Op->ShiftedImm.SrcReg = SrcReg; - Op->ShiftedImm.ShiftImm = ShiftImm; + Op->RegShiftedImm.ShiftTy = ShTy; + Op->RegShiftedImm.SrcReg = SrcReg; + Op->RegShiftedImm.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -1125,17 +1125,17 @@ break; case ShiftedRegister: OS << ""; break; case ShiftedImmediate: OS << ""; break; case RegisterList: @@ -1282,7 +1282,7 @@ if (ShiftReg && ShiftTy != ARM_AM::rrx) Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, - ShiftReg, Imm, + ShiftReg, Imm, S, Parser.getTok().getLoc())); else Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, From evan.cheng at apple.com Mon Jul 25 15:53:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 20:53:02 -0000 Subject: [llvm-commits] [llvm] r135963 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/MC/MCDisassembler/EDDisassembler.cpp lib/MC/MCDisassembler/EDDisassembler.h lib/Target/ARM/AsmParser/ARMAsmLexer.cpp lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp lib/Target/X86/AsmParser/X86AsmLexer.cpp tools/llvm-mc/llvm-mc.cpp tools/llvm-objdump/llvm-objdump.cpp Message-ID: <20110725205302.CB89E2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 15:53:02 2011 New Revision: 135963 URL: http://llvm.org/viewvc/llvm-project?rev=135963&view=rev Log: Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore. Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Mon Jul 25 15:53:02 2011 @@ -89,6 +89,7 @@ typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T, const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, + const MCRegisterInfo &MRI, const MCAsmInfo &MAI); typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI, MCAsmParser &P); @@ -333,10 +334,11 @@ /// createAsmLexer - Create a target specific assembly lexer. /// - TargetAsmLexer *createAsmLexer(const MCAsmInfo &MAI) const { + TargetAsmLexer *createAsmLexer(const MCRegisterInfo &MRI, + const MCAsmInfo &MAI) const { if (!AsmLexerCtorFn) return 0; - return AsmLexerCtorFn(*this, MAI); + return AsmLexerCtorFn(*this, MRI, MAI); } /// createAsmParser - Create a target specific assembly parser. @@ -989,8 +991,9 @@ } private: - static TargetAsmLexer *Allocator(const Target &T, const MCAsmInfo &MAI) { - return new AsmLexerImpl(T, MAI); + static TargetAsmLexer *Allocator(const Target &T, const MCRegisterInfo &MRI, + const MCAsmInfo &MAI) { + return new AsmLexerImpl(T, MRI, MAI); } }; Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Mon Jul 25 15:53:02 2011 @@ -34,8 +34,6 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSelect.h" using namespace llvm; @@ -107,7 +105,6 @@ sInitialized = true; InitializeAllTargetInfos(); - InitializeAllTargets(); InitializeAllTargetMCs(); InitializeAllAsmPrinters(); InitializeAllAsmParsers(); @@ -170,29 +167,18 @@ if (!Tgt) return; - std::string CPU; - std::string featureString; - TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, - featureString)); + MRI.reset(Tgt->createMCRegInfo(tripleString)); - // FIXME: It shouldn't be using TargetRegisterInfo! - const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); - - if (!registerInfo) + if (!MRI) return; - - initMaps(*registerInfo); + + initMaps(*MRI); AsmInfo.reset(Tgt->createMCAsmInfo(tripleString)); if (!AsmInfo) return; - MRI.reset(Tgt->createMCRegInfo(tripleString)); - - if (!MRI) - return; - Disassembler.reset(Tgt->createMCDisassembler()); if (!Disassembler) @@ -208,10 +194,10 @@ return; GenericAsmLexer.reset(new AsmLexer(*AsmInfo)); - SpecificAsmLexer.reset(Tgt->createAsmLexer(*AsmInfo)); + SpecificAsmLexer.reset(Tgt->createAsmLexer(*MRI, *AsmInfo)); SpecificAsmLexer->InstallLexer(*GenericAsmLexer); - initMaps(*TargetMachine->getRegisterInfo()); + initMaps(*MRI); Valid = true; } @@ -273,7 +259,7 @@ } } -void EDDisassembler::initMaps(const TargetRegisterInfo ®isterInfo) { +void EDDisassembler::initMaps(const MCRegisterInfo ®isterInfo) { unsigned numRegisters = registerInfo.getNumRegs(); unsigned registerIndex; Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Mon Jul 25 15:53:02 2011 @@ -46,8 +46,6 @@ class Target; class TargetAsmLexer; class TargetAsmParser; -class TargetMachine; -class TargetRegisterInfo; struct EDInstInfo; struct EDInst; @@ -137,8 +135,6 @@ CPUKey Key; /// The LLVM target corresponding to the disassembler const llvm::Target *Tgt; - /// The target machine instance. - llvm::OwningPtr TargetMachine; /// The assembly information for the target architecture llvm::OwningPtr AsmInfo; // The register information for the target architecture. @@ -219,7 +215,7 @@ /// info /// /// @arg registerInfo - the register information to use as a source - void initMaps(const llvm::TargetRegisterInfo ®isterInfo); + void initMaps(const llvm::MCRegisterInfo ®isterInfo); /// nameWithRegisterID - Returns the name (owned by the EDDisassembler) of a /// register for a given register ID, or NULL on failure /// Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Mon Jul 25 15:53:02 2011 @@ -8,14 +8,13 @@ //===----------------------------------------------------------------------===// #include "ARM.h" -#include "ARMTargetMachine.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" @@ -43,7 +42,7 @@ rmap_ty RegisterMap; - void InitRegisterMap(const TargetRegisterInfo *info) { + void InitRegisterMap(const MCRegisterInfo *info) { unsigned numRegs = info->getNumRegs(); for (unsigned i = 0; i < numRegs; ++i) { @@ -83,27 +82,17 @@ class ARMAsmLexer : public ARMBaseAsmLexer { public: - ARMAsmLexer(const Target &T, const MCAsmInfo &MAI) + ARMAsmLexer(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI) : ARMBaseAsmLexer(T, MAI) { - std::string tripleString("arm-unknown-unknown"); - std::string featureString; - std::string CPU; - OwningPtr - targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); - InitRegisterMap(targetMachine->getRegisterInfo()); + InitRegisterMap(&MRI); } }; class ThumbAsmLexer : public ARMBaseAsmLexer { public: - ThumbAsmLexer(const Target &T, const MCAsmInfo &MAI) + ThumbAsmLexer(const Target &T, const MCRegisterInfo &MRI,const MCAsmInfo &MAI) : ARMBaseAsmLexer(T, MAI) { - std::string tripleString("thumb-unknown-unknown"); - std::string featureString; - std::string CPU; - OwningPtr - targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); - InitRegisterMap(targetMachine->getRegisterInfo()); + InitRegisterMap(&MRI); } }; Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Mon Jul 25 15:53:02 2011 @@ -8,7 +8,6 @@ //===----------------------------------------------------------------------===// #include "MBlaze.h" -#include "MBlazeTargetMachine.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" @@ -17,9 +16,9 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/TargetAsmLexer.h" -#include "llvm/Target/TargetMachine.h" // FIXME #include "llvm/Target/TargetRegistry.h" #include @@ -42,7 +41,7 @@ rmap_ty RegisterMap; - void InitRegisterMap(const TargetRegisterInfo *info) { + void InitRegisterMap(const MCRegisterInfo *info) { unsigned numRegs = info->getNumRegs(); for (unsigned i = 0; i < numRegs; ++i) { @@ -82,14 +81,10 @@ class MBlazeAsmLexer : public MBlazeBaseAsmLexer { public: - MBlazeAsmLexer(const Target &T, const MCAsmInfo &MAI) + MBlazeAsmLexer(const Target &T, const MCRegisterInfo &MRI, + const MCAsmInfo &MAI) : MBlazeBaseAsmLexer(T, MAI) { - std::string tripleString("mblaze-unknown-unknown"); - std::string featureString; - std::string CPU; - OwningPtr - targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); - InitRegisterMap(targetMachine->getRegisterInfo()); + InitRegisterMap(&MRI); } }; } Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp Mon Jul 25 15:53:02 2011 @@ -60,7 +60,7 @@ } } public: - X86AsmLexer(const Target &T, const MCAsmInfo &MAI) + X86AsmLexer(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI) : TargetAsmLexer(T), AsmInfo(MAI), tentativeIsValid(false) { } }; Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 15:53:02 2011 @@ -26,7 +26,6 @@ #include "llvm/MC/SubtargetFeature.h" #include "llvm/MC/TargetAsmBackend.h" #include "llvm/MC/TargetAsmParser.h" -#include "llvm/Target/TargetData.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSelect.h" #include "llvm/ADT/OwningPtr.h" @@ -452,8 +451,6 @@ // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); - // FIXME: We shouldn't need to initialize the Target(Machine)s. - llvm::InitializeAllTargets(); llvm::InitializeAllTargetMCs(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=135963&r1=135962&r2=135963&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Jul 25 15:53:02 2011 @@ -308,8 +308,6 @@ // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); - // FIXME: We shouldn't need to initialize the Target(Machine)s. - llvm::InitializeAllTargets(); llvm::InitializeAllTargetMCs(); llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); From rafael.espindola at gmail.com Mon Jul 25 15:57:59 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 25 Jul 2011 20:57:59 -0000 Subject: [llvm-commits] [llvm] r135966 - in /llvm/trunk: include/llvm-c/Transforms/Scalar.h lib/Transforms/Scalar/Scalar.cpp Message-ID: <20110725205759.EBB622A6C12D@llvm.org> Author: rafael Date: Mon Jul 25 15:57:59 2011 New Revision: 135966 URL: http://llvm.org/viewvc/llvm-project?rev=135966&view=rev Log: Add LLVMAddLowerExpectIntrinsicPass to the C API. Modified: llvm/trunk/include/llvm-c/Transforms/Scalar.h llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Modified: llvm/trunk/include/llvm-c/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Transforms/Scalar.h?rev=135966&r1=135965&r2=135966&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm-c/Transforms/Scalar.h Mon Jul 25 15:57:59 2011 @@ -107,6 +107,9 @@ /** See llvm::createEarlyCSEPass function */ void LLVMAddEarlyCSEPass(LLVMPassManagerRef PM); +/** See llvm::createLowerExpectIntrinsicPass function */ +void LLVMAddLowerExpectIntrinsicPass(LLVMPassManagerRef PM); + /** See llvm::createTypeBasedAliasAnalysisPass function */ void LLVMAddTypeBasedAliasAnalysisPass(LLVMPassManagerRef PM); Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=135966&r1=135965&r2=135966&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Mon Jul 25 15:57:59 2011 @@ -187,3 +187,7 @@ void LLVMAddBasicAliasAnalysisPass(LLVMPassManagerRef PM) { unwrap(PM)->add(createBasicAliasAnalysisPass()); } + +void LLVMAddLowerExpectIntrinsicPass(LLVMPassManagerRef PM) { + unwrap(PM)->add(createLowerExpectIntrinsicPass()); +} From grosbach at apple.com Mon Jul 25 16:04:58 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 21:04:58 -0000 Subject: [llvm-commits] [llvm] r135968 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110725210459.229402A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 16:04:58 2011 New Revision: 135968 URL: http://llvm.org/viewvc/llvm-project?rev=135968&view=rev Log: Simply ARM so_reg MIOperandInfo definitions. The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135968&r1=135967&r2=135968&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 16:04:58 2011 @@ -411,7 +411,7 @@ let EncoderMethod = "getSORegRegOpValue"; let PrintMethod = "printSORegRegOperand"; let ParserMatchClass = ShiftedRegAsmOperand; - let MIOperandInfo = (ops GPR, GPR, shift_imm); + let MIOperandInfo = (ops GPR, GPR, i32imm); } def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } @@ -421,7 +421,7 @@ let EncoderMethod = "getSORegImmOpValue"; let PrintMethod = "printSORegImmOperand"; let ParserMatchClass = ShiftedImmAsmOperand; - let MIOperandInfo = (ops GPR, shift_imm); + let MIOperandInfo = (ops GPR, i32imm); } // FIXME: Does this need to be distinct from so_reg? @@ -430,7 +430,7 @@ [shl,srl,sra,rotr]> { let EncoderMethod = "getSORegRegOpValue"; let PrintMethod = "printSORegRegOperand"; - let MIOperandInfo = (ops GPR, GPR, shift_imm); + let MIOperandInfo = (ops GPR, GPR, i32imm); } // FIXME: Does this need to be distinct from so_reg? @@ -439,7 +439,7 @@ [shl,srl,sra,rotr]> { let EncoderMethod = "getSORegImmOpValue"; let PrintMethod = "printSORegImmOperand"; - let MIOperandInfo = (ops GPR, shift_imm); + let MIOperandInfo = (ops GPR, i32imm); } From nicholas at mxc.ca Mon Jul 25 16:12:44 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 25 Jul 2011 21:12:44 -0000 Subject: [llvm-commits] [llvm] r135971 - /llvm/trunk/tools/lto/LTOCodeGenerator.cpp Message-ID: <20110725211244.6EB082A6C12C@llvm.org> Author: nicholas Date: Mon Jul 25 16:12:44 2011 New Revision: 135971 URL: http://llvm.org/viewvc/llvm-project?rev=135971&view=rev Log: Fix typo. Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=135971&r1=135970&r2=135971&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Mon Jul 25 16:12:44 2011 @@ -263,7 +263,7 @@ break; } - // construct LTModule, hand over ownership of module and target + // construct LTOModule, hand over ownership of module and target SubtargetFeatures Features; Features.getDefaultSubtargetFeatures(llvm::Triple(Triple)); std::string FeatureStr = Features.getString(); From nicholas at mxc.ca Mon Jul 25 16:13:23 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 25 Jul 2011 21:13:23 -0000 Subject: [llvm-commits] [llvm] r135972 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20110725211323.CE3CA2A6C12C@llvm.org> Author: nicholas Date: Mon Jul 25 16:13:23 2011 New Revision: 135972 URL: http://llvm.org/viewvc/llvm-project?rev=135972&view=rev Log: 80 columns. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=135972&r1=135971&r2=135972&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Mon Jul 25 16:13:23 2011 @@ -298,8 +298,8 @@ of tags are loosely bound to the tag values of DWARF information entries. However, that does not restrict the use of the information supplied to DWARF targets. To facilitate versioning of debug information, the tag is augmented - with the current debug version (LLVMDebugVersion = 8 << 16 or 0x80000 or - 524288.)

    + with the current debug version (LLVMDebugVersion = 8 << 16 or + 0x80000 or 524288.)

    The details of the various descriptors follow.

    From chandlerc at google.com Mon Jul 25 16:16:35 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 25 Jul 2011 14:16:35 -0700 Subject: [llvm-commits] [llvm] r135963 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/MC/MCDisassembler/EDDisassembler.cpp lib/MC/MCDisassembler/EDDisassembler.h lib/Target/ARM/AsmParser/ARMAsmLexer.cpp lib/Target/MBlaze/AsmParser/MBlazeAsmLex Message-ID: On Mon, Jul 25, 2011 at 1:53 PM, Evan Cheng wrote: > Fix last bits of MC layer issues. llvm-mc doesn't need to initialize > TargetMachine's anymore. Wow, this is fantastic. Do you want me to try asserting that MC code doesn't #include (even transitively) Target code and report places where it still does? (I'm also working on removing a couple of the related kludges to the former target initialization) -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/d93ceab0/attachment.html From nicholas at mxc.ca Mon Jul 25 16:16:04 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 25 Jul 2011 21:16:04 -0000 Subject: [llvm-commits] [llvm] r135973 - /llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Message-ID: <20110725211604.423092A6C12C@llvm.org> Author: nicholas Date: Mon Jul 25 16:16:04 2011 New Revision: 135973 URL: http://llvm.org/viewvc/llvm-project?rev=135973&view=rev Log: Add missing space (this line is no longer pushing the 80-column limit). Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=135973&r1=135972&r2=135973&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Mon Jul 25 16:16:04 2011 @@ -156,7 +156,7 @@ /// class SCCPSolver : public InstVisitor { const TargetData *TD; - SmallPtrSet BBExecutable;// The BBs that are executable. + SmallPtrSet BBExecutable; // The BBs that are executable. DenseMap ValueState; // The state each value is in. /// StructValueState - This maintains ValueState for values that have From evan.cheng at apple.com Mon Jul 25 16:20:25 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 21:20:25 -0000 Subject: [llvm-commits] [llvm] r135974 - in /llvm/trunk: lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/ lib/Target/MBlaze/ lib/Target/MBlaze/MCTargetDesc/ lib/Target/MSP430/ lib/Target/MSP430/MCTargetDesc/ lib/Target/Mips/ lib/Target/Mips/MCTargetDesc/ lib/Target/PowerPC/ lib/Target/PowerPC/MCTargetDesc/ lib/Target/X86/ lib/Target/X86/MCTargetDesc/ tools/llvm-mc/ tools/llvm-objdump/ Message-ID: <20110725212025.3AEB52A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 16:20:24 2011 New Revision: 135974 URL: http://llvm.org/viewvc/llvm-project?rev=135974&view=rev Log: Separate MCInstPrinter registration from AsmPrinter registration. Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Mon Jul 25 16:20:24 2011 @@ -38,7 +38,6 @@ // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetMCs(); - llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Mon Jul 25 16:20:24 2011 @@ -106,7 +106,6 @@ InitializeAllTargetInfos(); InitializeAllTargetMCs(); - InitializeAllAsmPrinters(); InitializeAllAsmParsers(); InitializeAllDisassemblers(); } Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -1815,20 +1815,9 @@ // Target Registry Stuff //===----------------------------------------------------------------------===// -static MCInstPrinter *createARMMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - if (SyntaxVariant == 0) - return new ARMInstPrinter(MAI); - return 0; -} - // Force static initialization. extern "C" void LLVMInitializeARMAsmPrinter() { RegisterAsmPrinter X(TheARMTarget); RegisterAsmPrinter Y(TheThumbTarget); - - TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter); } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,7 @@ #include "ARMMCTargetDesc.h" #include "ARMMCAsmInfo.h" +#include "InstPrinter/ARMInstPrinter.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -150,6 +151,14 @@ return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack); } +static MCInstPrinter *createARMMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + if (SyntaxVariant == 0) + return new ARMInstPrinter(MAI); + return 0; +} + // Force static initialization. extern "C" void LLVMInitializeARMTargetMC() { @@ -186,4 +195,8 @@ // Register the object streamer. TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer); TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter); } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -316,18 +316,7 @@ return I == Pred->end() || !I->getDesc().isBarrier(); } -static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - if (SyntaxVariant == 0) - return new MBlazeInstPrinter(MAI); - return 0; -} - // Force static initialization. extern "C" void LLVMInitializeMBlazeAsmPrinter() { RegisterAsmPrinter X(TheMBlazeTarget); - TargetRegistry::RegisterMCInstPrinter(TheMBlazeTarget, - createMBlazeMCInstPrinter); - } Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,7 @@ #include "MBlazeMCTargetDesc.h" #include "MBlazeMCAsmInfo.h" +#include "InstPrinter/MBlazeInstPrinter.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -91,6 +92,14 @@ return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); } +static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + if (SyntaxVariant == 0) + return new MBlazeInstPrinter(MAI); + return 0; +} + // Force static initialization. extern "C" void LLVMInitializeMBlazeTargetMC() { // Register the MC asm info. @@ -122,4 +131,8 @@ // Register the object streamer TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget, createMCStreamer); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(TheMBlazeTarget, + createMBlazeMCInstPrinter); } Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,7 @@ #include "MSP430MCTargetDesc.h" #include "MSP430MCAsmInfo.h" +#include "InstPrinter/MSP430InstPrinter.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -55,6 +56,14 @@ return X; } +static MCInstPrinter *createMSP430MCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + if (SyntaxVariant == 0) + return new MSP430InstPrinter(MAI); + return 0; +} + extern "C" void LLVMInitializeMSP430TargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(TheMSP430Target); @@ -73,4 +82,8 @@ // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, createMSP430MCSubtargetInfo); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(TheMSP430Target, + createMSP430MCInstPrinter); } Modified: llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -163,17 +163,7 @@ OutStreamer.EmitInstruction(TmpInst); } -static MCInstPrinter *createMSP430MCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - if (SyntaxVariant == 0) - return new MSP430InstPrinter(MAI); - return 0; -} - // Force static initialization. extern "C" void LLVMInitializeMSP430AsmPrinter() { RegisterAsmPrinter X(TheMSP430Target); - TargetRegistry::RegisterMCInstPrinter(TheMSP430Target, - createMSP430MCInstPrinter); } Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,7 @@ #include "MipsMCTargetDesc.h" #include "MipsMCAsmInfo.h" +#include "InstPrinter/MipsInstPrinter.h" #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -74,6 +75,12 @@ return X; } +static MCInstPrinter *createMipsMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + return new MipsInstPrinter(MAI); +} + extern "C" void LLVMInitializeMipsTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo); @@ -95,4 +102,10 @@ // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, createMipsMCSubtargetInfo); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, + createMipsMCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(TheMipselTarget, + createMipsMCInstPrinter); } Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -424,17 +424,7 @@ } // Force static initialization. -static MCInstPrinter *createMipsMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - return new MipsInstPrinter(MAI); -} - extern "C" void LLVMInitializeMipsAsmPrinter() { RegisterAsmPrinter X(TheMipsTarget); RegisterAsmPrinter Y(TheMipselTarget); - - TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, createMipsMCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheMipselTarget, - createMipsMCInstPrinter); } Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,7 @@ #include "PPCMCTargetDesc.h" #include "PPCMCAsmInfo.h" +#include "InstPrinter/PPCInstPrinter.h" #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -101,6 +102,12 @@ return NULL; } +static MCInstPrinter *createPPCMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + return new PPCInstPrinter(MAI, SyntaxVariant); +} + extern "C" void LLVMInitializePowerPCTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo); @@ -135,4 +142,8 @@ // Register the object streamer. TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer); TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter); } Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -679,18 +679,8 @@ return new PPCLinuxAsmPrinter(tm, Streamer); } -static MCInstPrinter *createPPCMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - return new PPCInstPrinter(MAI, SyntaxVariant); -} - - // Force static initialization. extern "C" void LLVMInitializePowerPCAsmPrinter() { TargetRegistry::RegisterAsmPrinter(ThePPC32Target, createPPCAsmPrinterPass); TargetRegistry::RegisterAsmPrinter(ThePPC64Target, createPPCAsmPrinterPass); - - TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter); } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Jul 25 16:20:24 2011 @@ -13,6 +13,8 @@ #include "X86MCTargetDesc.h" #include "X86MCAsmInfo.h" +#include "InstPrinter/X86ATTInstPrinter.h" +#include "InstPrinter/X86IntelInstPrinter.h" #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -381,6 +383,16 @@ return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); } +static MCInstPrinter *createX86MCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI) { + if (SyntaxVariant == 0) + return new X86ATTInstPrinter(MAI); + if (SyntaxVariant == 1) + return new X86IntelInstPrinter(MAI); + return 0; +} + // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { // Register the MC asm info. @@ -422,4 +434,10 @@ createMCStreamer); TargetRegistry::RegisterObjectStreamer(TheX86_64Target, createMCStreamer); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, + createX86MCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(TheX86_64Target, + createX86MCInstPrinter); } Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Mon Jul 25 16:20:24 2011 @@ -708,21 +708,8 @@ // Target Registry Stuff //===----------------------------------------------------------------------===// -static MCInstPrinter *createX86MCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI) { - if (SyntaxVariant == 0) - return new X86ATTInstPrinter(MAI); - if (SyntaxVariant == 1) - return new X86IntelInstPrinter(MAI); - return 0; -} - // Force static initialization. extern "C" void LLVMInitializeX86AsmPrinter() { RegisterAsmPrinter X(TheX86_32Target); RegisterAsmPrinter Y(TheX86_64Target); - - TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,createX86MCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,createX86MCInstPrinter); } Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 16:20:24 2011 @@ -452,14 +452,9 @@ // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetMCs(); - llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); - // Register the target printer for --version. - // FIXME: Remove when we stop initializing the Target(Machine)s above. - cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion); - cl::ParseCommandLineOptions(argc, argv, "llvm machine code playground\n"); TripleName = Triple::normalize(TripleName); Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=135974&r1=135973&r2=135974&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Jul 25 16:20:24 2011 @@ -309,14 +309,9 @@ // Initialize targets and assembly printers/parsers. llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetMCs(); - llvm::InitializeAllAsmPrinters(); llvm::InitializeAllAsmParsers(); llvm::InitializeAllDisassemblers(); - // Register the target printer for --version. - // FIXME: Remove when we stop initializing the Target(Machine)s above. - cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion); - cl::ParseCommandLineOptions(argc, argv, "llvm object file dumper\n"); TripleName = Triple::normalize(TripleName); From rafael.espindola at gmail.com Mon Jul 25 16:20:54 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 25 Jul 2011 21:20:54 -0000 Subject: [llvm-commits] [llvm] r135975 - in /llvm/trunk: include/llvm-c/Target.h lib/Target/Target.cpp Message-ID: <20110725212054.2F7D42A6C12C@llvm.org> Author: rafael Date: Mon Jul 25 16:20:54 2011 New Revision: 135975 URL: http://llvm.org/viewvc/llvm-project?rev=135975&view=rev Log: Add LLVMAddTargetLibraryInfo to the C API. Modified: llvm/trunk/include/llvm-c/Target.h llvm/trunk/lib/Target/Target.cpp Modified: llvm/trunk/include/llvm-c/Target.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Target.h?rev=135975&r1=135974&r2=135975&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Target.h (original) +++ llvm/trunk/include/llvm-c/Target.h Mon Jul 25 16:20:54 2011 @@ -29,6 +29,7 @@ enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian }; typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef; +typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef; typedef struct LLVMStructLayout *LLVMStructLayoutRef; /* Declare all of the target-initialization functions that are available. */ @@ -90,6 +91,11 @@ See the method llvm::PassManagerBase::add. */ void LLVMAddTargetData(LLVMTargetDataRef, LLVMPassManagerRef); +/** Adds target library information to a pass manager. This does not take + ownership of the target library info. + See the method llvm::PassManagerBase::add. */ +void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef, LLVMPassManagerRef); + /** Converts target data to a target layout string. The string must be disposed with LLVMDisposeMessage. See the constructor llvm::TargetData::TargetData. */ @@ -157,6 +163,7 @@ namespace llvm { class TargetData; + class TargetLibraryInfo; inline TargetData *unwrap(LLVMTargetDataRef P) { return reinterpret_cast(P); @@ -165,6 +172,15 @@ inline LLVMTargetDataRef wrap(const TargetData *P) { return reinterpret_cast(const_cast(P)); } + + inline TargetLibraryInfo *unwrap(LLVMTargetLibraryInfoRef P) { + return reinterpret_cast(P); + } + + inline LLVMTargetLibraryInfoRef wrap(const TargetLibraryInfo *P) { + TargetLibraryInfo *X = const_cast(P); + return reinterpret_cast(X); + } } #endif /* defined(__cplusplus) */ Modified: llvm/trunk/lib/Target/Target.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.cpp?rev=135975&r1=135974&r2=135975&view=diff ============================================================================== --- llvm/trunk/lib/Target/Target.cpp (original) +++ llvm/trunk/lib/Target/Target.cpp Mon Jul 25 16:20:54 2011 @@ -17,6 +17,7 @@ #include "llvm/InitializePasses.h" #include "llvm/PassManager.h" #include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetLibraryInfo.h" #include "llvm/LLVMContext.h" #include @@ -39,6 +40,11 @@ unwrap(PM)->add(new TargetData(*unwrap(TD))); } +void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, + LLVMPassManagerRef PM) { + unwrap(PM)->add(new TargetLibraryInfo(*unwrap(TLI))); +} + char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) { std::string StringRep = unwrap(TD)->getStringRepresentation(); return strdup(StringRep.c_str()); From chandlerc at gmail.com Mon Jul 25 16:21:08 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 25 Jul 2011 21:21:08 -0000 Subject: [llvm-commits] [llvm] r135976 - /llvm/trunk/lib/MC/MCMachOStreamer.cpp Message-ID: <20110725212108.3859C2A6C12C@llvm.org> Author: chandlerc Date: Mon Jul 25 16:21:08 2011 New Revision: 135976 URL: http://llvm.org/viewvc/llvm-project?rev=135976&view=rev Log: Add a missing enumerator to this switch. Currently its in the assert-path code, as previously we would have fallen off the end of the function, but please review and let me know if this should go somewhere else. This fixes a Clang warning: lib/MC/MCMachOStreamer.cpp:201:11: error: enumeration value 'MCSA_IndirectSymbol' not handled in switch [-Werror,-Wswitch-enum] switch (Attribute) { ^ 1 error generated. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=135976&r1=135975&r2=135976&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Jul 25 16:21:08 2011 @@ -208,6 +208,7 @@ case MCSA_ELF_TypeNoType: case MCSA_ELF_TypeGnuUniqueObject: case MCSA_Hidden: + case MCSA_IndirectSymbol: case MCSA_Internal: case MCSA_Protected: case MCSA_Weak: From chandlerc at gmail.com Mon Jul 25 16:25:08 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 25 Jul 2011 21:25:08 -0000 Subject: [llvm-commits] [llvm] r135977 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110725212508.5E6BC2A6C12C@llvm.org> Author: chandlerc Date: Mon Jul 25 16:25:07 2011 New Revision: 135977 URL: http://llvm.org/viewvc/llvm-project?rev=135977&view=rev Log: Check in updated CMake dependencies after Evan's latest round of refactorings. Several places that shouldn't have dependend on Target no longer do. Also almost all of the CodeGen dependencies have gone away for the MCDisassembler. Others add reasonable dependencies within the target-specific layers. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=135977&r1=135976&r2=135977&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Mon Jul 25 16:25:07 2011 @@ -1,7 +1,7 @@ -set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMAsmPrinter LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -31,23 +31,23 @@ set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC) set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430Desc LLVMMSP430Info LLVMMipsDesc LLVMMipsInfo LLVMPTXDesc LLVMPTXInfo LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreDesc LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info) +set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsAsmPrinter LLVMMipsInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -55,7 +55,7 @@ set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils) @@ -69,10 +69,10 @@ set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) -set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) -set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86AsmPrinter LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) From evan.cheng at apple.com Mon Jul 25 16:29:26 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 21:29:26 -0000 Subject: [llvm-commits] [llvm] r135978 - in /llvm/trunk/lib/Target/MBlaze: Disassembler/MBlazeDisassembler.cpp MBlazeRegisterInfo.cpp MBlazeRegisterInfo.h MCTargetDesc/MBlazeBaseInfo.h Message-ID: <20110725212926.B0B512A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 16:29:26 2011 New Revision: 135978 URL: http://llvm.org/viewvc/llvm-project?rev=135978&view=rev Log: More MC layering violations. Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=135978&r1=135977&r2=135978&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Mon Jul 25 16:29:26 2011 @@ -60,27 +60,27 @@ }; static unsigned getRD(uint32_t insn) { - if (!MBlazeRegisterInfo::isRegister((insn>>21)&0x1F)) + if (!isMBlazeRegister((insn>>21)&0x1F)) return UNSUPPORTED; - return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>21)&0x1F); + return getMBlazeRegisterNumbering((insn>>21)&0x1F); } static unsigned getRA(uint32_t insn) { - if (!MBlazeRegisterInfo::getRegisterFromNumbering((insn>>16)&0x1F)) + if (!getMBlazeRegisterNumbering((insn>>16)&0x1F)) return UNSUPPORTED; - return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>16)&0x1F); + return getMBlazeRegisterNumbering((insn>>16)&0x1F); } static unsigned getRB(uint32_t insn) { - if (!MBlazeRegisterInfo::getRegisterFromNumbering((insn>>11)&0x1F)) + if (!getMBlazeRegisterNumbering((insn>>11)&0x1F)) return UNSUPPORTED; - return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>11)&0x1F); + return getMBlazeRegisterNumbering((insn>>11)&0x1F); } static int64_t getRS(uint32_t insn) { - if (!MBlazeRegisterInfo::isSpecialRegister(insn&0x3FFF)) + if (!isSpecialMBlazeRegister(insn&0x3FFF)) return UNSUPPORTED; - return MBlazeRegisterInfo::getSpecialRegisterFromNumbering(insn&0x3FFF); + return getSpecialMBlazeRegisterFromNumbering(insn&0x3FFF); } static int64_t getIMM(uint32_t insn) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=135978&r1=135977&r2=135978&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jul 25 16:29:26 2011 @@ -86,57 +86,6 @@ return 0; // Not reached } -unsigned MBlazeRegisterInfo::getSpecialRegisterFromNumbering(unsigned Reg) { - switch (Reg) { - case 0x0000 : return MBlaze::RPC; - case 0x0001 : return MBlaze::RMSR; - case 0x0003 : return MBlaze::REAR; - case 0x0005 : return MBlaze::RESR; - case 0x0007 : return MBlaze::RFSR; - case 0x000B : return MBlaze::RBTR; - case 0x000D : return MBlaze::REDR; - case 0x1000 : return MBlaze::RPID; - case 0x1001 : return MBlaze::RZPR; - case 0x1002 : return MBlaze::RTLBX; - case 0x1003 : return MBlaze::RTLBLO; - case 0x1004 : return MBlaze::RTLBHI; - case 0x2000 : return MBlaze::RPVR0; - case 0x2001 : return MBlaze::RPVR1; - case 0x2002 : return MBlaze::RPVR2; - case 0x2003 : return MBlaze::RPVR3; - case 0x2004 : return MBlaze::RPVR4; - case 0x2005 : return MBlaze::RPVR5; - case 0x2006 : return MBlaze::RPVR6; - case 0x2007 : return MBlaze::RPVR7; - case 0x2008 : return MBlaze::RPVR8; - case 0x2009 : return MBlaze::RPVR9; - case 0x200A : return MBlaze::RPVR10; - case 0x200B : return MBlaze::RPVR11; - default: llvm_unreachable("Unknown register number!"); - } - return 0; // Not reached -} - -bool MBlazeRegisterInfo::isRegister(unsigned Reg) { - return Reg <= 31; -} - -bool MBlazeRegisterInfo::isSpecialRegister(unsigned Reg) { - switch (Reg) { - case 0x0000 : case 0x0001 : case 0x0003 : case 0x0005 : - case 0x0007 : case 0x000B : case 0x000D : case 0x1000 : - case 0x1001 : case 0x1002 : case 0x1003 : case 0x1004 : - case 0x2000 : case 0x2001 : case 0x2002 : case 0x2003 : - case 0x2004 : case 0x2005 : case 0x2006 : case 0x2007 : - case 0x2008 : case 0x2009 : case 0x200A : case 0x200B : - return true; - - default: - return false; - } - return false; // Not reached -} - unsigned MBlazeRegisterInfo::getPICCallReg() { return MBlaze::R20; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=135978&r1=135977&r2=135978&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jul 25 16:29:26 2011 @@ -43,9 +43,6 @@ const TargetInstrInfo &tii); static unsigned getRegisterFromNumbering(unsigned RegEnum); - static unsigned getSpecialRegisterFromNumbering(unsigned RegEnum); - static bool isRegister(unsigned RegEnum); - static bool isSpecialRegister(unsigned RegEnum); /// Get PIC indirect call register static unsigned getPICCallReg(); Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h?rev=135978&r1=135977&r2=135978&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h Mon Jul 25 16:29:26 2011 @@ -78,6 +78,26 @@ }; } +static inline bool isMBlazeRegister(unsigned Reg) { + return Reg <= 31; +} + +static inline bool isSpecialMBlazeRegister(unsigned Reg) { + switch (Reg) { + case 0x0000 : case 0x0001 : case 0x0003 : case 0x0005 : + case 0x0007 : case 0x000B : case 0x000D : case 0x1000 : + case 0x1001 : case 0x1002 : case 0x1003 : case 0x1004 : + case 0x2000 : case 0x2001 : case 0x2002 : case 0x2003 : + case 0x2004 : case 0x2005 : case 0x2006 : case 0x2007 : + case 0x2008 : case 0x2009 : case 0x200A : case 0x200B : + return true; + + default: + return false; + } + return false; // Not reached +} + /// getMBlazeRegisterNumbering - Given the enum value for some register, e.g. /// MBlaze::R0, return the number that it corresponds to (e.g. 0). static inline unsigned getMBlazeRegisterNumbering(unsigned RegEnum) { @@ -143,6 +163,37 @@ return 0; // Not reached } +static inline unsigned getSpecialMBlazeRegisterFromNumbering(unsigned Reg) { + switch (Reg) { + case 0x0000 : return MBlaze::RPC; + case 0x0001 : return MBlaze::RMSR; + case 0x0003 : return MBlaze::REAR; + case 0x0005 : return MBlaze::RESR; + case 0x0007 : return MBlaze::RFSR; + case 0x000B : return MBlaze::RBTR; + case 0x000D : return MBlaze::REDR; + case 0x1000 : return MBlaze::RPID; + case 0x1001 : return MBlaze::RZPR; + case 0x1002 : return MBlaze::RTLBX; + case 0x1003 : return MBlaze::RTLBLO; + case 0x1004 : return MBlaze::RTLBHI; + case 0x2000 : return MBlaze::RPVR0; + case 0x2001 : return MBlaze::RPVR1; + case 0x2002 : return MBlaze::RPVR2; + case 0x2003 : return MBlaze::RPVR3; + case 0x2004 : return MBlaze::RPVR4; + case 0x2005 : return MBlaze::RPVR5; + case 0x2006 : return MBlaze::RPVR6; + case 0x2007 : return MBlaze::RPVR7; + case 0x2008 : return MBlaze::RPVR8; + case 0x2009 : return MBlaze::RPVR9; + case 0x200A : return MBlaze::RPVR10; + case 0x200B : return MBlaze::RPVR11; + default: llvm_unreachable("Unknown register number!"); + } + return 0; // Not reached +} + } // end namespace llvm; #endif From evan.cheng at apple.com Mon Jul 25 16:32:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 21:32:49 -0000 Subject: [llvm-commits] [llvm] r135979 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110725213249.4390B2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 16:32:49 2011 New Revision: 135979 URL: http://llvm.org/viewvc/llvm-project?rev=135979&view=rev Log: Fix more MC layering violations. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135979&r1=135978&r2=135979&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 16:32:49 2011 @@ -153,6 +153,11 @@ }; } // end anonymous namespace +namespace llvm { + // FIXME: TableGen this? + extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc. +} + namespace { /// ARMOperand - Instances of this class represent a parsed ARM machine @@ -971,9 +976,11 @@ SMLoc StartLoc, SMLoc EndLoc) { KindTy Kind = RegisterList; - if (ARM::DPRRegClass.contains(Regs.front().first)) + if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID]. + contains(Regs.front().first)) Kind = DPRRegisterList; - else if (ARM::SPRRegClass.contains(Regs.front().first)) + else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID]. + contains(Regs.front().first)) Kind = SPRRegisterList; ARMOperand *Op = new ARMOperand(Kind); From eli.friedman at gmail.com Mon Jul 25 16:36:45 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 21:36:45 -0000 Subject: [llvm-commits] [llvm] r135980 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/palignr.ll Message-ID: <20110725213645.F0B8C2A6C12C@llvm.org> Author: efriedma Date: Mon Jul 25 16:36:45 2011 New Revision: 135980 URL: http://llvm.org/viewvc/llvm-project?rev=135980&view=rev Log: Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/palignr.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=135980&r1=135979&r2=135980&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 16:36:45 2011 @@ -3075,27 +3075,16 @@ if (i == e) return false; - // Determine if it's ok to perform a palignr with only the LHS, since we - // don't have access to the actual shuffle elements to see if RHS is undef. - bool Unary = Mask[i] < (int)e; - bool NeedsUnary = false; + // Make sure we're shifting in the right direction. + if (Mask[i] <= i) + return false; int s = Mask[i] - i; // Check the rest of the elements to see if they are consecutive. for (++i; i != e; ++i) { int m = Mask[i]; - if (m < 0) - continue; - - Unary = Unary && (m < (int)e); - NeedsUnary = NeedsUnary || (m < s); - - if (NeedsUnary && !Unary) - return false; - if (Unary && m != ((s+i) & (e-1))) - return false; - if (!Unary && m != (s+i)) + if (m >= 0 && m != s+i) return false; } return true; @@ -3631,6 +3620,7 @@ if (Val >= 0) break; } + assert(Val - i > 0 && "PALIGNR imm should be positive"); return (Val - i) * EltSize; } Modified: llvm/trunk/test/CodeGen/X86/palignr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr.ll?rev=135980&r1=135979&r2=135980&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/palignr.ll (original) +++ llvm/trunk/test/CodeGen/X86/palignr.ll Mon Jul 25 16:36:45 2011 @@ -2,6 +2,7 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test1: ; CHECK: pshufd ; CHECK-YONAH: pshufd %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 > @@ -9,6 +10,7 @@ } define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test2: ; CHECK: palignr ; CHECK-YONAH: shufps %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 > @@ -16,43 +18,56 @@ } define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test3: ; CHECK: palignr %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 > ret <4 x i32> %C } define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test4: ; CHECK: palignr %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > ret <4 x i32> %C } define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind { +; CHECK: test5: ; CHECK: palignr %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > ret <4 x float> %C } define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: test6: ; CHECK: palignr %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 > ret <8 x i16> %C } define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: test7: ; CHECK: palignr %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 > ret <8 x i16> %C } -define <8 x i16> @test8(<8 x i16> %A, <8 x i16> %B) nounwind { -; CHECK: palignr - %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 > - ret <8 x i16> %C -} - -define <16 x i8> @test9(<16 x i8> %A, <16 x i8> %B) nounwind { +define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind { +; CHECK: test8: ; CHECK: palignr %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 > ret <16 x i8> %C } + +; Check that we don't do unary (circular on single operand) palignr incorrectly. +; (It is possible, but before this testcase was committed, it was being done +; incorrectly. In particular, one of the operands of the palignr node +; was an UNDEF.) +define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: test9: +; CHECK-NOT: palignr +; CHECK: pshufb + %C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 > + ret <8 x i16> %C +} + From evan.cheng at apple.com Mon Jul 25 16:44:12 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 21:44:12 -0000 Subject: [llvm-commits] [llvm] r135982 - in /llvm/trunk/lib/Target: CBackend/CBackend.cpp CBackend/TargetInfo/CBackendTargetInfo.cpp CppBackend/CPPBackend.cpp CppBackend/TargetInfo/CppBackendTargetInfo.cpp Message-ID: <20110725214412.ED5462A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 16:44:12 2011 New Revision: 135982 URL: http://llvm.org/viewvc/llvm-project?rev=135982&view=rev Log: Move CBackend and CppBackend MC initialization to TargetInfo. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=135982&r1=135981&r2=135982&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Jul 25 16:44:12 2011 @@ -64,8 +64,6 @@ RegisterTargetMachine X(TheCBackendTarget); } -extern "C" void LLVMInitializeCBackendTargetMC() {} - namespace { class CBEMCAsmInfo : public MCAsmInfo { public: Modified: llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp?rev=135982&r1=135981&r2=135982&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp Mon Jul 25 16:44:12 2011 @@ -17,3 +17,5 @@ extern "C" void LLVMInitializeCBackendTargetInfo() { RegisterTarget<> X(TheCBackendTarget, "c", "C backend"); } + +extern "C" void LLVMInitializeCBackendTargetMC() {} Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=135982&r1=135981&r2=135982&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Jul 25 16:44:12 2011 @@ -77,8 +77,6 @@ RegisterTargetMachine X(TheCppBackendTarget); } -extern "C" void LLVMInitializeCppBackendTargetMC() {} - namespace { typedef std::vector TypeList; typedef std::map TypeMap; Modified: llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp?rev=135982&r1=135981&r2=135982&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp Mon Jul 25 16:44:12 2011 @@ -24,3 +24,5 @@ "C++ backend", &CppBackend_TripleMatchQuality); } + +extern "C" void LLVMInitializeCppBackendTargetMC() {} From pichet2000 at gmail.com Mon Jul 25 17:08:28 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Mon, 25 Jul 2011 18:08:28 -0400 Subject: [llvm-commits] [llvm] r135980 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/palignr.ll In-Reply-To: <20110725213645.F0B8C2A6C12C@llvm.org> References: <20110725213645.F0B8C2A6C12C@llvm.org> Message-ID: On Mon, Jul 25, 2011 at 5:36 PM, Eli Friedman wrote: > Author: efriedma > Date: Mon Jul 25 16:36:45 2011 > New Revision: 135980 > > URL: http://llvm.org/viewvc/llvm-project?rev=135980&view=rev > Log: > Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. > > Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. > > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > ? ?llvm/trunk/test/CodeGen/X86/palignr.ll > Hi, this fails on MSVC: 8> Command 1 Stderr: 8> C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/palignr.ll:69:10: error: expected string not found in input 8> ; CHECK: pshufb 8> ^ 8> :101:9: note: scanning from here 8> _test9: # @test9 8> ^ 8> :101:13: note: possible intended match here 8> _test9: # @test9 From evan.cheng at apple.com Mon Jul 25 17:16:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 22:16:37 -0000 Subject: [llvm-commits] [llvm] r135986 - in /llvm/trunk/lib/Target/MBlaze: Disassembler/MBlazeDisassembler.cpp MBlazeISelLowering.cpp MBlazeRegisterInfo.cpp MBlazeRegisterInfo.h MCTargetDesc/MBlazeBaseInfo.h Message-ID: <20110725221637.89E0C2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 17:16:37 2011 New Revision: 135986 URL: http://llvm.org/viewvc/llvm-project?rev=135986&view=rev Log: Refactoring fail. Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=135986&r1=135985&r2=135986&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Mon Jul 25 17:16:37 2011 @@ -62,19 +62,19 @@ static unsigned getRD(uint32_t insn) { if (!isMBlazeRegister((insn>>21)&0x1F)) return UNSUPPORTED; - return getMBlazeRegisterNumbering((insn>>21)&0x1F); + return getMBlazeRegisterFromNumbering((insn>>21)&0x1F); } static unsigned getRA(uint32_t insn) { - if (!getMBlazeRegisterNumbering((insn>>16)&0x1F)) + if (!getMBlazeRegisterFromNumbering((insn>>16)&0x1F)) return UNSUPPORTED; - return getMBlazeRegisterNumbering((insn>>16)&0x1F); + return getMBlazeRegisterFromNumbering((insn>>16)&0x1F); } static unsigned getRB(uint32_t insn) { - if (!getMBlazeRegisterNumbering((insn>>11)&0x1F)) + if (!getMBlazeRegisterFromNumbering((insn>>11)&0x1F)) return UNSUPPORTED; - return getMBlazeRegisterNumbering((insn>>11)&0x1F); + return getMBlazeRegisterFromNumbering((insn>>11)&0x1F); } static int64_t getRS(uint32_t insn) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=135986&r1=135985&r2=135986&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Mon Jul 25 17:16:37 2011 @@ -970,7 +970,7 @@ unsigned StackLoc = Start - Begin + 1; for (; Start <= End; ++Start, ++StackLoc) { - unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start); + unsigned Reg = getMBlazeRegisterFromNumbering(Start); unsigned LiveReg = MF.addLiveIn(Reg, RC); SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=135986&r1=135985&r2=135986&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jul 25 17:16:37 2011 @@ -45,47 +45,6 @@ MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {} -/// getRegisterFromNumbering - Given the enum value for some register, e.g. -/// MBlaze::R0, return the number that it corresponds to (e.g. 0). -unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) { - switch (Reg) { - case 0 : return MBlaze::R0; - case 1 : return MBlaze::R1; - case 2 : return MBlaze::R2; - case 3 : return MBlaze::R3; - case 4 : return MBlaze::R4; - case 5 : return MBlaze::R5; - case 6 : return MBlaze::R6; - case 7 : return MBlaze::R7; - case 8 : return MBlaze::R8; - case 9 : return MBlaze::R9; - case 10 : return MBlaze::R10; - case 11 : return MBlaze::R11; - case 12 : return MBlaze::R12; - case 13 : return MBlaze::R13; - case 14 : return MBlaze::R14; - case 15 : return MBlaze::R15; - case 16 : return MBlaze::R16; - case 17 : return MBlaze::R17; - case 18 : return MBlaze::R18; - case 19 : return MBlaze::R19; - case 20 : return MBlaze::R20; - case 21 : return MBlaze::R21; - case 22 : return MBlaze::R22; - case 23 : return MBlaze::R23; - case 24 : return MBlaze::R24; - case 25 : return MBlaze::R25; - case 26 : return MBlaze::R26; - case 27 : return MBlaze::R27; - case 28 : return MBlaze::R28; - case 29 : return MBlaze::R29; - case 30 : return MBlaze::R30; - case 31 : return MBlaze::R31; - default: llvm_unreachable("Unknown register number!"); - } - return 0; // Not reached -} - unsigned MBlazeRegisterInfo::getPICCallReg() { return MBlaze::R20; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=135986&r1=135985&r2=135986&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jul 25 17:16:37 2011 @@ -42,8 +42,6 @@ MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget, const TargetInstrInfo &tii); - static unsigned getRegisterFromNumbering(unsigned RegEnum); - /// Get PIC indirect call register static unsigned getPICCallReg(); Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h?rev=135986&r1=135985&r2=135986&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h Mon Jul 25 17:16:37 2011 @@ -163,6 +163,47 @@ return 0; // Not reached } +/// getRegisterFromNumbering - Given the enum value for some register, e.g. +/// MBlaze::R0, return the number that it corresponds to (e.g. 0). +static inline unsigned getMBlazeRegisterFromNumbering(unsigned Reg) { + switch (Reg) { + case 0 : return MBlaze::R0; + case 1 : return MBlaze::R1; + case 2 : return MBlaze::R2; + case 3 : return MBlaze::R3; + case 4 : return MBlaze::R4; + case 5 : return MBlaze::R5; + case 6 : return MBlaze::R6; + case 7 : return MBlaze::R7; + case 8 : return MBlaze::R8; + case 9 : return MBlaze::R9; + case 10 : return MBlaze::R10; + case 11 : return MBlaze::R11; + case 12 : return MBlaze::R12; + case 13 : return MBlaze::R13; + case 14 : return MBlaze::R14; + case 15 : return MBlaze::R15; + case 16 : return MBlaze::R16; + case 17 : return MBlaze::R17; + case 18 : return MBlaze::R18; + case 19 : return MBlaze::R19; + case 20 : return MBlaze::R20; + case 21 : return MBlaze::R21; + case 22 : return MBlaze::R22; + case 23 : return MBlaze::R23; + case 24 : return MBlaze::R24; + case 25 : return MBlaze::R25; + case 26 : return MBlaze::R26; + case 27 : return MBlaze::R27; + case 28 : return MBlaze::R28; + case 29 : return MBlaze::R29; + case 30 : return MBlaze::R30; + case 31 : return MBlaze::R31; + default: llvm_unreachable("Unknown register number!"); + } + return 0; // Not reached +} + static inline unsigned getSpecialMBlazeRegisterFromNumbering(unsigned Reg) { switch (Reg) { case 0x0000 : return MBlaze::RPC; From atrick at apple.com Mon Jul 25 17:17:48 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 25 Jul 2011 22:17:48 -0000 Subject: [llvm-commits] [llvm] r135988 - /llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Message-ID: <20110725221748.20A132A6C12C@llvm.org> Author: atrick Date: Mon Jul 25 17:17:47 2011 New Revision: 135988 URL: http://llvm.org/viewvc/llvm-project?rev=135988&view=rev Log: Add clarifying comments for the new arguments to UnrollLoop. Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=135988&r1=135987&r2=135988&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Mon Jul 25 17:17:47 2011 @@ -106,6 +106,18 @@ /// branch instruction. However, if the trip count (and multiple) are not known, /// loop unrolling will mostly produce more code that is no faster. /// +/// TripCount is generally defined as the number of times the loop header +/// executes. UnrollLoop relaxes the definition to permit early exits: here +/// TripCount is the iteration on which control exits LatchBlock if no early +/// exits were taken. Note that UnrollLoop assumes that the loop counter test +/// terminates LatchBlock in order to remove unnecesssary instances of the +/// test. In other words, control may exit the loop prior to TripCount +/// iterations via an early branch, but control may not exit the loop from the +/// LatchBlock's terminator prior to TripCount iterations. +/// +/// Similarly, TripMultiple divides the number of times that the LatchBlock may +/// execute without exiting the loop. +/// /// The LoopInfo Analysis that is passed will be kept consistent. /// /// If a LoopPassManager is passed in, and the loop is fully removed, it will be From grosbach at apple.com Mon Jul 25 17:20:28 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 22:20:28 -0000 Subject: [llvm-commits] [llvm] r135990 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s Message-ID: <20110725222028.4BD5F2A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 17:20:28 2011 New Revision: 135990 URL: http://llvm.org/viewvc/llvm-project?rev=135990&view=rev Log: ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 17:20:28 2011 @@ -395,12 +395,18 @@ } // shift_imm: An integer that encodes a shift amount and the type of shift -// (currently either asr or lsl) using the same encoding used for the -// immediates in so_reg operands. -def ShifterAsmOperand : AsmOperandClass { let Name = "Shifter"; } +// (asr or lsl). The 6-bit immediate encodes as: +// {5} 0 ==> lsl +// 1 asr +// {4-0} imm5 shift amount. +// asr #32 encoded as imm5 == 0. +def ShifterImmAsmOperand : AsmOperandClass { + let Name = "ShifterImm"; + let ParserMethod = "parseShifterImm"; +} def shift_imm : Operand { let PrintMethod = "printShiftImmOperand"; - let ParserMatchClass = ShifterAsmOperand; + let ParserMatchClass = ShifterImmAsmOperand; } // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. @@ -2688,8 +2694,8 @@ // Signed/Unsigned saturate -- for disassembly only -def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$a, shift_imm:$sh), - SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh", []> { +def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh), + SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { bits<4> Rd; bits<5> sat_imm; bits<4> Rn; @@ -2698,8 +2704,8 @@ let Inst{5-4} = 0b01; let Inst{20-16} = sat_imm; let Inst{15-12} = Rd; - let Inst{11-7} = sh{7-3}; - let Inst{6} = sh{0}; + let Inst{11-7} = sh{4-0}; + let Inst{6} = sh{5}; let Inst{3-0} = Rn; } @@ -2715,9 +2721,8 @@ let Inst{3-0} = Rn; } -def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh), - SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh", - [/* For disassembly only; pattern left blank */]> { +def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh), + SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { bits<4> Rd; bits<5> sat_imm; bits<4> Rn; @@ -2725,8 +2730,8 @@ let Inst{27-21} = 0b0110111; let Inst{5-4} = 0b01; let Inst{15-12} = Rd; - let Inst{11-7} = sh{7-3}; - let Inst{6} = sh{0}; + let Inst{11-7} = sh{4-0}; + let Inst{6} = sh{5}; let Inst{20-16} = sat_imm; let Inst{3-0} = Rn; } @@ -4278,3 +4283,7 @@ def : InstAlias<"rsc${s}${p} $Rdn, $shift", (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, Requires<[IsARM]>; + +// SSAT optional shift operand. +def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", + (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jul 25 17:20:28 2011 @@ -1918,8 +1918,8 @@ let Inst{11-8} = Rd; let Inst{19-16} = Rn; - let Inst{4-0} = sat_imm{4-0}; - let Inst{21} = sh{6}; + let Inst{4-0} = sat_imm; + let Inst{21} = sh{5}; let Inst{14-12} = sh{4-2}; let Inst{7-6} = sh{1-0}; } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 17:20:28 2011 @@ -127,6 +127,7 @@ return parsePKHImm(O, "asr", 1, 32); } OperandMatchResultTy parseSetEndImm(SmallVectorImpl&); + OperandMatchResultTy parseShifterImm(SmallVectorImpl&); // Asm Match Converter Methods bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, @@ -179,7 +180,7 @@ SPRRegisterList, ShiftedRegister, ShiftedImmediate, - Shifter, + ShifterImmediate, Token } Kind; @@ -239,9 +240,9 @@ } Mem; struct { - ARM_AM::ShiftOpc ShiftTy; + bool isASR; unsigned Imm; - } Shift; + } ShifterImm; struct { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; @@ -296,8 +297,8 @@ case ProcIFlags: IFlags = o.IFlags; break; - case Shifter: - Shift = o.Shift; + case ShifterImmediate: + ShifterImm = o.ShifterImm; break; case ShiftedRegister: RegShiftedReg = o.RegShiftedReg; @@ -505,7 +506,7 @@ bool isToken() const { return Kind == Token; } bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } bool isMemory() const { return Kind == Memory; } - bool isShifter() const { return Kind == Shifter; } + bool isShifterImm() const { return Kind == ShifterImmediate; } bool isRegShiftedReg() const { return Kind == ShiftedRegister; } bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } bool isMemMode2() const { @@ -656,10 +657,10 @@ } - void addShifterOperands(MCInst &Inst, unsigned N) const { + void addShifterImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::CreateImm( - ARM_AM::getSORegOpc(Shift.ShiftTy, 0))); + Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | + ShifterImm.Imm)); } void addRegListOperands(MCInst &Inst, unsigned N) const { @@ -962,10 +963,11 @@ return Op; } - static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy, + static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, SMLoc S, SMLoc E) { - ARMOperand *Op = new ARMOperand(Shifter); - Op->Shift.ShiftTy = ShTy; + ARMOperand *Op = new ARMOperand(ShifterImmediate); + Op->ShifterImm.isASR = isASR; + Op->ShifterImm.Imm = Imm; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -1127,8 +1129,9 @@ case Register: OS << ""; break; - case Shifter: - OS << ""; + case ShifterImmediate: + OS << ""; break; case ShiftedRegister: OS << " &Operands) { + const AsmToken &Tok = Parser.getTok(); + SMLoc S = Tok.getLoc(); + if (Tok.isNot(AsmToken::Identifier)) { + Error(S, "shift operator 'asr' or 'lsl' expected"); + return MatchOperand_ParseFail; + } + StringRef ShiftName = Tok.getString(); + bool isASR; + if (ShiftName == "lsl" || ShiftName == "LSL") + isASR = false; + else if (ShiftName == "asr" || ShiftName == "ASR") + isASR = true; + else { + Error(S, "shift operator 'asr' or 'lsl' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat the operator. + + // A '#' and a shift amount. + if (Parser.getTok().isNot(AsmToken::Hash)) { + Error(Parser.getTok().getLoc(), "'#' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat hash token. + + const MCExpr *ShiftAmount; + SMLoc E = Parser.getTok().getLoc(); + if (getParser().ParseExpression(ShiftAmount)) { + Error(E, "malformed shift expression"); + return MatchOperand_ParseFail; + } + const MCConstantExpr *CE = dyn_cast(ShiftAmount); + if (!CE) { + Error(E, "shift amount must be an immediate"); + return MatchOperand_ParseFail; + } + + int64_t Val = CE->getValue(); + if (isASR) { + // Shift amount must be in [1,32] + if (Val < 1 || Val > 32) { + Error(E, "'asr' shift amount must be in range [1,32]"); + return MatchOperand_ParseFail; + } + // asr #32 encoded as asr #0. + if (Val == 32) Val = 0; + } else { + // Shift amount must be in [1,32] + if (Val < 0 || Val > 31) { + Error(E, "'lsr' shift amount must be in range [0,31]"); + return MatchOperand_ParseFail; + } + } + + E = Parser.getTok().getLoc(); + Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); + + return MatchOperand_Success; +} + /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Jul 25 17:20:28 2011 @@ -1732,17 +1732,11 @@ decodeRm(insn)))); if (NumOpsAdded == 4) { - ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl); + // Inst{6} encodes the shift type. + bool isASR = slice(insn, 6, 6); // Inst{11-7} encodes the imm5 shift amount. unsigned ShAmt = slice(insn, 11, 7); - if (ShAmt == 0) { - // A8.6.183. Possible ASR shift amount of 32... - if (Opc == ARM_AM::asr) - ShAmt = 32; - else - Opc = ARM_AM::no_shift; - } - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt))); + MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt)); } return true; } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Mon Jul 25 17:20:28 2011 @@ -1615,17 +1615,11 @@ decodeRn(insn)))); if (NumOpsAdded == 4) { - ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ? - ARM_AM::asr : ARM_AM::lsl); - // Inst{14-12:7-6} encodes the imm5 shift amount. - unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6); - if (ShAmt == 0) { - if (Opc == ARM_AM::asr) - ShAmt = 32; - else - Opc = ARM_AM::no_shift; - } - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt))); + // Inst{6} encodes the shift type. + bool isASR = slice(insn, 6, 6); + // Inst{11-7} encodes the imm5 shift amount. + unsigned ShAmt = slice(insn, 11, 7); + MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt)); } return true; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Jul 25 17:20:28 2011 @@ -450,20 +450,12 @@ void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned ShiftOp = MI->getOperand(OpNum).getImm(); - ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); - switch (Opc) { - case ARM_AM::no_shift: - return; - case ARM_AM::lsl: - O << ", lsl #"; - break; - case ARM_AM::asr: - O << ", asr #"; - break; - default: - assert(0 && "unexpected shift opcode for shift immediate operand"); - } - O << ARM_AM::getSORegOffset(ShiftOp); + bool isASR = (ShiftOp & (1 << 5)) != 0; + unsigned Amt = ShiftOp & 0x1f; + if (isASR) + O << ", asr #" << (Amt == 0 ? 32 : Amt); + else if (Amt) + O << ", lsl #" << Amt; } void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Jul 25 17:20:28 2011 @@ -1614,6 +1614,23 @@ @------------------------------------------------------------------------------ @ FIXME: SRS @------------------------------------------------------------------------------ + + + at ------------------------------------------------------------------------------ +@ SSAT + at ------------------------------------------------------------------------------ + ssat r8, #1, r10 + ssat r8, #1, r10, lsl #0 + ssat r8, #1, r10, lsl #31 + ssat r8, #1, r10, asr #32 + ssat r8, #1, r10, asr #1 + +@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x9a,0x8f,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6] + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135990&r1=135989&r2=135990&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Mon Jul 25 17:20:28 2011 @@ -160,3 +160,43 @@ @ CHECK: error: 'be' or 'le' operand expected @ CHECK: setend 1 @ CHECK: ^ + + + @ Out of range immediates and bad shift types for SSAT + ssat r8, #0, r10, lsl #8 + ssat r8, #33, r10, lsl #8 + ssat r8, #1, r10, lsl #-1 + ssat r8, #1, r10, lsl #32 + ssat r8, #1, r10, asr #0 + ssat r8, #1, r10, asr #33 + ssat r8, #1, r10, lsr #5 + ssat r8, #1, r10, lsl fred + ssat r8, #1, r10, lsl #fred + +@ CHECK: error: invalid operand for instruction +@ CHECK: ssat r8, #0, r10, lsl #8 +@ CHECK: ^ +@ CHECK: error: invalid operand for instruction +@ CHECK: ssat r8, #33, r10, lsl #8 +@ CHECK: ^ +@ CHECK: error: 'lsr' shift amount must be in range [0,31] +@ CHECK: ssat r8, #1, r10, lsl #-1 +@ CHECK: ^ +@ CHECK: error: 'lsr' shift amount must be in range [0,31] +@ CHECK: ssat r8, #1, r10, lsl #32 +@ CHECK: ^ +@ CHECK: error: 'asr' shift amount must be in range [1,32] +@ CHECK: ssat r8, #1, r10, asr #0 +@ CHECK: ^ +@ CHECK: error: 'asr' shift amount must be in range [1,32] +@ CHECK: ssat r8, #1, r10, asr #33 +@ CHECK: ^ +@ CHECK: error: shift operator 'asr' or 'lsl' expected +@ CHECK: ssat r8, #1, r10, lsr #5 +@ CHECK: ^ +@ CHECK: error: '#' expected +@ CHECK: ssat r8, #1, r10, lsl fred +@ CHECK: ^ +@ CHECK: error: shift amount must be an immediate +@ CHECK: ssat r8, #1, r10, lsl #fred +@ CHECK: ^ From grosser at fim.uni-passau.de Mon Jul 25 17:22:22 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 25 Jul 2011 22:22:22 -0000 Subject: [llvm-commits] [zorg] r135991 - /zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Message-ID: <20110725222222.744C52A6C12C@llvm.org> Author: grosser Date: Mon Jul 25 17:22:22 2011 New Revision: 135991 URL: http://llvm.org/viewvc/llvm-project?rev=135991&view=rev Log: Use http to checkout git repostitories It seems the git checkout from repo.or.cz does not work very reliable. At least manually the http checkout works better. Hopefully this fixes the unreliable polly builder. Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=135991&r1=135990&r2=135991&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Mon Jul 25 17:22:22 2011 @@ -15,13 +15,13 @@ global f # Get Cloog - f.addStep(Git(repourl='git://repo.or.cz/cloog.git', + f.addStep(Git(repourl='http://repo.or.cz/r/cloog.git', mode='update', workdir=cloog_srcdir, alwaysUseLatest=True, retry=(30, 10))) # Get isl - f.addStep(Git(repourl='git://repo.or.cz/isl.git', + f.addStep(Git(repourl='http://repo.or.cz/r/isl.git', mode='update', workdir=isl_srcdir, alwaysUseLatest=True, From jstaszak at apple.com Mon Jul 25 17:24:51 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 25 Jul 2011 22:24:51 -0000 Subject: [llvm-commits] [llvm] r135992 - in /llvm/trunk: include/llvm/Support/BlockFrequency.h lib/Support/BlockFrequency.cpp lib/Support/CMakeLists.txt Message-ID: <20110725222451.5972B2A6C12C@llvm.org> Author: kuba Date: Mon Jul 25 17:24:51 2011 New Revision: 135992 URL: http://llvm.org/viewvc/llvm-project?rev=135992&view=rev Log: Add BlockFrequency class. Added: llvm/trunk/include/llvm/Support/BlockFrequency.h llvm/trunk/lib/Support/BlockFrequency.cpp Modified: llvm/trunk/lib/Support/CMakeLists.txt Added: llvm/trunk/include/llvm/Support/BlockFrequency.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BlockFrequency.h?rev=135992&view=auto ============================================================================== --- llvm/trunk/include/llvm/Support/BlockFrequency.h (added) +++ llvm/trunk/include/llvm/Support/BlockFrequency.h Mon Jul 25 17:24:51 2011 @@ -0,0 +1,64 @@ +//===-------- BlockFrequency.h - Block Frequency Wrapper --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements Block Frequency class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_BLOCKFREQUENCY_H +#define LLVM_SUPPORT_BLOCKFREQUENCY_H + +namespace llvm { + +class raw_ostream; +class BranchProbability; + +// This class represents Block Frequency as a 64-bit value. +class BlockFrequency { + + uint64_t Frequency; + + static void mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]); + static uint64_t div96bit(uint64_t W[2], uint32_t D); + +public: + BlockFrequency(uint64_t Freq = 0) : Frequency(Freq) { } + + uint64_t getFrequency() const { return Frequency; } + + BlockFrequency &operator*=(const BranchProbability &Prob); + const BlockFrequency operator*(const BranchProbability &Prob) const; + + BlockFrequency &operator+=(const BlockFrequency &Freq); + const BlockFrequency operator+(const BlockFrequency &Freq) const; + + bool operator<(const BlockFrequency &RHS) const { + return Frequency < RHS.Frequency; + } + + bool operator<=(const BlockFrequency &RHS) const { + return Frequency <= RHS.Frequency; + } + + bool operator>(const BlockFrequency &RHS) const { + return Frequency > RHS.Frequency; + } + + bool operator>=(const BlockFrequency &RHS) const { + return Frequency >= RHS.Frequency; + } + + void print(raw_ostream &OS) const; +}; + +raw_ostream &operator<<(raw_ostream &OS, const BlockFrequency &Freq); + +} + +#endif Added: llvm/trunk/lib/Support/BlockFrequency.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=135992&view=auto ============================================================================== --- llvm/trunk/lib/Support/BlockFrequency.cpp (added) +++ llvm/trunk/lib/Support/BlockFrequency.cpp Mon Jul 25 17:24:51 2011 @@ -0,0 +1,120 @@ +//====--------------- lib/Support/BlockFrequency.cpp -----------*- C++ -*-====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements Block Frequency class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/BranchProbability.h" +#include "llvm/Support/BlockFrequency.h" +#include "llvm/Support/raw_ostream.h" +#include + +using namespace llvm; + +/// mult96bit - Multiply FREQ by N and store result in W array. +void BlockFrequency::mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]) { + uint64_t u0 = freq & UINT32_MAX; + uint64_t u1 = freq >> 32; + + // Represent 96-bit value as w[2]:w[1]:w[0]; + uint32_t w[3] = { 0, 0, 0 }; + + uint64_t t = u0 * N; + uint64_t k = t >> 32; + w[0] = t; + t = u1 * N + k; + w[1] = t; + w[2] = t >> 32; + + // W[1] - higher bits. + // W[0] - lower bits. + W[0] = w[0] + ((uint64_t) w[1] << 32); + W[1] = w[2]; +} + + +/// div96bit - Divide 96-bit value stored in W array by D. Return 64-bit frequency. +uint64_t BlockFrequency::div96bit(uint64_t W[2], uint32_t D) { + uint64_t y = W[0]; + uint64_t x = W[1]; + + for (int i = 1; i <= 64; ++i) { + uint32_t t = (int)x >> 31; + x = (x << 1) | (y >> 63); + y = y << 1; + if ((x | t) >= D) { + x -= D; + ++y; + } + } + + return y; +} + +BlockFrequency &BlockFrequency::operator*=(const BranchProbability &Prob) { + uint32_t n = Prob.getNumerator(); + uint32_t d = Prob.getDenominator(); + + assert(n <= d && "Probability must be less or equal to 1."); + + // If we can overflow use 96-bit operations. + if (n > 0 && Frequency > UINT64_MAX / n) { + // 96-bit value represented as W[1]:W[0]. + uint64_t W[2]; + + // Probability is less or equal to 1 which means that results must fit + // 64-bit. + mult96bit(Frequency, n, W); + Frequency = div96bit(W, d); + return *this; + } + + Frequency *= n; + Frequency /= d; + return *this; +} + +const BlockFrequency +BlockFrequency::operator*(const BranchProbability &Prob) const { + BlockFrequency Freq(Frequency); + Freq *= Prob; + return Freq; +} + +BlockFrequency &BlockFrequency::operator+=(const BlockFrequency &Freq) { + uint64_t Before = Freq.Frequency; + Frequency += Freq.Frequency; + + // If overflow, set frequency to the maximum value. + if (Frequency < Before) + Frequency = UINT64_MAX; + + return *this; +} + +const BlockFrequency +BlockFrequency::operator+(const BlockFrequency &Prob) const { + BlockFrequency Freq(Frequency); + Freq += Prob; + return Freq; +} + +void BlockFrequency::print(raw_ostream &OS) const { + OS << Frequency; +} + +namespace llvm { + +raw_ostream &operator<<(raw_ostream &OS, const BlockFrequency &Freq) { + Freq.print(OS); + return OS; +} + +} Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=135992&r1=135991&r2=135992&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Mon Jul 25 17:24:51 2011 @@ -9,6 +9,7 @@ APInt.cpp APSInt.cpp Allocator.cpp + BlockFrequency.cpp BranchProbability.cpp circular_raw_ostream.cpp CommandLine.cpp From eli.friedman at gmail.com Mon Jul 25 17:25:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 22:25:42 -0000 Subject: [llvm-commits] [llvm] r135993 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/extractelement-load.ll Message-ID: <20110725222543.056852A6C12C@llvm.org> Author: efriedma Date: Mon Jul 25 17:25:42 2011 New Revision: 135993 URL: http://llvm.org/viewvc/llvm-project?rev=135993&view=rev Log: Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/test/CodeGen/X86/extractelement-load.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=135993&r1=135992&r2=135993&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jul 25 17:25:42 2011 @@ -6896,7 +6896,7 @@ // If Idx was -1 above, Elt is going to be -1, so just return undef. if (Elt == -1) - return DAG.getUNDEF(LN0->getBasePtr().getValueType()); + return DAG.getUNDEF(LVT); unsigned Align = LN0->getAlignment(); if (NewLoad) { Modified: llvm/trunk/test/CodeGen/X86/extractelement-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractelement-load.ll?rev=135993&r1=135992&r2=135993&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/extractelement-load.ll (original) +++ llvm/trunk/test/CodeGen/X86/extractelement-load.ll Mon Jul 25 17:25:42 2011 @@ -1,9 +1,25 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd -; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd +; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s define i32 @t(<2 x i64>* %val) nounwind { +; CHECK: t: +; CHECK-NOT: movd +; CHECK: movl 8( +; CHECK-NEXT: ret %tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1] %tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1] %tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; [#uses=1] ret i32 %tmp4 } + +; Case where extractelement of load ends up as undef. +; (Making sure this doesn't crash.) +define i32 @t2(<8 x i32>* %xp) { +; CHECK: t2: +; CHECK: ret + %x = load <8 x i32>* %xp + %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> + %y = extractelement <8 x i32> %Shuff68, i32 0 + ret i32 %y +} From jstaszak at apple.com Mon Jul 25 17:27:42 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 25 Jul 2011 22:27:42 -0000 Subject: [llvm-commits] [llvm] r135994 - in /llvm/trunk: include/llvm/Support/BranchProbability.h lib/Support/BranchProbability.cpp Message-ID: <20110725222743.00E932A6C12C@llvm.org> Author: kuba Date: Mon Jul 25 17:27:42 2011 New Revision: 135994 URL: http://llvm.org/viewvc/llvm-project?rev=135994&view=rev Log: BranchProbability::print returns void now. Modified: llvm/trunk/include/llvm/Support/BranchProbability.h llvm/trunk/lib/Support/BranchProbability.cpp Modified: llvm/trunk/include/llvm/Support/BranchProbability.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=135994&r1=135993&r2=135994&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/BranchProbability.h (original) +++ llvm/trunk/include/llvm/Support/BranchProbability.h Mon Jul 25 17:27:42 2011 @@ -40,7 +40,7 @@ return BranchProbability(D - N, D); } - raw_ostream &print(raw_ostream &OS) const; + void print(raw_ostream &OS) const; void dump() const; }; Modified: llvm/trunk/lib/Support/BranchProbability.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BranchProbability.cpp?rev=135994&r1=135993&r2=135994&view=diff ============================================================================== --- llvm/trunk/lib/Support/BranchProbability.cpp (original) +++ llvm/trunk/lib/Support/BranchProbability.cpp Mon Jul 25 17:27:42 2011 @@ -24,9 +24,8 @@ D = d; } -raw_ostream &BranchProbability::print(raw_ostream &OS) const { +void BranchProbability::print(raw_ostream &OS) const { OS << N << " / " << D << " = " << ((double)N / D); - return OS; } void BranchProbability::dump() const { From eli.friedman at gmail.com Mon Jul 25 17:28:51 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 22:28:51 -0000 Subject: [llvm-commits] [llvm] r135995 - /llvm/trunk/test/CodeGen/X86/palignr.ll Message-ID: <20110725222851.DED672A6C12C@llvm.org> Author: efriedma Date: Mon Jul 25 17:28:51 2011 New Revision: 135995 URL: http://llvm.org/viewvc/llvm-project?rev=135995&view=rev Log: Attempt to fix test failure reported on llvm-commits. Modified: llvm/trunk/test/CodeGen/X86/palignr.ll Modified: llvm/trunk/test/CodeGen/X86/palignr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr.ll?rev=135995&r1=135994&r2=135995&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/palignr.ll (original) +++ llvm/trunk/test/CodeGen/X86/palignr.ll Mon Jul 25 17:28:51 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=core2 -mattr=+ssse3 | FileCheck %s ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { From eli.friedman at gmail.com Mon Jul 25 17:29:35 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 15:29:35 -0700 Subject: [llvm-commits] [llvm] r135980 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/palignr.ll In-Reply-To: References: <20110725213645.F0B8C2A6C12C@llvm.org> Message-ID: On Mon, Jul 25, 2011 at 3:08 PM, Francois Pichet wrote: > On Mon, Jul 25, 2011 at 5:36 PM, Eli Friedman wrote: >> Author: efriedma >> Date: Mon Jul 25 16:36:45 2011 >> New Revision: 135980 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=135980&view=rev >> Log: >> Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. >> >> Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. >> >> >> Modified: >> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> ? ?llvm/trunk/test/CodeGen/X86/palignr.ll >> > > Hi, this fails on MSVC: > > 8> ?Command 1 Stderr: > 8> ?C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/palignr.ll:69:10: error: > expected string not found in input > 8> ?; CHECK: pshufb > 8> ? ? ? ? ? ^ > 8> ?:101:9: note: scanning from here > 8> ?_test9: # @test9 > 8> ? ? ? ? ?^ > 8> ?:101:13: note: possible intended match here > 8> ?_test9: # @test9 > Does 135995 help? -Eli From benny.kra at googlemail.com Mon Jul 25 17:30:00 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 25 Jul 2011 22:30:00 -0000 Subject: [llvm-commits] [llvm] r135996 - /llvm/trunk/lib/Target/X86/README.txt Message-ID: <20110725223000.D0D782A6C12C@llvm.org> Author: d0k Date: Mon Jul 25 17:30:00 2011 New Revision: 135996 URL: http://llvm.org/viewvc/llvm-project?rev=135996&view=rev Log: Add a note about efficient codegen for binary log. Modified: llvm/trunk/lib/Target/X86/README.txt Modified: llvm/trunk/lib/Target/X86/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=135996&r1=135995&r2=135996&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README.txt (original) +++ llvm/trunk/lib/Target/X86/README.txt Mon Jul 25 17:30:00 2011 @@ -2066,3 +2066,51 @@ //===---------------------------------------------------------------------===// +unsigned log2(unsigned x) { + return x > 1 ? 32-__builtin_clz(x-1) : 0; +} + +generates (x86_64): + xorl %eax, %eax + cmpl $2, %edi + jb LBB0_2 +## BB#1: + decl %edi + movl $63, %eax + bsrl %edi, %ecx + cmovel %eax, %ecx + xorl $31, %ecx + movl $32, %eax + subl %ecx, %eax +LBB0_2: + ret + +The cmov and the early test are redundant: + xorl %eax, %eax + cmpl $2, %edi + jb LBB0_2 +## BB#1: + decl %edi + bsrl %edi, %ecx + xorl $31, %ecx + movl $32, %eax + subl %ecx, %eax +LBB0_2: + ret + +If we want to get really fancy we could use some two's complement magic: + xorl %eax, %eax + cmpl $2, %edi + jb LBB0_2 +## BB#1: + decl %edi + bsrl %edi, %ecx + xorl $-32, %ecx + leal 33(%ecx), %eax +LBB0_2: + ret + +This is only useful on targets that can't encode the first operand of a sub +directly. The rule is C1 - (X^C2) -> (C1+1) + (X^~C2). + +//===---------------------------------------------------------------------===// From evan.cheng at apple.com Mon Jul 25 17:40:38 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 15:40:38 -0700 Subject: [llvm-commits] [llvm] r135963 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/MC/MCDisassembler/EDDisassembler.cpp lib/MC/MCDisassembler/EDDisassembler.h lib/Target/ARM/AsmParser/ARMAsmLexer.cpp lib/Target/MBlaze/AsmParser/MBlazeAsmLex In-Reply-To: References: Message-ID: <2A9120B7-4FF6-4200-9CFE-AA6BF1A5044F@apple.com> On Jul 25, 2011, at 2:16 PM, Chandler Carruth wrote: > On Mon, Jul 25, 2011 at 1:53 PM, Evan Cheng wrote: > Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore. > > Wow, this is fantastic. > > Do you want me to try asserting that MC code doesn't #include (even transitively) Target code and report places where it still does? > > (I'm also working on removing a couple of the related kludges to the former target initialization) That would be great. Thanks. One more thing. Does anyone know why llvm-mc is still linking in CodeGen? I've manually verified it is not necessary. It would be nice if we can fix this and make sure it is not violated in the future. Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/25dab795/attachment.html From pichet2000 at gmail.com Mon Jul 25 17:43:41 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Mon, 25 Jul 2011 18:43:41 -0400 Subject: [llvm-commits] [llvm] r135980 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/palignr.ll In-Reply-To: References: <20110725213645.F0B8C2A6C12C@llvm.org> Message-ID: On Mon, Jul 25, 2011 at 6:29 PM, Eli Friedman wrote: > On Mon, Jul 25, 2011 at 3:08 PM, Francois Pichet wrote: >> On Mon, Jul 25, 2011 at 5:36 PM, Eli Friedman wrote: >>> Author: efriedma >>> Date: Mon Jul 25 16:36:45 2011 >>> New Revision: 135980 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=135980&view=rev >>> Log: >>> Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. >>> >>> Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. >>> >>> >>> Modified: >>> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>> ? ?llvm/trunk/test/CodeGen/X86/palignr.ll >>> >> >> Hi, this fails on MSVC: >> >> 8> ?Command 1 Stderr: >> 8> ?C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/palignr.ll:69:10: error: >> expected string not found in input >> 8> ?; CHECK: pshufb >> 8> ? ? ? ? ? ^ >> 8> ?:101:9: note: scanning from here >> 8> ?_test9: # @test9 >> 8> ? ? ? ? ?^ >> 8> ?:101:13: note: possible intended match here >> 8> ?_test9: # @test9 >> > > Does 135995 help? > yes thanks. From stoklund at 2pi.dk Mon Jul 25 17:44:26 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 25 Jul 2011 15:44:26 -0700 Subject: [llvm-commits] [llvm] r135992 - in /llvm/trunk: include/llvm/Support/BlockFrequency.h lib/Support/BlockFrequency.cpp lib/Support/CMakeLists.txt In-Reply-To: <20110725222451.5972B2A6C12C@llvm.org> References: <20110725222451.5972B2A6C12C@llvm.org> Message-ID: <858EB2D4-C6BF-435A-B932-4AF503AEB648@2pi.dk> On Jul 25, 2011, at 3:24 PM, Jakub Staszak wrote: > --- llvm/trunk/include/llvm/Support/BlockFrequency.h (added) > +++ llvm/trunk/include/llvm/Support/BlockFrequency.h Mon Jul 25 17:24:51 2011 > @@ -0,0 +1,64 @@ > + static void mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]); > + static uint64_t div96bit(uint64_t W[2], uint32_t D); These functions should not be in the header, they can be static functions in the .cpp file. > +/// div96bit - Divide 96-bit value stored in W array by D. Return 64-bit frequency. > +uint64_t BlockFrequency::div96bit(uint64_t W[2], uint32_t D) { > + uint64_t y = W[0]; > + uint64_t x = W[1]; > + > + for (int i = 1; i <= 64; ++i) { > + uint32_t t = (int)x >> 31; > + x = (x << 1) | (y >> 63); > + y = y << 1; > + if ((x | t) >= D) { > + x -= D; > + ++y; > + } > + } > + > + return y; > +} There has to be a faster way to divide two numbers than this. Please also compare the performance of these routines to the same computations in floating point. /jakob From evan.cheng at apple.com Mon Jul 25 17:52:04 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 22:52:04 -0000 Subject: [llvm-commits] [llvm] r135998 - in /llvm/trunk/include/llvm/MC: TargetAsmBackend.h TargetAsmLexer.h TargetAsmParser.h Message-ID: <20110725225204.9787C2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 17:52:04 2011 New Revision: 135998 URL: http://llvm.org/viewvc/llvm-project?rev=135998&view=rev Log: Fix include guards. Modified: llvm/trunk/include/llvm/MC/TargetAsmBackend.h llvm/trunk/include/llvm/MC/TargetAsmLexer.h llvm/trunk/include/llvm/MC/TargetAsmParser.h Modified: llvm/trunk/include/llvm/MC/TargetAsmBackend.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmBackend.h?rev=135998&r1=135997&r2=135998&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmBackend.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmBackend.h Mon Jul 25 17:52:04 2011 @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETASMBACKEND_H -#define LLVM_TARGET_TARGETASMBACKEND_H +#ifndef LLVM_MC_TARGETASMBACKEND_H +#define LLVM_MC_TARGETASMBACKEND_H #include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCFixup.h" Modified: llvm/trunk/include/llvm/MC/TargetAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmLexer.h?rev=135998&r1=135997&r2=135998&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmLexer.h Mon Jul 25 17:52:04 2011 @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETASMLEXER_H -#define LLVM_TARGET_TARGETASMLEXER_H +#ifndef LLVM_MC_TARGETASMLEXER_H +#define LLVM_MC_TARGETASMLEXER_H #include "llvm/MC/MCParser/MCAsmLexer.h" Modified: llvm/trunk/include/llvm/MC/TargetAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmParser.h?rev=135998&r1=135997&r2=135998&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmParser.h Mon Jul 25 17:52:04 2011 @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETPARSER_H -#define LLVM_TARGET_TARGETPARSER_H +#ifndef LLVM_MC_TARGETPARSER_H +#define LLVM_MC_TARGETPARSER_H #include "llvm/MC/MCParser/MCAsmParserExtension.h" From chandlerc at google.com Mon Jul 25 18:02:07 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 25 Jul 2011 16:02:07 -0700 Subject: [llvm-commits] [llvm] r135963 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/MC/MCDisassembler/EDDisassembler.cpp lib/MC/MCDisassembler/EDDisassembler.h lib/Target/ARM/AsmParser/ARMAsmLexer.cpp lib/Target/MBlaze/AsmParser/MBlazeAsmLex In-Reply-To: <2A9120B7-4FF6-4200-9CFE-AA6BF1A5044F@apple.com> References: <2A9120B7-4FF6-4200-9CFE-AA6BF1A5044F@apple.com> Message-ID: On Mon, Jul 25, 2011 at 3:40 PM, Evan Cheng wrote: > > On Jul 25, 2011, at 2:16 PM, Chandler Carruth wrote: > > On Mon, Jul 25, 2011 at 1:53 PM, Evan Cheng wrote: > >> Fix last bits of MC layer issues. llvm-mc doesn't need to initialize >> TargetMachine's anymore. > > > Wow, this is fantastic. > > Do you want me to try asserting that MC code doesn't #include (even > transitively) Target code and report places where it still does? > > (I'm also working on removing a couple of the related kludges to the former > target initialization) > > > That would be great. Thanks. > > One more thing. Does anyone know why llvm-mc is still linking in CodeGen? > I've manually verified it is not necessary. It would be nice if we can fix > this and make sure it is not violated in the future. > I'll let you know when we get the changes integrated and can run it through our layering-crazy build system. =D -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/532f0fdb/attachment.html From benny.kra at googlemail.com Mon Jul 25 18:04:36 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 25 Jul 2011 23:04:36 -0000 Subject: [llvm-commits] [llvm] r136000 - in /llvm/trunk/tools/llvm-objdump: MCFunction.cpp llvm-objdump.cpp Message-ID: <20110725230436.B67DE2A6C12C@llvm.org> Author: d0k Date: Mon Jul 25 18:04:36 2011 New Revision: 136000 URL: http://llvm.org/viewvc/llvm-project?rev=136000&view=rev Log: llvm-objdump: Ignore unreachable blocks when printing the CFG. Modified: llvm/trunk/tools/llvm-objdump/MCFunction.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/tools/llvm-objdump/MCFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MCFunction.cpp?rev=136000&r1=135999&r2=136000&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/MCFunction.cpp (original) +++ llvm/trunk/tools/llvm-objdump/MCFunction.cpp Mon Jul 25 18:04:36 2011 @@ -54,6 +54,8 @@ } } Splits.insert(Index+Size); + } else if (Desc.isReturn()) { + Splits.insert(Index+Size); } Instructions.push_back(MCDecodedInst(Index, Size, Inst)); Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=136000&r1=135999&r2=136000&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Jul 25 18:04:36 2011 @@ -27,6 +27,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Format.h" +#include "llvm/Support/GraphWriter.h" #include "llvm/Support/Host.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" @@ -280,12 +281,28 @@ Out << "digraph " << f.getName() << " {\n"; Out << "graph [ rankdir = \"LR\" ];\n"; for (MCFunction::iterator i = f.begin(), e = f.end(); i != e; ++i) { + bool hasPreds = false; + // Only print blocks that have predecessors. + // FIXME: Slow. + for (MCFunction::iterator pi = f.begin(), pe = f.end(); pi != pe; + ++pi) + for (pi->second->contains(&i->second)) { + hasPreds = true; + break; + } + + if (!hasPreds && i != f.begin()) + continue; + Out << '"' << (uintptr_t)&i->second << "\" [ label=\""; // Print instructions. for (unsigned ii = 0, ie = i->second.getInsts().size(); ii != ie; ++ii) { - IP->printInst(&i->second.getInsts()[ii].Inst, Out); - Out << '|'; + // Escape special chars and print the instruction in mnemonic form. + std::string Str; + raw_string_ostream OS(Str); + IP->printInst(&i->second.getInsts()[ii].Inst, OS); + Out << DOT::EscapeString(OS.str()) << '|'; } Out << "\" shape=\"record\" ];\n"; From bruno.cardoso at gmail.com Mon Jul 25 18:05:16 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 25 Jul 2011 23:05:16 -0000 Subject: [llvm-commits] [llvm] r136001 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110725230517.0CED12A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 18:05:16 2011 New Revision: 136001 URL: http://llvm.org/viewvc/llvm-project?rev=136001&view=rev Log: Reintroduce r135730, this is indeed the right approach, there is no native 256-bit vector instruction to do scalar_to_vector. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136001&r1=136000&r2=136001&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 18:05:16 2011 @@ -983,6 +983,7 @@ setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); } @@ -6324,9 +6325,26 @@ SDValue X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { + LLVMContext *Context = DAG.getContext(); DebugLoc dl = Op.getDebugLoc(); EVT OpVT = Op.getValueType(); + // If this is a 256-bit vector result, first insert into a 128-bit + // vector and then insert into the 256-bit vector. + if (OpVT.getSizeInBits() > 128) { + // Insert into a 128-bit vector. + EVT VT128 = EVT::getVectorVT(*Context, + OpVT.getVectorElementType(), + OpVT.getVectorNumElements() / 2); + + Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); + + // Insert the 128-bit vector. + return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, + DAG.getConstant(0, MVT::i32), + DAG, dl); + } + if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); From bruno.cardoso at gmail.com Mon Jul 25 18:05:25 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 25 Jul 2011 23:05:25 -0000 Subject: [llvm-commits] [llvm] r136002 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-256-splat.ll test/CodeGen/X86/avx-256.ll Message-ID: <20110725230525.7E6ED2A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 18:05:25 2011 New Revision: 136002 URL: http://llvm.org/viewvc/llvm-project?rev=136002&view=rev Log: - Handle special scalar_to_vector case: splats. Using a native 128-bit shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-256-splat.ll llvm/trunk/test/CodeGen/X86/avx-256.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 18:05:25 2011 @@ -3955,6 +3955,34 @@ return DAG.getNode(ISD::BITCAST, dl, VT, V); } +/// PromoteVectorToScalarSplat - Since there's no native support for +/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector + +/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the +/// shuffle before the insertion, this yields less instructions in the end. +static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV, + SelectionDAG &DAG) { + EVT SrcVT = SV->getValueType(0); + SDValue V1 = SV->getOperand(0); + DebugLoc dl = SV->getDebugLoc(); + int NumElems = SrcVT.getVectorNumElements(); + + assert(SrcVT.is256BitVector() && "unknown howto handle vector type"); + + SmallVector Mask; + for (int i = 0; i < NumElems/2; ++i) + Mask.push_back(SV->getMaskElt(i)); + + EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(), + NumElems/2); + SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1), + DAG.getUNDEF(SVT), &Mask[0]); + SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1, + DAG.getConstant(0, MVT::i32), DAG, dl); + + return Insert128BitVector(InsV, SV1, + DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); +} + /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and /// v8i32, v16i16 or v32i8 to v8f32. static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { @@ -5742,7 +5770,17 @@ if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) return Op; - // Handle splats by matching through known masks + // Since there's no native support for scalar_to_vector for 256-bit AVX, a + // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this + // idiom and do the shuffle before the insertion, this yields less + // instructions in the end. + if (VT.is256BitVector() && + V1.getOpcode() == ISD::INSERT_SUBVECTOR && + V1.getOperand(0).getOpcode() == ISD::UNDEF && + V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR) + return PromoteVectorToScalarSplat(SVOp, DAG); + + // Handle splats by matching through known shuffle masks if ((VT.is128BitVector() && NumElem <= 4) || (VT.is256BitVector() && NumElem <= 8)) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Jul 25 18:05:25 2011 @@ -501,6 +501,9 @@ class RPDI o, Format F, dag outs, dag ins, string asm, list pattern> : PDI, REX_W; +class VRPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : VPDI, VEX_W; // MMX Instruction templates // Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Jul 25 18:05:25 2011 @@ -467,3 +467,4 @@ node:$index), [{ return X86::isVINSERTF128Index(N); }], INSERT_get_vinsertf128_imm>; + Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 18:05:25 2011 @@ -2858,6 +2858,14 @@ [(set VR128:$dst, (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>, VEX; +def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), + "mov{d|q}\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>, VEX; +def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), + "mov{d|q}\t{$src, $dst|$dst, $src}", + [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX; + def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -5358,6 +5366,20 @@ (VINSERTF128rr VR256:$src1, VR128:$src2, (INSERT_get_vinsertf128_imm VR256:$ins))>; +// Special COPY patterns +def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)), + (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)), + (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)), + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)), + (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)), + (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)), + (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; + //===----------------------------------------------------------------------===// // VEXTRACTF128 - Extract packed floating-point values // Modified: llvm/trunk/test/CodeGen/X86/avx-256-splat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-splat.ll?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256-splat.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-256-splat.ll Mon Jul 25 18:05:25 2011 @@ -5,7 +5,6 @@ ; CHECK: vextractf128 $0 ; CHECK-NEXT: punpcklbw ; CHECK-NEXT: punpckhbw -; CHECK-NEXT: vinsertf128 $0 ; CHECK-NEXT: vinsertf128 $1 ; CHECK-NEXT: vpermilps $85 define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp { @@ -16,7 +15,6 @@ ; CHECK: vextractf128 $0 ; CHECK-NEXT: punpckhwd -; CHECK-NEXT: vinsertf128 $0 ; CHECK-NEXT: vinsertf128 $1 ; CHECK-NEXT: vpermilps $85 define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp { @@ -25,3 +23,25 @@ ret <16 x i16> %shuffle } +; CHECK: vmovd +; CHECK-NEXT: movlhps +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp { +entry: + %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0 + %vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1 + %vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2 + %vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3 + ret <4 x i64> %vecinit6.i +} + +; CHECK: vshufpd +; CHECK-NEXT: vinsertf128 $1 +define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp { +entry: + %vecinit.i = insertelement <4 x double> undef, double %q, i32 0 + %vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1 + %vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2 + %vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3 + ret <4 x double> %vecinit6.i +} Modified: llvm/trunk/test/CodeGen/X86/avx-256.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256.ll?rev=136002&r1=136001&r2=136002&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-256.ll Mon Jul 25 18:05:25 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s @x = common global <8 x float> zeroinitializer, align 32 @y = common global <4 x double> zeroinitializer, align 32 @@ -12,4 +12,3 @@ store <4 x double> zeroinitializer, <4 x double>* @y, align 32 ret void } - From bruno.cardoso at gmail.com Mon Jul 25 18:05:28 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 25 Jul 2011 23:05:28 -0000 Subject: [llvm-commits] [llvm] r136003 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110725230528.6EA5D2A6C12D@llvm.org> Author: bruno Date: Mon Jul 25 18:05:28 2011 New Revision: 136003 URL: http://llvm.org/viewvc/llvm-project?rev=136003&view=rev Log: Add remaining 256-bit vector bitcasts. This also fixes PR10451 Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136003&r1=136002&r2=136003&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 18:05:28 2011 @@ -3639,9 +3639,8 @@ def : Pat<(fextend (loadf32 addr:$src)), (CVTSS2SDrm addr:$src)>; - - -// bit_convert +// Bitcasts between 128-bit vector types. Return the original type since +// no instruction is needed for the conversion let Predicates = [HasXMMInt] in { def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; @@ -3675,24 +3674,39 @@ def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; } +// Bitcasts between 256-bit vector types. Return the original type since +// no instruction is needed for the conversion let Predicates = [HasAVX] in { def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>; def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>; def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>; def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>; def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>; def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>; def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>; def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>; def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>; def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>; } // Move scalar to XMM zero-extended From bruno.cardoso at gmail.com Mon Jul 25 18:05:32 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 25 Jul 2011 23:05:32 -0000 Subject: [llvm-commits] [llvm] r136004 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCInstLower.cpp test/CodeGen/X86/avx-256.ll Message-ID: <20110725230532.B68202A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 18:05:32 2011 New Revision: 136004 URL: http://llvm.org/viewvc/llvm-project?rev=136004&view=rev Log: Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 This also fixes PR10452 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/lib/Target/X86/X86MCInstLower.cpp llvm/trunk/test/CodeGen/X86/avx-256.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136004&r1=136003&r2=136004&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 18:05:32 2011 @@ -3831,21 +3831,25 @@ } /// getOnesVector - Returns a vector of specified type with all bits set. -/// Always build ones vectors as <4 x i32> or <8 x i32> bitcasted to -/// their original type, ensuring they get CSE'd. +/// Always build ones vectors as <4 x i32>. For 256-bit types, use two +/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their +/// original type, ensuring they get CSE'd. static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); assert((VT.is128BitVector() || VT.is256BitVector()) && "Expected a 128-bit or 256-bit vector type"); SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); + SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + Cst, Cst, Cst, Cst); - SDValue Vec; if (VT.is256BitVector()) { - SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); - } else - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), + Vec, DAG.getConstant(0, MVT::i32), DAG, dl); + Vec = Insert128BitVector(InsV, Vec, + DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); + } + return DAG.getNode(ISD::BITCAST, dl, VT, Vec); } @@ -12023,6 +12027,35 @@ return SDValue(); } +/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector +/// so it can be folded inside ANDNP. +static bool CanFoldXORWithAllOnes(const SDNode *N) { + EVT VT = N->getValueType(0); + + // Match direct AllOnes for 128 and 256-bit vectors + if (ISD::isBuildVectorAllOnes(N)) + return true; + + // Look through a bit convert. + if (N->getOpcode() == ISD::BITCAST) + N = N->getOperand(0).getNode(); + + // Sometimes the operand may come from a insert_subvector building a 256-bit + // allones vector + SDValue V1 = N->getOperand(0); + SDValue V2 = N->getOperand(1); + + if (VT.getSizeInBits() == 256 && + N->getOpcode() == ISD::INSERT_SUBVECTOR && + V1.getOpcode() == ISD::INSERT_SUBVECTOR && + V1.getOperand(0).getOpcode() == ISD::UNDEF && + ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && + ISD::isBuildVectorAllOnes(V2.getNode())) + return true; + + return false; +} + static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { @@ -12047,12 +12080,14 @@ // Check LHS for vnot if (N0.getOpcode() == ISD::XOR && - ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) + //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) + CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); // Check RHS for vnot if (N1.getOpcode() == ISD::XOR && - ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) + //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) + CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=136004&r1=136003&r2=136004&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jul 25 18:05:32 2011 @@ -2450,6 +2450,7 @@ case X86::AVX_SET0PS: case X86::AVX_SET0PD: case X86::AVX_SET0PI: + case X86::AVX_SETALLONES: Alignment = 16; break; case X86::FsFLD0SD: @@ -2494,6 +2495,7 @@ case X86::AVX_SET0PI: case X86::AVX_SET0PSY: case X86::AVX_SET0PDY: + case X86::AVX_SETALLONES: case X86::FsFLD0SD: case X86::FsFLD0SS: case X86::VFsFLD0SD: @@ -2531,9 +2533,10 @@ Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8); else Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); - const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? - Constant::getAllOnesValue(Ty) : - Constant::getNullValue(Ty); + + bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES); + const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : + Constant::getNullValue(Ty); unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); // Create operands to load from the constant pool entry. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136004&r1=136003&r2=136004&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 18:05:32 2011 @@ -3143,11 +3143,17 @@ // Alias instructions that map zero vector to pxor / xorp* for sse. // We set canFoldAsLoad because this can be converted to a constant-pool // load of an all-ones value if folding it would be beneficial. +// FIXME: Change encoding to pseudo! This is blocked right now by the x86 +// JIT implementation, it does not expand the instructions below like +// X86MCInstLower does. let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, isCodeGenOnly = 1, ExeDomain = SSEPackedInt in - // FIXME: Change encoding to pseudo. def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "", [(set VR128:$dst, (v4i32 immAllOnesV))]>; +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in + def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V; //===---------------------------------------------------------------------===// // SSE3 - Conversion Instructions Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=136004&r1=136003&r2=136004&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Mon Jul 25 18:05:32 2011 @@ -381,6 +381,7 @@ case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break; case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break; case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break; + case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break; case X86::MOV16r0: LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0 Modified: llvm/trunk/test/CodeGen/X86/avx-256.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256.ll?rev=136004&r1=136003&r2=136004&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-256.ll Mon Jul 25 18:05:32 2011 @@ -12,3 +12,15 @@ store <4 x double> zeroinitializer, <4 x double>* @y, align 32 ret void } + +; CHECK: vpcmpeqd +; CHECK: vinsertf128 $1 +define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind { +allocas: + %ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>* + store <8 x float> , <8 x +float>* %ptr2vec615, align 32 + ret void +} From eli.friedman at gmail.com Mon Jul 25 18:09:12 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 16:09:12 -0700 Subject: [llvm-commits] [PATCH] New (C++0x) atomics: start implementation of 'fence' instruction In-Reply-To: References: Message-ID: On Sat, Jul 23, 2011 at 6:59 PM, Jeffrey Yasskin wrote: > On Fri, Jul 22, 2011 at 5:40 PM, Eli Friedman wrote: >> Per subject; patch attached. ?This is the replacement for the very >> confusing llvm.memory.barrier intrinsic. ?Based off of Jeffrey >> Yasskin's branch where he started work on this. ?This patch is a >> little on the large side, but I couldn't usefully commit anything much >> smaller. > > Thanks for picking this up! No problem. :) >> There's one thing about the definition of fence in this patch I'm not >> sure about: it doesn't provide any obvious way to order a load/store >> marked !nontemporal. ?We don't really want to require that by default >> because it's a performance hit and not generally useful, but someone >> might need it. > > Two possible ways to support that would be to add values to the > SynchronizationScope enum or to attach !nontemporal to the fence > instruction. The alternative is not so much emitting extra > instructions for ordinary fences to make them apply to nontemporal > operations as having the x86 code generator automatically insert an > sfence after any sequence of nontemporal stores. The code generator, > of course, might not do as good a job as the optimizers in deciding > where to put sfences. Hmm... I guess I'll leave this for now; this wasn't really clearly specified for llvm.memory.barrier anyway. >> Index: include/llvm/Instruction.def >> =================================================================== >> --- include/llvm/Instruction.def ? ? ?(revision 135822) >> +++ include/llvm/Instruction.def ? ? ?(working copy) >> @@ -133,41 +133,42 @@ >> ?HANDLE_MEMORY_INST(27, Load ?, LoadInst ?) ?// Memory manipulation instrs >> ?HANDLE_MEMORY_INST(28, Store , StoreInst ) >> ?HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) >> - ?LAST_MEMORY_INST(29) >> +HANDLE_MEMORY_INST(30, Fence , FenceInst ) > > I assume you're skipping 31 and 32 here to save space for atomicrmw and cmpxchg? > >> + ?LAST_MEMORY_INST(32) Yes. And I just spotted an error a few lines down here; minor editing glitch. >> Index: docs/LangRef.html >> =================================================================== >> --- docs/LangRef.html (revision 135822) >> +++ docs/LangRef.html (working copy) >> @@ -4544,6 +4545,63 @@ >> ? >> >> ? >> +
    'fence' >> +Instruction
    >> + >> +
    >> + >> +
    Syntax:
    >> +
    >> + ?fence [singlethread] <ordering> ? ? ? ? ? ? ? ? ? ; yields {void}
>> +
    >> + >> +
    Overview:
    >> +

    The 'fence' instruction is used to introduce happens-before edges >> +between operations.

    >> + >> +
    Arguments:

    'fence' instructions take an > +href="#ordering">ordering argument which defines what >> +synchronizes-with edges they add. ?They can only be given >> +acquire, release, acq_rel, and >> +seq_cst orderings.

    >> + >> +
    Semantics:
    >> +

    A fence A which has (at least) release ordering >> +semantics synchronizes with a fence B with (at least) >> +acquire ordering semantics if and only if there exist atomic >> +operations X and Y, both operating on some atomic object >> +M, such that A is sequenced before X, >> +X modifies M (either directly or through some side effect >> +of a sequence headed by X), Y is sequenced before >> +B, and Y observes M. This provides a >> +happens-before dependency between A and B. Rather >> +than an explicit fence, one (but not both) of the atomic operations >> +X or Y might provide a release or >> +acquire (resp.) ordering constraint and still >> +synchronize-with the explicit fence and establish the >> +happens-before edge.

    >> + >> +

    A fence which has seq_cst ordering, in addition to >> +having both acquire and release semantics specified >> +above, participates in the global program order of other seq_cst >> +operations and/or fences.

    >> + >> +

    The optional "singlethread" argument >> +specifies that the fence only synchronizes with other fences in the same >> +thread.

    > > Do you want to mention that 'singlethread' fences are intended > for/useful in signal handlers? Sure. > Looks good to me. (But I would say that. ;) ;) -Eli From grosbach at apple.com Mon Jul 25 18:09:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 23:09:14 -0000 Subject: [llvm-commits] [llvm] r136006 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s utils/TableGen/EDEmitter.cpp Message-ID: <20110725230914.F01442A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 18:09:14 2011 New Revision: 136006 URL: http://llvm.org/viewvc/llvm-project?rev=136006&view=rev Log: ARM assembly parsing and encoding for SSAT16 instruction. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 18:09:14 2011 @@ -543,10 +543,20 @@ def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } def imm1_32 : Operand, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }], imm1_32_XFORM> { - let PrintMethod = "printImm1_32Operand"; + let PrintMethod = "printImmPlusOneOperand"; let ParserMatchClass = Imm1_32AsmOperand; } +def imm1_16_XFORM: SDNodeXFormgetTargetConstant((int)N->getZExtValue() - 1, MVT::i32); +}]>; +def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } +def imm1_16 : Operand, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], + imm1_16_XFORM> { + let PrintMethod = "printImmPlusOneOperand"; + let ParserMatchClass = Imm1_16AsmOperand; +} + // Define ARM specific addressing modes. // addrmode_imm12 := reg +/- imm12 // @@ -2709,7 +2719,7 @@ let Inst{3-0} = Rn; } -def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn), SatFrm, +def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm, NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { bits<4> Rd; bits<4> sat_imm; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jul 25 18:09:14 2011 @@ -1935,7 +1935,7 @@ } def t2SSAT16: T2SatI< - (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn), NoItinerary, + (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", [/* For disassembly only; pattern left blank */]>, Requires<[IsThumb2, HasThumb2DSP]> { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 18:09:14 2011 @@ -433,6 +433,14 @@ int64_t Value = CE->getValue(); return Value >= 0 && Value < 32; } + bool isImm1_16() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && Value < 17; + } bool isImm1_32() const { if (Kind != Immediate) return false; @@ -704,6 +712,14 @@ addExpr(Inst, getImm()); } + void addImm1_16Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The constant encodes as the immediate-1, and we store in the instruction + // the bits as encoded, so subtract off one here. + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); + } + void addImm1_32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate-1, and we store in the instruction Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Jul 25 18:09:14 2011 @@ -830,8 +830,8 @@ O << "#0x" << utohexstr(Val); } -void ARMInstPrinter::printImm1_32Operand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { +void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { unsigned Imm = MI->getOperand(OpNum).getImm(); O << "#" << Imm + 1; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Jul 25 18:09:14 2011 @@ -114,7 +114,7 @@ void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printImm1_32Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); }; Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Jul 25 18:09:14 2011 @@ -1631,6 +1631,17 @@ @ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6] @ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6] + + at ------------------------------------------------------------------------------ +@ SSAT16 + at ------------------------------------------------------------------------------ + ssat16 r2, #1, r7 + ssat16 r3, #16, r5 + +@ CHECK: ssat16 r2, #1, r7 @ encoding: [0x37,0x2f,0xa0,0xe6] +@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x35,0x3f,0xaf,0xe6] + + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Mon Jul 25 18:09:14 2011 @@ -200,3 +200,14 @@ @ CHECK: error: shift amount must be an immediate @ CHECK: ssat r8, #1, r10, lsl #fred @ CHECK: ^ + + @ Out of range immediates for SSAT16 + ssat16 r2, #0, r7 + ssat16 r3, #17, r5 + +@ CHECK: error: invalid operand for instruction +@ CHECK: ssat16 r2, #0, r7 +@ CHECK: ^ +@ CHECK: error: invalid operand for instruction +@ CHECK: ssat16 r3, #17, r5 +@ CHECK: ^ Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=136006&r1=136005&r2=136006&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Jul 25 18:09:14 2011 @@ -587,6 +587,7 @@ IMM("neg_zero"); IMM("imm0_31"); IMM("imm0_31_m1"); + IMM("imm1_16"); IMM("imm1_32"); IMM("nModImm"); IMM("imm0_7"); From benny.kra at googlemail.com Mon Jul 25 18:10:23 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 25 Jul 2011 23:10:23 -0000 Subject: [llvm-commits] [llvm] r136007 - in /llvm/trunk/tools/llvm-objdump: MCFunction.h llvm-objdump.cpp Message-ID: <20110725231024.06FB62A6C12C@llvm.org> Author: d0k Date: Mon Jul 25 18:10:23 2011 New Revision: 136007 URL: http://llvm.org/viewvc/llvm-project?rev=136007&view=rev Log: I will save before I commit. I will save before I commit. I will save before I commit. I will save before I commit. Modified: llvm/trunk/tools/llvm-objdump/MCFunction.h llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/tools/llvm-objdump/MCFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MCFunction.h?rev=136007&r1=136006&r2=136007&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/MCFunction.h (original) +++ llvm/trunk/tools/llvm-objdump/MCFunction.h Mon Jul 25 18:10:23 2011 @@ -48,6 +48,8 @@ succ_iterator succ_begin() const { return Succs.begin(); } succ_iterator succ_end() const { return Succs.end(); } + bool contains(MCBasicBlock *BB) const { return Succs.count(BB); } + void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } void addSucc(MCBasicBlock *BB) { Succs.insert(BB); } }; Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=136007&r1=136006&r2=136007&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Jul 25 18:10:23 2011 @@ -286,7 +286,7 @@ // FIXME: Slow. for (MCFunction::iterator pi = f.begin(), pe = f.end(); pi != pe; ++pi) - for (pi->second->contains(&i->second)) { + if (pi->second.contains(&i->second)) { hasPreds = true; break; } From nicholas at mxc.ca Mon Jul 25 18:14:22 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 25 Jul 2011 23:14:22 -0000 Subject: [llvm-commits] [llvm] r136008 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/lifetime.ll Message-ID: <20110725231422.AA4FB2A6C12C@llvm.org> Author: nicholas Date: Mon Jul 25 18:14:22 2011 New Revision: 136008 URL: http://llvm.org/viewvc/llvm-project?rev=136008&view=rev Log: Finish adding support for lifetime intrinsics to SROA. Fixes PR10121! Added: llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=136008&r1=136007&r2=136008&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jul 25 18:14:22 2011 @@ -145,6 +145,9 @@ SmallVector &NewElts); void RewriteGEP(GetElementPtrInst *GEPI, AllocaInst *AI, uint64_t Offset, SmallVector &NewElts); + void RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI, + uint64_t Offset, + SmallVector &NewElts); void RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst, AllocaInst *AI, SmallVector &NewElts); @@ -508,7 +511,8 @@ } if (BitCastInst *BCI = dyn_cast(User)) { - IsNotTrivial = true; // Can't be mem2reg'd. + if (!onlyUsedByLifetimeMarkers(BCI)) + IsNotTrivial = true; // Can't be mem2reg'd. if (!CanConvertToScalar(BCI, Offset)) return false; continue; @@ -566,6 +570,14 @@ continue; } + // If this is a lifetime intrinsic, we can handle it. + if (IntrinsicInst *II = dyn_cast(User)) { + if (II->getIntrinsicID() == Intrinsic::lifetime_start || + II->getIntrinsicID() == Intrinsic::lifetime_end) { + continue; + } + } + // Otherwise, we cannot handle this! return false; } @@ -709,6 +721,16 @@ continue; } + if (IntrinsicInst *II = dyn_cast(User)) { + if (II->getIntrinsicID() == Intrinsic::lifetime_start || + II->getIntrinsicID() == Intrinsic::lifetime_end) { + // There's no need to preserve these, as the resulting alloca will be + // converted to a register anyways. + II->eraseFromParent(); + continue; + } + } + llvm_unreachable("Unsupported operation!"); } } @@ -1349,6 +1371,13 @@ continue; } + if (BitCastInst *BCI = dyn_cast(U)) { + if (onlyUsedByLifetimeMarkers(BCI)) { + InstsToRewrite.insert(BCI); + continue; + } + } + return false; } @@ -1360,6 +1389,18 @@ // If we have instructions that need to be rewritten for this to be promotable // take care of it now. for (unsigned i = 0, e = InstsToRewrite.size(); i != e; ++i) { + if (BitCastInst *BCI = dyn_cast(InstsToRewrite[i])) { + // This could only be a bitcast used by nothing but lifetime intrinsics. + for (BitCastInst::use_iterator I = BCI->use_begin(), E = BCI->use_end(); + I != E;) { + Use &U = I.getUse(); + ++I; + cast(U.getUser())->eraseFromParent(); + } + BCI->eraseFromParent(); + continue; + } + if (SelectInst *SI = dyn_cast(InstsToRewrite[i])) { // Selects in InstsToRewrite only have load uses. Rewrite each as two // loads with a new select. @@ -1692,6 +1733,10 @@ isSafeMemAccess(Offset, TD->getTypeAllocSize(SIType), SIType, true, Info, SI, true /*AllowWholeAccess*/); Info.hasALoadOrStore = true; + } else if (IntrinsicInst *II = dyn_cast(User)) { + if (II->getIntrinsicID() != Intrinsic::lifetime_start && + II->getIntrinsicID() != Intrinsic::lifetime_end) + return MarkUnsafe(Info, User); } else if (isa(User) || isa(User)) { isSafePHISelectUseForScalarRepl(User, Offset, Info); } else { @@ -1929,6 +1974,14 @@ // address operand will be updated, so nothing else needs to be done. continue; } + + if (IntrinsicInst *II = dyn_cast(User)) { + if (II->getIntrinsicID() == Intrinsic::lifetime_start || + II->getIntrinsicID() == Intrinsic::lifetime_end) { + RewriteLifetimeIntrinsic(II, AI, Offset, NewElts); + } + continue; + } if (LoadInst *LI = dyn_cast(User)) { Type *LIType = LI->getType(); @@ -2095,6 +2148,62 @@ DeadInsts.push_back(GEPI); } +/// RewriteLifetimeIntrinsic - II is a lifetime.start/lifetime.end. Rewrite it +/// to mark the lifetime of the scalarized memory. +void SROA::RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI, + uint64_t Offset, + SmallVector &NewElts) { + ConstantInt *OldSize = cast(II->getArgOperand(0)); + // Put matching lifetime markers on everything from Offset up to + // Offset+OldSize. + Type *AIType = AI->getAllocatedType(); + uint64_t NewOffset = Offset; + Type *IdxTy; + uint64_t Idx = FindElementAndOffset(AIType, NewOffset, IdxTy); + + IRBuilder<> Builder(II); + uint64_t Size = OldSize->getLimitedValue(); + + if (NewOffset) { + // Splice the first element and index 'NewOffset' bytes in. SROA will + // split the alloca again later. + Value *V = Builder.CreateBitCast(NewElts[Idx], Builder.getInt8PtrTy()); + V = Builder.CreateGEP(V, Builder.getInt64(NewOffset)); + + IdxTy = NewElts[Idx]->getAllocatedType(); + uint64_t EltSize = TD->getTypeAllocSize(IdxTy) - NewOffset; + if (EltSize > Size) { + EltSize = Size; + Size = 0; + } else { + Size -= EltSize; + } + if (II->getIntrinsicID() == Intrinsic::lifetime_start) + Builder.CreateLifetimeStart(V, Builder.getInt64(EltSize)); + else + Builder.CreateLifetimeEnd(V, Builder.getInt64(EltSize)); + ++Idx; + } + + for (; Idx != NewElts.size() && Size; ++Idx) { + IdxTy = NewElts[Idx]->getAllocatedType(); + uint64_t EltSize = TD->getTypeAllocSize(IdxTy); + if (EltSize > Size) { + EltSize = Size; + Size = 0; + } else { + Size -= EltSize; + } + if (II->getIntrinsicID() == Intrinsic::lifetime_start) + Builder.CreateLifetimeStart(NewElts[Idx], + Builder.getInt64(EltSize)); + else + Builder.CreateLifetimeEnd(NewElts[Idx], + Builder.getInt64(EltSize)); + } + DeadInsts.push_back(II); +} + /// RewriteMemIntrinUserOfAlloca - MI is a memcpy/memset/memmove from or to AI. /// Rewrite it to copy or set the elements of the scalarized memory. void SROA::RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst, Added: llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll?rev=136008&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll Mon Jul 25 18:14:22 2011 @@ -0,0 +1,139 @@ +; RUN: opt -scalarrepl -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +declare void @llvm.lifetime.start(i64, i8*) +declare void @llvm.lifetime.end(i64, i8*) + +%t1 = type {i32, i32, i32} + +define void @test1() { +; CHECK: @test1 + %A = alloca %t1 + %A1 = getelementptr %t1* %A, i32 0, i32 0 + %A2 = getelementptr %t1* %A, i32 0, i32 1 + %A3 = getelementptr %t1* %A, i32 0, i32 2 + %B = bitcast i32* %A1 to i8* + store i32 0, i32* %A1 + call void @llvm.lifetime.start(i64 -1, i8* %B) + ret void +; CHECK-NEXT: ret void +} + +define void @test2() { +; CHECK: @test2 + %A = alloca %t1 + %A1 = getelementptr %t1* %A, i32 0, i32 0 + %A2 = getelementptr %t1* %A, i32 0, i32 1 + %A3 = getelementptr %t1* %A, i32 0, i32 2 + %B = bitcast i32* %A2 to i8* + store i32 0, i32* %A2 + call void @llvm.lifetime.start(i64 -1, i8* %B) + %C = load i32* %A2 + ret void +; CHECK: ret void +} + +define void @test3() { +; CHECK: @test3 + %A = alloca %t1 + %A1 = getelementptr %t1* %A, i32 0, i32 0 + %A2 = getelementptr %t1* %A, i32 0, i32 1 + %A3 = getelementptr %t1* %A, i32 0, i32 2 + %B = bitcast i32* %A2 to i8* + store i32 0, i32* %A2 + call void @llvm.lifetime.start(i64 6, i8* %B) + %C = load i32* %A2 + ret void +; CHECK-NEXT: ret void +} + +define void @test4() { +; CHECK: @test4 + %A = alloca %t1 + %A1 = getelementptr %t1* %A, i32 0, i32 0 + %A2 = getelementptr %t1* %A, i32 0, i32 1 + %A3 = getelementptr %t1* %A, i32 0, i32 2 + %B = bitcast i32* %A2 to i8* + store i32 0, i32* %A2 + call void @llvm.lifetime.start(i64 1, i8* %B) + %C = load i32* %A2 + ret void +; CHECK-NEXT: ret void +} + +%t2 = type {i32, [4 x i8], i32} + +define void @test5() { +; CHECK: @test5 + %A = alloca %t2 +; CHECK: alloca{{.*}}i8 +; CHECK: alloca{{.*}}i8 +; CHECK: alloca{{.*}}i8 + + %A21 = getelementptr %t2* %A, i32 0, i32 1, i32 0 + %A22 = getelementptr %t2* %A, i32 0, i32 1, i32 1 + %A23 = getelementptr %t2* %A, i32 0, i32 1, i32 2 + %A24 = getelementptr %t2* %A, i32 0, i32 1, i32 3 +; CHECK-NOT: store i8 1 + store i8 1, i8* %A21 + store i8 2, i8* %A22 + store i8 3, i8* %A23 + store i8 4, i8* %A24 + + %A1 = getelementptr %t2* %A, i32 0, i32 0 + %A2 = getelementptr %t2* %A, i32 0, i32 1, i32 1 + %A3 = getelementptr %t2* %A, i32 0, i32 2 + store i8 0, i8* %A2 + call void @llvm.lifetime.start(i64 5, i8* %A2) +; CHECK: llvm.lifetime{{.*}}i64 1 +; CHECK: llvm.lifetime{{.*}}i64 1 +; CHECK: llvm.lifetime{{.*}}i64 1 + %C = load i8* %A2 + ret void +} + +%t3 = type {[4 x i16], [4 x i8]} + +define void @test6() { +; CHECK: @test6 + %A = alloca %t3 +; CHECK: alloca i8 +; CHECK: alloca i8 +; CHECK: alloca i8 + + %A11 = getelementptr %t3* %A, i32 0, i32 0, i32 0 + %A12 = getelementptr %t3* %A, i32 0, i32 0, i32 1 + %A13 = getelementptr %t3* %A, i32 0, i32 0, i32 2 + %A14 = getelementptr %t3* %A, i32 0, i32 0, i32 3 + store i16 11, i16* %A11 + store i16 12, i16* %A12 + store i16 13, i16* %A13 + store i16 14, i16* %A14 +; CHECK-NOT: store i16 11 +; CHECK-NOT: store i16 12 +; CHECK-NOT: store i16 13 +; CHECK-NOT: store i16 14 + + %A21 = getelementptr %t3* %A, i32 0, i32 1, i32 0 + %A22 = getelementptr %t3* %A, i32 0, i32 1, i32 1 + %A23 = getelementptr %t3* %A, i32 0, i32 1, i32 2 + %A24 = getelementptr %t3* %A, i32 0, i32 1, i32 3 + store i8 21, i8* %A21 + store i8 22, i8* %A22 + store i8 23, i8* %A23 + store i8 24, i8* %A24 +; CHECK: store i8 21 +; CHECK: store i8 22 +; CHECK: store i8 23 +; CHECK-NOT: store i8 24 + + %B = bitcast i16* %A13 to i8* + call void @llvm.lifetime.start(i64 7, i8* %B) +; CHECK: lifetime.start{{.*}}i64 1 +; CHECK: lifetime.start{{.*}}i64 1 +; CHECK: lifetime.start{{.*}}i64 1 + + ret void +} From eli.friedman at gmail.com Mon Jul 25 18:16:38 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 25 Jul 2011 23:16:38 -0000 Subject: [llvm-commits] [llvm] r136009 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/SelectionDAG/ lib/VMCore/ Message-ID: <20110725231639.524322A6C12C@llvm.org> Author: efriedma Date: Mon Jul 25 18:16:38 2011 New Revision: 136009 URL: http://llvm.org/viewvc/llvm-project?rev=136009&view=rev Log: Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier. This is just a LangRef entry and reading/writing/memory representation; optimizer+codegen support coming soon. Modified: llvm/trunk/docs/LangRef.html llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h llvm/trunk/include/llvm/Instruction.def llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/Support/IRBuilder.h llvm/trunk/include/llvm/Support/InstVisitor.h llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h llvm/trunk/lib/AsmParser/LLToken.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/Instruction.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Jul 25 18:16:38 2011 @@ -170,6 +170,7 @@
  • 'alloca' Instruction
  • 'load' Instruction
  • 'store' Instruction
    • +
  • 'fence' Instruction
  • 'getelementptr' Instruction
    • @@ -4552,6 +4553,63 @@
    +
    'fence' +Instruction
    + +
    + +
    Syntax:
    +
    +  fence [singlethread] <ordering>                   ; yields {void}
+
    + +
    Overview:
    +

    The 'fence' instruction is used to introduce happens-before edges +between operations.

    + +
    Arguments:

    'fence' instructions take an ordering argument which defines what +synchronizes-with edges they add. They can only be given +acquire, release, acq_rel, and +seq_cst orderings.

    + +
    Semantics:
    +

    A fence A which has (at least) release ordering +semantics synchronizes with a fence B with (at least) +acquire ordering semantics if and only if there exist atomic +operations X and Y, both operating on some atomic object +M, such that A is sequenced before X, +X modifies M (either directly or through some side effect +of a sequence headed by X), Y is sequenced before +B, and Y observes M. This provides a +happens-before dependency between A and B. Rather +than an explicit fence, one (but not both) of the atomic operations +X or Y might provide a release or +acquire (resp.) ordering constraint and still +synchronize-with the explicit fence and establish the +happens-before edge.

    + +

    A fence which has seq_cst ordering, in addition to +having both acquire and release semantics specified +above, participates in the global program order of other seq_cst +operations and/or fences.

    + +

    The optional "singlethread" argument +specifies that the fence only synchronizes with other fences in the same +thread. (This is useful for interacting with signal handlers.)

    + +

    FIXME: This instruction is a work in progress; until it is finished, use + llvm.memory.barrier. + +

    Example:
    +
    +  fence acquire                          ; yields {void}
+  fence singlethread seq_cst             ; yields {void}
+
    + +
    + +

    'getelementptr' Instruction

    Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Mon Jul 25 18:16:38 2011 @@ -218,6 +218,23 @@ PEO_EXACT = 0 }; + /// Encoded AtomicOrdering values. + enum AtomicOrderingCodes { + ORDERING_NOTATOMIC = 0, + ORDERING_UNORDERED = 1, + ORDERING_MONOTONIC = 2, + ORDERING_ACQUIRE = 3, + ORDERING_RELEASE = 4, + ORDERING_ACQREL = 5, + ORDERING_SEQCST = 6 + }; + + /// Encoded SynchronizationScope values. + enum AtomicSynchScopeCodes { + SYNCHSCOPE_SINGLETHREAD = 0, + SYNCHSCOPE_CROSSTHREAD = 1 + }; + // The function body block (FUNCTION_BLOCK_ID) describes function bodies. It // can contain a constant block (CONSTANTS_BLOCK_ID). enum FunctionCodes { @@ -266,7 +283,8 @@ FUNC_CODE_INST_CALL = 34, // CALL: [attr, fnty, fnid, args...] - FUNC_CODE_DEBUG_LOC = 35 // DEBUG_LOC: [Line,Col,ScopeVal, IAVal] + FUNC_CODE_DEBUG_LOC = 35, // DEBUG_LOC: [Line,Col,ScopeVal, IAVal] + FUNC_CODE_INST_FENCE = 36 // FENCE: [ordering, synchscope] }; } // End bitc namespace } // End llvm namespace Modified: llvm/trunk/include/llvm/Instruction.def URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instruction.def (original) +++ llvm/trunk/include/llvm/Instruction.def Mon Jul 25 18:16:38 2011 @@ -133,43 +133,44 @@ HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs HANDLE_MEMORY_INST(28, Store , StoreInst ) HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) - LAST_MEMORY_INST(29) +HANDLE_MEMORY_INST(30, Fence , FenceInst ) + LAST_MEMORY_INST(32) // Cast operators ... // NOTE: The order matters here because CastInst::isEliminableCastPair // NOTE: (see Instructions.cpp) encodes a table based on this ordering. - FIRST_CAST_INST(30) -HANDLE_CAST_INST(30, Trunc , TruncInst ) // Truncate integers -HANDLE_CAST_INST(31, ZExt , ZExtInst ) // Zero extend integers -HANDLE_CAST_INST(32, SExt , SExtInst ) // Sign extend integers -HANDLE_CAST_INST(33, FPToUI , FPToUIInst ) // floating point -> UInt -HANDLE_CAST_INST(34, FPToSI , FPToSIInst ) // floating point -> SInt -HANDLE_CAST_INST(35, UIToFP , UIToFPInst ) // UInt -> floating point -HANDLE_CAST_INST(36, SIToFP , SIToFPInst ) // SInt -> floating point -HANDLE_CAST_INST(37, FPTrunc , FPTruncInst ) // Truncate floating point -HANDLE_CAST_INST(38, FPExt , FPExtInst ) // Extend floating point -HANDLE_CAST_INST(39, PtrToInt, PtrToIntInst) // Pointer -> Integer -HANDLE_CAST_INST(40, IntToPtr, IntToPtrInst) // Integer -> Pointer -HANDLE_CAST_INST(41, BitCast , BitCastInst ) // Type cast - LAST_CAST_INST(41) + FIRST_CAST_INST(33) +HANDLE_CAST_INST(33, Trunc , TruncInst ) // Truncate integers +HANDLE_CAST_INST(34, ZExt , ZExtInst ) // Zero extend integers +HANDLE_CAST_INST(35, SExt , SExtInst ) // Sign extend integers +HANDLE_CAST_INST(36, FPToUI , FPToUIInst ) // floating point -> UInt +HANDLE_CAST_INST(37, FPToSI , FPToSIInst ) // floating point -> SInt +HANDLE_CAST_INST(38, UIToFP , UIToFPInst ) // UInt -> floating point +HANDLE_CAST_INST(39, SIToFP , SIToFPInst ) // SInt -> floating point +HANDLE_CAST_INST(40, FPTrunc , FPTruncInst ) // Truncate floating point +HANDLE_CAST_INST(41, FPExt , FPExtInst ) // Extend floating point +HANDLE_CAST_INST(42, PtrToInt, PtrToIntInst) // Pointer -> Integer +HANDLE_CAST_INST(43, IntToPtr, IntToPtrInst) // Integer -> Pointer +HANDLE_CAST_INST(44, BitCast , BitCastInst ) // Type cast + LAST_CAST_INST(44) // Other operators... - FIRST_OTHER_INST(42) -HANDLE_OTHER_INST(42, ICmp , ICmpInst ) // Integer comparison instruction -HANDLE_OTHER_INST(43, FCmp , FCmpInst ) // Floating point comparison instr. -HANDLE_OTHER_INST(44, PHI , PHINode ) // PHI node instruction -HANDLE_OTHER_INST(45, Call , CallInst ) // Call a function -HANDLE_OTHER_INST(46, Select , SelectInst ) // select instruction -HANDLE_OTHER_INST(47, UserOp1, Instruction) // May be used internally in a pass -HANDLE_OTHER_INST(48, UserOp2, Instruction) // Internal to passes only -HANDLE_OTHER_INST(49, VAArg , VAArgInst ) // vaarg instruction -HANDLE_OTHER_INST(50, ExtractElement, ExtractElementInst)// extract from vector -HANDLE_OTHER_INST(51, InsertElement, InsertElementInst) // insert into vector -HANDLE_OTHER_INST(52, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. -HANDLE_OTHER_INST(53, ExtractValue, ExtractValueInst)// extract from aggregate -HANDLE_OTHER_INST(54, InsertValue, InsertValueInst) // insert into aggregate + FIRST_OTHER_INST(45) +HANDLE_OTHER_INST(45, ICmp , ICmpInst ) // Integer comparison instruction +HANDLE_OTHER_INST(46, FCmp , FCmpInst ) // Floating point comparison instr. +HANDLE_OTHER_INST(47, PHI , PHINode ) // PHI node instruction +HANDLE_OTHER_INST(48, Call , CallInst ) // Call a function +HANDLE_OTHER_INST(49, Select , SelectInst ) // select instruction +HANDLE_OTHER_INST(50, UserOp1, Instruction) // May be used internally in a pass +HANDLE_OTHER_INST(51, UserOp2, Instruction) // Internal to passes only +HANDLE_OTHER_INST(52, VAArg , VAArgInst ) // vaarg instruction +HANDLE_OTHER_INST(53, ExtractElement, ExtractElementInst)// extract from vector +HANDLE_OTHER_INST(54, InsertElement, InsertElementInst) // insert into vector +HANDLE_OTHER_INST(55, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. +HANDLE_OTHER_INST(56, ExtractValue, ExtractValueInst)// extract from aggregate +HANDLE_OTHER_INST(57, InsertValue, InsertValueInst) // insert into aggregate - LAST_OTHER_INST(54) + LAST_OTHER_INST(57) #undef FIRST_TERM_INST #undef HANDLE_TERM_INST Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Jul 25 18:16:38 2011 @@ -22,6 +22,7 @@ #include "llvm/CallingConv.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/Support/ErrorHandling.h" #include namespace llvm { @@ -31,6 +32,22 @@ class APInt; class LLVMContext; +enum AtomicOrdering { + NotAtomic = 0, + Unordered = 1, + Monotonic = 2, + // Consume = 3, // Not specified yet. + Acquire = 4, + Release = 5, + AcquireRelease = 6, + SequentiallyConsistent = 7 +}; + +enum SynchronizationScope { + SingleThread = 0, + CrossThread = 1 +}; + //===----------------------------------------------------------------------===// // AllocaInst Class //===----------------------------------------------------------------------===// @@ -269,6 +286,82 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value) //===----------------------------------------------------------------------===// +// FenceInst Class +//===----------------------------------------------------------------------===// + +/// FenceInst - an instruction for ordering other memory operations +/// +class FenceInst : public Instruction { + void *operator new(size_t, unsigned); // DO NOT IMPLEMENT + void Init(AtomicOrdering Ordering, SynchronizationScope SynchScope); +protected: + virtual FenceInst *clone_impl() const; +public: + // allocate space for exactly zero operands + void *operator new(size_t s) { + return User::operator new(s, 0); + } + + // Ordering may only be Acquire, Release, AcquireRelease, or + // SequentiallyConsistent. + FenceInst(LLVMContext &C, AtomicOrdering Ordering, + SynchronizationScope SynchScope = CrossThread, + Instruction *InsertBefore = 0); + FenceInst(LLVMContext &C, AtomicOrdering Ordering, + SynchronizationScope SynchScope, + BasicBlock *InsertAtEnd); + + /// Returns the ordering effect of this fence. + AtomicOrdering getOrdering() const { + return AtomicOrdering(getSubclassDataFromInstruction() >> 1); + } + + /// Set the ordering constraint on this fence. May only be Acquire, Release, + /// AcquireRelease, or SequentiallyConsistent. + void setOrdering(AtomicOrdering Ordering) { + switch (Ordering) { + case Acquire: + case Release: + case AcquireRelease: + case SequentiallyConsistent: + setInstructionSubclassData((getSubclassDataFromInstruction() & 1) | + (Ordering << 1)); + return; + default: + llvm_unreachable("FenceInst ordering must be Acquire, Release," + " AcquireRelease, or SequentiallyConsistent"); + } + } + + SynchronizationScope getSynchScope() const { + return SynchronizationScope(getSubclassDataFromInstruction() & 1); + } + + /// Specify whether this fence orders other operations with respect to all + /// concurrently executing threads, or only with respect to signal handlers + /// executing in the same thread. + void setSynchScope(SynchronizationScope xthread) { + setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) | + xthread); + } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const FenceInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Fence; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +private: + // Shadow Instruction::setInstructionSubclassData with a private forwarding + // method so that subclasses cannot accidentally use it. + void setInstructionSubclassData(unsigned short D) { + Instruction::setInstructionSubclassData(D); + } +}; + +//===----------------------------------------------------------------------===// // GetElementPtrInst Class //===----------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Mon Jul 25 18:16:38 2011 @@ -762,6 +762,10 @@ StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) { return Insert(new StoreInst(Val, Ptr, isVolatile)); } + FenceInst *CreateFence(AtomicOrdering Ordering, + SynchronizationScope SynchScope = CrossThread) { + return Insert(new FenceInst(Context, Ordering, SynchScope)); + } Value *CreateGEP(Value *Ptr, ArrayRef IdxList, const Twine &Name = "") { if (Constant *PC = dyn_cast(Ptr)) { Modified: llvm/trunk/include/llvm/Support/InstVisitor.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/InstVisitor.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/InstVisitor.h (original) +++ llvm/trunk/include/llvm/Support/InstVisitor.h Mon Jul 25 18:16:38 2011 @@ -169,6 +169,7 @@ RetTy visitAllocaInst(AllocaInst &I) { DELEGATE(Instruction); } RetTy visitLoadInst(LoadInst &I) { DELEGATE(Instruction); } RetTy visitStoreInst(StoreInst &I) { DELEGATE(Instruction); } + RetTy visitFenceInst(FenceInst &I) { DELEGATE(Instruction); } RetTy visitGetElementPtrInst(GetElementPtrInst &I){ DELEGATE(Instruction); } RetTy visitPHINode(PHINode &I) { DELEGATE(Instruction); } RetTy visitTruncInst(TruncInst &I) { DELEGATE(CastInst); } Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Jul 25 18:16:38 2011 @@ -506,6 +506,15 @@ KEYWORD(deplibs); KEYWORD(datalayout); KEYWORD(volatile); + KEYWORD(atomic); + KEYWORD(unordered); + KEYWORD(monotonic); + KEYWORD(acquire); + KEYWORD(release); + KEYWORD(acq_rel); + KEYWORD(seq_cst); + KEYWORD(singlethread); + KEYWORD(nuw); KEYWORD(nsw); KEYWORD(exact); @@ -630,6 +639,7 @@ INSTKEYWORD(alloca, Alloca); INSTKEYWORD(load, Load); INSTKEYWORD(store, Store); + INSTKEYWORD(fence, Fence); INSTKEYWORD(getelementptr, GetElementPtr); INSTKEYWORD(extractelement, ExtractElement); Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Jul 25 18:16:38 2011 @@ -1145,6 +1145,32 @@ return false; } +/// ParseScopeAndOrdering +/// if isAtomic: ::= 'singlethread'? AtomicOrdering +/// else: ::= +/// +/// This sets Scope and Ordering to the parsed values. +bool LLParser::ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope, + AtomicOrdering &Ordering) { + if (!isAtomic) + return false; + + Scope = CrossThread; + if (EatIfPresent(lltok::kw_singlethread)) + Scope = SingleThread; + switch (Lex.getKind()) { + default: return TokError("Expected ordering on atomic instruction"); + case lltok::kw_unordered: Ordering = Unordered; break; + case lltok::kw_monotonic: Ordering = Monotonic; break; + case lltok::kw_acquire: Ordering = Acquire; break; + case lltok::kw_release: Ordering = Release; break; + case lltok::kw_acq_rel: Ordering = AcquireRelease; break; + case lltok::kw_seq_cst: Ordering = SequentiallyConsistent; break; + } + Lex.Lex(); + return false; +} + /// ParseOptionalStackAlignment /// ::= /* empty */ /// ::= 'alignstack' '(' 4 ')' @@ -2924,6 +2950,7 @@ case lltok::kw_alloca: return ParseAlloc(Inst, PFS); case lltok::kw_load: return ParseLoad(Inst, PFS, false); case lltok::kw_store: return ParseStore(Inst, PFS, false); + case lltok::kw_fence: return ParseFence(Inst, PFS); case lltok::kw_volatile: if (EatIfPresent(lltok::kw_load)) return ParseLoad(Inst, PFS, true); @@ -3633,6 +3660,23 @@ return AteExtraComma ? InstExtraComma : InstNormal; } +/// ParseFence +/// ::= 'fence' 'singlethread'? AtomicOrdering +int LLParser::ParseFence(Instruction *&Inst, PerFunctionState &PFS) { + AtomicOrdering Ordering = NotAtomic; + SynchronizationScope Scope = CrossThread; + if (ParseScopeAndOrdering(true /*Always atomic*/, Scope, Ordering)) + return true; + + if (Ordering == Unordered) + return TokError("fence cannot be unordered"); + if (Ordering == Monotonic) + return TokError("fence cannot be monotonic"); + + Inst = new FenceInst(Context, Ordering, Scope); + return InstNormal; +} + /// ParseGetElementPtr /// ::= 'getelementptr' 'inbounds'? TypeAndValue (',' TypeAndValue)* int LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) { Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Mon Jul 25 18:16:38 2011 @@ -15,6 +15,7 @@ #define LLVM_ASMPARSER_LLPARSER_H #include "LLLexer.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Type.h" #include "llvm/ADT/DenseMap.h" @@ -178,6 +179,8 @@ bool ParseOptionalVisibility(unsigned &Visibility); bool ParseOptionalCallingConv(CallingConv::ID &CC); bool ParseOptionalAlignment(unsigned &Alignment); + bool ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope, + AtomicOrdering &Ordering); bool ParseOptionalStackAlignment(unsigned &Alignment); bool ParseOptionalCommaAlign(unsigned &Alignment, bool &AteExtraComma); bool ParseIndexList(SmallVectorImpl &Indices,bool &AteExtraComma); @@ -360,6 +363,7 @@ int ParseAlloc(Instruction *&I, PerFunctionState &PFS); int ParseLoad(Instruction *&I, PerFunctionState &PFS, bool isVolatile); int ParseStore(Instruction *&I, PerFunctionState &PFS, bool isVolatile); + int ParseFence(Instruction *&I, PerFunctionState &PFS); int ParseGetElementPtr(Instruction *&I, PerFunctionState &PFS); int ParseExtractValue(Instruction *&I, PerFunctionState &PFS); int ParseInsertValue(Instruction *&I, PerFunctionState &PFS); Modified: llvm/trunk/lib/AsmParser/LLToken.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLToken.h (original) +++ llvm/trunk/lib/AsmParser/LLToken.h Mon Jul 25 18:16:38 2011 @@ -53,6 +53,9 @@ kw_deplibs, kw_datalayout, kw_volatile, + kw_atomic, + kw_unordered, kw_monotonic, kw_acquire, kw_release, kw_acq_rel, kw_seq_cst, + kw_singlethread, kw_nuw, kw_nsw, kw_exact, @@ -121,7 +124,7 @@ kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind, kw_unreachable, - kw_alloca, kw_load, kw_store, kw_getelementptr, + kw_alloca, kw_load, kw_store, kw_fence, kw_getelementptr, kw_extractelement, kw_insertelement, kw_shufflevector, kw_extractvalue, kw_insertvalue, kw_blockaddress, Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Jul 25 18:16:38 2011 @@ -131,6 +131,27 @@ } } +static AtomicOrdering GetDecodedOrdering(unsigned Val) { + switch (Val) { + case bitc::ORDERING_NOTATOMIC: return NotAtomic; + case bitc::ORDERING_UNORDERED: return Unordered; + case bitc::ORDERING_MONOTONIC: return Monotonic; + case bitc::ORDERING_ACQUIRE: return Acquire; + case bitc::ORDERING_RELEASE: return Release; + case bitc::ORDERING_ACQREL: return AcquireRelease; + default: // Map unknown orderings to sequentially-consistent. + case bitc::ORDERING_SEQCST: return SequentiallyConsistent; + } +} + +static SynchronizationScope GetDecodedSynchScope(unsigned Val) { + switch (Val) { + case bitc::SYNCHSCOPE_SINGLETHREAD: return SingleThread; + default: // Map unknown scopes to cross-thread. + case bitc::SYNCHSCOPE_CROSSTHREAD: return CrossThread; + } +} + namespace llvm { namespace { /// @brief A class for maintaining the slot number definition @@ -2534,6 +2555,18 @@ InstructionList.push_back(I); break; } + case bitc::FUNC_CODE_INST_FENCE: { // FENCE:[ordering, synchscope] + if (2 != Record.size()) + return Error("Invalid FENCE record"); + AtomicOrdering Ordering = GetDecodedOrdering(Record[0]); + if (Ordering == NotAtomic || Ordering == Unordered || + Ordering == Monotonic) + return Error("Invalid FENCE record"); + SynchronizationScope SynchScope = GetDecodedSynchScope(Record[1]); + I = new FenceInst(Context, Ordering, SynchScope); + InstructionList.push_back(I); + break; + } case bitc::FUNC_CODE_INST_CALL: { // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...] if (Record.size() < 3) Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Jul 25 18:16:38 2011 @@ -101,6 +101,27 @@ } } +static unsigned GetEncodedOrdering(AtomicOrdering Ordering) { + switch (Ordering) { + default: llvm_unreachable("Unknown atomic ordering"); + case NotAtomic: return bitc::ORDERING_NOTATOMIC; + case Unordered: return bitc::ORDERING_UNORDERED; + case Monotonic: return bitc::ORDERING_MONOTONIC; + case Acquire: return bitc::ORDERING_ACQUIRE; + case Release: return bitc::ORDERING_RELEASE; + case AcquireRelease: return bitc::ORDERING_ACQREL; + case SequentiallyConsistent: return bitc::ORDERING_SEQCST; + } +} + +static unsigned GetEncodedSynchScope(SynchronizationScope SynchScope) { + switch (SynchScope) { + default: llvm_unreachable("Unknown synchronization scope"); + case SingleThread: return bitc::SYNCHSCOPE_SINGLETHREAD; + case CrossThread: return bitc::SYNCHSCOPE_CROSSTHREAD; + } +} + static void WriteStringRecord(unsigned Code, StringRef Str, unsigned AbbrevToUse, BitstreamWriter &Stream) { SmallVector Vals; @@ -1147,6 +1168,11 @@ Vals.push_back(Log2_32(cast(I).getAlignment())+1); Vals.push_back(cast(I).isVolatile()); break; + case Instruction::Fence: + Code = bitc::FUNC_CODE_INST_FENCE; + Vals.push_back(GetEncodedOrdering(cast(I).getOrdering())); + Vals.push_back(GetEncodedSynchScope(cast(I).getSynchScope())); + break; case Instruction::Call: { const CallInst &CI = cast(I); PointerType *PTy = cast(CI.getCalledValue()->getType()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jul 25 18:16:38 2011 @@ -3211,6 +3211,10 @@ DAG.setRoot(StoreNode); } +void SelectionDAGBuilder::visitFence(const FenceInst &I) { + llvm_unreachable("Not implemented yet"); +} + /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC /// node. void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Mon Jul 25 18:16:38 2011 @@ -504,6 +504,7 @@ void visitAlloca(const AllocaInst &I); void visitLoad(const LoadInst &I); void visitStore(const StoreInst &I); + void visitFence(const FenceInst &I); void visitPHI(const PHINode &I); void visitCall(const CallInst &I); bool visitMemCmpCall(const CallInst &I); Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Jul 25 18:16:38 2011 @@ -1098,6 +1098,7 @@ void writeOperand(const Value *Op, bool PrintType); void writeParamOperand(const Value *Operand, Attributes Attrs); + void writeAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope); void writeAllMDNodes(); @@ -1128,6 +1129,28 @@ WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule); } +void AssemblyWriter::writeAtomic(AtomicOrdering Ordering, + SynchronizationScope SynchScope) { + if (Ordering == NotAtomic) + return; + + switch (SynchScope) { + default: Out << " "; break; + case SingleThread: Out << " singlethread"; break; + case CrossThread: break; + } + + switch (Ordering) { + default: Out << " "; break; + case Unordered: Out << " unordered"; break; + case Monotonic: Out << " monotonic"; break; + case Acquire: Out << " acquire"; break; + case Release: Out << " release"; break; + case AcquireRelease: Out << " acq_rel"; break; + case SequentiallyConsistent: Out << " seq_cst"; break; + } +} + void AssemblyWriter::writeParamOperand(const Value *Operand, Attributes Attrs) { if (Operand == 0) { @@ -1883,6 +1906,8 @@ Out << ", align " << cast(I).getAlignment(); } else if (isa(I) && cast(I).getAlignment()) { Out << ", align " << cast(I).getAlignment(); + } else if (const FenceInst *FI = dyn_cast(&I)) { + writeAtomic(FI->getOrdering(), FI->getSynchScope()); } // Print Metadata info. Modified: llvm/trunk/lib/VMCore/Instruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instruction.cpp (original) +++ llvm/trunk/lib/VMCore/Instruction.cpp Mon Jul 25 18:16:38 2011 @@ -127,6 +127,7 @@ case Alloca: return "alloca"; case Load: return "load"; case Store: return "store"; + case Fence: return "fence"; case GetElementPtr: return "getelementptr"; // Convert instructions... Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jul 25 18:16:38 2011 @@ -996,6 +996,26 @@ } //===----------------------------------------------------------------------===// +// FenceInst Implementation +//===----------------------------------------------------------------------===// + +FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering, + SynchronizationScope SynchScope, + Instruction *InsertBefore) + : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertBefore) { + setOrdering(Ordering); + setSynchScope(SynchScope); +} + +FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering, + SynchronizationScope SynchScope, + BasicBlock *InsertAtEnd) + : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertAtEnd) { + setOrdering(Ordering); + setSynchScope(SynchScope); +} + +//===----------------------------------------------------------------------===// // GetElementPtrInst Implementation //===----------------------------------------------------------------------===// @@ -3018,6 +3038,10 @@ isVolatile(), getAlignment()); } +FenceInst *FenceInst::clone_impl() const { + return new FenceInst(getContext(), getOrdering(), getSynchScope()); +} + TruncInst *TruncInst::clone_impl() const { return new TruncInst(getOperand(0), getType()); } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=136009&r1=136008&r2=136009&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jul 25 18:16:38 2011 @@ -278,6 +278,7 @@ void visitUserOp1(Instruction &I); void visitUserOp2(Instruction &I) { visitUserOp1(I); } void visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI); + void visitFenceInst(FenceInst &FI); void visitAllocaInst(AllocaInst &AI); void visitExtractValueInst(ExtractValueInst &EVI); void visitInsertValueInst(InsertValueInst &IVI); @@ -1315,6 +1316,15 @@ visitInstruction(AI); } +void Verifier::visitFenceInst(FenceInst &FI) { + const AtomicOrdering Ordering = FI.getOrdering(); + Assert1(Ordering == Acquire || Ordering == Release || + Ordering == AcquireRelease || Ordering == SequentiallyConsistent, + "fence instructions may only have " + " acquire, release, acq_rel, or seq_cst ordering.", &FI); + visitInstruction(FI); +} + void Verifier::visitExtractValueInst(ExtractValueInst &EVI) { Assert1(ExtractValueInst::getIndexedType(EVI.getAggregateOperand()->getType(), EVI.getIndices()) == From evan.cheng at apple.com Mon Jul 25 18:24:55 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 23:24:55 -0000 Subject: [llvm-commits] [llvm] r136010 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/MC/ lib/Target/ARM/MCTargetDesc/ lib/Target/MBlaze/MCTargetDesc/ lib/Target/PTX/ lib/Target/PowerPC/MCTargetDesc/ lib/Target/X86/MCTargetDesc/ tools/llvm-mc/ Message-ID: <20110725232456.5DBBC2A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 18:24:55 2011 New Revision: 136010 URL: http://llvm.org/viewvc/llvm-project?rev=136010&view=rev Log: Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend. Added: llvm/trunk/include/llvm/MC/MCAsmBackend.h - copied, changed from r135998, llvm/trunk/include/llvm/MC/TargetAsmBackend.h llvm/trunk/lib/MC/MCAsmBackend.cpp - copied, changed from r135983, llvm/trunk/lib/MC/TargetAsmBackend.cpp Removed: llvm/trunk/include/llvm/MC/TargetAsmBackend.h llvm/trunk/lib/MC/TargetAsmBackend.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MCELF.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCELFStreamer.h llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/MC/MCPureStreamer.cpp llvm/trunk/lib/MC/MachObjectWriter.cpp llvm/trunk/lib/MC/WinCOFFStreamer.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp Copied: llvm/trunk/include/llvm/MC/MCAsmBackend.h (from r135998, llvm/trunk/include/llvm/MC/TargetAsmBackend.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?p2=llvm/trunk/include/llvm/MC/MCAsmBackend.h&p1=llvm/trunk/include/llvm/MC/TargetAsmBackend.h&r1=135998&r2=136010&rev=136010&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmBackend.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Mon Jul 25 18:24:55 2011 @@ -1,4 +1,4 @@ -//===-- llvm/MC/TargetAsmBackend.h - Target Asm Backend ---------*- C++ -*-===// +//===-- llvm/MC/MCAsmBack.h - MC Asm Backend --------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_MC_TARGETASMBACKEND_H -#define LLVM_MC_TARGETASMBACKEND_H +#ifndef LLVM_MC_MCASMBACKEND_H +#define LLVM_MC_MCASMBACKEND_H #include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCFixup.h" @@ -25,17 +25,17 @@ class SmallVectorImpl; class raw_ostream; -/// TargetAsmBackend - Generic interface to target specific assembler backends. -class TargetAsmBackend { - TargetAsmBackend(const TargetAsmBackend &); // DO NOT IMPLEMENT - void operator=(const TargetAsmBackend &); // DO NOT IMPLEMENT +/// MCAsmBackend - Generic interface to target specific assembler backends. +class MCAsmBackend { + MCAsmBackend(const MCAsmBackend &); // DO NOT IMPLEMENT + void operator=(const MCAsmBackend &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetAsmBackend(); + MCAsmBackend(); unsigned HasReliableSymbolDifference : 1; public: - virtual ~TargetAsmBackend(); + virtual ~MCAsmBackend(); /// createObjectWriter - Create a new MCObjectWriter instance for use by the /// assembler backend to emit the final object file. Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Jul 25 18:24:55 2011 @@ -10,14 +10,14 @@ #ifndef LLVM_MC_MCASSEMBLER_H #define LLVM_MC_MCASSEMBLER_H +#include "llvm/MC/MCFixup.h" +#include "llvm/MC/MCInst.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist_node.h" #include "llvm/Support/Casting.h" -#include "llvm/MC/MCFixup.h" -#include "llvm/MC/MCInst.h" #include "llvm/Support/DataTypes.h" #include // FIXME: Shouldn't be needed. @@ -36,7 +36,7 @@ class MCSymbol; class MCSymbolData; class MCValue; -class TargetAsmBackend; +class MCAsmBackend; class MCFragment : public ilist_node { friend class MCAsmLayout; @@ -660,7 +660,7 @@ MCContext &Context; - TargetAsmBackend &Backend; + MCAsmBackend &Backend; MCCodeEmitter &Emitter; @@ -780,14 +780,14 @@ // concrete and require clients to pass in a target like object. The other // option is to make this abstract, and have targets provide concrete // implementations as we do with AsmParser. - MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_, + MCAssembler(MCContext &Context_, MCAsmBackend &Backend_, MCCodeEmitter &Emitter_, MCObjectWriter &Writer_, raw_ostream &OS); ~MCAssembler(); MCContext &getContext() const { return Context; } - TargetAsmBackend &getBackend() const { return Backend; } + MCAsmBackend &getBackend() const { return Backend; } MCCodeEmitter &getEmitter() const { return Emitter; } Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Mon Jul 25 18:24:55 2011 @@ -19,7 +19,7 @@ class MCExpr; class MCFragment; class MCDataFragment; -class TargetAsmBackend; +class MCAsmBackend; class raw_ostream; /// \brief Streaming object file generation interface. @@ -36,9 +36,9 @@ virtual void EmitInstToData(const MCInst &Inst) = 0; protected: - MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter); - MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, MCAssembler *_Assembler); ~MCObjectStreamer(); Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Mon Jul 25 18:24:55 2011 @@ -22,6 +22,7 @@ #include "llvm/ADT/SmallVector.h" namespace llvm { + class MCAsmBackend; class MCAsmInfo; class MCCodeEmitter; class MCContext; @@ -31,7 +32,6 @@ class MCSection; class MCSymbol; class StringRef; - class TargetAsmBackend; class TargetLoweringObjectFile; class Twine; class raw_ostream; @@ -563,14 +563,14 @@ bool useCFI, MCInstPrinter *InstPrint = 0, MCCodeEmitter *CE = 0, - TargetAsmBackend *TAB = 0, + MCAsmBackend *TAB = 0, bool ShowInst = false); /// createMachOStreamer - Create a machine code streamer which will generate /// Mach-O format object files. /// /// Takes ownership of \arg TAB and \arg CE. - MCStreamer *createMachOStreamer(MCContext &Ctx, TargetAsmBackend &TAB, + MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll = false); @@ -579,13 +579,13 @@ /// /// Takes ownership of \arg TAB and \arg CE. MCStreamer *createWinCOFFStreamer(MCContext &Ctx, - TargetAsmBackend &TAB, + MCAsmBackend &TAB, MCCodeEmitter &CE, raw_ostream &OS, bool RelaxAll = false); /// createELFStreamer - Create a machine code streamer which will generate /// ELF format object files. - MCStreamer *createELFStreamer(MCContext &Ctx, TargetAsmBackend &TAB, + MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll, bool NoExecStack); @@ -599,7 +599,7 @@ /// "pure" MC object files, for use with MC-JIT and testing tools. /// /// Takes ownership of \arg TAB and \arg CE. - MCStreamer *createPureStreamer(MCContext &Ctx, TargetAsmBackend &TAB, + MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE); } // end namespace llvm Removed: llvm/trunk/include/llvm/MC/TargetAsmBackend.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmBackend.h?rev=136009&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmBackend.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmBackend.h (removed) @@ -1,131 +0,0 @@ -//===-- llvm/MC/TargetAsmBackend.h - Target Asm Backend ---------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_TARGETASMBACKEND_H -#define LLVM_MC_TARGETASMBACKEND_H - -#include "llvm/MC/MCDirectives.h" -#include "llvm/MC/MCFixup.h" -#include "llvm/MC/MCFixupKindInfo.h" -#include "llvm/Support/DataTypes.h" - -namespace llvm { -class MCELFObjectTargetWriter; -class MCFixup; -class MCInst; -class MCObjectWriter; -class MCSection; -template -class SmallVectorImpl; -class raw_ostream; - -/// TargetAsmBackend - Generic interface to target specific assembler backends. -class TargetAsmBackend { - TargetAsmBackend(const TargetAsmBackend &); // DO NOT IMPLEMENT - void operator=(const TargetAsmBackend &); // DO NOT IMPLEMENT -protected: // Can only create subclasses. - TargetAsmBackend(); - - unsigned HasReliableSymbolDifference : 1; - -public: - virtual ~TargetAsmBackend(); - - /// createObjectWriter - Create a new MCObjectWriter instance for use by the - /// assembler backend to emit the final object file. - virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0; - - /// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to enable - /// non-standard ELFObjectWriters. - virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const { - assert(0 && "createELFObjectTargetWriter is not supported by asm backend"); - return 0; - } - - /// hasReliableSymbolDifference - Check whether this target implements - /// accurate relocations for differences between symbols. If not, differences - /// between symbols will always be relocatable expressions and any references - /// to temporary symbols will be assumed to be in the same atom, unless they - /// reside in a different section. - /// - /// This should always be true (since it results in fewer relocations with no - /// loss of functionality), but is currently supported as a way to maintain - /// exact object compatibility with Darwin 'as' (on non-x86_64). It should - /// eventually should be eliminated. - bool hasReliableSymbolDifference() const { - return HasReliableSymbolDifference; - } - - /// doesSectionRequireSymbols - Check whether the given section requires that - /// all symbols (even temporaries) have symbol table entries. - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { - return false; - } - - /// isSectionAtomizable - Check whether the given section can be split into - /// atoms. - /// - /// \see MCAssembler::isSymbolLinkerVisible(). - virtual bool isSectionAtomizable(const MCSection &Section) const { - return true; - } - - /// @name Target Fixup Interfaces - /// @{ - - /// getNumFixupKinds - Get the number of target specific fixup kinds. - virtual unsigned getNumFixupKinds() const = 0; - - /// getFixupKindInfo - Get information on a fixup kind. - virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const; - - /// @} - - /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided - /// data fragment, at the offset specified by the fixup and following the - /// fixup kind as appropriate. - virtual void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const = 0; - - /// @} - - /// @name Target Relaxation Interfaces - /// @{ - - /// MayNeedRelaxation - Check whether the given instruction may need - /// relaxation. - /// - /// \param Inst - The instruction to test. - virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0; - - /// RelaxInstruction - Relax the instruction in the given fragment to the next - /// wider instruction. - /// - /// \param Inst - The instruction to relax, which may be the same as the - /// output. - /// \parm Res [output] - On return, the relaxed instruction. - virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0; - - /// @} - - /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given - /// output. If the target cannot generate such a sequence, it should return an - /// error. - /// - /// \return - True on success. - virtual bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const = 0; - - /// HandleAssemblerFlag - Handle any target-specific assembler flags. - /// By default, do nothing. - virtual void HandleAssemblerFlag(MCAssemblerFlag Flag) {} -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Mon Jul 25 18:24:55 2011 @@ -39,7 +39,7 @@ class MCStreamer; class MCSubtargetInfo; class MCCodeGenInfo; - class TargetAsmBackend; + class MCAsmBackend; class TargetAsmLexer; class TargetAsmParser; class TargetMachine; @@ -51,7 +51,7 @@ bool useLoc, bool useCFI, MCInstPrinter *InstPrint, MCCodeEmitter *CE, - TargetAsmBackend *TAB, + MCAsmBackend *TAB, bool ShowInst); /// Target - Wrapper for Target specific information. @@ -86,8 +86,7 @@ CodeModel::Model CM); typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); - typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T, - const std::string &TT); + typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI); @@ -103,7 +102,7 @@ typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T, const std::string &TT, MCContext &Ctx, - TargetAsmBackend &TAB, + MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, @@ -115,7 +114,7 @@ bool useCFI, MCInstPrinter *InstPrint, MCCodeEmitter *CE, - TargetAsmBackend *TAB, + MCAsmBackend *TAB, bool ShowInst); private: @@ -160,9 +159,9 @@ /// TargetMachine, if registered. TargetMachineCtorTy TargetMachineCtorFn; - /// AsmBackendCtorFn - Construction function for this target's - /// TargetAsmBackend, if registered. - AsmBackendCtorTy AsmBackendCtorFn; + /// MCAsmBackendCtorFn - Construction function for this target's + /// MCAsmBackend, if registered. + MCAsmBackendCtorTy MCAsmBackendCtorFn; /// AsmLexerCtorFn - Construction function for this target's TargetAsmLexer, /// if registered. @@ -221,8 +220,8 @@ /// hasTargetMachine - Check if this target supports code generation. bool hasTargetMachine() const { return TargetMachineCtorFn != 0; } - /// hasAsmBackend - Check if this target supports .o generation. - bool hasAsmBackend() const { return AsmBackendCtorFn != 0; } + /// hasMCAsmBackend - Check if this target supports .o generation. + bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; } /// hasAsmLexer - Check if this target supports .s lexing. bool hasAsmLexer() const { return AsmLexerCtorFn != 0; } @@ -322,14 +321,14 @@ return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM); } - /// createAsmBackend - Create a target specific assembly parser. + /// createMCAsmBackend - Create a target specific assembly parser. /// /// \arg Triple - The target triple string. /// \arg Backend - The target independent assembler object. - TargetAsmBackend *createAsmBackend(const std::string &Triple) const { - if (!AsmBackendCtorFn) + MCAsmBackend *createMCAsmBackend(StringRef Triple) const { + if (!MCAsmBackendCtorFn) return 0; - return AsmBackendCtorFn(*this, Triple); + return MCAsmBackendCtorFn(*this, Triple); } /// createAsmLexer - Create a target specific assembly lexer. @@ -393,7 +392,7 @@ /// \arg RelaxAll - Relax all fixups? /// \arg NoExecStack - Mark file as not needing a executable stack. MCStreamer *createObjectStreamer(const std::string &TT, MCContext &Ctx, - TargetAsmBackend &TAB, + MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, @@ -412,7 +411,7 @@ bool useCFI, MCInstPrinter *InstPrint, MCCodeEmitter *CE, - TargetAsmBackend *TAB, + MCAsmBackend *TAB, bool ShowInst) const { // AsmStreamerCtorFn is default to llvm::createAsmStreamer return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI, @@ -605,7 +604,7 @@ T.TargetMachineCtorFn = Fn; } - /// RegisterAsmBackend - Register a TargetAsmBackend implementation for the + /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the /// given target. /// /// Clients are responsible for ensuring that registration doesn't occur @@ -614,9 +613,9 @@ /// /// @param T - The target being registered. /// @param Fn - A function to construct an AsmBackend for the target. - static void RegisterAsmBackend(Target &T, Target::AsmBackendCtorTy Fn) { - if (!T.AsmBackendCtorFn) - T.AsmBackendCtorFn = Fn; + static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) { + if (!T.MCAsmBackendCtorFn) + T.MCAsmBackendCtorFn = Fn; } /// RegisterAsmLexer - Register a TargetAsmLexer implementation for the @@ -956,23 +955,22 @@ } }; - /// RegisterAsmBackend - Helper template for registering a target specific + /// RegisterMCAsmBackend - Helper template for registering a target specific /// assembler backend. Usage: /// - /// extern "C" void LLVMInitializeFooAsmBackend() { + /// extern "C" void LLVMInitializeFooMCAsmBackend() { /// extern Target TheFooTarget; - /// RegisterAsmBackend X(TheFooTarget); + /// RegisterMCAsmBackend X(TheFooTarget); /// } - template - struct RegisterAsmBackend { - RegisterAsmBackend(Target &T) { - TargetRegistry::RegisterAsmBackend(T, &Allocator); + template + struct RegisterMCAsmBackend { + RegisterMCAsmBackend(Target &T) { + TargetRegistry::RegisterMCAsmBackend(T, &Allocator); } private: - static TargetAsmBackend *Allocator(const Target &T, - const std::string &Triple) { - return new AsmBackendImpl(T, Triple); + static MCAsmBackend *Allocator(const Target &T, StringRef Triple) { + return new MCAsmBackendImpl(T, Triple); } }; Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Jul 25 18:24:55 2011 @@ -137,11 +137,11 @@ // Create a code emitter if asked to show the encoding. MCCodeEmitter *MCE = 0; - TargetAsmBackend *TAB = 0; + MCAsmBackend *MAB = 0; if (ShowMCEncoding) { const MCSubtargetInfo &STI = getSubtarget(); MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, *Context); - TAB = getTarget().createAsmBackend(getTargetTriple()); + MAB = getTarget().createMCAsmBackend(getTargetTriple()); } MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, @@ -149,7 +149,7 @@ hasMCUseLoc(), hasMCUseCFI(), InstPrinter, - MCE, TAB, + MCE, MAB, ShowMCInst); AsmStreamer.reset(S); break; @@ -160,12 +160,12 @@ const MCSubtargetInfo &STI = getSubtarget(); MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, *Context); - TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); - if (MCE == 0 || TAB == 0) + MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple()); + if (MCE == 0 || MAB == 0) return true; AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), - *Context, *TAB, Out, MCE, + *Context, *MAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); AsmStreamer.get()->InitSections(); @@ -237,13 +237,13 @@ // emission fails. const MCSubtargetInfo &STI = getSubtarget(); MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(),STI, *Ctx); - TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); - if (MCE == 0 || TAB == 0) + MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple()); + if (MCE == 0 || MAB == 0) return true; OwningPtr AsmStreamer; AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx, - *TAB, Out, MCE, + *MAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); AsmStreamer.get()->InitSections(); Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Jul 25 18:24:55 2011 @@ -15,12 +15,12 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/Twine.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCValue.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ELF.h" Copied: llvm/trunk/lib/MC/MCAsmBackend.cpp (from r135983, llvm/trunk/lib/MC/TargetAsmBackend.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmBackend.cpp?p2=llvm/trunk/lib/MC/MCAsmBackend.cpp&p1=llvm/trunk/lib/MC/TargetAsmBackend.cpp&r1=135983&r2=136010&rev=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/TargetAsmBackend.cpp (original) +++ llvm/trunk/lib/MC/MCAsmBackend.cpp Mon Jul 25 18:24:55 2011 @@ -1,4 +1,4 @@ -//===-- TargetAsmBackend.cpp - Target Assembly Backend ---------------------==// +//===-- MCAsmBackend.cpp - Target MC Assembly Backend ----------------------==// // // The LLVM Compiler Infrastructure // @@ -7,19 +7,19 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" using namespace llvm; -TargetAsmBackend::TargetAsmBackend() +MCAsmBackend::MCAsmBackend() : HasReliableSymbolDifference(false) { } -TargetAsmBackend::~TargetAsmBackend() { +MCAsmBackend::~MCAsmBackend() { } const MCFixupKindInfo & -TargetAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { +MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { static const MCFixupKindInfo Builtins[] = { { "FK_Data_1", 0, 8, 0 }, { "FK_Data_2", 0, 16, 0 }, Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" @@ -41,7 +41,7 @@ private: OwningPtr InstPrinter; OwningPtr Emitter; - OwningPtr AsmBackend; + OwningPtr AsmBackend; SmallString<128> CommentToEmit; raw_svector_ostream CommentStream; @@ -64,7 +64,7 @@ MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os, bool isVerboseAsm, bool useLoc, bool useCFI, MCInstPrinter *printer, MCCodeEmitter *emitter, - TargetAsmBackend *asmbackend, + MCAsmBackend *asmbackend, bool showInst) : MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()), InstPrinter(printer), Emitter(emitter), AsmBackend(asmbackend), @@ -1262,8 +1262,8 @@ formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, bool useCFI, MCInstPrinter *IP, - MCCodeEmitter *CE, TargetAsmBackend *TAB, + MCCodeEmitter *CE, MCAsmBackend *MAB, bool ShowInst) { return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc, useCFI, - IP, CE, TAB, ShowInst); + IP, CE, MAB, ShowInst); } Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Jul 25 18:24:55 2011 @@ -18,7 +18,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCValue.h" #include "llvm/MC/MCDwarf.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringExtras.h" @@ -194,7 +194,7 @@ /* *** */ -MCAssembler::MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_, +MCAssembler::MCAssembler(MCContext &Context_, MCAsmBackend &Backend_, MCCodeEmitter &Emitter_, MCObjectWriter &Writer_, raw_ostream &OS_) : Context(Context_), Backend(Backend_), Emitter(Emitter_), Writer(Writer_), Modified: llvm/trunk/lib/MC/MCELF.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELF.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELF.cpp (original) +++ llvm/trunk/lib/MC/MCELF.cpp Mon Jul 25 18:24:55 2011 @@ -15,7 +15,6 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCELFSymbolFlags.h" #include "llvm/MC/MCFixupKindInfo.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/Support/ELF.h" namespace llvm { Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -21,7 +21,7 @@ #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCValue.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -374,10 +374,10 @@ this->MCObjectStreamer::Finish(); } -MCStreamer *llvm::createELFStreamer(MCContext &Context, TargetAsmBackend &TAB, +MCStreamer *llvm::createELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll, bool NoExecStack) { - MCELFStreamer *S = new MCELFStreamer(Context, TAB, OS, CE); + MCELFStreamer *S = new MCELFStreamer(Context, MAB, OS, CE); if (RelaxAll) S->getAssembler().setRelaxAll(true); if (NoExecStack) Modified: llvm/trunk/lib/MC/MCELFStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.h (original) +++ llvm/trunk/lib/MC/MCELFStreamer.h Mon Jul 25 18:24:55 2011 @@ -25,11 +25,11 @@ class MCELFStreamer : public MCObjectStreamer { public: - MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter) : MCObjectStreamer(Context, TAB, OS, Emitter) {} - MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, MCAssembler *Assembler) : MCObjectStreamer(Context, TAB, OS, Emitter, Assembler) {} Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Mon Jul 25 18:24:55 2011 @@ -16,7 +16,6 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCValue.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -20,7 +20,7 @@ #include "llvm/MC/MCMachOSymbolFlags.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCDwarf.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/Support/Dwarf.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -34,9 +34,9 @@ virtual void EmitInstToData(const MCInst &Inst); public: - MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCMachOStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter) - : MCObjectStreamer(Context, TAB, OS, Emitter) {} + : MCObjectStreamer(Context, MAB, OS, Emitter) {} /// @name MCStreamer Interface /// @{ @@ -410,10 +410,10 @@ this->MCObjectStreamer::Finish(); } -MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, +MCStreamer *llvm::createMachOStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll) { - MCMachOStreamer *S = new MCMachOStreamer(Context, TAB, OS, CE); + MCMachOStreamer *S = new MCMachOStreamer(Context, MAB, OS, CE); if (RelaxAll) S->getAssembler().setRelaxAll(true); return S; Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -17,10 +17,10 @@ #include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" using namespace llvm; -MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, +MCObjectStreamer::MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter_) : MCStreamer(Context), Assembler(new MCAssembler(Context, TAB, @@ -30,7 +30,7 @@ { } -MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, +MCObjectStreamer::MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter_, MCAssembler *_Assembler) : MCStreamer(Context), Assembler(_Assembler), CurSectionData(0) Modified: llvm/trunk/lib/MC/MCPureStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCPureStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCPureStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCPureStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -28,7 +28,7 @@ virtual void EmitInstToData(const MCInst &Inst); public: - MCPureStreamer(MCContext &Context, TargetAsmBackend &TAB, + MCPureStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter) : MCObjectStreamer(Context, TAB, OS, Emitter) {} @@ -228,7 +228,7 @@ this->MCObjectStreamer::Finish(); } -MCStreamer *llvm::createPureStreamer(MCContext &Context, TargetAsmBackend &TAB, +MCStreamer *llvm::createPureStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *CE) { - return new MCPureStreamer(Context, TAB, OS, CE); + return new MCPureStreamer(Context, MAB, OS, CE); } Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Mon Jul 25 18:24:55 2011 @@ -12,6 +12,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCObjectWriter.h" @@ -19,7 +20,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCMachOSymbolFlags.h" #include "llvm/MC/MCValue.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/Object/MachOFormat.h" #include "llvm/Support/ErrorHandling.h" Removed: llvm/trunk/lib/MC/TargetAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/TargetAsmBackend.cpp?rev=136009&view=auto ============================================================================== --- llvm/trunk/lib/MC/TargetAsmBackend.cpp (original) +++ llvm/trunk/lib/MC/TargetAsmBackend.cpp (removed) @@ -1,37 +0,0 @@ -//===-- TargetAsmBackend.cpp - Target Assembly Backend ---------------------==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmBackend.h" -using namespace llvm; - -TargetAsmBackend::TargetAsmBackend() - : HasReliableSymbolDifference(false) -{ -} - -TargetAsmBackend::~TargetAsmBackend() { -} - -const MCFixupKindInfo & -TargetAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { - static const MCFixupKindInfo Builtins[] = { - { "FK_Data_1", 0, 8, 0 }, - { "FK_Data_2", 0, 16, 0 }, - { "FK_Data_4", 0, 32, 0 }, - { "FK_Data_8", 0, 64, 0 }, - { "FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, - { "FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, - { "FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "FK_PCRel_8", 0, 64, MCFixupKindInfo::FKF_IsPCRel } - }; - - assert((size_t)Kind <= sizeof(Builtins) / sizeof(Builtins[0]) && - "Unknown fixup kind"); - return Builtins[Kind]; -} Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -24,7 +24,7 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCWin64EH.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/StringMap.h" @@ -40,7 +40,7 @@ MCSymbol const *CurSymbol; WinCOFFStreamer(MCContext &Context, - TargetAsmBackend &TAB, + MCAsmBackend &MAB, MCCodeEmitter &CE, raw_ostream &OS); @@ -123,10 +123,10 @@ } // end anonymous namespace. WinCOFFStreamer::WinCOFFStreamer(MCContext &Context, - TargetAsmBackend &TAB, + MCAsmBackend &MAB, MCCodeEmitter &CE, raw_ostream &OS) - : MCObjectStreamer(Context, TAB, OS, &CE) + : MCObjectStreamer(Context, MAB, OS, &CE) , CurSymbol(NULL) { } @@ -395,11 +395,11 @@ namespace llvm { MCStreamer *createWinCOFFStreamer(MCContext &Context, - TargetAsmBackend &TAB, + MCAsmBackend &MAB, MCCodeEmitter &CE, raw_ostream &OS, bool RelaxAll) { - WinCOFFStreamer *S = new WinCOFFStreamer(Context, TAB, CE, OS); + WinCOFFStreamer *S = new WinCOFFStreamer(Context, MAB, CE, OS); S->getAssembler().setRelaxAll(RelaxAll); return S; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Jul 25 18:24:55 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionMachO.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/Object/MachOFormat.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -34,10 +34,10 @@ /*HasRelocationAddend*/ false) {} }; -class ARMAsmBackend : public TargetAsmBackend { +class ARMAsmBackend : public MCAsmBackend { bool isThumbMode; // Currently emitting Thumb code. public: - ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {} + ARMAsmBackend(const Target &T) : MCAsmBackend(), isThumbMode(false) {} unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } @@ -80,7 +80,7 @@ }; if (Kind < FirstTargetFixupKind) - return TargetAsmBackend::getFixupKindInfo(Kind); + return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); @@ -491,8 +491,7 @@ } // end anonymous namespace -TargetAsmBackend *llvm::createARMAsmBackend(const Target &T, - const std::string &TT) { +MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { Triple TheTriple(TT); if (TheTriple.isOSDarwin()) { Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Jul 25 18:24:55 2011 @@ -133,7 +133,7 @@ // This is duplicated code. Refactor this. static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, + MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, bool RelaxAll, @@ -141,14 +141,14 @@ Triple TheTriple(TT); if (TheTriple.isOSDarwin()) - return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); + return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll); if (TheTriple.isOSWindows()) { llvm_unreachable("ARM does not support Windows COFF format"); return NULL; } - return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack); + return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack); } static MCInstPrinter *createARMMCInstPrinter(const Target &T, @@ -189,8 +189,8 @@ TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); // Register the asm backend. - TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend); - TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend); + TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend); + TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend); // Register the object streamer. TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer); Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Mon Jul 25 18:24:55 2011 @@ -18,6 +18,7 @@ #include namespace llvm { +class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; @@ -25,7 +26,6 @@ class MCSubtargetInfo; class StringRef; class Target; -class TargetAsmBackend; class raw_ostream; extern Target TheARMTarget, TheThumbTarget; @@ -44,7 +44,7 @@ const MCSubtargetInfo &STI, MCContext &Ctx); -TargetAsmBackend *createARMAsmBackend(const Target&, const std::string &); +MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT); /// createARMMachObjectWriter - Construct an ARM Mach-O object writer. MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Mon Jul 25 18:24:55 2011 @@ -17,7 +17,6 @@ #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCValue.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/Object/MachOFormat.h" #include "llvm/Support/ErrorHandling.h" using namespace llvm; Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Mon Jul 25 18:24:55 2011 @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/MBlazeMCTargetDesc.h" -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCELFObjectWriter.h" @@ -46,10 +46,10 @@ /*HasRelocationAddend*/ true) {} }; -class MBlazeAsmBackend : public TargetAsmBackend { +class MBlazeAsmBackend : public MCAsmBackend { public: MBlazeAsmBackend(const Target &T) - : TargetAsmBackend() { + : MCAsmBackend() { } unsigned getNumFixupKinds() const { @@ -146,8 +146,7 @@ } } // end anonymous namespace -TargetAsmBackend *llvm::createMBlazeAsmBackend(const Target &T, - const std::string &TT) { +MCAsmBackend *llvm::createMBlazeAsmBackend(const Target &T, StringRef TT) { Triple TheTriple(TT); if (TheTriple.isOSDarwin()) Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Mon Jul 25 18:24:55 2011 @@ -72,7 +72,7 @@ } static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, + MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, @@ -89,7 +89,7 @@ return NULL; } - return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); + return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); } static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T, @@ -125,8 +125,8 @@ llvm::createMBlazeMCCodeEmitter); // Register the asm backend - TargetRegistry::RegisterAsmBackend(TheMBlazeTarget, - createMBlazeAsmBackend); + TargetRegistry::RegisterMCAsmBackend(TheMBlazeTarget, + createMBlazeAsmBackend); // Register the object streamer TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget, Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Mon Jul 25 18:24:55 2011 @@ -14,15 +14,13 @@ #ifndef MBLAZEMCTARGETDESC_H #define MBLAZEMCTARGETDESC_H -#include - namespace llvm { +class MCAsmBackend; class MCContext; class MCCodeEmitter; class MCInstrInfo; class MCSubtargetInfo; class Target; -class TargetAsmBackend; class StringRef; class formatted_raw_ostream; @@ -32,7 +30,7 @@ const MCSubtargetInfo &STI, MCContext &Ctx); -TargetAsmBackend *createMBlazeAsmBackend(const Target &, const std::string &); +MCAsmBackend *createMBlazeAsmBackend(const Target &T, StringRef TT); } // End llvm namespace Modified: llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Mon Jul 25 18:24:55 2011 @@ -533,7 +533,7 @@ formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, bool useCFI, MCInstPrinter *IP, - MCCodeEmitter *CE, TargetAsmBackend *TAB, + MCCodeEmitter *CE, MCAsmBackend *MAB, bool ShowInst) { return new PTXMCAsmStreamer(Context, OS, isVerboseAsm, useLoc, IP, CE, ShowInst); Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Mon Jul 25 18:24:55 2011 @@ -25,7 +25,7 @@ bool useCFI, MCInstPrinter *InstPrint, MCCodeEmitter *CE, - TargetAsmBackend *TAB, + MCAsmBackend *MAB, bool ShowInst); } Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Mon Jul 25 18:24:55 2011 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCFixupKinds.h" #include "llvm/MC/MCMachObjectWriter.h" @@ -31,10 +31,10 @@ MCValue Target, uint64_t &FixedValue) {} }; -class PPCAsmBackend : public TargetAsmBackend { +class PPCAsmBackend : public MCAsmBackend { const Target &TheTarget; public: - PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {} + PPCAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {} unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; } @@ -49,7 +49,7 @@ }; if (Kind < FirstTargetFixupKind) - return TargetAsmBackend::getFixupKindInfo(Kind); + return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); @@ -114,8 +114,7 @@ -TargetAsmBackend *llvm::createPPCAsmBackend(const Target &T, - const std::string &TT) { +MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, StringRef TT) { if (Triple(TT).isOSDarwin()) return new DarwinPPCAsmBackend(T); Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Mon Jul 25 18:24:55 2011 @@ -91,13 +91,13 @@ // This is duplicated code. Refactor this. static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, + MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, bool RelaxAll, bool NoExecStack) { if (Triple(TT).isOSDarwin()) - return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); + return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll); return NULL; } @@ -136,8 +136,8 @@ TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); // Register the asm backend. - TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend); - TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend); + TargetRegistry::RegisterMCAsmBackend(ThePPC32Target, createPPCAsmBackend); + TargetRegistry::RegisterMCAsmBackend(ThePPC64Target, createPPCAsmBackend); // Register the object streamer. TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer); Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Mon Jul 25 18:24:55 2011 @@ -14,15 +14,13 @@ #ifndef PPCMCTARGETDESC_H #define PPCMCTARGETDESC_H -#include - namespace llvm { +class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; class MCSubtargetInfo; class Target; -class TargetAsmBackend; class StringRef; extern Target ThePPC32Target; @@ -32,7 +30,7 @@ const MCSubtargetInfo &STI, MCContext &Ctx); -TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &); +MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT); } // End llvm namespace Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Mon Jul 25 18:24:55 2011 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmBackend.h" +#include "llvm/MC/MCAsmBackend.h" #include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86FixupKinds.h" #include "llvm/ADT/Twine.h" @@ -62,10 +62,10 @@ : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {} }; -class X86AsmBackend : public TargetAsmBackend { +class X86AsmBackend : public MCAsmBackend { public: X86AsmBackend(const Target &T) - : TargetAsmBackend() {} + : MCAsmBackend() {} unsigned getNumFixupKinds() const { return X86::NumTargetFixupKinds; @@ -80,7 +80,7 @@ }; if (Kind < FirstTargetFixupKind) - return TargetAsmBackend::getFixupKindInfo(Kind); + return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); @@ -425,8 +425,7 @@ } // end anonymous namespace -TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T, - const std::string &TT) { +MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) { Triple TheTriple(TT); if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) @@ -438,8 +437,7 @@ return new ELFX86_32AsmBackend(T, TheTriple.getOS()); } -TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T, - const std::string &TT) { +MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) { Triple TheTriple(TT); if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Jul 25 18:24:55 2011 @@ -367,7 +367,7 @@ } static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, + MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, @@ -375,12 +375,12 @@ Triple TheTriple(TT); if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) - return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll); + return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll); if (TheTriple.isOSWindows()) - return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll); + return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll); - return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); + return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); } static MCInstPrinter *createX86MCInstPrinter(const Target &T, @@ -424,10 +424,10 @@ createX86MCCodeEmitter); // Register the asm backend. - TargetRegistry::RegisterAsmBackend(TheX86_32Target, - createX86_32AsmBackend); - TargetRegistry::RegisterAsmBackend(TheX86_64Target, - createX86_64AsmBackend); + TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, + createX86_32AsmBackend); + TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, + createX86_64AsmBackend); // Register the object streamer. TargetRegistry::RegisterObjectStreamer(TheX86_32Target, Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Mon Jul 25 18:24:55 2011 @@ -18,6 +18,7 @@ #include namespace llvm { +class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; @@ -25,7 +26,6 @@ class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetAsmBackend; class StringRef; class raw_ostream; @@ -74,8 +74,8 @@ const MCSubtargetInfo &STI, MCContext &Ctx); -TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &); -TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &); +MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT); +MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT); /// createX86MachObjectWriter - Construct an X86 Mach-O object writer. MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=136010&r1=136009&r2=136010&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 18:24:55 2011 @@ -14,6 +14,7 @@ #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInstPrinter.h" @@ -24,7 +25,6 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/SubtargetFeature.h" -#include "llvm/MC/TargetAsmBackend.h" #include "llvm/MC/TargetAsmParser.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSelect.h" @@ -368,22 +368,22 @@ MCInstPrinter *IP = TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI); MCCodeEmitter *CE = 0; - TargetAsmBackend *TAB = 0; + MCAsmBackend *MAB = 0; if (ShowEncoding) { CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); - TAB = TheTarget->createAsmBackend(TripleName); + MAB = TheTarget->createMCAsmBackend(TripleName); } Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true, /*useLoc*/ true, - /*useCFI*/ true, IP, CE, TAB, + /*useCFI*/ true, IP, CE, MAB, ShowInst)); } else if (FileType == OFT_Null) { Str.reset(createNullStreamer(Ctx)); } else { assert(FileType == OFT_ObjectFile && "Invalid file type!"); MCCodeEmitter *CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); - TargetAsmBackend *TAB = TheTarget->createAsmBackend(TripleName); - Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *TAB, + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(TripleName); + Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *MAB, FOS, CE, RelaxAll, NoExecStack)); } From evan.cheng at apple.com Mon Jul 25 18:28:36 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 25 Jul 2011 23:28:36 -0000 Subject: [llvm-commits] [llvm] r136012 - /llvm/trunk/lib/MC/CMakeLists.txt Message-ID: <20110725232836.726F72A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 18:28:36 2011 New Revision: 136012 URL: http://llvm.org/viewvc/llvm-project?rev=136012&view=rev Log: TargetAsmBackend has been renamed to MCAsmBackend. Modified: llvm/trunk/lib/MC/CMakeLists.txt Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=136012&r1=136011&r2=136012&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Mon Jul 25 18:28:36 2011 @@ -38,7 +38,7 @@ WinCOFFStreamer.cpp WinCOFFObjectWriter.cpp SubtargetFeature.cpp - TargetAsmBackend.cpp + MCAsmBackend.cpp TargetAsmLexer.cpp ) From grosbach at apple.com Mon Jul 25 18:32:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 25 Jul 2011 23:32:14 -0000 Subject: [llvm-commits] [llvm] r136013 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110725233214.B78B42A6C12C@llvm.org> Author: grosbach Date: Mon Jul 25 18:32:14 2011 New Revision: 136013 URL: http://llvm.org/viewvc/llvm-project?rev=136013&view=rev Log: ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136013&r1=136012&r2=136013&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Jul 25 18:32:14 2011 @@ -1643,6 +1643,29 @@ @------------------------------------------------------------------------------ +@ SSAX + at ------------------------------------------------------------------------------ + ssax r2, r3, r4 + ssaxlt r2, r3, r4 + +@ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xb6] + + at ------------------------------------------------------------------------------ +@ SSUB16/SSUB8 + at ------------------------------------------------------------------------------ + ssub16 r1, r0, r6 + ssub16ne r5, r3, r2 + ssub8 r9, r2, r4 + ssub8eq r5, r1, r2 + +@ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6] +@ CHECK: ssub16ne r5, r3, r2 @ encoding: [0x72,0x5f,0x13,0x16] +@ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6] +@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xf2,0x5f,0x11,0x06] + + + at ------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} From chandlerc at gmail.com Mon Jul 25 19:09:11 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 26 Jul 2011 00:09:11 -0000 Subject: [llvm-commits] [llvm] r136024 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110726000911.884FD2A6C12D@llvm.org> Author: chandlerc Date: Mon Jul 25 19:09:11 2011 New Revision: 136024 URL: http://llvm.org/viewvc/llvm-project?rev=136024&view=rev Log: Still more library dependency updates. This reflects the ever decreasing dependence on CodeGen layers and backends from the MC layers. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=136024&r1=136023&r2=136024&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Mon Jul 25 19:09:11 2011 @@ -1,4 +1,4 @@ -set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport) +set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMAsmPrinter LLVMARMInfo LLVMMC LLVMSupport) @@ -35,10 +35,10 @@ set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC) +set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430Desc LLVMMSP430Info LLVMMipsDesc LLVMMipsInfo LLVMPTXDesc LLVMPTXInfo LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreDesc LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackendInfo LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430Desc LLVMMSP430Info LLVMMipsDesc LLVMMipsInfo LLVMPTXDesc LLVMPTXInfo LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreDesc LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) From chandlerc at gmail.com Mon Jul 25 19:09:08 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 26 Jul 2011 00:09:08 -0000 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/TargetInfo/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ lib/Target/MBlaze/MCTargetDesc/ lib/... Message-ID: <20110726000908.AB0912A6C12C@llvm.org> Author: chandlerc Date: Mon Jul 25 19:09:08 2011 New Revision: 136023 URL: http://llvm.org/viewvc/llvm-project?rev=136023&view=rev Log: Clean up a pile of hacks in our CMake build relating to TableGen. The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. Modified: llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/cmake/modules/TableGen.cmake llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt llvm/trunk/lib/Target/ARM/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Alpha/CMakeLists.txt llvm/trunk/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Alpha/TargetInfo/CMakeLists.txt llvm/trunk/lib/Target/Blackfin/CMakeLists.txt llvm/trunk/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/MSP430/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/SystemZ/CMakeLists.txt llvm/trunk/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt llvm/trunk/lib/Target/X86/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/XCore/CMakeLists.txt llvm/trunk/lib/Target/XCore/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Mon Jul 25 19:09:08 2011 @@ -2,7 +2,6 @@ include(LLVM-Config) macro(add_llvm_library name) - create_tablegenning_custom_target( ${name} ) llvm_process_sources( ALL_FILES ${ARGN} ) add_library( ${name} ${ALL_FILES} ) set_property( GLOBAL APPEND PROPERTY LLVM_LIBS ${name} ) @@ -33,7 +32,6 @@ add_dependencies(${name} ${CURRENT_LLVM_TARGET}) endif() set_target_properties(${name} PROPERTIES FOLDER "Libraries") - add_tablegenning_dependency( ${name} ) endmacro(add_llvm_library name) @@ -77,7 +75,6 @@ macro(add_llvm_executable name) - create_tablegenning_custom_target( ${name} ) llvm_process_sources( ALL_FILES ${ARGN} ) if( EXCLUDE_FROM_ALL ) add_executable(${name} EXCLUDE_FROM_ALL ${ALL_FILES}) @@ -91,7 +88,6 @@ add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) link_system_libs( ${name} ) - add_tablegenning_dependency( ${name} ) endmacro(add_llvm_executable name) Modified: llvm/trunk/cmake/modules/TableGen.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/TableGen.cmake?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/cmake/modules/TableGen.cmake (original) +++ llvm/trunk/cmake/modules/TableGen.cmake Mon Jul 25 19:09:08 2011 @@ -45,23 +45,11 @@ PROPERTIES GENERATED 1) endmacro(tablegen) - -function(create_tablegenning_custom_target target) - # Creates the global target that runs the file-level dependencies - # for tablegenning. +function(add_public_tablegen_target target) + # Creates a target for publicly exporting tablegen dependencies. if( TABLEGEN_OUTPUT ) - add_custom_target(${target}Table_gen + add_custom_target(${target} DEPENDS ${TABLEGEN_OUTPUT}) - add_dependencies(${target}Table_gen ${LLVM_COMMON_DEPENDS}) + add_dependencies(${target} ${LLVM_COMMON_DEPENDS}) endif( TABLEGEN_OUTPUT ) endfunction() - -function(add_tablegenning_dependency target) - # Makes the tablegenning step created with - # create_tablegenning_custom_target dependent on `target'. - if ( TABLEGEN_OUTPUT ) - add_dependencies(${target} ${target}Table_gen) - set_target_properties(${target}Table_gen PROPERTIES FOLDER "Tablegenning") - endif (TABLEGEN_OUTPUT) -endfunction() - Modified: llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -4,4 +4,4 @@ ARMAsmLexer.cpp ARMAsmParser.cpp ) - +add_dependencies(LLVMARMAsmParser ARMCommonTableGen) Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -13,6 +13,7 @@ tablegen(ARMGenSubtargetInfo.inc -gen-subtarget) tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info) tablegen(ARMGenDecoderTables.inc -gen-arm-decoder) +add_public_tablegen_target(ARMCommonTableGen) add_llvm_target(ARMCodeGen ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -11,4 +11,4 @@ PROPERTY COMPILE_FLAGS "/Od" ) endif() -add_dependencies(LLVMARMDisassembler ARMCodeGenTable_gen) +add_dependencies(LLVMARMDisassembler ARMCommonTableGen) Modified: llvm/trunk/lib/Target/ARM/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -3,4 +3,4 @@ add_llvm_library(LLVMARMAsmPrinter ARMInstPrinter.cpp ) -add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen) +add_dependencies(LLVMARMAsmPrinter ARMCommonTableGen) Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ ARMMCExpr.cpp ARMMachObjectWriter.cpp ) +add_dependencies(LLVMARMDesc ARMCommonTableGen) # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(AlphaGenDAGISel.inc -gen-dag-isel) tablegen(AlphaGenCallingConv.inc -gen-callingconv) tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(AlphaCommonTableGen) add_llvm_target(AlphaCodeGen AlphaAsmPrinter.cpp Modified: llvm/trunk/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ AlphaMCTargetDesc.cpp AlphaMCAsmInfo.cpp ) +add_dependencies(LLVMAlphaDesc AlphaCommonTableGen) Modified: llvm/trunk/lib/Target/Alpha/TargetInfo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/TargetInfo/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/TargetInfo/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/TargetInfo/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -3,5 +3,4 @@ add_llvm_library(LLVMAlphaInfo AlphaTargetInfo.cpp ) - -add_dependencies(LLVMAlphaInfo AlphaCodeGenTable_gen) +add_dependencies(LLVMAlphaInfo AlphaCommonTableGen) Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -7,6 +7,7 @@ tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget) tablegen(BlackfinGenCallingConv.inc -gen-callingconv) tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic) +add_public_tablegen_target(BlackfinCommonTableGen) add_llvm_target(BlackfinCodeGen BlackfinAsmPrinter.cpp Modified: llvm/trunk/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ BlackfinMCTargetDesc.cpp BlackfinMCAsmInfo.cpp ) +add_dependencies(LLVMBlackfinDesc BlackfinCommonTableGen) Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -7,6 +7,7 @@ tablegen(SPUGenDAGISel.inc -gen-dag-isel) tablegen(SPUGenSubtargetInfo.inc -gen-subtarget) tablegen(SPUGenCallingConv.inc -gen-callingconv) +add_public_tablegen_target(CellSPUCommonTableGen) add_llvm_target(CellSPUCodeGen SPUAsmPrinter.cpp Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ SPUMCTargetDesc.cpp SPUMCAsmInfo.cpp ) +add_dependencies(LLVMCellSPUDesc CellSPUCommonTableGen) Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -5,4 +5,5 @@ MBlazeAsmLexer.cpp MBlazeAsmParser.cpp ) +add_dependencies(LLVMMBlazeAsmParser MBlazeCommonTableGen) Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -10,6 +10,7 @@ tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget) tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic) tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info) +add_public_tablegen_target(MBlazeCommonTableGen) add_llvm_target(MBlazeCodeGen MBlazeDelaySlotFiller.cpp Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -13,4 +13,4 @@ ) endif() -add_dependencies(LLVMMBlazeDisassembler MBlazeCodeGenTable_gen) +add_dependencies(LLVMMBlazeDisassembler MBlazeCommonTableGen) Modified: llvm/trunk/lib/Target/MBlaze/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -5,4 +5,4 @@ MBlazeInstPrinter.cpp ) -add_dependencies(LLVMMBlazeAsmPrinter MBlazeCodeGenTable_gen) +add_dependencies(LLVMMBlazeAsmPrinter MBlazeCommonTableGen) Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -4,3 +4,4 @@ MBlazeMCCodeEmitter.cpp MBlazeMCTargetDesc.cpp ) +add_dependencies(LLVMMBlazeDesc MBlazeCommonTableGen) Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(MSP430GenDAGISel.inc -gen-dag-isel) tablegen(MSP430GenCallingConv.inc -gen-callingconv) tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(MSP430CommonTableGen) add_llvm_target(MSP430CodeGen MSP430BranchSelector.cpp Modified: llvm/trunk/lib/Target/MSP430/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -3,4 +3,4 @@ add_llvm_library(LLVMMSP430AsmPrinter MSP430InstPrinter.cpp ) -add_dependencies(LLVMMSP430AsmPrinter MSP430CodeGenTable_gen) +add_dependencies(LLVMMSP430AsmPrinter MSP430CommonTableGen) Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ MSP430MCTargetDesc.cpp MSP430MCAsmInfo.cpp ) +add_dependencies(LLVMMSP430Desc MSP430CommonTableGen) Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(MipsGenDAGISel.inc -gen-dag-isel) tablegen(MipsGenCallingConv.inc -gen-callingconv) tablegen(MipsGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(MipsCommonTableGen) add_llvm_target(MipsCodeGen MipsAsmPrinter.cpp Modified: llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -3,4 +3,4 @@ add_llvm_library(LLVMMipsAsmPrinter MipsInstPrinter.cpp ) -add_dependencies(LLVMMipsAsmPrinter MipsCodeGenTable_gen) +add_dependencies(LLVMMipsAsmPrinter MipsCommonTableGen) Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ MipsMCTargetDesc.cpp MipsMCAsmInfo.cpp ) +add_dependencies(LLVMMipsDesc MipsCommonTableGen) Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(PTXGenInstrInfo.inc -gen-instr-info) tablegen(PTXGenRegisterInfo.inc -gen-register-info) tablegen(PTXGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(PTXCommonTableGen) add_llvm_target(PTXCodeGen PTXAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ PTXMCTargetDesc.cpp PTXMCAsmInfo.cpp ) +add_dependencies(LLVMPTXDesc PTXCommonTableGen) Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -8,6 +8,7 @@ tablegen(PPCGenDAGISel.inc -gen-dag-isel) tablegen(PPCGenCallingConv.inc -gen-callingconv) tablegen(PPCGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(PowerPCCommonTableGen) add_llvm_target(PowerPCCodeGen PPCAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -3,4 +3,4 @@ add_llvm_library(LLVMPowerPCAsmPrinter PPCInstPrinter.cpp ) -add_dependencies(LLVMPowerPCAsmPrinter PowerPCCodeGenTable_gen) +add_dependencies(LLVMPowerPCAsmPrinter PowerPCCommonTableGen) Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -4,3 +4,4 @@ PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp ) +add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen) Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(SparcGenDAGISel.inc -gen-dag-isel) tablegen(SparcGenSubtargetInfo.inc -gen-subtarget) tablegen(SparcGenCallingConv.inc -gen-callingconv) +add_public_tablegen_target(SparcCommonTableGen) add_llvm_target(SparcCodeGen DelaySlotFiller.cpp Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,3 +2,4 @@ SparcMCTargetDesc.cpp SparcMCAsmInfo.cpp ) +add_dependencies(LLVMSparcDesc SparcCommonTableGen) Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(SystemZGenDAGISel.inc -gen-dag-isel) tablegen(SystemZGenCallingConv.inc -gen-callingconv) tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(SystemZCommonTableGen) add_llvm_target(SystemZCodeGen SystemZAsmPrinter.cpp Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,6 +2,7 @@ SystemZMCTargetDesc.cpp SystemZMCAsmInfo.cpp ) +add_dependencies(LLVMSystemZDesc SystemZCommonTableGen) # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) Modified: llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -4,4 +4,4 @@ X86AsmLexer.cpp X86AsmParser.cpp ) -add_dependencies(LLVMX86AsmParser X86CodeGenTable_gen) +add_dependencies(LLVMX86AsmParser X86CommonTableGen) Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -11,6 +11,7 @@ tablegen(X86GenCallingConv.inc -gen-callingconv) tablegen(X86GenSubtargetInfo.inc -gen-subtarget) tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info) +add_public_tablegen_target(X86CommonTableGen) set(sources SSEDomainFix.cpp Modified: llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -11,4 +11,4 @@ PROPERTY COMPILE_FLAGS "/Od" ) endif() -add_dependencies(LLVMX86Disassembler X86CodeGenTable_gen) +add_dependencies(LLVMX86Disassembler X86CommonTableGen) Modified: llvm/trunk/lib/Target/X86/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -5,4 +5,4 @@ X86IntelInstPrinter.cpp X86InstComments.cpp ) -add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen) +add_dependencies(LLVMX86AsmPrinter X86CommonTableGen) Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -5,6 +5,7 @@ X86MCCodeEmitter.cpp X86MachObjectWriter.cpp ) +add_dependencies(LLVMX86Desc X86CommonTableGen) # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -6,6 +6,7 @@ tablegen(XCoreGenDAGISel.inc -gen-dag-isel) tablegen(XCoreGenCallingConv.inc -gen-callingconv) tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget) +add_public_tablegen_target(XCoreCommonTableGen) add_llvm_target(XCoreCodeGen XCoreAsmPrinter.cpp Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:09:08 2011 @@ -2,6 +2,7 @@ XCoreMCTargetDesc.cpp XCoreMCAsmInfo.cpp ) +add_dependencies(LLVMXCoreDesc XCoreCommonTableGen) # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) From evan.cheng at apple.com Mon Jul 25 19:24:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 00:24:13 -0000 Subject: [llvm-commits] [llvm] r136027 - in /llvm/trunk: include/llvm/MC/ include/llvm/MC/MCParser/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Target/ARM/AsmParser/ lib/Target/MBlaze/AsmParser/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/PowerPC/MCTargetDesc/ lib/Target/X86/AsmParser/ lib/Target/X86/InstPrinter/ tools/llvm-mc/ tools/lto/ utils/TableGen/ Message-ID: <20110726002414.C78942A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 19:24:13 2011 New Revision: 136027 URL: http://llvm.org/viewvc/llvm-project?rev=136027&view=rev Log: Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. Added: llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h - copied, changed from r135998, llvm/trunk/include/llvm/MC/TargetAsmLexer.h llvm/trunk/include/llvm/MC/MCTargetAsmParser.h - copied, changed from r135998, llvm/trunk/include/llvm/MC/TargetAsmParser.h llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp - copied, changed from r136011, llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp llvm/trunk/lib/MC/MCTargetAsmLexer.cpp - copied, changed from r136011, llvm/trunk/lib/MC/TargetAsmLexer.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp - copied unchanged from r135983, llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h - copied, changed from r135983, llvm/trunk/lib/Target/PowerPC/PPCPredicates.h Removed: llvm/trunk/include/llvm/MC/TargetAsmLexer.h llvm/trunk/include/llvm/MC/TargetAsmParser.h llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp llvm/trunk/lib/MC/TargetAsmLexer.cpp llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp llvm/trunk/lib/Target/PowerPC/PPCPredicates.h Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/CMakeLists.txt llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Mon Jul 25 19:24:13 2011 @@ -36,7 +36,7 @@ // Real values. Real, - // Register values (stored in IntVal). Only used by TargetAsmLexer. + // Register values (stored in IntVal). Only used by MCTargetAsmLexer. Register, // No-value. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 25 19:24:13 2011 @@ -20,11 +20,11 @@ class MCContext; class MCExpr; class MCStreamer; +class MCTargetAsmParser; class SMLoc; class SourceMgr; class StringRef; class Target; -class TargetAsmParser; class Twine; /// MCAsmParser - Generic assembler parser interface, for use by target specific @@ -37,7 +37,7 @@ MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT void operator=(const MCAsmParser &); // DO NOT IMPLEMENT - TargetAsmParser *TargetParser; + MCTargetAsmParser *TargetParser; unsigned ShowParsedOperands : 1; @@ -60,8 +60,8 @@ /// getStreamer - Return the output streamer for the assembler. virtual MCStreamer &getStreamer() = 0; - TargetAsmParser &getTargetParser() const { return *TargetParser; } - void setTargetParser(TargetAsmParser &P); + MCTargetAsmParser &getTargetParser() const { return *TargetParser; } + void setTargetParser(MCTargetAsmParser &P); bool getShowParsedOperands() const { return ShowParsedOperands; } void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; } Copied: llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h (from r135998, llvm/trunk/include/llvm/MC/TargetAsmLexer.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h?p2=llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h&p1=llvm/trunk/include/llvm/MC/TargetAsmLexer.h&r1=135998&r2=136027&rev=136027&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h Mon Jul 25 19:24:13 2011 @@ -1,4 +1,4 @@ -//===-- llvm/Target/TargetAsmLexer.h - Target Assembly Lexer ----*- C++ -*-===// +//===-- llvm/MC/MCTargetAsmLexer.h - Target Assembly Lexer ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,16 +7,16 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_MC_TARGETASMLEXER_H -#define LLVM_MC_TARGETASMLEXER_H +#ifndef LLVM_MC_MCTARGETASMLEXER_H +#define LLVM_MC_MCTARGETASMLEXER_H #include "llvm/MC/MCParser/MCAsmLexer.h" namespace llvm { class Target; -/// TargetAsmLexer - Generic interface to target specific assembly lexers. -class TargetAsmLexer { +/// MCTargetAsmLexer - Generic interface to target specific assembly lexers. +class MCTargetAsmLexer { /// The current token AsmToken CurTok; @@ -24,10 +24,10 @@ SMLoc ErrLoc; std::string Err; - TargetAsmLexer(const TargetAsmLexer &); // DO NOT IMPLEMENT - void operator=(const TargetAsmLexer &); // DO NOT IMPLEMENT + MCTargetAsmLexer(const MCTargetAsmLexer &); // DO NOT IMPLEMENT + void operator=(const MCTargetAsmLexer &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetAsmLexer(const Target &); + MCTargetAsmLexer(const Target &); virtual AsmToken LexToken() = 0; @@ -41,7 +41,7 @@ MCAsmLexer *Lexer; public: - virtual ~TargetAsmLexer(); + virtual ~MCTargetAsmLexer(); const Target &getTarget() const { return TheTarget; } Copied: llvm/trunk/include/llvm/MC/MCTargetAsmParser.h (from r135998, llvm/trunk/include/llvm/MC/TargetAsmParser.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCTargetAsmParser.h?p2=llvm/trunk/include/llvm/MC/MCTargetAsmParser.h&p1=llvm/trunk/include/llvm/MC/TargetAsmParser.h&r1=135998&r2=136027&rev=136027&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCTargetAsmParser.h Mon Jul 25 19:24:13 2011 @@ -1,4 +1,4 @@ -//===-- llvm/Target/TargetAsmParser.h - Target Assembly Parser --*- C++ -*-===// +//===-- llvm/MC/MCTargetAsmParser.h - Target Assembly Parser ----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -20,18 +20,18 @@ class MCParsedAsmOperand; template class SmallVectorImpl; -/// TargetAsmParser - Generic interface to target specific assembly parsers. -class TargetAsmParser : public MCAsmParserExtension { - TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT - void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT +/// MCTargetAsmParser - Generic interface to target specific assembly parsers. +class MCTargetAsmParser : public MCAsmParserExtension { + MCTargetAsmParser(const MCTargetAsmParser &); // DO NOT IMPLEMENT + void operator=(const MCTargetAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetAsmParser(); + MCTargetAsmParser(); /// AvailableFeatures - The current set of available features. unsigned AvailableFeatures; public: - virtual ~TargetAsmParser(); + virtual ~MCTargetAsmParser(); unsigned getAvailableFeatures() const { return AvailableFeatures; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } Removed: llvm/trunk/include/llvm/MC/TargetAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmLexer.h?rev=136026&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmLexer.h (removed) @@ -1,89 +0,0 @@ -//===-- llvm/Target/TargetAsmLexer.h - Target Assembly Lexer ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_TARGETASMLEXER_H -#define LLVM_MC_TARGETASMLEXER_H - -#include "llvm/MC/MCParser/MCAsmLexer.h" - -namespace llvm { -class Target; - -/// TargetAsmLexer - Generic interface to target specific assembly lexers. -class TargetAsmLexer { - /// The current token - AsmToken CurTok; - - /// The location and description of the current error - SMLoc ErrLoc; - std::string Err; - - TargetAsmLexer(const TargetAsmLexer &); // DO NOT IMPLEMENT - void operator=(const TargetAsmLexer &); // DO NOT IMPLEMENT -protected: // Can only create subclasses. - TargetAsmLexer(const Target &); - - virtual AsmToken LexToken() = 0; - - void SetError(const SMLoc &errLoc, const std::string &err) { - ErrLoc = errLoc; - Err = err; - } - - /// TheTarget - The Target that this machine was created for. - const Target &TheTarget; - MCAsmLexer *Lexer; - -public: - virtual ~TargetAsmLexer(); - - const Target &getTarget() const { return TheTarget; } - - /// InstallLexer - Set the lexer to get tokens from lower-level lexer \arg L. - void InstallLexer(MCAsmLexer &L) { - Lexer = &L; - } - - MCAsmLexer *getLexer() { - return Lexer; - } - - /// Lex - Consume the next token from the input stream and return it. - const AsmToken &Lex() { - return CurTok = LexToken(); - } - - /// getTok - Get the current (last) lexed token. - const AsmToken &getTok() { - return CurTok; - } - - /// getErrLoc - Get the current error location - const SMLoc &getErrLoc() { - return ErrLoc; - } - - /// getErr - Get the current error string - const std::string &getErr() { - return Err; - } - - /// getKind - Get the kind of current token. - AsmToken::TokenKind getKind() const { return CurTok.getKind(); } - - /// is - Check if the current token has kind \arg K. - bool is(AsmToken::TokenKind K) const { return CurTok.is(K); } - - /// isNot - Check if the current token has kind \arg K. - bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); } -}; - -} // End llvm namespace - -#endif Removed: llvm/trunk/include/llvm/MC/TargetAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/TargetAsmParser.h?rev=136026&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/TargetAsmParser.h (removed) @@ -1,85 +0,0 @@ -//===-- llvm/Target/TargetAsmParser.h - Target Assembly Parser --*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_TARGETPARSER_H -#define LLVM_MC_TARGETPARSER_H - -#include "llvm/MC/MCParser/MCAsmParserExtension.h" - -namespace llvm { -class MCStreamer; -class StringRef; -class SMLoc; -class AsmToken; -class MCParsedAsmOperand; -template class SmallVectorImpl; - -/// TargetAsmParser - Generic interface to target specific assembly parsers. -class TargetAsmParser : public MCAsmParserExtension { - TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT - void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT -protected: // Can only create subclasses. - TargetAsmParser(); - - /// AvailableFeatures - The current set of available features. - unsigned AvailableFeatures; - -public: - virtual ~TargetAsmParser(); - - unsigned getAvailableFeatures() const { return AvailableFeatures; } - void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } - - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, - SMLoc &EndLoc) = 0; - - /// ParseInstruction - Parse one assembly instruction. - /// - /// The parser is positioned following the instruction name. The target - /// specific instruction parser should parse the entire instruction and - /// construct the appropriate MCInst, or emit an error. On success, the entire - /// line should be parsed up to and including the end-of-statement token. On - /// failure, the parser is not required to read to the end of the line. - // - /// \param Name - The instruction name. - /// \param NameLoc - The source location of the name. - /// \param Operands [out] - The list of parsed operands, this returns - /// ownership of them to the caller. - /// \return True on failure. - virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, - SmallVectorImpl &Operands) = 0; - - /// ParseDirective - Parse a target specific assembler directive - /// - /// The parser is positioned following the directive name. The target - /// specific directive parser should parse the entire directive doing or - /// recording any target specific work, or return true and do nothing if the - /// directive is not target specific. If the directive is specific for - /// the target, the entire line is parsed up to and including the - /// end-of-statement token and false is returned. - /// - /// \param DirectiveID - the identifier token of the directive. - virtual bool ParseDirective(AsmToken DirectiveID) = 0; - - /// MatchAndEmitInstruction - Recognize a series of operands of a parsed - /// instruction as an actual MCInst and emit it to the specified MCStreamer. - /// This returns false on success and returns true on failure to match. - /// - /// On failure, the target parser is responsible for emitting a diagnostic - /// explaining the match failure. - virtual bool - MatchAndEmitInstruction(SMLoc IDLoc, - SmallVectorImpl &Operands, - MCStreamer &Out) = 0; - -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Mon Jul 25 19:24:13 2011 @@ -28,9 +28,11 @@ class AsmPrinter; class Module; class MCAssembler; + class MCAsmBackend; class MCAsmInfo; class MCAsmParser; class MCCodeEmitter; + class MCCodeGenInfo; class MCContext; class MCDisassembler; class MCInstPrinter; @@ -38,10 +40,8 @@ class MCRegisterInfo; class MCStreamer; class MCSubtargetInfo; - class MCCodeGenInfo; - class MCAsmBackend; - class TargetAsmLexer; - class TargetAsmParser; + class MCTargetAsmLexer; + class MCTargetAsmParser; class TargetMachine; class raw_ostream; class formatted_raw_ostream; @@ -87,11 +87,11 @@ typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT); - typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, - const MCRegisterInfo &MRI, - const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI, - MCAsmParser &P); + typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T, + const MCRegisterInfo &MRI, + const MCAsmInfo &MAI); + typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI, + MCAsmParser &P); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, unsigned SyntaxVariant, @@ -163,13 +163,13 @@ /// MCAsmBackend, if registered. MCAsmBackendCtorTy MCAsmBackendCtorFn; - /// AsmLexerCtorFn - Construction function for this target's TargetAsmLexer, - /// if registered. - AsmLexerCtorTy AsmLexerCtorFn; - - /// AsmParserCtorFn - Construction function for this target's - /// TargetAsmParser, if registered. - AsmParserCtorTy AsmParserCtorFn; + /// MCAsmLexerCtorFn - Construction function for this target's + /// MCTargetAsmLexer, if registered. + MCAsmLexerCtorTy MCAsmLexerCtorFn; + + /// MCAsmParserCtorFn - Construction function for this target's + /// MCTargetAsmParser, if registered. + MCAsmParserCtorTy MCAsmParserCtorFn; /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter, /// if registered. @@ -223,11 +223,11 @@ /// hasMCAsmBackend - Check if this target supports .o generation. bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; } - /// hasAsmLexer - Check if this target supports .s lexing. - bool hasAsmLexer() const { return AsmLexerCtorFn != 0; } + /// hasMCAsmLexer - Check if this target supports .s lexing. + bool hasMCAsmLexer() const { return MCAsmLexerCtorFn != 0; } /// hasAsmParser - Check if this target supports .s parsing. - bool hasAsmParser() const { return AsmParserCtorFn != 0; } + bool hasMCAsmParser() const { return MCAsmParserCtorFn != 0; } /// hasAsmPrinter - Check if this target supports .s printing. bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; } @@ -331,24 +331,24 @@ return MCAsmBackendCtorFn(*this, Triple); } - /// createAsmLexer - Create a target specific assembly lexer. + /// createMCAsmLexer - Create a target specific assembly lexer. /// - TargetAsmLexer *createAsmLexer(const MCRegisterInfo &MRI, - const MCAsmInfo &MAI) const { - if (!AsmLexerCtorFn) + MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI, + const MCAsmInfo &MAI) const { + if (!MCAsmLexerCtorFn) return 0; - return AsmLexerCtorFn(*this, MRI, MAI); + return MCAsmLexerCtorFn(*this, MRI, MAI); } - /// createAsmParser - Create a target specific assembly parser. + /// createMCAsmParser - Create a target specific assembly parser. /// /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. - TargetAsmParser *createAsmParser(MCSubtargetInfo &STI, - MCAsmParser &Parser) const { - if (!AsmParserCtorFn) + MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, + MCAsmParser &Parser) const { + if (!MCAsmParserCtorFn) return 0; - return AsmParserCtorFn(STI, Parser); + return MCAsmParserCtorFn(STI, Parser); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -618,7 +618,7 @@ T.MCAsmBackendCtorFn = Fn; } - /// RegisterAsmLexer - Register a TargetAsmLexer implementation for the + /// RegisterMCAsmLexer - Register a MCTargetAsmLexer implementation for the /// given target. /// /// Clients are responsible for ensuring that registration doesn't occur @@ -626,24 +626,24 @@ /// this is done by initializing all targets at program startup. /// /// @param T - The target being registered. - /// @param Fn - A function to construct an AsmLexer for the target. - static void RegisterAsmLexer(Target &T, Target::AsmLexerCtorTy Fn) { - if (!T.AsmLexerCtorFn) - T.AsmLexerCtorFn = Fn; + /// @param Fn - A function to construct an MCAsmLexer for the target. + static void RegisterMCAsmLexer(Target &T, Target::MCAsmLexerCtorTy Fn) { + if (!T.MCAsmLexerCtorFn) + T.MCAsmLexerCtorFn = Fn; } - /// RegisterAsmParser - Register a TargetAsmParser implementation for the - /// given target. + /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for + /// the given target. /// /// Clients are responsible for ensuring that registration doesn't occur /// while another thread is attempting to access the registry. Typically /// this is done by initializing all targets at program startup. /// /// @param T - The target being registered. - /// @param Fn - A function to construct an AsmParser for the target. - static void RegisterAsmParser(Target &T, Target::AsmParserCtorTy Fn) { - if (!T.AsmParserCtorFn) - T.AsmParserCtorFn = Fn; + /// @param Fn - A function to construct an MCTargetAsmParser for the target. + static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) { + if (!T.MCAsmParserCtorFn) + T.MCAsmParserCtorFn = Fn; } /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given @@ -974,44 +974,45 @@ } }; - /// RegisterAsmLexer - Helper template for registering a target specific + /// RegisterMCAsmLexer - Helper template for registering a target specific /// assembly lexer, for use in the target machine initialization /// function. Usage: /// - /// extern "C" void LLVMInitializeFooAsmLexer() { + /// extern "C" void LLVMInitializeFooMCAsmLexer() { /// extern Target TheFooTarget; - /// RegisterAsmLexer X(TheFooTarget); + /// RegisterMCAsmLexer X(TheFooTarget); /// } - template - struct RegisterAsmLexer { - RegisterAsmLexer(Target &T) { - TargetRegistry::RegisterAsmLexer(T, &Allocator); + template + struct RegisterMCAsmLexer { + RegisterMCAsmLexer(Target &T) { + TargetRegistry::RegisterMCAsmLexer(T, &Allocator); } private: - static TargetAsmLexer *Allocator(const Target &T, const MCRegisterInfo &MRI, - const MCAsmInfo &MAI) { - return new AsmLexerImpl(T, MRI, MAI); + static MCTargetAsmLexer *Allocator(const Target &T, + const MCRegisterInfo &MRI, + const MCAsmInfo &MAI) { + return new MCAsmLexerImpl(T, MRI, MAI); } }; - /// RegisterAsmParser - Helper template for registering a target specific + /// RegisterMCAsmParser - Helper template for registering a target specific /// assembly parser, for use in the target machine initialization /// function. Usage: /// - /// extern "C" void LLVMInitializeFooAsmParser() { + /// extern "C" void LLVMInitializeFooMCAsmParser() { /// extern Target TheFooTarget; - /// RegisterAsmParser X(TheFooTarget); + /// RegisterMCAsmParser X(TheFooTarget); /// } - template - struct RegisterAsmParser { - RegisterAsmParser(Target &T) { - TargetRegistry::RegisterAsmParser(T, &Allocator); + template + struct RegisterMCAsmParser { + RegisterMCAsmParser(Target &T) { + TargetRegistry::RegisterMCAsmParser(T, &Allocator); } private: - static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) { - return new AsmParserImpl(STI, P); + static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) { + return new MCAsmParserImpl(STI, P); } }; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Mon Jul 25 19:24:13 2011 @@ -23,7 +23,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" @@ -121,7 +121,8 @@ STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(), TM.getTargetCPU(), TM.getTargetFeatureString())); - OwningPtr TAP(TM.getTarget().createAsmParser(*STI, *Parser)); + OwningPtr + TAP(TM.getTarget().createMCAsmParser(*STI, *Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Mon Jul 25 19:24:13 2011 @@ -39,7 +39,7 @@ WinCOFFObjectWriter.cpp SubtargetFeature.cpp MCAsmBackend.cpp - TargetAsmLexer.cpp + MCTargetAsmLexer.cpp ) add_subdirectory(MCParser) Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Mon Jul 25 19:24:13 2011 @@ -28,8 +28,8 @@ #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" -#include "llvm/MC/TargetAsmLexer.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmLexer.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/SourceMgr.h" @@ -193,7 +193,7 @@ return; GenericAsmLexer.reset(new AsmLexer(*AsmInfo)); - SpecificAsmLexer.reset(Tgt->createAsmLexer(*MRI, *AsmInfo)); + SpecificAsmLexer.reset(Tgt->createMCAsmLexer(*MRI, *AsmInfo)); SpecificAsmLexer->InstallLexer(*GenericAsmLexer); initMaps(*MRI); @@ -368,8 +368,8 @@ StringRef triple = tripleFromArch(Key.Arch); OwningPtr STI(Tgt->createMCSubtargetInfo(triple, "", "")); - OwningPtr TargetParser(Tgt->createAsmParser(*STI, - *genericParser)); + OwningPtr + TargetParser(Tgt->createMCAsmParser(*STI, *genericParser)); AsmToken OpcodeToken = genericParser->Lex(); AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Mon Jul 25 19:24:13 2011 @@ -41,11 +41,11 @@ class MCRegisterInfo; class MCStreamer; class MCSubtargetInfo; +class MCTargetAsmLexer; +class MCTargetAsmParser; template class SmallVectorImpl; class SourceMgr; class Target; -class TargetAsmLexer; -class TargetAsmParser; struct EDInstInfo; struct EDInst; @@ -159,7 +159,7 @@ /// The target-specific lexer for use in tokenizing strings, in /// target-independent and target-specific portions llvm::OwningPtr GenericAsmLexer; - llvm::OwningPtr SpecificAsmLexer; + llvm::OwningPtr SpecificAsmLexer; /// The guard for the above llvm::sys::Mutex ParserMutex; /// The LLVM number used for the target disassembly syntax variant Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -18,6 +18,7 @@ #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCParser/AsmCond.h" #include "llvm/MC/MCParser/AsmLexer.h" @@ -27,8 +28,7 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCDwarf.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/MemoryBuffer.h" Modified: llvm/trunk/lib/MC/MCParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/CMakeLists.txt?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCParser/CMakeLists.txt Mon Jul 25 19:24:13 2011 @@ -7,5 +7,5 @@ MCAsmLexer.cpp MCAsmParser.cpp MCAsmParserExtension.cpp - TargetAsmParser.cpp + MCTargetAsmParser.cpp ) Modified: llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/COFFAsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Support/COFF.h" using namespace llvm; Modified: llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -10,7 +10,7 @@ #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Debug.h" @@ -23,7 +23,7 @@ MCAsmParser::~MCAsmParser() { } -void MCAsmParser::setTargetParser(TargetAsmParser &P) { +void MCAsmParser::setTargetParser(MCTargetAsmParser &P) { assert(!TargetParser && "Target parser is already initialized!"); TargetParser = &P; TargetParser->Initialize(*this); Copied: llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp (from r136011, llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp?p2=llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp&p1=llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp&r1=136011&r2=136027&rev=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -1,4 +1,4 @@ -//===-- TargetAsmParser.cpp - Target Assembly Parser -----------------------==// +//===-- MCTargetAsmParser.cpp - Target Assembly Parser ---------------------==// // // The LLVM Compiler Infrastructure // @@ -7,13 +7,13 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" using namespace llvm; -TargetAsmParser::TargetAsmParser() +MCTargetAsmParser::MCTargetAsmParser() : AvailableFeatures(0) { } -TargetAsmParser::~TargetAsmParser() { +MCTargetAsmParser::~MCTargetAsmParser() { } Removed: llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp?rev=136026&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/TargetAsmParser.cpp (removed) @@ -1,19 +0,0 @@ -//===-- TargetAsmParser.cpp - Target Assembly Parser -----------------------==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmParser.h" -using namespace llvm; - -TargetAsmParser::TargetAsmParser() - : AvailableFeatures(0) -{ -} - -TargetAsmParser::~TargetAsmParser() { -} Copied: llvm/trunk/lib/MC/MCTargetAsmLexer.cpp (from r136011, llvm/trunk/lib/MC/TargetAsmLexer.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCTargetAsmLexer.cpp?p2=llvm/trunk/lib/MC/MCTargetAsmLexer.cpp&p1=llvm/trunk/lib/MC/TargetAsmLexer.cpp&r1=136011&r2=136027&rev=136027&view=diff ============================================================================== --- llvm/trunk/lib/MC/TargetAsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCTargetAsmLexer.cpp Mon Jul 25 19:24:13 2011 @@ -1,4 +1,4 @@ -//===-- llvm/MC/TargetAsmLexer.cpp - Target Assembly Lexer ----------------===// +//===-- llvm/MC/MCTargetAsmLexer.cpp - Target Assembly Lexer --------------===// // // The LLVM Compiler Infrastructure // @@ -7,8 +7,10 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmLexer.h" +#include "llvm/MC/MCTargetAsmLexer.h" using namespace llvm; -TargetAsmLexer::TargetAsmLexer(const Target &T) : TheTarget(T), Lexer(NULL) {} -TargetAsmLexer::~TargetAsmLexer() {} +MCTargetAsmLexer::MCTargetAsmLexer(const Target &T) + : TheTarget(T), Lexer(NULL) { +} +MCTargetAsmLexer::~MCTargetAsmLexer() {} Removed: llvm/trunk/lib/MC/TargetAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/TargetAsmLexer.cpp?rev=136026&view=auto ============================================================================== --- llvm/trunk/lib/MC/TargetAsmLexer.cpp (original) +++ llvm/trunk/lib/MC/TargetAsmLexer.cpp (removed) @@ -1,14 +0,0 @@ -//===-- llvm/MC/TargetAsmLexer.cpp - Target Assembly Lexer ----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/MC/TargetAsmLexer.h" -using namespace llvm; - -TargetAsmLexer::TargetAsmLexer(const Target &T) : TheTarget(T), Lexer(NULL) {} -TargetAsmLexer::~TargetAsmLexer() {} Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Mon Jul 25 19:24:13 2011 @@ -7,13 +7,13 @@ // //===----------------------------------------------------------------------===// -#include "ARM.h" +#include "MCTargetDesc/ARMBaseInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/TargetAsmLexer.h" +#include "llvm/MC/MCTargetAsmLexer.h" #include "llvm/Target/TargetRegistry.h" @@ -29,7 +29,7 @@ namespace { -class ARMBaseAsmLexer : public TargetAsmLexer { +class ARMBaseAsmLexer : public MCTargetAsmLexer { const MCAsmInfo &AsmInfo; const AsmToken &lexDefinite() { @@ -76,7 +76,7 @@ } public: ARMBaseAsmLexer(const Target &T, const MCAsmInfo &MAI) - : TargetAsmLexer(T), AsmInfo(MAI) { + : MCTargetAsmLexer(T), AsmInfo(MAI) { } }; @@ -138,6 +138,6 @@ } extern "C" void LLVMInitializeARMAsmLexer() { - RegisterAsmLexer X(TheARMTarget); - RegisterAsmLexer Y(TheThumbTarget); + RegisterMCAsmLexer X(TheARMTarget); + RegisterMCAsmLexer Y(TheThumbTarget); } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -7,9 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "ARM.h" -#include "ARMBaseRegisterInfo.h" -#include "ARMSubtarget.h" +#include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMMCExpr.h" #include "llvm/MC/MCParser/MCAsmLexer.h" @@ -20,12 +18,14 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -37,7 +37,7 @@ class ARMOperand; -class ARMAsmParser : public TargetAsmParser { +class ARMAsmParser : public MCTargetAsmParser { MCSubtargetInfo &STI; MCAsmParser &Parser; @@ -141,7 +141,7 @@ public: ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) - : TargetAsmParser(), STI(_STI), Parser(_Parser) { + : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { MCAsmParserExtension::Initialize(_Parser); // Initialize the set of available features. @@ -2665,8 +2665,8 @@ /// Force static initialization. extern "C" void LLVMInitializeARMAsmParser() { - RegisterAsmParser X(TheARMTarget); - RegisterAsmParser Y(TheThumbTarget); + RegisterMCAsmParser X(TheARMTarget); + RegisterMCAsmParser Y(TheThumbTarget); LLVMInitializeARMAsmLexer(); } Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Mon Jul 25 19:24:13 2011 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "MBlaze.h" +#include "MCTargetDesc/MBlazeBaseInfo.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" @@ -17,7 +17,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/TargetAsmLexer.h" +#include "llvm/MC/MCTargetAsmLexer.h" #include "llvm/Target/TargetRegistry.h" @@ -28,7 +28,7 @@ namespace { - class MBlazeBaseAsmLexer : public TargetAsmLexer { + class MBlazeBaseAsmLexer : public MCTargetAsmLexer { const MCAsmInfo &AsmInfo; const AsmToken &lexDefinite() { @@ -75,7 +75,7 @@ } public: MBlazeBaseAsmLexer(const Target &T, const MCAsmInfo &MAI) - : TargetAsmLexer(T), AsmInfo(MAI) { + : MCTargetAsmLexer(T), AsmInfo(MAI) { } }; @@ -118,6 +118,6 @@ } extern "C" void LLVMInitializeMBlazeAsmLexer() { - RegisterAsmLexer X(TheMBlazeTarget); + RegisterMCAsmLexer X(TheMBlazeTarget); } Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -7,17 +7,14 @@ // //===----------------------------------------------------------------------===// -#include "MBlaze.h" -#include "MBlazeSubtarget.h" -#include "MBlazeRegisterInfo.h" -#include "MBlazeISelLowering.h" +#include "MCTargetDesc/MBlazeBaseInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" @@ -30,7 +27,7 @@ namespace { struct MBlazeOperand; -class MBlazeAsmParser : public TargetAsmParser { +class MBlazeAsmParser : public MCTargetAsmParser { MCAsmParser &Parser; MCAsmParser &getParser() const { return Parser; } @@ -64,7 +61,7 @@ public: MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) - : TargetAsmParser(), Parser(_Parser) {} + : MCTargetAsmParser(), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); @@ -558,7 +555,7 @@ /// Force static initialization. extern "C" void LLVMInitializeMBlazeAsmParser() { - RegisterAsmParser X(TheMBlazeTarget); + RegisterMCAsmParser X(TheMBlazeTarget); LLVMInitializeMBlazeAsmLexer(); } Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon Jul 25 19:24:13 2011 @@ -13,7 +13,8 @@ #define DEBUG_TYPE "asm-printer" #include "PPCInstPrinter.h" -#include "PPCPredicates.h" +#include "MCTargetDesc/PPCBaseInfo.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Mon Jul 25 19:24:13 2011 @@ -3,5 +3,6 @@ PPCMCTargetDesc.cpp PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp + PPCPredicates.cpp ) add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen) Copied: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h (from r135983, llvm/trunk/lib/Target/PowerPC/PPCPredicates.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h?p2=llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h&p1=llvm/trunk/lib/Target/PowerPC/PPCPredicates.h&r1=135983&r2=136027&rev=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCPredicates.h (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h Mon Jul 25 19:24:13 2011 @@ -14,8 +14,6 @@ #ifndef LLVM_TARGET_POWERPC_PPCPREDICATES_H #define LLVM_TARGET_POWERPC_PPCPREDICATES_H -#include "PPC.h" - namespace llvm { namespace PPC { /// Predicate - These are "(BI << 5) | BO" for various predicates. Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Jul 25 19:24:13 2011 @@ -18,9 +18,9 @@ #define DEBUG_TYPE "asmprinter" #include "PPC.h" -#include "PPCPredicates.h" #include "PPCTargetMachine.h" #include "PPCSubtarget.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/Analysis/DebugInfo.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Mon Jul 25 19:24:13 2011 @@ -19,7 +19,7 @@ #include "PPC.h" #include "PPCInstrBuilder.h" #include "PPCInstrInfo.h" -#include "PPCPredicates.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/Statistic.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Jul 25 19:24:13 2011 @@ -14,8 +14,8 @@ #define DEBUG_TYPE "ppc-codegen" #include "PPC.h" -#include "PPCPredicates.h" #include "PPCTargetMachine.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 25 19:24:13 2011 @@ -14,8 +14,8 @@ #include "PPCISelLowering.h" #include "PPCMachineFunctionInfo.h" #include "PPCPerfectShuffle.h" -#include "PPCPredicates.h" #include "PPCTargetMachine.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/VectorExtras.h" #include "llvm/CodeGen/CallingConvLower.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Jul 25 19:24:13 2011 @@ -15,9 +15,9 @@ #include "PPC.h" #include "PPCInstrBuilder.h" #include "PPCMachineFunctionInfo.h" -#include "PPCPredicates.h" #include "PPCTargetMachine.h" #include "PPCHazardRecognizers.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" Removed: llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp?rev=136026&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCPredicates.cpp (removed) @@ -1,31 +0,0 @@ -//===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the PowerPC branch predicates. -// -//===----------------------------------------------------------------------===// - -#include "PPCPredicates.h" -#include "llvm/Support/ErrorHandling.h" -#include -using namespace llvm; - -PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { - switch (Opcode) { - default: llvm_unreachable("Unknown PPC branch opcode!"); - case PPC::PRED_EQ: return PPC::PRED_NE; - case PPC::PRED_NE: return PPC::PRED_EQ; - case PPC::PRED_LT: return PPC::PRED_GE; - case PPC::PRED_GE: return PPC::PRED_LT; - case PPC::PRED_GT: return PPC::PRED_LE; - case PPC::PRED_LE: return PPC::PRED_GT; - case PPC::PRED_NU: return PPC::PRED_UN; - case PPC::PRED_UN: return PPC::PRED_NU; - } -} Removed: llvm/trunk/lib/Target/PowerPC/PPCPredicates.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCPredicates.h?rev=136026&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCPredicates.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCPredicates.h (removed) @@ -1,39 +0,0 @@ -//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the PowerPC branch predicates. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_POWERPC_PPCPREDICATES_H -#define LLVM_TARGET_POWERPC_PPCPREDICATES_H - -#include "PPC.h" - -namespace llvm { -namespace PPC { - /// Predicate - These are "(BI << 5) | BO" for various predicates. - enum Predicate { - PRED_ALWAYS = (0 << 5) | 20, - PRED_LT = (0 << 5) | 12, - PRED_LE = (1 << 5) | 4, - PRED_EQ = (2 << 5) | 12, - PRED_GE = (0 << 5) | 4, - PRED_GT = (1 << 5) | 12, - PRED_NE = (2 << 5) | 4, - PRED_UN = (3 << 5) | 12, - PRED_NU = (3 << 5) | 4 - }; - - /// Invert the specified predicate. != -> ==, < -> >=. - Predicate InvertPredicate(Predicate Opcode); -} -} - -#endif Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp Mon Jul 25 19:24:13 2011 @@ -7,20 +7,20 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/X86BaseInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" -#include "llvm/MC/TargetAsmLexer.h" +#include "llvm/MC/MCTargetAsmLexer.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" -#include "X86.h" using namespace llvm; namespace { -class X86AsmLexer : public TargetAsmLexer { +class X86AsmLexer : public MCTargetAsmLexer { const MCAsmInfo &AsmInfo; bool tentativeIsValid; @@ -61,7 +61,7 @@ } public: X86AsmLexer(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI) - : TargetAsmLexer(T), AsmInfo(MAI), tentativeIsValid(false) { + : MCTargetAsmLexer(T), AsmInfo(MAI), tentativeIsValid(false) { } }; @@ -160,6 +160,6 @@ } extern "C" void LLVMInitializeX86AsmLexer() { - RegisterAsmLexer X(TheX86_32Target); - RegisterAsmLexer Y(TheX86_64Target); + RegisterMCAsmLexer X(TheX86_32Target); + RegisterMCAsmLexer Y(TheX86_64Target); } Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Jul 25 19:24:13 2011 @@ -7,9 +7,8 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/TargetAsmParser.h" -#include "X86.h" -#include "X86Subtarget.h" +#include "MCTargetDesc/X86BaseInfo.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" @@ -32,7 +31,7 @@ namespace { struct X86Operand; -class X86ATTAsmParser : public TargetAsmParser { +class X86ATTAsmParser : public MCTargetAsmParser { MCSubtargetInfo &STI; MCAsmParser &Parser; @@ -75,7 +74,7 @@ public: X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser) - : TargetAsmParser(), STI(sti), Parser(parser) { + : MCTargetAsmParser(), STI(sti), Parser(parser) { // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); @@ -1130,8 +1129,8 @@ // Force static initialization. extern "C" void LLVMInitializeX86AsmParser() { - RegisterAsmParser X(TheX86_32Target); - RegisterAsmParser Y(TheX86_64Target); + RegisterMCAsmParser X(TheX86_32Target); + RegisterMCAsmParser Y(TheX86_64Target); LLVMInitializeX86AsmLexer(); } Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Mon Jul 25 19:24:13 2011 @@ -14,9 +14,9 @@ #include "X86InstComments.h" #include "MCTargetDesc/X86MCTargetDesc.h" +#include "Utils/X86ShuffleDecode.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" -#include "../Utils/X86ShuffleDecode.h" using namespace llvm; //===----------------------------------------------------------------------===// Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 19:24:13 2011 @@ -24,8 +24,8 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/MC/SubtargetFeature.h" -#include "llvm/MC/TargetAsmParser.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSelect.h" #include "llvm/ADT/OwningPtr.h" @@ -394,7 +394,7 @@ OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI)); - OwningPtr TAP(TheTarget->createAsmParser(*STI, *Parser)); + OwningPtr TAP(TheTarget->createMCAsmParser(*STI, *Parser)); if (!TAP) { errs() << ProgName << ": error: this target does not support assembly parsing.\n"; Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jul 25 19:24:13 2011 @@ -38,7 +38,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/SubtargetFeature.h" -#include "llvm/MC/TargetAsmParser.h" +#include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" @@ -626,8 +626,8 @@ createMCSubtargetInfo(_target->getTargetTriple(), _target->getTargetCPU(), _target->getTargetFeatureString())); - OwningPtr - TAP(_target->getTarget().createAsmParser(*STI, *Parser.get())); + OwningPtr + TAP(_target->getTarget().createMCAsmParser(*STI, *Parser.get())); Parser->setTargetParser(*TAP); int Res = Parser->Run(false); if (Res) Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=136027&r1=136026&r2=136027&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Jul 25 19:24:13 2011 @@ -2172,7 +2172,7 @@ OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; OS << "#undef GET_ASSEMBLER_HEADER\n"; OS << " // This should be included into the middle of the declaration of\n"; - OS << " // your subclasses implementation of TargetAsmParser.\n"; + OS << " // your subclasses implementation of MCTargetAsmParser.\n"; OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; OS << " enum MatchResultTy {\n"; OS << " Match_ConversionFail,\n"; From chandlerc at gmail.com Mon Jul 25 19:30:33 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 26 Jul 2011 00:30:33 -0000 Subject: [llvm-commits] [llvm] r136030 - /llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Message-ID: <20110726003034.06CF42A6C12C@llvm.org> Author: chandlerc Date: Mon Jul 25 19:30:33 2011 New Revision: 136030 URL: http://llvm.org/viewvc/llvm-project?rev=136030&view=rev Log: Remove a file from CMakeLists.txt that Evan removed in r136027. Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=136030&r1=136029&r2=136030&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jul 25 19:30:33 2011 @@ -21,7 +21,6 @@ PPCFrameLowering.cpp PPCJITInfo.cpp PPCMCInstLower.cpp - PPCPredicates.cpp PPCRegisterInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp From evan.cheng at apple.com Mon Jul 25 19:42:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 00:42:34 -0000 Subject: [llvm-commits] [llvm] r136031 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/CodeGen/LLVMTargetMachine.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp tools/llvm-mc/llvm-mc.cpp Message-ID: <20110726004234.C56712A6C12C@llvm.org> Author: evancheng Date: Mon Jul 25 19:42:34 2011 New Revision: 136031 URL: http://llvm.org/viewvc/llvm-project?rev=136031&view=rev Log: Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer. Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Mon Jul 25 19:42:34 2011 @@ -96,17 +96,17 @@ typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI); - typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const MCInstrInfo &II, - const MCSubtargetInfo &STI, - MCContext &Ctx); - typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T, - const std::string &TT, - MCContext &Ctx, - MCAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack); + typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II, + const MCSubtargetInfo &STI, + MCContext &Ctx); + typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T, + StringRef TT, + MCContext &Ctx, + MCAsmBackend &TAB, + raw_ostream &_OS, + MCCodeEmitter *_Emitter, + bool RelaxAll, + bool NoExecStack); typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx, formatted_raw_ostream &OS, bool isVerboseAsm, @@ -183,13 +183,13 @@ /// MCInstPrinter, if registered. MCInstPrinterCtorTy MCInstPrinterCtorFn; - /// CodeEmitterCtorFn - Construction function for this target's CodeEmitter, - /// if registered. - CodeEmitterCtorTy CodeEmitterCtorFn; - - /// ObjectStreamerCtorFn - Construction function for this target's - /// ObjectStreamer, if registered. - ObjectStreamerCtorTy ObjectStreamerCtorFn; + /// MCCodeEmitterCtorFn - Construction function for this target's + /// CodeEmitter, if registered. + MCCodeEmitterCtorTy MCCodeEmitterCtorFn; + + /// MCObjectStreamerCtorFn - Construction function for this target's + /// MCObjectStreamer, if registered. + MCObjectStreamerCtorTy MCObjectStreamerCtorFn; /// AsmStreamerCtorFn - Construction function for this target's /// AsmStreamer, if registered (default = llvm::createAsmStreamer). @@ -238,11 +238,11 @@ /// hasMCInstPrinter - Check if this target has an instruction printer. bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; } - /// hasCodeEmitter - Check if this target supports instruction encoding. - bool hasCodeEmitter() const { return CodeEmitterCtorFn != 0; } + /// hasMCCodeEmitter - Check if this target supports instruction encoding. + bool hasMCCodeEmitter() const { return MCCodeEmitterCtorFn != 0; } - /// hasObjectStreamer - Check if this target supports streaming to files. - bool hasObjectStreamer() const { return ObjectStreamerCtorFn != 0; } + /// hasMCObjectStreamer - Check if this target supports streaming to files. + bool hasMCObjectStreamer() const { return MCObjectStreamerCtorFn != 0; } /// hasAsmStreamer - Check if this target supports streaming to files. bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; } @@ -373,16 +373,16 @@ } - /// createCodeEmitter - Create a target specific code emitter. - MCCodeEmitter *createCodeEmitter(const MCInstrInfo &II, - const MCSubtargetInfo &STI, - MCContext &Ctx) const { - if (!CodeEmitterCtorFn) + /// createMCCodeEmitter - Create a target specific code emitter. + MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II, + const MCSubtargetInfo &STI, + MCContext &Ctx) const { + if (!MCCodeEmitterCtorFn) return 0; - return CodeEmitterCtorFn(II, STI, Ctx); + return MCCodeEmitterCtorFn(II, STI, Ctx); } - /// createObjectStreamer - Create a target specific MCStreamer. + /// createMCObjectStreamer - Create a target specific MCStreamer. /// /// \arg TT - The target triple. /// \arg Ctx - The target context. @@ -391,16 +391,16 @@ /// \arg _Emitter - The target independent assembler object.Takes ownership. /// \arg RelaxAll - Relax all fixups? /// \arg NoExecStack - Mark file as not needing a executable stack. - MCStreamer *createObjectStreamer(const std::string &TT, MCContext &Ctx, - MCAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack) const { - if (!ObjectStreamerCtorFn) + MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx, + MCAsmBackend &TAB, + raw_ostream &_OS, + MCCodeEmitter *_Emitter, + bool RelaxAll, + bool NoExecStack) const { + if (!MCObjectStreamerCtorFn) return 0; - return ObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, RelaxAll, - NoExecStack); + return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, + RelaxAll, NoExecStack); } /// createAsmStreamer - Create a target specific MCStreamer. @@ -691,7 +691,7 @@ T.MCInstPrinterCtorFn = Fn; } - /// RegisterCodeEmitter - Register a MCCodeEmitter implementation for the + /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the /// given target. /// /// Clients are responsible for ensuring that registration doesn't occur @@ -700,13 +700,14 @@ /// /// @param T - The target being registered. /// @param Fn - A function to construct an MCCodeEmitter for the target. - static void RegisterCodeEmitter(Target &T, Target::CodeEmitterCtorTy Fn) { - if (!T.CodeEmitterCtorFn) - T.CodeEmitterCtorFn = Fn; + static void RegisterMCCodeEmitter(Target &T, + Target::MCCodeEmitterCtorTy Fn) { + if (!T.MCCodeEmitterCtorFn) + T.MCCodeEmitterCtorFn = Fn; } - /// RegisterObjectStreamer - Register a object code MCStreamer implementation - /// for the given target. + /// RegisterMCObjectStreamer - Register a object code MCStreamer + /// implementation for the given target. /// /// Clients are responsible for ensuring that registration doesn't occur /// while another thread is attempting to access the registry. Typically @@ -714,9 +715,10 @@ /// /// @param T - The target being registered. /// @param Fn - A function to construct an MCStreamer for the target. - static void RegisterObjectStreamer(Target &T, Target::ObjectStreamerCtorTy Fn) { - if (!T.ObjectStreamerCtorFn) - T.ObjectStreamerCtorFn = Fn; + static void RegisterMCObjectStreamer(Target &T, + Target::MCObjectStreamerCtorTy Fn) { + if (!T.MCObjectStreamerCtorFn) + T.MCObjectStreamerCtorFn = Fn; } /// RegisterAsmStreamer - Register an assembly MCStreamer implementation @@ -1036,25 +1038,25 @@ } }; - /// RegisterCodeEmitter - Helper template for registering a target specific + /// RegisterMCCodeEmitter - Helper template for registering a target specific /// machine code emitter, for use in the target initialization /// function. Usage: /// - /// extern "C" void LLVMInitializeFooCodeEmitter() { + /// extern "C" void LLVMInitializeFooMCCodeEmitter() { /// extern Target TheFooTarget; - /// RegisterCodeEmitter X(TheFooTarget); + /// RegisterMCCodeEmitter X(TheFooTarget); /// } - template - struct RegisterCodeEmitter { - RegisterCodeEmitter(Target &T) { - TargetRegistry::RegisterCodeEmitter(T, &Allocator); + template + struct RegisterMCCodeEmitter { + RegisterMCCodeEmitter(Target &T) { + TargetRegistry::RegisterMCCodeEmitter(T, &Allocator); } private: static MCCodeEmitter *Allocator(const MCInstrInfo &II, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new CodeEmitterImpl(); + return new MCCodeEmitterImpl(); } }; Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Jul 25 19:42:34 2011 @@ -140,7 +140,7 @@ MCAsmBackend *MAB = 0; if (ShowMCEncoding) { const MCSubtargetInfo &STI = getSubtarget(); - MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, *Context); + MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context); MAB = getTarget().createMCAsmBackend(getTargetTriple()); } @@ -158,16 +158,16 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. const MCSubtargetInfo &STI = getSubtarget(); - MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, - *Context); + MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, + *Context); MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple()); if (MCE == 0 || MAB == 0) return true; - AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), - *Context, *MAB, Out, MCE, - hasMCRelaxAll(), - hasMCNoExecStack())); + AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), + *Context, *MAB, Out, + MCE, hasMCRelaxAll(), + hasMCNoExecStack())); AsmStreamer.get()->InitSections(); break; } @@ -236,16 +236,16 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. const MCSubtargetInfo &STI = getSubtarget(); - MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(),STI, *Ctx); + MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx); MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple()); if (MCE == 0 || MAB == 0) return true; OwningPtr AsmStreamer; - AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx, - *MAB, Out, MCE, - hasMCRelaxAll(), - hasMCNoExecStack())); + AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx, + *MAB, Out, MCE, + hasMCRelaxAll(), + hasMCNoExecStack())); AsmStreamer.get()->InitSections(); // Create the AsmPrinter, which takes ownership of AsmStreamer if successful. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Jul 25 19:42:34 2011 @@ -132,7 +132,7 @@ } // This is duplicated code. Refactor this. -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, +static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, @@ -185,16 +185,16 @@ ARM_MC::createARMMCSubtargetInfo); // Register the MC Code Emitter - TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); // Register the asm backend. TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend); TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend); // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer); - TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter); Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Mon Jul 25 19:42:34 2011 @@ -71,7 +71,7 @@ return X; } -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, +static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, @@ -121,16 +121,16 @@ createMBlazeMCSubtargetInfo); // Register the MC code emitter - TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget, - llvm::createMBlazeMCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(TheMBlazeTarget, + llvm::createMBlazeMCCodeEmitter); // Register the asm backend TargetRegistry::RegisterMCAsmBackend(TheMBlazeTarget, createMBlazeAsmBackend); // Register the object streamer - TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget, - createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheMBlazeTarget, + createMCStreamer); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(TheMBlazeTarget, Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Mon Jul 25 19:42:34 2011 @@ -90,7 +90,7 @@ } // This is duplicated code. Refactor this. -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, +static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, @@ -132,16 +132,16 @@ createPPCMCSubtargetInfo); // Register the MC Code Emitter - TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); // Register the asm backend. TargetRegistry::RegisterMCAsmBackend(ThePPC32Target, createPPCAsmBackend); TargetRegistry::RegisterMCAsmBackend(ThePPC64Target, createPPCAsmBackend); // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer); - TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(ThePPC32Target, createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(ThePPC64Target, createMCStreamer); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter); Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Jul 25 19:42:34 2011 @@ -366,7 +366,7 @@ return X; } -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, +static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, @@ -418,10 +418,10 @@ X86_MC::createX86MCSubtargetInfo); // Register the code emitter. - TargetRegistry::RegisterCodeEmitter(TheX86_32Target, - createX86MCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(TheX86_64Target, - createX86MCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, + createX86MCCodeEmitter); + TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target, + createX86MCCodeEmitter); // Register the asm backend. TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, @@ -430,10 +430,10 @@ createX86_64AsmBackend); // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(TheX86_32Target, - createMCStreamer); - TargetRegistry::RegisterObjectStreamer(TheX86_64Target, - createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target, + createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target, + createMCStreamer); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=136031&r1=136030&r2=136031&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 19:42:34 2011 @@ -370,7 +370,7 @@ MCCodeEmitter *CE = 0; MCAsmBackend *MAB = 0; if (ShowEncoding) { - CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); + CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx); MAB = TheTarget->createMCAsmBackend(TripleName); } Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true, @@ -381,11 +381,11 @@ Str.reset(createNullStreamer(Ctx)); } else { assert(FileType == OFT_ObjectFile && "Invalid file type!"); - MCCodeEmitter *CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx); + MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx); MCAsmBackend *MAB = TheTarget->createMCAsmBackend(TripleName); - Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *MAB, - FOS, CE, RelaxAll, - NoExecStack)); + Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB, + FOS, CE, RelaxAll, + NoExecStack)); } if (EnableLogging) { From stoklund at 2pi.dk Mon Jul 25 19:54:56 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 26 Jul 2011 00:54:56 -0000 Subject: [llvm-commits] [llvm] r136034 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110726005456.B1E462A6C12C@llvm.org> Author: stoklund Date: Mon Jul 25 19:54:56 2011 New Revision: 136034 URL: http://llvm.org/viewvc/llvm-project?rev=136034&view=rev Log: Revert to RA_Assign when a virtreg separates into components. When dead code elimination deletes a PHI value, the virtual register may split into multiple connected components. In that case, revert each component to the RS_Assign stage. The new components are guaranteed to be smaller (the original value numbers are distributed among the components), so this will always be making progress. The components are now allowed to evict other live ranges or be split again. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=136034&r1=136033&r2=136034&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Jul 25 19:54:56 2011 @@ -341,8 +341,10 @@ void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) { // LRE may clone a virtual register because dead code elimination causes it to - // be split into connected components. Ensure that the new register gets the + // be split into connected components. The new components are much smaller + // than the original, so they should get a new chance at being assigned. // same stage as the parent. + ExtraRegInfo[Old].Stage = RS_Assign; ExtraRegInfo.grow(New); ExtraRegInfo[New] = ExtraRegInfo[Old]; } From ofv at wanadoo.es Mon Jul 25 20:17:35 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Tue, 26 Jul 2011 03:17:35 +0200 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/TargetInfo/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ lib/Target/MBlaze/MCTargetDesc/ lib/... References: <20110726000908.AB0912A6C12C@llvm.org> Message-ID: <87y5zlhmc0.fsf@wanadoo.es> Helo Chandler. Chandler Carruth writes: > Author: chandlerc > Date: Mon Jul 25 19:09:08 2011 > New Revision: 136023 > > URL: http://llvm.org/viewvc/llvm-project?rev=136023&view=rev > Log: > Clean up a pile of hacks in our CMake build relating to TableGen. Thanks for working on this. Tablegenning is a messy area (and you didn't entered the clang part :-) > The first problem to fix is to stop creating synthetic *Table_gen > targets next to all of the LLVM libraries. These had no real effect as > CMake specifies that add_custom_command(OUTPUT ...) directives (what the > 'tablegen(...)' stuff expands to) are implicitly added as dependencies > to all the rules in that CMakeLists.txt. At the beginning this wasn't true (either a bug or add_custom_command had not that effect at the time) so the custom targets were necessary. I'm glad they are gone. [snip] > This patch removes these synthetic rules completely, and adds a much > simpler function to declare explicitly that a collection of tablegen'ed > files are referenced by other libraries. From that, we can add explicit > dependencies from the smaller libraries (such as every architectures > Desc library) on this and correctly form a linear sequence. All of the > backends are updated to use it, sometimes replacing the existing attempt > at adding a dependency, sometimes adding a previously missing dependency > edge. I'm not sure I get this. Previous to your change, the LLVM library (LLVMX86CodeGen, for instance) had LLVMX86CodeGen_TableGen as a dependency (plus the tablegen source files) and its sublibraries (LLVMX86AsmPrinter, ...) had LLVMX86CodeGen as a dependency. Somehow this didn't work. So why do we need add_public_tablegen_target at all? The sublibraries, by depending on LLVMX86CodeGen, should not start building until after LLVMX86CodeGen is created, which means that the tablegenning is finished too. The fact that TABLEGEN_OUTPUT keeps its value when the sublibraries are processed may be a problem, but that's is trivially solvable (just unset it at the end of add_llvm_target.) I think that the really nasty problem with tablegenning lies on the dependencies on .td files included by the main file listed in LLVM_TARGET_DEFINITIONS. Specifically, on those .td files living outside CMAKE_CURRENT_SOURCE_DIR. I think that sometimes modifications to those files are not detected, apart from using a brute-force approach on the `tablegen' macro for adding them as dependencies to the custom command. I tried to devise a method for accurately retrieving the dependencies from the main .td file (X86.td, for instance) but all the possibilities were too complex. [snip] > Modified: llvm/trunk/cmake/modules/TableGen.cmake > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/TableGen.cmake?rev=136023&r1=136022&r2=136023&view=diff > ============================================================================== > --- llvm/trunk/cmake/modules/TableGen.cmake (original) > +++ llvm/trunk/cmake/modules/TableGen.cmake Mon Jul 25 19:09:08 2011 > @@ -45,23 +45,11 @@ > PROPERTIES GENERATED 1) > endmacro(tablegen) > > - > -function(create_tablegenning_custom_target target) > - # Creates the global target that runs the file-level dependencies > - # for tablegenning. > +function(add_public_tablegen_target target) > + # Creates a target for publicly exporting tablegen dependencies. > if( TABLEGEN_OUTPUT ) > - add_custom_target(${target}Table_gen > + add_custom_target(${target} > DEPENDS ${TABLEGEN_OUTPUT}) > - add_dependencies(${target}Table_gen ${LLVM_COMMON_DEPENDS}) > + add_dependencies(${target} ${LLVM_COMMON_DEPENDS}) > endif( TABLEGEN_OUTPUT ) > endfunction() > - > -function(add_tablegenning_dependency target) > - # Makes the tablegenning step created with > - # create_tablegenning_custom_target dependent on `target'. > - if ( TABLEGEN_OUTPUT ) > - add_dependencies(${target} ${target}Table_gen) > - set_target_properties(${target}Table_gen PROPERTIES FOLDER "Tablegenning") It would be a good thing if ${target}Table_gen on add_public_tablegen_target is keep in the "Tablegenning" folder, as above. [snip] > Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) > +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Jul 25 19:09:08 2011 > @@ -13,6 +13,7 @@ > tablegen(ARMGenSubtargetInfo.inc -gen-subtarget) > tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info) > tablegen(ARMGenDecoderTables.inc -gen-arm-decoder) > +add_public_tablegen_target(ARMCommonTableGen) > > add_llvm_target(ARMCodeGen > ARMAsmPrinter.cpp > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt?rev=136023&r1=136022&r2=136023&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt Mon Jul 25 19:09:08 2011 > @@ -11,4 +11,4 @@ > PROPERTY COMPILE_FLAGS "/Od" > ) > endif() > -add_dependencies(LLVMARMDisassembler ARMCodeGenTable_gen) > +add_dependencies(LLVMARMDisassembler ARMCommonTableGen) There is a pattern here. add_public_tablegen_target should be called from add_llvm_target and the add_dependencies for the sublibrary should be in add_library, the same way we create the dependency on the LLVM library target: if( CURRENT_LLVM_TARGET ) add_dependencies(${name} ${CURRENT_LLVM_TARGET}) endif() [snip] From wendling at apple.com Mon Jul 25 20:24:17 2011 From: wendling at apple.com (Bill Wendling) Date: Mon, 25 Jul 2011 18:24:17 -0700 Subject: [llvm-commits] [llvm] r136009 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/SelectionDAG/ lib/VMCore/ In-Reply-To: <20110725231639.524322A6C12C@llvm.org> References: <20110725231639.524322A6C12C@llvm.org> Message-ID: On Jul 25, 2011, at 4:16 PM, Eli Friedman wrote: > Modified: llvm/trunk/include/llvm/Instruction.def > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Instruction.def (original) > +++ llvm/trunk/include/llvm/Instruction.def Mon Jul 25 18:16:38 2011 > @@ -133,43 +133,44 @@ > HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs > HANDLE_MEMORY_INST(28, Store , StoreInst ) > HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) > - LAST_MEMORY_INST(29) > +HANDLE_MEMORY_INST(30, Fence , FenceInst ) > + LAST_MEMORY_INST(32) > Hi Eli, Did you mean to number these like this? It's skipping between here and the cast instructions. And the "LAST_MEMORY_INST" macro is wrong. -bw > // Cast operators ... > // NOTE: The order matters here because CastInst::isEliminableCastPair > // NOTE: (see Instructions.cpp) encodes a table based on this ordering. > - FIRST_CAST_INST(30) > -HANDLE_CAST_INST(30, Trunc , TruncInst ) // Truncate integers > -HANDLE_CAST_INST(31, ZExt , ZExtInst ) // Zero extend integers > -HANDLE_CAST_INST(32, SExt , SExtInst ) // Sign extend integers > -HANDLE_CAST_INST(33, FPToUI , FPToUIInst ) // floating point -> UInt > -HANDLE_CAST_INST(34, FPToSI , FPToSIInst ) // floating point -> SInt > -HANDLE_CAST_INST(35, UIToFP , UIToFPInst ) // UInt -> floating point > -HANDLE_CAST_INST(36, SIToFP , SIToFPInst ) // SInt -> floating point > -HANDLE_CAST_INST(37, FPTrunc , FPTruncInst ) // Truncate floating point > -HANDLE_CAST_INST(38, FPExt , FPExtInst ) // Extend floating point > -HANDLE_CAST_INST(39, PtrToInt, PtrToIntInst) // Pointer -> Integer > -HANDLE_CAST_INST(40, IntToPtr, IntToPtrInst) // Integer -> Pointer > -HANDLE_CAST_INST(41, BitCast , BitCastInst ) // Type cast > - LAST_CAST_INST(41) > + FIRST_CAST_INST(33) > +HANDLE_CAST_INST(33, Trunc , TruncInst ) // Truncate integers > +HANDLE_CAST_INST(34, ZExt , ZExtInst ) // Zero extend integers > +HANDLE_CAST_INST(35, SExt , SExtInst ) // Sign extend integers > +HANDLE_CAST_INST(36, FPToUI , FPToUIInst ) // floating point -> UInt > +HANDLE_CAST_INST(37, FPToSI , FPToSIInst ) // floating point -> SInt > +HANDLE_CAST_INST(38, UIToFP , UIToFPInst ) // UInt -> floating point > +HANDLE_CAST_INST(39, SIToFP , SIToFPInst ) // SInt -> floating point > +HANDLE_CAST_INST(40, FPTrunc , FPTruncInst ) // Truncate floating point > +HANDLE_CAST_INST(41, FPExt , FPExtInst ) // Extend floating point > +HANDLE_CAST_INST(42, PtrToInt, PtrToIntInst) // Pointer -> Integer > +HANDLE_CAST_INST(43, IntToPtr, IntToPtrInst) // Integer -> Pointer > +HANDLE_CAST_INST(44, BitCast , BitCastInst ) // Type cast > + LAST_CAST_INST(44) > > // Other operators... > - FIRST_OTHER_INST(42) > -HANDLE_OTHER_INST(42, ICmp , ICmpInst ) // Integer comparison instruction > -HANDLE_OTHER_INST(43, FCmp , FCmpInst ) // Floating point comparison instr. > -HANDLE_OTHER_INST(44, PHI , PHINode ) // PHI node instruction > -HANDLE_OTHER_INST(45, Call , CallInst ) // Call a function > -HANDLE_OTHER_INST(46, Select , SelectInst ) // select instruction > -HANDLE_OTHER_INST(47, UserOp1, Instruction) // May be used internally in a pass > -HANDLE_OTHER_INST(48, UserOp2, Instruction) // Internal to passes only > -HANDLE_OTHER_INST(49, VAArg , VAArgInst ) // vaarg instruction > -HANDLE_OTHER_INST(50, ExtractElement, ExtractElementInst)// extract from vector > -HANDLE_OTHER_INST(51, InsertElement, InsertElementInst) // insert into vector > -HANDLE_OTHER_INST(52, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. > -HANDLE_OTHER_INST(53, ExtractValue, ExtractValueInst)// extract from aggregate > -HANDLE_OTHER_INST(54, InsertValue, InsertValueInst) // insert into aggregate > + FIRST_OTHER_INST(45) > +HANDLE_OTHER_INST(45, ICmp , ICmpInst ) // Integer comparison instruction > +HANDLE_OTHER_INST(46, FCmp , FCmpInst ) // Floating point comparison instr. > +HANDLE_OTHER_INST(47, PHI , PHINode ) // PHI node instruction > +HANDLE_OTHER_INST(48, Call , CallInst ) // Call a function > +HANDLE_OTHER_INST(49, Select , SelectInst ) // select instruction > +HANDLE_OTHER_INST(50, UserOp1, Instruction) // May be used internally in a pass > +HANDLE_OTHER_INST(51, UserOp2, Instruction) // Internal to passes only > +HANDLE_OTHER_INST(52, VAArg , VAArgInst ) // vaarg instruction > +HANDLE_OTHER_INST(53, ExtractElement, ExtractElementInst)// extract from vector > +HANDLE_OTHER_INST(54, InsertElement, InsertElementInst) // insert into vector > +HANDLE_OTHER_INST(55, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. > +HANDLE_OTHER_INST(56, ExtractValue, ExtractValueInst)// extract from aggregate > +HANDLE_OTHER_INST(57, InsertValue, InsertValueInst) // insert into aggregate > > - LAST_OTHER_INST(54) > + LAST_OTHER_INST(57) > > #undef FIRST_TERM_INST > #undef HANDLE_TERM_INST > > Modified: llvm/trunk/include/llvm/Instructions.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Instructions.h (original) > +++ llvm/trunk/include/llvm/Instructions.h Mon Jul 25 18:16:38 2011 > @@ -22,6 +22,7 @@ > #include "llvm/CallingConv.h" > #include "llvm/ADT/ArrayRef.h" > #include "llvm/ADT/SmallVector.h" > +#include "llvm/Support/ErrorHandling.h" > #include > > namespace llvm { > @@ -31,6 +32,22 @@ > class APInt; > class LLVMContext; > > +enum AtomicOrdering { > + NotAtomic = 0, > + Unordered = 1, > + Monotonic = 2, > + // Consume = 3, // Not specified yet. > + Acquire = 4, > + Release = 5, > + AcquireRelease = 6, > + SequentiallyConsistent = 7 > +}; > + > +enum SynchronizationScope { > + SingleThread = 0, > + CrossThread = 1 > +}; > + > //===----------------------------------------------------------------------===// > // AllocaInst Class > //===----------------------------------------------------------------------===// > @@ -269,6 +286,82 @@ > DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value) > > //===----------------------------------------------------------------------===// > +// FenceInst Class > +//===----------------------------------------------------------------------===// > + > +/// FenceInst - an instruction for ordering other memory operations > +/// > +class FenceInst : public Instruction { > + void *operator new(size_t, unsigned); // DO NOT IMPLEMENT > + void Init(AtomicOrdering Ordering, SynchronizationScope SynchScope); > +protected: > + virtual FenceInst *clone_impl() const; > +public: > + // allocate space for exactly zero operands > + void *operator new(size_t s) { > + return User::operator new(s, 0); > + } > + > + // Ordering may only be Acquire, Release, AcquireRelease, or > + // SequentiallyConsistent. > + FenceInst(LLVMContext &C, AtomicOrdering Ordering, > + SynchronizationScope SynchScope = CrossThread, > + Instruction *InsertBefore = 0); > + FenceInst(LLVMContext &C, AtomicOrdering Ordering, > + SynchronizationScope SynchScope, > + BasicBlock *InsertAtEnd); > + > + /// Returns the ordering effect of this fence. > + AtomicOrdering getOrdering() const { > + return AtomicOrdering(getSubclassDataFromInstruction() >> 1); > + } > + > + /// Set the ordering constraint on this fence. May only be Acquire, Release, > + /// AcquireRelease, or SequentiallyConsistent. > + void setOrdering(AtomicOrdering Ordering) { > + switch (Ordering) { > + case Acquire: > + case Release: > + case AcquireRelease: > + case SequentiallyConsistent: > + setInstructionSubclassData((getSubclassDataFromInstruction() & 1) | > + (Ordering << 1)); > + return; > + default: > + llvm_unreachable("FenceInst ordering must be Acquire, Release," > + " AcquireRelease, or SequentiallyConsistent"); > + } > + } > + > + SynchronizationScope getSynchScope() const { > + return SynchronizationScope(getSubclassDataFromInstruction() & 1); > + } > + > + /// Specify whether this fence orders other operations with respect to all > + /// concurrently executing threads, or only with respect to signal handlers > + /// executing in the same thread. > + void setSynchScope(SynchronizationScope xthread) { > + setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) | > + xthread); > + } > + > + // Methods for support type inquiry through isa, cast, and dyn_cast: > + static inline bool classof(const FenceInst *) { return true; } > + static inline bool classof(const Instruction *I) { > + return I->getOpcode() == Instruction::Fence; > + } > + static inline bool classof(const Value *V) { > + return isa(V) && classof(cast(V)); > + } > +private: > + // Shadow Instruction::setInstructionSubclassData with a private forwarding > + // method so that subclasses cannot accidentally use it. > + void setInstructionSubclassData(unsigned short D) { > + Instruction::setInstructionSubclassData(D); > + } > +}; > + > +//===----------------------------------------------------------------------===// > // GetElementPtrInst Class > //===----------------------------------------------------------------------===// > > > Modified: llvm/trunk/include/llvm/Support/IRBuilder.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) > +++ llvm/trunk/include/llvm/Support/IRBuilder.h Mon Jul 25 18:16:38 2011 > @@ -762,6 +762,10 @@ > StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) { > return Insert(new StoreInst(Val, Ptr, isVolatile)); > } > + FenceInst *CreateFence(AtomicOrdering Ordering, > + SynchronizationScope SynchScope = CrossThread) { > + return Insert(new FenceInst(Context, Ordering, SynchScope)); > + } > Value *CreateGEP(Value *Ptr, ArrayRef IdxList, > const Twine &Name = "") { > if (Constant *PC = dyn_cast(Ptr)) { > > Modified: llvm/trunk/include/llvm/Support/InstVisitor.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/InstVisitor.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/InstVisitor.h (original) > +++ llvm/trunk/include/llvm/Support/InstVisitor.h Mon Jul 25 18:16:38 2011 > @@ -169,6 +169,7 @@ > RetTy visitAllocaInst(AllocaInst &I) { DELEGATE(Instruction); } > RetTy visitLoadInst(LoadInst &I) { DELEGATE(Instruction); } > RetTy visitStoreInst(StoreInst &I) { DELEGATE(Instruction); } > + RetTy visitFenceInst(FenceInst &I) { DELEGATE(Instruction); } > RetTy visitGetElementPtrInst(GetElementPtrInst &I){ DELEGATE(Instruction); } > RetTy visitPHINode(PHINode &I) { DELEGATE(Instruction); } > RetTy visitTruncInst(TruncInst &I) { DELEGATE(CastInst); } > > Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) > +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Jul 25 18:16:38 2011 > @@ -506,6 +506,15 @@ > KEYWORD(deplibs); > KEYWORD(datalayout); > KEYWORD(volatile); > + KEYWORD(atomic); > + KEYWORD(unordered); > + KEYWORD(monotonic); > + KEYWORD(acquire); > + KEYWORD(release); > + KEYWORD(acq_rel); > + KEYWORD(seq_cst); > + KEYWORD(singlethread); > + > KEYWORD(nuw); > KEYWORD(nsw); > KEYWORD(exact); > @@ -630,6 +639,7 @@ > INSTKEYWORD(alloca, Alloca); > INSTKEYWORD(load, Load); > INSTKEYWORD(store, Store); > + INSTKEYWORD(fence, Fence); > INSTKEYWORD(getelementptr, GetElementPtr); > > INSTKEYWORD(extractelement, ExtractElement); > > Modified: llvm/trunk/lib/AsmParser/LLParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) > +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Jul 25 18:16:38 2011 > @@ -1145,6 +1145,32 @@ > return false; > } > > +/// ParseScopeAndOrdering > +/// if isAtomic: ::= 'singlethread'? AtomicOrdering > +/// else: ::= > +/// > +/// This sets Scope and Ordering to the parsed values. > +bool LLParser::ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope, > + AtomicOrdering &Ordering) { > + if (!isAtomic) > + return false; > + > + Scope = CrossThread; > + if (EatIfPresent(lltok::kw_singlethread)) > + Scope = SingleThread; > + switch (Lex.getKind()) { > + default: return TokError("Expected ordering on atomic instruction"); > + case lltok::kw_unordered: Ordering = Unordered; break; > + case lltok::kw_monotonic: Ordering = Monotonic; break; > + case lltok::kw_acquire: Ordering = Acquire; break; > + case lltok::kw_release: Ordering = Release; break; > + case lltok::kw_acq_rel: Ordering = AcquireRelease; break; > + case lltok::kw_seq_cst: Ordering = SequentiallyConsistent; break; > + } > + Lex.Lex(); > + return false; > +} > + > /// ParseOptionalStackAlignment > /// ::= /* empty */ > /// ::= 'alignstack' '(' 4 ')' > @@ -2924,6 +2950,7 @@ > case lltok::kw_alloca: return ParseAlloc(Inst, PFS); > case lltok::kw_load: return ParseLoad(Inst, PFS, false); > case lltok::kw_store: return ParseStore(Inst, PFS, false); > + case lltok::kw_fence: return ParseFence(Inst, PFS); > case lltok::kw_volatile: > if (EatIfPresent(lltok::kw_load)) > return ParseLoad(Inst, PFS, true); > @@ -3633,6 +3660,23 @@ > return AteExtraComma ? InstExtraComma : InstNormal; > } > > +/// ParseFence > +/// ::= 'fence' 'singlethread'? AtomicOrdering > +int LLParser::ParseFence(Instruction *&Inst, PerFunctionState &PFS) { > + AtomicOrdering Ordering = NotAtomic; > + SynchronizationScope Scope = CrossThread; > + if (ParseScopeAndOrdering(true /*Always atomic*/, Scope, Ordering)) > + return true; > + > + if (Ordering == Unordered) > + return TokError("fence cannot be unordered"); > + if (Ordering == Monotonic) > + return TokError("fence cannot be monotonic"); > + > + Inst = new FenceInst(Context, Ordering, Scope); > + return InstNormal; > +} > + > /// ParseGetElementPtr > /// ::= 'getelementptr' 'inbounds'? TypeAndValue (',' TypeAndValue)* > int LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) { > > Modified: llvm/trunk/lib/AsmParser/LLParser.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/AsmParser/LLParser.h (original) > +++ llvm/trunk/lib/AsmParser/LLParser.h Mon Jul 25 18:16:38 2011 > @@ -15,6 +15,7 @@ > #define LLVM_ASMPARSER_LLPARSER_H > > #include "LLLexer.h" > +#include "llvm/Instructions.h" > #include "llvm/Module.h" > #include "llvm/Type.h" > #include "llvm/ADT/DenseMap.h" > @@ -178,6 +179,8 @@ > bool ParseOptionalVisibility(unsigned &Visibility); > bool ParseOptionalCallingConv(CallingConv::ID &CC); > bool ParseOptionalAlignment(unsigned &Alignment); > + bool ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope, > + AtomicOrdering &Ordering); > bool ParseOptionalStackAlignment(unsigned &Alignment); > bool ParseOptionalCommaAlign(unsigned &Alignment, bool &AteExtraComma); > bool ParseIndexList(SmallVectorImpl &Indices,bool &AteExtraComma); > @@ -360,6 +363,7 @@ > int ParseAlloc(Instruction *&I, PerFunctionState &PFS); > int ParseLoad(Instruction *&I, PerFunctionState &PFS, bool isVolatile); > int ParseStore(Instruction *&I, PerFunctionState &PFS, bool isVolatile); > + int ParseFence(Instruction *&I, PerFunctionState &PFS); > int ParseGetElementPtr(Instruction *&I, PerFunctionState &PFS); > int ParseExtractValue(Instruction *&I, PerFunctionState &PFS); > int ParseInsertValue(Instruction *&I, PerFunctionState &PFS); > > Modified: llvm/trunk/lib/AsmParser/LLToken.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/AsmParser/LLToken.h (original) > +++ llvm/trunk/lib/AsmParser/LLToken.h Mon Jul 25 18:16:38 2011 > @@ -53,6 +53,9 @@ > kw_deplibs, > kw_datalayout, > kw_volatile, > + kw_atomic, > + kw_unordered, kw_monotonic, kw_acquire, kw_release, kw_acq_rel, kw_seq_cst, > + kw_singlethread, > kw_nuw, > kw_nsw, > kw_exact, > @@ -121,7 +124,7 @@ > kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind, > kw_unreachable, > > - kw_alloca, kw_load, kw_store, kw_getelementptr, > + kw_alloca, kw_load, kw_store, kw_fence, kw_getelementptr, > > kw_extractelement, kw_insertelement, kw_shufflevector, > kw_extractvalue, kw_insertvalue, kw_blockaddress, > > Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) > +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Jul 25 18:16:38 2011 > @@ -131,6 +131,27 @@ > } > } > > +static AtomicOrdering GetDecodedOrdering(unsigned Val) { > + switch (Val) { > + case bitc::ORDERING_NOTATOMIC: return NotAtomic; > + case bitc::ORDERING_UNORDERED: return Unordered; > + case bitc::ORDERING_MONOTONIC: return Monotonic; > + case bitc::ORDERING_ACQUIRE: return Acquire; > + case bitc::ORDERING_RELEASE: return Release; > + case bitc::ORDERING_ACQREL: return AcquireRelease; > + default: // Map unknown orderings to sequentially-consistent. > + case bitc::ORDERING_SEQCST: return SequentiallyConsistent; > + } > +} > + > +static SynchronizationScope GetDecodedSynchScope(unsigned Val) { > + switch (Val) { > + case bitc::SYNCHSCOPE_SINGLETHREAD: return SingleThread; > + default: // Map unknown scopes to cross-thread. > + case bitc::SYNCHSCOPE_CROSSTHREAD: return CrossThread; > + } > +} > + > namespace llvm { > namespace { > /// @brief A class for maintaining the slot number definition > @@ -2534,6 +2555,18 @@ > InstructionList.push_back(I); > break; > } > + case bitc::FUNC_CODE_INST_FENCE: { // FENCE:[ordering, synchscope] > + if (2 != Record.size()) > + return Error("Invalid FENCE record"); > + AtomicOrdering Ordering = GetDecodedOrdering(Record[0]); > + if (Ordering == NotAtomic || Ordering == Unordered || > + Ordering == Monotonic) > + return Error("Invalid FENCE record"); > + SynchronizationScope SynchScope = GetDecodedSynchScope(Record[1]); > + I = new FenceInst(Context, Ordering, SynchScope); > + InstructionList.push_back(I); > + break; > + } > case bitc::FUNC_CODE_INST_CALL: { > // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...] > if (Record.size() < 3) > > Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) > +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Jul 25 18:16:38 2011 > @@ -101,6 +101,27 @@ > } > } > > +static unsigned GetEncodedOrdering(AtomicOrdering Ordering) { > + switch (Ordering) { > + default: llvm_unreachable("Unknown atomic ordering"); > + case NotAtomic: return bitc::ORDERING_NOTATOMIC; > + case Unordered: return bitc::ORDERING_UNORDERED; > + case Monotonic: return bitc::ORDERING_MONOTONIC; > + case Acquire: return bitc::ORDERING_ACQUIRE; > + case Release: return bitc::ORDERING_RELEASE; > + case AcquireRelease: return bitc::ORDERING_ACQREL; > + case SequentiallyConsistent: return bitc::ORDERING_SEQCST; > + } > +} > + > +static unsigned GetEncodedSynchScope(SynchronizationScope SynchScope) { > + switch (SynchScope) { > + default: llvm_unreachable("Unknown synchronization scope"); > + case SingleThread: return bitc::SYNCHSCOPE_SINGLETHREAD; > + case CrossThread: return bitc::SYNCHSCOPE_CROSSTHREAD; > + } > +} > + > static void WriteStringRecord(unsigned Code, StringRef Str, > unsigned AbbrevToUse, BitstreamWriter &Stream) { > SmallVector Vals; > @@ -1147,6 +1168,11 @@ > Vals.push_back(Log2_32(cast(I).getAlignment())+1); > Vals.push_back(cast(I).isVolatile()); > break; > + case Instruction::Fence: > + Code = bitc::FUNC_CODE_INST_FENCE; > + Vals.push_back(GetEncodedOrdering(cast(I).getOrdering())); > + Vals.push_back(GetEncodedSynchScope(cast(I).getSynchScope())); > + break; > case Instruction::Call: { > const CallInst &CI = cast(I); > PointerType *PTy = cast(CI.getCalledValue()->getType()); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jul 25 18:16:38 2011 > @@ -3211,6 +3211,10 @@ > DAG.setRoot(StoreNode); > } > > +void SelectionDAGBuilder::visitFence(const FenceInst &I) { > + llvm_unreachable("Not implemented yet"); > +} > + > /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC > /// node. > void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Mon Jul 25 18:16:38 2011 > @@ -504,6 +504,7 @@ > void visitAlloca(const AllocaInst &I); > void visitLoad(const LoadInst &I); > void visitStore(const StoreInst &I); > + void visitFence(const FenceInst &I); > void visitPHI(const PHINode &I); > void visitCall(const CallInst &I); > bool visitMemCmpCall(const CallInst &I); > > Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) > +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Jul 25 18:16:38 2011 > @@ -1098,6 +1098,7 @@ > > void writeOperand(const Value *Op, bool PrintType); > void writeParamOperand(const Value *Operand, Attributes Attrs); > + void writeAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope); > > void writeAllMDNodes(); > > @@ -1128,6 +1129,28 @@ > WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule); > } > > +void AssemblyWriter::writeAtomic(AtomicOrdering Ordering, > + SynchronizationScope SynchScope) { > + if (Ordering == NotAtomic) > + return; > + > + switch (SynchScope) { > + default: Out << " "; break; > + case SingleThread: Out << " singlethread"; break; > + case CrossThread: break; > + } > + > + switch (Ordering) { > + default: Out << " "; break; > + case Unordered: Out << " unordered"; break; > + case Monotonic: Out << " monotonic"; break; > + case Acquire: Out << " acquire"; break; > + case Release: Out << " release"; break; > + case AcquireRelease: Out << " acq_rel"; break; > + case SequentiallyConsistent: Out << " seq_cst"; break; > + } > +} > + > void AssemblyWriter::writeParamOperand(const Value *Operand, > Attributes Attrs) { > if (Operand == 0) { > @@ -1883,6 +1906,8 @@ > Out << ", align " << cast(I).getAlignment(); > } else if (isa(I) && cast(I).getAlignment()) { > Out << ", align " << cast(I).getAlignment(); > + } else if (const FenceInst *FI = dyn_cast(&I)) { > + writeAtomic(FI->getOrdering(), FI->getSynchScope()); > } > > // Print Metadata info. > > Modified: llvm/trunk/lib/VMCore/Instruction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Instruction.cpp (original) > +++ llvm/trunk/lib/VMCore/Instruction.cpp Mon Jul 25 18:16:38 2011 > @@ -127,6 +127,7 @@ > case Alloca: return "alloca"; > case Load: return "load"; > case Store: return "store"; > + case Fence: return "fence"; > case GetElementPtr: return "getelementptr"; > > // Convert instructions... > > Modified: llvm/trunk/lib/VMCore/Instructions.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Instructions.cpp (original) > +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jul 25 18:16:38 2011 > @@ -996,6 +996,26 @@ > } > > //===----------------------------------------------------------------------===// > +// FenceInst Implementation > +//===----------------------------------------------------------------------===// > + > +FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering, > + SynchronizationScope SynchScope, > + Instruction *InsertBefore) > + : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertBefore) { > + setOrdering(Ordering); > + setSynchScope(SynchScope); > +} > + > +FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering, > + SynchronizationScope SynchScope, > + BasicBlock *InsertAtEnd) > + : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertAtEnd) { > + setOrdering(Ordering); > + setSynchScope(SynchScope); > +} > + > +//===----------------------------------------------------------------------===// > // GetElementPtrInst Implementation > //===----------------------------------------------------------------------===// > > @@ -3018,6 +3038,10 @@ > isVolatile(), getAlignment()); > } > > +FenceInst *FenceInst::clone_impl() const { > + return new FenceInst(getContext(), getOrdering(), getSynchScope()); > +} > + > TruncInst *TruncInst::clone_impl() const { > return new TruncInst(getOperand(0), getType()); > } > > Modified: llvm/trunk/lib/VMCore/Verifier.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=136009&r1=136008&r2=136009&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Verifier.cpp (original) > +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jul 25 18:16:38 2011 > @@ -278,6 +278,7 @@ > void visitUserOp1(Instruction &I); > void visitUserOp2(Instruction &I) { visitUserOp1(I); } > void visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI); > + void visitFenceInst(FenceInst &FI); > void visitAllocaInst(AllocaInst &AI); > void visitExtractValueInst(ExtractValueInst &EVI); > void visitInsertValueInst(InsertValueInst &IVI); > @@ -1315,6 +1316,15 @@ > visitInstruction(AI); > } > > +void Verifier::visitFenceInst(FenceInst &FI) { > + const AtomicOrdering Ordering = FI.getOrdering(); > + Assert1(Ordering == Acquire || Ordering == Release || > + Ordering == AcquireRelease || Ordering == SequentiallyConsistent, > + "fence instructions may only have " > + " acquire, release, acq_rel, or seq_cst ordering.", &FI); > + visitInstruction(FI); > +} > + > void Verifier::visitExtractValueInst(ExtractValueInst &EVI) { > Assert1(ExtractValueInst::getIndexedType(EVI.getAggregateOperand()->getType(), > EVI.getIndices()) == > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ofv at wanadoo.es Mon Jul 25 21:18:27 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Tue, 26 Jul 2011 04:18:27 +0200 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/Targ In-Reply-To: (Chandler Carruth's message of "Mon, 25 Jul 2011 18:36:20 -0700") References: Message-ID: <87sjpthjik.fsf@wanadoo.es> Chandler Carruth writes: >> I'm not sure I get this. Previous to your change, the LLVM library >> (LLVMX86CodeGen, for instance) had LLVMX86CodeGen_TableGen as a >> dependency (plus the tablegen source files) and its sublibraries >> (LLVMX86AsmPrinter, ...) had LLVMX86CodeGen as a dependency. > > This is source of the confusion. The sublibraries no longer (in many cases) > depend on LLVMX86CodeGen; specifically MCTargetDesc actively avoids such a > dependency. This is tangential. What I'm trying to say is that the sublibrary is not built until the top library finishes building, which means that tablegenning is done. If the sublibrary references symbols defined by the top library (or the tablegenned files) that's a different topic. >> Somehow >> this didn't work. So why do we need add_public_tablegen_target at all? >> The sublibraries, by depending on LLVMX86CodeGen, should not start >> building until after LLVMX86CodeGen is created, which means that the >> tablegenning is finished too. > > See above. The dependency that previously existed no longer does. Thus the > need for a specific one for the only actual sharing between these two: the > tablegen files. This means an optimization for parallel builds, but doesn't make the build any more robust. The problem with explicitly stating the dependency on every sub-library is that the writer must decide if the dependency actually exists or not (and keep the decission up to date as changes are made to the libraries.) And he has a lot of room for making a mistake. A failed dependency on this scenario is, essentially, a heisenbug. Personally, I prefer a global conservative rule. BTW, possibly not related but the build is failing with: Linking CXX executable ../../bin/llvm-mc ../../lib/libLLVMMSP430Desc.a(MSP430MCTargetDesc.cpp.o): In function `createMSP430MCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo const&)': MSP430MCTargetDesc.cpp:(.text+0x18d): undefined reference to `vtable for llvm::MSP430InstPrinter' ../../lib/libLLVMMipsDesc.a(MipsMCTargetDesc.cpp.o): In function `createMipsMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo const&)': MipsMCTargetDesc.cpp:(.text+0x421): undefined reference to `vtable for llvm::MipsInstPrinter' ../../lib/libLLVMPowerPCDesc.a(PPCMCTargetDesc.cpp.o): In function `createPPCMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo const&)': PPCMCTargetDesc.cpp:(.text+0x330): undefined reference to `vtable for llvm::PPCInstPrinter' ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function `createARMMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo const&)': ARMMCTargetDesc.cpp:(.text+0x32d): undefined reference to `vtable for llvm::ARMInstPrinter' ../../lib/libLLVMMBlazeDesc.a(MBlazeMCTargetDesc.cpp.o): In function `createMBlazeMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo const&)': MBlazeMCTargetDesc.cpp:(.text+0x2ad): undefined reference to `vtable for llvm::MBlazeInstPrinter' collect2: ld returned 1 exit status make[2]: *** [bin/llvm-mc] Error 1 make[1]: *** [tools/llvm-mc/CMakeFiles/llvm-mc.dir/all] Error 2 make[1]: *** Waiting for unfinished jobs.... From bruno.cardoso at gmail.com Mon Jul 25 21:39:13 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 02:39:13 -0000 Subject: [llvm-commits] [llvm] r136047 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20110726023913.4485E2A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 21:39:13 2011 New Revision: 136047 URL: http://llvm.org/viewvc/llvm-project?rev=136047&view=rev Log: Cleanup movsldup/movshdup matching. 27 insertions(+), 62 deletions(-) Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136047&r1=136046&r2=136047&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Jul 25 21:39:13 2011 @@ -400,16 +400,6 @@ return X86::isMOVLMask(cast(N)); }]>; -def movshdup : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVSHDUPMask(cast(N)); -}]>; - -def movsldup : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVSLDUPMask(cast(N)); -}]>; - def unpckl : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ return X86::isUNPCKLMask(cast(N)); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136047&r1=136046&r2=136047&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 21:39:13 2011 @@ -3219,19 +3219,19 @@ // SSE3 - Move Instructions //===---------------------------------------------------------------------===// -// Replicate Single FP -multiclass sse3_replicate_sfp op, PatFrag rep_frag, string OpcodeStr> { +//===---------------------------------------------------------------------===// +// Replicate Single FP - MOVSHDUP and MOVSLDUP +// +multiclass sse3_replicate_sfp op, SDNode OpNode, string OpcodeStr> { def rr : S3SI; + [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>; def rm : S3SI; + [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>; } -multiclass sse3_replicate_sfp_y op, PatFrag rep_frag, +multiclass sse3_replicate_sfp_y op, SDNode OpNode, string OpcodeStr> { def rr : S3SI; @@ -3241,15 +3241,28 @@ let Predicates = [HasAVX] in { // FIXME: Merge above classes when we have patterns for the ymm version - defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX; - defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX; - defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX; - defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX; + defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup">, VEX; + defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup">, VEX; + defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, X86Movshdup, "vmovshdup">, VEX; + defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, X86Movsldup, "vmovsldup">, VEX; +} +defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup">; +defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup">; + +let Predicates = [HasSSE3] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (MOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (MOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))), + (MOVSLDUPrm addr:$src)>; } -defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">; -defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">; -// Replicate Double FP +//===---------------------------------------------------------------------===// +// Replicate Double FP - MOVDDUP +// multiclass sse3_replicate_dfp { def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), @@ -3306,22 +3319,6 @@ (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; } -// vector_shuffle v1, <1, 1, 3, 3> -let AddedComplexity = 15 in -def : Pat<(v4i32 (movshdup VR128:$src, (undef))), - (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>; -let AddedComplexity = 20 in -def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))), - (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>; - -// vector_shuffle v1, <0, 0, 2, 2> -let AddedComplexity = 15 in - def : Pat<(v4i32 (movsldup VR128:$src, (undef))), - (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>; -let AddedComplexity = 20 in - def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))), - (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>; - //===---------------------------------------------------------------------===// // SSE3 - Arithmetic //===---------------------------------------------------------------------===// @@ -5853,28 +5850,6 @@ def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; -// Shuffle with MOVSHDUP -def : Pat<(v4i32 (X86Movshdup VR128:$src)), - (MOVSHDUPrr VR128:$src)>; -def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))), - (MOVSHDUPrm addr:$src)>; - -def : Pat<(v4f32 (X86Movshdup VR128:$src)), - (MOVSHDUPrr VR128:$src)>; -def : Pat<(X86Movshdup (memopv4f32 addr:$src)), - (MOVSHDUPrm addr:$src)>; - -// Shuffle with MOVSLDUP -def : Pat<(v4i32 (X86Movsldup VR128:$src)), - (MOVSLDUPrr VR128:$src)>; -def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))), - (MOVSLDUPrm addr:$src)>; - -def : Pat<(v4f32 (X86Movsldup VR128:$src)), - (MOVSLDUPrr VR128:$src)>; -def : Pat<(X86Movsldup (memopv4f32 addr:$src)), - (MOVSLDUPrm addr:$src)>; - // Shuffle with PSHUFHW def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), (PSHUFHWri VR128:$src, imm:$imm)>; From bruno.cardoso at gmail.com Mon Jul 25 21:39:23 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 02:39:23 -0000 Subject: [llvm-commits] [llvm] r136048 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110726023923.6C1BB2A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 21:39:23 2011 New Revision: 136048 URL: http://llvm.org/viewvc/llvm-project?rev=136048&view=rev Log: Add 128-bit AVX versions of movshdup/mosldup Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136048&r1=136047&r2=136048&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 21:39:23 2011 @@ -3260,6 +3260,17 @@ (MOVSLDUPrm addr:$src)>; } +let Predicates = [HasAVX] in { + def : Pat<(v4i32 (X86Movshdup VR128:$src)), + (VMOVSHDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), + (VMOVSHDUPrm addr:$src)>; + def : Pat<(v4i32 (X86Movsldup VR128:$src)), + (VMOVSLDUPrr VR128:$src)>; + def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))), + (VMOVSLDUPrm addr:$src)>; +} + //===---------------------------------------------------------------------===// // Replicate Double FP - MOVDDUP // From bruno.cardoso at gmail.com Mon Jul 25 21:39:25 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 02:39:25 -0000 Subject: [llvm-commits] [llvm] r136049 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110726023926.0F3082A6C12D@llvm.org> Author: bruno Date: Mon Jul 25 21:39:25 2011 New Revision: 136049 URL: http://llvm.org/viewvc/llvm-project?rev=136049&view=rev Log: More cleanup, subtarget info isn't used here. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136049&r1=136048&r2=136049&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 21:39:25 2011 @@ -5721,7 +5721,7 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); } -static inline unsigned getUNPCKLOpcode(EVT VT, const X86Subtarget *Subtarget) { +static inline unsigned getUNPCKLOpcode(EVT VT) { switch(VT.getSimpleVT().SimpleTy) { case MVT::v4i32: return X86ISD::PUNPCKLDQ; case MVT::v2i64: return X86ISD::PUNPCKLQDQ; @@ -5870,7 +5870,7 @@ // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and // unpckh_undef). Only use pshufd if speed is more important than size. if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), dl, VT, V1, V1, DAG); + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); @@ -5990,8 +5990,7 @@ } if (X86::isUNPCKLMask(SVOp)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), - dl, VT, V1, V2, DAG); + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); if (X86::isUNPCKHMask(SVOp)) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); @@ -6018,8 +6017,7 @@ ShuffleVectorSDNode *NewSVOp = cast(NewOp); if (X86::isUNPCKLMask(NewSVOp)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), - dl, VT, V2, V1, DAG); + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); if (X86::isUNPCKHMask(NewSVOp)) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); @@ -6069,8 +6067,7 @@ } if (X86::isUNPCKL_v_undef_Mask(SVOp)) - return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), - dl, VT, V1, V1, DAG); + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); if (X86::isUNPCKH_v_undef_Mask(SVOp)) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); From bruno.cardoso at gmail.com Mon Jul 25 21:39:29 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 02:39:29 -0000 Subject: [llvm-commits] [llvm] r136050 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <20110726023929.2F0DB2A6C12E@llvm.org> Author: bruno Date: Mon Jul 25 21:39:28 2011 New Revision: 136050 URL: http://llvm.org/viewvc/llvm-project?rev=136050&view=rev Log: More movsldup/movshdup cleanup. Rewrite the mask matching function and add support for 256-bit versions (but no instruction selection yet, coming next). Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136050&r1=136049&r2=136050&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 21:39:28 2011 @@ -3457,51 +3457,58 @@ /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. -bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { - if (N->getValueType(0).getVectorNumElements() != 4) +/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> +bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, + const X86Subtarget *Subtarget) { + if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) return false; - // Expect 1, 1, 3, 3 - for (unsigned i = 0; i < 2; ++i) { - int Elt = N->getMaskElt(i); - if (Elt >= 0 && Elt != 1) - return false; - } + // The second vector must be undef + if (N->getOperand(1).getOpcode() != ISD::UNDEF) + return false; + + EVT VT = N->getValueType(0); + unsigned NumElems = VT.getVectorNumElements(); - bool HasHi = false; - for (unsigned i = 2; i < 4; ++i) { - int Elt = N->getMaskElt(i); - if (Elt >= 0 && Elt != 3) + if ((VT.getSizeInBits() == 128 && NumElems != 4) || + (VT.getSizeInBits() == 256 && NumElems != 8)) + return false; + + // "i+1" is the value the indexed mask element must have + for (unsigned i = 0; i < NumElems; i += 2) + if (!isUndefOrEqual(N->getMaskElt(i), i+1) || + !isUndefOrEqual(N->getMaskElt(i+1), i+1)) return false; - if (Elt == 3) - HasHi = true; - } - // Don't use movshdup if it can be done with a shufps. - // FIXME: verify that matching u, u, 3, 3 is what we want. - return HasHi; + + return true; } /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. -bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { - if (N->getValueType(0).getVectorNumElements() != 4) +/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> +bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, + const X86Subtarget *Subtarget) { + if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) return false; - // Expect 0, 0, 2, 2 - for (unsigned i = 0; i < 2; ++i) - if (N->getMaskElt(i) > 0) - return false; + // The second vector must be undef + if (N->getOperand(1).getOpcode() != ISD::UNDEF) + return false; + + EVT VT = N->getValueType(0); + unsigned NumElems = VT.getVectorNumElements(); - bool HasHi = false; - for (unsigned i = 2; i < 4; ++i) { - int Elt = N->getMaskElt(i); - if (Elt >= 0 && Elt != 2) + if ((VT.getSizeInBits() == 128 && NumElems != 4) || + (VT.getSizeInBits() == 256 && NumElems != 8)) + return false; + + // "i" is the value the indexed mask element must have + for (unsigned i = 0; i < NumElems; i += 2) + if (!isUndefOrEqual(N->getMaskElt(i), i) || + !isUndefOrEqual(N->getMaskElt(i+1), i)) return false; - if (Elt == 2) - HasHi = true; - } - // Don't use movsldup if it can be done with a shufps. - return HasHi; + + return true; } /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand @@ -5942,10 +5949,10 @@ if (X86::isMOVHLPSMask(SVOp)) return getMOVHighToLow(Op, dl, DAG); - if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) + if (X86::isMOVSHDUPMask(SVOp, Subtarget)) return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); - if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) + if (X86::isMOVSLDUPMask(SVOp, Subtarget)) return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); if (X86::isMOVLPMask(SVOp)) Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=136050&r1=136049&r2=136050&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jul 25 21:39:28 2011 @@ -406,11 +406,11 @@ /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. - bool isMOVSHDUPMask(ShuffleVectorSDNode *N); + bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget); /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. - bool isMOVSLDUPMask(ShuffleVectorSDNode *N); + bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget); /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVDDUP. From bruno.cardoso at gmail.com Mon Jul 25 21:39:32 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 02:39:32 -0000 Subject: [llvm-commits] [llvm] r136051 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-256-movdup.ll Message-ID: <20110726023932.D67042A6C12C@llvm.org> Author: bruno Date: Mon Jul 25 21:39:32 2011 New Revision: 136051 URL: http://llvm.org/viewvc/llvm-project?rev=136051&view=rev Log: Add 256-bit isel for movsldup/movshdup Added: llvm/trunk/test/CodeGen/X86/avx-256-movdup.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136051&r1=136050&r2=136051&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 25 21:39:32 2011 @@ -3222,32 +3222,31 @@ //===---------------------------------------------------------------------===// // Replicate Single FP - MOVSHDUP and MOVSLDUP // -multiclass sse3_replicate_sfp op, SDNode OpNode, string OpcodeStr> { -def rr : S3SI op, SDNode OpNode, string OpcodeStr, + ValueType vt, RegisterClass RC, PatFrag mem_frag, + X86MemOperand x86memop> { +def rr : S3SI; -def rm : S3SI; +def rm : S3SI; -} - -multiclass sse3_replicate_sfp_y op, SDNode OpNode, - string OpcodeStr> { -def rr : S3SI; -def rm : S3SI; + [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>; } let Predicates = [HasAVX] in { - // FIXME: Merge above classes when we have patterns for the ymm version - defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup">, VEX; - defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup">, VEX; - defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, X86Movshdup, "vmovshdup">, VEX; - defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, X86Movsldup, "vmovsldup">, VEX; -} -defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup">; -defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup">; + defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v4f32, VR128, memopv4f32, f128mem>, VEX; + defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v4f32, VR128, memopv4f32, f128mem>, VEX; + defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup", + v8f32, VR256, memopv8f32, f256mem>, VEX; + defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup", + v8f32, VR256, memopv8f32, f256mem>, VEX; +} +defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128, + memopv4f32, f128mem>; +defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128, + memopv4f32, f128mem>; let Predicates = [HasSSE3] in { def : Pat<(v4i32 (X86Movshdup VR128:$src)), @@ -3269,6 +3268,14 @@ (VMOVSLDUPrr VR128:$src)>; def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))), (VMOVSLDUPrm addr:$src)>; + def : Pat<(v8i32 (X86Movshdup VR256:$src)), + (VMOVSHDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))), + (VMOVSHDUPYrm addr:$src)>; + def : Pat<(v8i32 (X86Movsldup VR256:$src)), + (VMOVSLDUPYrr VR256:$src)>; + def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))), + (VMOVSLDUPYrm addr:$src)>; } //===---------------------------------------------------------------------===// Added: llvm/trunk/test/CodeGen/X86/avx-256-movdup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-movdup.ll?rev=136051&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256-movdup.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-256-movdup.ll Mon Jul 25 21:39:32 2011 @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vmovsldup +define <8 x float> @movdupA(<8 x float> %src) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src, <8 x float> undef, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK: vmovshdup +define <8 x float> @movdupB(<8 x float> %src) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src, <8 x float> undef, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK: vmovsldup +define <4 x i64> @movdupC(<4 x i64> %src) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x i64> %src to <8 x float> + %shuffle.i = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> + %1 = bitcast <8 x float> %shuffle.i to <4 x i64> + ret <4 x i64> %1 +} + +; CHECK: vmovshdup +define <4 x i64> @movdupD(<4 x i64> %src) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x i64> %src to <8 x float> + %shuffle.i = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> + %1 = bitcast <8 x float> %shuffle.i to <4 x i64> + ret <4 x i64> %1 +} + From ofv at wanadoo.es Mon Jul 25 21:55:57 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Tue, 26 Jul 2011 04:55:57 +0200 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/Targ In-Reply-To: (Chandler Carruth's message of "Mon, 25 Jul 2011 18:40:51 -0700") References: Message-ID: <87oc0hhhs2.fsf@wanadoo.es> Chandler Carruth writes: >> > - set_target_properties(${target}Table_gen PROPERTIES FOLDER >> > "Tablegenning") >> >> It would be a good thing if ${target}Table_gen on >> add_public_tablegen_target is keep in the "Tablegenning" folder, as >> above. >> > > I don't know what this does, but I'll try to look into it... Fixing build > issues is my primary concern. It puts the target on the correspondingly named folder on some IDEs (Visual Studio). Otherwise the project view gets cluttered. Just convenient aesthetics. >> -add_dependencies(LLVMARMDisassembler ARMCodeGenTable_gen) >> > +add_dependencies(LLVMARMDisassembler ARMCommonTableGen) >> >> There is a pattern here. add_public_tablegen_target should be called >> from add_llvm_target and the add_dependencies for the sublibrary should >> be in add_library, the same way we create the dependency on the LLVM >> library target: >> > > No, this is not at all correct. There are only a very very few llvm targets > which have tablegen files associated with them. See my previous message for my comments on this. > Also, fundamentally, this is > an incorrect model of the dependencies. Both the library and what you are > (mistakenly) calling a sublibrary depend on the tablegen files. Therefore > there should be an explicit rule for them both to refer to. For example, we > might delete the add_llvm_library from the target directory entirely, and > keep the tablegen and sublibraries. > > Similarly, many sublibraries don't need the tablegen from the parent target > directory, and we shouldn't assume they all do. > > My patch moves us toward an explict model of the dependencies in the CMake > build. That is the correct direction, and the one we are consistently moving > toward. I even have some hope of getting explicit dependencies in the > Makefile based build. Dependencies are a contract and a specification, not > something tools should deduce on the fly. I don't concur with this. It is very nice to talk about contracts, but the reality is that build (and library) dependencies are transitive and, in addition, you usually can reach a given dependecy through more than one path. Taking time on writing contracts is good if and only if they are enforced. In practice, you can state a set of build dependencies that omits certain edges and lists unnecessary edges and the build will work on some circunstances, and fail on another ones (usually those that you didn't tested.) That usually is hard to debug, moreover if you consider that different tools have different heuristics and parallel builds makes things really nasty. I've discussed this with other LLVM members on the past. My stance is that tools are here for helping us and build reliability is a top requirement. Going to a model that creates more opportunities for breakage due to forgetting to update or mistakengly updating the "contracts" is wrong, imho. See how often people forgets to update the CMakeLists.txt files. Fixing a missing dependecy will not be so easy as adding or removing a file name from a list. I'm not saying that I will oppose or reject such changes. I'm just giving my opinion: explicit dependencies will become outdated and create build failures, requiring more maintenance work, with no added benefit. From chandlerc at google.com Mon Jul 25 22:15:28 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 25 Jul 2011 20:15:28 -0700 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/Targ In-Reply-To: <87sjpthjik.fsf@wanadoo.es> References: <87sjpthjik.fsf@wanadoo.es> Message-ID: On Mon, Jul 25, 2011 at 7:18 PM, ?scar Fuentes wrote: > Chandler Carruth writes: > > >> I'm not sure I get this. Previous to your change, the LLVM library > >> (LLVMX86CodeGen, for instance) had LLVMX86CodeGen_TableGen as a > >> dependency (plus the tablegen source files) and its sublibraries > >> (LLVMX86AsmPrinter, ...) had LLVMX86CodeGen as a dependency. > > > > This is source of the confusion. The sublibraries no longer (in many > cases) > > depend on LLVMX86CodeGen; specifically MCTargetDesc actively avoids such > a > > dependency. > > This is tangential. What I'm trying to say is that the sublibrary is not > built until the top library finishes building, which means that > tablegenning is done. If the sublibrary references symbols defined by > the top library (or the tablegenned files) that's a different topic. > I'm not sure what platform your observe this behavior, but I don't observe it on Linux. I specifically observe the opposing behavior: subdirectories which do not depend on the libraries in the parent directory are started in parallel. This is one of the advantage of CMake; the builds are highly parallel because of this eager descent into subdirectories. >> Somehow > >> this didn't work. So why do we need add_public_tablegen_target at all? > >> The sublibraries, by depending on LLVMX86CodeGen, should not start > >> building until after LLVMX86CodeGen is created, which means that the > >> tablegenning is finished too. > > > > See above. The dependency that previously existed no longer does. Thus > the > > need for a specific one for the only actual sharing between these two: > the > > tablegen files. > > This means an optimization for parallel builds, but doesn't make the > build any more robust. I specifically, repeatedly saw the tablegen actions fail to be performed prior to the build and analysis of the subdirectory, so I do in fact find it makes it more robust... I'm sorry if you can't reproduce this, but I did several times, and confirmed with other CMake users. The problem with explicitly stating the dependency on every sub-library > is that the writer must decide if the dependency actually exists or not > (and keep the decission up to date as changes are made to the > libraries.) And he has a lot of room for making a mistake. A failed > dependency on this scenario is, essentially, a heisenbug. Personally, I > prefer a global conservative rule. > I don't really follow either of these paths of reasoning. First, I do expect authors of code to actively think about and maintain the dependencies of their code. LLVM has actually paid a dear price for not doing this, see Evans heroic work to re-separate the MC and Target layers. Developers are not left without tools here: the build should actually break if they forget to update the dependencies. I would be very interested in tightening this up so that the build *always* breaks when dependencies are mis-specified rather than merely becoming unreliable. BTW, possibly not related but the build is failing with: > This looks like a missing dependency in MSP430Desc. I can look into it. I'd like to point out however that all of our "automatic" management of dependencies didn't help here; we still have failures and still have to debug them by hand. Given that, its hard for me to argue that they are saving us from all of the manual work of maintaining dependencies. > > Linking CXX executable ../../bin/llvm-mc > ../../lib/libLLVMMSP430Desc.a(MSP430MCTargetDesc.cpp.o): In function > `createMSP430MCInstPrinter(llvm::Target const&, unsigned int, > llvm::MCAsmInfo const&)': > MSP430MCTargetDesc.cpp:(.text+0x18d): undefined reference to `vtable for > llvm::MSP430InstPrinter' > ../../lib/libLLVMMipsDesc.a(MipsMCTargetDesc.cpp.o): In function > `createMipsMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo > const&)': > MipsMCTargetDesc.cpp:(.text+0x421): undefined reference to `vtable for > llvm::MipsInstPrinter' > ../../lib/libLLVMPowerPCDesc.a(PPCMCTargetDesc.cpp.o): In function > `createPPCMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo > const&)': > PPCMCTargetDesc.cpp:(.text+0x330): undefined reference to `vtable for > llvm::PPCInstPrinter' > ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function > `createARMMCInstPrinter(llvm::Target const&, unsigned int, llvm::MCAsmInfo > const&)': > ARMMCTargetDesc.cpp:(.text+0x32d): undefined reference to `vtable for > llvm::ARMInstPrinter' > ../../lib/libLLVMMBlazeDesc.a(MBlazeMCTargetDesc.cpp.o): In function > `createMBlazeMCInstPrinter(llvm::Target const&, unsigned int, > llvm::MCAsmInfo const&)': > MBlazeMCTargetDesc.cpp:(.text+0x2ad): undefined reference to `vtable for > llvm::MBlazeInstPrinter' > collect2: ld returned 1 exit status > make[2]: *** [bin/llvm-mc] Error 1 > make[1]: *** [tools/llvm-mc/CMakeFiles/llvm-mc.dir/all] Error 2 > make[1]: *** Waiting for unfinished jobs.... > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/06cdee3e/attachment.html From chandlerc at google.com Mon Jul 25 22:20:38 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 25 Jul 2011 20:20:38 -0700 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/Targ In-Reply-To: <87oc0hhhs2.fsf@wanadoo.es> References: <87oc0hhhs2.fsf@wanadoo.es> Message-ID: Fundamentally, on the higher-level concepts, we may have to just disagree here. I find great value in explicitly specified dependencies (note I'm not talking about specifying every source file, but about specifying the relationship between libraries) as it makes the actual maintenance of the libraries and dependencies easier. I have sensed a growing appreciation and desire for this in LLVM, perhaps due to the latent layering problems that have gone unnoticed because the automatic system made things "just work". On Mon, Jul 25, 2011 at 7:55 PM, ?scar Fuentes wrote: > Taking time on writing contracts is good if and only if they > are enforced. In practice, you can state a set of build dependencies > that omits certain edges and lists unnecessary edges and the build will > work on some circunstances, and fail on another ones (usually those that > you didn't tested.) > I don't disagree with this however, I just take a different approach: lets make the contract *and* enforce it. I have the good (or mis-)fortune of working with a build system that does a very careful job of enforcing and checking dependencies and layering violations. I regularly compare the CMake build with it to try to keep everything as close to accurate as possible. I'm hoping to be able to automate that process some as the layering violations currently present get cleaned up, but all evidence is that *more* visibility and *more* explicitness will be what is required to get there. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110725/1b8d46c0/attachment.html From baldrick at free.fr Tue Jul 26 02:02:11 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 07:02:11 -0000 Subject: [llvm-commits] [dragonegg] r136061 - /dragonegg/trunk/src/Types.cpp Message-ID: <20110726070211.87DBC2A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 02:02:11 2011 New Revision: 136061 URL: http://llvm.org/viewvc/llvm-project?rev=136061&view=rev Log: Nasty hack to try to ressurect the dragonegg builders. This is fallout from the new LLVM type system. Modified: dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=136061&r1=136060&r2=136061&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Tue Jul 26 02:02:11 2011 @@ -408,12 +408,16 @@ if (RecursionStatus == CS_Struct) RecursionStatus = CS_StructPtr; - Ty = ConvertType(TREE_TYPE(type)); + if (RecursionStatus != CS_StructPtr) + Ty = ConvertType(TREE_TYPE(type)); + else + // FIXME: Hack to avoid crashes with the new LLVM type system. + Ty = GetUnitType(Context); RecursionStatus = SavedCS; if (Ty->isVoidTy()) - Ty = Type::getInt8Ty(Context); // void* -> i8* + Ty = GetUnitType(Context); // void* -> byte* return SET_TYPE_LLVM(type, Ty->getPointerTo()); } From isanbard at gmail.com Tue Jul 26 02:58:09 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 26 Jul 2011 07:58:09 -0000 Subject: [llvm-commits] [llvm] r136064 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20110726075809.E5D7A2A6C12D@llvm.org> Author: void Date: Tue Jul 26 02:58:09 2011 New Revision: 136064 URL: http://llvm.org/viewvc/llvm-project?rev=136064&view=rev Log: Describe the reasoning for compact unwind in better terms. Thanks to Nick Kledzik for the description. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=136064&r1=136063&r2=136064&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Tue Jul 26 02:58:09 2011 @@ -1813,12 +1813,14 @@
    -

    Unwinding out of a function is done virually via DWARF encodings. These - encodings exist in two forms: a Common Information Entry (CIE) and a Frame - Description Entry (FDE). These two tables contain the information necessary - for the unwinder to restore the state of the computer to before the function - was called. However, the tables themselves are rather large. LLVM can use a - "compact unwind" encoding to represent the virtual unwinding.

    +

    Throwing an exception requires unwinding out of a function. The + information on how to unwind a given function is traditionally expressed in + DWARF unwind (a.k.a. frame) info. But that format was originally developed + for debuggers to backtrace, and each Frame Description Entry (FDE) requires + ~20-30 bytes per function. There is also the cost of mapping from an address + in a function to the corresponding FDE at runtime. An alternative unwind + encoding is called compact unwind and requires just 4-bytes per + function.

    The compact unwind encoding is a 32-bit value, which is encoded in an architecture-specific way. It specifies which registers to restore and from @@ -1834,7 +1836,7 @@

    For X86, there are three modes for the compact unwind encoding:

    -
      +
      Function with a Frame Pointer (EBP or RBP)

      EBP/RBP-based frame, where EBP/RBP is pushed onto the stack immediately after the return address, @@ -1845,10 +1847,11 @@ more into the PC. All non-volatile registers that need to be restored must have been saved in a small range on the stack that starts EBP-4 to EBP-1020 (RBP-8 - to RBP-1020). The offset (divided by 4) is encoded in bits - 16-23 (mask: 0x00FF0000). The registers saved are encoded in - bits 0-14 (mask: 0x00007FFF) as five 3-bit entries from the - following table:

      + to RBP-1020). The offset (divided by 4 in 32-bit mode and 8 + in 64-bit mode) is encoded in bits 16-23 (mask: 0x00FF0000). + The registers saved are encoded in bits 0-14 + (mask: 0x00007FFF) as five 3-bit entries from the following + table:

      @@ -1895,13 +1898,14 @@ to the ESP/RSP. Then the return is done by popping the stack into the PC. All non-volatile registers that need to be restored must have been saved on the stack immediately after the return address. The stack - size (divided by 4) is encoded in bits 16-23 - (mask: 0x00FF0000). There is a maximum stack size of 1024 - bytes. The number of registers saved is encoded in bits 9-12 - (mask: 0x00001C00). Bits 0-9 (mask: - 0x000003FF) contain which registers were saved and their - order. (See the encodeCompactUnwindRegistersWithoutFrame() - function in lib/Target/X86FrameLowering.cpp for the encoding + size (divided by 4 in 32-bit mode and 8 in 64-bit mode) is encoded in bits + 16-23 (mask: 0x00FF0000). There is a maximum stack size of + 1024 bytes in 32-bit mode and 2048 in 64-bit mode. The number of registers + saved is encoded in bits 9-12 (mask: 0x00001C00). Bits 0-9 + (mask: 0x000003FF) contain which registers were saved and + their order. (See + the encodeCompactUnwindRegistersWithoutFrame() function + in lib/Target/X86FrameLowering.cpp for the encoding algorithm.)

      Frameless with a Large Constant Stack Size (EBP @@ -1912,7 +1916,7 @@ $nnnnnn, %esp" in its prolog. The compact encoding contains the offset to the $nnnnnn value in the function in bits 9-12 (mask: 0x00001C00).

      - + From isanbard at gmail.com Tue Jul 26 03:03:50 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 26 Jul 2011 08:03:50 -0000 Subject: [llvm-commits] [llvm] r136065 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110726080350.12C632A6C12D@llvm.org> Author: void Date: Tue Jul 26 03:03:49 2011 New Revision: 136065 URL: http://llvm.org/viewvc/llvm-project?rev=136065&view=rev Log: The compact unwinding offsets are divided by 8 on 64-bit machines. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=136065&r1=136064&r2=136065&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Jul 26 03:03:49 2011 @@ -490,6 +490,8 @@ unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta); unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); + unsigned StackDivide = (Is64Bit ? 8 : 4); + unsigned InstrOffset = 0; unsigned CFAOffset = 0; unsigned StackAdjust = 0; @@ -536,7 +538,7 @@ // %RSP = SUB64ri8 %RSP, 48 return 0; - StackAdjust = MI.getOperand(2).getImm() / 4; + StackAdjust = MI.getOperand(2).getImm() / StackDivide; SubtractInstrIdx += InstrOffset; ExpectEnd = true; } @@ -544,7 +546,7 @@ // Encode that we are using EBP/RBP as the frame pointer. uint32_t CompactUnwindEncoding = 0; - CFAOffset /= 4; + CFAOffset /= StackDivide; if (HasFP) { if ((CFAOffset & 0xFF) != CFAOffset) // Offset was too big for compact encoding. From nicholas at mxc.ca Tue Jul 26 03:25:05 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 26 Jul 2011 01:25:05 -0700 Subject: [llvm-commits] [llvm] r135471 - /llvm/trunk/test/Transforms/InstSimplify/compare.ll In-Reply-To: <4E2D6938.6080800@free.fr> References: <20110719082257.D4D482A6C12D@llvm.org> <4E2D6938.6080800@free.fr> Message-ID: <4E2E79E1.9030100@mxc.ca> Duncan Sands wrote: > Hi Nick, > >> Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed >> to perform a signed wrap. Don't rely on any particular handling of that case. > > I don't understand what you are saying. "sub nsw" never does a signed wrap (if > it does the program performs undefined behaviour). In the testcase, %A is > positive while %B is negative. Thus %C is positive because there is no signed > wrap. Thus %D is positive or zero and %E is false. If you feed 'sub nsw' an input which sign-wraps, then you've encountered undefined behaviour. That's what I'm claiming always happens; this test *always* puts the sub in a situation where it needs to do a signed wrap. %Y doesn't feed into the sub, so let's look at i16 %X. %A has 16-bits of 0 followed by 16-bits of unknown. %B has the sign bit set, then 15 bits of 0, followed by the same 16-bits of unknown. Visualized in hex with free variables pqrs, that's 0000pqrs - 7000pqrs = 70000000. If I understand the definition of nsw correctly, we aren't allowed to wrap that way. > > Ciao, Duncan. > >> >> Modified: >> llvm/trunk/test/Transforms/InstSimplify/compare.ll >> >> Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=135471&r1=135470&r2=135471&view=diff >> ============================================================================== >> --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original) >> +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Jul 19 03:22:57 2011 >> @@ -283,17 +283,6 @@ >> ret i1 %E >> } >> >> -; CHECK: @srem4 >> -; CHECK-NEXT: ret i1 false >> -define i1 @srem4(i16 %X, i32 %Y) { >> - %A = zext i16 %X to i32 >> - %B = or i32 2147483648, %A >> - %C = sub nsw i32 %A, %B >> - %D = srem i32 %C, %Y >> - %E = icmp slt i32 %D, 0 >> - ret i1 %E >> -} >> - >> define i1 @udiv1(i32 %X) { >> ; CHECK: @udiv1 >> %A = udiv i32 %X, 1000000 >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Tue Jul 26 03:28:15 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 10:28:15 +0200 Subject: [llvm-commits] [llvm] r135471 - /llvm/trunk/test/Transforms/InstSimplify/compare.ll In-Reply-To: <4E2E79E1.9030100@mxc.ca> References: <20110719082257.D4D482A6C12D@llvm.org> <4E2D6938.6080800@free.fr> <4E2E79E1.9030100@mxc.ca> Message-ID: <4E2E7A9F.9060606@free.fr> Hi Nick, > If you feed 'sub nsw' an input which sign-wraps, then you've encountered > undefined behaviour. That's what I'm claiming always happens; this test *always* > puts the sub in a situation where it needs to do a signed wrap. you are right, but I think it would be better to fix the test rather than just removing it. I suggest introducing a new argument i32 %Z and defining B to be %B = or i32 2147483648, %Z. Ciao, Duncan. > > %Y doesn't feed into the sub, so let's look at i16 %X. %A has 16-bits of 0 > followed by 16-bits of unknown. %B has the sign bit set, then 15 bits of 0, > followed by the same 16-bits of unknown. > > Visualized in hex with free variables pqrs, that's 0000pqrs - 7000pqrs = > 70000000. If I understand the definition of nsw correctly, we aren't allowed to > wrap that way. > >> >> Ciao, Duncan. >> >>> >>> Modified: >>> llvm/trunk/test/Transforms/InstSimplify/compare.ll >>> >>> Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll >>> URL: >>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=135471&r1=135470&r2=135471&view=diff >>> >>> ============================================================================== >>> --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original) >>> +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Jul 19 03:22:57 2011 >>> @@ -283,17 +283,6 @@ >>> ret i1 %E >>> } >>> >>> -; CHECK: @srem4 >>> -; CHECK-NEXT: ret i1 false >>> -define i1 @srem4(i16 %X, i32 %Y) { >>> - %A = zext i16 %X to i32 >>> - %B = or i32 2147483648, %A >>> - %C = sub nsw i32 %A, %B >>> - %D = srem i32 %C, %Y >>> - %E = icmp slt i32 %D, 0 >>> - ret i1 %E >>> -} >>> - >>> define i1 @udiv1(i32 %X) { >>> ; CHECK: @udiv1 >>> %A = udiv i32 %X, 1000000 >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From nicholas at mxc.ca Tue Jul 26 03:40:36 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 26 Jul 2011 08:40:36 -0000 Subject: [llvm-commits] [llvm] r136066 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <20110726084036.493F52A6C12C@llvm.org> Author: nicholas Date: Tue Jul 26 03:40:36 2011 New Revision: 136066 URL: http://llvm.org/viewvc/llvm-project?rev=136066&view=rev Log: Don't try to dereference syms[0] on an empty vector. Reported by Todd Jackson and Jeffrey Bosboom! Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=136066&r1=136065&r2=136066&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Tue Jul 26 03:40:36 2011 @@ -360,6 +360,8 @@ bool anySymbolsPreserved = false; for (std::list::iterator I = Modules.begin(), E = Modules.end(); I != E; ++I) { + if (I->syms.empty()) + continue; (*get_symbols)(I->handle, I->syms.size(), &I->syms[0]); for (unsigned i = 0, e = I->syms.size(); i != e; i++) { if (I->syms[i].resolution == LDPR_PREVAILING_DEF) { From joerg at britannica.bec.de Tue Jul 26 04:09:58 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Tue, 26 Jul 2011 11:09:58 +0200 Subject: [llvm-commits] [llvm] r136023 - in /llvm/trunk: cmake/modules/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Alpha/TargetInfo/ lib/Target/Blackfin/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ lib/Target/MBlaze/MCTargetDesc/ lib/... In-Reply-To: <87y5zlhmc0.fsf@wanadoo.es> References: <20110726000908.AB0912A6C12C@llvm.org> <87y5zlhmc0.fsf@wanadoo.es> Message-ID: <20110726090958.GA19535@britannica.bec.de> On Tue, Jul 26, 2011 at 03:17:35AM +0200, ?scar Fuentes wrote: > I think that the really nasty problem with tablegenning lies on the > dependencies on .td files included by the main file listed in > LLVM_TARGET_DEFINITIONS. Specifically, on those .td files living outside > CMAKE_CURRENT_SOURCE_DIR. I think that sometimes modifications to those > files are not detected, apart from using a brute-force approach on the > `tablegen' macro for adding them as dependencies to the custom command. > I tried to devise a method for accurately retrieving the dependencies > from the main .td file (X86.td, for instance) but all the possibilities > were too complex. I don't know how to integrate it into the cmake build system, but tblgen can give you proper dependencies with -d. Joerg From jay.foad at gmail.com Tue Jul 26 04:27:21 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 26 Jul 2011 10:27:21 +0100 Subject: [llvm-commits] [PATCH][RFC] upgrade to googletest 1.6.0 (was Re: [LLVMdev] Build of latest llvm gives warning and error) Message-ID: On 24 July 2011 10:59, Duncan Sands wrote: > Hi Edward, > >> Building of llvm with gcc-4.5.2-1 gives these warnings: >> >> 1) Building FileManagerTest >> >> "llvm[4]: Compiling FileManagerTest.cpp for Debug+Asserts build >> C:/Programming/VersionControl/llvm/tools/clang/unittests/Basic/FileManagerTest.cpp: >> In member function 'virtual >> void::FileManagerTest_NoVirtualDirectoryExistsBeforeAVirtualFileIsAdded_Test::TestBody()': >> C:/Programming/VersionControl/llvm/tools/clang/unittests/Basic/FileManagerTest.cpp:100:3: >> warning: passing NULL to non-pointer argument 3 of 'static >> testing::AssertionResult >> testing::internal::EqHelper::Compare(const char*, const char*, >> const T1&, T2*) [with T1 = int, T2 = const clang::DirectoryEntry]' > > yes, they are annoying aren't they. ?They all come from google's unittest > library. ?I think it is best to fix them upstream at google. We're using googletest 1.5.0. These warnings seem to be fixed in 1.6.0, so here's a patch to upgrade us. Disclaimer: I've only tested this by doing "make check-all" on Linux/x86_64. Incidentally, the upgrade would have been much easier if we weren't carrying local changes to support Haiku OS and Minix. Can these be pushed upstream (or thrown away if no-one is using them)? Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: googletest-1.6.0.diff Type: text/x-patch Size: 294819 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110726/628fd833/attachment-0001.bin From jay.foad at gmail.com Tue Jul 26 04:36:52 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 26 Jul 2011 09:36:52 -0000 Subject: [llvm-commits] [llvm] r136068 - /llvm/trunk/include/llvm/Transforms/IPO.h Message-ID: <20110726093652.A90182A6C12C@llvm.org> Author: foad Date: Tue Jul 26 04:36:52 2011 New Revision: 136068 URL: http://llvm.org/viewvc/llvm-project?rev=136068&view=rev Log: Fix typo in comment. Modified: llvm/trunk/include/llvm/Transforms/IPO.h Modified: llvm/trunk/include/llvm/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=136068&r1=136067&r2=136068&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm/Transforms/IPO.h Tue Jul 26 04:36:52 2011 @@ -81,7 +81,7 @@ //===----------------------------------------------------------------------===// -/// createGVExtractionPass - If deleteFn is true, this pass deletes as +/// createGVExtractionPass - If deleteFn is true, this pass deletes /// the specified global values. Otherwise, it deletes as much of the module as /// possible, except for the global values specified. /// From jay.foad at gmail.com Tue Jul 26 05:16:36 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 26 Jul 2011 11:16:36 +0100 Subject: [llvm-commits] [PATCH][RFC] upgrade to googletest 1.6.0 (was Re: [LLVMdev] Build of latest llvm gives warning and error) In-Reply-To: References: Message-ID: On 24 July 2011 10:59, Duncan Sands wrote: > Hi Edward, > >> Building of llvm with gcc-4.5.2-1 gives these warnings: >> >> 1) Building FileManagerTest >> >> "llvm[4]: Compiling FileManagerTest.cpp for Debug+Asserts build >> C:/Programming/VersionControl/llvm/tools/clang/unittests/Basic/FileManagerTest.cpp: >> In member function 'virtual >> void::FileManagerTest_NoVirtualDirectoryExistsBeforeAVirtualFileIsAdded_Test::TestBody()': >> C:/Programming/VersionControl/llvm/tools/clang/unittests/Basic/FileManagerTest.cpp:100:3: >> warning: passing NULL to non-pointer argument 3 of 'static >> testing::AssertionResult >> testing::internal::EqHelper::Compare(const char*, const char*, >> const T1&, T2*) [with T1 = int, T2 = const clang::DirectoryEntry]' > > yes, they are annoying aren't they. ?They all come from google's unittest > library. ?I think it is best to fix them upstream at google. We're using googletest 1.5.0. These warnings seem to be fixed in 1.6.0, so here's a patch to upgrade us. Disclaimer: I've only tested this by doing "make check-all" on Linux/x86_64. Incidentally, the upgrade would have been much easier if we weren't carrying local changes to support Haiku OS and Minix. Can these be pushed upstream (or thrown away if no-one is using them)? Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: googletest-1.6.0.diff.gz Type: application/x-gzip Size: 76389 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110726/c19cd264/attachment-0001.gz From isanbard at gmail.com Tue Jul 26 05:41:15 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 26 Jul 2011 10:41:15 -0000 Subject: [llvm-commits] [llvm] r136074 - /llvm/trunk/docs/LangRef.html Message-ID: <20110726104115.D28DD2A6C12C@llvm.org> Author: void Date: Tue Jul 26 05:41:15 2011 New Revision: 136074 URL: http://llvm.org/viewvc/llvm-project?rev=136074&view=rev Log: Clean up the HTML here a bit. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=136074&r1=136073&r2=136074&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 26 05:41:15 2011 @@ -3010,7 +3010,8 @@
      Syntax:
      -  br i1 <cond>, label <iftrue>, label <iffalse>
        br label <dest>          ; Unconditional branch
+  br i1 <cond>, label <iftrue>, label <iffalse>
+  br label <dest>          ; Unconditional branch
      Overview:
      From wendling at apple.com Tue Jul 26 06:01:29 2011 From: wendling at apple.com (Bill Wendling) Date: Tue, 26 Jul 2011 04:01:29 -0700 Subject: [llvm-commits] [PATCH] New (C++0x) atomics: start implementation of 'fence' instruction In-Reply-To: References: Message-ID: <83281B1A-12A7-4A58-9A8C-B3E6BE680674@apple.com> On Jul 25, 2011, at 4:09 PM, Eli Friedman wrote: > On Sat, Jul 23, 2011 at 6:59 PM, Jeffrey Yasskin wrote: >>> Index: include/llvm/Instruction.def >>> =================================================================== >>> --- include/llvm/Instruction.def (revision 135822) >>> +++ include/llvm/Instruction.def (working copy) >>> @@ -133,41 +133,42 @@ >>> HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs >>> HANDLE_MEMORY_INST(28, Store , StoreInst ) >>> HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) >>> - LAST_MEMORY_INST(29) >>> +HANDLE_MEMORY_INST(30, Fence , FenceInst ) >> >> I assume you're skipping 31 and 32 here to save space for atomicrmw and cmpxchg? >> >>> + LAST_MEMORY_INST(32) > > Yes. > > And I just spotted an error a few lines down here; minor editing glitch. > Okay. Then you'll want to modify llvm-c/Core.h. It seems like it needs to be in sync with these numbers. :) -bw From baldrick at free.fr Tue Jul 26 10:03:53 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 15:03:53 -0000 Subject: [llvm-commits] [llvm] r136079 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20110726150353.47AA32A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 10:03:53 2011 New Revision: 136079 URL: http://llvm.org/viewvc/llvm-project?rev=136079&view=rev Log: Add helper function for getting true/false constants in a uniform way for i1 and vector of i1 types. Use these to make some code more self-documenting. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=136079&r1=136078&r2=136079&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Jul 26 10:03:53 2011 @@ -48,6 +48,26 @@ static Value *SimplifyXorInst(Value *, Value *, const TargetData *, const DominatorTree *, unsigned); +/// getFalse - For a boolean type, or a vector of boolean type, return false, or +/// a vector with every element false, as appropriate for the type. +static Constant *getFalse(Type *Ty) { + assert((Ty->isIntegerTy(1) || + (Ty->isVectorTy() && + cast(Ty)->getElementType()->isIntegerTy(1))) && + "Expected i1 type or a vector of i1!"); + return Constant::getNullValue(Ty); +} + +/// getTrue - For a boolean type, or a vector of boolean type, return true, or +/// a vector with every element true, as appropriate for the type. +static Constant *getTrue(Type *Ty) { + assert((Ty->isIntegerTy(1) || + (Ty->isVectorTy() && + cast(Ty)->getElementType()->isIntegerTy(1))) && + "Expected i1 type or a vector of i1!"); + return Constant::getAllOnesValue(Ty); +} + /// ValueDominatesPHI - Does the given value dominate the specified phi node? static bool ValueDominatesPHI(Value *V, PHINode *P, const DominatorTree *DT) { Instruction *I = dyn_cast(V); @@ -1478,48 +1498,46 @@ default: assert(false && "Unknown ICmp predicate!"); case ICmpInst::ICMP_ULT: - // getNullValue also works for vectors, unlike getFalse. - return Constant::getNullValue(ITy); + return getFalse(ITy); case ICmpInst::ICMP_UGE: - // getAllOnesValue also works for vectors, unlike getTrue. - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_ULE: if (isKnownNonZero(LHS, TD)) - return Constant::getNullValue(ITy); + return getFalse(ITy); break; case ICmpInst::ICMP_NE: case ICmpInst::ICMP_UGT: if (isKnownNonZero(LHS, TD)) - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); break; case ICmpInst::ICMP_SLT: ComputeSignBit(LHS, LHSKnownNonNegative, LHSKnownNegative, TD); if (LHSKnownNegative) - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); if (LHSKnownNonNegative) - return Constant::getNullValue(ITy); + return getFalse(ITy); break; case ICmpInst::ICMP_SLE: ComputeSignBit(LHS, LHSKnownNonNegative, LHSKnownNegative, TD); if (LHSKnownNegative) - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); if (LHSKnownNonNegative && isKnownNonZero(LHS, TD)) - return Constant::getNullValue(ITy); + return getFalse(ITy); break; case ICmpInst::ICMP_SGE: ComputeSignBit(LHS, LHSKnownNonNegative, LHSKnownNegative, TD); if (LHSKnownNegative) - return Constant::getNullValue(ITy); + return getFalse(ITy); if (LHSKnownNonNegative) - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); break; case ICmpInst::ICMP_SGT: ComputeSignBit(LHS, LHSKnownNonNegative, LHSKnownNegative, TD); if (LHSKnownNegative) - return Constant::getNullValue(ITy); + return getFalse(ITy); if (LHSKnownNonNegative && isKnownNonZero(LHS, TD)) - return ConstantInt::getAllOnesValue(ITy); + return getTrue(ITy); break; } } @@ -1811,8 +1829,7 @@ case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_UGE: - // getNullValue also works for vectors, unlike getFalse. - return Constant::getNullValue(ITy); + return getFalse(ITy); case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_SLE: ComputeSignBit(LHS, KnownNonNegative, KnownNegative, TD); @@ -1822,8 +1839,7 @@ case ICmpInst::ICMP_NE: case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_ULE: - // getAllOnesValue also works for vectors, unlike getTrue. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); } } if (RBO && match(RBO, m_URem(m_Value(), m_Specific(LHS)))) { @@ -1840,8 +1856,7 @@ case ICmpInst::ICMP_NE: case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_UGE: - // getAllOnesValue also works for vectors, unlike getTrue. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_SLE: ComputeSignBit(RHS, KnownNonNegative, KnownNegative, TD); @@ -1851,8 +1866,7 @@ case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_ULE: - // getNullValue also works for vectors, unlike getFalse. - return Constant::getNullValue(ITy); + return getFalse(ITy); } } @@ -1955,10 +1969,10 @@ } case CmpInst::ICMP_SGE: // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); case CmpInst::ICMP_SLT: // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } } @@ -2025,10 +2039,10 @@ } case CmpInst::ICMP_UGE: // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); case CmpInst::ICMP_ULT: // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } } @@ -2040,40 +2054,40 @@ // max(x, ?) pred min(x, ?). if (Pred == CmpInst::ICMP_SGE) // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); if (Pred == CmpInst::ICMP_SLT) // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } else if (match(LHS, m_SMin(m_Value(A), m_Value(B))) && match(RHS, m_SMax(m_Value(C), m_Value(D))) && (A == C || A == D || B == C || B == D)) { // min(x, ?) pred max(x, ?). if (Pred == CmpInst::ICMP_SLE) // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); if (Pred == CmpInst::ICMP_SGT) // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } else if (match(LHS, m_UMax(m_Value(A), m_Value(B))) && match(RHS, m_UMin(m_Value(C), m_Value(D))) && (A == C || A == D || B == C || B == D)) { // max(x, ?) pred min(x, ?). if (Pred == CmpInst::ICMP_UGE) // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); if (Pred == CmpInst::ICMP_ULT) // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } else if (match(LHS, m_UMin(m_Value(A), m_Value(B))) && match(RHS, m_UMax(m_Value(C), m_Value(D))) && (A == C || A == D || B == C || B == D)) { // min(x, ?) pred max(x, ?). if (Pred == CmpInst::ICMP_ULE) // Always true. - return Constant::getAllOnesValue(ITy); + return getTrue(ITy); if (Pred == CmpInst::ICMP_UGT) // Always false. - return Constant::getNullValue(ITy); + return getFalse(ITy); } // If the comparison is with the result of a select instruction, check whether From baldrick at free.fr Tue Jul 26 10:05:06 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 15:05:06 -0000 Subject: [llvm-commits] [llvm] r136080 - /llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Message-ID: <20110726150506.80FC42A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 10:05:06 2011 New Revision: 136080 URL: http://llvm.org/viewvc/llvm-project?rev=136080&view=rev Log: SrcDef is only written and never read. Remove it. Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=136080&r1=136079&r2=136080&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Jul 26 10:05:06 2011 @@ -295,7 +295,6 @@ if (!DefMI || !DefMI->getDesc().isBitcast()) return false; - unsigned SrcDef = 0; unsigned SrcSrc = 0; NumDefs = DefMI->getDesc().getNumDefs(); NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; @@ -308,13 +307,13 @@ unsigned Reg = MO.getReg(); if (!Reg) continue; - if (MO.isDef()) - SrcDef = Reg; - else if (SrcSrc) - // Multiple sources? - return false; - else - SrcSrc = Reg; + if (!MO.isDef()) { + if (SrcSrc) + // Multiple sources? + return false; + else + SrcSrc = Reg; + } } if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def)) From rafael.espindola at gmail.com Tue Jul 26 10:17:33 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 26 Jul 2011 15:17:33 -0000 Subject: [llvm-commits] [llvm] r136082 - in /llvm/trunk: include/llvm-c/Transforms/IPO.h lib/Transforms/IPO/IPO.cpp Message-ID: <20110726151733.29B352A6C12C@llvm.org> Author: rafael Date: Tue Jul 26 10:17:32 2011 New Revision: 136082 URL: http://llvm.org/viewvc/llvm-project?rev=136082&view=rev Log: LLVM 3.0 is here, remove old do nothing method. Modified: llvm/trunk/include/llvm-c/Transforms/IPO.h llvm/trunk/lib/Transforms/IPO/IPO.cpp Modified: llvm/trunk/include/llvm-c/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Transforms/IPO.h?rev=136082&r1=136081&r2=136082&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm-c/Transforms/IPO.h Tue Jul 26 10:17:32 2011 @@ -57,9 +57,6 @@ /** See llvm::createInternalizePass function. */ void LLVMAddInternalizePass(LLVMPassManagerRef, unsigned AllButMain); -// FIXME: Remove in LLVM 3.0. -void LLVMAddRaiseAllocationsPass(LLVMPassManagerRef PM); - /** See llvm::createStripDeadPrototypesPass function. */ void LLVMAddStripDeadPrototypesPass(LLVMPassManagerRef PM); Modified: llvm/trunk/lib/Transforms/IPO/IPO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPO.cpp?rev=136082&r1=136081&r2=136082&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/IPO.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/IPO.cpp Tue Jul 26 10:17:32 2011 @@ -98,11 +98,6 @@ unwrap(PM)->add(createInternalizePass(AllButMain != 0)); } - -void LLVMAddRaiseAllocationsPass(LLVMPassManagerRef PM) { - // FIXME: Remove in LLVM 3.0. -} - void LLVMAddStripDeadPrototypesPass(LLVMPassManagerRef PM) { unwrap(PM)->add(createStripDeadPrototypesPass()); } From rafael.espindola at gmail.com Tue Jul 26 10:23:23 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 26 Jul 2011 15:23:23 -0000 Subject: [llvm-commits] [llvm] r136083 - in /llvm/trunk: include/llvm-c/Transforms/IPO.h lib/Transforms/IPO/IPO.cpp Message-ID: <20110726152323.51D4A2A6C12C@llvm.org> Author: rafael Date: Tue Jul 26 10:23:23 2011 New Revision: 136083 URL: http://llvm.org/viewvc/llvm-project?rev=136083&view=rev Log: Add LLVMAddAlwaysInlinerPass to the C API. Modified: llvm/trunk/include/llvm-c/Transforms/IPO.h llvm/trunk/lib/Transforms/IPO/IPO.cpp Modified: llvm/trunk/include/llvm-c/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Transforms/IPO.h?rev=136083&r1=136082&r2=136083&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm-c/Transforms/IPO.h Tue Jul 26 10:23:23 2011 @@ -36,6 +36,9 @@ /** See llvm::createFunctionInliningPass function. */ void LLVMAddFunctionInliningPass(LLVMPassManagerRef PM); +/** See llvm::createAlwaysInlinerPass function. */ +void LLVMAddAlwaysInlinerPass(LLVMPassManagerRef PM); + /** See llvm::createGlobalDCEPass function. */ void LLVMAddGlobalDCEPass(LLVMPassManagerRef PM); Modified: llvm/trunk/lib/Transforms/IPO/IPO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPO.cpp?rev=136083&r1=136082&r2=136083&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/IPO.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/IPO.cpp Tue Jul 26 10:23:23 2011 @@ -70,6 +70,10 @@ unwrap(PM)->add(createFunctionInliningPass()); } +void LLVMAddAlwaysInlinerPass(LLVMPassManagerRef PM) { + unwrap(PM)->add(llvm::createAlwaysInlinerPass()); +} + void LLVMAddGlobalDCEPass(LLVMPassManagerRef PM) { unwrap(PM)->add(createGlobalDCEPass()); } From baldrick at free.fr Tue Jul 26 10:30:04 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 15:30:04 -0000 Subject: [llvm-commits] [llvm] r136085 - in /llvm/trunk: include/llvm/ADT/Triple.h lib/Support/Triple.cpp Message-ID: <20110726153004.AAA452A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 10:30:04 2011 New Revision: 136085 URL: http://llvm.org/viewvc/llvm-project?rev=136085&view=rev Log: Teach the Triple class about kfreebsd (FreeBSD kernel with a GNU userspace). Modified: llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=136085&r1=136084&r2=136085&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Tue Jul 26 10:30:04 2011 @@ -82,6 +82,7 @@ DragonFly, FreeBSD, IOS, + KFreeBSD, Linux, Lv2, // PS3 MacOSX, Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=136085&r1=136084&r2=136085&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Tue Jul 26 10:30:04 2011 @@ -97,6 +97,7 @@ case DragonFly: return "dragonfly"; case FreeBSD: return "freebsd"; case IOS: return "ios"; + case KFreeBSD: return "kfreebsd"; case Linux: return "linux"; case Lv2: return "lv2"; case MacOSX: return "macosx"; @@ -327,6 +328,8 @@ return FreeBSD; else if (OSName.startswith("ios")) return IOS; + else if (OSName.startswith("kfreebsd")) + return KFreeBSD; else if (OSName.startswith("linux")) return Linux; else if (OSName.startswith("lv2")) From baldrick at free.fr Tue Jul 26 10:30:42 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 15:30:42 -0000 Subject: [llvm-commits] [dragonegg] r136086 - in /dragonegg/trunk/include/kfreebsd: ./ dragonegg/ dragonegg/OS.h Message-ID: <20110726153042.D2C1A2A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 10:30:42 2011 New Revision: 136086 URL: http://llvm.org/viewvc/llvm-project?rev=136086&view=rev Log: Basic support for kfreebsd. Added: dragonegg/trunk/include/kfreebsd/ dragonegg/trunk/include/kfreebsd/dragonegg/ dragonegg/trunk/include/kfreebsd/dragonegg/OS.h Added: dragonegg/trunk/include/kfreebsd/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/kfreebsd/dragonegg/OS.h?rev=136086&view=auto ============================================================================== --- dragonegg/trunk/include/kfreebsd/dragonegg/OS.h (added) +++ dragonegg/trunk/include/kfreebsd/dragonegg/OS.h Tue Jul 26 10:30:42 2011 @@ -0,0 +1,33 @@ +//===------------ OS.h - KFreeBSD specific definitions ----------*- C++ -*-===// +// +// Copyright (C) 2009, 2010, 2011 Duncan Sands et al. +// +// This file is part of DragonEgg. +// +// DragonEgg is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free Software +// Foundation; either version 2, or (at your option) any later version. +// +// DragonEgg is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with +// DragonEgg; see the file COPYING. If not, write to the Free Software +// Foundation, 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA. +// +//===----------------------------------------------------------------------===// +// This file provides KFreeBSD specific declarations. +//===----------------------------------------------------------------------===// + +#ifndef DRAGONEGG_OS_H +#define DRAGONEGG_OS_H + +/* Yes, we support PIC codegen for KFreeBSD targets! */ +#define LLVM_SET_RELOC_MODEL(RelocModel) \ + if (flag_pic) \ + RelocModel = Reloc::PIC_; \ + else \ + RelocModel = Reloc::Static; + +#endif /* DRAGONEGG_OS_H */ From baldrick at free.fr Tue Jul 26 10:31:41 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 15:31:41 -0000 Subject: [llvm-commits] [dragonegg] r136087 - /dragonegg/trunk/src/Types.cpp Message-ID: <20110726153141.28AC22A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 10:31:40 2011 New Revision: 136087 URL: http://llvm.org/viewvc/llvm-project?rev=136087&view=rev Log: Remove variable which is only written, never read. Modified: dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=136087&r1=136086&r2=136087&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Tue Jul 26 10:31:40 2011 @@ -1405,7 +1405,6 @@ bool FindBiggest = TREE_CODE(type) != QUAL_UNION_TYPE; Type *UnionTy = 0; - tree GccUnionTy = 0; tree UnionField = 0; unsigned MinAlign = ~0U; uint64_t BestSize = FindBiggest ? 0 : ~(uint64_t)0; @@ -1439,7 +1438,6 @@ (!FindBiggest && Size < BestSize)) { UnionTy = TheTy; UnionField = Field; - GccUnionTy = TheGccTy; BestSize = Size; MinAlign = Align; } From grosbach at apple.com Tue Jul 26 10:41:22 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 15:41:22 -0000 Subject: [llvm-commits] [llvm] r136088 - in /llvm/trunk/test/MC/ARM: basic-arm-instructions.s diagnostics.s Message-ID: <20110726154122.C943E2A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 10:41:22 2011 New Revision: 136088 URL: http://llvm.org/viewvc/llvm-project?rev=136088&view=rev Log: Update ARM STM tests. Fix check: prefix for diagnostic tests. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136088&r1=136087&r2=136088&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 26 10:41:22 2011 @@ -1669,25 +1669,26 @@ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} - stmia r2, {r1,r3-r6,sp} - stmib r2, {r1,r3-r6,sp} - stmda r2, {r1,r3-r6,sp} - stmdb r2, {r1,r3-r6,sp} - stmfd r2, {r1,r3-r6,sp} + stmia r3, {r1,r3-r6,lr} + stmib r4, {r1,r3-r6,sp} + stmda r5, {r1,r3-r6,sp} + stmdb r6, {r1,r3-r6,r8} + stmfd sp, {r1,r3-r6,sp} @ with update - stmia r2!, {r1,r3-r6,sp} - stmib r2!, {r1,r3-r6,sp} - stmda r2!, {r1,r3-r6,sp} - stmdb r2!, {r1,r3-r6,sp} -@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] -@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] + stm r8!, {r1,r3-r6,sp} + stmib r9!, {r1,r3-r6,sp} + stmda sp!, {r1,r3-r6} + stmdb r0!, {r1,r5,r7,sp} -@ CHECK: stm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8] -@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9] -@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8] -@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9] +@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stm r3, {lr, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x40,0x83,0xe8] +@ CHECK: stmib r4, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x84,0xe9] +@ CHECK: stmda r5, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x05,0xe8] +@ CHECK: stmdb r6, {r1, r3, r4, r5, r6, r8} @ encoding: [0x7a,0x01,0x06,0xe9] +@ CHECK: stmdb sp, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x0d,0xe9] + +@ CHECK: stm r8!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa8,0xe8] +@ CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa9,0xe9] +@ CHECK: stmda sp!, {r1, r3, r4, r5, r6} @ encoding: [0x7a,0x00,0x2d,0xe8] +@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9] Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136088&r1=136087&r2=136088&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 26 10:41:22 2011 @@ -126,24 +126,24 @@ pkhbt r2, r2, r3, asr #3 pkhtb r2, r2, r3, lsl #3 -@ CHECK: error: immediate value out of range -@ CHECK: pkhbt r2, r2, r3, lsl #-1 -@ CHECK: ^ -@ CHECK: error: immediate value out of range -@ CHECK: pkhbt r2, r2, r3, lsl #32 -@ CHECK: ^ -@ CHECK: error: immediate value out of range -@ CHECK: pkhtb r2, r2, r3, asr #0 -@ CHECK: ^ -@ CHECK: error: immediate value out of range -@ CHECK: pkhtb r2, r2, r3, asr #33 -@ CHECK: ^ -@ CHECK: error: lsl operand expected. -@ CHECK: pkhbt r2, r2, r3, asr #3 -@ CHECK: ^ -@ CHECK: error: asr operand expected. -@ CHECK: pkhtb r2, r2, r3, lsl #3 -@ CHECK: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: lsl operand expected. +@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: asr operand expected. +@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3 +@ CHECK-ERRORS: ^ @ bad values for SETEND @@ -151,15 +151,15 @@ setend me setend 1 -@ CHECK: error: instruction 'setend' is not predicable, but condition code specified -@ CHECK: setendne be -@ CHECK: ^ -@ CHECK: error: 'be' or 'le' operand expected -@ CHECK: setend me -@ CHECK: ^ -@ CHECK: error: 'be' or 'le' operand expected -@ CHECK: setend 1 -@ CHECK: ^ +@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified +@ CHECK-ERRORS: setendne be +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'be' or 'le' operand expected +@ CHECK-ERRORS: setend me +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'be' or 'le' operand expected +@ CHECK-ERRORS: setend 1 +@ CHECK-ERRORS: ^ @ Out of range immediates and bad shift types for SSAT @@ -173,41 +173,49 @@ ssat r8, #1, r10, lsl fred ssat r8, #1, r10, lsl #fred -@ CHECK: error: invalid operand for instruction -@ CHECK: ssat r8, #0, r10, lsl #8 -@ CHECK: ^ -@ CHECK: error: invalid operand for instruction -@ CHECK: ssat r8, #33, r10, lsl #8 -@ CHECK: ^ -@ CHECK: error: 'lsr' shift amount must be in range [0,31] -@ CHECK: ssat r8, #1, r10, lsl #-1 -@ CHECK: ^ -@ CHECK: error: 'lsr' shift amount must be in range [0,31] -@ CHECK: ssat r8, #1, r10, lsl #32 -@ CHECK: ^ -@ CHECK: error: 'asr' shift amount must be in range [1,32] -@ CHECK: ssat r8, #1, r10, asr #0 -@ CHECK: ^ -@ CHECK: error: 'asr' shift amount must be in range [1,32] -@ CHECK: ssat r8, #1, r10, asr #33 -@ CHECK: ^ -@ CHECK: error: shift operator 'asr' or 'lsl' expected -@ CHECK: ssat r8, #1, r10, lsr #5 -@ CHECK: ^ -@ CHECK: error: '#' expected -@ CHECK: ssat r8, #1, r10, lsl fred -@ CHECK: ^ -@ CHECK: error: shift amount must be an immediate -@ CHECK: ssat r8, #1, r10, lsl #fred -@ CHECK: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31] +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31] +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32] +@ CHECK-ERRORS: ssat r8, #1, r10, asr #0 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32] +@ CHECK-ERRORS: ssat r8, #1, r10, asr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected +@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: '#' expected +@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: shift amount must be an immediate +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred +@ CHECK-ERRORS: ^ @ Out of range immediates for SSAT16 ssat16 r2, #0, r7 ssat16 r3, #17, r5 -@ CHECK: error: invalid operand for instruction -@ CHECK: ssat16 r2, #0, r7 -@ CHECK: ^ -@ CHECK: error: invalid operand for instruction -@ CHECK: ssat16 r3, #17, r5 -@ CHECK: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat16 r2, #0, r7 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat16 r3, #17, r5 +@ CHECK-ERRORS: ^ + + + @ Out of order STM registers + stmda sp!, {r5, r2} + +@ CHECK-ERRORS: warning: register not in ascending order in register list +@ CHECK-ERRORS: stmda sp!, {r5, r2} +@ CHECK-ERRORS: ^ From grosbach at apple.com Tue Jul 26 10:44:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 15:44:05 -0000 Subject: [llvm-commits] [llvm] r136089 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110726154405.6475E2A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 10:44:05 2011 New Revision: 136089 URL: http://llvm.org/viewvc/llvm-project?rev=136089&view=rev Log: ARM assembly parsing and encoding tests for SUB instruction. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136089&r1=136088&r2=136089&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 26 10:44:05 2011 @@ -1692,3 +1692,63 @@ @ CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa9,0xe9] @ CHECK: stmda sp!, {r1, r3, r4, r5, r6} @ encoding: [0x7a,0x00,0x2d,0xe8] @ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9] + + + at ------------------------------------------------------------------------------ +@ FIXME:STR* + at ------------------------------------------------------------------------------ + + + at ------------------------------------------------------------------------------ +@ SUB + at ------------------------------------------------------------------------------ + sub r4, r5, #0xf000 + sub r4, r5, r6 + sub r4, r5, r6, lsl #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, asr #5 + sub r4, r5, r6, ror #5 + sub r6, r7, r8, lsl r9 + sub r6, r7, r8, lsr r9 + sub r6, r7, r8, asr r9 + sub r6, r7, r8, ror r9 + + @ destination register is optional + sub r5, #0xf000 + sub r4, r5 + sub r4, r5, lsl #5 + sub r4, r5, lsr #5 + sub r4, r5, lsr #5 + sub r4, r5, asr #5 + sub r4, r5, ror #5 + sub r6, r7, lsl r9 + sub r6, r7, lsr r9 + sub r6, r7, asr r9 + sub r6, r7, ror r9 + +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x45,0xe0] +@ CHECK: sub r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x47,0xe0] + + +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r4, r4, r5 @ encoding: [0x05,0x40,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x44,0xe0] +@ CHECK: sub r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x46,0xe0] + From baldrick at free.fr Tue Jul 26 10:57:52 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 17:57:52 +0200 Subject: [llvm-commits] [PATCH][RFC] upgrade to googletest 1.6.0 (was Re: [LLVMdev] Build of latest llvm gives warning and error) In-Reply-To: References: Message-ID: <4E2EE400.6000505@free.fr> Hi Jay, >> yes, they are annoying aren't they. They all come from google's unittest >> library. I think it is best to fix them upstream at google. > > We're using googletest 1.5.0. These warnings seem to be fixed in > 1.6.0, so here's a patch to upgrade us. Disclaimer: I've only tested > this by doing "make check-all" on Linux/x86_64. > > Incidentally, the upgrade would have been much easier if we weren't > carrying local changes to support Haiku OS and Minix. Can these be > pushed upstream (or thrown away if no-one is using them)? thanks for doing this. I vote that we throw Haiku and Minix support away. If the Haiku and Minix people want googletest to support these platforms I think we should insist that support should go upstream first (and we would then pull the fixes from upstream). Ciao, Duncan. From grosbach at apple.com Tue Jul 26 11:24:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 16:24:27 -0000 Subject: [llvm-commits] [llvm] r136090 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s utils/TableGen/EDEmitter.cpp Message-ID: <20110726162428.1EDEF2A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 11:24:27 2011 New Revision: 136090 URL: http://llvm.org/viewvc/llvm-project?rev=136090&view=rev Log: ARM parsing and encoding for SVC instruction. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 11:24:27 2011 @@ -515,6 +515,15 @@ let ParserMatchClass = Imm0_65535ExprAsmOperand; } +/// imm24b - True if the 32-bit immediate is encodable in 24 bits. +def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; } +def imm24b : Operand, ImmLeaf= 0 && Imm <= 0xffffff; +}]> { + let ParserMatchClass = Imm24bitAsmOperand; +} + + /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield /// e.g., 0xf000ffff def bf_inv_mask_imm : Operand, @@ -1730,10 +1739,9 @@ let Inst{3-0} = opt; } -// Supervisor Call (Software Interrupt) -- for disassembly only +// Supervisor Call (Software Interrupt) let isCall = 1, Uses = [SP] in { -def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", - [/* For disassembly only; pattern left blank */]> { +def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> { bits<24> svc; let Inst{23-0} = svc; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Jul 26 11:24:27 2011 @@ -547,7 +547,7 @@ // A8.6.16 B: Encoding T1 // If Inst{11-8} == 0b1111 then SEE SVC let isCall = 1, Uses = [SP] in -def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br, +def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, "svc", "\t$imm", []>, Encoding16 { bits<8> imm; let Inst{15-12} = 0b1101; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 26 11:24:27 2011 @@ -467,6 +467,14 @@ int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } + bool isImm24bit() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value >= 0 && Value <= 0xffffff; + } bool isPKHLSLImm() const { if (Kind != Immediate) return false; @@ -738,6 +746,11 @@ addExpr(Inst, getImm()); } + void addImm24bitOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 26 11:24:27 2011 @@ -1752,3 +1752,14 @@ @ CHECK: sub r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x46,0xe0] @ CHECK: sub r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x46,0xe0] + + at ------------------------------------------------------------------------------ +@ SVC + at ------------------------------------------------------------------------------ + svc #16 + svc #0 + svc #0xffffff + +@ CHECK: svc #16 @ encoding: [0x10,0x00,0x00,0xef] +@ CHECK: svc #0 @ encoding: [0x00,0x00,0x00,0xef] +@ CHECK: svc #16777215 @ encoding: [0xff,0xff,0xff,0xef] Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 26 11:24:27 2011 @@ -219,3 +219,10 @@ @ CHECK-ERRORS: warning: register not in ascending order in register list @ CHECK-ERRORS: stmda sp!, {r5, r2} @ CHECK-ERRORS: ^ + + + @ Out of range immediate on SVC + svc #0x1000000 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: svc #0x1000000 +@ CHECK-ERRORS: ^ Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=136090&r1=136089&r2=136090&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Jul 26 11:24:27 2011 @@ -596,6 +596,7 @@ IMM("imm0_4095"); IMM("imm0_65535"); IMM("imm0_65535_expr"); + IMM("imm24b"); IMM("pkh_lsl_amt"); IMM("pkh_asr_amt"); IMM("jt2block_operand"); From grosbach at apple.com Tue Jul 26 11:44:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 16:44:05 -0000 Subject: [llvm-commits] [llvm] r136091 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110726164405.3987B2A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 11:44:05 2011 New Revision: 136091 URL: http://llvm.org/viewvc/llvm-project?rev=136091&view=rev Log: ARM fix asm parsing range check for [0,31] immediates. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136091&r1=136090&r2=136091&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 11:44:05 2011 @@ -494,7 +494,9 @@ def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; } def imm0_31 : Operand, ImmLeaf= 0 && Imm < 32; -}]>; +}]> { + let ParserMatchClass = Imm0_31AsmOperand; +} /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'. def imm0_31_m1 : Operand, ImmLeaf Author: grosbach Date: Tue Jul 26 12:10:22 2011 New Revision: 136095 URL: http://llvm.org/viewvc/llvm-project?rev=136095&view=rev Log: Clean up the ARM asm parser a bit. No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=136095&r1=136094&r2=136095&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jul 26 12:10:22 2011 @@ -600,7 +600,7 @@ let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3"; + let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3"; } class AI3stridx op, bit isByte, bit isPre, dag oops, dag iops, Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136095&r1=136094&r2=136095&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 12:10:22 2011 @@ -1853,7 +1853,7 @@ let Inst{23} = addr{12}; let Inst{19-16} = addr{17-14}; let Inst{11-0} = addr{11-0}; - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2"; + let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins GPR:$Rn, am2offset:$offset), @@ -1950,7 +1950,7 @@ let Inst{21} = 1; // overwrite let Inst{19-16} = addr{17-14}; let Inst{11-0} = addr{11-0}; - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2"; + let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru, @@ -1965,7 +1965,7 @@ let Inst{21} = 1; // overwrite let Inst{19-16} = addr{17-14}; let Inst{11-0} = addr{11-0}; - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2"; + let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, @@ -2068,7 +2068,7 @@ "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { let Inst{21} = 1; // overwrite - let AsmMatchConverter = "CvtStWriteBackRegAddrMode2"; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), @@ -2076,7 +2076,7 @@ "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { let Inst{21} = 1; // overwrite - let AsmMatchConverter = "CvtStWriteBackRegAddrMode2"; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr), @@ -2084,7 +2084,7 @@ "strht", "\t$Rt, $addr", "$addr.base = $base_wb", [/* For disassembly only; pattern left blank */]> { let Inst{21} = 1; // overwrite - let AsmMatchConverter = "CvtStWriteBackRegAddrMode3"; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode3"; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136095&r1=136094&r2=136095&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 26 12:10:22 2011 @@ -47,20 +47,19 @@ void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } - int TryParseRegister(); - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); - bool TryParseRegisterWithWriteBack(SmallVectorImpl &); - int TryParseShiftRegister(SmallVectorImpl &); - bool ParseRegisterList(SmallVectorImpl &); - bool ParseMemory(SmallVectorImpl &, + int tryParseRegister(); + bool tryParseRegisterWithWriteBack(SmallVectorImpl &); + int tryparseShiftRegister(SmallVectorImpl &); + bool parseRegisterList(SmallVectorImpl &); + bool parseMemory(SmallVectorImpl &, ARMII::AddrMode AddrMode); - bool ParseOperand(SmallVectorImpl &, StringRef Mnemonic); - bool ParsePrefix(ARMMCExpr::VariantKind &RefKind); - const MCExpr *ApplyPrefixToExpr(const MCExpr *E, + bool parseOperand(SmallVectorImpl &, StringRef Mnemonic); + bool parsePrefix(ARMMCExpr::VariantKind &RefKind); + const MCExpr *applyPrefixToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind Variant); - bool ParseMemoryOffsetReg(bool &Negative, + bool parseMemoryOffsetReg(bool &Negative, bool &OffsetRegShifted, enum ARM_AM::ShiftOpc &ShiftType, const MCExpr *&ShiftAmount, @@ -68,20 +67,17 @@ bool &OffsetIsReg, int &OffsetRegNum, SMLoc &E); - bool ParseShift(enum ARM_AM::ShiftOpc &St, + bool parseShift(enum ARM_AM::ShiftOpc &St, const MCExpr *&ShiftAmount, SMLoc &E); - bool ParseDirectiveWord(unsigned Size, SMLoc L); - bool ParseDirectiveThumb(SMLoc L); - bool ParseDirectiveThumbFunc(SMLoc L); - bool ParseDirectiveCode(SMLoc L); - bool ParseDirectiveSyntax(SMLoc L); + bool parseDirectiveWord(unsigned Size, SMLoc L); + bool parseDirectiveThumb(SMLoc L); + bool parseDirectiveThumbFunc(SMLoc L); + bool parseDirectiveCode(SMLoc L); + bool parseDirectiveSyntax(SMLoc L); - bool MatchAndEmitInstruction(SMLoc IDLoc, - SmallVectorImpl &Operands, - MCStreamer &Out); - StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, + StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, bool &CarrySetting, unsigned &ProcessorIMod); - void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, + void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode); bool isThumb() const { @@ -130,13 +126,13 @@ OperandMatchResultTy parseShifterImm(SmallVectorImpl&); // Asm Match Converter Methods - bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, + bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, + bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, + bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, + bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); public: @@ -148,9 +144,15 @@ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } - virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, + // Implementation of the MCTargetAsmParser interface: + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); + bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); - virtual bool ParseDirective(AsmToken DirectiveID); + bool ParseDirective(AsmToken DirectiveID); + + bool MatchAndEmitInstruction(SMLoc IDLoc, + SmallVectorImpl &Operands, + MCStreamer &Out); }; } // end anonymous namespace @@ -1207,7 +1209,7 @@ bool ARMAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { - RegNo = TryParseRegister(); + RegNo = tryParseRegister(); return (RegNo == (unsigned)-1); } @@ -1216,7 +1218,7 @@ /// and if it is a register name the token is eaten and the register number is /// returned. Otherwise return -1. /// -int ARMAsmParser::TryParseRegister() { +int ARMAsmParser::tryParseRegister() { const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); @@ -1244,7 +1246,7 @@ // occurs, return -1. An irrecoverable error is one where tokens have been // consumed in the process of trying to parse the shifter (i.e., when it is // indeed a shifter operand, but malformed). -int ARMAsmParser::TryParseShiftRegister( +int ARMAsmParser::tryparseShiftRegister( SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); @@ -1306,7 +1308,7 @@ return -1; } } else if (Parser.getTok().is(AsmToken::Identifier)) { - ShiftReg = TryParseRegister(); + ShiftReg = tryParseRegister(); SMLoc L = Parser.getTok().getLoc(); if (ShiftReg == -1) { Error (L, "expected immediate or register in shift operand"); @@ -1338,9 +1340,9 @@ /// TODO this is likely to change to allow different register types and or to /// parse for a specific register type. bool ARMAsmParser:: -TryParseRegisterWithWriteBack(SmallVectorImpl &Operands) { +tryParseRegisterWithWriteBack(SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); - int RegNo = TryParseRegister(); + int RegNo = tryParseRegister(); if (RegNo == -1) return true; @@ -1438,7 +1440,7 @@ /// Parse a register list, return it if successful else return null. The first /// token must be a '{' when called. bool ARMAsmParser:: -ParseRegisterList(SmallVectorImpl &Operands) { +parseRegisterList(SmallVectorImpl &Operands) { assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Curly Brace"); SMLoc S = Parser.getTok().getLoc(); @@ -1458,7 +1460,7 @@ return true; } - int RegNum = TryParseRegister(); + int RegNum = tryParseRegister(); if (RegNum == -1) { Error(RegLoc, "register expected"); return true; @@ -1650,7 +1652,7 @@ parseMemMode2Operand(SmallVectorImpl &Operands) { assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); - if (ParseMemory(Operands, ARMII::AddrMode2)) + if (parseMemory(Operands, ARMII::AddrMode2)) return MatchOperand_NoMatch; return MatchOperand_Success; @@ -1661,7 +1663,7 @@ parseMemMode3Operand(SmallVectorImpl &Operands) { assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); - if (ParseMemory(Operands, ARMII::AddrMode3)) + if (parseMemory(Operands, ARMII::AddrMode3)) return MatchOperand_NoMatch; return MatchOperand_Success; @@ -1804,11 +1806,11 @@ return MatchOperand_Success; } -/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. +/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. bool ARMAsmParser:: -CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, +cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -1820,11 +1822,11 @@ return true; } -/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. +/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. bool ARMAsmParser:: -CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, +cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. Inst.addOperand(MCOperand::CreateImm(0)); @@ -1834,11 +1836,11 @@ return true; } -/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. +/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. bool ARMAsmParser:: -CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, +cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -1850,11 +1852,11 @@ return true; } -/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. +/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. bool ARMAsmParser:: -CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, +cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. Inst.addOperand(MCOperand::CreateImm(0)); @@ -1870,7 +1872,7 @@ /// TODO Only preindexing and postindexing addressing are started, unindexed /// with option, etc are still to do. bool ARMAsmParser:: -ParseMemory(SmallVectorImpl &Operands, +parseMemory(SmallVectorImpl &Operands, ARMII::AddrMode AddrMode = ARMII::AddrModeNone) { SMLoc S, E; assert(Parser.getTok().is(AsmToken::LBrac) && @@ -1883,7 +1885,7 @@ Error(BaseRegTok.getLoc(), "register expected"); return true; } - int BaseRegNum = TryParseRegister(); + int BaseRegNum = tryParseRegister(); if (BaseRegNum == -1) { Error(BaseRegTok.getLoc(), "register expected"); return true; @@ -1912,7 +1914,7 @@ Preindexed = true; Parser.Lex(); // Eat comma token. - if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, + if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, E)) return true; const AsmToken &RBracTok = Parser.getTok(); @@ -1958,7 +1960,7 @@ Parser.Lex(); // Eat comma token. - if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, + if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, E)) return true; @@ -1993,7 +1995,7 @@ /// +/-Rm, shift /// #offset /// we return false on success or an error otherwise. -bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative, +bool ARMAsmParser::parseMemoryOffsetReg(bool &Negative, bool &OffsetRegShifted, enum ARM_AM::ShiftOpc &ShiftType, const MCExpr *&ShiftAmount, @@ -2017,7 +2019,7 @@ const AsmToken &OffsetRegTok = Parser.getTok(); if (OffsetRegTok.is(AsmToken::Identifier)) { SMLoc CurLoc = OffsetRegTok.getLoc(); - OffsetRegNum = TryParseRegister(); + OffsetRegNum = tryParseRegister(); if (OffsetRegNum != -1) { OffsetIsReg = true; E = CurLoc; @@ -2032,7 +2034,7 @@ Parser.Lex(); // Eat comma token. const AsmToken &Tok = Parser.getTok(); - if (ParseShift(ShiftType, ShiftAmount, E)) + if (parseShift(ShiftType, ShiftAmount, E)) return Error(Tok.getLoc(), "shift expected"); OffsetRegShifted = true; } @@ -2052,11 +2054,11 @@ return false; } -/// ParseShift as one of these two: +/// parseShift as one of these two: /// ( lsl | lsr | asr | ror ) , # shift_amount /// rrx /// and returns true if it parses a shift otherwise it returns false. -bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St, +bool ARMAsmParser::parseShift(ARM_AM::ShiftOpc &St, const MCExpr *&ShiftAmount, SMLoc &E) { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) @@ -2094,7 +2096,7 @@ /// Parse a arm instruction operand. For now this parses the operand regardless /// of the mnemonic. -bool ARMAsmParser::ParseOperand(SmallVectorImpl &Operands, +bool ARMAsmParser::parseOperand(SmallVectorImpl &Operands, StringRef Mnemonic) { SMLoc S, E; @@ -2114,9 +2116,9 @@ Error(Parser.getTok().getLoc(), "unexpected token in operand"); return true; case AsmToken::Identifier: { - if (!TryParseRegisterWithWriteBack(Operands)) + if (!tryParseRegisterWithWriteBack(Operands)) return false; - int Res = TryParseShiftRegister(Operands); + int Res = tryparseShiftRegister(Operands); if (Res == 0) // success return false; else if (Res == -1) // irrecoverable error @@ -2138,9 +2140,9 @@ return false; } case AsmToken::LBrac: - return ParseMemory(Operands); + return parseMemory(Operands); case AsmToken::LCurly: - return ParseRegisterList(Operands); + return parseRegisterList(Operands); case AsmToken::Hash: // #42 -> immediate. // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate @@ -2157,7 +2159,7 @@ // FIXME: Check it's an expression prefix, // e.g. (FOO - :lower16:BAR) isn't legal. ARMMCExpr::VariantKind RefKind; - if (ParsePrefix(RefKind)) + if (parsePrefix(RefKind)) return true; const MCExpr *SubExprVal; @@ -2173,9 +2175,9 @@ } } -// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. +// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. // :lower16: and :upper16:. -bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) { +bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { RefKind = ARMMCExpr::VK_ARM_None; // :lower16: and :upper16: modifiers @@ -2207,7 +2209,7 @@ } const MCExpr * -ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, +ARMAsmParser::applyPrefixToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind Variant) { // Recurse over the given expression, rebuilding it to apply the given variant // to the leftmost symbol. @@ -2234,7 +2236,7 @@ case MCExpr::Binary: { const MCBinaryExpr *BE = cast(E); - const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); + const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant); const MCExpr *RHS = BE->getRHS(); if (!LHS) return 0; @@ -2251,7 +2253,7 @@ /// setting letters to form a canonical mnemonic and flags. // // FIXME: Would be nice to autogen this. -StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic, +StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, bool &CarrySetting, unsigned &ProcessorIMod) { @@ -2336,7 +2338,7 @@ // // FIXME: It would be nice to autogen this. void ARMAsmParser:: -GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, +getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || @@ -2381,7 +2383,7 @@ unsigned PredicationCode; unsigned ProcessorIMod; bool CarrySetting; - Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting, + Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, ProcessorIMod); Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); @@ -2397,7 +2399,7 @@ // the matcher deal with finding the right instruction or generating an // appropriate error. bool CanAcceptCarrySet, CanAcceptPredicationCode; - GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); + getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); // If we had a carry-set on an instruction that can't do that, issue an // error. @@ -2453,7 +2455,7 @@ // Read the remaining operands. if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. - if (ParseOperand(Operands, Mnemonic)) { + if (parseOperand(Operands, Mnemonic)) { Parser.EatToEndOfStatement(); return true; } @@ -2462,7 +2464,7 @@ Parser.Lex(); // Eat the comma. // Parse and remember the operand. - if (ParseOperand(Operands, Mnemonic)) { + if (parseOperand(Operands, Mnemonic)) { Parser.EatToEndOfStatement(); return true; } @@ -2534,25 +2536,25 @@ return true; } -/// ParseDirective parses the arm specific directives +/// parseDirective parses the arm specific directives bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { StringRef IDVal = DirectiveID.getIdentifier(); if (IDVal == ".word") - return ParseDirectiveWord(4, DirectiveID.getLoc()); + return parseDirectiveWord(4, DirectiveID.getLoc()); else if (IDVal == ".thumb") - return ParseDirectiveThumb(DirectiveID.getLoc()); + return parseDirectiveThumb(DirectiveID.getLoc()); else if (IDVal == ".thumb_func") - return ParseDirectiveThumbFunc(DirectiveID.getLoc()); + return parseDirectiveThumbFunc(DirectiveID.getLoc()); else if (IDVal == ".code") - return ParseDirectiveCode(DirectiveID.getLoc()); + return parseDirectiveCode(DirectiveID.getLoc()); else if (IDVal == ".syntax") - return ParseDirectiveSyntax(DirectiveID.getLoc()); + return parseDirectiveSyntax(DirectiveID.getLoc()); return true; } -/// ParseDirectiveWord +/// parseDirectiveWord /// ::= .word [ expression (, expression)* ] -bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { +bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { if (getLexer().isNot(AsmToken::EndOfStatement)) { for (;;) { const MCExpr *Value; @@ -2575,9 +2577,9 @@ return false; } -/// ParseDirectiveThumb +/// parseDirectiveThumb /// ::= .thumb -bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) { +bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(L, "unexpected token in directive"); Parser.Lex(); @@ -2588,9 +2590,9 @@ return false; } -/// ParseDirectiveThumbFunc +/// parseDirectiveThumbFunc /// ::= .thumbfunc symbol_name -bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) { +bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); bool isMachO = MAI.hasSubsectionsViaSymbols(); StringRef Name; @@ -2620,9 +2622,9 @@ return false; } -/// ParseDirectiveSyntax +/// parseDirectiveSyntax /// ::= .syntax unified | divided -bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) { +bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return Error(L, "unexpected token in .syntax directive"); @@ -2643,9 +2645,9 @@ return false; } -/// ParseDirectiveCode +/// parseDirectiveCode /// ::= .code 16 | 32 -bool ARMAsmParser::ParseDirectiveCode(SMLoc L) { +bool ARMAsmParser::parseDirectiveCode(SMLoc L) { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Integer)) return Error(L, "unexpected token in .code directive"); From grosbach at apple.com Tue Jul 26 12:11:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 17:11:05 -0000 Subject: [llvm-commits] [llvm] r136096 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110726171105.AABBA2A6C12D@llvm.org> Author: grosbach Date: Tue Jul 26 12:11:05 2011 New Revision: 136096 URL: http://llvm.org/viewvc/llvm-project?rev=136096&view=rev Log: ARM SWP instructions store, too, not just load. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136096&r1=136095&r2=136096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 12:11:05 2011 @@ -3660,11 +3660,9 @@ } // SWP/SWPB are deprecated in V6/V7 and for disassembly only. -let mayLoad = 1 in { -def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp", - [/* For disassembly only; pattern left blank */]>; -def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", - [/* For disassembly only; pattern left blank */]>; +let mayLoad = 1, mayStore = 1 in { +def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp", []>; +def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", []>; } //===----------------------------------------------------------------------===// From clattner at apple.com Tue Jul 26 12:11:43 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 26 Jul 2011 10:11:43 -0700 Subject: [llvm-commits] [LLVMdev] [PATCH][RFC] upgrade to googletest 1.6.0 (was Re: Build of latest llvm gives warning and error) In-Reply-To: <4E2EE400.6000505@free.fr> References: <4E2EE400.6000505@free.fr> Message-ID: <6FF6E408-6C23-47AC-B313-0FE9644D1FBB@apple.com> On Jul 26, 2011, at 8:57 AM, Duncan Sands wrote: > Hi Jay, > >>> yes, they are annoying aren't they. They all come from google's unittest >>> library. I think it is best to fix them upstream at google. >> >> We're using googletest 1.5.0. These warnings seem to be fixed in >> 1.6.0, so here's a patch to upgrade us. Disclaimer: I've only tested >> this by doing "make check-all" on Linux/x86_64. >> >> Incidentally, the upgrade would have been much easier if we weren't >> carrying local changes to support Haiku OS and Minix. Can these be >> pushed upstream (or thrown away if no-one is using them)? > > thanks for doing this. I vote that we throw Haiku and Minix support away. If > the Haiku and Minix people want googletest to support these platforms I think > we should insist that support should go upstream first (and we would then pull > the fixes from upstream). +1 -Chris From grosbach at apple.com Tue Jul 26 12:15:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 17:15:11 -0000 Subject: [llvm-commits] [llvm] r136098 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s Message-ID: <20110726171511.3B3352A6C12D@llvm.org> Author: grosbach Date: Tue Jul 26 12:15:11 2011 New Revision: 136098 URL: http://llvm.org/viewvc/llvm-project?rev=136098&view=rev Log: ARM assembly parsing and encoding for SWP[B] instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=136098&r1=136097&r2=136098&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jul 26 12:15:11 2011 @@ -442,14 +442,14 @@ let Inst{3-0} = Rt; } class AIswp pattern> - : AI { + : AI { bits<4> Rt; bits<4> Rt2; - bits<4> Rn; + bits<4> addr; let Inst{27-23} = 0b00010; let Inst{22} = b; let Inst{21-20} = 0b00; - let Inst{19-16} = Rn; + let Inst{19-16} = addr; let Inst{15-12} = Rt; let Inst{11-4} = 0b00001001; let Inst{3-0} = Rt2; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136098&r1=136097&r2=136098&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 12:15:11 2011 @@ -3659,10 +3659,10 @@ let Inst{31-0} = 0b11110101011111111111000000011111; } -// SWP/SWPB are deprecated in V6/V7 and for disassembly only. +// SWP/SWPB are deprecated in V6/V7. let mayLoad = 1, mayStore = 1 in { -def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp", []>; -def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", []>; +def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swp", []>; +def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swpb", []>; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136098&r1=136097&r2=136098&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 26 12:15:11 2011 @@ -1763,3 +1763,15 @@ @ CHECK: svc #16 @ encoding: [0x10,0x00,0x00,0xef] @ CHECK: svc #0 @ encoding: [0x00,0x00,0x00,0xef] @ CHECK: svc #16777215 @ encoding: [0xff,0xff,0xff,0xef] + + + at ------------------------------------------------------------------------------ +@ SWP/SWPB + at ------------------------------------------------------------------------------ + swp r1, r2, [r3] + swp r4, r4, [r6] + swpb r5, r1, [r9] + +@ CHECK: swp r1, r2, [r3] @ encoding: [0x92,0x10,0x03,0xe1] +@ CHECK: swp r4, r4, [r6] @ encoding: [0x94,0x40,0x06,0xe1] +@ CHECK: swpb r5, r1, [r9] @ encoding: [0x91,0x50,0x49,0xe1] From baldrick at free.fr Tue Jul 26 12:19:30 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 26 Jul 2011 17:19:30 -0000 Subject: [llvm-commits] [llvm] r136099 - /llvm/trunk/include/llvm/ADT/SCCIterator.h Message-ID: <20110726171930.F37912A6C12C@llvm.org> Author: baldrick Date: Tue Jul 26 12:19:30 2011 New Revision: 136099 URL: http://llvm.org/viewvc/llvm-project?rev=136099&view=rev Log: Strip trailing whitespace. Modified: llvm/trunk/include/llvm/ADT/SCCIterator.h Modified: llvm/trunk/include/llvm/ADT/SCCIterator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SCCIterator.h?rev=136099&r1=136098&r2=136099&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SCCIterator.h (original) +++ llvm/trunk/include/llvm/ADT/SCCIterator.h Tue Jul 26 12:19:30 2011 @@ -87,7 +87,7 @@ DFSVisitOne(childN); continue; } - + unsigned childNum = nodeVisitNumbers[childN]; if (MinVisitNumStack.back() > childNum) MinVisitNumStack.back() = childNum; @@ -114,7 +114,7 @@ if (minVisitNum != nodeVisitNumbers[visitingN]) continue; - + // A full SCC is on the SCCNodeStack! It includes all nodes below // visitingN on the stack. Copy those nodes to CurrentSCC, // reset their minVisit values, and return (this suspends @@ -183,7 +183,7 @@ return true; return false; } - + /// ReplaceNode - This informs the scc_iterator that the specified Old node /// has been deleted, and New is to be used in its place. void ReplaceNode(NodeType *Old, NodeType *New) { From atrick at apple.com Tue Jul 26 12:19:55 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 26 Jul 2011 17:19:55 -0000 Subject: [llvm-commits] [llvm] r136100 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp Message-ID: <20110726171955.423942A6C12C@llvm.org> Author: atrick Date: Tue Jul 26 12:19:55 2011 New Revision: 136100 URL: http://llvm.org/viewvc/llvm-project?rev=136100&view=rev Log: SCEV: Added a data structure for storing not-taken info per loop exit. Added an interfaces for querying either the loop's exact/max backedge taken count or a specific loop exit's not-taken count. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=136100&r1=136099&r2=136100&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jul 26 12:19:55 2011 @@ -241,31 +241,93 @@ /// ValueExprMapType ValueExprMap; + /// ExitLimit - Information about the number of loop iterations for + /// which a loop exit's branch condition evaluates to the not-taken path. + /// This is a temporary pair of exact and max expressions that are + /// eventually summarized in ExitNotTakenInfo and BackedgeTakenInfo. + struct ExitLimit { + const SCEV *Exact; + const SCEV *Max; + + /*implicit*/ ExitLimit(const SCEV *E) : Exact(E), Max(E) {} + + ExitLimit(const SCEV *E, const SCEV *M) : Exact(E), Max(M) {} + + /// hasAnyInfo - Test whether this ExitLimit contains any computed + /// information, or whether it's all SCEVCouldNotCompute values. + bool hasAnyInfo() const { + return !isa(Exact) || + !isa(Max); + } + }; + + /// ExitNotTakenInfo - Information about the number of times a particular + /// loop exit may be reached before exiting the loop. + struct ExitNotTakenInfo { + BasicBlock *ExitBlock; + const SCEV *ExactNotTaken; + PointerIntPair NextExit; + + ExitNotTakenInfo() : ExitBlock(0), ExactNotTaken(0) {} + + /// isCompleteList - Return true if all loop exits are computable. + bool isCompleteList() const { + return NextExit.getInt() == 0; + } + + void setIncomplete() { NextExit.setInt(1); } + + /// getNextExit - Return a pointer to the next exit's not-taken info. + ExitNotTakenInfo *getNextExit() const { + return NextExit.getPointer(); + } + + void setNextExit(ExitNotTakenInfo *ENT) { NextExit.setPointer(ENT); } + }; + /// BackedgeTakenInfo - Information about the backedge-taken count /// of a loop. This currently includes an exact count and a maximum count. /// - struct BackedgeTakenInfo { - /// Exact - An expression indicating the exact backedge-taken count of - /// the loop if it is known, or a SCEVCouldNotCompute otherwise. - const SCEV *Exact; + class BackedgeTakenInfo { + /// ExitNotTaken - A list of computable exits and their not-taken counts. + /// Loops almost never have more than one computable exit. + ExitNotTakenInfo ExitNotTaken; /// Max - An expression indicating the least maximum backedge-taken /// count of the loop that is known, or a SCEVCouldNotCompute. const SCEV *Max; - /*implicit*/ BackedgeTakenInfo(const SCEV *exact) : - Exact(exact), Max(exact) {} + public: + BackedgeTakenInfo() : Max(0) {} - BackedgeTakenInfo(const SCEV *exact, const SCEV *max) : - Exact(exact), Max(max) {} + /// Initialize BackedgeTakenInfo from a list of exact exit counts. + BackedgeTakenInfo( + SmallVectorImpl< std::pair > &ExitCounts, + bool Complete, const SCEV *MaxCount); /// hasAnyInfo - Test whether this BackedgeTakenInfo contains any /// computed information, or whether it's all SCEVCouldNotCompute /// values. bool hasAnyInfo() const { - return !isa(Exact) || - !isa(Max); + return ExitNotTaken.ExitBlock || !isa(Max); } + + /// getExact - Return an expression indicating the exact backedge-taken + /// count of the loop if it is known, or SCEVCouldNotCompute + /// otherwise. This is the number of times the loop header can be + /// guaranteed to execute, minus one. + const SCEV *getExact(ScalarEvolution *SE) const; + + /// getExact - Return the number of times this loop exit may fall through + /// to the back edge. The loop is guaranteed not to exit via this block + /// before this number of iterations, but may exit via another block. + const SCEV *getExact(BasicBlock *ExitBlock, ScalarEvolution *SE) const; + + /// getMax - Get the max backedge taken count for the loop. + const SCEV *getMax(ScalarEvolution *SE) const; + + /// clear - Invalidate this result and free associated memory. + void clear(); }; /// BackedgeTakenCounts - Cache the backedge-taken count of the loops for @@ -365,64 +427,59 @@ /// loop will iterate. BackedgeTakenInfo ComputeBackedgeTakenCount(const Loop *L); - /// ComputeBackedgeTakenCountFromExit - Compute the number of times the - /// backedge of the specified loop will execute if it exits via the - /// specified block. - BackedgeTakenInfo ComputeBackedgeTakenCountFromExit(const Loop *L, - BasicBlock *ExitingBlock); - - /// ComputeBackedgeTakenCountFromExitCond - Compute the number of times the - /// backedge of the specified loop will execute if its exit condition - /// were a conditional branch of ExitCond, TBB, and FBB. - BackedgeTakenInfo - ComputeBackedgeTakenCountFromExitCond(const Loop *L, - Value *ExitCond, - BasicBlock *TBB, - BasicBlock *FBB); - - /// ComputeBackedgeTakenCountFromExitCondICmp - Compute the number of - /// times the backedge of the specified loop will execute if its exit - /// condition were a conditional branch of the ICmpInst ExitCond, TBB, - /// and FBB. - BackedgeTakenInfo - ComputeBackedgeTakenCountFromExitCondICmp(const Loop *L, - ICmpInst *ExitCond, - BasicBlock *TBB, - BasicBlock *FBB); + /// ComputeExitLimit - Compute the number of times the backedge of the + /// specified loop will execute if it exits via the specified block. + ExitLimit ComputeExitLimit(const Loop *L, BasicBlock *ExitingBlock); + + /// ComputeExitLimitFromCond - Compute the number of times the backedge of + /// the specified loop will execute if its exit condition were a conditional + /// branch of ExitCond, TBB, and FBB. + ExitLimit ComputeExitLimitFromCond(const Loop *L, + Value *ExitCond, + BasicBlock *TBB, + BasicBlock *FBB); + + /// ComputeExitLimitFromICmp - Compute the number of times the backedge of + /// the specified loop will execute if its exit condition were a conditional + /// branch of the ICmpInst ExitCond, TBB, and FBB. + ExitLimit ComputeExitLimitFromICmp(const Loop *L, + ICmpInst *ExitCond, + BasicBlock *TBB, + BasicBlock *FBB); - /// ComputeLoadConstantCompareBackedgeTakenCount - Given an exit condition + /// ComputeLoadConstantCompareExitLimit - Given an exit condition /// of 'icmp op load X, cst', try to see if we can compute the /// backedge-taken count. - BackedgeTakenInfo - ComputeLoadConstantCompareBackedgeTakenCount(LoadInst *LI, - Constant *RHS, - const Loop *L, - ICmpInst::Predicate p); + ExitLimit ComputeLoadConstantCompareExitLimit(LoadInst *LI, + Constant *RHS, + const Loop *L, + ICmpInst::Predicate p); - /// ComputeBackedgeTakenCountExhaustively - If the loop is known to execute - /// a constant number of times (the condition evolves only from constants), + /// ComputeExitCountExhaustively - If the loop is known to execute a + /// constant number of times (the condition evolves only from constants), /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot - /// evaluate the backedge-taken count of the loop, return CouldNotCompute. - const SCEV *ComputeBackedgeTakenCountExhaustively(const Loop *L, - Value *Cond, - bool ExitWhen); + /// evaluate the exit count of the loop, return CouldNotCompute. + const SCEV *ComputeExitCountExhaustively(const Loop *L, + Value *Cond, + bool ExitWhen); - /// HowFarToZero - Return the number of times a backedge comparing the - /// specified value to zero will execute. If not computable, return + /// HowFarToZero - Return the number of times an exit condition comparing + /// the specified value to zero will execute. If not computable, return /// CouldNotCompute. - BackedgeTakenInfo HowFarToZero(const SCEV *V, const Loop *L); + ExitLimit HowFarToZero(const SCEV *V, const Loop *L); - /// HowFarToNonZero - Return the number of times a backedge checking the - /// specified value for nonzero will execute. If not computable, return + /// HowFarToNonZero - Return the number of times an exit condition checking + /// the specified value for nonzero will execute. If not computable, return /// CouldNotCompute. - BackedgeTakenInfo HowFarToNonZero(const SCEV *V, const Loop *L); + ExitLimit HowFarToNonZero(const SCEV *V, const Loop *L); - /// HowManyLessThans - Return the number of times a backedge containing the - /// specified less-than comparison will execute. If not computable, return - /// CouldNotCompute. isSigned specifies whether the less-than is signed. - BackedgeTakenInfo HowManyLessThans(const SCEV *LHS, const SCEV *RHS, - const Loop *L, bool isSigned); + /// HowManyLessThans - Return the number of times an exit condition + /// containing the specified less-than comparison will execute. If not + /// computable, return CouldNotCompute. isSigned specifies whether the + /// less-than is signed. + ExitLimit HowManyLessThans(const SCEV *LHS, const SCEV *RHS, + const Loop *L, bool isSigned); /// getPredecessorWithUniqueSuccessorForBB - Return a predecessor of BB /// (which may not be an immediate predecessor) which has exactly one @@ -653,6 +710,11 @@ bool isLoopBackedgeGuardedByCond(const Loop *L, ICmpInst::Predicate Pred, const SCEV *LHS, const SCEV *RHS); + // getExitCount - Get the expression for the number of loop iterations for + // which this loop is guaranteed not to exit via ExitBlock. Otherwise return + // SCEVCouldNotCompute. + const SCEV *getExitCount(Loop *L, BasicBlock *ExitBlock); + /// getBackedgeTakenCount - If the specified loop has a predictable /// backedge-taken count, return it, otherwise return a SCEVCouldNotCompute /// object. The backedge-taken count is the number of times the loop header Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=136100&r1=136099&r2=136100&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jul 26 12:19:55 2011 @@ -3813,6 +3813,13 @@ // Iteration Count Computation Code // +// getExitCount - Get the expression for the number of loop iterations for which +// this loop is guaranteed not to exit via ExitBlock. Otherwise return +// SCEVCouldNotCompute. +const SCEV *ScalarEvolution::getExitCount(Loop *L, BasicBlock *ExitBlock) { + return getBackedgeTakenInfo(L).getExact(ExitBlock, this); +} + /// getBackedgeTakenCount - If the specified loop has a predictable /// backedge-taken count, return it, otherwise return a SCEVCouldNotCompute /// object. The backedge-taken count is the number of times the loop header @@ -3825,14 +3832,14 @@ /// hasLoopInvariantBackedgeTakenCount). /// const SCEV *ScalarEvolution::getBackedgeTakenCount(const Loop *L) { - return getBackedgeTakenInfo(L).Exact; + return getBackedgeTakenInfo(L).getExact(this); } /// getMaxBackedgeTakenCount - Similar to getBackedgeTakenCount, except /// return the least SCEV value that is known never to be less than the /// actual backedge taken count. const SCEV *ScalarEvolution::getMaxBackedgeTakenCount(const Loop *L) { - return getBackedgeTakenInfo(L).Max; + return getBackedgeTakenInfo(L).getMax(this); } /// PushLoopPHIs - Push PHI nodes in the header of the given loop @@ -3849,33 +3856,31 @@ const ScalarEvolution::BackedgeTakenInfo & ScalarEvolution::getBackedgeTakenInfo(const Loop *L) { - // Initially insert a CouldNotCompute for this loop. If the insertion + // Initially insert an invalid entry for this loop. If the insertion // succeeds, proceed to actually compute a backedge-taken count and // update the value. The temporary CouldNotCompute value tells SCEV // code elsewhere that it shouldn't attempt to request a new // backedge-taken count, which could result in infinite recursion. std::pair::iterator, bool> Pair = - BackedgeTakenCounts.insert(std::make_pair(L, getCouldNotCompute())); + BackedgeTakenCounts.insert(std::make_pair(L, BackedgeTakenInfo())); if (!Pair.second) return Pair.first->second; - BackedgeTakenInfo Result = getCouldNotCompute(); - BackedgeTakenInfo Computed = ComputeBackedgeTakenCount(L); - if (Computed.Exact != getCouldNotCompute()) { - assert(isLoopInvariant(Computed.Exact, L) && - isLoopInvariant(Computed.Max, L) && + // ComputeBackedgeTakenCount may allocate memory for its result. Inserting it + // into the BackedgeTakenCounts map transfers ownership. Otherwise, the result + // must be cleared in this scope. + BackedgeTakenInfo Result = ComputeBackedgeTakenCount(L); + + if (Result.getExact(this) != getCouldNotCompute()) { + assert(isLoopInvariant(Result.getExact(this), L) && + isLoopInvariant(Result.getMax(this), L) && "Computed backedge-taken count isn't loop invariant for loop!"); ++NumTripCountsComputed; - - // Update the value in the map. - Result = Computed; - } else { - if (Computed.Max != getCouldNotCompute()) - // Update the value in the map. - Result = Computed; - if (isa(L->getHeader()->begin())) - // Only count loops that have phi nodes as not being computable. - ++NumTripCountsNotComputed; + } + else if (Result.getMax(this) == getCouldNotCompute() && + isa(L->getHeader()->begin())) { + // Only count loops that have phi nodes as not being computable. + ++NumTripCountsNotComputed; } // Now that we know more about the trip count for this loop, forget any @@ -3883,7 +3888,7 @@ // conservative estimates made without the benefit of trip count // information. This is similar to the code in forgetLoop, except that // it handles SCEVUnknown PHI nodes specially. - if (Computed.hasAnyInfo()) { + if (Result.hasAnyInfo()) { SmallVector Worklist; PushLoopPHIs(L, Worklist); @@ -3928,7 +3933,12 @@ /// compute a trip count, or if the loop is deleted. void ScalarEvolution::forgetLoop(const Loop *L) { // Drop any stored trip count value. - BackedgeTakenCounts.erase(L); + DenseMap::iterator BTCPos = + BackedgeTakenCounts.find(L); + if (BTCPos != BackedgeTakenCounts.end()) { + BTCPos->second.clear(); + BackedgeTakenCounts.erase(BTCPos); + } // Drop information about expressions based on loop-header PHIs. SmallVector Worklist; @@ -3984,6 +3994,84 @@ } } +/// getExact - Get the exact loop backedge taken count considering all loop +/// exits. If all exits are computable, this is the minimum computed count. +const SCEV * +ScalarEvolution::BackedgeTakenInfo::getExact(ScalarEvolution *SE) const { + // If any exits were not computable, the loop is not computable. + if (!ExitNotTaken.isCompleteList()) return SE->getCouldNotCompute(); + + // We need at least one computable exit. + if (!ExitNotTaken.ExitBlock) return SE->getCouldNotCompute(); + assert(ExitNotTaken.ExactNotTaken && "uninitialized not-taken info"); + + const SCEV *BECount = 0; + for (const ExitNotTakenInfo *ENT = &ExitNotTaken; + ENT != 0; ENT = ENT->getNextExit()) { + + assert(ENT->ExactNotTaken != SE->getCouldNotCompute() && "bad exit SCEV"); + + if (!BECount) + BECount = ENT->ExactNotTaken; + else + BECount = SE->getUMinFromMismatchedTypes(BECount, ENT->ExactNotTaken); + } + return BECount; +} + +/// getExact - Get the exact not taken count for this loop exit. +const SCEV * +ScalarEvolution::BackedgeTakenInfo::getExact(BasicBlock *ExitBlock, + ScalarEvolution *SE) const { + for (const ExitNotTakenInfo *ENT = &ExitNotTaken; + ENT != 0; ENT = ENT->getNextExit()) { + + if (ENT->ExitBlock == ExitBlock) + return ENT->ExactNotTaken; + } + return SE->getCouldNotCompute(); +} + +/// getMax - Get the max backedge taken count for the loop. +const SCEV * +ScalarEvolution::BackedgeTakenInfo::getMax(ScalarEvolution *SE) const { + return Max ? Max : SE->getCouldNotCompute(); +} + +/// Allocate memory for BackedgeTakenInfo and copy the not-taken count of each +/// computable exit into a persistent ExitNotTakenInfo array. +ScalarEvolution::BackedgeTakenInfo::BackedgeTakenInfo( + SmallVectorImpl< std::pair > &ExitCounts, + bool Complete, const SCEV *MaxCount) : Max(MaxCount) { + + if (!Complete) + ExitNotTaken.setIncomplete(); + + unsigned NumExits = ExitCounts.size(); + if (NumExits == 0) return; + + ExitNotTaken.ExitBlock = ExitCounts[0].first; + ExitNotTaken.ExactNotTaken = ExitCounts[0].second; + if (NumExits == 1) return; + + // Handle the rare case of multiple computable exits. + ExitNotTakenInfo *ENT = new ExitNotTakenInfo[NumExits-1]; + + ExitNotTakenInfo *PrevENT = &ExitNotTaken; + for (unsigned i = 1; i < NumExits; ++i, PrevENT = ENT, ++ENT) { + PrevENT->setNextExit(ENT); + ENT->ExitBlock = ExitCounts[i].first; + ENT->ExactNotTaken = ExitCounts[i].second; + } +} + +/// clear - Invalidate this result and free the ExitNotTakenInfo array. +void ScalarEvolution::BackedgeTakenInfo::clear() { + ExitNotTaken.ExitBlock = 0; + ExitNotTaken.ExactNotTaken = 0; + delete[] ExitNotTaken.getNextExit(); +} + /// ComputeBackedgeTakenCount - Compute the number of times the backedge /// of the specified loop will execute. ScalarEvolution::BackedgeTakenInfo @@ -3992,38 +4080,31 @@ L->getExitingBlocks(ExitingBlocks); // Examine all exits and pick the most conservative values. - const SCEV *BECount = getCouldNotCompute(); const SCEV *MaxBECount = getCouldNotCompute(); - bool CouldNotComputeBECount = false; + bool CouldComputeBECount = true; + SmallVector, 4> ExitCounts; for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) { - BackedgeTakenInfo NewBTI = - ComputeBackedgeTakenCountFromExit(L, ExitingBlocks[i]); - - if (NewBTI.Exact == getCouldNotCompute()) { + ExitLimit EL = ComputeExitLimit(L, ExitingBlocks[i]); + if (EL.Exact == getCouldNotCompute()) // We couldn't compute an exact value for this exit, so // we won't be able to compute an exact value for the loop. - CouldNotComputeBECount = true; - BECount = getCouldNotCompute(); - } else if (!CouldNotComputeBECount) { - if (BECount == getCouldNotCompute()) - BECount = NewBTI.Exact; - else - BECount = getUMinFromMismatchedTypes(BECount, NewBTI.Exact); - } + CouldComputeBECount = false; + else + ExitCounts.push_back(std::make_pair(ExitingBlocks[i], EL.Exact)); + if (MaxBECount == getCouldNotCompute()) - MaxBECount = NewBTI.Max; - else if (NewBTI.Max != getCouldNotCompute()) - MaxBECount = getUMinFromMismatchedTypes(MaxBECount, NewBTI.Max); + MaxBECount = EL.Max; + else if (EL.Max != getCouldNotCompute()) + MaxBECount = getUMinFromMismatchedTypes(MaxBECount, EL.Max); } - return BackedgeTakenInfo(BECount, MaxBECount); + return BackedgeTakenInfo(ExitCounts, CouldComputeBECount, MaxBECount); } -/// ComputeBackedgeTakenCountFromExit - Compute the number of times the backedge -/// of the specified loop will execute if it exits via the specified block. -ScalarEvolution::BackedgeTakenInfo -ScalarEvolution::ComputeBackedgeTakenCountFromExit(const Loop *L, - BasicBlock *ExitingBlock) { +/// ComputeExitLimit - Compute the number of times the backedge of the specified +/// loop will execute if it exits via the specified block. +ScalarEvolution::ExitLimit +ScalarEvolution::ComputeExitLimit(const Loop *L, BasicBlock *ExitingBlock) { // Okay, we've chosen an exiting block. See what condition causes us to // exit at this block. @@ -4081,95 +4162,91 @@ } // Proceed to the next level to examine the exit condition expression. - return ComputeBackedgeTakenCountFromExitCond(L, ExitBr->getCondition(), - ExitBr->getSuccessor(0), - ExitBr->getSuccessor(1)); + return ComputeExitLimitFromCond(L, ExitBr->getCondition(), + ExitBr->getSuccessor(0), + ExitBr->getSuccessor(1)); } -/// ComputeBackedgeTakenCountFromExitCond - Compute the number of times the +/// ComputeExitLimitFromCond - Compute the number of times the /// backedge of the specified loop will execute if its exit condition /// were a conditional branch of ExitCond, TBB, and FBB. -ScalarEvolution::BackedgeTakenInfo -ScalarEvolution::ComputeBackedgeTakenCountFromExitCond(const Loop *L, - Value *ExitCond, - BasicBlock *TBB, - BasicBlock *FBB) { +ScalarEvolution::ExitLimit +ScalarEvolution::ComputeExitLimitFromCond(const Loop *L, + Value *ExitCond, + BasicBlock *TBB, + BasicBlock *FBB) { // Check if the controlling expression for this loop is an And or Or. if (BinaryOperator *BO = dyn_cast(ExitCond)) { if (BO->getOpcode() == Instruction::And) { // Recurse on the operands of the and. - BackedgeTakenInfo BTI0 = - ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(0), TBB, FBB); - BackedgeTakenInfo BTI1 = - ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(1), TBB, FBB); + ExitLimit EL0 = ComputeExitLimitFromCond(L, BO->getOperand(0), TBB, FBB); + ExitLimit EL1 = ComputeExitLimitFromCond(L, BO->getOperand(1), TBB, FBB); const SCEV *BECount = getCouldNotCompute(); const SCEV *MaxBECount = getCouldNotCompute(); if (L->contains(TBB)) { // Both conditions must be true for the loop to continue executing. // Choose the less conservative count. - if (BTI0.Exact == getCouldNotCompute() || - BTI1.Exact == getCouldNotCompute()) + if (EL0.Exact == getCouldNotCompute() || + EL1.Exact == getCouldNotCompute()) BECount = getCouldNotCompute(); else - BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); - if (BTI0.Max == getCouldNotCompute()) - MaxBECount = BTI1.Max; - else if (BTI1.Max == getCouldNotCompute()) - MaxBECount = BTI0.Max; + BECount = getUMinFromMismatchedTypes(EL0.Exact, EL1.Exact); + if (EL0.Max == getCouldNotCompute()) + MaxBECount = EL1.Max; + else if (EL1.Max == getCouldNotCompute()) + MaxBECount = EL0.Max; else - MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); + MaxBECount = getUMinFromMismatchedTypes(EL0.Max, EL1.Max); } else { // Both conditions must be true at the same time for the loop to exit. // For now, be conservative. assert(L->contains(FBB) && "Loop block has no successor in loop!"); - if (BTI0.Max == BTI1.Max) - MaxBECount = BTI0.Max; - if (BTI0.Exact == BTI1.Exact) - BECount = BTI0.Exact; + if (EL0.Max == EL1.Max) + MaxBECount = EL0.Max; + if (EL0.Exact == EL1.Exact) + BECount = EL0.Exact; } - return BackedgeTakenInfo(BECount, MaxBECount); + return ExitLimit(BECount, MaxBECount); } if (BO->getOpcode() == Instruction::Or) { // Recurse on the operands of the or. - BackedgeTakenInfo BTI0 = - ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(0), TBB, FBB); - BackedgeTakenInfo BTI1 = - ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(1), TBB, FBB); + ExitLimit EL0 = ComputeExitLimitFromCond(L, BO->getOperand(0), TBB, FBB); + ExitLimit EL1 = ComputeExitLimitFromCond(L, BO->getOperand(1), TBB, FBB); const SCEV *BECount = getCouldNotCompute(); const SCEV *MaxBECount = getCouldNotCompute(); if (L->contains(FBB)) { // Both conditions must be false for the loop to continue executing. // Choose the less conservative count. - if (BTI0.Exact == getCouldNotCompute() || - BTI1.Exact == getCouldNotCompute()) + if (EL0.Exact == getCouldNotCompute() || + EL1.Exact == getCouldNotCompute()) BECount = getCouldNotCompute(); else - BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); - if (BTI0.Max == getCouldNotCompute()) - MaxBECount = BTI1.Max; - else if (BTI1.Max == getCouldNotCompute()) - MaxBECount = BTI0.Max; + BECount = getUMinFromMismatchedTypes(EL0.Exact, EL1.Exact); + if (EL0.Max == getCouldNotCompute()) + MaxBECount = EL1.Max; + else if (EL1.Max == getCouldNotCompute()) + MaxBECount = EL0.Max; else - MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); + MaxBECount = getUMinFromMismatchedTypes(EL0.Max, EL1.Max); } else { // Both conditions must be false at the same time for the loop to exit. // For now, be conservative. assert(L->contains(TBB) && "Loop block has no successor in loop!"); - if (BTI0.Max == BTI1.Max) - MaxBECount = BTI0.Max; - if (BTI0.Exact == BTI1.Exact) - BECount = BTI0.Exact; + if (EL0.Max == EL1.Max) + MaxBECount = EL0.Max; + if (EL0.Exact == EL1.Exact) + BECount = EL0.Exact; } - return BackedgeTakenInfo(BECount, MaxBECount); + return ExitLimit(BECount, MaxBECount); } } // With an icmp, it may be feasible to compute an exact backedge-taken count. // Proceed to the next level to examine the icmp. if (ICmpInst *ExitCondICmp = dyn_cast(ExitCond)) - return ComputeBackedgeTakenCountFromExitCondICmp(L, ExitCondICmp, TBB, FBB); + return ComputeExitLimitFromICmp(L, ExitCondICmp, TBB, FBB); // Check for a constant condition. These are normally stripped out by // SimplifyCFG, but ScalarEvolution may be used by a pass which wishes to @@ -4185,17 +4262,17 @@ } // If it's not an integer or pointer comparison then compute it the hard way. - return ComputeBackedgeTakenCountExhaustively(L, ExitCond, !L->contains(TBB)); + return ComputeExitCountExhaustively(L, ExitCond, !L->contains(TBB)); } -/// ComputeBackedgeTakenCountFromExitCondICmp - Compute the number of times the +/// ComputeExitLimitFromICmp - Compute the number of times the /// backedge of the specified loop will execute if its exit condition /// were a conditional branch of the ICmpInst ExitCond, TBB, and FBB. -ScalarEvolution::BackedgeTakenInfo -ScalarEvolution::ComputeBackedgeTakenCountFromExitCondICmp(const Loop *L, - ICmpInst *ExitCond, - BasicBlock *TBB, - BasicBlock *FBB) { +ScalarEvolution::ExitLimit +ScalarEvolution::ComputeExitLimitFromICmp(const Loop *L, + ICmpInst *ExitCond, + BasicBlock *TBB, + BasicBlock *FBB) { // If the condition was exit on true, convert the condition to exit on false ICmpInst::Predicate Cond; @@ -4207,8 +4284,8 @@ // Handle common loops like: for (X = "string"; *X; ++X) if (LoadInst *LI = dyn_cast(ExitCond->getOperand(0))) if (Constant *RHS = dyn_cast(ExitCond->getOperand(1))) { - BackedgeTakenInfo ItCnt = - ComputeLoadConstantCompareBackedgeTakenCount(LI, RHS, L, Cond); + ExitLimit ItCnt = + ComputeLoadConstantCompareExitLimit(LI, RHS, L, Cond); if (ItCnt.hasAnyInfo()) return ItCnt; } @@ -4247,36 +4324,36 @@ switch (Cond) { case ICmpInst::ICMP_NE: { // while (X != Y) // Convert to: while (X-Y != 0) - BackedgeTakenInfo BTI = HowFarToZero(getMinusSCEV(LHS, RHS), L); - if (BTI.hasAnyInfo()) return BTI; + ExitLimit EL = HowFarToZero(getMinusSCEV(LHS, RHS), L); + if (EL.hasAnyInfo()) return EL; break; } case ICmpInst::ICMP_EQ: { // while (X == Y) // Convert to: while (X-Y == 0) - BackedgeTakenInfo BTI = HowFarToNonZero(getMinusSCEV(LHS, RHS), L); - if (BTI.hasAnyInfo()) return BTI; + ExitLimit EL = HowFarToNonZero(getMinusSCEV(LHS, RHS), L); + if (EL.hasAnyInfo()) return EL; break; } case ICmpInst::ICMP_SLT: { - BackedgeTakenInfo BTI = HowManyLessThans(LHS, RHS, L, true); - if (BTI.hasAnyInfo()) return BTI; + ExitLimit EL = HowManyLessThans(LHS, RHS, L, true); + if (EL.hasAnyInfo()) return EL; break; } case ICmpInst::ICMP_SGT: { - BackedgeTakenInfo BTI = HowManyLessThans(getNotSCEV(LHS), + ExitLimit EL = HowManyLessThans(getNotSCEV(LHS), getNotSCEV(RHS), L, true); - if (BTI.hasAnyInfo()) return BTI; + if (EL.hasAnyInfo()) return EL; break; } case ICmpInst::ICMP_ULT: { - BackedgeTakenInfo BTI = HowManyLessThans(LHS, RHS, L, false); - if (BTI.hasAnyInfo()) return BTI; + ExitLimit EL = HowManyLessThans(LHS, RHS, L, false); + if (EL.hasAnyInfo()) return EL; break; } case ICmpInst::ICMP_UGT: { - BackedgeTakenInfo BTI = HowManyLessThans(getNotSCEV(LHS), + ExitLimit EL = HowManyLessThans(getNotSCEV(LHS), getNotSCEV(RHS), L, false); - if (BTI.hasAnyInfo()) return BTI; + if (EL.hasAnyInfo()) return EL; break; } default: @@ -4290,8 +4367,7 @@ #endif break; } - return - ComputeBackedgeTakenCountExhaustively(L, ExitCond, !L->contains(TBB)); + return ComputeExitCountExhaustively(L, ExitCond, !L->contains(TBB)); } static ConstantInt * @@ -4338,15 +4414,16 @@ return Init; } -/// ComputeLoadConstantCompareBackedgeTakenCount - Given an exit condition of +/// ComputeLoadConstantCompareExitLimit - Given an exit condition of /// 'icmp op load X, cst', try to see if we can compute the backedge /// execution count. -ScalarEvolution::BackedgeTakenInfo -ScalarEvolution::ComputeLoadConstantCompareBackedgeTakenCount( - LoadInst *LI, - Constant *RHS, - const Loop *L, - ICmpInst::Predicate predicate) { +ScalarEvolution::ExitLimit +ScalarEvolution::ComputeLoadConstantCompareExitLimit( + LoadInst *LI, + Constant *RHS, + const Loop *L, + ICmpInst::Predicate predicate) { + if (LI->isVolatile()) return getCouldNotCompute(); // Check to see if the loaded pointer is a getelementptr of a global. @@ -4547,15 +4624,14 @@ } } -/// ComputeBackedgeTakenCountExhaustively - If the loop is known to execute a +/// ComputeExitCountExhaustively - If the loop is known to execute a /// constant number of times (the condition evolves only from constants), /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot /// evaluate the trip count of the loop, return getCouldNotCompute(). -const SCEV * -ScalarEvolution::ComputeBackedgeTakenCountExhaustively(const Loop *L, - Value *Cond, - bool ExitWhen) { +const SCEV * ScalarEvolution::ComputeExitCountExhaustively(const Loop *L, + Value *Cond, + bool ExitWhen) { PHINode *PN = getConstantEvolvingPHI(Cond, L); if (PN == 0) return getCouldNotCompute(); @@ -4949,7 +5025,7 @@ /// now expressed as a single expression, V = x-y. So the exit test is /// effectively V != 0. We know and take advantage of the fact that this /// expression only being used in a comparison by zero context. -ScalarEvolution::BackedgeTakenInfo +ScalarEvolution::ExitLimit ScalarEvolution::HowFarToZero(const SCEV *V, const Loop *L) { // If the value is a constant if (const SCEVConstant *C = dyn_cast(V)) { @@ -5061,7 +5137,7 @@ /// HowFarToNonZero - Return the number of times a backedge checking the /// specified value for nonzero will execute. If not computable, return /// CouldNotCompute -ScalarEvolution::BackedgeTakenInfo +ScalarEvolution::ExitLimit ScalarEvolution::HowFarToNonZero(const SCEV *V, const Loop *L) { // Loops that look like: while (X == 0) are very strange indeed. We don't // handle them yet except for the trivial case. This could be expanded in the @@ -5774,7 +5850,7 @@ /// HowManyLessThans - Return the number of times a backedge containing the /// specified less-than comparison will execute. If not computable, return /// CouldNotCompute. -ScalarEvolution::BackedgeTakenInfo +ScalarEvolution::ExitLimit ScalarEvolution::HowManyLessThans(const SCEV *LHS, const SCEV *RHS, const Loop *L, bool isSigned) { // Only handle: "ADDREC < LoopInvariant". @@ -5881,7 +5957,7 @@ if (isa(MaxBECount)) MaxBECount = BECount; - return BackedgeTakenInfo(BECount, MaxBECount); + return ExitLimit(BECount, MaxBECount); } return getCouldNotCompute(); @@ -6089,6 +6165,15 @@ FirstUnknown = 0; ValueExprMap.clear(); + + // Free any extra memory created for ExitNotTakenInfo in the unlikely event + // that a loop had multiple computable exits. + for (DenseMap::iterator I = + BackedgeTakenCounts.begin(), E = BackedgeTakenCounts.end(); + I != E; ++I) { + I->second.clear(); + } + BackedgeTakenCounts.clear(); ConstantEvolutionLoopExitValue.clear(); ValuesAtScopes.clear(); From grosbach at apple.com Tue Jul 26 12:44:46 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 17:44:46 -0000 Subject: [llvm-commits] [llvm] r136102 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20110726174446.549122A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 12:44:46 2011 New Revision: 136102 URL: http://llvm.org/viewvc/llvm-project?rev=136102&view=rev Log: ARM fix for LDREX source register encoding. rdar://9842203 Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=136102&r1=136101&r2=136102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jul 26 12:44:46 2011 @@ -418,11 +418,11 @@ : I { bits<4> Rt; - bits<4> Rn; + bits<4> addr; let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; let Inst{20} = 1; - let Inst{19-16} = Rn; + let Inst{19-16} = addr; let Inst{15-12} = Rt; let Inst{11-0} = 0b111110011111; } From grosbach at apple.com Tue Jul 26 13:07:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 18:07:21 -0000 Subject: [llvm-commits] [llvm] r136105 - in /llvm/trunk/test/MC/ARM: arm_instructions.s basic-arm-instructions.s Message-ID: <20110726180721.3AA882A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 13:07:21 2011 New Revision: 136105 URL: http://llvm.org/viewvc/llvm-project?rev=136105&view=rev Log: ARM parsing and encoding tests for load/store exclusive instructions. Modified: llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=136105&r1=136104&r2=136105&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jul 26 13:07:21 2011 @@ -86,30 +86,6 @@ @ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] add r1, r2, r3, lsl r4 -@ CHECK: strexb r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1] - strexb r0, r1, [r2] - -@ CHECK: strexh r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1] - strexh r0, r1, [r2] - -@ CHECK: strex r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1] - strex r0, r1, [r2] - -@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1] - strexd r0, r2, r3, [r1] - -@ CHECK: ldrexb r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1] - ldrexb r0, [r0] - -@ CHECK: ldrexh r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1] - ldrexh r0, [r0] - -@ CHECK: ldrex r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1] - ldrex r0, [r0] - -@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1] - ldrexd r0, r1, [r0] - @ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6] ssat16 r0, #7, r0 Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136105&r1=136104&r2=136105&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Jul 26 13:07:21 2011 @@ -622,6 +622,21 @@ @------------------------------------------------------------------------------ @ FIXME: LDR* @------------------------------------------------------------------------------ + + at ------------------------------------------------------------------------------ +@ LDREX/LDREXB/LDREXH/LDREXD + at ------------------------------------------------------------------------------ + ldrexb r3, [r4] + ldrexh r2, [r5] + ldrex r1, [r7] + ldrexd r6, r7, [r8] + +@ CHECK: ldrexb r3, [r4] @ encoding: [0x9f,0x3f,0xd4,0xe1] +@ CHECK: ldrexh r2, [r5] @ encoding: [0x9f,0x2f,0xf5,0xe1] +@ CHECK: ldrex r1, [r7] @ encoding: [0x9f,0x1f,0x97,0xe1] +@ CHECK: ldrexd r6, r7, [r8] @ encoding: [0x9f,0x6f,0xb8,0xe1] + + @------------------------------------------------------------------------------ @ FIXME: LSL @------------------------------------------------------------------------------ @@ -1697,6 +1712,18 @@ @------------------------------------------------------------------------------ @ FIXME:STR* @------------------------------------------------------------------------------ + at ------------------------------------------------------------------------------ +@ STREX/STREXB/STREXH/STREXD + at ------------------------------------------------------------------------------ + strexb r1, r3, [r4] + strexh r4, r2, [r5] + strex r2, r1, [r7] + strexd r6, r2, r3, [r8] + +@ CHECK: strexb r1, r3, [r4] @ encoding: [0x93,0x1f,0xc4,0xe1] +@ CHECK: strexh r4, r2, [r5] @ encoding: [0x92,0x4f,0xe5,0xe1] +@ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1] +@ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1] @------------------------------------------------------------------------------ From dpatel at apple.com Tue Jul 26 13:09:53 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 26 Jul 2011 18:09:53 -0000 Subject: [llvm-commits] [llvm] r136106 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110726180953.660842A6C12C@llvm.org> Author: dpatel Date: Tue Jul 26 13:09:53 2011 New Revision: 136106 URL: http://llvm.org/viewvc/llvm-project?rev=136106&view=rev Log: While extracting lexical scopes from machine instruction stream, work on one machine basic block at a time. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=136106&r1=136105&r2=136106&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jul 26 13:09:53 2011 @@ -1702,11 +1702,11 @@ // Scan each instruction and create scopes. First build working set of scopes. SmallVector MIRanges; DenseMap MI2ScopeMap; - DebugLoc PrevDL; - const MachineInstr *RangeBeginMI = NULL; - const MachineInstr *PrevMI = NULL; for (MachineFunction::const_iterator I = Asm->MF->begin(), E = Asm->MF->end(); I != E; ++I) { + const MachineInstr *RangeBeginMI = NULL; + const MachineInstr *PrevMI = NULL; + DebugLoc PrevDL; for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end(); II != IE; ++II) { const MachineInstr *MInsn = II; @@ -1749,13 +1749,13 @@ PrevMI = MInsn; PrevDL = MIDL; } - } - // Create last instruction range. - if (RangeBeginMI && PrevMI && !PrevDL.isUnknown()) { - DbgRange R(RangeBeginMI, PrevMI); - MIRanges.push_back(R); - MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevDL); + // Create last instruction range. + if (RangeBeginMI && PrevMI && !PrevDL.isUnknown()) { + DbgRange R(RangeBeginMI, PrevMI); + MIRanges.push_back(R); + MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevDL); + } } if (!CurrentFnDbgScope) From bruno.cardoso at gmail.com Tue Jul 26 13:22:27 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 18:22:27 -0000 Subject: [llvm-commits] [llvm] r136108 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110726182227.DF0FF2A6C12C@llvm.org> Author: bruno Date: Tue Jul 26 13:22:27 2011 New Revision: 136108 URL: http://llvm.org/viewvc/llvm-project?rev=136108&view=rev Log: Cleanup old matching for PUNPCK* variants Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136108&r1=136107&r2=136108&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 26 13:22:27 2011 @@ -2646,71 +2646,69 @@ let ExeDomain = SSEPackedInt in { multiclass sse2_unpack opc, string OpcodeStr, ValueType vt, - PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> { + SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> { def rr : PDI; + [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>; def rm : PDI; } let Predicates = [HasAVX] in { - defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8, - 0>, VEX_4V; - defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16, - 0>, VEX_4V; - defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32, - 0>, VEX_4V; + defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw, + bc_v16i8, 0>, VEX_4V; + defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd, + bc_v8i16, 0>, VEX_4V; + defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq, + bc_v4i32, 0>, VEX_4V; /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen /// knew to collapse (bitconvert VT to VT) into its operand. def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, - (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), - "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set VR128:$dst, - (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V; + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1, + VR128:$src2)))]>, VEX_4V; def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, - (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), - "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set VR128:$dst, - (v2i64 (unpckl VR128:$src1, - (memopv2i64 addr:$src2))))]>, VEX_4V; - - defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8, - 0>, VEX_4V; - defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16, - 0>, VEX_4V; - defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32, - 0>, VEX_4V; + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), + "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1, + (memopv2i64 addr:$src2))))]>, VEX_4V; + + defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw, + bc_v16i8, 0>, VEX_4V; + defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd, + bc_v8i16, 0>, VEX_4V; + defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq, + bc_v4i32, 0>, VEX_4V; /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen /// knew to collapse (bitconvert VT to VT) into its operand. def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, - (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), - "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set VR128:$dst, - (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V; + (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), + "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1, + VR128:$src2)))]>, VEX_4V; def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, - (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), - "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set VR128:$dst, - (v2i64 (unpckh VR128:$src1, - (memopv2i64 addr:$src2))))]>, VEX_4V; + (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), + "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1, + (memopv2i64 addr:$src2))))]>, VEX_4V; } let Constraints = "$src1 = $dst" in { - defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>; - defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>; - defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>; + defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>; + defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>; + defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>; /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen /// knew to collapse (bitconvert VT to VT) into its operand. @@ -2718,17 +2716,17 @@ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpcklqdq\t{$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>; + (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>; def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpcklqdq\t{$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (unpckl VR128:$src1, + (v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))))]>; - defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>; - defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>; - defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>; + defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>; + defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>; + defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>; /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen /// knew to collapse (bitconvert VT to VT) into its operand. @@ -2736,12 +2734,12 @@ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpckhqdq\t{$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>; + (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>; def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), "punpckhqdq\t{$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (unpckh VR128:$src1, + (v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))))]>; } From bruno.cardoso at gmail.com Tue Jul 26 13:22:39 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 18:22:39 -0000 Subject: [llvm-commits] [llvm] r136109 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110726182239.CD5672A6C12C@llvm.org> Author: bruno Date: Tue Jul 26 13:22:39 2011 New Revision: 136109 URL: http://llvm.org/viewvc/llvm-project?rev=136109&view=rev Log: Remove now unused patterns. 0 insertions(+), 98 deletions(-) Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136109&r1=136108&r2=136109&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 26 13:22:39 2011 @@ -3748,12 +3748,8 @@ let AddedComplexity = 10 in { def : Pat<(splat_lo (v2f64 VR128:$src), (undef)), (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; -def : Pat<(unpckh (v2f64 VR128:$src), (undef)), - (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(splat_lo (v2i64 VR128:$src), (undef)), (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; -def : Pat<(unpckh (v2i64 VR128:$src), (undef)), - (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; } // Special unary SHUFPSrri case. @@ -3794,46 +3790,6 @@ (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE2]>; -// vector_shuffle v1, , <0, 0, 1, 1, ...> -let AddedComplexity = 15 in { -def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))), - (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[OptForSpeed, HasSSE2]>; -def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))), - (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[OptForSpeed, HasSSE2]>; -} -let AddedComplexity = 10 in { -def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))), - (UNPCKLPSrr VR128:$src, VR128:$src)>; -def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))), - (PUNPCKLBWrr VR128:$src, VR128:$src)>; -def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))), - (PUNPCKLWDrr VR128:$src, VR128:$src)>; -def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))), - (PUNPCKLDQrr VR128:$src, VR128:$src)>; -} - -// vector_shuffle v1, , <2, 2, 3, 3, ...> -let AddedComplexity = 15 in { -def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))), - (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[OptForSpeed, HasSSE2]>; -def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))), - (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[OptForSpeed, HasSSE2]>; -} -let AddedComplexity = 10 in { -def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))), - (UNPCKHPSrr VR128:$src, VR128:$src)>; -def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))), - (PUNPCKHBWrr VR128:$src, VR128:$src)>; -def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))), - (PUNPCKHWDrr VR128:$src, VR128:$src)>; -def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))), - (PUNPCKHDQrr VR128:$src, VR128:$src)>; -} - let AddedComplexity = 20 in { // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)), @@ -5747,60 +5703,6 @@ def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), (UNPCKHPDrr VR128:$src1, VR128:$src2)>; -// Shuffle with PUNPCKLBW -def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, - (bc_v16i8 (memopv2i64 addr:$src2)))), - (PUNPCKLBWrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)), - (PUNPCKLBWrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKLWD -def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, - (bc_v8i16 (memopv2i64 addr:$src2)))), - (PUNPCKLWDrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)), - (PUNPCKLWDrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKLDQ -def : Pat<(v4i32 (X86Punpckldq VR128:$src1, - (bc_v4i32 (memopv2i64 addr:$src2)))), - (PUNPCKLDQrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)), - (PUNPCKLDQrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKLQDQ -def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))), - (PUNPCKLQDQrm VR128:$src1, addr:$src2)>; -def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)), - (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKHBW -def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, - (bc_v16i8 (memopv2i64 addr:$src2)))), - (PUNPCKHBWrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)), - (PUNPCKHBWrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKHWD -def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, - (bc_v8i16 (memopv2i64 addr:$src2)))), - (PUNPCKHWDrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)), - (PUNPCKHWDrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKHDQ -def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, - (bc_v4i32 (memopv2i64 addr:$src2)))), - (PUNPCKHDQrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)), - (PUNPCKHDQrr VR128:$src1, VR128:$src2)>; - -// Shuffle with PUNPCKHQDQ -def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))), - (PUNPCKHQDQrm VR128:$src1, addr:$src2)>; -def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)), - (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>; - // Shuffle with MOVLHPS def : Pat<(X86Movlhps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), From grosbach at apple.com Tue Jul 26 13:25:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 18:25:40 -0000 Subject: [llvm-commits] [llvm] r136110 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/diagnostics.s Message-ID: <20110726182540.32B282A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 13:25:39 2011 New Revision: 136110 URL: http://llvm.org/viewvc/llvm-project?rev=136110&view=rev Log: ARM diagnostics for ldrexd/stredx out of order paired register operands. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136110&r1=136109&r2=136110&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 26 13:25:39 2011 @@ -135,6 +135,10 @@ bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); + + bool validateInstruction(MCInst &Inst, + const SmallVectorImpl &Ops); + public: ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { @@ -147,7 +151,7 @@ // Implementation of the MCTargetAsmParser interface: bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); bool ParseInstruction(StringRef Name, SMLoc NameLoc, - SmallVectorImpl &Operands); + SmallVectorImpl &Operands); bool ParseDirective(AsmToken DirectiveID); bool MatchAndEmitInstruction(SMLoc IDLoc, @@ -2499,6 +2503,35 @@ return false; } +// Validate context-sensitive operand constraints. +// FIXME: We would really like to be able to tablegen'erate this. +bool ARMAsmParser:: +validateInstruction(MCInst &Inst, + const SmallVectorImpl &Operands) { + switch (Inst.getOpcode()) { + case ARM::LDREXD: { + // Rt2 must be Rt + 1. + unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); + unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); + if (Rt2 != Rt + 1) + return Error(Operands[3]->getStartLoc(), + "destination operands must be sequential"); + return false; + } + case ARM::STREXD: { + // Rt2 must be Rt + 1. + unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); + unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); + if (Rt2 != Rt + 1) + return Error(Operands[4]->getStartLoc(), + "source operands must be sequential"); + return false; + } + } + + return false; +} + bool ARMAsmParser:: MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, @@ -2509,6 +2542,11 @@ MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); switch (MatchResult) { case Match_Success: + // Context sensitive operand constraints aren't handled by the matcher, + // so check them here. + if (validateInstruction(Inst, Operands)) + return true; + Out.EmitInstruction(Inst); return false; case Match_MissingFeature: Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136110&r1=136109&r2=136110&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Tue Jul 26 13:25:39 2011 @@ -226,3 +226,15 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: svc #0x1000000 @ CHECK-ERRORS: ^ + + + @ Out of order Rt/Rt2 operands for ldrexd/strexd + ldrexd r4, r3, [r8] + strexd r6, r5, r3, [r8] + +@ CHECK-ERRORS: error: destination operands must be sequential +@ CHECK-ERRORS: ldrexd r4, r3, [r8] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source operands must be sequential +@ CHECK-ERRORS: strexd r6, r5, r3, [r8] +@ CHECK-ERRORS: ^ From isanbard at gmail.com Tue Jul 26 13:31:42 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 26 Jul 2011 18:31:42 -0000 Subject: [llvm-commits] [llvm] r136111 - /llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Message-ID: <20110726183142.103762A6C12C@llvm.org> Author: void Date: Tue Jul 26 13:31:41 2011 New Revision: 136111 URL: http://llvm.org/viewvc/llvm-project?rev=136111&view=rev Log: Use the correct for for the version. It's little endian and my brain is obviously big endian. :-) PR10502 Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=136111&r1=136110&r2=136111&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Tue Jul 26 13:31:41 2011 @@ -377,7 +377,7 @@ if (!Use402Format) out->write("oncg*404MVLL", 12); else - out->write("oncg*402MVLL", 12); + out->write("oncg*204MVLL", 12); } for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(), From atrick at apple.com Tue Jul 26 13:31:49 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 26 Jul 2011 18:31:49 -0000 Subject: [llvm-commits] [llvm] r136112 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20110726183149.957282A6C12C@llvm.org> Author: atrick Date: Tue Jul 26 13:31:49 2011 New Revision: 136112 URL: http://llvm.org/viewvc/llvm-project?rev=136112&view=rev Log: Updating stale documentation on regalloc modes. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=136112&r1=136111&r2=136112&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Tue Jul 26 13:31:49 2011 @@ -1768,22 +1768,28 @@ different register allocators:

        -
      • Linear Scan — The default allocator. This is the - well-know linear scan register allocator. Whereas the - Simple and Local algorithms use a direct mapping - implementation technique, the Linear Scan implementation - uses a spiller in order to place load and stores.
        • -
      • Fast — This register allocator is the default for debug builds. It allocates registers on a basic block level, attempting to keep values in registers and reusing registers as appropriate.
        • +
      • Basic — This is an incremental approach to register + allocation. Live ranges are assigned to registers one at a time in + an order that is driven by heuristics. Since code can be rewritten + on-the-fly during allocation, this framework allows interesting + allocators to be developed as extensions. It is not itself a + production register allocator but is a potentially useful + stand-alone mode for triaging bugs and as a performance baseline. + +
      • Greedy — The default allocator. This is a + highly tuned implementation of the Basic allocator that + incorporates global live range splitting. This allocator works hard + to minimize the cost of spill code. +
      • PBQP — A Partitioned Boolean Quadratic Programming (PBQP) based register allocator. This allocator works by constructing a PBQP problem representing the register allocation problem under consideration, solving this using a PBQP solver, and mapping the solution back to a register assignment.
        • -

      The type of register allocator used in llc can be chosen with the From evan.cheng at apple.com Tue Jul 26 14:02:16 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 19:02:16 -0000 Subject: [llvm-commits] [llvm] r136115 - /llvm/trunk/tools/llvm-mc/llvm-mc.cpp Message-ID: <20110726190216.D67FE2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 26 14:02:16 2011 New Revision: 136115 URL: http://llvm.org/viewvc/llvm-project?rev=136115&view=rev Log: Fix llvm-mc target detection code to match llc. Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=136115&r1=136114&r2=136115&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jul 26 14:02:16 2011 @@ -170,21 +170,42 @@ // Figure out the target triple. if (TripleName.empty()) TripleName = sys::getHostTriple(); + Triple TheTriple(Triple::normalize(TripleName)); + + const Target *TheTarget = 0; if (!ArchName.empty()) { - llvm::Triple TT(TripleName); - TT.setArchName(ArchName); - TripleName = TT.str(); - } + for (TargetRegistry::iterator it = TargetRegistry::begin(), + ie = TargetRegistry::end(); it != ie; ++it) { + if (ArchName == it->getName()) { + TheTarget = &*it; + break; + } + } - // Get the target specific parser. - std::string Error; - const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error); - if (TheTarget) - return TheTarget; + if (!TheTarget) { + errs() << ProgName << ": error: invalid target '" << ArchName << "'.\n"; + return 0; + } - errs() << ProgName << ": error: unable to get target for '" << TripleName - << "', see --version and --triple.\n"; - return 0; + // Adjust the triple to match (if known), otherwise stick with the + // module/host triple. + Triple::ArchType Type = Triple::getArchTypeForLLVMName(ArchName); + if (Type != Triple::UnknownArch) + TheTriple.setArch(Type); + } else { + // Get the target specific parser. + std::string Error; + TheTarget = TargetRegistry::lookupTarget(TheTriple.getTriple(), Error); + if (TheTarget == 0) { + errs() << ProgName << ": error: unable to get target for '" + << TheTriple.getTriple() + << "', see --version and --triple.\n"; + return 0; + } + } + + TripleName = TheTriple.getTriple(); + return TheTarget; } static tool_output_file *GetOutputStream() { From eli.friedman at gmail.com Tue Jul 26 15:24:06 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 26 Jul 2011 20:24:06 -0000 Subject: [llvm-commits] [llvm] r136124 - in /llvm/trunk/include: llvm-c/Core.h llvm/Instruction.def Message-ID: <20110726202406.CA0822A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 15:24:06 2011 New Revision: 136124 URL: http://llvm.org/viewvc/llvm-project?rev=136124&view=rev Log: Fix a couple minor mistakes pointed out by Bill in adding 'fence' instruction. Modified: llvm/trunk/include/llvm-c/Core.h llvm/trunk/include/llvm/Instruction.def Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136124&r1=136123&r2=136124&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Tue Jul 26 15:24:06 2011 @@ -155,35 +155,36 @@ LLVMLoad = 27, LLVMStore = 28, LLVMGetElementPtr = 29, + LLVMFence = 30, /* Cast Operators */ - LLVMTrunc = 30, - LLVMZExt = 31, - LLVMSExt = 32, - LLVMFPToUI = 33, - LLVMFPToSI = 34, - LLVMUIToFP = 35, - LLVMSIToFP = 36, - LLVMFPTrunc = 37, - LLVMFPExt = 38, - LLVMPtrToInt = 39, - LLVMIntToPtr = 40, - LLVMBitCast = 41, + LLVMTrunc = 33, + LLVMZExt = 34, + LLVMSExt = 35, + LLVMFPToUI = 36, + LLVMFPToSI = 37, + LLVMUIToFP = 38, + LLVMSIToFP = 39, + LLVMFPTrunc = 40, + LLVMFPExt = 41, + LLVMPtrToInt = 42, + LLVMIntToPtr = 43, + LLVMBitCast = 44, /* Other Operators */ - LLVMICmp = 42, - LLVMFCmp = 43, - LLVMPHI = 44, - LLVMCall = 45, - LLVMSelect = 46, + LLVMICmp = 45, + LLVMFCmp = 46, + LLVMPHI = 47, + LLVMCall = 48, + LLVMSelect = 49, /* UserOp1 */ /* UserOp2 */ - LLVMVAArg = 49, - LLVMExtractElement = 50, - LLVMInsertElement = 51, - LLVMShuffleVector = 52, - LLVMExtractValue = 53, - LLVMInsertValue = 54 + LLVMVAArg = 52, + LLVMExtractElement = 53, + LLVMInsertElement = 54, + LLVMShuffleVector = 55, + LLVMExtractValue = 56, + LLVMInsertValue = 57 } LLVMOpcode; typedef enum { Modified: llvm/trunk/include/llvm/Instruction.def URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=136124&r1=136123&r2=136124&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instruction.def (original) +++ llvm/trunk/include/llvm/Instruction.def Tue Jul 26 15:24:06 2011 @@ -134,7 +134,7 @@ HANDLE_MEMORY_INST(28, Store , StoreInst ) HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) HANDLE_MEMORY_INST(30, Fence , FenceInst ) - LAST_MEMORY_INST(32) + LAST_MEMORY_INST(30) // Cast operators ... // NOTE: The order matters here because CastInst::isEliminableCastPair From eli.friedman at gmail.com Tue Jul 26 15:38:50 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 26 Jul 2011 20:38:50 -0000 Subject: [llvm-commits] [llvm] r136130 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/X86/split-vector-bitcast.ll Message-ID: <20110726203850.0A4CA2A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 15:38:49 2011 New Revision: 136130 URL: http://llvm.org/viewvc/llvm-project?rev=136130&view=rev Log: Add obvious missing case to switch. PR10497. Added: llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=136130&r1=136129&r2=136130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jul 26 15:38:49 2011 @@ -524,12 +524,11 @@ // Handle some special cases efficiently. switch (getTypeAction(InVT)) { - default: - assert(false && "Unknown type action!"); case TargetLowering::TypeLegal: case TargetLowering::TypePromoteInteger: case TargetLowering::TypeSoftenFloat: case TargetLowering::TypeScalarizeVector: + case TargetLowering::TypeWidenVector: break; case TargetLowering::TypeExpandInteger: case TargetLowering::TypeExpandFloat: Added: llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll?rev=136130&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll (added) +++ llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Tue Jul 26 15:38:49 2011 @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 -mattr=-sse2,+sse | grep addps + +; PR10497 +; (This is primarily checking that this construct doesn't crash.) +define void @a(<2 x float>* %a, <2 x i32>* %b) { + %cc = load <2 x float>* %a + %c = fadd <2 x float> %cc, %cc + %dd = bitcast <2 x float> %c to <2 x i32> + %d = add <2 x i32> %dd, %dd + store <2 x i32> %d, <2 x i32>* %b + ret void +} From eli.friedman at gmail.com Tue Jul 26 15:41:03 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 26 Jul 2011 20:41:03 -0000 Subject: [llvm-commits] [llvm] r136131 - /llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Message-ID: <20110726204103.8091F2A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 15:41:03 2011 New Revision: 136131 URL: http://llvm.org/viewvc/llvm-project?rev=136131&view=rev Log: XFAIL this test while I investigate it; it's failing for an unexpected reason. Modified: llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Modified: llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll?rev=136131&r1=136130&r2=136131&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll (original) +++ llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Tue Jul 26 15:41:03 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=-sse2,+sse | grep addps +; XFAIL: * ; PR10497 ; (This is primarily checking that this construct doesn't crash.) define void @a(<2 x float>* %a, <2 x i32>* %b) { From grosbach at apple.com Tue Jul 26 15:41:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 20:41:24 -0000 Subject: [llvm-commits] [llvm] r136132 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110726204124.360E42A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 15:41:24 2011 New Revision: 136132 URL: http://llvm.org/viewvc/llvm-project?rev=136132&view=rev Log: Fix over-zealous rename from r136095. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136132&r1=136131&r2=136132&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 26 15:41:24 2011 @@ -49,7 +49,7 @@ int tryParseRegister(); bool tryParseRegisterWithWriteBack(SmallVectorImpl &); - int tryparseShiftRegister(SmallVectorImpl &); + int tryParseShiftRegister(SmallVectorImpl &); bool parseRegisterList(SmallVectorImpl &); bool parseMemory(SmallVectorImpl &, ARMII::AddrMode AddrMode); @@ -1250,7 +1250,7 @@ // occurs, return -1. An irrecoverable error is one where tokens have been // consumed in the process of trying to parse the shifter (i.e., when it is // indeed a shifter operand, but malformed). -int ARMAsmParser::tryparseShiftRegister( +int ARMAsmParser::tryParseShiftRegister( SmallVectorImpl &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); @@ -2122,7 +2122,7 @@ case AsmToken::Identifier: { if (!tryParseRegisterWithWriteBack(Operands)) return false; - int Res = tryparseShiftRegister(Operands); + int Res = tryParseShiftRegister(Operands); if (Res == 0) // success return false; else if (Res == -1) // irrecoverable error From isanbard at gmail.com Tue Jul 26 15:42:29 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 26 Jul 2011 20:42:29 -0000 Subject: [llvm-commits] [llvm] r136133 - /llvm/trunk/docs/LangRef.html Message-ID: <20110726204229.5CB392A6C12C@llvm.org> Author: void Date: Tue Jul 26 15:42:28 2011 New Revision: 136133 URL: http://llvm.org/viewvc/llvm-project?rev=136133&view=rev Log: Fix a typo. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=136133&r1=136132&r2=136133&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 26 15:42:28 2011 @@ -4336,7 +4336,7 @@

      Syntax:
      -  <result> = insertvalue <aggregate type> <val>, <ty> <elt>, <idx>{, }*    ; yields <aggregate type>
+  <result> = insertvalue <aggregate type> <val>, <ty> <elt>, <idx>{, <idx>}*    ; yields <aggregate type>
      Overview:
      From grosbach at apple.com Tue Jul 26 15:49:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 20:49:45 -0000 Subject: [llvm-commits] [llvm] r136135 - /llvm/trunk/test/CodeGen/ARM/sxt_rot.ll Message-ID: <20110726204945.2732B2A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 15:49:44 2011 New Revision: 136135 URL: http://llvm.org/viewvc/llvm-project?rev=136135&view=rev Log: FileCheck'ize test. Modified: llvm/trunk/test/CodeGen/ARM/sxt_rot.ll Modified: llvm/trunk/test/CodeGen/ARM/sxt_rot.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sxt_rot.ll?rev=136135&r1=136134&r2=136135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/sxt_rot.ll (original) +++ llvm/trunk/test/CodeGen/ARM/sxt_rot.ll Tue Jul 26 15:49:44 2011 @@ -1,29 +1,30 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | \ -; RUN: grep sxtb | count 2 -; RUN: llc < %s -march=arm -mattr=+v6 | \ -; RUN: grep sxtb | grep ror | count 1 -; RUN: llc < %s -march=arm -mattr=+v6 | \ -; RUN: grep sxtab | count 1 +; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s define i32 @test0(i8 %A) { - %B = sext i8 %A to i32 - ret i32 %B +; CHECK: test0 +; CHECK: sxtb r0, r0 + %B = sext i8 %A to i32 + ret i32 %B } define signext i8 @test1(i32 %A) { - %B = lshr i32 %A, 8 - %C = shl i32 %A, 24 - %D = or i32 %B, %C - %E = trunc i32 %D to i8 - ret i8 %E +; CHECK: test1 +; CHECK: sxtb r0, r0, ror #8 + %B = lshr i32 %A, 8 + %C = shl i32 %A, 24 + %D = or i32 %B, %C + %E = trunc i32 %D to i8 + ret i8 %E } define signext i32 @test2(i32 %A, i32 %X) { - %B = lshr i32 %A, 8 - %C = shl i32 %A, 24 - %D = or i32 %B, %C - %E = trunc i32 %D to i8 - %F = sext i8 %E to i32 - %G = add i32 %F, %X - ret i32 %G +; CHECK: test2 +; CHECK: sxtab r0, r1, r0 + %B = lshr i32 %A, 8 + %C = shl i32 %A, 24 + %D = or i32 %B, %C + %E = trunc i32 %D to i8 + %F = sext i8 %E to i32 + %G = add i32 %F, %X + ret i32 %G } From nicolas.geoffray at lip6.fr Tue Jul 26 15:52:25 2011 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Tue, 26 Jul 2011 20:52:25 -0000 Subject: [llvm-commits] [llvm] r136138 - /llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Message-ID: <20110726205225.C72152A6C12D@llvm.org> Author: geoffray Date: Tue Jul 26 15:52:25 2011 New Revision: 136138 URL: http://llvm.org/viewvc/llvm-project?rev=136138&view=rev Log: Update generated code to use new API of GetElementPtrInst::Create. Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=136138&r1=136137&r2=136138&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jul 26 15:52:25 2011 @@ -1240,8 +1240,7 @@ nl(Out); } Out << "Instruction* " << iName << " = GetElementPtrInst::Create(" - << opNames[0] << ", " << iName << "_indices.begin(), " - << iName << "_indices.end()"; + << opNames[0] << ", " << iName << "_indices"; } Out << ", \""; printEscapedString(gep->getName()); From resistor at mac.com Tue Jul 26 15:54:26 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 26 Jul 2011 20:54:26 -0000 Subject: [llvm-commits] [llvm] r136141 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFrameLowering.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp utils/TableGen/EDEmitter.cpp Message-ID: <20110726205426.AB4B02A6C12C@llvm.org> Author: resistor Date: Tue Jul 26 15:54:26 2011 New Revision: 136141 URL: http://llvm.org/viewvc/llvm-project?rev=136141&view=rev Log: Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jul 26 15:54:26 2011 @@ -994,7 +994,8 @@ i != NumOps; ++i) RegList.push_back(MI->getOperand(i).getReg()); break; - case ARM::STR_PRE: + case ARM::STR_PRE_IMM: + case ARM::STR_PRE_REG: assert(MI->getOperand(2).getReg() == ARM::SP && "Only stack pointer as a source reg is supported"); RegList.push_back(SrcReg); Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Jul 26 15:54:26 2011 @@ -93,7 +93,8 @@ return false; return true; } - if ((MI->getOpcode() == ARM::LDR_POST || + if ((MI->getOpcode() == ARM::LDR_POST_IMM || + MI->getOpcode() == ARM::LDR_POST_REG || MI->getOpcode() == ARM::t2LDR_POST) && isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && MI->getOperand(1).getReg() == ARM::SP) @@ -590,7 +591,7 @@ .addReg(ARM::SP).setMIFlags(MIFlags); // ARM mode needs an extra reg0 here due to addrmode2. Will go away once // that refactoring is complete (eventually). - if (StrOpc == ARM::STR_PRE) { + if (StrOpc == ARM::STR_PRE_REG || StrOpc == ARM::STR_PRE_IMM) { MIB.addReg(0); MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift)); } else @@ -665,7 +666,7 @@ .addReg(ARM::SP); // ARM mode needs an extra reg0 here due to addrmode2. Will go away once // that refactoring is complete (eventually). - if (LdrOpc == ARM::LDR_POST) { + if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { MIB.addReg(0); MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); } else @@ -687,7 +688,7 @@ ARMFunctionInfo *AFI = MF.getInfo(); unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; - unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE; + unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM; unsigned FltOpc = ARM::VSTMDDB_UPD; emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, MachineInstr::FrameSetup); @@ -711,7 +712,7 @@ bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; - unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST; + unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM; unsigned FltOpc = ARM::VLDMDIA_UPD; emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register); emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jul 26 15:54:26 2011 @@ -129,7 +129,9 @@ return true; } - bool SelectAddrMode2Offset(SDNode *Op, SDValue N, + bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, + SDValue &Offset, SDValue &Opc); + bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc); bool SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); @@ -714,7 +716,7 @@ return AM2_SHOP; } -bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N, +bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { unsigned Opcode = Op->getOpcode(); ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) @@ -723,13 +725,8 @@ ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) ? ARM_AM::add : ARM_AM::sub; int Val; - if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. - Offset = CurDAG->getRegister(0, MVT::i32); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, - ARM_AM::no_shift), - MVT::i32); - return true; - } + if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) + return false; Offset = N; ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); @@ -755,6 +752,28 @@ return true; } +bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, + SDValue &Offset, SDValue &Opc) { + unsigned Opcode = Op->getOpcode(); + ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) + ? cast(Op)->getAddressingMode() + : cast(Op)->getAddressingMode(); + ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) + ? ARM_AM::add : ARM_AM::sub; + int Val; + if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. + Offset = CurDAG->getRegister(0, MVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, + ARM_AM::no_shift), + MVT::i32); + return true; + } + + return false; +} + + + bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, @@ -1298,9 +1317,14 @@ unsigned Opcode = 0; bool Match = false; if (LoadedVT == MVT::i32 && - SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { - Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; + SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { + Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST_IMM; + Match = true; + } else if (LoadedVT == MVT::i32 && + SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { + Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST_REG; Match = true; + } else if (LoadedVT == MVT::i16 && SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { Match = true; @@ -1314,9 +1338,12 @@ Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; } } else { - if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { + if (SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { + Match = true; + Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST_IMM; + } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { Match = true; - Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST; + Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST_REG; } } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jul 26 15:54:26 2011 @@ -507,22 +507,41 @@ let Inst{20} = isLd; // L bit let Inst{15-12} = Rt; } -class AI2stridx pattern> + : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, + pattern> { + // AM2 store w/ two operands: (GPR, am2offset) + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> Rn; + let Inst{25} = 1; + let Inst{23} = offset{12}; + let Inst{19-16} = Rn; + let Inst{11-5} = offset{11-5}; + let Inst{4} = 0; + let Inst{3-0} = offset{3-0}; +} + +class AI2stridx_imm pattern> : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, pattern> { // AM2 store w/ two operands: (GPR, am2offset) - // {13} 1 == Rm, 0 == imm12 // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> Rn; - let Inst{25} = offset{13}; + let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{19-16} = Rn; let Inst{11-0} = offset{11-0}; } + + // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB // but for now use this class for STRT and STRBT. class AI2stridxT= 0 && Imm < 32; }]> { let EncoderMethod = "getImmMinusOneOpValue"; + let DecoderMethod = "DecodeImmMinusOneOperand"; } // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference @@ -606,14 +607,23 @@ let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } -def am2offset : Operand, - ComplexPattern, + ComplexPattern { let EncoderMethod = "getAddrMode2OffsetOpValue"; let PrintMethod = "printAddrMode2OffsetOperand"; let MIOperandInfo = (ops GPR, i32imm); } +def am2offset_imm : Operand, + ComplexPattern { + let EncoderMethod = "getAddrMode2OffsetOpValue"; + let PrintMethod = "printAddrMode2OffsetOperand"; + let MIOperandInfo = (ops GPR, i32imm); +} + + // addrmode3 := reg +/- reg // addrmode3 := reg +/- imm8 // @@ -1845,7 +1855,7 @@ (ins addrmode2:$addr), IndexModePre, LdFrm, itin, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { // {17-14} Rn - // {13} 1 == Rm, 0 == imm12 + // {13} reg vs. imm // {12} isAdd // {11-0} imm12/Rm bits<18> addr; @@ -1855,19 +1865,35 @@ let Inst{11-0} = addr{11-0}; let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } - def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, am2offset:$offset), + + def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn, am2offset_reg:$offset), + IndexModePost, LdFrm, itin, + opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> Rn; + let Inst{25} = 1; + let Inst{23} = offset{12}; + let Inst{19-16} = Rn; + let Inst{11-0} = offset{11-0}; + let DecoderMethod = "DecodeAddrMode2IdxInstruction"; + } + + def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn, am2offset_imm:$offset), IndexModePost, LdFrm, itin, opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> { - // {13} 1 == Rm, 0 == imm12 // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> Rn; - let Inst{25} = offset{13}; + let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{19-16} = Rn; let Inst{11-0} = offset{11-0}; + let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } } @@ -1998,36 +2024,69 @@ "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>; // Indexed stores -def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb), - (ins GPR:$Rt, GPR:$Rn, am2offset:$offset), +def STR_PRE_REG : AI2stridx_reg<0, 1, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset), + IndexModePre, StFrm, IIC_iStore_ru, + "str", "\t$Rt, [$Rn, $offset]!", + "$Rn = $Rn_wb, at earlyclobber $Rn_wb", + [(set GPR:$Rn_wb, + (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; +def STR_PRE_IMM : AI2stridx_imm<0, 1, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset), IndexModePre, StFrm, IIC_iStore_ru, "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb, at earlyclobber $Rn_wb", [(set GPR:$Rn_wb, - (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>; + (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; + + -def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, GPR:$Rn, am2offset:$offset), +def STR_POST_REG : AI2stridx_reg<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset), IndexModePost, StFrm, IIC_iStore_ru, "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb, at earlyclobber $Rn_wb", [(set GPR:$Rn_wb, - (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>; + (post_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; +def STR_POST_IMM : AI2stridx_imm<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset), + IndexModePost, StFrm, IIC_iStore_ru, + "str", "\t$Rt, [$Rn], $offset", + "$Rn = $Rn_wb, at earlyclobber $Rn_wb", + [(set GPR:$Rn_wb, + (post_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; -def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb), - (ins GPR:$Rt, GPR:$Rn, am2offset:$offset), + +def STRB_PRE_REG : AI2stridx_reg<1, 1, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset), IndexModePre, StFrm, IIC_iStore_bh_ru, "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb, at earlyclobber $Rn_wb", [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, - GPR:$Rn, am2offset:$offset))]>; -def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, GPR:$Rn, am2offset:$offset), + GPR:$Rn, am2offset_reg:$offset))]>; +def STRB_PRE_IMM : AI2stridx_imm<1, 1, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset), + IndexModePre, StFrm, IIC_iStore_bh_ru, + "strb", "\t$Rt, [$Rn, $offset]!", + "$Rn = $Rn_wb, at earlyclobber $Rn_wb", + [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, + GPR:$Rn, am2offset_imm:$offset))]>; + +def STRB_POST_REG: AI2stridx_reg<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset), IndexModePost, StFrm, IIC_iStore_bh_ru, "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb, at earlyclobber $Rn_wb", [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt, - GPR:$Rn, am2offset:$offset))]>; + GPR:$Rn, am2offset_reg:$offset))]>; +def STRB_POST_IMM: AI2stridx_imm<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strb", "\t$Rt, [$Rn], $offset", + "$Rn = $Rn_wb, at earlyclobber $Rn_wb", + [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt, + GPR:$Rn, am2offset_imm:$offset))]>; + def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am3offset:$offset), Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Jul 26 15:54:26 2011 @@ -766,7 +766,7 @@ case ARM::LDRi12: return ARM::LDR_PRE; case ARM::STRi12: - return ARM::STR_PRE; + return ARM::STR_PRE_IMM; case ARM::VLDRS: return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; case ARM::VLDRD: @@ -790,9 +790,9 @@ ARM_AM::AddrOpc Mode) { switch (Opc) { case ARM::LDRi12: - return ARM::LDR_POST; + return ARM::LDR_POST_IMM; case ARM::STRi12: - return ARM::STR_POST; + return ARM::STR_POST_IMM; case ARM::VLDRS: return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; case ARM::VLDRD: Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=136141&r1=136140&r2=136141&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Jul 26 15:54:26 2011 @@ -639,7 +639,8 @@ MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I - MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I + MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I + MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I From evan.cheng at apple.com Tue Jul 26 15:57:44 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 20:57:44 -0000 Subject: [llvm-commits] [llvm] r136145 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110726205744.488BD2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 26 15:57:44 2011 New Revision: 136145 URL: http://llvm.org/viewvc/llvm-project?rev=136145&view=rev Log: Remove one last reference to Target in MC library. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=136145&r1=136144&r2=136145&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jul 26 15:57:44 2011 @@ -15,6 +15,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCSectionMachO.h" @@ -28,7 +29,6 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" -#include "llvm/Target/TargetLoweringObjectFile.h" #include using namespace llvm; From eli.friedman at gmail.com Tue Jul 26 16:02:58 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 26 Jul 2011 21:02:58 -0000 Subject: [llvm-commits] [llvm] r136148 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/split-vector-bitcast.ll Message-ID: <20110726210258.8499C2A6C12D@llvm.org> Author: efriedma Date: Tue Jul 26 16:02:58 2011 New Revision: 136148 URL: http://llvm.org/viewvc/llvm-project?rev=136148&view=rev Log: Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136148&r1=136147&r2=136148&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 26 16:02:58 2011 @@ -4520,7 +4520,8 @@ LDBase->getPointerInfo(), LDBase->isVolatile(), LDBase->isNonTemporal(), LDBase->getAlignment()); - } else if (NumElems == 4 && LastLoadedElt == 1) { + } else if (NumElems == 4 && LastLoadedElt == 1 && + DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Modified: llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll?rev=136148&r1=136147&r2=136148&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll (original) +++ llvm/trunk/test/CodeGen/X86/split-vector-bitcast.ll Tue Jul 26 16:02:58 2011 @@ -1,7 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=-sse2,+sse | grep addps -; XFAIL: * -; PR10497 +; PR10497 + another isel issue with sse2 disabled ; (This is primarily checking that this construct doesn't crash.) define void @a(<2 x float>* %a, <2 x i32>* %b) { %cc = load <2 x float>* %a From grosbach at apple.com Tue Jul 26 16:28:44 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 21:28:44 -0000 Subject: [llvm-commits] [llvm] r136152 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.td ARMInstrThumb2.td Disassembler/ARMDisassemblerCore.cpp Disassembler/ThumbDisassemblerCore.h InstPrinter/ARMInstPrinter.cpp InstPrinter/ARMInstPrinter.h MCTargetDesc/ARMMCCodeEmitter.cpp Message-ID: <20110726212844.4F4B92A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 16:28:43 2011 New Revision: 136152 URL: http://llvm.org/viewvc/llvm-project?rev=136152&view=rev Log: ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Jul 26 16:28:43 2011 @@ -215,8 +215,6 @@ const { return 0; } unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) - const { return 0; } unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 16:28:43 2011 @@ -388,10 +388,20 @@ } // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. -def rot_imm : Operand, ImmLeaf { - let EncoderMethod = "getRotImmOpValue"; +def rot_imm_XFORM: SDNodeXFormgetZExtValue()){ + default: assert(0); + case 0: return CurDAG->getTargetConstant(0, MVT::i32); + case 8: return CurDAG->getTargetConstant(1, MVT::i32); + case 16: return CurDAG->getTargetConstant(2, MVT::i32); + case 24: return CurDAG->getTargetConstant(3, MVT::i32); + } +}]>; +def rot_imm : Operand, PatLeaf<(i32 imm), [{ + int32_t v = N->getZExtValue(); + return v == 8 || v == 16 || v == 24; }], + rot_imm_XFORM> { + let PrintMethod = "printRotImmOperand"; } // shift_imm: An integer that encodes a shift amount and the type of shift @@ -989,7 +999,7 @@ let Inst{3-0} = Rm; } def r_rot : AExtI, Requires<[IsARM, HasV6]> { bits<4> Rd; @@ -1011,7 +1021,7 @@ let Inst{11-10} = 0b00; } def r_rot : AExtI, Requires<[IsARM, HasV6]> { bits<2> rot; @@ -1038,7 +1048,7 @@ } def rr_rot : AExtI, Requires<[IsARM, HasV6]> { @@ -1064,7 +1074,7 @@ } def rr_rot : AExtI, Requires<[IsARM, HasV6]> { bits<4> Rn; @@ -2414,9 +2424,9 @@ // instead so we can include a check for masking back in the upper // eight bits of the source into the lower eight bits of the result. //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), -// (UXTB16r_rot GPR:$Src, 24)>; +// (UXTB16r_rot GPR:$Src, 3)>; def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), - (UXTB16r_rot GPR:$Src, 8)>; + (UXTB16r_rot GPR:$Src, 1)>; defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jul 26 16:28:43 2011 @@ -990,7 +990,7 @@ let Inst{5-4} = 0b00; // rotate } def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, - opc, ".w\t$Rd, $Rm, ror $rot", + opc, ".w\t$Rd, $Rm, $rot", [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; @@ -1019,7 +1019,7 @@ let Inst{5-4} = 0b00; // rotate } def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), - IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot", + IIC_iEXTr, opc, "\t$dst, $Rm, $rot", [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; @@ -1079,7 +1079,7 @@ } def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { @@ -1094,9 +1094,7 @@ } } -// DO variant - disassembly only, no pattern - -multiclass T2I_exta_rrot_DO opcod, string opc> { +multiclass T2I_exta_rrot_np opcod, string opc> { def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", []> { let Inst{31-27} = 0b11111; @@ -1106,8 +1104,8 @@ let Inst{7} = 1; let Inst{5-4} = 0b00; // rotate } - def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> { + def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", []> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -1681,7 +1679,7 @@ BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; -defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">; +defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; // TODO: SXT(A){B|H}16 - done for disassembly only @@ -1700,17 +1698,17 @@ // instead so we can include a check for masking back in the upper // eight bits of the source into the lower eight bits of the result. //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), -// (t2UXTB16r_rot rGPR:$Src, 24)>, +// (t2UXTB16r_rot rGPR:$Src, 3)>, // Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), - (t2UXTB16r_rot rGPR:$Src, 8)>, + (t2UXTB16r_rot rGPR:$Src, 1)>, Requires<[HasT2ExtractPack, IsThumb2]>; defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah", BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; -defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">; +defm t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Jul 26 16:28:43 2011 @@ -1785,8 +1785,7 @@ && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Extract the 2-bit rotate field Inst{11-10}. unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3; - // Rotation by 8, 16, or 24 bits. - MI.addOperand(MCOperand::CreateImm(rot << 3)); + MI.addOperand(MCOperand::CreateImm(rot)); ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Tue Jul 26 16:28:43 2011 @@ -323,12 +323,6 @@ return SignExtend32<25>(Imm25); } -// See, for example, A8.6.221 SXTAB16. -static inline unsigned decodeRotate(uint32_t insn) { - unsigned rotate = slice(insn, 5, 4); - return rotate << 3; -} - /////////////////////////////////////////////// // // // Thumb1 instruction disassembly functions. // @@ -2195,7 +2189,7 @@ if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Add the rotation amount immediate. - MI.addOperand(MCOperand::CreateImm(decodeRotate(insn))); + MI.addOperand(MCOperand::CreateImm(slice(insn, 5, 4))); ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Jul 26 16:28:43 2011 @@ -835,3 +835,17 @@ unsigned Imm = MI->getOperand(OpNum).getImm(); O << "#" << Imm + 1; } + +void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNum).getImm(); + if (Imm == 0) + return; + O << "ror #"; + switch (Imm) { + default: assert (0 && "illegal ror immediate!"); + case 1: O << "8\n"; break; + case 2: O << "16\n"; break; + case 3: O << "24\n"; break; + } +} Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Jul 26 16:28:43 2011 @@ -115,6 +115,7 @@ void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); }; Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=136152&r1=136151&r2=136152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Jul 26 16:28:43 2011 @@ -259,17 +259,6 @@ unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; - unsigned getRotImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { - switch (MI.getOperand(Op).getImm()) { - default: assert (0 && "Not a valid rot_imm value!"); - case 0: return 0; - case 8: return 1; - case 16: return 2; - case 24: return 3; - } - } - unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { return MI.getOperand(Op).getImm() - 1; From grosbach at apple.com Tue Jul 26 16:44:37 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 26 Jul 2011 21:44:37 -0000 Subject: [llvm-commits] [llvm] r136154 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb2.td InstPrinter/ARMInstPrinter.cpp Message-ID: <20110726214437.791452A6C12C@llvm.org> Author: grosbach Date: Tue Jul 26 16:44:37 2011 New Revision: 136154 URL: http://llvm.org/viewvc/llvm-project?rev=136154&view=rev Log: ARM rot_imm printing adjustment. Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136154&r1=136153&r2=136154&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 26 16:44:37 2011 @@ -999,7 +999,7 @@ let Inst{3-0} = Rm; } def r_rot : AExtI, Requires<[IsARM, HasV6]> { bits<4> Rd; @@ -1021,7 +1021,7 @@ let Inst{11-10} = 0b00; } def r_rot : AExtI, Requires<[IsARM, HasV6]> { bits<2> rot; @@ -1048,7 +1048,7 @@ } def rr_rot : AExtI, Requires<[IsARM, HasV6]> { @@ -1074,7 +1074,7 @@ } def rr_rot : AExtI, Requires<[IsARM, HasV6]> { bits<4> Rn; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136154&r1=136153&r2=136154&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jul 26 16:44:37 2011 @@ -990,7 +990,7 @@ let Inst{5-4} = 0b00; // rotate } def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, - opc, ".w\t$Rd, $Rm, $rot", + opc, ".w\t$Rd, $Rm$rot", [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; @@ -1019,7 +1019,7 @@ let Inst{5-4} = 0b00; // rotate } def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), - IIC_iEXTr, opc, "\t$dst, $Rm, $rot", + IIC_iEXTr, opc, "\t$dst, $Rm$rot", [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; @@ -1079,7 +1079,7 @@ } def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { @@ -1105,7 +1105,7 @@ let Inst{5-4} = 0b00; // rotate } def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", []> { + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=136154&r1=136153&r2=136154&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Jul 26 16:44:37 2011 @@ -841,7 +841,7 @@ unsigned Imm = MI->getOperand(OpNum).getImm(); if (Imm == 0) return; - O << "ror #"; + O << ", ror #"; switch (Imm) { default: assert (0 && "illegal ror immediate!"); case 1: O << "8\n"; break; From gohman at apple.com Tue Jul 26 17:00:59 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 26 Jul 2011 22:00:59 -0000 Subject: [llvm-commits] [llvm] r136156 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110726220059.C73412A6C12C@llvm.org> Author: djg Date: Tue Jul 26 17:00:59 2011 New Revision: 136156 URL: http://llvm.org/viewvc/llvm-project?rev=136156&view=rev Log: Delete unnecessarily cautious LastCALLSEQ code. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=136156&r1=136155&r2=136156&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jul 26 17:00:59 2011 @@ -912,12 +912,7 @@ case ISD::BR_JT: case ISD::BR_CC: case ISD::BRCOND: - assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?"); - // Branches tweak the chain to include LastCALLSEQ - Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], - getLastCALLSEQ()); Ops[0] = LegalizeOp(Ops[0]); - setLastCALLSEQ(DAG.getEntryNode()); break; case ISD::SHL: case ISD::SRL: @@ -1021,14 +1016,6 @@ // libcalls), create the new CALLSEQ_START node. Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - // Merge in the last call to ensure that this call starts after the last - // call ended. - if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) { - Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - Tmp1, getLastCALLSEQ()); - Tmp1 = LegalizeOp(Tmp1); - } - // Do not try to legalize the target-specific arguments (#1+). if (Tmp1 != Node->getOperand(0)) { SmallVector Ops(Node->op_begin(), Node->op_end()); @@ -1050,7 +1037,7 @@ setLastCALLSEQ(SDValue(CallEnd, 0)); // Legalize the call, starting from the CALLSEQ_END. - LegalizeOp(getLastCALLSEQ()); + LegalizeOp(SDValue(CallEnd, 0)); return Result; } case ISD::CALLSEQ_END: From bruno.cardoso at gmail.com Tue Jul 26 17:03:40 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 26 Jul 2011 22:03:40 -0000 Subject: [llvm-commits] [llvm] r136157 - in /llvm/trunk: lib/Target/X86/Utils/X86ShuffleDecode.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/SIMD/dg.exp test/CodeGen/X86/SIMD/notvunpcklpd.ll test/CodeGen/X86/SIMD/notvunpcklps.ll test/CodeGen/X86/SIMD/vunpcklpd.ll test/CodeGen/X86/SIMD/vunpcklps.ll test/CodeGen/X86/avx-256-unpack.ll Message-ID: <20110726220340.91E6E2A6C12C@llvm.org> Author: bruno Date: Tue Jul 26 17:03:40 2011 New Revision: 136157 URL: http://llvm.org/viewvc/llvm-project?rev=136157&view=rev Log: Recognize unpckh* masks and match 256-bit versions. The new versions are different from the previous 128-bit because they work in lanes. Update a few comments and add testcases Added: llvm/trunk/test/CodeGen/X86/avx-256-unpack.ll Removed: llvm/trunk/test/CodeGen/X86/SIMD/dg.exp llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklpd.ll llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklps.ll llvm/trunk/test/CodeGen/X86/SIMD/vunpcklpd.ll llvm/trunk/test/CodeGen/X86/SIMD/vunpcklps.ll Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp?rev=136157&r1=136156&r2=136157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp (original) +++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp Tue Jul 26 17:03:40 2011 @@ -167,23 +167,22 @@ SmallVectorImpl &ShuffleMask) { unsigned NumElts = VT.getVectorNumElements(); - // Handle vector lengths > 128 bits. Define a "section" as a set of - // 128 bits. AVX defines UNPCK* to operate independently on 128-bit - // sections. - unsigned NumSections = VT.getSizeInBits() / 128; - if (NumSections == 0 ) NumSections = 1; // Handle MMX - unsigned NumSectionElts = NumElts / NumSections; + // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate + // independently on 128-bit lanes. + unsigned NumLanes = VT.getSizeInBits() / 128; + if (NumLanes == 0 ) NumLanes = 1; // Handle MMX + unsigned NumLaneElts = NumElts / NumLanes; unsigned Start = 0; - unsigned End = NumSectionElts / 2; - for (unsigned s = 0; s < NumSections; ++s) { + unsigned End = NumLaneElts / 2; + for (unsigned s = 0; s < NumLanes; ++s) { for (unsigned i = Start; i != End; ++i) { ShuffleMask.push_back(i); // Reads from dest/src1 - ShuffleMask.push_back(i+NumSectionElts); // Reads from src/src2 + ShuffleMask.push_back(i+NumLaneElts); // Reads from src/src2 } // Process the next 128 bits. - Start += NumSectionElts; - End += NumSectionElts; + Start += NumLaneElts; + End += NumLaneElts; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136157&r1=136156&r2=136157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 26 17:03:40 2011 @@ -2711,6 +2711,8 @@ case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::UNPCKHPD: + case X86ISD::VUNPCKHPSY: + case X86ISD::VUNPCKHPDY: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: @@ -2782,6 +2784,8 @@ case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::UNPCKHPD: + case X86ISD::VUNPCKHPSY: + case X86ISD::VUNPCKHPDY: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: @@ -3219,20 +3223,22 @@ static bool isUNPCKLMask(const SmallVectorImpl &Mask, EVT VT, bool V2IsSplat = false) { int NumElts = VT.getVectorNumElements(); - if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) + + assert((VT.is128BitVector() || VT.is256BitVector()) && + "Unsupported vector type for unpckh"); + + if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) return false; - // Handle vector lengths > 128 bits. Define a "section" as a set of - // 128 bits. AVX defines UNPCK* to operate independently on 128-bit - // sections. - unsigned NumSections = VT.getSizeInBits() / 128; - if (NumSections == 0 ) NumSections = 1; // Handle MMX - unsigned NumSectionElts = NumElts / NumSections; + // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate + // independently on 128-bit lanes. + unsigned NumLanes = VT.getSizeInBits()/128; + unsigned NumLaneElts = NumElts/NumLanes; unsigned Start = 0; - unsigned End = NumSectionElts; - for (unsigned s = 0; s < NumSections; ++s) { - for (unsigned i = Start, j = s * NumSectionElts; + unsigned End = NumLaneElts; + for (unsigned s = 0; s < NumLanes; ++s) { + for (unsigned i = Start, j = s * NumLaneElts; i != End; i += 2, ++j) { int BitI = Mask[i]; @@ -3248,8 +3254,8 @@ } } // Process the next 128 bits. - Start += NumSectionElts; - End += NumSectionElts; + Start += NumLaneElts; + End += NumLaneElts; } return true; @@ -3266,21 +3272,38 @@ static bool isUNPCKHMask(const SmallVectorImpl &Mask, EVT VT, bool V2IsSplat = false) { int NumElts = VT.getVectorNumElements(); - if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) + + assert((VT.is128BitVector() || VT.is256BitVector()) && + "Unsupported vector type for unpckh"); + + if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) return false; - for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { - int BitI = Mask[i]; - int BitI1 = Mask[i+1]; - if (!isUndefOrEqual(BitI, j + NumElts/2)) - return false; - if (V2IsSplat) { - if (isUndefOrEqual(BitI1, NumElts)) - return false; - } else { - if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) + // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate + // independently on 128-bit lanes. + unsigned NumLanes = VT.getSizeInBits()/128; + unsigned NumLaneElts = NumElts/NumLanes; + + unsigned Start = 0; + unsigned End = NumLaneElts; + for (unsigned l = 0; l != NumLanes; ++l) { + for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; + i != End; i += 2, ++j) { + int BitI = Mask[i]; + int BitI1 = Mask[i+1]; + if (!isUndefOrEqual(BitI, j)) return false; + if (V2IsSplat) { + if (isUndefOrEqual(BitI1, NumElts)) + return false; + } else { + if (!isUndefOrEqual(BitI1, j+NumElts)) + return false; + } } + // Process the next 128 bits. + Start += NumLaneElts; + End += NumLaneElts; } return true; } @@ -3299,16 +3322,14 @@ if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) return false; - // Handle vector lengths > 128 bits. Define a "section" as a set of - // 128 bits. AVX defines UNPCK* to operate independently on 128-bit - // sections. - unsigned NumSections = VT.getSizeInBits() / 128; - if (NumSections == 0 ) NumSections = 1; // Handle MMX - unsigned NumSectionElts = NumElems / NumSections; - - for (unsigned s = 0; s < NumSections; ++s) { - for (unsigned i = s * NumSectionElts, j = s * NumSectionElts; - i != NumSectionElts * (s + 1); + // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate + // independently on 128-bit lanes. + unsigned NumLanes = VT.getSizeInBits() / 128; + unsigned NumLaneElts = NumElems / NumLanes; + + for (unsigned s = 0; s < NumLanes; ++s) { + for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; + i != NumLaneElts * (s + 1); i += 2, ++j) { int BitI = Mask[i]; int BitI1 = Mask[i+1]; @@ -4095,6 +4116,8 @@ break; case X86ISD::UNPCKHPS: case X86ISD::UNPCKHPD: + case X86ISD::VUNPCKHPSY: + case X86ISD::VUNPCKHPDY: DecodeUNPCKHPMask(NumElems, ShuffleMask); break; case X86ISD::PUNPCKLBW: @@ -5751,6 +5774,8 @@ case MVT::v2i64: return X86ISD::PUNPCKHQDQ; case MVT::v4f32: return X86ISD::UNPCKHPS; case MVT::v2f64: return X86ISD::UNPCKHPD; + case MVT::v8f32: return X86ISD::VUNPCKHPSY; + case MVT::v4f64: return X86ISD::VUNPCKHPDY; case MVT::v16i8: return X86ISD::PUNPCKHBW; case MVT::v8i16: return X86ISD::PUNPCKHWD; default: @@ -12597,6 +12622,8 @@ case X86ISD::PUNPCKHQDQ: case X86ISD::UNPCKHPS: case X86ISD::UNPCKHPD: + case X86ISD::VUNPCKHPSY: + case X86ISD::VUNPCKHPDY: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLDQ: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=136157&r1=136156&r2=136157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Jul 26 17:03:40 2011 @@ -261,6 +261,8 @@ VUNPCKLPDY, UNPCKHPS, UNPCKHPD, + VUNPCKHPSY, + VUNPCKHPDY, PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136157&r1=136156&r2=136157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Jul 26 17:03:40 2011 @@ -133,12 +133,15 @@ def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; -def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>; -def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>; +def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>; +def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>; def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>; def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>; -def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>; -def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>; + +def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>; +def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>; +def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>; +def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>; def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>; def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136157&r1=136156&r2=136157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 26 17:03:40 2011 @@ -5677,6 +5677,12 @@ def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)), (UNPCKHPSrr VR128:$src1, VR128:$src2)>; +// Shuffle with VUNPCKHPSY +def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; +def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; + // Shuffle with UNPCKLPD def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))), (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>; @@ -5703,6 +5709,12 @@ def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), (UNPCKHPDrr VR128:$src1, VR128:$src2)>; +// Shuffle with VUNPCKHPDY +def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; +def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; + // Shuffle with MOVLHPS def : Pat<(X86Movlhps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), Removed: llvm/trunk/test/CodeGen/X86/SIMD/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/SIMD/dg.exp?rev=136156&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/SIMD/dg.exp (original) +++ llvm/trunk/test/CodeGen/X86/SIMD/dg.exp (removed) @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] -} Removed: llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklpd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklpd.ll?rev=136156&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklpd.ll (original) +++ llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklpd.ll (removed) @@ -1,20 +0,0 @@ -; RUN: llc < %s -mattr=+avx | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) { -entry: - %incarray1 = alloca [2 x <4 x double>]*, align 8 - %incarrayb1 = alloca [2 x <4 x double>]*, align 8 - %carray = alloca [2 x <4 x double>], align 16 - %r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0 - %rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0 - %r3 = load <4 x double>* %r, align 8 - %r4 = load <4 x double>* %rb, align 8 - %r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x double>> [#uses=1] -; CHECK-NOT: vunpcklpd %ymm - %r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1 - store <4 x double> %r11, <4 x double>* %r12, align 4 - ret void -} Removed: llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklps.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklps.ll?rev=136156&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklps.ll (original) +++ llvm/trunk/test/CodeGen/X86/SIMD/notvunpcklps.ll (removed) @@ -1,20 +0,0 @@ -; RUN: llc < %s -mattr=+avx | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) { -enmtry: - %incarray1 = alloca [2 x <8 x float>]*, align 8 - %incarrayb1 = alloca [2 x <8 x float>]*, align 8 - %carray = alloca [2 x <8 x float>], align 16 - %r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0 - %rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0 - %r3 = load <8 x float>* %r, align 8 - %r4 = load <8 x float>* %rb, align 8 - %r8 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x float>> [#uses=1] -; CHECK-NOT: vunpcklps %ymm - %r9 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 0 - store <8 x float> %r8, <8 x float>* %r9, align 4 - ret void -} Removed: llvm/trunk/test/CodeGen/X86/SIMD/vunpcklpd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/SIMD/vunpcklpd.ll?rev=136156&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/SIMD/vunpcklpd.ll (original) +++ llvm/trunk/test/CodeGen/X86/SIMD/vunpcklpd.ll (removed) @@ -1,20 +0,0 @@ -; RUN: llc < %s -mattr=+avx | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) { -entry: - %incarray1 = alloca [2 x <4 x double>]*, align 8 - %incarrayb1 = alloca [2 x <4 x double>]*, align 8 - %carray = alloca [2 x <4 x double>], align 16 - %r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0 - %rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0 - %r3 = load <4 x double>* %r, align 8 - %r4 = load <4 x double>* %rb, align 8 - %r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 2, i32 6 > ; <<4 x double>> [#uses=1] -; CHECK: vunpcklpd - %r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1 - store <4 x double> %r11, <4 x double>* %r12, align 4 - ret void -} Removed: llvm/trunk/test/CodeGen/X86/SIMD/vunpcklps.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/SIMD/vunpcklps.ll?rev=136156&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/SIMD/vunpcklps.ll (original) +++ llvm/trunk/test/CodeGen/X86/SIMD/vunpcklps.ll (removed) @@ -1,20 +0,0 @@ -; RUN: llc < %s -mattr=+avx | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) { -entry: - %incarray1 = alloca [2 x <8 x float>]*, align 8 - %incarrayb1 = alloca [2 x <8 x float>]*, align 8 - %carray = alloca [2 x <8 x float>], align 16 - %r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0 - %rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0 - %r3 = load <8 x float>* %r, align 8 - %r4 = load <8 x float>* %rb, align 8 - %r11 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13 > ; <<8 x float>> [#uses=1] -; CHECK: vunpcklps - %r12 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 1 - store <8 x float> %r11, <8 x float>* %r12, align 4 - ret void -} Added: llvm/trunk/test/CodeGen/X86/avx-256-unpack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-unpack.ll?rev=136157&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256-unpack.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-256-unpack.ll Tue Jul 26 17:03:40 2011 @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vunpckhps +define <8 x float> @unpackhips(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK: vunpckhpd +define <4 x double> @unpackhipd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> + ret <4 x double> %shuffle.i +} + +; CHECK: vunpcklps +define <8 x float> @unpacklops(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK: vunpcklpd +define <4 x double> @unpacklopd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> + ret <4 x double> %shuffle.i +} + +; CHECK-NOT: vunpcklps %ymm +define <8 x float> @unpacklops-not(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK-NOT: vunpcklpd %ymm +define <4 x double> @unpacklopd-not(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> + ret <4 x double> %shuffle.i +} + +; CHECK-NOT: vunpckhps %ymm +define <8 x float> @unpackhips-not(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> + ret <8 x float> %shuffle.i +} + +; CHECK-NOT: vunpckhpd %ymm +define <4 x double> @unpackhipd-not(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp { +entry: + %shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> + ret <4 x double> %shuffle.i +} + From benny.kra at googlemail.com Tue Jul 26 17:42:13 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 26 Jul 2011 22:42:13 -0000 Subject: [llvm-commits] [llvm] r136167 - in /llvm/trunk: lib/Target/X86/README.txt lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sub.ll Message-ID: <20110726224213.A940B2A6C12C@llvm.org> Author: d0k Date: Tue Jul 26 17:42:13 2011 New Revision: 136167 URL: http://llvm.org/viewvc/llvm-project?rev=136167&view=rev Log: Add a neat little two's complement hack for x86. On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add, which can be commuted and encoded efficiently. This code is generated for __builtin_clz and friends. Added: llvm/trunk/test/CodeGen/X86/sub.ll Modified: llvm/trunk/lib/Target/X86/README.txt llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=136167&r1=136166&r2=136167&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README.txt (original) +++ llvm/trunk/lib/Target/X86/README.txt Tue Jul 26 17:42:13 2011 @@ -2076,12 +2076,11 @@ jb LBB0_2 ## BB#1: decl %edi - movl $63, %eax - bsrl %edi, %ecx - cmovel %eax, %ecx - xorl $31, %ecx - movl $32, %eax - subl %ecx, %eax + movl $63, %ecx + bsrl %edi, %eax + cmovel %ecx, %eax + xorl $-32, %eax + addl $33, %eax LBB0_2: ret @@ -2091,26 +2090,10 @@ jb LBB0_2 ## BB#1: decl %edi - bsrl %edi, %ecx - xorl $31, %ecx - movl $32, %eax - subl %ecx, %eax + bsrl %edi, %eax + xorl $-32, %eax + addl $33, %eax LBB0_2: ret -If we want to get really fancy we could use some two's complement magic: - xorl %eax, %eax - cmpl $2, %edi - jb LBB0_2 -## BB#1: - decl %edi - bsrl %edi, %ecx - xorl $-32, %ecx - leal 33(%ecx), %eax -LBB0_2: - ret - -This is only useful on targets that can't encode the first operand of a sub -directly. The rule is C1 - (X^C2) -> (C1+1) + (X^~C2). - //===---------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136167&r1=136166&r2=136167&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 26 17:42:13 2011 @@ -12550,7 +12550,7 @@ // (add Y, (setne X, 0)) -> sbb -1, Y // (sub (sete X, 0), Y) -> sbb 0, Y // (sub (setne X, 0), Y) -> adc -1, Y -static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) { +static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { DebugLoc DL = N->getDebugLoc(); // Look through ZExts. @@ -12586,6 +12586,33 @@ DAG.getConstant(0, OtherVal.getValueType()), NewCmp); } +static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + + // X86 can't encode an immediate LHS of a sub. See if we can push the + // negation into a preceding instruction. + if (ConstantSDNode *C = dyn_cast(Op0)) { + uint64_t Op0C = C->getSExtValue(); + + // If the RHS of the sub is a XOR with one use and a constant, invert the + // immediate. Then add one to the LHS of the sub so we can turn + // X-Y -> X+~Y+1, saving one register. + if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && + isa(Op1.getOperand(1))) { + uint64_t XorC = cast(Op1.getOperand(1))->getSExtValue(); + EVT VT = Op0.getValueType(); + SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, + Op1.getOperand(0), + DAG.getConstant(~XorC, VT)); + return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, + DAG.getConstant(Op0C+1, VT)); + } + } + + return OptimizeConditionalInDecrement(N, DAG); +} + SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -12595,8 +12622,8 @@ return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); - case ISD::ADD: - case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG); + case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); + case ISD::SUB: return PerformSubCombine(N, DAG); case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); case ISD::MUL: return PerformMulCombine(N, DAG, DCI); case ISD::SHL: Added: llvm/trunk/test/CodeGen/X86/sub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sub.ll?rev=136167&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sub.ll (added) +++ llvm/trunk/test/CodeGen/X86/sub.ll Tue Jul 26 17:42:13 2011 @@ -0,0 +1,11 @@ +; RUN: llc -march=x86 < sub.ll | FileCheck %s + +define i32 @test1(i32 %x) { + %xor = xor i32 %x, 31 + %sub = sub i32 32, %xor + ret i32 %sub +; CHECK: test1: +; CHECK: xorl $-32 +; CHECK-NEXT: addl $33 +; CHECK-NEXT: ret +} From benny.kra at googlemail.com Tue Jul 26 17:45:39 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 26 Jul 2011 22:45:39 -0000 Subject: [llvm-commits] [llvm] r136170 - /llvm/trunk/test/CodeGen/X86/sub.ll Message-ID: <20110726224539.E3CD22A6C12C@llvm.org> Author: d0k Date: Tue Jul 26 17:45:39 2011 New Revision: 136170 URL: http://llvm.org/viewvc/llvm-project?rev=136170&view=rev Log: Update test. Modified: llvm/trunk/test/CodeGen/X86/sub.ll Modified: llvm/trunk/test/CodeGen/X86/sub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sub.ll?rev=136170&r1=136169&r2=136170&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sub.ll (original) +++ llvm/trunk/test/CodeGen/X86/sub.ll Tue Jul 26 17:45:39 2011 @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 < sub.ll | FileCheck %s +; RUN: llc -march=x86 < %s | FileCheck %s define i32 @test1(i32 %x) { %xor = xor i32 %x, 31 From stoklund at 2pi.dk Tue Jul 26 18:00:24 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 26 Jul 2011 23:00:24 -0000 Subject: [llvm-commits] [llvm] r136174 - in /llvm/trunk: lib/CodeGen/RegisterCoalescer.cpp lib/CodeGen/RegisterCoalescer.h test/CodeGen/X86/crash-nosse.ll Message-ID: <20110726230024.76F892A6C12C@llvm.org> Author: stoklund Date: Tue Jul 26 18:00:24 2011 New Revision: 136174 URL: http://llvm.org/viewvc/llvm-project?rev=136174&view=rev Log: Eliminate copies of undefined values during coalescing. These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. Added: llvm/trunk/test/CodeGen/X86/crash-nosse.ll Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.h Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=136174&r1=136173&r2=136174&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Jul 26 18:00:24 2011 @@ -760,6 +760,49 @@ return true; } +/// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of +/// values, it only removes local variables. When we have a copy like: +/// +/// %vreg1 = COPY %vreg2 +/// +/// We delete the copy and remove the corresponding value number from %vreg1. +/// Any uses of that value number are marked as . +bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI, + const CoalescerPair &CP) { + SlotIndex Idx = li_->getInstructionIndex(CopyMI); + LiveInterval *SrcInt = &li_->getInterval(CP.getSrcReg()); + if (SrcInt->liveAt(Idx)) + return false; + LiveInterval *DstInt = &li_->getInterval(CP.getDstReg()); + if (DstInt->liveAt(Idx)) + return false; + + // No intervals are live-in to CopyMI - it is undef. + if (CP.isFlipped()) + DstInt = SrcInt; + SrcInt = 0; + + VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getDefIndex()); + assert(DeadVNI && "No value defined in DstInt"); + DstInt->removeValNo(DeadVNI); + + // Find new undef uses. + for (MachineRegisterInfo::reg_nodbg_iterator + I = mri_->reg_nodbg_begin(DstInt->reg), E = mri_->reg_nodbg_end(); + I != E; ++I) { + MachineOperand &MO = I.getOperand(); + if (MO.isDef() || MO.isUndef()) + continue; + MachineInstr *MI = MO.getParent(); + SlotIndex Idx = li_->getInstructionIndex(MI); + if (DstInt->liveAt(Idx)) + continue; + MO.setIsUndef(true); + DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI); + } + return true; +} + /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and /// update the subregister number if it is not zero. If DstReg is a /// physical register and the existing subregister number of the def / use @@ -1018,6 +1061,13 @@ return false; // Not coalescable. } + // Eliminate undefs. + if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) { + markAsJoined(CopyMI); + DEBUG(dbgs() << "\tEliminated copy of value.\n"); + return false; // Not coalescable. + } + DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_) << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx()) << "\n"); Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.h?rev=136174&r1=136173&r2=136174&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.h (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.h Tue Jul 26 18:00:24 2011 @@ -136,6 +136,9 @@ /// markAsJoined - Remember that CopyMI has already been joined. void markAsJoined(MachineInstr *CopyMI); + /// eliminateUndefCopy - Handle copies of undef values. + bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP); + public: static char ID; // Class identification, replacement for typeinfo RegisterCoalescer() : MachineFunctionPass(ID) { Added: llvm/trunk/test/CodeGen/X86/crash-nosse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/crash-nosse.ll?rev=136174&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/crash-nosse.ll (added) +++ llvm/trunk/test/CodeGen/X86/crash-nosse.ll Tue Jul 26 18:00:24 2011 @@ -0,0 +1,27 @@ +; RUN: llc < %s -mattr=-sse2,-sse41 -verify-machineinstrs +target triple = "x86_64-unknown-linux-gnu" + +; PR10503 +; This test case produces INSERT_SUBREG 0, instructions that +; ProcessImplicitDefs doesn't eliminate. +define void @autogen_136178_500() { +BB: + %Shuff6 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> + %S17 = select i1 true, <8 x float>* null, <8 x float>* null + br label %CF + +CF: ; preds = %CF, %BB + %L19 = load <8 x float>* %S17 + %BC = bitcast <32 x i32> %Shuff6 to <32 x float> + %S28 = fcmp ord double 0x3ED1A1F787BB2185, 0x3EE59DE55A8DF890 + br i1 %S28, label %CF, label %CF39 + +CF39: ; preds = %CF39, %CF + store <8 x float> %L19, <8 x float>* %S17 + %I35 = insertelement <32 x float> %BC, float 0x3EC2489F60000000, i32 9 + %S38 = fcmp ule double 0x3EE59DE55A8DF890, 0x3EC4AB0CBB986A1A + br i1 %S38, label %CF39, label %CF40 + +CF40: ; preds = %CF39 + ret void +} From hwennborg at google.com Tue Jul 26 13:11:11 2011 From: hwennborg at google.com (Hans Wennborg) Date: Tue, 26 Jul 2011 19:11:11 +0100 Subject: [llvm-commits] [Patch] Missed instsimplify transformation Message-ID: Hi all, The attached patch adds a simplification for ((A & 1) == 0) | (A == 0) to (A & 1) == 0 Is this ok to add to instsimplify? Thanks, Hans -------------- next part -------------- A non-text attachment was scrubbed... Name: inst-simplify.patch Type: text/x-patch Size: 1946 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110726/f1d7f8dc/attachment.bin From stoklund at 2pi.dk Tue Jul 26 18:12:08 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 26 Jul 2011 23:12:08 -0000 Subject: [llvm-commits] [llvm] r136178 - /llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Message-ID: <20110726231209.017C62A6C12D@llvm.org> Author: stoklund Date: Tue Jul 26 18:12:08 2011 New Revision: 136178 URL: http://llvm.org/viewvc/llvm-project?rev=136178&view=rev Log: Print out the MBB live-in registers. Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=136178&r1=136177&r2=136178&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Jul 26 18:12:08 2011 @@ -439,6 +439,7 @@ LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg]; if (LiveUnion.empty()) continue; + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:"); MachineFunction::iterator MBB = llvm::next(MF->begin()); MachineFunction::iterator MFE = MF->end(); SlotIndex Start, Stop; @@ -449,6 +450,8 @@ if (SI.start() <= Start) { if (!MBB->isLiveIn(PhysReg)) MBB->addLiveIn(PhysReg); + DEBUG(dbgs() << "\tBB#" << MBB->getNumber() << ':' + << PrintReg(SI.value()->reg, TRI)); } else if (SI.start() > Stop) MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex()); if (++MBB == MFE) @@ -456,6 +459,7 @@ tie(Start, Stop) = Indexes->getMBBRange(MBB); SI.advanceTo(Start); } + DEBUG(dbgs() << '\n'); } } From stoklund at 2pi.dk Tue Jul 26 18:41:46 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 26 Jul 2011 23:41:46 -0000 Subject: [llvm-commits] [llvm] r136186 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110726234146.91A692A6C12C@llvm.org> Author: stoklund Date: Tue Jul 26 18:41:46 2011 New Revision: 136186 URL: http://llvm.org/viewvc/llvm-project?rev=136186&view=rev Log: Add support for multi-way live range splitting. When splitting global live ranges, it is now possible to split for multiple destination intervals at once. Previously, we only had the main and stack intervals. Each edge bundle is assigned to a split candidate, and splitAroundRegion will insert copies between the candidate intervals and the stack interval as needed. The multi-way splitting is used to split around compact regions when enabled with -compact-regions. The best candidate register still gets all the bundles it wants, but everything outside the main interval is first split around compact regions before we create single-block intervals. Compact region splitting still causes some regressions, so it is not enabled by default. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=136186&r1=136185&r2=136186&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jul 26 18:41:46 2011 @@ -38,6 +38,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -51,6 +52,8 @@ STATISTIC(NumLocalSplits, "Number of split local live ranges"); STATISTIC(NumEvicted, "Number of interferences evicted"); +cl::opt CompactRegions("compact-regions"); + static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator); @@ -171,17 +174,38 @@ /// Global live range splitting candidate info. struct GlobalSplitCandidate { + // Register intended for assignment, or 0. unsigned PhysReg; + + // SplitKit interval index for this candidate. + unsigned IntvIdx; + + // Interference for PhysReg. InterferenceCache::Cursor Intf; + + // Bundles where this candidate should be live. BitVector LiveBundles; SmallVector ActiveBlocks; void reset(InterferenceCache &Cache, unsigned Reg) { PhysReg = Reg; + IntvIdx = 0; Intf.setPhysReg(Cache, Reg); LiveBundles.clear(); ActiveBlocks.clear(); } + + // Set B[i] = C for every live bundle where B[i] was NoCand. + unsigned getBundles(SmallVectorImpl &B, unsigned C) { + unsigned Count = 0; + for (int i = LiveBundles.find_first(); i >= 0; + i = LiveBundles.find_next(i)) + if (B[i] == NoCand) { + B[i] = C; + Count++; + } + return Count; + } }; /// Candidate info for for each PhysReg in AllocationOrder. @@ -189,6 +213,12 @@ /// class. SmallVector GlobalCand; + enum { NoCand = ~0u }; + + /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to + /// NoCand which indicates the stack interval. + SmallVector BundleCand; + public: RAGreedy(); @@ -223,8 +253,7 @@ void growRegion(GlobalSplitCandidate &Cand); float calcGlobalSplitCost(GlobalSplitCandidate&); bool calcCompactRegion(GlobalSplitCandidate&); - void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&, - SmallVectorImpl&); + void splitAroundRegion(LiveRangeEdit&, ArrayRef); void calcGapWeights(unsigned, SmallVectorImpl&); bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&); @@ -896,81 +925,109 @@ return GlobalCost; } -/// splitAroundRegion - Split VirtReg around the region determined by -/// LiveBundles. Make an effort to avoid interference from PhysReg. +/// splitAroundRegion - Split the current live range around the regions +/// determined by BundleCand and GlobalCand. /// -/// The 'register' interval is going to contain as many uses as possible while -/// avoiding interference. The 'stack' interval is the complement constructed by -/// SplitEditor. It will contain the rest. +/// Before calling this function, GlobalCand and BundleCand must be initialized +/// so each bundle is assigned to a valid candidate, or NoCand for the +/// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor +/// objects must be initialized for the current live range, and intervals +/// created for the used candidates. /// -void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, - GlobalSplitCandidate &Cand, - SmallVectorImpl &NewVRegs) { - const BitVector &LiveBundles = Cand.LiveBundles; - - DEBUG({ - dbgs() << "Splitting around region for " << PrintReg(Cand.PhysReg, TRI) - << " with bundles"; - for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i)) - dbgs() << " EB#" << i; - dbgs() << ".\n"; - }); - - InterferenceCache::Cursor &Intf = Cand.Intf; - LiveRangeEdit LREdit(VirtReg, NewVRegs, this); - SE->reset(LREdit); - - // Create the main cross-block interval. - const unsigned MainIntv = SE->openIntv(); +/// @param LREdit The LiveRangeEdit object handling the current split. +/// @param UsedCands List of used GlobalCand entries. Every BundleCand value +/// must appear in this list. +void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, + ArrayRef UsedCands) { + // These are the intervals created for new global ranges. We may create more + // intervals for local ranges. + const unsigned NumGlobalIntvs = LREdit.size(); + DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n"); + assert(NumGlobalIntvs && "No global intervals configured"); // First handle all the blocks with uses. ArrayRef UseBlocks = SA->getUseBlocks(); for (unsigned i = 0; i != UseBlocks.size(); ++i) { const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = BI.LiveIn && - LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = BI.LiveOut && - LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + unsigned Number = BI.MBB->getNumber(); + unsigned IntvIn = 0, IntvOut = 0; + SlotIndex IntfIn, IntfOut; + if (BI.LiveIn) { + unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)]; + if (CandIn != NoCand) { + GlobalSplitCandidate &Cand = GlobalCand[CandIn]; + IntvIn = Cand.IntvIdx; + Cand.Intf.moveToBlock(Number); + IntfIn = Cand.Intf.first(); + } + } + if (BI.LiveOut) { + unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)]; + if (CandOut != NoCand) { + GlobalSplitCandidate &Cand = GlobalCand[CandOut]; + IntvOut = Cand.IntvIdx; + Cand.Intf.moveToBlock(Number); + IntfOut = Cand.Intf.last(); + } + } // Create separate intervals for isolated blocks with multiple uses. - if (!RegIn && !RegOut) { + if (!IntvIn && !IntvOut) { DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); - if (!BI.isOneInstr()) { + if (!BI.isOneInstr()) SE->splitSingleBlock(BI); - SE->selectIntv(MainIntv); - } continue; } - Intf.moveToBlock(BI.MBB->getNumber()); - - if (RegIn && RegOut) - SE->splitLiveThroughBlock(BI.MBB->getNumber(), - MainIntv, Intf.first(), - MainIntv, Intf.last()); - else if (RegIn) - SE->splitRegInBlock(BI, MainIntv, Intf.first()); + if (IntvIn && IntvOut) + SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut); + else if (IntvIn) + SE->splitRegInBlock(BI, IntvIn, IntfIn); else - SE->splitRegOutBlock(BI, MainIntv, Intf.last()); + SE->splitRegOutBlock(BI, IntvOut, IntfOut); } - // Handle live-through blocks. - for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { - unsigned Number = Cand.ActiveBlocks[i]; - bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; - bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)]; - if (!RegIn && !RegOut) - continue; - Intf.moveToBlock(Number); - SE->splitLiveThroughBlock(Number, RegIn ? MainIntv : 0, Intf.first(), - RegOut ? MainIntv : 0, Intf.last()); + // Handle live-through blocks. The relevant live-through blocks are stored in + // the ActiveBlocks list with each candidate. We need to filter out + // duplicates. + BitVector Todo = SA->getThroughBlocks(); + for (unsigned c = 0; c != UsedCands.size(); ++c) { + ArrayRef Blocks = GlobalCand[UsedCands[c]].ActiveBlocks; + for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { + unsigned Number = Blocks[i]; + if (!Todo.test(Number)) + continue; + Todo.reset(Number); + + unsigned IntvIn = 0, IntvOut = 0; + SlotIndex IntfIn, IntfOut; + + unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)]; + if (CandIn != NoCand) { + GlobalSplitCandidate &Cand = GlobalCand[CandIn]; + IntvIn = Cand.IntvIdx; + Cand.Intf.moveToBlock(Number); + IntfIn = Cand.Intf.first(); + } + + unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)]; + if (CandOut != NoCand) { + GlobalSplitCandidate &Cand = GlobalCand[CandOut]; + IntvOut = Cand.IntvIdx; + Cand.Intf.moveToBlock(Number); + IntfOut = Cand.Intf.last(); + } + if (!IntvIn && !IntvOut) + continue; + SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut); + } } ++NumGlobalSplits; SmallVector IntvMap; SE->finish(&IntvMap); - DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); + DebugVars->splitRegister(SA->getParent().reg, LREdit.regs()); ExtraRegInfo.resize(MRI->getNumVirtRegs()); unsigned OrigBlocks = SA->getNumLiveBlocks(); @@ -994,9 +1051,9 @@ continue; } - // Main interval. Allow repeated splitting as long as the number of live - // blocks is strictly decreasing. Otherwise force per-block splitting. - if (IntvMap[i] == MainIntv) { + // Global intervals. Allow repeated splitting as long as the number of live + // blocks is strictly decreasing. + if (IntvMap[i] < NumGlobalIntvs) { if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks << " blocks as original.\n"); @@ -1016,11 +1073,23 @@ unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl &NewVRegs) { - float BestCost = Hysteresis * calcSpillCost(); - DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n'); - const unsigned NoCand = ~0u; - unsigned BestCand = NoCand; unsigned NumCands = 0; + unsigned BestCand = NoCand; + float BestCost; + SmallVector UsedCands; + + // Check if we can split this live range around a compact region. + bool HasCompact = CompactRegions && calcCompactRegion(GlobalCand.front()); + if (HasCompact) { + // Yes, keep GlobalCand[0] as the compact region candidate. + NumCands = 1; + BestCost = HUGE_VALF; + } else { + // No benefit from the compact region, our fallback will be per-block + // splitting. Make sure we find a solution that is cheaper than spilling. + BestCost = Hysteresis * calcSpillCost(); + DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n'); + } Order.rewind(); while (unsigned PhysReg = Order.next()) { @@ -1030,7 +1099,7 @@ unsigned WorstCount = ~0u; unsigned Worst = 0; for (unsigned i = 0; i != NumCands; ++i) { - if (i == BestCand) + if (i == BestCand || !GlobalCand[i].PhysReg) continue; unsigned Count = GlobalCand[i].LiveBundles.count(); if (Count < WorstCount) @@ -1087,10 +1156,41 @@ ++NumCands; } - if (BestCand == NoCand) + // No solutions found, fall back to single block splitting. + if (!HasCompact && BestCand == NoCand) return 0; - splitAroundRegion(VirtReg, GlobalCand[BestCand], NewVRegs); + // Prepare split editor. + LiveRangeEdit LREdit(VirtReg, NewVRegs, this); + SE->reset(LREdit); + + // Assign all edge bundles to the preferred candidate, or NoCand. + BundleCand.assign(Bundles->getNumBundles(), NoCand); + + // Assign bundles for the best candidate region. + if (BestCand != NoCand) { + GlobalSplitCandidate &Cand = GlobalCand[BestCand]; + if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { + UsedCands.push_back(BestCand); + Cand.IntvIdx = SE->openIntv(); + DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " + << B << " bundles, intv " << Cand.IntvIdx << ".\n"); + } + } + + // Assign bundles for the compact region. + if (HasCompact) { + GlobalSplitCandidate &Cand = GlobalCand.front(); + assert(!Cand.PhysReg && "Compact region has no physreg"); + if (unsigned B = Cand.getBundles(BundleCand, 0)) { + UsedCands.push_back(0); + Cand.IntvIdx = SE->openIntv(); + DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv " + << Cand.IntvIdx << ".\n"); + } + } + + splitAroundRegion(LREdit, UsedCands); return 0; } @@ -1479,6 +1579,7 @@ ExtraRegInfo.resize(MRI->getNumVirtRegs()); NextCascade = 1; IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI); + GlobalCand.resize(32); // This will grow as needed. allocatePhysRegs(); addMBBLiveIns(MF); From evan.cheng at apple.com Tue Jul 26 18:46:58 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 16:46:58 -0700 Subject: [llvm-commits] [llvm] r135760 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt lib/Support/TargetRegistry.cpp lib/Target/CMakeLists.txt lib/Target/TargetRegistry.cpp In-Reply-To: <20110722081654.11A932A6C12E@llvm.org> References: <20110722081654.11A932A6C12E@llvm.org> Message-ID: <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> Hi Chandler, Sorry I missed this earlier. I don't think this is the right change. TargetRegistry is used by everything including those tools which don't need Target library e.g. llvm-mc. If you wish for consistency, the right fix is to move TargetRegistry.h to Support. But to do that, you would need to move Reloc::Model and CodeModel::Model out of MCCodeGenInfo.h first. We can't have something in Support that reference MC. Evan On Jul 22, 2011, at 1:16 AM, Chandler Carruth wrote: > Author: chandlerc > Date: Fri Jul 22 03:16:53 2011 > New Revision: 135760 > > URL: http://llvm.org/viewvc/llvm-project?rev=135760&view=rev > Log: > Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. > The header file was already properly located. The previous need for it > in Support had to do with the version string printing which was fixed in > r135757. > > Also update build dependencies where libraries that needed the > functionality of the Target library (in the form of the TargetRegistry) > were picking it up via Support. This is pretty pervasive, essentially > every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it > depend on Target. All of these were previously just sneaking by. > > Added: > llvm/trunk/lib/Target/TargetRegistry.cpp > - copied, changed from r135759, llvm/trunk/lib/Support/TargetRegistry.cpp > Removed: > llvm/trunk/lib/Support/TargetRegistry.cpp > Modified: > llvm/trunk/cmake/modules/LLVMLibDeps.cmake > llvm/trunk/lib/Support/CMakeLists.txt > llvm/trunk/lib/Target/CMakeLists.txt > > Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=135760&r1=135759&r2=135760&view=diff > ============================================================================== > --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) > +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jul 22 03:16:53 2011 > @@ -3,10 +3,10 @@ > set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMAlphaDesc LLVMAlphaInfo LLVMMC) > -set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport) > set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) > @@ -15,16 +15,16 @@ > set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) > set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMAsmPrinter LLVMBlackfinDesc LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMBlackfinDesc LLVMBlackfinInfo LLVMMC) > -set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > -set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUDesc LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMCellSPUDesc LLVMCellSPUInfo LLVMMC) > -set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) > set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) > -set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMTarget) > set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils) > set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMTransformUtils) > @@ -36,37 +36,37 @@ > set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC) > -set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo) > +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo) > set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info) > -set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) > set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMPTXDesc LLVMMC LLVMPTXInfo LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport) > set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils) > set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMTransformUtils) > set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMSparcDesc LLVMMC LLVMSparcInfo LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMSupport ) > set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget) > set(MSVC_LIB_DEPS_LLVMSystemZDesc LLVMMC LLVMSystemZInfo) > -set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) > set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) > set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) > @@ -74,10 +74,10 @@ > set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) > set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info) > set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) > -set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) > set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreDesc LLVMXCoreInfo) > set(MSVC_LIB_DEPS_LLVMXCoreDesc LLVMMC LLVMXCoreInfo) > -set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport) > +set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport LLVMTarget) > set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport) > set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) > > Modified: llvm/trunk/lib/Support/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > ============================================================================== > --- llvm/trunk/lib/Support/CMakeLists.txt (original) > +++ llvm/trunk/lib/Support/CMakeLists.txt Fri Jul 22 03:16:53 2011 > @@ -42,7 +42,6 @@ > StringPool.cpp > StringRef.cpp > SystemUtils.cpp > - TargetRegistry.cpp > Timer.cpp > ToolOutputFile.cpp > Triple.cpp > > Removed: llvm/trunk/lib/Support/TargetRegistry.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=135759&view=auto > ============================================================================== > --- llvm/trunk/lib/Support/TargetRegistry.cpp (original) > +++ llvm/trunk/lib/Support/TargetRegistry.cpp (removed) > @@ -1,122 +0,0 @@ > -//===--- TargetRegistry.cpp - Target registration -------------------------===// > -// > -// The LLVM Compiler Infrastructure > -// > -// This file is distributed under the University of Illinois Open Source > -// License. See LICENSE.TXT for details. > -// > -//===----------------------------------------------------------------------===// > - > -#include "llvm/ADT/STLExtras.h" > -#include "llvm/ADT/StringRef.h" > -#include "llvm/Target/TargetRegistry.h" > -#include "llvm/Support/Host.h" > -#include "llvm/Support/raw_ostream.h" > -#include > -#include > -using namespace llvm; > - > -// Clients are responsible for avoid race conditions in registration. > -static Target *FirstTarget = 0; > - > -TargetRegistry::iterator TargetRegistry::begin() { > - return iterator(FirstTarget); > -} > - > -const Target *TargetRegistry::lookupTarget(const std::string &TT, > - std::string &Error) { > - // Provide special warning when no targets are initialized. > - if (begin() == end()) { > - Error = "Unable to find target for this triple (no targets are registered)"; > - return 0; > - } > - const Target *Best = 0, *EquallyBest = 0; > - unsigned BestQuality = 0; > - for (iterator it = begin(), ie = end(); it != ie; ++it) { > - if (unsigned Qual = it->TripleMatchQualityFn(TT)) { > - if (!Best || Qual > BestQuality) { > - Best = &*it; > - EquallyBest = 0; > - BestQuality = Qual; > - } else if (Qual == BestQuality) > - EquallyBest = &*it; > - } > - } > - > - if (!Best) { > - Error = "No available targets are compatible with this triple, " > - "see -version for the available targets."; > - return 0; > - } > - > - // Otherwise, take the best target, but make sure we don't have two equally > - // good best targets. > - if (EquallyBest) { > - Error = std::string("Cannot choose between targets \"") + > - Best->Name + "\" and \"" + EquallyBest->Name + "\""; > - return 0; > - } > - > - return Best; > -} > - > -void TargetRegistry::RegisterTarget(Target &T, > - const char *Name, > - const char *ShortDesc, > - Target::TripleMatchQualityFnTy TQualityFn, > - bool HasJIT) { > - assert(Name && ShortDesc && TQualityFn && > - "Missing required target information!"); > - > - // Check if this target has already been initialized, we allow this as a > - // convenience to some clients. > - if (T.Name) > - return; > - > - // Add to the list of targets. > - T.Next = FirstTarget; > - FirstTarget = &T; > - > - T.Name = Name; > - T.ShortDesc = ShortDesc; > - T.TripleMatchQualityFn = TQualityFn; > - T.HasJIT = HasJIT; > -} > - > -const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) { > - const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); > - > - if (TheTarget && !TheTarget->hasJIT()) { > - Error = "No JIT compatible target available for this host"; > - return 0; > - } > - > - return TheTarget; > -} > - > -static int TargetArraySortFn(const void *LHS, const void *RHS) { > - typedef std::pair pair_ty; > - return ((const pair_ty*)LHS)->first.compare(((const pair_ty*)RHS)->first); > -} > - > -void TargetRegistry::printRegisteredTargetsForVersion() { > - std::vector > Targets; > - size_t Width = 0; > - for (TargetRegistry::iterator I = TargetRegistry::begin(), > - E = TargetRegistry::end(); > - I != E; ++I) { > - Targets.push_back(std::make_pair(I->getName(), &*I)); > - Width = std::max(Width, Targets.back().first.size()); > - } > - array_pod_sort(Targets.begin(), Targets.end(), TargetArraySortFn); > - > - raw_ostream &OS = outs(); > - OS << " Registered Targets:\n"; > - for (unsigned i = 0, e = Targets.size(); i != e; ++i) { > - OS << " " << Targets[i].first; > - OS.indent(Width - Targets[i].first.size()) << " - " > - << Targets[i].second->getShortDescription() << '\n'; > - } > - if (Targets.empty()) > - OS << " (none)\n"; > -} > > Modified: llvm/trunk/lib/Target/CMakeLists.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CMakeLists.txt (original) > +++ llvm/trunk/lib/Target/CMakeLists.txt Fri Jul 22 03:16:53 2011 > @@ -11,6 +11,7 @@ > TargetLoweringObjectFile.cpp > TargetMachine.cpp > TargetRegisterInfo.cpp > + TargetRegistry.cpp > TargetSubtargetInfo.cpp > ) > > > Copied: llvm/trunk/lib/Target/TargetRegistry.cpp (from r135759, llvm/trunk/lib/Support/TargetRegistry.cpp) > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegistry.cpp?p2=llvm/trunk/lib/Target/TargetRegistry.cpp&p1=llvm/trunk/lib/Support/TargetRegistry.cpp&r1=135759&r2=135760&rev=135760&view=diff > ============================================================================== > (empty) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Tue Jul 26 18:49:39 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 26 Jul 2011 23:49:39 -0000 Subject: [llvm-commits] [llvm] r136191 - /llvm/trunk/test/FrontendC/ Message-ID: <20110726234939.A67882A6C12C@llvm.org> Author: echristo Date: Tue Jul 26 18:49:39 2011 New Revision: 136191 URL: http://llvm.org/viewvc/llvm-project?rev=136191&view=rev Log: Remove test/FrontendC, almost all of the tests have been migrated to clang now, the rest are in process (6) or have been deleted. Removed: llvm/trunk/test/FrontendC/ From echristo at apple.com Tue Jul 26 18:51:08 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 26 Jul 2011 16:51:08 -0700 Subject: [llvm-commits] [llvm] r135342 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c In-Reply-To: <0169808D-6F76-4047-8E4F-248D1CA56222@apple.com> References: <20110716072835.BDAC72A6C12C@llvm.org> <219B41AE-4EC9-45A6-8014-E52311FD278A@apple.com> <04584A21-9481-4179-AB3D-B2E4A8D53123@apple.com> <443EBCCB-7E7F-4CA4-9924-043099FDFFAD@apple.com> <52725BD3-8C7A-41CE-98C1-B1A4FA90FC5E@apple.com> <56D1490B-E531-4904-8BD7-881C8A02D857@apple.com> <0169808D-6F76-4047-8E4F-248D1CA56222@apple.com> Message-ID: <9C4F26AE-343A-44E5-8F45-95BC53390EC2@apple.com> On Jul 19, 2011, at 7:08 PM, Chris Lattner wrote: > > On Jul 19, 2011, at 2:26 PM, Eric Christopher wrote: > >>> The Frontend* tests? Totally. A few of them will need to be changed for the different codegen, but that's not a problem and will make running "make check" for llvm way less annoying. >> >> FWIW I'm doing this now. I'm removing (not migrating) the tests that seem to test gcc front end things instead of clang front end things or where I'm positive we have a clang test already. > > Fantastic, thanks a lot Eric! FrontendC is gone. Now just C++, ObjC and ObjC++. -eric From chandlerc at gmail.com Tue Jul 26 19:06:53 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 26 Jul 2011 17:06:53 -0700 Subject: [llvm-commits] [llvm] r135760 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt lib/Support/TargetRegistry.cpp lib/Target/CMakeLists.txt lib/Target/TargetRegistry.cpp In-Reply-To: <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> References: <20110722081654.11A932A6C12E@llvm.org> <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> Message-ID: On Tue, Jul 26, 2011 at 4:46 PM, Evan Cheng wrote: > Hi Chandler, > > Sorry I missed this earlier. I don't think this is the right change. No problem, I'm open to any suggestions you have here. Without this change, lots of weird stuff broke due to the Support -> Target -> MC include chain that existed prior, that was my only motivation for making it at all. > TargetRegistry is used by everything including those tools which don't need > Target library e.g. llvm-mc. > Hrm, is there a better name for it? TargetRegistry seems very confusing for something that shouldn't live in Target. > If you wish for consistency, the right fix is to move TargetRegistry.h to > Support. But to do that, you would need to move Reloc::Model and > CodeModel::Model out of MCCodeGenInfo.h first. We can't have something in > Support that reference MC. > I don't have any strong feelings here. Is Support the correct logical home for the registry? (Is it more like the TargetedPlatformRegistry? maybe s/Platform/Architecture/ or Backend something...) If so, what would be required (in brief) to move these pieces to support? I'm happy to take a look at fixing them once I have an idea of what you'd like these to look like. =D > > Evan > > On Jul 22, 2011, at 1:16 AM, Chandler Carruth wrote: > > > Author: chandlerc > > Date: Fri Jul 22 03:16:53 2011 > > New Revision: 135760 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=135760&view=rev > > Log: > > Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. > > The header file was already properly located. The previous need for it > > in Support had to do with the version string printing which was fixed in > > r135757. > > > > Also update build dependencies where libraries that needed the > > functionality of the Target library (in the form of the TargetRegistry) > > were picking it up via Support. This is pretty pervasive, essentially > > every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it > > depend on Target. All of these were previously just sneaking by. > > > > Added: > > llvm/trunk/lib/Target/TargetRegistry.cpp > > - copied, changed from r135759, > llvm/trunk/lib/Support/TargetRegistry.cpp > > Removed: > > llvm/trunk/lib/Support/TargetRegistry.cpp > > Modified: > > llvm/trunk/cmake/modules/LLVMLibDeps.cmake > > llvm/trunk/lib/Support/CMakeLists.txt > > llvm/trunk/lib/Target/CMakeLists.txt > > > > Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=135760&r1=135759&r2=135760&view=diff > > > ============================================================================== > > --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) > > +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jul 22 03:16:53 2011 > > @@ -3,10 +3,10 @@ > > set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc > LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC > LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC > LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo > LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAlphaDesc LLVMAlphaInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) > > @@ -15,16 +15,16 @@ > > set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMAsmPrinter LLVMBlackfinDesc > LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMBlackfinDesc LLVMBlackfinInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen > LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > > -set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUDesc > LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCellSPUDesc LLVMCellSPUInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts > LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport > LLVMTarget) > > -set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMMC LLVMSupport > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport > LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport > LLVMTransformUtils) > > @@ -36,37 +36,37 @@ > > set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG > LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc > LLVMMBlazeInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen > LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc > LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo > LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc > LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser > LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo > LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info > LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc > LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo > LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen > LLVMSystemZDesc LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc > LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc > LLVMXCoreInfo) > > +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen > LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc > LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo > LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc > LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser > LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo > LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info > LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc > LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo > LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen > LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86CodeGen > LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc > LLVMXCoreInfo) > > set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld > LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG > LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info) > > -set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG > LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen > LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPTXDesc LLVMMC LLVMPTXInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter > LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc > LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine > LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore > LLVMMC LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMC LLVMSelectionDAG LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSparcDesc LLVMMC LLVMSparcInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSupport ) > > set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZDesc LLVMSystemZInfo > LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSystemZDesc LLVMMC LLVMSystemZInfo) > > -set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport > LLVMTarget LLVMipa) > > set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport > LLVMTarget LLVMX86Info) > > @@ -74,10 +74,10 @@ > > set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen > LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter > LLVMX86Desc LLVMX86Info LLVMX86Utils) > > set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info) > > set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) > > -set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore > LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreDesc LLVMXCoreInfo) > > set(MSVC_LIB_DEPS_LLVMXCoreDesc LLVMMC LLVMXCoreInfo) > > -set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts > LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) > > > > Modified: llvm/trunk/lib/Support/CMakeLists.txt > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > > > ============================================================================== > > --- llvm/trunk/lib/Support/CMakeLists.txt (original) > > +++ llvm/trunk/lib/Support/CMakeLists.txt Fri Jul 22 03:16:53 2011 > > @@ -42,7 +42,6 @@ > > StringPool.cpp > > StringRef.cpp > > SystemUtils.cpp > > - TargetRegistry.cpp > > Timer.cpp > > ToolOutputFile.cpp > > Triple.cpp > > > > Removed: llvm/trunk/lib/Support/TargetRegistry.cpp > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=135759&view=auto > > > ============================================================================== > > --- llvm/trunk/lib/Support/TargetRegistry.cpp (original) > > +++ llvm/trunk/lib/Support/TargetRegistry.cpp (removed) > > @@ -1,122 +0,0 @@ > > -//===--- TargetRegistry.cpp - Target registration > -------------------------===// > > -// > > -// The LLVM Compiler Infrastructure > > -// > > -// This file is distributed under the University of Illinois Open Source > > -// License. See LICENSE.TXT for details. > > -// > > > -//===----------------------------------------------------------------------===// > > - > > -#include "llvm/ADT/STLExtras.h" > > -#include "llvm/ADT/StringRef.h" > > -#include "llvm/Target/TargetRegistry.h" > > -#include "llvm/Support/Host.h" > > -#include "llvm/Support/raw_ostream.h" > > -#include > > -#include > > -using namespace llvm; > > - > > -// Clients are responsible for avoid race conditions in registration. > > -static Target *FirstTarget = 0; > > - > > -TargetRegistry::iterator TargetRegistry::begin() { > > - return iterator(FirstTarget); > > -} > > - > > -const Target *TargetRegistry::lookupTarget(const std::string &TT, > > - std::string &Error) { > > - // Provide special warning when no targets are initialized. > > - if (begin() == end()) { > > - Error = "Unable to find target for this triple (no targets are > registered)"; > > - return 0; > > - } > > - const Target *Best = 0, *EquallyBest = 0; > > - unsigned BestQuality = 0; > > - for (iterator it = begin(), ie = end(); it != ie; ++it) { > > - if (unsigned Qual = it->TripleMatchQualityFn(TT)) { > > - if (!Best || Qual > BestQuality) { > > - Best = &*it; > > - EquallyBest = 0; > > - BestQuality = Qual; > > - } else if (Qual == BestQuality) > > - EquallyBest = &*it; > > - } > > - } > > - > > - if (!Best) { > > - Error = "No available targets are compatible with this triple, " > > - "see -version for the available targets."; > > - return 0; > > - } > > - > > - // Otherwise, take the best target, but make sure we don't have two > equally > > - // good best targets. > > - if (EquallyBest) { > > - Error = std::string("Cannot choose between targets \"") + > > - Best->Name + "\" and \"" + EquallyBest->Name + "\""; > > - return 0; > > - } > > - > > - return Best; > > -} > > - > > -void TargetRegistry::RegisterTarget(Target &T, > > - const char *Name, > > - const char *ShortDesc, > > - Target::TripleMatchQualityFnTy > TQualityFn, > > - bool HasJIT) { > > - assert(Name && ShortDesc && TQualityFn && > > - "Missing required target information!"); > > - > > - // Check if this target has already been initialized, we allow this as > a > > - // convenience to some clients. > > - if (T.Name) > > - return; > > - > > - // Add to the list of targets. > > - T.Next = FirstTarget; > > - FirstTarget = &T; > > - > > - T.Name = Name; > > - T.ShortDesc = ShortDesc; > > - T.TripleMatchQualityFn = TQualityFn; > > - T.HasJIT = HasJIT; > > -} > > - > > -const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) > { > > - const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); > > - > > - if (TheTarget && !TheTarget->hasJIT()) { > > - Error = "No JIT compatible target available for this host"; > > - return 0; > > - } > > - > > - return TheTarget; > > -} > > - > > -static int TargetArraySortFn(const void *LHS, const void *RHS) { > > - typedef std::pair pair_ty; > > - return ((const pair_ty*)LHS)->first.compare(((const > pair_ty*)RHS)->first); > > -} > > - > > -void TargetRegistry::printRegisteredTargetsForVersion() { > > - std::vector > Targets; > > - size_t Width = 0; > > - for (TargetRegistry::iterator I = TargetRegistry::begin(), > > - E = TargetRegistry::end(); > > - I != E; ++I) { > > - Targets.push_back(std::make_pair(I->getName(), &*I)); > > - Width = std::max(Width, Targets.back().first.size()); > > - } > > - array_pod_sort(Targets.begin(), Targets.end(), TargetArraySortFn); > > - > > - raw_ostream &OS = outs(); > > - OS << " Registered Targets:\n"; > > - for (unsigned i = 0, e = Targets.size(); i != e; ++i) { > > - OS << " " << Targets[i].first; > > - OS.indent(Width - Targets[i].first.size()) << " - " > > - << Targets[i].second->getShortDescription() << '\n'; > > - } > > - if (Targets.empty()) > > - OS << " (none)\n"; > > -} > > > > Modified: llvm/trunk/lib/Target/CMakeLists.txt > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > > > ============================================================================== > > --- llvm/trunk/lib/Target/CMakeLists.txt (original) > > +++ llvm/trunk/lib/Target/CMakeLists.txt Fri Jul 22 03:16:53 2011 > > @@ -11,6 +11,7 @@ > > TargetLoweringObjectFile.cpp > > TargetMachine.cpp > > TargetRegisterInfo.cpp > > + TargetRegistry.cpp > > TargetSubtargetInfo.cpp > > ) > > > > > > Copied: llvm/trunk/lib/Target/TargetRegistry.cpp (from r135759, > llvm/trunk/lib/Support/TargetRegistry.cpp) > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegistry.cpp?p2=llvm/trunk/lib/Target/TargetRegistry.cpp&p1=llvm/trunk/lib/Support/TargetRegistry.cpp&r1=135759&r2=135760&rev=135760&view=diff > > > ============================================================================== > > (empty) > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110726/7e8dc4c6/attachment-0001.html From echristo at apple.com Tue Jul 26 19:07:56 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 27 Jul 2011 00:07:56 -0000 Subject: [llvm-commits] [llvm] r136193 - in /llvm/trunk/test: FrontendAda/ FrontendFortran/ Message-ID: <20110727000756.A53AB2A6C12C@llvm.org> Author: echristo Date: Tue Jul 26 19:07:56 2011 New Revision: 136193 URL: http://llvm.org/viewvc/llvm-project?rev=136193&view=rev Log: Remove these two directories. The tests can be ported to dragonegg if they're still wanted. Removed: llvm/trunk/test/FrontendAda/ llvm/trunk/test/FrontendFortran/ From dpatel at apple.com Tue Jul 26 19:34:13 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 27 Jul 2011 00:34:13 -0000 Subject: [llvm-commits] [llvm] r136196 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfDebug.cpp test/CodeGen/X86/dbg-inline.ll Message-ID: <20110727003413.E219E2A6C12C@llvm.org> Author: dpatel Date: Tue Jul 26 19:34:13 2011 New Revision: 136196 URL: http://llvm.org/viewvc/llvm-project?rev=136196&view=rev Log: It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. Added: llvm/trunk/test/CodeGen/X86/dbg-inline.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=136196&r1=136195&r2=136196&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jul 26 19:34:13 2011 @@ -565,10 +565,17 @@ assert (Ranges.empty() == false && "DbgScope does not have instruction markers!"); - // FIXME : .debug_inlined section specification does not clearly state how - // to emit inlined scope that is split into multiple instruction ranges. - // For now, use first instruction range and emit low_pc/high_pc pair and - // corresponding .debug_inlined section entry for this pair. + if (!Scope->getScopeNode()) + return NULL; + DIScope DS(Scope->getScopeNode()); + DISubprogram InlinedSP = getDISubprogram(DS); + CompileUnit *TheCU = getCompileUnit(InlinedSP); + DIE *OriginDIE = TheCU->getDIE(InlinedSP); + if (!OriginDIE) { + DEBUG(dbgs() << "Unable to find original DIE for inlined subprogram."); + return NULL; + } + SmallVector::const_iterator RI = Ranges.begin(); const MCSymbol *StartLabel = getLabelBeforeInsn(RI->first); const MCSymbol *EndLabel = getLabelAfterInsn(RI->second); @@ -582,26 +589,35 @@ assert(EndLabel->isDefined() && "Invalid end label for an inlined scope!"); - if (!Scope->getScopeNode()) - return NULL; - DIScope DS(Scope->getScopeNode()); - DISubprogram InlinedSP = getDISubprogram(DS); - CompileUnit *TheCU = getCompileUnit(InlinedSP); - DIE *OriginDIE = TheCU->getDIE(InlinedSP); - if (!OriginDIE) { - DEBUG(dbgs() << "Unable to find original DIE for inlined subprogram."); - return NULL; - } DIE *ScopeDIE = new DIE(dwarf::DW_TAG_inlined_subroutine); TheCU->addDIEEntry(ScopeDIE, dwarf::DW_AT_abstract_origin, dwarf::DW_FORM_ref4, OriginDIE); - TheCU->addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, StartLabel); - TheCU->addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, EndLabel); + if (Ranges.size() > 1) { + // .debug_range section has not been laid out yet. Emit offset in + // .debug_range as a uint, size 4, for now. emitDIE will handle + // DW_AT_ranges appropriately. + TheCU->addUInt(ScopeDIE, dwarf::DW_AT_ranges, dwarf::DW_FORM_data4, + DebugRangeSymbols.size() * Asm->getTargetData().getPointerSize()); + for (SmallVector::const_iterator RI = Ranges.begin(), + RE = Ranges.end(); RI != RE; ++RI) { + DebugRangeSymbols.push_back(getLabelBeforeInsn(RI->first)); + DebugRangeSymbols.push_back(getLabelAfterInsn(RI->second)); + } + DebugRangeSymbols.push_back(NULL); + DebugRangeSymbols.push_back(NULL); + } else { + TheCU->addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, StartLabel); + TheCU->addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, EndLabel); + } InlinedSubprogramDIEs.insert(OriginDIE); // Track the start label for this inlined function. + //.debug_inlined section specification does not clearly state how + // to emit inlined scope that is split into multiple instruction ranges. + // For now, use first instruction range and emit low_pc/high_pc pair and + // corresponding .debug_inlined section entry for this pair. DenseMap >::iterator I = InlineInfo.find(InlinedSP); @@ -1641,12 +1657,21 @@ WorkStack.push_back(ChildScope); visitedChildren = true; ChildScope->setDFSIn(++Counter); +#ifndef NDEBUG + if (PrintDbgScope) + dbgs() << "calculate dbgscope dom: In " << Counter << "\n"; +#endif break; } } if (!visitedChildren) { WorkStack.pop_back(); WS->setDFSOut(++Counter); +#ifndef NDEBUG + if (PrintDbgScope) + dbgs() << "calculate dbgscope dom: In " << WS->getDFSIn() + << " Out " << Counter << "\n"; +#endif } } } Added: llvm/trunk/test/CodeGen/X86/dbg-inline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-inline.ll?rev=136196&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-inline.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-inline.ll Tue Jul 26 19:34:13 2011 @@ -0,0 +1,140 @@ +; RUN: llc < %s | FileCheck %s +; Radar 7881628, 9747970 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.0" + +%class.APFloat = type { i32 } + +define i32 @_ZNK7APFloat9partCountEv(%class.APFloat* nocapture %this) nounwind uwtable readonly optsize ssp align 2 { +entry: + tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !28), !dbg !41 + %prec = getelementptr inbounds %class.APFloat* %this, i64 0, i32 0, !dbg !42 + %tmp = load i32* %prec, align 4, !dbg !42, !tbaa !44 + tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !47), !dbg !48 + %add.i = add i32 %tmp, 42, !dbg !49 + ret i32 %add.i, !dbg !42 +} + +define zeroext i1 @_ZNK7APFloat14bitwiseIsEqualERKS_(%class.APFloat* %this, %class.APFloat* %rhs) uwtable optsize ssp align 2 { +entry: + tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !29), !dbg !51 + tail call void @llvm.dbg.value(metadata !{%class.APFloat* %rhs}, i64 0, metadata !30), !dbg !52 + tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !53), !dbg !55 + %prec.i = getelementptr inbounds %class.APFloat* %this, i64 0, i32 0, !dbg !56 +;CHECK: DW_TAG_inlined_subroutine +;CHECK: DW_AT_abstract_origin +;CHECK: DW_AT_ranges + %tmp.i = load i32* %prec.i, align 4, !dbg !56, !tbaa !44 + tail call void @llvm.dbg.value(metadata !{i32 %tmp.i}, i64 0, metadata !57), !dbg !58 + %add.i.i = add i32 %tmp.i, 42, !dbg !59 + tail call void @llvm.dbg.value(metadata !{i32 %add.i.i}, i64 0, metadata !31), !dbg !54 + %call2 = tail call i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat* %this) optsize, !dbg !60 + tail call void @llvm.dbg.value(metadata !{i64* %call2}, i64 0, metadata !34), !dbg !60 + %call3 = tail call i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat* %rhs) optsize, !dbg !61 + tail call void @llvm.dbg.value(metadata !{i64* %call3}, i64 0, metadata !37), !dbg !61 + %tmp = zext i32 %add.i.i to i64 + br label %for.cond, !dbg !62 + +for.cond: ; preds = %for.inc, %entry + %indvar = phi i64 [ %indvar.next, %for.inc ], [ 0, %entry ] + %tmp13 = sub i64 %tmp, %indvar, !dbg !62 + %i.0 = trunc i64 %tmp13 to i32, !dbg !62 + %cmp = icmp sgt i32 %i.0, 0, !dbg !62 + br i1 %cmp, label %for.body, label %return, !dbg !62 + +for.body: ; preds = %for.cond + %p.0 = getelementptr i64* %call2, i64 %indvar, !dbg !63 + %tmp6 = load i64* %p.0, align 8, !dbg !63, !tbaa !66 + %tmp8 = load i64* %call3, align 8, !dbg !63, !tbaa !66 + %cmp9 = icmp eq i64 %tmp6, %tmp8, !dbg !63 + br i1 %cmp9, label %for.inc, label %return, !dbg !63 + +for.inc: ; preds = %for.body + %indvar.next = add i64 %indvar, 1, !dbg !67 + br label %for.cond, !dbg !67 + +return: ; preds = %for.cond, %for.body + %retval.0 = phi i1 [ false, %for.body ], [ true, %for.cond ] + ret i1 %retval.0, !dbg !68 +} + +declare i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat*) optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !7, !12, !23, !24, !25} +!llvm.dbg.lv._ZNK7APFloat9partCountEv = !{!28} +!llvm.dbg.lv._ZNK7APFloat14bitwiseIsEqualERKS_ = !{!29, !30, !31, !34, !37} +!llvm.dbg.lv._ZL16partCountForBitsj = !{!38} +!llvm.dbg.gv = !{!39} + +!0 = metadata !{i32 655377, i32 0, i32 4, metadata !"/Volumes/Athwagate/R9747970/apf.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 136149)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 655406, i32 0, metadata !2, metadata !"bitwiseIsEqual", metadata !"bitwiseIsEqual", metadata !"_ZNK7APFloat14bitwiseIsEqualERKS_", metadata !3, i32 8, metadata !19, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 655362, metadata !0, metadata !"APFloat", metadata !3, i32 6, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] +!3 = metadata !{i32 655401, metadata !"/Volumes/Athwagate/R9747970/apf.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !5, metadata !1, metadata !7, metadata !12} +!5 = metadata !{i32 655373, metadata !2, metadata !"prec", metadata !3, i32 13, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 655396, metadata !0, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 655406, i32 0, metadata !2, metadata !"partCount", metadata !"partCount", metadata !"_ZNK7APFloat9partCountEv", metadata !3, i32 9, metadata !8, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!9 = metadata !{metadata !6, metadata !10} +!10 = metadata !{i32 655375, metadata !0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !11} ; [ DW_TAG_pointer_type ] +!11 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!12 = metadata !{i32 655406, i32 0, metadata !2, metadata !"significandParts", metadata !"significandParts", metadata !"_ZNK7APFloat16significandPartsEv", metadata !3, i32 11, metadata !13, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!14 = metadata !{metadata !15, metadata !10} +!15 = metadata !{i32 655375, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ] +!16 = metadata !{i32 655382, metadata !0, metadata !"integerPart", metadata !3, i32 2, i64 0, i64 0, i64 0, i32 0, metadata !17} ; [ DW_TAG_typedef ] +!17 = metadata !{i32 655382, metadata !0, metadata !"uint64_t", metadata !3, i32 1, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_typedef ] +!18 = metadata !{i32 655396, metadata !0, metadata !"long long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!19 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !20, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!20 = metadata !{metadata !21, metadata !10, metadata !22} +!21 = metadata !{i32 655396, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!22 = metadata !{i32 655376, metadata !0, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_reference_type ] +!23 = metadata !{i32 655406, i32 0, metadata !0, metadata !"partCount", metadata !"partCount", metadata !"_ZNK7APFloat9partCountEv", metadata !3, i32 23, metadata !8, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%class.APFloat*)* @_ZNK7APFloat9partCountEv, null, metadata !7} ; [ DW_TAG_subprogram ] +!24 = metadata !{i32 655406, i32 0, metadata !0, metadata !"bitwiseIsEqual", metadata !"bitwiseIsEqual", metadata !"_ZNK7APFloat14bitwiseIsEqualERKS_", metadata !3, i32 28, metadata !19, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (%class.APFloat*, %class.APFloat*)* @_ZNK7APFloat14bitwiseIsEqualERKS_, null, metadata !1} ; [ DW_TAG_subprogram ] +!25 = metadata !{i32 655406, i32 0, metadata !3, metadata !"partCountForBits", metadata !"partCountForBits", metadata !"", metadata !3, i32 17, metadata !26, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null} ; [ DW_TAG_subprogram ] +!26 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !27, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!27 = metadata !{metadata !6} +!28 = metadata !{i32 655617, metadata !23, metadata !"this", metadata !3, i32 16777238, metadata !10, i32 64, i32 0} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 655617, metadata !24, metadata !"this", metadata !3, i32 16777244, metadata !10, i32 64, i32 0} ; [ DW_TAG_arg_variable ] +!30 = metadata !{i32 655617, metadata !24, metadata !"rhs", metadata !3, i32 33554460, metadata !22, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!31 = metadata !{i32 655616, metadata !32, metadata !"i", metadata !3, i32 29, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ] +!32 = metadata !{i32 655371, metadata !24, i32 28, i32 56, metadata !3, i32 1} ; [ DW_TAG_lexical_block ] +!33 = metadata !{i32 655396, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!34 = metadata !{i32 655616, metadata !32, metadata !"p", metadata !3, i32 30, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ] +!35 = metadata !{i32 655375, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !36} ; [ DW_TAG_pointer_type ] +!36 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !16} ; [ DW_TAG_const_type ] +!37 = metadata !{i32 655616, metadata !32, metadata !"q", metadata !3, i32 31, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ] +!38 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!39 = metadata !{i32 655412, i32 0, metadata !3, metadata !"integerPartWidth", metadata !"integerPartWidth", metadata !"integerPartWidth", metadata !3, i32 3, metadata !40, i32 1, i32 1, i32 42} ; [ DW_TAG_variable ] +!40 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_const_type ] +!41 = metadata !{i32 22, i32 23, metadata !23, null} +!42 = metadata !{i32 24, i32 10, metadata !43, null} +!43 = metadata !{i32 655371, metadata !23, i32 23, i32 1, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] +!44 = metadata !{metadata !"int", metadata !45} +!45 = metadata !{metadata !"omnipotent char", metadata !46} +!46 = metadata !{metadata !"Simple C/C++ TBAA", null} +!47 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, metadata !42} ; [ DW_TAG_arg_variable ] +!48 = metadata !{i32 16, i32 58, metadata !25, metadata !42} +!49 = metadata !{i32 18, i32 3, metadata !50, metadata !42} +!50 = metadata !{i32 655371, metadata !25, i32 17, i32 1, metadata !3, i32 4} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 28, i32 15, metadata !24, null} +!52 = metadata !{i32 28, i32 45, metadata !24, null} +!53 = metadata !{i32 655617, metadata !23, metadata !"this", metadata !3, i32 16777238, metadata !10, i32 64, metadata !54} ; [ DW_TAG_arg_variable ] +!54 = metadata !{i32 29, i32 10, metadata !32, null} +!55 = metadata !{i32 22, i32 23, metadata !23, metadata !54} +!56 = metadata !{i32 24, i32 10, metadata !43, metadata !54} +!57 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, metadata !56} ; [ DW_TAG_arg_variable ] +!58 = metadata !{i32 16, i32 58, metadata !25, metadata !56} +!59 = metadata !{i32 18, i32 3, metadata !50, metadata !56} +!60 = metadata !{i32 30, i32 24, metadata !32, null} +!61 = metadata !{i32 31, i32 24, metadata !32, null} +!62 = metadata !{i32 32, i32 3, metadata !32, null} +!63 = metadata !{i32 33, i32 5, metadata !64, null} +!64 = metadata !{i32 655371, metadata !65, i32 32, i32 25, metadata !3, i32 3} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 655371, metadata !32, i32 32, i32 3, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] +!66 = metadata !{metadata !"long long", metadata !45} +!67 = metadata !{i32 32, i32 15, metadata !65, null} +!68 = metadata !{i32 37, i32 1, metadata !32, null} From evan.cheng at apple.com Tue Jul 26 19:38:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 27 Jul 2011 00:38:13 -0000 Subject: [llvm-commits] [llvm] r136197 - in /llvm/trunk: include/llvm/MC/MCAsmInfo.h include/llvm/MC/MCAsmInfoDarwin.h include/llvm/MC/MCDirectives.h lib/MC/MCAsmInfo.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCMachOStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20110727003813.45BD12A6C12C@llvm.org> Author: evancheng Date: Tue Jul 26 19:38:12 2011 New Revision: 136197 URL: http://llvm.org/viewvc/llvm-project?rev=136197&view=rev Log: Support .code32 and .code64 in X86 assembler. Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h llvm/trunk/include/llvm/MC/MCAsmInfoDarwin.h llvm/trunk/include/llvm/MC/MCDirectives.h llvm/trunk/lib/MC/MCAsmInfo.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Jul 26 19:38:12 2011 @@ -117,6 +117,13 @@ const char *InlineAsmStart; // Defaults to "#APP\n" const char *InlineAsmEnd; // Defaults to "#NO_APP\n" + /// Code16Directive, Code32Directive, Code64Directive - These are assembly + /// directives that tells the assembler to interpret the following + /// instructions differently. + const char *Code16Directive; // Defaults to ".code16" + const char *Code32Directive; // Defaults to ".code32" + const char *Code64Directive; // Defaults to ".code64" + /// AssemblerDialect - Which dialect of an assembler variant to use. unsigned AssemblerDialect; // Defaults to 0 @@ -423,6 +430,15 @@ const char *getInlineAsmEnd() const { return InlineAsmEnd; } + const char *getCode16Directive() const { + return Code16Directive; + } + const char *getCode32Directive() const { + return Code32Directive; + } + const char *getCode64Directive() const { + return Code64Directive; + } unsigned getAssemblerDialect() const { return AssemblerDialect; } Modified: llvm/trunk/include/llvm/MC/MCAsmInfoDarwin.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfoDarwin.h?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfoDarwin.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfoDarwin.h Tue Jul 26 19:38:12 2011 @@ -18,11 +18,6 @@ #include "llvm/MC/MCAsmInfo.h" namespace llvm { - class GlobalValue; - class GlobalVariable; - class Type; - class Mangler; - struct MCAsmInfoDarwin : public MCAsmInfo { explicit MCAsmInfoDarwin(); }; Modified: llvm/trunk/include/llvm/MC/MCDirectives.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDirectives.h (original) +++ llvm/trunk/include/llvm/MC/MCDirectives.h Tue Jul 26 19:38:12 2011 @@ -47,8 +47,9 @@ enum MCAssemblerFlag { MCAF_SyntaxUnified, ///< .syntax (ARM/ELF) MCAF_SubsectionsViaSymbols, ///< .subsections_via_symbols (MachO) - MCAF_Code16, ///< .code 16 - MCAF_Code32 ///< .code 32 + MCAF_Code16, ///< .code16 (X86) / .code 16 (ARM) + MCAF_Code32, ///< .code32 (X86) / .code 32 (ARM) + MCAF_Code64 ///< .code64 (X86) }; } // end namespace llvm Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Tue Jul 26 19:38:12 2011 @@ -42,6 +42,9 @@ LinkerPrivateGlobalPrefix = ""; InlineAsmStart = "APP"; InlineAsmEnd = "NO_APP"; + Code16Directive = ".code16"; + Code32Directive = ".code32"; + Code64Directive = ".code64"; AssemblerDialect = 0; AllowQuotesInName = false; AllowNameToStartWithDigit = false; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jul 26 19:38:12 2011 @@ -335,8 +335,9 @@ default: assert(0 && "Invalid flag!"); case MCAF_SyntaxUnified: OS << "\t.syntax unified"; break; case MCAF_SubsectionsViaSymbols: OS << ".subsections_via_symbols"; break; - case MCAF_Code16: OS << "\t.code\t16"; break; - case MCAF_Code32: OS << "\t.code\t32"; break; + case MCAF_Code16: OS << '\t'<< MAI.getCode16Directive(); break; + case MCAF_Code32: OS << '\t'<< MAI.getCode32Directive(); break; + case MCAF_Code64: OS << '\t'<< MAI.getCode64Directive(); break; } EmitEOL(); } Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Tue Jul 26 19:38:12 2011 @@ -53,8 +53,9 @@ void MCELFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { switch (Flag) { case MCAF_SyntaxUnified: return; // no-op here. - case MCAF_Code16: return; // no-op here. - case MCAF_Code32: return; // no-op here. + case MCAF_Code16: return; // Change parsing mode; no-op here. + case MCAF_Code32: return; // Change parsing mode; no-op here. + case MCAF_Code64: return; // Change parsing mode; no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Tue Jul 26 19:38:12 2011 @@ -143,8 +143,9 @@ // Do any generic stuff we need to do. switch (Flag) { case MCAF_SyntaxUnified: return; // no-op here. - case MCAF_Code16: return; // no-op here. - case MCAF_Code32: return; // no-op here. + case MCAF_Code16: return; // Change parsing mode; no-op here. + case MCAF_Code32: return; // Change parsing mode; no-op here. + case MCAF_Code64: return; // Change parsing mode; no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Tue Jul 26 19:38:12 2011 @@ -1146,7 +1146,7 @@ if (IDVal == ".include") return ParseDirectiveInclude(); - if (IDVal == ".code16" || IDVal == ".code32" || IDVal == ".code64") + if (IDVal == ".code16") return TokError(Twine(IDVal) + " not supported yet"); // Look up the handler in the handler table. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jul 26 19:38:12 2011 @@ -2702,13 +2702,15 @@ Parser.Lex(); if (Val == 16) { - if (!isThumb()) + if (!isThumb()) { SwitchMode(); - getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); + } } else { - if (isThumb()) + if (isThumb()) { SwitchMode(); - getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); + } } return false; Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp Tue Jul 26 19:38:12 2011 @@ -52,6 +52,9 @@ AsmTransCBE = arm_asm_table; Data64bitsDirective = 0; CommentString = "@"; + Code16Directive = ".code\t16"; + Code32Directive = ".code\t32"; + SupportsDebugInformation = true; // Exceptions handling @@ -64,12 +67,14 @@ Data64bitsDirective = 0; CommentString = "@"; - - HasLEB128 = true; PrivateGlobalPrefix = ".L"; + Code16Directive = ".code\t16"; + Code32Directive = ".code\t32"; + WeakRefDirective = "\t.weak\t"; HasLCOMMDirective = true; + HasLEB128 = true; SupportsDebugInformation = true; // Exceptions handling Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136197&r1=136196&r2=136197&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Jul 26 19:38:12 2011 @@ -46,6 +46,7 @@ X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc); bool ParseDirectiveWord(unsigned Size, SMLoc L); + bool ParseDirectiveCode(StringRef IDVal, SMLoc L); bool MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, @@ -63,6 +64,10 @@ // FIXME: Can tablegen auto-generate this? return (STI.getFeatureBits() & X86::Mode64Bit) != 0; } + void SwitchMode() { + unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); + setAvailableFeatures(FB); + } /// @name Auto-generated Matcher Functions /// { @@ -1094,6 +1099,8 @@ StringRef IDVal = DirectiveID.getIdentifier(); if (IDVal == ".word") return ParseDirectiveWord(2, DirectiveID.getLoc()); + else if (IDVal.startswith(".code")) + return ParseDirectiveCode(IDVal, DirectiveID.getLoc()); return true; } @@ -1122,7 +1129,27 @@ return false; } +/// ParseDirectiveCode +/// ::= .code32 | .code64 +bool X86ATTAsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { + if (IDVal == ".code32") { + Parser.Lex(); + if (is64BitMode()) { + SwitchMode(); + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); + } + } else if (IDVal == ".code64") { + Parser.Lex(); + if (!is64BitMode()) { + SwitchMode(); + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64); + } + } else { + return Error(L, "unexpected directive " + IDVal); + } + return false; +} extern "C" void LLVMInitializeX86AsmLexer(); From eli.friedman at gmail.com Tue Jul 26 19:46:46 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 00:46:46 -0000 Subject: [llvm-commits] [llvm] r136198 - in /llvm/trunk: include/llvm/Analysis/AliasSetTracker.h include/llvm/Instruction.h lib/Analysis/AliasSetTracker.cpp Message-ID: <20110727004646.E1F092A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 19:46:46 2011 New Revision: 136198 URL: http://llvm.org/viewvc/llvm-project?rev=136198&view=rev Log: Fix AliasSetTracker so that it doesn't make any assumptions about instructions it doesn't know about (like the atomic instructions I'm adding). Modified: llvm/trunk/include/llvm/Analysis/AliasSetTracker.h llvm/trunk/include/llvm/Instruction.h llvm/trunk/lib/Analysis/AliasSetTracker.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasSetTracker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasSetTracker.h?rev=136198&r1=136197&r2=136198&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasSetTracker.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasSetTracker.h Tue Jul 26 19:46:46 2011 @@ -111,8 +111,8 @@ AliasSet *Forward; // Forwarding pointer. AliasSet *Next, *Prev; // Doubly linked list of AliasSets. - // All calls & invokes in this alias set. - std::vector > CallSites; + // All instructions without a specific address in this alias set. + std::vector > UnknownInsts; // RefCount - Number of nodes pointing to this AliasSet plus the number of // AliasSets forwarding to it. @@ -147,9 +147,9 @@ removeFromTracker(AST); } - CallSite getCallSite(unsigned i) const { - assert(i < CallSites.size()); - return CallSite(CallSites[i]); + Instruction *getUnknownInst(unsigned i) const { + assert(i < UnknownInsts.size()); + return UnknownInsts[i]; } public: @@ -253,12 +253,12 @@ void addPointer(AliasSetTracker &AST, PointerRec &Entry, uint64_t Size, const MDNode *TBAAInfo, bool KnownMustAlias = false); - void addCallSite(CallSite CS, AliasAnalysis &AA); - void removeCallSite(CallSite CS) { - for (size_t i = 0, e = CallSites.size(); i != e; ++i) - if (CallSites[i] == CS.getInstruction()) { - CallSites[i] = CallSites.back(); - CallSites.pop_back(); + void addUnknownInst(Instruction *I, AliasAnalysis &AA); + void removeUnknownInst(Instruction *I) { + for (size_t i = 0, e = UnknownInsts.size(); i != e; ++i) + if (UnknownInsts[i] == I) { + UnknownInsts[i] = UnknownInsts.back(); + UnknownInsts.pop_back(); --i; --e; // Revisit the moved entry. } } @@ -269,7 +269,7 @@ /// bool aliasesPointer(const Value *Ptr, uint64_t Size, const MDNode *TBAAInfo, AliasAnalysis &AA) const; - bool aliasesCallSite(CallSite CS, AliasAnalysis &AA) const; + bool aliasesUnknownInst(Instruction *Inst, AliasAnalysis &AA) const; }; inline raw_ostream& operator<<(raw_ostream &OS, const AliasSet &AS) { @@ -326,12 +326,10 @@ bool add(LoadInst *LI); bool add(StoreInst *SI); bool add(VAArgInst *VAAI); - bool add(CallSite CS); // Call/Invoke instructions - bool add(CallInst *CI) { return add(CallSite(CI)); } - bool add(InvokeInst *II) { return add(CallSite(II)); } bool add(Instruction *I); // Dispatch to one of the other add methods... void add(BasicBlock &BB); // Add all instructions in basic block void add(const AliasSetTracker &AST); // Add alias relations from another AST + bool addUnknown(Instruction *I); /// remove methods - These methods are used to remove all entries that might /// be aliased by the specified instruction. These methods return true if any @@ -341,11 +339,9 @@ bool remove(LoadInst *LI); bool remove(StoreInst *SI); bool remove(VAArgInst *VAAI); - bool remove(CallSite CS); - bool remove(CallInst *CI) { return remove(CallSite(CI)); } - bool remove(InvokeInst *II) { return remove(CallSite(II)); } bool remove(Instruction *I); void remove(AliasSet &AS); + bool removeUnknown(Instruction *I); void clear(); @@ -429,7 +425,7 @@ AliasSet *findAliasSetForPointer(const Value *Ptr, uint64_t Size, const MDNode *TBAAInfo); - AliasSet *findAliasSetForCallSite(CallSite CS); + AliasSet *findAliasSetForUnknownInst(Instruction *Inst); }; inline raw_ostream& operator<<(raw_ostream &OS, const AliasSetTracker &AST) { Modified: llvm/trunk/include/llvm/Instruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.h?rev=136198&r1=136197&r2=136198&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instruction.h (original) +++ llvm/trunk/include/llvm/Instruction.h Tue Jul 26 19:46:46 2011 @@ -223,6 +223,13 @@ /// bool mayReadFromMemory() const; + /// mayReadOrWriteMemory - Return true if this instruction may read or + /// write memory. + /// + bool mayReadOrWriteMemory() const { + return mayReadFromMemory() || mayWriteToMemory(); + } + /// mayThrow - Return true if this instruction may throw an exception. /// bool mayThrow() const; Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=136198&r1=136197&r2=136198&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Tue Jul 26 19:46:46 2011 @@ -56,12 +56,12 @@ AliasTy = MayAlias; } - if (CallSites.empty()) { // Merge call sites... - if (!AS.CallSites.empty()) - std::swap(CallSites, AS.CallSites); - } else if (!AS.CallSites.empty()) { - CallSites.insert(CallSites.end(), AS.CallSites.begin(), AS.CallSites.end()); - AS.CallSites.clear(); + if (UnknownInsts.empty()) { // Merge call sites... + if (!AS.UnknownInsts.empty()) + std::swap(UnknownInsts, AS.UnknownInsts); + } else if (!AS.UnknownInsts.empty()) { + UnknownInsts.insert(UnknownInsts.end(), AS.UnknownInsts.begin(), AS.UnknownInsts.end()); + AS.UnknownInsts.clear(); } AS.Forward = this; // Forward across AS now... @@ -123,13 +123,12 @@ addRef(); // Entry points to alias set. } -void AliasSet::addCallSite(CallSite CS, AliasAnalysis &AA) { - CallSites.push_back(CS.getInstruction()); +void AliasSet::addUnknownInst(Instruction *I, AliasAnalysis &AA) { + UnknownInsts.push_back(I); - AliasAnalysis::ModRefBehavior Behavior = AA.getModRefBehavior(CS); - if (Behavior == AliasAnalysis::DoesNotAccessMemory) + if (!I->mayReadOrWriteMemory()) return; - if (AliasAnalysis::onlyReadsMemory(Behavior)) { + if (!I->mayWriteToMemory()) { AliasTy = MayAlias; AccessTy |= Refs; return; @@ -147,7 +146,7 @@ const MDNode *TBAAInfo, AliasAnalysis &AA) const { if (AliasTy == MustAlias) { - assert(CallSites.empty() && "Illegal must alias set!"); + assert(UnknownInsts.empty() && "Illegal must alias set!"); // If this is a set of MustAliases, only check to see if the pointer aliases // SOME value in the set. @@ -167,10 +166,10 @@ I.getTBAAInfo()))) return true; - // Check the call sites list and invoke list... - if (!CallSites.empty()) { - for (unsigned i = 0, e = CallSites.size(); i != e; ++i) - if (AA.getModRefInfo(CallSites[i], + // Check the unknown instructions... + if (!UnknownInsts.empty()) { + for (unsigned i = 0, e = UnknownInsts.size(); i != e; ++i) + if (AA.getModRefInfo(UnknownInsts[i], AliasAnalysis::Location(Ptr, Size, TBAAInfo)) != AliasAnalysis::NoModRef) return true; @@ -179,18 +178,20 @@ return false; } -bool AliasSet::aliasesCallSite(CallSite CS, AliasAnalysis &AA) const { - if (AA.doesNotAccessMemory(CS)) +bool AliasSet::aliasesUnknownInst(Instruction *Inst, AliasAnalysis &AA) const { + if (!Inst->mayReadOrWriteMemory()) return false; - for (unsigned i = 0, e = CallSites.size(); i != e; ++i) { - if (AA.getModRefInfo(getCallSite(i), CS) != AliasAnalysis::NoModRef || - AA.getModRefInfo(CS, getCallSite(i)) != AliasAnalysis::NoModRef) + for (unsigned i = 0, e = UnknownInsts.size(); i != e; ++i) { + CallSite C1 = getUnknownInst(i), C2 = Inst; + if (!C1 || !C2 || + AA.getModRefInfo(getUnknownInst(i), Inst) != AliasAnalysis::NoModRef || + AA.getModRefInfo(Inst, getUnknownInst(i)) != AliasAnalysis::NoModRef) return true; } for (iterator I = begin(), E = end(); I != E; ++I) - if (AA.getModRefInfo(CS, I.getPointer(), I.getSize()) != + if (AA.getModRefInfo(Inst, I.getPointer(), I.getSize()) != AliasAnalysis::NoModRef) return true; @@ -244,10 +245,10 @@ -AliasSet *AliasSetTracker::findAliasSetForCallSite(CallSite CS) { +AliasSet *AliasSetTracker::findAliasSetForUnknownInst(Instruction *Inst) { AliasSet *FoundSet = 0; for (iterator I = begin(), E = end(); I != E; ++I) { - if (I->Forward || !I->aliasesCallSite(CS, AA)) + if (I->Forward || !I->aliasesUnknownInst(Inst, AA)) continue; if (FoundSet == 0) // If this is the first alias set ptr can go into. @@ -325,20 +326,20 @@ } -bool AliasSetTracker::add(CallSite CS) { - if (isa(CS.getInstruction())) +bool AliasSetTracker::addUnknown(Instruction *Inst) { + if (isa(Inst)) return true; // Ignore DbgInfo Intrinsics. - if (AA.doesNotAccessMemory(CS)) + if (!Inst->mayReadOrWriteMemory()) return true; // doesn't alias anything - AliasSet *AS = findAliasSetForCallSite(CS); + AliasSet *AS = findAliasSetForUnknownInst(Inst); if (AS) { - AS->addCallSite(CS, AA); + AS->addUnknownInst(Inst, AA); return false; } AliasSets.push_back(new AliasSet()); AS = &AliasSets.back(); - AS->addCallSite(CS, AA); + AS->addUnknownInst(Inst, AA); return true; } @@ -348,13 +349,9 @@ return add(LI); if (StoreInst *SI = dyn_cast(I)) return add(SI); - if (CallInst *CI = dyn_cast(I)) - return add(CI); - if (InvokeInst *II = dyn_cast(I)) - return add(II); if (VAArgInst *VAAI = dyn_cast(I)) return add(VAAI); - return true; + return addUnknown(I); } void AliasSetTracker::add(BasicBlock &BB) { @@ -375,8 +372,8 @@ AliasSet &AS = const_cast(*I); // If there are any call sites in the alias set, add them to this AST. - for (unsigned i = 0, e = AS.CallSites.size(); i != e; ++i) - add(AS.CallSites[i]); + for (unsigned i = 0, e = AS.UnknownInsts.size(); i != e; ++i) + add(AS.UnknownInsts[i]); // Loop over all of the pointers in this alias set. bool X; @@ -393,7 +390,7 @@ /// tracker. void AliasSetTracker::remove(AliasSet &AS) { // Drop all call sites. - AS.CallSites.clear(); + AS.UnknownInsts.clear(); // Clear the alias set. unsigned NumRefs = 0; @@ -453,11 +450,11 @@ return true; } -bool AliasSetTracker::remove(CallSite CS) { - if (AA.doesNotAccessMemory(CS)) +bool AliasSetTracker::removeUnknown(Instruction *I) { + if (!I->mayReadOrWriteMemory()) return false; // doesn't alias anything - AliasSet *AS = findAliasSetForCallSite(CS); + AliasSet *AS = findAliasSetForUnknownInst(I); if (!AS) return false; remove(*AS); return true; @@ -469,11 +466,9 @@ return remove(LI); if (StoreInst *SI = dyn_cast(I)) return remove(SI); - if (CallInst *CI = dyn_cast(I)) - return remove(CI); if (VAArgInst *VAAI = dyn_cast(I)) return remove(VAAI); - return true; + return removeUnknown(I); } @@ -488,13 +483,13 @@ // If this is a call instruction, remove the callsite from the appropriate // AliasSet (if present). - if (CallSite CS = PtrVal) { - if (!AA.doesNotAccessMemory(CS)) { + if (Instruction *Inst = dyn_cast(PtrVal)) { + if (Inst->mayReadOrWriteMemory()) { // Scan all the alias sets to see if this call site is contained. for (iterator I = begin(), E = end(); I != E; ++I) { if (I->Forward) continue; - I->removeCallSite(CS); + I->removeUnknownInst(Inst); } } } @@ -571,11 +566,11 @@ OS << ", " << I.getSize() << ")"; } } - if (!CallSites.empty()) { - OS << "\n " << CallSites.size() << " Call Sites: "; - for (unsigned i = 0, e = CallSites.size(); i != e; ++i) { + if (!UnknownInsts.empty()) { + OS << "\n " << UnknownInsts.size() << " Unknown instructions: "; + for (unsigned i = 0, e = UnknownInsts.size(); i != e; ++i) { if (i) OS << ", "; - WriteAsOperand(OS, CallSites[i]); + WriteAsOperand(OS, UnknownInsts[i]); } } OS << "\n"; From bruno.cardoso at gmail.com Tue Jul 26 19:56:27 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 27 Jul 2011 00:56:27 -0000 Subject: [llvm-commits] [llvm] r136199 - /llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Message-ID: <20110727005627.914432A6C12C@llvm.org> Author: bruno Date: Tue Jul 26 19:56:27 2011 New Revision: 136199 URL: http://llvm.org/viewvc/llvm-project?rev=136199&view=rev Log: Remove more dead code! Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136199&r1=136198&r2=136199&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Jul 26 19:56:27 2011 @@ -49,16 +49,16 @@ def X86andnp : SDNode<"X86ISD::ANDNP", SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86psignb : SDNode<"X86ISD::PSIGNB", +def X86psignb : SDNode<"X86ISD::PSIGNB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86psignw : SDNode<"X86ISD::PSIGNW", +def X86psignw : SDNode<"X86ISD::PSIGNW", SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86psignd : SDNode<"X86ISD::PSIGND", +def X86psignd : SDNode<"X86ISD::PSIGND", SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86pblendv : SDNode<"X86ISD::PBLENDVB", +def X86pblendv : SDNode<"X86ISD::PBLENDVB", SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; def X86pextrb : SDNode<"X86ISD::PEXTRB", @@ -361,7 +361,7 @@ return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N)); }]>; -// INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to +// INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to // VINSERTF128 imm. def INSERT_get_vinsertf128_imm : SDNodeXForm(N)); }]>; -def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKL_v_undef_Mask(cast(N)); -}]>; - -def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKH_v_undef_Mask(cast(N)); -}]>; - def pshufd : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ return X86::isPSHUFDMask(cast(N)); From bruno.cardoso at gmail.com Tue Jul 26 19:56:34 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 27 Jul 2011 00:56:34 -0000 Subject: [llvm-commits] [llvm] r136200 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-vpermil.ll Message-ID: <20110727005635.22F3E2A6C12C@llvm.org> Author: bruno Date: Tue Jul 26 19:56:34 2011 New Revision: 136200 URL: http://llvm.org/viewvc/llvm-project?rev=136200&view=rev Log: The vpermilps and vpermilpd have different behaviour regarding the usage of the shuffle bitmask. Both work in 128-bit lanes without crossing, but in the former the mask of the high part is the same used by the low part while in the later both lanes have independent masks. Handle this properly and and add support for vpermilpd. Added: llvm/trunk/test/CodeGen/X86/avx-vpermil.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136200&r1=136199&r2=136200&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 26 19:56:34 2011 @@ -2717,7 +2717,10 @@ case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: case X86ISD::PUNPCKHQDQ: - case X86ISD::VPERMIL: + case X86ISD::VPERMILPS: + case X86ISD::VPERMILPSY: + case X86ISD::VPERMILPD: + case X86ISD::VPERMILPDY: return true; } return false; @@ -2743,7 +2746,10 @@ case X86ISD::PSHUFD: case X86ISD::PSHUFHW: case X86ISD::PSHUFLW: - case X86ISD::VPERMIL: + case X86ISD::VPERMILPS: + case X86ISD::VPERMILPSY: + case X86ISD::VPERMILPD: + case X86ISD::VPERMILPDY: return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); } @@ -3400,21 +3406,63 @@ return ::isMOVLMask(M, N->getValueType(0)); } -/// isVPERMILMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to VPERMIL*. -static bool isVPERMILMask(const SmallVectorImpl &Mask, EVT VT) { +/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. +/// Note that VPERMIL mask matching is different depending whether theunderlying +/// type is 32 or 64. In the VPERMILPS the high half of the mask should point +/// to the same elements of the low, but to the higher half of the source. +/// In VPERMILPD the two lanes could be shuffled independently of each other +/// with the same restriction that lanes can't be crossed. +static bool isVPERMILPDMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { + int NumElts = VT.getVectorNumElements(); + int NumLanes = VT.getSizeInBits()/128; + + if (!Subtarget->hasAVX()) + return false; + + // Match any permutation of 128-bit vector with 64-bit types + if (NumLanes == 1 && NumElts != 2) + return false; + + // Only match 256-bit with 32 types + if (VT.getSizeInBits() == 256 && NumElts != 4) + return false; + + // The mask on the high lane is independent of the low. Both can match + // any element in inside its own lane, but can't cross. + int LaneSize = NumElts/NumLanes; + for (int l = 0; l < NumLanes; ++l) + for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { + int LaneStart = l*LaneSize; + if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) + return false; + } + + return true; +} + +/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. +/// Note that VPERMIL mask matching is different depending whether theunderlying +/// type is 32 or 64. In the VPERMILPS the high half of the mask should point +/// to the same elements of the low, but to the higher half of the source. +/// In VPERMILPD the two lanes could be shuffled independently of each other +/// with the same restriction that lanes can't be crossed. +static bool isVPERMILPSMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { unsigned NumElts = VT.getVectorNumElements(); unsigned NumLanes = VT.getSizeInBits()/128; - // Match any permutation of 128-bit vector with 32/64-bit types - if (NumLanes == 1) { - if (NumElts == 4 || NumElts == 2) - return true; + if (!Subtarget->hasAVX()) return false; - } - // Only match 256-bit with 32/64-bit types - if (NumElts != 8 && NumElts != 4) + // Match any permutation of 128-bit vector with 32-bit types + if (NumLanes == 1 && NumElts != 4) + return false; + + // Only match 256-bit with 32 types + if (VT.getSizeInBits() == 256 && NumElts != 8) return false; // The mask on the high lane should be the same as the low. Actually, @@ -3424,7 +3472,6 @@ int HighElt = i+LaneSize; if (Mask[i] < 0 || Mask[HighElt] < 0) continue; - if (Mask[HighElt]-Mask[i] != LaneSize) return false; } @@ -3432,9 +3479,9 @@ return true; } -/// getShuffleVPERMILImmediateediate - Return the appropriate immediate to shuffle -/// the specified VECTOR_MASK mask with VPERMIL* instructions. -static unsigned getShuffleVPERMILImmediate(SDNode *N) { +/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle +/// the specified VECTOR_MASK mask with VPERMILPS* instructions. +static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { ShuffleVectorSDNode *SVOp = cast(N); EVT VT = SVOp->getValueType(0); @@ -3448,6 +3495,24 @@ return Mask; } +/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle +/// the specified VECTOR_MASK mask with VPERMILPD* instructions. +static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { + ShuffleVectorSDNode *SVOp = cast(N); + EVT VT = SVOp->getValueType(0); + + int NumElts = VT.getVectorNumElements(); + int NumLanes = VT.getSizeInBits()/128; + + unsigned Mask = 0; + int LaneSize = NumElts/NumLanes; + for (int l = 0; l < NumLanes; ++l) + for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) + Mask |= (SVOp->getMaskElt(i)-l*LaneSize) << i; + + return Mask; +} + /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse /// of what x86 movss want. X86 movs requires the lowest element to be lowest /// element of vector 2 and the other elements to come from vector 1 in order. @@ -4163,7 +4228,9 @@ return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, Depth+1); } - case X86ISD::VPERMIL: + case X86ISD::VPERMILPS: + case X86ISD::VPERMILPSY: + // FIXME: Implement the other types ImmN = N->getOperand(N->getNumOperands()-1); DecodeVPERMILMask(VT, cast(ImmN)->getZExtValue(), ShuffleMask); @@ -5784,6 +5851,22 @@ return 0; } +static inline unsigned getVPERMILOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v4i32: + case MVT::v4f32: return X86ISD::VPERMILPS; + case MVT::v2i64: + case MVT::v2f64: return X86ISD::VPERMILPD; + case MVT::v8i32: + case MVT::v8f32: return X86ISD::VPERMILPSY; + case MVT::v4i64: + case MVT::v4f64: return X86ISD::VPERMILPDY; + default: + llvm_unreachable("Unknown type for vpermil"); + } + return 0; +} + static SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, @@ -6123,14 +6206,25 @@ return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); //===--------------------------------------------------------------------===// - // Custom lower or generate target specific nodes for 256-bit shuffles. + // Generate target specific nodes for 128 or 256-bit shuffles only + // supported in the AVX instruction set. + // - // Handle VPERMIL permutations - if (isVPERMILMask(M, VT)) { - unsigned TargetMask = getShuffleVPERMILImmediate(SVOp); - if (VT == MVT::v8f32) - return getTargetShuffleNode(X86ISD::VPERMIL, dl, VT, V1, TargetMask, DAG); - } + // Handle VPERMILPS* permutations + if (isVPERMILPSMask(M, VT, Subtarget)) + return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, + getShuffleVPERMILPSImmediate(SVOp), DAG); + + // Handle VPERMILPD* permutations + if (isVPERMILPDMask(M, VT, Subtarget)) + return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, + getShuffleVPERMILPDImmediate(SVOp), DAG); + + //===--------------------------------------------------------------------===// + // Since no target specific shuffle was selected for this generic one, + // lower it into other known shuffles. FIXME: this isn't true yet, but + // this is the plan. + // // Handle general 256-bit shuffles if (VT.is256BitVector()) @@ -9748,7 +9842,10 @@ case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; - case X86ISD::VPERMIL: return "X86ISD::VPERMIL"; + case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; + case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; + case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; + case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; @@ -12666,7 +12763,10 @@ case X86ISD::PSHUFLW: case X86ISD::MOVSS: case X86ISD::MOVSD: - case X86ISD::VPERMIL: + case X86ISD::VPERMILPS: + case X86ISD::VPERMILPSY: + case X86ISD::VPERMILPD: + case X86ISD::VPERMILPDY: case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI); } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=136200&r1=136199&r2=136200&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Jul 26 19:56:34 2011 @@ -271,7 +271,10 @@ PUNPCKHWD, PUNPCKHDQ, PUNPCKHQDQ, - VPERMIL, + VPERMILPS, + VPERMILPSY, + VPERMILPD, + VPERMILPDY, // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, // according to %al. An operator is needed so that this can be expanded Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136200&r1=136199&r2=136200&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Jul 26 19:56:34 2011 @@ -153,7 +153,10 @@ def X86Punpckhdq : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>; def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>; -def X86VPermil : SDNode<"X86ISD::VPERMIL", SDTShuff2OpI>; +def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>; +def X86VPermilpsy : SDNode<"X86ISD::VPERMILPSY", SDTShuff2OpI>; +def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>; +def X86VPermilpdy : SDNode<"X86ISD::VPERMILPDY", SDTShuff2OpI>; //===----------------------------------------------------------------------===// // SSE Complex Patterns Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136200&r1=136199&r2=136200&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 26 19:56:34 2011 @@ -5522,6 +5522,12 @@ VR256:$src1, (memopv8i32 addr:$src2), imm:$src3), (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>; +// Shuffle with VPERMIL instructions +def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))), + (VPERMILPSYri VR256:$src1, imm:$imm)>; +def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))), + (VPERMILPDYri VR256:$src1, imm:$imm)>; + //===----------------------------------------------------------------------===// // VZERO - Zero YMM registers // @@ -5543,10 +5549,6 @@ // The AVX version of some but not all of them are described here, and more // should come in a near future. -// Shuffle with VPERMIL instructions -def : Pat<(v8f32 (X86VPermil VR256:$src1, (i8 imm:$imm))), - (VPERMILPSYri VR256:$src1, imm:$imm)>; - // Shuffle with PSHUFD instruction folding loads. The first two patterns match // SSE2 loads, which are always promoted to v2i64. The last one should match // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD Added: llvm/trunk/test/CodeGen/X86/avx-vpermil.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vpermil.ll?rev=136200&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-vpermil.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-vpermil.ll Tue Jul 26 19:56:34 2011 @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vpermilps +define <8 x float> @funcA(<8 x float> %a) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> + ret <8 x float> %shuffle +} + +; CHECK: vpermilpd +define <4 x double> @funcB(<4 x double> %a) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> + ret <4 x double> %shuffle +} + From bruno.cardoso at gmail.com Tue Jul 26 19:56:37 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 27 Jul 2011 00:56:37 -0000 Subject: [llvm-commits] [llvm] r136201 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110727005638.1DDC02A6C12D@llvm.org> Author: bruno Date: Tue Jul 26 19:56:37 2011 New Revision: 136201 URL: http://llvm.org/viewvc/llvm-project?rev=136201&view=rev Log: Move some code around to open opportunity for more shuffle matching Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136201&r1=136200&r2=136201&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 26 19:56:37 2011 @@ -6187,24 +6187,6 @@ if (X86::isUNPCKH_v_undef_Mask(SVOp)) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); - // Handle v8i16 specifically since SSE can do byte extraction and insertion. - if (VT == MVT::v8i16) { - SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); - if (NewOp.getNode()) - return NewOp; - } - - if (VT == MVT::v16i8) { - SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); - if (NewOp.getNode()) - return NewOp; - } - - // Handle all 128-bit wide vectors with 4 elements, and match them with - // several different shuffle types. - if (NumElems == 4 && VT.getSizeInBits() == 128) - return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); - //===--------------------------------------------------------------------===// // Generate target specific nodes for 128 or 256-bit shuffles only // supported in the AVX instruction set. @@ -6226,6 +6208,24 @@ // this is the plan. // + // Handle v8i16 specifically since SSE can do byte extraction and insertion. + if (VT == MVT::v8i16) { + SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); + if (NewOp.getNode()) + return NewOp; + } + + if (VT == MVT::v16i8) { + SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); + if (NewOp.getNode()) + return NewOp; + } + + // Handle all 128-bit wide vectors with 4 elements, and match them with + // several different shuffle types. + if (NumElems == 4 && VT.getSizeInBits() == 128) + return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); + // Handle general 256-bit shuffles if (VT.is256BitVector()) return LowerVECTOR_SHUFFLE_256(SVOp, DAG); From eli.friedman at gmail.com Tue Jul 26 20:02:25 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 01:02:25 -0000 Subject: [llvm-commits] [llvm] r136202 - /llvm/trunk/lib/Analysis/AliasSetTracker.cpp Message-ID: <20110727010225.8EE6C2A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 20:02:25 2011 New Revision: 136202 URL: http://llvm.org/viewvc/llvm-project?rev=136202&view=rev Log: Minor simplification. Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=136202&r1=136201&r2=136202&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Tue Jul 26 20:02:25 2011 @@ -185,8 +185,8 @@ for (unsigned i = 0, e = UnknownInsts.size(); i != e; ++i) { CallSite C1 = getUnknownInst(i), C2 = Inst; if (!C1 || !C2 || - AA.getModRefInfo(getUnknownInst(i), Inst) != AliasAnalysis::NoModRef || - AA.getModRefInfo(Inst, getUnknownInst(i)) != AliasAnalysis::NoModRef) + AA.getModRefInfo(C1, C2) != AliasAnalysis::NoModRef || + AA.getModRefInfo(C2, C1) != AliasAnalysis::NoModRef) return true; } From eli.friedman at gmail.com Tue Jul 26 20:08:30 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 01:08:30 -0000 Subject: [llvm-commits] [llvm] r136205 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/Scalar/DeadStoreElimination.cpp lib/Transforms/Scalar/LowerAtomic.cpp lib/Transforms/Scalar/SCCP.cpp lib/VMCore/Instruction.cpp Message-ID: <20110727010830.AE3C52A6C12C@llvm.org> Author: efriedma Date: Tue Jul 26 20:08:30 2011 New Revision: 136205 URL: http://llvm.org/viewvc/llvm-project?rev=136205&view=rev Log: Misc mid-level changes for new 'fence' instruction. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp llvm/trunk/lib/Transforms/Scalar/SCCP.cpp llvm/trunk/lib/VMCore/Instruction.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=136205&r1=136204&r2=136205&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Jul 26 20:08:30 2011 @@ -341,6 +341,7 @@ case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, Loc); case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc); case Instruction::Store: return getModRefInfo((const StoreInst*)I, Loc); + case Instruction::Fence: return getModRefInfo((const FenceInst*)I, Loc); case Instruction::Call: return getModRefInfo((const CallInst*)I, Loc); case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,Loc); default: return NoModRef; @@ -406,6 +407,19 @@ return getModRefInfo(S, Location(P, Size)); } + /// getModRefInfo (for fences) - Return whether information about whether + /// a particular store modifies or reads the specified memory location. + ModRefResult getModRefInfo(const FenceInst *S, const Location &Loc) { + // Conservatively correct. (We could possibly be a bit smarter if + // Loc is a alloca that doesn't escape.) + return ModRef; + } + + /// getModRefInfo (for fences) - A convenience wrapper. + ModRefResult getModRefInfo(const FenceInst *S, const Value *P, uint64_t Size){ + return getModRefInfo(S, Location(P, Size)); + } + /// getModRefInfo (for va_args) - Return whether information about whether /// a particular va_arg modifies or reads the specified memory location. ModRefResult getModRefInfo(const VAArgInst* I, const Location &Loc); Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=136205&r1=136204&r2=136205&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Tue Jul 26 20:08:30 2011 @@ -665,7 +665,7 @@ continue; } - + AliasAnalysis::Location LoadedLoc; // If we encounter a use of the pointer, it is no longer considered dead @@ -675,9 +675,12 @@ LoadedLoc = AA->getLocation(V); } else if (MemTransferInst *MTI = dyn_cast(BBI)) { LoadedLoc = AA->getLocationForSource(MTI); - } else { - // Not a loading instruction. + } else if (!BBI->mayReadOrWriteMemory()) { + // Instruction doesn't touch memory. continue; + } else { + // Unknown inst; assume it clobbers everything. + break; } // Remove any allocas from the DeadPointer set that are loaded, as this Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=136205&r1=136204&r2=136205&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Tue Jul 26 20:08:30 2011 @@ -115,6 +115,11 @@ return true; } +static bool LowerFenceInst(FenceInst *FI) { + FI->eraseFromParent(); + return true; +} + namespace { struct LowerAtomic : public BasicBlockPass { static char ID; @@ -123,9 +128,13 @@ } bool runOnBasicBlock(BasicBlock &BB) { bool Changed = false; - for (BasicBlock::iterator DI = BB.begin(), DE = BB.end(); DI != DE; ) - if (IntrinsicInst *II = dyn_cast(DI++)) + for (BasicBlock::iterator DI = BB.begin(), DE = BB.end(); DI != DE; ) { + Instruction *Inst = DI++; + if (IntrinsicInst *II = dyn_cast(Inst)) Changed |= LowerAtomicIntrinsic(II); + if (FenceInst *FI = dyn_cast(Inst)) + Changed |= LowerFenceInst(FI); + } return Changed; } }; Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=136205&r1=136204&r2=136205&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Tue Jul 26 20:08:30 2011 @@ -530,6 +530,7 @@ void visitCallSite (CallSite CS); void visitUnwindInst (TerminatorInst &I) { /*returns void*/ } void visitUnreachableInst(TerminatorInst &I) { /*returns void*/ } + void visitFenceInst (FenceInst &I) { /*returns void*/ } void visitAllocaInst (Instruction &I) { markOverdefined(&I); } void visitVAArgInst (Instruction &I) { markAnythingOverdefined(&I); } Modified: llvm/trunk/lib/VMCore/Instruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=136205&r1=136204&r2=136205&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instruction.cpp (original) +++ llvm/trunk/lib/VMCore/Instruction.cpp Tue Jul 26 20:08:30 2011 @@ -209,6 +209,9 @@ return IVI->getIndices() == cast(I)->getIndices(); if (const ExtractValueInst *EVI = dyn_cast(this)) return EVI->getIndices() == cast(I)->getIndices(); + if (const FenceInst *FI = dyn_cast(this)) + return FI->getOrdering() == cast(FI)->getOrdering() && + FI->getSynchScope() == cast(FI)->getSynchScope(); return true; } @@ -249,6 +252,9 @@ return IVI->getIndices() == cast(I)->getIndices(); if (const ExtractValueInst *EVI = dyn_cast(this)) return EVI->getIndices() == cast(I)->getIndices(); + if (const FenceInst *FI = dyn_cast(this)) + return FI->getOrdering() == cast(FI)->getOrdering() && + FI->getSynchScope() == cast(FI)->getSynchScope(); return true; } @@ -281,6 +287,7 @@ default: return false; case Instruction::VAArg: case Instruction::Load: + case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory return true; case Instruction::Call: return !cast(this)->doesNotAccessMemory(); @@ -296,6 +303,7 @@ bool Instruction::mayWriteToMemory() const { switch (getOpcode()) { default: return false; + case Instruction::Fence: // FIXME: refine definition of mayWriteToMemory case Instruction::Store: case Instruction::VAArg: return true; @@ -393,6 +401,7 @@ case Switch: case Unwind: case Unreachable: + case Fence: return false; // Misc instructions which have effects } } From gohman at apple.com Tue Jul 26 20:10:27 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 27 Jul 2011 01:10:27 -0000 Subject: [llvm-commits] [llvm] r136206 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110727011027.65C412A6C12C@llvm.org> Author: djg Date: Tue Jul 26 20:10:27 2011 New Revision: 136206 URL: http://llvm.org/viewvc/llvm-project?rev=136206&view=rev Log: Revert r136156, which broke several buildbots. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=136206&r1=136205&r2=136206&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jul 26 20:10:27 2011 @@ -912,7 +912,12 @@ case ISD::BR_JT: case ISD::BR_CC: case ISD::BRCOND: + assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?"); + // Branches tweak the chain to include LastCALLSEQ + Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], + getLastCALLSEQ()); Ops[0] = LegalizeOp(Ops[0]); + setLastCALLSEQ(DAG.getEntryNode()); break; case ISD::SHL: case ISD::SRL: @@ -1016,6 +1021,14 @@ // libcalls), create the new CALLSEQ_START node. Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. + // Merge in the last call to ensure that this call starts after the last + // call ended. + if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) { + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Tmp1, getLastCALLSEQ()); + Tmp1 = LegalizeOp(Tmp1); + } + // Do not try to legalize the target-specific arguments (#1+). if (Tmp1 != Node->getOperand(0)) { SmallVector Ops(Node->op_begin(), Node->op_end()); @@ -1037,7 +1050,7 @@ setLastCALLSEQ(SDValue(CallEnd, 0)); // Legalize the call, starting from the CALLSEQ_END. - LegalizeOp(SDValue(CallEnd, 0)); + LegalizeOp(getLastCALLSEQ()); return Result; } case ISD::CALLSEQ_END: From clattner at apple.com Wed Jul 27 00:50:22 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 26 Jul 2011 22:50:22 -0700 Subject: [llvm-commits] [llvm] r136124 - in /llvm/trunk/include: llvm-c/Core.h llvm/Instruction.def In-Reply-To: <20110726202406.CA0822A6C12C@llvm.org> References: <20110726202406.CA0822A6C12C@llvm.org> Message-ID: <2EB8E3C9-8D97-46FB-AFEA-FA8AA033A21A@apple.com> On Jul 26, 2011, at 1:24 PM, Eli Friedman wrote: > Author: efriedma > Date: Tue Jul 26 15:24:06 2011 > New Revision: 136124 > > URL: http://llvm.org/viewvc/llvm-project?rev=136124&view=rev > Log: > Fix a couple minor mistakes pointed out by Bill in adding 'fence' instruction. Hi Eli, The enums in Core.h are considered to be stable API that can't change. Can you add the enum to the end of the list? -Chris > > > Modified: > llvm/trunk/include/llvm-c/Core.h > llvm/trunk/include/llvm/Instruction.def > > Modified: llvm/trunk/include/llvm-c/Core.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136124&r1=136123&r2=136124&view=diff > ============================================================================== > --- llvm/trunk/include/llvm-c/Core.h (original) > +++ llvm/trunk/include/llvm-c/Core.h Tue Jul 26 15:24:06 2011 > @@ -155,35 +155,36 @@ > LLVMLoad = 27, > LLVMStore = 28, > LLVMGetElementPtr = 29, > + LLVMFence = 30, > > /* Cast Operators */ > - LLVMTrunc = 30, > - LLVMZExt = 31, > - LLVMSExt = 32, > - LLVMFPToUI = 33, > - LLVMFPToSI = 34, > - LLVMUIToFP = 35, > - LLVMSIToFP = 36, > - LLVMFPTrunc = 37, > - LLVMFPExt = 38, > - LLVMPtrToInt = 39, > - LLVMIntToPtr = 40, > - LLVMBitCast = 41, > + LLVMTrunc = 33, > + LLVMZExt = 34, > + LLVMSExt = 35, > + LLVMFPToUI = 36, > + LLVMFPToSI = 37, > + LLVMUIToFP = 38, > + LLVMSIToFP = 39, > + LLVMFPTrunc = 40, > + LLVMFPExt = 41, > + LLVMPtrToInt = 42, > + LLVMIntToPtr = 43, > + LLVMBitCast = 44, > > /* Other Operators */ > - LLVMICmp = 42, > - LLVMFCmp = 43, > - LLVMPHI = 44, > - LLVMCall = 45, > - LLVMSelect = 46, > + LLVMICmp = 45, > + LLVMFCmp = 46, > + LLVMPHI = 47, > + LLVMCall = 48, > + LLVMSelect = 49, > /* UserOp1 */ > /* UserOp2 */ > - LLVMVAArg = 49, > - LLVMExtractElement = 50, > - LLVMInsertElement = 51, > - LLVMShuffleVector = 52, > - LLVMExtractValue = 53, > - LLVMInsertValue = 54 > + LLVMVAArg = 52, > + LLVMExtractElement = 53, > + LLVMInsertElement = 54, > + LLVMShuffleVector = 55, > + LLVMExtractValue = 56, > + LLVMInsertValue = 57 > } LLVMOpcode; > > typedef enum { > > Modified: llvm/trunk/include/llvm/Instruction.def > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=136124&r1=136123&r2=136124&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Instruction.def (original) > +++ llvm/trunk/include/llvm/Instruction.def Tue Jul 26 15:24:06 2011 > @@ -134,7 +134,7 @@ > HANDLE_MEMORY_INST(28, Store , StoreInst ) > HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) > HANDLE_MEMORY_INST(30, Fence , FenceInst ) > - LAST_MEMORY_INST(32) > + LAST_MEMORY_INST(30) > > // Cast operators ... > // NOTE: The order matters here because CastInst::isEliminableCastPair > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Jul 27 00:52:13 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 26 Jul 2011 22:52:13 -0700 Subject: [llvm-commits] [llvm] r135342 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c In-Reply-To: <9C4F26AE-343A-44E5-8F45-95BC53390EC2@apple.com> References: <20110716072835.BDAC72A6C12C@llvm.org> <219B41AE-4EC9-45A6-8014-E52311FD278A@apple.com> <04584A21-9481-4179-AB3D-B2E4A8D53123@apple.com> <443EBCCB-7E7F-4CA4-9924-043099FDFFAD@apple.com> <52725BD3-8C7A-41CE-98C1-B1A4FA90FC5E@apple.com> <56D1490B-E531-4904-8BD7-881C8A02D857@apple.com> <0169808D-6F76-4047-8E4F-248D1CA56222@apple.com> <9C4F26AE-343A-44E5-8F45-95BC53390EC2@apple.com> Message-ID: On Jul 26, 2011, at 4:51 PM, Eric Christopher wrote: >>> FWIW I'm doing this now. I'm removing (not migrating) the tests that seem to test gcc front end things instead of clang front end things or where I'm positive we have a clang test already. >> >> Fantastic, thanks a lot Eric! > > FrontendC is gone. Now just C++, ObjC and ObjC++. *cheers*!! -Chris From jyasskin at google.com Wed Jul 27 01:22:51 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 27 Jul 2011 06:22:51 -0000 Subject: [llvm-commits] [llvm] r136211 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86ISelLowering.cpp unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp Message-ID: <20110727062252.2628E2A6C12C@llvm.org> Author: jyasskin Date: Wed Jul 27 01:22:51 2011 New Revision: 136211 URL: http://llvm.org/viewvc/llvm-project?rev=136211&view=rev Log: Explicitly cast narrowing conversions inside {}s that will become errors in C++0x. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Jul 27 01:22:51 2011 @@ -374,7 +374,8 @@ } if (Scale) { - VariableGEPIndex Entry = {Index, Extension, Scale}; + VariableGEPIndex Entry = {Index, Extension, + static_cast(Scale)}; VarIndices.push_back(Entry); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 27 01:22:51 2011 @@ -2778,7 +2778,8 @@ // Analyze the access pattern of the vector to see if we can extract // two subvectors and do the shuffle. The analysis is done by calculating // the range of elements the mask access on both vectors. - int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; + int MinRange[2] = { static_cast(SrcNumElts+1), + static_cast(SrcNumElts+1)}; int MaxRange[2] = {-1, -1}; for (unsigned i = 0; i != MaskNumElts; ++i) { Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Jul 27 01:22:51 2011 @@ -357,7 +357,7 @@ } // Calculate what the SS field value should be... - static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 }; + static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; unsigned SS = SSTable[Scale.getImm()]; if (BaseReg == 0) { Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Jul 27 01:22:51 2011 @@ -559,7 +559,7 @@ } // Calculate what the SS field value should be... - static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 }; + static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; unsigned SS = SSTable[Scale.getImm()]; if (BaseReg == 0) { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 27 01:22:51 2011 @@ -6357,7 +6357,7 @@ return Op; // SHUFPS the element to the lowest double word, then movss. - int Mask[4] = { Idx, -1, -1, -1 }; + int Mask[4] = { static_cast(Idx), -1, -1, -1 }; EVT VVT = Op.getOperand(0).getValueType(); SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), DAG.getUNDEF(VVT), Mask); Modified: llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp?rev=136211&r1=136210&r2=136211&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp Wed Jul 27 01:22:51 2011 @@ -45,7 +45,7 @@ std::vector EmittedEvents; std::vector FreedEvents; - int NextIndex; + unsigned NextIndex; RecordingJITEventListener() : NextIndex(0) {} From nadav.rotem at intel.com Wed Jul 27 01:25:58 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 27 Jul 2011 09:25:58 +0300 Subject: [llvm-commits] [PATCH] Vector-select patch In-Reply-To: <6594DDFF12B03D4E89690887C24869940296D9096B@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C24869940296D9096B@hasmsx504.ger.corp.intel.com> Message-ID: <6594DDFF12B03D4E89690887C24869940296D91092@hasmsx504.ger.corp.intel.com> Ping. From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Rotem, Nadav Sent: Monday, July 25, 2011 17:34 To: llvm-commits at cs.uiuc.edu Subject: [llvm-commits] [PATCH] Vector-select patch Hi, Please review the attached file. The type legalization changes are mostly complete, and it is possible to match vector instructions. ?This patch contains the code-independent parts of the vector select. Thanks, Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From evan.cheng at apple.com Wed Jul 27 01:54:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 26 Jul 2011 23:54:23 -0700 Subject: [llvm-commits] [llvm] r135760 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt lib/Support/TargetRegistry.cpp lib/Target/CMakeLists.txt lib/Target/TargetRegistry.cpp In-Reply-To: References: <20110722081654.11A932A6C12E@llvm.org> <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> Message-ID: <24FFFF91-D94C-47EE-88A5-EF75658DEC6D@apple.com> On Jul 26, 2011, at 5:06 PM, Chandler Carruth wrote: > On Tue, Jul 26, 2011 at 4:46 PM, Evan Cheng wrote: > Hi Chandler, > > Sorry I missed this earlier. I don't think this is the right change. > > No problem, I'm open to any suggestions you have here. Without this change, lots of weird stuff broke due to the Support -> Target -> MC include chain that existed prior, that was my only motivation for making it at all. Sure, that was also bad. Thanks for tackling this. > > TargetRegistry is used by everything including those tools which don't need Target library e.g. llvm-mc. > > Hrm, is there a better name for it? TargetRegistry seems very confusing for something that shouldn't live in Target. I can't come up with a better one. After all, the name clearly matches the purpose of the code! > > If you wish for consistency, the right fix is to move TargetRegistry.h to Support. But to do that, you would need to move Reloc::Model and CodeModel::Model out of MCCodeGenInfo.h first. We can't have something in Support that reference MC. > > I don't have any strong feelings here. Is Support the correct logical home for the registry? (Is it more like the TargetedPlatformRegistry? maybe s/Platform/Architecture/ or Backend something...) If so, what would be required (in brief) to move these pieces to support? I'm happy to take a look at fixing them once I have an idea of what you'd like these to look like. =D I think Support is fine. We don't need to over-design it especially since it's just one file. Thanks, Evan > > Evan > > On Jul 22, 2011, at 1:16 AM, Chandler Carruth wrote: > > > Author: chandlerc > > Date: Fri Jul 22 03:16:53 2011 > > New Revision: 135760 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=135760&view=rev > > Log: > > Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. > > The header file was already properly located. The previous need for it > > in Support had to do with the version string printing which was fixed in > > r135757. > > > > Also update build dependencies where libraries that needed the > > functionality of the Target library (in the form of the TargetRegistry) > > were picking it up via Support. This is pretty pervasive, essentially > > every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it > > depend on Target. All of these were previously just sneaking by. > > > > Added: > > llvm/trunk/lib/Target/TargetRegistry.cpp > > - copied, changed from r135759, llvm/trunk/lib/Support/TargetRegistry.cpp > > Removed: > > llvm/trunk/lib/Support/TargetRegistry.cpp > > Modified: > > llvm/trunk/cmake/modules/LLVMLibDeps.cmake > > llvm/trunk/lib/Support/CMakeLists.txt > > llvm/trunk/lib/Target/CMakeLists.txt > > > > Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=135760&r1=135759&r2=135760&view=diff > > ============================================================================== > > --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) > > +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jul 22 03:16:53 2011 > > @@ -3,10 +3,10 @@ > > set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAlphaDesc LLVMAlphaInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) > > @@ -15,16 +15,16 @@ > > set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMAsmPrinter LLVMBlackfinDesc LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMBlackfinDesc LLVMBlackfinInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > > -set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUDesc LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCellSPUDesc LLVMCellSPUInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) > > -set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMTransformUtils) > > @@ -36,37 +36,37 @@ > > set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC) > > -set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo) > > +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo) > > set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info) > > -set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPTXDesc LLVMMC LLVMPTXInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMTransformUtils) > > set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSparcDesc LLVMMC LLVMSparcInfo LLVMSupport) > > -set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSupport ) > > set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMSystemZDesc LLVMMC LLVMSystemZInfo) > > -set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) > > set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) > > @@ -74,10 +74,10 @@ > > set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) > > set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info) > > set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) > > -set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreDesc LLVMXCoreInfo) > > set(MSVC_LIB_DEPS_LLVMXCoreDesc LLVMMC LLVMXCoreInfo) > > -set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport) > > +set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport LLVMTarget) > > set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport) > > set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) > > > > Modified: llvm/trunk/lib/Support/CMakeLists.txt > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > > ============================================================================== > > --- llvm/trunk/lib/Support/CMakeLists.txt (original) > > +++ llvm/trunk/lib/Support/CMakeLists.txt Fri Jul 22 03:16:53 2011 > > @@ -42,7 +42,6 @@ > > StringPool.cpp > > StringRef.cpp > > SystemUtils.cpp > > - TargetRegistry.cpp > > Timer.cpp > > ToolOutputFile.cpp > > Triple.cpp > > > > Removed: llvm/trunk/lib/Support/TargetRegistry.cpp > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?rev=135759&view=auto > > ============================================================================== > > --- llvm/trunk/lib/Support/TargetRegistry.cpp (original) > > +++ llvm/trunk/lib/Support/TargetRegistry.cpp (removed) > > @@ -1,122 +0,0 @@ > > -//===--- TargetRegistry.cpp - Target registration -------------------------===// > > -// > > -// The LLVM Compiler Infrastructure > > -// > > -// This file is distributed under the University of Illinois Open Source > > -// License. See LICENSE.TXT for details. > > -// > > -//===----------------------------------------------------------------------===// > > - > > -#include "llvm/ADT/STLExtras.h" > > -#include "llvm/ADT/StringRef.h" > > -#include "llvm/Target/TargetRegistry.h" > > -#include "llvm/Support/Host.h" > > -#include "llvm/Support/raw_ostream.h" > > -#include > > -#include > > -using namespace llvm; > > - > > -// Clients are responsible for avoid race conditions in registration. > > -static Target *FirstTarget = 0; > > - > > -TargetRegistry::iterator TargetRegistry::begin() { > > - return iterator(FirstTarget); > > -} > > - > > -const Target *TargetRegistry::lookupTarget(const std::string &TT, > > - std::string &Error) { > > - // Provide special warning when no targets are initialized. > > - if (begin() == end()) { > > - Error = "Unable to find target for this triple (no targets are registered)"; > > - return 0; > > - } > > - const Target *Best = 0, *EquallyBest = 0; > > - unsigned BestQuality = 0; > > - for (iterator it = begin(), ie = end(); it != ie; ++it) { > > - if (unsigned Qual = it->TripleMatchQualityFn(TT)) { > > - if (!Best || Qual > BestQuality) { > > - Best = &*it; > > - EquallyBest = 0; > > - BestQuality = Qual; > > - } else if (Qual == BestQuality) > > - EquallyBest = &*it; > > - } > > - } > > - > > - if (!Best) { > > - Error = "No available targets are compatible with this triple, " > > - "see -version for the available targets."; > > - return 0; > > - } > > - > > - // Otherwise, take the best target, but make sure we don't have two equally > > - // good best targets. > > - if (EquallyBest) { > > - Error = std::string("Cannot choose between targets \"") + > > - Best->Name + "\" and \"" + EquallyBest->Name + "\""; > > - return 0; > > - } > > - > > - return Best; > > -} > > - > > -void TargetRegistry::RegisterTarget(Target &T, > > - const char *Name, > > - const char *ShortDesc, > > - Target::TripleMatchQualityFnTy TQualityFn, > > - bool HasJIT) { > > - assert(Name && ShortDesc && TQualityFn && > > - "Missing required target information!"); > > - > > - // Check if this target has already been initialized, we allow this as a > > - // convenience to some clients. > > - if (T.Name) > > - return; > > - > > - // Add to the list of targets. > > - T.Next = FirstTarget; > > - FirstTarget = &T; > > - > > - T.Name = Name; > > - T.ShortDesc = ShortDesc; > > - T.TripleMatchQualityFn = TQualityFn; > > - T.HasJIT = HasJIT; > > -} > > - > > -const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) { > > - const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); > > - > > - if (TheTarget && !TheTarget->hasJIT()) { > > - Error = "No JIT compatible target available for this host"; > > - return 0; > > - } > > - > > - return TheTarget; > > -} > > - > > -static int TargetArraySortFn(const void *LHS, const void *RHS) { > > - typedef std::pair pair_ty; > > - return ((const pair_ty*)LHS)->first.compare(((const pair_ty*)RHS)->first); > > -} > > - > > -void TargetRegistry::printRegisteredTargetsForVersion() { > > - std::vector > Targets; > > - size_t Width = 0; > > - for (TargetRegistry::iterator I = TargetRegistry::begin(), > > - E = TargetRegistry::end(); > > - I != E; ++I) { > > - Targets.push_back(std::make_pair(I->getName(), &*I)); > > - Width = std::max(Width, Targets.back().first.size()); > > - } > > - array_pod_sort(Targets.begin(), Targets.end(), TargetArraySortFn); > > - > > - raw_ostream &OS = outs(); > > - OS << " Registered Targets:\n"; > > - for (unsigned i = 0, e = Targets.size(); i != e; ++i) { > > - OS << " " << Targets[i].first; > > - OS.indent(Width - Targets[i].first.size()) << " - " > > - << Targets[i].second->getShortDescription() << '\n'; > > - } > > - if (Targets.empty()) > > - OS << " (none)\n"; > > -} > > > > Modified: llvm/trunk/lib/Target/CMakeLists.txt > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=135760&r1=135759&r2=135760&view=diff > > ============================================================================== > > --- llvm/trunk/lib/Target/CMakeLists.txt (original) > > +++ llvm/trunk/lib/Target/CMakeLists.txt Fri Jul 22 03:16:53 2011 > > @@ -11,6 +11,7 @@ > > TargetLoweringObjectFile.cpp > > TargetMachine.cpp > > TargetRegisterInfo.cpp > > + TargetRegistry.cpp > > TargetSubtargetInfo.cpp > > ) > > > > > > Copied: llvm/trunk/lib/Target/TargetRegistry.cpp (from r135759, llvm/trunk/lib/Support/TargetRegistry.cpp) > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegistry.cpp?p2=llvm/trunk/lib/Target/TargetRegistry.cpp&p1=llvm/trunk/lib/Support/TargetRegistry.cpp&r1=135759&r2=135760&rev=135760&view=diff > > ============================================================================== > > (empty) > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110726/c7f58e0a/attachment.html From baldrick at free.fr Wed Jul 27 02:20:16 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 27 Jul 2011 09:20:16 +0200 Subject: [llvm-commits] [Patch] Missed instsimplify transformation In-Reply-To: References: Message-ID: <4E2FBC30.8080008@free.fr> Hi Hans, > The attached patch adds a simplification for > > ((A& 1) == 0) | (A == 0) to > (A& 1) == 0 > > Is this ok to add to instsimplify? this kind of thing and many variations indeed turn up all the time. It is a special case of: X | Y simplifies to X if Y implies X (in your case A == 0 implies A & 1 == 0). I would prefer to add some general machinery for handling this kind of thing, rather than sticking in a few cases, because there are so many different forms of this that occur. What I had in mind was introducing a Facts class that can store a certain number of facts like "A == 0", and would be passed internally to instsimplify routines. When trying to simplify "X | Y" you would push the fact Y into the Facts object, then try to simplify X. When simplifying "(A & 1) == 0", you would recursively try to simplify "A & 1"; when simplifying "A & 1" the fact "A == 0" would apply, allowing you to replace A with 0, giving "0 & 1" which would simplify to 0, resulting in "(A & 1) == 0" simplifying to "true". This would show that Y => X in your case, so you would then pop the fact from the Facts object and return X as the simplification for "X | Y". Unfortunately I don't have time to work on this right now - would you like to? Ciao, Duncan. From eli.friedman at gmail.com Wed Jul 27 02:31:12 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 00:31:12 -0700 Subject: [llvm-commits] [llvm] r136124 - in /llvm/trunk/include: llvm-c/Core.h llvm/Instruction.def In-Reply-To: <2EB8E3C9-8D97-46FB-AFEA-FA8AA033A21A@apple.com> References: <20110726202406.CA0822A6C12C@llvm.org> <2EB8E3C9-8D97-46FB-AFEA-FA8AA033A21A@apple.com> Message-ID: On Tue, Jul 26, 2011 at 10:50 PM, Chris Lattner wrote: > > On Jul 26, 2011, at 1:24 PM, Eli Friedman wrote: > >> Author: efriedma >> Date: Tue Jul 26 15:24:06 2011 >> New Revision: 136124 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=136124&view=rev >> Log: >> Fix a couple minor mistakes pointed out by Bill in adding 'fence' instruction. > > Hi Eli, > > The enums in Core.h are considered to be stable API that can't change. ?Can you add the enum to the end of the list? Oh, oops; I assume then that they aren't required to be the same as the ones in Instruction.def? -Eli From jay.foad at gmail.com Wed Jul 27 02:40:11 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 27 Jul 2011 08:40:11 +0100 Subject: [llvm-commits] [llvm] r136138 - /llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp In-Reply-To: <20110726205225.C72152A6C12D@llvm.org> References: <20110726205225.C72152A6C12D@llvm.org> Message-ID: On 26 July 2011 21:52, Nicolas Geoffray wrote: > Author: geoffray > Date: Tue Jul 26 15:52:25 2011 > New Revision: 136138 > > URL: http://llvm.org/viewvc/llvm-project?rev=136138&view=rev > Log: > Update generated code to use new API of GetElementPtrInst::Create. Thanks. Sorry I missed this, again! Jay. From jay.foad at gmail.com Wed Jul 27 04:25:14 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 27 Jul 2011 09:25:14 -0000 Subject: [llvm-commits] [llvm] r136212 - in /llvm/trunk/utils/unittest/googletest: ./ include/gtest/ include/gtest/internal/ Message-ID: <20110727092515.1E5202A6C12C@llvm.org> Author: foad Date: Wed Jul 27 04:25:14 2011 New Revision: 136212 URL: http://llvm.org/viewvc/llvm-project?rev=136212&view=rev Log: Merge gtest-1.6.0. Added: llvm/trunk/utils/unittest/googletest/gtest-printers.cc llvm/trunk/utils/unittest/googletest/include/gtest/gtest-printers.h Modified: llvm/trunk/utils/unittest/googletest/README.LLVM llvm/trunk/utils/unittest/googletest/gtest-death-test.cc llvm/trunk/utils/unittest/googletest/gtest-filepath.cc llvm/trunk/utils/unittest/googletest/gtest-port.cc llvm/trunk/utils/unittest/googletest/gtest-test-part.cc llvm/trunk/utils/unittest/googletest/gtest-typed-test.cc llvm/trunk/utils/unittest/googletest/gtest.cc llvm/trunk/utils/unittest/googletest/include/gtest/gtest-death-test.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest-message.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest-param-test.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest-spi.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest-test-part.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest-typed-test.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest.h llvm/trunk/utils/unittest/googletest/include/gtest/gtest_pred_impl.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal-inl.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-string.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h Modified: llvm/trunk/utils/unittest/googletest/README.LLVM URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/README.LLVM?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/README.LLVM (original) +++ llvm/trunk/utils/unittest/googletest/README.LLVM Wed Jul 27 04:25:14 2011 @@ -1,14 +1,14 @@ LLVM notes ---------- -This directory contains Google Test 1.5.0, with all elements removed except for +This directory contains Google Test 1.6.0, with all elements removed except for the actual source code, to minimize the addition to the LLVM distribution. Cleaned up as follows: # Remove all the unnecessary files and directories $ rm -f aclocal* CMakeLists.txt configure* Makefile* CHANGES CONTRIBUTORS README -$ rm -rf build-aux codegear fused-src m4 make msvc samples scripts test xcode +$ rm -rf build-aux cmake codegear fused-src m4 make msvc samples scripts test xcode $ rm -f `find . -name \*\.pump` # Move all the source files to the current directory @@ -21,6 +21,8 @@ # Update paths to the included files $ perl -pi -e 's|^#include "src/|#include "gtest/internal/|' *.cc +$ rm -f gtest-all.cc gtest_main.cc + $ mv COPYING LICENSE.TXT Modified: llvm/trunk/utils/unittest/googletest/gtest-death-test.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-death-test.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-death-test.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest-death-test.cc Wed Jul 27 04:25:14 2011 @@ -31,31 +31,31 @@ // // This file implements death tests. -#include -#include +#include "gtest/gtest-death-test.h" +#include "gtest/internal/gtest-port.h" #if GTEST_HAS_DEATH_TEST -#if GTEST_OS_MAC -#include -#endif // GTEST_OS_MAC - -#include -#include -#include -#include - -#if GTEST_OS_WINDOWS -#include -#else -#include -#include -#endif // GTEST_OS_WINDOWS +# if GTEST_OS_MAC +# include +# endif // GTEST_OS_MAC + +# include +# include +# include +# include + +# if GTEST_OS_WINDOWS +# include +# else +# include +# include +# endif // GTEST_OS_WINDOWS #endif // GTEST_HAS_DEATH_TEST -#include -#include +#include "gtest/gtest-message.h" +#include "gtest/internal/gtest-string.h" // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is @@ -113,14 +113,18 @@ // ExitedWithCode function-call operator. bool ExitedWithCode::operator()(int exit_status) const { -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS + return exit_status == exit_code_; -#else + +# else + return WIFEXITED(exit_status) && WEXITSTATUS(exit_status) == exit_code_; -#endif // GTEST_OS_WINDOWS + +# endif // GTEST_OS_WINDOWS } -#if !GTEST_OS_WINDOWS +# if !GTEST_OS_WINDOWS // KilledBySignal constructor. KilledBySignal::KilledBySignal(int signum) : signum_(signum) { } @@ -129,7 +133,7 @@ bool KilledBySignal::operator()(int exit_status) const { return WIFSIGNALED(exit_status) && WTERMSIG(exit_status) == signum_; } -#endif // !GTEST_OS_WINDOWS +# endif // !GTEST_OS_WINDOWS namespace internal { @@ -139,20 +143,25 @@ // specified by wait(2). static String ExitSummary(int exit_code) { Message m; -#if GTEST_OS_WINDOWS + +# if GTEST_OS_WINDOWS + m << "Exited with exit status " << exit_code; -#else + +# else + if (WIFEXITED(exit_code)) { m << "Exited with exit status " << WEXITSTATUS(exit_code); } else if (WIFSIGNALED(exit_code)) { m << "Terminated by signal " << WTERMSIG(exit_code); } -#ifdef WCOREDUMP +# ifdef WCOREDUMP if (WCOREDUMP(exit_code)) { m << " (core dumped)"; } -#endif -#endif // GTEST_OS_WINDOWS +# endif +# endif // GTEST_OS_WINDOWS + return m.GetString(); } @@ -162,7 +171,7 @@ return !ExitedWithCode(0)(exit_status); } -#if !GTEST_OS_WINDOWS +# if !GTEST_OS_WINDOWS // Generates a textual failure message when a death test finds more than // one thread running, or cannot determine the number of threads, prior // to executing the given statement. It is the responsibility of the @@ -177,20 +186,24 @@ msg << "detected " << thread_count << " threads."; return msg.GetString(); } -#endif // !GTEST_OS_WINDOWS +# endif // !GTEST_OS_WINDOWS // Flag characters for reporting a death test that did not die. static const char kDeathTestLived = 'L'; static const char kDeathTestReturned = 'R'; +static const char kDeathTestThrew = 'T'; static const char kDeathTestInternalError = 'I'; -// An enumeration describing all of the possible ways that a death test -// can conclude. DIED means that the process died while executing the -// test code; LIVED means that process lived beyond the end of the test -// code; and RETURNED means that the test statement attempted a "return," -// which is not allowed. IN_PROGRESS means the test has not yet -// concluded. -enum DeathTestOutcome { IN_PROGRESS, DIED, LIVED, RETURNED }; +// An enumeration describing all of the possible ways that a death test can +// conclude. DIED means that the process died while executing the test +// code; LIVED means that process lived beyond the end of the test code; +// RETURNED means that the test statement attempted to execute a return +// statement, which is not allowed; THREW means that the test statement +// returned control by throwing an exception. IN_PROGRESS means the test +// has not yet concluded. +// TODO(vladl at google.com): Unify names and possibly values for +// AbortReason, DeathTestOutcome, and flag characters above. +enum DeathTestOutcome { IN_PROGRESS, DIED, LIVED, RETURNED, THREW }; // Routine for aborting the program which is safe to call from an // exec-style death test child process, in which case the error @@ -212,13 +225,13 @@ } else { fprintf(stderr, "%s", message.c_str()); fflush(stderr); - abort(); + posix::Abort(); } } // A replacement for CHECK that calls DeathTestAbort if the assertion // fails. -#define GTEST_DEATH_TEST_CHECK_(expression) \ +# define GTEST_DEATH_TEST_CHECK_(expression) \ do { \ if (!::testing::internal::IsTrue(expression)) { \ DeathTestAbort(::testing::internal::String::Format( \ @@ -234,7 +247,7 @@ // evaluates the expression as long as it evaluates to -1 and sets // errno to EINTR. If the expression evaluates to -1 but errno is // something other than EINTR, DeathTestAbort is called. -#define GTEST_DEATH_TEST_CHECK_SYSCALL_(expression) \ +# define GTEST_DEATH_TEST_CHECK_SYSCALL_(expression) \ do { \ int gtest_retval; \ do { \ @@ -388,6 +401,9 @@ case kDeathTestReturned: set_outcome(RETURNED); break; + case kDeathTestThrew: + set_outcome(THREW); + break; case kDeathTestLived: set_outcome(LIVED); break; @@ -416,19 +432,46 @@ // it finds any data in our pipe. So, here we write a single flag byte // to the pipe, then exit. const char status_ch = - reason == TEST_DID_NOT_DIE ? kDeathTestLived : kDeathTestReturned; + reason == TEST_DID_NOT_DIE ? kDeathTestLived : + reason == TEST_THREW_EXCEPTION ? kDeathTestThrew : kDeathTestReturned; + GTEST_DEATH_TEST_CHECK_SYSCALL_(posix::Write(write_fd(), &status_ch, 1)); - GTEST_DEATH_TEST_CHECK_SYSCALL_(posix::Close(write_fd())); + // We are leaking the descriptor here because on some platforms (i.e., + // when built as Windows DLL), destructors of global objects will still + // run after calling _exit(). On such systems, write_fd_ will be + // indirectly closed from the destructor of UnitTestImpl, causing double + // close if it is also closed here. On debug configurations, double close + // may assert. As there are no in-process buffers to flush here, we are + // relying on the OS to close the descriptor after the process terminates + // when the destructors are not run. _exit(1); // Exits w/o any normal exit hooks (we were supposed to crash) } +// Returns an indented copy of stderr output for a death test. +// This makes distinguishing death test output lines from regular log lines +// much easier. +static ::std::string FormatDeathTestOutput(const ::std::string& output) { + ::std::string ret; + for (size_t at = 0; ; ) { + const size_t line_end = output.find('\n', at); + ret += "[ DEATH ] "; + if (line_end == ::std::string::npos) { + ret += output.substr(at); + break; + } + ret += output.substr(at, line_end + 1 - at); + at = line_end + 1; + } + return ret; +} + // Assesses the success or failure of a death test, using both private // members which have previously been set, and one argument: // // Private data members: // outcome: An enumeration describing how the death test -// concluded: DIED, LIVED, or RETURNED. The death test fails -// in the latter two cases. +// concluded: DIED, LIVED, THREW, or RETURNED. The death test +// fails in the latter three cases. // status: The exit status of the child process. On *nix, it is in the // in the format specified by wait(2). On Windows, this is the // value supplied to the ExitProcess() API or a numeric code @@ -457,11 +500,15 @@ switch (outcome()) { case LIVED: buffer << " Result: failed to die.\n" - << " Error msg: " << error_message; + << " Error msg:\n" << FormatDeathTestOutput(error_message); + break; + case THREW: + buffer << " Result: threw an exception.\n" + << " Error msg:\n" << FormatDeathTestOutput(error_message); break; case RETURNED: buffer << " Result: illegal return in test statement.\n" - << " Error msg: " << error_message; + << " Error msg:\n" << FormatDeathTestOutput(error_message); break; case DIED: if (status_ok) { @@ -471,11 +518,12 @@ } else { buffer << " Result: died but not with expected error.\n" << " Expected: " << regex()->pattern() << "\n" - << "Actual msg: " << error_message; + << "Actual msg:\n" << FormatDeathTestOutput(error_message); } } else { buffer << " Result: died but not with expected exit code:\n" - << " " << ExitSummary(status()) << "\n"; + << " " << ExitSummary(status()) << "\n" + << "Actual msg:\n" << FormatDeathTestOutput(error_message); } break; case IN_PROGRESS: @@ -488,7 +536,7 @@ return success; } -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS // WindowsDeathTest implements death tests on Windows. Due to the // specifics of starting new processes on Windows, death tests there are // always threadsafe, and Google Test considers the @@ -519,11 +567,11 @@ // class WindowsDeathTest : public DeathTestImpl { public: - WindowsDeathTest(const char* statement, - const RE* regex, + WindowsDeathTest(const char* a_statement, + const RE* a_regex, const char* file, int line) - : DeathTestImpl(statement, regex), file_(file), line_(line) {} + : DeathTestImpl(a_statement, a_regex), file_(file), line_(line) {} // All of these virtual functions are inherited from DeathTest. virtual int Wait(); @@ -580,12 +628,12 @@ GTEST_DEATH_TEST_CHECK_( WAIT_OBJECT_0 == ::WaitForSingleObject(child_handle_.Get(), INFINITE)); - DWORD status; - GTEST_DEATH_TEST_CHECK_(::GetExitCodeProcess(child_handle_.Get(), &status) - != FALSE); + DWORD status_code; + GTEST_DEATH_TEST_CHECK_( + ::GetExitCodeProcess(child_handle_.Get(), &status_code) != FALSE); child_handle_.Reset(); - set_status(static_cast(status)); - return this->status(); + set_status(static_cast(status_code)); + return status(); } // The AssumeRole process for a Windows death test. It creates a child @@ -684,7 +732,7 @@ set_spawned(true); return OVERSEE_TEST; } -#else // We are not on Windows. +# else // We are not on Windows. // ForkingDeathTest provides implementations for most of the abstract // methods of the DeathTest interface. Only the AssumeRole method is @@ -832,19 +880,19 @@ int close_fd; // File descriptor to close; the read end of a pipe }; -#if GTEST_OS_MAC +# if GTEST_OS_MAC inline char** GetEnviron() { // When Google Test is built as a framework on MacOS X, the environ variable // is unavailable. Apple's documentation (man environ) recommends using // _NSGetEnviron() instead. return *_NSGetEnviron(); } -#else +# else // Some POSIX platforms expect you to declare environ. extern "C" makes // it reside in the global namespace. extern "C" char** environ; inline char** GetEnviron() { return environ; } -#endif // GTEST_OS_MAC +# endif // GTEST_OS_MAC // The main function for a threadsafe-style death test child process. // This function is called in a clone()-ed process and thus must avoid @@ -884,6 +932,11 @@ // This could be accomplished more elegantly by a single recursive // function, but we want to guard against the unlikely possibility of // a smart compiler optimizing the recursion away. +// +// GTEST_NO_INLINE_ is required to prevent GCC 4.6 from inlining +// StackLowerThanAddress into StackGrowsDown, which then doesn't give +// correct answer. +bool StackLowerThanAddress(const void* ptr) GTEST_NO_INLINE_; bool StackLowerThanAddress(const void* ptr) { int dummy; return &dummy < ptr; @@ -901,7 +954,7 @@ ExecDeathTestArgs args = { argv, close_fd }; pid_t child_pid = -1; -#if GTEST_HAS_CLONE +# if GTEST_HAS_CLONE const bool use_fork = GTEST_FLAG(death_test_use_fork); if (!use_fork) { @@ -918,9 +971,9 @@ GTEST_DEATH_TEST_CHECK_(munmap(stack, stack_size) != -1); } -#else +# else const bool use_fork = true; -#endif // GTEST_HAS_CLONE +# endif // GTEST_HAS_CLONE if (use_fork && (child_pid = fork()) == 0) { ExecDeathTestChildMain(&args); @@ -981,7 +1034,7 @@ return OVERSEE_TEST; } -#endif // !GTEST_OS_WINDOWS +# endif // !GTEST_OS_WINDOWS // Creates a concrete DeathTest-derived class that depends on the // --gtest_death_test_style flag, and sets the pointer pointed to @@ -1012,18 +1065,23 @@ } } -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS + if (GTEST_FLAG(death_test_style) == "threadsafe" || GTEST_FLAG(death_test_style) == "fast") { *test = new WindowsDeathTest(statement, regex, file, line); } -#else + +# else + if (GTEST_FLAG(death_test_style) == "threadsafe") { *test = new ExecDeathTest(statement, regex, file, line); } else if (GTEST_FLAG(death_test_style) == "fast") { *test = new NoExecDeathTest(statement, regex); } -#endif // GTEST_OS_WINDOWS + +# endif // GTEST_OS_WINDOWS + else { // NOLINT - this is more readable than unbalanced brackets inside #if. DeathTest::set_last_death_test_message(String::Format( "Unknown death test style \"%s\" encountered", @@ -1054,7 +1112,7 @@ dest->swap(parsed); } -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS // Recreates the pipe and event handles from the provided parameters, // signals the event, and returns a file descriptor wrapped around the pipe // handle. This function is called in the child process only. @@ -1118,7 +1176,7 @@ return write_fd; } -#endif // GTEST_OS_WINDOWS +# endif // GTEST_OS_WINDOWS // Returns a newly created InternalRunDeathTestFlag object with fields // initialized from the GTEST_FLAG(internal_run_death_test) flag if @@ -1134,7 +1192,8 @@ SplitString(GTEST_FLAG(internal_run_death_test).c_str(), '|', &fields); int write_fd = -1; -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS + unsigned int parent_process_id = 0; size_t write_handle_as_size_t = 0; size_t event_handle_as_size_t = 0; @@ -1152,7 +1211,8 @@ write_fd = GetStatusFileDescriptor(parent_process_id, write_handle_as_size_t, event_handle_as_size_t); -#else +# else + if (fields.size() != 4 || !ParseNaturalNumber(fields[1], &line) || !ParseNaturalNumber(fields[2], &index) @@ -1161,7 +1221,9 @@ "Bad --gtest_internal_run_death_test flag: %s", GTEST_FLAG(internal_run_death_test).c_str())); } -#endif // GTEST_OS_WINDOWS + +# endif // GTEST_OS_WINDOWS + return new InternalRunDeathTestFlag(fields[0], line, index, write_fd); } Modified: llvm/trunk/utils/unittest/googletest/gtest-filepath.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-filepath.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-filepath.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest-filepath.cc Wed Jul 27 04:25:14 2011 @@ -29,35 +29,35 @@ // // Authors: keith.ray at gmail.com (Keith Ray) -#include -#include +#include "gtest/internal/gtest-filepath.h" +#include "gtest/internal/gtest-port.h" #include #if GTEST_OS_WINDOWS_MOBILE -#include +# include #elif GTEST_OS_WINDOWS -#include -#include -#elif GTEST_OS_SYMBIAN -// Symbian OpenC has PATH_MAX in sys/syslimits.h -#include +# include +# include +#elif GTEST_OS_SYMBIAN || GTEST_OS_NACL +// Symbian OpenC and NaCl have PATH_MAX in sys/syslimits.h +# include #else -#include -#include // Some Linux distributions define PATH_MAX here. +# include +# include // Some Linux distributions define PATH_MAX here. #endif // GTEST_OS_WINDOWS_MOBILE #if GTEST_OS_WINDOWS -#define GTEST_PATH_MAX_ _MAX_PATH +# define GTEST_PATH_MAX_ _MAX_PATH #elif defined(PATH_MAX) -#define GTEST_PATH_MAX_ PATH_MAX +# define GTEST_PATH_MAX_ PATH_MAX #elif defined(_XOPEN_PATH_MAX) -#define GTEST_PATH_MAX_ _XOPEN_PATH_MAX +# define GTEST_PATH_MAX_ _XOPEN_PATH_MAX #else -#define GTEST_PATH_MAX_ _POSIX_PATH_MAX +# define GTEST_PATH_MAX_ _POSIX_PATH_MAX #endif // GTEST_OS_WINDOWS -#include +#include "gtest/internal/gtest-string.h" namespace testing { namespace internal { @@ -71,16 +71,16 @@ const char kAlternatePathSeparator = '/'; const char kPathSeparatorString[] = "\\"; const char kAlternatePathSeparatorString[] = "/"; -#if GTEST_OS_WINDOWS_MOBILE +# if GTEST_OS_WINDOWS_MOBILE // Windows CE doesn't have a current directory. You should not use // the current directory in tests on Windows CE, but this at least // provides a reasonable fallback. const char kCurrentDirectoryString[] = "\\"; // Windows CE doesn't define INVALID_FILE_ATTRIBUTES const DWORD kInvalidFileAttributes = 0xffffffff; -#else +# else const char kCurrentDirectoryString[] = ".\\"; -#endif // GTEST_OS_WINDOWS_MOBILE +# endif // GTEST_OS_WINDOWS_MOBILE #else const char kPathSeparator = '/'; const char kPathSeparatorString[] = "/"; Modified: llvm/trunk/utils/unittest/googletest/gtest-port.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-port.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-port.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest-port.cc Wed Jul 27 04:25:14 2011 @@ -29,30 +29,32 @@ // // Author: wan at google.com (Zhanyong Wan) -#include +#include "gtest/internal/gtest-port.h" #include #include #include +#include #if GTEST_OS_WINDOWS_MOBILE -#include // For TerminateProcess() +# include // For TerminateProcess() #elif GTEST_OS_WINDOWS -#include -#include +# include +# include #else -#include +# include #endif // GTEST_OS_WINDOWS_MOBILE #if GTEST_OS_MAC -#include -#include -#include +# include +# include +# include #endif // GTEST_OS_MAC -#include -#include -#include +#include "gtest/gtest-spi.h" +#include "gtest/gtest-message.h" +#include "gtest/internal/gtest-internal.h" +#include "gtest/internal/gtest-string.h" // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is @@ -180,20 +182,20 @@ // Returns true iff ch belongs to the given classification. Unlike // similar functions in , these aren't affected by the // current locale. -bool IsDigit(char ch) { return '0' <= ch && ch <= '9'; } -bool IsPunct(char ch) { +bool IsAsciiDigit(char ch) { return '0' <= ch && ch <= '9'; } +bool IsAsciiPunct(char ch) { return IsInSet(ch, "^-!\"#$%&'()*+,./:;<=>?@[\\]_`{|}~"); } bool IsRepeat(char ch) { return IsInSet(ch, "?*+"); } -bool IsWhiteSpace(char ch) { return IsInSet(ch, " \f\n\r\t\v"); } -bool IsWordChar(char ch) { +bool IsAsciiWhiteSpace(char ch) { return IsInSet(ch, " \f\n\r\t\v"); } +bool IsAsciiWordChar(char ch) { return ('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') || ('0' <= ch && ch <= '9') || ch == '_'; } // Returns true iff "\\c" is a supported escape sequence. bool IsValidEscape(char c) { - return (IsPunct(c) || IsInSet(c, "dDfnrsStvwW")); + return (IsAsciiPunct(c) || IsInSet(c, "dDfnrsStvwW")); } // Returns true iff the given atom (specified by escaped and pattern) @@ -201,19 +203,19 @@ bool AtomMatchesChar(bool escaped, char pattern_char, char ch) { if (escaped) { // "\\p" where p is pattern_char. switch (pattern_char) { - case 'd': return IsDigit(ch); - case 'D': return !IsDigit(ch); + case 'd': return IsAsciiDigit(ch); + case 'D': return !IsAsciiDigit(ch); case 'f': return ch == '\f'; case 'n': return ch == '\n'; case 'r': return ch == '\r'; - case 's': return IsWhiteSpace(ch); - case 'S': return !IsWhiteSpace(ch); + case 's': return IsAsciiWhiteSpace(ch); + case 'S': return !IsAsciiWhiteSpace(ch); case 't': return ch == '\t'; case 'v': return ch == '\v'; - case 'w': return IsWordChar(ch); - case 'W': return !IsWordChar(ch); + case 'w': return IsAsciiWordChar(ch); + case 'W': return !IsAsciiWordChar(ch); } - return IsPunct(pattern_char) && pattern_char == ch; + return IsAsciiPunct(pattern_char) && pattern_char == ch; } return (pattern_char == '.' && ch != '\n') || pattern_char == ch; @@ -422,6 +424,38 @@ #endif // GTEST_USES_POSIX_RE +const char kUnknownFile[] = "unknown file"; + +// Formats a source file path and a line number as they would appear +// in an error message from the compiler used to compile this code. +GTEST_API_ ::std::string FormatFileLocation(const char* file, int line) { + const char* const file_name = file == NULL ? kUnknownFile : file; + + if (line < 0) { + return String::Format("%s:", file_name).c_str(); + } +#ifdef _MSC_VER + return String::Format("%s(%d):", file_name, line).c_str(); +#else + return String::Format("%s:%d:", file_name, line).c_str(); +#endif // _MSC_VER +} + +// Formats a file location for compiler-independent XML output. +// Although this function is not platform dependent, we put it next to +// FormatFileLocation in order to contrast the two functions. +// Note that FormatCompilerIndependentFileLocation() does NOT append colon +// to the file location it produces, unlike FormatFileLocation(). +GTEST_API_ ::std::string FormatCompilerIndependentFileLocation( + const char* file, int line) { + const char* const file_name = file == NULL ? kUnknownFile : file; + + if (line < 0) + return file_name; + else + return String::Format("%s:%d", file_name, line).c_str(); +} + GTestLog::GTestLog(GTestLogSeverity severity, const char* file, int line) : severity_(severity) { @@ -444,18 +478,19 @@ // Disable Microsoft deprecation warnings for POSIX functions called from // this class (creat, dup, dup2, and close) #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable: 4996) +# pragma warning(push) +# pragma warning(disable: 4996) #endif // _MSC_VER -#if GTEST_HAS_STREAM_REDIRECTION_ +#if GTEST_HAS_STREAM_REDIRECTION // Object that captures an output stream (stdout/stderr). class CapturedStream { public: // The ctor redirects the stream to a temporary file. CapturedStream(int fd) : fd_(fd), uncaptured_fd_(dup(fd)) { -#if GTEST_OS_WINDOWS + +# if GTEST_OS_WINDOWS char temp_dir_path[MAX_PATH + 1] = { '\0' }; // NOLINT char temp_file_path[MAX_PATH + 1] = { '\0' }; // NOLINT @@ -470,14 +505,14 @@ GTEST_CHECK_(captured_fd != -1) << "Unable to open temporary file " << temp_file_path; filename_ = temp_file_path; -#else +# else // There's no guarantee that a test has write access to the // current directory, so we create the temporary file in the /tmp // directory instead. char name_template[] = "/tmp/captured_stream.XXXXXX"; const int captured_fd = mkstemp(name_template); filename_ = name_template; -#endif // GTEST_OS_WINDOWS +# endif // GTEST_OS_WINDOWS fflush(NULL); dup2(captured_fd, fd_); close(captured_fd); @@ -546,9 +581,9 @@ return content; } -#ifdef _MSC_VER -#pragma warning(pop) -#endif // _MSC_VER +# ifdef _MSC_VER +# pragma warning(pop) +# endif // _MSC_VER static CapturedStream* g_captured_stderr = NULL; static CapturedStream* g_captured_stdout = NULL; @@ -588,7 +623,7 @@ // Stops capturing stderr and returns the captured string. String GetCapturedStderr() { return GetCapturedStream(&g_captured_stderr); } -#endif // GTEST_HAS_STREAM_REDIRECTION_ +#endif // GTEST_HAS_STREAM_REDIRECTION #if GTEST_HAS_DEATH_TEST @@ -618,7 +653,7 @@ Message env_var; for (size_t i = 0; i != full_flag.length(); i++) { - env_var << static_cast(toupper(full_flag.c_str()[i])); + env_var << ToUpper(full_flag.c_str()[i]); } return env_var.GetString(); Added: llvm/trunk/utils/unittest/googletest/gtest-printers.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-printers.cc?rev=136212&view=auto ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-printers.cc (added) +++ llvm/trunk/utils/unittest/googletest/gtest-printers.cc Wed Jul 27 04:25:14 2011 @@ -0,0 +1,356 @@ +// Copyright 2007, Google Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following disclaimer +// in the documentation and/or other materials provided with the +// distribution. +// * Neither the name of Google Inc. nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Author: wan at google.com (Zhanyong Wan) + +// Google Test - The Google C++ Testing Framework +// +// This file implements a universal value printer that can print a +// value of any type T: +// +// void ::testing::internal::UniversalPrinter::Print(value, ostream_ptr); +// +// It uses the << operator when possible, and prints the bytes in the +// object otherwise. A user can override its behavior for a class +// type Foo by defining either operator<<(::std::ostream&, const Foo&) +// or void PrintTo(const Foo&, ::std::ostream*) in the namespace that +// defines Foo. + +#include "gtest/gtest-printers.h" +#include +#include +#include // NOLINT +#include +#include "gtest/internal/gtest-port.h" + +namespace testing { + +namespace { + +using ::std::ostream; + +#if GTEST_OS_WINDOWS_MOBILE // Windows CE does not define _snprintf_s. +# define snprintf _snprintf +#elif _MSC_VER >= 1400 // VC 8.0 and later deprecate snprintf and _snprintf. +# define snprintf _snprintf_s +#elif _MSC_VER +# define snprintf _snprintf +#endif // GTEST_OS_WINDOWS_MOBILE + +// Prints a segment of bytes in the given object. +void PrintByteSegmentInObjectTo(const unsigned char* obj_bytes, size_t start, + size_t count, ostream* os) { + char text[5] = ""; + for (size_t i = 0; i != count; i++) { + const size_t j = start + i; + if (i != 0) { + // Organizes the bytes into groups of 2 for easy parsing by + // human. + if ((j % 2) == 0) + *os << ' '; + else + *os << '-'; + } + snprintf(text, sizeof(text), "%02X", obj_bytes[j]); + *os << text; + } +} + +// Prints the bytes in the given value to the given ostream. +void PrintBytesInObjectToImpl(const unsigned char* obj_bytes, size_t count, + ostream* os) { + // Tells the user how big the object is. + *os << count << "-byte object <"; + + const size_t kThreshold = 132; + const size_t kChunkSize = 64; + // If the object size is bigger than kThreshold, we'll have to omit + // some details by printing only the first and the last kChunkSize + // bytes. + // TODO(wan): let the user control the threshold using a flag. + if (count < kThreshold) { + PrintByteSegmentInObjectTo(obj_bytes, 0, count, os); + } else { + PrintByteSegmentInObjectTo(obj_bytes, 0, kChunkSize, os); + *os << " ... "; + // Rounds up to 2-byte boundary. + const size_t resume_pos = (count - kChunkSize + 1)/2*2; + PrintByteSegmentInObjectTo(obj_bytes, resume_pos, count - resume_pos, os); + } + *os << ">"; +} + +} // namespace + +namespace internal2 { + +// Delegates to PrintBytesInObjectToImpl() to print the bytes in the +// given object. The delegation simplifies the implementation, which +// uses the << operator and thus is easier done outside of the +// ::testing::internal namespace, which contains a << operator that +// sometimes conflicts with the one in STL. +void PrintBytesInObjectTo(const unsigned char* obj_bytes, size_t count, + ostream* os) { + PrintBytesInObjectToImpl(obj_bytes, count, os); +} + +} // namespace internal2 + +namespace internal { + +// Depending on the value of a char (or wchar_t), we print it in one +// of three formats: +// - as is if it's a printable ASCII (e.g. 'a', '2', ' '), +// - as a hexidecimal escape sequence (e.g. '\x7F'), or +// - as a special escape sequence (e.g. '\r', '\n'). +enum CharFormat { + kAsIs, + kHexEscape, + kSpecialEscape +}; + +// Returns true if c is a printable ASCII character. We test the +// value of c directly instead of calling isprint(), which is buggy on +// Windows Mobile. +inline bool IsPrintableAscii(wchar_t c) { + return 0x20 <= c && c <= 0x7E; +} + +// Prints a wide or narrow char c as a character literal without the +// quotes, escaping it when necessary; returns how c was formatted. +// The template argument UnsignedChar is the unsigned version of Char, +// which is the type of c. +template +static CharFormat PrintAsCharLiteralTo(Char c, ostream* os) { + switch (static_cast(c)) { + case L'\0': + *os << "\\0"; + break; + case L'\'': + *os << "\\'"; + break; + case L'\\': + *os << "\\\\"; + break; + case L'\a': + *os << "\\a"; + break; + case L'\b': + *os << "\\b"; + break; + case L'\f': + *os << "\\f"; + break; + case L'\n': + *os << "\\n"; + break; + case L'\r': + *os << "\\r"; + break; + case L'\t': + *os << "\\t"; + break; + case L'\v': + *os << "\\v"; + break; + default: + if (IsPrintableAscii(c)) { + *os << static_cast(c); + return kAsIs; + } else { + *os << String::Format("\\x%X", static_cast(c)); + return kHexEscape; + } + } + return kSpecialEscape; +} + +// Prints a char c as if it's part of a string literal, escaping it when +// necessary; returns how c was formatted. +static CharFormat PrintAsWideStringLiteralTo(wchar_t c, ostream* os) { + switch (c) { + case L'\'': + *os << "'"; + return kAsIs; + case L'"': + *os << "\\\""; + return kSpecialEscape; + default: + return PrintAsCharLiteralTo(c, os); + } +} + +// Prints a char c as if it's part of a string literal, escaping it when +// necessary; returns how c was formatted. +static CharFormat PrintAsNarrowStringLiteralTo(char c, ostream* os) { + return PrintAsWideStringLiteralTo(static_cast(c), os); +} + +// Prints a wide or narrow character c and its code. '\0' is printed +// as "'\\0'", other unprintable characters are also properly escaped +// using the standard C++ escape sequence. The template argument +// UnsignedChar is the unsigned version of Char, which is the type of c. +template +void PrintCharAndCodeTo(Char c, ostream* os) { + // First, print c as a literal in the most readable form we can find. + *os << ((sizeof(c) > 1) ? "L'" : "'"); + const CharFormat format = PrintAsCharLiteralTo(c, os); + *os << "'"; + + // To aid user debugging, we also print c's code in decimal, unless + // it's 0 (in which case c was printed as '\\0', making the code + // obvious). + if (c == 0) + return; + *os << " (" << String::Format("%d", c).c_str(); + + // For more convenience, we print c's code again in hexidecimal, + // unless c was already printed in the form '\x##' or the code is in + // [1, 9]. + if (format == kHexEscape || (1 <= c && c <= 9)) { + // Do nothing. + } else { + *os << String::Format(", 0x%X", + static_cast(c)).c_str(); + } + *os << ")"; +} + +void PrintTo(unsigned char c, ::std::ostream* os) { + PrintCharAndCodeTo(c, os); +} +void PrintTo(signed char c, ::std::ostream* os) { + PrintCharAndCodeTo(c, os); +} + +// Prints a wchar_t as a symbol if it is printable or as its internal +// code otherwise and also as its code. L'\0' is printed as "L'\\0'". +void PrintTo(wchar_t wc, ostream* os) { + PrintCharAndCodeTo(wc, os); +} + +// Prints the given array of characters to the ostream. +// The array starts at *begin, the length is len, it may include '\0' characters +// and may not be null-terminated. +static void PrintCharsAsStringTo(const char* begin, size_t len, ostream* os) { + *os << "\""; + bool is_previous_hex = false; + for (size_t index = 0; index < len; ++index) { + const char cur = begin[index]; + if (is_previous_hex && IsXDigit(cur)) { + // Previous character is of '\x..' form and this character can be + // interpreted as another hexadecimal digit in its number. Break string to + // disambiguate. + *os << "\" \""; + } + is_previous_hex = PrintAsNarrowStringLiteralTo(cur, os) == kHexEscape; + } + *os << "\""; +} + +// Prints a (const) char array of 'len' elements, starting at address 'begin'. +void UniversalPrintArray(const char* begin, size_t len, ostream* os) { + PrintCharsAsStringTo(begin, len, os); +} + +// Prints the given array of wide characters to the ostream. +// The array starts at *begin, the length is len, it may include L'\0' +// characters and may not be null-terminated. +static void PrintWideCharsAsStringTo(const wchar_t* begin, size_t len, + ostream* os) { + *os << "L\""; + bool is_previous_hex = false; + for (size_t index = 0; index < len; ++index) { + const wchar_t cur = begin[index]; + if (is_previous_hex && isascii(cur) && IsXDigit(static_cast(cur))) { + // Previous character is of '\x..' form and this character can be + // interpreted as another hexadecimal digit in its number. Break string to + // disambiguate. + *os << "\" L\""; + } + is_previous_hex = PrintAsWideStringLiteralTo(cur, os) == kHexEscape; + } + *os << "\""; +} + +// Prints the given C string to the ostream. +void PrintTo(const char* s, ostream* os) { + if (s == NULL) { + *os << "NULL"; + } else { + *os << ImplicitCast_(s) << " pointing to "; + PrintCharsAsStringTo(s, strlen(s), os); + } +} + +// MSVC compiler can be configured to define whar_t as a typedef +// of unsigned short. Defining an overload for const wchar_t* in that case +// would cause pointers to unsigned shorts be printed as wide strings, +// possibly accessing more memory than intended and causing invalid +// memory accesses. MSVC defines _NATIVE_WCHAR_T_DEFINED symbol when +// wchar_t is implemented as a native type. +#if !defined(_MSC_VER) || defined(_NATIVE_WCHAR_T_DEFINED) +// Prints the given wide C string to the ostream. +void PrintTo(const wchar_t* s, ostream* os) { + if (s == NULL) { + *os << "NULL"; + } else { + *os << ImplicitCast_(s) << " pointing to "; + PrintWideCharsAsStringTo(s, wcslen(s), os); + } +} +#endif // wchar_t is native + +// Prints a ::string object. +#if GTEST_HAS_GLOBAL_STRING +void PrintStringTo(const ::string& s, ostream* os) { + PrintCharsAsStringTo(s.data(), s.size(), os); +} +#endif // GTEST_HAS_GLOBAL_STRING + +void PrintStringTo(const ::std::string& s, ostream* os) { + PrintCharsAsStringTo(s.data(), s.size(), os); +} + +// Prints a ::wstring object. +#if GTEST_HAS_GLOBAL_WSTRING +void PrintWideStringTo(const ::wstring& s, ostream* os) { + PrintWideCharsAsStringTo(s.data(), s.size(), os); +} +#endif // GTEST_HAS_GLOBAL_WSTRING + +#if GTEST_HAS_STD_WSTRING +void PrintWideStringTo(const ::std::wstring& s, ostream* os) { + PrintWideCharsAsStringTo(s.data(), s.size(), os); +} +#endif // GTEST_HAS_STD_WSTRING + +} // namespace internal + +} // namespace testing Modified: llvm/trunk/utils/unittest/googletest/gtest-test-part.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-test-part.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-test-part.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest-test-part.cc Wed Jul 27 04:25:14 2011 @@ -31,7 +31,7 @@ // // The Google C++ Testing Framework (Google Test) -#include +#include "gtest/gtest-test-part.h" // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is Modified: llvm/trunk/utils/unittest/googletest/gtest-typed-test.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest-typed-test.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest-typed-test.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest-typed-test.cc Wed Jul 27 04:25:14 2011 @@ -29,8 +29,8 @@ // // Author: wan at google.com (Zhanyong Wan) -#include -#include +#include "gtest/gtest-typed-test.h" +#include "gtest/gtest.h" namespace testing { namespace internal { @@ -40,7 +40,7 @@ // Skips to the first non-space char in str. Returns an empty string if str // contains only whitespace characters. static const char* SkipSpaces(const char* str) { - while (isspace(*str)) + while (IsSpace(*str)) str++; return str; } Modified: llvm/trunk/utils/unittest/googletest/gtest.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest.cc?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest.cc Wed Jul 27 04:25:14 2011 @@ -31,8 +31,8 @@ // // The Google C++ Testing Framework (Google Test) -#include -#include +#include "gtest/gtest.h" +#include "gtest/gtest-spi.h" #include #include @@ -43,7 +43,7 @@ #include #include -#include +#include // NOLINT #include #include @@ -51,72 +51,76 @@ // TODO(kenton at google.com): Use autoconf to detect availability of // gettimeofday(). -#define GTEST_HAS_GETTIMEOFDAY_ 1 +# define GTEST_HAS_GETTIMEOFDAY_ 1 -#include -#include -#include +# include // NOLINT +# include // NOLINT +# include // NOLINT // Declares vsnprintf(). This header is not available on Windows. -#include -#include -#include -#include -#include -#include +# include // NOLINT +# include // NOLINT +# include // NOLINT +# include // NOLINT +# include #elif GTEST_OS_SYMBIAN -#define GTEST_HAS_GETTIMEOFDAY_ 1 -#include // NOLINT +# define GTEST_HAS_GETTIMEOFDAY_ 1 +# include // NOLINT #elif GTEST_OS_ZOS -#define GTEST_HAS_GETTIMEOFDAY_ 1 -#include // NOLINT +# define GTEST_HAS_GETTIMEOFDAY_ 1 +# include // NOLINT // On z/OS we additionally need strings.h for strcasecmp. -#include // NOLINT +# include // NOLINT #elif GTEST_OS_WINDOWS_MOBILE // We are on Windows CE. -#include // NOLINT +# include // NOLINT #elif GTEST_OS_WINDOWS // We are on Windows proper. -#include // NOLINT -#include // NOLINT -#include // NOLINT -#include // NOLINT +# include // NOLINT +# include // NOLINT +# include // NOLINT +# include // NOLINT -#if GTEST_OS_WINDOWS_MINGW +# if GTEST_OS_WINDOWS_MINGW // MinGW has gettimeofday() but not _ftime64(). // TODO(kenton at google.com): Use autoconf to detect availability of // gettimeofday(). // TODO(kenton at google.com): There are other ways to get the time on // Windows, like GetTickCount() or GetSystemTimeAsFileTime(). MinGW // supports these. consider using them instead. -#define GTEST_HAS_GETTIMEOFDAY_ 1 -#include // NOLINT -#endif // GTEST_OS_WINDOWS_MINGW +# define GTEST_HAS_GETTIMEOFDAY_ 1 +# include // NOLINT +# endif // GTEST_OS_WINDOWS_MINGW // cpplint thinks that the header is already included, so we want to // silence it. -#include // NOLINT +# include // NOLINT #else // Assume other platforms have gettimeofday(). // TODO(kenton at google.com): Use autoconf to detect availability of // gettimeofday(). -#define GTEST_HAS_GETTIMEOFDAY_ 1 +# define GTEST_HAS_GETTIMEOFDAY_ 1 // cpplint thinks that the header is already included, so we want to // silence it. -#include // NOLINT -#include // NOLINT +# include // NOLINT +# include // NOLINT #endif // GTEST_OS_LINUX #if GTEST_HAS_EXCEPTIONS -#include +# include +#endif + +#if GTEST_CAN_STREAM_RESULTS_ +# include // NOLINT +# include // NOLINT #endif // Indicates that this translation unit is part of Google Test's @@ -129,7 +133,7 @@ #undef GTEST_IMPLEMENTATION_ #if GTEST_OS_WINDOWS -#define vsnprintf _vsnprintf +# define vsnprintf _vsnprintf #endif // GTEST_OS_WINDOWS namespace testing { @@ -187,7 +191,7 @@ GTEST_DEFINE_bool_( catch_exceptions, - internal::BoolFromGTestEnv("catch_exceptions", false), + internal::BoolFromGTestEnv("catch_exceptions", true), "True iff " GTEST_NAME_ " should catch exceptions and treat them as test failures."); @@ -258,6 +262,13 @@ "The maximum number of stack frames to print when an " "assertion fails. The valid range is 0 through 100, inclusive."); +GTEST_DEFINE_string_( + stream_result_to, + internal::StringFromGTestEnv("stream_result_to", ""), + "This flag specifies the host name and the port number on which to stream " + "test results. Example: \"localhost:555\". The flag is effective only on " + "Linux."); + GTEST_DEFINE_bool_( throw_on_failure, internal::BoolFromGTestEnv("throw_on_failure", false), @@ -490,20 +501,33 @@ !MatchesFilter(full_name, negative.c_str())); } -#if GTEST_OS_WINDOWS +#if GTEST_HAS_SEH // Returns EXCEPTION_EXECUTE_HANDLER if Google Test should handle the // given SEH exception, or EXCEPTION_CONTINUE_SEARCH otherwise. // This function is useful as an __except condition. int UnitTestOptions::GTestShouldProcessSEH(DWORD exception_code) { - // Google Test should handle an exception if: + // Google Test should handle a SEH exception if: // 1. the user wants it to, AND - // 2. this is not a breakpoint exception. - return (GTEST_FLAG(catch_exceptions) && - exception_code != EXCEPTION_BREAKPOINT) ? - EXCEPTION_EXECUTE_HANDLER : - EXCEPTION_CONTINUE_SEARCH; + // 2. this is not a breakpoint exception, AND + // 3. this is not a C++ exception (VC++ implements them via SEH, + // apparently). + // + // SEH exception code for C++ exceptions. + // (see http://support.microsoft.com/kb/185294 for more information). + const DWORD kCxxExceptionCode = 0xe06d7363; + + bool should_handle = true; + + if (!GTEST_FLAG(catch_exceptions)) + should_handle = false; + else if (exception_code == EXCEPTION_BREAKPOINT) + should_handle = false; + else if (exception_code == kCxxExceptionCode) + should_handle = false; + + return should_handle ? EXCEPTION_EXECUTE_HANDLER : EXCEPTION_CONTINUE_SEARCH; } -#endif // GTEST_OS_WINDOWS +#endif // GTEST_HAS_SEH } // namespace internal @@ -583,7 +607,7 @@ const char* /* substr_expr */, const TestPartResultArray& results, TestPartResult::Type type, - const char* substr) { + const string& substr) { const String expected(type == TestPartResult::kFatalFailure ? "1 fatal failure" : "1 non-fatal failure"); @@ -594,23 +618,21 @@ for (int i = 0; i < results.size(); i++) { msg << "\n" << results.GetTestPartResult(i); } - return AssertionFailure(msg); + return AssertionFailure() << msg; } const TestPartResult& r = results.GetTestPartResult(0); if (r.type() != type) { - msg << "Expected: " << expected << "\n" - << " Actual:\n" - << r; - return AssertionFailure(msg); + return AssertionFailure() << "Expected: " << expected << "\n" + << " Actual:\n" + << r; } - if (strstr(r.message(), substr) == NULL) { - msg << "Expected: " << expected << " containing \"" - << substr << "\"\n" - << " Actual:\n" - << r; - return AssertionFailure(msg); + if (strstr(r.message(), substr.c_str()) == NULL) { + return AssertionFailure() << "Expected: " << expected << " containing \"" + << substr << "\"\n" + << " Actual:\n" + << r; } return AssertionSuccess(); @@ -622,7 +644,7 @@ SingleFailureChecker:: SingleFailureChecker( const TestPartResultArray* results, TestPartResult::Type type, - const char* substr) + const string& substr) : results_(results), type_(type), substr_(substr) {} @@ -632,7 +654,7 @@ // type and contains the given substring. If that's not the case, a // non-fatal failure will be generated. SingleFailureChecker::~SingleFailureChecker() { - EXPECT_PRED_FORMAT3(HasOneFailure, *results_, type_, substr_.c_str()); + EXPECT_PRED_FORMAT3(HasOneFailure, *results_, type_, substr_); } DefaultGlobalTestPartResultReporter::DefaultGlobalTestPartResultReporter( @@ -764,25 +786,30 @@ return 0; #elif GTEST_OS_WINDOWS && !GTEST_HAS_GETTIMEOFDAY_ __timeb64 now; -#ifdef _MSC_VER + +# ifdef _MSC_VER + // MSVC 8 deprecates _ftime64(), so we want to suppress warning 4996 // (deprecated function) there. // TODO(kenton at google.com): Use GetTickCount()? Or use // SystemTimeToFileTime() -#pragma warning(push) // Saves the current warning state. -#pragma warning(disable:4996) // Temporarily disables warning 4996. +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4996) // Temporarily disables warning 4996. _ftime64(&now); -#pragma warning(pop) // Restores the warning state. -#else +# pragma warning(pop) // Restores the warning state. +# else + _ftime64(&now); -#endif // _MSC_VER + +# endif // _MSC_VER + return static_cast(now.time) * 1000 + now.millitm; #elif GTEST_HAS_GETTIMEOFDAY_ struct timeval now; gettimeofday(&now, NULL); return static_cast(now.tv_sec) * 1000 + now.tv_usec / 1000; #else -#error "Don't know how to get the current time on your system." +# error "Don't know how to get the current time on your system." #endif } @@ -918,55 +945,13 @@ } #endif // GTEST_HAS_GLOBAL_WSTRING -namespace internal { - -// Formats a value to be used in a failure message. - -// For a char value, we print it as a C++ char literal and as an -// unsigned integer (both in decimal and in hexadecimal). -String FormatForFailureMessage(char ch) { - const unsigned int ch_as_uint = ch; - // A String object cannot contain '\0', so we print "\\0" when ch is - // '\0'. - return String::Format("'%s' (%u, 0x%X)", - ch ? String::Format("%c", ch).c_str() : "\\0", - ch_as_uint, ch_as_uint); -} - -// For a wchar_t value, we print it as a C++ wchar_t literal and as an -// unsigned integer (both in decimal and in hexidecimal). -String FormatForFailureMessage(wchar_t wchar) { - // The C++ standard doesn't specify the exact size of the wchar_t - // type. It just says that it shall have the same size as another - // integral type, called its underlying type. - // - // Therefore, in order to print a wchar_t value in the numeric form, - // we first convert it to the largest integral type (UInt64) and - // then print the converted value. - // - // We use streaming to print the value as "%llu" doesn't work - // correctly with MSVC 7.1. - const UInt64 wchar_as_uint64 = wchar; - Message msg; - // A String object cannot contain '\0', so we print "\\0" when wchar is - // L'\0'. - char buffer[32]; // CodePointToUtf8 requires a buffer that big. - msg << "L'" - << (wchar ? CodePointToUtf8(static_cast(wchar), buffer) : "\\0") - << "' (" << wchar_as_uint64 << ", 0x" << ::std::setbase(16) - << wchar_as_uint64 << ")"; - return msg.GetString(); -} - -} // namespace internal - // AssertionResult constructors. // Used in EXPECT_TRUE/FALSE(assertion_result). AssertionResult::AssertionResult(const AssertionResult& other) : success_(other.success_), message_(other.message_.get() != NULL ? - new internal::String(*other.message_) : - static_cast(NULL)) { + new ::std::string(*other.message_) : + static_cast< ::std::string*>(NULL)) { } // Returns the assertion's negation. Used with EXPECT/ASSERT_FALSE. @@ -1029,7 +1014,7 @@ msg << "\nWhich is: " << expected_value; } - return AssertionFailure(msg); + return AssertionFailure() << msg; } // Constructs a failure message for Boolean assertions such as EXPECT_TRUE. @@ -1059,13 +1044,12 @@ // TODO(wan): do not print the value of an expression if it's // already a literal. - Message msg; - msg << "The difference between " << expr1 << " and " << expr2 + return AssertionFailure() + << "The difference between " << expr1 << " and " << expr2 << " is " << diff << ", which exceeds " << abs_error_expr << ", where\n" << expr1 << " evaluates to " << val1 << ",\n" << expr2 << " evaluates to " << val2 << ", and\n" << abs_error_expr << " evaluates to " << abs_error << "."; - return AssertionFailure(msg); } @@ -1090,20 +1074,18 @@ // val2 is NaN, as the IEEE floating-point standard requires that // any predicate involving a NaN must return false. - StrStream val1_ss; + ::std::stringstream val1_ss; val1_ss << std::setprecision(std::numeric_limits::digits10 + 2) << val1; - StrStream val2_ss; + ::std::stringstream val2_ss; val2_ss << std::setprecision(std::numeric_limits::digits10 + 2) << val2; - Message msg; - msg << "Expected: (" << expr1 << ") <= (" << expr2 << ")\n" - << " Actual: " << StrStreamToString(&val1_ss) << " vs " - << StrStreamToString(&val2_ss); - - return AssertionFailure(msg); + return AssertionFailure() + << "Expected: (" << expr1 << ") <= (" << expr2 << ")\n" + << " Actual: " << StringStreamToString(&val1_ss) << " vs " + << StringStreamToString(&val2_ss); } } // namespace internal @@ -1150,11 +1132,10 @@ if (val1 op val2) {\ return AssertionSuccess();\ } else {\ - Message msg;\ - msg << "Expected: (" << expr1 << ") " #op " (" << expr2\ + return AssertionFailure() \ + << "Expected: (" << expr1 << ") " #op " (" << expr2\ << "), actual: " << FormatForComparisonFailureMessage(val1, val2)\ << " vs " << FormatForComparisonFailureMessage(val2, val1);\ - return AssertionFailure(msg);\ }\ } @@ -1216,11 +1197,9 @@ if (!String::CStringEquals(s1, s2)) { return AssertionSuccess(); } else { - Message msg; - msg << "Expected: (" << s1_expression << ") != (" - << s2_expression << "), actual: \"" - << s1 << "\" vs \"" << s2 << "\""; - return AssertionFailure(msg); + return AssertionFailure() << "Expected: (" << s1_expression << ") != (" + << s2_expression << "), actual: \"" + << s1 << "\" vs \"" << s2 << "\""; } } @@ -1232,11 +1211,10 @@ if (!String::CaseInsensitiveCStringEquals(s1, s2)) { return AssertionSuccess(); } else { - Message msg; - msg << "Expected: (" << s1_expression << ") != (" + return AssertionFailure() + << "Expected: (" << s1_expression << ") != (" << s2_expression << ") (ignoring case), actual: \"" << s1 << "\" vs \"" << s2 << "\""; - return AssertionFailure(msg); } } @@ -1285,13 +1263,12 @@ const bool is_wide_string = sizeof(needle[0]) > 1; const char* const begin_string_quote = is_wide_string ? "L\"" : "\""; - return AssertionFailure( - Message() + return AssertionFailure() << "Value of: " << needle_expr << "\n" << " Actual: " << begin_string_quote << needle << "\"\n" << "Expected: " << (expected_to_be_substring ? "" : "not ") << "a substring of " << haystack_expr << "\n" - << "Which is: " << begin_string_quote << haystack << "\""); + << "Which is: " << begin_string_quote << haystack << "\""; } } // namespace @@ -1360,10 +1337,13 @@ AssertionResult HRESULTFailureHelper(const char* expr, const char* expected, long hr) { // NOLINT -#if GTEST_OS_WINDOWS_MOBILE +# if GTEST_OS_WINDOWS_MOBILE + // Windows CE doesn't support FormatMessage. const char error_text[] = ""; -#else + +# else + // Looks up the human-readable system message for the HRESULT code // and since we're not passing any params to FormatMessage, we don't // want inserts expanded. @@ -1380,18 +1360,17 @@ kBufSize, // buf size NULL); // no arguments for inserts // Trims tailing white space (FormatMessage leaves a trailing cr-lf) - for (; message_length && isspace(error_text[message_length - 1]); + for (; message_length && IsSpace(error_text[message_length - 1]); --message_length) { error_text[message_length - 1] = '\0'; } -#endif // GTEST_OS_WINDOWS_MOBILE + +# endif // GTEST_OS_WINDOWS_MOBILE const String error_hex(String::Format("0x%08X ", hr)); - Message msg; - msg << "Expected: " << expr << " " << expected << ".\n" + return ::testing::AssertionFailure() + << "Expected: " << expr << " " << expected << ".\n" << " Actual: " << error_hex << error_text << "\n"; - - return ::testing::AssertionFailure(msg); } } // namespace @@ -1526,7 +1505,7 @@ if (num_chars == -1) num_chars = static_cast(wcslen(str)); - StrStream stream; + ::std::stringstream stream; for (int i = 0; i < num_chars; ++i) { UInt32 unicode_code_point; @@ -1543,7 +1522,7 @@ char buffer[32]; // CodePointToUtf8 requires a buffer this big. stream << CodePointToUtf8(unicode_code_point, buffer); } - return StrStreamToString(&stream); + return StringStreamToString(&stream); } // Converts a wide C string to a String using the UTF-8 encoding. @@ -1602,12 +1581,10 @@ return AssertionSuccess(); } - Message msg; - msg << "Expected: (" << s1_expression << ") != (" - << s2_expression << "), actual: " - << String::ShowWideCStringQuoted(s1) - << " vs " << String::ShowWideCStringQuoted(s2); - return AssertionFailure(msg); + return AssertionFailure() << "Expected: (" << s1_expression << ") != (" + << s2_expression << "), actual: " + << String::ShowWideCStringQuoted(s1) + << " vs " << String::ShowWideCStringQuoted(s2); } // Compares two C strings, ignoring case. Returns true iff they have @@ -1638,17 +1615,17 @@ // current locale. bool String::CaseInsensitiveWideCStringEquals(const wchar_t* lhs, const wchar_t* rhs) { - if ( lhs == NULL ) return rhs == NULL; + if (lhs == NULL) return rhs == NULL; - if ( rhs == NULL ) return false; + if (rhs == NULL) return false; #if GTEST_OS_WINDOWS return _wcsicmp(lhs, rhs) == 0; -#elif GTEST_OS_LINUX +#elif GTEST_OS_LINUX && !GTEST_OS_LINUX_ANDROID return wcscasecmp(lhs, rhs) == 0; #else - // Mac OS X and Cygwin don't define wcscasecmp. Other unknown OSes - // may not define it either. + // Android, Mac OS X and Cygwin don't define wcscasecmp. + // Other unknown OSes may not define it either. wint_t left, right; do { left = towlower(*lhs++); @@ -1730,10 +1707,12 @@ // MSVC 8 deprecates vsnprintf(), so we want to suppress warning // 4996 (deprecated function) there. #ifdef _MSC_VER // We are using MSVC. -#pragma warning(push) // Saves the current warning state. -#pragma warning(disable:4996) // Temporarily disables warning 4996. +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4996) // Temporarily disables warning 4996. + const int size = vsnprintf(buffer, kBufferSize, format, args); -#pragma warning(pop) // Restores the warning state. + +# pragma warning(pop) // Restores the warning state. #else // We are not using MSVC. const int size = vsnprintf(buffer, kBufferSize, format, args); #endif // _MSC_VER @@ -1751,16 +1730,16 @@ } } -// Converts the buffer in a StrStream to a String, converting NUL +// Converts the buffer in a stringstream to a String, converting NUL // bytes to "\\0" along the way. -String StrStreamToString(StrStream* ss) { +String StringStreamToString(::std::stringstream* ss) { const ::std::string& str = ss->str(); const char* const start = str.c_str(); const char* const end = start + str.length(); - // We need to use a helper StrStream to do this transformation + // We need to use a helper stringstream to do this transformation // because String doesn't support push_back(). - StrStream helper; + ::std::stringstream helper; for (const char* ch = start; ch != end; ++ch) { if (*ch == '\0') { helper << "\\0"; // Replaces NUL with "\\0"; @@ -1964,22 +1943,6 @@ } // namespace internal -#if GTEST_HAS_SEH -// We are on Windows with SEH. - -// Adds an "exception thrown" fatal failure to the current test. -static void AddExceptionThrownFailure(DWORD exception_code, - const char* location) { - Message message; - message << "Exception thrown with code 0x" << std::setbase(16) << - exception_code << std::setbase(10) << " in " << location << "."; - - internal::ReportFailureInUnknownLocation(TestPartResult::kFatalFailure, - message.GetString()); -} - -#endif // GTEST_HAS_SEH - // Google Test requires all tests in the same test case to use the same test // fixture class. This function checks if the current test has the // same fixture class as the first test in the current test case. If @@ -1990,15 +1953,13 @@ const TestCase* const test_case = impl->current_test_case(); // Info about the first test in the current test case. - const internal::TestInfoImpl* const first_test_info = - test_case->test_info_list()[0]->impl(); - const internal::TypeId first_fixture_id = first_test_info->fixture_class_id(); + const TestInfo* const first_test_info = test_case->test_info_list()[0]; + const internal::TypeId first_fixture_id = first_test_info->fixture_class_id_; const char* const first_test_name = first_test_info->name(); // Info about the current test. - const internal::TestInfoImpl* const this_test_info = - impl->current_test_info()->impl(); - const internal::TypeId this_fixture_id = this_test_info->fixture_class_id(); + const TestInfo* const this_test_info = impl->current_test_info(); + const internal::TypeId this_fixture_id = this_test_info->fixture_class_id_; const char* const this_test_name = this_test_info->name(); if (this_fixture_id != first_fixture_id) { @@ -2048,62 +2009,167 @@ return true; } -// Runs the test and updates the test result. -void Test::Run() { - if (!HasSameFixtureClass()) return; +#if GTEST_HAS_SEH - internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); +// Adds an "exception thrown" fatal failure to the current test. This +// function returns its result via an output parameter pointer because VC++ +// prohibits creation of objects with destructors on stack in functions +// using __try (see error C2712). +static internal::String* FormatSehExceptionMessage(DWORD exception_code, + const char* location) { + Message message; + message << "SEH exception with code 0x" << std::setbase(16) << + exception_code << std::setbase(10) << " thrown in " << location << "."; + + return new internal::String(message.GetString()); +} + +#endif // GTEST_HAS_SEH + +#if GTEST_HAS_EXCEPTIONS + +// Adds an "exception thrown" fatal failure to the current test. +static internal::String FormatCxxExceptionMessage(const char* description, + const char* location) { + Message message; + if (description != NULL) { + message << "C++ exception with description \"" << description << "\""; + } else { + message << "Unknown C++ exception"; + } + message << " thrown in " << location << "."; + + return message.GetString(); +} + +static internal::String PrintTestPartResultToString( + const TestPartResult& test_part_result); + +// A failed Google Test assertion will throw an exception of this type when +// GTEST_FLAG(throw_on_failure) is true (if exceptions are enabled). We +// derive it from std::runtime_error, which is for errors presumably +// detectable only at run time. Since std::runtime_error inherits from +// std::exception, many testing frameworks know how to extract and print the +// message inside it. +class GoogleTestFailureException : public ::std::runtime_error { + public: + explicit GoogleTestFailureException(const TestPartResult& failure) + : ::std::runtime_error(PrintTestPartResultToString(failure).c_str()) {} +}; +#endif // GTEST_HAS_EXCEPTIONS + +namespace internal { +// We put these helper functions in the internal namespace as IBM's xlC +// compiler rejects the code if they were declared static. + +// Runs the given method and handles SEH exceptions it throws, when +// SEH is supported; returns the 0-value for type Result in case of an +// SEH exception. (Microsoft compilers cannot handle SEH and C++ +// exceptions in the same function. Therefore, we provide a separate +// wrapper function for handling SEH exceptions.) +template +Result HandleSehExceptionsInMethodIfSupported( + T* object, Result (T::*method)(), const char* location) { #if GTEST_HAS_SEH - // Catch SEH-style exceptions. - impl->os_stack_trace_getter()->UponLeavingGTest(); __try { - SetUp(); - } __except(internal::UnitTestOptions::GTestShouldProcessSEH( + return (object->*method)(); + } __except (internal::UnitTestOptions::GTestShouldProcessSEH( // NOLINT GetExceptionCode())) { - AddExceptionThrownFailure(GetExceptionCode(), "SetUp()"); + // We create the exception message on the heap because VC++ prohibits + // creation of objects with destructors on stack in functions using __try + // (see error C2712). + internal::String* exception_message = FormatSehExceptionMessage( + GetExceptionCode(), location); + internal::ReportFailureInUnknownLocation(TestPartResult::kFatalFailure, + *exception_message); + delete exception_message; + return static_cast(0); } +#else + (void)location; + return (object->*method)(); +#endif // GTEST_HAS_SEH +} - // We will run the test only if SetUp() had no fatal failure. - if (!HasFatalFailure()) { - impl->os_stack_trace_getter()->UponLeavingGTest(); - __try { - TestBody(); - } __except(internal::UnitTestOptions::GTestShouldProcessSEH( - GetExceptionCode())) { - AddExceptionThrownFailure(GetExceptionCode(), "the test body"); +// Runs the given method and catches and reports C++ and/or SEH-style +// exceptions, if they are supported; returns the 0-value for type +// Result in case of an SEH exception. +template +Result HandleExceptionsInMethodIfSupported( + T* object, Result (T::*method)(), const char* location) { + // NOTE: The user code can affect the way in which Google Test handles + // exceptions by setting GTEST_FLAG(catch_exceptions), but only before + // RUN_ALL_TESTS() starts. It is technically possible to check the flag + // after the exception is caught and either report or re-throw the + // exception based on the flag's value: + // + // try { + // // Perform the test method. + // } catch (...) { + // if (GTEST_FLAG(catch_exceptions)) + // // Report the exception as failure. + // else + // throw; // Re-throws the original exception. + // } + // + // However, the purpose of this flag is to allow the program to drop into + // the debugger when the exception is thrown. On most platforms, once the + // control enters the catch block, the exception origin information is + // lost and the debugger will stop the program at the point of the + // re-throw in this function -- instead of at the point of the original + // throw statement in the code under test. For this reason, we perform + // the check early, sacrificing the ability to affect Google Test's + // exception handling in the method where the exception is thrown. + if (internal::GetUnitTestImpl()->catch_exceptions()) { +#if GTEST_HAS_EXCEPTIONS + try { + return HandleSehExceptionsInMethodIfSupported(object, method, location); + } catch (const GoogleTestFailureException&) { // NOLINT + // This exception doesn't originate in code under test. It makes no + // sense to report it as a test failure. + throw; + } catch (const std::exception& e) { // NOLINT + internal::ReportFailureInUnknownLocation( + TestPartResult::kFatalFailure, + FormatCxxExceptionMessage(e.what(), location)); + } catch (...) { // NOLINT + internal::ReportFailureInUnknownLocation( + TestPartResult::kFatalFailure, + FormatCxxExceptionMessage(NULL, location)); } + return static_cast(0); +#else + return HandleSehExceptionsInMethodIfSupported(object, method, location); +#endif // GTEST_HAS_EXCEPTIONS + } else { + return (object->*method)(); } +} - // However, we want to clean up as much as possible. Hence we will - // always call TearDown(), even if SetUp() or the test body has - // failed. - impl->os_stack_trace_getter()->UponLeavingGTest(); - __try { - TearDown(); - } __except(internal::UnitTestOptions::GTestShouldProcessSEH( - GetExceptionCode())) { - AddExceptionThrownFailure(GetExceptionCode(), "TearDown()"); - } +} // namespace internal -#else // We are on a compiler or platform that doesn't support SEH. - impl->os_stack_trace_getter()->UponLeavingGTest(); - SetUp(); +// Runs the test and updates the test result. +void Test::Run() { + if (!HasSameFixtureClass()) return; + internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); + impl->os_stack_trace_getter()->UponLeavingGTest(); + internal::HandleExceptionsInMethodIfSupported(this, &Test::SetUp, "SetUp()"); // We will run the test only if SetUp() was successful. if (!HasFatalFailure()) { impl->os_stack_trace_getter()->UponLeavingGTest(); - TestBody(); + internal::HandleExceptionsInMethodIfSupported( + this, &Test::TestBody, "the test body"); } // However, we want to clean up as much as possible. Hence we will // always call TearDown(), even if SetUp() or the test body has // failed. impl->os_stack_trace_getter()->UponLeavingGTest(); - TearDown(); -#endif // GTEST_HAS_SEH + internal::HandleExceptionsInMethodIfSupported( + this, &Test::TearDown, "TearDown()"); } - // Returns true iff the current test has a fatal failure. bool Test::HasFatalFailure() { return internal::GetUnitTestImpl()->current_test_result()->HasFatalFailure(); @@ -2118,22 +2184,28 @@ // class TestInfo // Constructs a TestInfo object. It assumes ownership of the test factory -// object via impl_. +// object. +// TODO(vladl at google.com): Make a_test_case_name and a_name const string&'s +// to signify they cannot be NULLs. TestInfo::TestInfo(const char* a_test_case_name, const char* a_name, - const char* a_test_case_comment, - const char* a_comment, + const char* a_type_param, + const char* a_value_param, internal::TypeId fixture_class_id, - internal::TestFactoryBase* factory) { - impl_ = new internal::TestInfoImpl(this, a_test_case_name, a_name, - a_test_case_comment, a_comment, - fixture_class_id, factory); -} + internal::TestFactoryBase* factory) + : test_case_name_(a_test_case_name), + name_(a_name), + type_param_(a_type_param ? new std::string(a_type_param) : NULL), + value_param_(a_value_param ? new std::string(a_value_param) : NULL), + fixture_class_id_(fixture_class_id), + should_run_(false), + is_disabled_(false), + matches_filter_(false), + factory_(factory), + result_() {} // Destructs a TestInfo object. -TestInfo::~TestInfo() { - delete impl_; -} +TestInfo::~TestInfo() { delete factory_; } namespace internal { @@ -2144,10 +2216,10 @@ // // test_case_name: name of the test case // name: name of the test -// test_case_comment: a comment on the test case that will be included in -// the test output -// comment: a comment on the test that will be included in the -// test output +// type_param: the name of the test's type parameter, or NULL if +// this is not a typed or a type-parameterized test. +// value_param: text representation of the test's value parameter, +// or NULL if this is not a value-parameterized test. // fixture_class_id: ID of the test fixture class // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case @@ -2156,13 +2228,14 @@ // ownership of the factory object. TestInfo* MakeAndRegisterTestInfo( const char* test_case_name, const char* name, - const char* test_case_comment, const char* comment, + const char* type_param, + const char* value_param, TypeId fixture_class_id, SetUpTestCaseFunc set_up_tc, TearDownTestCaseFunc tear_down_tc, TestFactoryBase* factory) { TestInfo* const test_info = - new TestInfo(test_case_name, name, test_case_comment, comment, + new TestInfo(test_case_name, name, type_param, value_param, fixture_class_id, factory); GetUnitTestImpl()->AddTestInfo(set_up_tc, tear_down_tc, test_info); return test_info; @@ -2189,41 +2262,6 @@ } // namespace internal -// Returns the test case name. -const char* TestInfo::test_case_name() const { - return impl_->test_case_name(); -} - -// Returns the test name. -const char* TestInfo::name() const { - return impl_->name(); -} - -// Returns the test case comment. -const char* TestInfo::test_case_comment() const { - return impl_->test_case_comment(); -} - -// Returns the test comment. -const char* TestInfo::comment() const { - return impl_->comment(); -} - -// Returns true if this test should run. -bool TestInfo::should_run() const { return impl_->should_run(); } - -// Returns true if this test matches the user-specified filter. -bool TestInfo::matches_filter() const { return impl_->matches_filter(); } - -// Returns the result of the test. -const TestResult* TestInfo::result() const { return impl_->result(); } - -// Increments the number of death tests encountered in this test so -// far. -int TestInfo::increment_death_test_count() { - return impl_->result()->increment_death_test_count(); -} - namespace internal { // This method expands all parameterized tests registered with macros TEST_P @@ -2238,70 +2276,54 @@ #endif } +} // namespace internal + // Creates the test object, runs it, records its result, and then // deletes it. -void TestInfoImpl::Run() { +void TestInfo::Run() { if (!should_run_) return; // Tells UnitTest where to store test result. - UnitTestImpl* const impl = internal::GetUnitTestImpl(); - impl->set_current_test_info(parent_); + internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); + impl->set_current_test_info(this); TestEventListener* repeater = UnitTest::GetInstance()->listeners().repeater(); // Notifies the unit test event listeners that a test is about to start. - repeater->OnTestStart(*parent_); + repeater->OnTestStart(*this); - const TimeInMillis start = GetTimeInMillis(); + const TimeInMillis start = internal::GetTimeInMillis(); impl->os_stack_trace_getter()->UponLeavingGTest(); -#if GTEST_HAS_SEH - // Catch SEH-style exceptions. - Test* test = NULL; - - __try { - // Creates the test object. - test = factory_->CreateTest(); - } __except(internal::UnitTestOptions::GTestShouldProcessSEH( - GetExceptionCode())) { - AddExceptionThrownFailure(GetExceptionCode(), - "the test fixture's constructor"); - return; - } -#else // We are on a compiler or platform that doesn't support SEH. - - // TODO(wan): If test->Run() throws, test won't be deleted. This is - // not a problem now as we don't use exceptions. If we were to - // enable exceptions, we should revise the following to be - // exception-safe. // Creates the test object. - Test* test = factory_->CreateTest(); -#endif // GTEST_HAS_SEH - - // Runs the test only if the constructor of the test fixture didn't - // generate a fatal failure. - if (!Test::HasFatalFailure()) { + Test* const test = internal::HandleExceptionsInMethodIfSupported( + factory_, &internal::TestFactoryBase::CreateTest, + "the test fixture's constructor"); + + // Runs the test only if the test object was created and its + // constructor didn't generate a fatal failure. + if ((test != NULL) && !Test::HasFatalFailure()) { + // This doesn't throw as all user code that can throw are wrapped into + // exception handling code. test->Run(); } // Deletes the test object. impl->os_stack_trace_getter()->UponLeavingGTest(); - delete test; - test = NULL; + internal::HandleExceptionsInMethodIfSupported( + test, &Test::DeleteSelf_, "the test fixture's destructor"); - result_.set_elapsed_time(GetTimeInMillis() - start); + result_.set_elapsed_time(internal::GetTimeInMillis() - start); // Notifies the unit test event listener that a test has just finished. - repeater->OnTestEnd(*parent_); + repeater->OnTestEnd(*this); // Tells UnitTest to stop associating assertion results to this // test. impl->set_current_test_info(NULL); } -} // namespace internal - // class TestCase // Gets the number of successful tests in this test case. @@ -2333,13 +2355,15 @@ // Arguments: // // name: name of the test case +// a_type_param: the name of the test case's type parameter, or NULL if +// this is not a typed or a type-parameterized test case. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case -TestCase::TestCase(const char* a_name, const char* a_comment, +TestCase::TestCase(const char* a_name, const char* a_type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc) : name_(a_name), - comment_(a_comment), + type_param_(a_type_param ? new std::string(a_type_param) : NULL), set_up_tc_(set_up_tc), tear_down_tc_(tear_down_tc), should_run_(false), @@ -2384,45 +2408,26 @@ repeater->OnTestCaseStart(*this); impl->os_stack_trace_getter()->UponLeavingGTest(); - set_up_tc_(); + internal::HandleExceptionsInMethodIfSupported( + this, &TestCase::RunSetUpTestCase, "SetUpTestCase()"); const internal::TimeInMillis start = internal::GetTimeInMillis(); for (int i = 0; i < total_test_count(); i++) { - GetMutableTestInfo(i)->impl()->Run(); + GetMutableTestInfo(i)->Run(); } elapsed_time_ = internal::GetTimeInMillis() - start; impl->os_stack_trace_getter()->UponLeavingGTest(); - tear_down_tc_(); + internal::HandleExceptionsInMethodIfSupported( + this, &TestCase::RunTearDownTestCase, "TearDownTestCase()"); + repeater->OnTestCaseEnd(*this); impl->set_current_test_case(NULL); } // Clears the results of all tests in this test case. void TestCase::ClearResult() { - ForEach(test_info_list_, internal::TestInfoImpl::ClearTestResult); -} - -// Returns true iff test passed. -bool TestCase::TestPassed(const TestInfo * test_info) { - const internal::TestInfoImpl* const impl = test_info->impl(); - return impl->should_run() && impl->result()->Passed(); -} - -// Returns true iff test failed. -bool TestCase::TestFailed(const TestInfo * test_info) { - const internal::TestInfoImpl* const impl = test_info->impl(); - return impl->should_run() && impl->result()->Failed(); -} - -// Returns true iff test is disabled. -bool TestCase::TestDisabled(const TestInfo * test_info) { - return test_info->impl()->is_disabled(); -} - -// Returns true if the given test should run. -bool TestCase::ShouldRunTest(const TestInfo *test_info) { - return test_info->impl()->should_run(); + ForEach(test_info_list_, TestInfo::ClearTestResult); } // Shuffles the tests in this test case. @@ -2475,9 +2480,9 @@ #else return "Failure\n"; #endif + default: + return "Unknown result type"; } - - return "Unknown result type"; } // Prints a TestPartResult to a String. @@ -2563,6 +2568,7 @@ String::CStringEquals(term, "xterm") || String::CStringEquals(term, "xterm-color") || String::CStringEquals(term, "xterm-256color") || + String::CStringEquals(term, "screen") || String::CStringEquals(term, "linux") || String::CStringEquals(term, "cygwin"); return stdout_is_tty && term_supports_color; @@ -2628,6 +2634,23 @@ va_end(args); } +void PrintFullTestCommentIfPresent(const TestInfo& test_info) { + const char* const type_param = test_info.type_param(); + const char* const value_param = test_info.value_param(); + + if (type_param != NULL || value_param != NULL) { + printf(", where "); + if (type_param != NULL) { + printf("TypeParam = %s", type_param); + if (value_param != NULL) + printf(" and "); + } + if (value_param != NULL) { + printf("GetParam() = %s", value_param); + } + } +} + // This class implements the TestEventListener interface. // // Class PrettyUnitTestResultPrinter is copyable. @@ -2675,9 +2698,10 @@ } if (internal::ShouldShard(kTestTotalShards, kTestShardIndex, false)) { + const Int32 shard_index = Int32FromEnvOrDie(kTestShardIndex, -1); ColoredPrintf(COLOR_YELLOW, - "Note: This is test shard %s of %s.\n", - internal::posix::GetEnv(kTestShardIndex), + "Note: This is test shard %d of %s.\n", + static_cast(shard_index) + 1, internal::posix::GetEnv(kTestTotalShards)); } @@ -2707,10 +2731,10 @@ FormatCountableNoun(test_case.test_to_run_count(), "test", "tests"); ColoredPrintf(COLOR_GREEN, "[----------] "); printf("%s from %s", counts.c_str(), test_case_name_.c_str()); - if (test_case.comment()[0] == '\0') { + if (test_case.type_param() == NULL) { printf("\n"); } else { - printf(", where %s\n", test_case.comment()); + printf(", where TypeParam = %s\n", test_case.type_param()); } fflush(stdout); } @@ -2718,11 +2742,7 @@ void PrettyUnitTestResultPrinter::OnTestStart(const TestInfo& test_info) { ColoredPrintf(COLOR_GREEN, "[ RUN ] "); PrintTestName(test_case_name_.c_str(), test_info.name()); - if (test_info.comment()[0] == '\0') { - printf("\n"); - } else { - printf(", where %s\n", test_info.comment()); - } + printf("\n"); fflush(stdout); } @@ -2745,6 +2765,9 @@ ColoredPrintf(COLOR_RED, "[ FAILED ] "); } PrintTestName(test_case_name_.c_str(), test_info.name()); + if (test_info.result()->Failed()) + PrintFullTestCommentIfPresent(test_info); + if (GTEST_FLAG(print_time)) { printf(" (%s ms)\n", internal::StreamableToString( test_info.result()->elapsed_time()).c_str()); @@ -2793,21 +2816,14 @@ } ColoredPrintf(COLOR_RED, "[ FAILED ] "); printf("%s.%s", test_case.name(), test_info.name()); - if (test_case.comment()[0] != '\0' || - test_info.comment()[0] != '\0') { - printf(", where %s", test_case.comment()); - if (test_case.comment()[0] != '\0' && - test_info.comment()[0] != '\0') { - printf(" and "); - } - } - printf("%s\n", test_info.comment()); + PrintFullTestCommentIfPresent(test_info); + printf("\n"); } } } - void PrettyUnitTestResultPrinter::OnTestIterationEnd(const UnitTest& unit_test, - int /*iteration*/) { +void PrettyUnitTestResultPrinter::OnTestIterationEnd(const UnitTest& unit_test, + int /*iteration*/) { ColoredPrintf(COLOR_GREEN, "[==========] "); printf("%s from %s ran.", FormatTestCount(unit_test.test_to_run_count()).c_str(), @@ -2987,7 +3003,7 @@ static String EscapeXml(const char* str, bool is_attribute); // Returns the given string with all characters invalid in XML removed. - static String RemoveInvalidXmlCharacters(const char* str); + static string RemoveInvalidXmlCharacters(const string& str); // Convenience wrapper around EscapeXml when str is an attribute value. static String EscapeXmlAttribute(const char* str) { @@ -3121,17 +3137,14 @@ // Returns the given string with all characters invalid in XML removed. // Currently invalid characters are dropped from the string. An // alternative is to replace them with certain characters such as . or ?. -String XmlUnitTestResultPrinter::RemoveInvalidXmlCharacters(const char* str) { - char* const output = new char[strlen(str) + 1]; - char* appender = output; - for (char ch = *str; ch != '\0'; ch = *++str) - if (IsValidXmlCharacter(ch)) - *appender++ = ch; - *appender = '\0'; - - String ret_value(output); - delete[] output; - return ret_value; +string XmlUnitTestResultPrinter::RemoveInvalidXmlCharacters(const string& str) { + string output; + output.reserve(str.size()); + for (string::const_iterator it = str.begin(); it != str.end(); ++it) + if (IsValidXmlCharacter(*it)) + output.push_back(*it); + + return output; } // The following routines generate an XML representation of a UnitTest @@ -3184,8 +3197,18 @@ const TestInfo& test_info) { const TestResult& result = *test_info.result(); *stream << " "; - const String message = RemoveInvalidXmlCharacters(String::Format( - "%s:%d\n%s", - part.file_name(), part.line_number(), - part.message()).c_str()); - OutputXmlCDataSection(stream, message.c_str()); + const string location = internal::FormatCompilerIndependentFileLocation( + part.file_name(), part.line_number()); + const string message = location + "\n" + part.message(); + OutputXmlCDataSection(stream, + RemoveInvalidXmlCharacters(message).c_str()); *stream << "\n"; } } @@ -3230,9 +3253,9 @@ "errors=\"0\" time=\"%s\">\n", FormatTimeInMillisAsSeconds(test_case.elapsed_time()).c_str()); for (int i = 0; i < test_case.total_test_count(); ++i) { - StrStream stream; + ::std::stringstream stream; OutputXmlTestInfo(&stream, test_case.name(), *test_case.GetTestInfo(i)); - fprintf(out, "%s", StrStreamToString(&stream).c_str()); + fprintf(out, "%s", StringStreamToString(&stream).c_str()); } fprintf(out, " \n"); } @@ -3272,6 +3295,182 @@ // End XmlUnitTestResultPrinter +#if GTEST_CAN_STREAM_RESULTS_ + +// Streams test results to the given port on the given host machine. +class StreamingListener : public EmptyTestEventListener { + public: + // Escapes '=', '&', '%', and '\n' characters in str as "%xx". + static string UrlEncode(const char* str); + + StreamingListener(const string& host, const string& port) + : sockfd_(-1), host_name_(host), port_num_(port) { + MakeConnection(); + Send("gtest_streaming_protocol_version=1.0\n"); + } + + virtual ~StreamingListener() { + if (sockfd_ != -1) + CloseConnection(); + } + + void OnTestProgramStart(const UnitTest& /* unit_test */) { + Send("event=TestProgramStart\n"); + } + + void OnTestProgramEnd(const UnitTest& unit_test) { + // Note that Google Test current only report elapsed time for each + // test iteration, not for the entire test program. + Send(String::Format("event=TestProgramEnd&passed=%d\n", + unit_test.Passed())); + + // Notify the streaming server to stop. + CloseConnection(); + } + + void OnTestIterationStart(const UnitTest& /* unit_test */, int iteration) { + Send(String::Format("event=TestIterationStart&iteration=%d\n", + iteration)); + } + + void OnTestIterationEnd(const UnitTest& unit_test, int /* iteration */) { + Send(String::Format("event=TestIterationEnd&passed=%d&elapsed_time=%sms\n", + unit_test.Passed(), + StreamableToString(unit_test.elapsed_time()).c_str())); + } + + void OnTestCaseStart(const TestCase& test_case) { + Send(String::Format("event=TestCaseStart&name=%s\n", test_case.name())); + } + + void OnTestCaseEnd(const TestCase& test_case) { + Send(String::Format("event=TestCaseEnd&passed=%d&elapsed_time=%sms\n", + test_case.Passed(), + StreamableToString(test_case.elapsed_time()).c_str())); + } + + void OnTestStart(const TestInfo& test_info) { + Send(String::Format("event=TestStart&name=%s\n", test_info.name())); + } + + void OnTestEnd(const TestInfo& test_info) { + Send(String::Format( + "event=TestEnd&passed=%d&elapsed_time=%sms\n", + (test_info.result())->Passed(), + StreamableToString((test_info.result())->elapsed_time()).c_str())); + } + + void OnTestPartResult(const TestPartResult& test_part_result) { + const char* file_name = test_part_result.file_name(); + if (file_name == NULL) + file_name = ""; + Send(String::Format("event=TestPartResult&file=%s&line=%d&message=", + UrlEncode(file_name).c_str(), + test_part_result.line_number())); + Send(UrlEncode(test_part_result.message()) + "\n"); + } + + private: + // Creates a client socket and connects to the server. + void MakeConnection(); + + // Closes the socket. + void CloseConnection() { + GTEST_CHECK_(sockfd_ != -1) + << "CloseConnection() can be called only when there is a connection."; + + close(sockfd_); + sockfd_ = -1; + } + + // Sends a string to the socket. + void Send(const string& message) { + GTEST_CHECK_(sockfd_ != -1) + << "Send() can be called only when there is a connection."; + + const int len = static_cast(message.length()); + if (write(sockfd_, message.c_str(), len) != len) { + GTEST_LOG_(WARNING) + << "stream_result_to: failed to stream to " + << host_name_ << ":" << port_num_; + } + } + + int sockfd_; // socket file descriptor + const string host_name_; + const string port_num_; + + GTEST_DISALLOW_COPY_AND_ASSIGN_(StreamingListener); +}; // class StreamingListener + +// Checks if str contains '=', '&', '%' or '\n' characters. If yes, +// replaces them by "%xx" where xx is their hexadecimal value. For +// example, replaces "=" with "%3D". This algorithm is O(strlen(str)) +// in both time and space -- important as the input str may contain an +// arbitrarily long test failure message and stack trace. +string StreamingListener::UrlEncode(const char* str) { + string result; + result.reserve(strlen(str) + 1); + for (char ch = *str; ch != '\0'; ch = *++str) { + switch (ch) { + case '%': + case '=': + case '&': + case '\n': + result.append(String::Format("%%%02x", static_cast(ch))); + break; + default: + result.push_back(ch); + break; + } + } + return result; +} + +void StreamingListener::MakeConnection() { + GTEST_CHECK_(sockfd_ == -1) + << "MakeConnection() can't be called when there is already a connection."; + + addrinfo hints; + memset(&hints, 0, sizeof(hints)); + hints.ai_family = AF_UNSPEC; // To allow both IPv4 and IPv6 addresses. + hints.ai_socktype = SOCK_STREAM; + addrinfo* servinfo = NULL; + + // Use the getaddrinfo() to get a linked list of IP addresses for + // the given host name. + const int error_num = getaddrinfo( + host_name_.c_str(), port_num_.c_str(), &hints, &servinfo); + if (error_num != 0) { + GTEST_LOG_(WARNING) << "stream_result_to: getaddrinfo() failed: " + << gai_strerror(error_num); + } + + // Loop through all the results and connect to the first we can. + for (addrinfo* cur_addr = servinfo; sockfd_ == -1 && cur_addr != NULL; + cur_addr = cur_addr->ai_next) { + sockfd_ = socket( + cur_addr->ai_family, cur_addr->ai_socktype, cur_addr->ai_protocol); + if (sockfd_ != -1) { + // Connect the client socket to the server socket. + if (connect(sockfd_, cur_addr->ai_addr, cur_addr->ai_addrlen) == -1) { + close(sockfd_); + sockfd_ = -1; + } + } + } + + freeaddrinfo(servinfo); // all done with this structure + + if (sockfd_ == -1) { + GTEST_LOG_(WARNING) << "stream_result_to: failed to connect to " + << host_name_ << ":" << port_num_; + } +} + +// End of class Streaming Listener +#endif // GTEST_CAN_STREAM_RESULTS__ + // Class ScopedTrace // Pushes the given source file location and message onto a per-thread @@ -3512,19 +3711,6 @@ return env; } -#if GTEST_HAS_EXCEPTIONS -// A failed Google Test assertion will throw an exception of this type -// when exceptions are enabled. We derive it from std::runtime_error, -// which is for errors presumably detectable only at run time. Since -// std::runtime_error inherits from std::exception, many testing -// frameworks know how to extract and print the message inside it. -class GoogleTestFailureException : public ::std::runtime_error { - public: - explicit GoogleTestFailureException(const TestPartResult& failure) - : ::std::runtime_error(PrintTestPartResultToString(failure).c_str()) {} -}; -#endif - // Adds a TestPartResult to the current TestResult object. All Google Test // assertion macros (e.g. ASSERT_TRUE, EXPECT_EQ, etc) eventually call // this to report their results. The user code should use the @@ -3601,31 +3787,34 @@ // We don't protect this under mutex_, as we only support calling it // from the main thread. int UnitTest::Run() { -#if GTEST_HAS_SEH - // Catch SEH-style exceptions. + // Captures the value of GTEST_FLAG(catch_exceptions). This value will be + // used for the duration of the program. + impl()->set_catch_exceptions(GTEST_FLAG(catch_exceptions)); +#if GTEST_HAS_SEH const bool in_death_test_child_process = internal::GTEST_FLAG(internal_run_death_test).length() > 0; // Either the user wants Google Test to catch exceptions thrown by the // tests or this is executing in the context of death test child // process. In either case the user does not want to see pop-up dialogs - // about crashes - they are expected.. - if (GTEST_FLAG(catch_exceptions) || in_death_test_child_process) { -#if !GTEST_OS_WINDOWS_MOBILE + // about crashes - they are expected. + if (impl()->catch_exceptions() || in_death_test_child_process) { + +# if !GTEST_OS_WINDOWS_MOBILE // SetErrorMode doesn't exist on CE. SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOALIGNMENTFAULTEXCEPT | SEM_NOGPFAULTERRORBOX | SEM_NOOPENFILEERRORBOX); -#endif // !GTEST_OS_WINDOWS_MOBILE +# endif // !GTEST_OS_WINDOWS_MOBILE -#if (defined(_MSC_VER) || GTEST_OS_WINDOWS_MINGW) && !GTEST_OS_WINDOWS_MOBILE +# if (defined(_MSC_VER) || GTEST_OS_WINDOWS_MINGW) && !GTEST_OS_WINDOWS_MOBILE // Death test children can be terminated with _abort(). On Windows, // _abort() can show a dialog with a warning message. This forces the // abort message to go to stderr instead. _set_error_mode(_OUT_TO_STDERR); -#endif +# endif -#if _MSC_VER >= 1400 && !GTEST_OS_WINDOWS_MOBILE +# if _MSC_VER >= 1400 && !GTEST_OS_WINDOWS_MOBILE // In the debug version, Visual Studio pops up a separate dialog // offering a choice to debug the aborted program. We need to suppress // this dialog or it will pop up for every EXPECT/ASSERT_DEATH statement @@ -3641,22 +3830,15 @@ _set_abort_behavior( 0x0, // Clear the following flags: _WRITE_ABORT_MSG | _CALL_REPORTFAULT); // pop-up window, core dump. -#endif - } +# endif - __try { - return impl_->RunAllTests(); - } __except(internal::UnitTestOptions::GTestShouldProcessSEH( - GetExceptionCode())) { - printf("Exception thrown with code 0x%x.\nFAIL\n", GetExceptionCode()); - fflush(stdout); - return 1; } - -#else // We are on a compiler or platform that doesn't support SEH. - - return impl_->RunAllTests(); #endif // GTEST_HAS_SEH + + return internal::HandleExceptionsInMethodIfSupported( + impl(), + &internal::UnitTestImpl::RunAllTests, + "auxiliary test code (environments or event listeners)") ? 0 : 1; } // Returns the working directory when the first TEST() or TEST_F() was @@ -3724,12 +3906,12 @@ UnitTestImpl::UnitTestImpl(UnitTest* parent) : parent_(parent), #ifdef _MSC_VER -#pragma warning(push) // Saves the current warning state. -#pragma warning(disable:4355) // Temporarily disables warning 4355 +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4355) // Temporarily disables warning 4355 // (using this in initializer). default_global_test_part_result_reporter_(this), default_per_thread_test_part_result_reporter_(this), -#pragma warning(pop) // Restores the warning state again. +# pragma warning(pop) // Restores the warning state again. #else default_global_test_part_result_reporter_(this), default_per_thread_test_part_result_reporter_(this), @@ -3750,13 +3932,13 @@ post_flag_parse_init_performed_(false), random_seed_(0), // Will be overridden by the flag before first use. random_(0), // Will be reseeded before first use. -#if GTEST_HAS_DEATH_TEST elapsed_time_(0), +#if GTEST_HAS_DEATH_TEST internal_run_death_test_flag_(NULL), - death_test_factory_(new DefaultDeathTestFactory) { -#else - elapsed_time_(0) { -#endif // GTEST_HAS_DEATH_TEST + death_test_factory_(new DefaultDeathTestFactory), +#endif + // Will be overridden by the flag before first use. + catch_exceptions_(false) { listeners()->SetDefaultResultPrinter(new PrettyUnitTestResultPrinter); } @@ -3793,6 +3975,25 @@ } } +#if GTEST_CAN_STREAM_RESULTS_ +// Initializes event listeners for streaming test results in String form. +// Must not be called before InitGoogleTest. +void UnitTestImpl::ConfigureStreamingOutput() { + const string& target = GTEST_FLAG(stream_result_to); + if (!target.empty()) { + const size_t pos = target.find(':'); + if (pos != string::npos) { + listeners()->Append(new StreamingListener(target.substr(0, pos), + target.substr(pos+1))); + } else { + printf("WARNING: unrecognized streaming target \"%s\" ignored.\n", + target.c_str()); + fflush(stdout); + } + } +} +#endif // GTEST_CAN_STREAM_RESULTS_ + // Performs initialization dependent upon flag values obtained in // ParseGoogleTestFlagsOnly. Is called from InitGoogleTest after the call to // ParseGoogleTestFlagsOnly. In case a user neglects to call InitGoogleTest @@ -3816,6 +4017,11 @@ // Configures listeners for XML output. This makes it possible for users // to shut down the default XML output before invoking RUN_ALL_TESTS. ConfigureXmlOutput(); + +#if GTEST_CAN_STREAM_RESULTS_ + // Configures listeners for streaming test results to the specified server. + ConfigureStreamingOutput(); +#endif // GTEST_CAN_STREAM_RESULTS_ } } @@ -3850,10 +4056,12 @@ // Arguments: // // test_case_name: name of the test case +// type_param: the name of the test case's type parameter, or NULL if +// this is not a typed or a type-parameterized test case. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase* UnitTestImpl::GetTestCase(const char* test_case_name, - const char* comment, + const char* type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc) { // Can we find a TestCase with the given name? @@ -3866,7 +4074,7 @@ // No. Let's create one. TestCase* const new_test_case = - new TestCase(test_case_name, comment, set_up_tc, tear_down_tc); + new TestCase(test_case_name, type_param, set_up_tc, tear_down_tc); // Is this a death test case? if (internal::UnitTestOptions::MatchesFilter(String(test_case_name), @@ -3893,27 +4101,26 @@ static void TearDownEnvironment(Environment* env) { env->TearDown(); } // Runs all tests in this UnitTest object, prints the result, and -// returns 0 if all tests are successful, or 1 otherwise. If any -// exception is thrown during a test on Windows, this test is -// considered to be failed, but the rest of the tests will still be -// run. (We disable exceptions on Linux and Mac OS X, so the issue -// doesn't apply there.) +// returns true if all tests are successful. If any exception is +// thrown during a test, the test is considered to be failed, but the +// rest of the tests will still be run. +// // When parameterized tests are enabled, it expands and registers // parameterized tests first in RegisterParameterizedTests(). // All other functions called from RunAllTests() may safely assume that // parameterized tests are ready to be counted and run. -int UnitTestImpl::RunAllTests() { +bool UnitTestImpl::RunAllTests() { // Makes sure InitGoogleTest() was called. if (!GTestIsInitialized()) { printf("%s", "\nThis test program did NOT call ::testing::InitGoogleTest " "before calling RUN_ALL_TESTS(). Please fix it.\n"); - return 1; + return false; } // Do not run any test if the --help flag was specified. if (g_help_flag) - return 0; + return true; // Repeats the call to the post-flag parsing initialization in case the // user didn't call InitGoogleTest. @@ -3945,7 +4152,7 @@ if (GTEST_FLAG(list_tests)) { // This must be called *after* FilterTests() has been called. ListTestsMatchingFilter(); - return 0; + return true; } random_seed_ = GTEST_FLAG(shuffle) ? @@ -3964,7 +4171,9 @@ // Repeats forever if the repeat count is negative. const bool forever = repeat < 0; for (int i = 0; forever || i != repeat; i++) { - ClearResult(); + // We want to preserve failures generated by ad-hoc test + // assertions executed before RUN_ALL_TESTS(). + ClearNonAdHocTestResult(); const TimeInMillis start = GetTimeInMillis(); @@ -4029,8 +4238,7 @@ repeater->OnTestProgramEnd(*parent_); - // Returns 0 if all tests passed, or 1 other wise. - return failed ? 1 : 0; + return !failed; } // Reads the GTEST_SHARD_STATUS_FILE environment variable, and creates the file @@ -4104,7 +4312,7 @@ // Parses the environment variable var as an Int32. If it is unset, // returns default_val. If it is not an Int32, prints an error // and aborts. -Int32 Int32FromEnvOrDie(const char* const var, Int32 default_val) { +Int32 Int32FromEnvOrDie(const char* var, Int32 default_val) { const char* str_val = posix::GetEnv(var); if (str_val == NULL) { return default_val; @@ -4160,12 +4368,12 @@ kDisableTestFilter) || internal::UnitTestOptions::MatchesFilter(test_name, kDisableTestFilter); - test_info->impl()->set_is_disabled(is_disabled); + test_info->is_disabled_ = is_disabled; const bool matches_filter = internal::UnitTestOptions::FilterMatchesTest(test_case_name, test_name); - test_info->impl()->set_matches_filter(matches_filter); + test_info->matches_filter_ = matches_filter; const bool is_runnable = (GTEST_FLAG(also_run_disabled_tests) || !is_disabled) && @@ -4179,7 +4387,7 @@ num_runnable_tests += is_runnable; num_selected_tests += is_selected; - test_info->impl()->set_should_run(is_selected); + test_info->should_run_ = is_selected; test_case->set_should_run(test_case->should_run() || is_selected); } } @@ -4195,7 +4403,7 @@ for (size_t j = 0; j < test_case->test_info_list().size(); j++) { const TestInfo* const test_info = test_case->test_info_list()[j]; - if (test_info->matches_filter()) { + if (test_info->matches_filter_) { if (!printed_test_case_name) { printed_test_case_name = true; printf("%s.\n", test_case->name()); @@ -4235,7 +4443,7 @@ // the TestResult for the ad hoc test if no test is running. TestResult* UnitTestImpl::current_test_result() { return current_test_info_ ? - current_test_info_->impl()->result() : &ad_hoc_test_result_; + &(current_test_info_->result_) : &ad_hoc_test_result_; } // Shuffles all test cases, and the tests within each test case, @@ -4264,32 +4472,6 @@ } } -// TestInfoImpl constructor. The new instance assumes ownership of the test -// factory object. -TestInfoImpl::TestInfoImpl(TestInfo* parent, - const char* a_test_case_name, - const char* a_name, - const char* a_test_case_comment, - const char* a_comment, - TypeId a_fixture_class_id, - internal::TestFactoryBase* factory) : - parent_(parent), - test_case_name_(String(a_test_case_name)), - name_(String(a_name)), - test_case_comment_(String(a_test_case_comment)), - comment_(String(a_comment)), - fixture_class_id_(a_fixture_class_id), - should_run_(false), - is_disabled_(false), - matches_filter_(false), - factory_(factory) { -} - -// TestInfoImpl destructor. -TestInfoImpl::~TestInfoImpl() { - delete factory_; -} - // Returns the current OS stack trace as a String. // // The maximum number of stack frames to be included is specified by @@ -4307,8 +4489,8 @@ return GetUnitTestImpl()->CurrentOsStackTraceExceptTop(skip_count + 1); } -// Used by the GTEST_HIDE_UNREACHABLE_CODE_ macro to suppress unreachable -// code warnings. +// Used by the GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_ macro to +// suppress unreachable code warnings. namespace { class ClassUniqueToAlwaysTrue {}; } @@ -4520,6 +4702,10 @@ GTEST_PATH_SEP_ "@Y|@G:@YFILE_PATH]@D\n" " Generate an XML report in the given directory or with the given file\n" " name. @YFILE_PATH at D defaults to @Gtest_details.xml at D.\n" +#if GTEST_CAN_STREAM_RESULTS_ +" @G--" GTEST_FLAG_PREFIX_ "stream_result_to=@YHOST at G:@YPORT at D\n" +" Stream test results to the given server.\n" +#endif // GTEST_CAN_STREAM_RESULTS_ "\n" "Assertion Behavior:\n" #if GTEST_HAS_DEATH_TEST && !GTEST_OS_WINDOWS @@ -4530,10 +4716,9 @@ " Turn assertion failures into debugger break-points.\n" " @G--" GTEST_FLAG_PREFIX_ "throw_on_failure at D\n" " Turn assertion failures into C++ exceptions.\n" -#if GTEST_OS_WINDOWS -" @G--" GTEST_FLAG_PREFIX_ "catch_exceptions at D\n" -" Suppress pop-ups caused by exceptions.\n" -#endif // GTEST_OS_WINDOWS +" @G--" GTEST_FLAG_PREFIX_ "catch_exceptions=0 at D\n" +" Do not report exceptions as test failures. Instead, allow them\n" +" to crash the program or throw a pop-up (on Windows).\n" "\n" "Except for @G--" GTEST_FLAG_PREFIX_ "list_tests at D, you can alternatively set " "the corresponding\n" @@ -4583,7 +4768,10 @@ ParseBoolFlag(arg, kShuffleFlag, >EST_FLAG(shuffle)) || ParseInt32Flag(arg, kStackTraceDepthFlag, >EST_FLAG(stack_trace_depth)) || - ParseBoolFlag(arg, kThrowOnFailureFlag, >EST_FLAG(throw_on_failure)) + ParseStringFlag(arg, kStreamResultToFlag, + >EST_FLAG(stream_result_to)) || + ParseBoolFlag(arg, kThrowOnFailureFlag, + >EST_FLAG(throw_on_failure)) ) { // Yes. Shift the remainder of the argv list left by one. Note // that argv has (*argc + 1) elements, the last one always being @@ -4641,10 +4829,12 @@ internal::g_executable_path = internal::StreamableToString(argv[0]); #if GTEST_HAS_DEATH_TEST + g_argvs.clear(); for (int i = 0; i != *argc; i++) { g_argvs.push_back(StreamableToString(argv[i])); } + #endif // GTEST_HAS_DEATH_TEST ParseGoogleTestFlagsOnly(argc, argv); Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-death-test.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-death-test.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-death-test.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-death-test.h Wed Jul 27 04:25:14 2011 @@ -38,7 +38,7 @@ #ifndef GTEST_INCLUDE_GTEST_GTEST_DEATH_TEST_H_ #define GTEST_INCLUDE_GTEST_GTEST_DEATH_TEST_H_ -#include +#include "gtest/internal/gtest-death-test-internal.h" namespace testing { @@ -154,24 +154,24 @@ // Asserts that a given statement causes the program to exit, with an // integer exit status that satisfies predicate, and emitting error output // that matches regex. -#define ASSERT_EXIT(statement, predicate, regex) \ - GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_FATAL_FAILURE_) +# define ASSERT_EXIT(statement, predicate, regex) \ + GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_FATAL_FAILURE_) // Like ASSERT_EXIT, but continues on to successive tests in the // test case, if any: -#define EXPECT_EXIT(statement, predicate, regex) \ - GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_NONFATAL_FAILURE_) +# define EXPECT_EXIT(statement, predicate, regex) \ + GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_NONFATAL_FAILURE_) // Asserts that a given statement causes the program to exit, either by // explicitly exiting with a nonzero exit code or being killed by a // signal, and emitting error output that matches regex. -#define ASSERT_DEATH(statement, regex) \ - ASSERT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) +# define ASSERT_DEATH(statement, regex) \ + ASSERT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) // Like ASSERT_DEATH, but continues on to successive tests in the // test case, if any: -#define EXPECT_DEATH(statement, regex) \ - EXPECT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) +# define EXPECT_DEATH(statement, regex) \ + EXPECT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) // Two predicate classes that can be used in {ASSERT,EXPECT}_EXIT*: @@ -187,7 +187,7 @@ const int exit_code_; }; -#if !GTEST_OS_WINDOWS +# if !GTEST_OS_WINDOWS // Tests that an exit code describes an exit due to termination by a // given signal. class GTEST_API_ KilledBySignal { @@ -197,7 +197,7 @@ private: const int signum_; }; -#endif // !GTEST_OS_WINDOWS +# endif // !GTEST_OS_WINDOWS // EXPECT_DEBUG_DEATH asserts that the given statements die in debug mode. // The death testing framework causes this to have interesting semantics, @@ -242,23 +242,23 @@ // EXPECT_EQ(12, DieInDebugOr12(&sideeffect)); // }, "death"); // -#ifdef NDEBUG +# ifdef NDEBUG -#define EXPECT_DEBUG_DEATH(statement, regex) \ +# define EXPECT_DEBUG_DEATH(statement, regex) \ do { statement; } while (::testing::internal::AlwaysFalse()) -#define ASSERT_DEBUG_DEATH(statement, regex) \ +# define ASSERT_DEBUG_DEATH(statement, regex) \ do { statement; } while (::testing::internal::AlwaysFalse()) -#else +# else -#define EXPECT_DEBUG_DEATH(statement, regex) \ +# define EXPECT_DEBUG_DEATH(statement, regex) \ EXPECT_DEATH(statement, regex) -#define ASSERT_DEBUG_DEATH(statement, regex) \ +# define ASSERT_DEBUG_DEATH(statement, regex) \ ASSERT_DEATH(statement, regex) -#endif // NDEBUG for EXPECT_DEBUG_DEATH +# endif // NDEBUG for EXPECT_DEBUG_DEATH #endif // GTEST_HAS_DEATH_TEST // EXPECT_DEATH_IF_SUPPORTED(statement, regex) and @@ -267,14 +267,14 @@ // useful when you are combining death test assertions with normal test // assertions in one test. #if GTEST_HAS_DEATH_TEST -#define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ +# define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ EXPECT_DEATH(statement, regex) -#define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ +# define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ ASSERT_DEATH(statement, regex) #else -#define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ +# define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, ) -#define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ +# define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, return) #endif Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-message.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-message.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-message.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-message.h Wed Jul 27 04:25:14 2011 @@ -48,8 +48,8 @@ #include -#include -#include +#include "gtest/internal/gtest-string.h" +#include "gtest/internal/gtest-internal.h" namespace testing { @@ -58,7 +58,7 @@ // Typical usage: // // 1. You stream a bunch of values to a Message object. -// It will remember the text in a StrStream. +// It will remember the text in a stringstream. // 2. Then you stream the Message object to an ostream. // This causes the text in the Message to be streamed // to the ostream. @@ -74,7 +74,7 @@ // Message is not intended to be inherited from. In particular, its // destructor is not virtual. // -// Note that StrStream behaves differently in gcc and in MSVC. You +// Note that stringstream behaves differently in gcc and in MSVC. You // can stream a NULL char pointer to it in the former, but not in the // latter (it causes an access violation if you do). The Message // class hides this difference by treating a NULL char pointer as @@ -87,27 +87,26 @@ public: // Constructs an empty Message. - // We allocate the StrStream separately because it otherwise each use of + // We allocate the stringstream separately because otherwise each use of // ASSERT/EXPECT in a procedure adds over 200 bytes to the procedure's // stack frame leading to huge stack frames in some cases; gcc does not reuse // the stack space. - Message() : ss_(new internal::StrStream) { + Message() : ss_(new ::std::stringstream) { // By default, we want there to be enough precision when printing // a double to a Message. *ss_ << std::setprecision(std::numeric_limits::digits10 + 2); } // Copy constructor. - Message(const Message& msg) : ss_(new internal::StrStream) { // NOLINT + Message(const Message& msg) : ss_(new ::std::stringstream) { // NOLINT *ss_ << msg.GetString(); } // Constructs a Message from a C-string. - explicit Message(const char* str) : ss_(new internal::StrStream) { + explicit Message(const char* str) : ss_(new ::std::stringstream) { *ss_ << str; } - ~Message() { delete ss_; } #if GTEST_OS_SYMBIAN // Streams a value (either a pointer or not) to this object. template @@ -119,7 +118,7 @@ // Streams a non-pointer value to this object. template inline Message& operator <<(const T& val) { - ::GTestStreamToHelper(ss_, val); + ::GTestStreamToHelper(ss_.get(), val); return *this; } @@ -141,7 +140,7 @@ if (pointer == NULL) { *ss_ << "(null)"; } else { - ::GTestStreamToHelper(ss_, pointer); + ::GTestStreamToHelper(ss_.get(), pointer); } return *this; } @@ -189,10 +188,11 @@ // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. internal::String GetString() const { - return internal::StrStreamToString(ss_); + return internal::StringStreamToString(ss_.get()); } private: + #if GTEST_OS_SYMBIAN // These are needed as the Nokia Symbian Compiler cannot decide between // const T& and const T* in a function template. The Nokia compiler _can_ @@ -203,17 +203,17 @@ if (pointer == NULL) { *ss_ << "(null)"; } else { - ::GTestStreamToHelper(ss_, pointer); + ::GTestStreamToHelper(ss_.get(), pointer); } } template inline void StreamHelper(internal::false_type /*dummy*/, const T& value) { - ::GTestStreamToHelper(ss_, value); + ::GTestStreamToHelper(ss_.get(), value); } #endif // GTEST_OS_SYMBIAN // We'll hold the text streamed to this object here. - internal::StrStream* const ss_; + const internal::scoped_ptr< ::std::stringstream> ss_; // We declare (but don't implement) this to prevent the compiler // from implementing the assignment operator. Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-param-test.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-param-test.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-param-test.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-param-test.h Wed Jul 27 04:25:14 2011 @@ -1,4 +1,6 @@ -// This file was GENERATED by a script. DO NOT EDIT BY HAND!!! +// This file was GENERATED by command: +// pump.py gtest-param-test.h.pump +// DO NOT EDIT BY HAND!!! // Copyright 2008, Google Inc. // All rights reserved. @@ -48,10 +50,12 @@ #if 0 // To write value-parameterized tests, first you should define a fixture -// class. It must be derived from testing::TestWithParam, where T is -// the type of your parameter values. TestWithParam is itself derived -// from testing::Test. T can be any copyable type. If it's a raw pointer, -// you are responsible for managing the lifespan of the pointed values. +// class. It is usually derived from testing::TestWithParam (see below for +// another inheritance scheme that's sometimes useful in more complicated +// class hierarchies), where the type of your parameter values. +// TestWithParam is itself derived from testing::Test. T can be any +// copyable type. If it's a raw pointer, you are responsible for managing the +// lifespan of the pointed values. class FooTest : public ::testing::TestWithParam { // You can implement all the usual class fixture members here. @@ -146,20 +150,46 @@ // In the future, we plan to publish the API for defining new parameter // generators. But for now this interface remains part of the internal // implementation and is subject to change. +// +// +// A parameterized test fixture must be derived from testing::Test and from +// testing::WithParamInterface, where T is the type of the parameter +// values. Inheriting from TestWithParam satisfies that requirement because +// TestWithParam inherits from both Test and WithParamInterface. In more +// complicated hierarchies, however, it is occasionally useful to inherit +// separately from Test and WithParamInterface. For example: + +class BaseTest : public ::testing::Test { + // You can inherit all the usual members for a non-parameterized test + // fixture here. +}; + +class DerivedTest : public BaseTest, public ::testing::WithParamInterface { + // The usual test fixture members go here too. +}; + +TEST_F(BaseTest, HasFoo) { + // This is an ordinary non-parameterized test. +} + +TEST_P(DerivedTest, DoesBlah) { + // GetParam works just the same here as if you inherit from TestWithParam. + EXPECT_TRUE(foo.Blah(GetParam())); +} #endif // 0 -#include +#include "gtest/internal/gtest-port.h" #if !GTEST_OS_SYMBIAN -#include +# include #endif // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. -#include -#include +#include "gtest/internal/gtest-internal.h" +#include "gtest/internal/gtest-param-util.h" #if GTEST_HAS_PARAM_TEST @@ -275,11 +305,10 @@ // template internal::ParamGenerator< - typename ::std::iterator_traits::value_type> ValuesIn( - ForwardIterator begin, - ForwardIterator end) { - typedef typename ::std::iterator_traits::value_type - ParamType; + typename ::testing::internal::IteratorTraits::value_type> +ValuesIn(ForwardIterator begin, ForwardIterator end) { + typedef typename ::testing::internal::IteratorTraits + ::value_type ParamType; return internal::ParamGenerator( new internal::ValuesInIteratorRangeGenerator(begin, end)); } @@ -1197,7 +1226,7 @@ return Values(false, true); } -#if GTEST_HAS_COMBINE +# if GTEST_HAS_COMBINE // Combine() allows the user to combine two or more sequences to produce // values of a Cartesian product of those sequences' elements. // @@ -1349,11 +1378,11 @@ Generator10>( g1, g2, g3, g4, g5, g6, g7, g8, g9, g10); } -#endif // GTEST_HAS_COMBINE +# endif // GTEST_HAS_COMBINE -#define TEST_P(test_case_name, test_name) \ +# define TEST_P(test_case_name, test_name) \ class GTEST_TEST_CLASS_NAME_(test_case_name, test_name) \ : public test_case_name { \ public: \ @@ -1379,7 +1408,7 @@ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)::AddToRegistry(); \ void GTEST_TEST_CLASS_NAME_(test_case_name, test_name)::TestBody() -#define INSTANTIATE_TEST_CASE_P(prefix, test_case_name, generator) \ +# define INSTANTIATE_TEST_CASE_P(prefix, test_case_name, generator) \ ::testing::internal::ParamGenerator \ gtest_##prefix##test_case_name##_EvalGenerator_() { return generator; } \ int gtest_##prefix##test_case_name##_dummy_ = \ Added: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-printers.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-printers.h?rev=136212&view=auto ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-printers.h (added) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-printers.h Wed Jul 27 04:25:14 2011 @@ -0,0 +1,796 @@ +// Copyright 2007, Google Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following disclaimer +// in the documentation and/or other materials provided with the +// distribution. +// * Neither the name of Google Inc. nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Author: wan at google.com (Zhanyong Wan) + +// Google Test - The Google C++ Testing Framework +// +// This file implements a universal value printer that can print a +// value of any type T: +// +// void ::testing::internal::UniversalPrinter::Print(value, ostream_ptr); +// +// A user can teach this function how to print a class type T by +// defining either operator<<() or PrintTo() in the namespace that +// defines T. More specifically, the FIRST defined function in the +// following list will be used (assuming T is defined in namespace +// foo): +// +// 1. foo::PrintTo(const T&, ostream*) +// 2. operator<<(ostream&, const T&) defined in either foo or the +// global namespace. +// +// If none of the above is defined, it will print the debug string of +// the value if it is a protocol buffer, or print the raw bytes in the +// value otherwise. +// +// To aid debugging: when T is a reference type, the address of the +// value is also printed; when T is a (const) char pointer, both the +// pointer value and the NUL-terminated string it points to are +// printed. +// +// We also provide some convenient wrappers: +// +// // Prints a value to a string. For a (const or not) char +// // pointer, the NUL-terminated string (but not the pointer) is +// // printed. +// std::string ::testing::PrintToString(const T& value); +// +// // Prints a value tersely: for a reference type, the referenced +// // value (but not the address) is printed; for a (const or not) char +// // pointer, the NUL-terminated string (but not the pointer) is +// // printed. +// void ::testing::internal::UniversalTersePrint(const T& value, ostream*); +// +// // Prints value using the type inferred by the compiler. The difference +// // from UniversalTersePrint() is that this function prints both the +// // pointer and the NUL-terminated string for a (const or not) char pointer. +// void ::testing::internal::UniversalPrint(const T& value, ostream*); +// +// // Prints the fields of a tuple tersely to a string vector, one +// // element for each field. Tuple support must be enabled in +// // gtest-port.h. +// std::vector UniversalTersePrintTupleFieldsToStrings( +// const Tuple& value); +// +// Known limitation: +// +// The print primitives print the elements of an STL-style container +// using the compiler-inferred type of *iter where iter is a +// const_iterator of the container. When const_iterator is an input +// iterator but not a forward iterator, this inferred type may not +// match value_type, and the print output may be incorrect. In +// practice, this is rarely a problem as for most containers +// const_iterator is a forward iterator. We'll fix this if there's an +// actual need for it. Note that this fix cannot rely on value_type +// being defined as many user-defined container types don't have +// value_type. + +#ifndef GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ +#define GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ + +#include // NOLINT +#include +#include +#include +#include +#include "gtest/internal/gtest-port.h" +#include "gtest/internal/gtest-internal.h" + +namespace testing { + +// Definitions in the 'internal' and 'internal2' name spaces are +// subject to change without notice. DO NOT USE THEM IN USER CODE! +namespace internal2 { + +// Prints the given number of bytes in the given object to the given +// ostream. +GTEST_API_ void PrintBytesInObjectTo(const unsigned char* obj_bytes, + size_t count, + ::std::ostream* os); + +// For selecting which printer to use when a given type has neither << +// nor PrintTo(). +enum TypeKind { + kProtobuf, // a protobuf type + kConvertibleToInteger, // a type implicitly convertible to BiggestInt + // (e.g. a named or unnamed enum type) + kOtherType // anything else +}; + +// TypeWithoutFormatter::PrintValue(value, os) is called +// by the universal printer to print a value of type T when neither +// operator<< nor PrintTo() is defined for T, where kTypeKind is the +// "kind" of T as defined by enum TypeKind. +template +class TypeWithoutFormatter { + public: + // This default version is called when kTypeKind is kOtherType. + static void PrintValue(const T& value, ::std::ostream* os) { + PrintBytesInObjectTo(reinterpret_cast(&value), + sizeof(value), os); + } +}; + +// We print a protobuf using its ShortDebugString() when the string +// doesn't exceed this many characters; otherwise we print it using +// DebugString() for better readability. +const size_t kProtobufOneLinerMaxLength = 50; + +template +class TypeWithoutFormatter { + public: + static void PrintValue(const T& value, ::std::ostream* os) { + const ::testing::internal::string short_str = value.ShortDebugString(); + const ::testing::internal::string pretty_str = + short_str.length() <= kProtobufOneLinerMaxLength ? + short_str : ("\n" + value.DebugString()); + *os << ("<" + pretty_str + ">"); + } +}; + +template +class TypeWithoutFormatter { + public: + // Since T has no << operator or PrintTo() but can be implicitly + // converted to BiggestInt, we print it as a BiggestInt. + // + // Most likely T is an enum type (either named or unnamed), in which + // case printing it as an integer is the desired behavior. In case + // T is not an enum, printing it as an integer is the best we can do + // given that it has no user-defined printer. + static void PrintValue(const T& value, ::std::ostream* os) { + const internal::BiggestInt kBigInt = value; + *os << kBigInt; + } +}; + +// Prints the given value to the given ostream. If the value is a +// protocol message, its debug string is printed; if it's an enum or +// of a type implicitly convertible to BiggestInt, it's printed as an +// integer; otherwise the bytes in the value are printed. This is +// what UniversalPrinter::Print() does when it knows nothing about +// type T and T has neither << operator nor PrintTo(). +// +// A user can override this behavior for a class type Foo by defining +// a << operator in the namespace where Foo is defined. +// +// We put this operator in namespace 'internal2' instead of 'internal' +// to simplify the implementation, as much code in 'internal' needs to +// use << in STL, which would conflict with our own << were it defined +// in 'internal'. +// +// Note that this operator<< takes a generic std::basic_ostream type instead of the more restricted std::ostream. If +// we define it to take an std::ostream instead, we'll get an +// "ambiguous overloads" compiler error when trying to print a type +// Foo that supports streaming to std::basic_ostream, as the compiler cannot tell whether +// operator<<(std::ostream&, const T&) or +// operator<<(std::basic_stream, const Foo&) is more +// specific. +template +::std::basic_ostream& operator<<( + ::std::basic_ostream& os, const T& x) { + TypeWithoutFormatter::value ? kProtobuf : + internal::ImplicitlyConvertible::value ? + kConvertibleToInteger : kOtherType)>::PrintValue(x, &os); + return os; +} + +} // namespace internal2 +} // namespace testing + +// This namespace MUST NOT BE NESTED IN ::testing, or the name look-up +// magic needed for implementing UniversalPrinter won't work. +namespace testing_internal { + +// Used to print a value that is not an STL-style container when the +// user doesn't define PrintTo() for it. +template +void DefaultPrintNonContainerTo(const T& value, ::std::ostream* os) { + // With the following statement, during unqualified name lookup, + // testing::internal2::operator<< appears as if it was declared in + // the nearest enclosing namespace that contains both + // ::testing_internal and ::testing::internal2, i.e. the global + // namespace. For more details, refer to the C++ Standard section + // 7.3.4-1 [namespace.udir]. This allows us to fall back onto + // testing::internal2::operator<< in case T doesn't come with a << + // operator. + // + // We cannot write 'using ::testing::internal2::operator<<;', which + // gcc 3.3 fails to compile due to a compiler bug. + using namespace ::testing::internal2; // NOLINT + + // Assuming T is defined in namespace foo, in the next statement, + // the compiler will consider all of: + // + // 1. foo::operator<< (thanks to Koenig look-up), + // 2. ::operator<< (as the current namespace is enclosed in ::), + // 3. testing::internal2::operator<< (thanks to the using statement above). + // + // The operator<< whose type matches T best will be picked. + // + // We deliberately allow #2 to be a candidate, as sometimes it's + // impossible to define #1 (e.g. when foo is ::std, defining + // anything in it is undefined behavior unless you are a compiler + // vendor.). + *os << value; +} + +} // namespace testing_internal + +namespace testing { +namespace internal { + +// UniversalPrinter::Print(value, ostream_ptr) prints the given +// value to the given ostream. The caller must ensure that +// 'ostream_ptr' is not NULL, or the behavior is undefined. +// +// We define UniversalPrinter as a class template (as opposed to a +// function template), as we need to partially specialize it for +// reference types, which cannot be done with function templates. +template +class UniversalPrinter; + +template +void UniversalPrint(const T& value, ::std::ostream* os); + +// Used to print an STL-style container when the user doesn't define +// a PrintTo() for it. +template +void DefaultPrintTo(IsContainer /* dummy */, + false_type /* is not a pointer */, + const C& container, ::std::ostream* os) { + const size_t kMaxCount = 32; // The maximum number of elements to print. + *os << '{'; + size_t count = 0; + for (typename C::const_iterator it = container.begin(); + it != container.end(); ++it, ++count) { + if (count > 0) { + *os << ','; + if (count == kMaxCount) { // Enough has been printed. + *os << " ..."; + break; + } + } + *os << ' '; + // We cannot call PrintTo(*it, os) here as PrintTo() doesn't + // handle *it being a native array. + internal::UniversalPrint(*it, os); + } + + if (count > 0) { + *os << ' '; + } + *os << '}'; +} + +// Used to print a pointer that is neither a char pointer nor a member +// pointer, when the user doesn't define PrintTo() for it. (A member +// variable pointer or member function pointer doesn't really point to +// a location in the address space. Their representation is +// implementation-defined. Therefore they will be printed as raw +// bytes.) +template +void DefaultPrintTo(IsNotContainer /* dummy */, + true_type /* is a pointer */, + T* p, ::std::ostream* os) { + if (p == NULL) { + *os << "NULL"; + } else { + // C++ doesn't allow casting from a function pointer to any object + // pointer. + // + // IsTrue() silences warnings: "Condition is always true", + // "unreachable code". + if (IsTrue(ImplicitlyConvertible::value)) { + // T is not a function type. We just call << to print p, + // relying on ADL to pick up user-defined << for their pointer + // types, if any. + *os << p; + } else { + // T is a function type, so '*os << p' doesn't do what we want + // (it just prints p as bool). We want to print p as a const + // void*. However, we cannot cast it to const void* directly, + // even using reinterpret_cast, as earlier versions of gcc + // (e.g. 3.4.5) cannot compile the cast when p is a function + // pointer. Casting to UInt64 first solves the problem. + *os << reinterpret_cast( + reinterpret_cast(p)); + } + } +} + +// Used to print a non-container, non-pointer value when the user +// doesn't define PrintTo() for it. +template +void DefaultPrintTo(IsNotContainer /* dummy */, + false_type /* is not a pointer */, + const T& value, ::std::ostream* os) { + ::testing_internal::DefaultPrintNonContainerTo(value, os); +} + +// Prints the given value using the << operator if it has one; +// otherwise prints the bytes in it. This is what +// UniversalPrinter::Print() does when PrintTo() is not specialized +// or overloaded for type T. +// +// A user can override this behavior for a class type Foo by defining +// an overload of PrintTo() in the namespace where Foo is defined. We +// give the user this option as sometimes defining a << operator for +// Foo is not desirable (e.g. the coding style may prevent doing it, +// or there is already a << operator but it doesn't do what the user +// wants). +template +void PrintTo(const T& value, ::std::ostream* os) { + // DefaultPrintTo() is overloaded. The type of its first two + // arguments determine which version will be picked. If T is an + // STL-style container, the version for container will be called; if + // T is a pointer, the pointer version will be called; otherwise the + // generic version will be called. + // + // Note that we check for container types here, prior to we check + // for protocol message types in our operator<<. The rationale is: + // + // For protocol messages, we want to give people a chance to + // override Google Mock's format by defining a PrintTo() or + // operator<<. For STL containers, other formats can be + // incompatible with Google Mock's format for the container + // elements; therefore we check for container types here to ensure + // that our format is used. + // + // The second argument of DefaultPrintTo() is needed to bypass a bug + // in Symbian's C++ compiler that prevents it from picking the right + // overload between: + // + // PrintTo(const T& x, ...); + // PrintTo(T* x, ...); + DefaultPrintTo(IsContainerTest(0), is_pointer(), value, os); +} + +// The following list of PrintTo() overloads tells +// UniversalPrinter::Print() how to print standard types (built-in +// types, strings, plain arrays, and pointers). + +// Overloads for various char types. +GTEST_API_ void PrintTo(unsigned char c, ::std::ostream* os); +GTEST_API_ void PrintTo(signed char c, ::std::ostream* os); +inline void PrintTo(char c, ::std::ostream* os) { + // When printing a plain char, we always treat it as unsigned. This + // way, the output won't be affected by whether the compiler thinks + // char is signed or not. + PrintTo(static_cast(c), os); +} + +// Overloads for other simple built-in types. +inline void PrintTo(bool x, ::std::ostream* os) { + *os << (x ? "true" : "false"); +} + +// Overload for wchar_t type. +// Prints a wchar_t as a symbol if it is printable or as its internal +// code otherwise and also as its decimal code (except for L'\0'). +// The L'\0' char is printed as "L'\\0'". The decimal code is printed +// as signed integer when wchar_t is implemented by the compiler +// as a signed type and is printed as an unsigned integer when wchar_t +// is implemented as an unsigned type. +GTEST_API_ void PrintTo(wchar_t wc, ::std::ostream* os); + +// Overloads for C strings. +GTEST_API_ void PrintTo(const char* s, ::std::ostream* os); +inline void PrintTo(char* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} + +// signed/unsigned char is often used for representing binary data, so +// we print pointers to it as void* to be safe. +inline void PrintTo(const signed char* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} +inline void PrintTo(signed char* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} +inline void PrintTo(const unsigned char* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} +inline void PrintTo(unsigned char* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} + +// MSVC can be configured to define wchar_t as a typedef of unsigned +// short. It defines _NATIVE_WCHAR_T_DEFINED when wchar_t is a native +// type. When wchar_t is a typedef, defining an overload for const +// wchar_t* would cause unsigned short* be printed as a wide string, +// possibly causing invalid memory accesses. +#if !defined(_MSC_VER) || defined(_NATIVE_WCHAR_T_DEFINED) +// Overloads for wide C strings +GTEST_API_ void PrintTo(const wchar_t* s, ::std::ostream* os); +inline void PrintTo(wchar_t* s, ::std::ostream* os) { + PrintTo(ImplicitCast_(s), os); +} +#endif + +// Overload for C arrays. Multi-dimensional arrays are printed +// properly. + +// Prints the given number of elements in an array, without printing +// the curly braces. +template +void PrintRawArrayTo(const T a[], size_t count, ::std::ostream* os) { + UniversalPrint(a[0], os); + for (size_t i = 1; i != count; i++) { + *os << ", "; + UniversalPrint(a[i], os); + } +} + +// Overloads for ::string and ::std::string. +#if GTEST_HAS_GLOBAL_STRING +GTEST_API_ void PrintStringTo(const ::string&s, ::std::ostream* os); +inline void PrintTo(const ::string& s, ::std::ostream* os) { + PrintStringTo(s, os); +} +#endif // GTEST_HAS_GLOBAL_STRING + +GTEST_API_ void PrintStringTo(const ::std::string&s, ::std::ostream* os); +inline void PrintTo(const ::std::string& s, ::std::ostream* os) { + PrintStringTo(s, os); +} + +// Overloads for ::wstring and ::std::wstring. +#if GTEST_HAS_GLOBAL_WSTRING +GTEST_API_ void PrintWideStringTo(const ::wstring&s, ::std::ostream* os); +inline void PrintTo(const ::wstring& s, ::std::ostream* os) { + PrintWideStringTo(s, os); +} +#endif // GTEST_HAS_GLOBAL_WSTRING + +#if GTEST_HAS_STD_WSTRING +GTEST_API_ void PrintWideStringTo(const ::std::wstring&s, ::std::ostream* os); +inline void PrintTo(const ::std::wstring& s, ::std::ostream* os) { + PrintWideStringTo(s, os); +} +#endif // GTEST_HAS_STD_WSTRING + +#if GTEST_HAS_TR1_TUPLE +// Overload for ::std::tr1::tuple. Needed for printing function arguments, +// which are packed as tuples. + +// Helper function for printing a tuple. T must be instantiated with +// a tuple type. +template +void PrintTupleTo(const T& t, ::std::ostream* os); + +// Overloaded PrintTo() for tuples of various arities. We support +// tuples of up-to 10 fields. The following implementation works +// regardless of whether tr1::tuple is implemented using the +// non-standard variadic template feature or not. + +inline void PrintTo(const ::std::tr1::tuple<>& t, ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo(const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} + +template +void PrintTo( + const ::std::tr1::tuple& t, + ::std::ostream* os) { + PrintTupleTo(t, os); +} +#endif // GTEST_HAS_TR1_TUPLE + +// Overload for std::pair. +template +void PrintTo(const ::std::pair& value, ::std::ostream* os) { + *os << '('; + // We cannot use UniversalPrint(value.first, os) here, as T1 may be + // a reference type. The same for printing value.second. + UniversalPrinter::Print(value.first, os); + *os << ", "; + UniversalPrinter::Print(value.second, os); + *os << ')'; +} + +// Implements printing a non-reference type T by letting the compiler +// pick the right overload of PrintTo() for T. +template +class UniversalPrinter { + public: + // MSVC warns about adding const to a function type, so we want to + // disable the warning. +#ifdef _MSC_VER +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4180) // Temporarily disables warning 4180. +#endif // _MSC_VER + + // Note: we deliberately don't call this PrintTo(), as that name + // conflicts with ::testing::internal::PrintTo in the body of the + // function. + static void Print(const T& value, ::std::ostream* os) { + // By default, ::testing::internal::PrintTo() is used for printing + // the value. + // + // Thanks to Koenig look-up, if T is a class and has its own + // PrintTo() function defined in its namespace, that function will + // be visible here. Since it is more specific than the generic ones + // in ::testing::internal, it will be picked by the compiler in the + // following statement - exactly what we want. + PrintTo(value, os); + } + +#ifdef _MSC_VER +# pragma warning(pop) // Restores the warning state. +#endif // _MSC_VER +}; + +// UniversalPrintArray(begin, len, os) prints an array of 'len' +// elements, starting at address 'begin'. +template +void UniversalPrintArray(const T* begin, size_t len, ::std::ostream* os) { + if (len == 0) { + *os << "{}"; + } else { + *os << "{ "; + const size_t kThreshold = 18; + const size_t kChunkSize = 8; + // If the array has more than kThreshold elements, we'll have to + // omit some details by printing only the first and the last + // kChunkSize elements. + // TODO(wan at google.com): let the user control the threshold using a flag. + if (len <= kThreshold) { + PrintRawArrayTo(begin, len, os); + } else { + PrintRawArrayTo(begin, kChunkSize, os); + *os << ", ..., "; + PrintRawArrayTo(begin + len - kChunkSize, kChunkSize, os); + } + *os << " }"; + } +} +// This overload prints a (const) char array compactly. +GTEST_API_ void UniversalPrintArray(const char* begin, + size_t len, + ::std::ostream* os); + +// Implements printing an array type T[N]. +template +class UniversalPrinter { + public: + // Prints the given array, omitting some elements when there are too + // many. + static void Print(const T (&a)[N], ::std::ostream* os) { + UniversalPrintArray(a, N, os); + } +}; + +// Implements printing a reference type T&. +template +class UniversalPrinter { + public: + // MSVC warns about adding const to a function type, so we want to + // disable the warning. +#ifdef _MSC_VER +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4180) // Temporarily disables warning 4180. +#endif // _MSC_VER + + static void Print(const T& value, ::std::ostream* os) { + // Prints the address of the value. We use reinterpret_cast here + // as static_cast doesn't compile when T is a function type. + *os << "@" << reinterpret_cast(&value) << " "; + + // Then prints the value itself. + UniversalPrint(value, os); + } + +#ifdef _MSC_VER +# pragma warning(pop) // Restores the warning state. +#endif // _MSC_VER +}; + +// Prints a value tersely: for a reference type, the referenced value +// (but not the address) is printed; for a (const) char pointer, the +// NUL-terminated string (but not the pointer) is printed. +template +void UniversalTersePrint(const T& value, ::std::ostream* os) { + UniversalPrint(value, os); +} +inline void UniversalTersePrint(const char* str, ::std::ostream* os) { + if (str == NULL) { + *os << "NULL"; + } else { + UniversalPrint(string(str), os); + } +} +inline void UniversalTersePrint(char* str, ::std::ostream* os) { + UniversalTersePrint(static_cast(str), os); +} + +// Prints a value using the type inferred by the compiler. The +// difference between this and UniversalTersePrint() is that for a +// (const) char pointer, this prints both the pointer and the +// NUL-terminated string. +template +void UniversalPrint(const T& value, ::std::ostream* os) { + UniversalPrinter::Print(value, os); +} + +#if GTEST_HAS_TR1_TUPLE +typedef ::std::vector Strings; + +// This helper template allows PrintTo() for tuples and +// UniversalTersePrintTupleFieldsToStrings() to be defined by +// induction on the number of tuple fields. The idea is that +// TuplePrefixPrinter::PrintPrefixTo(t, os) prints the first N +// fields in tuple t, and can be defined in terms of +// TuplePrefixPrinter. + +// The inductive case. +template +struct TuplePrefixPrinter { + // Prints the first N fields of a tuple. + template + static void PrintPrefixTo(const Tuple& t, ::std::ostream* os) { + TuplePrefixPrinter::PrintPrefixTo(t, os); + *os << ", "; + UniversalPrinter::type> + ::Print(::std::tr1::get(t), os); + } + + // Tersely prints the first N fields of a tuple to a string vector, + // one element for each field. + template + static void TersePrintPrefixToStrings(const Tuple& t, Strings* strings) { + TuplePrefixPrinter::TersePrintPrefixToStrings(t, strings); + ::std::stringstream ss; + UniversalTersePrint(::std::tr1::get(t), &ss); + strings->push_back(ss.str()); + } +}; + +// Base cases. +template <> +struct TuplePrefixPrinter<0> { + template + static void PrintPrefixTo(const Tuple&, ::std::ostream*) {} + + template + static void TersePrintPrefixToStrings(const Tuple&, Strings*) {} +}; +// We have to specialize the entire TuplePrefixPrinter<> class +// template here, even though the definition of +// TersePrintPrefixToStrings() is the same as the generic version, as +// Embarcadero (formerly CodeGear, formerly Borland) C++ doesn't +// support specializing a method template of a class template. +template <> +struct TuplePrefixPrinter<1> { + template + static void PrintPrefixTo(const Tuple& t, ::std::ostream* os) { + UniversalPrinter::type>:: + Print(::std::tr1::get<0>(t), os); + } + + template + static void TersePrintPrefixToStrings(const Tuple& t, Strings* strings) { + ::std::stringstream ss; + UniversalTersePrint(::std::tr1::get<0>(t), &ss); + strings->push_back(ss.str()); + } +}; + +// Helper function for printing a tuple. T must be instantiated with +// a tuple type. +template +void PrintTupleTo(const T& t, ::std::ostream* os) { + *os << "("; + TuplePrefixPrinter< ::std::tr1::tuple_size::value>:: + PrintPrefixTo(t, os); + *os << ")"; +} + +// Prints the fields of a tuple tersely to a string vector, one +// element for each field. See the comment before +// UniversalTersePrint() for how we define "tersely". +template +Strings UniversalTersePrintTupleFieldsToStrings(const Tuple& value) { + Strings result; + TuplePrefixPrinter< ::std::tr1::tuple_size::value>:: + TersePrintPrefixToStrings(value, &result); + return result; +} +#endif // GTEST_HAS_TR1_TUPLE + +} // namespace internal + +template +::std::string PrintToString(const T& value) { + ::std::stringstream ss; + internal::UniversalTersePrint(value, &ss); + return ss.str(); +} + +} // namespace testing + +#endif // GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-spi.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-spi.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-spi.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-spi.h Wed Jul 27 04:25:14 2011 @@ -35,7 +35,7 @@ #ifndef GTEST_INCLUDE_GTEST_GTEST_SPI_H_ #define GTEST_INCLUDE_GTEST_GTEST_SPI_H_ -#include +#include "gtest/gtest.h" namespace testing { @@ -98,12 +98,12 @@ // The constructor remembers the arguments. SingleFailureChecker(const TestPartResultArray* results, TestPartResult::Type type, - const char* substr); + const string& substr); ~SingleFailureChecker(); private: const TestPartResultArray* const results_; const TestPartResult::Type type_; - const String substr_; + const string substr_; GTEST_DISALLOW_COPY_AND_ASSIGN_(SingleFailureChecker); }; Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-test-part.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-test-part.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-test-part.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-test-part.h Wed Jul 27 04:25:14 2011 @@ -35,8 +35,8 @@ #include #include -#include -#include +#include "gtest/internal/gtest-internal.h" +#include "gtest/internal/gtest-string.h" namespace testing { Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest-typed-test.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest-typed-test.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest-typed-test.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest-typed-test.h Wed Jul 27 04:25:14 2011 @@ -146,8 +146,8 @@ #endif // 0 -#include -#include +#include "gtest/internal/gtest-port.h" +#include "gtest/internal/gtest-type-util.h" // Implements typed tests. @@ -157,16 +157,16 @@ // // Expands to the name of the typedef for the type parameters of the // given test case. -#define GTEST_TYPE_PARAMS_(TestCaseName) gtest_type_params_##TestCaseName##_ +# define GTEST_TYPE_PARAMS_(TestCaseName) gtest_type_params_##TestCaseName##_ // The 'Types' template argument below must have spaces around it // since some compilers may choke on '>>' when passing a template // instance (e.g. Types) -#define TYPED_TEST_CASE(CaseName, Types) \ +# define TYPED_TEST_CASE(CaseName, Types) \ typedef ::testing::internal::TypeList< Types >::type \ GTEST_TYPE_PARAMS_(CaseName) -#define TYPED_TEST(CaseName, TestName) \ +# define TYPED_TEST(CaseName, TestName) \ template \ class GTEST_TEST_CLASS_NAME_(CaseName, TestName) \ : public CaseName { \ @@ -175,7 +175,7 @@ typedef gtest_TypeParam_ TypeParam; \ virtual void TestBody(); \ }; \ - bool gtest_##CaseName##_##TestName##_registered_ = \ + bool gtest_##CaseName##_##TestName##_registered_ GTEST_ATTRIBUTE_UNUSED_ = \ ::testing::internal::TypeParameterizedTest< \ CaseName, \ ::testing::internal::TemplateSel< \ @@ -196,31 +196,31 @@ // Expands to the namespace name that the type-parameterized tests for // the given type-parameterized test case are defined in. The exact // name of the namespace is subject to change without notice. -#define GTEST_CASE_NAMESPACE_(TestCaseName) \ +# define GTEST_CASE_NAMESPACE_(TestCaseName) \ gtest_case_##TestCaseName##_ // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Expands to the name of the variable used to remember the names of // the defined tests in the given test case. -#define GTEST_TYPED_TEST_CASE_P_STATE_(TestCaseName) \ +# define GTEST_TYPED_TEST_CASE_P_STATE_(TestCaseName) \ gtest_typed_test_case_p_state_##TestCaseName##_ // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE DIRECTLY. // // Expands to the name of the variable used to remember the names of // the registered tests in the given test case. -#define GTEST_REGISTERED_TEST_NAMES_(TestCaseName) \ +# define GTEST_REGISTERED_TEST_NAMES_(TestCaseName) \ gtest_registered_test_names_##TestCaseName##_ // The variables defined in the type-parameterized test macros are // static as typically these macros are used in a .h file that can be // #included in multiple translation units linked together. -#define TYPED_TEST_CASE_P(CaseName) \ +# define TYPED_TEST_CASE_P(CaseName) \ static ::testing::internal::TypedTestCasePState \ GTEST_TYPED_TEST_CASE_P_STATE_(CaseName) -#define TYPED_TEST_P(CaseName, TestName) \ +# define TYPED_TEST_P(CaseName, TestName) \ namespace GTEST_CASE_NAMESPACE_(CaseName) { \ template \ class TestName : public CaseName { \ @@ -229,14 +229,14 @@ typedef gtest_TypeParam_ TypeParam; \ virtual void TestBody(); \ }; \ - static bool gtest_##TestName##_defined_ = \ + static bool gtest_##TestName##_defined_ GTEST_ATTRIBUTE_UNUSED_ = \ GTEST_TYPED_TEST_CASE_P_STATE_(CaseName).AddTestName(\ __FILE__, __LINE__, #CaseName, #TestName); \ } \ template \ void GTEST_CASE_NAMESPACE_(CaseName)::TestName::TestBody() -#define REGISTER_TYPED_TEST_CASE_P(CaseName, ...) \ +# define REGISTER_TYPED_TEST_CASE_P(CaseName, ...) \ namespace GTEST_CASE_NAMESPACE_(CaseName) { \ typedef ::testing::internal::Templates<__VA_ARGS__>::type gtest_AllTests_; \ } \ @@ -247,8 +247,8 @@ // The 'Types' template argument below must have spaces around it // since some compilers may choke on '>>' when passing a template // instance (e.g. Types) -#define INSTANTIATE_TYPED_TEST_CASE_P(Prefix, CaseName, Types) \ - bool gtest_##Prefix##_##CaseName = \ +# define INSTANTIATE_TYPED_TEST_CASE_P(Prefix, CaseName, Types) \ + bool gtest_##Prefix##_##CaseName GTEST_ATTRIBUTE_UNUSED_ = \ ::testing::internal::TypeParameterizedTestCase::type>::Register(\ Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest.h Wed Jul 27 04:25:14 2011 @@ -54,14 +54,15 @@ #include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include "gtest/internal/gtest-internal.h" +#include "gtest/internal/gtest-string.h" +#include "gtest/gtest-death-test.h" +#include "gtest/gtest-message.h" +#include "gtest/gtest-param-test.h" +#include "gtest/gtest-printers.h" +#include "gtest/gtest_prod.h" +#include "gtest/gtest-test-part.h" +#include "gtest/gtest-typed-test.h" // Depending on the platform, different string classes are available. // On Linux, in addition to ::std::string, Google also makes use of @@ -136,6 +137,11 @@ // non-zero code otherwise. GTEST_DECLARE_bool_(throw_on_failure); +// When this flag is set with a "host:port" string, on supported +// platforms test results are streamed to the specified port on +// the specified host machine. +GTEST_DECLARE_string_(stream_result_to); + // The upper limit for valid stack trace depths. const int kMaxStackTraceDepth = 100; @@ -147,7 +153,6 @@ class NoExecDeathTest; class FinalSuccessChecker; class GTestFlagSaver; -class TestInfoImpl; class TestResultAccessor; class TestEventListenersAccessor; class TestEventRepeater; @@ -155,8 +160,6 @@ class UnitTestImpl* GetUnitTestImpl(); void ReportFailureInUnknownLocation(TestPartResult::Type result_type, const String& message); -class PrettyUnitTestResultPrinter; -class XmlUnitTestResultPrinter; // Converts a streamable value to a String. A NULL pointer is // converted to "(null)". When the input value is a ::string, @@ -172,6 +175,14 @@ } // namespace internal +// The friend relationship of some of these classes is cyclic. +// If we don't forward declare them the compiler might confuse the classes +// in friendship clauses with same named classes on the scope. +class Test; +class TestCase; +class TestInfo; +class UnitTest; + // A class for indicating whether an assertion was successful. When // the assertion wasn't successful, the AssertionResult object // remembers a non-empty message that describes how it failed. @@ -270,20 +281,33 @@ // assertion's expectation). When nothing has been streamed into the // object, returns an empty string. const char* message() const { - return message_.get() != NULL && message_->c_str() != NULL ? - message_->c_str() : ""; + return message_.get() != NULL ? message_->c_str() : ""; } // TODO(vladl at google.com): Remove this after making sure no clients use it. // Deprecated; please use message() instead. const char* failure_message() const { return message(); } // Streams a custom failure message into this object. - template AssertionResult& operator<<(const T& value); + template AssertionResult& operator<<(const T& value) { + AppendMessage(Message() << value); + return *this; + } + + // Allows streaming basic output manipulators such as endl or flush into + // this object. + AssertionResult& operator<<( + ::std::ostream& (*basic_manipulator)(::std::ostream& stream)) { + AppendMessage(Message() << basic_manipulator); + return *this; + } private: - // No implementation - we want AssertionResult to be - // copy-constructible but not assignable. - void operator=(const AssertionResult& other); + // Appends the contents of message to message_. + void AppendMessage(const Message& a_message) { + if (message_.get() == NULL) + message_.reset(new ::std::string); + message_->append(a_message.GetString().c_str()); + } // Stores result of the assertion predicate. bool success_; @@ -291,19 +315,10 @@ // construct is not satisfied with the predicate's outcome. // Referenced via a pointer to avoid taking too much stack frame space // with test assertions. - internal::scoped_ptr message_; -}; // class AssertionResult + internal::scoped_ptr< ::std::string> message_; -// Streams a custom failure message into this object. -template -AssertionResult& AssertionResult::operator<<(const T& value) { - Message msg; - if (message_.get() != NULL) - msg << *message_; - msg << value; - message_.reset(new internal::String(msg.GetString())); - return *this; -} + GTEST_DISALLOW_ASSIGN_(AssertionResult); +}; // Makes a successful assertion result. GTEST_API_ AssertionResult AssertionSuccess(); @@ -340,7 +355,7 @@ // Test is not copyable. class GTEST_API_ Test { public: - friend class internal::TestInfoImpl; + friend class TestInfo; // Defines types for pointers to functions that set up and tear down // a test case. @@ -417,6 +432,10 @@ // Sets up, executes, and tears down the test. void Run(); + // Deletes self. We deliberately pick an unusual name for this + // internal method to avoid clashing with names used in user TESTs. + void DeleteSelf_() { delete this; } + // Uses a GTestFlagSaver to save and restore all Google Test flags. const internal::GTestFlagSaver* const gtest_flag_saver_; @@ -531,7 +550,6 @@ friend class UnitTest; friend class internal::DefaultGlobalTestPartResultReporter; friend class internal::ExecDeathTest; - friend class internal::TestInfoImpl; friend class internal::TestResultAccessor; friend class internal::UnitTestImpl; friend class internal::WindowsDeathTest; @@ -611,16 +629,26 @@ ~TestInfo(); // Returns the test case name. - const char* test_case_name() const; + const char* test_case_name() const { return test_case_name_.c_str(); } // Returns the test name. - const char* name() const; + const char* name() const { return name_.c_str(); } - // Returns the test case comment. - const char* test_case_comment() const; + // Returns the name of the parameter type, or NULL if this is not a typed + // or a type-parameterized test. + const char* type_param() const { + if (type_param_.get() != NULL) + return type_param_->c_str(); + return NULL; + } - // Returns the test comment. - const char* comment() const; + // Returns the text representation of the value parameter, or NULL if this + // is not a value-parameterized test. + const char* value_param() const { + if (value_param_.get() != NULL) + return value_param_->c_str(); + return NULL; + } // Returns true if this test should run, that is if the test is not disabled // (or it is disabled but the also_run_disabled_tests flag has been specified) @@ -638,47 +666,70 @@ // // For example, *A*:Foo.* is a filter that matches any string that // contains the character 'A' or starts with "Foo.". - bool should_run() const; + bool should_run() const { return should_run_; } // Returns the result of the test. - const TestResult* result() const; + const TestResult* result() const { return &result_; } private: + #if GTEST_HAS_DEATH_TEST friend class internal::DefaultDeathTestFactory; #endif // GTEST_HAS_DEATH_TEST friend class Test; friend class TestCase; - friend class internal::TestInfoImpl; friend class internal::UnitTestImpl; friend TestInfo* internal::MakeAndRegisterTestInfo( const char* test_case_name, const char* name, - const char* test_case_comment, const char* comment, + const char* type_param, + const char* value_param, internal::TypeId fixture_class_id, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc, internal::TestFactoryBase* factory); - // Returns true if this test matches the user-specified filter. - bool matches_filter() const; - - // Increments the number of death tests encountered in this test so - // far. - int increment_death_test_count(); - - // Accessors for the implementation object. - internal::TestInfoImpl* impl() { return impl_; } - const internal::TestInfoImpl* impl() const { return impl_; } - // Constructs a TestInfo object. The newly constructed instance assumes // ownership of the factory object. TestInfo(const char* test_case_name, const char* name, - const char* test_case_comment, const char* comment, + const char* a_type_param, + const char* a_value_param, internal::TypeId fixture_class_id, internal::TestFactoryBase* factory); - // An opaque implementation object. - internal::TestInfoImpl* impl_; + // Increments the number of death tests encountered in this test so + // far. + int increment_death_test_count() { + return result_.increment_death_test_count(); + } + + // Creates the test object, runs it, records its result, and then + // deletes it. + void Run(); + + static void ClearTestResult(TestInfo* test_info) { + test_info->result_.Clear(); + } + + // These fields are immutable properties of the test. + const std::string test_case_name_; // Test case name + const std::string name_; // Test name + // Name of the parameter type, or NULL if this is not a typed or a + // type-parameterized test. + const internal::scoped_ptr type_param_; + // Text representation of the value parameter, or NULL if this is not a + // value-parameterized test. + const internal::scoped_ptr value_param_; + const internal::TypeId fixture_class_id_; // ID of the test fixture class + bool should_run_; // True iff this test should run + bool is_disabled_; // True iff this test is disabled + bool matches_filter_; // True if this test matches the + // user-specified filter. + internal::TestFactoryBase* const factory_; // The factory that creates + // the test object + + // This field is mutable and needs to be reset before running the + // test for the second time. + TestResult result_; GTEST_DISALLOW_COPY_AND_ASSIGN_(TestInfo); }; @@ -696,9 +747,11 @@ // Arguments: // // name: name of the test case + // a_type_param: the name of the test's type parameter, or NULL if + // this is not a type-parameterized test. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case - TestCase(const char* name, const char* comment, + TestCase(const char* name, const char* a_type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc); @@ -708,8 +761,13 @@ // Gets the name of the TestCase. const char* name() const { return name_.c_str(); } - // Returns the test case comment. - const char* comment() const { return comment_.c_str(); } + // Returns the name of the parameter type, or NULL if this is not a + // type-parameterized test case. + const char* type_param() const { + if (type_param_.get() != NULL) + return type_param_->c_str(); + return NULL; + } // Returns true if any test in this test case should run. bool should_run() const { return should_run_; } @@ -776,17 +834,33 @@ // Runs every test in this TestCase. void Run(); + // Runs SetUpTestCase() for this TestCase. This wrapper is needed + // for catching exceptions thrown from SetUpTestCase(). + void RunSetUpTestCase() { (*set_up_tc_)(); } + + // Runs TearDownTestCase() for this TestCase. This wrapper is + // needed for catching exceptions thrown from TearDownTestCase(). + void RunTearDownTestCase() { (*tear_down_tc_)(); } + // Returns true iff test passed. - static bool TestPassed(const TestInfo * test_info); + static bool TestPassed(const TestInfo* test_info) { + return test_info->should_run() && test_info->result()->Passed(); + } // Returns true iff test failed. - static bool TestFailed(const TestInfo * test_info); + static bool TestFailed(const TestInfo* test_info) { + return test_info->should_run() && test_info->result()->Failed(); + } // Returns true iff test is disabled. - static bool TestDisabled(const TestInfo * test_info); + static bool TestDisabled(const TestInfo* test_info) { + return test_info->is_disabled_; + } // Returns true if the given test should run. - static bool ShouldRunTest(const TestInfo *test_info); + static bool ShouldRunTest(const TestInfo* test_info) { + return test_info->should_run(); + } // Shuffles the tests in this test case. void ShuffleTests(internal::Random* random); @@ -796,8 +870,9 @@ // Name of the test case. internal::String name_; - // Comment on the test case. - internal::String comment_; + // Name of the parameter type, or NULL if this is not a typed or a + // type-parameterized test. + const internal::scoped_ptr type_param_; // The vector of TestInfos in their original order. It owns the // elements in the vector. std::vector test_info_list_; @@ -876,7 +951,7 @@ // Fired before the test starts. virtual void OnTestStart(const TestInfo& test_info) = 0; - // Fired after a failed assertion or a SUCCESS(). + // Fired after a failed assertion or a SUCCEED() invocation. virtual void OnTestPartResult(const TestPartResult& test_part_result) = 0; // Fired after the test ends. @@ -961,10 +1036,10 @@ private: friend class TestCase; + friend class TestInfo; friend class internal::DefaultGlobalTestPartResultReporter; friend class internal::NoExecDeathTest; friend class internal::TestEventListenersAccessor; - friend class internal::TestInfoImpl; friend class internal::UnitTestImpl; // Returns repeater that broadcasts the TestEventListener events to all @@ -1206,30 +1281,6 @@ namespace internal { -// These overloaded versions handle ::std::string and ::std::wstring. -GTEST_API_ inline String FormatForFailureMessage(const ::std::string& str) { - return (Message() << '"' << str << '"').GetString(); -} - -#if GTEST_HAS_STD_WSTRING -GTEST_API_ inline String FormatForFailureMessage(const ::std::wstring& wstr) { - return (Message() << "L\"" << wstr << '"').GetString(); -} -#endif // GTEST_HAS_STD_WSTRING - -// These overloaded versions handle ::string and ::wstring. -#if GTEST_HAS_GLOBAL_STRING -GTEST_API_ inline String FormatForFailureMessage(const ::string& str) { - return (Message() << '"' << str << '"').GetString(); -} -#endif // GTEST_HAS_GLOBAL_STRING - -#if GTEST_HAS_GLOBAL_WSTRING -GTEST_API_ inline String FormatForFailureMessage(const ::wstring& wstr) { - return (Message() << "L\"" << wstr << '"').GetString(); -} -#endif // GTEST_HAS_GLOBAL_WSTRING - // Formats a comparison assertion (e.g. ASSERT_EQ, EXPECT_LT, and etc) // operand to be used in a failure message. The type (but not value) // of the other operand may affect the format. This allows us to @@ -1245,7 +1296,9 @@ template String FormatForComparisonFailureMessage(const T1& value, const T2& /* other_operand */) { - return FormatForFailureMessage(value); + // C++Builder compiles this incorrectly if the namespace isn't explicitly + // given. + return ::testing::PrintToString(value); } // The helper function for {ASSERT|EXPECT}_EQ. @@ -1255,8 +1308,8 @@ const T1& expected, const T2& actual) { #ifdef _MSC_VER -#pragma warning(push) // Saves the current warning state. -#pragma warning(disable:4389) // Temporarily disables warning on +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4389) // Temporarily disables warning on // signed/unsigned mismatch. #pragma warning(disable:4805) // Temporarily disables warning on // unsafe mix of types @@ -1267,7 +1320,7 @@ } #ifdef _MSC_VER -#pragma warning(pop) // Restores the warning state. +# pragma warning(pop) // Restores the warning state. #endif return EqFailure(expected_expression, @@ -1318,7 +1371,7 @@ }; // This specialization is used when the first argument to ASSERT_EQ() -// is a null pointer literal. +// is a null pointer literal, like NULL, false, or 0. template <> class EqHelper { public: @@ -1327,24 +1380,38 @@ // NOT a pointer, e.g. ASSERT_EQ(0, AnIntFunction()) or // EXPECT_EQ(false, a_bool). template - static AssertionResult Compare(const char* expected_expression, - const char* actual_expression, - const T1& expected, - const T2& actual) { + static AssertionResult Compare( + const char* expected_expression, + const char* actual_expression, + const T1& expected, + const T2& actual, + // The following line prevents this overload from being considered if T2 + // is not a pointer type. We need this because ASSERT_EQ(NULL, my_ptr) + // expands to Compare("", "", NULL, my_ptr), which requires a conversion + // to match the Secret* in the other overload, which would otherwise make + // this template match better. + typename EnableIf::value>::type* = 0) { return CmpHelperEQ(expected_expression, actual_expression, expected, actual); } - // This version will be picked when the second argument to - // ASSERT_EQ() is a pointer, e.g. ASSERT_EQ(NULL, a_pointer). - template - static AssertionResult Compare(const char* expected_expression, - const char* actual_expression, - const T1& /* expected */, - T2* actual) { + // This version will be picked when the second argument to ASSERT_EQ() is a + // pointer, e.g. ASSERT_EQ(NULL, a_pointer). + template + static AssertionResult Compare( + const char* expected_expression, + const char* actual_expression, + // We used to have a second template parameter instead of Secret*. That + // template parameter would deduce to 'long', making this a better match + // than the first overload even without the first overload's EnableIf. + // Unfortunately, gcc with -Wconversion-null warns when "passing NULL to + // non-pointer argument" (even a deduced integral argument), so the old + // implementation caused warnings in user code. + Secret* /* expected (NULL) */, + T* actual) { // We already know that 'expected' is a null pointer. return CmpHelperEQ(expected_expression, actual_expression, - static_cast(NULL), actual); + static_cast(NULL), actual); } }; @@ -1365,11 +1432,10 @@ if (val1 op val2) {\ return AssertionSuccess();\ } else {\ - Message msg;\ - msg << "Expected: (" << expr1 << ") " #op " (" << expr2\ + return AssertionFailure() \ + << "Expected: (" << expr1 << ") " #op " (" << expr2\ << "), actual: " << FormatForComparisonFailureMessage(val1, val2)\ << " vs " << FormatForComparisonFailureMessage(val2, val1);\ - return AssertionFailure(msg);\ }\ }\ GTEST_API_ AssertionResult CmpHelper##op_name(\ @@ -1497,18 +1563,18 @@ return AssertionSuccess(); } - StrStream expected_ss; + ::std::stringstream expected_ss; expected_ss << std::setprecision(std::numeric_limits::digits10 + 2) << expected; - StrStream actual_ss; + ::std::stringstream actual_ss; actual_ss << std::setprecision(std::numeric_limits::digits10 + 2) << actual; return EqFailure(expected_expression, actual_expression, - StrStreamToString(&expected_ss), - StrStreamToString(&actual_ss), + StringStreamToString(&expected_ss), + StringStreamToString(&actual_ss), false); } @@ -1566,9 +1632,13 @@ } // namespace internal #if GTEST_HAS_PARAM_TEST -// The abstract base class that all value-parameterized tests inherit from. +// The pure interface class that all value-parameterized tests inherit from. +// A value-parameterized class must inherit from both ::testing::Test and +// ::testing::WithParamInterface. In most cases that just means inheriting +// from ::testing::TestWithParam, but more complicated test hierarchies +// may need to inherit from Test and WithParamInterface at different levels. // -// This class adds support for accessing the test parameter value via +// This interface has support for accessing the test parameter value via // the GetParam() method. // // Use it with one of the parameter generator defining functions, like Range(), @@ -1597,12 +1667,16 @@ // INSTANTIATE_TEST_CASE_P(OneToTenRange, FooTest, ::testing::Range(1, 10)); template -class TestWithParam : public Test { +class WithParamInterface { public: typedef T ParamType; + virtual ~WithParamInterface() {} // The current parameter value. Is also available in the test fixture's - // constructor. + // constructor. This member function is non-static, even though it only + // references static data, to reduce the opportunity for incorrect uses + // like writing 'WithParamInterface::GetParam()' for a test that + // uses a fixture whose parameter type is int. const ParamType& GetParam() const { return *parameter_; } private: @@ -1615,12 +1689,19 @@ // Static value used for accessing parameter during a test lifetime. static const ParamType* parameter_; - // TestClass must be a subclass of TestWithParam. + // TestClass must be a subclass of WithParamInterface and Test. template friend class internal::ParameterizedTestFactory; }; template -const T* TestWithParam::parameter_ = NULL; +const T* WithParamInterface::parameter_ = NULL; + +// Most value-parameterized classes can ignore the existence of +// WithParamInterface, and can just inherit from ::testing::TestWithParam. + +template +class TestWithParam : public Test, public WithParamInterface { +}; #endif // GTEST_HAS_PARAM_TEST @@ -1652,13 +1733,19 @@ // Generates a nonfatal failure with a generic message. #define ADD_FAILURE() GTEST_NONFATAL_FAILURE_("Failed") +// Generates a nonfatal failure at the given source file location with +// a generic message. +#define ADD_FAILURE_AT(file, line) \ + GTEST_MESSAGE_AT_(file, line, "Failed", \ + ::testing::TestPartResult::kNonFatalFailure) + // Generates a fatal failure with a generic message. #define GTEST_FAIL() GTEST_FATAL_FAILURE_("Failed") // Define this macro to 1 to omit the definition of FAIL(), which is a // generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_FAIL -#define FAIL() GTEST_FAIL() +# define FAIL() GTEST_FAIL() #endif // Generates a success with a generic message. @@ -1667,7 +1754,7 @@ // Define this macro to 1 to omit the definition of SUCCEED(), which // is a generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_SUCCEED -#define SUCCEED() GTEST_SUCCEED() +# define SUCCEED() GTEST_SUCCEED() #endif // Macros for testing exceptions. @@ -1710,7 +1797,7 @@ // Includes the auto-generated header that implements a family of // generic predicate assertion macros. -#include +#include "gtest/gtest_pred_impl.h" // Macros for testing equalities and inequalities. // @@ -1773,21 +1860,48 @@ #define EXPECT_GT(val1, val2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperGT, val1, val2) -#define ASSERT_EQ(expected, actual) \ +#define GTEST_ASSERT_EQ(expected, actual) \ ASSERT_PRED_FORMAT2(::testing::internal:: \ EqHelper::Compare, \ expected, actual) -#define ASSERT_NE(val1, val2) \ +#define GTEST_ASSERT_NE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperNE, val1, val2) -#define ASSERT_LE(val1, val2) \ +#define GTEST_ASSERT_LE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperLE, val1, val2) -#define ASSERT_LT(val1, val2) \ +#define GTEST_ASSERT_LT(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperLT, val1, val2) -#define ASSERT_GE(val1, val2) \ +#define GTEST_ASSERT_GE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperGE, val1, val2) -#define ASSERT_GT(val1, val2) \ +#define GTEST_ASSERT_GT(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperGT, val1, val2) +// Define macro GTEST_DONT_DEFINE_ASSERT_XY to 1 to omit the definition of +// ASSERT_XY(), which clashes with some users' own code. + +#if !GTEST_DONT_DEFINE_ASSERT_EQ +# define ASSERT_EQ(val1, val2) GTEST_ASSERT_EQ(val1, val2) +#endif + +#if !GTEST_DONT_DEFINE_ASSERT_NE +# define ASSERT_NE(val1, val2) GTEST_ASSERT_NE(val1, val2) +#endif + +#if !GTEST_DONT_DEFINE_ASSERT_LE +# define ASSERT_LE(val1, val2) GTEST_ASSERT_LE(val1, val2) +#endif + +#if !GTEST_DONT_DEFINE_ASSERT_LT +# define ASSERT_LT(val1, val2) GTEST_ASSERT_LT(val1, val2) +#endif + +#if !GTEST_DONT_DEFINE_ASSERT_GE +# define ASSERT_GE(val1, val2) GTEST_ASSERT_GE(val1, val2) +#endif + +#if !GTEST_DONT_DEFINE_ASSERT_GT +# define ASSERT_GT(val1, val2) GTEST_ASSERT_GT(val1, val2) +#endif + // C String Comparisons. All tests treat NULL and any non-NULL string // as different. Two NULLs are equal. // @@ -1884,16 +1998,16 @@ // expected result and the actual result with both a human-readable // string representation of the error, if available, as well as the // hex result code. -#define EXPECT_HRESULT_SUCCEEDED(expr) \ +# define EXPECT_HRESULT_SUCCEEDED(expr) \ EXPECT_PRED_FORMAT1(::testing::internal::IsHRESULTSuccess, (expr)) -#define ASSERT_HRESULT_SUCCEEDED(expr) \ +# define ASSERT_HRESULT_SUCCEEDED(expr) \ ASSERT_PRED_FORMAT1(::testing::internal::IsHRESULTSuccess, (expr)) -#define EXPECT_HRESULT_FAILED(expr) \ +# define EXPECT_HRESULT_FAILED(expr) \ EXPECT_PRED_FORMAT1(::testing::internal::IsHRESULTFailure, (expr)) -#define ASSERT_HRESULT_FAILED(expr) \ +# define ASSERT_HRESULT_FAILED(expr) \ ASSERT_PRED_FORMAT1(::testing::internal::IsHRESULTFailure, (expr)) #endif // GTEST_OS_WINDOWS @@ -1928,17 +2042,6 @@ ::testing::internal::ScopedTrace GTEST_CONCAT_TOKEN_(gtest_trace_, __LINE__)(\ __FILE__, __LINE__, ::testing::Message() << (message)) -namespace internal { - -// This template is declared, but intentionally undefined. -template -struct StaticAssertTypeEqHelper; - -template -struct StaticAssertTypeEqHelper {}; - -} // namespace internal - // Compile-time assertion for type equality. // StaticAssertTypeEq() compiles iff type1 and type2 are // the same type. The value it returns is not interesting. @@ -1971,7 +2074,7 @@ // to cause a compiler error. template bool StaticAssertTypeEq() { - internal::StaticAssertTypeEqHelper(); + (void)internal::StaticAssertTypeEqHelper(); return true; } @@ -2007,7 +2110,7 @@ // Define this macro to 1 to omit the definition of TEST(), which // is a generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_TEST -#define TEST(test_case_name, test_name) GTEST_TEST(test_case_name, test_name) +# define TEST(test_case_name, test_name) GTEST_TEST(test_case_name, test_name) #endif // Defines a test that uses a test fixture. Modified: llvm/trunk/utils/unittest/googletest/include/gtest/gtest_pred_impl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/gtest_pred_impl.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/gtest_pred_impl.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/gtest_pred_impl.h Wed Jul 27 04:25:14 2011 @@ -27,7 +27,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// This file is AUTOMATICALLY GENERATED on 10/02/2008 by command +// This file is AUTOMATICALLY GENERATED on 09/24/2010 by command // 'gen_gtest_pred_impl.py 5'. DO NOT EDIT BY HAND! // // Implements a family of generic predicate assertion macros. @@ -37,7 +37,7 @@ // Makes sure this header is not included before gtest.h. #ifndef GTEST_INCLUDE_GTEST_GTEST_H_ -#error Do not include gtest_pred_impl.h directly. Include gtest.h instead. +# error Do not include gtest_pred_impl.h directly. Include gtest.h instead. #endif // GTEST_INCLUDE_GTEST_GTEST_H_ // This header implements a family of generic predicate assertion @@ -90,11 +90,9 @@ const T1& v1) { if (pred(v1)) return AssertionSuccess(); - Message msg; - msg << pred_text << "(" - << e1 << ") evaluates to false, where" - << "\n" << e1 << " evaluates to " << v1; - return AssertionFailure(msg); + return AssertionFailure() << pred_text << "(" + << e1 << ") evaluates to false, where" + << "\n" << e1 << " evaluates to " << v1; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT1. @@ -136,13 +134,11 @@ const T2& v2) { if (pred(v1, v2)) return AssertionSuccess(); - Message msg; - msg << pred_text << "(" - << e1 << ", " - << e2 << ") evaluates to false, where" - << "\n" << e1 << " evaluates to " << v1 - << "\n" << e2 << " evaluates to " << v2; - return AssertionFailure(msg); + return AssertionFailure() << pred_text << "(" + << e1 << ", " + << e2 << ") evaluates to false, where" + << "\n" << e1 << " evaluates to " << v1 + << "\n" << e2 << " evaluates to " << v2; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT2. @@ -189,15 +185,13 @@ const T3& v3) { if (pred(v1, v2, v3)) return AssertionSuccess(); - Message msg; - msg << pred_text << "(" - << e1 << ", " - << e2 << ", " - << e3 << ") evaluates to false, where" - << "\n" << e1 << " evaluates to " << v1 - << "\n" << e2 << " evaluates to " << v2 - << "\n" << e3 << " evaluates to " << v3; - return AssertionFailure(msg); + return AssertionFailure() << pred_text << "(" + << e1 << ", " + << e2 << ", " + << e3 << ") evaluates to false, where" + << "\n" << e1 << " evaluates to " << v1 + << "\n" << e2 << " evaluates to " << v2 + << "\n" << e3 << " evaluates to " << v3; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT3. @@ -249,17 +243,15 @@ const T4& v4) { if (pred(v1, v2, v3, v4)) return AssertionSuccess(); - Message msg; - msg << pred_text << "(" - << e1 << ", " - << e2 << ", " - << e3 << ", " - << e4 << ") evaluates to false, where" - << "\n" << e1 << " evaluates to " << v1 - << "\n" << e2 << " evaluates to " << v2 - << "\n" << e3 << " evaluates to " << v3 - << "\n" << e4 << " evaluates to " << v4; - return AssertionFailure(msg); + return AssertionFailure() << pred_text << "(" + << e1 << ", " + << e2 << ", " + << e3 << ", " + << e4 << ") evaluates to false, where" + << "\n" << e1 << " evaluates to " << v1 + << "\n" << e2 << " evaluates to " << v2 + << "\n" << e3 << " evaluates to " << v3 + << "\n" << e4 << " evaluates to " << v4; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT4. @@ -316,19 +308,17 @@ const T5& v5) { if (pred(v1, v2, v3, v4, v5)) return AssertionSuccess(); - Message msg; - msg << pred_text << "(" - << e1 << ", " - << e2 << ", " - << e3 << ", " - << e4 << ", " - << e5 << ") evaluates to false, where" - << "\n" << e1 << " evaluates to " << v1 - << "\n" << e2 << " evaluates to " << v2 - << "\n" << e3 << " evaluates to " << v3 - << "\n" << e4 << " evaluates to " << v4 - << "\n" << e5 << " evaluates to " << v5; - return AssertionFailure(msg); + return AssertionFailure() << pred_text << "(" + << e1 << ", " + << e2 << ", " + << e3 << ", " + << e4 << ", " + << e5 << ") evaluates to false, where" + << "\n" << e1 << " evaluates to " << v1 + << "\n" << e2 << " evaluates to " << v2 + << "\n" << e3 << " evaluates to " << v3 + << "\n" << e4 << " evaluates to " << v4 + << "\n" << e5 << " evaluates to " << v5; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT5. Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h Wed Jul 27 04:25:14 2011 @@ -37,7 +37,9 @@ #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_DEATH_TEST_INTERNAL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_DEATH_TEST_INTERNAL_H_ -#include +#include "gtest/internal/gtest-internal.h" + +#include namespace testing { namespace internal { @@ -96,8 +98,12 @@ // test, then wait for it to complete. enum TestRole { OVERSEE_TEST, EXECUTE_TEST }; - // An enumeration of the two reasons that a test might be aborted. - enum AbortReason { TEST_ENCOUNTERED_RETURN_STATEMENT, TEST_DID_NOT_DIE }; + // An enumeration of the three reasons that a test might be aborted. + enum AbortReason { + TEST_ENCOUNTERED_RETURN_STATEMENT, + TEST_THREW_EXCEPTION, + TEST_DID_NOT_DIE + }; // Assumes one of the above roles. virtual TestRole AssumeRole() = 0; @@ -149,9 +155,34 @@ // by a signal, or exited normally with a nonzero exit code. GTEST_API_ bool ExitedUnsuccessfully(int exit_status); +// Traps C++ exceptions escaping statement and reports them as test +// failures. Note that trapping SEH exceptions is not implemented here. +# if GTEST_HAS_EXCEPTIONS +# define GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, death_test) \ + try { \ + GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ + } catch (const ::std::exception& gtest_exception) { \ + fprintf(\ + stderr, \ + "\n%s: Caught std::exception-derived exception escaping the " \ + "death test statement. Exception message: %s\n", \ + ::testing::internal::FormatFileLocation(__FILE__, __LINE__).c_str(), \ + gtest_exception.what()); \ + fflush(stderr); \ + death_test->Abort(::testing::internal::DeathTest::TEST_THREW_EXCEPTION); \ + } catch (...) { \ + death_test->Abort(::testing::internal::DeathTest::TEST_THREW_EXCEPTION); \ + } + +# else +# define GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, death_test) \ + GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement) + +# endif + // This macro is for implementing ASSERT_DEATH*, EXPECT_DEATH*, // ASSERT_EXIT*, and EXPECT_EXIT*. -#define GTEST_DEATH_TEST_(statement, predicate, regex, fail) \ +# define GTEST_DEATH_TEST_(statement, predicate, regex, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ const ::testing::internal::RE& gtest_regex = (regex); \ @@ -172,10 +203,12 @@ case ::testing::internal::DeathTest::EXECUTE_TEST: { \ ::testing::internal::DeathTest::ReturnSentinel \ gtest_sentinel(gtest_dt); \ - GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ + GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, gtest_dt); \ gtest_dt->Abort(::testing::internal::DeathTest::TEST_DID_NOT_DIE); \ break; \ } \ + default: \ + break; \ } \ } \ } else \ @@ -254,7 +287,7 @@ // statement unconditionally returns or throws. The Message constructor at // the end allows the syntax of streaming additional messages into the // macro, for compilational compatibility with EXPECT_DEATH/ASSERT_DEATH. -#define GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, terminator) \ +# define GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, terminator) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ GTEST_LOG_(WARNING) \ Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h Wed Jul 27 04:25:14 2011 @@ -40,7 +40,7 @@ #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_FILEPATH_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_FILEPATH_H_ -#include +#include "gtest/internal/gtest-string.h" namespace testing { namespace internal { Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal-inl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal-inl.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal-inl.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal-inl.h Wed Jul 27 04:25:14 2011 @@ -41,12 +41,12 @@ // part of Google Test's implementation; otherwise it's undefined. #if !GTEST_IMPLEMENTATION_ // A user is trying to include this from his code - just say no. -#error "gtest-internal-inl.h is part of Google Test's internal implementation." -#error "It must not be included except by Google Test itself." +# error "gtest-internal-inl.h is part of Google Test's internal implementation." +# error "It must not be included except by Google Test itself." #endif // GTEST_IMPLEMENTATION_ #ifndef _WIN32_WCE -#include +# include #endif // !_WIN32_WCE #include #include // For strtoll/_strtoul64/malloc/free. @@ -56,14 +56,14 @@ #include #include -#include +#include "gtest/internal/gtest-port.h" #if GTEST_OS_WINDOWS -#include // For DWORD. +# include // NOLINT #endif // GTEST_OS_WINDOWS -#include // NOLINT -#include +#include "gtest/gtest.h" // NOLINT +#include "gtest/gtest-spi.h" namespace testing { @@ -93,6 +93,7 @@ const char kRepeatFlag[] = "repeat"; const char kShuffleFlag[] = "shuffle"; const char kStackTraceDepthFlag[] = "stack_trace_depth"; +const char kStreamResultToFlag[] = "stream_result_to"; const char kThrowOnFailureFlag[] = "throw_on_failure"; // A valid random seed must be in [1, kMaxRandomSeed]. @@ -165,6 +166,7 @@ repeat_ = GTEST_FLAG(repeat); shuffle_ = GTEST_FLAG(shuffle); stack_trace_depth_ = GTEST_FLAG(stack_trace_depth); + stream_result_to_ = GTEST_FLAG(stream_result_to); throw_on_failure_ = GTEST_FLAG(throw_on_failure); } @@ -185,6 +187,7 @@ GTEST_FLAG(repeat) = repeat_; GTEST_FLAG(shuffle) = shuffle_; GTEST_FLAG(stack_trace_depth) = stack_trace_depth_; + GTEST_FLAG(stream_result_to) = stream_result_to_; GTEST_FLAG(throw_on_failure) = throw_on_failure_; } private: @@ -205,6 +208,7 @@ internal::Int32 repeat_; bool shuffle_; internal::Int32 stack_trace_depth_; + String stream_result_to_; bool throw_on_failure_; } GTEST_ATTRIBUTE_UNUSED_; @@ -267,7 +271,14 @@ // the given predicate. template inline int CountIf(const Container& c, Predicate predicate) { - return static_cast(std::count_if(c.begin(), c.end(), predicate)); + // Implemented as an explicit loop since std::count_if() in libCstd on + // Solaris has a non-standard signature. + int count = 0; + for (typename Container::const_iterator it = c.begin(); it != c.end(); ++it) { + if (predicate(*it)) + ++count; + } + return count; } // Applies a function/functor to each element in the container. @@ -340,85 +351,6 @@ String key_; }; -class TestInfoImpl { - public: - TestInfoImpl(TestInfo* parent, const char* test_case_name, - const char* name, const char* test_case_comment, - const char* comment, TypeId fixture_class_id, - internal::TestFactoryBase* factory); - ~TestInfoImpl(); - - // Returns true if this test should run. - bool should_run() const { return should_run_; } - - // Sets the should_run member. - void set_should_run(bool should) { should_run_ = should; } - - // Returns true if this test is disabled. Disabled tests are not run. - bool is_disabled() const { return is_disabled_; } - - // Sets the is_disabled member. - void set_is_disabled(bool is) { is_disabled_ = is; } - - // Returns true if this test matches the filter specified by the user. - bool matches_filter() const { return matches_filter_; } - - // Sets the matches_filter member. - void set_matches_filter(bool matches) { matches_filter_ = matches; } - - // Returns the test case name. - const char* test_case_name() const { return test_case_name_.c_str(); } - - // Returns the test name. - const char* name() const { return name_.c_str(); } - - // Returns the test case comment. - const char* test_case_comment() const { return test_case_comment_.c_str(); } - - // Returns the test comment. - const char* comment() const { return comment_.c_str(); } - - // Returns the ID of the test fixture class. - TypeId fixture_class_id() const { return fixture_class_id_; } - - // Returns the test result. - TestResult* result() { return &result_; } - const TestResult* result() const { return &result_; } - - // Creates the test object, runs it, records its result, and then - // deletes it. - void Run(); - - // Clears the test result. - void ClearResult() { result_.Clear(); } - - // Clears the test result in the given TestInfo object. - static void ClearTestResult(TestInfo * test_info) { - test_info->impl()->ClearResult(); - } - - private: - // These fields are immutable properties of the test. - TestInfo* const parent_; // The owner of this object - const String test_case_name_; // Test case name - const String name_; // Test name - const String test_case_comment_; // Test case comment - const String comment_; // Test comment - const TypeId fixture_class_id_; // ID of the test fixture class - bool should_run_; // True iff this test should run - bool is_disabled_; // True iff this test is disabled - bool matches_filter_; // True if this test matches the - // user-specified filter. - internal::TestFactoryBase* const factory_; // The factory that creates - // the test object - - // This field is mutable and needs to be reset before running the - // test for the second time. - TestResult result_; - - GTEST_DISALLOW_COPY_AND_ASSIGN_(TestInfoImpl); -}; - // Class UnitTestOptions. // // This class contains functions for processing options the user @@ -682,10 +614,12 @@ // Arguments: // // test_case_name: name of the test case + // type_param: the name of the test's type parameter, or NULL if + // this is not a typed or a type-parameterized test. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase* GetTestCase(const char* test_case_name, - const char* comment, + const char* type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc); @@ -698,7 +632,7 @@ // test_info: the TestInfo object void AddTestInfo(Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc, - TestInfo * test_info) { + TestInfo* test_info) { // In order to support thread-safe death tests, we need to // remember the original working directory when the test program // was first invoked. We cannot do this in RUN_ALL_TESTS(), as @@ -713,7 +647,7 @@ } GetTestCase(test_info->test_case_name(), - test_info->test_case_comment(), + test_info->type_param(), set_up_tc, tear_down_tc)->AddTestInfo(test_info); } @@ -739,24 +673,26 @@ } // Registers all parameterized tests defined using TEST_P and - // INSTANTIATE_TEST_P, creating regular tests for each test/parameter - // combination. This method can be called more then once; it has - // guards protecting from registering the tests more then once. - // If value-parameterized tests are disabled, RegisterParameterizedTests - // is present but does nothing. + // INSTANTIATE_TEST_CASE_P, creating regular tests for each test/parameter + // combination. This method can be called more then once; it has guards + // protecting from registering the tests more then once. If + // value-parameterized tests are disabled, RegisterParameterizedTests is + // present but does nothing. void RegisterParameterizedTests(); // Runs all tests in this UnitTest object, prints the result, and - // returns 0 if all tests are successful, or 1 otherwise. If any - // exception is thrown during a test on Windows, this test is - // considered to be failed, but the rest of the tests will still be - // run. (We disable exceptions on Linux and Mac OS X, so the issue - // doesn't apply there.) - int RunAllTests(); + // returns true if all tests are successful. If any exception is + // thrown during a test, this test is considered to be failed, but + // the rest of the tests will still be run. + bool RunAllTests(); - // Clears the results of all tests, including the ad hoc test. - void ClearResult() { + // Clears the results of all tests, except the ad hoc tests. + void ClearNonAdHocTestResult() { ForEach(test_cases_, TestCase::ClearTestCaseResult); + } + + // Clears the results of ad-hoc test assertions. + void ClearAdHocTestResult() { ad_hoc_test_result_.Clear(); } @@ -818,6 +754,12 @@ // UnitTestOptions. Must not be called before InitGoogleTest. void ConfigureXmlOutput(); +#if GTEST_CAN_STREAM_RESULTS_ + // Initializes the event listener for streaming test results to a socket. + // Must not be called before InitGoogleTest. + void ConfigureStreamingOutput(); +#endif + // Performs initialization dependent upon flag values obtained in // ParseGoogleTestFlagsOnly. Is called from InitGoogleTest after the call to // ParseGoogleTestFlagsOnly. In case a user neglects to call InitGoogleTest @@ -838,9 +780,17 @@ // Restores the test cases and tests to their order before the first shuffle. void UnshuffleTests(); + // Returns the value of GTEST_FLAG(catch_exceptions) at the moment + // UnitTest::Run() starts. + bool catch_exceptions() const { return catch_exceptions_; } + private: friend class ::testing::UnitTest; + // Used by UnitTest::Run() to capture the state of + // GTEST_FLAG(catch_exceptions) at the moment it starts. + void set_catch_exceptions(bool value) { catch_exceptions_ = value; } + // The UnitTest object that owns this implementation object. UnitTest* const parent_; @@ -943,6 +893,10 @@ // A per-thread stack of traces created by the SCOPED_TRACE() macro. internal::ThreadLocal > gtest_trace_stack_; + // The value of GTEST_FLAG(catch_exceptions) at the moment RunAllTests() + // starts. + bool catch_exceptions_; + GTEST_DISALLOW_COPY_AND_ASSIGN_(UnitTestImpl); }; // class UnitTestImpl @@ -952,14 +906,16 @@ return UnitTest::GetInstance()->impl(); } +#if GTEST_USES_SIMPLE_RE + // Internal helper functions for implementing the simple regular // expression matcher. GTEST_API_ bool IsInSet(char ch, const char* str); -GTEST_API_ bool IsDigit(char ch); -GTEST_API_ bool IsPunct(char ch); +GTEST_API_ bool IsAsciiDigit(char ch); +GTEST_API_ bool IsAsciiPunct(char ch); GTEST_API_ bool IsRepeat(char ch); -GTEST_API_ bool IsWhiteSpace(char ch); -GTEST_API_ bool IsWordChar(char ch); +GTEST_API_ bool IsAsciiWhiteSpace(char ch); +GTEST_API_ bool IsAsciiWordChar(char ch); GTEST_API_ bool IsValidEscape(char ch); GTEST_API_ bool AtomMatchesChar(bool escaped, char pattern, char ch); GTEST_API_ bool ValidateRegex(const char* regex); @@ -968,6 +924,8 @@ bool escaped, char ch, char repeat, const char* regex, const char* str); GTEST_API_ bool MatchRegexAnywhere(const char* regex, const char* str); +#endif // GTEST_USES_SIMPLE_RE + // Parses the command line for Google Test flags, without initializing // other parts of Google Test. GTEST_API_ void ParseGoogleTestFlagsOnly(int* argc, char** argv); @@ -977,9 +935,9 @@ // Returns the message describing the last system error, regardless of the // platform. -String GetLastErrnoDescription(); +GTEST_API_ String GetLastErrnoDescription(); -#if GTEST_OS_WINDOWS +# if GTEST_OS_WINDOWS // Provides leak-safe Windows kernel handle ownership. class AutoHandle { public: @@ -1003,7 +961,7 @@ GTEST_DISALLOW_COPY_AND_ASSIGN_(AutoHandle); }; -#endif // GTEST_OS_WINDOWS +# endif // GTEST_OS_WINDOWS // Attempts to parse a string into a positive integer pointed to by the // number parameter. Returns true if that is possible. @@ -1014,7 +972,7 @@ // Fail fast if the given string does not begin with a digit; // this bypasses strtoXXX's "optional leading whitespace and plus // or minus sign" semantics, which are undesirable here. - if (str.empty() || !isdigit(str[0])) { + if (str.empty() || !IsDigit(str[0])) { return false; } errno = 0; @@ -1022,14 +980,20 @@ char* end; // BiggestConvertible is the largest integer type that system-provided // string-to-number conversion routines can return. -#if GTEST_OS_WINDOWS && !defined(__GNUC__) + +# if GTEST_OS_WINDOWS && !defined(__GNUC__) + // MSVC and C++ Builder define __int64 instead of the standard long long. typedef unsigned __int64 BiggestConvertible; const BiggestConvertible parsed = _strtoui64(str.c_str(), &end, 10); -#else + +# else + typedef unsigned long long BiggestConvertible; // NOLINT const BiggestConvertible parsed = strtoull(str.c_str(), &end, 10); -#endif // GTEST_OS_WINDOWS && !defined(__GNUC__) + +# endif // GTEST_OS_WINDOWS && !defined(__GNUC__) + const bool parse_success = *end == '\0' && errno == 0; // TODO(vladl at google.com): Convert this to compile time assertion when it is Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-internal.h Wed Jul 27 04:25:14 2011 @@ -37,13 +37,13 @@ #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_INTERNAL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_INTERNAL_H_ -#include +#include "gtest/internal/gtest-port.h" #if GTEST_OS_LINUX -#include -#include -#include -#include +# include +# include +# include +# include #endif // GTEST_OS_LINUX #include @@ -52,9 +52,9 @@ #include #include -#include -#include -#include +#include "gtest/internal/gtest-string.h" +#include "gtest/internal/gtest-filepath.h" +#include "gtest/internal/gtest-type-util.h" #include "llvm/Support/raw_os_ostream.h" @@ -117,9 +117,12 @@ cos << val; } +class ProtocolMessage; +namespace proto2 { class Message; } + namespace testing { -// Forward declaration of classes. +// Forward declarations. class AssertionResult; // Result of an assertion. class Message; // Represents a failure message. @@ -128,6 +131,9 @@ class TestPartResult; // Result of a test part. class UnitTest; // A collection of test cases. +template +::std::string PrintToString(const T& value); + namespace internal { struct TraceInfo; // Information about a trace point. @@ -170,9 +176,9 @@ #ifdef GTEST_ELLIPSIS_NEEDS_POD_ // We lose support for NULL detection where the compiler doesn't like // passing non-POD classes through ellipsis (...). -#define GTEST_IS_NULL_LITERAL_(x) false +# define GTEST_IS_NULL_LITERAL_(x) false #else -#define GTEST_IS_NULL_LITERAL_(x) \ +# define GTEST_IS_NULL_LITERAL_(x) \ (sizeof(::testing::internal::IsNullLiteralHelper(x)) == 1) #endif // GTEST_ELLIPSIS_NEEDS_POD_ @@ -209,72 +215,32 @@ template String StreamableToString(const T& streamable); -// Formats a value to be used in a failure message. - -#ifdef GTEST_NEEDS_IS_POINTER_ - -// These are needed as the Nokia Symbian and IBM XL C/C++ compilers -// cannot decide between const T& and const T* in a function template. -// These compilers _can_ decide between class template specializations -// for T and T*, so a tr1::type_traits-like is_pointer works, and we -// can overload on that. - -// This overload makes sure that all pointers (including -// those to char or wchar_t) are printed as raw pointers. -template -inline String FormatValueForFailureMessage(internal::true_type /*dummy*/, - T* pointer) { - return StreamableToString(static_cast(pointer)); -} - -template -inline String FormatValueForFailureMessage(internal::false_type /*dummy*/, - const T& value) { - return StreamableToString(value); -} - -template -inline String FormatForFailureMessage(const T& value) { - return FormatValueForFailureMessage( - typename internal::is_pointer::type(), value); -} - +// The Symbian compiler has a bug that prevents it from selecting the +// correct overload of FormatForComparisonFailureMessage (see below) +// unless we pass the first argument by reference. If we do that, +// however, Visual Age C++ 10.1 generates a compiler error. Therefore +// we only apply the work-around for Symbian. +#if defined(__SYMBIAN32__) +# define GTEST_CREF_WORKAROUND_ const& #else +# define GTEST_CREF_WORKAROUND_ +#endif -// These are needed as the above solution using is_pointer has the -// limitation that T cannot be a type without external linkage, when -// compiled using MSVC. - -template -inline String FormatForFailureMessage(const T& value) { - return StreamableToString(value); -} - -// This overload makes sure that all pointers (including -// those to char or wchar_t) are printed as raw pointers. -template -inline String FormatForFailureMessage(T* pointer) { - return StreamableToString(static_cast(pointer)); -} - -#endif // GTEST_NEEDS_IS_POINTER_ - -// These overloaded versions handle narrow and wide characters. -GTEST_API_ String FormatForFailureMessage(char ch); -GTEST_API_ String FormatForFailureMessage(wchar_t wchar); - -// When this operand is a const char* or char*, and the other operand +// When this operand is a const char* or char*, if the other operand // is a ::std::string or ::string, we print this operand as a C string -// rather than a pointer. We do the same for wide strings. +// rather than a pointer (we do the same for wide strings); otherwise +// we print it as a pointer to be safe. // This internal macro is used to avoid duplicated code. #define GTEST_FORMAT_IMPL_(operand2_type, operand1_printer)\ inline String FormatForComparisonFailureMessage(\ - operand2_type::value_type* str, const operand2_type& /*operand2*/) {\ + operand2_type::value_type* GTEST_CREF_WORKAROUND_ str, \ + const operand2_type& /*operand2*/) {\ return operand1_printer(str);\ }\ inline String FormatForComparisonFailureMessage(\ - const operand2_type::value_type* str, const operand2_type& /*operand2*/) {\ + const operand2_type::value_type* GTEST_CREF_WORKAROUND_ str, \ + const operand2_type& /*operand2*/) {\ return operand1_printer(str);\ } @@ -292,6 +258,24 @@ #undef GTEST_FORMAT_IMPL_ +// The next four overloads handle the case where the operand being +// printed is a char/wchar_t pointer and the other operand is not a +// string/wstring object. In such cases, we just print the operand as +// a pointer to be safe. +#define GTEST_FORMAT_CHAR_PTR_IMPL_(CharType) \ + template \ + String FormatForComparisonFailureMessage(CharType* GTEST_CREF_WORKAROUND_ p, \ + const T&) { \ + return PrintToString(static_cast(p)); \ + } + +GTEST_FORMAT_CHAR_PTR_IMPL_(char) +GTEST_FORMAT_CHAR_PTR_IMPL_(const char) +GTEST_FORMAT_CHAR_PTR_IMPL_(wchar_t) +GTEST_FORMAT_CHAR_PTR_IMPL_(const wchar_t) + +#undef GTEST_FORMAT_CHAR_PTR_IMPL_ + // Constructs and returns the message for an equality assertion // (e.g. ASSERT_EQ, EXPECT_STREQ, etc) failure. // @@ -578,20 +562,6 @@ #endif // GTEST_OS_WINDOWS -// Formats a source file path and a line number as they would appear -// in a compiler error message. -inline String FormatFileLocation(const char* file, int line) { - const char* const file_name = file == NULL ? "unknown file" : file; - if (line < 0) { - return String::Format("%s:", file_name); - } -#ifdef _MSC_VER - return String::Format("%s(%d):", file_name, line); -#else - return String::Format("%s:%d:", file_name, line); -#endif // _MSC_VER -} - // Types of SetUpTestCase() and TearDownTestCase() functions. typedef void (*SetUpTestCaseFunc)(); typedef void (*TearDownTestCaseFunc)(); @@ -603,10 +573,10 @@ // // test_case_name: name of the test case // name: name of the test -// test_case_comment: a comment on the test case that will be included in -// the test output -// comment: a comment on the test that will be included in the -// test output +// type_param the name of the test's type parameter, or NULL if +// this is not a typed or a type-parameterized test. +// value_param text representation of the test's value parameter, +// or NULL if this is not a type-parameterized test. // fixture_class_id: ID of the test fixture class // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case @@ -615,7 +585,8 @@ // ownership of the factory object. GTEST_API_ TestInfo* MakeAndRegisterTestInfo( const char* test_case_name, const char* name, - const char* test_case_comment, const char* comment, + const char* type_param, + const char* value_param, TypeId fixture_class_id, SetUpTestCaseFunc set_up_tc, TearDownTestCaseFunc tear_down_tc, @@ -624,7 +595,7 @@ // If *pstr starts with the given prefix, modifies *pstr to be right // past the prefix and returns true; otherwise leaves *pstr unchanged // and returns false. None of pstr, *pstr, and prefix can be NULL. -bool SkipPrefix(const char* prefix, const char** pstr); +GTEST_API_ bool SkipPrefix(const char* prefix, const char** pstr); #if GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P @@ -667,7 +638,7 @@ if (comma == NULL) { return NULL; } - while (isspace(*(++comma))) {} + while (IsSpace(*(++comma))) {} return comma; } @@ -704,8 +675,8 @@ String::Format("%s%s%s/%d", prefix, prefix[0] == '\0' ? "" : "/", case_name, index).c_str(), GetPrefixUntilComma(test_names).c_str(), - String::Format("TypeParam = %s", GetTypeName().c_str()).c_str(), - "", + GetTypeName().c_str(), + NULL, // No value parameter. GetTypeId(), TestClass::SetUpTestCase, TestClass::TearDownTestCase, @@ -782,6 +753,15 @@ // Always returns false. inline bool AlwaysFalse() { return !AlwaysTrue(); } +// Helper for suppressing false warning from Clang on a const char* +// variable declared in a conditional expression always being NULL in +// the else branch. +struct GTEST_API_ ConstCharPtr { + ConstCharPtr(const char* str) : value(str) {} + operator bool() const { return true; } + const char* value; +}; + // A simple Linear Congruential Generator for generating random // numbers with a uniform distribution. Unlike rand() and srand(), it // doesn't use global state (and therefore can't interfere with user @@ -804,13 +784,338 @@ GTEST_DISALLOW_COPY_AND_ASSIGN_(Random); }; +// Defining a variable of type CompileAssertTypesEqual will cause a +// compiler error iff T1 and T2 are different types. +template +struct CompileAssertTypesEqual; + +template +struct CompileAssertTypesEqual { +}; + +// Removes the reference from a type if it is a reference type, +// otherwise leaves it unchanged. This is the same as +// tr1::remove_reference, which is not widely available yet. +template +struct RemoveReference { typedef T type; }; // NOLINT +template +struct RemoveReference { typedef T type; }; // NOLINT + +// A handy wrapper around RemoveReference that works when the argument +// T depends on template parameters. +#define GTEST_REMOVE_REFERENCE_(T) \ + typename ::testing::internal::RemoveReference::type + +// Removes const from a type if it is a const type, otherwise leaves +// it unchanged. This is the same as tr1::remove_const, which is not +// widely available yet. +template +struct RemoveConst { typedef T type; }; // NOLINT +template +struct RemoveConst { typedef T type; }; // NOLINT + +// MSVC 8.0, Sun C++, and IBM XL C++ have a bug which causes the above +// definition to fail to remove the const in 'const int[3]' and 'const +// char[3][4]'. The following specialization works around the bug. +// However, it causes trouble with GCC and thus needs to be +// conditionally compiled. +#if defined(_MSC_VER) || defined(__SUNPRO_CC) || defined(__IBMCPP__) +template +struct RemoveConst { + typedef typename RemoveConst::type type[N]; +}; +#endif + +// A handy wrapper around RemoveConst that works when the argument +// T depends on template parameters. +#define GTEST_REMOVE_CONST_(T) \ + typename ::testing::internal::RemoveConst::type + +// Turns const U&, U&, const U, and U all into U. +#define GTEST_REMOVE_REFERENCE_AND_CONST_(T) \ + GTEST_REMOVE_CONST_(GTEST_REMOVE_REFERENCE_(T)) + +// Adds reference to a type if it is not a reference type, +// otherwise leaves it unchanged. This is the same as +// tr1::add_reference, which is not widely available yet. +template +struct AddReference { typedef T& type; }; // NOLINT +template +struct AddReference { typedef T& type; }; // NOLINT + +// A handy wrapper around AddReference that works when the argument T +// depends on template parameters. +#define GTEST_ADD_REFERENCE_(T) \ + typename ::testing::internal::AddReference::type + +// Adds a reference to const on top of T as necessary. For example, +// it transforms +// +// char ==> const char& +// const char ==> const char& +// char& ==> const char& +// const char& ==> const char& +// +// The argument T must depend on some template parameters. +#define GTEST_REFERENCE_TO_CONST_(T) \ + GTEST_ADD_REFERENCE_(const GTEST_REMOVE_REFERENCE_(T)) + +// ImplicitlyConvertible::value is a compile-time bool +// constant that's true iff type From can be implicitly converted to +// type To. +template +class ImplicitlyConvertible { + private: + // We need the following helper functions only for their types. + // They have no implementations. + + // MakeFrom() is an expression whose type is From. We cannot simply + // use From(), as the type From may not have a public default + // constructor. + static From MakeFrom(); + + // These two functions are overloaded. Given an expression + // Helper(x), the compiler will pick the first version if x can be + // implicitly converted to type To; otherwise it will pick the + // second version. + // + // The first version returns a value of size 1, and the second + // version returns a value of size 2. Therefore, by checking the + // size of Helper(x), which can be done at compile time, we can tell + // which version of Helper() is used, and hence whether x can be + // implicitly converted to type To. + static char Helper(To); + static char (&Helper(...))[2]; // NOLINT + + // We have to put the 'public' section after the 'private' section, + // or MSVC refuses to compile the code. + public: + // MSVC warns about implicitly converting from double to int for + // possible loss of data, so we need to temporarily disable the + // warning. +#ifdef _MSC_VER +# pragma warning(push) // Saves the current warning state. +# pragma warning(disable:4244) // Temporarily disables warning 4244. + + static const bool value = + sizeof(Helper(ImplicitlyConvertible::MakeFrom())) == 1; +# pragma warning(pop) // Restores the warning state. +#elif defined(__BORLANDC__) + // C++Builder cannot use member overload resolution during template + // instantiation. The simplest workaround is to use its C++0x type traits + // functions (C++Builder 2009 and above only). + static const bool value = __is_convertible(From, To); +#else + static const bool value = + sizeof(Helper(ImplicitlyConvertible::MakeFrom())) == 1; +#endif // _MSV_VER +}; +template +const bool ImplicitlyConvertible::value; + +// IsAProtocolMessage::value is a compile-time bool constant that's +// true iff T is type ProtocolMessage, proto2::Message, or a subclass +// of those. +template +struct IsAProtocolMessage + : public bool_constant< + ImplicitlyConvertible::value || + ImplicitlyConvertible::value> { +}; + +// When the compiler sees expression IsContainerTest(0), if C is an +// STL-style container class, the first overload of IsContainerTest +// will be viable (since both C::iterator* and C::const_iterator* are +// valid types and NULL can be implicitly converted to them). It will +// be picked over the second overload as 'int' is a perfect match for +// the type of argument 0. If C::iterator or C::const_iterator is not +// a valid type, the first overload is not viable, and the second +// overload will be picked. Therefore, we can determine whether C is +// a container class by checking the type of IsContainerTest(0). +// The value of the expression is insignificant. +// +// Note that we look for both C::iterator and C::const_iterator. The +// reason is that C++ injects the name of a class as a member of the +// class itself (e.g. you can refer to class iterator as either +// 'iterator' or 'iterator::iterator'). If we look for C::iterator +// only, for example, we would mistakenly think that a class named +// iterator is an STL container. +// +// Also note that the simpler approach of overloading +// IsContainerTest(typename C::const_iterator*) and +// IsContainerTest(...) doesn't work with Visual Age C++ and Sun C++. +typedef int IsContainer; +template +IsContainer IsContainerTest(int /* dummy */, + typename C::iterator* /* it */ = NULL, + typename C::const_iterator* /* const_it */ = NULL) { + return 0; +} + +typedef char IsNotContainer; +template +IsNotContainer IsContainerTest(long /* dummy */) { return '\0'; } + +// EnableIf::type is void when 'Cond' is true, and +// undefined when 'Cond' is false. To use SFINAE to make a function +// overload only apply when a particular expression is true, add +// "typename EnableIf::type* = 0" as the last parameter. +template struct EnableIf; +template<> struct EnableIf { typedef void type; }; // NOLINT + +// Utilities for native arrays. + +// ArrayEq() compares two k-dimensional native arrays using the +// elements' operator==, where k can be any integer >= 0. When k is +// 0, ArrayEq() degenerates into comparing a single pair of values. + +template +bool ArrayEq(const T* lhs, size_t size, const U* rhs); + +// This generic version is used when k is 0. +template +inline bool ArrayEq(const T& lhs, const U& rhs) { return lhs == rhs; } + +// This overload is used when k >= 1. +template +inline bool ArrayEq(const T(&lhs)[N], const U(&rhs)[N]) { + return internal::ArrayEq(lhs, N, rhs); +} + +// This helper reduces code bloat. If we instead put its logic inside +// the previous ArrayEq() function, arrays with different sizes would +// lead to different copies of the template code. +template +bool ArrayEq(const T* lhs, size_t size, const U* rhs) { + for (size_t i = 0; i != size; i++) { + if (!internal::ArrayEq(lhs[i], rhs[i])) + return false; + } + return true; +} + +// Finds the first element in the iterator range [begin, end) that +// equals elem. Element may be a native array type itself. +template +Iter ArrayAwareFind(Iter begin, Iter end, const Element& elem) { + for (Iter it = begin; it != end; ++it) { + if (internal::ArrayEq(*it, elem)) + return it; + } + return end; +} + +// CopyArray() copies a k-dimensional native array using the elements' +// operator=, where k can be any integer >= 0. When k is 0, +// CopyArray() degenerates into copying a single value. + +template +void CopyArray(const T* from, size_t size, U* to); + +// This generic version is used when k is 0. +template +inline void CopyArray(const T& from, U* to) { *to = from; } + +// This overload is used when k >= 1. +template +inline void CopyArray(const T(&from)[N], U(*to)[N]) { + internal::CopyArray(from, N, *to); +} + +// This helper reduces code bloat. If we instead put its logic inside +// the previous CopyArray() function, arrays with different sizes +// would lead to different copies of the template code. +template +void CopyArray(const T* from, size_t size, U* to) { + for (size_t i = 0; i != size; i++) { + internal::CopyArray(from[i], to + i); + } +} + +// The relation between an NativeArray object (see below) and the +// native array it represents. +enum RelationToSource { + kReference, // The NativeArray references the native array. + kCopy // The NativeArray makes a copy of the native array and + // owns the copy. +}; + +// Adapts a native array to a read-only STL-style container. Instead +// of the complete STL container concept, this adaptor only implements +// members useful for Google Mock's container matchers. New members +// should be added as needed. To simplify the implementation, we only +// support Element being a raw type (i.e. having no top-level const or +// reference modifier). It's the client's responsibility to satisfy +// this requirement. Element can be an array type itself (hence +// multi-dimensional arrays are supported). +template +class NativeArray { + public: + // STL-style container typedefs. + typedef Element value_type; + typedef Element* iterator; + typedef const Element* const_iterator; + + // Constructs from a native array. + NativeArray(const Element* array, size_t count, RelationToSource relation) { + Init(array, count, relation); + } + + // Copy constructor. + NativeArray(const NativeArray& rhs) { + Init(rhs.array_, rhs.size_, rhs.relation_to_source_); + } + + ~NativeArray() { + // Ensures that the user doesn't instantiate NativeArray with a + // const or reference type. + static_cast(StaticAssertTypeEqHelper()); + if (relation_to_source_ == kCopy) + delete[] array_; + } + + // STL-style container methods. + size_t size() const { return size_; } + const_iterator begin() const { return array_; } + const_iterator end() const { return array_ + size_; } + bool operator==(const NativeArray& rhs) const { + return size() == rhs.size() && + ArrayEq(begin(), size(), rhs.begin()); + } + + private: + // Initializes this object; makes a copy of the input array if + // 'relation' is kCopy. + void Init(const Element* array, size_t a_size, RelationToSource relation) { + if (relation == kReference) { + array_ = array; + } else { + Element* const copy = new Element[a_size]; + CopyArray(array, a_size, copy); + array_ = copy; + } + size_ = a_size; + relation_to_source_ = relation; + } + + const Element* array_; + size_t size_; + RelationToSource relation_to_source_; + + GTEST_DISALLOW_ASSIGN_(NativeArray); +}; + } // namespace internal } // namespace testing -#define GTEST_MESSAGE_(message, result_type) \ - ::testing::internal::AssertHelper(result_type, __FILE__, __LINE__, message) \ +#define GTEST_MESSAGE_AT_(file, line, message, result_type) \ + ::testing::internal::AssertHelper(result_type, file, line, message) \ = ::testing::Message() +#define GTEST_MESSAGE_(message, result_type) \ + GTEST_MESSAGE_AT_(__FILE__, __LINE__, message, result_type) + #define GTEST_FATAL_FAILURE_(message) \ return GTEST_MESSAGE_(message, ::testing::TestPartResult::kFatalFailure) @@ -828,7 +1133,7 @@ #define GTEST_TEST_THROW_(statement, expected_exception, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ - if (const char* gtest_msg = "") { \ + if (::testing::internal::ConstCharPtr gtest_msg = "") { \ bool gtest_caught_expected = false; \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ @@ -837,38 +1142,38 @@ gtest_caught_expected = true; \ } \ catch (...) { \ - gtest_msg = "Expected: " #statement " throws an exception of type " \ - #expected_exception ".\n Actual: it throws a different " \ - "type."; \ + gtest_msg.value = \ + "Expected: " #statement " throws an exception of type " \ + #expected_exception ".\n Actual: it throws a different type."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__); \ } \ if (!gtest_caught_expected) { \ - gtest_msg = "Expected: " #statement " throws an exception of type " \ - #expected_exception ".\n Actual: it throws nothing."; \ + gtest_msg.value = \ + "Expected: " #statement " throws an exception of type " \ + #expected_exception ".\n Actual: it throws nothing."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__): \ - fail(gtest_msg) + fail(gtest_msg.value) #define GTEST_TEST_NO_THROW_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ - if (const char* gtest_msg = "") { \ + if (::testing::internal::AlwaysTrue()) { \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ } \ catch (...) { \ - gtest_msg = "Expected: " #statement " doesn't throw an exception.\n" \ - " Actual: it throws."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testnothrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testnothrow_, __LINE__): \ - fail(gtest_msg) + fail("Expected: " #statement " doesn't throw an exception.\n" \ + " Actual: it throws.") #define GTEST_TEST_ANY_THROW_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ - if (const char* gtest_msg = "") { \ + if (::testing::internal::AlwaysTrue()) { \ bool gtest_caught_any = false; \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ @@ -877,13 +1182,12 @@ gtest_caught_any = true; \ } \ if (!gtest_caught_any) { \ - gtest_msg = "Expected: " #statement " throws an exception.\n" \ - " Actual: it doesn't."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testanythrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testanythrow_, __LINE__): \ - fail(gtest_msg) + fail("Expected: " #statement " throws an exception.\n" \ + " Actual: it doesn't.") // Implements Boolean test assertions such as EXPECT_TRUE. expression can be @@ -900,18 +1204,17 @@ #define GTEST_TEST_NO_FATAL_FAILURE_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ - if (const char* gtest_msg = "") { \ + if (::testing::internal::AlwaysTrue()) { \ ::testing::internal::HasNewFatalFailureHelper gtest_fatal_failure_checker; \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ if (gtest_fatal_failure_checker.has_new_fatal_failure()) { \ - gtest_msg = "Expected: " #statement " doesn't generate new fatal " \ - "failures in the current thread.\n" \ - " Actual: it does."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testnofatal_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testnofatal_, __LINE__): \ - fail(gtest_msg) + fail("Expected: " #statement " doesn't generate new fatal " \ + "failures in the current thread.\n" \ + " Actual: it does.") // Expands to the name of the class that implements the given test. #define GTEST_TEST_CLASS_NAME_(test_case_name, test_name) \ @@ -924,7 +1227,7 @@ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)() {}\ private:\ virtual void TestBody();\ - static ::testing::TestInfo* const test_info_;\ + static ::testing::TestInfo* const test_info_ GTEST_ATTRIBUTE_UNUSED_;\ GTEST_DISALLOW_COPY_AND_ASSIGN_(\ GTEST_TEST_CLASS_NAME_(test_case_name, test_name));\ };\ @@ -932,7 +1235,7 @@ ::testing::TestInfo* const GTEST_TEST_CLASS_NAME_(test_case_name, test_name)\ ::test_info_ =\ ::testing::internal::MakeAndRegisterTestInfo(\ - #test_case_name, #test_name, "", "", \ + #test_case_name, #test_name, NULL, NULL, \ (parent_id), \ parent_class::SetUpTestCase, \ parent_class::TearDownTestCase, \ Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h Wed Jul 27 04:25:14 2011 @@ -71,7 +71,7 @@ #include #include -#include +#include "gtest/internal/gtest-port.h" namespace testing { namespace internal { @@ -172,16 +172,6 @@ T* get() const { return value_; } T* operator->() const { return value_; } T& operator*() const { return *value_; } - // Release ownership of the pointed object and returns it. - // Sole ownership by this linked_ptr object is required. - T* release() { - bool last = link_.depart(); - (void) last; - assert(last); - T* v = value_; - value_ = NULL; - return v; - } bool operator==(T* p) const { return value_ == p; } bool operator!=(T* p) const { return value_ != p; } Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h Wed Jul 27 04:25:14 2011 @@ -1,4 +1,6 @@ -// This file was GENERATED by a script. DO NOT EDIT BY HAND!!! +// This file was GENERATED by command: +// pump.py gtest-param-util-generated.h.pump +// DO NOT EDIT BY HAND!!! // Copyright 2008 Google Inc. // All Rights Reserved. @@ -47,8 +49,8 @@ // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. -#include -#include +#include "gtest/internal/gtest-param-util.h" +#include "gtest/internal/gtest-port.h" #if GTEST_HAS_PARAM_TEST @@ -58,8 +60,8 @@ // include/gtest/gtest-param-test.h. template internal::ParamGenerator< - typename ::std::iterator_traits::value_type> ValuesIn( - ForwardIterator begin, ForwardIterator end); + typename ::testing::internal::IteratorTraits::value_type> +ValuesIn(ForwardIterator begin, ForwardIterator end); template internal::ParamGenerator ValuesIn(const T (&array)[N]); @@ -2826,7 +2828,7 @@ const T50 v50_; }; -#if GTEST_HAS_COMBINE +# if GTEST_HAS_COMBINE // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Generates values from the Cartesian product of values produced @@ -4810,7 +4812,7 @@ const Generator10 g10_; }; // class CartesianProductHolder10 -#endif // GTEST_HAS_COMBINE +# endif // GTEST_HAS_COMBINE } // namespace internal } // namespace testing Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h Wed Jul 27 04:25:14 2011 @@ -41,9 +41,10 @@ // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. -#include -#include -#include +#include "gtest/internal/gtest-internal.h" +#include "gtest/internal/gtest-linked_ptr.h" +#include "gtest/internal/gtest-port.h" +#include "gtest/gtest-printers.h" #if GTEST_HAS_PARAM_TEST @@ -171,7 +172,7 @@ iterator end() const { return iterator(impl_->End()); } private: - ::testing::internal::linked_ptr > impl_; + linked_ptr > impl_; }; // Generates values from a range of two comparable values. Can be used to @@ -285,7 +286,7 @@ public: Iterator(const ParamGeneratorInterface* base, typename ContainerType::const_iterator iterator) - : base_(base), iterator_(iterator) {} + : base_(base), iterator_(iterator) {} virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { @@ -416,7 +417,7 @@ virtual ~ParameterizedTestCaseInfoBase() {} // Base part of test case name for display purposes. - virtual const String& GetTestCaseName() const = 0; + virtual const string& GetTestCaseName() const = 0; // Test case id to verify identity. virtual TypeId GetTestCaseTypeId() const = 0; // UnitTest class invokes this method to register tests in this @@ -453,7 +454,7 @@ : test_case_name_(name) {} // Test case base name for display purposes. - virtual const String& GetTestCaseName() const { return test_case_name_; } + virtual const string& GetTestCaseName() const { return test_case_name_; } // Test case id to verify identity. virtual TypeId GetTestCaseTypeId() const { return GetTypeId(); } // TEST_P macro uses AddTestPattern() to record information @@ -471,7 +472,7 @@ } // INSTANTIATE_TEST_CASE_P macro uses AddGenerator() to record information // about a generator. - int AddTestCaseInstantiation(const char* instantiation_name, + int AddTestCaseInstantiation(const string& instantiation_name, GeneratorCreationFunc* func, const char* /* file */, int /* line */) { @@ -490,26 +491,25 @@ for (typename InstantiationContainer::iterator gen_it = instantiations_.begin(); gen_it != instantiations_.end(); ++gen_it) { - const String& instantiation_name = gen_it->first; + const string& instantiation_name = gen_it->first; ParamGenerator generator((*gen_it->second)()); Message test_case_name_stream; if ( !instantiation_name.empty() ) - test_case_name_stream << instantiation_name.c_str() << "/"; - test_case_name_stream << test_info->test_case_base_name.c_str(); + test_case_name_stream << instantiation_name << "/"; + test_case_name_stream << test_info->test_case_base_name; int i = 0; for (typename ParamGenerator::iterator param_it = generator.begin(); param_it != generator.end(); ++param_it, ++i) { Message test_name_stream; - test_name_stream << test_info->test_base_name.c_str() << "/" << i; - ::testing::internal::MakeAndRegisterTestInfo( + test_name_stream << test_info->test_base_name << "/" << i; + MakeAndRegisterTestInfo( test_case_name_stream.GetString().c_str(), test_name_stream.GetString().c_str(), - "", // test_case_comment - "", // comment; TODO(vladl at google.com): provide parameter value - // representation. + NULL, // No type parameter. + PrintToString(*param_it).c_str(), GetTestCaseTypeId(), TestCase::SetUpTestCase, TestCase::TearDownTestCase, @@ -530,17 +530,17 @@ test_base_name(a_test_base_name), test_meta_factory(a_test_meta_factory) {} - const String test_case_base_name; - const String test_base_name; + const string test_case_base_name; + const string test_base_name; const scoped_ptr > test_meta_factory; }; typedef ::std::vector > TestInfoContainer; // Keeps pairs of // received from INSTANTIATE_TEST_CASE_P macros. - typedef ::std::vector > + typedef ::std::vector > InstantiationContainer; - const String test_case_name_; + const string test_case_name_; TestInfoContainer tests_; InstantiationContainer instantiations_; @@ -579,7 +579,7 @@ // and terminate the program since we cannot guaranty correct // test case setup and tear-down in this case. ReportInvalidTestCaseType(test_case_name, file, line); - abort(); + posix::Abort(); } else { // At this point we are sure that the object we found is of the same // type we are looking for, so we downcast it to that type Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h Wed Jul 27 04:25:14 2011 @@ -50,6 +50,8 @@ // GTEST_HAS_GLOBAL_WSTRING - Define it to 1/0 to indicate that ::string // is/isn't available (some systems define // ::wstring, which is different to std::wstring). +// GTEST_HAS_POSIX_RE - Define it to 1/0 to indicate that POSIX regular +// expressions are/aren't available. // GTEST_HAS_PTHREAD - Define it to 1/0 to indicate that // is/isn't available. // GTEST_HAS_RTTI - Define it to 1/0 to indicate that RTTI is/isn't @@ -62,6 +64,10 @@ // GTEST_HAS_SEH - Define it to 1/0 to indicate whether the // compiler supports Microsoft's "Structured // Exception Handling". +// GTEST_HAS_STREAM_REDIRECTION +// - Define it to 1/0 to indicate whether the +// platform supports I/O stream redirection using +// dup() and dup2(). // GTEST_USE_OWN_TR1_TUPLE - Define it to 1/0 to indicate whether Google // Test's own tr1 tuple implementation should be // used. Unused when the user sets @@ -81,8 +87,11 @@ // GTEST_OS_AIX - IBM AIX // GTEST_OS_CYGWIN - Cygwin // GTEST_OS_HAIKU - Haiku +// GTEST_OS_HPUX - HP-UX // GTEST_OS_LINUX - Linux +// GTEST_OS_LINUX_ANDROID - Google Android // GTEST_OS_MAC - Mac OS X +// GTEST_OS_NACL - Google Native Client (NaCl) // GTEST_OS_SOLARIS - Sun Solaris // GTEST_OS_SYMBIAN - Symbian // GTEST_OS_WINDOWS - Windows (Desktop, MinGW, or Mobile) @@ -108,7 +117,9 @@ // GTEST_HAS_PARAM_TEST - value-parameterized tests // GTEST_HAS_TYPED_TEST - typed tests // GTEST_HAS_TYPED_TEST_P - type-parameterized tests -// GTEST_USES_POSIX_RE - enhanced POSIX regex is used. +// GTEST_USES_POSIX_RE - enhanced POSIX regex is used. Do not confuse with +// GTEST_HAS_POSIX_RE (see above) which users can +// define themselves. // GTEST_USES_SIMPLE_RE - our own simple regex is used; // the above two are mutually exclusive. // GTEST_CAN_COMPARE_NULL - accepts untyped NULL in EXPECT_EQ(). @@ -130,14 +141,17 @@ // // Template meta programming: // is_pointer - as in TR1; needed on Symbian and IBM XL C/C++ only. +// IteratorTraits - partial implementation of std::iterator_traits, which +// is not available in libCstd when compiled with Sun C++. // // Smart pointers: // scoped_ptr - as in TR2. // // Regular expressions: // RE - a simple regular expression class using the POSIX -// Extended Regular Expression syntax. Not available on -// Windows. +// Extended Regular Expression syntax on UNIX-like +// platforms, or a reduced regular exception syntax on +// other platforms, including Windows. // // Logging: // GTEST_LOG_() - logs messages at the specified severity level. @@ -170,12 +184,14 @@ // Int32FromGTestEnv() - parses an Int32 environment variable. // StringFromGTestEnv() - parses a string environment variable. -#include // For ptrdiff_t +#include // for isspace, etc +#include // for ptrdiff_t #include #include #include #ifndef _WIN32_WCE -#include +# include +# include #endif // !_WIN32_WCE #include // NOLINT @@ -192,116 +208,140 @@ // Determines the version of gcc that is used to compile this. #ifdef __GNUC__ // 40302 means version 4.3.2. -#define GTEST_GCC_VER_ \ +# define GTEST_GCC_VER_ \ (__GNUC__*10000 + __GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__) #endif // __GNUC__ // Determines the platform on which Google Test is compiled. #ifdef __CYGWIN__ -#define GTEST_OS_CYGWIN 1 +# define GTEST_OS_CYGWIN 1 #elif defined __SYMBIAN32__ -#define GTEST_OS_SYMBIAN 1 +# define GTEST_OS_SYMBIAN 1 #elif defined _WIN32 -#define GTEST_OS_WINDOWS 1 -#ifdef _WIN32_WCE -#define GTEST_OS_WINDOWS_MOBILE 1 -#elif defined(__MINGW__) || defined(__MINGW32__) -#define GTEST_OS_WINDOWS_MINGW 1 -#else -#define GTEST_OS_WINDOWS_DESKTOP 1 -#endif // _WIN32_WCE +# define GTEST_OS_WINDOWS 1 +# ifdef _WIN32_WCE +# define GTEST_OS_WINDOWS_MOBILE 1 +# elif defined(__MINGW__) || defined(__MINGW32__) +# define GTEST_OS_WINDOWS_MINGW 1 +# else +# define GTEST_OS_WINDOWS_DESKTOP 1 +# endif // _WIN32_WCE #elif defined __APPLE__ -#define GTEST_OS_MAC 1 +# define GTEST_OS_MAC 1 #elif defined __linux__ -#define GTEST_OS_LINUX 1 +# define GTEST_OS_LINUX 1 +# ifdef ANDROID +# define GTEST_OS_LINUX_ANDROID 1 +# endif // ANDROID #elif defined __MVS__ -#define GTEST_OS_ZOS 1 +# define GTEST_OS_ZOS 1 #elif defined(__sun) && defined(__SVR4) -#define GTEST_OS_SOLARIS 1 +# define GTEST_OS_SOLARIS 1 #elif defined(_AIX) -#define GTEST_OS_AIX 1 +# define GTEST_OS_AIX 1 +#elif defined(__hpux) +# define GTEST_OS_HPUX 1 +#elif defined __native_client__ +# define GTEST_OS_NACL 1 #elif defined(__HAIKU__) -#define GTEST_OS_HAIKU 1 +# define GTEST_OS_HAIKU 1 #endif // __CYGWIN__ -#if GTEST_OS_CYGWIN || GTEST_OS_HAIKU || GTEST_OS_LINUX || GTEST_OS_MAC || \ - GTEST_OS_SYMBIAN || GTEST_OS_SOLARIS || GTEST_OS_AIX +// Brings in definitions for functions used in the testing::internal::posix +// namespace (read, write, close, chdir, isatty, stat). We do not currently +// use them on Windows Mobile. +#if !GTEST_OS_WINDOWS +// This assumes that non-Windows OSes provide unistd.h. For OSes where this +// is not the case, we need to include headers that provide the functions +// mentioned above. +# include +# if !GTEST_OS_NACL +// TODO(vladl at google.com): Remove this condition when Native Client SDK adds +// strings.h (tracked in +// http://code.google.com/p/nativeclient/issues/detail?id=1175). +# include // Native Client doesn't provide strings.h. +# endif +#elif !GTEST_OS_WINDOWS_MOBILE +# include +# include +#endif + +// Defines this to true iff Google Test can use POSIX regular expressions. +#ifndef GTEST_HAS_POSIX_RE +# define GTEST_HAS_POSIX_RE (!GTEST_OS_WINDOWS) +#endif + +#if GTEST_HAS_POSIX_RE // On some platforms, needs someone to define size_t, and // won't compile otherwise. We can #include it here as we already // included , which is guaranteed to define size_t through // . -#include // NOLINT -#include // NOLINT -#include // NOLINT -#include // NOLINT -#include // NOLINT +# include // NOLINT -#define GTEST_USES_POSIX_RE 1 +# define GTEST_USES_POSIX_RE 1 #elif GTEST_OS_WINDOWS -#if !GTEST_OS_WINDOWS_MOBILE -#include // NOLINT -#include // NOLINT -#endif - // is not available on Windows. Use our own simple regex // implementation instead. -#define GTEST_USES_SIMPLE_RE 1 +# define GTEST_USES_SIMPLE_RE 1 #else // may not be available on this platform. Use our own // simple regex implementation instead. -#define GTEST_USES_SIMPLE_RE 1 +# define GTEST_USES_SIMPLE_RE 1 -#endif // GTEST_OS_CYGWIN || GTEST_OS_LINUX || GTEST_OS_MAC || - // GTEST_OS_SYMBIAN || GTEST_OS_SOLARIS || GTEST_OS_AIX +#endif // GTEST_HAS_POSIX_RE #ifndef GTEST_HAS_EXCEPTIONS // The user didn't tell us whether exceptions are enabled, so we need // to figure it out. -#if defined(_MSC_VER) || defined(__BORLANDC__) +# if defined(_MSC_VER) || defined(__BORLANDC__) // MSVC's and C++Builder's implementations of the STL use the _HAS_EXCEPTIONS // macro to enable exceptions, so we'll do the same. // Assumes that exceptions are enabled by default. -#ifndef _HAS_EXCEPTIONS -#define _HAS_EXCEPTIONS 1 -#endif // _HAS_EXCEPTIONS -#define GTEST_HAS_EXCEPTIONS _HAS_EXCEPTIONS -#elif defined(__GNUC__) && __EXCEPTIONS +# ifndef _HAS_EXCEPTIONS +# define _HAS_EXCEPTIONS 1 +# endif // _HAS_EXCEPTIONS +# define GTEST_HAS_EXCEPTIONS _HAS_EXCEPTIONS +# elif defined(__GNUC__) && __EXCEPTIONS // gcc defines __EXCEPTIONS to 1 iff exceptions are enabled. -#define GTEST_HAS_EXCEPTIONS 1 -#elif defined(__SUNPRO_CC) +# define GTEST_HAS_EXCEPTIONS 1 +# elif defined(__SUNPRO_CC) // Sun Pro CC supports exceptions. However, there is no compile-time way of // detecting whether they are enabled or not. Therefore, we assume that // they are enabled unless the user tells us otherwise. -#define GTEST_HAS_EXCEPTIONS 1 -#elif defined(__IBMCPP__) && __EXCEPTIONS +# define GTEST_HAS_EXCEPTIONS 1 +# elif defined(__IBMCPP__) && __EXCEPTIONS // xlC defines __EXCEPTIONS to 1 iff exceptions are enabled. -#define GTEST_HAS_EXCEPTIONS 1 -#else +# define GTEST_HAS_EXCEPTIONS 1 +# elif defined(__HP_aCC) +// Exception handling is in effect by default in HP aCC compiler. It has to +// be turned of by +noeh compiler option if desired. +# define GTEST_HAS_EXCEPTIONS 1 +# else // For other compilers, we assume exceptions are disabled to be // conservative. -#define GTEST_HAS_EXCEPTIONS 0 -#endif // defined(_MSC_VER) || defined(__BORLANDC__) +# define GTEST_HAS_EXCEPTIONS 0 +# endif // defined(_MSC_VER) || defined(__BORLANDC__) #endif // GTEST_HAS_EXCEPTIONS #if !defined(GTEST_HAS_STD_STRING) // Even though we don't use this macro any longer, we keep it in case // some clients still depend on it. -#define GTEST_HAS_STD_STRING 1 +# define GTEST_HAS_STD_STRING 1 #elif !GTEST_HAS_STD_STRING // The user told us that ::std::string isn't available. -#error "Google Test cannot be used where ::std::string isn't available." +# error "Google Test cannot be used where ::std::string isn't available." #endif // !defined(GTEST_HAS_STD_STRING) #ifndef GTEST_HAS_GLOBAL_STRING // The user didn't tell us whether ::string is available, so we need // to figure it out. -#define GTEST_HAS_GLOBAL_STRING 0 +# define GTEST_HAS_GLOBAL_STRING 0 #endif // GTEST_HAS_GLOBAL_STRING @@ -311,18 +351,19 @@ // TODO(wan at google.com): uses autoconf to detect whether ::std::wstring // is available. -// Cygwin 1.5 and below doesn't support ::std::wstring. -// Cygwin 1.7 might add wstring support; this should be updated when clear. -// Solaris' libc++ doesn't support it either. +// Cygwin 1.7 and below doesn't support ::std::wstring. +// Solaris' libc++ doesn't support it either. Android has +// no support for it at least as recent as Froyo (2.2). // Minix currently doesn't support it either. -#define GTEST_HAS_STD_WSTRING (!(GTEST_OS_CYGWIN || GTEST_OS_SOLARIS || GTEST_OS_HAIKU || defined(_MINIX))) +# define GTEST_HAS_STD_WSTRING \ + (!(GTEST_OS_LINUX_ANDROID || GTEST_OS_CYGWIN || GTEST_OS_SOLARIS || GTEST_OS_HAIKU || defined(_MINIX))) #endif // GTEST_HAS_STD_WSTRING #ifndef GTEST_HAS_GLOBAL_WSTRING // The user didn't tell us whether ::wstring is available, so we need // to figure it out. -#define GTEST_HAS_GLOBAL_WSTRING \ +# define GTEST_HAS_GLOBAL_WSTRING \ (GTEST_HAS_STD_WSTRING && GTEST_HAS_GLOBAL_STRING) #endif // GTEST_HAS_GLOBAL_WSTRING @@ -331,46 +372,46 @@ // The user didn't tell us whether RTTI is enabled, so we need to // figure it out. -#ifdef _MSC_VER +# ifdef _MSC_VER -#ifdef _CPPRTTI // MSVC defines this macro iff RTTI is enabled. -#define GTEST_HAS_RTTI 1 -#else -#define GTEST_HAS_RTTI 0 -#endif +# ifdef _CPPRTTI // MSVC defines this macro iff RTTI is enabled. +# define GTEST_HAS_RTTI 1 +# else +# define GTEST_HAS_RTTI 0 +# endif // Starting with version 4.3.2, gcc defines __GXX_RTTI iff RTTI is enabled. -#elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40302) +# elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40302) -#ifdef __GXX_RTTI -#define GTEST_HAS_RTTI 1 -#else -#define GTEST_HAS_RTTI 0 -#endif // __GXX_RTTI +# ifdef __GXX_RTTI +# define GTEST_HAS_RTTI 1 +# else +# define GTEST_HAS_RTTI 0 +# endif // __GXX_RTTI // Starting with version 9.0 IBM Visual Age defines __RTTI_ALL__ to 1 if // both the typeid and dynamic_cast features are present. -#elif defined(__IBMCPP__) && (__IBMCPP__ >= 900) +# elif defined(__IBMCPP__) && (__IBMCPP__ >= 900) -#ifdef __RTTI_ALL__ -#define GTEST_HAS_RTTI 1 -#else -#define GTEST_HAS_RTTI 0 -#endif +# ifdef __RTTI_ALL__ +# define GTEST_HAS_RTTI 1 +# else +# define GTEST_HAS_RTTI 0 +# endif -#else +# else // For all other compilers, we assume RTTI is enabled. -#define GTEST_HAS_RTTI 1 +# define GTEST_HAS_RTTI 1 -#endif // _MSC_VER +# endif // _MSC_VER #endif // GTEST_HAS_RTTI // It's this header's responsibility to #include when RTTI // is enabled. #if GTEST_HAS_RTTI -#include +# include #endif // Determines whether Google Test can use the pthreads library. @@ -380,15 +421,24 @@ // // To disable threading support in Google Test, add -DGTEST_HAS_PTHREAD=0 // to your compiler flags. -#define GTEST_HAS_PTHREAD (GTEST_OS_LINUX || GTEST_OS_MAC) +# define GTEST_HAS_PTHREAD (GTEST_OS_LINUX || GTEST_OS_MAC || GTEST_OS_HPUX) #endif // GTEST_HAS_PTHREAD +#if GTEST_HAS_PTHREAD +// gtest-port.h guarantees to #include when GTEST_HAS_PTHREAD is +// true. +# include // NOLINT + +// For timespec and nanosleep, used below. +# include // NOLINT +#endif + // Determines whether Google Test can use tr1/tuple. You can define // this macro to 0 to prevent Google Test from using tuple (any // feature depending on tuple with be disabled in this mode). #ifndef GTEST_HAS_TR1_TUPLE // The user didn't tell us not to do it, so we assume it's OK. -#define GTEST_HAS_TR1_TUPLE 1 +# define GTEST_HAS_TR1_TUPLE 1 #endif // GTEST_HAS_TR1_TUPLE // Determines whether Google Test's own tr1 tuple implementation @@ -403,13 +453,13 @@ // defining __GNUC__ and friends, but cannot compile GCC's tuple // implementation. MSVC 2008 (9.0) provides TR1 tuple in a 323 MB // Feature Pack download, which we cannot assume the user has. -#if (defined(__GNUC__) && !(defined(__CUDACC__) || defined(__clang__)) \ - && (GTEST_GCC_VER_ >= 40000)) \ +# if (defined(__GNUC__) && !(defined(__CUDACC__) || defined(__clang__)) \ + && (GTEST_GCC_VER_ >= 40000)) \ || _MSC_VER >= 1600 -#define GTEST_USE_OWN_TR1_TUPLE 0 -#else -#define GTEST_USE_OWN_TR1_TUPLE 1 -#endif +# define GTEST_USE_OWN_TR1_TUPLE 0 +# else +# define GTEST_USE_OWN_TR1_TUPLE 1 +# endif #endif // GTEST_USE_OWN_TR1_TUPLE @@ -418,47 +468,47 @@ // tr1/tuple. #if GTEST_HAS_TR1_TUPLE -#if GTEST_USE_OWN_TR1_TUPLE -#include -#elif GTEST_OS_SYMBIAN +# if GTEST_USE_OWN_TR1_TUPLE +# include "gtest/internal/gtest-tuple.h" +# elif GTEST_OS_SYMBIAN // On Symbian, BOOST_HAS_TR1_TUPLE causes Boost's TR1 tuple library to // use STLport's tuple implementation, which unfortunately doesn't // work as the copy of STLport distributed with Symbian is incomplete. // By making sure BOOST_HAS_TR1_TUPLE is undefined, we force Boost to // use its own tuple implementation. -#ifdef BOOST_HAS_TR1_TUPLE -#undef BOOST_HAS_TR1_TUPLE -#endif // BOOST_HAS_TR1_TUPLE +# ifdef BOOST_HAS_TR1_TUPLE +# undef BOOST_HAS_TR1_TUPLE +# endif // BOOST_HAS_TR1_TUPLE // This prevents , which defines // BOOST_HAS_TR1_TUPLE, from being #included by Boost's . -#define BOOST_TR1_DETAIL_CONFIG_HPP_INCLUDED -#include +# define BOOST_TR1_DETAIL_CONFIG_HPP_INCLUDED +# include -#elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40000) +# elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40000) // GCC 4.0+ implements tr1/tuple in the header. This does // not conform to the TR1 spec, which requires the header to be . -#if !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 +# if !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 // Until version 4.3.2, gcc has a bug that causes , // which is #included by , to not compile when RTTI is // disabled. _TR1_FUNCTIONAL is the header guard for // . Hence the following #define is a hack to prevent // from being included. -#define _TR1_FUNCTIONAL 1 -#include -#undef _TR1_FUNCTIONAL // Allows the user to #include +# define _TR1_FUNCTIONAL 1 +# include +# undef _TR1_FUNCTIONAL // Allows the user to #include // if he chooses to. -#else -#include // NOLINT -#endif // !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 +# else +# include // NOLINT +# endif // !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 -#else +# else // If the compiler is not GCC 4.0+, we assume the user is using a // spec-conforming TR1 implementation. -#include // NOLINT -#endif // GTEST_USE_OWN_TR1_TUPLE +# include // NOLINT +# endif // GTEST_USE_OWN_TR1_TUPLE #endif // GTEST_HAS_TR1_TUPLE @@ -469,19 +519,25 @@ #ifndef GTEST_HAS_CLONE // The user didn't tell us, so we need to figure it out. -#if GTEST_OS_LINUX && !defined(__ia64__) -#define GTEST_HAS_CLONE 1 -#else -#define GTEST_HAS_CLONE 0 -#endif // GTEST_OS_LINUX && !defined(__ia64__) +# if GTEST_OS_LINUX && !defined(__ia64__) +# define GTEST_HAS_CLONE 1 +# else +# define GTEST_HAS_CLONE 0 +# endif // GTEST_OS_LINUX && !defined(__ia64__) #endif // GTEST_HAS_CLONE // Determines whether to support stream redirection. This is used to test // output correctness and to implement death tests. -#if !GTEST_OS_WINDOWS_MOBILE && !GTEST_OS_SYMBIAN -#define GTEST_HAS_STREAM_REDIRECTION_ 1 -#endif // !GTEST_OS_WINDOWS_MOBILE && !GTEST_OS_SYMBIAN +#ifndef GTEST_HAS_STREAM_REDIRECTION +// By default, we assume that stream redirection is supported on all +// platforms except known mobile ones. +# if GTEST_OS_WINDOWS_MOBILE || GTEST_OS_SYMBIAN +# define GTEST_HAS_STREAM_REDIRECTION 0 +# else +# define GTEST_HAS_STREAM_REDIRECTION 1 +# endif // !GTEST_OS_WINDOWS_MOBILE && !GTEST_OS_SYMBIAN +#endif // GTEST_HAS_STREAM_REDIRECTION // Determines whether to support death tests. // Google Test does not support death tests for VC 7.1 and earlier as @@ -489,9 +545,9 @@ // pops up a dialog window that cannot be suppressed programmatically. #if (GTEST_OS_LINUX || GTEST_OS_MAC || GTEST_OS_CYGWIN || GTEST_OS_SOLARIS || \ (GTEST_OS_WINDOWS_DESKTOP && _MSC_VER >= 1400) || \ - GTEST_OS_WINDOWS_MINGW || GTEST_OS_AIX) -#define GTEST_HAS_DEATH_TEST 1 -#include // NOLINT + GTEST_OS_WINDOWS_MINGW || GTEST_OS_AIX || GTEST_OS_HPUX) +# define GTEST_HAS_DEATH_TEST 1 +# include // NOLINT #endif // We don't support MSVC 7.1 with exceptions disabled now. Therefore @@ -502,11 +558,11 @@ // Determines whether to support type-driven tests. // Typed tests need and variadic macros, which GCC, VC++ 8.0, -// Sun Pro CC, and IBM Visual Age support. +// Sun Pro CC, IBM Visual Age, and HP aCC support. #if defined(__GNUC__) || (_MSC_VER >= 1400) || defined(__SUNPRO_CC) || \ - defined(__IBMCPP__) -#define GTEST_HAS_TYPED_TEST 1 -#define GTEST_HAS_TYPED_TEST_P 1 + defined(__IBMCPP__) || defined(__HP_aCC) +# define GTEST_HAS_TYPED_TEST 1 +# define GTEST_HAS_TYPED_TEST_P 1 #endif // Determines whether to support Combine(). This only makes sense when @@ -514,13 +570,18 @@ // work on Sun Studio since it doesn't understand templated conversion // operators. #if GTEST_HAS_PARAM_TEST && GTEST_HAS_TR1_TUPLE && !defined(__SUNPRO_CC) -#define GTEST_HAS_COMBINE 1 +# define GTEST_HAS_COMBINE 1 #endif // Determines whether the system compiler uses UTF-16 for encoding wide strings. #define GTEST_WIDE_STRING_USES_UTF16_ \ (GTEST_OS_WINDOWS || GTEST_OS_CYGWIN || GTEST_OS_SYMBIAN || GTEST_OS_AIX) +// Determines whether test results can be streamed to a socket. +#if GTEST_OS_LINUX +# define GTEST_CAN_STREAM_RESULTS_ 1 +#endif + // Defines some utility macros. // The GNU compiler emits a warning if nested "if" statements are followed by @@ -532,9 +593,9 @@ // // The "switch (0) case 0:" idiom is used to suppress this. #ifdef __INTEL_COMPILER -#define GTEST_AMBIGUOUS_ELSE_BLOCKER_ +# define GTEST_AMBIGUOUS_ELSE_BLOCKER_ #else -#define GTEST_AMBIGUOUS_ELSE_BLOCKER_ switch (0) case 0: // NOLINT +# define GTEST_AMBIGUOUS_ELSE_BLOCKER_ switch (0) case 0: default: // NOLINT #endif // Use this annotation at the end of a struct/class definition to @@ -549,9 +610,9 @@ // Also use it after a variable or parameter declaration to tell the // compiler the variable/parameter does not have to be used. #if defined(__GNUC__) && !defined(COMPILER_ICC) -#define GTEST_ATTRIBUTE_UNUSED_ __attribute__ ((unused)) +# define GTEST_ATTRIBUTE_UNUSED_ __attribute__ ((unused)) #else -#define GTEST_ATTRIBUTE_UNUSED_ +# define GTEST_ATTRIBUTE_UNUSED_ #endif // A macro to disallow operator= @@ -571,9 +632,9 @@ // // Sprocket* AllocateSprocket() GTEST_MUST_USE_RESULT_; #if defined(__GNUC__) && (GTEST_GCC_VER_ >= 30400) && !defined(COMPILER_ICC) -#define GTEST_MUST_USE_RESULT_ __attribute__ ((warn_unused_result)) +# define GTEST_MUST_USE_RESULT_ __attribute__ ((warn_unused_result)) #else -#define GTEST_MUST_USE_RESULT_ +# define GTEST_MUST_USE_RESULT_ #endif // __GNUC__ && (GTEST_GCC_VER_ >= 30400) && !COMPILER_ICC // Determine whether the compiler supports Microsoft's Structured Exception @@ -582,28 +643,35 @@ #ifndef GTEST_HAS_SEH // The user didn't tell us, so we need to figure it out. -#if defined(_MSC_VER) || defined(__BORLANDC__) +# if defined(_MSC_VER) || defined(__BORLANDC__) // These two compilers are known to support SEH. -#define GTEST_HAS_SEH 1 -#else +# define GTEST_HAS_SEH 1 +# else // Assume no SEH. -#define GTEST_HAS_SEH 0 -#endif +# define GTEST_HAS_SEH 0 +# endif #endif // GTEST_HAS_SEH #ifdef _MSC_VER -#if GTEST_LINKED_AS_SHARED_LIBRARY -#define GTEST_API_ __declspec(dllimport) -#elif GTEST_CREATE_SHARED_LIBRARY -#define GTEST_API_ __declspec(dllexport) -#endif +# if GTEST_LINKED_AS_SHARED_LIBRARY +# define GTEST_API_ __declspec(dllimport) +# elif GTEST_CREATE_SHARED_LIBRARY +# define GTEST_API_ __declspec(dllexport) +# endif #endif // _MSC_VER #ifndef GTEST_API_ -#define GTEST_API_ +# define GTEST_API_ +#endif + +#ifdef __GNUC__ +// Ask the compiler to never inline a given function. +# define GTEST_NO_INLINE_ __attribute__((noinline)) +#else +# define GTEST_NO_INLINE_ #endif namespace testing { @@ -614,7 +682,90 @@ class String; -typedef ::std::stringstream StrStream; +// The GTEST_COMPILE_ASSERT_ macro can be used to verify that a compile time +// expression is true. For example, you could use it to verify the +// size of a static array: +// +// GTEST_COMPILE_ASSERT_(ARRAYSIZE(content_type_names) == CONTENT_NUM_TYPES, +// content_type_names_incorrect_size); +// +// or to make sure a struct is smaller than a certain size: +// +// GTEST_COMPILE_ASSERT_(sizeof(foo) < 128, foo_too_large); +// +// The second argument to the macro is the name of the variable. If +// the expression is false, most compilers will issue a warning/error +// containing the name of the variable. + +template +struct CompileAssert { +}; + +#define GTEST_COMPILE_ASSERT_(expr, msg) \ + typedef ::testing::internal::CompileAssert<(bool(expr))> \ + msg[bool(expr) ? 1 : -1] + +// Implementation details of GTEST_COMPILE_ASSERT_: +// +// - GTEST_COMPILE_ASSERT_ works by defining an array type that has -1 +// elements (and thus is invalid) when the expression is false. +// +// - The simpler definition +// +// #define GTEST_COMPILE_ASSERT_(expr, msg) typedef char msg[(expr) ? 1 : -1] +// +// does not work, as gcc supports variable-length arrays whose sizes +// are determined at run-time (this is gcc's extension and not part +// of the C++ standard). As a result, gcc fails to reject the +// following code with the simple definition: +// +// int foo; +// GTEST_COMPILE_ASSERT_(foo, msg); // not supposed to compile as foo is +// // not a compile-time constant. +// +// - By using the type CompileAssert<(bool(expr))>, we ensures that +// expr is a compile-time constant. (Template arguments must be +// determined at compile-time.) +// +// - The outter parentheses in CompileAssert<(bool(expr))> are necessary +// to work around a bug in gcc 3.4.4 and 4.0.1. If we had written +// +// CompileAssert +// +// instead, these compilers will refuse to compile +// +// GTEST_COMPILE_ASSERT_(5 > 0, some_message); +// +// (They seem to think the ">" in "5 > 0" marks the end of the +// template argument list.) +// +// - The array size is (bool(expr) ? 1 : -1), instead of simply +// +// ((expr) ? 1 : -1). +// +// This is to avoid running into a bug in MS VC 7.1, which +// causes ((0.0) ? 1 : -1) to incorrectly evaluate to 1. + +// StaticAssertTypeEqHelper is used by StaticAssertTypeEq defined in gtest.h. +// +// This template is declared, but intentionally undefined. +template +struct StaticAssertTypeEqHelper; + +template +struct StaticAssertTypeEqHelper {}; + +#if GTEST_HAS_GLOBAL_STRING +typedef ::string string; +#else +typedef ::std::string string; +#endif // GTEST_HAS_GLOBAL_STRING + +#if GTEST_HAS_GLOBAL_WSTRING +typedef ::wstring wstring; +#elif GTEST_HAS_STD_WSTRING +typedef ::std::wstring wstring; +#endif // GTEST_HAS_GLOBAL_WSTRING // A helper for suppressing warnings on constant condition. It just // returns 'condition'. @@ -670,7 +821,9 @@ RE(const ::std::string& regex) { Init(regex.c_str()); } // NOLINT #if GTEST_HAS_GLOBAL_STRING + RE(const ::string& regex) { Init(regex.c_str()); } // NOLINT + #endif // GTEST_HAS_GLOBAL_STRING RE(const char* regex) { Init(regex); } // NOLINT @@ -694,12 +847,14 @@ } #if GTEST_HAS_GLOBAL_STRING + static bool FullMatch(const ::string& str, const RE& re) { return FullMatch(str.c_str(), re); } static bool PartialMatch(const ::string& str, const RE& re) { return PartialMatch(str.c_str(), re); } + #endif // GTEST_HAS_GLOBAL_STRING static bool FullMatch(const char* str, const RE& re); @@ -714,16 +869,31 @@ // files. const char* pattern_; bool is_valid_; + #if GTEST_USES_POSIX_RE + regex_t full_regex_; // For FullMatch(). regex_t partial_regex_; // For PartialMatch(). + #else // GTEST_USES_SIMPLE_RE + const char* full_pattern_; // For FullMatch(); + #endif GTEST_DISALLOW_ASSIGN_(RE); }; +// Formats a source file path and a line number as they would appear +// in an error message from the compiler used to compile this code. +GTEST_API_ ::std::string FormatFileLocation(const char* file, int line); + +// Formats a file location for compiler-independent XML output. +// Although this function is not platform dependent, we put it next to +// FormatFileLocation in order to contrast the two functions. +GTEST_API_ ::std::string FormatCompilerIndependentFileLocation(const char* file, + int line); + // Defines logging utilities: // GTEST_LOG_(severity) - logs messages at the specified severity level. The // message itself is streamed into the macro. @@ -795,6 +965,66 @@ // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // +// Use ImplicitCast_ as a safe version of static_cast for upcasting in +// the type hierarchy (e.g. casting a Foo* to a SuperclassOfFoo* or a +// const Foo*). When you use ImplicitCast_, the compiler checks that +// the cast is safe. Such explicit ImplicitCast_s are necessary in +// surprisingly many situations where C++ demands an exact type match +// instead of an argument type convertable to a target type. +// +// The syntax for using ImplicitCast_ is the same as for static_cast: +// +// ImplicitCast_(expr) +// +// ImplicitCast_ would have been part of the C++ standard library, +// but the proposal was submitted too late. It will probably make +// its way into the language in the future. +// +// This relatively ugly name is intentional. It prevents clashes with +// similar functions users may have (e.g., implicit_cast). The internal +// namespace alone is not enough because the function can be found by ADL. +template +inline To ImplicitCast_(To x) { return x; } + +// When you upcast (that is, cast a pointer from type Foo to type +// SuperclassOfFoo), it's fine to use ImplicitCast_<>, since upcasts +// always succeed. When you downcast (that is, cast a pointer from +// type Foo to type SubclassOfFoo), static_cast<> isn't safe, because +// how do you know the pointer is really of type SubclassOfFoo? It +// could be a bare Foo, or of type DifferentSubclassOfFoo. Thus, +// when you downcast, you should use this macro. In debug mode, we +// use dynamic_cast<> to double-check the downcast is legal (we die +// if it's not). In normal mode, we do the efficient static_cast<> +// instead. Thus, it's important to test in debug mode to make sure +// the cast is legal! +// This is the only place in the code we should use dynamic_cast<>. +// In particular, you SHOULDN'T be using dynamic_cast<> in order to +// do RTTI (eg code like this: +// if (dynamic_cast(foo)) HandleASubclass1Object(foo); +// if (dynamic_cast(foo)) HandleASubclass2Object(foo); +// You should design the code some other way not to need this. +// +// This relatively ugly name is intentional. It prevents clashes with +// similar functions users may have (e.g., down_cast). The internal +// namespace alone is not enough because the function can be found by ADL. +template // use like this: DownCast_(foo); +inline To DownCast_(From* f) { // so we only accept pointers + // Ensures that To is a sub-type of From *. This test is here only + // for compile-time type checking, and has no overhead in an + // optimized build at run-time, as it will be optimized away + // completely. + if (false) { + const To to = NULL; + ::testing::internal::ImplicitCast_(to); + } + +#if GTEST_HAS_RTTI + // RTTI: debug mode only! + GTEST_CHECK_(f == NULL || dynamic_cast(f) != NULL); +#endif + return static_cast(f); +} + // Downcasts the pointer of type Base to Derived. // Derived must be a subclass of Base. The parameter MUST // point to a class of type Derived, not any subclass of it. @@ -810,7 +1040,7 @@ #endif } -#if GTEST_HAS_STREAM_REDIRECTION_ +#if GTEST_HAS_STREAM_REDIRECTION // Defines the stderr capturer: // CaptureStdout - starts capturing stdout. @@ -823,7 +1053,7 @@ GTEST_API_ void CaptureStderr(); GTEST_API_ String GetCapturedStderr(); -#endif // GTEST_HAS_STREAM_REDIRECTION_ +#endif // GTEST_HAS_STREAM_REDIRECTION #if GTEST_HAS_DEATH_TEST @@ -957,10 +1187,6 @@ GTEST_DISALLOW_COPY_AND_ASSIGN_(ThreadWithParam); }; -// gtest-port.h guarantees to #include when GTEST_HAS_PTHREAD is -// true. -#include - // MutexBase and Mutex implement mutex on pthreads-based platforms. They // are used in conjunction with class MutexLock: // @@ -1015,11 +1241,11 @@ }; // Forward-declares a static mutex. -#define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ +# define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ extern ::testing::internal::MutexBase mutex // Defines and statically (i.e. at link time) initializes a static mutex. -#define GTEST_DEFINE_STATIC_MUTEX_(mutex) \ +# define GTEST_DEFINE_STATIC_MUTEX_(mutex) \ ::testing::internal::MutexBase mutex = { PTHREAD_MUTEX_INITIALIZER, 0 } // The Mutex class can only be used for mutexes created at runtime. It @@ -1166,7 +1392,7 @@ GTEST_DISALLOW_COPY_AND_ASSIGN_(ThreadLocal); }; -#define GTEST_IS_THREADSAFE 1 +# define GTEST_IS_THREADSAFE 1 #else // GTEST_HAS_PTHREAD @@ -1181,10 +1407,10 @@ void AssertHeld() const {} }; -#define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ +# define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ extern ::testing::internal::Mutex mutex -#define GTEST_DEFINE_STATIC_MUTEX_(mutex) ::testing::internal::Mutex mutex +# define GTEST_DEFINE_STATIC_MUTEX_(mutex) ::testing::internal::Mutex mutex class GTestMutexLock { public: @@ -1208,7 +1434,7 @@ // The above synchronization primitives have dummy implementations. // Therefore Google Test is not thread-safe. -#define GTEST_IS_THREADSAFE 0 +# define GTEST_IS_THREADSAFE 0 #endif // GTEST_HAS_PTHREAD @@ -1225,9 +1451,9 @@ #if defined(__SYMBIAN32__) || defined(__IBMCPP__) || defined(__SUNPRO_CC) // We lose support for NULL detection where the compiler doesn't like // passing non-POD classes through ellipsis (...). -#define GTEST_ELLIPSIS_NEEDS_POD_ 1 +# define GTEST_ELLIPSIS_NEEDS_POD_ 1 #else -#define GTEST_CAN_COMPARE_NULL 1 +# define GTEST_CAN_COMPARE_NULL 1 #endif // The Nokia Symbian and IBM XL C/C++ compilers cannot decide between @@ -1235,7 +1461,7 @@ // _can_ decide between class template specializations for T and T*, // so a tr1::type_traits-like is_pointer works. #if defined(__SYMBIAN32__) || defined(__IBMCPP__) -#define GTEST_NEEDS_IS_POINTER_ 1 +# define GTEST_NEEDS_IS_POINTER_ 1 #endif template @@ -1254,17 +1480,68 @@ template struct is_pointer : public true_type {}; +template +struct IteratorTraits { + typedef typename Iterator::value_type value_type; +}; + +template +struct IteratorTraits { + typedef T value_type; +}; + +template +struct IteratorTraits { + typedef T value_type; +}; + #if GTEST_OS_WINDOWS -#define GTEST_PATH_SEP_ "\\" -#define GTEST_HAS_ALT_PATH_SEP_ 1 +# define GTEST_PATH_SEP_ "\\" +# define GTEST_HAS_ALT_PATH_SEP_ 1 // The biggest signed integer type the compiler supports. typedef __int64 BiggestInt; #else -#define GTEST_PATH_SEP_ "/" -#define GTEST_HAS_ALT_PATH_SEP_ 0 +# define GTEST_PATH_SEP_ "/" +# define GTEST_HAS_ALT_PATH_SEP_ 0 typedef long long BiggestInt; // NOLINT #endif // GTEST_OS_WINDOWS +// Utilities for char. + +// isspace(int ch) and friends accept an unsigned char or EOF. char +// may be signed, depending on the compiler (or compiler flags). +// Therefore we need to cast a char to unsigned char before calling +// isspace(), etc. + +inline bool IsAlpha(char ch) { + return isalpha(static_cast(ch)) != 0; +} +inline bool IsAlNum(char ch) { + return isalnum(static_cast(ch)) != 0; +} +inline bool IsDigit(char ch) { + return isdigit(static_cast(ch)) != 0; +} +inline bool IsLower(char ch) { + return islower(static_cast(ch)) != 0; +} +inline bool IsSpace(char ch) { + return isspace(static_cast(ch)) != 0; +} +inline bool IsUpper(char ch) { + return isupper(static_cast(ch)) != 0; +} +inline bool IsXDigit(char ch) { + return isxdigit(static_cast(ch)) != 0; +} + +inline char ToLower(char ch) { + return static_cast(tolower(static_cast(ch))); +} +inline char ToUpper(char ch) { + return static_cast(toupper(static_cast(ch))); +} + // The testing::internal::posix namespace holds wrappers for common // POSIX functions. These wrappers hide the differences between // Windows/MSVC and POSIX systems. Since some compilers define these @@ -1279,36 +1556,36 @@ typedef struct _stat StatStruct; -#ifdef __BORLANDC__ +# ifdef __BORLANDC__ inline int IsATTY(int fd) { return isatty(fd); } inline int StrCaseCmp(const char* s1, const char* s2) { return stricmp(s1, s2); } inline char* StrDup(const char* src) { return strdup(src); } -#else // !__BORLANDC__ -#if GTEST_OS_WINDOWS_MOBILE +# else // !__BORLANDC__ +# if GTEST_OS_WINDOWS_MOBILE inline int IsATTY(int /* fd */) { return 0; } -#else +# else inline int IsATTY(int fd) { return _isatty(fd); } -#endif // GTEST_OS_WINDOWS_MOBILE +# endif // GTEST_OS_WINDOWS_MOBILE inline int StrCaseCmp(const char* s1, const char* s2) { return _stricmp(s1, s2); } inline char* StrDup(const char* src) { return _strdup(src); } -#endif // __BORLANDC__ +# endif // __BORLANDC__ -#if GTEST_OS_WINDOWS_MOBILE +# if GTEST_OS_WINDOWS_MOBILE inline int FileNo(FILE* file) { return reinterpret_cast(_fileno(file)); } // Stat(), RmDir(), and IsDir() are not needed on Windows CE at this // time and thus not defined there. -#else +# else inline int FileNo(FILE* file) { return _fileno(file); } inline int Stat(const char* path, StatStruct* buf) { return _stat(path, buf); } inline int RmDir(const char* dir) { return _rmdir(dir); } inline bool IsDir(const StatStruct& st) { return (_S_IFDIR & st.st_mode) != 0; } -#endif // GTEST_OS_WINDOWS_MOBILE +# endif // GTEST_OS_WINDOWS_MOBILE #else @@ -1330,8 +1607,8 @@ #ifdef _MSC_VER // Temporarily disable warning 4996 (deprecated function). -#pragma warning(push) -#pragma warning(disable:4996) +# pragma warning(push) +# pragma warning(disable:4996) #endif inline const char* StrNCpy(char* dest, const char* src, size_t n) { @@ -1380,7 +1657,7 @@ } #ifdef _MSC_VER -#pragma warning(pop) // Restores the warning state. +# pragma warning(pop) // Restores the warning state. #endif #if GTEST_OS_WINDOWS_MOBILE @@ -1446,6 +1723,7 @@ template <> class TypeWithSize<8> { public: + #if GTEST_OS_WINDOWS typedef __int64 Int; typedef unsigned __int64 UInt; Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-string.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-string.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-string.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-string.h Wed Jul 27 04:25:14 2011 @@ -43,11 +43,11 @@ #ifdef __BORLANDC__ // string.h is not guaranteed to provide strcpy on C++ Builder. -#include +# include #endif #include -#include +#include "gtest/internal/gtest-port.h" #include @@ -296,7 +296,7 @@ private: // Constructs a non-NULL String from the given content. This - // function can only be called when data_ has not been allocated. + // function can only be called when c_str_ has not been allocated. // ConstructNonNull(NULL, 0) results in an empty string (""). // ConstructNonNull(NULL, non_zero) is undefined behavior. void ConstructNonNull(const char* buffer, size_t a_length) { @@ -329,9 +329,9 @@ return os; } -// Gets the content of the StrStream's buffer as a String. Each '\0' +// Gets the content of the stringstream's buffer as a String. Each '\0' // character in the buffer is replaced with "\\0". -GTEST_API_ String StrStreamToString(StrStream* stream); +GTEST_API_ String StringStreamToString(::std::stringstream* stream); // Converts a streamable value to a String. A NULL pointer is // converted to "(null)". When the input value is a ::string, Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h Wed Jul 27 04:25:14 2011 @@ -44,9 +44,9 @@ // private as public. // Sun Studio versions < 12 also have the above bug. #if defined(__SYMBIAN32__) || (defined(__SUNPRO_CC) && __SUNPRO_CC < 0x590) -#define GTEST_DECLARE_TUPLE_AS_FRIEND_ public: +# define GTEST_DECLARE_TUPLE_AS_FRIEND_ public: #else -#define GTEST_DECLARE_TUPLE_AS_FRIEND_ \ +# define GTEST_DECLARE_TUPLE_AS_FRIEND_ \ template friend class tuple; \ private: #endif Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h?rev=136212&r1=136211&r2=136212&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h (original) +++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h Wed Jul 27 04:25:14 2011 @@ -44,55 +44,64 @@ #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ -#include -#include - -#if GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P +#include "gtest/internal/gtest-port.h" +#include "gtest/internal/gtest-string.h" // #ifdef __GNUC__ is too general here. It is possible to use gcc without using // libstdc++ (which is where cxxabi.h comes from). -#ifdef __GLIBCXX__ -#include -#endif // __GLIBCXX__ +# ifdef __GLIBCXX__ +# include +# elif defined(__HP_aCC) +# include +# endif // __GLIBCXX__ namespace testing { namespace internal { -// AssertyTypeEq::type is defined iff T1 and T2 are the same -// type. This can be used as a compile-time assertion to ensure that -// two types are equal. - -template -struct AssertTypeEq; - -template -struct AssertTypeEq { - typedef bool type; -}; - // GetTypeName() returns a human-readable name of type T. +// NB: This function is also used in Google Mock, so don't move it inside of +// the typed-test-only section below. template String GetTypeName() { -#if GTEST_HAS_RTTI +# if GTEST_HAS_RTTI const char* const name = typeid(T).name(); -#ifdef __GLIBCXX__ +# if defined(__GLIBCXX__) || defined(__HP_aCC) int status = 0; // gcc's implementation of typeid(T).name() mangles the type name, // so we have to demangle it. - char* const readable_name = abi::__cxa_demangle(name, 0, 0, &status); +# ifdef __GLIBCXX__ + using abi::__cxa_demangle; +# endif // __GLIBCXX__ + char* const readable_name = __cxa_demangle(name, 0, 0, &status); const String name_str(status == 0 ? readable_name : name); free(readable_name); return name_str; -#else +# else return name; -#endif // __GLIBCXX__ +# endif // __GLIBCXX__ || __HP_aCC + +# else -#else return ""; -#endif // GTEST_HAS_RTTI + +# endif // GTEST_HAS_RTTI } +#if GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P + +// AssertyTypeEq::type is defined iff T1 and T2 are the same +// type. This can be used as a compile-time assertion to ensure that +// two types are equal. + +template +struct AssertTypeEq; + +template +struct AssertTypeEq { + typedef bool type; +}; + // A unique type used as the default value for the arguments of class // template Types. This allows us to simulate variadic templates // (e.g. Types, Type, and etc), which C++ doesn't @@ -1611,7 +1620,7 @@ namespace internal { -#define GTEST_TEMPLATE_ template class +# define GTEST_TEMPLATE_ template class // The template "selector" struct TemplateSel is used to // represent Tmpl, which must be a class template with one type @@ -1629,7 +1638,7 @@ }; }; -#define GTEST_BIND_(TmplSel, T) \ +# define GTEST_BIND_(TmplSel, T) \ TmplSel::template Bind::type // A unique struct template used as the default value for the @@ -3313,9 +3322,9 @@ T41, T42, T43, T44, T45, T46, T47, T48, T49, T50>::type type; }; +#endif // GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P + } // namespace internal } // namespace testing -#endif // GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P - #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ From jay.foad at gmail.com Wed Jul 27 04:26:13 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 27 Jul 2011 09:26:13 -0000 Subject: [llvm-commits] [llvm] r136213 - /llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp Message-ID: <20110727092613.75ADA2A6C12C@llvm.org> Author: foad Date: Wed Jul 27 04:26:13 2011 New Revision: 136213 URL: http://llvm.org/viewvc/llvm-project?rev=136213&view=rev Log: Remove some code that is no longer needed now that googletest knows how to print STL containers. Modified: llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp Modified: llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp?rev=136213&r1=136212&r2=136213&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp (original) +++ llvm/trunk/unittests/ADT/DAGDeltaAlgorithmTest.cpp Wed Jul 27 04:26:13 2011 @@ -13,23 +13,6 @@ #include using namespace llvm; -namespace std { - -static std::ostream &operator<<(std::ostream &OS, - const std::set &S) { - OS << "{"; - for (std::set::const_iterator it = S.begin(), - ie = S.end(); it != ie; ++it) { - if (it != S.begin()) - OS << ","; - OS << *it; - } - OS << "}"; - return OS; -} - -} - namespace { typedef DAGDeltaAlgorithm::edge_ty edge_ty; From jay.foad at gmail.com Wed Jul 27 04:46:40 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 27 Jul 2011 10:46:40 +0100 Subject: [llvm-commits] [PATCH][RFC] upgrade to googletest 1.6.0 (was Re: [LLVMdev] Build of latest llvm gives warning and error) In-Reply-To: <4E2EE400.6000505@free.fr> References: <4E2EE400.6000505@free.fr> Message-ID: >>> yes, they are annoying aren't they. ?They all come from google's unittest >>> library. ?I think it is best to fix them upstream at google. >> >> We're using googletest 1.5.0. These warnings seem to be fixed in >> 1.6.0, so here's a patch to upgrade us. Disclaimer: I've only tested >> this by doing "make check-all" on Linux/x86_64. >> >> Incidentally, the upgrade would have been much easier if we weren't >> carrying local changes to support Haiku OS and Minix. Can these be >> pushed upstream (or thrown away if no-one is using them)? > > thanks for doing this. ?I vote that we throw Haiku and Minix support away. > ?If > the Haiku and Minix people want googletest to support these platforms I > think > we should insist that support should go upstream first (and we would then > pull > the fixes from upstream). I've committed the upgrade to 1.6.0. I've kept Haiku and Minix support for now (since I'd already done the merge work), but emailed the relevant parties to try to get them to push the patches upstream. Thanks, Jay. From baldrick at free.fr Wed Jul 27 05:17:09 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 27 Jul 2011 10:17:09 -0000 Subject: [llvm-commits] [dragonegg] r136214 - /dragonegg/trunk/TODO Message-ID: <20110727101709.4E7262A6C12C@llvm.org> Author: baldrick Date: Wed Jul 27 05:17:09 2011 New Revision: 136214 URL: http://llvm.org/viewvc/llvm-project?rev=136214&view=rev Log: Random TODO items. Modified: dragonegg/trunk/TODO Modified: dragonegg/trunk/TODO URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/TODO?rev=136214&r1=136213&r2=136214&view=diff ============================================================================== --- dragonegg/trunk/TODO (original) +++ dragonegg/trunk/TODO Wed Jul 27 05:17:09 2011 @@ -36,6 +36,27 @@ gcc). Instead, either try to get ABI info from the gcc hooks (which may mean translating RTL) or reuse the clang code. +Testing +------- + +Add nightly testers that build using dragonegg. + +Move the old FrontendXYZ tests from LLVM to dragonegg. + +Add a "compilator" lit test mode that compiles everything it is +pointed at using gcc and dragonegg, and generates "fail" if gcc +compiles something but dragonegg doesn't (and vice versa). Point +the compilator at the gcc and clang testsuites. Have some buildbots +that do this. + +Make the dragonegg testsuite public. Have some buildbots run it. + +Have the dragonegg self-host script also check that "make check" +is working fine after LLVM is built. + +Have the dragonegg buildbots use a proper buildbot script rather than +just handing everything off to the dragonegg self-host script. + Code quality ------------ From fvbommel at gmail.com Wed Jul 27 05:19:32 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Wed, 27 Jul 2011 10:19:32 -0000 Subject: [llvm-commits] [llvm] r136215 - /llvm/trunk/utils/unittest/CMakeLists.txt Message-ID: <20110727101932.5D0C42A6C12C@llvm.org> Author: fvbommel Date: Wed Jul 27 05:19:32 2011 New Revision: 136215 URL: http://llvm.org/viewvc/llvm-project?rev=136215&view=rev Log: Update CMake build for new gtest file. Modified: llvm/trunk/utils/unittest/CMakeLists.txt Modified: llvm/trunk/utils/unittest/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/CMakeLists.txt?rev=136215&r1=136214&r2=136215&view=diff ============================================================================== --- llvm/trunk/utils/unittest/CMakeLists.txt (original) +++ llvm/trunk/utils/unittest/CMakeLists.txt Wed Jul 27 05:19:32 2011 @@ -32,6 +32,7 @@ googletest/gtest-death-test.cc googletest/gtest-filepath.cc googletest/gtest-port.cc + googletest/gtest-printers.cc googletest/gtest-test-part.cc googletest/gtest-typed-test.cc ) From nadav.rotem at intel.com Wed Jul 27 07:59:34 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 27 Jul 2011 15:59:34 +0300 Subject: [llvm-commits] Updated vector-select patch Message-ID: <6594DDFF12B03D4E89690887C24869940296D91406@hasmsx504.ger.corp.intel.com> Hi, I have updated the vector-select patch. In this patch I disable a few tests that expect to see vector-compare. This is due to the enabling of vector-compare/select when building the dag node. It will be easy to match the vector compares once we enable the 'promote-elements' flag. Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: vector_select_list.diff Type: application/octet-stream Size: 22779 bytes Desc: vector_select_list.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/386bd828/attachment.obj From hwennborg at google.com Wed Jul 27 09:29:36 2011 From: hwennborg at google.com (Hans Wennborg) Date: Wed, 27 Jul 2011 15:29:36 +0100 Subject: [llvm-commits] [Patch] Missed instsimplify transformation In-Reply-To: <4E2FBC30.8080008@free.fr> References: <4E2FBC30.8080008@free.fr> Message-ID: On Wed, Jul 27, 2011 at 8:20 AM, Duncan Sands wrote: > Hi Hans, > >> The attached patch adds a simplification for >> >> ((A& ?1) == 0) | (A == 0) to >> (A& ?1) == 0 >> >> Is this ok to add to instsimplify? > > this kind of thing and many variations indeed turn up all the time. ?It is > a special case of: X | Y simplifies to X if Y implies X (in your case A == 0 > implies A & 1 == 0). ?I would prefer to add some general machinery for handling > this kind of thing, rather than sticking in a few cases, because there are so > many different forms of this that occur. ?What I had in mind was introducing a > Facts class that can store a certain number of facts like "A == 0", and would > be passed internally to instsimplify routines. ?When trying to simplify "X | Y" > you would push the fact Y into the Facts object, then try to simplify X. ?When > simplifying "(A & 1) == 0", you would recursively try to simplify "A & 1"; when > simplifying "A & 1" the fact "A == 0" would apply, allowing you to replace A > with 0, giving "0 & 1" which would simplify to 0, resulting in "(A & 1) == 0" > simplifying to "true". ?This would show that Y => X in your case, so you would > then pop the fact from the Facts object and return X as the simplification for > "X | Y". > > Unfortunately I don't have time to work on this right now - would you like to? I can try :) Thanks, Hans From clattner at apple.com Wed Jul 27 10:09:50 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 27 Jul 2011 08:09:50 -0700 Subject: [llvm-commits] [llvm] r136124 - in /llvm/trunk/include: llvm-c/Core.h llvm/Instruction.def In-Reply-To: References: <20110726202406.CA0822A6C12C@llvm.org> <2EB8E3C9-8D97-46FB-AFEA-FA8AA033A21A@apple.com> Message-ID: <3759AB4B-B2A0-4C9E-83B1-9B9C49FDDCA4@apple.com> On Jul 27, 2011, at 12:31 AM, Eli Friedman wrote: > On Tue, Jul 26, 2011 at 10:50 PM, Chris Lattner wrote: >> >> On Jul 26, 2011, at 1:24 PM, Eli Friedman wrote: >> >>> Author: efriedma >>> Date: Tue Jul 26 15:24:06 2011 >>> New Revision: 136124 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=136124&view=rev >>> Log: >>> Fix a couple minor mistakes pointed out by Bill in adding 'fence' instruction. >> >> Hi Eli, >> >> The enums in Core.h are considered to be stable API that can't change. Can you add the enum to the end of the list? > > Oh, oops; I assume then that they aren't required to be the same as > the ones in Instruction.def? Right, exactly. Instruction.def isn't guaranteed to be stable. -Chris From fvbommel at gmail.com Wed Jul 27 10:20:06 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Wed, 27 Jul 2011 15:20:06 -0000 Subject: [llvm-commits] [llvm] r136218 - /llvm/trunk/lib/Support/ConstantRange.cpp Message-ID: <20110727152006.70DF32A6C12C@llvm.org> Author: fvbommel Date: Wed Jul 27 10:20:06 2011 New Revision: 136218 URL: http://llvm.org/viewvc/llvm-project?rev=136218&view=rev Log: Trim includes. Modified: llvm/trunk/lib/Support/ConstantRange.cpp Modified: llvm/trunk/lib/Support/ConstantRange.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ConstantRange.cpp?rev=136218&r1=136217&r2=136218&view=diff ============================================================================== --- llvm/trunk/lib/Support/ConstantRange.cpp (original) +++ llvm/trunk/lib/Support/ConstantRange.cpp Wed Jul 27 10:20:06 2011 @@ -21,11 +21,10 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Constants.h" +#include "llvm/InstrTypes.h" #include "llvm/Support/ConstantRange.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Instructions.h" using namespace llvm; /// Initialize a full (the default) or empty set for the specified type. @@ -57,55 +56,55 @@ uint32_t W = CR.getBitWidth(); switch (Pred) { default: assert(!"Invalid ICmp predicate to makeICmpRegion()"); - case ICmpInst::ICMP_EQ: + case CmpInst::ICMP_EQ: return CR; - case ICmpInst::ICMP_NE: + case CmpInst::ICMP_NE: if (CR.isSingleElement()) return ConstantRange(CR.getUpper(), CR.getLower()); return ConstantRange(W); - case ICmpInst::ICMP_ULT: { + case CmpInst::ICMP_ULT: { APInt UMax(CR.getUnsignedMax()); if (UMax.isMinValue()) return ConstantRange(W, /* empty */ false); return ConstantRange(APInt::getMinValue(W), UMax); } - case ICmpInst::ICMP_SLT: { + case CmpInst::ICMP_SLT: { APInt SMax(CR.getSignedMax()); if (SMax.isMinSignedValue()) return ConstantRange(W, /* empty */ false); return ConstantRange(APInt::getSignedMinValue(W), SMax); } - case ICmpInst::ICMP_ULE: { + case CmpInst::ICMP_ULE: { APInt UMax(CR.getUnsignedMax()); if (UMax.isMaxValue()) return ConstantRange(W); return ConstantRange(APInt::getMinValue(W), UMax + 1); } - case ICmpInst::ICMP_SLE: { + case CmpInst::ICMP_SLE: { APInt SMax(CR.getSignedMax()); if (SMax.isMaxSignedValue()) return ConstantRange(W); return ConstantRange(APInt::getSignedMinValue(W), SMax + 1); } - case ICmpInst::ICMP_UGT: { + case CmpInst::ICMP_UGT: { APInt UMin(CR.getUnsignedMin()); if (UMin.isMaxValue()) return ConstantRange(W, /* empty */ false); return ConstantRange(UMin + 1, APInt::getNullValue(W)); } - case ICmpInst::ICMP_SGT: { + case CmpInst::ICMP_SGT: { APInt SMin(CR.getSignedMin()); if (SMin.isMaxSignedValue()) return ConstantRange(W, /* empty */ false); return ConstantRange(SMin + 1, APInt::getSignedMinValue(W)); } - case ICmpInst::ICMP_UGE: { + case CmpInst::ICMP_UGE: { APInt UMin(CR.getUnsignedMin()); if (UMin.isMinValue()) return ConstantRange(W); return ConstantRange(UMin, APInt::getNullValue(W)); } - case ICmpInst::ICMP_SGE: { + case CmpInst::ICMP_SGE: { APInt SMin(CR.getSignedMin()); if (SMin.isMinSignedValue()) return ConstantRange(W); From jstaszak at apple.com Wed Jul 27 10:42:09 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 15:42:09 -0000 Subject: [llvm-commits] [llvm] r136219 - /llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Message-ID: <20110727154209.F32DF2A6C12C@llvm.org> Author: kuba Date: Wed Jul 27 10:42:09 2011 New Revision: 136219 URL: http://llvm.org/viewvc/llvm-project?rev=136219&view=rev Log: Edge to itself is backedge as well. Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=136219&r1=136218&r2=136219&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Wed Jul 27 10:42:09 2011 @@ -160,7 +160,7 @@ unsigned a = RPO[Src]; unsigned b = RPO[Dst]; - return a > b; + return a >= b; } /// getSingleBlockPred - return single BB block predecessor or NULL if From jstaszak at apple.com Wed Jul 27 10:51:51 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 15:51:51 -0000 Subject: [llvm-commits] [llvm] r136221 - in /llvm/trunk: include/llvm/Support/BlockFrequency.h lib/Support/BlockFrequency.cpp Message-ID: <20110727155151.DF1762A6C12C@llvm.org> Author: kuba Date: Wed Jul 27 10:51:51 2011 New Revision: 136221 URL: http://llvm.org/viewvc/llvm-project?rev=136221&view=rev Log: Move static methods to the anonymous namespace. Modified: llvm/trunk/include/llvm/Support/BlockFrequency.h llvm/trunk/lib/Support/BlockFrequency.cpp Modified: llvm/trunk/include/llvm/Support/BlockFrequency.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BlockFrequency.h?rev=136221&r1=136220&r2=136221&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/BlockFrequency.h (original) +++ llvm/trunk/include/llvm/Support/BlockFrequency.h Wed Jul 27 10:51:51 2011 @@ -24,9 +24,6 @@ uint64_t Frequency; - static void mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]); - static uint64_t div96bit(uint64_t W[2], uint32_t D); - public: BlockFrequency(uint64_t Freq = 0) : Frequency(Freq) { } Modified: llvm/trunk/lib/Support/BlockFrequency.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=136221&r1=136220&r2=136221&view=diff ============================================================================== --- llvm/trunk/lib/Support/BlockFrequency.cpp (original) +++ llvm/trunk/lib/Support/BlockFrequency.cpp Wed Jul 27 10:51:51 2011 @@ -18,8 +18,10 @@ using namespace llvm; +namespace { + /// mult96bit - Multiply FREQ by N and store result in W array. -void BlockFrequency::mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]) { +void mult96bit(uint64_t freq, uint32_t N, uint64_t W[2]) { uint64_t u0 = freq & UINT32_MAX; uint64_t u1 = freq >> 32; @@ -41,7 +43,7 @@ /// div96bit - Divide 96-bit value stored in W array by D. Return 64-bit frequency. -uint64_t BlockFrequency::div96bit(uint64_t W[2], uint32_t D) { +uint64_t div96bit(uint64_t W[2], uint32_t D) { uint64_t y = W[0]; uint64_t x = W[1]; @@ -58,6 +60,9 @@ return y; } +} + + BlockFrequency &BlockFrequency::operator*=(const BranchProbability &Prob) { uint32_t n = Prob.getNumerator(); uint32_t d = Prob.getDenominator(); From jstaszak at apple.com Wed Jul 27 11:00:41 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 16:00:41 -0000 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp Message-ID: <20110727160041.1C6DE2A6C12C@llvm.org> Author: kuba Date: Wed Jul 27 11:00:40 2011 New Revision: 136222 URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev Log: Optimize 96-bit division a little bit. Modified: llvm/trunk/lib/Support/BlockFrequency.cpp Modified: llvm/trunk/lib/Support/BlockFrequency.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=136222&r1=136221&r2=136222&view=diff ============================================================================== --- llvm/trunk/lib/Support/BlockFrequency.cpp (original) +++ llvm/trunk/lib/Support/BlockFrequency.cpp Wed Jul 27 11:00:40 2011 @@ -46,8 +46,9 @@ uint64_t div96bit(uint64_t W[2], uint32_t D) { uint64_t y = W[0]; uint64_t x = W[1]; + int i; - for (int i = 1; i <= 64; ++i) { + for (i = 1; i <= 64 && x; ++i) { uint32_t t = (int)x >> 31; x = (x << 1) | (y >> 63); y = y << 1; @@ -57,7 +58,7 @@ } } - return y; + return y << (64 - i + 1); } } From stoklund at 2pi.dk Wed Jul 27 11:27:33 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 27 Jul 2011 09:27:33 -0700 Subject: [llvm-commits] [llvm] r136221 - in /llvm/trunk: include/llvm/Support/BlockFrequency.h lib/Support/BlockFrequency.cpp In-Reply-To: <20110727155151.DF1762A6C12C@llvm.org> References: <20110727155151.DF1762A6C12C@llvm.org> Message-ID: On Jul 27, 2011, at 8:51 AM, Jakub Staszak wrote: > Author: kuba > Date: Wed Jul 27 10:51:51 2011 > New Revision: 136221 > > URL: http://llvm.org/viewvc/llvm-project?rev=136221&view=rev > Log: > Move static methods to the anonymous namespace. > > Modified: > llvm/trunk/include/llvm/Support/BlockFrequency.h > llvm/trunk/lib/Support/BlockFrequency.cpp Thanks! You should add some unit tests to unittests/Support/BlockFrequency.cpp to make sure that this stuff is actually working. /jakob From grosbach at apple.com Wed Jul 27 11:47:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 16:47:19 -0000 Subject: [llvm-commits] [llvm] r136225 - in /llvm/trunk/lib/Target/ARM: ARMFastISel.cpp ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb2.td Thumb2SizeReduction.cpp Message-ID: <20110727164719.A7A872A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 11:47:19 2011 New Revision: 136225 URL: http://llvm.org/viewvc/llvm-project?rev=136225&view=rev Log: ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=136225&r1=136224&r2=136225&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Jul 27 11:47:19 2011 @@ -2003,15 +2003,15 @@ default: return false; case MVT::i16: if (isZext) - Opc = isThumb ? ARM::t2UXTHr : ARM::UXTHr; + Opc = isThumb ? ARM::t2UXTH : ARM::UXTH; else - Opc = isThumb ? ARM::t2SXTHr : ARM::SXTHr; + Opc = isThumb ? ARM::t2SXTH : ARM::SXTH; break; case MVT::i8: if (isZext) - Opc = isThumb ? ARM::t2UXTBr : ARM::UXTBr; + Opc = isThumb ? ARM::t2UXTB : ARM::UXTB; else - Opc = isThumb ? ARM::t2SXTBr : ARM::SXTBr; + Opc = isThumb ? ARM::t2SXTB : ARM::SXTB; break; case MVT::i1: if (isZext) { @@ -2033,6 +2033,8 @@ .addReg(SrcReg); if (isBoolZext) MIB.addImm(1); + else + MIB.addImm(0); AddOptionalDefs(MIB); UpdateValueMap(I, DestReg); return true; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=136225&r1=136224&r2=136225&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 27 11:47:19 2011 @@ -5125,12 +5125,12 @@ case 1: ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; - extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr; + extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; break; case 2: ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; - extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr; + extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; break; case 4: ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; @@ -5175,7 +5175,9 @@ // Sign extend the value, if necessary. if (signExtend && extendOpc) { oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); - AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest)); + AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) + .addReg(dest) + .addImm(0)); } // Build compare and cmov instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136225&r1=136224&r2=136225&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 11:47:19 2011 @@ -986,48 +986,27 @@ /// AI_ext_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. /// FIXME: Remove the 'r' variant. Its rot_imm is zero. -multiclass AI_ext_rrot opcod, string opc, PatFrag opnode> { - def r : AExtI, - Requires<[IsARM, HasV6]> { - bits<4> Rd; - bits<4> Rm; - let Inst{19-16} = 0b1111; - let Inst{15-12} = Rd; - let Inst{11-10} = 0b00; - let Inst{3-0} = Rm; - } - def r_rot : AExtI, - Requires<[IsARM, HasV6]> { - bits<4> Rd; - bits<4> Rm; - bits<2> rot; - let Inst{19-16} = 0b1111; - let Inst{15-12} = Rd; - let Inst{11-10} = rot; - let Inst{3-0} = Rm; - } +class AI_ext_rrot opcod, string opc, PatFrag opnode> + : AExtI, + Requires<[IsARM, HasV6]> { + bits<4> Rd; + bits<4> Rm; + bits<2> rot; + let Inst{19-16} = 0b1111; + let Inst{15-12} = Rd; + let Inst{11-10} = rot; + let Inst{3-0} = Rm; } -multiclass AI_ext_rrot_np opcod, string opc> { - def r : AExtI, - Requires<[IsARM, HasV6]> { - let Inst{19-16} = 0b1111; - let Inst{11-10} = 0b00; - } - def r_rot : AExtI, - Requires<[IsARM, HasV6]> { - bits<2> rot; - let Inst{19-16} = 0b1111; - let Inst{11-10} = rot; - } +class AI_ext_rrot_np opcod, string opc> + : AExtI, + Requires<[IsARM, HasV6]> { + bits<2> rot; + let Inst{19-16} = 0b1111; + let Inst{11-10} = rot; } /// AI_exta_rrot - A binary operation with two forms: one whose operand is a @@ -2393,9 +2372,9 @@ // Sign extenders -defm SXTB : AI_ext_rrot<0b01101010, +def SXTB : AI_ext_rrot<0b01101010, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; -defm SXTH : AI_ext_rrot<0b01101011, +def SXTH : AI_ext_rrot<0b01101011, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; defm SXTAB : AI_exta_rrot<0b01101010, @@ -2403,20 +2382,18 @@ defm SXTAH : AI_exta_rrot<0b01101011, "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; -// For disassembly only -defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; +def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; -// For disassembly only defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; // Zero extenders let AddedComplexity = 16 in { -defm UXTB : AI_ext_rrot<0b01101110, +def UXTB : AI_ext_rrot<0b01101110, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; -defm UXTH : AI_ext_rrot<0b01101111, +def UXTH : AI_ext_rrot<0b01101111, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; -defm UXTB16 : AI_ext_rrot<0b01101100, +def UXTB16 : AI_ext_rrot<0b01101100, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; // FIXME: This pattern incorrectly assumes the shl operator is a rotate. @@ -2426,7 +2403,7 @@ //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), // (UXTB16r_rot GPR:$Src, 3)>; def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), - (UXTB16r_rot GPR:$Src, 1)>; + (UXTB16 GPR:$Src, 1)>; defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; @@ -4287,6 +4264,14 @@ def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, Requires<[IsARM, HasV6]>; +// SXT/UXT with no rotate +def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; +def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; +let AddedComplexity = 10 in +def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; + +def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; +def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; //===----------------------------------------------------------------------===// // Thumb Support Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136225&r1=136224&r2=136225&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 27 11:47:19 2011 @@ -977,31 +977,19 @@ /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -multiclass T2I_ext_rrot opcod, string opc, PatFrag opnode> { - def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, - opc, ".w\t$Rd, $Rm", - [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = 0b00; // rotate - } - def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, - opc, ".w\t$Rd, $Rm$rot", - [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; +class T2I_ext_rrot opcod, string opc, PatFrag opnode> + : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, + opc, ".w\t$Rd, $Rm$rot", + [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> { + let Inst{31-27} = 0b11111; + let Inst{26-23} = 0b0100; + let Inst{22-20} = opcod; + let Inst{19-16} = 0b1111; // Rn + let Inst{15-12} = 0b1111; + let Inst{7} = 1; - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate - } + bits<2> rot; + let Inst{5-4} = rot{1-0}; // rotate } // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. @@ -1669,9 +1657,9 @@ // Sign extenders -defm t2SXTB : T2I_ext_rrot<0b100, "sxtb", +def t2SXTB : T2I_ext_rrot<0b100, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; -defm t2SXTH : T2I_ext_rrot<0b000, "sxth", +def t2SXTH : T2I_ext_rrot<0b000, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; @@ -1686,9 +1674,9 @@ // Zero extenders let AddedComplexity = 16 in { -defm t2UXTB : T2I_ext_rrot<0b101, "uxtb", +def t2UXTB : T2I_ext_rrot<0b101, "uxtb", UnOpFrag<(and node:$Src, 0x000000FF)>>; -defm t2UXTH : T2I_ext_rrot<0b001, "uxth", +def t2UXTH : T2I_ext_rrot<0b001, "uxth", UnOpFrag<(and node:$Src, 0x0000FFFF)>>; defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; @@ -3462,3 +3450,16 @@ let Inst{19-16} = CRn; let Inst{23-20} = opc1; } + + + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +// + +// SXT/UXT with no rotate +def : T2Pat<(and rGPR:$Src, 0x000000FF), (t2UXTB rGPR:$Src, 0)>; +def : T2Pat<(and rGPR:$Src, 0x0000FFFF), (t2UXTH rGPR:$Src, 0)>; + +def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>; +def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>; Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=136225&r1=136224&r2=136225&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jul 27 11:47:19 2011 @@ -97,11 +97,11 @@ { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 }, { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 }, { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 }, - { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, - { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, + { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1 }, + { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1 }, { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 }, - { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, - { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, + { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1 }, + { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1 }, // FIXME: Clean this up after splitting each Thumb load / store opcode // into multiple ones. @@ -546,6 +546,10 @@ } case ARM::t2RSBri: case ARM::t2RSBSri: + case ARM::t2SXTB: + case ARM::t2SXTH: + case ARM::t2UXTB: + case ARM::t2UXTH: if (MI->getOperand(2).getImm() == 0) return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); break; @@ -742,7 +746,11 @@ if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) continue; if ((MCID.getOpcode() == ARM::t2RSBSri || - MCID.getOpcode() == ARM::t2RSBri) && i == 2) + MCID.getOpcode() == ARM::t2RSBri || + MCID.getOpcode() == ARM::t2SXTB || + MCID.getOpcode() == ARM::t2SXTH || + MCID.getOpcode() == ARM::t2UXTB || + MCID.getOpcode() == ARM::t2UXTH) && i == 2) // Skip the zero immediate operand, it's now implicit. continue; bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); From clattner at apple.com Wed Jul 27 11:50:27 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 27 Jul 2011 09:50:27 -0700 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp In-Reply-To: <20110727160041.1C6DE2A6C12C@llvm.org> References: <20110727160041.1C6DE2A6C12C@llvm.org> Message-ID: <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> On Jul 27, 2011, at 9:00 AM, Jakub Staszak wrote: > Author: kuba > Date: Wed Jul 27 11:00:40 2011 > New Revision: 136222 > > URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev > Log: > Optimize 96-bit division a little bit. How about: if (top_part1 == 0 && top_part2 == 0) return low1/low2; .. slow path.. ? -Chris > > Modified: > llvm/trunk/lib/Support/BlockFrequency.cpp > > Modified: llvm/trunk/lib/Support/BlockFrequency.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=136222&r1=136221&r2=136222&view=diff > ============================================================================== > --- llvm/trunk/lib/Support/BlockFrequency.cpp (original) > +++ llvm/trunk/lib/Support/BlockFrequency.cpp Wed Jul 27 11:00:40 2011 > @@ -46,8 +46,9 @@ > uint64_t div96bit(uint64_t W[2], uint32_t D) { > uint64_t y = W[0]; > uint64_t x = W[1]; > + int i; > > - for (int i = 1; i <= 64; ++i) { > + for (i = 1; i <= 64 && x; ++i) { > uint32_t t = (int)x >> 31; > x = (x << 1) | (y >> 63); > y = y << 1; > @@ -57,7 +58,7 @@ > } > } > > - return y; > + return y << (64 - i + 1); > } > > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jstaszak at apple.com Wed Jul 27 12:24:06 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 10:24:06 -0700 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp In-Reply-To: <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> References: <20110727160041.1C6DE2A6C12C@llvm.org> <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> Message-ID: <63B4FA3E-F475-4BB3-9790-C0CC0CA27333@apple.com> -Kuba On Jul 27, 2011, at 9:50 AM, Chris Lattner wrote: > > On Jul 27, 2011, at 9:00 AM, Jakub Staszak wrote: > >> Author: kuba >> Date: Wed Jul 27 11:00:40 2011 >> New Revision: 136222 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev >> Log: >> Optimize 96-bit division a little bit. > > How about: > if (top_part1 == 0 && top_part2 == 0) > return low1/low2; > .. slow path.. > ? Sorry Chris, I don't fully understand your comment. - Kuba -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/4335109d/attachment.html From atrick at apple.com Wed Jul 27 12:47:01 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 27 Jul 2011 10:47:01 -0700 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp In-Reply-To: <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> References: <20110727160041.1C6DE2A6C12C@llvm.org> <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> Message-ID: <58B04D00-9133-4D9A-8F59-04FC438E7BD5@apple.com> On Jul 27, 2011, at 9:50 AM, Chris Lattner wrote: > > On Jul 27, 2011, at 9:00 AM, Jakub Staszak wrote: > >> Author: kuba >> Date: Wed Jul 27 11:00:40 2011 >> New Revision: 136222 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev >> Log: >> Optimize 96-bit division a little bit. > > How about: > if (top_part1 == 0 && top_part2 == 0) > return low1/low2; > .. slow path.. > ? > > -Chris div96bit is currently just a local helper. Kuba already checks for 64-bit overflow before calling it. But it does seem like it would be better to do mult96bit then check the top_part instead of UINT64_MAX / n. if (n > 0 && Frequency > UINT64_MAX / n) { // 96-bit value represented as W[1]:W[0]. uint64_t W[2]; // Probability is less or equal to 1 which means that results must fit // 64-bit. mult96bit(Frequency, n, W); Frequency = div96bit(W, d); -Andy > >> >> Modified: >> llvm/trunk/lib/Support/BlockFrequency.cpp >> >> Modified: llvm/trunk/lib/Support/BlockFrequency.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=136222&r1=136221&r2=136222&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Support/BlockFrequency.cpp (original) >> +++ llvm/trunk/lib/Support/BlockFrequency.cpp Wed Jul 27 11:00:40 2011 >> @@ -46,8 +46,9 @@ >> uint64_t div96bit(uint64_t W[2], uint32_t D) { >> uint64_t y = W[0]; >> uint64_t x = W[1]; >> + int i; >> >> - for (int i = 1; i <= 64; ++i) { >> + for (i = 1; i <= 64 && x; ++i) { >> uint32_t t = (int)x >> 31; >> x = (x << 1) | (y >> 63); >> y = y << 1; >> @@ -57,7 +58,7 @@ >> } >> } >> >> - return y; >> + return y << (64 - i + 1); >> } >> >> } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Wed Jul 27 12:46:49 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 27 Jul 2011 10:46:49 -0700 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp In-Reply-To: <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> References: <20110727160041.1C6DE2A6C12C@llvm.org> <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> Message-ID: On Wed, Jul 27, 2011 at 09:50, Chris Lattner wrote: > > On Jul 27, 2011, at 9:00 AM, Jakub Staszak wrote: > >> Author: kuba >> Date: Wed Jul 27 11:00:40 2011 >> New Revision: 136222 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev >> Log: >> Optimize 96-bit division a little bit. > > How about: > ?if (top_part1 == 0 && top_part2 == 0) > ? ?return low1/low2; > ?.. slow path.. It looks like the code already checks that and only uses 96 bit arithmetic if it's really necessary. However, there's a lot of optimization potential in the 96 bit division algorithm. As the bit widths are known it should be possible to do it with a bunch of 64 bit divs+mods. Trying to optimize it without unit tests is dangerous though ? - Ben From grosbach at apple.com Wed Jul 27 12:48:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 17:48:13 -0000 Subject: [llvm-commits] [llvm] r136226 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb2.td Message-ID: <20110727174813.EE3662A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 12:48:13 2011 New Revision: 136226 URL: http://llvm.org/viewvc/llvm-project?rev=136226&view=rev Log: ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136226&r1=136225&r2=136226&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 12:48:13 2011 @@ -1011,56 +1011,30 @@ /// AI_exta_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -multiclass AI_exta_rrot opcod, string opc, PatFrag opnode> { - def rr : AExtI, - Requires<[IsARM, HasV6]> { - bits<4> Rd; - bits<4> Rm; - bits<4> Rn; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-10} = 0b00; - let Inst{9-4} = 0b000111; - let Inst{3-0} = Rm; - } - def rr_rot : AExtI, - Requires<[IsARM, HasV6]> { - bits<4> Rd; - bits<4> Rm; - bits<4> Rn; - bits<2> rot; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-10} = rot; - let Inst{9-4} = 0b000111; - let Inst{3-0} = Rm; - } +class AI_exta_rrot opcod, string opc, PatFrag opnode> + : AExtI, + Requires<[IsARM, HasV6]> { + bits<4> Rd; + bits<4> Rm; + bits<4> Rn; + bits<2> rot; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-10} = rot; + let Inst{9-4} = 0b000111; + let Inst{3-0} = Rm; } -// For disassembly only. -multiclass AI_exta_rrot_np opcod, string opc> { - def rr : AExtI, - Requires<[IsARM, HasV6]> { - let Inst{11-10} = 0b00; - } - def rr_rot : AExtI, - Requires<[IsARM, HasV6]> { - bits<4> Rn; - bits<2> rot; - let Inst{19-16} = Rn; - let Inst{11-10} = rot; - } +class AI_exta_rrot_np opcod, string opc> + : AExtI, + Requires<[IsARM, HasV6]> { + bits<4> Rn; + bits<2> rot; + let Inst{19-16} = Rn; + let Inst{11-10} = rot; } /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. @@ -2377,14 +2351,14 @@ def SXTH : AI_ext_rrot<0b01101011, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; -defm SXTAB : AI_exta_rrot<0b01101010, +def SXTAB : AI_exta_rrot<0b01101010, "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; -defm SXTAH : AI_exta_rrot<0b01101011, +def SXTAH : AI_exta_rrot<0b01101011, "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; -defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; +def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; // Zero extenders @@ -2405,15 +2379,14 @@ def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), (UXTB16 GPR:$Src, 1)>; -defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", +def UXTAB : AI_exta_rrot<0b01101110, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; -defm UXTAH : AI_exta_rrot<0b01101111, "uxtah", +def UXTAH : AI_exta_rrot<0b01101111, "uxtah", BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; } // This isn't safe in general, the add is two 16-bit units, not a 32-bit add. -// For disassembly only -defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; +def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; def SBFX : I<(outs GPR:$Rd), @@ -4265,14 +4238,24 @@ Requires<[IsARM, HasV6]>; // SXT/UXT with no rotate +let AddedComplexity = 16 in { def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; -let AddedComplexity = 10 in def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; +def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), + (UXTAB GPR:$Rn, GPR:$Rm, 0)>; +def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), + (UXTAH GPR:$Rn, GPR:$Rm, 0)>; +} def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; +def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i8)), + (SXTAB GPR:$Rn, GPR:$Rm, 0)>; +def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i16)), + (SXTAH GPR:$Rn, GPR:$Rm, 0)>; + //===----------------------------------------------------------------------===// // Thumb Support // Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136226&r1=136225&r2=136226&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 27 12:48:13 2011 @@ -993,116 +993,64 @@ } // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. -multiclass T2I_ext_rrot_uxtb16 opcod, string opc, PatFrag opnode> { - def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, - opc, "\t$Rd, $Rm", - [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = 0b00; // rotate - } - def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), - IIC_iEXTr, opc, "\t$dst, $Rm$rot", - [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate - } +class T2I_ext_rrot_uxtb16 opcod, string opc, PatFrag opnode> + : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), + IIC_iEXTr, opc, "\t$dst, $Rm$rot", + [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, + Requires<[HasT2ExtractPack, IsThumb2]> { + bits<2> rot; + let Inst{31-27} = 0b11111; + let Inst{26-23} = 0b0100; + let Inst{22-20} = opcod; + let Inst{19-16} = 0b1111; // Rn + let Inst{15-12} = 0b1111; + let Inst{7} = 1; + let Inst{5-4} = rot; } // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern // supported yet. -multiclass T2I_ext_rrot_sxtb16 opcod, string opc> { - def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, - opc, "\t$Rd, $Rm", []>, +class T2I_ext_rrot_sxtb16 opcod, string opc> + : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, + opc, "\t$Rd, $Rm$rot", []>, Requires<[IsThumb2, HasT2ExtractPack]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = 0b00; // rotate - } - def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr, - opc, "\t$Rd, $Rm, ror $rot", []>, - Requires<[IsThumb2, HasT2ExtractPack]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate - } + bits<2> rot; + let Inst{31-27} = 0b11111; + let Inst{26-23} = 0b0100; + let Inst{22-20} = opcod; + let Inst{19-16} = 0b1111; // Rn + let Inst{15-12} = 0b1111; + let Inst{7} = 1; + let Inst{5-4} = rot; } /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -multiclass T2I_exta_rrot opcod, string opc, PatFrag opnode> { - def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr, - opc, "\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = 0b00; // rotate - } - def rr_rot : T2ThreeReg<(outs rGPR:$Rd), - (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", - [(set rGPR:$Rd, (opnode rGPR:$Rn, - (rotr rGPR:$Rm, rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate - } -} - -multiclass T2I_exta_rrot_np opcod, string opc> { - def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr, - opc, "\t$Rd, $Rn, $Rm", []> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = 0b00; // rotate - } - def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate - } +class T2I_exta_rrot opcod, string opc, PatFrag opnode> + : T2ThreeReg<(outs rGPR:$Rd), + (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", + [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, + Requires<[HasT2ExtractPack, IsThumb2]> { + bits<2> rot; + let Inst{31-27} = 0b11111; + let Inst{26-23} = 0b0100; + let Inst{22-20} = opcod; + let Inst{15-12} = 0b1111; + let Inst{7} = 1; + let Inst{5-4} = rot; +} + +class T2I_exta_rrot_np opcod, string opc> + : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), + IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { + bits<2> rot; + let Inst{31-27} = 0b11111; + let Inst{26-23} = 0b0100; + let Inst{22-20} = opcod; + let Inst{15-12} = 0b1111; + let Inst{7} = 1; + let Inst{5-4} = rot; } //===----------------------------------------------------------------------===// @@ -1661,15 +1609,15 @@ UnOpFrag<(sext_inreg node:$Src, i8)>>; def t2SXTH : T2I_ext_rrot<0b000, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; -defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; +def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; -defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab", +def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; -defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah", +def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; -defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; +def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; -// TODO: SXT(A){B|H}16 - done for disassembly only +// TODO: SXT(A){B|H}16 // Zero extenders @@ -1678,7 +1626,7 @@ UnOpFrag<(and node:$Src, 0x000000FF)>>; def t2UXTH : T2I_ext_rrot<0b001, "uxth", UnOpFrag<(and node:$Src, 0x0000FFFF)>>; -defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", +def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; // FIXME: This pattern incorrectly assumes the shl operator is a rotate. @@ -1686,17 +1634,17 @@ // instead so we can include a check for masking back in the upper // eight bits of the source into the lower eight bits of the result. //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), -// (t2UXTB16r_rot rGPR:$Src, 3)>, +// (t2UXTB16 rGPR:$Src, 3)>, // Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), - (t2UXTB16r_rot rGPR:$Src, 1)>, + (t2UXTB16 rGPR:$Src, 1)>, Requires<[HasT2ExtractPack, IsThumb2]>; -defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab", +def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; -defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah", +def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; -defm t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; +def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; } //===----------------------------------------------------------------------===// @@ -3458,8 +3406,28 @@ // // SXT/UXT with no rotate -def : T2Pat<(and rGPR:$Src, 0x000000FF), (t2UXTB rGPR:$Src, 0)>; -def : T2Pat<(and rGPR:$Src, 0x0000FFFF), (t2UXTH rGPR:$Src, 0)>; - -def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>; -def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>; +let AddedComplexity = 16 in { +def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), + (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), + (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +} + +def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), + (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; +def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), + (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, + Requires<[HasT2ExtractPack, IsThumb2]>; From jstaszak at apple.com Wed Jul 27 12:52:35 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 10:52:35 -0700 Subject: [llvm-commits] [llvm] r136222 - /llvm/trunk/lib/Support/BlockFrequency.cpp In-Reply-To: References: <20110727160041.1C6DE2A6C12C@llvm.org> <20E09186-2027-4449-BCFC-C72D6F22DC03@apple.com> Message-ID: <5DA2A828-13A0-46BF-A5A5-A5698FBE4F26@apple.com> -Kuba On Jul 27, 2011, at 10:46 AM, Benjamin Kramer wrote: > On Wed, Jul 27, 2011 at 09:50, Chris Lattner wrote: >> >> On Jul 27, 2011, at 9:00 AM, Jakub Staszak wrote: >> >>> Author: kuba >>> Date: Wed Jul 27 11:00:40 2011 >>> New Revision: 136222 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=136222&view=rev >>> Log: >>> Optimize 96-bit division a little bit. >> >> How about: >> if (top_part1 == 0 && top_part2 == 0) >> return low1/low2; >> .. slow path.. > > It looks like the code already checks that and only uses 96 bit > arithmetic if it's really necessary. However, there's a lot of > optimization potential in the 96 bit division algorithm. As the bit > widths are known it should be possible to do it with a bunch of 64 bit > divs+mods. > > Trying to optimize it without unit tests is dangerous though ? > > - Ben I'm working on unit tests right now. Actually I have them, I'm just copying them to unittests/Support/. I will also try to optimize the algorithm, but it is not so easy (for me) as I thought at the beginning. I had an algorithm with "bunch of 64 bit divs+mods" and it was slower than the one we have here. - Kuba -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/a7249b84/attachment.html From dpatel at apple.com Wed Jul 27 13:14:50 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 27 Jul 2011 18:14:50 -0000 Subject: [llvm-commits] [llvm] r136228 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20110727181450.A4BC62A6C12C@llvm.org> Author: dpatel Date: Wed Jul 27 13:14:50 2011 New Revision: 136228 URL: http://llvm.org/viewvc/llvm-project?rev=136228&view=rev Log: Update document listing DIVariable elements to reflect recent changes. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=136228&r1=136227&r2=136228&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Wed Jul 27 13:14:50 2011 @@ -750,7 +750,9 @@ metadata, ;; Reference to file where defined i32, ;; 24 bit - Line number where defined ;; 8 bit - Argument number. 1 indicates 1st argument. - metadata ;; Type descriptor + metadata, ;; Type descriptor + i32, ;; flags + metadata ;; (optional) Reference to inline location } From grosbach at apple.com Wed Jul 27 13:19:32 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 18:19:32 -0000 Subject: [llvm-commits] [llvm] r136229 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110727181932.DFB4B2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 13:19:32 2011 New Revision: 136229 URL: http://llvm.org/viewvc/llvm-project?rev=136229&view=rev Log: ARM assembly parsing aliases for extend instructions w/o rotate. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136229&r1=136228&r2=136229&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 13:19:32 2011 @@ -4342,3 +4342,25 @@ // SSAT optional shift operand. def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>; + + +// Extend instruction optional rotate operand. +def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm", + (SXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm", + (SXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", + (SXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"sxtb${p} $Rd, $Rm", (SXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"sxtb16${p} $Rd, $Rm", (SXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"sxth${p} $Rd, $Rm", (SXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>; + +def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm", + (UXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm", + (UXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", + (UXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>; +def : InstAlias<"uxth${p} $Rd, $Rm", (UXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>; From kremenek at apple.com Wed Jul 27 13:40:45 2011 From: kremenek at apple.com (Ted Kremenek) Date: Wed, 27 Jul 2011 18:40:45 -0000 Subject: [llvm-commits] [llvm] r136233 - in /llvm/trunk/include/llvm: ADT/DenseMap.h ADT/SmallVector.h Support/Capacity.h Message-ID: <20110727184045.D6B8D2A6C12C@llvm.org> Author: kremenek Date: Wed Jul 27 13:40:45 2011 New Revision: 136233 URL: http://llvm.org/viewvc/llvm-project?rev=136233&view=rev Log: Add a generic 'capacity_in_bytes' function to allow inspection of memory usage of various data structures. Added: llvm/trunk/include/llvm/Support/Capacity.h Modified: llvm/trunk/include/llvm/ADT/DenseMap.h llvm/trunk/include/llvm/ADT/SmallVector.h Modified: llvm/trunk/include/llvm/ADT/DenseMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=136233&r1=136232&r2=136233&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/DenseMap.h (original) +++ llvm/trunk/include/llvm/ADT/DenseMap.h Wed Jul 27 13:40:45 2011 @@ -540,6 +540,12 @@ ++Ptr; } }; + +template +static inline size_t +capacity_in_bytes(const DenseMap &X) { + return X.getMemorySize(); +} } // end namespace llvm Modified: llvm/trunk/include/llvm/ADT/SmallVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=136233&r1=136232&r2=136233&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallVector.h (original) +++ llvm/trunk/include/llvm/ADT/SmallVector.h Wed Jul 27 13:40:45 2011 @@ -78,21 +78,21 @@ return BeginX == static_cast(&FirstEl); } + /// grow_pod - This is an implementation of the grow() method which only works + /// on POD-like data types and is out of line to reduce code duplication. + void grow_pod(size_t MinSizeInBytes, size_t TSize); + +public: /// size_in_bytes - This returns size()*sizeof(T). size_t size_in_bytes() const { return size_t((char*)EndX - (char*)BeginX); } - + /// capacity_in_bytes - This returns capacity()*sizeof(T). size_t capacity_in_bytes() const { return size_t((char*)CapacityX - (char*)BeginX); } - /// grow_pod - This is an implementation of the grow() method which only works - /// on POD-like data types and is out of line to reduce code duplication. - void grow_pod(size_t MinSizeInBytes, size_t TSize); - -public: bool empty() const { return BeginX == EndX; } }; @@ -738,6 +738,11 @@ }; +template +static inline size_t capacity_in_bytes(const SmallVector &X) { + return X.capacity_in_bytes(); +} + } // End llvm namespace namespace std { Added: llvm/trunk/include/llvm/Support/Capacity.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Capacity.h?rev=136233&view=auto ============================================================================== --- llvm/trunk/include/llvm/Support/Capacity.h (added) +++ llvm/trunk/include/llvm/Support/Capacity.h Wed Jul 27 13:40:45 2011 @@ -0,0 +1,30 @@ +//===--- Capacity.h - Generic computation of ADT memory use -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the capacity function that computes the amount of +// memory used by an ADT. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_CAPACITY_H +#define LLVM_SUPPORT_CAPACITY_H + +namespace llvm { + +template +static inline size_t capacity_in_bytes(const T &x) { + // This default definition of capacity should work for things like std::vector + // and friends. More specialized versions will work for others. + return x.capacity() * sizeof(typename T::value_type); +} + +} // end namespace llvm + +#endif + From jstaszak at apple.com Wed Jul 27 13:57:41 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 18:57:41 -0000 Subject: [llvm-commits] [llvm] r136244 - /llvm/trunk/unittests/Support/BlockFrequencyTest.cpp Message-ID: <20110727185741.1D0002A6C12C@llvm.org> Author: kuba Date: Wed Jul 27 13:57:40 2011 New Revision: 136244 URL: http://llvm.org/viewvc/llvm-project?rev=136244&view=rev Log: Add test cases for BlockFrequency. Added: llvm/trunk/unittests/Support/BlockFrequencyTest.cpp Added: llvm/trunk/unittests/Support/BlockFrequencyTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/BlockFrequencyTest.cpp?rev=136244&view=auto ============================================================================== --- llvm/trunk/unittests/Support/BlockFrequencyTest.cpp (added) +++ llvm/trunk/unittests/Support/BlockFrequencyTest.cpp Wed Jul 27 13:57:40 2011 @@ -0,0 +1,56 @@ +#include "llvm/Support/DataTypes.h" +#include "llvm/Support/BlockFrequency.h" +#include "llvm/Support/BranchProbability.h" + +#include "gtest/gtest.h" +#include + +using namespace llvm; + +namespace { + +TEST(BlockFrequencyTest, OneToZero) { + BlockFrequency Freq(1); + BranchProbability Prob(UINT32_MAX - 1, UINT32_MAX); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), 0u); +} + +TEST(BlockFrequencyTest, OneToOne) { + BlockFrequency Freq(1); + BranchProbability Prob(UINT32_MAX, UINT32_MAX); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), 1u); +} + +TEST(BlockFrequencyTest, ThreeToOne) { + BlockFrequency Freq(3); + BranchProbability Prob(3000000, 9000000); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), 1u); +} + +TEST(BlockFrequencyTest, MaxToHalfMax) { + BlockFrequency Freq(UINT64_MAX); + BranchProbability Prob(UINT32_MAX / 2, UINT32_MAX); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), 9223372034707292159LLu); +} + +TEST(BlockFrequencyTest, BigToBig) { + const uint64_t Big = 387246523487234346LL; + const uint32_t P = 123456789; + BlockFrequency Freq(Big); + BranchProbability Prob(P, P); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), Big); +} + +TEST(BlockFrequencyTest, MaxToMax) { + BlockFrequency Freq(UINT64_MAX); + BranchProbability Prob(UINT32_MAX, UINT32_MAX); + Freq *= Prob; + EXPECT_EQ(Freq.getFrequency(), UINT64_MAX); +} + +} From eli.friedman at gmail.com Wed Jul 27 13:59:19 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 18:59:19 -0000 Subject: [llvm-commits] [llvm] r136245 - /llvm/trunk/include/llvm-c/Core.h Message-ID: <20110727185919.3FA712A6C12C@llvm.org> Author: efriedma Date: Wed Jul 27 13:59:19 2011 New Revision: 136245 URL: http://llvm.org/viewvc/llvm-project?rev=136245&view=rev Log: The numbering of LLVMOpcode is supposed to be stable; revert my earlier change, and append Fence onto the end. Modified: llvm/trunk/include/llvm-c/Core.h Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136245&r1=136244&r2=136245&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 13:59:19 2011 @@ -155,36 +155,38 @@ LLVMLoad = 27, LLVMStore = 28, LLVMGetElementPtr = 29, - LLVMFence = 30, /* Cast Operators */ - LLVMTrunc = 33, - LLVMZExt = 34, - LLVMSExt = 35, - LLVMFPToUI = 36, - LLVMFPToSI = 37, - LLVMUIToFP = 38, - LLVMSIToFP = 39, - LLVMFPTrunc = 40, - LLVMFPExt = 41, - LLVMPtrToInt = 42, - LLVMIntToPtr = 43, - LLVMBitCast = 44, + LLVMTrunc = 30, + LLVMZExt = 31, + LLVMSExt = 32, + LLVMFPToUI = 33, + LLVMFPToSI = 34, + LLVMUIToFP = 35, + LLVMSIToFP = 36, + LLVMFPTrunc = 37, + LLVMFPExt = 38, + LLVMPtrToInt = 39, + LLVMIntToPtr = 40, + LLVMBitCast = 41, /* Other Operators */ - LLVMICmp = 45, - LLVMFCmp = 46, - LLVMPHI = 47, - LLVMCall = 48, - LLVMSelect = 49, + LLVMICmp = 42, + LLVMFCmp = 43, + LLVMPHI = 44, + LLVMCall = 45, + LLVMSelect = 46, /* UserOp1 */ /* UserOp2 */ - LLVMVAArg = 52, - LLVMExtractElement = 53, - LLVMInsertElement = 54, - LLVMShuffleVector = 55, - LLVMExtractValue = 56, - LLVMInsertValue = 57 + LLVMVAArg = 49, + LLVMExtractElement = 50, + LLVMInsertElement = 51, + LLVMShuffleVector = 52, + LLVMExtractValue = 53, + LLVMInsertValue = 54, + + /* Atomic operators */ + LLVMFence = 55 } LLVMOpcode; typedef enum { From eli.friedman at gmail.com Wed Jul 27 14:43:50 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 19:43:50 -0000 Subject: [llvm-commits] [llvm] r136249 - /llvm/trunk/lib/Target/X86/X86InstrCompiler.td Message-ID: <20110727194351.040B72A6C12C@llvm.org> Author: efriedma Date: Wed Jul 27 14:43:50 2011 New Revision: 136249 URL: http://llvm.org/viewvc/llvm-project?rev=136249&view=rev Log: X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics. Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=136249&r1=136248&r2=136249&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Jul 27 14:43:50 2011 @@ -532,7 +532,7 @@ let hasSideEffects = 1 in def Int_MemBarrier : I<0, Pseudo, (outs), (ins), "#MEMBARRIER", - [(X86MemBarrier)]>, Requires<[HasSSE2]>; + [(X86MemBarrier)]>; // TODO: Get this to fold the constant into the instruction. let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in From clattner at apple.com Wed Jul 27 14:45:01 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 27 Jul 2011 12:45:01 -0700 Subject: [llvm-commits] [llvm] r136233 - in /llvm/trunk/include/llvm: ADT/DenseMap.h ADT/SmallVector.h Support/Capacity.h In-Reply-To: <20110727184045.D6B8D2A6C12C@llvm.org> References: <20110727184045.D6B8D2A6C12C@llvm.org> Message-ID: <7BE97676-3AC7-465D-A577-155D6B7446EA@apple.com> On Jul 27, 2011, at 11:40 AM, Ted Kremenek wrote: > Author: kremenek > Date: Wed Jul 27 13:40:45 2011 > New Revision: 136233 > > URL: http://llvm.org/viewvc/llvm-project?rev=136233&view=rev > Log: > Add a generic 'capacity_in_bytes' function to allow inspection of memory usage of various data structures. Cool, how about adding this to STLExtras.h instead of a new header? -Chris > > Added: > llvm/trunk/include/llvm/Support/Capacity.h > Modified: > llvm/trunk/include/llvm/ADT/DenseMap.h > llvm/trunk/include/llvm/ADT/SmallVector.h > > Modified: llvm/trunk/include/llvm/ADT/DenseMap.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=136233&r1=136232&r2=136233&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/ADT/DenseMap.h (original) > +++ llvm/trunk/include/llvm/ADT/DenseMap.h Wed Jul 27 13:40:45 2011 > @@ -540,6 +540,12 @@ > ++Ptr; > } > }; > + > +template > +static inline size_t > +capacity_in_bytes(const DenseMap &X) { > + return X.getMemorySize(); > +} > > } // end namespace llvm > > > Modified: llvm/trunk/include/llvm/ADT/SmallVector.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=136233&r1=136232&r2=136233&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/ADT/SmallVector.h (original) > +++ llvm/trunk/include/llvm/ADT/SmallVector.h Wed Jul 27 13:40:45 2011 > @@ -78,21 +78,21 @@ > return BeginX == static_cast(&FirstEl); > } > > + /// grow_pod - This is an implementation of the grow() method which only works > + /// on POD-like data types and is out of line to reduce code duplication. > + void grow_pod(size_t MinSizeInBytes, size_t TSize); > + > +public: > /// size_in_bytes - This returns size()*sizeof(T). > size_t size_in_bytes() const { > return size_t((char*)EndX - (char*)BeginX); > } > - > + > /// capacity_in_bytes - This returns capacity()*sizeof(T). > size_t capacity_in_bytes() const { > return size_t((char*)CapacityX - (char*)BeginX); > } > > - /// grow_pod - This is an implementation of the grow() method which only works > - /// on POD-like data types and is out of line to reduce code duplication. > - void grow_pod(size_t MinSizeInBytes, size_t TSize); > - > -public: > bool empty() const { return BeginX == EndX; } > }; > > @@ -738,6 +738,11 @@ > > }; > > +template > +static inline size_t capacity_in_bytes(const SmallVector &X) { > + return X.capacity_in_bytes(); > +} > + > } // End llvm namespace > > namespace std { > > Added: llvm/trunk/include/llvm/Support/Capacity.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Capacity.h?rev=136233&view=auto > ============================================================================== > --- llvm/trunk/include/llvm/Support/Capacity.h (added) > +++ llvm/trunk/include/llvm/Support/Capacity.h Wed Jul 27 13:40:45 2011 > @@ -0,0 +1,30 @@ > +//===--- Capacity.h - Generic computation of ADT memory use -----*- C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file defines the capacity function that computes the amount of > +// memory used by an ADT. > +// > +//===----------------------------------------------------------------------===// > + > +#ifndef LLVM_SUPPORT_CAPACITY_H > +#define LLVM_SUPPORT_CAPACITY_H > + > +namespace llvm { > + > +template > +static inline size_t capacity_in_bytes(const T &x) { > + // This default definition of capacity should work for things like std::vector > + // and friends. More specialized versions will work for others. > + return x.capacity() * sizeof(typename T::value_type); > +} > + > +} // end namespace llvm > + > +#endif > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nicholas at mxc.ca Wed Jul 27 14:47:34 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 27 Jul 2011 19:47:34 -0000 Subject: [llvm-commits] [llvm] r136250 - in /llvm/trunk: lib/Transforms/IPO/ConstantMerge.cpp test/Transforms/ConstantMerge/merge-both.ll Message-ID: <20110727194734.AAA4F2A6C12C@llvm.org> Author: nicholas Date: Wed Jul 27 14:47:34 2011 New Revision: 136250 URL: http://llvm.org/viewvc/llvm-project?rev=136250&view=rev Log: Teach the ConstantMerge pass about alignment. Fixes PR10514! Modified: llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp llvm/trunk/test/Transforms/ConstantMerge/merge-both.ll Modified: llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp?rev=136250&r1=136249&r2=136250&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp Wed Jul 27 14:47:34 2011 @@ -23,7 +23,9 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/Pass.h" +#include "llvm/Target/TargetData.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" using namespace llvm; @@ -37,10 +39,18 @@ initializeConstantMergePass(*PassRegistry::getPassRegistry()); } - // run - For this pass, process all of the globals in the module, - // eliminating duplicate constants. - // + // For this pass, process all of the globals in the module, eliminating + // duplicate constants. bool runOnModule(Module &M); + + // Return true iff we can determine the alignment of this global variable. + bool hasKnownAlignment(GlobalVariable *GV) const; + + // Return the alignment of the global, including converting the default + // alignment to a concrete value. + unsigned getAlignment(GlobalVariable *GV) const; + + const TargetData *TD; }; } @@ -77,15 +87,28 @@ return A.hasUnnamedAddr(); } +bool ConstantMerge::hasKnownAlignment(GlobalVariable *GV) const { + return TD || GV->getAlignment() != 0; +} + +unsigned ConstantMerge::getAlignment(GlobalVariable *GV) const { + if (TD) + return TD->getPreferredAlignment(GV); + return GV->getAlignment(); +} + bool ConstantMerge::runOnModule(Module &M) { + TD = getAnalysisIfAvailable(); + // Find all the globals that are marked "used". These cannot be merged. SmallPtrSet UsedGlobals; FindUsedValues(M.getGlobalVariable("llvm.used"), UsedGlobals); FindUsedValues(M.getGlobalVariable("llvm.compiler.used"), UsedGlobals); - // Map unique constant/section pairs to globals. We don't want to merge - // globals in different sections. - DenseMap CMap; + // Map unique pairs to globals. We don't + // want to merge globals of unknown alignment with those of explicit + // alignment. If we have TargetData, we always know the alignment. + DenseMap, GlobalVariable*> CMap; // Replacements - This vector contains a list of replacements to perform. SmallVector, 32> Replacements; @@ -120,7 +143,8 @@ Constant *Init = GV->getInitializer(); // Check to see if the initializer is already known. - GlobalVariable *&Slot = CMap[Init]; + PointerIntPair Pair(Init, hasKnownAlignment(GV)); + GlobalVariable *&Slot = CMap[Pair]; // If this is the first constant we find or if the old on is local, // replace with the current one. It the current is externally visible @@ -152,7 +176,8 @@ Constant *Init = GV->getInitializer(); // Check to see if the initializer is already known. - GlobalVariable *Slot = CMap[Init]; + PointerIntPair Pair(Init, hasKnownAlignment(GV)); + GlobalVariable *Slot = CMap[Pair]; if (!Slot || Slot == GV) continue; @@ -175,6 +200,14 @@ // now. This avoid invalidating the pointers in CMap, which are unneeded // now. for (unsigned i = 0, e = Replacements.size(); i != e; ++i) { + // Bump the alignment if necessary. + if (Replacements[i].first->getAlignment() || + Replacements[i].second->getAlignment()) { + Replacements[i].second->setAlignment(std::max( + Replacements[i].first->getAlignment(), + Replacements[i].second->getAlignment())); + } + // Eliminate any uses of the dead global. Replacements[i].first->replaceAllUsesWith(Replacements[i].second); Modified: llvm/trunk/test/Transforms/ConstantMerge/merge-both.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantMerge/merge-both.ll?rev=136250&r1=136249&r2=136250&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstantMerge/merge-both.ll (original) +++ llvm/trunk/test/Transforms/ConstantMerge/merge-both.ll Wed Jul 27 14:47:34 2011 @@ -1,5 +1,7 @@ ; RUN: opt -constmerge %s -S -o - | FileCheck %s ; Test that in one run var3 is merged into var2 and var1 into var4. +; Test that we merge @var5 and @var6 into one with the higher alignment, and +; don't merge var7/var8 into var5/var6. declare void @zed(%struct.foobar*, %struct.foobar*) @@ -14,13 +16,24 @@ ; CHECK-NOT: @ ; CHECK: @var2 = constant %struct.foobar { i32 2 } ; CHECK-NEXT: @var4 = constant %struct.foobar { i32 2 } -; CHECK-NOT: @ -; CHECK: declare void @zed(%struct.foobar*, %struct.foobar*) + +declare void @helper([16 x i8]*) + at var5 = internal constant [16 x i8] c"foo1bar2foo3bar\00", align 16 + at var6 = private unnamed_addr constant [16 x i8] c"foo1bar2foo3bar\00", align 1 + at var7 = internal constant [16 x i8] c"foo1bar2foo3bar\00" + at var8 = private unnamed_addr constant [16 x i8] c"foo1bar2foo3bar\00" + +; CHECK-NEXT: @var6 = private constant [16 x i8] c"foo1bar2foo3bar\00", align 16 +; CHECK-NEXT: @var8 = private constant [16 x i8] c"foo1bar2foo3bar\00" define i32 @main() { entry: call void @zed(%struct.foobar* @var1, %struct.foobar* @var2) call void @zed(%struct.foobar* @var3, %struct.foobar* @var4) + call void @helper([16 x i8]* @var5) + call void @helper([16 x i8]* @var6) + call void @helper([16 x i8]* @var7) + call void @helper([16 x i8]* @var8) ret i32 0 } From grosbach at apple.com Wed Jul 27 15:15:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 20:15:40 -0000 Subject: [llvm-commits] [llvm] r136252 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s Message-ID: <20110727201540.9AEE62A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 15:15:40 2011 New Revision: 136252 URL: http://llvm.org/viewvc/llvm-project?rev=136252&view=rev Log: ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136252&r1=136251&r2=136252&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 15:15:40 2011 @@ -397,11 +397,16 @@ case 24: return CurDAG->getTargetConstant(3, MVT::i32); } }]>; +def RotImmAsmOperand : AsmOperandClass { + let Name = "RotImm"; + let ParserMethod = "parseRotImm"; +} def rot_imm : Operand, PatLeaf<(i32 imm), [{ int32_t v = N->getZExtValue(); return v == 8 || v == 16 || v == 24; }], rot_imm_XFORM> { let PrintMethod = "printRotImmOperand"; + let ParserMatchClass = RotImmAsmOperand; } // shift_imm: An integer that encodes a shift amount and the type of shift Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136252&r1=136251&r2=136252&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 15:15:40 2011 @@ -124,6 +124,7 @@ } OperandMatchResultTy parseSetEndImm(SmallVectorImpl&); OperandMatchResultTy parseShifterImm(SmallVectorImpl&); + OperandMatchResultTy parseRotImm(SmallVectorImpl&); // Asm Match Converter Methods bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, @@ -187,6 +188,7 @@ ShiftedRegister, ShiftedImmediate, ShifterImmediate, + RotateImmediate, Token } Kind; @@ -260,6 +262,9 @@ unsigned SrcReg; unsigned ShiftImm; } RegShiftedImm; + struct { + unsigned Imm; + } RotImm; }; ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -312,6 +317,9 @@ case ShiftedImmediate: RegShiftedImm = o.RegShiftedImm; break; + case RotateImmediate: + RotImm = o.RotImm; + break; } } @@ -531,6 +539,7 @@ bool isShifterImm() const { return Kind == ShifterImmediate; } bool isRegShiftedReg() const { return Kind == ShiftedRegister; } bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } + bool isRotImm() const { return Kind == RotateImmediate; } bool isMemMode2() const { if (getMemAddrMode() != ARMII::AddrMode2) return false; @@ -701,6 +710,12 @@ addRegListOperands(Inst, N); } + void addRotImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // Encoded as val>>3. The printer handles display as 8, 16, 24. + Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); + } + void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); @@ -1008,6 +1023,14 @@ return Op; } + static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { + ARMOperand *Op = new ARMOperand(RotateImmediate); + Op->RotImm.Imm = Imm; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + static ARMOperand * CreateRegList(const SmallVectorImpl > &Regs, SMLoc StartLoc, SMLoc EndLoc) { @@ -1183,6 +1206,9 @@ << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) << ">"; break; + case RotateImmediate: + OS << ""; + break; case RegisterList: case DPRRegisterList: case SPRRegisterList: { @@ -1810,6 +1836,58 @@ return MatchOperand_Success; } +/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family +/// of instructions. Legal values are: +/// ror #n 'n' in {0, 8, 16, 24} +ARMAsmParser::OperandMatchResultTy ARMAsmParser:: +parseRotImm(SmallVectorImpl &Operands) { + const AsmToken &Tok = Parser.getTok(); + SMLoc S = Tok.getLoc(); + if (Tok.isNot(AsmToken::Identifier)) { + Error(S, "rotate operator 'ror' expected"); + return MatchOperand_ParseFail; + } + StringRef ShiftName = Tok.getString(); + if (ShiftName != "ror" && ShiftName != "ROR") { + Error(S, "rotate operator 'ror' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat the operator. + + // A '#' and a rotate amount. + if (Parser.getTok().isNot(AsmToken::Hash)) { + Error(Parser.getTok().getLoc(), "'#' expected"); + return MatchOperand_ParseFail; + } + Parser.Lex(); // Eat hash token. + + const MCExpr *ShiftAmount; + SMLoc E = Parser.getTok().getLoc(); + if (getParser().ParseExpression(ShiftAmount)) { + Error(E, "malformed rotate expression"); + return MatchOperand_ParseFail; + } + const MCConstantExpr *CE = dyn_cast(ShiftAmount); + if (!CE) { + Error(E, "rotate amount must be an immediate"); + return MatchOperand_ParseFail; + } + + int64_t Val = CE->getValue(); + // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) + // normally, zero is represented in asm by omitting the rotate operand + // entirely. + if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { + Error(E, "'ror' rotate amount must be 8, 16, or 24"); + return MatchOperand_ParseFail; + } + + E = Parser.getTok().getLoc(); + Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); + + return MatchOperand_Success; +} + /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136252&r1=136251&r2=136252&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 15:15:40 2011 @@ -1802,3 +1802,115 @@ @ CHECK: swp r1, r2, [r3] @ encoding: [0x92,0x10,0x03,0xe1] @ CHECK: swp r4, r4, [r6] @ encoding: [0x94,0x40,0x06,0xe1] @ CHECK: swpb r5, r1, [r9] @ encoding: [0x91,0x50,0x49,0xe1] + + + at ------------------------------------------------------------------------------ +@ SXTAB + at ------------------------------------------------------------------------------ + sxtab r2, r3, r4 + sxtab r4, r5, r6, ror #0 + sxtablt r6, r2, r9, ror #8 + sxtab r5, r1, r4, ror #16 + sxtab r7, r8, r3, ror #24 + +@ CHECK: sxtab r2, r3, r4 @ encoding: [0x74,0x20,0xa3,0xe6] +@ CHECK: sxtab r4, r5, r6 @ encoding: [0x76,0x40,0xa5,0xe6] +@ CHECK: sxtablt r6, r2, r9, ror #8 + @ encoding: [0x79,0x64,0xa2,0xb6] +@ CHECK: sxtab r5, r1, r4, ror #16 + @ encoding: [0x74,0x58,0xa1,0xe6] +@ CHECK: sxtab r7, r8, r3, ror #24 + @ encoding: [0x73,0x7c,0xa8,0xe6] + + + at ------------------------------------------------------------------------------ +@ SXTAB16 + at ------------------------------------------------------------------------------ + sxtab16ge r0, r1, r4 + sxtab16 r6, r2, r7, ror #0 + sxtab16 r3, r5, r8, ror #8 + sxtab16 r3, r2, r1, ror #16 + sxtab16eq r1, r2, r3, ror #24 + +@ CHECK: sxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0x81,0xa6] +@ CHECK: sxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0x82,0xe6] +@ CHECK: sxtab16 r3, r5, r8, ror #8 + @ encoding: [0x78,0x34,0x85,0xe6] +@ CHECK: sxtab16 r3, r2, r1, ror #16 + @ encoding: [0x71,0x38,0x82,0xe6] +@ CHECK: sxtab16eq r1, r2, r3, ror #24 + @ encoding: [0x73,0x1c,0x82,0x06] + + at ------------------------------------------------------------------------------ +@ SXTAH + at ------------------------------------------------------------------------------ + sxtah r1, r3, r9 + sxtahhi r6, r1, r6, ror #0 + sxtah r3, r8, r3, ror #8 + sxtahlo r2, r2, r4, ror #16 + sxtah r9, r3, r3, ror #24 + +@ CHECK: sxtah r1, r3, r9 @ encoding: [0x79,0x10,0xb3,0xe6] +@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xb1,0x86] +@ CHECK: sxtah r3, r8, r3, ror #8 + @ encoding: [0x73,0x34,0xb8,0xe6] +@ CHECK: sxtahlo r2, r2, r4, ror #16 + @ encoding: [0x74,0x28,0xb2,0x36] +@ CHECK: sxtah r9, r3, r3, ror #24 + @ encoding: [0x73,0x9c,0xb3,0xe6] + + at ------------------------------------------------------------------------------ +@ SXTB + at ------------------------------------------------------------------------------ + sxtbge r2, r4 + sxtb r5, r6, ror #0 + sxtb r6, r9, ror #8 + sxtbcc r5, r1, ror #16 + sxtb r8, r3, ror #24 + +@ CHECK: sxtbge r2, r4 @ encoding: [0x74,0x20,0xaf,0xa6] +@ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6] +@ CHECK: sxtb r6, r9, ror #8 + @ encoding: [0x79,0x64,0xaf,0xe6] +@ CHECK: sxtblo r5, r1, ror #16 + @ encoding: [0x71,0x58,0xaf,0x36] +@ CHECK: sxtb r8, r3, ror #24 + @ encoding: [0x73,0x8c,0xaf,0xe6] + + + at ------------------------------------------------------------------------------ +@ SXTB16 + at ------------------------------------------------------------------------------ + sxtb16 r1, r4 + sxtb16 r6, r7, ror #0 + sxtb16cs r3, r5, ror #8 + sxtb16 r3, r1, ror #16 + sxtb16ge r2, r3, ror #24 + +@ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6] +@ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6] +@ CHECK: sxtb16hs r3, r5, ror #8 + @ encoding: [0x75,0x34,0x8f,0x26] +@ CHECK: sxtb16 r3, r1, ror #16 + @ encoding: [0x71,0x38,0x8f,0xe6] +@ CHECK: sxtb16ge r2, r3, ror #24 + @ encoding: [0x73,0x2c,0x8f,0xa6] + + + at ------------------------------------------------------------------------------ +@ SXTH + at ------------------------------------------------------------------------------ + sxthne r3, r9 + sxth r1, r6, ror #0 + sxth r3, r8, ror #8 + sxthle r2, r2, ror #16 + sxth r9, r3, ror #24 + +@ CHECK: sxthne r3, r9 @ encoding: [0x79,0x30,0xbf,0x16] +@ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6] +@ CHECK: sxth r3, r8, ror #8 + @ encoding: [0x78,0x34,0xbf,0xe6] +@ CHECK: sxthle r2, r2, ror #16 + @ encoding: [0x72,0x28,0xbf,0xd6] +@ CHECK: sxth r9, r3, ror #24 + @ encoding: [0x73,0x9c,0xbf,0xe6] Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136252&r1=136251&r2=136252&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Wed Jul 27 15:15:40 2011 @@ -238,3 +238,37 @@ @ CHECK-ERRORS: error: source operands must be sequential @ CHECK-ERRORS: strexd r6, r5, r3, [r8] @ CHECK-ERRORS: ^ + + @ Illegal rotate operators for extend instructions + sxtb r8, r3, #8 + sxtb r8, r3, ror 24 + sxtb r8, r3, ror #8 - + sxtab r3, r8, r3, ror #(fred - wilma) + sxtab r7, r8, r3, ror #25 + sxtah r9, r3, r3, ror #-8 + sxtb16ge r2, r3, lsr #24 + +@ CHECK-ERRORS: error: rotate operator 'ror' expected +@ CHECK-ERRORS: sxtb r8, r3, #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: '#' expected +@ CHECK-ERRORS: sxtb r8, r3, ror 24 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: unknown token in expression +@ CHECK-ERRORS: sxtb r8, r3, ror #8 - +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: malformed rotate expression +@ CHECK-ERRORS: sxtb r8, r3, ror #8 - +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: rotate amount must be an immediate +@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma) +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24 +@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24 +@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: rotate operator 'ror' expected +@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24 +@ CHECK-ERRORS: ^ From fvbommel at gmail.com Wed Jul 27 15:17:13 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Wed, 27 Jul 2011 22:17:13 +0200 Subject: [llvm-commits] [llvm] r136250 - in /llvm/trunk: lib/Transforms/IPO/ConstantMerge.cpp test/Transforms/ConstantMerge/merge-both.ll In-Reply-To: <20110727194734.AAA4F2A6C12C@llvm.org> References: <20110727194734.AAA4F2A6C12C@llvm.org> Message-ID: On 27 July 2011 21:47, Nick Lewycky wrote: > +unsigned ConstantMerge::getAlignment(GlobalVariable *GV) const { > + ?if (TD) > + ? ?return TD->getPreferredAlignment(GV); > + ?return GV->getAlignment(); > +} This seems to be the wrong way around: shouldn't an explicit alignment override the preferred alignment? From isanbard at gmail.com Wed Jul 27 15:18:04 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 27 Jul 2011 20:18:04 -0000 Subject: [llvm-commits] [llvm] r136253 - in /llvm/trunk: docs/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCore/ test/Feature/ Message-ID: <20110727201805.154E62A6C12C@llvm.org> Author: void Date: Wed Jul 27 15:18:04 2011 New Revision: 136253 URL: http://llvm.org/viewvc/llvm-project?rev=136253&view=rev Log: Merge the contents from exception-handling-rewrite to the mainline. This adds the new instructions 'landingpad' and 'resume'. Added: llvm/trunk/test/Feature/exceptionhandling.ll Modified: llvm/trunk/docs/LangRef.html llvm/trunk/include/llvm-c/Core.h llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h llvm/trunk/include/llvm/Instruction.def llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/Support/IRBuilder.h llvm/trunk/include/llvm/Support/InstVisitor.h llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h llvm/trunk/lib/AsmParser/LLToken.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/lib/CodeGen/ShadowStackGC.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Scalar/SCCP.cpp llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/Core.cpp llvm/trunk/lib/VMCore/Instruction.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Jul 27 15:18:04 2011 @@ -123,6 +123,7 @@
    • 'indirectbr' Instruction
    • 'invoke' Instruction
    • 'unwind' Instruction
      • +
    • 'resume' Instruction
    • 'unreachable' Instruction
      • @@ -2942,13 +2943,14 @@ control flow, not values (the one exception being the 'invoke' instruction).

      -

      There are seven different terminator instructions: the +

      There are eight different terminator instructions: the 'ret' instruction, the 'br' instruction, the 'switch' instruction, the ''indirectbr' Instruction, the 'invoke' instruction, the - 'unwind' instruction, and the + 'unwind' instruction, the + 'resume' instruction, and the 'unreachable' instruction.

      @@ -3272,6 +3274,35 @@

      + 'resume' Instruction +

      + +
      + +
      Syntax:
      +
      +  resume <type> <value>
+
      + +
      Overview:
      +

      The 'resume' instruction is a terminator instruction that has no + successors. Its operand must have the same type as the result of any + 'landingpad' instruction in the same function.

      + +
      Semantics:
      +

      The 'resume' instruction resumes propagation of an existing + (in-flight) exception.

      + +
      Example:
      +
      + resume { i8*, i32 } %exn
+
      + +
      + + + +

      'unreachable' Instruction

      Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 15:18:04 2011 @@ -126,67 +126,69 @@ LLVMIndirectBr = 4, LLVMInvoke = 5, LLVMUnwind = 6, - LLVMUnreachable = 7, + LLVMResume = 7, + LLVMUnreachable = 8, /* Standard Binary Operators */ - LLVMAdd = 8, - LLVMFAdd = 9, - LLVMSub = 10, - LLVMFSub = 11, - LLVMMul = 12, - LLVMFMul = 13, - LLVMUDiv = 14, - LLVMSDiv = 15, - LLVMFDiv = 16, - LLVMURem = 17, - LLVMSRem = 18, - LLVMFRem = 19, + LLVMAdd = 9, + LLVMFAdd = 10, + LLVMSub = 11, + LLVMFSub = 12, + LLVMMul = 13, + LLVMFMul = 14, + LLVMUDiv = 15, + LLVMSDiv = 16, + LLVMFDiv = 17, + LLVMURem = 18, + LLVMSRem = 19, + LLVMFRem = 20, /* Logical Operators */ - LLVMShl = 20, - LLVMLShr = 21, - LLVMAShr = 22, - LLVMAnd = 23, - LLVMOr = 24, - LLVMXor = 25, + LLVMShl = 21, + LLVMLShr = 22, + LLVMAShr = 23, + LLVMAnd = 24, + LLVMOr = 25, + LLVMXor = 26, /* Memory Operators */ - LLVMAlloca = 26, - LLVMLoad = 27, - LLVMStore = 28, - LLVMGetElementPtr = 29, + LLVMAlloca = 27, + LLVMLoad = 28, + LLVMStore = 29, + LLVMGetElementPtr = 30, /* Cast Operators */ - LLVMTrunc = 30, - LLVMZExt = 31, - LLVMSExt = 32, - LLVMFPToUI = 33, - LLVMFPToSI = 34, - LLVMUIToFP = 35, - LLVMSIToFP = 36, - LLVMFPTrunc = 37, - LLVMFPExt = 38, - LLVMPtrToInt = 39, - LLVMIntToPtr = 40, - LLVMBitCast = 41, + LLVMTrunc = 31, + LLVMZExt = 32, + LLVMSExt = 33, + LLVMFPToUI = 34, + LLVMFPToSI = 35, + LLVMUIToFP = 36, + LLVMSIToFP = 37, + LLVMFPTrunc = 38, + LLVMFPExt = 39, + LLVMPtrToInt = 40, + LLVMIntToPtr = 41, + LLVMBitCast = 42, /* Other Operators */ - LLVMICmp = 42, - LLVMFCmp = 43, - LLVMPHI = 44, - LLVMCall = 45, - LLVMSelect = 46, + LLVMICmp = 43, + LLVMFCmp = 44, + LLVMPHI = 45, + LLVMCall = 46, + LLVMSelect = 47, /* UserOp1 */ /* UserOp2 */ - LLVMVAArg = 49, - LLVMExtractElement = 50, - LLVMInsertElement = 51, - LLVMShuffleVector = 52, - LLVMExtractValue = 53, - LLVMInsertValue = 54, + LLVMVAArg = 50, + LLVMExtractElement = 51, + LLVMInsertElement = 52, + LLVMShuffleVector = 53, + LLVMExtractValue = 54, + LLVMInsertValue = 55, + LLVMLandingPad = 56, /* Atomic operators */ - LLVMFence = 55 + LLVMFence = 57 } LLVMOpcode; typedef enum { @@ -277,6 +279,11 @@ LLVMRealPredicateTrue /**< Always true (always folded) */ } LLVMRealPredicate; +typedef enum { + LLVMCatch, /**< A catch clause */ + LLVMFilter /**< A filter clause */ +} LLVMLandingPadClauseTy; + void LLVMInitializeCore(LLVMPassRegistryRef R); @@ -463,6 +470,7 @@ macro(GetElementPtrInst) \ macro(InsertElementInst) \ macro(InsertValueInst) \ + macro(LandingPadInst) \ macro(PHINode) \ macro(SelectInst) \ macro(ShuffleVectorInst) \ @@ -474,6 +482,7 @@ macro(SwitchInst) \ macro(UnreachableInst) \ macro(UnwindInst) \ + macro(ResumeInst) \ macro(UnaryInstruction) \ macro(AllocaInst) \ macro(CastInst) \ @@ -822,6 +831,7 @@ LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch, const char *Name); LLVMValueRef LLVMBuildUnwind(LLVMBuilderRef); +LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn); LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef); /* Add a case to the switch instruction */ @@ -831,6 +841,13 @@ /* Add a destination to the indirectbr instruction */ void LLVMAddDestination(LLVMValueRef IndirectBr, LLVMBasicBlockRef Dest); +/* Add a clause to the landingpad instruction */ +void LLVMAddClause(LLVMValueRef LandingPad, LLVMLandingPadClauseTy ClauseTy, + LLVMValueRef ClauseVal); + +/* Set the 'cleanup' flag in the landingpad instruction */ +void LLVMSetCleanup(LLVMValueRef LandingPad, LLVMBool Val); + /* Arithmetic */ LLVMValueRef LLVMBuildAdd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name); Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Wed Jul 27 15:18:04 2011 @@ -257,7 +257,7 @@ FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE FUNC_CODE_INST_PHI = 16, // PHI: [ty, val0,bb0, ...] - // 17 is unused. + FUNC_CODE_INST_RESUME = 17, // RESUME: [opval] // 18 is unused. FUNC_CODE_INST_ALLOCA = 19, // ALLOCA: [instty, op, align] FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol] @@ -284,7 +284,8 @@ FUNC_CODE_INST_CALL = 34, // CALL: [attr, fnty, fnid, args...] FUNC_CODE_DEBUG_LOC = 35, // DEBUG_LOC: [Line,Col,ScopeVal, IAVal] - FUNC_CODE_INST_FENCE = 36 // FENCE: [ordering, synchscope] + FUNC_CODE_INST_FENCE = 36, // FENCE: [ordering, synchscope] + FUNC_CODE_INST_LANDINGPAD = 37 // LANDINGPAD: [ty,val,val,num,id0,val0...] }; } // End bitc namespace } // End llvm namespace Modified: llvm/trunk/include/llvm/Instruction.def URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instruction.def (original) +++ llvm/trunk/include/llvm/Instruction.def Wed Jul 27 15:18:04 2011 @@ -100,41 +100,42 @@ HANDLE_TERM_INST ( 4, IndirectBr , IndirectBrInst) HANDLE_TERM_INST ( 5, Invoke , InvokeInst) HANDLE_TERM_INST ( 6, Unwind , UnwindInst) -HANDLE_TERM_INST ( 7, Unreachable, UnreachableInst) - LAST_TERM_INST ( 7) +HANDLE_TERM_INST ( 7, Resume , ResumeInst) +HANDLE_TERM_INST ( 8, Unreachable, UnreachableInst) + LAST_TERM_INST ( 8) // Standard binary operators... - FIRST_BINARY_INST( 8) -HANDLE_BINARY_INST( 8, Add , BinaryOperator) -HANDLE_BINARY_INST( 9, FAdd , BinaryOperator) -HANDLE_BINARY_INST(10, Sub , BinaryOperator) -HANDLE_BINARY_INST(11, FSub , BinaryOperator) -HANDLE_BINARY_INST(12, Mul , BinaryOperator) -HANDLE_BINARY_INST(13, FMul , BinaryOperator) -HANDLE_BINARY_INST(14, UDiv , BinaryOperator) -HANDLE_BINARY_INST(15, SDiv , BinaryOperator) -HANDLE_BINARY_INST(16, FDiv , BinaryOperator) -HANDLE_BINARY_INST(17, URem , BinaryOperator) -HANDLE_BINARY_INST(18, SRem , BinaryOperator) -HANDLE_BINARY_INST(19, FRem , BinaryOperator) + FIRST_BINARY_INST( 9) +HANDLE_BINARY_INST( 9, Add , BinaryOperator) +HANDLE_BINARY_INST(10, FAdd , BinaryOperator) +HANDLE_BINARY_INST(11, Sub , BinaryOperator) +HANDLE_BINARY_INST(12, FSub , BinaryOperator) +HANDLE_BINARY_INST(13, Mul , BinaryOperator) +HANDLE_BINARY_INST(14, FMul , BinaryOperator) +HANDLE_BINARY_INST(15, UDiv , BinaryOperator) +HANDLE_BINARY_INST(16, SDiv , BinaryOperator) +HANDLE_BINARY_INST(17, FDiv , BinaryOperator) +HANDLE_BINARY_INST(18, URem , BinaryOperator) +HANDLE_BINARY_INST(19, SRem , BinaryOperator) +HANDLE_BINARY_INST(20, FRem , BinaryOperator) // Logical operators (integer operands) -HANDLE_BINARY_INST(20, Shl , BinaryOperator) // Shift left (logical) -HANDLE_BINARY_INST(21, LShr , BinaryOperator) // Shift right (logical) -HANDLE_BINARY_INST(22, AShr , BinaryOperator) // Shift right (arithmetic) -HANDLE_BINARY_INST(23, And , BinaryOperator) -HANDLE_BINARY_INST(24, Or , BinaryOperator) -HANDLE_BINARY_INST(25, Xor , BinaryOperator) - LAST_BINARY_INST(25) +HANDLE_BINARY_INST(21, Shl , BinaryOperator) // Shift left (logical) +HANDLE_BINARY_INST(22, LShr , BinaryOperator) // Shift right (logical) +HANDLE_BINARY_INST(23, AShr , BinaryOperator) // Shift right (arithmetic) +HANDLE_BINARY_INST(24, And , BinaryOperator) +HANDLE_BINARY_INST(25, Or , BinaryOperator) +HANDLE_BINARY_INST(26, Xor , BinaryOperator) + LAST_BINARY_INST(26) // Memory operators... - FIRST_MEMORY_INST(26) -HANDLE_MEMORY_INST(26, Alloca, AllocaInst) // Stack management -HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs -HANDLE_MEMORY_INST(28, Store , StoreInst ) -HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst) -HANDLE_MEMORY_INST(30, Fence , FenceInst ) - LAST_MEMORY_INST(30) + FIRST_MEMORY_INST(27) +HANDLE_MEMORY_INST(27, Alloca, AllocaInst) // Stack management +HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs +HANDLE_MEMORY_INST(29, Store , StoreInst ) +HANDLE_MEMORY_INST(30, GetElementPtr, GetElementPtrInst) +HANDLE_MEMORY_INST(31, Fence , FenceInst ) + LAST_MEMORY_INST(31) // Cast operators ... // NOTE: The order matters here because CastInst::isEliminableCastPair @@ -169,8 +170,8 @@ HANDLE_OTHER_INST(55, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. HANDLE_OTHER_INST(56, ExtractValue, ExtractValueInst)// extract from aggregate HANDLE_OTHER_INST(57, InsertValue, InsertValueInst) // insert into aggregate - - LAST_OTHER_INST(57) +HANDLE_OTHER_INST(58, LandingPad, LandingPadInst) // Landing pad instruction. + LAST_OTHER_INST(58) #undef FIRST_TERM_INST #undef HANDLE_TERM_INST Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Wed Jul 27 15:18:04 2011 @@ -1775,6 +1775,116 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(PHINode, Value) +//===----------------------------------------------------------------------===// +// LandingPadInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// LandingPadInst - The landingpad instruction holds all of the information +/// necessary to generate correct exception handling. The landingpad instruction +/// cannot be moved from the top of a landing pad block, which itself is +/// accessible only from the 'unwind' edge of an invoke. +/// +class LandingPadInst : public Instruction { + /// ReservedSpace - The number of operands actually allocated. NumOperands is + /// the number actually in use. + unsigned ReservedSpace; + + /// IsCleanup - True if the landingpad instruction is also a cleanup. + bool IsCleanup; + LandingPadInst(const LandingPadInst &LP); +public: + enum ClauseType { Catch, Filter }; +private: + /// ClauseIdxs - This indexes into the OperandList, indicating what the + /// values are at a given index. + SmallVector ClauseIdxs; + + void *operator new(size_t, unsigned); // DO NOT IMPLEMENT + // Allocate space for exactly zero operands. + void *operator new(size_t s) { + return User::operator new(s, 0); + } + void growOperands(); + void init(Value *PersFn, unsigned NumReservedValues, const Twine &NameStr); + + explicit LandingPadInst(Type *RetTy, Value *PersonalityFn, + unsigned NumReservedValues, const Twine &NameStr, + Instruction *InsertBefore) + : Instruction(RetTy, Instruction::LandingPad, 0, 0, InsertBefore), + IsCleanup(false) { + init(PersonalityFn, 1 + NumReservedValues, NameStr); + } + explicit LandingPadInst(Type *RetTy, Value *PersonalityFn, + unsigned NumReservedValues, const Twine &NameStr, + BasicBlock *InsertAtEnd) + : Instruction(RetTy, Instruction::LandingPad, 0, 0, InsertAtEnd), + IsCleanup(false) { + init(PersonalityFn, 1 + NumReservedValues, NameStr); + } +protected: + virtual LandingPadInst *clone_impl() const; +public: + static LandingPadInst *Create(Type *RetTy, Value *PersonalityFn, + unsigned NumReservedValues, + const Twine &NameStr = "", + Instruction *InsertBefore = 0) { + return new LandingPadInst(RetTy, PersonalityFn, NumReservedValues, NameStr, + InsertBefore); + } + static LandingPadInst *Create(Type *RetTy, Value *PersonalityFn, + unsigned NumReservedValues, + const Twine &NameStr, BasicBlock *InsertAtEnd) { + return new LandingPadInst(RetTy, PersonalityFn, NumReservedValues, NameStr, + InsertAtEnd); + } + ~LandingPadInst(); + + /// Provide fast operand accessors + DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); + + /// getPersonalityFn - Get the personality function associated with this + /// landing pad. + const Value *getPersonalityFn() const { return getOperand(0); } + + // Simple accessors. + bool isCleanup() const { return IsCleanup; } + void setCleanup(bool Val) { IsCleanup = Val; } + + /// addClause - Add a clause to the landing pad. + void addClause(ClauseType CT, Value *ClauseVal); + + /// getClauseType - Return the type of the clause at this index. The two + /// supported clauses are Catch and Filter. + ClauseType getClauseType(unsigned I) const { + assert(I < ClauseIdxs.size() && "Index too large!"); + return ClauseIdxs[I]; + } + + /// getClauseValue - Return the value of the clause at this index. + Value *getClauseValue(unsigned I) const { + assert(I + 1 < getNumOperands() && "Index too large!"); + return OperandList[I + 1]; + } + + /// getNumClauses - Get the number of clauses for this landing pad. + unsigned getNumClauses() const { return getNumOperands() - 1; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const LandingPadInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::LandingPad; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +template <> +struct OperandTraits : public HungoffOperandTraits<2> { +}; + +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(LandingPadInst, Value) //===----------------------------------------------------------------------===// // ReturnInst Class @@ -2463,6 +2573,59 @@ }; //===----------------------------------------------------------------------===// +// ResumeInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// ResumeInst - Resume the propagation of an exception. +/// +class ResumeInst : public TerminatorInst { + ResumeInst(const ResumeInst &RI); + + explicit ResumeInst(LLVMContext &C, Value *Exn, Instruction *InsertBefore=0); + ResumeInst(LLVMContext &C, Value *Exn, BasicBlock *InsertAtEnd); +protected: + virtual ResumeInst *clone_impl() const; +public: + static ResumeInst *Create(LLVMContext &C, Value *Exn, + Instruction *InsertBefore = 0) { + return new(1) ResumeInst(C, Exn, InsertBefore); + } + static ResumeInst *Create(LLVMContext &C, Value *Exn, + BasicBlock *InsertAtEnd) { + return new(1) ResumeInst(C, Exn, InsertAtEnd); + } + + /// Provide fast operand accessors + DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); + + /// Convenience accessor. + Value *getResumeValue() const { return Op<0>(); } + + unsigned getNumSuccessors() const { return 0; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const ResumeInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Resume; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +private: + virtual BasicBlock *getSuccessorV(unsigned idx) const; + virtual unsigned getNumSuccessorsV() const; + virtual void setSuccessorV(unsigned idx, BasicBlock *B); +}; + +template <> +struct OperandTraits : + public FixedNumOperandTraits { +}; + +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ResumeInst, Value) + +//===----------------------------------------------------------------------===// // UnreachableInst Class //===----------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Jul 27 15:18:04 2011 @@ -479,6 +479,10 @@ return Insert(new UnwindInst(Context)); } + ResumeInst *CreateResume(Value *Exn) { + return Insert(ResumeInst::Create(Context, Exn)); + } + UnreachableInst *CreateUnreachable() { return Insert(new UnreachableInst(Context)); } @@ -1194,6 +1198,11 @@ return Insert(InsertValueInst::Create(Agg, Val, Idxs), Name); } + Value *CreateLandingPad(Type *Ty, Value *PersFn, unsigned NumClauses, + const Twine &Name = "") { + return Insert(LandingPadInst::Create(Ty, PersFn, NumClauses, Name)); + } + //===--------------------------------------------------------------------===// // Utility creation methods //===--------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/Support/InstVisitor.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/InstVisitor.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/InstVisitor.h (original) +++ llvm/trunk/include/llvm/Support/InstVisitor.h Wed Jul 27 15:18:04 2011 @@ -163,6 +163,7 @@ RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorInst);} RetTy visitInvokeInst(InvokeInst &I) { DELEGATE(TerminatorInst);} RetTy visitUnwindInst(UnwindInst &I) { DELEGATE(TerminatorInst);} + RetTy visitResumeInst(ResumeInst &I) { DELEGATE(TerminatorInst);} RetTy visitUnreachableInst(UnreachableInst &I) { DELEGATE(TerminatorInst);} RetTy visitICmpInst(ICmpInst &I) { DELEGATE(CmpInst);} RetTy visitFCmpInst(FCmpInst &I) { DELEGATE(CmpInst);} @@ -192,6 +193,7 @@ RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction); } RetTy visitExtractValueInst(ExtractValueInst &I) { DELEGATE(Instruction);} RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction); } + RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction); } // Next level propagators: If the user does not overload a specific // instruction type, they can overload one of these to get the whole class Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Wed Jul 27 15:18:04 2011 @@ -581,6 +581,11 @@ KEYWORD(x); KEYWORD(blockaddress); + + KEYWORD(personality); + KEYWORD(cleanup); + KEYWORD(catch); + KEYWORD(filter); #undef KEYWORD // Keywords for types. @@ -633,6 +638,7 @@ INSTKEYWORD(switch, Switch); INSTKEYWORD(indirectbr, IndirectBr); INSTKEYWORD(invoke, Invoke); + INSTKEYWORD(resume, Resume); INSTKEYWORD(unwind, Unwind); INSTKEYWORD(unreachable, Unreachable); @@ -647,6 +653,7 @@ INSTKEYWORD(shufflevector, ShuffleVector); INSTKEYWORD(extractvalue, ExtractValue); INSTKEYWORD(insertvalue, InsertValue); + INSTKEYWORD(landingpad, LandingPad); #undef INSTKEYWORD // Check for [us]0x[0-9A-Fa-f]+ which are Hexadecimal constant generated by @@ -674,7 +681,6 @@ return lltok::Error; } - /// Lex0x: Handle productions that start with 0x, knowing that it matches and /// that this is not a label: /// HexFPConstant 0x[0-9A-Fa-f]+ Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Jul 27 15:18:04 2011 @@ -2885,6 +2885,7 @@ case lltok::kw_switch: return ParseSwitch(Inst, PFS); case lltok::kw_indirectbr: return ParseIndirectBr(Inst, PFS); case lltok::kw_invoke: return ParseInvoke(Inst, PFS); + case lltok::kw_resume: return ParseResume(Inst, PFS); // Binary Operators. case lltok::kw_add: case lltok::kw_sub: @@ -2944,6 +2945,7 @@ case lltok::kw_insertelement: return ParseInsertElement(Inst, PFS); case lltok::kw_shufflevector: return ParseShuffleVector(Inst, PFS); case lltok::kw_phi: return ParsePHI(Inst, PFS); + case lltok::kw_landingpad: return ParseLandingPad(Inst, PFS); case lltok::kw_call: return ParseCall(Inst, PFS, false); case lltok::kw_tail: return ParseCall(Inst, PFS, true); // Memory. @@ -3247,7 +3249,18 @@ return false; } +/// ParseResume +/// ::= 'resume' TypeAndValue +bool LLParser::ParseResume(Instruction *&Inst, PerFunctionState &PFS) { + Value *Exn; LocTy ExnLoc; + LocTy Loc = Lex.getLoc(); + if (ParseTypeAndValue(Exn, ExnLoc, PFS)) + return true; + ResumeInst *RI = ResumeInst::Create(Context, Exn); + Inst = RI; + return false; +} //===----------------------------------------------------------------------===// // Binary Operators. @@ -3495,6 +3508,56 @@ return AteExtraComma ? InstExtraComma : InstNormal; } +/// ParseLandingPad +/// ::= 'landingpad' Type 'personality' TypeAndValue 'cleanup'? +/// (ClauseID ClauseList)+ +/// ClauseID +/// ::= 'catch' +/// ::= 'filter' +/// ClauseList +/// ::= TypeAndValue (',' TypeAndValue)* +bool LLParser::ParseLandingPad(Instruction *&Inst, PerFunctionState &PFS) { + Type *Ty = 0; LocTy TyLoc; + Value *PersFn; LocTy PersFnLoc; + LocTy LPLoc = Lex.getLoc(); + + if (ParseType(Ty, TyLoc) || + ParseToken(lltok::kw_personality, "expected 'personality'") || + ParseTypeAndValue(PersFn, PersFnLoc, PFS)) + return true; + + bool IsCleanup = EatIfPresent(lltok::kw_cleanup); + + SmallVector, 16> Clauses; + while (Lex.getKind() == lltok::kw_catch || Lex.getKind() == lltok::kw_filter){ + LandingPadInst::ClauseType CT; + if (Lex.getKind() == lltok::kw_catch) { + CT = LandingPadInst::Catch; + ParseToken(lltok::kw_catch, "expected 'catch'"); + } else { + CT = LandingPadInst::Filter; + ParseToken(lltok::kw_filter, "expected 'filter'"); + } + + do { + Value *V; LocTy VLoc; + if (ParseTypeAndValue(V, VLoc, PFS)) + return true; + Clauses.push_back(std::make_pair(CT, V)); + } while (EatIfPresent(lltok::comma)); + } + + LandingPadInst *LP = LandingPadInst::Create(Ty, PersFn, Clauses.size()); + LP->setCleanup(IsCleanup); + + for (SmallVectorImpl >::iterator + I = Clauses.begin(), E = Clauses.end(); I != E; ++I) + LP->addClause(I->first, I->second); + + Inst = LP; + return false; +} + /// ParseCall /// ::= 'tail'? 'call' OptionalCallingConv OptionalAttrs Type Value /// ParameterList OptionalAttrs Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Wed Jul 27 15:18:04 2011 @@ -347,6 +347,7 @@ bool ParseSwitch(Instruction *&Inst, PerFunctionState &PFS); bool ParseIndirectBr(Instruction *&Inst, PerFunctionState &PFS); bool ParseInvoke(Instruction *&Inst, PerFunctionState &PFS); + bool ParseResume(Instruction *&Inst, PerFunctionState &PFS); bool ParseArithmetic(Instruction *&I, PerFunctionState &PFS, unsigned Opc, unsigned OperandType); @@ -359,6 +360,7 @@ bool ParseInsertElement(Instruction *&I, PerFunctionState &PFS); bool ParseShuffleVector(Instruction *&I, PerFunctionState &PFS); int ParsePHI(Instruction *&I, PerFunctionState &PFS); + bool ParseLandingPad(Instruction *&I, PerFunctionState &PFS); bool ParseCall(Instruction *&I, PerFunctionState &PFS, bool isTail); int ParseAlloc(Instruction *&I, PerFunctionState &PFS); int ParseLoad(Instruction *&I, PerFunctionState &PFS, bool isVolatile); Modified: llvm/trunk/lib/AsmParser/LLToken.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLToken.h (original) +++ llvm/trunk/lib/AsmParser/LLToken.h Wed Jul 27 15:18:04 2011 @@ -121,7 +121,9 @@ kw_fptoui, kw_fptosi, kw_inttoptr, kw_ptrtoint, kw_bitcast, kw_select, kw_va_arg, - kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind, + kw_landingpad, kw_personality, kw_cleanup, kw_catch, kw_filter, + + kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind, kw_resume, kw_unreachable, kw_alloca, kw_load, kw_store, kw_fence, kw_getelementptr, @@ -143,8 +145,8 @@ // Type valued tokens (TyVal). Type, - APFloat, // APFloatVal - APSInt // APSInt + APFloat, // APFloatVal + APSInt // APSInt }; } // end namespace lltok } // end namespace llvm Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Jul 27 15:18:04 2011 @@ -2491,6 +2491,14 @@ cast(I)->setAttributes(PAL); break; } + case bitc::FUNC_CODE_INST_RESUME: { // RESUME: [opval] + unsigned Idx = 0; + Value *Val = 0; + if (getValueTypePair(Record, Idx, NextValueNo, Val)) + return Error("Invalid RESUME record"); + I = ResumeInst::Create(Context, Val); + break; + } case bitc::FUNC_CODE_INST_UNWIND: // UNWIND I = new UnwindInst(Context); InstructionList.push_back(I); @@ -2518,6 +2526,37 @@ break; } + case bitc::FUNC_CODE_INST_LANDINGPAD: { + // LANDINGPAD: [ty, val, val, num, (id0,val0 ...)?] + unsigned Idx = 0; + if (Record.size() < 4) + return Error("Invalid LANDINGPAD record"); + Type *Ty = getTypeByID(Record[Idx++]); + if (!Ty) return Error("Invalid LANDINGPAD record"); + Value *PersFn = 0; + if (getValueTypePair(Record, Idx, NextValueNo, PersFn)) + return Error("Invalid LANDINGPAD record"); + + bool IsCleanup = !!Record[Idx++]; + unsigned NumClauses = Record[Idx++]; + LandingPadInst *LP = LandingPadInst::Create(Ty, PersFn, NumClauses); + LP->setCleanup(IsCleanup); + for (unsigned J = 0; J != NumClauses; ++J) { + LandingPadInst::ClauseType CT = + LandingPadInst::ClauseType(Record[Idx++]); + Value *Val = 0; + if (getValueTypePair(Record, Idx, NextValueNo, Val)) { + delete LP; + return Error("Invalid LANDINGPAD record"); + } + + LP->addClause(CT, Val); + } + + I = LP; + break; + } + case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, opty, op, align] if (Record.size() != 4) return Error("Invalid ALLOCA record"); Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Jul 27 15:18:04 2011 @@ -1126,6 +1126,10 @@ } break; } + case Instruction::Resume: + Code = bitc::FUNC_CODE_INST_RESUME; + PushValueAndType(I.getOperand(0), InstID, Vals, VE); + break; case Instruction::Unwind: Code = bitc::FUNC_CODE_INST_UNWIND; break; @@ -1145,6 +1149,20 @@ break; } + case Instruction::LandingPad: { + const LandingPadInst &LP = cast(I); + Code = bitc::FUNC_CODE_INST_LANDINGPAD; + Vals.push_back(VE.getTypeID(LP.getType())); + PushValueAndType(LP.getPersonalityFn(), InstID, Vals, VE); + Vals.push_back(LP.isCleanup()); + Vals.push_back(LP.getNumClauses()); + for (unsigned I = 0, E = LP.getNumClauses(); I != E; ++I) { + Vals.push_back(LP.getClauseType(I)); + PushValueAndType(LP.getClauseValue(I), InstID, Vals, VE); + } + break; + } + case Instruction::Alloca: Code = bitc::FUNC_CODE_INST_ALLOCA; Vals.push_back(VE.getTypeID(I.getType())); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 27 15:18:04 2011 @@ -914,6 +914,10 @@ llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); } +void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &) { + // FIXME: Handle this +} + void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { // Note: this doesn't use InstVisitor, because it has to work with // ConstantExpr's in addition to instructions. @@ -1808,6 +1812,10 @@ void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { } +void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { + // FIXME: Handle this +} + /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for /// small case ranges). bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Wed Jul 27 15:18:04 2011 @@ -453,6 +453,7 @@ private: // These all get lowered before this pass. void visitInvoke(const InvokeInst &I); + void visitResume(const ResumeInst &I); void visitUnwind(const UnwindInst &I); void visitBinary(const User &I, unsigned OpCode); @@ -497,6 +498,7 @@ void visitExtractValue(const ExtractValueInst &I); void visitInsertValue(const InsertValueInst &I); + void visitLandingPad(const LandingPadInst &I); void visitGetElementPtr(const User &I); void visitSelect(const User &I); Modified: llvm/trunk/lib/CodeGen/ShadowStackGC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShadowStackGC.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ShadowStackGC.cpp (original) +++ llvm/trunk/lib/CodeGen/ShadowStackGC.cpp Wed Jul 27 15:18:04 2011 @@ -113,9 +113,11 @@ while (StateBB != StateE) { BasicBlock *CurBB = StateBB++; - // Branches and invokes do not escape, only unwind and return do. + // Branches and invokes do not escape, only unwind, resume, and return + // do. TerminatorInst *TI = CurBB->getTerminator(); - if (!isa(TI) && !isa(TI)) + if (!isa(TI) && !isa(TI) && + !isa(TI)) continue; Builder.SetInsertPoint(TI->getParent(), TI); Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Jul 27 15:18:04 2011 @@ -288,10 +288,12 @@ void visitInvokeInst(InvokeInst &I) { llvm_unreachable("Lowerinvoke pass didn't work!"); } - void visitUnwindInst(UnwindInst &I) { llvm_unreachable("Lowerinvoke pass didn't work!"); } + void visitResumeInst(ResumeInst &I) { + llvm_unreachable("Lowerinvoke pass didn't work!"); + } void visitUnreachableInst(UnreachableInst &I); void visitPHINode(PHINode &I); Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Jul 27 15:18:04 2011 @@ -1064,6 +1064,11 @@ } break; } + case Instruction::Resume: { + Out << "ResumeInst::Create(mod->getContext(), " << opNames[0] + << ", " << bbname << ");"; + break; + } case Instruction::Invoke: { const InvokeInst* inv = cast(I); Out << "std::vector " << iName << "_params;"; @@ -1423,6 +1428,9 @@ Out << "\", " << bbname << ");"; break; } + case Instruction::LandingPad: { + break; + } } DefinedValues.insert(I); nl(Out); Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Wed Jul 27 15:18:04 2011 @@ -2506,7 +2506,7 @@ CallStack.pop_back(); // return from fn. return true; // We succeeded at evaluating this ctor! } else { - // invoke, unwind, unreachable. + // invoke, unwind, resume, unreachable. return false; // Cannot handle this terminator. } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed Jul 27 15:18:04 2011 @@ -732,9 +732,11 @@ } } - // If the stack restore is in a return/unwind block and if there are no - // allocas or calls between the restore and the return, nuke the restore. - if (!CannotRemove && (isa(TI) || isa(TI))) + // If the stack restore is in a return, resume, or unwind block and if there + // are no allocas or calls between the restore and the return, nuke the + // restore. + if (!CannotRemove && (isa(TI) || isa(TI) || + isa(TI))) return EraseInstFromFunction(CI); break; } Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Wed Jul 27 15:18:04 2011 @@ -515,6 +515,7 @@ void visitShuffleVectorInst(ShuffleVectorInst &I); void visitExtractValueInst(ExtractValueInst &EVI); void visitInsertValueInst(InsertValueInst &IVI); + void visitLandingPadInst(LandingPadInst &I) { markAnythingOverdefined(&I); } // Instructions that cannot be folded away. void visitStoreInst (StoreInst &I); @@ -528,6 +529,7 @@ visitTerminatorInst(II); } void visitCallSite (CallSite CS); + void visitResumeInst (TerminatorInst &I) { /*returns void*/ } void visitUnwindInst (TerminatorInst &I) { /*returns void*/ } void visitUnreachableInst(TerminatorInst &I) { /*returns void*/ } void visitFenceInst (FenceInst &I) { /*returns void*/ } Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Wed Jul 27 15:18:04 2011 @@ -1710,6 +1710,9 @@ writeOperand(I.getOperand(i), true); } Out << ']'; + } else if (isa(I)) { + Out << ' '; + writeOperand(Operand, true); } else if (const PHINode *PN = dyn_cast(&I)) { Out << ' '; TypePrinter.print(I.getType(), Out); @@ -1732,6 +1735,33 @@ writeOperand(I.getOperand(1), true); for (const unsigned *i = IVI->idx_begin(), *e = IVI->idx_end(); i != e; ++i) Out << ", " << *i; + } else if (const LandingPadInst *LPI = dyn_cast(&I)) { + Out << ' '; + TypePrinter.print(I.getType(), Out); + Out << " personality "; + writeOperand(LPI->getPersonalityFn(), true); Out << '\n'; + + if (LPI->isCleanup()) + Out << " cleanup"; + + for (unsigned i = 0, e = LPI->getNumClauses(); i != e; ) { + if (i != 0 || LPI->isCleanup()) Out << "\n"; + + SmallVector Vals; + LandingPadInst::ClauseType CT = LPI->getClauseType(i); + for (; i != e && LPI->getClauseType(i) == CT; ++i) + Vals.push_back(LPI->getClauseValue(i)); + + if (CT == LandingPadInst::Catch) + Out << " catch "; + else + Out << " filter "; + + for (unsigned II = 0, IE = Vals.size(); II != IE; ++II) { + if (II != 0) Out << ", "; + writeOperand(Vals[II], true); + } + } } else if (isa(I) && !Operand) { Out << " void"; } else if (const CallInst *CI = dyn_cast(&I)) { Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Wed Jul 27 15:18:04 2011 @@ -1683,10 +1683,21 @@ Name)); } +LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty, + LLVMValueRef PersFn, unsigned NumClauses, + const char *Name) { + return wrap(unwrap(B)->CreateLandingPad(unwrap(Ty), unwrap(PersFn), + NumClauses, Name)); +} + LLVMValueRef LLVMBuildUnwind(LLVMBuilderRef B) { return wrap(unwrap(B)->CreateUnwind()); } +LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn) { + return wrap(unwrap(B)->CreateResume(unwrap(Exn))); +} + LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef B) { return wrap(unwrap(B)->CreateUnreachable()); } @@ -1700,6 +1711,17 @@ unwrap(IndirectBr)->addDestination(unwrap(Dest)); } +void LLVMAddClause(LLVMValueRef LandingPad, LLVMLandingPadClauseTy ClauseTy, + LLVMValueRef ClauseVal) { + unwrap(LandingPad)-> + addClause(static_cast(ClauseTy), + unwrap(ClauseVal)); +} + +void LLVMSetCleanup(LLVMValueRef LandingPad, LLVMBool Val) { + unwrap(LandingPad)->setCleanup(Val); +} + /*--.. Arithmetic ..........................................................--*/ LLVMValueRef LLVMBuildAdd(LLVMBuilderRef B, LLVMValueRef LHS, LLVMValueRef RHS, Modified: llvm/trunk/lib/VMCore/Instruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instruction.cpp (original) +++ llvm/trunk/lib/VMCore/Instruction.cpp Wed Jul 27 15:18:04 2011 @@ -101,6 +101,7 @@ case Switch: return "switch"; case IndirectBr: return "indirectbr"; case Invoke: return "invoke"; + case Resume: return "resume"; case Unwind: return "unwind"; case Unreachable: return "unreachable"; @@ -159,6 +160,7 @@ case ShuffleVector: return "shufflevector"; case ExtractValue: return "extractvalue"; case InsertValue: return "insertvalue"; + case LandingPad: return "landingpad"; default: return " "; } Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jul 27 15:18:04 2011 @@ -166,6 +166,63 @@ return ConstantValue; } +//===----------------------------------------------------------------------===// +// LandingPadInst Implementation +//===----------------------------------------------------------------------===// + +void LandingPadInst::init(Value *PersFn, unsigned NumReservedValues, + const Twine &NameStr) { + ReservedSpace = NumReservedValues; + NumOperands = 1; + OperandList = allocHungoffUses(ReservedSpace); + OperandList[0] = PersFn; + setName(NameStr); +} + +LandingPadInst::LandingPadInst(const LandingPadInst &LP) + : Instruction(LP.getType(), Instruction::LandingPad, + allocHungoffUses(LP.getNumOperands()), LP.getNumOperands()), + ReservedSpace(LP.getNumOperands()) { + Use *OL = OperandList, *InOL = LP.OperandList; + for (unsigned I = 0, E = ReservedSpace; I != E; ++I) + OL[I] = InOL[I]; + + for (SmallVectorImpl::const_iterator + I = LP.ClauseIdxs.begin(), E = LP.ClauseIdxs.end(); I != E; ++I) + ClauseIdxs.push_back(*I); + + IsCleanup = LP.IsCleanup; + SubclassOptionalData = LP.SubclassOptionalData; +} + +LandingPadInst::~LandingPadInst() { + dropHungoffUses(); +} + +/// growOperands - grow operands - This grows the operand list in response to a +/// push_back style of operation. This grows the number of ops by 2 times. +void LandingPadInst::growOperands() { + unsigned e = getNumOperands(); + ReservedSpace = e * 2; + + Use *NewOps = allocHungoffUses(ReservedSpace); + Use *OldOps = OperandList; + for (unsigned i = 0; i != e; ++i) + NewOps[i] = OldOps[i]; + + OperandList = NewOps; + Use::zap(OldOps, OldOps + e, true); +} + +void LandingPadInst::addClause(ClauseType CT, Value *ClauseVal) { + unsigned OpNo = getNumOperands(); + if (OpNo + 1 > ReservedSpace) + growOperands(); + assert(OpNo < ReservedSpace && "Growing didn't work!"); + ClauseIdxs.push_back(CT); + ++NumOperands; + OperandList[OpNo] = ClauseVal; +} //===----------------------------------------------------------------------===// // CallInst Implementation @@ -574,6 +631,42 @@ } //===----------------------------------------------------------------------===// +// ResumeInst Implementation +//===----------------------------------------------------------------------===// + +ResumeInst::ResumeInst(const ResumeInst &RI) + : TerminatorInst(Type::getVoidTy(RI.getContext()), Instruction::Resume, + OperandTraits::op_begin(this), 1) { + Op<0>() = RI.Op<0>(); + SubclassOptionalData = RI.SubclassOptionalData; +} + +ResumeInst::ResumeInst(LLVMContext &C, Value *Exn, Instruction *InsertBefore) + : TerminatorInst(Type::getVoidTy(C), Instruction::Resume, + OperandTraits::op_begin(this), 1, InsertBefore) { + Op<0>() = Exn; +} + +ResumeInst::ResumeInst(LLVMContext &C, Value *Exn, BasicBlock *InsertAtEnd) + : TerminatorInst(Type::getVoidTy(C), Instruction::Resume, + OperandTraits::op_begin(this), 1, InsertAtEnd) { + Op<0>() = Exn; +} + +unsigned ResumeInst::getNumSuccessorsV() const { + return getNumSuccessors(); +} + +void ResumeInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { + llvm_unreachable("ResumeInst has no successors!"); +} + +BasicBlock *ResumeInst::getSuccessorV(unsigned idx) const { + llvm_unreachable("ResumeInst has no successors!"); + return 0; +} + +//===----------------------------------------------------------------------===// // UnreachableInst Implementation //===----------------------------------------------------------------------===// @@ -592,11 +685,11 @@ } void UnreachableInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - llvm_unreachable("UnwindInst has no successors!"); + llvm_unreachable("UnreachableInst has no successors!"); } BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const { - llvm_unreachable("UnwindInst has no successors!"); + llvm_unreachable("UnreachableInst has no successors!"); return 0; } @@ -3122,6 +3215,10 @@ return new PHINode(*this); } +LandingPadInst *LandingPadInst::clone_impl() const { + return new LandingPadInst(*this); +} + ReturnInst *ReturnInst::clone_impl() const { return new(getNumOperands()) ReturnInst(*this); } @@ -3143,6 +3240,10 @@ return new(getNumOperands()) InvokeInst(*this); } +ResumeInst *ResumeInst::clone_impl() const { + return new(1) ResumeInst(*this); +} + UnwindInst *UnwindInst::clone_impl() const { LLVMContext &Context = getContext(); return new UnwindInst(Context); Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=136253&r1=136252&r2=136253&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Jul 27 15:18:04 2011 @@ -35,6 +35,12 @@ // * It is illegal to have a ret instruction that returns a value that does not // agree with the function return value type. // * Function call argument types match the function prototype +// * A landing pad is defined by a landingpad instruction, and can be jumped to +// only by the unwind edge of an invoke instruction. +// * A landingpad instruction must be the first non-PHI instruction in the +// block. +// * All landingpad instructions must use the same personality function with +// the same function. // * All other things that are tested by asserts spread about the code... // //===----------------------------------------------------------------------===// @@ -131,18 +137,22 @@ /// already. SmallPtrSet MDNodes; + /// PersonalityFn - The personality function referenced by the + /// LandingPadInsts. All LandingPadInsts within the same function must use + /// the same personality function. + const Value *PersonalityFn; + Verifier() - : FunctionPass(ID), - Broken(false), RealPass(true), action(AbortProcessAction), - Mod(0), Context(0), DT(0), MessagesStr(Messages) { - initializeVerifierPass(*PassRegistry::getPassRegistry()); - } + : FunctionPass(ID), Broken(false), RealPass(true), + action(AbortProcessAction), Mod(0), Context(0), DT(0), + MessagesStr(Messages), PersonalityFn(0) { + initializeVerifierPass(*PassRegistry::getPassRegistry()); + } explicit Verifier(VerifierFailureAction ctn) - : FunctionPass(ID), - Broken(false), RealPass(true), action(ctn), Mod(0), Context(0), DT(0), - MessagesStr(Messages) { - initializeVerifierPass(*PassRegistry::getPassRegistry()); - } + : FunctionPass(ID), Broken(false), RealPass(true), action(ctn), Mod(0), + Context(0), DT(0), MessagesStr(Messages), PersonalityFn(0) { + initializeVerifierPass(*PassRegistry::getPassRegistry()); + } bool doInitialization(Module &M) { Mod = &M; @@ -282,6 +292,7 @@ void visitAllocaInst(AllocaInst &AI); void visitExtractValueInst(ExtractValueInst &EVI); void visitInsertValueInst(InsertValueInst &IVI); + void visitLandingPadInst(LandingPadInst &LPI); void VerifyCallSite(CallSite CS); bool PerformTypeCheck(Intrinsic::ID ID, Function *F, Type *Ty, @@ -1321,7 +1332,7 @@ Assert1(Ordering == Acquire || Ordering == Release || Ordering == AcquireRelease || Ordering == SequentiallyConsistent, "fence instructions may only have " - " acquire, release, acq_rel, or seq_cst ordering.", &FI); + "acquire, release, acq_rel, or seq_cst ordering.", &FI); visitInstruction(FI); } @@ -1343,6 +1354,42 @@ visitInstruction(IVI); } +void Verifier::visitLandingPadInst(LandingPadInst &LPI) { + BasicBlock *BB = LPI.getParent(); + + // The landingpad instruction is ill-formed if it doesn't have any clauses and + // isn't a cleanup. + Assert1(LPI.getNumClauses() > 0 || LPI.isCleanup(), + "LandingPadInst needs at least one clause or to be a cleanup.", &LPI); + + // The landingpad instruction defines its parent as a landing pad block. The + // landing pad block may be branched to only by the unwind edge of an invoke. + for (pred_iterator I = pred_begin(BB), E = pred_end(BB); I != E; ++I) { + const InvokeInst *II = dyn_cast((*I)->getTerminator()); + Assert1(II && II->getUnwindDest() == BB, + "Block containing LandingPadInst must be jumped to " + "only by the unwind edge of an invoke.", &LPI); + } + + // The landingpad instruction must be the first non-PHI instruction in the + // block. + BasicBlock::iterator I = BB->begin(), E = BB->end(); + while (I != E && isa(I)) + ++I; + Assert1(I != E && isa(I) && I == LPI, + "LandingPadInst not the first non-PHI instruction in the block.", + &LPI); + + // The personality functions for all landingpad instructions within the same + // function should match. + if (PersonalityFn) + Assert1(LPI.getPersonalityFn() == PersonalityFn, + "Personality function doesn't match others in function", &LPI); + PersonalityFn = LPI.getPersonalityFn(); + + visitInstruction(LPI); +} + /// verifyInstruction - Verify that an instruction is well formed. /// void Verifier::visitInstruction(Instruction &I) { Added: llvm/trunk/test/Feature/exceptionhandling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/exceptionhandling.ll?rev=136253&view=auto ============================================================================== --- llvm/trunk/test/Feature/exceptionhandling.ll (added) +++ llvm/trunk/test/Feature/exceptionhandling.ll Wed Jul 27 15:18:04 2011 @@ -0,0 +1,54 @@ +; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll +; RUN: diff %t1.ll %t2.ll + + at _ZTIc = external constant i8* + at _ZTId = external constant i8* + at _ZTIPKc = external constant i8* + at .str = private unnamed_addr constant [16 x i8] c"caught char %c\0A\00", align 1 + +define void @_Z3barv() uwtable optsize alwaysinline ssp { +entry: + invoke void @_Z3quxv() optsize + to label %try.cont unwind label %lpad + +invoke.cont4: ; preds = %lpad + %eh.obj = extractvalue {i8*, i32} %exn, 0 + %tmp0 = tail call i8* @__cxa_begin_catch(i8* %eh.obj) nounwind + %exn.scalar = load i8* %tmp0, align 1 + %conv = sext i8 %exn.scalar to i32 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str, i64 0, i64 0), i32 %conv) optsize + tail call void @__cxa_end_catch() nounwind + br label %try.cont + +try.cont: ; preds = %entry, %invoke.cont4 + ret void + +lpad: ; preds = %entry + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + catch i8** @_ZTIc + filter i8** @_ZTIPKc + catch i8** @_ZTId + %tmp1 = extractvalue {i8*, i32} %exn, 1 + %tmp2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIc to i8*)) nounwind + %tmp3 = icmp eq i32 %tmp1, %tmp2 + br i1 %tmp3, label %invoke.cont4, label %eh.resume + +eh.resume: + resume { i8*, i32 } %exn +} + +declare void @_Z3quxv() optsize + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.typeid.for(i8*) nounwind + +declare void @llvm.eh.resume(i8*, i32) + +declare i8* @__cxa_begin_catch(i8*) + +declare i32 @printf(i8* nocapture, ...) nounwind optsize + +declare void @__cxa_end_catch() From resistor at mac.com Wed Jul 27 15:29:48 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 27 Jul 2011 20:29:48 -0000 Subject: [llvm-commits] [llvm] r136255 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/arm_addrmode2.s Message-ID: <20110727202948.7AEDF2A6C12D@llvm.org> Author: resistor Date: Wed Jul 27 15:29:48 2011 New Revision: 136255 URL: http://llvm.org/viewvc/llvm-project?rev=136255&view=rev Log: Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/MC/ARM/arm_addrmode2.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136255&r1=136254&r2=136255&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 15:29:48 2011 @@ -2090,22 +2090,50 @@ // STRT, STRBT, and STRHT are for disassembly only. -def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), IndexModePost, StFrm, IIC_iStore_ru, "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; + let Inst{21} = 1; // overwrite + let Inst{4} = 0; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + +def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; + let Inst{21} = 1; // overwrite + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + + +def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; let Inst{21} = 1; // overwrite + let Inst{4} = 0; let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } -def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePost, StFrm, IIC_iStore_bh_ru, "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; let Inst{21} = 1; // overwrite let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } + def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, IIC_iStore_bh_ru, "strht", "\t$Rt, $addr", "$addr.base = $base_wb", Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?rev=136255&r1=136254&r2=136255&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original) +++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Wed Jul 27 15:29:48 2011 @@ -1,4 +1,5 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s +@ XFAIL: * @ Post-indexed @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] From grosbach at apple.com Wed Jul 27 15:37:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 20:37:36 -0000 Subject: [llvm-commits] [llvm] r136259 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727203736.3B7CF2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 15:37:36 2011 New Revision: 136259 URL: http://llvm.org/viewvc/llvm-project?rev=136259&view=rev Log: ARM assembly parsing and encoding tests for TEQ instruction. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136259&r1=136258&r2=136259&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 15:37:36 2011 @@ -1914,3 +1914,37 @@ @ encoding: [0x72,0x28,0xbf,0xd6] @ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6] + + + at ------------------------------------------------------------------------------ +@ FIXME: TBB/TBH + at ------------------------------------------------------------------------------ + + + at ------------------------------------------------------------------------------ +@ TEQ + at ------------------------------------------------------------------------------ + teq r5, #0xf000 + teq r4, r5 + teq r4, r5, lsl #5 + teq r4, r5, lsr #5 + teq r4, r5, lsr #5 + teq r4, r5, asr #5 + teq r4, r5, ror #5 + teq r6, r7, lsl r9 + teq r6, r7, lsr r9 + teq r6, r7, asr r9 + teq r6, r7, ror r9 + +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1] +@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, asr #5 @ encoding: [0xc5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, ror #5 @ encoding: [0xe5,0x02,0x34,0xe1] +@ CHECK: teq r6, r7, lsl r9 @ encoding: [0x17,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, lsr r9 @ encoding: [0x37,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, asr r9 @ encoding: [0x57,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, ror r9 @ encoding: [0x77,0x09,0x36,0xe1] + From grosbach at apple.com Wed Jul 27 15:38:58 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 20:38:58 -0000 Subject: [llvm-commits] [llvm] r136260 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727203858.B3B652A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 15:38:58 2011 New Revision: 136260 URL: http://llvm.org/viewvc/llvm-project?rev=136260&view=rev Log: ARM assembly parsing and encoding tests for TST instruction. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136260&r1=136259&r2=136260&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 15:38:58 2011 @@ -1948,3 +1948,31 @@ @ CHECK: teq r6, r7, asr r9 @ encoding: [0x57,0x09,0x36,0xe1] @ CHECK: teq r6, r7, ror r9 @ encoding: [0x77,0x09,0x36,0xe1] + + at ------------------------------------------------------------------------------ +@ TST + at ------------------------------------------------------------------------------ + tst r5, #0xf000 + tst r4, r5 + tst r4, r5, lsl #5 + tst r4, r5, lsr #5 + tst r4, r5, lsr #5 + tst r4, r5, asr #5 + tst r4, r5, ror #5 + tst r6, r7, lsl r9 + tst r6, r7, lsr r9 + tst r6, r7, asr r9 + tst r6, r7, ror r9 + +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1] +@ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, asr #5 @ encoding: [0xc5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, ror #5 @ encoding: [0xe5,0x02,0x14,0xe1] +@ CHECK: tst r6, r7, lsl r9 @ encoding: [0x17,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, lsr r9 @ encoding: [0x37,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, asr r9 @ encoding: [0x57,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, ror r9 @ encoding: [0x77,0x09,0x16,0xe1] + From grosbach at apple.com Wed Jul 27 15:43:44 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 20:43:44 -0000 Subject: [llvm-commits] [llvm] r136261 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727204344.DB6D72A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 15:43:44 2011 New Revision: 136261 URL: http://llvm.org/viewvc/llvm-project?rev=136261&view=rev Log: ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136261&r1=136260&r2=136261&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 15:43:44 2011 @@ -1976,3 +1976,28 @@ @ CHECK: tst r6, r7, asr r9 @ encoding: [0x57,0x09,0x16,0xe1] @ CHECK: tst r6, r7, ror r9 @ encoding: [0x77,0x09,0x16,0xe1] + + at ------------------------------------------------------------------------------ +@ UADD16/UADD8 + at ------------------------------------------------------------------------------ + uadd16 r1, r2, r3 + uadd16gt r1, r2, r3 + uadd8 r1, r2, r3 + uadd8le r1, r2, r3 + +@ CHECK: uadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x52,0xe6] +@ CHECK: uadd16gt r1, r2, r3 @ encoding: [0x13,0x1f,0x52,0xc6] +@ CHECK: uadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xe6] +@ CHECK: uadd8le r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xd6] + + + at ------------------------------------------------------------------------------ +@ UASX + at ------------------------------------------------------------------------------ + uasx r9, r12, r0 + uasxeq r9, r12, r0 + +@ CHECK: uasx r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0xe6] +@ CHECK: uasxeq r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0x06] + + From nlewycky at google.com Wed Jul 27 15:46:56 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 27 Jul 2011 13:46:56 -0700 Subject: [llvm-commits] [llvm] r136250 - in /llvm/trunk: lib/Transforms/IPO/ConstantMerge.cpp test/Transforms/ConstantMerge/merge-both.ll In-Reply-To: References: <20110727194734.AAA4F2A6C12C@llvm.org> Message-ID: On 27 July 2011 13:17, Frits van Bommel wrote: > On 27 July 2011 21:47, Nick Lewycky wrote: > > +unsigned ConstantMerge::getAlignment(GlobalVariable *GV) const { > > + if (TD) > > + return TD->getPreferredAlignment(GV); > > + return GV->getAlignment(); > > +} > > This seems to be the wrong way around: shouldn't an explicit alignment > override the preferred alignment? > TargetData::getPreferredAlignment returns the explicit alignment on the GV if it has one. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/bec4ea32/attachment.html From rjmccall at apple.com Wed Jul 27 15:54:51 2011 From: rjmccall at apple.com (John McCall) Date: Wed, 27 Jul 2011 13:54:51 -0700 Subject: [llvm-commits] [llvm] r136253 - in /llvm/trunk: docs/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCore/ test/Feature/ In-Reply-To: <20110727201805.154E62A6C12C@llvm.org> References: <20110727201805.154E62A6C12C@llvm.org> Message-ID: On Jul 27, 2011, at 1:18 PM, Bill Wendling wrote: > Modified: llvm/trunk/include/llvm-c/Core.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136253&r1=136252&r2=136253&view=diff > ============================================================================== > --- llvm/trunk/include/llvm-c/Core.h (original) > +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 15:18:04 2011 > @@ -126,67 +126,69 @@ > LLVMIndirectBr = 4, > LLVMInvoke = 5, > LLVMUnwind = 6, > - LLVMUnreachable = 7, > + LLVMResume = 7, > + LLVMUnreachable = 8, > > /* Standard Binary Operators */ > - LLVMAdd = 8, > - LLVMFAdd = 9, > - LLVMSub = 10, > - LLVMFSub = 11, > - LLVMMul = 12, > - LLVMFMul = 13, > - LLVMUDiv = 14, > - LLVMSDiv = 15, > - LLVMFDiv = 16, > - LLVMURem = 17, > - LLVMSRem = 18, > - LLVMFRem = 19, > + LLVMAdd = 9, > + LLVMFAdd = 10, > + LLVMSub = 11, > + LLVMFSub = 12, > + LLVMMul = 13, > + LLVMFMul = 14, > + LLVMUDiv = 15, > + LLVMSDiv = 16, > + LLVMFDiv = 17, > + LLVMURem = 18, > + LLVMSRem = 19, > + LLVMFRem = 20, > > /* Logical Operators */ > - LLVMShl = 20, > - LLVMLShr = 21, > - LLVMAShr = 22, > - LLVMAnd = 23, > - LLVMOr = 24, > - LLVMXor = 25, > + LLVMShl = 21, > + LLVMLShr = 22, > + LLVMAShr = 23, > + LLVMAnd = 24, > + LLVMOr = 25, > + LLVMXor = 26, > > /* Memory Operators */ > - LLVMAlloca = 26, > - LLVMLoad = 27, > - LLVMStore = 28, > - LLVMGetElementPtr = 29, > + LLVMAlloca = 27, > + LLVMLoad = 28, > + LLVMStore = 29, > + LLVMGetElementPtr = 30, > > /* Cast Operators */ > - LLVMTrunc = 30, > - LLVMZExt = 31, > - LLVMSExt = 32, > - LLVMFPToUI = 33, > - LLVMFPToSI = 34, > - LLVMUIToFP = 35, > - LLVMSIToFP = 36, > - LLVMFPTrunc = 37, > - LLVMFPExt = 38, > - LLVMPtrToInt = 39, > - LLVMIntToPtr = 40, > - LLVMBitCast = 41, > + LLVMTrunc = 31, > + LLVMZExt = 32, > + LLVMSExt = 33, > + LLVMFPToUI = 34, > + LLVMFPToSI = 35, > + LLVMUIToFP = 36, > + LLVMSIToFP = 37, > + LLVMFPTrunc = 38, > + LLVMFPExt = 39, > + LLVMPtrToInt = 40, > + LLVMIntToPtr = 41, > + LLVMBitCast = 42, > > /* Other Operators */ > - LLVMICmp = 42, > - LLVMFCmp = 43, > - LLVMPHI = 44, > - LLVMCall = 45, > - LLVMSelect = 46, > + LLVMICmp = 43, > + LLVMFCmp = 44, > + LLVMPHI = 45, > + LLVMCall = 46, > + LLVMSelect = 47, > /* UserOp1 */ > /* UserOp2 */ > - LLVMVAArg = 49, > - LLVMExtractElement = 50, > - LLVMInsertElement = 51, > - LLVMShuffleVector = 52, > - LLVMExtractValue = 53, > - LLVMInsertValue = 54, > + LLVMVAArg = 50, > + LLVMExtractElement = 51, > + LLVMInsertElement = 52, > + LLVMShuffleVector = 53, > + LLVMExtractValue = 54, > + LLVMInsertValue = 55, > + LLVMLandingPad = 56, > > /* Atomic operators */ > - LLVMFence = 55 > + LLVMFence = 57 > } LLVMOpcode; There was just discussion about these values being required to be stable. See r136245 and the review of r136124. If we can't just replace UnwindInst, that might force isa to not use a simple range check. John. From isanbard at gmail.com Wed Jul 27 16:00:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 27 Jul 2011 21:00:28 -0000 Subject: [llvm-commits] [llvm] r136263 - /llvm/trunk/include/llvm-c/Core.h Message-ID: <20110727210028.7D9212A6C12C@llvm.org> Author: void Date: Wed Jul 27 16:00:28 2011 New Revision: 136263 URL: http://llvm.org/viewvc/llvm-project?rev=136263&view=rev Log: Keep enums stable. Append EH stuff to the end. Modified: llvm/trunk/include/llvm-c/Core.h Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136263&r1=136262&r2=136263&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 16:00:28 2011 @@ -126,69 +126,72 @@ LLVMIndirectBr = 4, LLVMInvoke = 5, LLVMUnwind = 6, - LLVMResume = 7, - LLVMUnreachable = 8, + LLVMUnreachable = 7, /* Standard Binary Operators */ - LLVMAdd = 9, - LLVMFAdd = 10, - LLVMSub = 11, - LLVMFSub = 12, - LLVMMul = 13, - LLVMFMul = 14, - LLVMUDiv = 15, - LLVMSDiv = 16, - LLVMFDiv = 17, - LLVMURem = 18, - LLVMSRem = 19, - LLVMFRem = 20, + LLVMAdd = 8, + LLVMFAdd = 9, + LLVMSub = 10, + LLVMFSub = 11, + LLVMMul = 12, + LLVMFMul = 13, + LLVMUDiv = 14, + LLVMSDiv = 15, + LLVMFDiv = 16, + LLVMURem = 17, + LLVMSRem = 18, + LLVMFRem = 19, /* Logical Operators */ - LLVMShl = 21, - LLVMLShr = 22, - LLVMAShr = 23, - LLVMAnd = 24, - LLVMOr = 25, - LLVMXor = 26, + LLVMShl = 20, + LLVMLShr = 21, + LLVMAShr = 22, + LLVMAnd = 23, + LLVMOr = 24, + LLVMXor = 25, /* Memory Operators */ - LLVMAlloca = 27, - LLVMLoad = 28, - LLVMStore = 29, - LLVMGetElementPtr = 30, + LLVMAlloca = 26, + LLVMLoad = 27, + LLVMStore = 28, + LLVMGetElementPtr = 29, /* Cast Operators */ - LLVMTrunc = 31, - LLVMZExt = 32, - LLVMSExt = 33, - LLVMFPToUI = 34, - LLVMFPToSI = 35, - LLVMUIToFP = 36, - LLVMSIToFP = 37, - LLVMFPTrunc = 38, - LLVMFPExt = 39, - LLVMPtrToInt = 40, - LLVMIntToPtr = 41, - LLVMBitCast = 42, + LLVMTrunc = 30, + LLVMZExt = 31, + LLVMSExt = 32, + LLVMFPToUI = 33, + LLVMFPToSI = 34, + LLVMUIToFP = 35, + LLVMSIToFP = 36, + LLVMFPTrunc = 37, + LLVMFPExt = 38, + LLVMPtrToInt = 39, + LLVMIntToPtr = 40, + LLVMBitCast = 41, /* Other Operators */ - LLVMICmp = 43, - LLVMFCmp = 44, - LLVMPHI = 45, - LLVMCall = 46, - LLVMSelect = 47, + LLVMICmp = 42, + LLVMFCmp = 43, + LLVMPHI = 44, + LLVMCall = 45, + LLVMSelect = 46, /* UserOp1 */ /* UserOp2 */ - LLVMVAArg = 50, - LLVMExtractElement = 51, - LLVMInsertElement = 52, - LLVMShuffleVector = 53, - LLVMExtractValue = 54, - LLVMInsertValue = 55, - LLVMLandingPad = 56, + LLVMVAArg = 49, + LLVMExtractElement = 50, + LLVMInsertElement = 51, + LLVMShuffleVector = 52, + LLVMExtractValue = 53, + LLVMInsertValue = 54, /* Atomic operators */ - LLVMFence = 57 + LLVMFence = 55, + + /* Exception Handling Operators */ + LLVMLandingPad = 56, + LLVMResume = 57 + } LLVMOpcode; typedef enum { From isanbard at gmail.com Wed Jul 27 16:02:06 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 27 Jul 2011 14:02:06 -0700 Subject: [llvm-commits] [llvm] r136253 - in /llvm/trunk: docs/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCore/ test/Feature/ In-Reply-To: References: <20110727201805.154E62A6C12C@llvm.org> Message-ID: On Jul 27, 2011, at 1:54 PM, John McCall wrote: > On Jul 27, 2011, at 1:18 PM, Bill Wendling wrote: >> /* Atomic operators */ >> - LLVMFence = 55 >> + LLVMFence = 57 >> } LLVMOpcode; > > There was just discussion about these values being required to be stable. See r136245 and the review of r136124. > > If we can't just replace UnwindInst, that might force isa to not use a simple range check. > Okay. I changed it back. I'll try to remove the UnwindInst soon. It's used in a lot of places, though... -bw From eli.friedman at gmail.com Wed Jul 27 16:05:32 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 14:05:32 -0700 Subject: [llvm-commits] [llvm] r136253 - in /llvm/trunk: docs/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CBackend/ lib Message-ID: On Wed, Jul 27, 2011 at 1:54 PM, John McCall wrote: > On Jul 27, 2011, at 1:18 PM, Bill Wendling wrote: >> Modified: llvm/trunk/include/llvm-c/Core.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=136253&r1=136252&r2=136253&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm-c/Core.h (original) >> +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 15:18:04 2011 >> @@ -126,67 +126,69 @@ >> ? LLVMIndirectBr ? ? = 4, >> ? LLVMInvoke ? ? ? ? = 5, >> ? LLVMUnwind ? ? ? ? = 6, >> - ?LLVMUnreachable ? ?= 7, >> + ?LLVMResume ? ? ? ? = 7, >> + ?LLVMUnreachable ? ?= 8, >> >> ? /* Standard Binary Operators */ >> - ?LLVMAdd ? ? ? ? ? ?= 8, >> - ?LLVMFAdd ? ? ? ? ? = 9, >> - ?LLVMSub ? ? ? ? ? ?= 10, >> - ?LLVMFSub ? ? ? ? ? = 11, >> - ?LLVMMul ? ? ? ? ? ?= 12, >> - ?LLVMFMul ? ? ? ? ? = 13, >> - ?LLVMUDiv ? ? ? ? ? = 14, >> - ?LLVMSDiv ? ? ? ? ? = 15, >> - ?LLVMFDiv ? ? ? ? ? = 16, >> - ?LLVMURem ? ? ? ? ? = 17, >> - ?LLVMSRem ? ? ? ? ? = 18, >> - ?LLVMFRem ? ? ? ? ? = 19, >> + ?LLVMAdd ? ? ? ? ? ?= 9, >> + ?LLVMFAdd ? ? ? ? ? = 10, >> + ?LLVMSub ? ? ? ? ? ?= 11, >> + ?LLVMFSub ? ? ? ? ? = 12, >> + ?LLVMMul ? ? ? ? ? ?= 13, >> + ?LLVMFMul ? ? ? ? ? = 14, >> + ?LLVMUDiv ? ? ? ? ? = 15, >> + ?LLVMSDiv ? ? ? ? ? = 16, >> + ?LLVMFDiv ? ? ? ? ? = 17, >> + ?LLVMURem ? ? ? ? ? = 18, >> + ?LLVMSRem ? ? ? ? ? = 19, >> + ?LLVMFRem ? ? ? ? ? = 20, >> >> ? /* Logical Operators */ >> - ?LLVMShl ? ? ? ? ? ?= 20, >> - ?LLVMLShr ? ? ? ? ? = 21, >> - ?LLVMAShr ? ? ? ? ? = 22, >> - ?LLVMAnd ? ? ? ? ? ?= 23, >> - ?LLVMOr ? ? ? ? ? ? = 24, >> - ?LLVMXor ? ? ? ? ? ?= 25, >> + ?LLVMShl ? ? ? ? ? ?= 21, >> + ?LLVMLShr ? ? ? ? ? = 22, >> + ?LLVMAShr ? ? ? ? ? = 23, >> + ?LLVMAnd ? ? ? ? ? ?= 24, >> + ?LLVMOr ? ? ? ? ? ? = 25, >> + ?LLVMXor ? ? ? ? ? ?= 26, >> >> ? /* Memory Operators */ >> - ?LLVMAlloca ? ? ? ? = 26, >> - ?LLVMLoad ? ? ? ? ? = 27, >> - ?LLVMStore ? ? ? ? ?= 28, >> - ?LLVMGetElementPtr ?= 29, >> + ?LLVMAlloca ? ? ? ? = 27, >> + ?LLVMLoad ? ? ? ? ? = 28, >> + ?LLVMStore ? ? ? ? ?= 29, >> + ?LLVMGetElementPtr ?= 30, >> >> ? /* Cast Operators */ >> - ?LLVMTrunc ? ? ? ? ?= 30, >> - ?LLVMZExt ? ? ? ? ? = 31, >> - ?LLVMSExt ? ? ? ? ? = 32, >> - ?LLVMFPToUI ? ? ? ? = 33, >> - ?LLVMFPToSI ? ? ? ? = 34, >> - ?LLVMUIToFP ? ? ? ? = 35, >> - ?LLVMSIToFP ? ? ? ? = 36, >> - ?LLVMFPTrunc ? ? ? ?= 37, >> - ?LLVMFPExt ? ? ? ? ?= 38, >> - ?LLVMPtrToInt ? ? ? = 39, >> - ?LLVMIntToPtr ? ? ? = 40, >> - ?LLVMBitCast ? ? ? ?= 41, >> + ?LLVMTrunc ? ? ? ? ?= 31, >> + ?LLVMZExt ? ? ? ? ? = 32, >> + ?LLVMSExt ? ? ? ? ? = 33, >> + ?LLVMFPToUI ? ? ? ? = 34, >> + ?LLVMFPToSI ? ? ? ? = 35, >> + ?LLVMUIToFP ? ? ? ? = 36, >> + ?LLVMSIToFP ? ? ? ? = 37, >> + ?LLVMFPTrunc ? ? ? ?= 38, >> + ?LLVMFPExt ? ? ? ? ?= 39, >> + ?LLVMPtrToInt ? ? ? = 40, >> + ?LLVMIntToPtr ? ? ? = 41, >> + ?LLVMBitCast ? ? ? ?= 42, >> >> ? /* Other Operators */ >> - ?LLVMICmp ? ? ? ? ? = 42, >> - ?LLVMFCmp ? ? ? ? ? = 43, >> - ?LLVMPHI ? ? ? ? ? ?= 44, >> - ?LLVMCall ? ? ? ? ? = 45, >> - ?LLVMSelect ? ? ? ? = 46, >> + ?LLVMICmp ? ? ? ? ? = 43, >> + ?LLVMFCmp ? ? ? ? ? = 44, >> + ?LLVMPHI ? ? ? ? ? ?= 45, >> + ?LLVMCall ? ? ? ? ? = 46, >> + ?LLVMSelect ? ? ? ? = 47, >> ? /* UserOp1 */ >> ? /* UserOp2 */ >> - ?LLVMVAArg ? ? ? ? ?= 49, >> - ?LLVMExtractElement = 50, >> - ?LLVMInsertElement ?= 51, >> - ?LLVMShuffleVector ?= 52, >> - ?LLVMExtractValue ? = 53, >> - ?LLVMInsertValue ? ?= 54, >> + ?LLVMVAArg ? ? ? ? ?= 50, >> + ?LLVMExtractElement = 51, >> + ?LLVMInsertElement ?= 52, >> + ?LLVMShuffleVector ?= 53, >> + ?LLVMExtractValue ? = 54, >> + ?LLVMInsertValue ? ?= 55, >> + ?LLVMLandingPad ? ? = 56, >> >> ? /* Atomic operators */ >> - ?LLVMFence ? ? ? ? ?= 55 >> + ?LLVMFence ? ? ? ? ?= 57 >> } LLVMOpcode; > > There was just discussion about these values being required to be stable. ?See r136245 and the review of r136124. > > If we can't just replace UnwindInst, that might force isa to not use a simple range check. These values have to be stable; the ones in Instructions.def, however, don't. -Eli From grosbach at apple.com Wed Jul 27 16:09:26 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 21:09:26 -0000 Subject: [llvm-commits] [llvm] r136264 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s Message-ID: <20110727210926.3600A2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 16:09:25 2011 New Revision: 136264 URL: http://llvm.org/viewvc/llvm-project?rev=136264&view=rev Log: ARM parsing and encoding of SBFX and UBFX. Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/diagnostics.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Jul 27 16:09:25 2011 @@ -215,8 +215,6 @@ const { return 0; } unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) - const { return 0; } unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Jul 27 16:09:25 2011 @@ -2024,7 +2024,8 @@ Srl_imm)) { assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); - unsigned Width = CountTrailingOnes_32(And_imm); + // Note: The width operand is encoded as width-1. + unsigned Width = CountTrailingOnes_32(And_imm) - 1; unsigned LSB = Srl_imm; SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Ops[] = { N->getOperand(0).getOperand(0), @@ -2044,7 +2045,8 @@ unsigned Srl_imm = 0; if (isInt32Immediate(N->getOperand(1), Srl_imm)) { assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); - unsigned Width = 32 - Srl_imm; + // Note: The width operand is encoded as width-1. + unsigned Width = 32 - Srl_imm - 1; int LSB = Srl_imm - Shl_imm; if (LSB < 0) return NULL; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 16:09:25 2011 @@ -513,14 +513,6 @@ let ParserMatchClass = Imm0_31AsmOperand; } -/// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'. -def imm0_31_m1 : Operand, ImmLeaf= 0 && Imm < 32; -}]> { - let EncoderMethod = "getImmMinusOneOpValue"; - let DecoderMethod = "DecodeImmMinusOneOperand"; -} - // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference // a relocatable expression. // @@ -2423,7 +2415,7 @@ def SBFX : I<(outs GPR:$Rd), - (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), + (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { @@ -2440,7 +2432,7 @@ } def UBFX : I<(outs GPR:$Rd), - (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), + (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 27 16:09:25 2011 @@ -2024,7 +2024,7 @@ } def t2SBFX: T2TwoRegBitFI< - (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb), + (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; @@ -2033,7 +2033,7 @@ } def t2UBFX: T2TwoRegBitFI< - (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb), + (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 16:09:25 2011 @@ -2605,6 +2605,15 @@ "source operands must be sequential"); return false; } + case ARM::SBFX: + case ARM::UBFX: { + // width must be in range [1, 32-lsb] + unsigned lsb = Inst.getOperand(2).getImm(); + unsigned widthm1 = Inst.getOperand(3).getImm(); + if (widthm1 >= 32 - lsb) + return Error(Operands[5]->getStartLoc(), + "bitfield width must be in range [1,32-lsb]"); + } } return false; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 27 16:09:25 2011 @@ -1026,7 +1026,7 @@ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7))); - MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1)); + MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16))); OpIdx += 3; return true; } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Jul 27 16:09:25 2011 @@ -1698,7 +1698,7 @@ assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX) && "Unexpected opcode"); MI.addOperand(MCOperand::CreateImm(getLsb(insn))); - MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1)); + MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn))); ++OpIdx; } Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Jul 27 16:09:25 2011 @@ -259,11 +259,6 @@ unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; - unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { - return MI.getOperand(Op).getImm() - 1; - } - unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { return 64 - MI.getOperand(Op).getImm(); Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 16:09:25 2011 @@ -1309,6 +1309,16 @@ @------------------------------------------------------------------------------ +@ SBFX + at ------------------------------------------------------------------------------ + sbfx r4, r5, #16, #1 + sbfxgt r4, r5, #16, #16 + +@ CHECK: sbfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xa0,0xe7] +@ CHECK: sbfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xaf,0xc7] + + + at ------------------------------------------------------------------------------ @ SEL @------------------------------------------------------------------------------ sel r9, r2, r1 @@ -2001,3 +2011,11 @@ @ CHECK: uasxeq r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0x06] + at ------------------------------------------------------------------------------ +@ UBFX + at ------------------------------------------------------------------------------ + ubfx r4, r5, #16, #1 + ubfxgt r4, r5, #16, #16 + +@ CHECK: ubfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xe0,0xe7] +@ CHECK: ubfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xef,0xc7] Modified: llvm/trunk/test/MC/ARM/diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=136264&r1=136263&r2=136264&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/diagnostics.s Wed Jul 27 16:09:25 2011 @@ -272,3 +272,14 @@ @ CHECK-ERRORS: error: rotate operator 'ror' expected @ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24 @ CHECK-ERRORS: ^ + + @ Out of range width for SBFX/UBFX + sbfx r4, r5, #31, #2 + ubfxgt r4, r5, #16, #17 + +@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb] +@ CHECK-ERRORS: sbfx r4, r5, #31, #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb] +@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17 +@ CHECK-ERRORS: ^ From grosbach at apple.com Wed Jul 27 16:20:46 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 21:20:46 -0000 Subject: [llvm-commits] [llvm] r136266 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727212046.150032A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 16:20:45 2011 New Revision: 136266 URL: http://llvm.org/viewvc/llvm-project?rev=136266&view=rev Log: ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136266&r1=136265&r2=136266&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 16:20:45 2011 @@ -2019,3 +2019,29 @@ @ CHECK: ubfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xe0,0xe7] @ CHECK: ubfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xef,0xc7] + + + at ------------------------------------------------------------------------------ +@ UHADD16/UHADD8 + at ------------------------------------------------------------------------------ + uhadd16 r4, r8, r2 + uhadd16gt r4, r8, r2 + uhadd8 r4, r8, r2 + uhadd8gt r4, r8, r2 + +@ CHECK: uhadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x78,0xe6] +@ CHECK: uhadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x78,0xc6] +@ CHECK: uhadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x78,0xe6] +@ CHECK: uhadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x78,0xc6] + + + at ------------------------------------------------------------------------------ +@ UHASX + at ------------------------------------------------------------------------------ + uhasx r4, r8, r2 + uhasxgt r4, r8, r2 + +@ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6] +@ CHECK: uhasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xc6] + + From grosbach at apple.com Wed Jul 27 16:21:59 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 21:21:59 -0000 Subject: [llvm-commits] [llvm] r136267 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727212159.7D6D72A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 16:21:59 2011 New Revision: 136267 URL: http://llvm.org/viewvc/llvm-project?rev=136267&view=rev Log: ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136267&r1=136266&r2=136267&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 16:21:59 2011 @@ -2045,3 +2045,15 @@ @ CHECK: uhasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xc6] + at ------------------------------------------------------------------------------ +@ UHSUB16/UHSUB8 + at ------------------------------------------------------------------------------ + uhsub16 r4, r8, r2 + uhsub16gt r4, r8, r2 + uhsub8 r4, r8, r2 + uhsub8gt r4, r8, r2 + +@ CHECK: uhsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x78,0xe6] +@ CHECK: uhsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x78,0xc6] +@ CHECK: uhsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xe6] +@ CHECK: uhsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xc6] From isanbard at gmail.com Wed Jul 27 16:44:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 27 Jul 2011 21:44:28 -0000 Subject: [llvm-commits] [llvm] r136269 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110727214428.913592A6C12C@llvm.org> Author: void Date: Wed Jul 27 16:44:28 2011 New Revision: 136269 URL: http://llvm.org/viewvc/llvm-project?rev=136269&view=rev Log: Refuse to inline two functions which use different personality functions. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=136269&r1=136268&r2=136269&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Wed Jul 27 16:44:28 2011 @@ -829,6 +829,40 @@ return false; } + // Find the personality function used by the landing pads of the caller. If it + // exists, then check to see that it matches the personality function used in + // the callee. + for (Function::const_iterator + I = Caller->begin(), E = Caller->end(); I != E; ++I) + if (const InvokeInst *II = dyn_cast(I->getTerminator())) { + const BasicBlock *BB = II->getUnwindDest(); + // FIXME: This 'isa' here should become go away once the new EH system is + // in place. + if (!isa(BB->getFirstNonPHI())) + continue; + const LandingPadInst *LP = cast(BB->getFirstNonPHI()); + const Value *CallerPersFn = LP->getPersonalityFn(); + + // If the personality functions match, then we can perform the + // inlining. Otherwise, we can't inline. + // TODO: This isn't 100% true. Some personality functions are proper + // supersets of others and can be used in place of the other. + for (Function::const_iterator + I = CalledFunc->begin(), E = CalledFunc->end(); I != E; ++I) + if (const InvokeInst *II = dyn_cast(I->getTerminator())) { + const BasicBlock *BB = II->getUnwindDest(); + // FIXME: This 'if/dyn_cast' here should become a normal 'cast' once + // the new EH system is in place. + if (const LandingPadInst *LP = + dyn_cast(BB->getFirstNonPHI())) + if (CallerPersFn != LP->getPersonalityFn()) + return false; + break; + } + + break; + } + // Get an iterator to the last basic block in the function, which will have // the new function inlined after it. // From grosbach at apple.com Wed Jul 27 16:53:43 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 21:53:43 -0000 Subject: [llvm-commits] [llvm] r136272 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727215343.1A17D2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 16:53:42 2011 New Revision: 136272 URL: http://llvm.org/viewvc/llvm-project?rev=136272&view=rev Log: ARM assembly parsing and encoding tests for UMAAL. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136272&r1=136271&r2=136272&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 16:53:42 2011 @@ -2057,3 +2057,14 @@ @ CHECK: uhsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x78,0xc6] @ CHECK: uhsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xe6] @ CHECK: uhsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xc6] + + + at ------------------------------------------------------------------------------ +@ UMAAL + at ------------------------------------------------------------------------------ + umaal r3, r4, r5, r6 + umaallt r3, r4, r5, r6 + +@ CHECK: umaal r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xe0] +@ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xb0] + From grosbach at apple.com Wed Jul 27 16:58:12 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 21:58:12 -0000 Subject: [llvm-commits] [llvm] r136274 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727215812.0C7902A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 16:58:11 2011 New Revision: 136274 URL: http://llvm.org/viewvc/llvm-project?rev=136274&view=rev Log: ARM assembly parsing and encoding for UMLAL. Fix parsing of the 's' suffix for the mnemonic. Add tests. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136274&r1=136273&r2=136274&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 16:58:11 2011 @@ -2359,7 +2359,8 @@ // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && - Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls") { + Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && + Mnemonic != "umlals") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136274&r1=136273&r2=136274&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 16:58:11 2011 @@ -2068,3 +2068,16 @@ @ CHECK: umaal r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xe0] @ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xb0] + + at ------------------------------------------------------------------------------ +@ UMLAL + at ------------------------------------------------------------------------------ + umlal r2, r4, r6, r8 + umlalgt r6, r1, r2, r6 + umlals r2, r9, r2, r3 + umlalseq r3, r5, r1, r2 + +@ CHECK: umlal r2, r4, r6, r8 @ encoding: [0x96,0x28,0xa4,0xe0] +@ CHECK: umlalgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0xa1,0xc0] +@ CHECK: umlals r2, r9, r2, r3 @ encoding: [0x92,0x23,0xb9,0xe0] +@ CHECK: umlalseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0xb5,0x00] From dpatel at apple.com Wed Jul 27 17:00:01 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 27 Jul 2011 22:00:01 -0000 Subject: [llvm-commits] [llvm] r136275 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110727220001.729362A6C12C@llvm.org> Author: dpatel Date: Wed Jul 27 17:00:01 2011 New Revision: 136275 URL: http://llvm.org/viewvc/llvm-project?rev=136275&view=rev Log: Remove outdated FIXME comment. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=136275&r1=136274&r2=136275&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jul 27 17:00:01 2011 @@ -722,7 +722,6 @@ if (DVI != DbgVariableToDbgInstMap.end()) { const MachineInstr *DVInsn = DVI->second; bool updated = false; - // FIXME : Handle getNumOperands != 3 if (DVInsn->getNumOperands() == 3) { if (DVInsn->getOperand(0).isReg()) { const MachineOperand RegOp = DVInsn->getOperand(0); From grosbach at apple.com Wed Jul 27 17:01:42 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:01:42 -0000 Subject: [llvm-commits] [llvm] r136277 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727220142.81AFC2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:01:42 2011 New Revision: 136277 URL: http://llvm.org/viewvc/llvm-project?rev=136277&view=rev Log: ARM assembly parsing and encoding for UMULL. Fix parsing of the 's' suffix for the mnemonic. Add tests. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136277&r1=136276&r2=136277&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 17:01:42 2011 @@ -2360,7 +2360,7 @@ // predicated but do have a carry-set and so weren't caught above. if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && - Mnemonic != "umlals") { + Mnemonic != "umlals" && Mnemonic != "umulls") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136277&r1=136276&r2=136277&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:01:42 2011 @@ -2081,3 +2081,17 @@ @ CHECK: umlalgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0xa1,0xc0] @ CHECK: umlals r2, r9, r2, r3 @ encoding: [0x92,0x23,0xb9,0xe0] @ CHECK: umlalseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0xb5,0x00] + + + at ------------------------------------------------------------------------------ +@ UMULL + at ------------------------------------------------------------------------------ + umull r2, r4, r6, r8 + umullgt r6, r1, r2, r6 + umulls r2, r9, r2, r3 + umullseq r3, r5, r1, r2 + +@ CHECK: umull r2, r4, r6, r8 @ encoding: [0x96,0x28,0x84,0xe0] +@ CHECK: umullgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0x81,0xc0] +@ CHECK: umulls r2, r9, r2, r3 @ encoding: [0x92,0x23,0x99,0xe0] +@ CHECK: umullseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0x95,0x00] From jstaszak at apple.com Wed Jul 27 17:05:51 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 27 Jul 2011 22:05:51 -0000 Subject: [llvm-commits] [llvm] r136278 - in /llvm/trunk: include/llvm/Analysis/BlockFrequencyImpl.h include/llvm/Analysis/BlockFrequencyInfo.h include/llvm/CodeGen/MachineBlockFrequencyInfo.h lib/Analysis/BlockFrequencyInfo.cpp lib/CodeGen/MachineBlockFrequencyInfo.cpp Message-ID: <20110727220551.D60922A6C12C@llvm.org> Author: kuba Date: Wed Jul 27 17:05:51 2011 New Revision: 136278 URL: http://llvm.org/viewvc/llvm-project?rev=136278&view=rev Log: Use BlockFrequency instead of uint32_t in BlockFrequencyInfo. Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=136278&r1=136277&r2=136278&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Wed Jul 27 17:05:51 2011 @@ -19,6 +19,7 @@ #include "llvm/ADT/PostOrderIterator.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Support/BlockFrequency.h" #include "llvm/Support/BranchProbability.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -40,7 +41,7 @@ template class BlockFrequencyImpl { - DenseMap Freqs; + DenseMap Freqs; BlockProbInfoT *BPI; @@ -64,26 +65,21 @@ return ss.str(); } - void setBlockFreq(BlockT *BB, uint32_t Freq) { + void setBlockFreq(BlockT *BB, BlockFrequency Freq) { Freqs[BB] = Freq; DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") = " << Freq << "\n"); } /// getEdgeFreq - Return edge frequency based on SRC frequency and Src -> Dst /// edge probability. - uint32_t getEdgeFreq(BlockT *Src, BlockT *Dst) const { + BlockFrequency getEdgeFreq(BlockT *Src, BlockT *Dst) const { BranchProbability Prob = BPI->getEdgeProbability(Src, Dst); - uint64_t N = Prob.getNumerator(); - uint64_t D = Prob.getDenominator(); - uint64_t Res = (N * getBlockFreq(Src)) / D; - - assert(Res <= UINT32_MAX); - return (uint32_t) Res; + return getBlockFreq(Src) * Prob; } /// incBlockFreq - Increase BB block frequency by FREQ. /// - void incBlockFreq(BlockT *BB, uint32_t Freq) { + void incBlockFreq(BlockT *BB, BlockFrequency Freq) { Freqs[BB] += Freq; DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") += " << Freq << " --> " << Freqs[BB] << "\n"); @@ -95,13 +91,13 @@ uint64_t N = Prob.getNumerator(); assert(N && "Illegal division by zero!"); uint64_t D = Prob.getDenominator(); - uint64_t Freq = (Freqs[BB] * D) / N; + uint64_t Freq = (Freqs[BB].getFrequency() * D) / N; // Should we assert it? if (Freq > UINT32_MAX) Freq = UINT32_MAX; - Freqs[BB] = (uint32_t) Freq; + Freqs[BB] = BlockFrequency(Freq); DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") /= (" << Prob << ") --> " << Freqs[BB] << "\n"); } @@ -136,15 +132,6 @@ } - /// Return a probability of getting to the DST block through SRC->DST edge. - /// - BranchProbability getBackEdgeProbability(BlockT *Src, BlockT *Dst) const { - uint32_t N = getEdgeFreq(Src, Dst); - uint32_t D = getBlockFreq(Dst); - - return BranchProbability(N, D); - } - /// isReachable - Returns if BB block is reachable from the entry. /// bool isReachable(BlockT *BB) { @@ -252,9 +239,9 @@ BlockT *Pred = *PI; assert(Pred); if (isReachable(Pred) && isBackedge(Pred, Head)) { - BranchProbability Prob = getBackEdgeProbability(Pred, Head); - uint64_t N = Prob.getNumerator(); - uint64_t D = Prob.getDenominator(); + uint64_t N = getEdgeFreq(Pred, Head).getFrequency(); + uint64_t D = getBlockFreq(Head).getFrequency(); + assert(N <= 1024 && "Backedge frequency must be <= 1024!"); uint64_t Res = (N * START_FREQ) / D; assert(Res <= UINT32_MAX); @@ -315,8 +302,8 @@ public: /// getBlockFreq - Return block frequency. Return 0 if we don't have it. - uint32_t getBlockFreq(BlockT *BB) const { - typename DenseMap::const_iterator I = Freqs.find(BB); + BlockFrequency getBlockFreq(BlockT *BB) const { + typename DenseMap::const_iterator I = Freqs.find(BB); if (I != Freqs.end()) return I->second; return 0; Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h?rev=136278&r1=136277&r2=136278&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h Wed Jul 27 17:05:51 2011 @@ -15,6 +15,7 @@ #define LLVM_ANALYSIS_BLOCKFREQUENCYINFO_H #include "llvm/Pass.h" +#include "llvm/Support/BlockFrequency.h" #include namespace llvm { @@ -45,7 +46,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - uint32_t getBlockFreq(BasicBlock *BB); + BlockFrequency getBlockFreq(BasicBlock *BB); }; } Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?rev=136278&r1=136277&r2=136278&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Wed Jul 27 17:05:51 2011 @@ -15,6 +15,7 @@ #define LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/BlockFrequency.h" #include namespace llvm { @@ -45,7 +46,7 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// - uint32_t getBlockFreq(MachineBasicBlock *MBB); + BlockFrequency getBlockFreq(MachineBasicBlock *MBB); }; } Modified: llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp?rev=136278&r1=136277&r2=136278&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp Wed Jul 27 17:05:51 2011 @@ -54,6 +54,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -uint32_t BlockFrequencyInfo::getBlockFreq(BasicBlock *BB) { +BlockFrequency BlockFrequencyInfo::getBlockFreq(BasicBlock *BB) { return BFI->getBlockFreq(BB); } Modified: llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp?rev=136278&r1=136277&r2=136278&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp Wed Jul 27 17:05:51 2011 @@ -55,6 +55,6 @@ /// that we should not rely on the value itself, but only on the comparison to /// the other block frequencies. We do this to avoid using of floating points. /// -uint32_t MachineBlockFrequencyInfo::getBlockFreq(MachineBasicBlock *MBB) { +BlockFrequency MachineBlockFrequencyInfo::getBlockFreq(MachineBasicBlock *MBB) { return MBFI->getBlockFreq(MBB); } From grosbach at apple.com Wed Jul 27 17:08:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:08:14 -0000 Subject: [llvm-commits] [llvm] r136279 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727220814.97CB62A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:08:14 2011 New Revision: 136279 URL: http://llvm.org/viewvc/llvm-project?rev=136279&view=rev Log: ARM assembly parsing and encoding tests for UQADD16 and UQADD8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136279&r1=136278&r2=136279&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:08:14 2011 @@ -2095,3 +2095,18 @@ @ CHECK: umullgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0x81,0xc0] @ CHECK: umulls r2, r9, r2, r3 @ encoding: [0x92,0x23,0x99,0xe0] @ CHECK: umullseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0x95,0x00] + + + at ------------------------------------------------------------------------------ +@ UQADD16/UQADD8 + at ------------------------------------------------------------------------------ + uqadd16 r1, r2, r3 + uqadd16gt r4, r7, r9 + uqadd8 r3, r4, r8 + uqadd8le r8, r1, r2 + + +@ CHECK: uqadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x62,0xe6] +@ CHECK: uqadd16gt r4, r7, r9 @ encoding: [0x19,0x4f,0x67,0xc6] +@ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6] +@ CHECK: uqadd8le r8, r1, r2 @ encoding: [0x92,0x8f,0x61,0xd6] From grosbach at apple.com Wed Jul 27 17:09:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:09:30 -0000 Subject: [llvm-commits] [llvm] r136280 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727220930.626522A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:09:30 2011 New Revision: 136280 URL: http://llvm.org/viewvc/llvm-project?rev=136280&view=rev Log: ARM assembly parsing and encoding tests for UQASX and UQSAX. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136280&r1=136279&r2=136280&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:09:30 2011 @@ -2110,3 +2110,24 @@ @ CHECK: uqadd16gt r4, r7, r9 @ encoding: [0x19,0x4f,0x67,0xc6] @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6] @ CHECK: uqadd8le r8, r1, r2 @ encoding: [0x92,0x8f,0x61,0xd6] + + + at ------------------------------------------------------------------------------ +@ UQASX + at ------------------------------------------------------------------------------ + uqasx r2, r4, r1 + uqasxhi r5, r2, r9 + +@ CHECK: uqasx r2, r4, r1 @ encoding: [0x31,0x2f,0x64,0xe6] +@ CHECK: uqasxhi r5, r2, r9 @ encoding: [0x39,0x5f,0x62,0x86] + + + at ------------------------------------------------------------------------------ +@ UQSAX + at ------------------------------------------------------------------------------ + uqsax r1, r3, r7 + uqsaxal r3, r6, r2 + +@ CHECK: uqsax r1, r3, r7 @ encoding: [0x57,0x1f,0x63,0xe6] +@ CHECK: uqsax r3, r6, r2 @ encoding: [0x52,0x3f,0x66,0xe6] + From grosbach at apple.com Wed Jul 27 17:11:41 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:11:41 -0000 Subject: [llvm-commits] [llvm] r136281 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727221141.88FBB2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:11:41 2011 New Revision: 136281 URL: http://llvm.org/viewvc/llvm-project?rev=136281&view=rev Log: Fix comment copy/paste-o. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136281&r1=136280&r2=136281&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:11:41 2011 @@ -1078,7 +1078,7 @@ @------------------------------------------------------------------------------ -@ QADD/QADD16/QADD8 +@ QSUB/QSUB16/QSUB8 @------------------------------------------------------------------------------ qsub r1, r2, r3 qsubne r1, r2, r3 From grosbach at apple.com Wed Jul 27 17:13:08 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:13:08 -0000 Subject: [llvm-commits] [llvm] r136282 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727221308.A929E2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:13:08 2011 New Revision: 136282 URL: http://llvm.org/viewvc/llvm-project?rev=136282&view=rev Log: ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136282&r1=136281&r2=136282&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:13:08 2011 @@ -2131,3 +2131,16 @@ @ CHECK: uqsax r1, r3, r7 @ encoding: [0x57,0x1f,0x63,0xe6] @ CHECK: uqsax r3, r6, r2 @ encoding: [0x52,0x3f,0x66,0xe6] + + at ------------------------------------------------------------------------------ +@ UQSUB16/UQSUB8 + at ------------------------------------------------------------------------------ + uqsub16 r1, r5, r3 + uqsub16gt r3, r2, r5 + uqsub8 r2, r1, r4 + uqsub8le r4, r6, r9 + +@ CHECK: uqsub16 r1, r5, r3 @ encoding: [0x73,0x1f,0x65,0xe6] +@ CHECK: uqsub16gt r3, r2, r5 @ encoding: [0x75,0x3f,0x62,0xc6] +@ CHECK: uqsub8 r2, r1, r4 @ encoding: [0xf4,0x2f,0x61,0xe6] +@ CHECK: uqsub8le r4, r6, r9 @ encoding: [0xf9,0x4f,0x66,0xd6] From eli.friedman at gmail.com Wed Jul 27 17:21:52 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 22:21:52 -0000 Subject: [llvm-commits] [llvm] r136283 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ Message-ID: <20110727222153.2FEED2A6C12C@llvm.org> Author: efriedma Date: Wed Jul 27 17:21:52 2011 New Revision: 136283 URL: http://llvm.org/viewvc/llvm-project?rev=136283&view=rev Log: Code generation for 'fence' instruction. Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Wed Jul 27 17:21:52 2011 @@ -592,6 +592,11 @@ // and produces an output chain. MEMBARRIER, + // OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) + // This corresponds to the fence instruction. It takes an input chain, and + // two integer constants: an AtomicOrdering and a SynchronizationScope. + ATOMIC_FENCE, + // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) // this corresponds to the atomic.lcs intrinsic. // cmp is compared to *ptr, and if equal, swap is stored in *ptr. Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Wed Jul 27 17:21:52 2011 @@ -205,6 +205,9 @@ SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, SDTCisInt<0> ]>; +def SDTAtomicFence : SDTypeProfile<0, 2, [ + SDTCisSameAs<0,1>, SDTCisPtrTy<0> +]>; def SDTAtomic3 : SDTypeProfile<1, 3, [ SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> ]>; @@ -397,6 +400,9 @@ def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, [SDNPHasChain, SDNPSideEffect]>; +def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, + [SDNPHasChain, SDNPSideEffect]>; + def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jul 27 17:21:52 2011 @@ -2955,8 +2955,10 @@ Results.push_back(DAG.getConstant(0, MVT::i32)); Results.push_back(Node->getOperand(0)); break; + case ISD::ATOMIC_FENCE: case ISD::MEMBARRIER: { // If the target didn't lower this, lower it to '__sync_synchronize()' call + // FIXME: handle "fence singlethread" more efficiently. TargetLowering::ArgListTy Args; std::pair CallResult = TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul 27 17:21:52 2011 @@ -5769,6 +5769,7 @@ #endif case ISD::PREFETCH: return "Prefetch"; case ISD::MEMBARRIER: return "MemBarrier"; + case ISD::ATOMIC_FENCE: return "AtomicFence"; case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; case ISD::ATOMIC_SWAP: return "AtomicSwap"; case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 27 17:21:52 2011 @@ -3221,7 +3221,12 @@ } void SelectionDAGBuilder::visitFence(const FenceInst &I) { - llvm_unreachable("Not implemented yet"); + DebugLoc dl = getCurDebugLoc(); + SDValue Ops[3]; + Ops[0] = getRoot(); + Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); + Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); + DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); } /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -601,9 +601,11 @@ // membarrier needs custom lowering; the rest are legal and handled // normally. setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); } else { // Set them all for expansion, which will force libcalls. setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); @@ -2277,6 +2279,33 @@ DAG.getConstant(DMBOpt, MVT::i32)); } + +static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, + const ARMSubtarget *Subtarget) { + // FIXME: handle "fence singlethread" more efficiently. + DebugLoc dl = Op.getDebugLoc(); + if (!Subtarget->hasDataBarrier()) { + // Some ARMv6 cpus can support data barriers with an mcr instruction. + // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get + // here. + assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && + "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); + return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), + DAG.getConstant(0, MVT::i32)); + } + + AtomicOrdering FenceOrdering = static_cast( + cast(Op.getOperand(1))->getZExtValue()); + + ARM_MB::MemBOpt DMBOpt; + if (FenceOrdering == Release) + DMBOpt = ARM_MB::ISHST; + else + DMBOpt = ARM_MB::ISH; + return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), + DAG.getConstant(DMBOpt, MVT::i32)); +} + static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) { // ARM pre v5TE and Thumb1 does not have preload instructions. @@ -4834,6 +4863,7 @@ case ISD::BR_JT: return LowerBR_JT(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); + case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Wed Jul 27 17:21:52 2011 @@ -607,6 +607,8 @@ def : Pat<(membarrier (i64 imm), (i64 imm), (i64 imm), (i64 imm), (i64 imm)), (MB)>; +def : Pat<(atomic_fence (imm), (imm)), (MB)>; + //Basic Floating point ops //Floats Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -99,6 +99,7 @@ // Blackfin has no intrinsics for these particular operations. setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -174,6 +174,7 @@ // SPU has no intrinsics for these particular operations: setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); // SPU has no division/remainder instructions setOperationAction(ISD::SREM, MVT::i8, Expand); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Wed Jul 27 17:21:52 2011 @@ -877,6 +877,9 @@ // Peepholes def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>; +// Atomic fence +def : Pat<(atomic_fence (imm), (imm)), (MEMBARRIER)>; + //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -160,7 +160,9 @@ // Use the default for now setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); if (Subtarget->isSingleFloat()) setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); @@ -529,6 +531,7 @@ case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); + case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); } return SDValue(); } @@ -1536,6 +1539,16 @@ DAG.getConstant(SType, MVT::i32)); } +SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, + SelectionDAG& DAG) const { + // FIXME: Need pseudo-fence for 'singlethread' fences + // FIXME: Set SType for weaker fences where supported/appropriate. + unsigned SType = 0; + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), + DAG.getConstant(SType, MVT::i32)); +} + //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Jul 27 17:21:52 2011 @@ -131,6 +131,7 @@ SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; + SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; virtual SDValue LowerFormalArguments(SDValue Chain, Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Jul 27 17:21:52 2011 @@ -1472,5 +1472,7 @@ (i32 imm /*device*/)), (SYNC)>; +def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; + include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -748,8 +748,10 @@ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); - // SPARC has no intrinsics for these particular operations. + // FIXME: There are instructions available for ATOMIC_FENCE + // on SparcV8 and later. setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 27 17:21:52 2011 @@ -449,8 +449,8 @@ if (Subtarget->hasXMM()) setOperationAction(ISD::PREFETCH , MVT::Other, Legal); - // We may not have a libcall for MEMBARRIER so we should lower this. setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); + setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); // On X86 and X86-64, atomic operations are lowered to locked instructions. // Locked instructions, in turn, have implicit fence semantics (all memory @@ -9407,6 +9407,45 @@ return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); } +SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, + SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + AtomicOrdering FenceOrdering = static_cast( + cast(Op.getOperand(1))->getZExtValue()); + SynchronizationScope FenceScope = static_cast( + cast(Op.getOperand(2))->getZExtValue()); + + // The only fence that needs an instruction is a sequentially-consistent + // cross-thread fence. + if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { + // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for + // no-sse2). There isn't any reason to disable it if the target processor + // supports it. + if (Subtarget->hasSSE2() || Subtarget->is64Bit()) + return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); + + SDValue Chain = Op.getOperand(0); + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue Ops[] = { + DAG.getRegister(X86::ESP, MVT::i32), // Base + DAG.getTargetConstant(1, MVT::i8), // Scale + DAG.getRegister(0, MVT::i32), // Index + DAG.getTargetConstant(0, MVT::i32), // Disp + DAG.getRegister(0, MVT::i32), // Segment. + Zero, + Chain + }; + SDNode *Res = + DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, + array_lengthof(Ops)); + return SDValue(Res, 0); + } + + // MEMBARRIER is a compiler barrier; it codegens to a no-op. + return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); +} + + SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { EVT T = Op.getValueType(); DebugLoc DL = Op.getDebugLoc(); @@ -9526,6 +9565,7 @@ default: llvm_unreachable("Should not custom lower this!"); case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); + case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); @@ -9849,6 +9889,7 @@ case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; + case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=136283&r1=136282&r2=136283&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jul 27 17:21:52 2011 @@ -829,6 +829,7 @@ SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; // Utility functions to help LowerVECTOR_SHUFFLE From grosbach at apple.com Wed Jul 27 17:23:02 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:23:02 -0000 Subject: [llvm-commits] [llvm] r136284 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727222303.06A162A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:23:02 2011 New Revision: 136284 URL: http://llvm.org/viewvc/llvm-project?rev=136284&view=rev Log: ARM assembly parsing and encoding tests for USAD8 and USADA8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136284&r1=136283&r2=136284&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:23:02 2011 @@ -2144,3 +2144,17 @@ @ CHECK: uqsub16gt r3, r2, r5 @ encoding: [0x75,0x3f,0x62,0xc6] @ CHECK: uqsub8 r2, r1, r4 @ encoding: [0xf4,0x2f,0x61,0xe6] @ CHECK: uqsub8le r4, r6, r9 @ encoding: [0xf9,0x4f,0x66,0xd6] + + + at ------------------------------------------------------------------------------ +@ USADA8/USAD8 + at ------------------------------------------------------------------------------ + usad8 r2, r1, r4 + usad8le r4, r6, r9 + usada8 r1, r5, r3, r7 + usada8gt r3, r2, r5, r1 + +@ CHECK: usad8 r2, r1, r4 @ encoding: [0x11,0xf4,0x82,0xe7] +@ CHECK: usad8le r4, r6, r9 @ encoding: [0x16,0xf9,0x84,0xd7] +@ CHECK: usada8 r1, r5, r3, r7 @ encoding: [0x15,0x73,0x81,0xe7] +@ CHECK: usada8gt r3, r2, r5, r1 @ encoding: [0x12,0x15,0x83,0xc7] From grosbach at apple.com Wed Jul 27 17:34:17 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:34:17 -0000 Subject: [llvm-commits] [llvm] r136285 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727223417.410202A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:34:17 2011 New Revision: 136285 URL: http://llvm.org/viewvc/llvm-project?rev=136285&view=rev Log: ARM assembly parsing and encoding support for USAT and USAT16. Use range checked immediate operands for instructions. Add tests. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136285&r1=136284&r2=136285&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 17:34:17 2011 @@ -2785,7 +2785,7 @@ let Inst{3-0} = Rn; } -def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh), +def USAT : AI<(outs GPR:$Rd), (ins imm0_31:$sat_imm, GPR:$Rn, shift_imm:$sh), SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { bits<4> Rd; bits<5> sat_imm; @@ -2800,7 +2800,7 @@ let Inst{3-0} = Rn; } -def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm, +def USAT16 : AI<(outs GPR:$Rd), (ins imm0_15:$sat_imm, GPR:$a), SatFrm, NoItinerary, "usat16", "\t$Rd, $sat_imm, $a", [/* For disassembly only; pattern left blank */]> { bits<4> Rd; @@ -4364,9 +4364,11 @@ (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, Requires<[IsARM]>; -// SSAT optional shift operand. +// SSAT/USAT optional shift operand. def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>; +def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn", + (USAT GPR:$Rd, imm0_31:$sat_imm, GPR:$Rn, 0, pred:$p)>; // Extend instruction optional rotate operand. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136285&r1=136284&r2=136285&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:34:17 2011 @@ -2158,3 +2158,29 @@ @ CHECK: usad8le r4, r6, r9 @ encoding: [0x16,0xf9,0x84,0xd7] @ CHECK: usada8 r1, r5, r3, r7 @ encoding: [0x15,0x73,0x81,0xe7] @ CHECK: usada8gt r3, r2, r5, r1 @ encoding: [0x12,0x15,0x83,0xc7] + + + at ------------------------------------------------------------------------------ +@ USAT + at ------------------------------------------------------------------------------ + + usat r8, #1, r10 + usat r8, #4, r10, lsl #0 + usat r8, #5, r10, lsl #31 + usat r8, #31, r10, asr #32 + usat r8, #16, r10, asr #1 + +@ CHECK: usat r8, #1, r10 @ encoding: [0x1a,0x80,0xe1,0xe6] +@ CHECK: usat r8, #4, r10 @ encoding: [0x1a,0x80,0xe4,0xe6] +@ CHECK: usat r8, #5, r10, lsl #31 @ encoding: [0x9a,0x8f,0xe5,0xe6] +@ CHECK: usat r8, #31, r10, asr #32 @ encoding: [0x5a,0x80,0xff,0xe6] +@ CHECK: usat r8, #16, r10, asr #1 @ encoding: [0xda,0x80,0xf0,0xe6] + + at ------------------------------------------------------------------------------ +@ USAT16 + at ------------------------------------------------------------------------------ + usat16 r2, #2, r7 + usat16 r3, #15, r5 + +@ CHECK: usat16 r2, #2, r7 @ encoding: [0x32,0x2f,0xe2,0xe6] +@ CHECK: usat16 r3, #15, r5 @ encoding: [0x33,0x3f,0xef,0xe6] From grosbach at apple.com Wed Jul 27 17:35:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 22:35:07 -0000 Subject: [llvm-commits] [llvm] r136286 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727223507.2453F2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 17:35:06 2011 New Revision: 136286 URL: http://llvm.org/viewvc/llvm-project?rev=136286&view=rev Log: Clean up tabs. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136286&r1=136285&r2=136286&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:35:06 2011 @@ -1334,8 +1334,8 @@ setend be setend le - sel r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0xe6] - selne r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0x16] + sel r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0xe6] + selne r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0x16] @------------------------------------------------------------------------------ @@ -1644,11 +1644,11 @@ @------------------------------------------------------------------------------ @ SSAT @------------------------------------------------------------------------------ - ssat r8, #1, r10 - ssat r8, #1, r10, lsl #0 - ssat r8, #1, r10, lsl #31 - ssat r8, #1, r10, asr #32 - ssat r8, #1, r10, asr #1 + ssat r8, #1, r10 + ssat r8, #1, r10, lsl #0 + ssat r8, #1, r10, lsl #31 + ssat r8, #1, r10, asr #32 + ssat r8, #1, r10, asr #1 @ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] @ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] @@ -1660,8 +1660,8 @@ @------------------------------------------------------------------------------ @ SSAT16 @------------------------------------------------------------------------------ - ssat16 r2, #1, r7 - ssat16 r3, #16, r5 + ssat16 r2, #1, r7 + ssat16 r3, #16, r5 @ CHECK: ssat16 r2, #1, r7 @ encoding: [0x37,0x2f,0xa0,0xe6] @ CHECK: ssat16 r3, #16, r5 @ encoding: [0x35,0x3f,0xaf,0xe6] @@ -2164,11 +2164,11 @@ @ USAT @------------------------------------------------------------------------------ - usat r8, #1, r10 - usat r8, #4, r10, lsl #0 - usat r8, #5, r10, lsl #31 - usat r8, #31, r10, asr #32 - usat r8, #16, r10, asr #1 + usat r8, #1, r10 + usat r8, #4, r10, lsl #0 + usat r8, #5, r10, lsl #31 + usat r8, #31, r10, asr #32 + usat r8, #16, r10, asr #1 @ CHECK: usat r8, #1, r10 @ encoding: [0x1a,0x80,0xe1,0xe6] @ CHECK: usat r8, #4, r10 @ encoding: [0x1a,0x80,0xe4,0xe6] @@ -2179,8 +2179,8 @@ @------------------------------------------------------------------------------ @ USAT16 @------------------------------------------------------------------------------ - usat16 r2, #2, r7 - usat16 r3, #15, r5 + usat16 r2, #2, r7 + usat16 r3, #15, r5 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x32,0x2f,0xe2,0xe6] @ CHECK: usat16 r3, #15, r5 @ encoding: [0x33,0x3f,0xef,0xe6] From enderby at apple.com Wed Jul 27 18:01:50 2011 From: enderby at apple.com (Kevin Enderby) Date: Wed, 27 Jul 2011 23:01:50 -0000 Subject: [llvm-commits] [llvm] r136287 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-32-avx.s test/MC/X86/x86-32-coverage.s utils/TableGen/EDEmitter.cpp utils/TableGen/X86RecognizableInstr.cpp Message-ID: <20110727230150.8F60D2A6C12C@llvm.org> Author: enderby Date: Wed Jul 27 18:01:50 2011 New Revision: 136287 URL: http://llvm.org/viewvc/llvm-project?rev=136287&view=rev Log: Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/X86/x86-32-avx.s llvm/trunk/test/MC/X86/x86-32-coverage.s llvm/trunk/utils/TableGen/EDEmitter.cpp llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136287&r1=136286&r2=136287&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Jul 27 18:01:50 2011 @@ -226,6 +226,21 @@ (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)|| (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL)); } + bool isImmZExtu32u8() const { + if (!isImm()) + return false; + + // If this isn't a constant expr, just assume it fits and let relaxation + // handle it. + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) + return true; + + // Otherwise, check the value is in a range that makes sense for this + // extension. + uint64_t Value = CE->getValue(); + return (Value <= 0x00000000000000FFULL); + } bool isImmSExti64i8() const { if (!isImm()) return false; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=136287&r1=136286&r2=136287&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jul 27 18:01:50 2011 @@ -331,6 +331,11 @@ let RenderMethod = "addImmOperands"; } +class ImmZExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + // Sign-extended immediate classes. We don't need to define the full lattice // here because there is no instruction with an ambiguity between ImmSExti64i32 // and ImmSExti32i8. @@ -358,6 +363,12 @@ let Name = "ImmSExti32i8"; } +// [0, 0x000000FF] +def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { + let Name = "ImmZExtu32u8"; +} + + // [0, 0x0000007F] | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { @@ -377,6 +388,11 @@ let ParserMatchClass = ImmSExti32i8AsmOperand; let OperandType = "OPERAND_IMMEDIATE"; } +// 32-bits but only 8 bits are significant, and those 8 bits are unsigned. +def u32u8imm : Operand { + let ParserMatchClass = ImmZExtu32u8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} // 64-bits but only 32 bits are significant. def i64i32imm : Operand { Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136287&r1=136286&r2=136287&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 27 18:01:50 2011 @@ -4298,7 +4298,7 @@ // in the target vector. multiclass SS41I_insertf32 opc, string asm, bit Is2Addr = 1> { def rr : SS4AIi8, OpSize; def rm : SS4AIi8 { let isCommutable = 1 in def rri : SS4AIi8, OpSize; def rmi : SS4AIi8 Author: grosbach Date: Wed Jul 27 18:07:00 2011 New Revision: 136288 URL: http://llvm.org/viewvc/llvm-project?rev=136288&view=rev Log: ARM assembly parsing and encoding for USAX. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136288&r1=136287&r2=136288&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 18:07:00 2011 @@ -2184,3 +2184,14 @@ @ CHECK: usat16 r2, #2, r7 @ encoding: [0x32,0x2f,0xe2,0xe6] @ CHECK: usat16 r3, #15, r5 @ encoding: [0x33,0x3f,0xef,0xe6] + + + at ------------------------------------------------------------------------------ +@ USAX + at ------------------------------------------------------------------------------ + usax r2, r3, r4 + usaxne r2, r3, r4 + +@ CHECK: usax r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0xe6] +@ CHECK: usaxne r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0x16] + From tobias at grosser.es Wed Jul 27 18:08:51 2011 From: tobias at grosser.es (Tobias Grosser) Date: Thu, 28 Jul 2011 01:08:51 +0200 Subject: [llvm-commits] [llvm] r136024 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake In-Reply-To: <20110726000911.884FD2A6C12D@llvm.org> References: <20110726000911.884FD2A6C12D@llvm.org> Message-ID: <4E309A83.9070804@grosser.es> On 07/26/2011 02:09 AM, Chandler Carruth wrote: > Author: chandlerc > Date: Mon Jul 25 19:09:11 2011 > New Revision: 136024 > > URL: http://llvm.org/viewvc/llvm-project?rev=136024&view=rev > Log: > Still more library dependency updates. This reflects the ever decreasing > dependence on CodeGen layers and backends from the MC layers. Hi, it seems this commit broke the cmake build. At my home machine as well as on the Polly buildbot we fail with the following error message: Linking CXX executable ../../bin/llvm-mc ../../lib/libLLVMARMDisassembler.a(ARMDisassembler.cpp.o):(.data.rel.ro+0x0): undefined reference to `llvm::ARM::CCRRegClass' ../../lib/libLLVMARMDisassembler.a(ARMDisassembler.cpp.o):(.data.rel.ro+0x8): undefined reference to `llvm::ARM::DPRRegClass' ../../lib/libLLVMARMDisassembler.a(ARMDisassembler.cpp.o):(.data.rel.ro+0x10): undefined reference to `llvm::ARM::DPR_8RegClass' ../../lib/libLLVMARMDisassembler.a(ARMDisassembler.cpp.o):(.data.rel.ro+0x18): undefined reference to `llvm::ARM::DPR_VFP2RegClass' ../../lib/libLLVMARMDisassembler.a(ARMDisassembler.cpp.o):(.data.rel.ro+0x20): undefined reference to `llvm::ARM::GPRRegClass' [...] Here the complete log: http://google1.osuosl.org:8011/builders/polly-amd64-linux/builds/359/steps/build_polly/logs/stdio Could you have a look? Tobi From grosbach at apple.com Wed Jul 27 18:10:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 27 Jul 2011 23:10:05 -0000 Subject: [llvm-commits] [llvm] r136289 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110727231005.65B072A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 18:10:05 2011 New Revision: 136289 URL: http://llvm.org/viewvc/llvm-project?rev=136289&view=rev Log: ARM assembly parsing and encoding for USUB16 and USUB8. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136289&r1=136288&r2=136289&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 18:10:05 2011 @@ -2195,3 +2195,16 @@ @ CHECK: usax r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0xe6] @ CHECK: usaxne r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0x16] + at ------------------------------------------------------------------------------ +@ USUB16/USUB8 + at ------------------------------------------------------------------------------ + usub16 r4, r2, r7 + usub16hi r1, r1, r3 + usub8 r1, r8, r5 + usub8le r9, r2, r3 + +@ CHECK: usub16 r4, r2, r7 @ encoding: [0x77,0x4f,0x52,0xe6] +@ CHECK: usub16hi r1, r1, r3 @ encoding: [0x73,0x1f,0x51,0x86] +@ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6] +@ CHECK: usub8le r9, r2, r3 @ encoding: [0xf3,0x9f,0x52,0xd6] + From evan.cheng at apple.com Wed Jul 27 18:22:03 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 27 Jul 2011 23:22:03 -0000 Subject: [llvm-commits] [llvm] r136292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp test/MC/X86/3DNow.s test/MC/X86/x86-32-coverage.s test/MC/X86/x86_errors.s utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110727232203.DF89A2A6C12C@llvm.org> Author: evancheng Date: Wed Jul 27 18:22:03 2011 New Revision: 136292 URL: http://llvm.org/viewvc/llvm-project?rev=136292&view=rev Log: Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp llvm/trunk/test/MC/X86/3DNow.s llvm/trunk/test/MC/X86/x86-32-coverage.s llvm/trunk/test/MC/X86/x86_errors.s llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 18:22:03 2011 @@ -161,11 +161,6 @@ }; } // end anonymous namespace -namespace llvm { - // FIXME: TableGen this? - extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc. -} - namespace { /// ARMOperand - Instances of this class represent a parsed ARM machine Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Jul 27 18:22:03 2011 @@ -1152,11 +1152,6 @@ return msb; } -namespace llvm { - // FIXME: TableGen this? - extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc. -} - unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Jul 27 18:22:03 2011 @@ -13,6 +13,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" @@ -400,19 +401,25 @@ if (Tok.isNot(AsmToken::Identifier)) return Error(Tok.getLoc(), "invalid register name"); - // FIXME: Validate register for the current architecture; we have to do - // validation later, so maybe there is no need for this here. RegNo = MatchRegisterName(Tok.getString()); // If the match failed, try the register name as lowercase. if (RegNo == 0) RegNo = MatchRegisterName(LowercaseString(Tok.getString())); - // FIXME: This should be done using Requires and - // Requires so "eiz" usage in 64-bit instructions - // can be also checked. - if (RegNo == X86::RIZ && !is64BitMode()) - return Error(Tok.getLoc(), "riz register in 64-bit mode only"); + if (!is64BitMode()) { + // FIXME: This should be done using Requires and + // Requires so "eiz" usage in 64-bit instructions can be also + // checked. + // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a + // REX prefix. + if (RegNo == X86::RIZ || + X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) || + X86II::isX86_64NonExtLowByteReg(RegNo) || + X86II::isX86_64ExtendedReg(RegNo)) + return Error(Tok.getLoc(), "register %" + + Tok.getString() + " is only available in 64-bit mode"); + } // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) { @@ -490,7 +497,7 @@ SMLoc Start, End; if (ParseRegister(RegNo, Start, End)) return 0; if (RegNo == X86::EIZ || RegNo == X86::RIZ) { - Error(Start, "eiz and riz can only be used as index registers"); + Error(Start, "%eiz and %riz can only be used as index registers"); return 0; } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Jul 27 18:22:03 2011 @@ -155,11 +155,6 @@ return MCFixup::getKindForSize(Size, isPCRel); } -namespace llvm { - // FIXME: TableGen this? - extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc. -} - /// Is32BitMemOperand - Return true if the specified instruction with a memory /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit /// memory operand. Op specifies the operand # of the memoperand. Modified: llvm/trunk/test/MC/X86/3DNow.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/3DNow.s?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/3DNow.s (original) +++ llvm/trunk/test/MC/X86/3DNow.s Wed Jul 27 18:22:03 2011 @@ -1,18 +1,18 @@ -// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s // PR8283 // CHECK: pavgusb %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xbf] pavgusb %mm2, %mm1 -// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0xbf] +// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf] pavgusb 9(%esi,%edx), %mm3 // CHECK: pf2id %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0x1d] pf2id %mm2, %mm1 -// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0x1d] +// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d] pf2id 9(%esi,%edx), %mm3 // CHECK: pfacc %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xae] Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-32-coverage.s (original) +++ llvm/trunk/test/MC/X86/x86-32-coverage.s Wed Jul 27 18:22:03 2011 @@ -19571,8 +19571,8 @@ // CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2 aeskeygenassist $125, (%edx,%eax,4), %xmm2 -// CHECK: blendvps (%rax), %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0x08] - blendvps (%rax), %xmm1 +// CHECK: blendvps (%eax), %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0x08] + blendvps (%eax), %xmm1 // CHECK: blendvps %xmm2, %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0xca] blendvps %xmm2, %xmm1 Modified: llvm/trunk/test/MC/X86/x86_errors.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86_errors.s (original) +++ llvm/trunk/test/MC/X86/x86_errors.s Wed Jul 27 18:22:03 2011 @@ -1,5 +1,12 @@ // RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err -// RUN: FileCheck < %t.err %s +// RUN: FileCheck --check-prefix=64 < %t.err %s -// CHECK: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq') +// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err +// RUN: FileCheck --check-prefix=32 < %t.err %s +// rdar://8204588 + +// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq') cmp $0, 0(%eax) + +// 32: error: register %rax is only available in 64-bit mode +addl $0, 0(%rax) Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Jul 27 18:22:03 2011 @@ -40,6 +40,9 @@ OS << "namespace llvm {\n\n"; + OS << "class MCRegisterClass;\n" + << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n"; + if (!Namespace.empty()) OS << "namespace " << Namespace << " {\n"; OS << "enum {\n NoRegister,\n"; From resistor at mac.com Wed Jul 27 18:36:57 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 27 Jul 2011 23:36:57 -0000 Subject: [llvm-commits] [llvm] r136295 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td AsmParser/ARMAsmParser.cpp Disassembler/ARMDisassemblerCore.cpp Message-ID: <20110727233657.A479F2A6C12C@llvm.org> Author: resistor Date: Wed Jul 27 18:36:57 2011 New Revision: 136295 URL: http://llvm.org/viewvc/llvm-project?rev=136295&view=rev Log: Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136295&r1=136294&r2=136295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 18:36:57 2011 @@ -1863,7 +1863,7 @@ } multiclass AI3_ldridx op, bit op20, string opc, InstrItinClass itin> { - def _PRE : AI3ldstidx { @@ -1874,7 +1874,7 @@ let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm } - def _POST : AI3ldstidx { @@ -1893,7 +1893,7 @@ defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>; defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>; let hasExtraDefRegAllocReq = 1 in { -def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), +def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), IndexModePre, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr!", @@ -1904,8 +1904,9 @@ let Inst{19-16} = addr{12-9}; // Rn let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm + let DecoderMethod = "DecodeAddrMode3Instruction"; } -def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), +def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn, am3offset:$offset), IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, [$Rn], $offset", @@ -1917,6 +1918,7 @@ let Inst{19-16} = Rn; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm + let DecoderMethod = "DecodeAddrMode3Instruction"; } } // hasExtraDefRegAllocReq = 1 } // mayLoad = 1, neverHasSideEffects = 1 @@ -1953,17 +1955,17 @@ let Inst{11-0} = addr{11-0}; let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } -def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), +def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt), (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> { let Inst{21} = 1; // overwrite } -def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), +def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt), (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> { let Inst{21} = 1; // overwrite } -def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), +def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt), (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> { let Inst{21} = 1; // overwrite @@ -1981,7 +1983,10 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr), StMiscFrm, IIC_iStore_d_r, - "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>; + "strd", "\t$Rt, $src2, $addr", []>, + Requires<[IsARM, HasV5TE]> { + let Inst{21} = 0; +} // Indexed stores def STR_PRE_REG : AI2stridx_reg<0, 1, (outs GPR:$Rn_wb), @@ -2070,14 +2075,38 @@ (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), StMiscFrm, IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base, $offset]!", - "$base = $base_wb", []>; + "$base = $base_wb", []> { + bits<4> src1; + bits<4> base; + bits<10> offset; + let Inst{23} = offset{8}; // U bit + let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm + let Inst{19-16} = base; + let Inst{15-12} = src1; + let Inst{11-8} = offset{7-4}; + let Inst{3-0} = offset{3-0}; + + let DecoderMethod = "DecodeAddrMode3Instruction"; +} // For disassembly only def STRD_POST: AI3stdpo<(outs GPR:$base_wb), (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), StMiscFrm, IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base], $offset", - "$base = $base_wb", []>; + "$base = $base_wb", []> { + bits<4> src1; + bits<4> base; + bits<10> offset; + let Inst{23} = offset{8}; // U bit + let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm + let Inst{19-16} = base; + let Inst{15-12} = src1; + let Inst{11-8} = offset{7-4}; + let Inst{3-0} = offset{3-0}; + + let DecoderMethod = "DecodeAddrMode3Instruction"; +} } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 // STRT, STRBT, and STRHT are for disassembly only. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136295&r1=136294&r2=136295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 18:36:57 2011 @@ -1919,11 +1919,9 @@ bool ARMAsmParser:: cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { - ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); - // Create a writeback register dummy placeholder. Inst.addOperand(MCOperand::CreateImm(0)); - + ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); return true; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=136295&r1=136294&r2=136295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 27 18:36:57 2011 @@ -1460,7 +1460,7 @@ && "Invalid arguments"); // Operand 0 of a pre- and post-indexed store is the address base writeback. - if (isPrePost && isStore) { + if (isPrePost) { assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, @@ -1485,15 +1485,6 @@ ++OpIdx; } - // After dst of a pre- and post-indexed load is the address base writeback. - if (isPrePost && !isStore) { - assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && - "Reg operand expected"); - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, - decodeRn(insn)))); - ++OpIdx; - } - // Disassemble the base operand. if (OpIdx >= NumOps) return false; From eli.friedman at gmail.com Wed Jul 27 19:22:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 17:22:42 -0700 Subject: [llvm-commits] [llvm] r136292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp test/MC/X86/3DNo Message-ID: On Wed, Jul 27, 2011 at 4:22 PM, Evan Cheng wrote: > Modified: llvm/trunk/test/MC/X86/3DNow.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/3DNow.s?rev=136292&r1=136291&r2=136292&view=diff > ============================================================================== > --- llvm/trunk/test/MC/X86/3DNow.s (original) > +++ llvm/trunk/test/MC/X86/3DNow.s Wed Jul 27 18:22:03 2011 > @@ -1,18 +1,18 @@ > -// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s > +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s > > ?// PR8283 > > ?// CHECK: pavgusb %mm2, %mm1 ?# encoding: [0x0f,0x0f,0xca,0xbf] > ?pavgusb ? ? ? ?%mm2, %mm1 > > -// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0xbf] > +// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf] > ?pavgusb ? ? ? ?9(%esi,%edx), %mm3 > > > ?// CHECK: pf2id %mm2, %mm1 ?# encoding: [0x0f,0x0f,0xca,0x1d] > ?pf2id ?%mm2, %mm1 > > -// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0x1d] > +// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d] > ?pf2id ?9(%esi,%edx), %mm3 Err, this seems like an odd place to be testing unusual address-size prefixes... -Eli From akyrtzi at gmail.com Wed Jul 27 19:29:20 2011 From: akyrtzi at gmail.com (Argyrios Kyrtzidis) Date: Thu, 28 Jul 2011 00:29:20 -0000 Subject: [llvm-commits] [llvm] r136310 - in /llvm/trunk: include/llvm/Support/FileSystem.h lib/Support/Unix/PathV2.inc lib/Support/Windows/PathV2.inc Message-ID: <20110728002920.AE4C52A6C12C@llvm.org> Author: akirtzidis Date: Wed Jul 27 19:29:20 2011 New Revision: 136310 URL: http://llvm.org/viewvc/llvm-project?rev=136310&view=rev Log: Add an optional 'bool makeAbsolute' in llvm::sys::fs::unique_file function. If true and 'model' parameter is not an absolute path, a temp directory will be prepended. Make it true by default to match current behaviour. Modified: llvm/trunk/include/llvm/Support/FileSystem.h llvm/trunk/lib/Support/Unix/PathV2.inc llvm/trunk/lib/Support/Windows/PathV2.inc Modified: llvm/trunk/include/llvm/Support/FileSystem.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/FileSystem.h?rev=136310&r1=136309&r2=136310&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/FileSystem.h (original) +++ llvm/trunk/include/llvm/Support/FileSystem.h Wed Jul 27 19:29:20 2011 @@ -427,10 +427,13 @@ /// @param model Name to base unique path off of. /// @param result_fs Set to the opened file's file descriptor. /// @param result_path Set to the opened file's absolute path. +/// @param makeAbsolute If true and @model is not an absolute path, a temp +/// directory will be prepended. /// @results errc::success if result_{fd,path} have been successfully set, /// otherwise a platform specific error_code. error_code unique_file(const Twine &model, int &result_fd, - SmallVectorImpl &result_path); + SmallVectorImpl &result_path, + bool makeAbsolute = true); /// @brief Canonicalize path. /// Modified: llvm/trunk/lib/Support/Unix/PathV2.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/PathV2.inc?rev=136310&r1=136309&r2=136310&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/PathV2.inc (original) +++ llvm/trunk/lib/Support/Unix/PathV2.inc Wed Jul 27 19:29:20 2011 @@ -342,19 +342,22 @@ } error_code unique_file(const Twine &model, int &result_fd, - SmallVectorImpl &result_path) { + SmallVectorImpl &result_path, + bool makeAbsolute) { SmallString<128> Model; model.toVector(Model); // Null terminate. Model.c_str(); - // Make model absolute by prepending a temp directory if it's not already. - bool absolute = path::is_absolute(Twine(Model)); - if (!absolute) { - SmallString<128> TDir; - if (error_code ec = TempDir(TDir)) return ec; - path::append(TDir, Twine(Model)); - Model.swap(TDir); + if (makeAbsolute) { + // Make model absolute by prepending a temp directory if it's not already. + bool absolute = path::is_absolute(Twine(Model)); + if (!absolute) { + SmallString<128> TDir; + if (error_code ec = TempDir(TDir)) return ec; + path::append(TDir, Twine(Model)); + Model.swap(TDir); + } } // Replace '%' with random chars. From here on, DO NOT modify model. It may be Modified: llvm/trunk/lib/Support/Windows/PathV2.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/PathV2.inc?rev=136310&r1=136309&r2=136310&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/PathV2.inc (original) +++ llvm/trunk/lib/Support/Windows/PathV2.inc Wed Jul 27 19:29:20 2011 @@ -501,7 +501,8 @@ } error_code unique_file(const Twine &model, int &result_fd, - SmallVectorImpl &result_path) { + SmallVectorImpl &result_path, + bool makeAbsolute) { // Use result_path as temp storage. result_path.set_size(0); StringRef m = model.toStringRef(result_path); @@ -509,17 +510,19 @@ SmallVector model_utf16; if (error_code ec = UTF8ToUTF16(m, model_utf16)) return ec; - // Make model absolute by prepending a temp directory if it's not already. - bool absolute = path::is_absolute(m); - - if (!absolute) { - SmallVector temp_dir; - if (error_code ec = TempDir(temp_dir)) return ec; - // Handle c: by removing it. - if (model_utf16.size() > 2 && model_utf16[1] == L':') { - model_utf16.erase(model_utf16.begin(), model_utf16.begin() + 2); + if (makeAbsolute) { + // Make model absolute by prepending a temp directory if it's not already. + bool absolute = path::is_absolute(m); + + if (!absolute) { + SmallVector temp_dir; + if (error_code ec = TempDir(temp_dir)) return ec; + // Handle c: by removing it. + if (model_utf16.size() > 2 && model_utf16[1] == L':') { + model_utf16.erase(model_utf16.begin(), model_utf16.begin() + 2); + } + model_utf16.insert(model_utf16.begin(), temp_dir.begin(), temp_dir.end()); } - model_utf16.insert(model_utf16.begin(), temp_dir.begin(), temp_dir.end()); } // Replace '%' with random chars. From here on, DO NOT modify model. It may be From grosbach at apple.com Wed Jul 27 19:37:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 28 Jul 2011 00:37:03 -0000 Subject: [llvm-commits] [llvm] r136312 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s Message-ID: <20110728003703.EC90F2A6C12C@llvm.org> Author: grosbach Date: Wed Jul 27 19:37:03 2011 New Revision: 136312 URL: http://llvm.org/viewvc/llvm-project?rev=136312&view=rev Log: ARM parsing and encoding tests. UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH. Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136312&r1=136311&r2=136312&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 19:37:03 2011 @@ -2208,3 +2208,115 @@ @ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6] @ CHECK: usub8le r9, r2, r3 @ encoding: [0xf3,0x9f,0x52,0xd6] + + at ------------------------------------------------------------------------------ +@ UXTAB + at ------------------------------------------------------------------------------ + uxtab r2, r3, r4 + uxtab r4, r5, r6, ror #0 + uxtablt r6, r2, r9, ror #8 + uxtab r5, r1, r4, ror #16 + uxtab r7, r8, r3, ror #24 + +@ CHECK: uxtab r2, r3, r4 @ encoding: [0x74,0x20,0xe3,0xe6] +@ CHECK: uxtab r4, r5, r6 @ encoding: [0x76,0x40,0xe5,0xe6] +@ CHECK: uxtablt r6, r2, r9, ror #8 + @ encoding: [0x79,0x64,0xe2,0xb6] +@ CHECK: uxtab r5, r1, r4, ror #16 + @ encoding: [0x74,0x58,0xe1,0xe6] +@ CHECK: uxtab r7, r8, r3, ror #24 + @ encoding: [0x73,0x7c,0xe8,0xe6] + + + at ------------------------------------------------------------------------------ +@ UXTAB16 + at ------------------------------------------------------------------------------ + uxtab16ge r0, r1, r4 + uxtab16 r6, r2, r7, ror #0 + uxtab16 r3, r5, r8, ror #8 + uxtab16 r3, r2, r1, ror #16 + uxtab16eq r1, r2, r3, ror #24 + +@ CHECK: uxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0xc1,0xa6] +@ CHECK: uxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0xc2,0xe6] +@ CHECK: uxtab16 r3, r5, r8, ror #8 + @ encoding: [0x78,0x34,0xc5,0xe6] +@ CHECK: uxtab16 r3, r2, r1, ror #16 + @ encoding: [0x71,0x38,0xc2,0xe6] +@ CHECK: uxtab16eq r1, r2, r3, ror #24 + @ encoding: [0x73,0x1c,0xc2,0x06] + + at ------------------------------------------------------------------------------ +@ UXTAH + at ------------------------------------------------------------------------------ + uxtah r1, r3, r9 + uxtahhi r6, r1, r6, ror #0 + uxtah r3, r8, r3, ror #8 + uxtahlo r2, r2, r4, ror #16 + uxtah r9, r3, r3, ror #24 + +@ CHECK: uxtah r1, r3, r9 @ encoding: [0x79,0x10,0xf3,0xe6] +@ CHECK: uxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xf1,0x86] +@ CHECK: uxtah r3, r8, r3, ror #8 + @ encoding: [0x73,0x34,0xf8,0xe6] +@ CHECK: uxtahlo r2, r2, r4, ror #16 + @ encoding: [0x74,0x28,0xf2,0x36] +@ CHECK: uxtah r9, r3, r3, ror #24 + @ encoding: [0x73,0x9c,0xf3,0xe6] + + at ------------------------------------------------------------------------------ +@ UXTB + at ------------------------------------------------------------------------------ + uxtbge r2, r4 + uxtb r5, r6, ror #0 + uxtb r6, r9, ror #8 + uxtbcc r5, r1, ror #16 + uxtb r8, r3, ror #24 + +@ CHECK: uxtbge r2, r4 @ encoding: [0x74,0x20,0xef,0xa6] +@ CHECK: uxtb r5, r6 @ encoding: [0x76,0x50,0xef,0xe6] +@ CHECK: uxtb r6, r9, ror #8 + @ encoding: [0x79,0x64,0xef,0xe6] +@ CHECK: uxtblo r5, r1, ror #16 + @ encoding: [0x71,0x58,0xef,0x36] +@ CHECK: uxtb r8, r3, ror #24 + @ encoding: [0x73,0x8c,0xef,0xe6] + + + at ------------------------------------------------------------------------------ +@ UXTB16 + at ------------------------------------------------------------------------------ + uxtb16 r1, r4 + uxtb16 r6, r7, ror #0 + uxtb16cs r3, r5, ror #8 + uxtb16 r3, r1, ror #16 + uxtb16ge r2, r3, ror #24 + +@ CHECK: uxtb16 r1, r4 @ encoding: [0x74,0x10,0xcf,0xe6] +@ CHECK: uxtb16 r6, r7 @ encoding: [0x77,0x60,0xcf,0xe6] +@ CHECK: uxtb16hs r3, r5, ror #8 + @ encoding: [0x75,0x34,0xcf,0x26] +@ CHECK: uxtb16 r3, r1, ror #16 + @ encoding: [0x71,0x38,0xcf,0xe6] +@ CHECK: uxtb16ge r2, r3, ror #24 + @ encoding: [0x73,0x2c,0xcf,0xa6] + + + at ------------------------------------------------------------------------------ +@ UXTH + at ------------------------------------------------------------------------------ + uxthne r3, r9 + uxth r1, r6, ror #0 + uxth r3, r8, ror #8 + uxthle r2, r2, ror #16 + uxth r9, r3, ror #24 + +@ CHECK: uxthne r3, r9 @ encoding: [0x79,0x30,0xff,0x16] +@ CHECK: uxth r1, r6 @ encoding: [0x76,0x10,0xff,0xe6] +@ CHECK: uxth r3, r8, ror #8 + @ encoding: [0x78,0x34,0xff,0xe6] +@ CHECK: uxthle r2, r2, ror #16 + @ encoding: [0x72,0x28,0xff,0xd6] +@ CHECK: uxth r9, r3, ror #24 + @ encoding: [0x73,0x9c,0xff,0xe6] + From isanbard at gmail.com Wed Jul 27 19:38:23 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 00:38:23 -0000 Subject: [llvm-commits] [llvm] r136313 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110728003823.981A52A6C12C@llvm.org> Author: void Date: Wed Jul 27 19:38:23 2011 New Revision: 136313 URL: http://llvm.org/viewvc/llvm-project?rev=136313&view=rev Log: Initial stab at getting inlining working with the EH rewrite. This takes the new 'resume' instruction and turns it into a direct jump to the caller's landing pad code. The caller's landingpad instruction is merged with the landingpad instructions of the callee. This is a bit rough and makes some assumptions in how the code works. But it passes a simple test. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=136313&r1=136312&r2=136313&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Wed Jul 27 19:38:23 2011 @@ -250,21 +250,29 @@ PHINode *InnerSelectorPHI; SmallVector UnwindDestPHIValues; - public: - InvokeInliningInfo(InvokeInst *II) : - OuterUnwindDest(II->getUnwindDest()), OuterSelector(0), - InnerUnwindDest(0), InnerExceptionPHI(0), InnerSelectorPHI(0) { + SmallVector CalleeLPads; + LandingPadInst *CallerLPad; + BasicBlock *SplitLPad; + public: + InvokeInliningInfo(InvokeInst *II) + : OuterUnwindDest(II->getUnwindDest()), OuterSelector(0), + InnerUnwindDest(0), InnerExceptionPHI(0), InnerSelectorPHI(0), + CallerLPad(0), SplitLPad(0) { // If there are PHI nodes in the unwind destination block, we // need to keep track of which values came into them from the // invoke before removing the edge from this block. llvm::BasicBlock *invokeBB = II->getParent(); - for (BasicBlock::iterator I = OuterUnwindDest->begin(); - isa(I); ++I) { + BasicBlock::iterator I = OuterUnwindDest->begin(); + for (; isa(I); ++I) { // Save the value to use for this edge. PHINode *phi = cast(I); UnwindDestPHIValues.push_back(phi->getIncomingValueForBlock(invokeBB)); } + + // FIXME: With the new EH, this if/dyn_cast should be a 'cast'. + if (LandingPadInst *LPI = dyn_cast(I)) + CallerLPad = LPI; } /// The outer unwind destination is the target of unwind edges @@ -281,15 +289,39 @@ BasicBlock *getInnerUnwindDest(); + void addCalleeLandingPad(LandingPadInst *LPI) { + CalleeLPads.push_back(LPI); + } + + LandingPadInst *getLandingPadInst() const { return CallerLPad; } + BasicBlock *getSplitLandingPad() { + if (SplitLPad) return SplitLPad; + assert(CallerLPad && "Trying to split a block that isn't a landing pad!"); + BasicBlock::iterator I = CallerLPad; ++I; + SplitLPad = CallerLPad->getParent()->splitBasicBlock(I, "split.lpad"); + return SplitLPad; + } + bool forwardEHResume(CallInst *call, BasicBlock *src); - /// Add incoming-PHI values to the unwind destination block for - /// the given basic block, using the values for the original - /// invoke's source block. + /// forwardResume - Forward the 'resume' instruction to the caller's landing + /// pad block. When the landing pad block has only one predecessor, this is + /// a simple branch. When there is more than one predecessor, we need to + /// split the landing pad block after the landingpad instruction and jump + /// to there. + void forwardResume(ResumeInst *RI); + + /// mergeLandingPadClauses - Visit all of the landing pad instructions which + /// supply the value for the ResumeInst, and merge the clauses from the new + /// destination (the caller's landing pad). + void mergeLandingPadClauses(ResumeInst *RI); + + /// addIncomingPHIValuesFor - Add incoming-PHI values to the unwind + /// destination block for the given basic block, using the values for the + /// original invoke's source block. void addIncomingPHIValuesFor(BasicBlock *BB) const { addIncomingPHIValuesForInto(BB, OuterUnwindDest); } - void addIncomingPHIValuesForInto(BasicBlock *src, BasicBlock *dest) const { BasicBlock::iterator I = dest->begin(); for (unsigned i = 0, e = UnwindDestPHIValues.size(); i != e; ++i, ++I) { @@ -404,6 +436,51 @@ return true; } +/// mergeLandingPadClauses - Visit all of the landing pad instructions merge the +/// clauses from the new destination (the caller's landing pad). +void InvokeInliningInfo::mergeLandingPadClauses(ResumeInst *RI) { + for (SmallVectorImpl::iterator + I = CalleeLPads.begin(), E = CalleeLPads.end(); I != E; ++I) + for (unsigned i = 0, e = CallerLPad->getNumClauses(); i != e; ++i) + (*I)->addClause(CallerLPad->getClauseType(i), + CallerLPad->getClauseValue(i)); +} + +/// forwardResume - Forward the 'resume' instruction to the caller's landing pad +/// block. When the landing pad block has only one predecessor, this is a simple +/// branch. When there is more than one predecessor, we need to split the +/// landing pad block after the landingpad instruction and jump to there. +void InvokeInliningInfo::forwardResume(ResumeInst *RI) { + BasicBlock *LPadBB = CallerLPad->getParent(); + Value *ResumeOp = RI->getOperand(0); + + if (!LPadBB->getSinglePredecessor()) { + // There are multiple predecessors to this landing pad block. Split this + // landing pad block and jump to the new BB. + BasicBlock *SplitLPad = getSplitLandingPad(); + BranchInst::Create(SplitLPad, RI->getParent()); + + if (CallerLPad->hasOneUse() && isa(CallerLPad->use_back())) { + PHINode *PN = cast(CallerLPad->use_back()); + PN->addIncoming(ResumeOp, RI->getParent()); + } else { + PHINode *PN = PHINode::Create(ResumeOp->getType(), 0, "lpad.phi", + &SplitLPad->front()); + CallerLPad->replaceAllUsesWith(PN); + PN->addIncoming(ResumeOp, RI->getParent()); + PN->addIncoming(CallerLPad, LPadBB); + } + + RI->eraseFromParent(); + return; + } + + BranchInst::Create(LPadBB, RI->getParent()); + CallerLPad->replaceAllUsesWith(ResumeOp); + CallerLPad->eraseFromParent(); + RI->eraseFromParent(); +} + /// [LIBUNWIND] Check whether this selector is "only cleanups": /// call i32 @llvm.eh.selector(blah, blah, i32 0) static bool isCleanupOnlySelector(EHSelectorInst *selector) { @@ -423,6 +500,12 @@ InvokeInliningInfo &Invoke) { for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) { Instruction *I = BBI++; + + // Collect the callee's landingpad instructions. + if (LandingPadInst *LPI = dyn_cast(I)) { + Invoke.addCalleeLandingPad(LPI); + continue; + } // We only need to check for function calls: inlined invoke // instructions require no special handling. @@ -557,6 +640,11 @@ // there is now a new entry in them. Invoke.addIncomingPHIValuesFor(BB); } + + if (ResumeInst *RI = dyn_cast(BB->getTerminator())) { + Invoke.mergeLandingPadClauses(RI); + Invoke.forwardResume(RI); + } } // Now that everything is happy, we have one final detail. The PHI nodes in From benny.kra at googlemail.com Wed Jul 27 20:20:19 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 28 Jul 2011 01:20:19 -0000 Subject: [llvm-commits] [llvm] r136319 - /llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Message-ID: <20110728012019.38AE72A6C12C@llvm.org> Author: d0k Date: Wed Jul 27 20:20:19 2011 New Revision: 136319 URL: http://llvm.org/viewvc/llvm-project?rev=136319&view=rev Log: Fix a use after free. An instruction can't be both an intrinsic call and a fence. Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=136319&r1=136318&r2=136319&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Wed Jul 27 20:20:19 2011 @@ -132,7 +132,7 @@ Instruction *Inst = DI++; if (IntrinsicInst *II = dyn_cast(Inst)) Changed |= LowerAtomicIntrinsic(II); - if (FenceInst *FI = dyn_cast(Inst)) + else if (FenceInst *FI = dyn_cast(Inst)) Changed |= LowerFenceInst(FI); } return Changed; From rjmccall at apple.com Wed Jul 27 20:23:08 2011 From: rjmccall at apple.com (John McCall) Date: Wed, 27 Jul 2011 18:23:08 -0700 Subject: [llvm-commits] [llvm] r136313 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <20110728003823.981A52A6C12C@llvm.org> References: <20110728003823.981A52A6C12C@llvm.org> Message-ID: <3FDA960A-E9CD-4ABC-8767-25308BBE4D1E@apple.com> On Jul 27, 2011, at 5:38 PM, Bill Wendling wrote: > Author: void > Date: Wed Jul 27 19:38:23 2011 > New Revision: 136313 > > URL: http://llvm.org/viewvc/llvm-project?rev=136313&view=rev > Log: > Initial stab at getting inlining working with the EH rewrite. > > This takes the new 'resume' instruction and turns it into a direct jump to the > caller's landing pad code. The caller's landingpad instruction is merged with > the landingpad instructions of the callee. This is a bit rough and makes some > assumptions in how the code works. But it passes a simple test. +void InvokeInliningInfo::forwardResume(ResumeInst *RI) { I would suggest patterning this code more closely after forwardEHResume: 1. Make getInnerUnwindDest() recognize a LandingPadInst in the outer landing pad; if present, set up a InnerEHValues PHI instead of the InnerSelectionPHI / InnerExceptionPHI. 2. Teach forwardEHResume how to forward to either an InnerEHValues PHI (with a pair of insertvalues) or a Selection/Exception PHI pair, or just have it assert that it's an S/E PHI pair. 3. Teach forwardResume how to forward to either an InnerEHValues PHI or a Selection/Exception PHI pair (with a pair of extractvalues), or just have it assert that it's an EHValues PHI. +/// mergeLandingPadClauses - Visit all of the landing pad instructions merge the +/// clauses from the new destination (the caller's landing pad). +void InvokeInliningInfo::mergeLandingPadClauses(ResumeInst *RI) { + for (SmallVectorImpl::iterator + I = CalleeLPads.begin(), E = CalleeLPads.end(); I != E; ++I) + for (unsigned i = 0, e = CallerLPad->getNumClauses(); i != e; ++i) + (*I)->addClause(CallerLPad->getClauseType(i), + CallerLPad->getClauseValue(i)); +} I don't see the value in queuing up the landingpad instructions here; just merge in the caller's clauses as you find them. That would have the added advantage of not adding the clauses twice if you find two or more resume instructions in the callee. Also, you're not merging the cleanup bit. You might find it useful to assert that personalities and return types match, just to catch mistakes in your preflight check. It might be a good idea to have LandingPadInst provide a reserveClauses(unsigned) method, and you might also want to explicitly constrain addClause and getClauseValue to take and return a Constant*. John. From bruno.cardoso at gmail.com Wed Jul 27 20:26:39 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 28 Jul 2011 01:26:39 -0000 Subject: [llvm-commits] [llvm] r136320 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-256-cvt.ll Message-ID: <20110728012639.EA1D42A6C12C@llvm.org> Author: bruno Date: Wed Jul 27 20:26:39 2011 New Revision: 136320 URL: http://llvm.org/viewvc/llvm-project?rev=136320&view=rev Log: Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move a convert pattern close to the instruction definition. Added: llvm/trunk/test/CodeGen/X86/avx-256-cvt.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136320&r1=136319&r2=136320&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 27 20:26:39 2011 @@ -964,6 +964,9 @@ setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); setOperationAction(ISD::FNEG, MVT::v4f64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); + setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); + // Custom lower several nodes for 256-bit types. for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136320&r1=136319&r2=136320&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 27 20:26:39 2011 @@ -884,7 +884,6 @@ [(set VR128:$dst, (int_x86_sse2_cvttps2dq (memop addr:$src)))]>; - def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvttps2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -896,6 +895,16 @@ (memop addr:$src)))]>, XS, VEX, Requires<[HasAVX]>; +def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))), + (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), + (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>; + +def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))), + (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>; +def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))), + (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>; + def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvttpd2dq\t{$src, $dst|$dst, $src}", @@ -3857,12 +3866,6 @@ def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; -// vector -> vector casts -def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))), - (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>; -def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), - (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>; - // Use movaps / movups for SSE integer load / store (one byte shorter). // The instructions selected below are then converted to MOVDQA/MOVDQU // during the SSE domain pass. Added: llvm/trunk/test/CodeGen/X86/avx-256-cvt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-256-cvt.ll?rev=136320&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-256-cvt.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-256-cvt.ll Wed Jul 27 20:26:39 2011 @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vcvtdq2ps %ymm +define <8 x float> @funcA(<8 x i32> %a) nounwind { + %b = sitofp <8 x i32> %a to <8 x float> + ret <8 x float> %b +} + +; CHECK: vcvttps2dq %ymm +define <8 x i32> @funcB(<8 x float> %a) nounwind { + %b = fptosi <8 x float> %a to <8 x i32> + ret <8 x i32> %b +} + From bruno.cardoso at gmail.com Wed Jul 27 20:26:44 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 28 Jul 2011 01:26:44 -0000 Subject: [llvm-commits] [llvm] r136321 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-cast.ll Message-ID: <20110728012644.29E782A6C12D@llvm.org> Author: bruno Date: Wed Jul 27 20:26:43 2011 New Revision: 136321 URL: http://llvm.org/viewvc/llvm-project?rev=136321&view=rev Log: Add a few patterns to match allzeros without having to use the fp unit. Take advantage that the 128-bit vpxor zeros the higher part and use it. This also fixes PR10491 Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-cast.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136321&r1=136320&r2=136321&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 27 20:26:43 2011 @@ -2098,6 +2098,16 @@ def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; +// AVX has no support for 256-bit integer instructions, but since the 128-bit +// VPXOR instruction writes zero to its upper part, it's safe build zeros. +def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v8i32 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; + +def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v4i64 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; + //===----------------------------------------------------------------------===// // SSE 1 & 2 - Load/Store XCSR register //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/CodeGen/X86/avx-cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cast.ll?rev=136321&r1=136320&r2=136321&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-cast.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-cast.ll Wed Jul 27 20:26:43 2011 @@ -16,7 +16,7 @@ ret <4 x double> %shuffle.i } -; CHECK: vxorps +; CHECK: vpxor ; CHECK-NEXT: vinsertf128 $0 define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp { entry: From bruno.cardoso at gmail.com Wed Jul 27 20:26:46 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 28 Jul 2011 01:26:46 -0000 Subject: [llvm-commits] [llvm] r136322 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110728012646.CDAE32A6C12C@llvm.org> Author: bruno Date: Wed Jul 27 20:26:46 2011 New Revision: 136322 URL: http://llvm.org/viewvc/llvm-project?rev=136322&view=rev Log: movd/movq write zeros in the high 128-bit part of the vector. Use them to match 256-bit scalar_to_vector+zext. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136322&r1=136321&r2=136322&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 27 20:26:46 2011 @@ -2865,7 +2865,9 @@ // SSE2 - Move Doubleword //===---------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Move Int Doubleword to Packed Double Int +// def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -2899,8 +2901,9 @@ "mov{d|q}\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (bitconvert GR64:$src))]>; - +//===---------------------------------------------------------------------===// // Move Int Doubleword to Single Scalar +// def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX; @@ -2917,7 +2920,9 @@ "movd\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>; +//===---------------------------------------------------------------------===// // Move Packed Doubleword Int to Packed Double Int +// def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), "movd\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (vector_extract (v4i32 VR128:$src), @@ -2951,7 +2956,9 @@ "movq\t{$src, $dst|$dst, $src}", [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>; +//===---------------------------------------------------------------------===// // Move Scalar Single to Double Int +// def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), "movd\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX; @@ -2965,7 +2972,9 @@ "movd\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>; -// movd / movq to XMM register zero-extends +//===---------------------------------------------------------------------===// +// Patterns and instructions to describe movd/movq to XMM register zero-extends +// let AddedComplexity = 15 in { def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", @@ -3010,6 +3019,15 @@ (MOVZDI2PDIrm addr:$src)>; } +// AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. +// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. +def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, + (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))), + (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>; +def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))), + (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>; + // These are the correct encodings of the instructions so that we know how to // read correct assembly, even though we continue to emit the wrong ones for // compatibility with Darwin's buggy assembler. @@ -3030,7 +3048,9 @@ // SSE2 - Move Quadword //===---------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Move Quadword Int to Packed Quadword Int +// def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "vmovq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -3042,7 +3062,9 @@ (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix +//===---------------------------------------------------------------------===// // Move Packed Quadword Int to Quadword Int +// def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), "movq\t{$src, $dst|$dst, $src}", [(store (i64 (vector_extract (v2i64 VR128:$src), @@ -3055,7 +3077,9 @@ def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>; +//===---------------------------------------------------------------------===// // Store / copy lower 64-bits of a XMM register. +// def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), "movq\t{$src, $dst|$dst, $src}", [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX; @@ -3086,8 +3110,10 @@ def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>; } +//===---------------------------------------------------------------------===// // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in // IA32 document. movq xmm1, xmm2 does clear the high bits. +// let AddedComplexity = 15 in def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vmovq\t{$src, $dst|$dst, $src}", From bruno.cardoso at gmail.com Wed Jul 27 20:26:53 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 28 Jul 2011 01:26:53 -0000 Subject: [llvm-commits] [llvm] r136324 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110728012653.789B52A6C12C@llvm.org> Author: bruno Date: Wed Jul 27 20:26:53 2011 New Revision: 136324 URL: http://llvm.org/viewvc/llvm-project?rev=136324&view=rev Log: Invert the subvector insertion to be more likely to be taken as a COPY Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=136324&r1=136323&r2=136324&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 27 20:26:53 2011 @@ -4809,9 +4809,9 @@ NumElems/2); // Recreate the wider vector with the lower and upper part. - SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper, - DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); - return Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32), + SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, + DAG.getConstant(0, MVT::i32), DAG, dl); + return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); } From bruno.cardoso at gmail.com Wed Jul 27 20:26:50 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 28 Jul 2011 01:26:50 -0000 Subject: [llvm-commits] [llvm] r136323 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-cast.ll Message-ID: <20110728012650.C1BCF2A6C12D@llvm.org> Author: bruno Date: Wed Jul 27 20:26:50 2011 New Revision: 136323 URL: http://llvm.org/viewvc/llvm-project?rev=136323&view=rev Log: Add patterns to generate copies for extract_subvector instead of using vextractf128. This will reduce the number of issued instruction for several avx codes. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-cast.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136323&r1=136322&r2=136323&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 27 20:26:50 2011 @@ -5452,6 +5452,18 @@ (v32i8 VR256:$src1), (EXTRACT_get_vextractf128_imm VR128:$ext)))>; +// Special COPY patterns +def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>; +def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>; + +def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>; +def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; + + //===----------------------------------------------------------------------===// // VMASKMOV - Conditional SIMD Packed Loads and Stores // Modified: llvm/trunk/test/CodeGen/X86/avx-cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cast.ll?rev=136323&r1=136322&r2=136323&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-cast.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-cast.ll Wed Jul 27 20:26:50 2011 @@ -24,21 +24,21 @@ ret <4 x i64> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> ret <4 x float> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> ret <2 x i64> %shuffle.i } -; CHECK: vextractf128 $0 +; CHECK-NOT: vextractf128 $0 define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp { entry: %shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> From eli.friedman at gmail.com Wed Jul 27 20:31:24 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 27 Jul 2011 18:31:24 -0700 Subject: [llvm-commits] [llvm] r136319 - /llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp In-Reply-To: <20110728012019.38AE72A6C12C@llvm.org> References: <20110728012019.38AE72A6C12C@llvm.org> Message-ID: On Wed, Jul 27, 2011 at 6:20 PM, Benjamin Kramer wrote: > Author: d0k > Date: Wed Jul 27 20:20:19 2011 > New Revision: 136319 > > URL: http://llvm.org/viewvc/llvm-project?rev=136319&view=rev > Log: > Fix a use after free. An instruction can't be both an intrinsic call and a fence. > > Modified: > ? ?llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=136319&r1=136318&r2=136319&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Wed Jul 27 20:20:19 2011 > @@ -132,7 +132,7 @@ > ? ? ? ? Instruction *Inst = DI++; > ? ? ? ? if (IntrinsicInst *II = dyn_cast(Inst)) > ? ? ? ? ? Changed |= LowerAtomicIntrinsic(II); > - ? ? ? ?if (FenceInst *FI = dyn_cast(Inst)) > + ? ? ? ?else if (FenceInst *FI = dyn_cast(Inst)) > ? ? ? ? ? Changed |= LowerFenceInst(FI); > ? ? ? } > ? ? ? return Changed; Thanks for spotting that. -Eli From isanbard at gmail.com Wed Jul 27 20:55:17 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 27 Jul 2011 18:55:17 -0700 Subject: [llvm-commits] [llvm] r136313 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <3FDA960A-E9CD-4ABC-8767-25308BBE4D1E@apple.com> References: <20110728003823.981A52A6C12C@llvm.org> <3FDA960A-E9CD-4ABC-8767-25308BBE4D1E@apple.com> Message-ID: On Jul 27, 2011, at 6:23 PM, John McCall wrote: > On Jul 27, 2011, at 5:38 PM, Bill Wendling wrote: >> Author: void >> Date: Wed Jul 27 19:38:23 2011 >> New Revision: 136313 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=136313&view=rev >> Log: >> Initial stab at getting inlining working with the EH rewrite. >> >> This takes the new 'resume' instruction and turns it into a direct jump to the >> caller's landing pad code. The caller's landingpad instruction is merged with >> the landingpad instructions of the callee. This is a bit rough and makes some >> assumptions in how the code works. But it passes a simple test. > > +void InvokeInliningInfo::forwardResume(ResumeInst *RI) { > > I would suggest patterning this code more closely after forwardEHResume: > 1. Make getInnerUnwindDest() recognize a LandingPadInst in the outer > landing pad; if present, set up a InnerEHValues PHI instead of the > InnerSelectionPHI / InnerExceptionPHI. > 2. Teach forwardEHResume how to forward to either an InnerEHValues PHI > (with a pair of insertvalues) or a Selection/Exception PHI pair, or just have it > assert that it's an S/E PHI pair. > 3. Teach forwardResume how to forward to either an InnerEHValues PHI > or a Selection/Exception PHI pair (with a pair of extractvalues), or just have > it assert that it's an EHValues PHI. > Okay. I'll take a look at those methods. > +/// mergeLandingPadClauses - Visit all of the landing pad instructions merge the > +/// clauses from the new destination (the caller's landing pad). > +void InvokeInliningInfo::mergeLandingPadClauses(ResumeInst *RI) { > + for (SmallVectorImpl::iterator > + I = CalleeLPads.begin(), E = CalleeLPads.end(); I != E; ++I) > + for (unsigned i = 0, e = CallerLPad->getNumClauses(); i != e; ++i) > + (*I)->addClause(CallerLPad->getClauseType(i), > + CallerLPad->getClauseValue(i)); > +} > > I don't see the value in queuing up the landingpad instructions here; > just merge in the caller's clauses as you find them. That would have > the added advantage of not adding the clauses twice if you find two > or more resume instructions in the callee. > > Also, you're not merging the cleanup bit. > Is that the correct semantics? I know I need to keep the cleanup bit on the callee's landingpad instruction, but what about the caller's cleanup bit? > You might find it useful to assert that personalities and return types match, > just to catch mistakes in your preflight check. > > It might be a good idea to have LandingPadInst provide a > reserveClauses(unsigned) method, and you might also want to > explicitly constrain addClause and getClauseValue to take and > return a Constant*. > Okay. -bw From isanbard at gmail.com Wed Jul 27 21:15:52 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 02:15:52 -0000 Subject: [llvm-commits] [llvm] r136325 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp Message-ID: <20110728021552.AC8762A6C12C@llvm.org> Author: void Date: Wed Jul 27 21:15:52 2011 New Revision: 136325 URL: http://llvm.org/viewvc/llvm-project?rev=136325&view=rev Log: Add a couple of convenience functions: * InvokeInst: Get the landingpad instruction associated with this invoke. * LandingPadInst: A method to reserve extra space for clauses. Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=136325&r1=136324&r2=136325&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Wed Jul 27 21:15:52 2011 @@ -1870,6 +1870,10 @@ /// getNumClauses - Get the number of clauses for this landing pad. unsigned getNumClauses() const { return getNumOperands() - 1; } + /// reserveClauses - Grow the size of the operand list to accomodate the new + /// number of clauses. + void reserveClauses(unsigned Size); + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const LandingPadInst *) { return true; } static inline bool classof(const Instruction *I) { @@ -2474,6 +2478,10 @@ Op<-1>() = reinterpret_cast(B); } + // getLandingPad - Get the landingpad instruction from the landing pad block + // (the unwind destination). + LandingPadInst *getLandingPad() const; + BasicBlock *getSuccessor(unsigned i) const { assert(i < 2 && "Successor # out of range for invoke!"); return i == 0 ? getNormalDest() : getUnwindDest(); Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136325&r1=136324&r2=136325&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jul 27 21:15:52 2011 @@ -214,6 +214,20 @@ Use::zap(OldOps, OldOps + e, true); } +void LandingPadInst::reserveClauses(unsigned Size) { + unsigned e = getNumOperands() + Size; + if (ReservedSpace >= e) return; + ReservedSpace = e; + + Use *NewOps = allocHungoffUses(ReservedSpace); + Use *OldOps = OperandList; + for (unsigned i = 0; i != e; ++i) + NewOps[i] = OldOps[i]; + + OperandList = NewOps; + Use::zap(OldOps, OldOps + e, true); +} + void LandingPadInst::addClause(ClauseType CT, Value *ClauseVal) { unsigned OpNo = getNumOperands(); if (OpNo + 1 > ReservedSpace) @@ -551,6 +565,9 @@ setAttributes(PAL); } +LandingPadInst *InvokeInst::getLandingPad() const { + return cast(getUnwindDest()->getFirstNonPHI()); +} //===----------------------------------------------------------------------===// // ReturnInst Implementation From isanbard at gmail.com Wed Jul 27 21:27:12 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 02:27:12 -0000 Subject: [llvm-commits] [llvm] r136326 - in /llvm/trunk: include/llvm/Instructions.h lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp lib/VMCore/Core.cpp lib/VMCore/Instructions.cpp Message-ID: <20110728022712.63BC12A6C12C@llvm.org> Author: void Date: Wed Jul 27 21:27:12 2011 New Revision: 136326 URL: http://llvm.org/viewvc/llvm-project?rev=136326&view=rev Log: Make sure that the landingpad instruction takes a Constant* as the clause's value. Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/VMCore/Core.cpp llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=136326&r1=136325&r2=136326&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Wed Jul 27 21:27:12 2011 @@ -1852,7 +1852,7 @@ void setCleanup(bool Val) { IsCleanup = Val; } /// addClause - Add a clause to the landing pad. - void addClause(ClauseType CT, Value *ClauseVal); + void addClause(ClauseType CT, Constant *ClauseVal); /// getClauseType - Return the type of the clause at this index. The two /// supported clauses are Catch and Filter. @@ -1862,9 +1862,9 @@ } /// getClauseValue - Return the value of the clause at this index. - Value *getClauseValue(unsigned I) const { + Constant *getClauseValue(unsigned I) const { assert(I + 1 < getNumOperands() && "Index too large!"); - return OperandList[I + 1]; + return cast(OperandList[I + 1]); } /// getNumClauses - Get the number of clauses for this landing pad. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=136326&r1=136325&r2=136326&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Jul 27 21:27:12 2011 @@ -3528,7 +3528,7 @@ bool IsCleanup = EatIfPresent(lltok::kw_cleanup); - SmallVector, 16> Clauses; + SmallVector, 16> Clauses; while (Lex.getKind() == lltok::kw_catch || Lex.getKind() == lltok::kw_filter){ LandingPadInst::ClauseType CT; if (Lex.getKind() == lltok::kw_catch) { @@ -3543,14 +3543,15 @@ Value *V; LocTy VLoc; if (ParseTypeAndValue(V, VLoc, PFS)) return true; - Clauses.push_back(std::make_pair(CT, V)); + Clauses.push_back(std::make_pair(CT, cast(V))); } while (EatIfPresent(lltok::comma)); } LandingPadInst *LP = LandingPadInst::Create(Ty, PersFn, Clauses.size()); LP->setCleanup(IsCleanup); - for (SmallVectorImpl >::iterator + for (SmallVectorImpl >::iterator I = Clauses.begin(), E = Clauses.end(); I != E; ++I) LP->addClause(I->first, I->second); Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=136326&r1=136325&r2=136326&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Jul 27 21:27:12 2011 @@ -2550,7 +2550,7 @@ return Error("Invalid LANDINGPAD record"); } - LP->addClause(CT, Val); + LP->addClause(CT, cast(Val)); } I = LP; Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=136326&r1=136325&r2=136326&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Wed Jul 27 21:27:12 2011 @@ -1715,7 +1715,7 @@ LLVMValueRef ClauseVal) { unwrap(LandingPad)-> addClause(static_cast(ClauseTy), - unwrap(ClauseVal)); + cast(unwrap(ClauseVal))); } void LLVMSetCleanup(LLVMValueRef LandingPad, LLVMBool Val) { Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136326&r1=136325&r2=136326&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jul 27 21:27:12 2011 @@ -228,14 +228,14 @@ Use::zap(OldOps, OldOps + e, true); } -void LandingPadInst::addClause(ClauseType CT, Value *ClauseVal) { +void LandingPadInst::addClause(ClauseType CT, Constant *ClauseVal) { unsigned OpNo = getNumOperands(); if (OpNo + 1 > ReservedSpace) growOperands(); assert(OpNo < ReservedSpace && "Growing didn't work!"); ClauseIdxs.push_back(CT); ++NumOperands; - OperandList[OpNo] = ClauseVal; + OperandList[OpNo] = (Value*)ClauseVal; } //===----------------------------------------------------------------------===// From ofv at wanadoo.es Wed Jul 27 21:33:34 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 28 Jul 2011 02:33:34 -0000 Subject: [llvm-commits] [llvm] r136327 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110728023334.1F3F32A6C12C@llvm.org> Author: ofv Date: Wed Jul 27 21:33:33 2011 New Revision: 136327 URL: http://llvm.org/viewvc/llvm-project?rev=136327&view=rev Log: Updated cmake library dependencies. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=136327&r1=136326&r2=136327&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Wed Jul 27 21:33:33 2011 @@ -1,7 +1,7 @@ set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMAsmPrinter LLVMARMInfo LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -34,7 +34,7 @@ set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) @@ -43,11 +43,11 @@ set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info) +set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsAsmPrinter LLVMMipsInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) @@ -55,7 +55,7 @@ set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils) @@ -69,7 +69,7 @@ set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) -set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMX86Desc LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils) set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86AsmPrinter LLVMX86Info) From ofv at wanadoo.es Wed Jul 27 21:33:52 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 28 Jul 2011 02:33:52 -0000 Subject: [llvm-commits] [llvm] r136328 - in /llvm/trunk/lib/Target: ARM/MCTargetDesc/CMakeLists.txt MBlaze/MCTargetDesc/CMakeLists.txt MSP430/MCTargetDesc/CMakeLists.txt Mips/MCTargetDesc/CMakeLists.txt PowerPC/MCTargetDesc/CMakeLists.txt X86/MCTargetDesc/CMakeLists.txt Message-ID: <20110728023352.8C35D2A6C12C@llvm.org> Author: ofv Date: Wed Jul 27 21:33:52 2011 New Revision: 136328 URL: http://llvm.org/viewvc/llvm-project?rev=136328&view=rev Log: Explicitly declare a library dependency of LLVM*Desc to LLVM*AsmPrinter. GenLibDeps.pl fails to detect vtable references. As this is the only referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized builds, the algorithm that creates the list of libraries to be linked into tools doesn't know about the dependency and sometimes places the libraries on the wrong order, yielding error messages like this: ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function `llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)': ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE [llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)]+0x2a): undefined reference to `vtable for llvm::ARMInstPrinter' Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -10,3 +10,5 @@ # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) + +target_link_libraries(LLVMARMDesc LLVMARMAsmPrinter) Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -5,3 +5,5 @@ MBlazeMCTargetDesc.cpp ) add_dependencies(LLVMMBlazeDesc MBlazeCommonTableGen) + +target_link_libraries(LLVMMBlazeDesc LLVMMBlazeAsmPrinter) Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -3,3 +3,5 @@ MSP430MCAsmInfo.cpp ) add_dependencies(LLVMMSP430Desc MSP430CommonTableGen) + +target_link_libraries(LLVMMSP430Desc LLVMMSP430AsmPrinter) Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -3,3 +3,5 @@ MipsMCAsmInfo.cpp ) add_dependencies(LLVMMipsDesc MipsCommonTableGen) + +target_link_libraries(LLVMMipsDesc LLVMMipsAsmPrinter) Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -6,3 +6,5 @@ PPCPredicates.cpp ) add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen) + +target_link_libraries(LLVMPowerPCDesc LLVMPowerPCAsmPrinter) Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=136328&r1=136327&r2=136328&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Wed Jul 27 21:33:52 2011 @@ -9,3 +9,5 @@ # Hack: we need to include 'main' target directory to grab private headers include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) + +target_link_libraries(LLVMX86Desc LLVMX86AsmPrinter) From isanbard at gmail.com Wed Jul 27 21:40:14 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 02:40:14 -0000 Subject: [llvm-commits] [llvm] r136329 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110728024014.267C72A6C12C@llvm.org> Author: void Date: Wed Jul 27 21:40:13 2011 New Revision: 136329 URL: http://llvm.org/viewvc/llvm-project?rev=136329&view=rev Log: Automatically merge the landingpad clauses when we come across a callee's landingpad. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=136329&r1=136328&r2=136329&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Wed Jul 27 21:40:13 2011 @@ -250,7 +250,7 @@ PHINode *InnerSelectorPHI; SmallVector UnwindDestPHIValues; - SmallVector CalleeLPads; + PHINode *InnerEHValuesPHI; LandingPadInst *CallerLPad; BasicBlock *SplitLPad; @@ -258,7 +258,7 @@ InvokeInliningInfo(InvokeInst *II) : OuterUnwindDest(II->getUnwindDest()), OuterSelector(0), InnerUnwindDest(0), InnerExceptionPHI(0), InnerSelectorPHI(0), - CallerLPad(0), SplitLPad(0) { + InnerEHValuesPHI(0), CallerLPad(0), SplitLPad(0) { // If there are PHI nodes in the unwind destination block, we // need to keep track of which values came into them from the // invoke before removing the edge from this block. @@ -289,10 +289,6 @@ BasicBlock *getInnerUnwindDest(); - void addCalleeLandingPad(LandingPadInst *LPI) { - CalleeLPads.push_back(LPI); - } - LandingPadInst *getLandingPadInst() const { return CallerLPad; } BasicBlock *getSplitLandingPad() { if (SplitLPad) return SplitLPad; @@ -311,11 +307,6 @@ /// to there. void forwardResume(ResumeInst *RI); - /// mergeLandingPadClauses - Visit all of the landing pad instructions which - /// supply the value for the ResumeInst, and merge the clauses from the new - /// destination (the caller's landing pad). - void mergeLandingPadClauses(ResumeInst *RI); - /// addIncomingPHIValuesFor - Add incoming-PHI values to the unwind /// destination block for the given basic block, using the values for the /// original invoke's source block. @@ -436,16 +427,6 @@ return true; } -/// mergeLandingPadClauses - Visit all of the landing pad instructions merge the -/// clauses from the new destination (the caller's landing pad). -void InvokeInliningInfo::mergeLandingPadClauses(ResumeInst *RI) { - for (SmallVectorImpl::iterator - I = CalleeLPads.begin(), E = CalleeLPads.end(); I != E; ++I) - for (unsigned i = 0, e = CallerLPad->getNumClauses(); i != e; ++i) - (*I)->addClause(CallerLPad->getClauseType(i), - CallerLPad->getClauseValue(i)); -} - /// forwardResume - Forward the 'resume' instruction to the caller's landing pad /// block. When the landing pad block has only one predecessor, this is a simple /// branch. When there is more than one predecessor, we need to split the @@ -498,15 +479,19 @@ /// Returns true to indicate that the next block should be skipped. static bool HandleCallsInBlockInlinedThroughInvoke(BasicBlock *BB, InvokeInliningInfo &Invoke) { + LandingPadInst *LPI = Invoke.getLandingPadInst(); + for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) { Instruction *I = BBI++; - // Collect the callee's landingpad instructions. - if (LandingPadInst *LPI = dyn_cast(I)) { - Invoke.addCalleeLandingPad(LPI); - continue; - } - + if (LPI) // FIXME: This won't be NULL in the new EH. + if (LandingPadInst *L = dyn_cast(I)) { + unsigned NumClauses = LPI->getNumClauses(); + L->reserveClauses(NumClauses); + for (unsigned i = 0; i != NumClauses; ++i) + L->addClause(LPI->getClauseType(i), LPI->getClauseValue(i)); + } + // We only need to check for function calls: inlined invoke // instructions require no special handling. CallInst *CI = dyn_cast(I); @@ -642,7 +627,6 @@ } if (ResumeInst *RI = dyn_cast(BB->getTerminator())) { - Invoke.mergeLandingPadClauses(RI); Invoke.forwardResume(RI); } } From chandlerc at google.com Wed Jul 27 22:14:17 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 20:14:17 -0700 Subject: [llvm-commits] [llvm] r136327 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake In-Reply-To: <20110728023334.1F3F32A6C12C@llvm.org> References: <20110728023334.1F3F32A6C12C@llvm.org> Message-ID: On Wed, Jul 27, 2011 at 7:33 PM, Oscar Fuentes wrote: > Updated cmake library dependencies. These dependencies are incorrect. I'm tracking down bugs in how we are automatically computing dependencies related to this, but please revert or I will when I get to it. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/7429a841/attachment.html From chandlerc at google.com Wed Jul 27 22:16:01 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 20:16:01 -0700 Subject: [llvm-commits] [llvm] r136328 - in /llvm/trunk/lib/Target: ARM/MCTargetDesc/CMakeLists.txt MBlaze/MCTargetDesc/CMakeLists.txt MSP430/MCTargetDesc/CMakeLists.txt Mips/MCTargetDesc/CMakeLists.txt PowerPC/MCTargetDesc/CMakeLists.txt X86/MCTargetDesc Message-ID: On Wed, Jul 27, 2011 at 7:33 PM, Oscar Fuentes wrote: > Explicitly declare a library dependency of LLVM*Desc to > LLVM*AsmPrinter. > > GenLibDeps.pl fails to detect vtable references. As this is the only > referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized > builds, the algorithm that creates the list of libraries to be linked > into tools doesn't know about the dependency and sometimes places the > libraries on the wrong order, yielding error messages like this: > Ahh, I see, you handled like this. This really doesn't work. Clearly our automated process is deeply flawed if it can't handle this. Have you been looking at *why* it can't handle it? Are you trying to figure out the root cause? (I have been for the past 2 hours, which is why I haven't committed a fix yet...) -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/7f4650a5/attachment.html From ofv at wanadoo.es Wed Jul 27 23:10:47 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 28 Jul 2011 06:10:47 +0200 Subject: [llvm-commits] [llvm] r136327 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake In-Reply-To: (Chandler Carruth's message of "Wed, 27 Jul 2011 20:14:17 -0700") References: <20110728023334.1F3F32A6C12C@llvm.org> Message-ID: <87zkjzujso.fsf@wanadoo.es> Chandler Carruth writes: > On Wed, Jul 27, 2011 at 7:33 PM, Oscar Fuentes wrote: > >> Updated cmake library dependencies. > > > These dependencies are incorrect. I'm tracking down bugs in how we are > automatically computing dependencies related to this, but please revert or I > will when I get to it. Reverting will cause lots of pain to users who will see how the build automatically updates LLVMLibDeps.cmake, and then the subsequent builds will fail. r136328 adds some explicit library dependencies that makes the build succeed with this change. So let's keep this for now until we figure out a proper fix for the problem. From chandlerc at google.com Wed Jul 27 23:11:19 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 21:11:19 -0700 Subject: [llvm-commits] Switching LLVM CMake build to use explicit dependencies, and completely removing implicit dependency re-generation Message-ID: Oscar, after working for several hours to fix two intertwined bugs in the dependencies generated for LLVM, I can't fix it fully. I can teach the scripts to detect vtable dependencies, but there are other dependencies being missed as well. Fundamentally, the fact that we've had to hack around one implicit dep failure in the CMakeFiles themselves is indicative that this system isn't working. I'm now working on completely removing this aspect of LLVM's CMake build, and replacing it with explicit dependencies, spelled out locally to each CMake target. I think this is the best strategy going forward for the following reasons: 1) It can express dependencies we can't auto-detect such as TableGen dependencies. 2) It isn't subject to optimization levels or toolchains. 3) It is *easier* to update for those not using CMake: the references of note are located locally to the code being changed. 4) Fundamentally, there aren't enough libraries for these to change rapidly or often. Therefore, it seems very unlikely this will be a major maintenance burden (especially compared with the burden of maintaining explicit source file lists). After several discussions on IRC, almost every user of CMake there agreed with this move. Doug and I both have advocated for this for a long time. My plan is to check this in somewhat as an experiment, and explicitly tell non-CMake users to not worry about updating them. Myself and a few others who are constantly using CMake can maintain them and make sure they don't become a huge burden to update. Any objections, shout out now! =D I'm hoping to do this really really soon as my builds and several others are completely broken due to failures not fixed by the patch you committed. -Chandler On Wed, Jul 27, 2011 at 8:16 PM, Chandler Carruth wrote: > On Wed, Jul 27, 2011 at 7:33 PM, Oscar Fuentes wrote: > >> Explicitly declare a library dependency of LLVM*Desc to >> LLVM*AsmPrinter. >> >> GenLibDeps.pl fails to detect vtable references. As this is the only >> referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized >> builds, the algorithm that creates the list of libraries to be linked >> into tools doesn't know about the dependency and sometimes places the >> libraries on the wrong order, yielding error messages like this: >> > > Ahh, I see, you handled like this. > > This really doesn't work. Clearly our automated process is deeply flawed if > it can't handle this. Have you been looking at *why* it can't handle it? Are > you trying to figure out the root cause? > > (I have been for the past 2 hours, which is why I haven't committed a fix > yet...) > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/ddb20007/attachment.html From evan.cheng at apple.com Wed Jul 27 23:19:27 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 27 Jul 2011 21:19:27 -0700 Subject: [llvm-commits] [llvm] r136292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp test/MC/X86/3DNo In-Reply-To: References: Message-ID: <624451E2-3613-41FC-BCB1-13208741A444@apple.com> On Jul 27, 2011, at 5:22 PM, Eli Friedman wrote: > On Wed, Jul 27, 2011 at 4:22 PM, Evan Cheng wrote: >> Modified: llvm/trunk/test/MC/X86/3DNow.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/3DNow.s?rev=136292&r1=136291&r2=136292&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/X86/3DNow.s (original) >> +++ llvm/trunk/test/MC/X86/3DNow.s Wed Jul 27 18:22:03 2011 >> @@ -1,18 +1,18 @@ >> -// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s >> +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s >> >> // PR8283 >> >> // CHECK: pavgusb %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xbf] >> pavgusb %mm2, %mm1 >> >> -// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0xbf] >> +// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf] >> pavgusb 9(%esi,%edx), %mm3 >> >> >> // CHECK: pf2id %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0x1d] >> pf2id %mm2, %mm1 >> >> -// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0x1d] >> +// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d] >> pf2id 9(%esi,%edx), %mm3 > > Err, this seems like an odd place to be testing unusual address-size prefixes... It's not. The tests were using 64-bit registers in 32-bit mode so I changed the triple. Evan > > -Eli From ofv at wanadoo.es Wed Jul 27 23:20:09 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 28 Jul 2011 06:20:09 +0200 Subject: [llvm-commits] [llvm] r136328 - in /llvm/trunk/lib/Target: ARM/MCTargetDesc/CMakeLists.txt MBlaze/MCTargetDesc/CMakeLists.txt MSP430/MCTargetDesc/CMakeLists.txt Mips/MCTargetDesc/CMakeLists.txt PowerPC/MCTargetDesc/CMakeLists.txt X86/MCTargetDesc In-Reply-To: (Chandler Carruth's message of "Wed, 27 Jul 2011 20:16:01 -0700") References: Message-ID: <87vcunujd2.fsf@wanadoo.es> Chandler Carruth writes: > On Wed, Jul 27, 2011 at 7:33 PM, Oscar Fuentes wrote: > >> Explicitly declare a library dependency of LLVM*Desc to >> LLVM*AsmPrinter. >> >> GenLibDeps.pl fails to detect vtable references. As this is the only >> referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized >> builds, the algorithm that creates the list of libraries to be linked >> into tools doesn't know about the dependency and sometimes places the >> libraries on the wrong order, yielding error messages like this: >> > > Ahh, I see, you handled like this. > > This really doesn't work. Clearly our automated process is deeply flawed if > it can't handle this. Have you been looking at *why* it can't handle it? Are > you trying to figure out the root cause? > > (I have been for the past 2 hours, which is why I haven't committed a fix > yet...) Not tried yet. Please note that it affects both build systems. And it is an old bug. I guess that until now when developers who use the traditional system (almost all of them) found this kind of problem while testing before commit, they applied some workaround either in the C++ code or in the makefiles. I don't believe that the cmake build is so unfortunate as for always stumbling on this GenLibDeps.pl bug while the other is happily churning along. From rjmccall at apple.com Wed Jul 27 23:39:49 2011 From: rjmccall at apple.com (John McCall) Date: Wed, 27 Jul 2011 21:39:49 -0700 Subject: [llvm-commits] [llvm] r136313 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: References: <20110728003823.981A52A6C12C@llvm.org> <3FDA960A-E9CD-4ABC-8767-25308BBE4D1E@apple.com> Message-ID: On Jul 27, 2011, at 6:55 PM, Bill Wendling wrote: > On Jul 27, 2011, at 6:23 PM, John McCall wrote: >> +/// mergeLandingPadClauses - Visit all of the landing pad instructions merge the >> +/// clauses from the new destination (the caller's landing pad). >> +void InvokeInliningInfo::mergeLandingPadClauses(ResumeInst *RI) { >> + for (SmallVectorImpl::iterator >> + I = CalleeLPads.begin(), E = CalleeLPads.end(); I != E; ++I) >> + for (unsigned i = 0, e = CallerLPad->getNumClauses(); i != e; ++i) >> + (*I)->addClause(CallerLPad->getClauseType(i), >> + CallerLPad->getClauseValue(i)); >> +} >> >> I don't see the value in queuing up the landingpad instructions here; >> just merge in the caller's clauses as you find them. That would have >> the added advantage of not adding the clauses twice if you find two >> or more resume instructions in the callee. >> >> Also, you're not merging the cleanup bit. >> > Is that the correct semantics? I know I need to keep the cleanup bit on the callee's landingpad instruction, but what about the caller's cleanup bit? Unless the inner landing pad can't resume unwinding, yes; otherwise, the combined landing pad has all the cleanups of both landing pads, so the unwinder needs to land there even if there are no handlers in either landing pad. The minimal example would be an inner function with a catch(int) but no cleanups, and an outer function with cleanups but no handlers. The unwinder has to stop at this landing pad to run the cleanups even if the exception is not an int. Incidentally, that same example also demonstrates a constraint on front-ends that may not be obvious: every landing pad that can resume unwinding must be prepared for the unwinder to "spuriously" land there, even if it has no cleanups, just in case the inliner inlines it into an invoke. If you decide to have a bit on the landingpad instruction that says that it can't resume unwinding, I suggest spelling it "noresume". John. From ofv at wanadoo.es Wed Jul 27 23:49:19 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 28 Jul 2011 06:49:19 +0200 Subject: [llvm-commits] Switching LLVM CMake build to use explicit dependencies, and completely removing implicit dependency re-generation In-Reply-To: (Chandler Carruth's message of "Wed, 27 Jul 2011 21:11:19 -0700") References: Message-ID: <87r55bui0g.fsf@wanadoo.es> Chandler Carruth writes: [snip] > Any objections, shout out now! =D Yes, I have objections. This was already discussed with Doug on the past and I won't waste my time rehashing the topic. Just one observation: it would be a big mistake to not make the same switch on the traditional build as well. Why? because the automatic library dependency detection system is the same and because people will not remember to update the library dependencies in cmake if they are not required to update them in the makefiles too. > I'm hoping to do this really really soon as my builds and several > others are completely broken due to failures not fixed by the patch > you committed. If this change fixes problems with the build (as much as I'll like to see the corresponding bug reports) the Right Thing is to apply it. I retire from the informal role of maintainer of the cmake build, not in disgust, but just due to differences of opinion about how the build must work to provide the best service to its users. As a LLVM user I will be happy as long as the build works. Otherwise I'll mail-bomb you with bug reports :-) From baldrick at free.fr Thu Jul 28 00:28:04 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 28 Jul 2011 07:28:04 +0200 Subject: [llvm-commits] [llvm] r136253 - in /llvm/trunk: docs/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCore/ test/Feature/ In-Reply-To: References: <20110727201805.154E62A6C12C@llvm.org> Message-ID: <4E30F364.80905@free.fr> Hi John, >> --- llvm/trunk/include/llvm-c/Core.h (original) >> +++ llvm/trunk/include/llvm-c/Core.h Wed Jul 27 15:18:04 2011 >> @@ -126,67 +126,69 @@ >> LLVMIndirectBr = 4, >> LLVMInvoke = 5, >> LLVMUnwind = 6, >> - LLVMUnreachable = 7, >> + LLVMResume = 7, >> + LLVMUnreachable = 8, >> >> /* Standard Binary Operators */ >> - LLVMAdd = 8, >> - LLVMFAdd = 9, >> - LLVMSub = 10, >> - LLVMFSub = 11, >> - LLVMMul = 12, >> - LLVMFMul = 13, >> - LLVMUDiv = 14, >> - LLVMSDiv = 15, >> - LLVMFDiv = 16, >> - LLVMURem = 17, >> - LLVMSRem = 18, >> - LLVMFRem = 19, >> + LLVMAdd = 9, >> + LLVMFAdd = 10, >> + LLVMSub = 11, >> + LLVMFSub = 12, >> + LLVMMul = 13, >> + LLVMFMul = 14, >> + LLVMUDiv = 15, >> + LLVMSDiv = 16, >> + LLVMFDiv = 17, >> + LLVMURem = 18, >> + LLVMSRem = 19, >> + LLVMFRem = 20, >> >> /* Logical Operators */ >> - LLVMShl = 20, >> - LLVMLShr = 21, >> - LLVMAShr = 22, >> - LLVMAnd = 23, >> - LLVMOr = 24, >> - LLVMXor = 25, >> + LLVMShl = 21, >> + LLVMLShr = 22, >> + LLVMAShr = 23, >> + LLVMAnd = 24, >> + LLVMOr = 25, >> + LLVMXor = 26, >> >> /* Memory Operators */ >> - LLVMAlloca = 26, >> - LLVMLoad = 27, >> - LLVMStore = 28, >> - LLVMGetElementPtr = 29, >> + LLVMAlloca = 27, >> + LLVMLoad = 28, >> + LLVMStore = 29, >> + LLVMGetElementPtr = 30, >> >> /* Cast Operators */ >> - LLVMTrunc = 30, >> - LLVMZExt = 31, >> - LLVMSExt = 32, >> - LLVMFPToUI = 33, >> - LLVMFPToSI = 34, >> - LLVMUIToFP = 35, >> - LLVMSIToFP = 36, >> - LLVMFPTrunc = 37, >> - LLVMFPExt = 38, >> - LLVMPtrToInt = 39, >> - LLVMIntToPtr = 40, >> - LLVMBitCast = 41, >> + LLVMTrunc = 31, >> + LLVMZExt = 32, >> + LLVMSExt = 33, >> + LLVMFPToUI = 34, >> + LLVMFPToSI = 35, >> + LLVMUIToFP = 36, >> + LLVMSIToFP = 37, >> + LLVMFPTrunc = 38, >> + LLVMFPExt = 39, >> + LLVMPtrToInt = 40, >> + LLVMIntToPtr = 41, >> + LLVMBitCast = 42, >> >> /* Other Operators */ >> - LLVMICmp = 42, >> - LLVMFCmp = 43, >> - LLVMPHI = 44, >> - LLVMCall = 45, >> - LLVMSelect = 46, >> + LLVMICmp = 43, >> + LLVMFCmp = 44, >> + LLVMPHI = 45, >> + LLVMCall = 46, >> + LLVMSelect = 47, >> /* UserOp1 */ >> /* UserOp2 */ >> - LLVMVAArg = 49, >> - LLVMExtractElement = 50, >> - LLVMInsertElement = 51, >> - LLVMShuffleVector = 52, >> - LLVMExtractValue = 53, >> - LLVMInsertValue = 54, >> + LLVMVAArg = 50, >> + LLVMExtractElement = 51, >> + LLVMInsertElement = 52, >> + LLVMShuffleVector = 53, >> + LLVMExtractValue = 54, >> + LLVMInsertValue = 55, >> + LLVMLandingPad = 56, >> >> /* Atomic operators */ >> - LLVMFence = 55 >> + LLVMFence = 57 >> } LLVMOpcode; > > There was just discussion about these values being required to be stable. See r136245 and the review of r136124. > > If we can't just replace UnwindInst, that might force isa to not use a simple range check. The above enum is only for the C binding, nothing in LLVM itself uses it. The enum in Instruction.def *can* be reordered, and that's what's used by (eg) isa, so there shouldn't be a problem. Ciao, Duncan. From baldrick at free.fr Thu Jul 28 00:45:16 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 28 Jul 2011 05:45:16 -0000 Subject: [llvm-commits] [dragonegg] r136334 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110728054516.71DCA2A6C12C@llvm.org> Author: baldrick Date: Thu Jul 28 00:45:16 2011 New Revision: 136334 URL: http://llvm.org/viewvc/llvm-project?rev=136334&view=rev Log: Fix a few places that were making assumptions about the kind of pointer type returned by ConvertType on a pointer. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=136334&r1=136333&r2=136334&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Thu Jul 28 00:45:16 2011 @@ -2413,7 +2413,7 @@ // Perform a cast here if necessary. For example, GCC sometimes forms an // ADDR_EXPR where the operand is an array, and the ADDR_EXPR type is a // pointer to the first element. - return Builder.CreateBitCast(LV.Ptr, ConvertType(TREE_TYPE(exp))); + return Builder.CreateBitCast(LV.Ptr, getRegType(TREE_TYPE(exp))); } Value *TreeToLLVM::EmitCondExpr(tree exp) { @@ -6308,6 +6308,11 @@ return Builder.CreateIntCast(V, RegTy, /*isSigned*/!TYPE_UNSIGNED(type)); } + if (RegTy->isPointerTy()) { + assert(MemTy->isPointerTy() && "Type mismatch!"); + return Builder.CreateBitCast(V, RegTy); + } + if (RegTy->isStructTy()) { assert(TREE_CODE(type) == COMPLEX_TYPE && "Expected a complex type!"); assert(MemTy->isStructTy() && "Type mismatch!"); @@ -6350,6 +6355,11 @@ return Builder.CreateIntCast(V, MemTy, /*isSigned*/!TYPE_UNSIGNED(type)); } + if (MemTy->isPointerTy()) { + assert(RegTy->isPointerTy() && "Type mismatch!"); + return Builder.CreateBitCast(V, MemTy); + } + if (MemTy->isStructTy()) { assert(TREE_CODE(type) == COMPLEX_TYPE && "Expected a complex type!"); assert(RegTy->isStructTy() && "Type mismatch!"); From tobias at grosser.es Thu Jul 28 00:49:02 2011 From: tobias at grosser.es (Tobias Grosser) Date: Thu, 28 Jul 2011 07:49:02 +0200 Subject: [llvm-commits] [PATCH] Fix cmake build Message-ID: <4E30F84E.60106@grosser.es> Hi, at the moment the cmake build is for me still broken. Can I apply the attached patch, which fixes the build for me? I have the feeling those dependences are not wanted and there may be a way to solve this issue better. However, until someone figured out this way, can I commit this patch to fix the build? Cheers Tobi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Fix-cmake-build-that-is-broken-due-to-missing-depend.patch Type: text/x-diff Size: 2348 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110728/abf905c5/attachment.bin From chandlerc at google.com Thu Jul 28 00:57:05 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 22:57:05 -0700 Subject: [llvm-commits] [PATCH] Fix cmake build In-Reply-To: <4E30F84E.60106@grosser.es> References: <4E30F84E.60106@grosser.es> Message-ID: This won't help. This is the issue i'm hitting as well, but even if you apply this, the implicit dependency calculation will run as part of the build and helpfully remove it, breaking teh build again. I'm currently rewriting the entire CMake build system to use explicit dependencies, and will add these deps as part of that. On Wed, Jul 27, 2011 at 10:49 PM, Tobias Grosser wrote: > Hi, > > at the moment the cmake build is for me still broken. Can I apply the > attached patch, which fixes the build for me? > > I have the feeling those dependences are not wanted and there may be a way > to solve this issue better. However, until someone figured out this way, can > I commit this patch to fix the build? > > Cheers > Tobi > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/4364545e/attachment.html From tobias at grosser.es Thu Jul 28 00:59:31 2011 From: tobias at grosser.es (Tobias Grosser) Date: Thu, 28 Jul 2011 07:59:31 +0200 Subject: [llvm-commits] [PATCH] Fix cmake build In-Reply-To: References: <4E30F84E.60106@grosser.es> Message-ID: <4E30FAC3.1020800@grosser.es> On 07/28/2011 07:57 AM, Chandler Carruth wrote: > This won't help. > > This is the issue i'm hitting as well, but even if you apply this, the > implicit dependency calculation will run as part of the build and > helpfully remove it, breaking teh build again. > > I'm currently rewriting the entire CMake build system to use explicit > dependencies, and will add these deps as part of that. Interesting. For me this fixes (at least on my machine, the times I tried it) the build. I don't understand why. Will it hurt to apply this patch? And btw, thanks for working on the overall issue. Cheers Tobi Anyways, From chandlerc at google.com Thu Jul 28 01:02:57 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 23:02:57 -0700 Subject: [llvm-commits] [PATCH] Fix cmake build In-Reply-To: <4E30FAC3.1020800@grosser.es> References: <4E30F84E.60106@grosser.es> <4E30FAC3.1020800@grosser.es> Message-ID: On Wed, Jul 27, 2011 at 10:59 PM, Tobias Grosser wrote: > Interesting. For me this fixes (at least on my machine, the times I tried > it) the build. I don't understand why. Will it hurt to apply this patch? > I don't think so.... however for me, the moment i rebuild, it breaks again, so it seems like churn for no real benefit. To make things more confusing, not all build targets cause a regeneration of the lib deps file... =[ When i've applied this patch locally (which I have for the last 3 hours on and off trying to understand this idiocy) it would go away the first time I ran 'make check'. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/81968185/attachment.html From chandlerc at google.com Thu Jul 28 01:22:40 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 27 Jul 2011 23:22:40 -0700 Subject: [llvm-commits] [PATCH] Fix cmake build In-Reply-To: References: <4E30F84E.60106@grosser.es> <4E30FAC3.1020800@grosser.es> Message-ID: On Wed, Jul 27, 2011 at 11:02 PM, Chandler Carruth wrote: > On Wed, Jul 27, 2011 at 10:59 PM, Tobias Grosser wrote: > >> Interesting. For me this fixes (at least on my machine, the times I tried >> it) the build. I don't understand why. Will it hurt to apply this patch? >> > > I don't think so.... however for me, the moment i rebuild, it breaks again, > so it seems like churn for no real benefit. > Also, to give a concrete timeline, I don't plan to stop working on this until it works for me. I'm hoping to check in a working CMake set of dependencies that builds cleanly, at least on Linux, tonight. I'm somewhat hopeful that with some of the Windows' folks help, we'll have a working build there as well. I think I'm a couple hours out. I have most of the meaty libraries done, and am just mechanically porting the various backends. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110727/8f16402d/attachment.html From baldrick at free.fr Thu Jul 28 01:36:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 28 Jul 2011 06:36:44 -0000 Subject: [llvm-commits] [dragonegg] r136335 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110728063644.DAAFB2A6C12C@llvm.org> Author: baldrick Date: Thu Jul 28 01:36:44 2011 New Revision: 136335 URL: http://llvm.org/viewvc/llvm-project?rev=136335&view=rev Log: Another place that was using the in-memory type for a register. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=136335&r1=136334&r2=136335&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Thu Jul 28 01:36:44 2011 @@ -2441,7 +2441,7 @@ Value *TreeToLLVM::EmitOBJ_TYPE_REF(tree exp) { return Builder.CreateBitCast(EmitRegister(OBJ_TYPE_REF_EXPR(exp)), - ConvertType(TREE_TYPE(exp))); + getRegType(TREE_TYPE(exp))); } /// EmitCONSTRUCTOR - emit the constructor into the location specified by From nicholas at mxc.ca Thu Jul 28 01:48:33 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 28 Jul 2011 06:48:33 -0000 Subject: [llvm-commits] [llvm] r136336 - /llvm/trunk/include/llvm/ADT/DenseMapInfo.h Message-ID: <20110728064833.8542A2A6C12C@llvm.org> Author: nicholas Date: Thu Jul 28 01:48:33 2011 New Revision: 136336 URL: http://llvm.org/viewvc/llvm-project?rev=136336&view=rev Log: In DenseMapInfo> tombstone key, use the tombstone for T and U instead of the empty key for U. This shouldn't really matter because the tombstone key for the pair was still distinct from every other key, but it is odd. Patch by Michael Ilseman! Modified: llvm/trunk/include/llvm/ADT/DenseMapInfo.h Modified: llvm/trunk/include/llvm/ADT/DenseMapInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMapInfo.h?rev=136336&r1=136335&r2=136336&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/DenseMapInfo.h (original) +++ llvm/trunk/include/llvm/ADT/DenseMapInfo.h Thu Jul 28 01:48:33 2011 @@ -142,7 +142,7 @@ } static inline Pair getTombstoneKey() { return std::make_pair(FirstInfo::getTombstoneKey(), - SecondInfo::getEmptyKey()); + SecondInfo::getTombstoneKey()); } static unsigned getHashValue(const Pair& PairVal) { uint64_t key = (uint64_t)FirstInfo::getHashValue(PairVal.first) << 32 @@ -158,7 +158,7 @@ return (unsigned)key; } static bool isEqual(const Pair &LHS, const Pair &RHS) { - return FirstInfo::isEqual(LHS.first, RHS.first) && + return FirstInfo::isEqual(LHS.first, RHS.first) && SecondInfo::isEqual(LHS.second, RHS.second); } }; From isanbard at gmail.com Thu Jul 28 02:26:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 07:26:41 -0000 Subject: [llvm-commits] [llvm] r136338 - /llvm/trunk/lib/VMCore/Instructions.cpp Message-ID: <20110728072641.5E43E2A6C12C@llvm.org> Author: void Date: Thu Jul 28 02:26:41 2011 New Revision: 136338 URL: http://llvm.org/viewvc/llvm-project?rev=136338&view=rev Log: Don't add in the asked for size so that we don't copy too much from the old to new vectors. Modified: llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=136338&r1=136337&r2=136338&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jul 28 02:26:41 2011 @@ -215,9 +215,9 @@ } void LandingPadInst::reserveClauses(unsigned Size) { - unsigned e = getNumOperands() + Size; - if (ReservedSpace >= e) return; - ReservedSpace = e; + unsigned e = getNumOperands(); + if (ReservedSpace >= e + Size) return; + ReservedSpace = e + Size; Use *NewOps = allocHungoffUses(ReservedSpace); Use *OldOps = OperandList; From isanbard at gmail.com Thu Jul 28 02:31:46 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 28 Jul 2011 07:31:46 -0000 Subject: [llvm-commits] [llvm] r136339 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110728073146.50A642A6C12D@llvm.org> Author: void Date: Thu Jul 28 02:31:46 2011 New Revision: 136339 URL: http://llvm.org/viewvc/llvm-project?rev=136339&view=rev Log: Leverage some of the code that John wrote to manage the landing pads. The new EH is more simple in many respects. Mainly, we don't have to worry about the "llvm.eh.exception" and "llvm.eh.selector" calls being in weird places. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=136339&r1=136338&r2=136339&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jul 28 02:31:46 2011 @@ -250,24 +250,29 @@ PHINode *InnerSelectorPHI; SmallVector UnwindDestPHIValues; - PHINode *InnerEHValuesPHI; + // New EH: + BasicBlock *OuterResumeDest; + BasicBlock *InnerResumeDest; LandingPadInst *CallerLPad; + PHINode *InnerEHValuesPHI; BasicBlock *SplitLPad; public: InvokeInliningInfo(InvokeInst *II) : OuterUnwindDest(II->getUnwindDest()), OuterSelector(0), InnerUnwindDest(0), InnerExceptionPHI(0), InnerSelectorPHI(0), - InnerEHValuesPHI(0), CallerLPad(0), SplitLPad(0) { + + OuterResumeDest(II->getUnwindDest()), InnerResumeDest(0), + CallerLPad(0), InnerEHValuesPHI(0), SplitLPad(0) { // If there are PHI nodes in the unwind destination block, we // need to keep track of which values came into them from the // invoke before removing the edge from this block. - llvm::BasicBlock *invokeBB = II->getParent(); + llvm::BasicBlock *InvokeBB = II->getParent(); BasicBlock::iterator I = OuterUnwindDest->begin(); for (; isa(I); ++I) { // Save the value to use for this edge. - PHINode *phi = cast(I); - UnwindDestPHIValues.push_back(phi->getIncomingValueForBlock(invokeBB)); + PHINode *PHI = cast(I); + UnwindDestPHIValues.push_back(PHI->getIncomingValueForBlock(InvokeBB)); } // FIXME: With the new EH, this if/dyn_cast should be a 'cast'. @@ -288,6 +293,7 @@ } BasicBlock *getInnerUnwindDest(); + BasicBlock *getInnerUnwindDest_new(); LandingPadInst *getLandingPadInst() const { return CallerLPad; } BasicBlock *getSplitLandingPad() { @@ -316,8 +322,8 @@ void addIncomingPHIValuesForInto(BasicBlock *src, BasicBlock *dest) const { BasicBlock::iterator I = dest->begin(); for (unsigned i = 0, e = UnwindDestPHIValues.size(); i != e; ++i, ++I) { - PHINode *phi = cast(I); - phi->addIncoming(UnwindDestPHIValues[i], src); + PHINode *PHI = cast(I); + PHI->addIncoming(UnwindDestPHIValues[i], src); } } }; @@ -427,38 +433,56 @@ return true; } +/// Get or create a target for the branch from ResumeInsts. +BasicBlock *InvokeInliningInfo::getInnerUnwindDest_new() { + if (InnerResumeDest) return InnerResumeDest; + + // Split the landing pad. + BasicBlock::iterator SplitPoint = CallerLPad; ++SplitPoint; + InnerResumeDest = + OuterResumeDest->splitBasicBlock(SplitPoint, + OuterResumeDest->getName() + ".body"); + + // The number of incoming edges we expect to the inner landing pad. + const unsigned PHICapacity = 2; + + // Create corresponding new PHIs for all the PHIs in the outer landing pad. + BasicBlock::iterator InsertPoint = InnerResumeDest->begin(); + BasicBlock::iterator I = OuterRes
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