From baldrick at free.fr  Mon Aug 15 03:20:05 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 15 Aug 2011 08:20:05 -0000
Subject: [llvm-commits] [dragonegg] r137606 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110815082005.50D142A6C12D@llvm.org>

Author: baldrick
Date: Mon Aug 15 03:20:05 2011
New Revision: 137606

URL: http://llvm.org/viewvc/llvm-project?rev=137606&view=rev
Log:
When processing a constructor and default initializing the fields
which did not get an explicit constructor entry, default initialize
in reverse order to ensure that the first field of a union is always
default initialized.  This is a theoretical fix since I failed to
construct a testcase for which this made a difference.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=137606&r1=137605&r2=137606&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Mon Aug 15 03:20:05 2011
@@ -1076,9 +1076,18 @@
   // initial value is supplied for a field then the value will overwrite and
   // replace the zero starting value later.
   if (flag_default_initialize_globals) {
+    // Process the fields in reverse order.  This is for the benefit of union
+    // types for which the first field must be default initialized (iterating
+    // in forward order would default initialize the last field).
+    SmallVector<tree, 16> Fields;
     for (tree field = TYPE_FIELDS(TREE_TYPE(exp)); field;
          field = TREE_CHAIN(field)) {
       assert(TREE_CODE(field) == FIELD_DECL && "Lang data not freed?");
+      Fields.push_back(field);
+    }
+    for (SmallVector<tree, 16>::reverse_iterator I = Fields.rbegin(),
+         E = Fields.rend(); I != E; ++I) {
+      tree field = *I;
       // If the field has variable or unknown position then it cannot be default
       // initialized - skip it.
       if (!OffsetIsLLVMCompatible(field))



From wendling at apple.com  Mon Aug 15 03:31:33 2011
From: wendling at apple.com (Bill Wendling)
Date: Mon, 15 Aug 2011 01:31:33 -0700
Subject: [llvm-commits] [PATCH] DWARF EH Prepare for the New EH
Message-ID: <FE861719-0915-4664-B9FA-46DE5945269D@apple.com>

This is a patch for the DwarfEHPrepare.cpp file to support the new EH model. It's very straight-forward. Any 'resume' instruction in the function is turned into a call to the appropriate "_Unwind_Resume()". The rest of the module isn't needed (and will be removed once we switch over) because of the lovely invariants. :-)

Please review and let me know if you have any comments.

-bw

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From raghesh.a at gmail.com  Mon Aug 15 04:37:46 2011
From: raghesh.a at gmail.com (Raghesh Aloor)
Date: Mon, 15 Aug 2011 09:37:46 -0000
Subject: [llvm-commits] [polly] r137607 -
	/polly/trunk/www/documentation/memaccess.html
Message-ID: <20110815093746.9F41D2A6C12C@llvm.org>

Author: raghesh
Date: Mon Aug 15 04:37:46 2011
New Revision: 137607

URL: http://llvm.org/viewvc/llvm-project?rev=137607&view=rev
Log:
www: Updating memaccess Documentation


Modified:
    polly/trunk/www/documentation/memaccess.html

Modified: polly/trunk/www/documentation/memaccess.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=137607&r1=137606&r2=137607&view=diff
==============================================================================
--- polly/trunk/www/documentation/memaccess.html (original)
+++ polly/trunk/www/documentation/memaccess.html Mon Aug 15 04:37:46 2011
@@ -85,6 +85,24 @@
 <h3>Step 2</h3>
 Update the code generation module to reflect the access function change made
 in Step 1.
+<h3>Step 2.1 Code generation for a constant</h3>
+In the JSCOP file an access function which has variables is changed to a
+constant. Code is generated to reflect this change. Let the content of original
+JSCOP file be:
+<pre>
+"accesses" : [{
+        "kind" : "read",
+                 "relation" : "{ Stmt_for_body[i0] -> MemRef_A[i0] }"
+}]
+</pre>
+The transformed JSCOP file is:
+<pre>
+"accesses" : [{
+        "kind" : "read",
+                 "relation" : "{ Stmt_for_body[i0] -> MemRef_A[10] }"
+}]
+</pre>
+Code is generated for this change.
 </div>
 </body>
 </html>



From geek4civic at gmail.com  Mon Aug 15 04:49:50 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Mon, 15 Aug 2011 18:49:50 +0900
Subject: [llvm-commits] [PATCH] CrashRecoveryContext.cpp Win32 support
In-Reply-To: <CAAt6xTtrnZMDaBwYtNYz=SymNssyNWcN9RhXSgr4mN8StMwgdQ@mail.gmail.com>
References: <CAAt6xTtrnZMDaBwYtNYz=SymNssyNWcN9RhXSgr4mN8StMwgdQ@mail.gmail.com>
Message-ID: <CADiQthOCqtc5CZ+uwncJdvwBN6OEYBRmSh0sVspmWaPE_ifEpw@mail.gmail.com>

Aaron and Anton,

Aaron's patch is good at functionality but a little redundant due to
considering w2k.

Anton, I propose it would be the time for us to abandon Windows 2000
to coming llvm 3.0.
It was 20th Century System :D
How do you think?

Aaron, do you think your patch would be simpler if we could get rid of w2k?
(oc, I think so)

...Takumi


2011/8/8 Aaron Ballman <aaron at aaronballman.com>:
> Hello! ?I noticed there was a "fixme" listed in
> CrashRecoveryContext.cpp and that some Win32 support was needed. ?I
> believe this patch will solve the issue. ?I have tested it with Visual
> Studio 2010, and MinGW gcc 4.5.2 and the behavior is the same as what
> I get on OS X.
>
> I was unable to get the test suite to run in my environment (had all
> the prerequisites installed, followed the instructions on the site),
> so I've not been able to run this against the suite.
>
> One thing to note about this patch is that is only provides support
> for Windows XP and higher. ?Trying to support older versions of
> Windows is possible (Win2k and higher) but comes with more pitfalls
> (as noted in the comments).
>
> If you have any questions, please ask!
>
> ~Aaron
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From aaron at aaronballman.com  Mon Aug 15 07:16:49 2011
From: aaron at aaronballman.com (Aaron Ballman)
Date: Mon, 15 Aug 2011 07:16:49 -0500
Subject: [llvm-commits] [PATCH] CrashRecoveryContext.cpp Win32 support
In-Reply-To: <CADiQthOCqtc5CZ+uwncJdvwBN6OEYBRmSh0sVspmWaPE_ifEpw@mail.gmail.com>
References: <CAAt6xTtrnZMDaBwYtNYz=SymNssyNWcN9RhXSgr4mN8StMwgdQ@mail.gmail.com>
	<CADiQthOCqtc5CZ+uwncJdvwBN6OEYBRmSh0sVspmWaPE_ifEpw@mail.gmail.com>
Message-ID: <CAAt6xTuZiRH-jjDvcrf-c8sjNjbQ=eH2QtfnG2udW7pOCTkv1A@mail.gmail.com>

On Mon, Aug 15, 2011 at 4:49 AM, NAKAMURA Takumi <geek4civic at gmail.com> wrote:
> Aaron and Anton,
>
> Aaron's patch is good at functionality but a little redundant due to
> considering w2k.
>
> Anton, I propose it would be the time for us to abandon Windows 2000
> to coming llvm 3.0.
> It was 20th Century System :D
> How do you think?
>
> Aaron, do you think your patch would be simpler if we could get rid of w2k?
> (oc, I think so)

I was unsure of how far back we wanted support to extend, which is why
I lazy-loaded the code.  If we're going to support XP and higher, the
code would be cleaner.

I'll make the modifications tonight and resubmit.

Thanks for the review!

~Aaron

From james.molloy at arm.com  Mon Aug 15 09:22:33 2011
From: james.molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 15:22:33 +0100
Subject: [llvm-commits] [PATCH] Fixes in ARM TableGen
Message-ID: <002401cc5b56$c62a0760$527e1620$@molloy@arm.com>

Hi,

 

The attached patch does three things (they're each so small I kept them in
the same patch file - hope this is OK):

 

.         Fix the field offsets for UMAAL - RdHi and RdLo were the incorrect
way around (see A8.6.244). This required a fix to a test.

.         Set the DecoderMethod for STRH (and other addrmode3 stores)
correctly.

.         Remove two pieces of dead code - class AI3stridx and class AIsthpr
in ARMInstrFormats.td were not used anywhere.

 

Cheers,

 

James
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From james.molloy at arm.com  Mon Aug 15 09:23:34 2011
From: james.molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 15:23:34 +0100
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
Message-ID: <002a01cc5b56$eaa99880$bffcc980$@molloy@arm.com>

Hi,

 

The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode.
Testcase added.

 

Cheers,

 

James
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From james.molloy at arm.com  Mon Aug 15 09:50:12 2011
From: james.molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 15:50:12 +0100
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd Rt
	field
Message-ID: <003001cc5b5a$a30611d0$e9123570$@molloy@arm.com>

Hi,

 

The attached patch causes decoding to fail if the Rt field of an LDRD/STRD
is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.

 

I wanted to add an assert to the encoder too, but couldn't see an obvious
way to do this as the Rt field is decoded by the generic
"getMachineOpValue()" function direct from tablegen.

 

Cheers,

 

James

 
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From criswell at uiuc.edu  Mon Aug 15 09:52:04 2011
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 15 Aug 2011 14:52:04 -0000
Subject: [llvm-commits] [poolalloc] r137609 - in /poolalloc/trunk/lib:
 AssistDS/Makefile DSA/Makefile PoolAllocate/Makefile
Message-ID: <20110815145204.B683B2A6C12C@llvm.org>

Author: criswell
Date: Mon Aug 15 09:52:04 2011
New Revision: 137609

URL: http://llvm.org/viewvc/llvm-project?rev=137609&view=rev
Log:
Disable building of dynamic libraries because it breaks the build on Mac OS X.
I'll have to determine how to fix it since having dynamic libraries is valuable.

Modified:
    poolalloc/trunk/lib/AssistDS/Makefile
    poolalloc/trunk/lib/DSA/Makefile
    poolalloc/trunk/lib/PoolAllocate/Makefile

Modified: poolalloc/trunk/lib/AssistDS/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/Makefile?rev=137609&r1=137608&r2=137609&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/Makefile (original)
+++ poolalloc/trunk/lib/AssistDS/Makefile Mon Aug 15 09:52:04 2011
@@ -10,7 +10,7 @@
 LEVEL = ../..
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-SHARED_LIBRARY=1
+#SHARED_LIBRARY=1
 endif
 endif
 LIBRARYNAME = AssistDS

Modified: poolalloc/trunk/lib/DSA/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Makefile?rev=137609&r1=137608&r2=137609&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Makefile (original)
+++ poolalloc/trunk/lib/DSA/Makefile Mon Aug 15 09:52:04 2011
@@ -12,7 +12,7 @@
 BUILD_ARCHIVE := 1
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-SHARED_LIBRARY := 1
+#SHARED_LIBRARY := 1
 #LOADABLE_MODULE := 1
 endif
 endif

Modified: poolalloc/trunk/lib/PoolAllocate/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Makefile?rev=137609&r1=137608&r2=137609&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Makefile (original)
+++ poolalloc/trunk/lib/PoolAllocate/Makefile Mon Aug 15 09:52:04 2011
@@ -10,7 +10,7 @@
 BUILD_ARCHIVE := 1
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-SHARED_LIBRARY := 1
+#SHARED_LIBRARY := 1
 #LOADABLE_MODULE := 1
 endif
 endif



From criswell at uiuc.edu  Mon Aug 15 10:47:11 2011
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 15 Aug 2011 15:47:11 -0000
Subject: [llvm-commits] [poolalloc] r137610 - in /poolalloc/trunk/runtime:
 DynCount/Makefile DynamicTypeChecks/Makefile FL2Allocator/Makefile
 FreeListAllocator/Makefile HeapFrag/Makefile PreRT/Makefile
Message-ID: <20110815154711.1A0E22A6C12C@llvm.org>

Author: criswell
Date: Mon Aug 15 10:47:10 2011
New Revision: 137610

URL: http://llvm.org/viewvc/llvm-project?rev=137610&view=rev
Log:
Fixed compilation on Mac OS X by disabling bitcode libraries for only that
platform.  XCode has its own llvm-gcc that the LLVM build system finds and
tries to use.  Disabling bitcode libraries seems to be the easiest fix.
Also modified one of the Makefiles so that LOADABLE_MODULE and SHARED_LIBRARY
are defined together; this seems necessary for building dynamically loadable
modules on Mac OS X.

Modified:
    poolalloc/trunk/runtime/DynCount/Makefile
    poolalloc/trunk/runtime/DynamicTypeChecks/Makefile
    poolalloc/trunk/runtime/FL2Allocator/Makefile
    poolalloc/trunk/runtime/FreeListAllocator/Makefile
    poolalloc/trunk/runtime/HeapFrag/Makefile
    poolalloc/trunk/runtime/PreRT/Makefile

Modified: poolalloc/trunk/runtime/DynCount/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynCount/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynCount/Makefile (original)
+++ poolalloc/trunk/runtime/DynCount/Makefile Mon Aug 15 10:47:10 2011
@@ -1,6 +1,5 @@
 LEVEL = ../..
 LIBRARYNAME=count
-BYTECODE_LIBRARY=1
 
 #
 # Build shared libraries on all platforms except Cygwin and MingW (which do
@@ -21,5 +20,14 @@
 CXX.Flags += -fno-threadsafe-statics
 include $(LEVEL)/Makefile.common
 
+#
+# Do not build bitcode library on Mac OS X; XCode will pre-install llvm-gcc,
+# and that can cause the build to fail if it doesn't match the current version
+# of LLVM.
+#
+ifneq ($(OS),Darwin)
+BYTECODE_LIBRARY=1
+endif
+
 # Always build optimized and debug versions
 all:: $(LIBNAME_OBJO) $(LIBNAME_OBJG)

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/Makefile (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/Makefile Mon Aug 15 10:47:10 2011
@@ -1,10 +1,14 @@
 LEVEL = ../..
 LIBRARYNAME = typechecks_rt
-BYTECODE_LIBRARY=1
 
+#
+# Don't build shared libraries on Windows.  Note that we need to specify
+# both SHARED_LIBRARY and LOADABLE_MODULE on Mac OS X.
+#
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
 SHARED_LIBRARY=1
+LOADABLE_MODULE := 1
 endif
 endif
 
@@ -14,5 +18,14 @@
 
 include $(LEVEL)/Makefile.common
 
+#
+# Do not build bitcode library on Mac OS X; XCode will pre-install llvm-gcc,
+# and that can cause the build to fail if it doesn't match the current version
+# of LLVM.
+#
+ifneq ($(OS),Darwin)
+BYTECODE_LIBRARY=1
+endif
+
 # Always build optimized and debug versions
 all:: $(LIBNAME_OBJO) $(LIBNAME_OBJG)

Modified: poolalloc/trunk/runtime/FL2Allocator/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/FL2Allocator/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/FL2Allocator/Makefile (original)
+++ poolalloc/trunk/runtime/FL2Allocator/Makefile Mon Aug 15 10:47:10 2011
@@ -1,6 +1,5 @@
 LEVEL = ../..
 LIBRARYNAME=poolalloc_rt
-BYTECODE_LIBRARY=1
 
 #
 # Build shared libraries on all platforms except Cygwin and MingW (which do
@@ -20,3 +19,12 @@
 
 include $(LEVEL)/Makefile.common
 
+#
+# Do not build bitcode library on Mac OS X; XCode will pre-install llvm-gcc,
+# and that can cause the build to fail if it doesn't match the current version
+# of LLVM.
+#
+ifneq ($(OS),Darwin)
+BYTECODE_LIBRARY=1
+endif
+

Modified: poolalloc/trunk/runtime/FreeListAllocator/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/FreeListAllocator/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/FreeListAllocator/Makefile (original)
+++ poolalloc/trunk/runtime/FreeListAllocator/Makefile Mon Aug 15 10:47:10 2011
@@ -7,7 +7,8 @@
 #
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-SHARED_LIBRARY=1
+#SHARED_LIBRARY=1
+#LOADABLE_MODULE := 1
 endif
 endif
 

Modified: poolalloc/trunk/runtime/HeapFrag/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/HeapFrag/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/HeapFrag/Makefile (original)
+++ poolalloc/trunk/runtime/HeapFrag/Makefile Mon Aug 15 10:47:10 2011
@@ -1,8 +1,6 @@
 LEVEL = ../..
 LIBRARYNAME=heapfrag
 
-#BYTECODE_LIBRARY=1
-
 #
 # Build shared libraries on all platforms except Cygwin and MingW (which do
 # not support them).
@@ -15,5 +13,14 @@
 
 include $(LEVEL)/Makefile.common
 
+#
+# Do not build bitcode library on Mac OS X; XCode will pre-install llvm-gcc,
+# and that can cause the build to fail if it doesn't match the current version
+# of LLVM.
+#
+ifneq ($(OS),Darwin)
+BYTECODE_LIBRARY=1
+endif
+
 # Always build optimized and debug versions
 all:: $(LIBNAME_OBJO) $(LIBNAME_OBJG)

Modified: poolalloc/trunk/runtime/PreRT/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/PreRT/Makefile?rev=137610&r1=137609&r2=137610&view=diff
==============================================================================
--- poolalloc/trunk/runtime/PreRT/Makefile (original)
+++ poolalloc/trunk/runtime/PreRT/Makefile Mon Aug 15 10:47:10 2011
@@ -1,6 +1,14 @@
 LEVEL = ../..
 LIBRARYNAME=pa_pre_rt
-BYTECODE_LIBRARY=1
 
 include $(LEVEL)/Makefile.common
 
+#
+# Do not build bitcode library on Mac OS X; XCode will pre-install llvm-gcc,
+# and that can cause the build to fail if it doesn't match the current version
+# of LLVM.
+#
+ifneq ($(OS),Darwin)
+BYTECODE_LIBRARY=1
+endif
+



From criswell at uiuc.edu  Mon Aug 15 10:54:00 2011
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 15 Aug 2011 15:54:00 -0000
Subject: [llvm-commits] [poolalloc] r137611 - in /poolalloc/trunk/lib:
 AssistDS/Makefile DSA/Makefile PoolAllocate/Makefile
Message-ID: <20110815155400.CED8D2A6C12C@llvm.org>

Author: criswell
Date: Mon Aug 15 10:54:00 2011
New Revision: 137611

URL: http://llvm.org/viewvc/llvm-project?rev=137611&view=rev
Log:
Always enable LOADABLE_MODULE and SHARED_LIBRARY together so that compilation
works on Mac OS X.

Modified:
    poolalloc/trunk/lib/AssistDS/Makefile
    poolalloc/trunk/lib/DSA/Makefile
    poolalloc/trunk/lib/PoolAllocate/Makefile

Modified: poolalloc/trunk/lib/AssistDS/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/Makefile?rev=137611&r1=137610&r2=137611&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/Makefile (original)
+++ poolalloc/trunk/lib/AssistDS/Makefile Mon Aug 15 10:54:00 2011
@@ -10,7 +10,8 @@
 LEVEL = ../..
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-#SHARED_LIBRARY=1
+SHARED_LIBRARY=1
+LOADABLE_MODULE=1
 endif
 endif
 LIBRARYNAME = AssistDS

Modified: poolalloc/trunk/lib/DSA/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Makefile?rev=137611&r1=137610&r2=137611&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Makefile (original)
+++ poolalloc/trunk/lib/DSA/Makefile Mon Aug 15 10:54:00 2011
@@ -12,8 +12,8 @@
 BUILD_ARCHIVE := 1
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-#SHARED_LIBRARY := 1
-#LOADABLE_MODULE := 1
+SHARED_LIBRARY := 1
+LOADABLE_MODULE := 1
 endif
 endif
 

Modified: poolalloc/trunk/lib/PoolAllocate/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Makefile?rev=137611&r1=137610&r2=137611&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Makefile (original)
+++ poolalloc/trunk/lib/PoolAllocate/Makefile Mon Aug 15 10:54:00 2011
@@ -10,8 +10,8 @@
 BUILD_ARCHIVE := 1
 ifneq ($(OS),Cygwin)
 ifneq ($(OS),MingW)
-#SHARED_LIBRARY := 1
-#LOADABLE_MODULE := 1
+SHARED_LIBRARY := 1
+LOADABLE_MODULE := 1
 endif
 endif
 



From greened at obbligato.org  Mon Aug 15 11:29:17 2011
From: greened at obbligato.org (David A. Greene)
Date: Mon, 15 Aug 2011 11:29:17 -0500
Subject: [llvm-commits] [llvm] r137232 - in /llvm/trunk/utils/TableGen:
	Record.cpp Record.h TGParser.cpp
In-Reply-To: <nngliuznan1.fsf@transit.us.cray.com> (David A. Greene's message
	of "Thu, 11 Aug 2011 12:03:30 -0500")
References: <20110810182747.24D1D2A6C12D@llvm.org>
	<FA7FB8AC-43A4-4ECC-B78E-799E252E7698@apple.com>
	<nng62m5nj38.fsf@transit.us.cray.com>
	<A7CCFD41-C0FF-45F3-A2A9-DA142A39ED15@apple.com>
	<nngliuznan1.fsf@transit.us.cray.com>
Message-ID: <nngty9iljtu.fsf@transit.us.cray.com>

greened at obbligato.org (David A. Greene) writes:

> Fair enough.  Here's a moderately complex example.  Take HADDPD.  The
> way we have this specified in our X86InstrSIMD.td file looks like
> this:

Ping?

                           -Dave

From grosbach at apple.com  Mon Aug 15 11:52:25 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 16:52:25 -0000
Subject: [llvm-commits] [llvm] r137615 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20110815165225.286852A6C12C@llvm.org>

Author: grosbach
Date: Mon Aug 15 11:52:24 2011
New Revision: 137615

URL: http://llvm.org/viewvc/llvm-project?rev=137615&view=rev
Log:
Update comment to reflect MC target machine refactor.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137615&r1=137614&r2=137615&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 15 11:52:24 2011
@@ -240,7 +240,7 @@
   // If this is a pseudo instruction, mark it isCodeGenOnly.
   let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
 
-  // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
+  // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
   let TSFlags{4-0}   = AM.Value;
   let TSFlags{6-5}   = IndexModeBits;
   let TSFlags{12-7} = Form;



From dpatel at apple.com  Mon Aug 15 12:24:54 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 17:24:54 -0000
Subject: [llvm-commits] [llvm] r137618 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfCompileUnit.h
 DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815172454.7F4192A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 12:24:54 2011
New Revision: 137618

URL: http://llvm.org/viewvc/llvm-project?rev=137618&view=rev
Log:
Refactor. A subprogram is part of compile unit so let CompileUnit construct new subprogram.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=137618&r1=137617&r2=137618&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Aug 15 12:24:54 2011
@@ -564,7 +564,7 @@
     DIE *ContextDIE = getOrCreateNameSpace(DINameSpace(Context));
     ContextDIE->addChild(Die);
   } else if (Context.isSubprogram()) {
-    DIE *ContextDIE = DD->createSubprogramDIE(DISubprogram(Context));
+    DIE *ContextDIE = getOrCreateSubprogramDIE(DISubprogram(Context));
     ContextDIE->addChild(Die);
   } else if (DIE *ContextDIE = getDIE(Context))
     ContextDIE->addChild(Die);
@@ -761,7 +761,7 @@
       DIE *ElemDie = NULL;
       if (Element.isSubprogram()) {
         DISubprogram SP(Element);
-        ElemDie = DD->createSubprogramDIE(DISubprogram(Element));
+        ElemDie = getOrCreateSubprogramDIE(DISubprogram(Element));
         if (SP.isProtected())
           addUInt(ElemDie, dwarf::DW_AT_accessibility, dwarf::DW_FORM_flag,
                   dwarf::DW_ACCESS_protected);
@@ -889,6 +889,111 @@
   return NDie;
 }
 
+/// getRealLinkageName - If special LLVM prefix that is used to inform the asm
+/// printer to not emit usual symbol prefix before the symbol name is used then
+/// return linkage name after skipping this special LLVM prefix.
+static StringRef getRealLinkageName(StringRef LinkageName) {
+  char One = '\1';
+  if (LinkageName.startswith(StringRef(&One, 1)))
+    return LinkageName.substr(1);
+  return LinkageName;
+}
+
+/// getOrCreateSubprogramDIE - Create new DIE using SP.
+DIE *CompileUnit::getOrCreateSubprogramDIE(DISubprogram SP) {
+  DIE *SPDie = getDIE(SP);
+  if (SPDie)
+    return SPDie;
+
+  SPDie = new DIE(dwarf::DW_TAG_subprogram);
+  
+  // DW_TAG_inlined_subroutine may refer to this DIE.
+  insertDIE(SP, SPDie);
+  
+  // Add to context owner.
+  addToContextOwner(SPDie, SP.getContext());
+
+  // Add function template parameters.
+  addTemplateParams(*SPDie, SP.getTemplateParams());
+
+  StringRef LinkageName = SP.getLinkageName();
+  if (!LinkageName.empty())
+    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, 
+                    dwarf::DW_FORM_string,
+                    getRealLinkageName(LinkageName));
+
+  // If this DIE is going to refer declaration info using AT_specification
+  // then there is no need to add other attributes.
+  if (SP.getFunctionDeclaration().isSubprogram())
+    return SPDie;
+
+  // Constructors and operators for anonymous aggregates do not have names.
+  if (!SP.getName().empty())
+    addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, 
+                    SP.getName());
+
+  addSourceLine(SPDie, SP);
+
+  if (SP.isPrototyped()) 
+    addUInt(SPDie, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1);
+
+  // Add Return Type.
+  DICompositeType SPTy = SP.getType();
+  DIArray Args = SPTy.getTypeArray();
+  unsigned SPTag = SPTy.getTag();
+
+  if (Args.getNumElements() == 0 || SPTag != dwarf::DW_TAG_subroutine_type)
+    addType(SPDie, SPTy);
+  else
+    addType(SPDie, DIType(Args.getElement(0)));
+
+  unsigned VK = SP.getVirtuality();
+  if (VK) {
+    addUInt(SPDie, dwarf::DW_AT_virtuality, dwarf::DW_FORM_flag, VK);
+    DIEBlock *Block = getDIEBlock();
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
+    addUInt(Block, 0, dwarf::DW_FORM_udata, SP.getVirtualIndex());
+    addBlock(SPDie, dwarf::DW_AT_vtable_elem_location, 0, Block);
+    ContainingTypeMap.insert(std::make_pair(SPDie,
+                                            SP.getContainingType()));
+  }
+
+  if (!SP.isDefinition()) {
+    addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
+    
+    // Add arguments. Do not add arguments for subprogram definition. They will
+    // be handled while processing variables.
+    DICompositeType SPTy = SP.getType();
+    DIArray Args = SPTy.getTypeArray();
+    unsigned SPTag = SPTy.getTag();
+
+    if (SPTag == dwarf::DW_TAG_subroutine_type)
+      for (unsigned i = 1, N =  Args.getNumElements(); i < N; ++i) {
+        DIE *Arg = new DIE(dwarf::DW_TAG_formal_parameter);
+        DIType ATy = DIType(DIType(Args.getElement(i)));
+        addType(Arg, ATy);
+        if (ATy.isArtificial())
+          addUInt(Arg, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1);
+        SPDie->addChild(Arg);
+      }
+  }
+
+  if (SP.isArtificial())
+    addUInt(SPDie, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1);
+
+  if (!SP.isLocalToUnit())
+    addUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
+
+  if (SP.isOptimized())
+    addUInt(SPDie, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
+
+  if (unsigned isa = Asm->getISAEncoding()) {
+    addUInt(SPDie, dwarf::DW_AT_APPLE_isa, dwarf::DW_FORM_flag, isa);
+  }
+
+  return SPDie;
+}
+
 /// constructSubrangeDIE - Construct subrange DIE from DISubrange.
 void CompileUnit::constructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){
   DIE *DW_Subrange = new DIE(dwarf::DW_TAG_subrange_type);
@@ -953,6 +1058,20 @@
   return Enumerator;
 }
 
+/// constructContainingTypeDIEs - Construct DIEs for types that contain
+/// vtables.
+void CompileUnit::constructContainingTypeDIEs() {
+  for (DenseMap<DIE *, const MDNode *>::iterator CI = ContainingTypeMap.begin(),
+         CE = ContainingTypeMap.end(); CI != CE; ++CI) {
+    DIE *SPDie = CI->first;
+    const MDNode *N = CI->second;
+    if (!N) continue;
+    DIE *NDie = getDIE(N);
+    if (!NDie) continue;
+    addDIEEntry(SPDie, dwarf::DW_AT_containing_type, dwarf::DW_FORM_ref4, NDie);
+  }
+}
+
 /// createMemberDIE - Create new member DIE.
 DIE *CompileUnit::createMemberDIE(DIDerivedType DT) {
   DIE *MemberDie = new DIE(DT.getTag());

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=137618&r1=137617&r2=137618&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Mon Aug 15 12:24:54 2011
@@ -67,6 +67,11 @@
   /// DIEBlocks - A list of all the DIEBlocks in use.
   std::vector<DIEBlock *> DIEBlocks;
 
+  /// ContainingTypeMap - This map is used to keep track of subprogram DIEs that
+  /// need DW_AT_containing_type attribute. This attribute points to a DIE that
+  /// corresponds to the MDNode mapped with the subprogram DIE.
+  DenseMap<DIE *, const MDNode *> ContainingTypeMap;
+
 public:
   CompileUnit(unsigned I, DIE *D, AsmPrinter *A, DwarfDebug *DW);
   ~CompileUnit();
@@ -226,6 +231,9 @@
   /// getOrCreateNameSpace - Create a DIE for DINameSpace.
   DIE *getOrCreateNameSpace(DINameSpace NS);
 
+  /// getOrCreateSubprogramDIE - Create new DIE using SP.
+  DIE *getOrCreateSubprogramDIE(DISubprogram SP);
+
   /// getOrCreateTypeDIE - Find existing DIE or create new DIE for the
   /// given DIType.
   DIE *getOrCreateTypeDIE(DIType Ty);
@@ -266,6 +274,10 @@
   /// constructEnumTypeDIE - Construct enum type DIE from DIEnumerator.
   DIE *constructEnumTypeDIE(DIEnumerator ETy);
 
+  /// constructContainingTypeDIEs - Construct DIEs for types that contain
+  /// vtables.
+  void constructContainingTypeDIEs();
+
   /// createMemberDIE - Create new member DIE.
   DIE *createMemberDIE(DIDerivedType DT);
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137618&r1=137617&r2=137618&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 12:24:54 2011
@@ -179,102 +179,6 @@
   return LinkageName;
 }
 
-/// createSubprogramDIE - Create new DIE using SP.
-DIE *DwarfDebug::createSubprogramDIE(DISubprogram SP) {
-  CompileUnit *SPCU = getCompileUnit(SP);
-  DIE *SPDie = SPCU->getDIE(SP);
-  if (SPDie)
-    return SPDie;
-
-  SPDie = new DIE(dwarf::DW_TAG_subprogram);
-  
-  // DW_TAG_inlined_subroutine may refer to this DIE.
-  SPCU->insertDIE(SP, SPDie);
-  
-  // Add to context owner.
-  SPCU->addToContextOwner(SPDie, SP.getContext());
-
-  // Add function template parameters.
-  SPCU->addTemplateParams(*SPDie, SP.getTemplateParams());
-
-  StringRef LinkageName = SP.getLinkageName();
-  if (!LinkageName.empty())
-    SPCU->addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, 
-                    dwarf::DW_FORM_string,
-                    getRealLinkageName(LinkageName));
-
-  // If this DIE is going to refer declaration info using AT_specification
-  // then there is no need to add other attributes.
-  if (SP.getFunctionDeclaration().isSubprogram())
-    return SPDie;
-
-  // Constructors and operators for anonymous aggregates do not have names.
-  if (!SP.getName().empty())
-    SPCU->addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, 
-                    SP.getName());
-
-  SPCU->addSourceLine(SPDie, SP);
-
-  if (SP.isPrototyped()) 
-    SPCU->addUInt(SPDie, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1);
-
-  // Add Return Type.
-  DICompositeType SPTy = SP.getType();
-  DIArray Args = SPTy.getTypeArray();
-  unsigned SPTag = SPTy.getTag();
-
-  if (Args.getNumElements() == 0 || SPTag != dwarf::DW_TAG_subroutine_type)
-    SPCU->addType(SPDie, SPTy);
-  else
-    SPCU->addType(SPDie, DIType(Args.getElement(0)));
-
-  unsigned VK = SP.getVirtuality();
-  if (VK) {
-    SPCU->addUInt(SPDie, dwarf::DW_AT_virtuality, dwarf::DW_FORM_flag, VK);
-    DIEBlock *Block = SPCU->getDIEBlock();
-    SPCU->addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
-    SPCU->addUInt(Block, 0, dwarf::DW_FORM_udata, SP.getVirtualIndex());
-    SPCU->addBlock(SPDie, dwarf::DW_AT_vtable_elem_location, 0, Block);
-    ContainingTypeMap.insert(std::make_pair(SPDie,
-                                            SP.getContainingType()));
-  }
-
-  if (!SP.isDefinition()) {
-    SPCU->addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
-    
-    // Add arguments. Do not add arguments for subprogram definition. They will
-    // be handled while processing variables.
-    DICompositeType SPTy = SP.getType();
-    DIArray Args = SPTy.getTypeArray();
-    unsigned SPTag = SPTy.getTag();
-
-    if (SPTag == dwarf::DW_TAG_subroutine_type)
-      for (unsigned i = 1, N =  Args.getNumElements(); i < N; ++i) {
-        DIE *Arg = new DIE(dwarf::DW_TAG_formal_parameter);
-        DIType ATy = DIType(DIType(Args.getElement(i)));
-        SPCU->addType(Arg, ATy);
-        if (ATy.isArtificial())
-          SPCU->addUInt(Arg, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1);
-        SPDie->addChild(Arg);
-      }
-  }
-
-  if (SP.isArtificial())
-    SPCU->addUInt(SPDie, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1);
-
-  if (!SP.isLocalToUnit())
-    SPCU->addUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
-
-  if (SP.isOptimized())
-    SPCU->addUInt(SPDie, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
-
-  if (unsigned isa = Asm->getISAEncoding()) {
-    SPCU->addUInt(SPDie, dwarf::DW_AT_APPLE_isa, dwarf::DW_FORM_flag, isa);
-  }
-
-  return SPDie;
-}
-
 /// isSubprogramContext - Return true if Context is either a subprogram
 /// or another context nested inside a subprogram.
 static bool isSubprogramContext(const MDNode *Context) {
@@ -303,7 +207,7 @@
   if (SPDecl.isSubprogram())
     // Refer function declaration directly.
     SPCU->addDIEEntry(SPDie, dwarf::DW_AT_specification, dwarf::DW_FORM_ref4,
-                      createSubprogramDIE(SPDecl));
+                      SPCU->getOrCreateSubprogramDIE(SPDecl));
   else {
     // There is not any need to generate specification DIE for a function
     // defined at compile unit level. If a function is defined inside another
@@ -922,7 +826,7 @@
     // class type.
     return;
 
-  DIE *SubprogramDie = createSubprogramDIE(SP);
+  DIE *SubprogramDie = TheCU->getOrCreateSubprogramDIE(SP);
 
   // Add to map.
   TheCU->insertDIE(N, SubprogramDie);
@@ -1070,15 +974,12 @@
     FirstCU->addUInt(ISP, dwarf::DW_AT_inline, 0, dwarf::DW_INL_inlined);
   }
 
-  for (DenseMap<DIE *, const MDNode *>::iterator CI = ContainingTypeMap.begin(),
-         CE = ContainingTypeMap.end(); CI != CE; ++CI) {
-    DIE *SPDie = CI->first;
-    const MDNode *N = dyn_cast_or_null<MDNode>(CI->second);
-    if (!N) continue;
-    DIE *NDie = getCompileUnit(N)->getDIE(N);
-    if (!NDie) continue;
-    getCompileUnit(N)->addDIEEntry(SPDie, dwarf::DW_AT_containing_type, 
-                                   dwarf::DW_FORM_ref4, NDie);
+  // Emit DW_AT_containing_type attribute to connect types with their
+  // vtable holding type.
+  for (DenseMap<const MDNode *, CompileUnit *>::iterator CUI = CUMap.begin(),
+         CUE = CUMap.end(); CUI != CUE; ++CUI) {
+    CompileUnit *TheCU = CUI->second;
+    TheCU->constructContainingTypeDIEs();
   }
 
   // Standard sections final addresses.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137618&r1=137617&r2=137618&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 12:24:54 2011
@@ -229,11 +229,6 @@
   /// (at the end of the module) as DW_AT_inline.
   SmallPtrSet<DIE *, 4> InlinedSubprogramDIEs;
 
-  /// ContainingTypeMap - This map is used to keep track of subprogram DIEs that
-  /// need DW_AT_containing_type attribute. This attribute points to a DIE that
-  /// corresponds to the MDNode mapped with the subprogram DIE.
-  DenseMap<DIE *, const MDNode *> ContainingTypeMap;
-
   /// InlineInfo - Keep track of inlined functions and their location.  This
   /// information is used to populate debug_inlined section.
   typedef std::pair<const MCSymbol *, DIE *> InlineInfoLabels;



From grosbach at apple.com  Mon Aug 15 12:30:25 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 17:30:25 -0000
Subject: [llvm-commits] [llvm] r137619 -
	/llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
Message-ID: <20110815173026.010582A6C12C@llvm.org>

Author: grosbach
Date: Mon Aug 15 12:30:25 2011
New Revision: 137619

URL: http://llvm.org/viewvc/llvm-project?rev=137619&view=rev
Log:
Tidy up trailing whitespace.

Modified:
    llvm/trunk/include/llvm/MC/MCTargetAsmParser.h

Modified: llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCTargetAsmParser.h?rev=137619&r1=137618&r2=137619&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCTargetAsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCTargetAsmParser.h Mon Aug 15 12:30:25 2011
@@ -26,7 +26,7 @@
   void operator=(const MCTargetAsmParser &);  // DO NOT IMPLEMENT
 protected: // Can only create subclasses.
   MCTargetAsmParser();
- 
+
   /// AvailableFeatures - The current set of available features.
   unsigned AvailableFeatures;
 
@@ -66,18 +66,18 @@
   ///
   /// \param DirectiveID - the identifier token of the directive.
   virtual bool ParseDirective(AsmToken DirectiveID) = 0;
-  
+
   /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
   /// instruction as an actual MCInst and emit it to the specified MCStreamer.
   /// This returns false on success and returns true on failure to match.
   ///
   /// On failure, the target parser is responsible for emitting a diagnostic
   /// explaining the match failure.
-  virtual bool 
+  virtual bool
   MatchAndEmitInstruction(SMLoc IDLoc,
                           SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                           MCStreamer &Out) = 0;
-  
+
 };
 
 } // End llvm namespace



From grosbach at apple.com  Mon Aug 15 12:47:02 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 10:47:02 -0700
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
Message-ID: <AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>

Hi Kristof,

This is a lot closer. Using Target/TargetSubtargetInfo.h is a layering violation, however. Nothing in the MC layer, which includes the AsmBackend, should reference anything in the Target layer. In this case, just include MC/MCSubtargetInfo.h directly, instead.

Also, please add test cases to the LLVM MC tests (in test/MC/ARM) to verify that this is doing what you expect. If you're not already familiar with it, there are some examples in there (prefetch.ll is a good one) for how to use the -check-prefix option FileCheck for this sort of conditional behaviour.

Thanks again!

-Jim


On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:

> Hi Jim,
> 
> Thanks to have a look!
> 
> 1.  I need the exact functionality provided by ARMSubTarget::HasV6T2Ops.
> Therefore, in trying not to reinvent the wheel, and 
> to avoid code duplication, I'm trying to use ARMSubTarget::HasV6T2Ops. I
> think I've found a way to create an ARMSubTarget object from the Triple, so
> that it doesn't have to be passed across a lot of interfaces. The patch now
> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see attachment).
> Since it no longer touches Clang, I dropped the cfe-commits list. Could you
> have another look and see if this patch is closer to being acceptable?
> 
> 2. I've created the following bug report:
> http://llvm.org/bugs/show_bug.cgi?id=10632
> 
> 
> Thanks,
> 
> Kristof
> 
> -----Original Message-----
> From: Jim Grosbach [mailto:grosbach at apple.com] 
> Sent: 10 August 2011 00:08
> To: Kristof Beyls
> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
> 
> Hi Kristof,
> 
> Thanks for looking at this.
> 
> 1. You should be able to derive the needed information from the Triple,
> which is already passed in. There's already some code there that does
> something similar to set the CPU Subtype correctly for Darwin MachO files.
> See the factory method createARMAsmBackend() for details. There shouldn't be
> any need to change the top level constructors or the target-independent
> bits.
> 
> 2. That sounds like a nasty bug. A bugzilla with a test case would be great.
> 
> -Jim
> 
> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
> 
>> Hi,
>> 
>> With the attached patch, I'm trying to fix a FIXME in the ARM backend.
> This
>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into account the
>> version of the ARM architecture that is being targeted. For versions
> before
>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as MOV r0,r0
> (in
>> ARM
>> mode) or MOV r8,r8 (in Thumb mode). For targets later than ARMv6T2, the
>> encoding for the NOP instruction is created.
>> 
>> I have a few questions about this patch:
>> 
>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out which ARM
>>  sub-target it compiles for, I had to adapt the
> Target::MCAsmBackendCtorTy
>> to
>>  also pass on an MCSubtargetInfo argument. Is this the best way to get
>>  sub-target information to the ARMAsmBackend object?
>>  (this change results in a few function signature changes in the
>>   ARM, PowerPC, X86 and MBlaze backends).
>> 
>> 2. It's hard to create test cases to test this properly, since I think
>>  that there is another bug in lib/MC/MCAssembler.cpp, where processing 
>>  an alignment fragment results in calling ARMAsmBackend::WriteNopData,
> but
>>  without putting the ARMAsmBackend in the right ARM or Thumb state.
>>  Therefore, e.g. when processing an assembler file with .align directives
>>  in the middle of a Thumb code section, still ARM NOP encodings are 
>>  generated instead of Thumb NOP encodings.
>>  Question 2a: Is it OK to write a FIXME to indicate this brokenness?
>> Should
>>  I also file a bugzilla issue?
>>  Question 2b: Is it OK to leave that fix for a later, separate, patch?
> For
>>  that fix, it will be easier to create good test cases that will also
> test
>>  this patch.
>> 
>> Thanks,
>> 
>> Kristof
>> 
>> PS. I'm cc-ing to the cfe-commits list because the change in
>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang too, see
>> attached file
> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_nop_enc
> oding.patch>_______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> <llvm_arm_nop_encoding_v2.patch>


From dpatel at apple.com  Mon Aug 15 12:57:41 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 17:57:41 -0000
Subject: [llvm-commits] [llvm] r137621 - in /llvm/trunk:
 include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20110815175741.4D3422A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 12:57:41 2011
New Revision: 137621

URL: http://llvm.org/viewvc/llvm-project?rev=137621&view=rev
Log:
Refactor. Global variables are part of compile unit so let CompileUnit create new global variable.

Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DebugInfo.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=137621&r1=137620&r2=137621&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Mon Aug 15 12:57:41 2011
@@ -291,6 +291,9 @@
       return getFieldAs<DIFile>(3).getFilename();
     }
 
+    /// isUnsignedDIType - Return true if type encoding is unsigned.
+    bool isUnsignedDIType();
+
     /// replaceAllUsesWith - Replace all uses of debug info referenced by
     /// this descriptor.
     void replaceAllUsesWith(DIDescriptor &D);
@@ -714,6 +717,10 @@
   /// getDICompositeType - Find underlying composite type.
   DICompositeType getDICompositeType(DIType T);
 
+  /// isSubprogramContext - Return true if Context is either a subprogram
+  /// or another context nested inside a subprogram.
+  bool isSubprogramContext(const MDNode *Context);
+
   /// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable
   /// to hold function specific information.
   NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, StringRef Name);

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=137621&r1=137620&r2=137621&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Mon Aug 15 12:57:41 2011
@@ -328,6 +328,22 @@
   }
 }
 
+/// isUnsignedDIType - Return true if type encoding is unsigned.
+bool DIType::isUnsignedDIType() {
+  DIDerivedType DTy(DbgNode);
+  if (DTy.Verify())
+    return DTy.getTypeDerivedFrom().isUnsignedDIType();
+
+  DIBasicType BTy(DbgNode);
+  if (BTy.Verify()) {
+    unsigned Encoding = BTy.getEncoding();
+    if (Encoding == dwarf::DW_ATE_unsigned ||
+        Encoding == dwarf::DW_ATE_unsigned_char)
+      return true;
+  }
+  return false;
+}
+
 /// Verify - Verify that a compile unit is well formed.
 bool DICompileUnit::Verify() const {
   if (!DbgNode)
@@ -1014,3 +1030,17 @@
 
   return DICompositeType();
 }
+
+/// isSubprogramContext - Return true if Context is either a subprogram
+/// or another context nested inside a subprogram.
+bool llvm::isSubprogramContext(const MDNode *Context) {
+  if (!Context)
+    return false;
+  DIDescriptor D(Context);
+  if (D.isSubprogram())
+    return true;
+  if (D.isType())
+    return isSubprogramContext(DIType(Context).getContext());
+  return false;
+}
+

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=137621&r1=137620&r2=137621&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Aug 15 12:57:41 2011
@@ -16,7 +16,10 @@
 #include "DwarfCompileUnit.h"
 #include "DwarfDebug.h"
 #include "llvm/Constants.h"
+#include "llvm/GlobalVariable.h"
+#include "llvm/Instructions.h"
 #include "llvm/Analysis/DIBuilder.h"
+#include "llvm/Target/Mangler.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetFrameLowering.h"
 #include "llvm/Target/TargetMachine.h"
@@ -994,6 +997,112 @@
   return SPDie;
 }
 
+// Return const expression if value is a GEP to access merged global
+// constant. e.g.
+// i8* getelementptr ({ i8, i8, i8, i8 }* @_MergedGlobals, i32 0, i32 0)
+static const ConstantExpr *getMergedGlobalExpr(const Value *V) {
+  const ConstantExpr *CE = dyn_cast_or_null<ConstantExpr>(V);
+  if (!CE || CE->getNumOperands() != 3 ||
+      CE->getOpcode() != Instruction::GetElementPtr)
+    return NULL;
+
+  // First operand points to a global struct.
+  Value *Ptr = CE->getOperand(0);
+  if (!isa<GlobalValue>(Ptr) ||
+      !isa<StructType>(cast<PointerType>(Ptr->getType())->getElementType()))
+    return NULL;
+
+  // Second operand is zero.
+  const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CE->getOperand(1));
+  if (!CI || !CI->isZero())
+    return NULL;
+
+  // Third operand is offset.
+  if (!isa<ConstantInt>(CE->getOperand(2)))
+    return NULL;
+
+  return CE;
+}
+
+/// createGlobalVariableDIE - create global variable DIE.
+void CompileUnit::createGlobalVariableDIE(const MDNode *N) {
+  DIGlobalVariable GV(N);
+
+  // Check for pre-existence.
+  if (getDIE(GV))
+    return;
+
+  DIType GTy = GV.getType();
+  DIE *VariableDIE = new DIE(GV.getTag());
+
+  bool isGlobalVariable = GV.getGlobal() != NULL;
+
+  // Add name.
+  addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
+                   GV.getDisplayName());
+  StringRef LinkageName = GV.getLinkageName();
+  if (!LinkageName.empty() && isGlobalVariable)
+    addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name, 
+                     dwarf::DW_FORM_string,
+                     getRealLinkageName(LinkageName));
+  // Add type.
+  addType(VariableDIE, GTy);
+
+  // Add scoping info.
+  if (!GV.isLocalToUnit()) {
+    addUInt(VariableDIE, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
+    // Expose as global. 
+    addGlobal(GV.getName(), VariableDIE);
+  }
+  // Add line number info.
+  addSourceLine(VariableDIE, GV);
+  // Add to map.
+  insertDIE(N, VariableDIE);
+  // Add to context owner.
+  DIDescriptor GVContext = GV.getContext();
+  addToContextOwner(VariableDIE, GVContext);
+  // Add location.
+  if (isGlobalVariable) {
+    DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr);
+    addLabel(Block, 0, dwarf::DW_FORM_udata,
+             Asm->Mang->getSymbol(GV.getGlobal()));
+    // Do not create specification DIE if context is either compile unit
+    // or a subprogram.
+    if (GV.isDefinition() && !GVContext.isCompileUnit() &&
+        !GVContext.isFile() && !isSubprogramContext(GVContext)) {
+      // Create specification DIE.
+      DIE *VariableSpecDIE = new DIE(dwarf::DW_TAG_variable);
+      addDIEEntry(VariableSpecDIE, dwarf::DW_AT_specification,
+                  dwarf::DW_FORM_ref4, VariableDIE);
+      addBlock(VariableSpecDIE, dwarf::DW_AT_location, 0, Block);
+      addUInt(VariableDIE, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag,
+                     1);
+      addDie(VariableSpecDIE);
+    } else {
+      addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block);
+    } 
+  } else if (const ConstantInt *CI = 
+             dyn_cast_or_null<ConstantInt>(GV.getConstant()))
+    addConstantValue(VariableDIE, CI, GTy.isUnsignedDIType());
+  else if (const ConstantExpr *CE = getMergedGlobalExpr(N->getOperand(11))) {
+    // GV is a merged global.
+    DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
+    Value *Ptr = CE->getOperand(0);
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr);
+    addLabel(Block, 0, dwarf::DW_FORM_udata,
+                    Asm->Mang->getSymbol(cast<GlobalValue>(Ptr)));
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
+    SmallVector<Value*, 3> Idx(CE->op_begin()+1, CE->op_end());
+    addUInt(Block, 0, dwarf::DW_FORM_udata, 
+                   Asm->getTargetData().getIndexedOffset(Ptr->getType(), Idx));
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus);
+    addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block);
+  }
+
+  return;
+}
+
 /// constructSubrangeDIE - Construct subrange DIE from DISubrange.
 void CompileUnit::constructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){
   DIE *DW_Subrange = new DIE(dwarf::DW_TAG_subrange_type);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=137621&r1=137620&r2=137621&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Mon Aug 15 12:57:41 2011
@@ -250,6 +250,9 @@
   /// information entry.
   DIEEntry *createDIEEntry(DIE *Entry);
 
+  /// createGlobalVariableDIE - create global variable DIE.
+  void createGlobalVariableDIE(const MDNode *N);
+
   void addPubTypes(DISubprogram SP);
 
   /// constructTypeDIE - Construct basic type die from DIBasicType.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137621&r1=137620&r2=137621&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 12:57:41 2011
@@ -24,7 +24,6 @@
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetFrameLowering.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
@@ -179,19 +178,6 @@
   return LinkageName;
 }
 
-/// isSubprogramContext - Return true if Context is either a subprogram
-/// or another context nested inside a subprogram.
-static bool isSubprogramContext(const MDNode *Context) {
-  if (!Context)
-    return false;
-  DIDescriptor D(Context);
-  if (D.isSubprogram())
-    return true;
-  if (D.isType())
-    return isSubprogramContext(DIType(Context).getContext());
-  return false;
-}
-
 /// updateSubprogramScopeDIE - Find DIE for the given subprogram and
 /// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes.
 /// If there are global variables in this scope then create and insert
@@ -385,22 +371,6 @@
   return ScopeDIE;
 }
 
-/// isUnsignedDIType - Return true if type encoding is unsigned.
-static bool isUnsignedDIType(DIType Ty) {
-  DIDerivedType DTy(Ty);
-  if (DTy.Verify())
-    return isUnsignedDIType(DTy.getTypeDerivedFrom());
-
-  DIBasicType BTy(Ty);
-  if (BTy.Verify()) {
-    unsigned Encoding = BTy.getEncoding();
-    if (Encoding == dwarf::DW_ATE_unsigned ||
-        Encoding == dwarf::DW_ATE_unsigned_char)
-      return true;
-  }
-  return false;
-}
-
 /// constructVariableDIE - Construct a DIE for the given DbgVariable.
 DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, LexicalScope *Scope) {
   StringRef Name = DV->getName();
@@ -504,7 +474,7 @@
         updated =
           VariableCU->addConstantValue(VariableDie, 
                                        DVInsn->getOperand(0).getCImm(),
-                                       isUnsignedDIType(DV->getType()));
+                                       DV->getType().isUnsignedDIType());
     } else {
       VariableCU->addVariableAddress(DV, VariableDie, 
                                      Asm->getDebugValueLocation(DVInsn));
@@ -701,33 +671,6 @@
   return I->second;
 }
 
-// Return const expression if value is a GEP to access merged global
-// constant. e.g.
-// i8* getelementptr ({ i8, i8, i8, i8 }* @_MergedGlobals, i32 0, i32 0)
-static const ConstantExpr *getMergedGlobalExpr(const Value *V) {
-  const ConstantExpr *CE = dyn_cast_or_null<ConstantExpr>(V);
-  if (!CE || CE->getNumOperands() != 3 ||
-      CE->getOpcode() != Instruction::GetElementPtr)
-    return NULL;
-
-  // First operand points to a global struct.
-  Value *Ptr = CE->getOperand(0);
-  if (!isa<GlobalValue>(Ptr) ||
-      !isa<StructType>(cast<PointerType>(Ptr->getType())->getElementType()))
-    return NULL;
-
-  // Second operand is zero.
-  const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CE->getOperand(1));
-  if (!CI || !CI->isZero())
-    return NULL;
-
-  // Third operand is offset.
-  if (!isa<ConstantInt>(CE->getOperand(2)))
-    return NULL;
-
-  return CE;
-}
-
 /// constructGlobalVariableDIE - Construct global variable DIE.
 void DwarfDebug::constructGlobalVariableDIE(const MDNode *N) {
   DIGlobalVariable GV(N);
@@ -738,77 +681,7 @@
 
   // Check for pre-existence.
   CompileUnit *TheCU = getCompileUnit(N);
-  if (TheCU->getDIE(GV))
-    return;
-
-  DIType GTy = GV.getType();
-  DIE *VariableDIE = new DIE(GV.getTag());
-
-  bool isGlobalVariable = GV.getGlobal() != NULL;
-
-  // Add name.
-  TheCU->addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
-                   GV.getDisplayName());
-  StringRef LinkageName = GV.getLinkageName();
-  if (!LinkageName.empty() && isGlobalVariable)
-    TheCU->addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name, 
-                     dwarf::DW_FORM_string,
-                     getRealLinkageName(LinkageName));
-  // Add type.
-  TheCU->addType(VariableDIE, GTy);
-
-  // Add scoping info.
-  if (!GV.isLocalToUnit()) {
-    TheCU->addUInt(VariableDIE, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
-    // Expose as global. 
-    TheCU->addGlobal(GV.getName(), VariableDIE);
-  }
-  // Add line number info.
-  TheCU->addSourceLine(VariableDIE, GV);
-  // Add to map.
-  TheCU->insertDIE(N, VariableDIE);
-  // Add to context owner.
-  DIDescriptor GVContext = GV.getContext();
-  TheCU->addToContextOwner(VariableDIE, GVContext);
-  // Add location.
-  if (isGlobalVariable) {
-    DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
-    TheCU->addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr);
-    TheCU->addLabel(Block, 0, dwarf::DW_FORM_udata,
-             Asm->Mang->getSymbol(GV.getGlobal()));
-    // Do not create specification DIE if context is either compile unit
-    // or a subprogram.
-    if (GV.isDefinition() && !GVContext.isCompileUnit() &&
-        !GVContext.isFile() && !isSubprogramContext(GVContext)) {
-      // Create specification DIE.
-      DIE *VariableSpecDIE = new DIE(dwarf::DW_TAG_variable);
-      TheCU->addDIEEntry(VariableSpecDIE, dwarf::DW_AT_specification,
-                  dwarf::DW_FORM_ref4, VariableDIE);
-      TheCU->addBlock(VariableSpecDIE, dwarf::DW_AT_location, 0, Block);
-      TheCU->addUInt(VariableDIE, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag,
-                     1);
-      TheCU->addDie(VariableSpecDIE);
-    } else {
-      TheCU->addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block);
-    } 
-  } else if (const ConstantInt *CI = 
-             dyn_cast_or_null<ConstantInt>(GV.getConstant()))
-    TheCU->addConstantValue(VariableDIE, CI, isUnsignedDIType(GTy));
-  else if (const ConstantExpr *CE = getMergedGlobalExpr(N->getOperand(11))) {
-    // GV is a merged global.
-    DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
-    Value *Ptr = CE->getOperand(0);
-    TheCU->addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr);
-    TheCU->addLabel(Block, 0, dwarf::DW_FORM_udata,
-                    Asm->Mang->getSymbol(cast<GlobalValue>(Ptr)));
-    TheCU->addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
-    SmallVector<Value*, 3> Idx(CE->op_begin()+1, CE->op_end());
-    TheCU->addUInt(Block, 0, dwarf::DW_FORM_udata, 
-                   Asm->getTargetData().getIndexedOffset(Ptr->getType(), Idx));
-    TheCU->addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus);
-    TheCU->addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block);
-  }
-
+  TheCU->createGlobalVariableDIE(N);
   return;
 }
 



From James.Molloy at arm.com  Mon Aug 15 13:08:06 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 19:08:06 +0100
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
Message-ID: <912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>

Hi Jim,

Kristof is out of office for a few weeks, so I'll be taking over dealing with this patch.

I'll change the code to include MCSubtargetInfo.h as you suggest. I'm not sure about what to do with testcases, because Kristof apparently found broken behaviour in another part of the MC (for which he's added a FIXME) that will stop a normal test from exhibiting the correct behaviour - see the first email in the chain for a better description of that.

He was loath to have his first patch to the list be a large and contentious one, as he thinks it will be if he fixes the other brokenness immediately. What do you suggest?

My suggestion would be to add tests but mark them XFAIL for now - would this be acceptable?

Cheers,

James



On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com> wrote:

> Hi Kristof,
>
> This is a lot closer. Using Target/TargetSubtargetInfo.h is a layering violation, however. Nothing in the MC layer, which includes the AsmBackend, should reference anything in the Target layer. In this case, just include MC/MCSubtargetInfo.h directly, instead.
>
> Also, please add test cases to the LLVM MC tests (in test/MC/ARM) to verify that this is doing what you expect. If you're not already familiar with it, there are some examples in there (prefetch.ll is a good one) for how to use the -check-prefix option FileCheck for this sort of conditional behaviour.
>
> Thanks again!
>
> -Jim
>
>
> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
>
>> Hi Jim,
>>
>> Thanks to have a look!
>>
>> 1.  I need the exact functionality provided by ARMSubTarget::HasV6T2Ops.
>> Therefore, in trying not to reinvent the wheel, and
>> to avoid code duplication, I'm trying to use ARMSubTarget::HasV6T2Ops. I
>> think I've found a way to create an ARMSubTarget object from the Triple, so
>> that it doesn't have to be passed across a lot of interfaces. The patch now
>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see attachment).
>> Since it no longer touches Clang, I dropped the cfe-commits list. Could you
>> have another look and see if this patch is closer to being acceptable?
>>
>> 2. I've created the following bug report:
>> http://llvm.org/bugs/show_bug.cgi?id=10632
>>
>>
>> Thanks,
>>
>> Kristof
>>
>> -----Original Message-----
>> From: Jim Grosbach [mailto:grosbach at apple.com]
>> Sent: 10 August 2011 00:08
>> To: Kristof Beyls
>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
>>
>> Hi Kristof,
>>
>> Thanks for looking at this.
>>
>> 1. You should be able to derive the needed information from the Triple,
>> which is already passed in. There's already some code there that does
>> something similar to set the CPU Subtype correctly for Darwin MachO files.
>> See the factory method createARMAsmBackend() for details. There shouldn't be
>> any need to change the top level constructors or the target-independent
>> bits.
>>
>> 2. That sounds like a nasty bug. A bugzilla with a test case would be great.
>>
>> -Jim
>>
>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
>>
>>> Hi,
>>>
>>> With the attached patch, I'm trying to fix a FIXME in the ARM backend.
>> This
>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into account the
>>> version of the ARM architecture that is being targeted. For versions
>> before
>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as MOV r0,r0
>> (in
>>> ARM
>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than ARMv6T2, the
>>> encoding for the NOP instruction is created.
>>>
>>> I have a few questions about this patch:
>>>
>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out which ARM
>>> sub-target it compiles for, I had to adapt the
>> Target::MCAsmBackendCtorTy
>>> to
>>> also pass on an MCSubtargetInfo argument. Is this the best way to get
>>> sub-target information to the ARMAsmBackend object?
>>> (this change results in a few function signature changes in the
>>>  ARM, PowerPC, X86 and MBlaze backends).
>>>
>>> 2. It's hard to create test cases to test this properly, since I think
>>> that there is another bug in lib/MC/MCAssembler.cpp, where processing
>>> an alignment fragment results in calling ARMAsmBackend::WriteNopData,
>> but
>>> without putting the ARMAsmBackend in the right ARM or Thumb state.
>>> Therefore, e.g. when processing an assembler file with .align directives
>>> in the middle of a Thumb code section, still ARM NOP encodings are
>>> generated instead of Thumb NOP encodings.
>>> Question 2a: Is it OK to write a FIXME to indicate this brokenness?
>>> Should
>>> I also file a bugzilla issue?
>>> Question 2b: Is it OK to leave that fix for a later, separate, patch?
>> For
>>> that fix, it will be easier to create good test cases that will also
>> test
>>> this patch.
>>>
>>> Thanks,
>>>
>>> Kristof
>>>
>>> PS. I'm cc-ing to the cfe-commits list because the change in
>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang too, see
>>> attached file
>> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_nop_enc
>> oding.patch>_______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>> <llvm_arm_nop_encoding_v2.patch>
>
>
>

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From echristo at apple.com  Mon Aug 15 13:06:38 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 11:06:38 -0700
Subject: [llvm-commits] [PATCH] EH Changes for Optimization Passes
In-Reply-To: <F56146C8-0DD2-4642-A6DB-373B86831CB9@apple.com>
References: <F56146C8-0DD2-4642-A6DB-373B86831CB9@apple.com>
Message-ID: <02FFD23A-0E0E-448E-9251-A596B6D1C32D@apple.com>


On Aug 14, 2011, at 1:12 AM, Bill Wendling wrote:

> This is a patch that changes some of the optimization passes. With this patch (and the code-gen changes which I haven't submitted for approval yet), all of these EH programs in SingleSource pass for -O0, -O2, and -O3.
> 
> Okay?

This looks pretty obviously fine :)

-eric

From baldrick at free.fr  Mon Aug 15 13:14:04 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 15 Aug 2011 18:14:04 -0000
Subject: [llvm-commits] [dragonegg] r137624 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110815181404.CC0582A6C12C@llvm.org>

Author: baldrick
Date: Mon Aug 15 13:14:04 2011
New Revision: 137624

URL: http://llvm.org/viewvc/llvm-project?rev=137624&view=rev
Log:
Don't bother remembering fields that we aren't going to do anything with
anyway.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=137624&r1=137623&r2=137624&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Mon Aug 15 13:14:04 2011
@@ -1076,22 +1076,23 @@
   // initial value is supplied for a field then the value will overwrite and
   // replace the zero starting value later.
   if (flag_default_initialize_globals) {
-    // Process the fields in reverse order.  This is for the benefit of union
-    // types for which the first field must be default initialized (iterating
-    // in forward order would default initialize the last field).
+    // Record all interesting fields so they can easily be visited backwards.
     SmallVector<tree, 16> Fields;
     for (tree field = TYPE_FIELDS(TREE_TYPE(exp)); field;
          field = TREE_CHAIN(field)) {
       assert(TREE_CODE(field) == FIELD_DECL && "Lang data not freed?");
-      Fields.push_back(field);
+      // Ignore fields with variable or unknown position since they cannot be
+      // default initialized.
+      if (OffsetIsLLVMCompatible(field))
+        Fields.push_back(field);
     }
+
+    // Process the fields in reverse order.  This is for the benefit of union
+    // types for which the first field must be default initialized (iterating
+    // in forward order would default initialize the last field).
     for (SmallVector<tree, 16>::reverse_iterator I = Fields.rbegin(),
          E = Fields.rend(); I != E; ++I) {
       tree field = *I;
-      // If the field has variable or unknown position then it cannot be default
-      // initialized - skip it.
-      if (!OffsetIsLLVMCompatible(field))
-        continue;
       uint64_t FirstBit = getFieldOffsetInBits(field);
       assert(FirstBit <= TypeSize && "Field off end of type!");
       // Determine the width of the field.



From isanbard at gmail.com  Mon Aug 15 13:21:07 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 18:21:07 -0000
Subject: [llvm-commits] [llvm] r137626 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20110815182107.624912A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 13:21:07 2011
New Revision: 137626

URL: http://llvm.org/viewvc/llvm-project?rev=137626&view=rev
Log:
Skip the insertion iterator past the landingpad instruction if there.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137626&r1=137625&r2=137626&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Aug 15 13:21:07 2011
@@ -411,6 +411,7 @@
 
     if (!InsertedCast) {
       BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
+      if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
 
       InsertedCast =
         CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",



From isanbard at gmail.com  Mon Aug 15 13:22:01 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 18:22:01 -0000
Subject: [llvm-commits] [llvm] r137627 -
	/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
Message-ID: <20110815182201.270262A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 13:22:00 2011
New Revision: 137627

URL: http://llvm.org/viewvc/llvm-project?rev=137627&view=rev
Log:
Mark the SCC as "might unwind" if we run into a 'resume' instruction.

Modified:
    llvm/trunk/lib/Transforms/IPO/PruneEH.cpp

Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=137627&r1=137626&r2=137627&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Mon Aug 15 13:22:00 2011
@@ -101,8 +101,9 @@
       // Check to see if this function performs an unwind or calls an
       // unwinding function.
       for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
-        if (CheckUnwind && isa<UnwindInst>(BB->getTerminator())) {
-          // Uses unwind!
+        if (CheckUnwind && (isa<UnwindInst>(BB->getTerminator()) ||
+                            isa<ResumeInst>(BB->getTerminator()))) {
+          // Uses unwind / resume!
           SCCMightUnwind = true;
         } else if (CheckReturn && isa<ReturnInst>(BB->getTerminator())) {
           SCCMightReturn = true;



From isanbard at gmail.com  Mon Aug 15 13:22:49 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 18:22:49 -0000
Subject: [llvm-commits] [llvm] r137628 -
	/llvm/trunk/lib/Analysis/LoopInfo.cpp
Message-ID: <20110815182249.AB5152A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 13:22:49 2011
New Revision: 137628

URL: http://llvm.org/viewvc/llvm-project?rev=137628&view=rev
Log:
The landingpad instruction isn't loop-invariant.

Modified:
    llvm/trunk/lib/Analysis/LoopInfo.cpp

Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=137628&r1=137627&r2=137628&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopInfo.cpp Mon Aug 15 13:22:49 2011
@@ -99,6 +99,9 @@
     return false;
   if (I->mayReadFromMemory())
     return false;
+  // The landingpad instruction is immobile.
+  if (isa<LandingPadInst>(I))
+    return false;
   // Determine the insertion point, unless one was given.
   if (!InsertPt) {
     BasicBlock *Preheader = getLoopPreheader();



From isanbard at gmail.com  Mon Aug 15 13:23:40 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 18:23:40 -0000
Subject: [llvm-commits] [llvm] r137629 -
 /llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
Message-ID: <20110815182340.3884E2A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 13:23:40 2011
New Revision: 137629

URL: http://llvm.org/viewvc/llvm-project?rev=137629&view=rev
Log:
Don't try to sink the landingpad instruction. It's immobile.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137629&r1=137628&r2=137629&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 13:23:40 2011
@@ -1417,8 +1417,9 @@
 static bool TryToSinkInstruction(Instruction *I, BasicBlock *DestBlock) {
   assert(I->hasOneUse() && "Invariants didn't hold!");
 
-  // Cannot move control-flow-involving, volatile loads, vaarg, etc.
-  if (isa<PHINode>(I) || I->mayHaveSideEffects() || isa<TerminatorInst>(I))
+  // Cannot move control-flow-involving, volatile loads, vaarg, landingpad, etc.
+  if (isa<PHINode>(I) || isa<LandingPadInst>(I) || I->mayHaveSideEffects() ||
+      isa<TerminatorInst>(I))
     return false;
 
   // Do not sink alloca instructions out of the entry block.



From wendling at apple.com  Mon Aug 15 13:25:05 2011
From: wendling at apple.com (Bill Wendling)
Date: Mon, 15 Aug 2011 11:25:05 -0700
Subject: [llvm-commits] [PATCH] EH Changes for Optimization Passes
In-Reply-To: <02FFD23A-0E0E-448E-9251-A596B6D1C32D@apple.com>
References: <F56146C8-0DD2-4642-A6DB-373B86831CB9@apple.com>
	<02FFD23A-0E0E-448E-9251-A596B6D1C32D@apple.com>
Message-ID: <D85784B2-D5AF-44C6-B38E-EDD676AC874E@apple.com>

On Aug 15, 2011, at 11:06 AM, Eric Christopher wrote:

> On Aug 14, 2011, at 1:12 AM, Bill Wendling wrote:
> 
>> This is a patch that changes some of the optimization passes. With this patch (and the code-gen changes which I haven't submitted for approval yet), all of these EH programs in SingleSource pass for -O0, -O2, and -O3.
>> 
>> Okay?
> 
> This looks pretty obviously fine :)
> 
Thanks! :-)

-bw



From baldrick at free.fr  Mon Aug 15 13:26:24 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 15 Aug 2011 20:26:24 +0200
Subject: [llvm-commits] [llvm] r137628 -
	/llvm/trunk/lib/Analysis/LoopInfo.cpp
In-Reply-To: <20110815182249.AB5152A6C12C@llvm.org>
References: <20110815182249.AB5152A6C12C@llvm.org>
Message-ID: <4E4964D0.4070407@free.fr>

Hi Bill,

> The landingpad instruction isn't loop-invariant.

shouldn't mayReadFromMemory() return 'true' for a landing pad instruction?

Ciao, Duncan.

>
> Modified:
>      llvm/trunk/lib/Analysis/LoopInfo.cpp
>
> Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=137628&r1=137627&r2=137628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
> +++ llvm/trunk/lib/Analysis/LoopInfo.cpp Mon Aug 15 13:22:49 2011
> @@ -99,6 +99,9 @@
>       return false;
>     if (I->mayReadFromMemory())
>       return false;
> +  // The landingpad instruction is immobile.
> +  if (isa<LandingPadInst>(I))
> +    return false;
>     // Determine the insertion point, unless one was given.
>     if (!InsertPt) {
>       BasicBlock *Preheader = getLoopPreheader();
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Mon Aug 15 13:27:10 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 11:27:10 -0700
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
Message-ID: <00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>


On Aug 15, 2011, at 11:08 AM, James Molloy wrote:

> Hi Jim,
> 
> Kristof is out of office for a few weeks, so I'll be taking over dealing with this patch.
> 
> I'll change the code to include MCSubtargetInfo.h as you suggest. I'm not sure about what to do with testcases, because Kristof apparently found broken behaviour in another part of the MC (for which he's added a FIXME) that will stop a normal test from exhibiting the correct behaviour - see the first email in the chain for a better description of that.

Ah, right. Forgot about that part. Fixing the mode setting bit shouldn't be very invasive, I would hope. I haven't looked at that in detail recently, though, I confess.

In any case, I don't think that will prevent testcases. It just makes it not work to have them all be in a single source file (which we probably don't want anyway. One file for thumb and one file for ARM seems cleaner).

For example, we can get thumb padding with something like:
$ cat x.s
.thumb_func _foo
.code 16
_foo:
        mov r0, r1
        .align 4
        mov r0, r2
$ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
$ otool -vt x.o
x.o:
(__TEXT,__text) section
_foo:
00000000	    4608	mov	r0, r1
00000002	    bf00	nop
00000004	    bf00	nop
00000006	    bf00	nop
00000008	    bf00	nop
0000000a	    bf00	nop
0000000c	    bf00	nop
0000000e	    bf00	nop
00000010	    4610	mov	r0, r2

And ARM padding with something like:
$ cat x.s
_foo:
        mov r0, r1
        .align 4
        mov r0, r2
$ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
$ otool -vt x.o
x.o:
(__TEXT,__text) section
_foo:
00000000	e1a00001	mov	r0, r1
00000004	e1a00000	nop			(mov r0,r0)
00000008	e1a00000	nop			(mov r0,r0)
0000000c	e1a00000	nop			(mov r0,r0)
00000010	e1a00002	mov	r0, r2

The tests would want to use macho-dump, not otool, of course, for platform independence.

-Jim



> He was loath to have his first patch to the list be a large and contentious one, as he thinks it will be if he fixes the other brokenness immediately. What do you suggest?
> 
> My suggestion would be to add tests but mark them XFAIL for now - would this be acceptable?
> 
> Cheers,
> 
> James
> 
> 
> 
> On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com> wrote:
> 
>> Hi Kristof,
>> 
>> This is a lot closer. Using Target/TargetSubtargetInfo.h is a layering violation, however. Nothing in the MC layer, which includes the AsmBackend, should reference anything in the Target layer. In this case, just include MC/MCSubtargetInfo.h directly, instead.
>> 
>> Also, please add test cases to the LLVM MC tests (in test/MC/ARM) to verify that this is doing what you expect. If you're not already familiar with it, there are some examples in there (prefetch.ll is a good one) for how to use the -check-prefix option FileCheck for this sort of conditional behaviour.
>> 
>> Thanks again!
>> 
>> -Jim
>> 
>> 
>> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
>> 
>>> Hi Jim,
>>> 
>>> Thanks to have a look!
>>> 
>>> 1.  I need the exact functionality provided by ARMSubTarget::HasV6T2Ops.
>>> Therefore, in trying not to reinvent the wheel, and
>>> to avoid code duplication, I'm trying to use ARMSubTarget::HasV6T2Ops. I
>>> think I've found a way to create an ARMSubTarget object from the Triple, so
>>> that it doesn't have to be passed across a lot of interfaces. The patch now
>>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see attachment).
>>> Since it no longer touches Clang, I dropped the cfe-commits list. Could you
>>> have another look and see if this patch is closer to being acceptable?
>>> 
>>> 2. I've created the following bug report:
>>> http://llvm.org/bugs/show_bug.cgi?id=10632
>>> 
>>> 
>>> Thanks,
>>> 
>>> Kristof
>>> 
>>> -----Original Message-----
>>> From: Jim Grosbach [mailto:grosbach at apple.com]
>>> Sent: 10 August 2011 00:08
>>> To: Kristof Beyls
>>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
>>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
>>> 
>>> Hi Kristof,
>>> 
>>> Thanks for looking at this.
>>> 
>>> 1. You should be able to derive the needed information from the Triple,
>>> which is already passed in. There's already some code there that does
>>> something similar to set the CPU Subtype correctly for Darwin MachO files.
>>> See the factory method createARMAsmBackend() for details. There shouldn't be
>>> any need to change the top level constructors or the target-independent
>>> bits.
>>> 
>>> 2. That sounds like a nasty bug. A bugzilla with a test case would be great.
>>> 
>>> -Jim
>>> 
>>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
>>> 
>>>> Hi,
>>>> 
>>>> With the attached patch, I'm trying to fix a FIXME in the ARM backend.
>>> This
>>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into account the
>>>> version of the ARM architecture that is being targeted. For versions
>>> before
>>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as MOV r0,r0
>>> (in
>>>> ARM
>>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than ARMv6T2, the
>>>> encoding for the NOP instruction is created.
>>>> 
>>>> I have a few questions about this patch:
>>>> 
>>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out which ARM
>>>> sub-target it compiles for, I had to adapt the
>>> Target::MCAsmBackendCtorTy
>>>> to
>>>> also pass on an MCSubtargetInfo argument. Is this the best way to get
>>>> sub-target information to the ARMAsmBackend object?
>>>> (this change results in a few function signature changes in the
>>>> ARM, PowerPC, X86 and MBlaze backends).
>>>> 
>>>> 2. It's hard to create test cases to test this properly, since I think
>>>> that there is another bug in lib/MC/MCAssembler.cpp, where processing
>>>> an alignment fragment results in calling ARMAsmBackend::WriteNopData,
>>> but
>>>> without putting the ARMAsmBackend in the right ARM or Thumb state.
>>>> Therefore, e.g. when processing an assembler file with .align directives
>>>> in the middle of a Thumb code section, still ARM NOP encodings are
>>>> generated instead of Thumb NOP encodings.
>>>> Question 2a: Is it OK to write a FIXME to indicate this brokenness?
>>>> Should
>>>> I also file a bugzilla issue?
>>>> Question 2b: Is it OK to leave that fix for a later, separate, patch?
>>> For
>>>> that fix, it will be easier to create good test cases that will also
>>> test
>>>> this patch.
>>>> 
>>>> Thanks,
>>>> 
>>>> Kristof
>>>> 
>>>> PS. I'm cc-ing to the cfe-commits list because the change in
>>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang too, see
>>>> attached file
>>> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_nop_enc
>>> oding.patch>_______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>>> 
>>> <llvm_arm_nop_encoding_v2.patch>
>> 
>> 
>> 
> 
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
> 


From baldrick at free.fr  Mon Aug 15 13:27:26 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 15 Aug 2011 20:27:26 +0200
Subject: [llvm-commits] [llvm] r137629 -
	/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
In-Reply-To: <20110815182340.3884E2A6C12C@llvm.org>
References: <20110815182340.3884E2A6C12C@llvm.org>
Message-ID: <4E49650E.7030106@free.fr>

Hi Bill,

> Don't try to sink the landingpad instruction. It's immobile.

this would be taken care of automatically if landing pad instructions were
marked as reading memory (which presumably they do, since otherwise where
do they get the info about which exception was raised etc from?).

Ciao, Duncan.

>
> Modified:
>      llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>
> Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137629&r1=137628&r2=137629&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 13:23:40 2011
> @@ -1417,8 +1417,9 @@
>   static bool TryToSinkInstruction(Instruction *I, BasicBlock *DestBlock) {
>     assert(I->hasOneUse()&&  "Invariants didn't hold!");
>
> -  // Cannot move control-flow-involving, volatile loads, vaarg, etc.
> -  if (isa<PHINode>(I) || I->mayHaveSideEffects() || isa<TerminatorInst>(I))
> +  // Cannot move control-flow-involving, volatile loads, vaarg, landingpad, etc.
> +  if (isa<PHINode>(I) || isa<LandingPadInst>(I) || I->mayHaveSideEffects() ||
> +      isa<TerminatorInst>(I))
>       return false;
>
>     // Do not sink alloca instructions out of the entry block.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From eli.friedman at gmail.com  Mon Aug 15 13:33:07 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 11:33:07 -0700
Subject: [llvm-commits] [llvm] r137626 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
In-Reply-To: <20110815182107.624912A6C12C@llvm.org>
References: <20110815182107.624912A6C12C@llvm.org>
Message-ID: <CAJdarcGgnC5BOXXkmp9tMcV17JAMwsSCCUzMeoj_QWJ+St5qyg@mail.gmail.com>

On Mon, Aug 15, 2011 at 11:21 AM, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Mon Aug 15 13:21:07 2011
> New Revision: 137626
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137626&view=rev
> Log:
> Skip the insertion iterator past the landingpad instruction if there.
>
> Modified:
> ? ?llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
>
> Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137626&r1=137625&r2=137626&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Aug 15 13:21:07 2011
> @@ -411,6 +411,7 @@
>
> ? ? if (!InsertedCast) {
> ? ? ? BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
> + ? ? ?if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
>
> ? ? ? InsertedCast =
> ? ? ? ? CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",

Does every other user of getFirstNonPHI need to check for this as well?

-Eli


From stoklund at 2pi.dk  Mon Aug 15 13:35:27 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 15 Aug 2011 11:35:27 -0700
Subject: [llvm-commits] [llvm] r137551 - in /llvm/trunk:
 lib/Target/ARM/ARMExpandPseudoInsts.cpp
 test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
In-Reply-To: <20110813051455.DAC2A2A6C12C@llvm.org>
References: <20110813051455.DAC2A2A6C12C@llvm.org>
Message-ID: <882B91C5-0B4A-4ACD-8421-F4AC7D7A142B@2pi.dk>


On Aug 12, 2011, at 10:14 PM, Bob Wilson wrote:

> Author: bwilson
> Date: Sat Aug 13 00:14:55 2011
> New Revision: 137551
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137551&view=rev
> Log:
> Expand VMOVQQQQ pseudo instructions.
> 
> Apparently we never added code to expand these pseudo instructions, and in
> over a year, no one has noticed.  Our register allocator must be awesome!

Yep!

As far as I can tell, VMOVQQQQ is only ever created by ARMBaseInstrInfo::copyPhysReg now.

I don't think it would be a problem to expand the instruction directly in copyPhysReg. That way you can eliminate the pseudo completely.

QQQQ copies are represented with abstract COPY instructions during register allocation, so the pseudo probably doesn't help us any more.

/jakob


From isanbard at gmail.com  Mon Aug 15 13:36:05 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 11:36:05 -0700
Subject: [llvm-commits] [llvm] r137626 -
 /llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
In-Reply-To: <CAJdarcGgnC5BOXXkmp9tMcV17JAMwsSCCUzMeoj_QWJ+St5qyg@mail.gmail.com>
References: <20110815182107.624912A6C12C@llvm.org>
	<CAJdarcGgnC5BOXXkmp9tMcV17JAMwsSCCUzMeoj_QWJ+St5qyg@mail.gmail.com>
Message-ID: <ACFA481E-4745-44FB-ADC3-B83DC174FAFB@gmail.com>

On Aug 15, 2011, at 11:33 AM, Eli Friedman wrote:

> On Mon, Aug 15, 2011 at 11:21 AM, Bill Wendling <isanbard at gmail.com> wrote:
>> Author: void
>> Date: Mon Aug 15 13:21:07 2011
>> New Revision: 137626
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137626&view=rev
>> Log:
>> Skip the insertion iterator past the landingpad instruction if there.
>> 
>> Modified:
>>    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
>> 
>> Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137626&r1=137625&r2=137626&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Aug 15 13:21:07 2011
>> @@ -411,6 +411,7 @@
>> 
>>     if (!InsertedCast) {
>>       BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
>> +      if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
>> 
>>       InsertedCast =
>>         CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
> 
> Does every other user of getFirstNonPHI need to check for this as well?
> 
No, not every one. Though there will almost certainly be more places that need similar fixes.

-bw


From dpatel at apple.com  Mon Aug 15 13:35:43 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 18:35:43 -0000
Subject: [llvm-commits] [llvm] r137631 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815183543.19C632A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 13:35:42 2011
New Revision: 137631

URL: http://llvm.org/viewvc/llvm-project?rev=137631&view=rev
Log:
Refactor.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137631&r1=137630&r2=137631&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 13:35:42 2011
@@ -377,20 +377,8 @@
   if (Name.empty())
     return NULL;
 
-  // Translate tag to proper Dwarf tag.  The result variable is dropped for
-  // now.
-  unsigned Tag;
-  switch (DV->getTag()) {
-  case dwarf::DW_TAG_return_variable:
-    return NULL;
-  case dwarf::DW_TAG_arg_variable:
-    Tag = dwarf::DW_TAG_formal_parameter;
-    break;
-  case dwarf::DW_TAG_auto_variable:    // fall thru
-  default:
-    Tag = dwarf::DW_TAG_variable;
-    break;
-  }
+  // Translate tag to proper Dwarf tag.
+  unsigned Tag = DV->getTag();
 
   // Define variable debug information entry.
   DIE *VariableDie = new DIE(Tag);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137631&r1=137630&r2=137631&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 13:35:42 2011
@@ -136,7 +136,13 @@
   void setDotDebugLocOffset(unsigned O)    { DotDebugLocOffset = O; }
   unsigned getDotDebugLocOffset()    const { return DotDebugLocOffset; }
   StringRef getName()                const { return Var.getName(); }
-  unsigned getTag()                  const { return Var.getTag(); }
+  // Translate tag to proper Dwarf tag.  
+  unsigned getTag()                  const { 
+    if (Var.getTag() == dwarf::DW_TAG_arg_variable)
+      return dwarf::DW_TAG_formal_parameter;
+    
+    return dwarf::DW_TAG_variable;
+  }
   bool variableHasComplexAddress()   const {
     assert(Var.Verify() && "Invalid complex DbgVariable!");
     return Var.hasComplexAddress();



From echristo at apple.com  Mon Aug 15 13:37:51 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 11:37:51 -0700
Subject: [llvm-commits] [PATCH] Fixes in ARM TableGen
In-Reply-To: <002401cc5b56$c62a0760$527e1620$%molloy@arm.com>
References: <002401cc5b56$c62a0760$527e1620$%molloy@arm.com>
Message-ID: <F6FAEF0C-1717-40F1-9E15-E78FDCC4F9B9@apple.com>


On Aug 15, 2011, at 7:22 AM, James Molloy wrote:

> Hi,
>  
> The attached patch does three things (they're each so small I kept them in the same patch file - hope this is OK):
>  
> ?         Fix the field offsets for UMAAL - RdHi and RdLo were the incorrect way around (see A8.6.244). This required a fix to a test.
> ?         Set the DecoderMethod for STRH (and other addrmode3 stores) correctly.
> ?         Remove two pieces of dead code - class AI3stridx and class AIsthpr in ARMInstrFormats.td were not used anywhere.
>  
> Cheers,
>  
> James
> <STRH_UMAAL.patch>_______________________________________________

LGTM.

Any objections Jim?

-eric

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From echristo at apple.com  Mon Aug 15 13:40:11 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 11:40:11 -0700
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
Message-ID: <CE2DAC4C-6FE2-4095-8AE8-91F58381E242@apple.com>


On Aug 15, 2011, at 7:23 AM, James Molloy wrote:

> Hi,
>  
> The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.
>  
> Cheers,
>  

   let EncoderMethod = "getThumbAddrModeRegRegOpValue";
   let PrintMethod = "printThumbAddrModeRROperand";
+  let DecoderMethod = "DecodeThumbAddrModeRR";
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
 }

This appears to be the actual fix and the rest is some random renaming? Also could you add a test for ldrsh as well?

-eric
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From grosbach at apple.com  Mon Aug 15 13:40:48 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 11:40:48 -0700
Subject: [llvm-commits] [PATCH] Fixes in ARM TableGen
In-Reply-To: <F6FAEF0C-1717-40F1-9E15-E78FDCC4F9B9@apple.com>
References: <002401cc5b56$c62a0760$527e1620$%molloy@arm.com>
	<F6FAEF0C-1717-40F1-9E15-E78FDCC4F9B9@apple.com>
Message-ID: <BB4FE69F-7053-4921-971A-4AD8178684FD@apple.com>


On Aug 15, 2011, at 11:37 AM, Eric Christopher wrote:

> 
> On Aug 15, 2011, at 7:22 AM, James Molloy wrote:
> 
>> Hi,
>>  
>> The attached patch does three things (they're each so small I kept them in the same patch file - hope this is OK):
>>  
>> ?         Fix the field offsets for UMAAL - RdHi and RdLo were the incorrect way around (see A8.6.244). This required a fix to a test.
>> ?         Set the DecoderMethod for STRH (and other addrmode3 stores) correctly.
>> ?         Remove two pieces of dead code - class AI3stridx and class AIsthpr in ARMInstrFormats.td were not used anywhere.
>>  
>> Cheers,
>>  
>> James
>> <STRH_UMAAL.patch>_______________________________________________
> 
> LGTM.
> 
> Any objections Jim?


OK w/ me. I would prefer the changes be checked in as separate patches, though, even though they're very small. Keeps the revision history easier to follow.

-jim

From dpatel at apple.com  Mon Aug 15 13:40:17 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 18:40:17 -0000
Subject: [llvm-commits] [llvm] r137632 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815184017.30B9A2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 13:40:16 2011
New Revision: 137632

URL: http://llvm.org/viewvc/llvm-project?rev=137632&view=rev
Log:
Refactor.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137632&r1=137631&r2=137632&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 13:40:16 2011
@@ -401,11 +401,8 @@
     VariableCU->addType(VariableDie, DV->getType());
   }
 
-  if (Tag == dwarf::DW_TAG_formal_parameter && DV->getType().isArtificial())
-    VariableCU->addUInt(VariableDie, dwarf::DW_AT_artificial, 
-                        dwarf::DW_FORM_flag, 1);
-  else if (DIVariable(DV->getVariable()).isArtificial())
-    VariableCU->addUInt(VariableDie, dwarf::DW_AT_artificial, 
+  if (DV->isArtificial())
+    VariableCU->addUInt(VariableDie, dwarf::DW_AT_artificial,
                         dwarf::DW_FORM_flag, 1);
 
   if (Scope->isAbstractScope()) {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137632&r1=137631&r2=137632&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 13:40:16 2011
@@ -143,6 +143,15 @@
     
     return dwarf::DW_TAG_variable;
   }
+  /// isArtificial - Return true if DbgVariable is artificial.
+  bool isArtificial()                const {
+    if (Var.isArtificial())
+      return true;
+    if (Var.getTag() == dwarf::DW_TAG_arg_variable
+        && getType().isArtificial())
+      return true;
+    return false;
+  }
   bool variableHasComplexAddress()   const {
     assert(Var.Verify() && "Invalid complex DbgVariable!");
     return Var.hasComplexAddress();



From resistor at mac.com  Mon Aug 15 13:44:44 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 18:44:44 -0000
Subject: [llvm-commits] [llvm] r137635 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/neon.txt
Message-ID: <20110815184444.9B0D72A6C12D@llvm.org>

Author: resistor
Date: Mon Aug 15 13:44:44 2011
New Revision: 137635

URL: http://llvm.org/viewvc/llvm-project?rev=137635&view=rev
Log:
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=137635&r1=137634&r2=137635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 15 13:44:44 2011
@@ -547,6 +547,7 @@
                                          (i32 (LoadOp addrmode6:$Rn)),
                                          imm:$lane))]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD1LN";
 }
 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
              PatFrag LoadOp>
@@ -558,6 +559,7 @@
                                          (i32 (LoadOp addrmode6oneL32:$Rn)),
                                          imm:$lane))]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD1LN";
 }
 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
   let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
@@ -597,7 +599,9 @@
           (ins addrmode6:$Rn, am6offset:$Rm,
            DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
           "\\{$Vd[$lane]\\}, $Rn$Rm",
-          "$src = $Vd, $Rn.addr = $wb", []>;
+          "$src = $Vd, $Rn.addr = $wb", []> {
+  let DecoderMethod = "DecodeVLD1LN";
+}
 
 def VLD1LNd8_UPD  : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -624,6 +628,7 @@
           "$src1 = $Vd, $src2 = $dst2", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD2LN";
 }
 
 def VLD2LNd8  : VLD2LN<0b0001, {?,?,?,?}, "8"> {
@@ -659,6 +664,7 @@
           "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
           "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD2LN";
 }
 
 def VLD2LNd8_UPD  : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
@@ -693,6 +699,7 @@
           "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD3LN";
 }
 
 def VLD3LNd8  : VLD3LN<0b0010, {?,?,?,0}, "8"> {
@@ -729,7 +736,9 @@
           IIC_VLD3lnu, "vld3", Dt,
           "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
-          []>;
+          []> {
+  let DecoderMethod = "DecodeVLD3LN";
+}
 
 def VLD3LNd8_UPD  : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -765,6 +774,7 @@
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD4LN";
 }
 
 def VLD4LNd8  : VLD4LN<0b0011, {?,?,?,?}, "8"> {
@@ -805,6 +815,7 @@
 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
           []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD4LN"  ;
 }
 
 def VLD4LNd8_UPD  : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
@@ -1424,6 +1435,7 @@
           IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
           [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST1LN";
 }
 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
              PatFrag StoreOp, SDNode ExtractOp>
@@ -1432,6 +1444,7 @@
           IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
           [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST1LN";
 }
 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
   : VSTQLNPseudo<IIC_VST1ln> {
@@ -1472,7 +1485,9 @@
           "\\{$Vd[$lane]\\}, $Rn$Rm",
           "$Rn.addr = $wb",
           [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
-                                  addrmode6:$Rn, am6offset:$Rm))]>;
+                                  addrmode6:$Rn, am6offset:$Rm))]> {
+  let DecoderMethod = "DecodeVST1LN";
+}
 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
   : VSTQLNWBPseudo<IIC_VST1lnu> {
   let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
@@ -1508,6 +1523,7 @@
           "", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVST2LN";
 }
 
 def VST2LNd8  : VST2LN<0b0001, {?,?,?,?}, "8"> {
@@ -1545,6 +1561,7 @@
           "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
           "$addr.addr = $wb", []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVST2LN";
 }
 
 def VST2LNd8_UPD  : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
@@ -1578,6 +1595,7 @@
            nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
           "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST3LN";
 }
 
 def VST3LNd8  : VST3LN<0b0010, {?,?,?,0}, "8"> {
@@ -1612,7 +1630,9 @@
            DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
           IIC_VST3lnu, "vst3", Dt,
           "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
-          "$Rn.addr = $wb", []>;
+          "$Rn.addr = $wb", []> {
+  let DecoderMethod = "DecodeVST3LN";
+}
 
 def VST3LNd8_UPD  : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -1647,6 +1667,7 @@
           "", []> {
   let Rm = 0b1111;
   let Inst{4} = Rn{4};
+  let DecoderMethod = "DecodeVST4LN";
 }
 
 def VST4LNd8  : VST4LN<0b0011, {?,?,?,?}, "8"> {
@@ -1685,6 +1706,7 @@
   "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
           "$Rn.addr = $wb", []> {
   let Inst{4} = Rn{4};
+  let DecoderMethod = "DecodeVST4LN";
 }
 
 def VST4LNd8_UPD  : VST4LNWB<0b0011, {?,?,?,?}, "8"> {

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137635&r1=137634&r2=137635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 15 13:44:44 2011
@@ -141,6 +141,22 @@
                                uint64_t Address, const void *Decoder);
 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 
 
 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2560,3 +2576,447 @@
 
   return true;
 }
+
+static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 6, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 2) != 0)
+        align = 4;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 6, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 2) != 0)
+        align = 4;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      index = fieldFromInstruction32(Insn, 5, 3);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 1:
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 1) != 0)
+        align = 8;
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      index = fieldFromInstruction32(Insn, 5, 3);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 1:
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 1) != 0)
+        align = 8;
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 8;
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        align = 4 << fieldFromInstruction32(Insn, 4, 2);
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 8;
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        align = 4 << fieldFromInstruction32(Insn, 4, 2);
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+

Added: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=137635&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 15 13:44:44 2011
@@ -0,0 +1,1847 @@
+# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble < %s | FileCheck %s
+
+0x20 0x03 0xf1 0xf3
+# CHECK: vabs.s8	d16, d16
+0x20 0x03 0xf5 0xf3
+# CHECK: vabs.s16	d16, d16
+0x20 0x03 0xf9 0xf3
+# CHECK: vabs.s32	d16, d16
+0x20 0x07 0xf9 0xf3
+# CHECK: vabs.f32	d16, d16
+0x60 0x03 0xf1 0xf3
+# CHECK: vabs.s8	q8, q8
+0x60 0x03 0xf5 0xf3
+# CHECK: vabs.s16	q8, q8
+0x60 0x03 0xf9 0xf3
+# CHECK: vabs.s32	q8, q8
+0x60 0x07 0xf9 0xf3
+# CHECK: vabs.f32	q8, q8
+
+0x20 0x07 0xf0 0xf3
+# CHECK: vqabs.s8	d16, d16
+0x20 0x07 0xf4 0xf3
+# CHECK: vqabs.s16	d16, d16
+0x20 0x07 0xf8 0xf3
+# CHECK: vqabs.s32	d16, d16
+0x60 0x07 0xf0 0xf3
+# CHECK: vqabs.s8	q8, q8
+0x60 0x07 0xf4 0xf3
+# CHECK: vqabs.s16	q8, q8
+0x60 0x07 0xf8 0xf3
+# CHECK: vqabs.s32	q8, q8
+
+0xa1 0x07 0x40 0xf2
+# CHECK: vabd.s8	d16, d16, d17
+0xa1 0x07 0x50 0xf2
+# CHECK: vabd.s16	d16, d16, d17
+0xa1 0x07 0x60 0xf2
+# CHECK: vabd.s32	d16, d16, d17
+0xa1 0x07 0x40 0xf3
+# CHECK: vabd.u8	d16, d16, d17
+0xa1 0x07 0x50 0xf3
+# CHECK: vabd.u16	d16, d16, d17
+  0xa1 0x07 0x60 0xf3
+# CHECK: vabd.u32	d16, d16, d17
+0xa1 0x0d 0x60 0xf3
+# CHECK: vabd.f32	d16, d16, d17
+0xe2 0x07 0x40 0xf2
+# CHECK: vabd.s8	q8, q8, q9
+0xe2 0x07 0x50 0xf2
+# CHECK: vabd.s16	q8, q8, q9
+0xe2 0x07 0x60 0xf2
+# CHECK: vabd.s32	q8, q8, q9
+0xe2 0x07 0x40 0xf3
+# CHECK: vabd.u8	q8, q8, q9
+0xe2 0x07 0x50 0xf3
+# CHECK: vabd.u16	q8, q8, q9
+0xe2 0x07 0x60 0xf3
+# CHECK: vabd.u32	q8, q8, q9
+0xe2 0x0d 0x60 0xf3
+# CHECK: vabd.f32	q8, q8, q9
+
+0xa1 0x07 0xc0 0xf2
+# CHECK: vabdl.s8	q8, d16, d17
+0xa1 0x07 0xd0 0xf2
+# CHECK: vabdl.s16	q8, d16, d17
+0xa1 0x07 0xe0 0xf2
+# CHECK: vabdl.s32	q8, d16, d17
+0xa1 0x07 0xc0 0xf3
+# CHECK: vabdl.u8	q8, d16, d17
+0xa1 0x07 0xd0 0xf3
+# CHECK: vabdl.u16	q8, d16, d17
+0xa1 0x07 0xe0 0xf3
+# CHECK: vabdl.u32	q8, d16, d17
+
+0xb1 0x07 0x42 0xf2
+# CHECK: vaba.s8	d16, d18, d17
+0xb1 0x07 0x52 0xf2
+# CHECK: vaba.s16	d16, d18, d17
+0xb1 0x07 0x62 0xf2
+# CHECK: vaba.s32	d16, d18, d17
+0xb1 0x07 0x42 0xf3
+# CHECK: vaba.u8	d16, d18, d17
+0xb1 0x07 0x52 0xf3
+# CHECK: vaba.u16	d16, d18, d17
+0xb1 0x07 0x62 0xf3
+# CHECK: vaba.u32	d16, d18, d17
+0xf4 0x27 0x40 0xf2
+# CHECK: vaba.s8	q9, q8, q10
+0xf4 0x27 0x50 0xf2
+# CHECK: vaba.s16	q9, q8, q10
+0xf4 0x27 0x60 0xf2
+# CHECK: vaba.s32	q9, q8, q10
+0xf4 0x27 0x40 0xf3
+# CHECK: vaba.u8	q9, q8, q10
+0xf4 0x27 0x50 0xf3
+# CHECK: vaba.u16	q9, q8, q10
+0xf4 0x27 0x60 0xf3
+# CHECK: vaba.u32	q9, q8, q10
+
+0xa2 0x05 0xc3 0xf2
+# CHECK: vabal.s8	q8, d19, d18
+0xa2 0x05 0xd3 0xf2
+# CHECK: vabal.s16	q8, d19, d18
+0xa2 0x05 0xe3 0xf2
+# CHECK: vabal.s32	q8, d19, d18
+0xa2 0x05 0xc3 0xf3
+# CHECK: vabal.u8	q8, d19, d18
+0xa2 0x05 0xd3 0xf3
+# CHECK: vabal.u16	q8, d19, d18
+0xa2 0x05 0xe3 0xf3
+# CHECK: vabal.u32	q8, d19, d18
+
+
+
+
+0xa0 0x08 0x41 0xf2
+# CHECK: vadd.i8	d16, d17, d16
+0xa0 0x08 0x51 0xf2
+# CHECK: vadd.i16	d16, d17, d16
+0xa0 0x08 0x71 0xf2
+# CHECK: vadd.i64	d16, d17, d16
+0xa0 0x08 0x61 0xf2
+# CHECK: vadd.i32	d16, d17, d16
+0xa1 0x0d 0x40 0xf2
+# CHECK: vadd.f32	d16, d16, d17
+0xe2 0x0d 0x40 0xf2
+# CHECK: vadd.f32	q8, q8, q9
+
+0xa0 0x00 0xc1 0xf2
+# CHECK: vaddl.s8	q8, d17, d16
+0xa0 0x00 0xd1 0xf2
+# CHECK: vaddl.s16	q8, d17, d16
+0xa0 0x00 0xe1 0xf2
+# CHECK: vaddl.s32	q8, d17, d16
+0xa0 0x00 0xc1 0xf3
+# CHECK: vaddl.u8	q8, d17, d16
+0xa0 0x00 0xd1 0xf3
+# CHECK: vaddl.u16	q8, d17, d16
+0xa0 0x00 0xe1 0xf3
+# CHECK: vaddl.u32	q8, d17, d16
+
+0xa2 0x01 0xc0 0xf2
+# CHECK: vaddw.s8	q8, q8, d18
+0xa2 0x01 0xd0 0xf2
+# CHECK: vaddw.s16	q8, q8, d18
+0xa2 0x01 0xe0 0xf2
+# CHECK: vaddw.s32	q8, q8, d18
+0xa2 0x01 0xc0 0xf3
+# CHECK: vaddw.u8	q8, q8, d18
+0xa2 0x01 0xd0 0xf3
+# CHECK: vaddw.u16	q8, q8, d18
+0xa2 0x01 0xe0 0xf3
+# CHECK: vaddw.u32	q8, q8, d18
+
+0xa1 0x00 0x40 0xf2
+# CHECK: vhadd.s8	d16, d16, d17
+0xa1 0x00 0x50 0xf2
+# CHECK: vhadd.s16	d16, d16, d17
+0xa1 0x00 0x60 0xf2
+# CHECK: vhadd.s32	d16, d16, d17
+0xa1 0x00 0x40 0xf3
+# CHECK: vhadd.u8	d16, d16, d17
+0xa1 0x00 0x50 0xf3
+# CHECK: vhadd.u16	d16, d16, d17
+0xa1 0x00 0x60 0xf3
+# CHECK: vhadd.u32	d16, d16, d17
+0xe2 0x00 0x40 0xf2
+# CHECK: vhadd.s8	q8, q8, q9
+0xe2 0x00 0x50 0xf2
+# CHECK: vhadd.s16	q8, q8, q9
+0xe2 0x00 0x60 0xf2
+# CHECK: vhadd.s32	q8, q8, q9
+  0xe2 0x00 0x40 0xf3
+# CHECK: vhadd.u8	q8, q8, q9
+0xe2 0x00 0x50 0xf3
+# CHECK: vhadd.u16	q8, q8, q9
+0xe2 0x00 0x60 0xf3
+# CHECK: vhadd.u32	q8, q8, q9
+
+0xa1 0x01 0x40 0xf2
+# CHECK: vrhadd.s8	d16, d16, d17
+0xa1 0x01 0x50 0xf2
+# CHECK: vrhadd.s16	d16, d16, d17
+0xa1 0x01 0x60 0xf2
+# CHECK: vrhadd.s32	d16, d16, d17
+0xa1 0x01 0x40 0xf3
+# CHECK: vrhadd.u8	d16, d16, d17
+0xa1 0x01 0x50 0xf3
+# CHECK: vrhadd.u16	d16, d16, d17
+0xa1 0x01 0x60 0xf3
+# CHECK: vrhadd.u32	d16, d16, d17
+0xe2 0x01 0x40 0xf2
+# CHECK: vrhadd.s8	q8, q8, q9
+0xe2 0x01 0x50 0xf2
+# CHECK: vrhadd.s16	q8, q8, q9
+0xe2 0x01 0x60 0xf2
+# CHECK: vrhadd.s32	q8, q8, q9
+0xe2 0x01 0x40 0xf3
+# CHECK: vrhadd.u8	q8, q8, q9
+0xe2 0x01 0x50 0xf3
+# CHECK: vrhadd.u16	q8, q8, q9
+0xe2 0x01 0x60 0xf3
+# CHECK: vrhadd.u32	q8, q8, q9
+
+0xb1 0x00 0x40 0xf2
+# CHECK: vqadd.s8	d16, d16, d17
+0xb1 0x00 0x50 0xf2
+# CHECK: vqadd.s16	d16, d16, d17
+0xb1 0x00 0x60 0xf2
+# CHECK: vqadd.s32	d16, d16, d17
+0xb1 0x00 0x70 0xf2
+# CHECK: vqadd.s64	d16, d16, d17
+0xb1 0x00 0x40 0xf3
+# CHECK: vqadd.u8	d16, d16, d17
+0xb1 0x00 0x50 0xf3
+# CHECK: vqadd.u16	d16, d16, d17
+0xb1 0x00 0x60 0xf3
+# CHECK: vqadd.u32	d16, d16, d17
+0xb1 0x00 0x70 0xf3
+# CHECK: vqadd.u64	d16, d16, d17
+0xf2 0x00 0x40 0xf2
+# CHECK: vqadd.s8	q8, q8, q9
+0xf2 0x00 0x50 0xf2
+# CHECK: vqadd.s16	q8, q8, q9
+0xf2 0x00 0x60 0xf2
+# CHECK: vqadd.s32	q8, q8, q9
+0xf2 0x00 0x70 0xf2
+# CHECK: vqadd.s64	q8, q8, q9
+0xf2 0x00 0x40 0xf3
+# CHECK: vqadd.u8	q8, q8, q9
+0xf2 0x00 0x50 0xf3
+# CHECK: vqadd.u16	q8, q8, q9
+0xf2 0x00 0x60 0xf3
+# CHECK: vqadd.u32	q8, q8, q9
+0xf2 0x00 0x70 0xf3
+# CHECK: vqadd.u64	q8, q8, q9
+
+0xa2 0x04 0xc0 0xf2
+# CHECK: vaddhn.i16	d16, q8, q9
+0xa2 0x04 0xd0 0xf2
+# CHECK: vaddhn.i32	d16, q8, q9
+0xa2 0x04 0xe0 0xf2
+# CHECK: vaddhn.i64	d16, q8, q9
+0xa2 0x04 0xc0 0xf3
+# CHECK: vraddhn.i16	d16, q8, q9
+0xa2 0x04 0xd0 0xf3
+# CHECK: vraddhn.i32	d16, q8, q9
+0xa2 0x04 0xe0 0xf3
+# CHECK: vraddhn.i64	d16, q8, q9
+
+
+0x20 0x05 0xf0 0xf3
+# CHECK: vcnt.8	d16, d16
+0x60 0x05 0xf0 0xf3
+# CHECK: vcnt.8	q8, q8
+0xa0 0x04 0xf0 0xf3
+# CHECK: vclz.i8	d16, d16
+0xa0 0x04 0xf4 0xf3
+# CHECK: vclz.i16	d16, d16
+0xa0 0x04 0xf8 0xf3
+# CHECK: vclz.i32	d16, d16
+0xe0 0x04 0xf0 0xf3
+# CHECK: vclz.i8	q8, q8
+0xe0 0x04 0xf4 0xf3
+# CHECK: vclz.i16	q8, q8
+0xe0 0x04 0xf8 0xf3
+# CHECK: vclz.i32	q8, q8
+0x20 0x04 0xf0 0xf3
+# CHECK: vcls.s8	d16, d16
+0x20 0x04 0xf4 0xf3
+# CHECK: vcls.s16	d16, d16
+0x20 0x04 0xf8 0xf3
+# CHECK: vcls.s32	d16, d16
+0x60 0x04 0xf0 0xf3
+# CHECK: vcls.s8	q8, q8
+0x60 0x04 0xf4 0xf3
+# CHECK: vcls.s16	q8, q8
+0x60 0x04 0xf8 0xf3
+# CHECK: vcls.s32	q8, q8
+
+
+
+
+0xb0 0x01 0x41 0xf2
+# CHECK: vand	d16, d17, d16
+0xf2 0x01 0x40 0xf2
+# CHECK: vand	q8, q8, q9
+
+0xb0 0x01 0x41 0xf3
+# CHECK: veor	d16, d17, d16
+0xf2 0x01 0x40 0xf3
+# CHECK: veor	q8, q8, q9
+
+0xb0 0x01 0x61 0xf2
+# CHECK: vorr	d16, d17, d16
+0xf2 0x01 0x60 0xf2
+# CHECK: vorr	q8, q8, q9
+0x11 0x07 0xc0 0xf2
+# CHECK: vorr.i32	d16, #0x1000000
+0x51 0x07 0xc0 0xf2
+# CHECK: vorr.i32	q8, #0x1000000
+0x50 0x01 0xc0 0xf2
+# CHECK: vorr.i32	q8, #0x0
+
+0xb0 0x01 0x51 0xf2
+# CHECK: vbic	d16, d17, d16
+0xf2 0x01 0x50 0xf2
+# CHECK: vbic	q8, q8, q9
+0x3f 0x07 0xc7 0xf3
+# CHECK: vbic.i32	d16, #0xFF000000
+0x7f 0x07 0xc7 0xf3
+# CHECK: vbic.i32	q8, #0xFF000000
+
+0xb0 0x01 0x71 0xf2
+# CHECK: vorn	d16, d17, d16
+0xf2 0x01 0x70 0xf2
+# CHECK: vorn	q8, q8, q9
+
+0xa0 0x05 0xf0 0xf3
+# CHECK: vmvn	d16, d16
+0xe0 0x05 0xf0 0xf3
+# CHECK: vmvn	q8, q8
+
+0xb0 0x21 0x51 0xf3
+# CHECK: vbsl	d18, d17, d16
+0xf2 0x01 0x54 0xf3
+# CHECK: vbsl	q8, q10, q9
+
+
+# CHECK: vceq.i8	d16, d16, d17
+# CHECK: vceq.i16	d16, d16, d17
+# CHECK: vceq.i32	d16, d16, d17
+# CHECK: vceq.f32	d16, d16, d17
+# CHECK: vceq.i8	q8, q8, q9
+# CHECK: vceq.i16	q8, q8, q9
+# CHECK: vceq.i32	q8, q8, q9
+# CHECK: vceq.f32	q8, q8, q9
+
+0xb1 0x08 0x40 0xf3
+0xb1 0x08 0x50 0xf3
+0xb1 0x08 0x60 0xf3
+0xa1 0x0e 0x40 0xf2
+0xf2 0x08 0x40 0xf3
+0xf2 0x08 0x50 0xf3
+0xf2 0x08 0x60 0xf3
+0xe2 0x0e 0x40 0xf2
+
+# CHECK: vcge.s8	d16, d16, d17
+# CHECK: vcge.s16	d16, d16, d17
+# CHECK: vcge.s32	d16, d16, d17
+# CHECK: vcge.u8	d16, d16, d17
+# CHECK: vcge.u16	d16, d16, d17
+# CHECK: vcge.u32	d16, d16, d17
+# CHECK: vcge.f32	d16, d16, d17
+# CHECK: vcge.s8	q8, q8, q9
+# CHECK: vcge.s16	q8, q8, q9
+# CHECK: vcge.s32	q8, q8, q9
+# CHECK: vcge.u8	q8, q8, q9
+# CHECK: vcge.u16	q8, q8, q9
+# CHECK: vcge.u32	q8, q8, q9
+# CHECK: vcge.f32	q8, q8, q9
+# CHECK: vacge.f32	d16, d16, d17
+# CHECK: vacge.f32	q8, q8, q9
+
+0xb1 0x03 0x40 0xf2
+0xb1 0x03 0x50 0xf2
+0xb1 0x03 0x60 0xf2
+0xb1 0x03 0x40 0xf3
+0xb1 0x03 0x50 0xf3
+0xb1 0x03 0x60 0xf3
+0xa1 0x0e 0x40 0xf3
+0xf2 0x03 0x40 0xf2
+0xf2 0x03 0x50 0xf2
+0xf2 0x03 0x60 0xf2
+0xf2 0x03 0x40 0xf3
+0xf2 0x03 0x50 0xf3
+0xf2 0x03 0x60 0xf3
+0xe2 0x0e 0x40 0xf3
+0xb1 0x0e 0x40 0xf3
+0xf2 0x0e 0x40 0xf3
+
+# CHECK: vcgt.s8	d16, d16, d17
+# CHECK: vcgt.s16	d16, d16, d17
+# CHECK: vcgt.s32	d16, d16, d17
+# CHECK: vcgt.u8	d16, d16, d17
+# CHECK: vcgt.u16	d16, d16, d17
+# CHECK: vcgt.u32	d16, d16, d17
+# CHECK: vcgt.f32	d16, d16, d17
+# CHECK: vcgt.s8	q8, q8, q9
+# CHECK: vcgt.s16	q8, q8, q9
+# CHECK: vcgt.s32	q8, q8, q9
+# CHECK: vcgt.u8	q8, q8, q9
+# CHECK: vcgt.u16	q8, q8, q9
+# CHECK: vcgt.u32	q8, q8, q9
+# CHECK: vcgt.f32	q8, q8, q9
+# CHECK: vacgt.f32	d16, d16, d17
+# CHECK: vacgt.f32	q8, q8, q9
+
+0xa1 0x03 0x40 0xf2
+0xa1 0x03 0x50 0xf2
+0xa1 0x03 0x60 0xf2
+0xa1 0x03 0x40 0xf3
+0xa1 0x03 0x50 0xf3
+0xa1 0x03 0x60 0xf3
+0xa1 0x0e 0x60 0xf3
+0xe2 0x03 0x40 0xf2
+0xe2 0x03 0x50 0xf2
+0xe2 0x03 0x60 0xf2
+0xe2 0x03 0x40 0xf3
+0xe2 0x03 0x50 0xf3
+0xe2 0x03 0x60 0xf3
+0xe2 0x0e 0x60 0xf3
+0xb1 0x0e 0x60 0xf3
+0xf2 0x0e 0x60 0xf3
+
+# CHECK: vtst.8	d16, d16, d17
+# CHECK: vtst.16	d16, d16, d17
+# CHECK: vtst.32	d16, d16, d17
+# CHECK: vtst.8	q8, q8, q9
+# CHECK: vtst.16	q8, q8, q9
+# CHECK: vtst.32	q8, q8, q9
+
+0xb1 0x08 0x40 0xf2
+0xb1 0x08 0x50 0xf2
+0xb1 0x08 0x60 0xf2
+0xf2 0x08 0x40 0xf2
+0xf2 0x08 0x50 0xf2
+0xf2 0x08 0x60 0xf2
+
+# CHECK: vceq.i8	d16, d16, #0
+# CHECK: vcge.s8	d16, d16, #0
+# CHECK: vcle.s8	d16, d16, #0
+# CHECK: vcgt.s8	d16, d16, #0
+# CHECK: vclt.s8	d16, d16, #0
+
+0x20 0x01 0xf1 0xf3
+0xa0 0x00 0xf1 0xf3
+0xa0 0x01 0xf1 0xf3
+0x20 0x00 0xf1 0xf3
+0x20 0x02 0xf1 0xf3
+
+
+0x20 0x07 0xfb 0xf3
+# CHECK: vcvt.s32.f32	d16, d16
+0xa0 0x07 0xfb 0xf3
+# CHECK: vcvt.u32.f32	d16, d16
+0x20 0x06 0xfb 0xf3
+# CHECK: vcvt.f32.s32	d16, d16
+0xa0 0x06 0xfb 0xf3
+# CHECK: vcvt.f32.u32	d16, d16
+0x60 0x07 0xfb 0xf3
+# CHECK: vcvt.s32.f32	q8, q8
+0xe0 0x07 0xfb 0xf3
+# CHECK: vcvt.u32.f32	q8, q8
+0x60 0x06 0xfb 0xf3
+# CHECK: vcvt.f32.s32	q8, q8
+0xe0 0x06 0xfb 0xf3
+# CHECK: vcvt.f32.u32	q8, q8
+0x30 0x0f 0xff 0xf2
+# CHECK: vcvt.s32.f32	d16, d16, #1
+0x30 0x0f 0xff 0xf3
+# CHECK: vcvt.u32.f32	d16, d16, #1
+0x30 0x0e 0xff 0xf2
+# CHECK: vcvt.f32.s32	d16, d16, #1
+0x30 0x0e 0xff 0xf3
+# CHECK: vcvt.f32.u32	d16, d16, #1
+0x70 0x0f 0xff 0xf2
+# CHECK: vcvt.s32.f32	q8, q8, #1
+0x70 0x0f 0xff 0xf3
+# CHECK: vcvt.u32.f32	q8, q8, #1
+0x70 0x0e 0xff 0xf2
+# CHECK: vcvt.f32.s32	q8, q8, #1
+0x70 0x0e 0xff 0xf3
+# CHECK: vcvt.f32.u32	q8, q8, #1
+0x20 0x07 0xf6 0xf3
+# CHECK: vcvt.f32.f16	q8, d16
+0x20 0x06 0xf6 0xf3
+# CHECK: vcvt.f16.f32	d16, q8
+
+
+
+
+# CHECK: vdup.8	d16, r0
+# CHECK: vdup.16	d16, r0
+# CHECK: vdup.32	d16, r0
+
+0x90 0x0b 0xc0 0xee
+0xb0 0x0b 0x80 0xee
+0x90 0x0b 0x80 0xee
+
+# CHECK: vdup.8	q8, r0
+# CHECK: vdup.16	q8, r0
+# CHECK: vdup.32	q8, r0
+
+0x90 0x0b 0xe0 0xee
+0xb0 0x0b 0xa0 0xee
+0x90 0x0b 0xa0 0xee
+
+# CHECK: vdup.8	d16, d16[1
+# CHECK: vdup.16	d16, d16[1
+# CHECK: vdup.32	d16, d16[1
+
+0x20 0x0c 0xf3 0xf3
+0x20 0x0c 0xf6 0xf3
+0x20 0x0c 0xfc 0xf3
+
+# CHECK: vdup.8	q8, d16[1
+# CHECK: vdup.16	q8, d16[1
+# CHECK: vdup.32	q8, d16[1
+
+0x60 0x0c 0xf3 0xf3
+0x60 0x0c 0xf6 0xf3
+0x60 0x0c 0xfc 0xf3
+
+
+0xb1 0x06 0x40 0xf2
+# CHECK: vmin.s8	d16, d16, d17
+0xb1 0x06 0x50 0xf2
+# CHECK: vmin.s16	d16, d16, d17
+0xb1 0x06 0x60 0xf2
+# CHECK: vmin.s32	d16, d16, d17
+0xb1 0x06 0x40 0xf3
+# CHECK: vmin.u8	d16, d16, d17
+0xb1 0x06 0x50 0xf3
+# CHECK: vmin.u16	d16, d16, d17
+0xb1 0x06 0x60 0xf3
+# CHECK: vmin.u32	d16, d16, d17
+0xa1 0x0f 0x60 0xf2
+# CHECK: vmin.f32	d16, d16, d17
+0xf2 0x06 0x40 0xf2
+# CHECK: vmin.s8	q8, q8, q9
+0xf2 0x06 0x50 0xf2
+# CHECK: vmin.s16	q8, q8, q9
+0xf2 0x06 0x60 0xf2
+# CHECK: vmin.s32	q8, q8, q9
+0xf2 0x06 0x40 0xf3
+# CHECK: vmin.u8	q8, q8, q9
+0xf2 0x06 0x50 0xf3
+# CHECK: vmin.u16	q8, q8, q9
+0xf2 0x06 0x60 0xf3
+# CHECK: vmin.u32	q8, q8, q9
+0xe2 0x0f 0x60 0xf2
+# CHECK: vmin.f32	q8, q8, q9
+0xa1 0x06 0x40 0xf2
+# CHECK: vmax.s8	d16, d16, d17
+0xa1 0x06 0x50 0xf2
+# CHECK: vmax.s16	d16, d16, d17
+0xa1 0x06 0x60 0xf2
+# CHECK: vmax.s32	d16, d16, d17
+0xa1 0x06 0x40 0xf3
+# CHECK: vmax.u8	d16, d16, d17
+0xa1 0x06 0x50 0xf3
+# CHECK: vmax.u16	d16, d16, d17
+0xa1 0x06 0x60 0xf3
+# CHECK: vmax.u32	d16, d16, d17
+0xa1 0x0f 0x40 0xf2
+# CHECK: vmax.f32	d16, d16, d17
+0xe2 0x06 0x40 0xf2
+# CHECK: vmax.s8	q8, q8, q9
+0xe2 0x06 0x50 0xf2
+# CHECK: vmax.s16	q8, q8, q9
+0xe2 0x06 0x60 0xf2
+# CHECK: vmax.s32	q8, q8, q9
+0xe2 0x06 0x40 0xf3
+# CHECK: vmax.u8	q8, q8, q9
+0xe2 0x06 0x50 0xf3
+# CHECK: vmax.u16	q8, q8, q9
+0xe2 0x06 0x60 0xf3
+# CHECK: vmax.u32	q8, q8, q9
+0xe2 0x0f 0x40 0xf2
+# CHECK: vmax.f32	q8, q8, q9
+
+
+
+0x18 0x0e 0xc0 0xf2
+# CHECK: vmov.i8	d16, #0x8
+0x10 0x08 0xc1 0xf2
+# CHECK: vmov.i16	d16, #0x10
+0x10 0x0a 0xc1 0xf2
+# CHECK: vmov.i16	d16, #0x1000
+0x10 0x00 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x20
+0x10 0x02 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x2000
+0x10 0x04 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x200000
+0x10 0x06 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x20000000
+0x10 0x0c 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x20FF
+0x10 0x0d 0xc2 0xf2
+# CHECK: vmov.i32	d16, #0x20FFFF
+0x33 0x0e 0xc1 0xf3
+# CHECK: vmov.i64	d16, #0xFF0000FF0000FFFF
+0x58 0x0e 0xc0 0xf2
+# CHECK: vmov.i8	q8, #0x8
+0x50 0x08 0xc1 0xf2
+# CHECK: vmov.i16	q8, #0x10
+0x50 0x0a 0xc1 0xf2
+# CHECK: vmov.i16	q8, #0x1000
+0x50 0x00 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x20
+0x50 0x02 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x2000
+0x50 0x04 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x200000
+0x50 0x06 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x20000000
+0x50 0x0c 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x20FF
+0x50 0x0d 0xc2 0xf2
+# CHECK: vmov.i32	q8, #0x20FFFF
+0x73 0x0e 0xc1 0xf3
+# CHECK: vmov.i64	q8, #0xFF0000FF0000FFFF
+0x30 0x08 0xc1 0xf2
+# CHECK: vmvn.i16	d16, #0x10
+0x30 0x0a 0xc1 0xf2
+# CHECK: vmvn.i16	d16, #0x1000
+0x30 0x00 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x20
+0x30 0x02 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x2000
+0x30 0x04 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x200000
+0x30 0x06 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x20000000
+0x30 0x0c 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x20FF
+0x30 0x0d 0xc2 0xf2
+# CHECK: vmvn.i32	d16, #0x20FFFF
+0x30 0x0a 0xc8 0xf2
+# CHECK: vmovl.s8	q8, d16
+0x30 0x0a 0xd0 0xf2
+# CHECK: vmovl.s16	q8, d16
+0x30 0x0a 0xe0 0xf2
+# CHECK: vmovl.s32	q8, d16
+0x30 0x0a 0xc8 0xf3
+# CHECK: vmovl.u8	q8, d16
+0x30 0x0a 0xd0 0xf3
+# CHECK: vmovl.u16	q8, d16
+0x30 0x0a 0xe0 0xf3
+# CHECK: vmovl.u32	q8, d16
+0x20 0x02 0xf2 0xf3
+# CHECK: vmovn.i16	d16, q8
+0x20 0x02 0xf6 0xf3
+# CHECK: vmovn.i32	d16, q8
+0x20 0x02 0xfa 0xf3
+# CHECK: vmovn.i64	d16, q8
+0xa0 0x02 0xf2 0xf3
+# CHECK: vqmovn.s16	d16, q8
+0xa0 0x02 0xf6 0xf3
+# CHECK: vqmovn.s32	d16, q8
+0xa0 0x02 0xfa 0xf3
+# CHECK: vqmovn.s64	d16, q8
+0xe0 0x02 0xf2 0xf3
+# CHECK: vqmovn.u16	d16, q8
+0xe0 0x02 0xf6 0xf3
+# CHECK: vqmovn.u32	d16, q8
+0xe0 0x02 0xfa 0xf3
+# CHECK: vqmovn.u64	d16, q8
+0x60 0x02 0xf2 0xf3
+# CHECK: vqmovun.s16	d16, q8
+0x60 0x02 0xf6 0xf3
+# CHECK: vqmovun.s32	d16, q8
+0x60 0x02 0xfa 0xf3
+# CHECK: vqmovun.s64	d16, q8
+0xb0 0x0b 0x50 0xee
+# CHECK: vmov.s8	r0, d16[1
+0xf0 0x0b 0x10 0xee
+# CHECK: vmov.s16	r0, d16[1
+0xb0 0x0b 0xd0 0xee
+# CHECK: vmov.u8	r0, d16[1
+0xf0 0x0b 0x90 0xee
+# CHECK: vmov.u16	r0, d16[1
+0x90 0x0b 0x30 0xee
+# CHECK: vmov.32	r0, d16[1
+0xb0 0x1b 0x40 0xee
+# CHECK: vmov.8	d16[1], r1
+0xf0 0x1b 0x00 0xee
+# CHECK: vmov.16	d16[1], r1
+0x90 0x1b 0x20 0xee
+# CHECK: vmov.32	d16[1], r1
+0xb0 0x1b 0x42 0xee
+# CHECK: vmov.8	d18[1], r1
+0xf0 0x1b 0x02 0xee
+# CHECK: vmov.16	d18[1], r1
+0x90 0x1b 0x22 0xee
+# CHECK: vmov.32	d18[1], r1
+
+
+
+0xa1 0x09 0x42 0xf2
+# CHECK: vmla.i8	d16, d18, d17
+0xa1 0x09 0x52 0xf2
+# CHECK: vmla.i16	d16, d18, d17
+0xa1 0x09 0x62 0xf2
+# CHECK: vmla.i32	d16, d18, d17
+0xb1 0x0d 0x42 0xf2
+# CHECK: vmla.f32	d16, d18, d17
+0xe4 0x29 0x40 0xf2
+# CHECK: vmla.i8	q9, q8, q10
+0xe4 0x29 0x50 0xf2
+# CHECK: vmla.i16	q9, q8, q10
+0xe4 0x29 0x60 0xf2
+# CHECK: vmla.i32	q9, q8, q10
+0xf4 0x2d 0x40 0xf2
+# CHECK: vmla.f32	q9, q8, q10
+0xa2 0x08 0xc3 0xf2
+# CHECK: vmlal.s8	q8, d19, d18
+0xa2 0x08 0xd3 0xf2
+# CHECK: vmlal.s16	q8, d19, d18
+0xa2 0x08 0xe3 0xf2
+# CHECK: vmlal.s32	q8, d19, d18
+0xa2 0x08 0xc3 0xf3
+# CHECK: vmlal.u8	q8, d19, d18
+0xa2 0x08 0xd3 0xf3
+# CHECK: vmlal.u16	q8, d19, d18
+0xa2 0x08 0xe3 0xf3
+# CHECK: vmlal.u32	q8, d19, d18
+0xa2 0x09 0xd3 0xf2
+# CHECK: vqdmlal.s16	q8, d19, d18
+0xa2 0x09 0xe3 0xf2
+# CHECK: vqdmlal.s32	q8, d19, d18
+0xa1 0x09 0x42 0xf3
+# CHECK: vmls.i8	d16, d18, d17
+0xa1 0x09 0x52 0xf3
+# CHECK: vmls.i16	d16, d18, d17
+0xa1 0x09 0x62 0xf3
+# CHECK: vmls.i32	d16, d18, d17
+0xb1 0x0d 0x62 0xf2
+# CHECK: vmls.f32	d16, d18, d17
+0xe4 0x29 0x40 0xf3
+# CHECK: vmls.i8	q9, q8, q10
+0xe4 0x29 0x50 0xf3
+# CHECK: vmls.i16	q9, q8, q10
+0xe4 0x29 0x60 0xf3
+# CHECK: vmls.i32	q9, q8, q10
+0xf4 0x2d 0x60 0xf2
+# CHECK: vmls.f32	q9, q8, q10
+0xa2 0x0a 0xc3 0xf2
+# CHECK: vmlsl.s8	q8, d19, d18
+0xa2 0x0a 0xd3 0xf2
+# CHECK: vmlsl.s16	q8, d19, d18
+0xa2 0x0a 0xe3 0xf2
+# CHECK: vmlsl.s32	q8, d19, d18
+0xa2 0x0a 0xc3 0xf3
+# CHECK: vmlsl.u8	q8, d19, d18
+0xa2 0x0a 0xd3 0xf3
+# CHECK: vmlsl.u16	q8, d19, d18
+0xa2 0x0a 0xe3 0xf3
+# CHECK: vmlsl.u32	q8, d19, d18
+0xa2 0x0b 0xd3 0xf2
+# CHECK: vqdmlsl.s16	q8, d19, d18
+0xa2 0x0b 0xe3 0xf2
+# CHECK: vqdmlsl.s32	q8, d19, d18
+
+
+0xb1 0x09 0x40 0xf2
+# CHECK: vmul.i8	d16, d16, d17
+0xb1 0x09 0x50 0xf2
+# CHECK: vmul.i16	d16, d16, d17
+0xb1 0x09 0x60 0xf2
+# CHECK: vmul.i32	d16, d16, d17
+0xb1 0x0d 0x40 0xf3
+# CHECK: vmul.f32	d16, d16, d17
+0xf2 0x09 0x40 0xf2
+# CHECK: vmul.i8	q8, q8, q9
+0xf2 0x09 0x50 0xf2
+# CHECK: vmul.i16	q8, q8, q9
+0xf2 0x09 0x60 0xf2
+# CHECK: vmul.i32	q8, q8, q9
+0xf2 0x0d 0x40 0xf3
+# CHECK: vmul.f32	q8, q8, q9
+0xb1 0x09 0x40 0xf3
+# CHECK: vmul.p8	d16, d16, d17
+0xf2 0x09 0x40 0xf3
+# CHECK: vmul.p8	q8, q8, q9
+0xa1 0x0b 0x50 0xf2
+# CHECK: vqdmulh.s16	d16, d16, d17
+0xa1 0x0b 0x60 0xf2
+# CHECK: vqdmulh.s32	d16, d16, d17
+0xe2 0x0b 0x50 0xf2
+# CHECK: vqdmulh.s16	q8, q8, q9
+0xe2 0x0b 0x60 0xf2
+# CHECK: vqdmulh.s32	q8, q8, q9
+0xa1 0x0b 0x50 0xf3
+# CHECK: vqrdmulh.s16	d16, d16, d17
+0xa1 0x0b 0x60 0xf3
+# CHECK: vqrdmulh.s32	d16, d16, d17
+0xe2 0x0b 0x50 0xf3
+# CHECK: vqrdmulh.s16	q8, q8, q9
+0xe2 0x0b 0x60 0xf3
+# CHECK: vqrdmulh.s32	q8, q8, q9
+0xa1 0x0c 0xc0 0xf2
+# CHECK: vmull.s8	q8, d16, d17
+0xa1 0x0c 0xd0 0xf2
+# CHECK: vmull.s16	q8, d16, d17
+0xa1 0x0c 0xe0 0xf2
+# CHECK: vmull.s32	q8, d16, d17
+0xa1 0x0c 0xc0 0xf3
+# CHECK: vmull.u8	q8, d16, d17
+0xa1 0x0c 0xd0 0xf3
+# CHECK: vmull.u16	q8, d16, d17
+0xa1 0x0c 0xe0 0xf3
+# CHECK: vmull.u32	q8, d16, d17
+0xa1 0x0e 0xc0 0xf2
+# CHECK: vmull.p8	q8, d16, d17
+0xa1 0x0d 0xd0 0xf2
+# CHECK: vqdmull.s16	q8, d16, d17
+0xa1 0x0d 0xe0 0xf2
+# CHECK: vqdmull.s32	q8, d16, d17
+
+
+0xa0 0x03 0xf1 0xf3
+# CHECK: vneg.s8	d16, d16
+0xa0 0x03 0xf5 0xf3
+# CHECK: vneg.s16	d16, d16
+0xa0 0x03 0xf9 0xf3
+# CHECK: vneg.s32	d16, d16
+0xa0 0x07 0xf9 0xf3
+# CHECK: vneg.f32	d16, d16
+0xe0 0x03 0xf1 0xf3
+# CHECK: vneg.s8	q8, q8
+0xe0 0x03 0xf5 0xf3
+# CHECK: vneg.s16	q8, q8
+0xe0 0x03 0xf9 0xf3
+# CHECK: vneg.s32	q8, q8
+0xe0 0x07 0xf9 0xf3
+# CHECK: vneg.f32	q8, q8
+0xa0 0x07 0xf0 0xf3
+# CHECK: vqneg.s8	d16, d16
+0xa0 0x07 0xf4 0xf3
+# CHECK: vqneg.s16	d16, d16
+0xa0 0x07 0xf8 0xf3
+# CHECK: vqneg.s32	d16, d16
+0xe0 0x07 0xf0 0xf3
+# CHECK: vqneg.s8	q8, q8
+0xe0 0x07 0xf4 0xf3
+# CHECK: vqneg.s16	q8, q8
+0xe0 0x07 0xf8 0xf3
+# CHECK: vqneg.s32	q8, q8
+
+
+0xb0 0x0b 0x41 0xf2
+# CHECK: vpadd.i8	d16, d17, d16
+0xb0 0x0b 0x51 0xf2
+# CHECK: vpadd.i16	d16, d17, d16
+0xb0 0x0b 0x61 0xf2
+# CHECK: vpadd.i32	d16, d17, d16
+0xa1 0x0d 0x40 0xf3
+# CHECK: vpadd.f32	d16, d16, d17
+0x20 0x02 0xf0 0xf3
+# CHECK: vpaddl.s8	d16, d16
+0x20 0x02 0xf4 0xf3
+# CHECK: vpaddl.s16	d16, d16
+0x20 0x02 0xf8 0xf3
+# CHECK: vpaddl.s32	d16, d16
+0xa0 0x02 0xf0 0xf3
+# CHECK: vpaddl.u8	d16, d16
+0xa0 0x02 0xf4 0xf3
+# CHECK: vpaddl.u16	d16, d16
+0xa0 0x02 0xf8 0xf3
+# CHECK: vpaddl.u32	d16, d16
+0x60 0x02 0xf0 0xf3
+# CHECK: vpaddl.s8	q8, q8
+0x60 0x02 0xf4 0xf3
+# CHECK: vpaddl.s16	q8, q8
+0x60 0x02 0xf8 0xf3
+# CHECK: vpaddl.s32	q8, q8
+0xe0 0x02 0xf0 0xf3
+# CHECK: vpaddl.u8	q8, q8
+0xe0 0x02 0xf4 0xf3
+# CHECK: vpaddl.u16	q8, q8
+0xe0 0x02 0xf8 0xf3
+# CHECK: vpaddl.u32	q8, q8
+0x21 0x06 0xf0 0xf3
+# CHECK: vpadal.s8	d16, d17
+0x21 0x06 0xf4 0xf3
+# CHECK: vpadal.s16	d16, d17
+0x21 0x06 0xf8 0xf3
+# CHECK: vpadal.s32	d16, d17
+0xa1 0x06 0xf0 0xf3
+# CHECK: vpadal.u8	d16, d17
+0xa1 0x06 0xf4 0xf3
+# CHECK: vpadal.u16	d16, d17
+0xa1 0x06 0xf8 0xf3
+# CHECK: vpadal.u32	d16, d17
+0x60 0x26 0xf0 0xf3
+# CHECK: vpadal.s8	q9, q8
+0x60 0x26 0xf4 0xf3
+# CHECK: vpadal.s16	q9, q8
+0x60 0x26 0xf8 0xf3
+# CHECK: vpadal.s32	q9, q8
+0xe0 0x26 0xf0 0xf3
+# CHECK: vpadal.u8	q9, q8
+0xe0 0x26 0xf4 0xf3
+# CHECK: vpadal.u16	q9, q8
+0xe0 0x26 0xf8 0xf3
+# CHECK: vpadal.u32	q9, q8
+0xb1 0x0a 0x40 0xf2
+# CHECK: vpmin.s8	d16, d16, d17
+0xb1 0x0a 0x50 0xf2
+# CHECK: vpmin.s16	d16, d16, d17
+0xb1 0x0a 0x60 0xf2
+# CHECK: vpmin.s32	d16, d16, d17
+0xb1 0x0a 0x40 0xf3
+# CHECK: vpmin.u8	d16, d16, d17
+0xb1 0x0a 0x50 0xf3
+# CHECK: vpmin.u16	d16, d16, d17
+0xb1 0x0a 0x60 0xf3
+# CHECK: vpmin.u32	d16, d16, d17
+0xa1 0x0f 0x60 0xf3
+# CHECK: vpmin.f32	d16, d16, d17
+0xa1 0x0a 0x40 0xf2
+# CHECK: vpmax.s8	d16, d16, d17
+0xa1 0x0a 0x50 0xf2
+# CHECK: vpmax.s16	d16, d16, d17
+0xa1 0x0a 0x60 0xf2
+# CHECK: vpmax.s32	d16, d16, d17
+0xa1 0x0a 0x40 0xf3
+# CHECK: vpmax.u8	d16, d16, d17
+0xa1 0x0a 0x50 0xf3
+# CHECK: vpmax.u16	d16, d16, d17
+0xa1 0x0a 0x60 0xf3
+# CHECK: vpmax.u32	d16, d16, d17
+0xa1 0x0f 0x40 0xf3
+# CHECK: vpmax.f32	d16, d16, d17
+
+
+0x20 0x04 0xfb 0xf3
+# CHECK: vrecpe.u32	d16, d16
+0x60 0x04 0xfb 0xf3
+# CHECK: vrecpe.u32	q8, q8
+0x20 0x05 0xfb 0xf3
+# CHECK: vrecpe.f32	d16, d16
+0x60 0x05 0xfb 0xf3
+# CHECK: vrecpe.f32	q8, q8
+0xb1 0x0f 0x40 0xf2
+# CHECK: vrecps.f32	d16, d16, d17
+0xf2 0x0f 0x40 0xf2
+# CHECK: vrecps.f32	q8, q8, q9
+0xa0 0x04 0xfb 0xf3
+# CHECK: vrsqrte.u32	d16, d16
+0xe0 0x04 0xfb 0xf3
+# CHECK: vrsqrte.u32	q8, q8
+0xa0 0x05 0xfb 0xf3
+# CHECK: vrsqrte.f32	d16, d16
+0xe0 0x05 0xfb 0xf3
+# CHECK: vrsqrte.f32	q8, q8
+0xb1 0x0f 0x60 0xf2
+# CHECK: vrsqrts.f32	d16, d16, d17
+0xf2 0x0f 0x60 0xf2
+# CHECK: vrsqrts.f32	q8, q8, q9
+
+
+0x20 0x00 0xf0 0xf3
+# CHECK: vrev64.8	d16, d16
+0x20 0x00 0xf4 0xf3
+# CHECK: vrev64.16	d16, d16
+0x20 0x00 0xf8 0xf3
+# CHECK: vrev64.32	d16, d16
+0x60 0x00 0xf0 0xf3
+# CHECK: vrev64.8	q8, q8
+0x60 0x00 0xf4 0xf3
+# CHECK: vrev64.16	q8, q8
+0x60 0x00 0xf8 0xf3
+# CHECK: vrev64.32	q8, q8
+0xa0 0x00 0xf0 0xf3
+# CHECK: vrev32.8	d16, d16
+0xa0 0x00 0xf4 0xf3
+# CHECK: vrev32.16	d16, d16
+0xe0 0x00 0xf0 0xf3
+# CHECK: vrev32.8	q8, q8
+0xe0 0x00 0xf4 0xf3
+# CHECK: vrev32.16	q8, q8
+0x20 0x01 0xf0 0xf3
+# CHECK: vrev16.8	d16, d16
+0x60 0x01 0xf0 0xf3
+# CHECK: vrev16.8	q8, q8
+
+
+0xb0 0x04 0x41 0xf2
+# CHECK: vqshl.s8	d16, d16, d17
+0xb0 0x04 0x51 0xf2
+# CHECK: vqshl.s16	d16, d16, d17
+0xb0 0x04 0x61 0xf2
+# CHECK: vqshl.s32	d16, d16, d17
+0xb0 0x04 0x71 0xf2
+# CHECK: vqshl.s64	d16, d16, d17
+0xb0 0x04 0x41 0xf3
+# CHECK: vqshl.u8	d16, d16, d17
+0xb0 0x04 0x51 0xf3
+# CHECK: vqshl.u16	d16, d16, d17
+0xb0 0x04 0x61 0xf3
+# CHECK: vqshl.u32	d16, d16, d17
+0xb0 0x04 0x71 0xf3
+# CHECK: vqshl.u64	d16, d16, d17
+0xf0 0x04 0x42 0xf2
+# CHECK: vqshl.s8	q8, q8, q9
+0xf0 0x04 0x52 0xf2
+# CHECK: vqshl.s16	q8, q8, q9
+0xf0 0x04 0x62 0xf2
+# CHECK: vqshl.s32	q8, q8, q9
+0xf0 0x04 0x72 0xf2
+# CHECK: vqshl.s64	q8, q8, q9
+0xf0 0x04 0x42 0xf3
+# CHECK: vqshl.u8	q8, q8, q9
+0xf0 0x04 0x52 0xf3
+# CHECK: vqshl.u16	q8, q8, q9
+0xf0 0x04 0x62 0xf3
+# CHECK: vqshl.u32	q8, q8, q9
+0xf0 0x04 0x72 0xf3
+# CHECK: vqshl.u64	q8, q8, q9
+0x30 0x07 0xcf 0xf2
+# CHECK: vqshl.s8	d16, d16, #7
+0x30 0x07 0xdf 0xf2
+# CHECK: vqshl.s16	d16, d16, #15
+0x30 0x07 0xff 0xf2
+# CHECK: vqshl.s32	d16, d16, #31
+0xb0 0x07 0xff 0xf2
+# CHECK: vqshl.s64	d16, d16, #63
+0x30 0x07 0xcf 0xf3
+# CHECK: vqshl.u8	d16, d16, #7
+0x30 0x07 0xdf 0xf3
+# CHECK: vqshl.u16	d16, d16, #15
+0x30 0x07 0xff 0xf3
+# CHECK: vqshl.u32	d16, d16, #31
+0xb0 0x07 0xff 0xf3
+# CHECK: vqshl.u64	d16, d16, #63
+0x30 0x06 0xcf 0xf3
+# CHECK: vqshlu.s8	d16, d16, #7
+0x30 0x06 0xdf 0xf3
+# CHECK: vqshlu.s16	d16, d16, #15
+0x30 0x06 0xff 0xf3
+# CHECK: vqshlu.s32	d16, d16, #31
+0xb0 0x06 0xff 0xf3
+# CHECK: vqshlu.s64	d16, d16, #63
+0x70 0x07 0xcf 0xf2
+# CHECK: vqshl.s8	q8, q8, #7
+0x70 0x07 0xdf 0xf2
+# CHECK: vqshl.s16	q8, q8, #15
+0x70 0x07 0xff 0xf2
+# CHECK: vqshl.s32	q8, q8, #31
+0xf0 0x07 0xff 0xf2
+# CHECK: vqshl.s64	q8, q8, #63
+0x70 0x07 0xcf 0xf3
+# CHECK: vqshl.u8	q8, q8, #7
+0x70 0x07 0xdf 0xf3
+# CHECK: vqshl.u16	q8, q8, #15
+0x70 0x07 0xff 0xf3
+# CHECK: vqshl.u32	q8, q8, #31
+0xf0 0x07 0xff 0xf3
+# CHECK: vqshl.u64	q8, q8, #63
+0x70 0x06 0xcf 0xf3
+# CHECK: vqshlu.s8	q8, q8, #7
+0x70 0x06 0xdf 0xf3
+# CHECK: vqshlu.s16	q8, q8, #15
+0x70 0x06 0xff 0xf3
+# CHECK: vqshlu.s32	q8, q8, #31
+0xf0 0x06 0xff 0xf3
+# CHECK: vqshlu.s64	q8, q8, #63
+0xb0 0x05 0x41 0xf2
+# CHECK: vqrshl.s8	d16, d16, d17
+0xb0 0x05 0x51 0xf2
+# CHECK: vqrshl.s16	d16, d16, d17
+0xb0 0x05 0x61 0xf2
+# CHECK: vqrshl.s32	d16, d16, d17
+0xb0 0x05 0x71 0xf2
+# CHECK: vqrshl.s64	d16, d16, d17
+0xb0 0x05 0x41 0xf3
+# CHECK: vqrshl.u8	d16, d16, d17
+0xb0 0x05 0x51 0xf3
+# CHECK: vqrshl.u16	d16, d16, d17
+0xb0 0x05 0x61 0xf3
+# CHECK: vqrshl.u32	d16, d16, d17
+0xb0 0x05 0x71 0xf3
+# CHECK: vqrshl.u64	d16, d16, d17
+0xf0 0x05 0x42 0xf2
+# CHECK: vqrshl.s8	q8, q8, q9
+0xf0 0x05 0x52 0xf2
+# CHECK: vqrshl.s16	q8, q8, q9
+0xf0 0x05 0x62 0xf2
+# CHECK: vqrshl.s32	q8, q8, q9
+0xf0 0x05 0x72 0xf2
+# CHECK: vqrshl.s64	q8, q8, q9
+0xf0 0x05 0x42 0xf3
+# CHECK: vqrshl.u8	q8, q8, q9
+0xf0 0x05 0x52 0xf3
+# CHECK: vqrshl.u16	q8, q8, q9
+0xf0 0x05 0x62 0xf3
+# CHECK: vqrshl.u32	q8, q8, q9
+0xf0 0x05 0x72 0xf3
+# CHECK: vqrshl.u64	q8, q8, q9
+0x30 0x09 0xc8 0xf2
+# CHECK: vqshrn.s16	d16, q8, #8
+0x30 0x09 0xd0 0xf2
+# CHECK: vqshrn.s32	d16, q8, #16
+0x30 0x09 0xe0 0xf2
+# CHECK: vqshrn.s64	d16, q8, #32
+0x30 0x09 0xc8 0xf3
+# CHECK: vqshrn.u16	d16, q8, #8
+0x30 0x09 0xd0 0xf3
+# CHECK: vqshrn.u32	d16, q8, #16
+0x30 0x09 0xe0 0xf3
+# CHECK: vqshrn.u64	d16, q8, #32
+0x30 0x08 0xc8 0xf3
+# CHECK: vqshrun.s16	d16, q8, #8
+0x30 0x08 0xd0 0xf3
+# CHECK: vqshrun.s32	d16, q8, #16
+0x30 0x08 0xe0 0xf3
+# CHECK: vqshrun.s64	d16, q8, #32
+0x70 0x09 0xc8 0xf2
+# CHECK: vqrshrn.s16	d16, q8, #8
+0x70 0x09 0xd0 0xf2
+# CHECK: vqrshrn.s32	d16, q8, #16
+0x70 0x09 0xe0 0xf2
+# CHECK: vqrshrn.s64	d16, q8, #32
+0x70 0x09 0xc8 0xf3
+# CHECK: vqrshrn.u16	d16, q8, #8
+0x70 0x09 0xd0 0xf3
+# CHECK: vqrshrn.u32	d16, q8, #16
+0x70 0x09 0xe0 0xf3
+# CHECK: vqrshrn.u64	d16, q8, #32
+0x70 0x08 0xc8 0xf3
+# CHECK: vqrshrun.s16	d16, q8, #8
+0x70 0x08 0xd0 0xf3
+# CHECK: vqrshrun.s32	d16, q8, #16
+0x70 0x08 0xe0 0xf3
+# CHECK: vqrshrun.s64	d16, q8, #32
+
+
+0xa1 0x04 0x40 0xf3
+# CHECK: vshl.u8	d16, d17, d16
+0xa1 0x04 0x50 0xf3
+# CHECK: vshl.u16	d16, d17, d16
+0xa1 0x04 0x60 0xf3
+# CHECK: vshl.u32	d16, d17, d16
+0xa1 0x04 0x70 0xf3
+# CHECK: vshl.u64	d16, d17, d16
+0x30 0x05 0xcf 0xf2
+# CHECK: vshl.i8	d16, d16, #7
+0x30 0x05 0xdf 0xf2
+# CHECK: vshl.i16	d16, d16, #15
+0x30 0x05 0xff 0xf2
+# CHECK: vshl.i32	d16, d16, #31
+0xb0 0x05 0xff 0xf2
+# CHECK: vshl.i64	d16, d16, #63
+0xe2 0x04 0x40 0xf3
+# CHECK: vshl.u8	q8, q9, q8
+0xe2 0x04 0x50 0xf3
+# CHECK: vshl.u16	q8, q9, q8
+0xe2 0x04 0x60 0xf3
+# CHECK: vshl.u32	q8, q9, q8
+0xe2 0x04 0x70 0xf3
+# CHECK: vshl.u64	q8, q9, q8
+0x70 0x05 0xcf 0xf2
+# CHECK: vshl.i8	q8, q8, #7
+0x70 0x05 0xdf 0xf2
+# CHECK: vshl.i16	q8, q8, #15
+0x70 0x05 0xff 0xf2
+# CHECK: vshl.i32	q8, q8, #31
+0xf0 0x05 0xff 0xf2
+# CHECK: vshl.i64	q8, q8, #63
+0x30 0x00 0xc9 0xf3
+# CHECK: vshr.u8	d16, d16, #7
+0x30 0x00 0xd1 0xf3
+# CHECK: vshr.u16	d16, d16, #15
+0x30 0x00 0xe1 0xf3
+# CHECK: vshr.u32	d16, d16, #31
+0xb0 0x00 0xc1 0xf3
+# CHECK: vshr.u64	d16, d16, #63
+0x70 0x00 0xc9 0xf3
+# CHECK: vshr.u8	q8, q8, #7
+0x70 0x00 0xd1 0xf3
+# CHECK: vshr.u16	q8, q8, #15
+0x70 0x00 0xe1 0xf3
+# CHECK: vshr.u32	q8, q8, #31
+0xf0 0x00 0xc1 0xf3
+# CHECK: vshr.u64	q8, q8, #63
+0x30 0x00 0xc9 0xf2
+# CHECK: vshr.s8	d16, d16, #7
+0x30 0x00 0xd1 0xf2
+# CHECK: vshr.s16	d16, d16, #15
+0x30 0x00 0xe1 0xf2
+# CHECK: vshr.s32	d16, d16, #31
+0xb0 0x00 0xc1 0xf2
+# CHECK: vshr.s64	d16, d16, #63
+0x70 0x00 0xc9 0xf2
+# CHECK: vshr.s8	q8, q8, #7
+0x70 0x00 0xd1 0xf2
+# CHECK: vshr.s16	q8, q8, #15
+0x70 0x00 0xe1 0xf2
+# CHECK: vshr.s32	q8, q8, #31
+0xf0 0x00 0xc1 0xf2
+# CHECK: vshr.s64	q8, q8, #63
+0x30 0x01 0xc9 0xf3
+# CHECK: vsra.u8   d16, d16, #7
+0x30 0x01 0xd1 0xf3
+# CHECK: vsra.u16  d16, d16, #15
+0x30 0x01 0xe1 0xf3
+# CHECK: vsra.u32  d16, d16, #31
+0xb0 0x01 0xc1 0xf3
+# CHECK: vsra.u64  d16, d16, #63
+0x70 0x01 0xc9 0xf3
+# CHECK: vsra.u8   q8, q8, #7
+0x70 0x01 0xd1 0xf3
+# CHECK: vsra.u16  q8, q8, #15
+0x70 0x01 0xe1 0xf3
+# CHECK: vsra.u32  q8, q8, #31
+0xf0 0x01 0xc1 0xf3
+# CHECK: vsra.u64  q8, q8, #63
+0x30 0x01 0xc9 0xf2
+# CHECK: vsra.s8   d16, d16, #7
+0x30 0x01 0xd1 0xf2
+# CHECK: vsra.s16  d16, d16, #15
+0x30 0x01 0xe1 0xf2
+# CHECK: vsra.s32  d16, d16, #31
+0xb0 0x01 0xc1 0xf2
+# CHECK: vsra.s64  d16, d16, #63
+0x70 0x01 0xc9 0xf2
+# CHECK: vsra.s8   q8, q8, #7
+0x70 0x01 0xd1 0xf2
+# CHECK: vsra.s16  q8, q8, #15
+0x70 0x01 0xe1 0xf2
+# CHECK: vsra.s32  q8, q8, #31
+0xf0 0x01 0xc1 0xf2
+# CHECK: vsra.s64  q8, q8, #63
+0x30 0x04 0xc9 0xf3
+# CHECK: vsri.8   d16, d16, #7
+0x30 0x04 0xd1 0xf3
+# CHECK: vsri.16  d16, d16, #15
+0x30 0x04 0xe1 0xf3
+# CHECK: vsri.32  d16, d16, #31
+0xb0 0x04 0xc1 0xf3
+# CHECK: vsri.64  d16, d16, #63
+0x70 0x04 0xc9 0xf3
+# CHECK: vsri.8   q8, q8, #7
+0x70 0x04 0xd1 0xf3
+# CHECK: vsri.16  q8, q8, #15
+0x70 0x04 0xe1 0xf3
+# CHECK: vsri.32  q8, q8, #31
+0xf0 0x04 0xc1 0xf3
+# CHECK: vsri.64  q8, q8, #63
+0x30 0x05 0xcf 0xf3
+# CHECK: vsli.8   d16, d16, #7
+0x30 0x05 0xdf 0xf3
+# CHECK: vsli.16  d16, d16, #15
+0x30 0x05 0xff 0xf3
+# CHECK: vsli.32  d16, d16, #31
+0xb0 0x05 0xff 0xf3
+# CHECK: vsli.64  d16, d16, #63
+0x70 0x05 0xcf 0xf3
+# CHECK: vsli.8   q8, q8, #7
+0x70 0x05 0xdf 0xf3
+# CHECK: vsli.16  q8, q8, #15
+0x70 0x05 0xff 0xf3
+# CHECK: vsli.32  q8, q8, #31
+0xf0 0x05 0xff 0xf3
+# CHECK: vsli.64  q8, q8, #63
+0x30 0x0a 0xcf 0xf2
+# CHECK: vshll.s8	q8, d16, #7
+0x30 0x0a 0xdf 0xf2
+# CHECK: vshll.s16	q8, d16, #15
+0x30 0x0a 0xff 0xf2
+# CHECK: vshll.s32	q8, d16, #31
+0x30 0x0a 0xcf 0xf3
+# CHECK: vshll.u8	q8, d16, #7
+0x30 0x0a 0xdf 0xf3
+# CHECK: vshll.u16	q8, d16, #15
+0x30 0x0a 0xff 0xf3
+# CHECK: vshll.u32	q8, d16, #31
+0x20 0x03 0xf2 0xf3
+# CHECK: vshll.i8	q8, d16, #8
+0x20 0x03 0xf6 0xf3
+# CHECK: vshll.i16	q8, d16, #16
+0x20 0x03 0xfa 0xf3
+# CHECK: vshll.i32	q8, d16, #32
+0x30 0x08 0xc8 0xf2
+# CHECK: vshrn.i16	d16, q8, #8
+0x30 0x08 0xd0 0xf2
+# CHECK: vshrn.i32	d16, q8, #16
+0x30 0x08 0xe0 0xf2
+# CHECK: vshrn.i64	d16, q8, #32
+0xa1 0x05 0x40 0xf2
+# CHECK: vrshl.s8	d16, d17, d16
+0xa1 0x05 0x50 0xf2
+# CHECK: vrshl.s16	d16, d17, d16
+0xa1 0x05 0x60 0xf2
+# CHECK: vrshl.s32	d16, d17, d16
+0xa1 0x05 0x70 0xf2
+# CHECK: vrshl.s64	d16, d17, d16
+0xa1 0x05 0x40 0xf3
+# CHECK: vrshl.u8	d16, d17, d16
+0xa1 0x05 0x50 0xf3
+# CHECK: vrshl.u16	d16, d17, d16
+0xa1 0x05 0x60 0xf3
+# CHECK: vrshl.u32	d16, d17, d16
+0xa1 0x05 0x70 0xf3
+# CHECK: vrshl.u64	d16, d17, d16
+0xe2 0x05 0x40 0xf2
+# CHECK: vrshl.s8	q8, q9, q8
+0xe2 0x05 0x50 0xf2
+# CHECK: vrshl.s16	q8, q9, q8
+0xe2 0x05 0x60 0xf2
+# CHECK: vrshl.s32	q8, q9, q8
+0xe2 0x05 0x70 0xf2
+# CHECK: vrshl.s64	q8, q9, q8
+0xe2 0x05 0x40 0xf3
+# CHECK: vrshl.u8	q8, q9, q8
+0xe2 0x05 0x50 0xf3
+# CHECK: vrshl.u16	q8, q9, q8
+0xe2 0x05 0x60 0xf3
+# CHECK: vrshl.u32	q8, q9, q8
+0xe2 0x05 0x70 0xf3
+# CHECK: vrshl.u64	q8, q9, q8
+0x30 0x02 0xc8 0xf2
+# CHECK: vrshr.s8	d16, d16, #8
+0x30 0x02 0xd0 0xf2
+# CHECK: vrshr.s16	d16, d16, #16
+0x30 0x02 0xe0 0xf2
+# CHECK: vrshr.s32	d16, d16, #32
+0xb0 0x02 0xc0 0xf2
+# CHECK: vrshr.s64	d16, d16, #64
+0x30 0x02 0xc8 0xf3
+# CHECK: vrshr.u8	d16, d16, #8
+0x30 0x02 0xd0 0xf3
+# CHECK: vrshr.u16	d16, d16, #16
+0x30 0x02 0xe0 0xf3
+# CHECK: vrshr.u32	d16, d16, #32
+0xb0 0x02 0xc0 0xf3
+# CHECK: vrshr.u64	d16, d16, #64
+0x70 0x02 0xc8 0xf2
+# CHECK: vrshr.s8	q8, q8, #8
+0x70 0x02 0xd0 0xf2
+# CHECK: vrshr.s16	q8, q8, #16
+0x70 0x02 0xe0 0xf2
+# CHECK: vrshr.s32	q8, q8, #32
+0xf0 0x02 0xc0 0xf2
+# CHECK: vrshr.s64	q8, q8, #64
+0x70 0x02 0xc8 0xf3
+# CHECK: vrshr.u8	q8, q8, #8
+0x70 0x02 0xd0 0xf3
+# CHECK: vrshr.u16	q8, q8, #16
+0x70 0x02 0xe0 0xf3
+# CHECK: vrshr.u32	q8, q8, #32
+0xf0 0x02 0xc0 0xf3
+# CHECK: vrshr.u64	q8, q8, #64
+0x70 0x08 0xc8 0xf2
+# CHECK: vrshrn.i16	d16, q8, #8
+0x70 0x08 0xd0 0xf2
+# CHECK: vrshrn.i32	d16, q8, #16
+0x70 0x08 0xe0 0xf2
+# CHECK: vrshrn.i64	d16, q8, #32
+0x70 0x09 0xcc 0xf2
+# CHECK: vqrshrn.s16	d16, q8, #4
+0x70 0x09 0xd3 0xf2
+# CHECK: vqrshrn.s32	d16, q8, #13
+0x70 0x09 0xf3 0xf2
+# CHECK: vqrshrn.s64	d16, q8, #13
+0x70 0x09 0xcc 0xf3
+# CHECK: vqrshrn.u16	d16, q8, #4
+0x70 0x09 0xd3 0xf3
+# CHECK: vqrshrn.u32	d16, q8, #13
+0x70 0x09 0xf3 0xf3
+# CHECK: vqrshrn.u64	d16, q8, #13
+
+
+0x30 0x11 0xc8 0xf2
+# CHECK: vsra.s8	d17, d16, #8
+0x30 0x11 0xd0 0xf2
+# CHECK: vsra.s16	d17, d16, #16
+0x30 0x11 0xe0 0xf2
+# CHECK: vsra.s32	d17, d16, #32
+0xb0 0x11 0xc0 0xf2
+# CHECK: vsra.s64	d17, d16, #64
+0x72 0x01 0xc8 0xf2
+# CHECK: vsra.s8	q8, q9, #8
+0x72 0x01 0xd0 0xf2
+# CHECK: vsra.s16	q8, q9, #16
+0x72 0x01 0xe0 0xf2
+# CHECK: vsra.s32	q8, q9, #32
+0xf2 0x01 0xc0 0xf2
+# CHECK: vsra.s64	q8, q9, #64
+0x30 0x11 0xc8 0xf3
+# CHECK: vsra.u8	d17, d16, #8
+0x30 0x11 0xd0 0xf3
+# CHECK: vsra.u16	d17, d16, #16
+0x30 0x11 0xe0 0xf3
+# CHECK: vsra.u32	d17, d16, #32
+0xb0 0x11 0xc0 0xf3
+# CHECK: vsra.u64	d17, d16, #64
+0x72 0x01 0xc8 0xf3
+# CHECK: vsra.u8	q8, q9, #8
+0x72 0x01 0xd0 0xf3
+# CHECK: vsra.u16	q8, q9, #16
+0x72 0x01 0xe0 0xf3
+# CHECK: vsra.u32	q8, q9, #32
+0xf2 0x01 0xc0 0xf3
+# CHECK: vsra.u64	q8, q9, #64
+0x30 0x13 0xc8 0xf2
+# CHECK: vrsra.s8	d17, d16, #8
+0x30 0x13 0xd0 0xf2
+# CHECK: vrsra.s16	d17, d16, #16
+0x30 0x13 0xe0 0xf2
+# CHECK: vrsra.s32	d17, d16, #32
+0xb0 0x13 0xc0 0xf2
+# CHECK: vrsra.s64	d17, d16, #64
+0x30 0x13 0xc8 0xf3
+# CHECK: vrsra.u8	d17, d16, #8
+0x30 0x13 0xd0 0xf3
+# CHECK: vrsra.u16	d17, d16, #16
+0x30 0x13 0xe0 0xf3
+# CHECK: vrsra.u32	d17, d16, #32
+0xb0 0x13 0xc0 0xf3
+# CHECK: vrsra.u64	d17, d16, #64
+0x72 0x03 0xc8 0xf2
+# CHECK: vrsra.s8	q8, q9, #8
+0x72 0x03 0xd0 0xf2
+# CHECK: vrsra.s16	q8, q9, #16
+0x72 0x03 0xe0 0xf2
+# CHECK: vrsra.s32	q8, q9, #32
+0xf2 0x03 0xc0 0xf2
+# CHECK: vrsra.s64	q8, q9, #64
+0x72 0x03 0xc8 0xf3
+# CHECK: vrsra.u8	q8, q9, #8
+0x72 0x03 0xd0 0xf3
+# CHECK: vrsra.u16	q8, q9, #16
+0x72 0x03 0xe0 0xf3
+# CHECK: vrsra.u32	q8, q9, #32
+0xf2 0x03 0xc0 0xf3
+# CHECK: vrsra.u64	q8, q9, #64
+0x30 0x15 0xcf 0xf3
+# CHECK: vsli.8	d17, d16, #7
+0x30 0x15 0xdf 0xf3
+# CHECK: vsli.16	d17, d16, #15
+0x30 0x15 0xff 0xf3
+# CHECK: vsli.32	d17, d16, #31
+0xb0 0x15 0xff 0xf3
+# CHECK: vsli.64	d17, d16, #63
+0x70 0x25 0xcf 0xf3
+# CHECK: vsli.8	q9, q8, #7
+0x70 0x25 0xdf 0xf3
+# CHECK: vsli.16	q9, q8, #15
+0x70 0x25 0xff 0xf3
+# CHECK: vsli.32	q9, q8, #31
+0xf0 0x25 0xff 0xf3
+# CHECK: vsli.64	q9, q8, #63
+0x30 0x14 0xc8 0xf3
+# CHECK: vsri.8	d17, d16, #8
+0x30 0x14 0xd0 0xf3
+# CHECK: vsri.16	d17, d16, #16
+0x30 0x14 0xe0 0xf3
+# CHECK: vsri.32	d17, d16, #32
+0xb0 0x14 0xc0 0xf3
+# CHECK: vsri.64	d17, d16, #64
+0x70 0x24 0xc8 0xf3
+# CHECK: vsri.8	q9, q8, #8
+0x70 0x24 0xd0 0xf3
+# CHECK: vsri.16	q9, q8, #16
+0x70 0x24 0xe0 0xf3
+# CHECK: vsri.32	q9, q8, #32
+0xf0 0x24 0xc0 0xf3
+# CHECK: vsri.64	q9, q8, #64
+
+
+0xa0 0x03 0xf1 0xf2
+# CHECK: vext.8	d16, d17, d16, #3
+0xa0 0x05 0xf1 0xf2
+# CHECK: vext.8	d16, d17, d16, #5
+0xe0 0x03 0xf2 0xf2
+# CHECK: vext.8	q8, q9, q8, #3
+0xe0 0x07 0xf2 0xf2
+# CHECK: vext.8	q8, q9, q8, #7
+0xa0 0x06 0xf1 0xf2
+# CHECK: vext.16	d16, d17, d16, #3
+0xe0 0x0c 0xf2 0xf2
+# CHECK: vext.32	q8, q9, q8, #3
+0xa0 0x10 0xf2 0xf3
+# CHECK: vtrn.8	d17, d16
+0xa0 0x10 0xf6 0xf3
+# CHECK: vtrn.16	d17, d16
+0xa0 0x10 0xfa 0xf3
+# CHECK: vtrn.32	d17, d16
+0xe0 0x20 0xf2 0xf3
+# CHECK: vtrn.8	q9, q8
+0xe0 0x20 0xf6 0xf3
+# CHECK: vtrn.16	q9, q8
+0xe0 0x20 0xfa 0xf3
+# CHECK: vtrn.32	q9, q8
+0x20 0x11 0xf2 0xf3
+# CHECK: vuzp.8	d17, d16
+0x20 0x11 0xf6 0xf3
+# CHECK: vuzp.16	d17, d16
+0x60 0x21 0xf2 0xf3
+# CHECK: vuzp.8	q9, q8
+0x60 0x21 0xf6 0xf3
+# CHECK: vuzp.16	q9, q8
+0x60 0x21 0xfa 0xf3
+# CHECK: vuzp.32	q9, q8
+0xa0 0x11 0xf2 0xf3
+# CHECK: vzip.8	d17, d16
+0xa0 0x11 0xf6 0xf3
+# CHECK: vzip.16	d17, d16
+0xe0 0x21 0xf2 0xf3
+# CHECK: vzip.8	q9, q8
+0xe0 0x21 0xf6 0xf3
+# CHECK: vzip.16	q9, q8
+0xe0 0x21 0xfa 0xf3
+# CHECK: vzip.32	q9, q8
+
+
+0xa0 0x08 0x41 0xf3
+# CHECK: vsub.i8	d16, d17, d16
+0xa0 0x08 0x51 0xf3
+# CHECK: vsub.i16	d16, d17, d16
+0xa0 0x08 0x61 0xf3
+# CHECK: vsub.i32	d16, d17, d16
+0xa0 0x08 0x71 0xf3
+# CHECK: vsub.i64	d16, d17, d16
+0xa1 0x0d 0x60 0xf2
+# CHECK: vsub.f32	d16, d16, d17
+0xe2 0x08 0x40 0xf3
+# CHECK: vsub.i8	q8, q8, q9
+0xe2 0x08 0x50 0xf3
+# CHECK: vsub.i16	q8, q8, q9
+0xe2 0x08 0x60 0xf3
+# CHECK: vsub.i32	q8, q8, q9
+0xe2 0x08 0x70 0xf3
+# CHECK: vsub.i64	q8, q8, q9
+0xe2 0x0d 0x60 0xf2
+# CHECK: vsub.f32	q8, q8, q9
+0xa0 0x02 0xc1 0xf2
+# CHECK: vsubl.s8	q8, d17, d16
+0xa0 0x02 0xd1 0xf2
+# CHECK: vsubl.s16	q8, d17, d16
+0xa0 0x02 0xe1 0xf2
+# CHECK: vsubl.s32	q8, d17, d16
+0xa0 0x02 0xc1 0xf3
+# CHECK: vsubl.u8	q8, d17, d16
+0xa0 0x02 0xd1 0xf3
+# CHECK: vsubl.u16	q8, d17, d16
+0xa0 0x02 0xe1 0xf3
+# CHECK: vsubl.u32	q8, d17, d16
+0xa2 0x03 0xc0 0xf2
+# CHECK: vsubw.s8	q8, q8, d18
+0xa2 0x03 0xd0 0xf2
+# CHECK: vsubw.s16	q8, q8, d18
+0xa2 0x03 0xe0 0xf2
+# CHECK: vsubw.s32	q8, q8, d18
+0xa2 0x03 0xc0 0xf3
+# CHECK: vsubw.u8	q8, q8, d18
+0xa2 0x03 0xd0 0xf3
+# CHECK: vsubw.u16	q8, q8, d18
+0xa2 0x03 0xe0 0xf3
+# CHECK: vsubw.u32	q8, q8, d18
+0xa1 0x02 0x40 0xf2
+# CHECK: vhsub.s8	d16, d16, d17
+0xa1 0x02 0x50 0xf2
+# CHECK: vhsub.s16	d16, d16, d17
+0xa1 0x02 0x60 0xf2
+# CHECK: vhsub.s32	d16, d16, d17
+0xa1 0x02 0x40 0xf3
+# CHECK: vhsub.u8	d16, d16, d17
+0xa1 0x02 0x50 0xf3
+# CHECK: vhsub.u16	d16, d16, d17
+0xa1 0x02 0x60 0xf3
+# CHECK: vhsub.u32	d16, d16, d17
+0xe2 0x02 0x40 0xf2
+# CHECK: vhsub.s8	q8, q8, q9
+0xe2 0x02 0x50 0xf2
+# CHECK: vhsub.s16	q8, q8, q9
+0xe2 0x02 0x60 0xf2
+# CHECK: vhsub.s32	q8, q8, q9
+0xb1 0x02 0x40 0xf2
+# CHECK: vqsub.s8	d16, d16, d17
+0xb1 0x02 0x50 0xf2
+# CHECK: vqsub.s16	d16, d16, d17
+0xb1 0x02 0x60 0xf2
+# CHECK: vqsub.s32	d16, d16, d17
+0xb1 0x02 0x70 0xf2
+# CHECK: vqsub.s64	d16, d16, d17
+0xb1 0x02 0x40 0xf3
+# CHECK: vqsub.u8	d16, d16, d17
+0xb1 0x02 0x50 0xf3
+# CHECK: vqsub.u16	d16, d16, d17
+0xb1 0x02 0x60 0xf3
+# CHECK: vqsub.u32	d16, d16, d17
+0xb1 0x02 0x70 0xf3
+# CHECK: vqsub.u64	d16, d16, d17
+0xf2 0x02 0x40 0xf2
+# CHECK: vqsub.s8	q8, q8, q9
+0xf2 0x02 0x50 0xf2
+# CHECK: vqsub.s16	q8, q8, q9
+0xf2 0x02 0x60 0xf2
+# CHECK: vqsub.s32	q8, q8, q9
+0xf2 0x02 0x70 0xf2
+# CHECK: vqsub.s64	q8, q8, q9
+0xf2 0x02 0x40 0xf3
+# CHECK: vqsub.u8	q8, q8, q9
+0xf2 0x02 0x50 0xf3
+# CHECK: vqsub.u16	q8, q8, q9
+0xf2 0x02 0x60 0xf3
+# CHECK: vqsub.u32	q8, q8, q9
+0xf2 0x02 0x70 0xf3
+# CHECK: vqsub.u64	q8, q8, q9
+0xa2 0x06 0xc0 0xf2
+# CHECK: vsubhn.i16	d16, q8, q9
+0xa2 0x06 0xd0 0xf2
+# CHECK: vsubhn.i32	d16, q8, q9
+0xa2 0x06 0xe0 0xf2
+# CHECK: vsubhn.i64	d16, q8, q9
+0xa2 0x06 0xc0 0xf3
+# CHECK: vrsubhn.i16	d16, q8, q9
+0xa2 0x06 0xd0 0xf3
+# CHECK: vrsubhn.i32	d16, q8, q9
+0xa2 0x06 0xe0 0xf3
+# CHECK: vrsubhn.i64	d16, q8, q9
+
+
+
+0xa0 0x08 0xf1 0xf3
+# CHECK: vtbl.8	d16, {d17}, d16
+0xa2 0x09 0xf0 0xf3
+# CHECK: vtbl.8	d16, {d16, d17}, d18
+0xa4 0x0a 0xf0 0xf3
+# CHECK: vtbl.8	d16, {d16, d17, d18}, d20
+0xa4 0x0b 0xf0 0xf3
+# CHECK: vtbl.8	d16, {d16, d17, d18, d19}, d20
+0xe1 0x28 0xf0 0xf3
+# CHECK: vtbx.8	d18, {d16}, d17
+0xe2 0x39 0xf0 0xf3
+# CHECK: vtbx.8	d19, {d16, d17}, d18
+0xe5 0x4a 0xf0 0xf3
+# CHECK: vtbx.8	d20, {d16, d17, d18}, d21
+0xe5 0x4b 0xf0 0xf3
+# CHECK: vtbx.8	d20, {d16, d17, d18, d19}, d21
+
+
+
+0x1f 0x07 0x60 0xf4
+# CHECK: vld1.8	{d16}, [r0, :64]
+0x4f 0x07 0x60 0xf4
+# CHECK: vld1.16	{d16}, [r0]
+0x8f 0x07 0x60 0xf4
+# CHECK: vld1.32	{d16}, [r0]
+0xcf 0x07 0x60 0xf4
+# CHECK: vld1.64	{d16}, [r0]
+0x1f 0x0a 0x60 0xf4
+# CHECK: vld1.8	{d16, d17}, [r0, :64]
+0x6f 0x0a 0x60 0xf4
+# CHECK: vld1.16	{d16, d17}, [r0, :128]
+0x8f 0x0a 0x60 0xf4
+# CHECK: vld1.32	{d16, d17}, [r0]
+0xcf 0x0a 0x60 0xf4
+# CHECK: vld1.64	{d16, d17}, [r0]
+
+0x1f 0x08 0x60 0xf4
+# CHECK: vld2.8	{d16, d17}, [r0, :64]
+0x6f 0x08 0x60 0xf4
+# CHECK: vld2.16	{d16, d17}, [r0, :128]
+0x8f 0x08 0x60 0xf4
+# CHECK: vld2.32	{d16, d17}, [r0]
+0x1f 0x03 0x60 0xf4
+# CHECK: vld2.8	{d16, d17, d18, d19}, [r0, :64]
+0x6f 0x03 0x60 0xf4
+# CHECK: vld2.16	{d16, d17, d18, d19}, [r0, :128]
+0xbf 0x03 0x60 0xf4
+# CHECK: vld2.32	{d16, d17, d18, d19}, [r0, :256]
+
+0x1f 0x04 0x60 0xf4
+# CHECK: vld3.8	{d16, d17, d18}, [r0, :64]
+0x4f 0x04 0x60 0xf4
+# CHECK: vld3.16	{d16, d17, d18}, [r0]
+0x8f 0x04 0x60 0xf4
+# CHECK: vld3.32	{d16, d17, d18}, [r0]
+0x1d 0x05 0x60 0xf4
+# CHECK: vld3.8	{d16, d18, d20}, [r0, :64]!
+0x1d 0x15 0x60 0xf4
+# CHECK: vld3.8	{d17, d19, d21}, [r0, :64]!
+0x4d 0x05 0x60 0xf4
+# CHECK: vld3.16	{d16, d18, d20}, [r0]!
+0x4d 0x15 0x60 0xf4
+# CHECK: vld3.16	{d17, d19, d21}, [r0]!
+0x8d 0x05 0x60 0xf4
+# CHECK: vld3.32	{d16, d18, d20}, [r0]!
+0x8d 0x15 0x60 0xf4
+# CHECK: vld3.32	{d17, d19, d21}, [r0]!
+
+0x1f 0x00 0x60 0xf4
+# CHECK: vld4.8	{d16, d17, d18, d19}, [r0, :64]
+0x6f 0x00 0x60 0xf4
+# CHECK: vld4.16	{d16, d17, d18, d19}, [r0, :128]
+0xbf 0x00 0x60 0xf4
+# CHECK: vld4.32	{d16, d17, d18, d19}, [r0, :256]
+0x3d 0x01 0x60 0xf4
+# CHECK: vld4.8	{d16, d18, d20, d22}, [r0, :256]!
+0x3d 0x11 0x60 0xf4
+# CHECK: vld4.8	{d17, d19, d21, d23}, [r0, :256]!
+0x4d 0x01 0x60 0xf4
+# CHECK: vld4.16	{d16, d18, d20, d22}, [r0]!
+0x4d 0x11 0x60 0xf4
+# CHECK: vld4.16	{d17, d19, d21, d23}, [r0]!
+0x8d 0x01 0x60 0xf4
+# CHECK: vld4.32	{d16, d18, d20, d22}, [r0]!
+0x8d 0x11 0x60 0xf4
+# CHECK: vld4.32	{d17, d19, d21, d23}, [r0]!
+
+0x6f 0x00 0xe0 0xf4
+# CHECK: vld1.8	{d16[3]}, [r0]
+0x9f 0x04 0xe0 0xf4
+# CHECK: vld1.16	{d16[2]}, [r0, :16]
+0xbf 0x08 0xe0 0xf4
+# CHECK: vld1.32	{d16[1]}, [r0, :32]
+
+0x3f 0x01 0xe0 0xf4
+# CHECK: vld2.8	{d16[1], d17[1]}, [r0, :16]
+0x5f 0x05 0xe0 0xf4
+# CHECK: vld2.16	{d16[1], d17[1]}, [r0, :32]
+0x8f 0x09 0xe0 0xf4
+# CHECK: vld2.32	{d16[1], d17[1]}, [r0]
+0x6f 0x15 0xe0 0xf4
+# CHECK: vld2.16	{d17[1], d19[1]}, [r0]
+0x5f 0x19 0xe0 0xf4
+# CHECK: vld2.32	{d17[0], d19[0]}, [r0, :64]
+
+0x2f 0x02 0xe0 0xf4
+# CHECK: vld3.8	{d16[1], d17[1], d18[1]}, [r0]
+0x4f 0x06 0xe0 0xf4
+# CHECK: vld3.16	{d16[1], d17[1], d18[1]}, [r0]
+0x8f 0x0a 0xe0 0xf4
+# CHECK: vld3.32	{d16[1], d17[1], d18[1]}, [r0]
+0x6f 0x06 0xe0 0xf4
+# CHECK: vld3.16	{d16[1], d18[1], d20[1]}, [r0]
+0xcf 0x1a 0xe0 0xf4
+# CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
+
+0x3f 0x03 0xe0 0xf4
+# CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
+0x4f 0x07 0xe0 0xf4
+# CHECK: vld4.16	{d16[1], d17[1], d18[1], d19[1]}, [r0]
+0xaf 0x0b 0xe0 0xf4
+# CHECK: vld4.32	{d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
+0x7f 0x07 0xe0 0xf4
+# CHECK: vld4.16	{d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
+0x4f 0x1b 0xe0 0xf4
+# CHECK: vld4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+
+
+0x1f 0x07 0x40 0xf4
+# CHECK: vst1.8	{d16}, [r0, :64]
+0x4f 0x07 0x40 0xf4
+# CHECK: vst1.16	{d16}, [r0]
+0x8f 0x07 0x40 0xf4
+# CHECK: vst1.32	{d16}, [r0]
+0xcf 0x07 0x40 0xf4
+# CHECK: vst1.64	{d16}, [r0]
+0x1f 0x0a 0x40 0xf4
+# CHECK: vst1.8	{d16, d17}, [r0, :64]
+0x6f 0x0a 0x40 0xf4
+# CHECK: vst1.16	{d16, d17}, [r0, :128]
+0x8f 0x0a 0x40 0xf4
+# CHECK: vst1.32	{d16, d17}, [r0]
+0xcf 0x0a 0x40 0xf4
+# CHECK: vst1.64	{d16, d17}, [r0]
+
+0x1f 0x08 0x40 0xf4
+# CHECK: vst2.8	{d16, d17}, [r0, :64]
+0x6f 0x08 0x40 0xf4
+# CHECK: vst2.16	{d16, d17}, [r0, :128]
+0x8f 0x08 0x40 0xf4
+# CHECK: vst2.32	{d16, d17}, [r0]
+0x1f 0x03 0x40 0xf4
+# CHECK: vst2.8	{d16, d17, d18, d19}, [r0, :64]
+0x6f 0x03 0x40 0xf4
+# CHECK: vst2.16	{d16, d17, d18, d19}, [r0, :128]
+0xbf 0x03 0x40 0xf4
+# CHECK: vst2.32	{d16, d17, d18, d19}, [r0, :256]
+
+0x1f 0x04 0x40 0xf4
+# CHECK: vst3.8	{d16, d17, d18}, [r0, :64]
+0x4f 0x04 0x40 0xf4
+# CHECK: vst3.16	{d16, d17, d18}, [r0]
+0x8f 0x04 0x40 0xf4
+# CHECK: vst3.32	{d16, d17, d18}, [r0]
+0x1d 0x05 0x40 0xf4
+# CHECK: vst3.8	{d16, d18, d20}, [r0, :64]!
+0x1d 0x15 0x40 0xf4
+# CHECK: vst3.8	{d17, d19, d21}, [r0, :64]!
+0x4d 0x05 0x40 0xf4
+# CHECK: vst3.16	{d16, d18, d20}, [r0]!
+0x4d 0x15 0x40 0xf4
+# CHECK: vst3.16	{d17, d19, d21}, [r0]!
+0x8d 0x05 0x40 0xf4
+# CHECK: vst3.32	{d16, d18, d20}, [r0]!
+0x8d 0x15 0x40 0xf4
+# CHECK: vst3.32	{d17, d19, d21}, [r0]!
+
+0x1f 0x00 0x40 0xf4
+# CHECK: vst4.8	{d16, d17, d18, d19}, [r0, :64]
+0x6f 0x00 0x40 0xf4
+# CHECK: vst4.16	{d16, d17, d18, d19}, [r0, :128]
+0x3d 0x01 0x40 0xf4
+# CHECK: vst4.8	{d16, d18, d20, d22}, [r0, :256]!
+0x3d 0x11 0x40 0xf4
+# CHECK: vst4.8	{d17, d19, d21, d23}, [r0, :256]!
+0x4d 0x01 0x40 0xf4
+# CHECK: vst4.16	{d16, d18, d20, d22}, [r0]!
+0x4d 0x11 0x40 0xf4
+# CHECK: vst4.16	{d17, d19, d21, d23}, [r0]!
+0x8d 0x01 0x40 0xf4
+# CHECK: vst4.32	{d16, d18, d20, d22}, [r0]!
+0x8d 0x11 0x40 0xf4
+# CHECK: vst4.32	{d17, d19, d21, d23}, [r0]!
+
+0x3f 0x01 0xc0 0xf4
+# CHECK: vst2.8	{d16[1], d17[1]}, [r0, :16]
+0x5f 0x05 0xc0 0xf4
+# CHECK: vst2.16	{d16[1], d17[1]}, [r0, :32]
+0x8f 0x09 0xc0 0xf4
+# CHECK: vst2.32	{d16[1], d17[1]}, [r0]
+0x6f 0x15 0xc0 0xf4
+# CHECK: vst2.16	{d17[1], d19[1]}, [r0]
+0x5f 0x19 0xc0 0xf4
+# CHECK: vst2.32	{d17[0], d19[0]}, [r0, :64]
+
+0x2f 0x02 0xc0 0xf4
+# CHECK: vst3.8	{d16[1], d17[1], d18[1]}, [r0]
+0x4f 0x06 0xc0 0xf4
+# CHECK: vst3.16	{d16[1], d17[1], d18[1]}, [r0]
+0x8f 0x0a 0xc0 0xf4
+# CHECK: vst3.32	{d16[1], d17[1], d18[1]}, [r0]
+0xaf 0x16 0xc0 0xf4
+# CHECK: vst3.16	{d17[2], d19[2], d21[2]}, [r0]
+0x4f 0x0a 0xc0 0xf4
+# CHECK: vst3.32	{d16[0], d18[0], d20[0]}, [r0]
+
+0x3f 0x03 0xc0 0xf4
+# CHECK: vst4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
+0x4f 0x07 0xc0 0xf4
+# CHECK: vst4.16	{d16[1], d17[1], d18[1], d19[1]}, [r0]
+0xaf 0x0b 0xc0 0xf4
+# CHECK: vst4.32	{d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
+0xff 0x17 0xc0 0xf4
+# CHECK: vst4.16	{d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
+0x4f 0x1b 0xc0 0xf4
+# CHECK: vst4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]



From echristo at apple.com  Mon Aug 15 13:47:30 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 11:47:30 -0700
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd
 Rt field
In-Reply-To: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
References: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
Message-ID: <422A3032-1E35-422C-8D8E-645C235FDAE9@apple.com>


On Aug 15, 2011, at 7:50 AM, James Molloy wrote:

> Hi,
>  
> The attached patch causes decoding to fail if the Rt field of an LDRD/STRD is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.
>  
> I wanted to add an assert to the encoder too, but couldn't see an obvious way to do this as the Rt field is decoded by the generic "getMachineOpValue()" function direct from tablegen.
>  

LGTM. Owen? Any objections?

-eric
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From resistor at me.com  Mon Aug 15 13:51:31 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 11:51:31 -0700
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd
 Rt field
In-Reply-To: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
References: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
Message-ID: <EC880D4E-B04D-40A7-9C1A-352118C344B7@me.com>

James, 

This looks good in principle, but I'm seeing a number of failures on MC/Disassembler/ARM/memory-arm-instructions.txt.  Perhaps the old tests need to be updated?

--Owen

On Aug 15, 2011, at 7:50 AM, James Molloy wrote:

> Hi,
>  
> The attached patch causes decoding to fail if the Rt field of an LDRD/STRD is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.
>  
> I wanted to add an assert to the encoder too, but couldn't see an obvious way to do this as the Rt field is decoded by the generic "getMachineOpValue()" function direct from tablegen.
>  
> Cheers,
>  
> James
>  
> <LDRDSTRD.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From resistor at me.com  Mon Aug 15 13:53:03 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 11:53:03 -0700
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <CE2DAC4C-6FE2-4095-8AE8-91F58381E242@apple.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
	<CE2DAC4C-6FE2-4095-8AE8-91F58381E242@apple.com>
Message-ID: <75583386-8CA2-4CE0-9C53-93C9A1C669BA@me.com>


On Aug 15, 2011, at 11:40 AM, Eric Christopher wrote:

> 
> On Aug 15, 2011, at 7:23 AM, James Molloy wrote:
> 
>> Hi,
>>  
>> The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.
>>  
>> Cheers,
>>  
> 
>    let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>    let PrintMethod = "printThumbAddrModeRROperand";
> +  let DecoderMethod = "DecodeThumbAddrModeRR";
>    let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>  }
> 
> This appears to be the actual fix and the rest is some random renaming? Also could you add a test for ldrsh as well?

No, the renaming is necessary because the auto-generated decoder emitter can only auto-generate operand parsers when the names match up.

Otherwise, this looks fine, and I'll apply it, but please do submit a testcase when you can.

--Owen

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From echristo at apple.com  Mon Aug 15 13:53:35 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 11:53:35 -0700
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <75583386-8CA2-4CE0-9C53-93C9A1C669BA@me.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
	<CE2DAC4C-6FE2-4095-8AE8-91F58381E242@apple.com>
	<75583386-8CA2-4CE0-9C53-93C9A1C669BA@me.com>
Message-ID: <C77B8E3D-6FFA-4928-9ACF-5D3014D11DEA@apple.com>


On Aug 15, 2011, at 11:53 AM, Owen Anderson wrote:

> 
> On Aug 15, 2011, at 11:40 AM, Eric Christopher wrote:
> 
>> 
>> On Aug 15, 2011, at 7:23 AM, James Molloy wrote:
>> 
>>> Hi,
>>>  
>>> The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.
>>>  
>>> Cheers,
>>>  
>> 
>>    let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>    let PrintMethod = "printThumbAddrModeRROperand";
>> +  let DecoderMethod = "DecodeThumbAddrModeRR";
>>    let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>  }
>> 
>> This appears to be the actual fix and the rest is some random renaming? Also could you add a test for ldrsh as well?
> 
> No, the renaming is necessary because the auto-generated decoder emitter can only auto-generate operand parsers when the names match up.

Oh yuck, that's heinous.

-eric


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From James.Molloy at arm.com  Mon Aug 15 13:58:50 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 19:58:50 +0100
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <C77B8E3D-6FFA-4928-9ACF-5D3014D11DEA@apple.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
	<CE2DAC4C-6FE2-4095-8AE8-91F58381E242@apple.com>
	<75583386-8CA2-4CE0-9C53-93C9A1C669BA@me.com>
	<C77B8E3D-6FFA-4928-9ACF-5D3014D11DEA@apple.com>
Message-ID: <3D6137FD-4DEE-4476-8DEB-910A6ABBB9C7@arm.com>

You guys beat me to it - typing on this Apple Generic Tablet can be slow ;)

Owen - theres a testcase for ldrsb, do you want one for ldrsh too? The change is identical to both which is why I left creating tests for both.

Up to you guys!


James



On 15 Aug 2011, at 19:54, "Eric Christopher" <echristo at apple.com<mailto:echristo at apple.com>> wrote:


On Aug 15, 2011, at 11:53 AM, Owen Anderson wrote:


On Aug 15, 2011, at 11:40 AM, Eric Christopher wrote:


On Aug 15, 2011, at 7:23 AM, James Molloy wrote:

Hi,

The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.

Cheers,


   let EncoderMethod = "getThumbAddrModeRegRegOpValue";
   let PrintMethod = "printThumbAddrModeRROperand";
+  let DecoderMethod = "DecodeThumbAddrModeRR";
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
 }

This appears to be the actual fix and the rest is some random renaming? Also could you add a test for ldrsh as well?

No, the renaming is necessary because the auto-generated decoder emitter can only auto-generate operand parsers when the names match up.

Oh yuck, that's heinous.

-eric



-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


From resistor at mac.com  Mon Aug 15 14:00:06 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 19:00:06 -0000
Subject: [llvm-commits] [llvm] r137636 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110815190006.7F7322A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 14:00:06 2011
New Revision: 137636

URL: http://llvm.org/viewvc/llvm-project?rev=137636&view=rev
Log:
Fix decoding LDRSB and LDRSH in Thumb1 mode.  Patch by James Molloy.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137636&r1=137635&r2=137636&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 15 14:00:06 2011
@@ -113,6 +113,7 @@
                     ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
   let EncoderMethod = "getThumbAddrModeRegRegOpValue";
   let PrintMethod = "printThumbAddrModeRROperand";
+  let DecoderMethod = "DecodeThumbAddrModeRR";
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
 }
 
@@ -620,17 +621,17 @@
 
 let AddedComplexity = 10 in
 def tLDRSB :                    // A8.6.80
-  T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
+  T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
                  AddrModeT1_1, IIC_iLoad_bh_r,
-                 "ldrsb", "\t$dst, $addr",
-                 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
+                 "ldrsb", "\t$Rt, $addr",
+                 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
 
 let AddedComplexity = 10 in
 def tLDRSH :                    // A8.6.84
-  T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
+  T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
                  AddrModeT1_2, IIC_iLoad_bh_r,
-                 "ldrsh", "\t$dst, $addr",
-                 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
+                 "ldrsh", "\t$Rt, $addr",
+                 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
 
 let canFoldAsLoad = 1 in
 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=137636&r1=137635&r2=137636&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 15 14:00:06 2011
@@ -268,3 +268,6 @@
 
 # CHECK:	vadd.f32	q0, q1, q2
 0x02 0xef 0x44 0x0d
+
+# CHECK:        ldrsb   r1, [r0, r0]
+0x01 0x56



From resistor at me.com  Mon Aug 15 14:01:40 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 12:01:40 -0700
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
Message-ID: <4D6767A3-8B1E-4D95-9D1C-45D2C4008C4F@me.com>

Applied in r137636.  It's still be nice to have a testcase for LDRSH, if only for completeness.

--Owen

On Aug 15, 2011, at 7:23 AM, James Molloy wrote:

> Hi,
>  
> The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.
>  
> Cheers,
>  
> James
> <LDRSB_Thumb.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From dpatel at apple.com  Mon Aug 15 14:01:20 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 19:01:20 -0000
Subject: [llvm-commits] [llvm] r137637 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815190120.B79B02A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 14:01:20 2011
New Revision: 137637

URL: http://llvm.org/viewvc/llvm-project?rev=137637&view=rev
Log:
Simplify mapping to variable from its abstract variable info.
When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137637&r1=137636&r2=137637&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 14:01:20 2011
@@ -383,21 +383,15 @@
   // Define variable debug information entry.
   DIE *VariableDie = new DIE(Tag);
   CompileUnit *VariableCU = getCompileUnit(DV->getVariable());
-  DIE *AbsDIE = NULL;
-  DenseMap<const DbgVariable *, const DbgVariable *>::iterator
-    V2AVI = VarToAbstractVarMap.find(DV);
-  if (V2AVI != VarToAbstractVarMap.end())
-    AbsDIE = V2AVI->second->getDIE();
-
+  DbgVariable *AbsVar = DV->getAbstractVariable();
+  DIE *AbsDIE = AbsVar ? AbsVar->getDIE() : NULL;
   if (AbsDIE)
     VariableCU->addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin,
-                       dwarf::DW_FORM_ref4, AbsDIE);
+                            dwarf::DW_FORM_ref4, AbsDIE);
   else {
-    VariableCU->addString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string,
-                          Name);
+    VariableCU->addString(VariableDie, dwarf::DW_AT_name, 
+                          dwarf::DW_FORM_string, Name);
     VariableCU->addSourceLine(VariableDie, DV->getVariable());
-
-    // Add variable type.
     VariableCU->addType(VariableDie, DV->getType());
   }
 
@@ -812,7 +806,7 @@
       for (unsigned I = 0; I != E; ++I) {
         DIVariable DV(NMD->getOperand(I));
         if (!DV.Verify()) continue;
-        Variables.push_back(DbgVariable(DV));
+        Variables.push_back(DbgVariable(DV, NULL));
       }
 
       // Construct subprogram DIE and add variables DIEs.
@@ -907,7 +901,7 @@
   if (!Scope)
     return NULL;
 
-  AbsDbgVariable = new DbgVariable(Var);
+  AbsDbgVariable = new DbgVariable(Var, NULL);
   addScopeVariable(Scope, AbsDbgVariable);
   AbstractVariables[Var] = AbsDbgVariable;
   return AbsDbgVariable;
@@ -958,14 +952,12 @@
       continue;
 
     DbgVariable *AbsDbgVariable = findAbstractVariable(DV, VP.second);
-    DbgVariable *RegVar = new DbgVariable(DV);
+    DbgVariable *RegVar = new DbgVariable(DV, AbsDbgVariable);
     recordVariableFrameIndex(RegVar, VP.first);
     if (!addCurrentFnArgument(MF, RegVar, Scope))
       addScopeVariable(Scope, RegVar);
-    if (AbsDbgVariable) {
+    if (AbsDbgVariable)
       recordVariableFrameIndex(AbsDbgVariable, VP.first);
-      VarToAbstractVarMap[RegVar] = AbsDbgVariable;
-    }
   }
 }
 
@@ -1049,13 +1041,12 @@
 
     Processed.insert(DV);
     assert(MInsn->isDebugValue() && "History must begin with debug value");
-    DbgVariable *RegVar = new DbgVariable(DV);
+    DbgVariable *AbsVar = findAbstractVariable(DV, MInsn->getDebugLoc());
+    DbgVariable *RegVar = new DbgVariable(DV, AbsVar);
     if (!addCurrentFnArgument(MF, RegVar, Scope))
       addScopeVariable(Scope, RegVar);
-    if (DbgVariable *AbsVar = findAbstractVariable(DV, MInsn->getDebugLoc())) {
+    if (AbsVar)
       DbgVariableToDbgInstMap[AbsVar] = MInsn;
-      VarToAbstractVarMap[RegVar] = AbsVar;
-    }
 
     // Simple ranges that are fully coalesced.
     if (History.size() <= 1 || (History.size() == 2 &&
@@ -1113,7 +1104,7 @@
       if (!DV || !Processed.insert(DV))
         continue;
       if (LexicalScope *Scope = LScopes.findLexicalScope(DV.getContext()))
-        addScopeVariable(Scope, new DbgVariable(DV));
+        addScopeVariable(Scope, new DbgVariable(DV, NULL));
     }
   }
 }
@@ -1455,7 +1446,7 @@
           if (!DV || !ProcessedVars.insert(DV))
             continue;
           if (LexicalScope *Scope = LScopes.findAbstractScope(DV.getContext()))
-            addScopeVariable(Scope, new DbgVariable(DV));
+            addScopeVariable(Scope, new DbgVariable(DV, NULL));
         }
       }
     }
@@ -1481,7 +1472,6 @@
   ScopeVariables.clear();
   DeleteContainerPointers(CurrentFnArguments);
   DbgVariableToFrameIndexMap.clear();
-  VarToAbstractVarMap.clear();
   DbgVariableToDbgInstMap.clear();
   UserVariables.clear();
   DbgValues.clear();

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137637&r1=137636&r2=137637&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 14:01:20 2011
@@ -125,9 +125,11 @@
   DIVariable Var;                    // Variable Descriptor.
   DIE *TheDIE;                       // Variable DIE.
   unsigned DotDebugLocOffset;        // Offset in DotDebugLocEntries.
+  DbgVariable *AbsVar;               // Corresponding Abstract variable, if any.
 public:
   // AbsVar may be NULL.
-  DbgVariable(DIVariable V) : Var(V), TheDIE(0), DotDebugLocOffset(~0U) {}
+  DbgVariable(DIVariable V, DbgVariable *AV) 
+    : Var(V), TheDIE(0), DotDebugLocOffset(~0U), AbsVar(AV) {}
 
   // Accessors.
   DIVariable getVariable()           const { return Var; }
@@ -136,6 +138,7 @@
   void setDotDebugLocOffset(unsigned O)    { DotDebugLocOffset = O; }
   unsigned getDotDebugLocOffset()    const { return DotDebugLocOffset; }
   StringRef getName()                const { return Var.getName(); }
+  DbgVariable *getAbstractVariable() const { return AbsVar; }
   // Translate tag to proper Dwarf tag.  
   unsigned getTag()                  const { 
     if (Var.getTag() == dwarf::DW_TAG_arg_variable)
@@ -236,10 +239,6 @@
   /// idetifies corresponding .debug_loc entry offset.
   SmallPtrSet<const DIE *, 4> UseDotDebugLocEntry;
 
-  /// VarToAbstractVarMap - Maps DbgVariable with corresponding Abstract
-  /// DbgVariable, if any.
-  DenseMap<const DbgVariable *, const DbgVariable *> VarToAbstractVarMap;
-
   /// InliendSubprogramDIEs - Collection of subprgram DIEs that are marked
   /// (at the end of the module) as DW_AT_inline.
   SmallPtrSet<DIE *, 4> InlinedSubprogramDIEs;



From resistor at mac.com  Mon Aug 15 14:04:27 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 12:04:27 -0700
Subject: [llvm-commits] [PATCH] Fixes in ARM TableGen
In-Reply-To: <BB4FE69F-7053-4921-971A-4AD8178684FD@apple.com>
References: <002401cc5b56$c62a0760$527e1620$%molloy@arm.com>
	<F6FAEF0C-1717-40F1-9E15-E78FDCC4F9B9@apple.com>
	<BB4FE69F-7053-4921-971A-4AD8178684FD@apple.com>
Message-ID: <B5DD26B3-0359-4750-A5C0-95158D06496A@mac.com>

Looks good to me as well.  I'll go through and apply it piece-by-piece in a bit.

--Owen

On Aug 15, 2011, at 11:40 AM, Jim Grosbach wrote:

> 
> On Aug 15, 2011, at 11:37 AM, Eric Christopher wrote:
> 
>> 
>> On Aug 15, 2011, at 7:22 AM, James Molloy wrote:
>> 
>>> Hi,
>>> 
>>> The attached patch does three things (they're each so small I kept them in the same patch file - hope this is OK):
>>> 
>>> ?         Fix the field offsets for UMAAL - RdHi and RdLo were the incorrect way around (see A8.6.244). This required a fix to a test.
>>> ?         Set the DecoderMethod for STRH (and other addrmode3 stores) correctly.
>>> ?         Remove two pieces of dead code - class AI3stridx and class AIsthpr in ARMInstrFormats.td were not used anywhere.
>>> 
>>> Cheers,
>>> 
>>> James
>>> <STRH_UMAAL.patch>_______________________________________________
>> 
>> LGTM.
>> 
>> Any objections Jim?
> 
> 
> OK w/ me. I would prefer the changes be checked in as separate patches, though, even though they're very small. Keeps the revision history easier to follow.
> 
> -jim
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From James.Molloy at arm.com  Mon Aug 15 14:13:15 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 20:13:15 +0100
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd
 Rt field
In-Reply-To: <EC880D4E-B04D-40A7-9C1A-352118C344B7@me.com>
References: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
	<EC880D4E-B04D-40A7-9C1A-352118C344B7@me.com>
Message-ID: <517015F1-305A-49D0-AB29-EF19135D50D0@arm.com>

Hi Owen,

I do apologise, it appears my tree was a few days old and those tests didnt exist.

The tests are totally incorrect. I'll attach an updated patch file that adapts the test shortly.

Cheers,

James


On 15 Aug 2011, at 19:52, "Owen Anderson" <resistor at me.com<mailto:resistor at me.com>> wrote:

James,

This looks good in principle, but I'm seeing a number of failures on MC/Disassembler/ARM/memory-arm-instructions.txt.  Perhaps the old tests need to be updated?

--Owen

On Aug 15, 2011, at 7:50 AM, James Molloy wrote:

Hi,

The attached patch causes decoding to fail if the Rt field of an LDRD/STRD is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.

I wanted to add an assert to the encoder too, but couldn't see an obvious way to do this as the Rt field is decoded by the generic "getMachineOpValue()" function direct from tablegen.

Cheers,

James

<LDRDSTRD.patch>_______________________________________________
llvm-commits mailing list
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<http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

_______________________________________________
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llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
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From James.Molloy at arm.com  Mon Aug 15 14:14:44 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 20:14:44 +0100
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <4D6767A3-8B1E-4D95-9D1C-45D2C4008C4F@me.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
	<4D6767A3-8B1E-4D95-9D1C-45D2C4008C4F@me.com>
Message-ID: <9F029ACA-B304-4B57-A23C-D11F01D7F9EA@arm.com>

I'll send one, hopefully tomorrow but we have a gatekeeping process for any patch sent externally which can take up to a day.

James



On 15 Aug 2011, at 20:01, "Owen Anderson" <resistor at me.com<mailto:resistor at me.com>> wrote:

Applied in r137636.  It's still be nice to have a testcase for LDRSH, if only for completeness.

--Owen

On Aug 15, 2011, at 7:23 AM, James Molloy wrote:

Hi,

The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.

Cheers,

James
<LDRSB_Thumb.patch>_______________________________________________
llvm-commits mailing list
<mailto:llvm-commits at cs.uiuc.edu>llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
<http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


From resistor at mac.com  Mon Aug 15 15:08:25 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 20:08:25 -0000
Subject: [llvm-commits] [llvm] r137641 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s
 test/MC/Disassembler/ARM/basic-arm-instructions.txt
Message-ID: <20110815200825.A00A22A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 15:08:25 2011
New Revision: 137641

URL: http://llvm.org/viewvc/llvm-project?rev=137641&view=rev
Log:
Fix incorrect encoding of UMAAL and friends.  Patch by James Molloy.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s
    llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137641&r1=137640&r2=137641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 15 15:08:25 2011
@@ -3461,8 +3461,8 @@
   bits<4> RdHi;
   bits<4> Rm;
   bits<4> Rn;
-  let Inst{19-16} = RdLo;
-  let Inst{15-12} = RdHi;
+  let Inst{19-16} = RdHi;
+  let Inst{15-12} = RdLo;
   let Inst{11-8}  = Rm;
   let Inst{3-0}   = Rn;
 }

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=137641&r1=137640&r2=137641&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Aug 15 15:08:25 2011
@@ -2197,8 +2197,8 @@
         umaal r3, r4, r5, r6
         umaallt r3, r4, r5, r6
 
-@ CHECK: umaal	r3, r4, r5, r6          @ encoding: [0x95,0x46,0x43,0xe0]
-@ CHECK: umaallt	r3, r4, r5, r6  @ encoding: [0x95,0x46,0x43,0xb0]
+@ CHECK: umaal	r3, r4, r5, r6          @ encoding: [0x95,0x36,0x44,0xe0]
+@ CHECK: umaallt	r3, r4, r5, r6          @ encoding: [0x95,0x36,0x44,0xb0]
 
 
 @------------------------------------------------------------------------------

Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=137641&r1=137640&r2=137641&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Mon Aug 15 15:08:25 2011
@@ -2090,8 +2090,8 @@
 # CHECK: umaal r3, r4, r5, r6
 # CHECK: umaallt r3, r4, r5, r6
 
-0x95 0x46 0x43 0xe0
-0x95 0x46 0x43 0xb0
+0x95 0x36 0x44 0xe0
+0x95 0x36 0x44 0xb0
 
 
 #------------------------------------------------------------------------------



From resistor at me.com  Mon Aug 15 15:11:43 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 13:11:43 -0700
Subject: [llvm-commits] [PATCH] Fix decoding of 16-bit LDRSB
In-Reply-To: <9F029ACA-B304-4B57-A23C-D11F01D7F9EA@arm.com>
References: <002a01cc5b56$eaa99880$bffcc980$%molloy@arm.com>
	<4D6767A3-8B1E-4D95-9D1C-45D2C4008C4F@me.com>
	<9F029ACA-B304-4B57-A23C-D11F01D7F9EA@arm.com>
Message-ID: <27DC8788-037B-494F-ADC7-8D9E90E3D22E@me.com>

If it's that much trouble, I'll just make one myself.

--Owen

On Aug 15, 2011, at 12:14 PM, James Molloy wrote:

> I'll send one, hopefully tomorrow but we have a gatekeeping process for any patch sent externally which can take up to a day.
> 
> James
> 
> 
> 
> On 15 Aug 2011, at 20:01, "Owen Anderson" <resistor at me.com<mailto:resistor at me.com>> wrote:
> 
> Applied in r137636.  It's still be nice to have a testcase for LDRSH, if only for completeness.
> 
> --Owen
> 
> On Aug 15, 2011, at 7:23 AM, James Molloy wrote:
> 
> Hi,
> 
> The attached patch fixes decoding of LDRSB and LDRSH in 16-bit Thumb mode. Testcase added.
> 
> Cheers,
> 
> James
> <LDRSB_Thumb.patch>_______________________________________________
> llvm-commits mailing list
> <mailto:llvm-commits at cs.uiuc.edu>llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> <http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
> 
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From isanbard at gmail.com  Mon Aug 15 15:10:51 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 20:10:51 -0000
Subject: [llvm-commits] [llvm] r137642 -
	/llvm/trunk/lib/Transforms/Utils/Local.cpp
Message-ID: <20110815201051.736AD2A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 15:10:51 2011
New Revision: 137642

URL: http://llvm.org/viewvc/llvm-project?rev=137642&view=rev
Log:
The "landingpad" instruction will never be "trivially" dead.

Modified:
    llvm/trunk/lib/Transforms/Utils/Local.cpp

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=137642&r1=137641&r2=137642&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Aug 15 15:10:51 2011
@@ -226,6 +226,10 @@
 bool llvm::isInstructionTriviallyDead(Instruction *I) {
   if (!I->use_empty() || isa<TerminatorInst>(I)) return false;
 
+  // We don't want the landingpad instruction removed by anything this general.
+  if (isa<LandingPadInst>(I))
+    return false;
+
   // We don't want debug info removed by anything this general, unless
   // debug info is empty.
   if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(I)) {



From resistor at mac.com  Mon Aug 15 15:11:11 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 20:11:11 -0000
Subject: [llvm-commits] [llvm] r137643 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20110815201111.3D6C82A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 15:11:11 2011
New Revision: 137643

URL: http://llvm.org/viewvc/llvm-project?rev=137643&view=rev
Log:
Remove dead classes.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137643&r1=137642&r2=137643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 15 15:11:11 2011
@@ -627,25 +627,6 @@
   let Inst{7-4}   = op;
 }
 
-class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
-                IndexMode im, Format f, InstrItinClass itin, string opc,
-                string asm, string cstr, list<dag> pattern>
-  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
-               pattern> {
-  // AM3 store w/ two operands: (GPR, am3offset)
-  bits<14> offset;
-  bits<4> Rt;
-  bits<4> Rn;
-  let Inst{27-25} = 0b000;
-  let Inst{23}    = offset{8};
-  let Inst{22}    = offset{9};
-  let Inst{19-16} = Rn;
-  let Inst{15-12} = Rt;           // Rt
-  let Inst{11-8}  = offset{7-4};  // imm7_4/zero
-  let Inst{7-4}   = op;
-  let Inst{3-0}   = offset{3-0};  // imm3_0/Rm
-}
-
 // stores
 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
              string opc, string asm, list<dag> pattern>
@@ -667,20 +648,6 @@
   let DecoderMethod = "DecodeAddrMode3Instruction";
 }
 
-// Pre-indexed stores
-class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
-               string opc, string asm, string cstr, list<dag> pattern>
-  : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
-      opc, asm, cstr, pattern> {
-  let Inst{4}     = 1;
-  let Inst{5}     = 1; // H bit
-  let Inst{6}     = 0; // S bit
-  let Inst{7}     = 1;
-  let Inst{20}    = 0; // L bit
-  let Inst{21}    = 1; // W bit
-  let Inst{24}    = 1; // P bit
-  let Inst{27-25} = 0b000;
-}
 // addrmode4 instructions
 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
            string asm, string cstr, list<dag> pattern>



From resistor at mac.com  Mon Aug 15 15:12:03 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 20:12:03 -0000
Subject: [llvm-commits] [llvm] r137644 -
	/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110815201203.ED5BD2A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 15:12:03 2011
New Revision: 137644

URL: http://llvm.org/viewvc/llvm-project?rev=137644&view=rev
Log:
Add testcase for STRH.  Patch by James Molloy.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=137644&r1=137643&r2=137644&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Mon Aug 15 15:12:03 2011
@@ -308,3 +308,6 @@
 
 # CHECK: strb	r3, [r2], #1
 0x01 0x30 0xc2 0xe4
+
+# CHECK:         strheq  r0, [r0, -r0]
+0xb0 0x00 0x00 0x01



From resistor at mac.com  Mon Aug 15 15:15:43 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 20:15:43 -0000
Subject: [llvm-commits] [llvm] r137645 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110815201543.CA3022A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 15:15:43 2011
New Revision: 137645

URL: http://llvm.org/viewvc/llvm-project?rev=137645&view=rev
Log:
Add a test for Thumb1 LDRSH decoding.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=137645&r1=137644&r2=137645&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 15 15:15:43 2011
@@ -271,3 +271,6 @@
 
 # CHECK:        ldrsb   r1, [r0, r0]
 0x01 0x56
+
+# CHECK:        ldrsh   r1, [r0, r0]
+0x01 0x5E



From resistor at me.com  Mon Aug 15 15:16:53 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 13:16:53 -0700
Subject: [llvm-commits] [llvm] r137643 -
 /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
In-Reply-To: <20110815201111.3D6C82A6C12C@llvm.org>
References: <20110815201111.3D6C82A6C12C@llvm.org>
Message-ID: <7F6C5462-4294-4E09-8C96-433DBF187691@me.com>

This patch was also by James Molloy.

--Owen

On Aug 15, 2011, at 1:11 PM, Owen Anderson wrote:

> Author: resistor
> Date: Mon Aug 15 15:11:11 2011
> New Revision: 137643
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137643&view=rev
> Log:
> Remove dead classes.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137643&r1=137642&r2=137643&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 15 15:11:11 2011
> @@ -627,25 +627,6 @@
>   let Inst{7-4}   = op;
> }
> 
> -class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
> -                IndexMode im, Format f, InstrItinClass itin, string opc,
> -                string asm, string cstr, list<dag> pattern>
> -  : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
> -               pattern> {
> -  // AM3 store w/ two operands: (GPR, am3offset)
> -  bits<14> offset;
> -  bits<4> Rt;
> -  bits<4> Rn;
> -  let Inst{27-25} = 0b000;
> -  let Inst{23}    = offset{8};
> -  let Inst{22}    = offset{9};
> -  let Inst{19-16} = Rn;
> -  let Inst{15-12} = Rt;           // Rt
> -  let Inst{11-8}  = offset{7-4};  // imm7_4/zero
> -  let Inst{7-4}   = op;
> -  let Inst{3-0}   = offset{3-0};  // imm3_0/Rm
> -}
> -
> // stores
> class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
>              string opc, string asm, list<dag> pattern>
> @@ -667,20 +648,6 @@
>   let DecoderMethod = "DecodeAddrMode3Instruction";
> }
> 
> -// Pre-indexed stores
> -class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
> -               string opc, string asm, string cstr, list<dag> pattern>
> -  : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
> -      opc, asm, cstr, pattern> {
> -  let Inst{4}     = 1;
> -  let Inst{5}     = 1; // H bit
> -  let Inst{6}     = 0; // S bit
> -  let Inst{7}     = 1;
> -  let Inst{20}    = 0; // L bit
> -  let Inst{21}    = 1; // W bit
> -  let Inst{24}    = 1; // P bit
> -  let Inst{27-25} = 0b000;
> -}
> // addrmode4 instructions
> class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
>            string asm, string cstr, list<dag> pattern>
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From echristo at apple.com  Mon Aug 15 15:50:36 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 20:50:36 -0000
Subject: [llvm-commits] [llvm] r137646 -
	/llvm/trunk/test/Transforms/IPConstantProp/global.ll
Message-ID: <20110815205036.F06EA2A6C12C@llvm.org>

Author: echristo
Date: Mon Aug 15 15:50:36 2011
New Revision: 137646

URL: http://llvm.org/viewvc/llvm-project?rev=137646&view=rev
Log:
Add an ipsccp test. Migrated from test/FrontendC++.

Added:
    llvm/trunk/test/Transforms/IPConstantProp/global.ll

Added: llvm/trunk/test/Transforms/IPConstantProp/global.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IPConstantProp/global.ll?rev=137646&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/IPConstantProp/global.ll (added)
+++ llvm/trunk/test/Transforms/IPConstantProp/global.ll Mon Aug 15 15:50:36 2011
@@ -0,0 +1,26 @@
+; RUN: opt < %s -S -ipsccp | FileCheck %s
+
+ at _ZL6test1g = internal global i32 42, align 4
+
+define void @_Z7test1f1v() nounwind {
+entry:
+  %tmp = load i32* @_ZL6test1g, align 4
+  %cmp = icmp eq i32 %tmp, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* @_ZL6test1g, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; CHECK: @_Z7test1f2v()
+; CHECK: entry:
+; CHECK-NEXT: ret i32 42
+define i32 @_Z7test1f2v() nounwind {
+entry:
+  %tmp = load i32* @_ZL6test1g, align 4
+  ret i32 %tmp
+}



From resistor at mac.com  Mon Aug 15 15:51:32 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 20:51:32 -0000
Subject: [llvm-commits] [llvm] r137647 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/memory-arm-instructions.txt
Message-ID: <20110815205132.A94202A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 15:51:32 2011
New Revision: 137647

URL: http://llvm.org/viewvc/llvm-project?rev=137647&view=rev
Log:
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode.  Update tests to reflect this fact.
Patch by James Molloy.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/memory-arm-instructions.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137647&r1=137646&r2=137647&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 15 15:51:32 2011
@@ -1094,6 +1094,21 @@
   unsigned P = fieldFromInstruction32(Insn, 24, 1);
 
   bool writeback = (W == 1) | (P == 0);
+
+  // For {LD,ST}RD, Rt must be even, else undefined.
+  switch (Inst.getOpcode()) {
+    case ARM::STRD:
+    case ARM::STRD_PRE:
+    case ARM::STRD_POST:
+    case ARM::LDRD:
+    case ARM::LDRD_PRE:
+    case ARM::LDRD_POST:
+      if (Rt & 0x1) return false;
+      break;
+  default:
+    break;
+  }
+
   if (writeback) { // Writeback
     if (P)
       U |= ARMII::IndexModePre << 9;

Modified: llvm/trunk/test/MC/Disassembler/ARM/memory-arm-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/memory-arm-instructions.txt?rev=137647&r1=137646&r2=137647&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/memory-arm-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/memory-arm-instructions.txt Mon Aug 15 15:51:32 2011
@@ -104,21 +104,21 @@
 #------------------------------------------------------------------------------
 # LDRD (immediate)
 #------------------------------------------------------------------------------
-# CHECK: ldrd r3, r4, [r5
-# CHECK: ldrd r7, r8, [r2, #15
-# CHECK: ldrd r1, r2, [r9, #32]!
+# CHECK: ldrd r0, r1, [r5]
+# CHECK: ldrd r8, r9, [r2, #15]
+# CHECK: ldrd r2, r3, [r9, #32]!
 # CHECK: ldrd r6, r7, [r1], #8
-# CHECK: ldrd r1, r2, [r8], #0
-# CHECK: ldrd r1, r2, [r8], #0
-# CHECK: ldrd r1, r2, [r8], #-0
-
-0xd0 0x30 0xc5 0xe1
-0xdf 0x70 0xc2 0xe1
-0xd0 0x12 0xe9 0xe1
+# CHECK: ldrd r2, r3, [r8], #0
+# CHECK: ldrd r2, r3, [r8], #0
+# CHECK: ldrd r2, r3, [r8], #-0
+
+0xd0 0x00 0xc5 0xe1
+0xdf 0x80 0xc2 0xe1
+0xd0 0x22 0xe9 0xe1
 0xd8 0x60 0xc1 0xe0
-0xd0 0x10 0xc8 0xe0
-0xd0 0x10 0xc8 0xe0
-0xd0 0x10 0x48 0xe0
+0xd0 0x20 0xc8 0xe0
+0xd0 0x20 0xc8 0xe0
+0xd0 0x20 0x48 0xe0
 
 
 #------------------------------------------------------------------------------
@@ -128,15 +128,15 @@
 #------------------------------------------------------------------------------
 # LDRD (register)
 #------------------------------------------------------------------------------
-# CHECK: ldrd r3, r4, [r1, r3
+# CHECK: ldrd r4, r5, [r1, r3]
 # CHECK: ldrd r4, r5, [r7, r2]!
-# CHECK: ldrd r1, r2, [r8], r12
-# CHECK: ldrd r1, r2, [r8], -r12
+# CHECK: ldrd r0, r1, [r8], r12
+# CHECK: ldrd r0, r1, [r8], -r12
 
-0xd3 0x30 0x81 0xe1
+0xd3 0x40 0x81 0xe1
 0xd2 0x40 0xa7 0xe1
-0xdc 0x10 0x88 0xe0
-0xdc 0x10 0x08 0xe0
+0xdc 0x00 0x88 0xe0
+0xdc 0x00 0x08 0xe0
 
 
 #------------------------------------------------------------------------------
@@ -388,21 +388,21 @@
 #------------------------------------------------------------------------------
 # STRD (immediate)
 #------------------------------------------------------------------------------
-# CHECK: strd r1, r2, [r4
-# CHECK: strd r2, r3, [r6, #1
-# CHECK: strd r3, r4, [r7, #22]!
+# CHECK: strd r0, r1, [r4]
+# CHECK: strd r2, r3, [r6, #1]
+# CHECK: strd r2, r3, [r7, #22]!
 # CHECK: strd r4, r5, [r8], #7
-# CHECK: strd r5, r6, [sp], #0
+# CHECK: strd r4, r5, [sp], #0
 # CHECK: strd r6, r7, [lr], #0
-# CHECK: strd r7, r8, [r9], #-0
+# CHECK: strd r6, r7, [r9], #-0
 
-0xf0 0x10 0xc4 0xe1
+0xf0 0x00 0xc4 0xe1
 0xf1 0x20 0xc6 0xe1
-0xf6 0x31 0xe7 0xe1
+0xf6 0x21 0xe7 0xe1
 0xf7 0x40 0xc8 0xe0
-0xf0 0x50 0xcd 0xe0
+0xf0 0x40 0xcd 0xe0
 0xf0 0x60 0xce 0xe0
-0xf0 0x70 0x49 0xe0
+0xf0 0x60 0x49 0xe0
 
 
 #------------------------------------------------------------------------------
@@ -412,16 +412,15 @@
 #------------------------------------------------------------------------------
 # STRD (register)
 #------------------------------------------------------------------------------
-# CHECK: strd r8, r9, [r4, r1
-# CHECK: strd r7, r8, [r3, r9]!
+# CHECK: strd r8, r9, [r4, r1]
+# CHECK: strd r6, r7, [r3, r9]!
 # CHECK: strd r6, r7, [r5], r8
-# CHECK: strd r5, r6, [r12], -r10
+# CHECK: strd r4, r5, [r12], -r10
 
 0xf1 0x80 0x84 0xe1
-0xf9 0x70 0xa3 0xe1
+0xf9 0x60 0xa3 0xe1
 0xf8 0x60 0x85 0xe0
-0xfa 0x50 0x0c 0xe0
-
+0xfa 0x40 0x0c 0xe0
 
 #------------------------------------------------------------------------------
 # STRH (immediate)



From eli.friedman at gmail.com  Mon Aug 15 15:52:09 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 20:52:09 -0000
Subject: [llvm-commits] [llvm] r137648 - in /llvm/trunk:
 lib/Analysis/AliasSetTracker.cpp lib/Transforms/Scalar/LICM.cpp
 test/Transforms/LICM/atomics.ll
Message-ID: <20110815205209.8BAFC2A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 15:52:09 2011
New Revision: 137648

URL: http://llvm.org/viewvc/llvm-project?rev=137648&view=rev
Log:
Atomic load/store support in LICM.


Added:
    llvm/trunk/test/Transforms/LICM/atomics.ll
Modified:
    llvm/trunk/lib/Analysis/AliasSetTracker.cpp
    llvm/trunk/lib/Transforms/Scalar/LICM.cpp

Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=137648&r1=137647&r2=137648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Mon Aug 15 15:52:09 2011
@@ -126,8 +126,6 @@
 void AliasSet::addUnknownInst(Instruction *I, AliasAnalysis &AA) {
   UnknownInsts.push_back(I);
 
-  if (!I->mayReadOrWriteMemory())
-    return;
   if (!I->mayWriteToMemory()) {
     AliasTy = MayAlias;
     AccessTy |= Refs;
@@ -297,22 +295,28 @@
 
 
 bool AliasSetTracker::add(LoadInst *LI) {
+  if (LI->getOrdering() > Monotonic) return addUnknown(LI);
+  AliasSet::AccessType ATy = AliasSet::Refs;
+  if (!LI->isUnordered()) ATy = AliasSet::ModRef;
   bool NewPtr;
   AliasSet &AS = addPointer(LI->getOperand(0),
                             AA.getTypeStoreSize(LI->getType()),
                             LI->getMetadata(LLVMContext::MD_tbaa),
-                            AliasSet::Refs, NewPtr);
+                            ATy, NewPtr);
   if (LI->isVolatile()) AS.setVolatile();
   return NewPtr;
 }
 
 bool AliasSetTracker::add(StoreInst *SI) {
+  if (SI->getOrdering() > Monotonic) return addUnknown(SI);
+  AliasSet::AccessType ATy = AliasSet::Mods;
+  if (!SI->isUnordered()) ATy = AliasSet::ModRef;
   bool NewPtr;
   Value *Val = SI->getOperand(0);
   AliasSet &AS = addPointer(SI->getOperand(1),
                             AA.getTypeStoreSize(Val->getType()),
                             SI->getMetadata(LLVMContext::MD_tbaa),
-                            AliasSet::Mods, NewPtr);
+                            ATy, NewPtr);
   if (SI->isVolatile()) AS.setVolatile();
   return NewPtr;
 }

Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=137648&r1=137647&r2=137648&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Mon Aug 15 15:52:09 2011
@@ -362,8 +362,8 @@
 bool LICM::canSinkOrHoistInst(Instruction &I) {
   // Loads have extra constraints we have to verify before we can hoist them.
   if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
-    if (LI->isVolatile())
-      return false;        // Don't hoist volatile loads!
+    if (!LI->isUnordered())
+      return false;        // Don't hoist volatile/atomic loads!
 
     // Loads from constant memory are always safe to move, even if they end up
     // in the same alias set as something that ends up being modified.
@@ -722,15 +722,18 @@
 
       // If there is an non-load/store instruction in the loop, we can't promote
       // it.
-      if (isa<LoadInst>(Use)) {
-        assert(!cast<LoadInst>(Use)->isVolatile() && "AST broken");
+      if (LoadInst *load = dyn_cast<LoadInst>(Use)) {
+        assert(!load->isVolatile() && "AST broken");
+        if (!load->isSimple())
+          return;
       } else if (StoreInst *store = dyn_cast<StoreInst>(Use)) {
         // Stores *of* the pointer are not interesting, only stores *to* the
         // pointer.
         if (Use->getOperand(1) != ASIV)
           continue;
-        unsigned InstAlignment = store->getAlignment();
-        assert(!cast<StoreInst>(Use)->isVolatile() && "AST broken");
+        assert(!store->isVolatile() && "AST broken");
+        if (!store->isSimple())
+          return;
 
         // Note that we only check GuaranteedToExecute inside the store case
         // so that we do not introduce stores where they did not exist before
@@ -740,6 +743,7 @@
         // restrictive (and performant) alignment and if we are sure this
         // instruction will be executed, update the alignment.
         // Larger is better, with the exception of 0 being the best alignment.
+        unsigned InstAlignment = store->getAlignment();
         if ((InstAlignment > Alignment || InstAlignment == 0)
             && (Alignment != 0))
           if (isGuaranteedToExecute(*Use)) {

Added: llvm/trunk/test/Transforms/LICM/atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/atomics.ll?rev=137648&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LICM/atomics.ll (added)
+++ llvm/trunk/test/Transforms/LICM/atomics.ll Mon Aug 15 15:52:09 2011
@@ -0,0 +1,79 @@
+; RUN: opt < %s -S -basicaa -licm | FileCheck %s
+
+; Check that we can hoist unordered loads
+define i32 @test1(i32* nocapture %y) nounwind uwtable ssp {
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ %inc, %loop ], [ 0, %entry ]
+  %val = load atomic i32* %y unordered, align 4
+  %inc = add nsw i32 %i, 1
+  %exitcond = icmp eq i32 %inc, %val
+  br i1 %exitcond, label %end, label %loop
+
+end:
+  ret i32 %val
+; CHECK: define i32 @test1(
+; CHECK: load atomic
+; CHECK-NEXT: br label %loop
+}
+
+; Check that we don't sink/hoist monotonic loads
+; (Strictly speaking, it's not forbidden, but it's supposed to be possible to
+; use monotonic for spinlock-like constructs.)
+define i32 @test2(i32* nocapture %y) nounwind uwtable ssp {
+entry:
+  br label %loop
+
+loop:
+  %val = load atomic i32* %y monotonic, align 4
+  %exitcond = icmp ne i32 %val, 0
+  br i1 %exitcond, label %end, label %loop
+
+end:
+  ret i32 %val
+; CHECK: define i32 @test2(
+; CHECK: load atomic
+; CHECK-NEXT: %exitcond = icmp ne
+; CHECK-NEXT: br i1 %exitcond, label %end, label %loop
+}
+
+; Check that we hoist unordered around monotonic.
+; (The noalias shouldn't be necessary in theory, but LICM isn't quite that
+; smart yet.)
+define i32 @test3(i32* nocapture noalias %x, i32* nocapture %y) nounwind uwtable ssp {
+entry:
+  br label %loop
+
+loop:
+  %vala = load atomic i32* %y monotonic, align 4
+  %valb = load atomic i32* %x unordered, align 4
+  %exitcond = icmp ne i32 %vala, %valb
+  br i1 %exitcond, label %end, label %loop
+
+end:
+  ret i32 %vala
+; CHECK: define i32 @test3(
+; CHECK: load atomic i32* %x unordered
+; CHECK-NEXT: br label %loop
+}
+
+; Don't try to "sink" unordered stores yet; it is legal, but the machinery
+; isn't there.
+define i32 @test4(i32* nocapture noalias %x, i32* nocapture %y) nounwind uwtable ssp {
+entry:
+  br label %loop
+
+loop:
+  %vala = load atomic i32* %y monotonic, align 4
+  store atomic i32 %vala, i32* %x unordered, align 4
+  %exitcond = icmp ne i32 %vala, 0
+  br i1 %exitcond, label %end, label %loop
+
+end:
+  ret i32 %vala
+; CHECK: define i32 @test4(
+; CHECK: load atomic i32* %y monotonic
+; CHECK-NEXT: store atomic
+}



From resistor at me.com  Mon Aug 15 15:53:02 2011
From: resistor at me.com (Owen Anderson)
Date: Mon, 15 Aug 2011 13:53:02 -0700
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd
 Rt field
In-Reply-To: <517015F1-305A-49D0-AB29-EF19135D50D0@arm.com>
References: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
	<EC880D4E-B04D-40A7-9C1A-352118C344B7@me.com>
	<517015F1-305A-49D0-AB29-EF19135D50D0@arm.com>
Message-ID: <EF0E61A8-358E-43AD-84EE-8C0D79EEE349@me.com>

I went ahead and corrected the tests, and applied your patch as r137647.

--Owen

On Aug 15, 2011, at 12:13 PM, James Molloy wrote:

> Hi Owen,
> 
> I do apologise, it appears my tree was a few days old and those tests didnt exist.
> 
> The tests are totally incorrect. I'll attach an updated patch file that adapts the test shortly.
> 
> Cheers,
> 
> James
> 
> 
> On 15 Aug 2011, at 19:52, "Owen Anderson" <resistor at me.com<mailto:resistor at me.com>> wrote:
> 
> James,
> 
> This looks good in principle, but I'm seeing a number of failures on MC/Disassembler/ARM/memory-arm-instructions.txt.  Perhaps the old tests need to be updated?
> 
> --Owen
> 
> On Aug 15, 2011, at 7:50 AM, James Molloy wrote:
> 
> Hi,
> 
> The attached patch causes decoding to fail if the Rt field of an LDRD/STRD is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.
> 
> I wanted to add an assert to the encoder too, but couldn't see an obvious way to do this as the Rt field is decoded by the generic "getMachineOpValue()" function direct from tablegen.
> 
> Cheers,
> 
> James
> 
> <LDRDSTRD.patch>_______________________________________________
> llvm-commits mailing list
> <mailto:llvm-commits at cs.uiuc.edu>llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> <http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
> 
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Mon Aug 15 15:53:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 20:53:08 -0000
Subject: [llvm-commits] [llvm] r137649 - in /llvm/trunk:
 include/llvm/MC/MCTargetAsmParser.h utils/TableGen/AsmMatcherEmitter.cpp
Message-ID: <20110815205308.F14992A6C12C@llvm.org>

Author: grosbach
Date: Mon Aug 15 15:53:08 2011
New Revision: 137649

URL: http://llvm.org/viewvc/llvm-project?rev=137649&view=rev
Log:
Move MatchResultTy enum into base class definition.

No need for it to be redefined as part of every derived target asm parser
class.

Modified:
    llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCTargetAsmParser.h?rev=137649&r1=137648&r2=137649&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCTargetAsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCTargetAsmParser.h Mon Aug 15 15:53:08 2011
@@ -22,6 +22,16 @@
 
 /// MCTargetAsmParser - Generic interface to target specific assembly parsers.
 class MCTargetAsmParser : public MCAsmParserExtension {
+public:
+  enum MatchResultTy {
+    Match_ConversionFail,
+    Match_InvalidOperand,
+    Match_MissingFeature,
+    Match_MnemonicFail,
+    Match_Success
+  };
+
+private:
   MCTargetAsmParser(const MCTargetAsmParser &);   // DO NOT IMPLEMENT
   void operator=(const MCTargetAsmParser &);  // DO NOT IMPLEMENT
 protected: // Can only create subclasses.

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=137649&r1=137648&r2=137649&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Aug 15 15:53:08 2011
@@ -2174,13 +2174,6 @@
   OS << "  // This should be included into the middle of the declaration of\n";
   OS << "  // your subclasses implementation of MCTargetAsmParser.\n";
   OS << "  unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
-  OS << "  enum MatchResultTy {\n";
-  OS << "    Match_ConversionFail,\n";
-  OS << "    Match_InvalidOperand,\n";
-  OS << "    Match_MissingFeature,\n";
-  OS << "    Match_MnemonicFail,\n";
-  OS << "    Match_Success\n";
-  OS << "  };\n";
   OS << "  bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
      << "unsigned Opcode,\n"
      << "                       const SmallVectorImpl<MCParsedAsmOperand*> "



From eli.friedman at gmail.com  Mon Aug 15 15:54:19 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 20:54:19 -0000
Subject: [llvm-commits] [llvm] r137650 - in /llvm/trunk/lib/Analysis:
 AliasAnalysis.cpp LoopDependenceAnalysis.cpp MemDepPrinter.cpp
 MemoryDependenceAnalysis.cpp
Message-ID: <20110815205419.404FF2A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 15:54:19 2011
New Revision: 137650

URL: http://llvm.org/viewvc/llvm-project?rev=137650&view=rev
Log:
Misc analysis passes that need to be aware of atomic load/store.


Modified:
    llvm/trunk/lib/Analysis/AliasAnalysis.cpp
    llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp
    llvm/trunk/lib/Analysis/MemDepPrinter.cpp
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=137650&r1=137649&r2=137650&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Aug 15 15:54:19 2011
@@ -268,8 +268,8 @@
 
 AliasAnalysis::ModRefResult
 AliasAnalysis::getModRefInfo(const LoadInst *L, const Location &Loc) {
-  // Be conservative in the face of volatile.
-  if (L->isVolatile())
+  // Be conservative in the face of volatile/atomic.
+  if (!L->isUnordered())
     return ModRef;
 
   // If the load address doesn't alias the given address, it doesn't read
@@ -283,8 +283,8 @@
 
 AliasAnalysis::ModRefResult
 AliasAnalysis::getModRefInfo(const StoreInst *S, const Location &Loc) {
-  // Be conservative in the face of volatile.
-  if (S->isVolatile())
+  // Be conservative in the face of volatile/atomic.
+  if (!S->isUnordered())
     return ModRef;
 
   // If the store address cannot alias the pointer in question, then the

Modified: llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp?rev=137650&r1=137649&r2=137650&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp Mon Aug 15 15:54:19 2011
@@ -76,7 +76,13 @@
 }
 
 static bool IsLoadOrStoreInst(Value *I) {
-  return isa<LoadInst>(I) || isa<StoreInst>(I);
+  // Returns true if the load or store can be analyzed. Atomic and volatile
+  // operations have properties which this analysis does not understand.
+  if (LoadInst *LI = dyn_cast<LoadInst>(I))
+    return LI->isUnordered();
+  else if (StoreInst *SI = dyn_cast<StoreInst>(I))
+    return SI->isUnordered();
+  return false;
 }
 
 static Value *GetPointerOperand(Value *I) {

Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=137650&r1=137649&r2=137650&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (original)
+++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Mon Aug 15 15:54:19 2011
@@ -102,12 +102,21 @@
     } else {
       SmallVector<NonLocalDepResult, 4> NLDI;
       if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
-        // FIXME: Volatile is not handled properly here.
+        if (!LI->isUnordered()) {
+          // FIXME: Handle atomic/volatile loads.
+          Deps[Inst].insert(std::make_pair(InstAndClobberFlag(0, false),
+                                           static_cast<BasicBlock *>(0)));
+          continue;
+        }
         AliasAnalysis::Location Loc = AA.getLocation(LI);
-        MDA.getNonLocalPointerDependency(Loc, !LI->isVolatile(),
-                                         LI->getParent(), NLDI);
+        MDA.getNonLocalPointerDependency(Loc, true, LI->getParent(), NLDI);
       } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
-        // FIXME: Volatile is not handled properly here.
+        if (!LI->isUnordered()) {
+          // FIXME: Handle atomic/volatile stores.
+          Deps[Inst].insert(std::make_pair(InstAndClobberFlag(0, false),
+                                           static_cast<BasicBlock *>(0)));
+          continue;
+        }
         AliasAnalysis::Location Loc = AA.getLocation(SI);
         MDA.getNonLocalPointerDependency(Loc, false, SI->getParent(), NLDI);
       } else if (VAArgInst *VI = dyn_cast<VAArgInst>(Inst)) {

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=137650&r1=137649&r2=137650&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Aug 15 15:54:19 2011
@@ -120,21 +120,27 @@
                                         AliasAnalysis::Location &Loc,
                                         AliasAnalysis *AA) {
   if (const LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
-    if (LI->isVolatile()) {
-      Loc = AliasAnalysis::Location();
+    if (LI->isUnordered()) {
+      Loc = AA->getLocation(LI);
+      return AliasAnalysis::Ref;
+    } else if (LI->getOrdering() == Monotonic) {
+      Loc = AA->getLocation(LI);
       return AliasAnalysis::ModRef;
     }
-    Loc = AA->getLocation(LI);
-    return AliasAnalysis::Ref;
+    Loc = AliasAnalysis::Location();
+    return AliasAnalysis::ModRef;
   }
 
   if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
-    if (SI->isVolatile()) {
-      Loc = AliasAnalysis::Location();
+    if (SI->isUnordered()) {
+      Loc = AA->getLocation(SI);
+      return AliasAnalysis::Mod;
+    } else if (SI->getOrdering() == Monotonic) {
+      Loc = AA->getLocation(SI);
       return AliasAnalysis::ModRef;
     }
-    Loc = AA->getLocation(SI);
-    return AliasAnalysis::Mod;
+    Loc = AliasAnalysis::Location();
+    return AliasAnalysis::ModRef;
   }
 
   if (const VAArgInst *V = dyn_cast<VAArgInst>(Inst)) {
@@ -270,8 +276,8 @@
 getLoadLoadClobberFullWidthSize(const Value *MemLocBase, int64_t MemLocOffs,
                                 unsigned MemLocSize, const LoadInst *LI,
                                 const TargetData &TD) {
-  // We can only extend non-volatile integer loads.
-  if (!isa<IntegerType>(LI->getType()) || LI->isVolatile()) return 0;
+  // We can only extend simple integer loads.
+  if (!isa<IntegerType>(LI->getType()) || !LI->isSimple()) return 0;
   
   // Get the base of this load.
   int64_t LIOffs = 0;
@@ -369,6 +375,11 @@
     // Values depend on loads if the pointers are must aliased.  This means that
     // a load depends on another must aliased load from the same value.
     if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
+      // Atomic loads have complications involved.
+      // FIXME: This is overly conservative.
+      if (!LI->isUnordered())
+        return MemDepResult::getClobber(LI);
+
       AliasAnalysis::Location LoadLoc = AA->getLocation(LI);
       
       // If we found a pointer, check if it could be the same as our pointer.
@@ -424,6 +435,11 @@
     }
     
     if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
+      // Atomic stores have complications involved.
+      // FIXME: This is overly conservative.
+      if (!SI->isUnordered())
+        return MemDepResult::getClobber(SI);
+
       // If alias analysis can tell that this store is guaranteed to not modify
       // the query pointer, ignore it.  Use getModRefInfo to handle cases where
       // the query pointer points to constant memory etc.



From echristo at apple.com  Mon Aug 15 15:55:03 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 15 Aug 2011 20:55:03 -0000
Subject: [llvm-commits] [llvm] r137651 -
	/llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
Message-ID: <20110815205503.EFE432A6C12C@llvm.org>

Author: echristo
Date: Mon Aug 15 15:55:03 2011
New Revision: 137651

URL: http://llvm.org/viewvc/llvm-project?rev=137651&view=rev
Log:
Fix this test to avoid leaving a temporary file behind.

Modified:
    llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll

Modified: llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll?rev=137651&r1=137650&r2=137651&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll Mon Aug 15 15:55:03 2011
@@ -1,4 +1,4 @@
-; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0
+; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 -o -
 ; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
 ; Make sure that it gets expanded; otherwise, the compile fails when trying
 ; to print the pseudo-instruction.



From eli.friedman at gmail.com  Mon Aug 15 16:00:18 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 21:00:18 -0000
Subject: [llvm-commits] [llvm] r137652 -
	/llvm/trunk/lib/VMCore/Instruction.cpp
Message-ID: <20110815210018.EF8972A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 16:00:18 2011
New Revision: 137652

URL: http://llvm.org/viewvc/llvm-project?rev=137652&view=rev
Log:
Fix predicates methods on Instruction to handle atomic load/store correctly.


Modified:
    llvm/trunk/lib/VMCore/Instruction.cpp

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=137652&r1=137651&r2=137652&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Mon Aug 15 16:00:18 2011
@@ -196,10 +196,14 @@
   // Check special state that is a part of some instructions.
   if (const LoadInst *LI = dyn_cast<LoadInst>(this))
     return LI->isVolatile() == cast<LoadInst>(I)->isVolatile() &&
-           LI->getAlignment() == cast<LoadInst>(I)->getAlignment();
+           LI->getAlignment() == cast<LoadInst>(I)->getAlignment() &&
+           LI->getOrdering() == cast<LoadInst>(I)->getOrdering() &&
+           LI->getSynchScope() == cast<LoadInst>(I)->getSynchScope();
   if (const StoreInst *SI = dyn_cast<StoreInst>(this))
     return SI->isVolatile() == cast<StoreInst>(I)->isVolatile() &&
-           SI->getAlignment() == cast<StoreInst>(I)->getAlignment();
+           SI->getAlignment() == cast<StoreInst>(I)->getAlignment() &&
+           SI->getOrdering() == cast<StoreInst>(I)->getOrdering() &&
+           SI->getSynchScope() == cast<StoreInst>(I)->getSynchScope();
   if (const CmpInst *CI = dyn_cast<CmpInst>(this))
     return CI->getPredicate() == cast<CmpInst>(I)->getPredicate();
   if (const CallInst *CI = dyn_cast<CallInst>(this))
@@ -247,10 +251,14 @@
   // Check special state that is a part of some instructions.
   if (const LoadInst *LI = dyn_cast<LoadInst>(this))
     return LI->isVolatile() == cast<LoadInst>(I)->isVolatile() &&
-           LI->getAlignment() == cast<LoadInst>(I)->getAlignment();
+           LI->getAlignment() == cast<LoadInst>(I)->getAlignment() &&
+           LI->getOrdering() == cast<LoadInst>(I)->getOrdering() &&
+           LI->getSynchScope() == cast<LoadInst>(I)->getSynchScope();
   if (const StoreInst *SI = dyn_cast<StoreInst>(this))
     return SI->isVolatile() == cast<StoreInst>(I)->isVolatile() &&
-           SI->getAlignment() == cast<StoreInst>(I)->getAlignment();
+           SI->getAlignment() == cast<StoreInst>(I)->getAlignment() &&
+           SI->getOrdering() == cast<StoreInst>(I)->getOrdering() &&
+           SI->getSynchScope() == cast<StoreInst>(I)->getSynchScope();
   if (const CmpInst *CI = dyn_cast<CmpInst>(this))
     return CI->getPredicate() == cast<CmpInst>(I)->getPredicate();
   if (const CallInst *CI = dyn_cast<CallInst>(this))
@@ -318,7 +326,7 @@
   case Instruction::Invoke:
     return !cast<InvokeInst>(this)->doesNotAccessMemory();
   case Instruction::Store:
-    return cast<StoreInst>(this)->isVolatile();
+    return !cast<StoreInst>(this)->isUnordered();
   }
 }
 
@@ -338,7 +346,7 @@
   case Instruction::Invoke:
     return !cast<InvokeInst>(this)->onlyReadsMemory();
   case Instruction::Load:
-    return cast<LoadInst>(this)->isVolatile();
+    return !cast<LoadInst>(this)->isUnordered();
   }
 }
 
@@ -407,7 +415,7 @@
   }
   case Load: {
     const LoadInst *LI = cast<LoadInst>(this);
-    if (LI->isVolatile())
+    if (!LI->isUnordered())
       return false;
     return LI->getPointerOperand()->isDereferenceablePointer();
   }



From James.Molloy at arm.com  Mon Aug 15 16:04:17 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 15 Aug 2011 22:04:17 +0100
Subject: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd
 Rt field
In-Reply-To: <EF0E61A8-358E-43AD-84EE-8C0D79EEE349@me.com>
References: <003001cc5b5a$a30611d0$e9123570$%molloy@arm.com>
	<EC880D4E-B04D-40A7-9C1A-352118C344B7@me.com>
	<517015F1-305A-49D0-AB29-EF19135D50D0@arm.com>,
	<EF0E61A8-358E-43AD-84EE-8C0D79EEE349@me.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133D5@GEORGE.Emea.Arm.com>

Owen,

Much appreciated, thanks! I didn't get time to change the patch tonight.

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 15 August 2011 21:53
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Correctly fail decoding of LDRD with odd Rt field

I went ahead and corrected the tests, and applied your patch as r137647.

--Owen

On Aug 15, 2011, at 12:13 PM, James Molloy wrote:

> Hi Owen,
>
> I do apologise, it appears my tree was a few days old and those tests didnt exist.
>
> The tests are totally incorrect. I'll attach an updated patch file that adapts the test shortly.
>
> Cheers,
>
> James
>
>
> On 15 Aug 2011, at 19:52, "Owen Anderson" <resistor at me.com<mailto:resistor at me.com>> wrote:
>
> James,
>
> This looks good in principle, but I'm seeing a number of failures on MC/Disassembler/ARM/memory-arm-instructions.txt.  Perhaps the old tests need to be updated?
>
> --Owen
>
> On Aug 15, 2011, at 7:50 AM, James Molloy wrote:
>
> Hi,
>
> The attached patch causes decoding to fail if the Rt field of an LDRD/STRD is odd (Rt&0x1 != 0), as specified in A.6.68. Testcase added.
>
> I wanted to add an assert to the encoder too, but couldn't see an obvious way to do this as the Rt field is decoded by the generic "getMachineOpValue()" function direct from tablegen.
>
> Cheers,
>
> James
>
> <LDRDSTRD.patch>_______________________________________________
> llvm-commits mailing list
> <mailto:llvm-commits at cs.uiuc.edu>llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> <http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
>
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From eli.friedman at gmail.com  Mon Aug 15 16:05:06 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 21:05:06 -0000
Subject: [llvm-commits] [llvm] r137654 -
	/llvm/trunk/lib/Transforms/Utils/CloneModule.cpp
Message-ID: <20110815210506.E36B52A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 16:05:06 2011
New Revision: 137654

URL: http://llvm.org/viewvc/llvm-project?rev=137654&view=rev
Log:
Fix llvm::CloneModule to correctly clone globals.  Patch per bug report by Simon Moll on llvmdev.


Modified:
    llvm/trunk/lib/Transforms/Utils/CloneModule.cpp

Modified: llvm/trunk/lib/Transforms/Utils/CloneModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneModule.cpp?rev=137654&r1=137653&r2=137654&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneModule.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneModule.cpp Mon Aug 15 16:05:06 2011
@@ -50,10 +50,12 @@
        I != E; ++I) {
     GlobalVariable *GV = new GlobalVariable(*New, 
                                             I->getType()->getElementType(),
-                                            false,
-                                            GlobalValue::ExternalLinkage, 0,
-                                            I->getName());
-    GV->setAlignment(I->getAlignment());
+                                            I->isConstant(), I->getLinkage(),
+                                            (Constant*) 0, I->getName(),
+                                            (GlobalVariable*) 0,
+                                            I->isThreadLocal(),
+                                            I->getType()->getAddressSpace());
+    GV->copyAttributesFrom(I);
     VMap[I] = GV;
   }
 
@@ -61,16 +63,19 @@
   for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) {
     Function *NF =
       Function::Create(cast<FunctionType>(I->getType()->getElementType()),
-                       GlobalValue::ExternalLinkage, I->getName(), New);
+                       I->getLinkage(), I->getName(), New);
     NF->copyAttributesFrom(I);
     VMap[I] = NF;
   }
 
   // Loop over the aliases in the module
   for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
-       I != E; ++I)
-    VMap[I] = new GlobalAlias(I->getType(), GlobalAlias::ExternalLinkage,
-                                  I->getName(), NULL, New);
+       I != E; ++I) {
+    GlobalAlias *GA = new GlobalAlias(I->getType(), I->getLinkage(),
+                                      I->getName(), NULL, New);
+    GA->copyAttributesFrom(I);
+    VMap[I] = GA;
+  }
   
   // Now that all of the things that global variable initializer can refer to
   // have been created, loop through and copy the global variable referrers
@@ -81,9 +86,6 @@
     GlobalVariable *GV = cast<GlobalVariable>(VMap[I]);
     if (I->hasInitializer())
       GV->setInitializer(MapValue(I->getInitializer(), VMap));
-    GV->setLinkage(I->getLinkage());
-    GV->setThreadLocal(I->isThreadLocal());
-    GV->setConstant(I->isConstant());
   }
 
   // Similarly, copy over function bodies now...
@@ -101,15 +103,12 @@
       SmallVector<ReturnInst*, 8> Returns;  // Ignore returns cloned.
       CloneFunctionInto(F, I, VMap, /*ModuleLevelChanges=*/true, Returns);
     }
-
-    F->setLinkage(I->getLinkage());
   }
 
   // And aliases
   for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
        I != E; ++I) {
     GlobalAlias *GA = cast<GlobalAlias>(VMap[I]);
-    GA->setLinkage(I->getLinkage());
     if (const Constant *C = I->getAliasee())
       GA->setAliasee(MapValue(C, VMap));
   }



From wendling at apple.com  Mon Aug 15 16:14:28 2011
From: wendling at apple.com (Bill Wendling)
Date: Mon, 15 Aug 2011 14:14:28 -0700
Subject: [llvm-commits] [llvm] r137629 -
 /llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
In-Reply-To: <4E49650E.7030106@free.fr>
References: <20110815182340.3884E2A6C12C@llvm.org> <4E49650E.7030106@free.fr>
Message-ID: <0FFFFADE-D4E5-477E-8E01-C8D4E83DCEC9@apple.com>

On Aug 15, 2011, at 11:27 AM, Duncan Sands wrote:

> Hi Bill,
> 
>> Don't try to sink the landingpad instruction. It's immobile.
> 
> this would be taken care of automatically if landing pad instructions were
> marked as reading memory (which presumably they do, since otherwise where
> do they get the info about which exception was raised etc from?).
> 
Good point. :) They can also potentially write to memory (see the SjLj exception handling stuff). I made the changes. Thanks!

-bw


From isanbard at gmail.com  Mon Aug 15 16:14:31 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 21:14:31 -0000
Subject: [llvm-commits] [llvm] r137655 - in /llvm/trunk/lib:
 Analysis/LoopInfo.cpp Transforms/InstCombine/InstructionCombining.cpp
 VMCore/Instruction.cpp
Message-ID: <20110815211431.769072A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 16:14:31 2011
New Revision: 137655

URL: http://llvm.org/viewvc/llvm-project?rev=137655&view=rev
Log:
Duncan pointed out that the LandingPadInst might read memory. (It might also
write to memory.) Marking it as such makes some checks for immobility go away.

Modified:
    llvm/trunk/lib/Analysis/LoopInfo.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
    llvm/trunk/lib/VMCore/Instruction.cpp

Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=137655&r1=137654&r2=137655&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopInfo.cpp Mon Aug 15 16:14:31 2011
@@ -99,9 +99,6 @@
     return false;
   if (I->mayReadFromMemory())
     return false;
-  // The landingpad instruction is immobile.
-  if (isa<LandingPadInst>(I))
-    return false;
   // Determine the insertion point, unless one was given.
   if (!InsertPt) {
     BasicBlock *Preheader = getLoopPreheader();

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137655&r1=137654&r2=137655&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 16:14:31 2011
@@ -1417,9 +1417,8 @@
 static bool TryToSinkInstruction(Instruction *I, BasicBlock *DestBlock) {
   assert(I->hasOneUse() && "Invariants didn't hold!");
 
-  // Cannot move control-flow-involving, volatile loads, vaarg, landingpad, etc.
-  if (isa<PHINode>(I) || isa<LandingPadInst>(I) || I->mayHaveSideEffects() ||
-      isa<TerminatorInst>(I))
+  // Cannot move control-flow-involving, volatile loads, vaarg, etc.
+  if (isa<PHINode>(I) || I->mayHaveSideEffects() || isa<TerminatorInst>(I))
     return false;
 
   // Do not sink alloca instructions out of the entry block.

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=137655&r1=137654&r2=137655&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Mon Aug 15 16:14:31 2011
@@ -320,6 +320,7 @@
   case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
+  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->doesNotAccessMemory();
@@ -340,6 +341,7 @@
   case Instruction::VAArg:
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
+  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->onlyReadsMemory();



From dpatel at apple.com  Mon Aug 15 16:24:36 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 21:24:36 -0000
Subject: [llvm-commits] [llvm] r137656 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815212436.372BE2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 16:24:36 2011
New Revision: 137656

URL: http://llvm.org/viewvc/llvm-project?rev=137656&view=rev
Log:
Simplify. Let DbgVariable keep track of variable's DBG_VALUE machine instruction.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137656&r1=137655&r2=137656&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 16:24:36 2011
@@ -417,10 +417,7 @@
   }
 
   // Check if variable is described by a  DBG_VALUE instruction.
-  DenseMap<const DbgVariable *, const MachineInstr *>::iterator DVI =
-    DbgVariableToDbgInstMap.find(DV);
-  if (DVI != DbgVariableToDbgInstMap.end()) {
-    const MachineInstr *DVInsn = DVI->second;
+  if (const MachineInstr *DVInsn = DV->getMInsn()) {
     bool updated = false;
     if (DVInsn->getNumOperands() == 3) {
       if (DVInsn->getOperand(0).isReg()) {
@@ -467,17 +464,17 @@
     }
     DV->setDIE(VariableDie);
     return VariableDie;
-  }
-
-  // .. else use frame index, if available.
-  int FI = 0;
-  if (findVariableFrameIndex(DV, &FI)) {
-    unsigned FrameReg = 0;
-    const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
-    int Offset = 
-      TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
-    MachineLocation Location(FrameReg, Offset);
-    VariableCU->addVariableAddress(DV, VariableDie, Location);
+  } else {
+    // .. else use frame index.
+    int FI = DV->getFrameIndex();
+    if (FI != ~0U) {
+      unsigned FrameReg = 0;
+      const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
+      int Offset = 
+        TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
+      MachineLocation Location(FrameReg, Offset);
+      VariableCU->addVariableAddress(DV, VariableDie, Location);
+    }
   }
 
   DV->setDIE(VariableDie);
@@ -953,11 +950,11 @@
 
     DbgVariable *AbsDbgVariable = findAbstractVariable(DV, VP.second);
     DbgVariable *RegVar = new DbgVariable(DV, AbsDbgVariable);
-    recordVariableFrameIndex(RegVar, VP.first);
+    RegVar->setFrameIndex(VP.first);
     if (!addCurrentFnArgument(MF, RegVar, Scope))
       addScopeVariable(Scope, RegVar);
     if (AbsDbgVariable)
-      recordVariableFrameIndex(AbsDbgVariable, VP.first);
+      AbsDbgVariable->setFrameIndex(VP.first);
   }
 }
 
@@ -1046,12 +1043,12 @@
     if (!addCurrentFnArgument(MF, RegVar, Scope))
       addScopeVariable(Scope, RegVar);
     if (AbsVar)
-      DbgVariableToDbgInstMap[AbsVar] = MInsn;
+      AbsVar->setMInsn(MInsn);
 
     // Simple ranges that are fully coalesced.
     if (History.size() <= 1 || (History.size() == 2 &&
                                 MInsn->isIdenticalTo(History.back()))) {
-      DbgVariableToDbgInstMap[RegVar] = MInsn;
+      RegVar->setMInsn(MInsn);
       continue;
     }
 
@@ -1471,8 +1468,6 @@
     DeleteContainerPointers(I->second);
   ScopeVariables.clear();
   DeleteContainerPointers(CurrentFnArguments);
-  DbgVariableToFrameIndexMap.clear();
-  DbgVariableToDbgInstMap.clear();
   UserVariables.clear();
   DbgValues.clear();
   AbstractVariables.clear();
@@ -1481,24 +1476,6 @@
   PrevLabel = NULL;
 }
 
-/// recordVariableFrameIndex - Record a variable's index.
-void DwarfDebug::recordVariableFrameIndex(const DbgVariable *V, int Index) {
-  assert (V && "Invalid DbgVariable!");
-  DbgVariableToFrameIndexMap[V] = Index;
-}
-
-/// findVariableFrameIndex - Return true if frame index for the variable
-/// is found. Update FI to hold value of the index.
-bool DwarfDebug::findVariableFrameIndex(const DbgVariable *V, int *FI) {
-  assert (V && "Invalid DbgVariable!");
-  DenseMap<const DbgVariable *, int>::iterator I =
-    DbgVariableToFrameIndexMap.find(V);
-  if (I == DbgVariableToFrameIndexMap.end())
-    return false;
-  *FI = I->second;
-  return true;
-}
-
 /// recordSourceLine - Register a source line with debug info. Returns the
 /// unique label that was emitted and which provides correspondence to
 /// the source line list.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137656&r1=137655&r2=137656&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 16:24:36 2011
@@ -126,10 +126,13 @@
   DIE *TheDIE;                       // Variable DIE.
   unsigned DotDebugLocOffset;        // Offset in DotDebugLocEntries.
   DbgVariable *AbsVar;               // Corresponding Abstract variable, if any.
+  const MachineInstr *MInsn;         // DBG_VALUE instruction of the variable.
+  int FrameIndex;
 public:
   // AbsVar may be NULL.
   DbgVariable(DIVariable V, DbgVariable *AV) 
-    : Var(V), TheDIE(0), DotDebugLocOffset(~0U), AbsVar(AV) {}
+    : Var(V), TheDIE(0), DotDebugLocOffset(~0U), AbsVar(AV), MInsn(0),
+      FrameIndex(~0U) {}
 
   // Accessors.
   DIVariable getVariable()           const { return Var; }
@@ -139,6 +142,10 @@
   unsigned getDotDebugLocOffset()    const { return DotDebugLocOffset; }
   StringRef getName()                const { return Var.getName(); }
   DbgVariable *getAbstractVariable() const { return AbsVar; }
+  const MachineInstr *getMInsn()     const { return MInsn; }
+  void setMInsn(const MachineInstr *M)     { MInsn = M; }
+  int getFrameIndex()                const { return FrameIndex; }
+  void setFrameIndex(int FI)               { FrameIndex = FI; }
   // Translate tag to proper Dwarf tag.  
   unsigned getTag()                  const { 
     if (Var.getTag() == dwarf::DW_TAG_arg_variable)
@@ -224,14 +231,6 @@
   /// AbstractVariables - Collection on abstract variables.
   DenseMap<const MDNode *, DbgVariable *> AbstractVariables;
 
-  /// DbgVariableToFrameIndexMap - Tracks frame index used to find 
-  /// variable's value.
-  DenseMap<const DbgVariable *, int> DbgVariableToFrameIndexMap;
-
-  /// DbgVariableToDbgInstMap - Maps DbgVariable to corresponding DBG_VALUE
-  /// machine instruction.
-  DenseMap<const DbgVariable *, const MachineInstr *> DbgVariableToDbgInstMap;
-
   /// DotDebugLocEntries - Collection of DotDebugLocEntry.
   SmallVector<DotDebugLocEntry, 4> DotDebugLocEntries;
 
@@ -432,13 +431,6 @@
   void recordSourceLine(unsigned Line, unsigned Col, const MDNode *Scope,
                         unsigned Flags);
   
-  /// recordVariableFrameIndex - Record a variable's index.
-  void recordVariableFrameIndex(const DbgVariable *V, int Index);
-
-  /// findVariableFrameIndex - Return true if frame index for the variable
-  /// is found. Update FI to hold value of the index.
-  bool findVariableFrameIndex(const DbgVariable *V, int *FI);
-
   /// identifyScopeMarkers() - Indentify instructions that are marking
   /// beginning of or end of a scope.
   void identifyScopeMarkers();



From krasin at google.com  Mon Aug 15 16:29:33 2011
From: krasin at google.com (Ivan Krasin)
Date: Mon, 15 Aug 2011 14:29:33 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
Message-ID: <CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>

On Thu, Aug 11, 2011 at 3:20 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Aug 10, 2011, at 4:01 PM, Ivan Krasin wrote:
>
> <flush-local-value-map.patch>
>
> In general I think the patch is OK. ?A few requests:
> ? ?MachineInstr *LastLocalValue;
> + ?MachineInstr *OrigLocalValue;
> ?.
> ? ?// Start out as null, meaining no local-value instructions have
> ? ?// been emitted.
> - ?LastLocalValue = 0;
> + ?OrigLocalValue = 0;
> A lot of the code you've changed hasn't had any comments written or updated
> for the new behavior. It'd be good to get an updated description of how the
> LocalValueMap is working and how it interacts with constants.
I have renamed OrigLocalValue to EmitStartPt which is (I believe) less
confusing naming, since it points to the place in the block where it's
allowed to start emitting instructions.

> In particular:
> + ?if (!isa<IntrinsicInst>(F))
> + ? ?flushLocalValueMap();
> +
> Here. The location of this here doesn't make a whole lot of sense and it'd
> be good if you could explain it.
I've added the explanation. Thanks for the suggestion.

> A better way to do this would be, as Jakob suggested, use the LocalValueMap
> as a storage for constants and locations that you've used them in the block
> and then emit all of the constants at that point rather than this weird
> flushing mechanism.
I've tried to do that. It slows down -O0 build which is unacceptable.
The problem is that we have to emit all local values to the start of
the block, store last use for each of them and spread them through the
block once the processing of the block is done. It makes it slower...
So, I would prefer to stay with the patch that makes all the metrics
slightly better on average (code size/stack size/compile time). Is it
fine with you?

Please, find the updated patch attached.

Ivan Krasin

> -eric
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From resistor at mac.com  Mon Aug 15 16:29:01 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 21:29:01 -0000
Subject: [llvm-commits] [llvm] r137657 -
	/llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt
Message-ID: <20110815212901.8509D2A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 16:29:01 2011
New Revision: 137657

URL: http://llvm.org/viewvc/llvm-project?rev=137657&view=rev
Log:
Add some more comprehensive VFP decoding tests.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt

Added: llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt?rev=137657&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt Mon Aug 15 16:29:01 2011
@@ -0,0 +1,213 @@
+# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s
+
+0xa0 0x0b 0x71 0xee
+# CHECK: vadd.f64        d16, d17, d16
+
+0x80 0x0a 0x30 0xee
+# CHECK: vadd.f32        s0, s1, s0
+
+0xe0 0x0b 0x71 0xee
+# CHECK: vsub.f64        d16, d17, d16
+
+0xc0 0x0a 0x30 0xee
+# CHECK: vsub.f32        s0, s1, s0
+
+0xa0 0x0b 0xc1 0xee
+# CHECK: vdiv.f64        d16, d17, d16
+
+0x80 0x0a 0x80 0xee
+# CHECK: vdiv.f32        s0, s1, s0
+
+0xa0 0x0b 0x61 0xee
+# CHECK: vmul.f64        d16, d17, d16
+
+0x80 0x0a 0x20 0xee
+# CHECK: vmul.f32        s0, s1, s0
+
+0xe0 0x0b 0x61 0xee
+# CHECK: vnmul.f64       d16, d17, d16
+
+0xc0 0x0a 0x20 0xee
+# CHECK: vnmul.f32       s0, s1, s0
+
+0xe0 0x1b 0xf4 0xee
+# CHECK: vcmpe.f64       d17, d16
+
+0xc0 0x0a 0xf4 0xee
+# CHECK: vcmpe.f32       s1, s0
+
+0xe0 0x0b 0xf0 0xee
+# CHECK: vabs.f64        d16, d16
+
+0xc0 0x0a 0xb0 0xee
+# CHECK: vabs.f32        s0, s0
+
+0xe0 0x0b 0xb7 0xee
+# CHECK: vcvt.f32.f64    s0, d16
+
+0xc0 0x0a 0xf7 0xee
+# CHECK: vcvt.f64.f32    d16, s0
+
+0x60 0x0b 0xf1 0xee
+# CHECK: vneg.f64        d16, d16
+
+0x40 0x0a 0xb1 0xee
+# CHECK: vneg.f32        s0, s0
+
+0xe0 0x0b 0xf1 0xee
+# CHECK: vsqrt.f64       d16, d16
+
+0xc0 0x0a 0xb1 0xee
+# CHECK: vsqrt.f32       s0, s0
+
+0xc0 0x0b 0xf8 0xee
+# CHECK: vcvt.f64.s32    d16, s0
+
+0xc0 0x0a 0xb8 0xee
+# CHECK: vcvt.f32.s32    s0, s0
+
+0x40 0x0b 0xf8 0xee
+# CHECK: vcvt.f64.u32    d16, s0
+
+0x40 0x0a 0xb8 0xee
+# CHECK: vcvt.f32.u32    s0, s0
+
+0xe0 0x0b 0xbd 0xee
+# CHECK: vcvt.s32.f64    s0, d16
+
+0xc0 0x0a 0xbd 0xee
+# CHECK: vcvt.s32.f32    s0, s0
+
+0xe0 0x0b 0xbc 0xee
+# CHECK: vcvt.u32.f64    s0, d16
+
+0xc0 0x0a 0xbc 0xee
+# CHECK: vcvt.u32.f32    s0, s0
+
+0xa1 0x0b 0x42 0xee
+# CHECK: vmla.f64        d16, d18, d17
+
+0x00 0x0a 0x41 0xee
+# CHECK: vmla.f32        s1, s2, s0
+
+0xe1 0x0b 0x42 0xee
+# CHECK: vmls.f64        d16, d18, d17
+
+0x40 0x0a 0x41 0xee
+# CHECK: vmls.f32        s1, s2, s0
+
+0xe1 0x0b 0x52 0xee
+# CHECK: vnmla.f64       d16, d18, d17
+
+0x40 0x0a 0x51 0xee
+# CHECK: vnmla.f32       s1, s2, s0
+
+0xa1 0x0b 0x52 0xee
+# CHECK: vnmls.f64       d16, d18, d17
+
+0x00 0x0a 0x51 0xee
+# CHECK: vnmls.f32       s1, s2, s0
+
+0x60 0x0b 0xf1 0x1e
+# CHECK: vnegne.f64      d16, d16
+
+0x10 0x0a 0x00 0x1e
+0x10 0x1a 0x00 0x0e
+# CHECK: vmovne  s0, r0
+# CHECK: vmoveq  s0, r1
+
+0x10 0x0a 0xf1 0xee
+# CHECK: vmrs    r0, fpscr
+0x10 0x0a 0xf8 0xee
+# CHECK: vmrs  r0, fpexc
+0x10 0x0a 0xf0 0xee
+# CHECK: vmrs  r0, fpsid
+
+0x10 0x0a 0xe1 0xee
+# CHECK: vmsr    fpscr, r0
+0x10 0x0a 0xe8 0xee
+# CHECK: vmsr  fpexc, r0
+0x10 0x0a 0xe0 0xee
+# CHECK: vmsr  fpsid, r0
+
+0x10 0x0a 0x00 0xee
+0x90 0x1a 0x00 0xee
+0x10 0x2a 0x01 0xee
+0x90 0x3a 0x01 0xee
+# CHECK: vmov    s0, r0
+# CHECK: vmov    s1, r1
+# CHECK: vmov    s2, r2
+# CHECK: vmov    s3, r3
+
+0x10 0x0a 0x10 0xee
+0x90 0x1a 0x10 0xee
+0x10 0x2a 0x11 0xee
+0x90 0x3a 0x11 0xee
+# CHECK: vmov    r0, s0
+# CHECK: vmov    r1, s1
+# CHECK: vmov    r2, s2
+# CHECK: vmov    r3, s3
+
+0x30 0x0b 0x51 0xec
+# CHECK: vmov    r0, r1, d16
+
+0x00 0x1b 0xd0 0xed
+# CHECK: vldr.64	d17, [r0]
+
+0x08 0x1b 0x92 0xed
+0x08 0x1b 0x12 0xed
+# CHECK: vldr.64	d1, [r2, #32]
+# CHECK: vldr.64	d1, [r2, #-32]
+
+0x00 0x2b 0x93 0xed
+# CHECK: vldr.64 d2, [r3]
+
+0x00 0x3b 0x9f 0xed
+# CHECK: vldr.64 d3, [pc]
+
+0x00 0x6a 0xd0 0xed
+# CHECK: vldr.32	s13, [r0]
+
+0x08 0x0a 0xd2 0xed
+0x08 0x0a 0x52 0xed
+# CHECK: vldr.32	s1, [r2, #32]
+# CHECK: vldr.32	s1, [r2, #-32]
+
+0x00 0x1a 0x93 0xed
+# CHECK: vldr.32 s2, [r3]
+
+0x00 0x2a 0xdf 0xed
+# CHECK: vldr.32 s5, [pc]
+
+0x00 0x4b 0x81 0xed
+0x06 0x4b 0x81 0xed
+0x06 0x4b 0x01 0xed
+# CHECK: vstr.64 d4, [r1]
+# CHECK: vstr.64 d4, [r1, #24]
+# CHECK: vstr.64 d4, [r1, #-24]
+
+0x00 0x2a 0x81 0xed
+0x06 0x2a 0x81 0xed
+0x06 0x2a 0x01 0xed
+# CHECK: vstr.32 s4, [r1]
+# CHECK: vstr.32 s4, [r1, #24]
+# CHECK: vstr.32 s4, [r1, #-24]
+
+0x0c 0x2b 0x91 0xec
+0x06 0x1a 0x91 0xec
+# CHECK: vldmia  r1, {d2, d3, d4, d5, d6, d7}
+# CHECK: vldmia  r1, {s2, s3, s4, s5, s6, s7}
+
+0x0c 0x2b 0x81 0xec
+0x06 0x1a 0x81 0xec
+# CHECK: vstmia  r1, {d2, d3, d4, d5, d6, d7}
+# CHECK: vstmia  r1, {s2, s3, s4, s5, s6, s7}
+
+0x40 0x0b 0xbd 0xee
+0x60 0x0a 0xbd 0xee
+0x40 0x0b 0xbc 0xee
+0x60 0x0a 0xbc 0xee
+# CHECK: vcvtr.s32.f64  s0, d0
+# CHECK: vcvtr.s32.f32  s0, s1
+# CHECK: vcvtr.u32.f64  s0, d0
+# CHECK: vcvtr.u32.f32  s0, s1



From dpatel at apple.com  Mon Aug 15 16:35:16 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 21:35:16 -0000
Subject: [llvm-commits] [llvm] r137658 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815213516.E105D2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 16:35:16 2011
New Revision: 137658

URL: http://llvm.org/viewvc/llvm-project?rev=137658&view=rev
Log:
Fix warning.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137658&r1=137657&r2=137658&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 16:35:16 2011
@@ -467,7 +467,7 @@
   } else {
     // .. else use frame index.
     int FI = DV->getFrameIndex();
-    if (FI != ~0U) {
+    if (FI != ~0) {
       unsigned FrameReg = 0;
       const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
       int Offset = 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137658&r1=137657&r2=137658&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 16:35:16 2011
@@ -132,7 +132,7 @@
   // AbsVar may be NULL.
   DbgVariable(DIVariable V, DbgVariable *AV) 
     : Var(V), TheDIE(0), DotDebugLocOffset(~0U), AbsVar(AV), MInsn(0),
-      FrameIndex(~0U) {}
+      FrameIndex(~0) {}
 
   // Accessors.
   DIVariable getVariable()           const { return Var; }



From dpatel at apple.com  Mon Aug 15 16:43:21 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 21:43:21 -0000
Subject: [llvm-commits] [llvm] r137659 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815214321.397B42A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 16:43:21 2011
New Revision: 137659

URL: http://llvm.org/viewvc/llvm-project?rev=137659&view=rev
Log:
There is no need to maintain a set to keep track of variables that use location expressions. In such cases, AT_location attribute's value will be a label.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137659&r1=137658&r2=137659&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 16:43:21 2011
@@ -412,7 +412,6 @@
                          dwarf::DW_FORM_data4,
                          Asm->GetTempSymbol("debug_loc", Offset));
     DV->setDIE(VariableDie);
-    UseDotDebugLocEntry.insert(VariableDie);
     return VariableDie;
   }
 
@@ -1676,10 +1675,9 @@
       break;
     }
     case dwarf::DW_AT_location: {
-      if (UseDotDebugLocEntry.count(Die) != 0) {
-        DIELabel *L = cast<DIELabel>(Values[i]);
+      if (DIELabel *L = dyn_cast<DIELabel>(Values[i]))
         Asm->EmitLabelDifference(L->getValue(), DwarfDebugLocSectionSym, 4);
-      } else
+      else
         Values[i]->EmitValue(Asm, Form);
       break;
     }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137659&r1=137658&r2=137659&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 16:43:21 2011
@@ -234,10 +234,6 @@
   /// DotDebugLocEntries - Collection of DotDebugLocEntry.
   SmallVector<DotDebugLocEntry, 4> DotDebugLocEntries;
 
-  /// UseDotDebugLocEntry - DW_AT_location attributes for the DIEs in this set
-  /// idetifies corresponding .debug_loc entry offset.
-  SmallPtrSet<const DIE *, 4> UseDotDebugLocEntry;
-
   /// InliendSubprogramDIEs - Collection of subprgram DIEs that are marked
   /// (at the end of the module) as DW_AT_inline.
   SmallPtrSet<DIE *, 4> InlinedSubprogramDIEs;



From bruno.cardoso at gmail.com  Mon Aug 15 16:45:54 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Mon, 15 Aug 2011 21:45:54 -0000
Subject: [llvm-commits] [llvm] r137661 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-vinsertf128.ll
Message-ID: <20110815214554.D9EAA2A6C12C@llvm.org>

Author: bruno
Date: Mon Aug 15 16:45:54 2011
New Revision: 137661

URL: http://llvm.org/viewvc/llvm-project?rev=137661&view=rev
Log:
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
when AVX mode is one. Otherwise is just more work for the type
legalizer.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137661&r1=137660&r2=137661&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 15 16:45:54 2011
@@ -11737,7 +11737,8 @@
 
 /// PerformShuffleCombine - Performs several different shuffle combines.
 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
-                                     TargetLowering::DAGCombinerInfo &DCI) {
+                                     TargetLowering::DAGCombinerInfo &DCI,
+                                     const X86Subtarget *Subtarget) {
   DebugLoc dl = N->getDebugLoc();
   EVT VT = N->getValueType(0);
 
@@ -11746,8 +11747,9 @@
   if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
     return SDValue();
 
-  // Only handle pure VECTOR_SHUFFLE nodes.
-  if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE)
+  // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
+  if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
+      N->getOpcode() == ISD::VECTOR_SHUFFLE)
     return PerformShuffleCombine256(N, DAG, DCI);
 
   // Only handle 128 wide vector from here on.
@@ -13220,7 +13222,7 @@
   case X86ISD::VPERMILPD:
   case X86ISD::VPERMILPDY:
   case X86ISD::VPERM2F128:
-  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
+  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
   }
 
   return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll?rev=137661&r1=137660&r2=137661&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vinsertf128.ll Mon Aug 15 16:45:54 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s
 
 ; CHECK-NOT: vunpck
 ; CHECK: vinsertf128 $1
@@ -16,3 +17,22 @@
   ret <4 x double> %shuffle
 }
 
+declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
+
+declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
+
+; Just check that no crash happens
+; CHECK-SSE: _insert_crash
+define void @insert_crash() nounwind {
+allocas:
+  %v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+  %ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+  %vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
+  %ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
+  %ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0
+  %double2float = fptrunc double %ret.i1.i.i464 to float
+  %smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3
+  %blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>
+  store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4
+  ret void
+}



From eli.friedman at gmail.com  Mon Aug 15 16:56:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 21:56:39 -0000
Subject: [llvm-commits] [llvm] r137662 - /llvm/trunk/lib/Analysis/Loads.cpp
Message-ID: <20110815215639.C70242A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 16:56:39 2011
New Revision: 137662

URL: http://llvm.org/viewvc/llvm-project?rev=137662&view=rev
Log:
Add some comments here because the lack of a check for volatile/atomic here is a bit unusual.


Modified:
    llvm/trunk/lib/Analysis/Loads.cpp

Modified: llvm/trunk/lib/Analysis/Loads.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Loads.cpp?rev=137662&r1=137661&r2=137662&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Loads.cpp (original)
+++ llvm/trunk/lib/Analysis/Loads.cpp Mon Aug 15 16:56:39 2011
@@ -188,12 +188,16 @@
     
     --ScanFrom;
     // If this is a load of Ptr, the loaded value is available.
+    // (This is true even if the load is volatile or atomic, although
+    // those cases are unlikely.)
     if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
       if (AreEquivalentAddressValues(LI->getOperand(0), Ptr))
         return LI;
     
     if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
       // If this is a store through Ptr, the value is available!
+      // (This is true even if the store is volatile or atomic, although
+      // those cases are unlikely.)
       if (AreEquivalentAddressValues(SI->getOperand(1), Ptr))
         return SI->getOperand(0);
       



From dpatel at apple.com  Mon Aug 15 17:04:40 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 22:04:40 -0000
Subject: [llvm-commits] [llvm] r137663 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfCompileUnit.h
 DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815220440.CC59C2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 17:04:40 2011
New Revision: 137663

URL: http://llvm.org/viewvc/llvm-project?rev=137663&view=rev
Log:
Refactor. Variables are part of compile unit so let CompileUnit create new variable.


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=137663&r1=137662&r2=137663&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Aug 15 17:04:40 2011
@@ -1181,6 +1181,114 @@
   }
 }
 
+/// constructVariableDIE - Construct a DIE for the given DbgVariable.
+DIE *CompileUnit::constructVariableDIE(DbgVariable *DV, bool isScopeAbstract) {
+  StringRef Name = DV->getName();
+  if (Name.empty())
+    return NULL;
+
+  // Translate tag to proper Dwarf tag.
+  unsigned Tag = DV->getTag();
+
+  // Define variable debug information entry.
+  DIE *VariableDie = new DIE(Tag);
+  DbgVariable *AbsVar = DV->getAbstractVariable();
+  DIE *AbsDIE = AbsVar ? AbsVar->getDIE() : NULL;
+  if (AbsDIE)
+    addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin,
+                            dwarf::DW_FORM_ref4, AbsDIE);
+  else {
+    addString(VariableDie, dwarf::DW_AT_name, 
+                          dwarf::DW_FORM_string, Name);
+    addSourceLine(VariableDie, DV->getVariable());
+    addType(VariableDie, DV->getType());
+  }
+
+  if (DV->isArtificial())
+    addUInt(VariableDie, dwarf::DW_AT_artificial,
+                        dwarf::DW_FORM_flag, 1);
+
+  if (isScopeAbstract) {
+    DV->setDIE(VariableDie);
+    return VariableDie;
+  }
+
+  // Add variable address.
+
+  unsigned Offset = DV->getDotDebugLocOffset();
+  if (Offset != ~0U) {
+    addLabel(VariableDie, dwarf::DW_AT_location,
+                         dwarf::DW_FORM_data4,
+                         Asm->GetTempSymbol("debug_loc", Offset));
+    DV->setDIE(VariableDie);
+    return VariableDie;
+  }
+
+  // Check if variable is described by a  DBG_VALUE instruction.
+  if (const MachineInstr *DVInsn = DV->getMInsn()) {
+    bool updated = false;
+    if (DVInsn->getNumOperands() == 3) {
+      if (DVInsn->getOperand(0).isReg()) {
+        const MachineOperand RegOp = DVInsn->getOperand(0);
+        const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
+        if (DVInsn->getOperand(1).isImm() &&
+            TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
+          unsigned FrameReg = 0;
+          const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
+          int Offset = 
+            TFI->getFrameIndexReference(*Asm->MF, 
+                                        DVInsn->getOperand(1).getImm(), 
+                                        FrameReg);
+          MachineLocation Location(FrameReg, Offset);
+          addVariableAddress(DV, VariableDie, Location);
+          
+        } else if (RegOp.getReg())
+          addVariableAddress(DV, VariableDie, 
+                                         MachineLocation(RegOp.getReg()));
+        updated = true;
+      }
+      else if (DVInsn->getOperand(0).isImm())
+        updated = 
+          addConstantValue(VariableDie, DVInsn->getOperand(0),
+                                       DV->getType());
+      else if (DVInsn->getOperand(0).isFPImm())
+        updated =
+          addConstantFPValue(VariableDie, DVInsn->getOperand(0));
+      else if (DVInsn->getOperand(0).isCImm())
+        updated =
+          addConstantValue(VariableDie, 
+                                       DVInsn->getOperand(0).getCImm(),
+                                       DV->getType().isUnsignedDIType());
+    } else {
+      addVariableAddress(DV, VariableDie, 
+                                     Asm->getDebugValueLocation(DVInsn));
+      updated = true;
+    }
+    if (!updated) {
+      // If variableDie is not updated then DBG_VALUE instruction does not
+      // have valid variable info.
+      delete VariableDie;
+      return NULL;
+    }
+    DV->setDIE(VariableDie);
+    return VariableDie;
+  } else {
+    // .. else use frame index.
+    int FI = DV->getFrameIndex();
+    if (FI != ~0) {
+      unsigned FrameReg = 0;
+      const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
+      int Offset = 
+        TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
+      MachineLocation Location(FrameReg, Offset);
+      addVariableAddress(DV, VariableDie, Location);
+    }
+  }
+
+  DV->setDIE(VariableDie);
+  return VariableDie;
+}
+
 /// createMemberDIE - Create new member DIE.
 DIE *CompileUnit::createMemberDIE(DIDerivedType DT) {
   DIE *MemberDie = new DIE(DT.getTag());

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=137663&r1=137662&r2=137663&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Mon Aug 15 17:04:40 2011
@@ -281,6 +281,9 @@
   /// vtables.
   void constructContainingTypeDIEs();
 
+  /// constructVariableDIE - Construct a DIE for the given DbgVariable.
+  DIE *constructVariableDIE(DbgVariable *DV, bool isScopeAbstract);
+
   /// createMemberDIE - Create new member DIE.
   DIE *createMemberDIE(DIDerivedType DT);
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137663&r1=137662&r2=137663&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 17:04:40 2011
@@ -371,118 +371,8 @@
   return ScopeDIE;
 }
 
-/// constructVariableDIE - Construct a DIE for the given DbgVariable.
-DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, LexicalScope *Scope) {
-  StringRef Name = DV->getName();
-  if (Name.empty())
-    return NULL;
-
-  // Translate tag to proper Dwarf tag.
-  unsigned Tag = DV->getTag();
-
-  // Define variable debug information entry.
-  DIE *VariableDie = new DIE(Tag);
-  CompileUnit *VariableCU = getCompileUnit(DV->getVariable());
-  DbgVariable *AbsVar = DV->getAbstractVariable();
-  DIE *AbsDIE = AbsVar ? AbsVar->getDIE() : NULL;
-  if (AbsDIE)
-    VariableCU->addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin,
-                            dwarf::DW_FORM_ref4, AbsDIE);
-  else {
-    VariableCU->addString(VariableDie, dwarf::DW_AT_name, 
-                          dwarf::DW_FORM_string, Name);
-    VariableCU->addSourceLine(VariableDie, DV->getVariable());
-    VariableCU->addType(VariableDie, DV->getType());
-  }
-
-  if (DV->isArtificial())
-    VariableCU->addUInt(VariableDie, dwarf::DW_AT_artificial,
-                        dwarf::DW_FORM_flag, 1);
-
-  if (Scope->isAbstractScope()) {
-    DV->setDIE(VariableDie);
-    return VariableDie;
-  }
-
-  // Add variable address.
-
-  unsigned Offset = DV->getDotDebugLocOffset();
-  if (Offset != ~0U) {
-    VariableCU->addLabel(VariableDie, dwarf::DW_AT_location,
-                         dwarf::DW_FORM_data4,
-                         Asm->GetTempSymbol("debug_loc", Offset));
-    DV->setDIE(VariableDie);
-    return VariableDie;
-  }
-
-  // Check if variable is described by a  DBG_VALUE instruction.
-  if (const MachineInstr *DVInsn = DV->getMInsn()) {
-    bool updated = false;
-    if (DVInsn->getNumOperands() == 3) {
-      if (DVInsn->getOperand(0).isReg()) {
-        const MachineOperand RegOp = DVInsn->getOperand(0);
-        const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
-        if (DVInsn->getOperand(1).isImm() &&
-            TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
-          unsigned FrameReg = 0;
-          const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
-          int Offset = 
-            TFI->getFrameIndexReference(*Asm->MF, 
-                                        DVInsn->getOperand(1).getImm(), 
-                                        FrameReg);
-          MachineLocation Location(FrameReg, Offset);
-          VariableCU->addVariableAddress(DV, VariableDie, Location);
-          
-        } else if (RegOp.getReg())
-          VariableCU->addVariableAddress(DV, VariableDie, 
-                                         MachineLocation(RegOp.getReg()));
-        updated = true;
-      }
-      else if (DVInsn->getOperand(0).isImm())
-        updated = 
-          VariableCU->addConstantValue(VariableDie, DVInsn->getOperand(0),
-                                       DV->getType());
-      else if (DVInsn->getOperand(0).isFPImm())
-        updated =
-          VariableCU->addConstantFPValue(VariableDie, DVInsn->getOperand(0));
-      else if (DVInsn->getOperand(0).isCImm())
-        updated =
-          VariableCU->addConstantValue(VariableDie, 
-                                       DVInsn->getOperand(0).getCImm(),
-                                       DV->getType().isUnsignedDIType());
-    } else {
-      VariableCU->addVariableAddress(DV, VariableDie, 
-                                     Asm->getDebugValueLocation(DVInsn));
-      updated = true;
-    }
-    if (!updated) {
-      // If variableDie is not updated then DBG_VALUE instruction does not
-      // have valid variable info.
-      delete VariableDie;
-      return NULL;
-    }
-    DV->setDIE(VariableDie);
-    return VariableDie;
-  } else {
-    // .. else use frame index.
-    int FI = DV->getFrameIndex();
-    if (FI != ~0) {
-      unsigned FrameReg = 0;
-      const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
-      int Offset = 
-        TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
-      MachineLocation Location(FrameReg, Offset);
-      VariableCU->addVariableAddress(DV, VariableDie, Location);
-    }
-  }
-
-  DV->setDIE(VariableDie);
-  return VariableDie;
-
-}
-
 /// constructScopeDIE - Construct a DIE for this scope.
-DIE *DwarfDebug::constructScopeDIE(LexicalScope *Scope) {
+DIE *DwarfDebug::constructScopeDIE(CompileUnit *TheCU, LexicalScope *Scope) {
   if (!Scope || !Scope->getScopeNode())
     return NULL;
 
@@ -492,17 +382,19 @@
   if (LScopes.isCurrentFunctionScope(Scope))
     for (unsigned i = 0, N = CurrentFnArguments.size(); i < N; ++i)
       if (DbgVariable *ArgDV = CurrentFnArguments[i])
-        if (DIE *Arg = constructVariableDIE(ArgDV, Scope))
+        if (DIE *Arg = 
+            TheCU->constructVariableDIE(ArgDV, Scope->isAbstractScope()))
           Children.push_back(Arg);
 
   // Collect lexical scope childrens first.
   const SmallVector<DbgVariable *, 8> &Variables = ScopeVariables.lookup(Scope);
   for (unsigned i = 0, N = Variables.size(); i < N; ++i)
-    if (DIE *Variable = constructVariableDIE(Variables[i], Scope))
+    if (DIE *Variable = 
+        TheCU->constructVariableDIE(Variables[i], Scope->isAbstractScope()))
       Children.push_back(Variable);
   const SmallVector<LexicalScope *, 4> &Scopes = Scope->getChildren();
   for (unsigned j = 0, M = Scopes.size(); j < M; ++j)
-    if (DIE *Nested = constructScopeDIE(Scopes[j]))
+    if (DIE *Nested = constructScopeDIE(TheCU, Scopes[j]))
       Children.push_back(Nested);
   DIScope DS(Scope->getScopeNode());
   DIE *ScopeDIE = NULL;
@@ -807,9 +699,11 @@
 
       // Construct subprogram DIE and add variables DIEs.
       constructSubprogramDIE(SP);
-      DIE *ScopeDIE = getCompileUnit(SP)->getDIE(SP);
+      CompileUnit *SPCU = getCompileUnit(SP);
+      DIE *ScopeDIE = SPCU->getDIE(SP);
       for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
-        if (DIE *VariableDIE = constructVariableDIE(&Variables[i], Scope))
+        if (DIE *VariableDIE = 
+            SPCU->constructVariableDIE(&Variables[i], Scope->isAbstractScope()))
           ScopeDIE->addChild(VariableDIE);
       }
     }
@@ -1425,6 +1319,9 @@
   SmallPtrSet<const MDNode *, 16> ProcessedVars;
   collectVariableInfo(MF, ProcessedVars);
   
+  LexicalScope *FnScope = LScopes.getCurrentFunctionScope();
+  CompileUnit *TheCU = getCompileUnit(FnScope->getScopeNode());
+
   // Construct abstract scopes.
   ArrayRef<LexicalScope *> AList = LScopes.getAbstractScopesList();
   for (unsigned i = 0, e = AList.size(); i != e; ++i) {
@@ -1447,17 +1344,15 @@
       }
     }
     if (ProcessedSPNodes.count(AScope->getScopeNode()) == 0)
-      constructScopeDIE(AScope);
+      constructScopeDIE(TheCU, AScope);
   }
   
-  DIE *CurFnDIE = constructScopeDIE(LScopes.getCurrentFunctionScope());
+  DIE *CurFnDIE = constructScopeDIE(TheCU, FnScope);
   
-  if (!DisableFramePointerElim(*MF)) {
-    LexicalScope *FnScope = LScopes.getCurrentFunctionScope();
-    CompileUnit *TheCU = getCompileUnit(FnScope->getScopeNode());
+  if (!DisableFramePointerElim(*MF))
     TheCU->addUInt(CurFnDIE, dwarf::DW_AT_APPLE_omit_frame_ptr,
                    dwarf::DW_FORM_flag, 1);
-  }
+
   DebugFrames.push_back(FunctionDebugFrameInfo(Asm->getFunctionNumber(),
                                                MMI->getFrameMoves()));
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137663&r1=137662&r2=137663&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 17:04:40 2011
@@ -329,7 +329,7 @@
   DIE *constructVariableDIE(DbgVariable *DV, LexicalScope *S);
 
   /// constructScopeDIE - Construct a DIE for this scope.
-  DIE *constructScopeDIE(LexicalScope *Scope);
+  DIE *constructScopeDIE(CompileUnit *TheCU, LexicalScope *Scope);
 
   /// EmitSectionLabels - Emit initial Dwarf sections with a label at
   /// the start of each one.



From eli.friedman at gmail.com  Mon Aug 15 17:09:40 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 22:09:40 -0000
Subject: [llvm-commits] [llvm] r137664 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
 lib/Transforms/InstCombine/InstCombinePHI.cpp
 lib/Transforms/InstCombine/InstructionCombining.cpp
 test/Transforms/InstCombine/atomic.ll
Message-ID: <20110815220940.F03372A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 17:09:40 2011
New Revision: 137664

URL: http://llvm.org/viewvc/llvm-project?rev=137664&view=rev
Log:
Update instcombine for atomic load/store.


Added:
    llvm/trunk/test/Transforms/InstCombine/atomic.ll
Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=137664&r1=137663&r2=137664&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Aug 15 17:09:40 2011
@@ -132,6 +132,7 @@
         LoadInst *NewLoad = 
           IC.Builder->CreateLoad(CastOp, LI.isVolatile(), CI->getName());
         NewLoad->setAlignment(LI.getAlignment());
+        NewLoad->setAtomic(LI.getOrdering(), LI.getSynchScope());
         // Now cast the result of the load.
         return new BitCastInst(NewLoad, LI.getType());
       }
@@ -162,8 +163,9 @@
     if (Instruction *Res = InstCombineLoadCast(*this, LI, TD))
       return Res;
 
-  // None of the following transforms are legal for volatile loads.
-  if (LI.isVolatile()) return 0;
+  // None of the following transforms are legal for volatile/atomic loads.
+  // FIXME: Some of it is okay for atomic loads; needs refactoring.
+  if (!LI.isSimple()) return 0;
   
   // Do really simple store-to-load forwarding and load CSE, to catch cases
   // where there are several consecutive memory accesses to the same location,
@@ -368,21 +370,6 @@
   Value *Val = SI.getOperand(0);
   Value *Ptr = SI.getOperand(1);
 
-  // If the RHS is an alloca with a single use, zapify the store, making the
-  // alloca dead.
-  if (!SI.isVolatile()) {
-    if (Ptr->hasOneUse()) {
-      if (isa<AllocaInst>(Ptr)) 
-        return EraseInstFromFunction(SI);
-      if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
-        if (isa<AllocaInst>(GEP->getOperand(0))) {
-          if (GEP->getOperand(0)->hasOneUse())
-            return EraseInstFromFunction(SI);
-        }
-      }
-    }
-  }
-
   // Attempt to improve the alignment.
   if (TD) {
     unsigned KnownAlign =
@@ -398,6 +385,23 @@
       SI.setAlignment(EffectiveStoreAlign);
   }
 
+  // Don't hack volatile/atomic stores.
+  // FIXME: Some bits are legal for atomic stores; needs refactoring.
+  if (!SI.isSimple()) return 0;
+
+  // If the RHS is an alloca with a single use, zapify the store, making the
+  // alloca dead.
+  if (Ptr->hasOneUse()) {
+    if (isa<AllocaInst>(Ptr)) 
+      return EraseInstFromFunction(SI);
+    if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr)) {
+      if (isa<AllocaInst>(GEP->getOperand(0))) {
+        if (GEP->getOperand(0)->hasOneUse())
+          return EraseInstFromFunction(SI);
+      }
+    }
+  }
+
   // Do really simple DSE, to catch cases where there are several consecutive
   // stores to the same location, separated by a few arithmetic operations. This
   // situation often occurs with bitfield accesses.
@@ -415,8 +419,8 @@
     
     if (StoreInst *PrevSI = dyn_cast<StoreInst>(BBI)) {
       // Prev store isn't volatile, and stores to the same location?
-      if (!PrevSI->isVolatile() &&equivalentAddressValues(PrevSI->getOperand(1),
-                                                          SI.getOperand(1))) {
+      if (PrevSI->isSimple() && equivalentAddressValues(PrevSI->getOperand(1),
+                                                        SI.getOperand(1))) {
         ++NumDeadStore;
         ++BBI;
         EraseInstFromFunction(*PrevSI);
@@ -430,7 +434,7 @@
     // then *this* store is dead (X = load P; store X -> P).
     if (LoadInst *LI = dyn_cast<LoadInst>(BBI)) {
       if (LI == Val && equivalentAddressValues(LI->getOperand(0), Ptr) &&
-          !SI.isVolatile())
+          LI->isSimple())
         return EraseInstFromFunction(SI);
       
       // Otherwise, this is a load from some other location.  Stores before it
@@ -442,9 +446,6 @@
     if (BBI->mayWriteToMemory() || BBI->mayReadFromMemory())
       break;
   }
-  
-  
-  if (SI.isVolatile()) return 0;  // Don't hack volatile stores.
 
   // store X, null    -> turns into 'unreachable' in SimplifyCFG
   if (isa<ConstantPointerNull>(Ptr) && SI.getPointerAddressSpace() == 0) {
@@ -547,11 +548,11 @@
         return false;
       --BBI;
     }
-    // If this isn't a store, isn't a store to the same location, or if the
-    // alignments differ, bail out.
+    // If this isn't a store, isn't a store to the same location, or is not the
+    // right kind of store, bail out.
     OtherStore = dyn_cast<StoreInst>(BBI);
     if (!OtherStore || OtherStore->getOperand(1) != SI.getOperand(1) ||
-        OtherStore->getAlignment() != SI.getAlignment())
+        !SI.isSameOperationAs(OtherStore))
       return false;
   } else {
     // Otherwise, the other block ended with a conditional branch. If one of the
@@ -567,7 +568,7 @@
       // Check to see if we find the matching store.
       if ((OtherStore = dyn_cast<StoreInst>(BBI))) {
         if (OtherStore->getOperand(1) != SI.getOperand(1) ||
-            OtherStore->getAlignment() != SI.getAlignment())
+            !SI.isSameOperationAs(OtherStore))
           return false;
         break;
       }
@@ -601,8 +602,10 @@
   // insert it.
   BBI = DestBB->getFirstNonPHI();
   StoreInst *NewSI = new StoreInst(MergedVal, SI.getOperand(1),
-                                   OtherStore->isVolatile(),
-                                   SI.getAlignment());
+                                   SI.isVolatile(),
+                                   SI.getAlignment(),
+                                   SI.getOrdering(),
+                                   SI.getSynchScope());
   InsertNewInstBefore(NewSI, *BBI);
   NewSI->setDebugLoc(OtherStore->getDebugLoc()); 
 

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=137664&r1=137663&r2=137664&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Aug 15 17:09:40 2011
@@ -286,7 +286,12 @@
 
 Instruction *InstCombiner::FoldPHIArgLoadIntoPHI(PHINode &PN) {
   LoadInst *FirstLI = cast<LoadInst>(PN.getIncomingValue(0));
-  
+
+  // FIXME: This is overconservative; this transform is allowed in some cases
+  // for atomic operations.
+  if (FirstLI->isAtomic())
+    return 0;
+
   // When processing loads, we need to propagate two bits of information to the
   // sunk load: whether it is volatile, and what its alignment is.  We currently
   // don't sink loads when some have their alignment specified and some don't.

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137664&r1=137663&r2=137664&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 17:09:40 2011
@@ -1379,7 +1379,7 @@
     // load from a GEP. This reduces the size of the load.
     // FIXME: If a load is used only by extractvalue instructions then this
     //        could be done regardless of having multiple uses.
-    if (!L->isVolatile() && L->hasOneUse()) {
+    if (L->isSimple() && L->hasOneUse()) {
       // extractvalue has integer indices, getelementptr has Value*s. Convert.
       SmallVector<Value*, 4> Indices;
       // Prefix an i32 0 since we need the first element.

Added: llvm/trunk/test/Transforms/InstCombine/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/atomic.ll?rev=137664&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/atomic.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/atomic.ll Mon Aug 15 17:09:40 2011
@@ -0,0 +1,15 @@
+; RUN: opt -S < %s -instcombine | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+; Check transforms involving atomic operations
+
+define i32* @test1(i8** %p) {
+; CHECK: define i32* @test1
+; CHECK: load atomic i8** %p monotonic, align 8
+  %c = bitcast i8** %p to i32**
+  %r = load atomic i32** %c monotonic, align 8
+  ret i32* %r
+}
+



From eli.friedman at gmail.com  Mon Aug 15 17:16:46 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 22:16:46 -0000
Subject: [llvm-commits] [llvm] r137667 - in /llvm/trunk/lib/Transforms/IPO:
 ArgumentPromotion.cpp FunctionAttrs.cpp GlobalOpt.cpp MergeFunctions.cpp
Message-ID: <20110815221646.B1C662A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 17:16:46 2011
New Revision: 137667

URL: http://llvm.org/viewvc/llvm-project?rev=137667&view=rev
Log:
Update inter-procedural optimizations for atomic load/store.


Modified:
    llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
    llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp
    llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
    llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp

Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=137667&r1=137666&r2=137667&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Mon Aug 15 17:16:46 2011
@@ -382,7 +382,8 @@
     User *U = *UI;
     Operands.clear();
     if (LoadInst *LI = dyn_cast<LoadInst>(U)) {
-      if (LI->isVolatile()) return false;  // Don't hack volatile loads
+      // Don't hack volatile/atomic loads
+      if (!LI->isSimple()) return false;
       Loads.push_back(LI);
       // Direct loads are equivalent to a GEP with a zero index and then a load.
       Operands.push_back(0);
@@ -410,7 +411,8 @@
       for (Value::use_iterator UI = GEP->use_begin(), E = GEP->use_end();
            UI != E; ++UI)
         if (LoadInst *LI = dyn_cast<LoadInst>(*UI)) {
-          if (LI->isVolatile()) return false;  // Don't hack volatile loads
+          // Don't hack volatile/atomic loads
+          if (!LI->isSimple()) return false;
           Loads.push_back(LI);
         } else {
           // Other uses than load?

Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=137667&r1=137666&r2=137667&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Aug 15 17:16:46 2011
@@ -164,14 +164,14 @@
         continue;
       } else if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
         // Ignore non-volatile loads from local memory.
-        if (!LI->isVolatile()) {
+        if (LI->isUnordered()) {
           AliasAnalysis::Location Loc = AA->getLocation(LI);
           if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true))
             continue;
         }
       } else if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
         // Ignore non-volatile stores to local memory.
-        if (!SI->isVolatile()) {
+        if (SI->isUnordered()) {
           AliasAnalysis::Location Loc = AA->getLocation(SI);
           if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true))
             continue;

Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=137667&r1=137666&r2=137667&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Mon Aug 15 17:16:46 2011
@@ -195,12 +195,12 @@
       }
       if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
         GS.isLoaded = true;
-        if (LI->isVolatile()) return true;  // Don't hack on volatile loads.
+        if (!LI->isSimple()) return true;  // Don't hack on volatile loads.
       } else if (const StoreInst *SI = dyn_cast<StoreInst>(I)) {
         // Don't allow a store OF the address, only stores TO the address.
         if (SI->getOperand(0) == V) return true;
 
-        if (SI->isVolatile()) return true;  // Don't hack on volatile stores.
+        if (!SI->isSimple()) return true;  // Don't hack on volatile stores.
 
         // If this is a direct store to the global (i.e., the global is a scalar
         // value, not an aggregate), keep more specific information about
@@ -2333,7 +2333,7 @@
     Constant *InstResult = 0;
 
     if (StoreInst *SI = dyn_cast<StoreInst>(CurInst)) {
-      if (SI->isVolatile()) return false;  // no volatile accesses.
+      if (!SI->isSimple()) return false;  // no volatile accesses.
       Constant *Ptr = getVal(Values, SI->getOperand(1));
       if (!isSimpleEnoughPointerToCommit(Ptr))
         // If this is too complex for us to commit, reject it.
@@ -2410,7 +2410,7 @@
         ConstantExpr::getGetElementPtr(P, GEPOps,
                                        cast<GEPOperator>(GEP)->isInBounds());
     } else if (LoadInst *LI = dyn_cast<LoadInst>(CurInst)) {
-      if (LI->isVolatile()) return false;  // no volatile accesses.
+      if (!LI->isSimple()) return false;  // no volatile accesses.
       InstResult = ComputeLoadResult(getVal(Values, LI->getOperand(0)),
                                      MutatedMemory);
       if (InstResult == 0) return false; // Could not evaluate load.

Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=137667&r1=137666&r2=137667&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Mon Aug 15 17:16:46 2011
@@ -305,10 +305,14 @@
   // Check special state that is a part of some instructions.
   if (const LoadInst *LI = dyn_cast<LoadInst>(I1))
     return LI->isVolatile() == cast<LoadInst>(I2)->isVolatile() &&
-           LI->getAlignment() == cast<LoadInst>(I2)->getAlignment();
+           LI->getAlignment() == cast<LoadInst>(I2)->getAlignment() &&
+           LI->getOrdering() == cast<LoadInst>(I2)->getOrdering() &&
+           LI->getSynchScope() == cast<LoadInst>(I2)->getSynchScope();
   if (const StoreInst *SI = dyn_cast<StoreInst>(I1))
     return SI->isVolatile() == cast<StoreInst>(I2)->isVolatile() &&
-           SI->getAlignment() == cast<StoreInst>(I2)->getAlignment();
+           SI->getAlignment() == cast<StoreInst>(I2)->getAlignment() &&
+           SI->getOrdering() == cast<StoreInst>(I2)->getOrdering() &&
+           SI->getSynchScope() == cast<StoreInst>(I2)->getSynchScope();
   if (const CmpInst *CI = dyn_cast<CmpInst>(I1))
     return CI->getPredicate() == cast<CmpInst>(I2)->getPredicate();
   if (const CallInst *CI = dyn_cast<CallInst>(I1))



From aaron at aaronballman.com  Mon Aug 15 17:23:39 2011
From: aaron at aaronballman.com (Aaron Ballman)
Date: Mon, 15 Aug 2011 17:23:39 -0500
Subject: [llvm-commits] [PATCH] CrashRecoveryContext.cpp Win32 support
In-Reply-To: <CAAt6xTuZiRH-jjDvcrf-c8sjNjbQ=eH2QtfnG2udW7pOCTkv1A@mail.gmail.com>
References: <CAAt6xTtrnZMDaBwYtNYz=SymNssyNWcN9RhXSgr4mN8StMwgdQ@mail.gmail.com>
	<CADiQthOCqtc5CZ+uwncJdvwBN6OEYBRmSh0sVspmWaPE_ifEpw@mail.gmail.com>
	<CAAt6xTuZiRH-jjDvcrf-c8sjNjbQ=eH2QtfnG2udW7pOCTkv1A@mail.gmail.com>
Message-ID: <CAAt6xTuSP9yLLaXuu8CjPfMgkj7k--vrMv8Wo5wvLhV6fHY2VQ@mail.gmail.com>

On Mon, Aug 15, 2011 at 7:16 AM, Aaron Ballman <aaron at aaronballman.com> wrote:
> On Mon, Aug 15, 2011 at 4:49 AM, NAKAMURA Takumi <geek4civic at gmail.com> wrote:
>> Aaron and Anton,
>>
>> Aaron's patch is good at functionality but a little redundant due to
>> considering w2k.
>>
>> Anton, I propose it would be the time for us to abandon Windows 2000
>> to coming llvm 3.0.
>> It was 20th Century System :D
>> How do you think?
>>
>> Aaron, do you think your patch would be simpler if we could get rid of w2k?
>> (oc, I think so)
>
> I was unsure of how far back we wanted support to extend, which is why
> I lazy-loaded the code. ?If we're going to support XP and higher, the
> code would be cleaner.
>
> I'll make the modifications tonight and resubmit.

I've made the modifications and tested them out in Visual Studio 2010
and MinGW, and they appear to work in my tests.  I've attached the
revised patch.

If there are any questions or problems, please let me know.

Thanks!

~Aaron
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From dpatel at apple.com  Mon Aug 15 17:24:33 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 22:24:33 -0000
Subject: [llvm-commits] [llvm] r137668 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815222433.20FBA2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 17:24:32 2011
New Revision: 137668

URL: http://llvm.org/viewvc/llvm-project?rev=137668&view=rev
Log:
This is somewhat d?j?-vu, but avoid using getCompileUnit() as much as possible.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137668&r1=137667&r2=137668&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 17:24:32 2011
@@ -182,8 +182,8 @@
 /// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes.
 /// If there are global variables in this scope then create and insert
 /// DIEs for these variables.
-DIE *DwarfDebug::updateSubprogramScopeDIE(const MDNode *SPNode) {
-  CompileUnit *SPCU = getCompileUnit(SPNode);
+DIE *DwarfDebug::updateSubprogramScopeDIE(CompileUnit *SPCU,
+                                          const MDNode *SPNode) {
   DIE *SPDie = SPCU->getDIE(SPNode);
 
   assert(SPDie && "Unable to find subprogram DIE!");
@@ -246,7 +246,8 @@
 
 /// constructLexicalScope - Construct new DW_TAG_lexical_block
 /// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels.
-DIE *DwarfDebug::constructLexicalScopeDIE(LexicalScope *Scope) {
+DIE *DwarfDebug::constructLexicalScopeDIE(CompileUnit *TheCU, 
+                                          LexicalScope *Scope) {
 
   DIE *ScopeDIE = new DIE(dwarf::DW_TAG_lexical_block);
   if (Scope->isAbstractScope())
@@ -256,7 +257,6 @@
   if (Ranges.empty())
     return 0;
 
-  CompileUnit *TheCU = getCompileUnit(Scope->getScopeNode());
   SmallVector<InsnRange, 4>::const_iterator RI = Ranges.begin();
   if (Ranges.size() > 1) {
     // .debug_range section has not been laid out yet. Emit offset in
@@ -292,7 +292,8 @@
 /// constructInlinedScopeDIE - This scope represents inlined body of
 /// a function. Construct DIE to represent this concrete inlined copy
 /// of the function.
-DIE *DwarfDebug::constructInlinedScopeDIE(LexicalScope *Scope) {
+DIE *DwarfDebug::constructInlinedScopeDIE(CompileUnit *TheCU,
+                                          LexicalScope *Scope) {
 
   const SmallVector<InsnRange, 4> &Ranges = Scope->getRanges();
   assert (Ranges.empty() == false
@@ -302,7 +303,6 @@
     return NULL;
   DIScope DS(Scope->getScopeNode());
   DISubprogram InlinedSP = getDISubprogram(DS);
-  CompileUnit *TheCU = getCompileUnit(InlinedSP);
   DIE *OriginDIE = TheCU->getDIE(InlinedSP);
   if (!OriginDIE) {
     DEBUG(dbgs() << "Unable to find original DIE for inlined subprogram.");
@@ -399,23 +399,23 @@
   DIScope DS(Scope->getScopeNode());
   DIE *ScopeDIE = NULL;
   if (Scope->getInlinedAt())
-    ScopeDIE = constructInlinedScopeDIE(Scope);
+    ScopeDIE = constructInlinedScopeDIE(TheCU, Scope);
   else if (DS.isSubprogram()) {
     ProcessedSPNodes.insert(DS);
     if (Scope->isAbstractScope()) {
-      ScopeDIE = getCompileUnit(DS)->getDIE(DS);
+      ScopeDIE = TheCU->getDIE(DS);
       // Note down abstract DIE.
       if (ScopeDIE)
         AbstractSPDies.insert(std::make_pair(DS, ScopeDIE));
     }
     else
-      ScopeDIE = updateSubprogramScopeDIE(DS);
+      ScopeDIE = updateSubprogramScopeDIE(TheCU, DS);
   }
   else {
     // There is no need to emit empty lexical block DIE.
     if (Children.empty())
       return NULL;
-    ScopeDIE = constructLexicalScopeDIE(Scope);
+    ScopeDIE = constructLexicalScopeDIE(TheCU, Scope);
   }
   
   if (!ScopeDIE) return NULL;
@@ -426,7 +426,7 @@
     ScopeDIE->addChild(*I);
 
   if (DS.isSubprogram())
-    getCompileUnit(DS)->addPubTypes(DISubprogram(DS));
+   TheCU->addPubTypes(DISubprogram(DS));
 
  return ScopeDIE;
 }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137668&r1=137667&r2=137668&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 17:24:32 2011
@@ -314,16 +314,16 @@
   /// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes.
   /// If there are global variables in this scope then create and insert
   /// DIEs for these variables.
-  DIE *updateSubprogramScopeDIE(const MDNode *SPNode);
+  DIE *updateSubprogramScopeDIE(CompileUnit *SPCU, const MDNode *SPNode);
 
   /// constructLexicalScope - Construct new DW_TAG_lexical_block 
   /// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels.
-  DIE *constructLexicalScopeDIE(LexicalScope *Scope);
+  DIE *constructLexicalScopeDIE(CompileUnit *TheCU, LexicalScope *Scope);
 
   /// constructInlinedScopeDIE - This scope represents inlined body of
   /// a function. Construct DIE to represent this concrete inlined copy
   /// of the function.
-  DIE *constructInlinedScopeDIE(LexicalScope *Scope);
+  DIE *constructInlinedScopeDIE(CompileUnit *TheCU, LexicalScope *Scope);
 
   /// constructVariableDIE - Construct a DIE for the given DbgVariable.
   DIE *constructVariableDIE(DbgVariable *DV, LexicalScope *S);



From chandlerc at google.com  Mon Aug 15 17:37:12 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Mon, 15 Aug 2011 15:37:12 -0700
Subject: [llvm-commits] [llvm] r137667 - in
 /llvm/trunk/lib/Transforms/IPO: ArgumentPromotion.cpp FunctionAttrs.cpp
 GlobalOpt.cpp MergeFunctions.cpp
In-Reply-To: <20110815221646.B1C662A6C12C@llvm.org>
References: <20110815221646.B1C662A6C12C@llvm.org>
Message-ID: <CAGCO0KgiZDZ0yrS8yQXyAZBE=-e=hHsxuJ26TgPaCL1GXbdrWQ@mail.gmail.com>

On Mon, Aug 15, 2011 at 3:16 PM, Eli Friedman <eli.friedman at gmail.com>wrote:

> Update inter-procedural optimizations for atomic load/store.


No test cases?
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From isanbard at gmail.com  Mon Aug 15 17:53:05 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 22:53:05 -0000
Subject: [llvm-commits] [llvm] r137672 -
 /llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
Message-ID: <20110815225305.7CF9A2A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 17:53:05 2011
New Revision: 137672

URL: http://llvm.org/viewvc/llvm-project?rev=137672&view=rev
Log:
Don't sink the instruction to before a landingpad instruction.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137672&r1=137671&r2=137672&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 17:53:05 2011
@@ -1436,7 +1436,7 @@
   }
 
   BasicBlock::iterator InsertPos = DestBlock->getFirstNonPHI();
-
+  if (isa<LandingPadInst>(InsertPos)) ++InsertPos; // Skip landingpad inst.
   I->moveBefore(InsertPos);
   ++NumSunkInst;
   return true;



From eli.friedman at gmail.com  Mon Aug 15 18:00:31 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 16:00:31 -0700
Subject: [llvm-commits] [llvm] r137672 -
	/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
In-Reply-To: <20110815225305.7CF9A2A6C12C@llvm.org>
References: <20110815225305.7CF9A2A6C12C@llvm.org>
Message-ID: <CAJdarcEZrnUq2n_psviYFyFouqM0wn5rZBrjgMW5ZRXoSs70Jw@mail.gmail.com>

On Mon, Aug 15, 2011 at 3:53 PM, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Mon Aug 15 17:53:05 2011
> New Revision: 137672
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137672&view=rev
> Log:
> Don't sink the instruction to before a landingpad instruction.
>
> Modified:
> ? ?llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>
> Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137672&r1=137671&r2=137672&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 17:53:05 2011
> @@ -1436,7 +1436,7 @@
> ? }
>
> ? BasicBlock::iterator InsertPos = DestBlock->getFirstNonPHI();
> -
> + ?if (isa<LandingPadInst>(InsertPos)) ++InsertPos; // Skip landingpad inst.
> ? I->moveBefore(InsertPos);
> ? ++NumSunkInst;
> ? return true;

Is it legal to sink an arbitrary load past a LandingPadInst?

-Eli


From dpatel at apple.com  Mon Aug 15 18:00:01 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 23:00:01 -0000
Subject: [llvm-commits] [llvm] r137673 - in /llvm/trunk:
 docs/ReleaseNotes.html include/llvm/Analysis/DIBuilder.h
 lib/Analysis/DIBuilder.cpp
Message-ID: <20110815230001.21AAD2A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 18:00:00 2011
New Revision: 137673

URL: http://llvm.org/viewvc/llvm-project?rev=137673&view=rev
Log:
Add a finalize() hook, that'll let DIBuilder construct compile unit lazily.

Modified:
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/include/llvm/Analysis/DIBuilder.h
    llvm/trunk/lib/Analysis/DIBuilder.cpp

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=137673&r1=137672&r2=137673&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Aug 15 18:00:00 2011
@@ -673,6 +673,10 @@
 <li>The <code>LLVMAddLowerSetJmpPass</code> function from the C API was removed
     because the <code>LowerSetJmp</code> pass was removed.</li>
 
+<li>The <code>DIBuilder</code> interface used by front ends to encode debugging 
+    information in the LLVM IR now expects clients to use <code>DIBuilder::finalize()</code>
+    at the end of translation unit to complete debugging information encoding.</li>
+
 </ul>
 </div>
 

Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=137673&r1=137672&r2=137673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original)
+++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Mon Aug 15 18:00:00 2011
@@ -59,6 +59,9 @@
     const MDNode *getCU() { return TheCU; }
     enum ComplexAddrKind { OpPlus=1, OpDeref };
 
+    /// finalize - Construct any deferred debug info descriptors.
+    void finalize();
+
     /// createCompileUnit - A CompileUnit provides an anchor for all debugging
     /// information generated during this instance of compilation.
     /// @param Lang     Source programming language, eg. dwarf::DW_LANG_C99

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=137673&r1=137672&r2=137673&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Mon Aug 15 18:00:00 2011
@@ -31,6 +31,10 @@
 DIBuilder::DIBuilder(Module &m)
   : M(m), VMContext(M.getContext()), TheCU(0), DeclareFn(0), ValueFn(0) {}
 
+/// finalize - Construct any deferred debug info descriptors.
+void DIBuilder::finalize() {
+}
+
 /// createCompileUnit - A CompileUnit provides an anchor for all debugging
 /// information generated during this instance of compilation.
 void DIBuilder::createCompileUnit(unsigned Lang, StringRef Filename, 



From grosbach at apple.com  Mon Aug 15 18:03:29 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 15 Aug 2011 23:03:29 -0000
Subject: [llvm-commits] [llvm] r137675 - in /llvm/trunk:
 include/llvm/MC/MCTargetAsmParser.h
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 utils/TableGen/AsmMatcherEmitter.cpp
Message-ID: <20110815230330.0D05C2A6C12C@llvm.org>

Author: grosbach
Date: Mon Aug 15 18:03:29 2011
New Revision: 137675

URL: http://llvm.org/viewvc/llvm-project?rev=137675&view=rev
Log:
MCTargetAsmParser target match predicate support.

Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.


Modified:
    llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCTargetAsmParser.h?rev=137675&r1=137674&r2=137675&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCTargetAsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCTargetAsmParser.h Mon Aug 15 18:03:29 2011
@@ -18,6 +18,7 @@
 class SMLoc;
 class AsmToken;
 class MCParsedAsmOperand;
+class MCInst;
 template <typename T> class SmallVectorImpl;
 
 /// MCTargetAsmParser - Generic interface to target specific assembly parsers.
@@ -28,7 +29,8 @@
     Match_InvalidOperand,
     Match_MissingFeature,
     Match_MnemonicFail,
-    Match_Success
+    Match_Success,
+    FIRST_TARGET_MATCH_RESULT_TY
   };
 
 private:
@@ -88,6 +90,12 @@
                           SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                           MCStreamer &Out) = 0;
 
+  /// checkTargetMatchPredicate - Validate the instruction match against
+  /// any complex target predicates not expressible via match classes.
+  virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
+    return Match_Success;
+  }
+
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137675&r1=137674&r2=137675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 15 18:03:29 2011
@@ -2981,9 +2981,10 @@
                         MCStreamer &Out) {
   MCInst Inst;
   unsigned ErrorInfo;
-  MatchResultTy MatchResult;
+  unsigned MatchResult;
   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
   switch (MatchResult) {
+  default: break;
   case Match_Success:
     // Context sensitive operand constraints aren't handled by the matcher,
     // so check them here.

Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=137675&r1=137674&r2=137675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Mon Aug 15 18:03:29 2011
@@ -323,6 +323,7 @@
   unsigned ErrorInfo;
 
   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
+  default: break;
   case Match_Success:
     Out.EmitInstruction(Inst);
     return false;

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=137675&r1=137674&r2=137675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Aug 15 18:03:29 2011
@@ -981,6 +981,7 @@
 
   // First, try a direct match.
   switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
+  default: break;
   case Match_Success:
     Out.EmitInstruction(Inst);
     return false;
@@ -1019,7 +1020,7 @@
   // Check for the various suffix matches.
   Tmp[Base.size()] = Suffixes[0];
   unsigned ErrorInfoIgnore;
-  MatchResultTy Match1, Match2, Match3, Match4;
+  unsigned Match1, Match2, Match3, Match4;
   
   Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
   Tmp[Base.size()] = Suffixes[1];

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=137675&r1=137674&r2=137675&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Aug 15 18:03:29 2011
@@ -2179,7 +2179,7 @@
      << "                       const SmallVectorImpl<MCParsedAsmOperand*> "
      << "&Operands);\n";
   OS << "  bool MnemonicIsValid(StringRef Mnemonic);\n";
-  OS << "  MatchResultTy MatchInstructionImpl(\n";
+  OS << "  unsigned MatchInstructionImpl(\n";
   OS << "    const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
   OS << "    MCInst &Inst, unsigned &ErrorInfo);\n";
 
@@ -2321,7 +2321,7 @@
   OS << "}\n\n";
 
   // Finally, build the match function.
-  OS << Target.getName() << ClassName << "::MatchResultTy "
+  OS << "unsigned "
      << Target.getName() << ClassName << "::\n"
      << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
      << " &Operands,\n";
@@ -2348,7 +2348,8 @@
   OS << "  }\n\n";
 
   OS << "  // Some state to try to produce better error messages.\n";
-  OS << "  bool HadMatchOtherThanFeatures = false;\n\n";
+  OS << "  bool HadMatchOtherThanFeatures = false;\n";
+  OS << "  unsigned RetCode = Match_InvalidOperand;\n";
   OS << "  // Set ErrorInfo to the operand that mismatches if it is\n";
   OS << "  // wrong for all instances of the instruction.\n";
   OS << "  ErrorInfo = ~0U;\n";
@@ -2404,6 +2405,17 @@
   OS << "      return Match_ConversionFail;\n";
   OS << "\n";
 
+  // Verify the instruction with the target-specific match predicate function.
+  OS << "    // We have a potential match. Check the target predicate to\n"
+     << "    // handle any context sensitive constraints.\n"
+     << "    unsigned MatchResult;\n"
+     << "    if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
+     << " Match_Success) {\n"
+     << "      Inst.clear();\n"
+     << "      RetCode = MatchResult;\n"
+     << "      continue;\n"
+     << "    }\n\n";
+
   // Call the post-processing function, if used.
   std::string InsnCleanupFn =
     AsmParser->getValueAsString("AsmParserInstCleanup");
@@ -2415,7 +2427,7 @@
 
   OS << "  // Okay, we had no match.  Try to return a useful error code.\n";
   OS << "  if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
-  OS << "  return Match_InvalidOperand;\n";
+  OS << "  return RetCode;\n";
   OS << "}\n\n";
 
   if (Info.OperandMatchInfo.size())



From isanbard at gmail.com  Mon Aug 15 18:15:04 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 16:15:04 -0700
Subject: [llvm-commits] [llvm] r137672 -
 /llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
In-Reply-To: <CAJdarcEZrnUq2n_psviYFyFouqM0wn5rZBrjgMW5ZRXoSs70Jw@mail.gmail.com>
References: <20110815225305.7CF9A2A6C12C@llvm.org>
	<CAJdarcEZrnUq2n_psviYFyFouqM0wn5rZBrjgMW5ZRXoSs70Jw@mail.gmail.com>
Message-ID: <79D8F947-8CA5-4500-B531-2ADBBCE3D69A@gmail.com>

On Aug 15, 2011, at 4:00 PM, Eli Friedman wrote:

> On Mon, Aug 15, 2011 at 3:53 PM, Bill Wendling <isanbard at gmail.com> wrote:
>> Author: void
>> Date: Mon Aug 15 17:53:05 2011
>> New Revision: 137672
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137672&view=rev
>> Log:
>> Don't sink the instruction to before a landingpad instruction.
>> 
>> Modified:
>>    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>> 
>> Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137672&r1=137671&r2=137672&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
>> +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Aug 15 17:53:05 2011
>> @@ -1436,7 +1436,7 @@
>>   }
>> 
>>   BasicBlock::iterator InsertPos = DestBlock->getFirstNonPHI();
>> -
>> +  if (isa<LandingPadInst>(InsertPos)) ++InsertPos; // Skip landingpad inst.
>>   I->moveBefore(InsertPos);
>>   ++NumSunkInst;
>>   return true;
> 
> Is it legal to sink an arbitrary load past a LandingPadInst?
> 
Sure. It's not illegal, at least. The optimizer should be aware that it's taking a 'load' from before an 'invoke' and sinking it into the 'unwind' edge. If it's aware that it's doing that and okay with it, then I don't have a problem allowing it. :)

-bw


From isanbard at gmail.com  Mon Aug 15 18:19:54 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 15 Aug 2011 23:19:54 -0000
Subject: [llvm-commits] [llvm] r137679 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20110815231954.E60502A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 18:19:54 2011
New Revision: 137679

URL: http://llvm.org/viewvc/llvm-project?rev=137679&view=rev
Log:
In places where it's using "getFirstNonPHI", skip the landingpad instruction if necessary.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137679&r1=137678&r2=137679&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Aug 15 18:19:54 2011
@@ -469,7 +469,7 @@
 
     if (!InsertedCmp) {
       BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
-
+      if (isa<LandingPadInst>(InsertPt)) ++InsertPt; // Skip landingpad inst.
       InsertedCmp =
         CmpInst::Create(CI->getOpcode(),
                         CI->getPredicate(),  CI->getOperand(0),
@@ -561,10 +561,13 @@
           (DVI->getParent() != VI->getParent() || DT->dominates(DVI, VI))) {
         DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI);
         DVI->removeFromParent();
-        if (isa<PHINode>(VI))
-          DVI->insertBefore(VI->getParent()->getFirstNonPHI());
-        else
+        if (isa<PHINode>(VI)) {
+          BasicBlock::iterator InsertPt = VI->getParent()->getFirstNonPHI();
+          if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
+          DVI->insertBefore(InsertPt);
+        } else {
           DVI->insertAfter(VI);
+        }
         return true;
       }
 
@@ -1061,7 +1064,7 @@
 
     if (!InsertedTrunc) {
       BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
-
+      if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
       InsertedTrunc = new TruncInst(I, Src->getType(), "", InsertPt);
     }
 



From bob.wilson at apple.com  Mon Aug 15 18:22:56 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 15 Aug 2011 23:22:56 -0000
Subject: [llvm-commits] [llvm] r137680 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20110815232256.525642A6C12C@llvm.org>

Author: bwilson
Date: Mon Aug 15 18:22:56 2011
New Revision: 137680

URL: http://llvm.org/viewvc/llvm-project?rev=137680&view=rev
Log:
Avoid evaluating Neon macro arguments more than once by disabling type checks.
It turns out that the use of "__extension__" in these macros was disabling
the expected "incompatible pointer" warnings, so these type checks were not
doing anything anyway.  They introduced a serious bug by evaluating some
macro arguments twice, which is a big problem for arguments with side effects.
I'll have to find another way to get the right type checking.  Radar 9947657.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=137680&r1=137679&r2=137680&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Mon Aug 15 18:22:56 2011
@@ -485,6 +485,7 @@
 /// defined as a macro should be accessed directly instead of being first
 /// assigned to a local temporary.
 static bool MacroArgUsedDirectly(const std::string &proto, unsigned i) {
+  // True for constant ints (i), pointers (p) and const pointers (c).
   return (proto[i] == 'i' || proto[i] == 'p' || proto[i] == 'c');
 }
 
@@ -525,24 +526,16 @@
   for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) {
     // Do not create a temporary for an immediate argument.
     // That would defeat the whole point of using a macro!
-    if (proto[i] == 'i')
+    // FIXME: For other (non-immediate) arguments that are used directly, a
+    // local temporary (or some other method) is still needed to get the
+    // correct type checking, even if that temporary is not used for anything.
+    // This is omitted for now because it turns out the the use of
+    // "__extension__" in the macro disables any warnings from the pointer
+    // assignment.
+    if (MacroArgUsedDirectly(proto, i))
       continue;
     generatedLocal = true;
 
-    // For other (non-immediate) arguments that are used directly, a local
-    // temporary is still needed to get the correct type checking, even though
-    // that temporary is not used for anything.
-    if (MacroArgUsedDirectly(proto, i)) {
-      s += TypeString(proto[i], typestr) + " __";
-      s.push_back(arg);
-      s += "_ = (__";
-      s.push_back(arg);
-      s += "); (void)__";
-      s.push_back(arg);
-      s += "_; ";
-      continue;
-    }
-
     s += TypeString(proto[i], typestr) + " __";
     s.push_back(arg);
     s += " = (";



From dpatel at apple.com  Mon Aug 15 18:36:40 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 23:36:40 -0000
Subject: [llvm-commits] [llvm] r137683 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815233640.CB9032A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 18:36:40 2011
New Revision: 137683

URL: http://llvm.org/viewvc/llvm-project?rev=137683&view=rev
Log:
Continue to hoist uses of getCompileUnit() up. The goal is to get rid of uses of getCompileUnit().

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137683&r1=137682&r2=137683&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 18:36:40 2011
@@ -539,28 +539,22 @@
 }
 
 /// constructGlobalVariableDIE - Construct global variable DIE.
-void DwarfDebug::constructGlobalVariableDIE(const MDNode *N) {
+void DwarfDebug::constructGlobalVariableDIE(CompileUnit *TheCU,
+                                            const MDNode *N) {
   DIGlobalVariable GV(N);
 
   // If debug information is malformed then ignore it.
   if (GV.Verify() == false)
     return;
 
-  // Check for pre-existence.
-  CompileUnit *TheCU = getCompileUnit(N);
   TheCU->createGlobalVariableDIE(N);
   return;
 }
 
 /// construct SubprogramDIE - Construct subprogram DIE.
-void DwarfDebug::constructSubprogramDIE(const MDNode *N) {
+void DwarfDebug::constructSubprogramDIE(CompileUnit *TheCU, 
+                                        const MDNode *N) {
   DISubprogram SP(N);
-
-  // Check for pre-existence.
-  CompileUnit *TheCU = getCompileUnit(N);
-  if (TheCU->getDIE(N))
-    return;
-
   if (!SP.isDefinition())
     // This is a method declaration which will be handled while constructing
     // class type.
@@ -603,12 +597,16 @@
       constructCompileUnit(CU_Nodes->getOperand(i));
 
     if (GV_Nodes)
-      for (unsigned i = 0, e = GV_Nodes->getNumOperands(); i != e; ++i)
-        constructGlobalVariableDIE(GV_Nodes->getOperand(i));
+      for (unsigned i = 0, e = GV_Nodes->getNumOperands(); i != e; ++i) {
+        const MDNode *N = GV_Nodes->getOperand(i);
+        constructGlobalVariableDIE(getCompileUnit(N), N);
+      }
 
     if (SP_Nodes)
-      for (unsigned i = 0, e = SP_Nodes->getNumOperands(); i != e; ++i)
-        constructSubprogramDIE(SP_Nodes->getOperand(i));
+      for (unsigned i = 0, e = SP_Nodes->getNumOperands(); i != e; ++i) {
+        const MDNode *N = SP_Nodes->getOperand(i);
+        constructSubprogramDIE(getCompileUnit(N), N);
+      }
     
   } else {
 
@@ -634,13 +632,18 @@
     
     // Create DIEs for each global variable.
     for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
-           E = DbgFinder.global_variable_end(); I != E; ++I)
-      constructGlobalVariableDIE(*I);
+           E = DbgFinder.global_variable_end(); I != E; ++I) {
+      const MDNode *N = *I;
+      if (DIGlobalVariable(N).getVersion() <= LLVMDebugVersion9)
+        constructGlobalVariableDIE(getCompileUnit(N), N);
+    }
     
     // Create DIEs for each subprogram.
     for (DebugInfoFinder::iterator I = DbgFinder.subprogram_begin(),
-           E = DbgFinder.subprogram_end(); I != E; ++I)
-      constructSubprogramDIE(*I);
+           E = DbgFinder.subprogram_end(); I != E; ++I) {
+      const MDNode *N = *I;
+      constructSubprogramDIE(getCompileUnit(N), N);
+    }
   }
   
   // Tell MMI that we have debug info.
@@ -698,8 +701,8 @@
       }
 
       // Construct subprogram DIE and add variables DIEs.
-      constructSubprogramDIE(SP);
       CompileUnit *SPCU = getCompileUnit(SP);
+      constructSubprogramDIE(SPCU, SP);
       DIE *ScopeDIE = SPCU->getDIE(SP);
       for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
         if (DIE *VariableDIE = 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137683&r1=137682&r2=137683&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 18:36:40 2011
@@ -416,10 +416,10 @@
   CompileUnit *getCompileUnit(const MDNode *N) const;
 
   /// constructGlobalVariableDIE - Construct global variable DIE.
-  void constructGlobalVariableDIE(const MDNode *N);
+  void constructGlobalVariableDIE(CompileUnit *TheCU, const MDNode *N);
 
   /// construct SubprogramDIE - Construct subprogram DIE.
-  void constructSubprogramDIE(const MDNode *N);
+  void constructSubprogramDIE(CompileUnit *TheCU, const MDNode *N);
 
   /// recordSourceLine - Register a source line with debug info. Returns the
   /// unique label that was emitted and which provides correspondence to



From bruno.cardoso at gmail.com  Mon Aug 15 18:36:45 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Mon, 15 Aug 2011 23:36:45 -0000
Subject: [llvm-commits] [llvm] r137684 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-32-avx.s
Message-ID: <20110815233645.E86642A6C12D@llvm.org>

Author: bruno
Date: Mon Aug 15 18:36:45 2011
New Revision: 137684

URL: http://llvm.org/viewvc/llvm-project?rev=137684&view=rev
Log:
Reorder declarations of vmovmskp* and also put the necessary AVX
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/X86/x86-32-avx.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=137684&r1=137683&r2=137684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 15 18:36:45 2011
@@ -1475,17 +1475,6 @@
                 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
 }
 
-// Mask creation
-defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
-                                      "movmskps", SSEPackedSingle>, VEX;
-defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
-                                      "movmskpd", SSEPackedDouble>, OpSize,
-                                      VEX;
-defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
-                                      "movmskps", SSEPackedSingle>, VEX;
-defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
-                                      "movmskpd", SSEPackedDouble>, OpSize,
-                                      VEX;
 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
                                      SSEPackedSingle>, TB;
 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
@@ -1493,29 +1482,44 @@
 
 // X86fgetsign
 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
-                    "movmskpd\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
+               "movmskpd\t{$src, $dst|$dst, $src}",
+               [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB,
+               OpSize;
 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
-                    "movmskpd\t{$src, $dst|$dst, $src}",
-                    [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
+               "movmskpd\t{$src, $dst|$dst, $src}",
+               [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB,
+               OpSize;
 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
-                    "movmskps\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
+               "movmskps\t{$src, $dst|$dst, $src}",
+               [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
-                    "movmskps\t{$src, $dst|$dst, $src}",
-                    [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
+               "movmskps\t{$src, $dst|$dst, $src}",
+               [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
 
-// Assembler Only
-def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
-           "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
-def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
-           "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
-           VEX;
-def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
-           "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
-def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
-           "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
-           VEX;
+let Predicates = [HasAVX] in {
+  defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
+                                        "movmskps", SSEPackedSingle>, TB, VEX;
+  defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
+                                        "movmskpd", SSEPackedDouble>, TB, OpSize,
+                                        VEX;
+  defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
+                                        "movmskps", SSEPackedSingle>, TB, VEX;
+  defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
+                                        "movmskpd", SSEPackedDouble>, TB, OpSize,
+                                        VEX;
+
+  // Assembler Only
+  def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
+             "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
+  def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
+             "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
+             VEX;
+  def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
+             "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
+  def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
+             "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
+             VEX;
+}
 
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions

Modified: llvm/trunk/test/MC/X86/x86-32-avx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-avx.s?rev=137684&r1=137683&r2=137684&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-avx.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-avx.s Mon Aug 15 18:36:45 2011
@@ -479,6 +479,14 @@
 // CHECK: encoding: [0xc5,0xf9,0x50,0xc2]
           vmovmskpd  %xmm2, %eax
 
+// CHECK: vmovmskps  %ymm2, %eax
+// CHECK: encoding: [0xc5,0xfc,0x50,0xc2]
+          vmovmskps  %ymm2, %eax
+
+// CHECK: vmovmskpd  %ymm2, %eax
+// CHECK: encoding: [0xc5,0xfd,0x50,0xc2]
+          vmovmskpd  %ymm2, %eax
+
 // CHECK: vcmpss  $0, %xmm1, %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x00]
           vcmpeqss   %xmm1, %xmm2, %xmm3



From bruno.cardoso at gmail.com  Mon Aug 15 18:36:51 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Mon, 15 Aug 2011 23:36:51 -0000
Subject: [llvm-commits] [llvm] r137685 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20110815233651.81CCC2A6C12C@llvm.org>

Author: bruno
Date: Mon Aug 15 18:36:51 2011
New Revision: 137685

URL: http://llvm.org/viewvc/llvm-project?rev=137685&view=rev
Log:
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
also add the AVX versions of the 128-bit patterns

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=137685&r1=137684&r2=137685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 15 18:36:51 2011
@@ -1480,21 +1480,18 @@
 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
                                      SSEPackedDouble>, TB, OpSize;
 
-// X86fgetsign
-def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
-               "movmskpd\t{$src, $dst|$dst, $src}",
-               [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB,
-               OpSize;
-def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
-               "movmskpd\t{$src, $dst|$dst, $src}",
-               [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB,
-               OpSize;
-def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
-               "movmskps\t{$src, $dst|$dst, $src}",
-               [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
-def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
-               "movmskps\t{$src, $dst|$dst, $src}",
-               [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
+def : Pat<(i32 (X86fgetsign FR32:$src)),
+          (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
+                                       sub_ss))>, Requires<[HasSSE1]>;
+def : Pat<(i64 (X86fgetsign FR32:$src)),
+          (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
+                                       sub_ss))>, Requires<[HasSSE1]>;
+def : Pat<(i32 (X86fgetsign FR64:$src)),
+          (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
+                                       sub_sd))>, Requires<[HasSSE2]>;
+def : Pat<(i64 (X86fgetsign FR64:$src)),
+          (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
+                                       sub_sd))>, Requires<[HasSSE2]>;
 
 let Predicates = [HasAVX] in {
   defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
@@ -1508,6 +1505,19 @@
                                         "movmskpd", SSEPackedDouble>, TB, OpSize,
                                         VEX;
 
+  def : Pat<(i32 (X86fgetsign FR32:$src)),
+            (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
+                                          sub_ss))>;
+  def : Pat<(i64 (X86fgetsign FR32:$src)),
+            (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
+                                          sub_ss))>;
+  def : Pat<(i32 (X86fgetsign FR64:$src)),
+            (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
+                                          sub_sd))>;
+  def : Pat<(i64 (X86fgetsign FR64:$src)),
+            (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
+                                          sub_sd))>;
+
   // Assembler Only
   def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
              "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;



From resistor at mac.com  Mon Aug 15 18:38:54 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 23:38:54 -0000
Subject: [llvm-commits] [llvm] r137686 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td Disassembler/ARMDisassembler.cpp
Message-ID: <20110815233854.541B12A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 18:38:54 2011
New Revision: 137686

URL: http://llvm.org/viewvc/llvm-project?rev=137686&view=rev
Log:
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137686&r1=137685&r2=137686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 15 18:38:54 2011
@@ -1548,7 +1548,7 @@
   let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
   let Pattern = pattern;
   list<Predicate> Predicates = [HasNEON];
-  let DecoderNamespace = "NEONData";
+  let DecoderNamespace = "NEON";
 }
 
 // Same as NeonI except it does not have a "data type" specifier.
@@ -1561,7 +1561,7 @@
   let AsmString = !strconcat(opc, "${p}", "\t", asm);
   let Pattern = pattern;
   list<Predicate> Predicates = [HasNEON];
-  let DecoderNamespace = "NEONData";
+  let DecoderNamespace = "NEON";
 }
 
 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
@@ -1620,6 +1620,7 @@
           pattern> {
   let Inst{31-25} = 0b1111001;
   let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
+  let DecoderNamespace = "NEONData";
 }
 
 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
@@ -1628,6 +1629,7 @@
            cstr, pattern> {
   let Inst{31-25} = 0b1111001;
   let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
+  let DecoderNamespace = "NEONData";
 }
 
 // NEON "one register and a modified immediate" format.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=137686&r1=137685&r2=137686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 15 18:38:54 2011
@@ -966,7 +966,7 @@
           (ins addrmode6dup:$Rn), IIC_VLD3dup,
           "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
   let Rm = 0b1111;
-  let Inst{4} = Rn{4};
+  let Inst{4} = 0;
   let DecoderMethod = "DecodeVLD3DupInstruction";
 }
 
@@ -989,7 +989,7 @@
           (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
           "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
           "$Rn.addr = $wb", []> {
-  let Inst{4} = Rn{4};
+  let Inst{4} = 0;
   let DecoderMethod = "DecodeVLD3DupInstruction";
 }
 

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137686&r1=137685&r2=137686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 15 18:38:54 2011
@@ -494,7 +494,28 @@
   }
 
   MI.clear();
+  result = decodeNEONDupInstruction32(MI, insn32, Address, this);
+  if (result) {
+    Size = 4;
+    AddThumbPredicate(MI);
+    return true;
+  }
+
+  if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
+    MI.clear();
+    uint32_t NEONLdStInsn = insn32;
+    NEONLdStInsn &= 0xF0FFFFFF;
+    NEONLdStInsn |= 0x04000000;
+    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
+    if (result) {
+      Size = 4;
+      AddThumbPredicate(MI);
+      return true;
+    }
+  }
+
   if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
+    MI.clear();
     uint32_t NEONDataInsn = insn32;
     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
@@ -507,22 +528,6 @@
     }
   }
 
-  MI.clear();
-  result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this);
-  if (result) {
-    Size = 4;
-    AddThumbPredicate(MI);
-    return true;
-  }
-
-  MI.clear();
-  result = decodeNEONDupInstruction32(MI, insn32, Address, this);
-  if (result) {
-    Size = 4;
-    AddThumbPredicate(MI);
-    return true;
-  }
-
   return false;
 }
 



From resistor at mac.com  Mon Aug 15 18:42:20 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 15 Aug 2011 23:42:20 -0000
Subject: [llvm-commits] [llvm] r137687 -
	/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
Message-ID: <20110815234220.3455E2A6C12C@llvm.org>

Author: resistor
Date: Mon Aug 15 18:42:20 2011
New Revision: 137687

URL: http://llvm.org/viewvc/llvm-project?rev=137687&view=rev
Log:
Add a test file for Thumb2 NEON.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt

Added: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=137687&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Mon Aug 15 18:42:20 2011
@@ -0,0 +1,1586 @@
+# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble < %s | FileCheck %s
+
+0xf1 0xff 0x20 0x03
+# CHECK: vabs.s8	d16, d16
+0xf5 0xff 0x20 0x03
+# CHECK: vabs.s16	d16, d16
+0xf9 0xff 0x20 0x03
+# CHECK: vabs.s32	d16, d16
+0xf9 0xff 0x20 0x07
+# CHECK: vabs.f32	d16, d16
+0xf1 0xff 0x60 0x03
+# CHECK: vabs.s8	q8, q8
+0xf5 0xff 0x60 0x03
+# CHECK: vabs.s16	q8, q8
+0xf9 0xff 0x60 0x03
+# CHECK: vabs.s32	q8, q8
+0xf9 0xff 0x60 0x07
+# CHECK: vabs.f32	q8, q8
+
+0xf0 0xff 0x20 0x07
+# CHECK: vqabs.s8	d16, d16
+0xf4 0xff 0x20 0x07
+# CHECK: vqabs.s16	d16, d16
+0xf8 0xff 0x20 0x07
+# CHECK: vqabs.s32	d16, d16
+0xf0 0xff 0x60 0x07
+# CHECK: vqabs.s8	q8, q8
+0xf4 0xff 0x60 0x07
+# CHECK: vqabs.s16	q8, q8
+0xf8 0xff 0x60 0x07
+# CHECK: vqabs.s32	q8, q8
+
+0x40 0xef 0xa1 0x07
+# CHECK: vabd.s8	d16, d16, d17
+0x50 0xef 0xa1 0x07
+# CHECK: vabd.s16	d16, d16, d17
+0x60 0xef 0xa1 0x07
+# CHECK: vabd.s32	d16, d16, d17
+0x40 0xff 0xa1 0x07
+# CHECK: vabd.u8	d16, d16, d17
+0x50 0xff 0xa1 0x07
+# CHECK: vabd.u16	d16, d16, d17
+0x60 0xff 0xa1 0x07
+# CHECK: vabd.u32	d16, d16, d17
+0x60 0xff 0xa1 0x0d
+# CHECK: vabd.f32	d16, d16, d17
+0x40 0xef 0xe2 0x07
+# CHECK: vabd.s8	q8, q8, q9
+0x50 0xef 0xe2 0x07
+# CHECK: vabd.s16	q8, q8, q9
+0x60 0xef 0xe2 0x07
+# CHECK: vabd.s32	q8, q8, q9
+0x40 0xff 0xe2 0x07
+# CHECK: vabd.u8	q8, q8, q9
+0x50 0xff 0xe2 0x07
+# CHECK: vabd.u16	q8, q8, q9
+0x60 0xff 0xe2 0x07
+# CHECK: vabd.u32	q8, q8, q9
+0x60 0xff 0xe2 0x0d
+# CHECK: vabd.f32	q8, q8, q9
+
+0xc0 0xef 0xa1 0x07
+# CHECK: vabdl.s8	q8, d16, d17
+0xd0 0xef 0xa1 0x07
+# CHECK: vabdl.s16	q8, d16, d17
+0xe0 0xef 0xa1 0x07
+# CHECK: vabdl.s32	q8, d16, d17
+0xc0 0xff 0xa1 0x07
+# CHECK: vabdl.u8	q8, d16, d17
+0xd0 0xff 0xa1 0x07
+# CHECK: vabdl.u16	q8, d16, d17
+0xe0 0xff 0xa1 0x07
+# CHECK: vabdl.u32	q8, d16, d17
+
+0x42 0xef 0xb1 0x07
+# CHECK: vaba.s8	d16, d18, d17
+0x52 0xef 0xb1 0x07
+# CHECK: vaba.s16	d16, d18, d17
+0x62 0xef 0xb1 0x07
+# CHECK: vaba.s32	d16, d18, d17
+0x42 0xff 0xb1 0x07
+# CHECK: vaba.u8	d16, d18, d17
+0x52 0xff 0xb1 0x07
+# CHECK: vaba.u16	d16, d18, d17
+0x62 0xff 0xb1 0x07
+# CHECK: vaba.u32	d16, d18, d17
+0x40 0xef 0xf4 0x27
+# CHECK: vaba.s8	q9, q8, q10
+0x50 0xef 0xf4 0x27
+# CHECK: vaba.s16	q9, q8, q10
+0x60 0xef 0xf4 0x27
+# CHECK: vaba.s32	q9, q8, q10
+0x40 0xff 0xf4 0x27
+# CHECK: vaba.u8	q9, q8, q10
+0x50 0xff 0xf4 0x27
+# CHECK: vaba.u16	q9, q8, q10
+0x60 0xff 0xf4 0x27
+# CHECK: vaba.u32	q9, q8, q10
+
+0xc3 0xef 0xa2 0x05
+# CHECK: vabal.s8	q8, d19, d18
+0xd3 0xef 0xa2 0x05
+# CHECK: vabal.s16	q8, d19, d18
+0xe3 0xef 0xa2 0x05
+# CHECK: vabal.s32	q8, d19, d18
+0xc3 0xff 0xa2 0x05
+# CHECK: vabal.u8	q8, d19, d18
+0xd3 0xff 0xa2 0x05
+# CHECK: vabal.u16	q8, d19, d18
+0xe3 0xff 0xa2 0x05
+# CHECK: vabal.u32	q8, d19, d18
+
+0x41 0xef 0xa0 0x08
+# CHECK: vadd.i8	d16, d17, d16
+0x51 0xef 0xa0 0x08
+# CHECK: vadd.i16	d16, d17, d16
+0x71 0xef 0xa0 0x08
+# CHECK: vadd.i64	d16, d17, d16
+0x61 0xef 0xa0 0x08
+# CHECK: vadd.i32	d16, d17, d16
+0x40 0xef 0xa1 0x0d
+# CHECK: vadd.f32	d16, d16, d17
+0x40 0xef 0xe2 0x0d
+# CHECK: vadd.f32	q8, q8, q9
+
+0xc1 0xef 0xa0 0x00
+# CHECK: vaddl.s8	q8, d17, d16
+0xd1 0xef 0xa0 0x00
+# CHECK: vaddl.s16	q8, d17, d16
+0xe1 0xef 0xa0 0x00
+# CHECK: vaddl.s32	q8, d17, d16
+0xc1 0xff 0xa0 0x00
+# CHECK: vaddl.u8	q8, d17, d16
+0xd1 0xff 0xa0 0x00
+# CHECK: vaddl.u16	q8, d17, d16
+0xe1 0xff 0xa0 0x00
+# CHECK: vaddl.u32	q8, d17, d16
+
+0xc0 0xef 0xa2 0x01
+# CHECK: vaddw.s8	q8, q8, d18
+0xd0 0xef 0xa2 0x01
+# CHECK: vaddw.s16	q8, q8, d18
+0xe0 0xef 0xa2 0x01
+# CHECK: vaddw.s32	q8, q8, d18
+0xc0 0xff 0xa2 0x01
+# CHECK: vaddw.u8	q8, q8, d18
+0xd0 0xff 0xa2 0x01
+# CHECK: vaddw.u16	q8, q8, d18
+0xe0 0xff 0xa2 0x01
+# CHECK: vaddw.u32	q8, q8, d18
+
+0x40 0xef 0xa1 0x00
+# CHECK: vhadd.s8	d16, d16, d17
+0x50 0xef 0xa1 0x00
+# CHECK: vhadd.s16	d16, d16, d17
+0x60 0xef 0xa1 0x00
+# CHECK: vhadd.s32	d16, d16, d17
+0x40 0xff 0xa1 0x00
+# CHECK: vhadd.u8	d16, d16, d17
+0x50 0xff 0xa1 0x00
+# CHECK: vhadd.u16	d16, d16, d17
+0x60 0xff 0xa1 0x00
+# CHECK: vhadd.u32	d16, d16, d17
+0x40 0xef 0xe2 0x00
+# CHECK: vhadd.s8	q8, q8, q9
+0x50 0xef 0xe2 0x00
+# CHECK: vhadd.s16	q8, q8, q9
+0x60 0xef 0xe2 0x00
+# CHECK: vhadd.s32	q8, q8, q9
+0x40 0xff 0xe2 0x00
+# CHECK: vhadd.u8	q8, q8, q9
+0x50 0xff 0xe2 0x00
+# CHECK: vhadd.u16	q8, q8, q9
+0x60 0xff 0xe2 0x00
+# CHECK: vhadd.u32	q8, q8, q9
+
+0x40 0xef 0xa1 0x01
+# CHECK: vrhadd.s8	d16, d16, d17
+0x50 0xef 0xa1 0x01
+# CHECK: vrhadd.s16	d16, d16, d17
+0x60 0xef 0xa1 0x01
+# CHECK: vrhadd.s32	d16, d16, d17
+0x40 0xff 0xa1 0x01
+# CHECK: vrhadd.u8	d16, d16, d17
+0x50 0xff 0xa1 0x01
+# CHECK: vrhadd.u16	d16, d16, d17
+0x60 0xff 0xa1 0x01
+# CHECK: vrhadd.u32	d16, d16, d17
+0x40 0xef 0xe2 0x01
+# CHECK: vrhadd.s8	q8, q8, q9
+0x50 0xef 0xe2 0x01
+# CHECK: vrhadd.s16	q8, q8, q9
+0x60 0xef 0xe2 0x01
+# CHECK: vrhadd.s32	q8, q8, q9
+0x40 0xff 0xe2 0x01
+# CHECK: vrhadd.u8	q8, q8, q9
+0x50 0xff 0xe2 0x01
+# CHECK: vrhadd.u16	q8, q8, q9
+0x60 0xff 0xe2 0x01
+# CHECK: vrhadd.u32	q8, q8, q9
+
+0x40 0xef 0xb1 0x00
+# CHECK: vqadd.s8	d16, d16, d17
+0x50 0xef 0xb1 0x00
+# CHECK: vqadd.s16	d16, d16, d17
+0x60 0xef 0xb1 0x00
+# CHECK: vqadd.s32	d16, d16, d17
+0x70 0xef 0xb1 0x00
+# CHECK: vqadd.s64	d16, d16, d17
+0x40 0xff 0xb1 0x00
+# CHECK: vqadd.u8	d16, d16, d17
+0x50 0xff 0xb1 0x00
+# CHECK: vqadd.u16	d16, d16, d17
+0x60 0xff 0xb1 0x00
+# CHECK: vqadd.u32	d16, d16, d17
+0x70 0xff 0xb1 0x00
+# CHECK: vqadd.u64	d16, d16, d17
+0x40 0xef 0xf2 0x00
+# CHECK: vqadd.s8	q8, q8, q9
+0x50 0xef 0xf2 0x00
+# CHECK: vqadd.s16	q8, q8, q9
+0x60 0xef 0xf2 0x00
+# CHECK: vqadd.s32	q8, q8, q9
+0x70 0xef 0xf2 0x00
+# CHECK: vqadd.s64	q8, q8, q9
+0x40 0xff 0xf2 0x00
+# CHECK: vqadd.u8	q8, q8, q9
+0x50 0xff 0xf2 0x00
+# CHECK: vqadd.u16	q8, q8, q9
+0x60 0xff 0xf2 0x00
+# CHECK: vqadd.u32	q8, q8, q9
+0x70 0xff 0xf2 0x00
+# CHECK: vqadd.u64	q8, q8, q9
+
+0xc0 0xef 0xa2 0x04
+# CHECK: vaddhn.i16	d16, q8, q9
+0xd0 0xef 0xa2 0x04
+# CHECK: vaddhn.i32	d16, q8, q9
+0xe0 0xef 0xa2 0x04
+# CHECK: vaddhn.i64	d16, q8, q9
+0xc0 0xff 0xa2 0x04
+# CHECK: vraddhn.i16	d16, q8, q9
+0xd0 0xff 0xa2 0x04
+# CHECK: vraddhn.i32	d16, q8, q9
+0xe0 0xff 0xa2 0x04
+# CHECK: vraddhn.i64	d16, q8, q9
+
+0xf0 0xff 0x20 0x05
+# CHECK: vcnt.8	d16, d16
+0xf0 0xff 0x60 0x05
+# CHECK: vcnt.8	q8, q8
+0xf0 0xff 0xa0 0x04
+# CHECK: vclz.i8	d16, d16
+0xf4 0xff 0xa0 0x04
+# CHECK: vclz.i16	d16, d16
+0xf8 0xff 0xa0 0x04
+# CHECK: vclz.i32	d16, d16
+0xf0 0xff 0xe0 0x04
+# CHECK: vclz.i8	q8, q8
+0xf4 0xff 0xe0 0x04
+# CHECK: vclz.i16	q8, q8
+0xf8 0xff 0xe0 0x04
+# CHECK: vclz.i32	q8, q8
+0xf0 0xff 0x20 0x04
+# CHECK: vcls.s8	d16, d16
+0xf4 0xff 0x20 0x04
+# CHECK: vcls.s16	d16, d16
+0xf8 0xff 0x20 0x04
+# CHECK: vcls.s32	d16, d16
+0xf0 0xff 0x60 0x04
+# CHECK: vcls.s8	q8, q8
+0xf4 0xff 0x60 0x04
+# CHECK: vcls.s16	q8, q8
+0xf8 0xff 0x60 0x04
+# CHECK: vcls.s32	q8, q8
+
+
+0x41 0xef 0xb0 0x01
+# CHECK: vand	d16, d17, d16
+0x40 0xef 0xf2 0x01
+# CHECK: vand	q8, q8, q9
+
+0x41 0xff 0xb0 0x01
+# CHECK: veor	d16, d17, d16
+0x40 0xff 0xf2 0x01
+# CHECK: veor	q8, q8, q9
+
+0x61 0xef 0xb0 0x01
+# CHECK: vorr	d16, d17, d16
+0x60 0xef 0xf2 0x01
+# CHECK: vorr	q8, q8, q9
+0xc0 0xef 0x11 0x07
+# CHECK: vorr.i32	d16, #0x1000000
+0xc0 0xef 0x51 0x07
+# CHECK: vorr.i32	q8, #0x1000000
+0xc0 0xef 0x50 0x01
+# CHECK: vorr.i32	q8, #0x0
+
+0x51 0xef 0xb0 0x01
+# CHECK: vbic	d16, d17, d16
+0x50 0xef 0xf2 0x01
+# CHECK: vbic	q8, q8, q9
+0xc7 0xff 0x3f 0x07
+# CHECK: vbic.i32	d16, #0xFF000000
+0xc7 0xff 0x7f 0x07
+# CHECK: vbic.i32	q8, #0xFF000000
+
+0x71 0xef 0xb0 0x01
+# CHECK: vorn	d16, d17, d16
+0x70 0xef 0xf2 0x01
+# CHECK: vorn	q8, q8, q9
+
+0xf0 0xff 0xa0 0x05
+# CHECK: vmvn	d16, d16
+0xf0 0xff 0xe0 0x05
+# CHECK: vmvn	q8, q8
+
+0x51 0xff 0xb0 0x21
+# CHECK: vbsl	d18, d17, d16
+0x54 0xff 0xf2 0x01
+# CHECK: vbsl	q8, q10, q9
+
+0xfb 0xff 0x20 0x07
+# CHECK: vcvt.s32.f32	d16, d16
+0xfb 0xff 0xa0 0x07
+# CHECK: vcvt.u32.f32	d16, d16
+0xfb 0xff 0x20 0x06
+# CHECK: vcvt.f32.s32	d16, d16
+0xfb 0xff 0xa0 0x06
+# CHECK: vcvt.f32.u32	d16, d16
+0xfb 0xff 0x60 0x07
+# CHECK: vcvt.s32.f32	q8, q8
+0xfb 0xff 0xe0 0x07
+# CHECK: vcvt.u32.f32	q8, q8
+0xfb 0xff 0x60 0x06
+# CHECK: vcvt.f32.s32	q8, q8
+0xfb 0xff 0xe0 0x06
+# CHECK: vcvt.f32.u32	q8, q8
+0xff 0xef 0x30 0x0f
+# CHECK: vcvt.s32.f32	d16, d16, #1
+0xff 0xff 0x30 0x0f
+# CHECK: vcvt.u32.f32	d16, d16, #1
+0xff 0xef 0x30 0x0e
+# CHECK: vcvt.f32.s32	d16, d16, #1
+0xff 0xff 0x30 0x0e
+# CHECK: vcvt.f32.u32	d16, d16, #1
+0xff 0xef 0x70 0x0f
+# CHECK: vcvt.s32.f32	q8, q8, #1
+0xff 0xff 0x70 0x0f
+# CHECK: vcvt.u32.f32	q8, q8, #1
+0xff 0xef 0x70 0x0e
+# CHECK: vcvt.f32.s32	q8, q8, #1
+0xff 0xff 0x70 0x0e
+# CHECK: vcvt.f32.u32	q8, q8, #1
+0xfb 0xff 0x20 0x07
+# CHECK: vcvt.s32.f32	d16, d16
+0xfb 0xff 0xa0 0x07
+# CHECK: vcvt.u32.f32	d16, d16
+0xfb 0xff 0x20 0x06
+# CHECK: vcvt.f32.s32	d16, d16
+0xfb 0xff 0xa0 0x06
+# CHECK: vcvt.f32.u32	d16, d16
+0xfb 0xff 0x60 0x07
+# CHECK: vcvt.s32.f32	q8, q8
+0xfb 0xff 0xe0 0x07
+# CHECK: vcvt.u32.f32	q8, q8
+0xfb 0xff 0x60 0x06
+# CHECK: vcvt.f32.s32	q8, q8
+0xfb 0xff 0xe0 0x06
+# CHECK: vcvt.f32.u32	q8, q8
+0xff 0xef 0x30 0x0f
+# CHECK: vcvt.s32.f32	d16, d16, #1
+0xff 0xff 0x30 0x0f
+# CHECK: vcvt.u32.f32	d16, d16, #1
+0xff 0xef 0x30 0x0e
+# CHECK: vcvt.f32.s32	d16, d16, #1
+0xff 0xff 0x30 0x0e
+# CHECK: vcvt.f32.u32	d16, d16, #1
+0xff 0xef 0x70 0x0f
+# CHECK: vcvt.s32.f32	q8, q8, #1
+0xff 0xff 0x70 0x0f
+# CHECK: vcvt.u32.f32	q8, q8, #1
+0xff 0xef 0x70 0x0e
+# CHECK: vcvt.f32.s32	q8, q8, #1
+0xff 0xff 0x70 0x0e
+# CHECK: vcvt.f32.u32	q8, q8, #1
+0xf6 0xff 0x20 0x07
+# CHECK: vcvt.f32.f16	q8, d16
+0xf6 0xff 0x20 0x06
+# CHECK: vcvt.f16.f32	d16, q8
+
+0xc0 0xee 0x90 0x0b
+# CHECK: vdup.8	d16, r0
+0x80 0xee 0xb0 0x0b
+# CHECK: vdup.16	d16, r0
+0x80 0xee 0x90 0x0b
+# CHECK: vdup.32	d16, r0
+0xe0 0xee 0x90 0x0b
+# CHECK: vdup.8	q8, r0
+0xa0 0xee 0xb0 0x0b
+# CHECK: vdup.16	q8, r0
+0xa0 0xee 0x90 0x0b
+# CHECK: vdup.32	q8, r0
+0xf3 0xff 0x20 0x0c
+# CHECK: vdup.8	d16, d16[1]
+0xf6 0xff 0x20 0x0c
+# CHECK: vdup.16	d16, d16[1]
+0xfc 0xff 0x20 0x0c
+# CHECK: vdup.32	d16, d16[1]
+0xf3 0xff 0x60 0x0c
+# CHECK: vdup.8	q8, d16[1]
+0xf6 0xff 0x60 0x0c
+# CHECK: vdup.16	q8, d16[1]
+0xfc 0xff 0x60 0x0c
+# CHECK: vdup.32	q8, d16[1]
+
+0x40 0xef 0xb1 0x06
+# CHECK: vmin.s8	d16, d16, d17
+0x50 0xef 0xb1 0x06
+# CHECK: vmin.s16	d16, d16, d17
+0x60 0xef 0xb1 0x06
+# CHECK: vmin.s32	d16, d16, d17
+0x40 0xff 0xb1 0x06
+# CHECK: vmin.u8	d16, d16, d17
+0x50 0xff 0xb1 0x06
+# CHECK: vmin.u16	d16, d16, d17
+0x60 0xff 0xb1 0x06
+# CHECK: vmin.u32	d16, d16, d17
+0x60 0xef 0xa1 0x0f
+# CHECK: vmin.f32	d16, d16, d17
+0x40 0xef 0xf2 0x06
+# CHECK: vmin.s8	q8, q8, q9
+0x50 0xef 0xf2 0x06
+# CHECK: vmin.s16	q8, q8, q9
+0x60 0xef 0xf2 0x06
+# CHECK: vmin.s32	q8, q8, q9
+0x40 0xff 0xf2 0x06
+# CHECK: vmin.u8	q8, q8, q9
+0x50 0xff 0xf2 0x06
+# CHECK: vmin.u16	q8, q8, q9
+0x60 0xff 0xf2 0x06
+# CHECK: vmin.u32	q8, q8, q9
+0x60 0xef 0xe2 0x0f
+# CHECK: vmin.f32	q8, q8, q9
+0x40 0xef 0xa1 0x06
+# CHECK: vmax.s8	d16, d16, d17
+0x50 0xef 0xa1 0x06
+# CHECK: vmax.s16	d16, d16, d17
+0x60 0xef 0xa1 0x06
+# CHECK: vmax.s32	d16, d16, d17
+0x40 0xff 0xa1 0x06
+# CHECK: vmax.u8	d16, d16, d17
+0x50 0xff 0xa1 0x06
+# CHECK: vmax.u16	d16, d16, d17
+0x60 0xff 0xa1 0x06
+# CHECK: vmax.u32	d16, d16, d17
+0x40 0xef 0xa1 0x0f
+# CHECK: vmax.f32	d16, d16, d17
+0x40 0xef 0xe2 0x06
+# CHECK: vmax.s8	q8, q8, q9
+0x50 0xef 0xe2 0x06
+# CHECK: vmax.s16	q8, q8, q9
+0x60 0xef 0xe2 0x06
+# CHECK: vmax.s32	q8, q8, q9
+0x40 0xff 0xe2 0x06
+# CHECK: vmax.u8	q8, q8, q9
+0x50 0xff 0xe2 0x06
+# CHECK: vmax.u16	q8, q8, q9
+0x60 0xff 0xe2 0x06
+# CHECK: vmax.u32	q8, q8, q9
+0x40 0xef 0xe2 0x0f
+# CHECK: vmax.f32	q8, q8, q9
+
+0xc0 0xef 0x18 0x0e
+# CHECK: vmov.i8	d16, #0x8
+0xc1 0xef 0x10 0x08
+# CHECK: vmov.i16	d16, #0x10
+0xc1 0xef 0x10 0x0a
+# CHECK: vmov.i16	d16, #0x1000
+0xc2 0xef 0x10 0x00
+# CHECK: vmov.i32	d16, #0x20
+0xc2 0xef 0x10 0x02
+# CHECK: vmov.i32	d16, #0x2000
+0xc2 0xef 0x10 0x04
+# CHECK: vmov.i32	d16, #0x200000
+0xc2 0xef 0x10 0x06
+# CHECK: vmov.i32	d16, #0x20000000
+0xc2 0xef 0x10 0x0c
+# CHECK: vmov.i32	d16, #0x20FF
+0xc2 0xef 0x10 0x0d
+# CHECK: vmov.i32	d16, #0x20FFFF
+0xc1 0xff 0x33 0x0e
+# CHECK: vmov.i64	d16, #0xFF0000FF0000FFFF
+0xc0 0xef 0x58 0x0e
+# CHECK: vmov.i8	q8, #0x8
+0xc1 0xef 0x50 0x08
+# CHECK: vmov.i16	q8, #0x10
+0xc1 0xef 0x50 0x0a
+# CHECK: vmov.i16	q8, #0x1000
+0xc2 0xef 0x50 0x00
+# CHECK: vmov.i32	q8, #0x20
+0xc2 0xef 0x50 0x02
+# CHECK: vmov.i32	q8, #0x2000
+0xc2 0xef 0x50 0x04
+# CHECK: vmov.i32	q8, #0x200000
+0xc2 0xef 0x50 0x06
+# CHECK: vmov.i32	q8, #0x20000000
+0xc2 0xef 0x50 0x0c
+# CHECK: vmov.i32	q8, #0x20FF
+0xc2 0xef 0x50 0x0d
+# CHECK: vmov.i32	q8, #0x20FFFF
+0xc1 0xff 0x73 0x0e
+# CHECK: vmov.i64	q8, #0xFF0000FF0000FFFF
+0xc1 0xef 0x30 0x08
+# CHECK: vmvn.i16	d16, #0x10
+0xc1 0xef 0x30 0x0a
+# CHECK: vmvn.i16	d16, #0x1000
+0xc2 0xef 0x30 0x00
+# CHECK: vmvn.i32	d16, #0x20
+0xc2 0xef 0x30 0x02
+# CHECK: vmvn.i32	d16, #0x2000
+0xc2 0xef 0x30 0x04
+# CHECK: vmvn.i32	d16, #0x200000
+0xc2 0xef 0x30 0x06
+# CHECK: vmvn.i32	d16, #0x20000000
+0xc2 0xef 0x30 0x0c
+# CHECK: vmvn.i32	d16, #0x20FF
+0xc2 0xef 0x30 0x0d
+# CHECK: vmvn.i32	d16, #0x20FFFF
+0xc8 0xef 0x30 0x0a
+# CHECK: vmovl.s8	q8, d16
+0xd0 0xef 0x30 0x0a
+# CHECK: vmovl.s16	q8, d16
+0xe0 0xef 0x30 0x0a
+# CHECK: vmovl.s32	q8, d16
+0xc8 0xff 0x30 0x0a
+# CHECK: vmovl.u8	q8, d16
+0xd0 0xff 0x30 0x0a
+# CHECK: vmovl.u16	q8, d16
+0xe0 0xff 0x30 0x0a
+# CHECK: vmovl.u32	q8, d16
+0xf2 0xff 0x20 0x02
+# CHECK: vmovn.i16	d16, q8
+0xf6 0xff 0x20 0x02
+# CHECK: vmovn.i32	d16, q8
+0xfa 0xff 0x20 0x02
+# CHECK: vmovn.i64	d16, q8
+0xf2 0xff 0xa0 0x02
+# CHECK: vqmovn.s16	d16, q8
+0xf6 0xff 0xa0 0x02
+# CHECK: vqmovn.s32	d16, q8
+0xfa 0xff 0xa0 0x02
+# CHECK: vqmovn.s64	d16, q8
+0xf2 0xff 0xe0 0x02
+# CHECK: vqmovn.u16	d16, q8
+0xf6 0xff 0xe0 0x02
+# CHECK: vqmovn.u32	d16, q8
+0xfa 0xff 0xe0 0x02
+# CHECK: vqmovn.u64	d16, q8
+0xf2 0xff 0x60 0x02
+# CHECK: vqmovun.s16	d16, q8
+0xf6 0xff 0x60 0x02
+# CHECK: vqmovun.s32	d16, q8
+0xfa 0xff 0x60 0x02
+# CHECK: vqmovun.s64	d16, q8
+0x50 0xee 0xb0 0x0b
+# CHECK: vmov.s8	r0, d16[1]
+0x10 0xee 0xf0 0x0b
+# CHECK: vmov.s16	r0, d16[1]
+0xd0 0xee 0xb0 0x0b
+# CHECK: vmov.u8	r0, d16[1]
+0x90 0xee 0xf0 0x0b
+# CHECK: vmov.u16	r0, d16[1]
+0x30 0xee 0x90 0x0b
+# CHECK: vmov.32	r0, d16[1]
+0x40 0xee 0xb0 0x1b
+# CHECK: vmov.8	d16[1], r1
+0x00 0xee 0xf0 0x1b
+# CHECK: vmov.16	d16[1], r1
+0x20 0xee 0x90 0x1b
+# CHECK: vmov.32	d16[1], r1
+0x42 0xee 0xb0 0x1b
+# CHECK: vmov.8	d18[1], r1
+0x02 0xee 0xf0 0x1b
+# CHECK: vmov.16	d18[1], r1
+0x22 0xee 0x90 0x1b
+# CHECK: vmov.32	d18[1], r1
+
+0x42 0xef 0xa1 0x09
+# CHECK: vmla.i8	d16, d18, d17
+0x52 0xef 0xa1 0x09
+# CHECK: vmla.i16	d16, d18, d17
+0x62 0xef 0xa1 0x09
+# CHECK: vmla.i32	d16, d18, d17
+0x42 0xef 0xb1 0x0d
+# CHECK: vmla.f32	d16, d18, d17
+0x40 0xef 0xe4 0x29
+# CHECK: vmla.i8	q9, q8, q10
+0x50 0xef 0xe4 0x29
+# CHECK: vmla.i16	q9, q8, q10
+0x60 0xef 0xe4 0x29
+# CHECK: vmla.i32	q9, q8, q10
+0x40 0xef 0xf4 0x2d
+# CHECK: vmla.f32	q9, q8, q10
+0xc3 0xef 0xa2 0x08
+# CHECK: vmlal.s8	q8, d19, d18
+0xd3 0xef 0xa2 0x08
+# CHECK: vmlal.s16	q8, d19, d18
+0xe3 0xef 0xa2 0x08
+# CHECK: vmlal.s32	q8, d19, d18
+0xc3 0xff 0xa2 0x08
+# CHECK: vmlal.u8	q8, d19, d18
+0xd3 0xff 0xa2 0x08
+# CHECK: vmlal.u16	q8, d19, d18
+0xe3 0xff 0xa2 0x08
+# CHECK: vmlal.u32	q8, d19, d18
+0xd3 0xef 0xa2 0x09
+# CHECK: vqdmlal.s16	q8, d19, d18
+0xe3 0xef 0xa2 0x09
+# CHECK: vqdmlal.s32	q8, d19, d18
+0x42 0xff 0xa1 0x09
+# CHECK: vmls.i8	d16, d18, d17
+0x52 0xff 0xa1 0x09
+# CHECK: vmls.i16	d16, d18, d17
+0x62 0xff 0xa1 0x09
+# CHECK: vmls.i32	d16, d18, d17
+0x62 0xef 0xb1 0x0d
+# CHECK: vmls.f32	d16, d18, d17
+0x40 0xff 0xe4 0x29
+# CHECK: vmls.i8	q9, q8, q10
+0x50 0xff 0xe4 0x29
+# CHECK: vmls.i16	q9, q8, q10
+0x60 0xff 0xe4 0x29
+# CHECK: vmls.i32	q9, q8, q10
+0x60 0xef 0xf4 0x2d
+# CHECK: vmls.f32	q9, q8, q10
+0xc3 0xef 0xa2 0x0a
+# CHECK: vmlsl.s8	q8, d19, d18
+0xd3 0xef 0xa2 0x0a
+# CHECK: vmlsl.s16	q8, d19, d18
+0xe3 0xef 0xa2 0x0a
+# CHECK: vmlsl.s32	q8, d19, d18
+0xc3 0xff 0xa2 0x0a
+# CHECK: vmlsl.u8	q8, d19, d18
+0xd3 0xff 0xa2 0x0a
+# CHECK: vmlsl.u16	q8, d19, d18
+0xe3 0xff 0xa2 0x0a
+# CHECK: vmlsl.u32	q8, d19, d18
+0xd3 0xef 0xa2 0x0b
+# CHECK: vqdmlsl.s16	q8, d19, d18
+0xe3 0xef 0xa2 0x0b
+# CHECK: vqdmlsl.s32	q8, d19, d18
+
+0x40 0xef 0xb1 0x09
+# CHECK: vmul.i8	d16, d16, d17
+0x50 0xef 0xb1 0x09
+# CHECK: vmul.i16	d16, d16, d17
+0x60 0xef 0xb1 0x09
+# CHECK: vmul.i32	d16, d16, d17
+0x40 0xff 0xb1 0x0d
+# CHECK: vmul.f32	d16, d16, d17
+0x40 0xef 0xf2 0x09
+# CHECK: vmul.i8	q8, q8, q9
+0x50 0xef 0xf2 0x09
+# CHECK: vmul.i16	q8, q8, q9
+0x60 0xef 0xf2 0x09
+# CHECK: vmul.i32	q8, q8, q9
+0x40 0xff 0xf2 0x0d
+# CHECK: vmul.f32	q8, q8, q9
+0x40 0xff 0xb1 0x09
+# CHECK: vmul.p8	d16, d16, d17
+0x40 0xff 0xf2 0x09
+# CHECK: vmul.p8	q8, q8, q9
+0x50 0xef 0xa1 0x0b
+# CHECK: vqdmulh.s16	d16, d16, d17
+0x60 0xef 0xa1 0x0b
+# CHECK: vqdmulh.s32	d16, d16, d17
+0x50 0xef 0xe2 0x0b
+# CHECK: vqdmulh.s16	q8, q8, q9
+0x60 0xef 0xe2 0x0b
+# CHECK: vqdmulh.s32	q8, q8, q9
+0x50 0xff 0xa1 0x0b
+# CHECK: vqrdmulh.s16	d16, d16, d17
+0x60 0xff 0xa1 0x0b
+# CHECK: vqrdmulh.s32	d16, d16, d17
+0x50 0xff 0xe2 0x0b
+# CHECK: vqrdmulh.s16	q8, q8, q9
+0x60 0xff 0xe2 0x0b
+# CHECK: vqrdmulh.s32	q8, q8, q9
+0xc0 0xef 0xa1 0x0c
+# CHECK: vmull.s8	q8, d16, d17
+0xd0 0xef 0xa1 0x0c
+# CHECK: vmull.s16	q8, d16, d17
+0xe0 0xef 0xa1 0x0c
+# CHECK: vmull.s32	q8, d16, d17
+0xc0 0xff 0xa1 0x0c
+# CHECK: vmull.u8	q8, d16, d17
+0xd0 0xff 0xa1 0x0c
+# CHECK: vmull.u16	q8, d16, d17
+0xe0 0xff 0xa1 0x0c
+# CHECK: vmull.u32	q8, d16, d17
+0xc0 0xef 0xa1 0x0e
+# CHECK: vmull.p8	q8, d16, d17
+0xd0 0xef 0xa1 0x0d
+# CHECK: vqdmull.s16	q8, d16, d17
+0xe0 0xef 0xa1 0x0d
+# CHECK: vqdmull.s32	q8, d16, d17
+0xf1 0xff 0xa0 0x03
+# CHECK: vneg.s8	d16, d16
+0xf5 0xff 0xa0 0x03
+# CHECK: vneg.s16	d16, d16
+0xf9 0xff 0xa0 0x03
+# CHECK: vneg.s32	d16, d16
+0xf9 0xff 0xa0 0x07
+# CHECK: vneg.f32	d16, d16
+0xf1 0xff 0xe0 0x03
+# CHECK: vneg.s8	q8, q8
+0xf5 0xff 0xe0 0x03
+# CHECK: vneg.s16	q8, q8
+0xf9 0xff 0xe0 0x03
+# CHECK: vneg.s32	q8, q8
+0xf9 0xff 0xe0 0x07
+# CHECK: vneg.f32	q8, q8
+0xf0 0xff 0xa0 0x07
+# CHECK: vqneg.s8	d16, d16
+0xf4 0xff 0xa0 0x07
+# CHECK: vqneg.s16	d16, d16
+0xf8 0xff 0xa0 0x07
+# CHECK: vqneg.s32	d16, d16
+0xf0 0xff 0xe0 0x07
+# CHECK: vqneg.s8	q8, q8
+0xf4 0xff 0xe0 0x07
+# CHECK: vqneg.s16	q8, q8
+0xf8 0xff 0xe0 0x07
+# CHECK: vqneg.s32	q8, q8
+
+0x41 0xef 0xb0 0x0b
+# CHECK: vpadd.i8	d16, d17, d16
+0x51 0xef 0xb0 0x0b
+# CHECK: vpadd.i16	d16, d17, d16
+0x61 0xef 0xb0 0x0b
+# CHECK: vpadd.i32	d16, d17, d16
+0x40 0xff 0xa1 0x0d
+# CHECK: vpadd.f32	d16, d16, d17
+0xf0 0xff 0x20 0x02
+# CHECK: vpaddl.s8	d16, d16
+0xf4 0xff 0x20 0x02
+# CHECK: vpaddl.s16	d16, d16
+0xf8 0xff 0x20 0x02
+# CHECK: vpaddl.s32	d16, d16
+0xf0 0xff 0xa0 0x02
+# CHECK: vpaddl.u8	d16, d16
+0xf4 0xff 0xa0 0x02
+# CHECK: vpaddl.u16	d16, d16
+0xf8 0xff 0xa0 0x02
+# CHECK: vpaddl.u32	d16, d16
+0xf0 0xff 0x60 0x02
+# CHECK: vpaddl.s8	q8, q8
+0xf4 0xff 0x60 0x02
+# CHECK: vpaddl.s16	q8, q8
+0xf8 0xff 0x60 0x02
+# CHECK: vpaddl.s32	q8, q8
+0xf0 0xff 0xe0 0x02
+# CHECK: vpaddl.u8	q8, q8
+0xf4 0xff 0xe0 0x02
+# CHECK: vpaddl.u16	q8, q8
+0xf8 0xff 0xe0 0x02
+# CHECK: vpaddl.u32	q8, q8
+0xf0 0xff 0x21 0x06
+# CHECK: vpadal.s8	d16, d17
+0xf4 0xff 0x21 0x06
+# CHECK: vpadal.s16	d16, d17
+0xf8 0xff 0x21 0x06
+# CHECK: vpadal.s32	d16, d17
+0xf0 0xff 0xa1 0x06
+# CHECK: vpadal.u8	d16, d17
+0xf4 0xff 0xa1 0x06
+# CHECK: vpadal.u16	d16, d17
+0xf8 0xff 0xa1 0x06
+# CHECK: vpadal.u32	d16, d17
+0xf0 0xff 0x60 0x26
+# CHECK: vpadal.s8	q9, q8
+0xf4 0xff 0x60 0x26
+# CHECK: vpadal.s16	q9, q8
+0xf8 0xff 0x60 0x26
+# CHECK: vpadal.s32	q9, q8
+0xf0 0xff 0xe0 0x26
+# CHECK: vpadal.u8	q9, q8
+0xf4 0xff 0xe0 0x26
+# CHECK: vpadal.u16	q9, q8
+0xf8 0xff 0xe0 0x26
+# CHECK: vpadal.u32	q9, q8
+0x40 0xef 0xb1 0x0a
+# CHECK: vpmin.s8	d16, d16, d17
+0x50 0xef 0xb1 0x0a
+# CHECK: vpmin.s16	d16, d16, d17
+0x60 0xef 0xb1 0x0a
+# CHECK: vpmin.s32	d16, d16, d17
+0x40 0xff 0xb1 0x0a
+# CHECK: vpmin.u8	d16, d16, d17
+0x50 0xff 0xb1 0x0a
+# CHECK: vpmin.u16	d16, d16, d17
+0x60 0xff 0xb1 0x0a
+# CHECK: vpmin.u32	d16, d16, d17
+0x60 0xff 0xa1 0x0f
+# CHECK: vpmin.f32	d16, d16, d17
+0x40 0xef 0xa1 0x0a
+# CHECK: vpmax.s8	d16, d16, d17
+0x50 0xef 0xa1 0x0a
+# CHECK: vpmax.s16	d16, d16, d17
+0x60 0xef 0xa1 0x0a
+# CHECK: vpmax.s32	d16, d16, d17
+0x40 0xff 0xa1 0x0a
+# CHECK: vpmax.u8	d16, d16, d17
+0x50 0xff 0xa1 0x0a
+# CHECK: vpmax.u16	d16, d16, d17
+0x60 0xff 0xa1 0x0a
+# CHECK: vpmax.u32	d16, d16, d17
+0x40 0xff 0xa1 0x0f
+# CHECK: vpmax.f32	d16, d16, d17
+0xfb 0xff 0x20 0x04
+# CHECK: vrecpe.u32	d16, d16
+0xfb 0xff 0x60 0x04
+# CHECK: vrecpe.u32	q8, q8
+0xfb 0xff 0x20 0x05
+# CHECK: vrecpe.f32	d16, d16
+0xfb 0xff 0x60 0x05
+# CHECK: vrecpe.f32	q8, q8
+0x40 0xef 0xb1 0x0f
+# CHECK: vrecps.f32	d16, d16, d17
+0x40 0xef 0xf2 0x0f
+# CHECK: vrecps.f32	q8, q8, q9
+0xfb 0xff 0xa0 0x04
+# CHECK: vrsqrte.u32	d16, d16
+0xfb 0xff 0xe0 0x04
+# CHECK: vrsqrte.u32	q8, q8
+0xfb 0xff 0xa0 0x05
+# CHECK: vrsqrte.f32	d16, d16
+0xfb 0xff 0xe0 0x05
+# CHECK: vrsqrte.f32	q8, q8
+0x60 0xef 0xb1 0x0f
+# CHECK: vrsqrts.f32	d16, d16, d17
+0x60 0xef 0xf2 0x0f
+# CHECK: vrsqrts.f32	q8, q8, q9
+
+
+0xf0 0xff 0x20 0x00
+# CHECK: vrev64.8	d16, d16
+0xf4 0xff 0x20 0x00
+# CHECK: vrev64.16	d16, d16
+0xf8 0xff 0x20 0x00
+# CHECK: vrev64.32	d16, d16
+0xf0 0xff 0x60 0x00
+# CHECK: vrev64.8	q8, q8
+0xf4 0xff 0x60 0x00
+# CHECK: vrev64.16	q8, q8
+0xf8 0xff 0x60 0x00
+# CHECK: vrev64.32	q8, q8
+0xf0 0xff 0xa0 0x00
+# CHECK: vrev32.8	d16, d16
+0xf4 0xff 0xa0 0x00
+# CHECK: vrev32.16	d16, d16
+0xf0 0xff 0xe0 0x00
+# CHECK: vrev32.8	q8, q8
+0xf4 0xff 0xe0 0x00
+# CHECK: vrev32.16	q8, q8
+0xf0 0xff 0x20 0x01
+# CHECK: vrev16.8	d16, d16
+0xf0 0xff 0x60 0x01
+# CHECK: vrev16.8	q8, q8
+0x41 0xef 0xb0 0x04
+# CHECK: vqshl.s8	d16, d16, d17
+0x51 0xef 0xb0 0x04
+# CHECK: vqshl.s16	d16, d16, d17
+0x61 0xef 0xb0 0x04
+# CHECK: vqshl.s32	d16, d16, d17
+0x71 0xef 0xb0 0x04
+# CHECK: vqshl.s64	d16, d16, d17
+0x41 0xff 0xb0 0x04
+# CHECK: vqshl.u8	d16, d16, d17
+0x51 0xff 0xb0 0x04
+# CHECK: vqshl.u16	d16, d16, d17
+0x61 0xff 0xb0 0x04
+# CHECK: vqshl.u32	d16, d16, d17
+0x71 0xff 0xb0 0x04
+# CHECK: vqshl.u64	d16, d16, d17
+0x42 0xef 0xf0 0x04
+# CHECK: vqshl.s8	q8, q8, q9
+0x52 0xef 0xf0 0x04
+# CHECK: vqshl.s16	q8, q8, q9
+0x62 0xef 0xf0 0x04
+# CHECK: vqshl.s32	q8, q8, q9
+0x72 0xef 0xf0 0x04
+# CHECK: vqshl.s64	q8, q8, q9
+0x42 0xff 0xf0 0x04
+# CHECK: vqshl.u8	q8, q8, q9
+0x52 0xff 0xf0 0x04
+# CHECK: vqshl.u16	q8, q8, q9
+0x62 0xff 0xf0 0x04
+# CHECK: vqshl.u32	q8, q8, q9
+0x72 0xff 0xf0 0x04
+# CHECK: vqshl.u64	q8, q8, q9
+0xcf 0xef 0x30 0x07
+# CHECK: vqshl.s8	d16, d16, #7
+0xdf 0xef 0x30 0x07
+# CHECK: vqshl.s16	d16, d16, #15
+0xff 0xef 0x30 0x07
+# CHECK: vqshl.s32	d16, d16, #31
+0xff 0xef 0xb0 0x07
+# CHECK: vqshl.s64	d16, d16, #63
+0xcf 0xff 0x30 0x07
+# CHECK: vqshl.u8	d16, d16, #7
+0xdf 0xff 0x30 0x07
+# CHECK: vqshl.u16	d16, d16, #15
+0xff 0xff 0x30 0x07
+# CHECK: vqshl.u32	d16, d16, #31
+0xff 0xff 0xb0 0x07
+# CHECK: vqshl.u64	d16, d16, #63
+0xcf 0xff 0x30 0x06
+# CHECK: vqshlu.s8	d16, d16, #7
+0xdf 0xff 0x30 0x06
+# CHECK: vqshlu.s16	d16, d16, #15
+0xff 0xff 0x30 0x06
+# CHECK: vqshlu.s32	d16, d16, #31
+0xff 0xff 0xb0 0x06
+# CHECK: vqshlu.s64	d16, d16, #63
+0xcf 0xef 0x70 0x07
+# CHECK: vqshl.s8	q8, q8, #7
+0xdf 0xef 0x70 0x07
+# CHECK: vqshl.s16	q8, q8, #15
+0xff 0xef 0x70 0x07
+# CHECK: vqshl.s32	q8, q8, #31
+0xff 0xef 0xf0 0x07
+# CHECK: vqshl.s64	q8, q8, #63
+0xcf 0xff 0x70 0x07
+# CHECK: vqshl.u8	q8, q8, #7
+0xdf 0xff 0x70 0x07
+# CHECK: vqshl.u16	q8, q8, #15
+0xff 0xff 0x70 0x07
+# CHECK: vqshl.u32	q8, q8, #31
+0xff 0xff 0xf0 0x07
+# CHECK: vqshl.u64	q8, q8, #63
+0xcf 0xff 0x70 0x06
+# CHECK: vqshlu.s8	q8, q8, #7
+0xdf 0xff 0x70 0x06
+# CHECK: vqshlu.s16	q8, q8, #15
+0xff 0xff 0x70 0x06
+# CHECK: vqshlu.s32	q8, q8, #31
+0xff 0xff 0xf0 0x06
+# CHECK: vqshlu.s64	q8, q8, #63
+0x41 0xef 0xb0 0x05
+# CHECK: vqrshl.s8	d16, d16, d17
+0x51 0xef 0xb0 0x05
+# CHECK: vqrshl.s16	d16, d16, d17
+0x61 0xef 0xb0 0x05
+# CHECK: vqrshl.s32	d16, d16, d17
+0x71 0xef 0xb0 0x05
+# CHECK: vqrshl.s64	d16, d16, d17
+0x41 0xff 0xb0 0x05
+# CHECK: vqrshl.u8	d16, d16, d17
+0x51 0xff 0xb0 0x05
+# CHECK: vqrshl.u16	d16, d16, d17
+0x61 0xff 0xb0 0x05
+# CHECK: vqrshl.u32	d16, d16, d17
+0x71 0xff 0xb0 0x05
+# CHECK: vqrshl.u64	d16, d16, d17
+0x42 0xef 0xf0 0x05
+# CHECK: vqrshl.s8	q8, q8, q9
+0x52 0xef 0xf0 0x05
+# CHECK: vqrshl.s16	q8, q8, q9
+0x62 0xef 0xf0 0x05
+# CHECK: vqrshl.s32	q8, q8, q9
+0x72 0xef 0xf0 0x05
+# CHECK: vqrshl.s64	q8, q8, q9
+0x42 0xff 0xf0 0x05
+# CHECK: vqrshl.u8	q8, q8, q9
+0x52 0xff 0xf0 0x05
+# CHECK: vqrshl.u16	q8, q8, q9
+0x62 0xff 0xf0 0x05
+# CHECK: vqrshl.u32	q8, q8, q9
+0x72 0xff 0xf0 0x05
+# CHECK: vqrshl.u64	q8, q8, q9
+0xc8 0xef 0x30 0x09
+# CHECK: vqshrn.s16	d16, q8, #8
+0xd0 0xef 0x30 0x09
+# CHECK: vqshrn.s32	d16, q8, #16
+0xe0 0xef 0x30 0x09
+# CHECK: vqshrn.s64	d16, q8, #32
+0xc8 0xff 0x30 0x09
+# CHECK: vqshrn.u16	d16, q8, #8
+0xd0 0xff 0x30 0x09
+# CHECK: vqshrn.u32	d16, q8, #16
+0xe0 0xff 0x30 0x09
+# CHECK: vqshrn.u64	d16, q8, #32
+0xc8 0xff 0x30 0x08
+# CHECK: vqshrun.s16	d16, q8, #8
+0xd0 0xff 0x30 0x08
+# CHECK: vqshrun.s32	d16, q8, #16
+0xe0 0xff 0x30 0x08
+# CHECK: vqshrun.s64	d16, q8, #32
+0xc8 0xef 0x70 0x09
+# CHECK: vqrshrn.s16	d16, q8, #8
+0xd0 0xef 0x70 0x09
+# CHECK: vqrshrn.s32	d16, q8, #16
+0xe0 0xef 0x70 0x09
+# CHECK: vqrshrn.s64	d16, q8, #32
+0xc8 0xff 0x70 0x09
+# CHECK: vqrshrn.u16	d16, q8, #8
+0xd0 0xff 0x70 0x09
+# CHECK: vqrshrn.u32	d16, q8, #16
+0xe0 0xff 0x70 0x09
+# CHECK: vqrshrn.u64	d16, q8, #32
+0xc8 0xff 0x70 0x08
+# CHECK: vqrshrun.s16	d16, q8, #8
+0xd0 0xff 0x70 0x08
+# CHECK: vqrshrun.s32	d16, q8, #16
+0xe0 0xff 0x70 0x08
+# CHECK: vqrshrun.s64	d16, q8, #32
+0x40 0xff 0xa1 0x04
+# CHECK: vshl.u8	d16, d17, d16
+0x50 0xff 0xa1 0x04
+# CHECK: vshl.u16	d16, d17, d16
+0x60 0xff 0xa1 0x04
+# CHECK: vshl.u32	d16, d17, d16
+0x70 0xff 0xa1 0x04
+# CHECK: vshl.u64	d16, d17, d16
+0xcf 0xef 0x30 0x05
+# CHECK: vshl.i8	d16, d16, #7
+0xdf 0xef 0x30 0x05
+# CHECK: vshl.i16	d16, d16, #15
+0xff 0xef 0x30 0x05
+# CHECK: vshl.i32	d16, d16, #31
+0xff 0xef 0xb0 0x05
+# CHECK: vshl.i64	d16, d16, #63
+0x40 0xff 0xe2 0x04
+# CHECK: vshl.u8	q8, q9, q8
+0x50 0xff 0xe2 0x04
+# CHECK: vshl.u16	q8, q9, q8
+0x60 0xff 0xe2 0x04
+# CHECK: vshl.u32	q8, q9, q8
+0x70 0xff 0xe2 0x04
+# CHECK: vshl.u64	q8, q9, q8
+0xcf 0xef 0x70 0x05
+# CHECK: vshl.i8	q8, q8, #7
+0xdf 0xef 0x70 0x05
+# CHECK: vshl.i16	q8, q8, #15
+0xff 0xef 0x70 0x05
+# CHECK: vshl.i32	q8, q8, #31
+0xff 0xef 0xf0 0x05
+# CHECK: vshl.i64	q8, q8, #63
+0xc8 0xff 0x30 0x00
+# CHECK: vshr.u8	d16, d16, #8
+0xd0 0xff 0x30 0x00
+# CHECK: vshr.u16	d16, d16, #16
+0xe0 0xff 0x30 0x00
+# CHECK: vshr.u32	d16, d16, #32
+0xc0 0xff 0xb0 0x00
+# CHECK: vshr.u64	d16, d16, #64
+0xc8 0xff 0x70 0x00
+# CHECK: vshr.u8	q8, q8, #8
+0xd0 0xff 0x70 0x00
+# CHECK: vshr.u16	q8, q8, #16
+0xe0 0xff 0x70 0x00
+# CHECK: vshr.u32	q8, q8, #32
+0xc0 0xff 0xf0 0x00
+# CHECK: vshr.u64	q8, q8, #64
+0xc8 0xef 0x30 0x00
+# CHECK: vshr.s8	d16, d16, #8
+0xd0 0xef 0x30 0x00
+# CHECK: vshr.s16	d16, d16, #16
+0xe0 0xef 0x30 0x00
+# CHECK: vshr.s32	d16, d16, #32
+0xc0 0xef 0xb0 0x00
+# CHECK: vshr.s64	d16, d16, #64
+0xc8 0xef 0x70 0x00
+# CHECK: vshr.s8	q8, q8, #8
+0xd0 0xef 0x70 0x00
+# CHECK: vshr.s16	q8, q8, #16
+0xe0 0xef 0x70 0x00
+# CHECK: vshr.s32	q8, q8, #32
+0xc0 0xef 0xf0 0x00
+# CHECK: vshr.s64	q8, q8, #64
+0xcf 0xef 0x30 0x0a
+# CHECK: vshll.s8	q8, d16, #7
+0xdf 0xef 0x30 0x0a
+# CHECK: vshll.s16	q8, d16, #15
+0xff 0xef 0x30 0x0a
+# CHECK: vshll.s32	q8, d16, #31
+0xcf 0xff 0x30 0x0a
+# CHECK: vshll.u8	q8, d16, #7
+0xdf 0xff 0x30 0x0a
+# CHECK: vshll.u16	q8, d16, #15
+0xff 0xff 0x30 0x0a
+# CHECK: vshll.u32	q8, d16, #31
+0xf2 0xff 0x20 0x03
+# CHECK: vshll.i8	q8, d16, #8
+0xf6 0xff 0x20 0x03
+# CHECK: vshll.i16	q8, d16, #16
+0xfa 0xff 0x20 0x03
+# CHECK: vshll.i32	q8, d16, #32
+0xc8 0xef 0x30 0x08
+# CHECK: vshrn.i16	d16, q8, #8
+0xd0 0xef 0x30 0x08
+# CHECK: vshrn.i32	d16, q8, #16
+0xe0 0xef 0x30 0x08
+# CHECK: vshrn.i64	d16, q8, #32
+0x40 0xef 0xa1 0x05
+# CHECK: vrshl.s8	d16, d17, d16
+0x50 0xef 0xa1 0x05
+# CHECK: vrshl.s16	d16, d17, d16
+0x60 0xef 0xa1 0x05
+# CHECK: vrshl.s32	d16, d17, d16
+0x70 0xef 0xa1 0x05
+# CHECK: vrshl.s64	d16, d17, d16
+0x40 0xff 0xa1 0x05
+# CHECK: vrshl.u8	d16, d17, d16
+0x50 0xff 0xa1 0x05
+# CHECK: vrshl.u16	d16, d17, d16
+0x60 0xff 0xa1 0x05
+# CHECK: vrshl.u32	d16, d17, d16
+0x70 0xff 0xa1 0x05
+# CHECK: vrshl.u64	d16, d17, d16
+0x40 0xef 0xe2 0x05
+# CHECK: vrshl.s8	q8, q9, q8
+0x50 0xef 0xe2 0x05
+# CHECK: vrshl.s16	q8, q9, q8
+0x60 0xef 0xe2 0x05
+# CHECK: vrshl.s32	q8, q9, q8
+0x70 0xef 0xe2 0x05
+# CHECK: vrshl.s64	q8, q9, q8
+0x40 0xff 0xe2 0x05
+# CHECK: vrshl.u8	q8, q9, q8
+0x50 0xff 0xe2 0x05
+# CHECK: vrshl.u16	q8, q9, q8
+0x60 0xff 0xe2 0x05
+# CHECK: vrshl.u32	q8, q9, q8
+0x70 0xff 0xe2 0x05
+# CHECK: vrshl.u64	q8, q9, q8
+0xc8 0xef 0x30 0x02
+# CHECK: vrshr.s8	d16, d16, #8
+0xd0 0xef 0x30 0x02
+# CHECK: vrshr.s16	d16, d16, #16
+0xe0 0xef 0x30 0x02
+# CHECK: vrshr.s32	d16, d16, #32
+0xc0 0xef 0xb0 0x02
+# CHECK: vrshr.s64	d16, d16, #64
+0xc8 0xff 0x30 0x02
+# CHECK: vrshr.u8	d16, d16, #8
+0xd0 0xff 0x30 0x02
+# CHECK: vrshr.u16	d16, d16, #16
+0xe0 0xff 0x30 0x02
+# CHECK: vrshr.u32	d16, d16, #32
+0xc0 0xff 0xb0 0x02
+# CHECK: vrshr.u64	d16, d16, #64
+0xc8 0xef 0x70 0x02
+# CHECK: vrshr.s8	q8, q8, #8
+0xd0 0xef 0x70 0x02
+# CHECK: vrshr.s16	q8, q8, #16
+0xe0 0xef 0x70 0x02
+# CHECK: vrshr.s32	q8, q8, #32
+0xc0 0xef 0xf0 0x02
+# CHECK: vrshr.s64	q8, q8, #64
+0xc8 0xff 0x70 0x02
+# CHECK: vrshr.u8	q8, q8, #8
+0xd0 0xff 0x70 0x02
+# CHECK: vrshr.u16	q8, q8, #16
+0xe0 0xff 0x70 0x02
+# CHECK: vrshr.u32	q8, q8, #32
+0xc0 0xff 0xf0 0x02
+# CHECK: vrshr.u64	q8, q8, #64
+0xc8 0xef 0x70 0x08
+# CHECK: vrshrn.i16	d16, q8, #8
+0xd0 0xef 0x70 0x08
+# CHECK: vrshrn.i32	d16, q8, #16
+0xe0 0xef 0x70 0x08
+# CHECK: vrshrn.i64	d16, q8, #32
+0xc8 0xef 0x30 0x11
+# CHECK: vsra.s8	d17, d16, #8
+0xd0 0xef 0x30 0x11
+# CHECK: vsra.s16	d17, d16, #16
+0xe0 0xef 0x30 0x11
+# CHECK: vsra.s32	d17, d16, #32
+0xc0 0xef 0xb0 0x11
+# CHECK: vsra.s64	d17, d16, #64
+0xc8 0xef 0x72 0x01
+# CHECK: vsra.s8	q8, q9, #8
+0xd0 0xef 0x72 0x01
+# CHECK: vsra.s16	q8, q9, #16
+0xe0 0xef 0x72 0x01
+# CHECK: vsra.s32	q8, q9, #32
+0xc0 0xef 0xf2 0x01
+# CHECK: vsra.s64	q8, q9, #64
+0xc8 0xff 0x30 0x11
+# CHECK: vsra.u8	d17, d16, #8
+0xd0 0xff 0x30 0x11
+# CHECK: vsra.u16	d17, d16, #16
+0xe0 0xff 0x30 0x11
+# CHECK: vsra.u32	d17, d16, #32
+0xc0 0xff 0xb0 0x11
+# CHECK: vsra.u64	d17, d16, #64
+0xc8 0xff 0x72 0x01
+# CHECK: vsra.u8	q8, q9, #8
+0xd0 0xff 0x72 0x01
+# CHECK: vsra.u16	q8, q9, #16
+0xe0 0xff 0x72 0x01
+# CHECK: vsra.u32	q8, q9, #32
+0xc0 0xff 0xf2 0x01
+# CHECK: vsra.u64	q8, q9, #64
+0xc8 0xef 0x30 0x13
+# CHECK: vrsra.s8	d17, d16, #8
+0xd0 0xef 0x30 0x13
+# CHECK: vrsra.s16	d17, d16, #16
+0xe0 0xef 0x30 0x13
+# CHECK: vrsra.s32	d17, d16, #32
+0xc0 0xef 0xb0 0x13
+# CHECK: vrsra.s64	d17, d16, #64
+0xc8 0xff 0x30 0x13
+# CHECK: vrsra.u8	d17, d16, #8
+0xd0 0xff 0x30 0x13
+# CHECK: vrsra.u16	d17, d16, #16
+0xe0 0xff 0x30 0x13
+# CHECK: vrsra.u32	d17, d16, #32
+0xc0 0xff 0xb0 0x13
+# CHECK: vrsra.u64	d17, d16, #64
+0xc8 0xef 0x72 0x03
+# CHECK: vrsra.s8	q8, q9, #8
+0xd0 0xef 0x72 0x03
+# CHECK: vrsra.s16	q8, q9, #16
+0xe0 0xef 0x72 0x03
+# CHECK: vrsra.s32	q8, q9, #32
+0xc0 0xef 0xf2 0x03
+# CHECK: vrsra.s64	q8, q9, #64
+0xc8 0xff 0x72 0x03
+# CHECK: vrsra.u8	q8, q9, #8
+0xd0 0xff 0x72 0x03
+# CHECK: vrsra.u16	q8, q9, #16
+0xe0 0xff 0x72 0x03
+# CHECK: vrsra.u32	q8, q9, #32
+0xc0 0xff 0xf2 0x03
+# CHECK: vrsra.u64	q8, q9, #64
+0xcf 0xff 0x30 0x15
+# CHECK: vsli.8	d17, d16, #7
+0xdf 0xff 0x30 0x15
+# CHECK: vsli.16	d17, d16, #15
+0xff 0xff 0x30 0x15
+# CHECK: vsli.32	d17, d16, #31
+0xff 0xff 0xb0 0x15
+# CHECK: vsli.64	d17, d16, #63
+0xcf 0xff 0x70 0x25
+# CHECK: vsli.8	q9, q8, #7
+0xdf 0xff 0x70 0x25
+# CHECK: vsli.16	q9, q8, #15
+0xff 0xff 0x70 0x25
+# CHECK: vsli.32	q9, q8, #31
+0xff 0xff 0xf0 0x25
+# CHECK: vsli.64	q9, q8, #63
+0xc8 0xff 0x30 0x14
+# CHECK: vsri.8	d17, d16, #8
+0xd0 0xff 0x30 0x14
+# CHECK: vsri.16	d17, d16, #16
+0xe0 0xff 0x30 0x14
+# CHECK: vsri.32	d17, d16, #32
+0xc0 0xff 0xb0 0x14
+# CHECK: vsri.64	d17, d16, #64
+0xc8 0xff 0x70 0x24
+# CHECK: vsri.8	q9, q8, #8
+0xd0 0xff 0x70 0x24
+# CHECK: vsri.16	q9, q8, #16
+0xe0 0xff 0x70 0x24
+# CHECK: vsri.32	q9, q8, #32
+0xc0 0xff 0xf0 0x24
+# CHECK: vsri.64	q9, q8, #64
+0xf1 0xef 0xa0 0x03
+# CHECK: vext.8	d16, d17, d16, #3
+0xf1 0xef 0xa0 0x05
+# CHECK: vext.8	d16, d17, d16, #5
+0xf2 0xef 0xe0 0x03
+# CHECK: vext.8	q8, q9, q8, #3
+0xf2 0xef 0xe0 0x07
+# CHECK: vext.8	q8, q9, q8, #7
+0xf1 0xef 0xa0 0x06
+# CHECK: vext.16	d16, d17, d16, #3
+0xf2 0xef 0xe0 0x0c
+# CHECK: vext.32	q8, q9, q8, #3
+0xf2 0xff 0xa0 0x10
+# CHECK: vtrn.8	d17, d16
+0xf6 0xff 0xa0 0x10
+# CHECK: vtrn.16	d17, d16
+0xfa 0xff 0xa0 0x10
+# CHECK: vtrn.32	d17, d16
+0xf2 0xff 0xe0 0x20
+# CHECK: vtrn.8	q9, q8
+0xf6 0xff 0xe0 0x20
+# CHECK: vtrn.16	q9, q8
+0xfa 0xff 0xe0 0x20
+# CHECK: vtrn.32	q9, q8
+0xf2 0xff 0x20 0x11
+# CHECK: vuzp.8	d17, d16
+0xf6 0xff 0x20 0x11
+# CHECK: vuzp.16	d17, d16
+0xf2 0xff 0x60 0x21
+# CHECK: vuzp.8	q9, q8
+0xf6 0xff 0x60 0x21
+# CHECK: vuzp.16	q9, q8
+0xfa 0xff 0x60 0x21
+# CHECK: vuzp.32	q9, q8
+0xf2 0xff 0xa0 0x11
+# CHECK: vzip.8	d17, d16
+0xf6 0xff 0xa0 0x11
+# CHECK: vzip.16	d17, d16
+0xf2 0xff 0xe0 0x21
+# CHECK: vzip.8	q9, q8
+0xf6 0xff 0xe0 0x21
+# CHECK: vzip.16	q9, q8
+0xfa 0xff 0xe0 0x21
+# CHECK: vzip.32	q9, q8
+
+
+0xf1 0xef 0xa0 0x03
+# CHECK: vext.8	d16, d17, d16, #3
+0xf1 0xef 0xa0 0x05
+# CHECK: vext.8	d16, d17, d16, #5
+0xf2 0xef 0xe0 0x03
+# CHECK: vext.8	q8, q9, q8, #3
+0xf2 0xef 0xe0 0x07
+# CHECK: vext.8	q8, q9, q8, #7
+0xf1 0xef 0xa0 0x06
+# CHECK: vext.16	d16, d17, d16, #3
+0xf2 0xef 0xe0 0x0c
+# CHECK: vext.32	q8, q9, q8, #3
+0xf2 0xff 0xa0 0x10
+# CHECK: vtrn.8	d17, d16
+0xf6 0xff 0xa0 0x10
+# CHECK: vtrn.16	d17, d16
+0xfa 0xff 0xa0 0x10
+# CHECK: vtrn.32	d17, d16
+0xf2 0xff 0xe0 0x20
+# CHECK: vtrn.8	q9, q8
+0xf6 0xff 0xe0 0x20
+# CHECK: vtrn.16	q9, q8
+0xfa 0xff 0xe0 0x20
+# CHECK: vtrn.32	q9, q8
+0xf2 0xff 0x20 0x11
+# CHECK: vuzp.8	d17, d16
+0xf6 0xff 0x20 0x11
+# CHECK: vuzp.16	d17, d16
+0xf2 0xff 0x60 0x21
+# CHECK: vuzp.8	q9, q8
+0xf6 0xff 0x60 0x21
+# CHECK: vuzp.16	q9, q8
+0xfa 0xff 0x60 0x21
+# CHECK: vuzp.32	q9, q8
+0xf2 0xff 0xa0 0x11
+# CHECK: vzip.8	d17, d16
+0xf6 0xff 0xa0 0x11
+# CHECK: vzip.16	d17, d16
+0xf2 0xff 0xe0 0x21
+# CHECK: vzip.8	q9, q8
+0xf6 0xff 0xe0 0x21
+# CHECK: vzip.16	q9, q8
+0xfa 0xff 0xe0 0x21
+# CHECK: vzip.32	q9, q8
+
+0xf1 0xff 0xa0 0x08
+# CHECK: vtbl.8	d16, {d17}, d16
+0xf0 0xff 0xa2 0x09
+# CHECK: vtbl.8	d16, {d16, d17}, d18
+0xf0 0xff 0xa4 0x0a
+# CHECK: vtbl.8	d16, {d16, d17, d18}, d20
+0xf0 0xff 0xa4 0x0b
+# CHECK: vtbl.8	d16, {d16, d17, d18, d19}, d20
+0xf0 0xff 0xe1 0x28
+# CHECK: vtbx.8	d18, {d16}, d17
+0xf0 0xff 0xe2 0x39
+# CHECK: vtbx.8	d19, {d16, d17}, d18
+0xf0 0xff 0xe5 0x4a
+# CHECK: vtbx.8	d20, {d16, d17, d18}, d21
+0xf0 0xff 0xe5 0x4b
+# CHECK: vtbx.8	d20, {d16, d17, d18, d19}, d21
+
+0x60 0xf9 0x1f 0x07
+# CHECK: vld1.8	{d16}, [r0, :64]
+0x60 0xf9 0x4f 0x07
+# CHECK: vld1.16	{d16}, [r0]
+0x60 0xf9 0x8f 0x07
+# CHECK: vld1.32	{d16}, [r0]
+0x60 0xf9 0xcf 0x07
+# CHECK: vld1.64	{d16}, [r0]
+0x60 0xf9 0x1f 0x0a
+# CHECK: vld1.8	{d16, d17}, [r0, :64]
+0x60 0xf9 0x6f 0x0a
+# CHECK: vld1.16	{d16, d17}, [r0, :128]
+0x60 0xf9 0x8f 0x0a
+# CHECK: vld1.32	{d16, d17}, [r0]
+0x60 0xf9 0xcf 0x0a
+# CHECK: vld1.64	{d16, d17}, [r0]
+
+0x60 0xf9 0x1f 0x08
+# CHECK: vld2.8	{d16, d17}, [r0, :64]
+0x60 0xf9 0x6f 0x08
+# CHECK: vld2.16	{d16, d17}, [r0, :128]
+0x60 0xf9 0x8f 0x08
+# CHECK: vld2.32	{d16, d17}, [r0]
+0x60 0xf9 0x1f 0x03
+# CHECK: vld2.8	{d16, d17, d18, d19}, [r0, :64]
+0x60 0xf9 0x6f 0x03
+# CHECK: vld2.16	{d16, d17, d18, d19}, [r0, :128]
+0x60 0xf9 0xbf 0x03
+# CHECK: vld2.32	{d16, d17, d18, d19}, [r0, :256]
+
+0x60 0xf9 0x1f 0x04
+# CHECK: vld3.8	{d16, d17, d18}, [r0, :64]
+0x60 0xf9 0x4f 0x04
+# CHECK: vld3.16	{d16, d17, d18}, [r0]
+0x60 0xf9 0x8f 0x04
+# CHECK: vld3.32	{d16, d17, d18}, [r0]
+0x60 0xf9 0x1d 0x05
+# CHECK: vld3.8	{d16, d18, d20}, [r0, :64]!
+0x60 0xf9 0x1d 0x15
+# CHECK: vld3.8	{d17, d19, d21}, [r0, :64]!
+0x60 0xf9 0x4d 0x05
+# CHECK: vld3.16	{d16, d18, d20}, [r0]!
+0x60 0xf9 0x4d 0x15
+# CHECK: vld3.16	{d17, d19, d21}, [r0]!
+0x60 0xf9 0x8d 0x05
+# CHECK: vld3.32	{d16, d18, d20}, [r0]!
+0x60 0xf9 0x8d 0x15
+# CHECK: vld3.32	{d17, d19, d21}, [r0]!
+
+0x60 0xf9 0x1f 0x00
+# CHECK: vld4.8	{d16, d17, d18, d19}, [r0, :64]
+0x60 0xf9 0x6f 0x00
+# CHECK: vld4.16	{d16, d17, d18, d19}, [r0, :128]
+0x60 0xf9 0xbf 0x00
+# CHECK: vld4.32	{d16, d17, d18, d19}, [r0, :256]
+0x60 0xf9 0x3d 0x01
+# CHECK: vld4.8	{d16, d18, d20, d22}, [r0, :256]!
+0x60 0xf9 0x3d 0x11
+# CHECK: vld4.8	{d17, d19, d21, d23}, [r0, :256]!
+0x60 0xf9 0x4d 0x01
+# CHECK: vld4.16	{d16, d18, d20, d22}, [r0]!
+0x60 0xf9 0x4d 0x11
+# CHECK: vld4.16	{d17, d19, d21, d23}, [r0]!
+0x60 0xf9 0x8d 0x01
+# CHECK: vld4.32	{d16, d18, d20, d22}, [r0]!
+0x60 0xf9 0x8d 0x11
+# CHECK: vld4.32	{d17, d19, d21, d23}, [r0]!
+
+0xe0 0xf9 0x6f 0x00
+# CHECK: vld1.8	{d16[3]}, [r0]
+0xe0 0xf9 0x9f 0x04
+# CHECK: vld1.16	{d16[2]}, [r0, :16]
+0xe0 0xf9 0xbf 0x08
+# CHECK: vld1.32	{d16[1]}, [r0, :32]
+
+0xe0 0xf9 0x3f 0x01
+# CHECK: vld2.8	{d16[1], d17[1]}, [r0, :16]
+0xe0 0xf9 0x5f 0x05
+# CHECK: vld2.16	{d16[1], d17[1]}, [r0, :32]
+0xe0 0xf9 0x8f 0x09
+# CHECK: vld2.32	{d16[1], d17[1]}, [r0]
+0xe0 0xf9 0x6f 0x15
+# CHECK: vld2.16	{d17[1], d19[1]}, [r0]
+0xe0 0xf9 0x5f 0x19
+# CHECK: vld2.32	{d17[0], d19[0]}, [r0, :64]
+
+0xe0 0xf9 0x2f 0x02
+# CHECK: vld3.8	{d16[1], d17[1], d18[1]}, [r0]
+0xe0 0xf9 0x4f 0x06
+# CHECK: vld3.16	{d16[1], d17[1], d18[1]}, [r0]
+0xe0 0xf9 0x8f 0x0a
+# CHECK: vld3.32	{d16[1], d17[1], d18[1]}, [r0]
+0xe0 0xf9 0x6f 0x06
+# CHECK: vld3.16	{d16[1], d18[1], d20[1]}, [r0]
+0xe0 0xf9 0xcf 0x1a
+# CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
+
+0xe0 0xf9 0x3f 0x03
+# CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
+0xe0 0xf9 0x4f 0x07
+# CHECK: vld4.16	{d16[1], d17[1], d18[1], d19[1]}, [r0]
+0xe0 0xf9 0xaf 0x0b
+# CHECK: vld4.32	{d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
+0xe0 0xf9 0x7f 0x07
+# CHECK: vld4.16	{d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
+0xe0 0xf9 0x4f 0x1b
+# CHECK: vld4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+0x40 0xf9 0x1f 0x07
+# CHECK: vst1.8	{d16}, [r0, :64]
+0x40 0xf9 0x4f 0x07
+# CHECK: vst1.16	{d16}, [r0]
+0x40 0xf9 0x8f 0x07
+# CHECK: vst1.32	{d16}, [r0]
+0x40 0xf9 0xcf 0x07
+# CHECK: vst1.64	{d16}, [r0]
+0x40 0xf9 0x1f 0x0a
+# CHECK: vst1.8	{d16, d17}, [r0, :64]
+0x40 0xf9 0x6f 0x0a
+# CHECK: vst1.16	{d16, d17}, [r0, :128]
+0x40 0xf9 0x8f 0x0a
+# CHECK: vst1.32	{d16, d17}, [r0]
+0x40 0xf9 0xcf 0x0a
+# CHECK: vst1.64	{d16, d17}, [r0]
+
+0x40 0xf9 0x1f 0x08
+# CHECK: vst2.8	{d16, d17}, [r0, :64]
+0x40 0xf9 0x6f 0x08
+# CHECK: vst2.16	{d16, d17}, [r0, :128]
+0x40 0xf9 0x8f 0x08
+# CHECK: vst2.32	{d16, d17}, [r0]
+0x40 0xf9 0x1f 0x03
+# CHECK: vst2.8	{d16, d17, d18, d19}, [r0, :64]
+0x40 0xf9 0x6f 0x03
+# CHECK: vst2.16	{d16, d17, d18, d19}, [r0, :128]
+0x40 0xf9 0xbf 0x03
+# CHECK: vst2.32	{d16, d17, d18, d19}, [r0, :256]
+
+0x40 0xf9 0x1f 0x04
+# CHECK: vst3.8	{d16, d17, d18}, [r0, :64]
+0x40 0xf9 0x4f 0x04
+# CHECK: vst3.16	{d16, d17, d18}, [r0]
+0x40 0xf9 0x8f 0x04
+# CHECK: vst3.32	{d16, d17, d18}, [r0]
+0x40 0xf9 0x1d 0x05
+# CHECK: vst3.8	{d16, d18, d20}, [r0, :64]!
+0x40 0xf9 0x1d 0x15
+# CHECK: vst3.8	{d17, d19, d21}, [r0, :64]!
+0x40 0xf9 0x4d 0x05
+# CHECK: vst3.16	{d16, d18, d20}, [r0]!
+0x40 0xf9 0x4d 0x15
+# CHECK: vst3.16	{d17, d19, d21}, [r0]!
+0x40 0xf9 0x8d 0x05
+# CHECK: vst3.32	{d16, d18, d20}, [r0]!
+0x40 0xf9 0x8d 0x15
+# CHECK: vst3.32	{d17, d19, d21}, [r0]!
+
+0x40 0xf9 0x1f 0x00
+# CHECK: vst4.8	{d16, d17, d18, d19}, [r0, :64]
+0x40 0xf9 0x6f 0x00
+# CHECK: vst4.16	{d16, d17, d18, d19}, [r0, :128]
+0x40 0xf9 0x3d 0x01
+# CHECK: vst4.8	{d16, d18, d20, d22}, [r0, :256]!
+0x40 0xf9 0x3d 0x11
+# CHECK: vst4.8	{d17, d19, d21, d23}, [r0, :256]!
+0x40 0xf9 0x4d 0x01
+# CHECK: vst4.16	{d16, d18, d20, d22}, [r0]!
+0x40 0xf9 0x4d 0x11
+# CHECK: vst4.16	{d17, d19, d21, d23}, [r0]!
+0x40 0xf9 0x8d 0x01
+# CHECK: vst4.32	{d16, d18, d20, d22}, [r0]!
+0x40 0xf9 0x8d 0x11
+# CHECK: vst4.32	{d17, d19, d21, d23}, [r0]!
+
+0xc0 0xf9 0x3f 0x01
+# CHECK: vst2.8	{d16[1], d17[1]}, [r0, :16]
+0xc0 0xf9 0x5f 0x05
+# CHECK: vst2.16	{d16[1], d17[1]}, [r0, :32]
+0xc0 0xf9 0x8f 0x09
+# CHECK: vst2.32	{d16[1], d17[1]}, [r0]
+0xc0 0xf9 0x6f 0x15
+# CHECK: vst2.16	{d17[1], d19[1]}, [r0]
+0xc0 0xf9 0x5f 0x19
+# CHECK: vst2.32	{d17[0], d19[0]}, [r0, :64]
+
+0xc0 0xf9 0x2f 0x02
+# CHECK: vst3.8	{d16[1], d17[1], d18[1]}, [r0]
+0xc0 0xf9 0x4f 0x06
+# CHECK: vst3.16	{d16[1], d17[1], d18[1]}, [r0]
+0xc0 0xf9 0x8f 0x0a
+# CHECK: vst3.32	{d16[1], d17[1], d18[1]}, [r0]
+0xc0 0xf9 0xaf 0x16
+# CHECK: vst3.16	{d17[2], d19[2], d21[2]}, [r0]
+0xc0 0xf9 0x4f 0x0a
+# CHECK: vst3.32	{d16[0], d18[0], d20[0]}, [r0]
+
+0xc0 0xf9 0x3f 0x03
+# CHECK: vst4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
+0xc0 0xf9 0x4f 0x07
+# CHECK: vst4.16	{d16[1], d17[1], d18[1], d19[1]}, [r0]
+0xc0 0xf9 0xaf 0x0b
+# CHECK: vst4.32	{d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
+0xc0 0xf9 0xff 0x17
+# CHECK: vst4.16	{d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
+0xc0 0xf9 0x4f 0x1b
+# CHECK: vst4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]



From dpatel at apple.com  Mon Aug 15 18:47:24 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 15 Aug 2011 23:47:24 -0000
Subject: [llvm-commits] [llvm] r137689 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110815234724.D4E202A6C12C@llvm.org>

Author: dpatel
Date: Mon Aug 15 18:47:24 2011
New Revision: 137689

URL: http://llvm.org/viewvc/llvm-project?rev=137689&view=rev
Log:
Refactor.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137689&r1=137688&r2=137689&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Aug 15 18:47:24 2011
@@ -574,6 +574,63 @@
   return;
 }
 
+/// collectInfoFromNamedMDNodes - Collect debug info from named mdnodes such
+/// as llvm.dbg.enum and llvm.dbg.ty
+void DwarfDebug::collectInfoFromNamedMDNodes(Module *M) {
+  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.enum"))
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+      DIType Ty(NMD->getOperand(i));
+      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
+    }
+  
+  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.ty"))
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+      DIType Ty(NMD->getOperand(i));
+      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
+    }
+}
+
+/// collectLegacyDebugInfo - Collect debug info using DebugInfoFinder.
+/// FIXME - Remove this when dragon-egg and llvm-gcc switch to DIBuilder.
+bool DwarfDebug::collectLegacyDebugInfo(Module *M) {
+  DebugInfoFinder DbgFinder;
+  DbgFinder.processModule(*M);
+  
+  bool HasDebugInfo = false;
+  // Scan all the compile-units to see if there are any marked as the main
+  // unit. If not, we do not generate debug info.
+  for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
+         E = DbgFinder.compile_unit_end(); I != E; ++I) {
+    if (DICompileUnit(*I).isMain()) {
+      HasDebugInfo = true;
+      break;
+    }
+  }
+  if (!HasDebugInfo) return false;
+  
+  // Create all the compile unit DIEs.
+  for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
+         E = DbgFinder.compile_unit_end(); I != E; ++I)
+    constructCompileUnit(*I);
+  
+  // Create DIEs for each global variable.
+  for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
+         E = DbgFinder.global_variable_end(); I != E; ++I) {
+    const MDNode *N = *I;
+    if (DIGlobalVariable(N).getVersion() <= LLVMDebugVersion9)
+      constructGlobalVariableDIE(getCompileUnit(N), N);
+  }
+  
+  // Create DIEs for each subprogram.
+  for (DebugInfoFinder::iterator I = DbgFinder.subprogram_begin(),
+         E = DbgFinder.subprogram_end(); I != E; ++I) {
+    const MDNode *N = *I;
+    constructSubprogramDIE(getCompileUnit(N), N);
+  }
+
+  return HasDebugInfo;
+}
+
 /// beginModule - Emit all Dwarf sections that should come prior to the
 /// content. Create global DIEs and emit initial debug info sections.
 /// This is invoked by the target AsmPrinter.
@@ -608,43 +665,10 @@
         constructSubprogramDIE(getCompileUnit(N), N);
       }
     
-  } else {
+  } else if (!collectLegacyDebugInfo(M))
+    return;
 
-    DebugInfoFinder DbgFinder;
-    DbgFinder.processModule(*M);
-    
-    bool HasDebugInfo = false;
-    // Scan all the compile-units to see if there are any marked as the main
-    // unit. If not, we do not generate debug info.
-    for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
-           E = DbgFinder.compile_unit_end(); I != E; ++I) {
-      if (DICompileUnit(*I).isMain()) {
-        HasDebugInfo = true;
-        break;
-      }
-    }
-    if (!HasDebugInfo) return;
-    
-    // Create all the compile unit DIEs.
-    for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
-           E = DbgFinder.compile_unit_end(); I != E; ++I)
-      constructCompileUnit(*I);
-    
-    // Create DIEs for each global variable.
-    for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
-           E = DbgFinder.global_variable_end(); I != E; ++I) {
-      const MDNode *N = *I;
-      if (DIGlobalVariable(N).getVersion() <= LLVMDebugVersion9)
-        constructGlobalVariableDIE(getCompileUnit(N), N);
-    }
-    
-    // Create DIEs for each subprogram.
-    for (DebugInfoFinder::iterator I = DbgFinder.subprogram_begin(),
-           E = DbgFinder.subprogram_end(); I != E; ++I) {
-      const MDNode *N = *I;
-      constructSubprogramDIE(getCompileUnit(N), N);
-    }
-  }
+  collectInfoFromNamedMDNodes(M);
   
   // Tell MMI that we have debug info.
   MMI->setDebugInfoAvailability(true);
@@ -652,19 +676,6 @@
   // Emit initial sections.
   EmitSectionLabels();
 
-  //getOrCreateTypeDIE
-  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.enum"))
-    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
-      DIType Ty(NMD->getOperand(i));
-      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
-    }
-
-  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.ty"))
-    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
-      DIType Ty(NMD->getOperand(i));
-      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
-    }
-
   // Prime section data.
   SectionMap.insert(Asm->getObjFileLowering().getTextSection());
 }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137689&r1=137688&r2=137689&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Aug 15 18:47:24 2011
@@ -468,6 +468,14 @@
   DwarfDebug(AsmPrinter *A, Module *M);
   ~DwarfDebug();
 
+  /// collectInfoFromNamedMDNodes - Collect debug info from named mdnodes such
+  /// as llvm.dbg.enum and llvm.dbg.ty
+  void collectInfoFromNamedMDNodes(Module *M);
+
+  /// collectLegacyDebugInfo - Collect debug info using DebugInfoFinder.
+  /// FIXME - Remove this when dragon-egg and llvm-gcc switch to DIBuilder.
+  bool collectLegacyDebugInfo(Module *M);
+
   /// beginModule - Emit all Dwarf sections that should come prior to the
   /// content.
   void beginModule(Module *M);



From eli.friedman at gmail.com  Mon Aug 15 18:55:52 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 23:55:52 -0000
Subject: [llvm-commits] [llvm] r137690 - in /llvm/trunk:
 lib/Transforms/Utils/PromoteMemoryToRegister.cpp
 test/Transforms/Mem2Reg/atomic.ll
Message-ID: <20110815235552.465272A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 18:55:52 2011
New Revision: 137690

URL: http://llvm.org/viewvc/llvm-project?rev=137690&view=rev
Log:
Add comments and test for atomic load/store and mem2reg.


Added:
    llvm/trunk/test/Transforms/Mem2Reg/atomic.ll
Modified:
    llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp

Modified: llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp?rev=137690&r1=137689&r2=137690&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Mon Aug 15 18:55:52 2011
@@ -86,11 +86,15 @@
        UI != UE; ++UI) {   // Loop over all of the uses of the alloca
     const User *U = *UI;
     if (const LoadInst *LI = dyn_cast<LoadInst>(U)) {
+      // Note that atomic loads can be transformed; atomic semantics do
+      // not have any meaning for a local alloca.
       if (LI->isVolatile())
         return false;
     } else if (const StoreInst *SI = dyn_cast<StoreInst>(U)) {
       if (SI->getOperand(0) == AI)
         return false;   // Don't allow a store OF the AI, only INTO the AI.
+      // Note that atomic stores can be transformed; atomic semantics do
+      // not have any meaning for a local alloca.
       if (SI->isVolatile())
         return false;
     } else if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(U)) {

Added: llvm/trunk/test/Transforms/Mem2Reg/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Mem2Reg/atomic.ll?rev=137690&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/Mem2Reg/atomic.ll (added)
+++ llvm/trunk/test/Transforms/Mem2Reg/atomic.ll Mon Aug 15 18:55:52 2011
@@ -0,0 +1,12 @@
+; RUN: opt -mem2reg < %s -S | FileCheck %s
+
+; mem2reg is allowed with arbitrary atomic operations (although we only support
+; it for atomic load and store at the moment).
+define i32 @test1(i32 %x) {
+; CHECK: @test1
+; CHECK: ret i32 %x
+  %a = alloca i32
+  store atomic i32 %x, i32* %a seq_cst, align 4
+  %r = load atomic i32* %a seq_cst, align 4
+  ret i32 %r
+}



From eli.friedman at gmail.com  Mon Aug 15 18:59:28 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 23:59:28 -0000
Subject: [llvm-commits] [llvm] r137691 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
Message-ID: <20110815235928.32C022A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 18:59:28 2011
New Revision: 137691

URL: http://llvm.org/viewvc/llvm-project?rev=137691&view=rev
Log:
Update SimplifyCFG for atomic operations.

This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?


Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=137691&r1=137690&r2=137691&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Aug 15 18:59:28 2011
@@ -2244,18 +2244,34 @@
   while (UI != BB->begin()) {
     BasicBlock::iterator BBI = UI;
     --BBI;
-    // Do not delete instructions that can have side effects, like calls
-    // (which may never return) and volatile loads and stores.
+    // Do not delete instructions that can have side effects which might cause
+    // the unreachable to not be reachable; specifically, calls and volatile
+    // operations may have this effect.
     if (isa<CallInst>(BBI) && !isa<DbgInfoIntrinsic>(BBI)) break;
-    
-    if (StoreInst *SI = dyn_cast<StoreInst>(BBI))
-      if (SI->isVolatile())
-        break;
-    
-    if (LoadInst *LI = dyn_cast<LoadInst>(BBI))
-      if (LI->isVolatile())
+
+    if (BBI->mayHaveSideEffects()) {
+      if (StoreInst *SI = dyn_cast<StoreInst>(BBI)) {
+        if (SI->isVolatile())
+          break;
+      } else if (LoadInst *LI = dyn_cast<LoadInst>(BBI)) {
+        if (LI->isVolatile())
+          break;
+      } else if (AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(BBI)) {
+        if (RMWI->isVolatile())
+          break;
+      } else if (AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(BBI)) {
+        if (CXI->isVolatile())
+          break;
+      } else if (!isa<FenceInst>(BBI) && !isa<VAArgInst>(BBI) &&
+                 !isa<LandingPadInst>(BBI)) {
         break;
-    
+      }
+      // Note that deleting LandingPad's here is in fact okay, although it
+      // involves a bit of subtle reasoning. If this inst is a LandingPad,
+      // all the predecessors of this block will be the unwind edges of Invokes,
+      // and we can therefore guaranteed this block will be erased.
+    }
+
     // Delete this instruction (any uses are guaranteed to be dead)
     if (!BBI->use_empty())
       BBI->replaceAllUsesWith(UndefValue::get(BBI->getType()));

Modified: llvm/trunk/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll?rev=137691&r1=137690&r2=137691&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll Mon Aug 15 18:59:28 2011
@@ -42,3 +42,46 @@
 ; CHECK: store volatile i32 4, i32* null
 ; CHECK: ret
 }
+
+; Check store before unreachable.
+define void @test4(i1 %C, i32* %P) {
+; CHECK: @test4
+; CHECK: entry:
+; CHECK-NEXT: br i1 %C
+entry:
+  br i1 %C, label %T, label %F
+T:
+  store volatile i32 0, i32* %P
+  unreachable
+F:
+  ret void
+}
+
+; Check cmpxchg before unreachable.
+define void @test5(i1 %C, i32* %P) {
+; CHECK: @test5
+; CHECK: entry:
+; CHECK-NEXT: br i1 %C
+entry:
+  br i1 %C, label %T, label %F
+T:
+  cmpxchg volatile i32* %P, i32 0, i32 1 seq_cst
+  unreachable
+F:
+  ret void
+}
+
+; Check atomicrmw before unreachable.
+define void @test6(i1 %C, i32* %P) {
+; CHECK: @test6
+; CHECK: entry:
+; CHECK-NEXT: br i1 %C
+entry:
+  br i1 %C, label %T, label %F
+T:
+  atomicrmw volatile xchg i32* %P, i32 0 seq_cst
+  unreachable
+F:
+  ret void
+}
+



From wendling at apple.com  Mon Aug 15 19:18:36 2011
From: wendling at apple.com (Bill Wendling)
Date: Mon, 15 Aug 2011 17:18:36 -0700
Subject: [llvm-commits] [llvm] r137691 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
In-Reply-To: <20110815235928.32C022A6C12C@llvm.org>
References: <20110815235928.32C022A6C12C@llvm.org>
Message-ID: <EA68500F-4A9D-44E4-8CAD-704EADBAEFB2@apple.com>

On Aug 15, 2011, at 4:59 PM, Eli Friedman wrote:

> Author: efriedma
> Date: Mon Aug 15 18:59:28 2011
> New Revision: 137691
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137691&view=rev
> Log:
> Update SimplifyCFG for atomic operations.
> 
> This commit includes a mention of the landingpad instruction, but it's not
> changing the behavior around it.  I think the current behavior is correct,
> though.  Bill, can you double-check that?
> 
Hi Eli,

The changes look okay, but I have a question about this comment:

> +      // Note that deleting LandingPad's here is in fact okay, although it
> +      // involves a bit of subtle reasoning. If this inst is a LandingPad,
> +      // all the predecessors of this block will be the unwind edges of Invokes,
> +      // and we can therefore guaranteed this block will be erased.

I'm not sure what you're trying to get at here. If we have a landing pad instruction followed by an unreachable, that landing pad would be a "terminate" landing pad. I.e., we expect the personality function to call the 'terminate' function. In fact, I initially wanted something like this:

bb1:
  invoke ...
     to label %normal unwind to %unwind

unwind:
  %val = landingpad { i8*, i32 }, personality ...
            terminate
  unreachable

In which case we would not be able to delete the landingpad instruction. I would still like to implement something akin to this, as it's a useful optimization.

My point is that removing landingpad instructions is very tricky, and should be done only if all of the invokes unwinding to the landing pad have been removed or converted into 'call's. :-)

-bw


From eli.friedman at gmail.com  Mon Aug 15 19:20:11 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 00:20:11 -0000
Subject: [llvm-commits] [llvm] r137693 - in /llvm/trunk/lib/Transforms:
 IPO/GlobalOpt.cpp Utils/SimplifyCFG.cpp
Message-ID: <20110816002011.7B1672A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 19:20:11 2011
New Revision: 137693

URL: http://llvm.org/viewvc/llvm-project?rev=137693&view=rev
Log:
Minor comment fixes.


Modified:
    llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=137693&r1=137692&r2=137693&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Mon Aug 15 19:20:11 2011
@@ -195,12 +195,14 @@
       }
       if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
         GS.isLoaded = true;
-        if (!LI->isSimple()) return true;  // Don't hack on volatile loads.
+        // Don't hack on volatile/atomic loads.
+        if (!LI->isSimple()) return true;
       } else if (const StoreInst *SI = dyn_cast<StoreInst>(I)) {
         // Don't allow a store OF the address, only stores TO the address.
         if (SI->getOperand(0) == V) return true;
 
-        if (!SI->isSimple()) return true;  // Don't hack on volatile stores.
+        // Don't hack on volatile/atomic stores.
+        if (!SI->isSimple()) return true;
 
         // If this is a direct store to the global (i.e., the global is a scalar
         // value, not an aggregate), keep more specific information about
@@ -2333,7 +2335,7 @@
     Constant *InstResult = 0;
 
     if (StoreInst *SI = dyn_cast<StoreInst>(CurInst)) {
-      if (!SI->isSimple()) return false;  // no volatile accesses.
+      if (!SI->isSimple()) return false;  // no volatile/atomic accesses.
       Constant *Ptr = getVal(Values, SI->getOperand(1));
       if (!isSimpleEnoughPointerToCommit(Ptr))
         // If this is too complex for us to commit, reject it.
@@ -2410,7 +2412,7 @@
         ConstantExpr::getGetElementPtr(P, GEPOps,
                                        cast<GEPOperator>(GEP)->isInBounds());
     } else if (LoadInst *LI = dyn_cast<LoadInst>(CurInst)) {
-      if (!LI->isSimple()) return false;  // no volatile accesses.
+      if (!LI->isSimple()) return false;  // no volatile/atomic accesses.
       InstResult = ComputeLoadResult(getVal(Values, LI->getOperand(0)),
                                      MutatedMemory);
       if (InstResult == 0) return false; // Could not evaluate load.

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=137693&r1=137692&r2=137693&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Aug 15 19:20:11 2011
@@ -2269,7 +2269,7 @@
       // Note that deleting LandingPad's here is in fact okay, although it
       // involves a bit of subtle reasoning. If this inst is a LandingPad,
       // all the predecessors of this block will be the unwind edges of Invokes,
-      // and we can therefore guaranteed this block will be erased.
+      // and we can therefore guarantee this block will be erased.
     }
 
     // Delete this instruction (any uses are guaranteed to be dead)



From eli.friedman at gmail.com  Mon Aug 15 19:25:00 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 15 Aug 2011 17:25:00 -0700
Subject: [llvm-commits] [llvm] r137691 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
In-Reply-To: <EA68500F-4A9D-44E4-8CAD-704EADBAEFB2@apple.com>
References: <20110815235928.32C022A6C12C@llvm.org>
	<EA68500F-4A9D-44E4-8CAD-704EADBAEFB2@apple.com>
Message-ID: <CAJdarcHa0ypWKRCnJOL4JeHYTe9oygi8ue55+9xAv65_62jWXQ@mail.gmail.com>

On Mon, Aug 15, 2011 at 5:18 PM, Bill Wendling <wendling at apple.com> wrote:
> On Aug 15, 2011, at 4:59 PM, Eli Friedman wrote:
>
>> Author: efriedma
>> Date: Mon Aug 15 18:59:28 2011
>> New Revision: 137691
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=137691&view=rev
>> Log:
>> Update SimplifyCFG for atomic operations.
>>
>> This commit includes a mention of the landingpad instruction, but it's not
>> changing the behavior around it. ?I think the current behavior is correct,
>> though. ?Bill, can you double-check that?
>>
> Hi Eli,
>
> The changes look okay, but I have a question about this comment:
>
>> + ? ? ?// Note that deleting LandingPad's here is in fact okay, although it
>> + ? ? ?// involves a bit of subtle reasoning. If this inst is a LandingPad,
>> + ? ? ?// all the predecessors of this block will be the unwind edges of Invokes,
>> + ? ? ?// and we can therefore guaranteed this block will be erased.
>
> I'm not sure what you're trying to get at here. If we have a landing pad instruction followed by an unreachable, that landing pad would be a "terminate" landing pad. I.e., we expect the personality function to call the 'terminate' function. In fact, I initially wanted something like this:
>
> bb1:
> ?invoke ...
> ? ? to label %normal unwind to %unwind
>
> unwind:
> ?%val = landingpad { i8*, i32 }, personality ...
> ? ? ? ? ? ?terminate
> ?unreachable
>
> In which case we would not be able to delete the landingpad instruction. I would still like to implement something akin to this, as it's a useful optimization.
>
> My point is that removing landingpad instructions is very tricky, and should be done only if all of the invokes unwinding to the landing pad have been removed or converted into 'call's. :-)

What the code currently does is if there is a landingpad followed by
an unreachable, it will remove the block and change all invokes
referring to it into calls.  From what you're saying, it sounds like
that is correct, but we won't want to do it once we have terminate?

-Eli


From wendling at apple.com  Mon Aug 15 19:34:44 2011
From: wendling at apple.com (Bill Wendling)
Date: Mon, 15 Aug 2011 17:34:44 -0700
Subject: [llvm-commits] [llvm] r137691 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
In-Reply-To: <CAJdarcHa0ypWKRCnJOL4JeHYTe9oygi8ue55+9xAv65_62jWXQ@mail.gmail.com>
References: <20110815235928.32C022A6C12C@llvm.org>
	<EA68500F-4A9D-44E4-8CAD-704EADBAEFB2@apple.com>
	<CAJdarcHa0ypWKRCnJOL4JeHYTe9oygi8ue55+9xAv65_62jWXQ@mail.gmail.com>
Message-ID: <14E61A8D-8607-45BD-9699-79B4F172875D@apple.com>

On Aug 15, 2011, at 5:25 PM, Eli Friedman wrote:

>> My point is that removing landingpad instructions is very tricky, and should be done only if all of the invokes unwinding to the landing pad have been removed or converted into 'call's. :-)
> 
> What the code currently does is if there is a landingpad followed by
> an unreachable, it will remove the block and change all invokes
> referring to it into calls.  From what you're saying, it sounds like
> that is correct, but we won't want to do it once we have terminate?
> 
I would rather that it be kept around and that the only time we delete the landingpad instruction and block is when all invokes that unwind to it are removed or changed into calls. The current way, it's removing the landing pad block and then changing the invokes to calls.

-bw


From eli.friedman at gmail.com  Mon Aug 15 19:41:37 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 00:41:37 -0000
Subject: [llvm-commits] [llvm] r137694 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20110816004137.4EFD92A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 19:41:37 2011
New Revision: 137694

URL: http://llvm.org/viewvc/llvm-project?rev=137694&view=rev
Log:
After talking with Bill, it seems like the LandingPad handling here is likely
to be wrong (or at least somewhat suspect).  Leave a FIXME for Bill.



Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=137694&r1=137693&r2=137694&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Aug 15 19:41:37 2011
@@ -2266,10 +2266,7 @@
                  !isa<LandingPadInst>(BBI)) {
         break;
       }
-      // Note that deleting LandingPad's here is in fact okay, although it
-      // involves a bit of subtle reasoning. If this inst is a LandingPad,
-      // all the predecessors of this block will be the unwind edges of Invokes,
-      // and we can therefore guarantee this block will be erased.
+      // FIXME: Handling of LandingPadInst (landingpad) is suspicious.
     }
 
     // Delete this instruction (any uses are guaranteed to be dead)



From chandlerc at google.com  Mon Aug 15 20:13:14 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Mon, 15 Aug 2011 18:13:14 -0700
Subject: [llvm-commits] [llvm] r137650 - in /llvm/trunk/lib/Analysis:
 AliasAnalysis.cpp LoopDependenceAnalysis.cpp MemDepPrinter.cpp
 MemoryDependenceAnalysis.cpp
In-Reply-To: <20110815205419.404FF2A6C12C@llvm.org>
References: <20110815205419.404FF2A6C12C@llvm.org>
Message-ID: <CAGCO0KgBkf7E-YmOK8=4C3L9Pq1cdRZCnkYbgmTY6LG0XiM7KQ@mail.gmail.com>

On Mon, Aug 15, 2011 at 1:54 PM, Eli Friedman <eli.friedman at gmail.com>wrote:

> Misc analysis passes that need to be aware of atomic load/store.


Another patch in need of test case love.
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From echristo at apple.com  Mon Aug 15 20:17:17 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 16 Aug 2011 01:17:17 -0000
Subject: [llvm-commits] [llvm] r137700 -
	/llvm/trunk/test/Transforms/InstCombine/devirt.ll
Message-ID: <20110816011717.8800C2A6C12C@llvm.org>

Author: echristo
Date: Mon Aug 15 20:17:17 2011
New Revision: 137700

URL: http://llvm.org/viewvc/llvm-project?rev=137700&view=rev
Log:
Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and
FileCheckize. It is more properly an optimizer test.

Added:
    llvm/trunk/test/Transforms/InstCombine/devirt.ll

Added: llvm/trunk/test/Transforms/InstCombine/devirt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/devirt.ll?rev=137700&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/devirt.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/devirt.ll Mon Aug 15 20:17:17 2011
@@ -0,0 +1,39 @@
+; RUN: opt -instcombine -S -o - %s | FileCheck %s
+
+; CHECK-NOT: getelementptr
+; CHECK-NOT: ptrtoint
+; CHECK: bitcast i8*
+%struct.S = type { i32 (...)** }
+
+ at _ZL1p = internal constant { i64, i64 } { i64 1, i64 0 }, align 8
+
+define void @_Z1g1S(%struct.S* %s) nounwind {
+entry:
+  %tmp = load { i64, i64 }* @_ZL1p, align 8
+  %memptr.adj = extractvalue { i64, i64 } %tmp, 1
+  %0 = bitcast %struct.S* %s to i8*
+  %1 = getelementptr inbounds i8* %0, i64 %memptr.adj
+  %this.adjusted = bitcast i8* %1 to %struct.S*
+  %memptr.ptr = extractvalue { i64, i64 } %tmp, 0
+  %2 = and i64 %memptr.ptr, 1
+  %memptr.isvirtual = icmp ne i64 %2, 0
+  br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
+
+memptr.virtual:                                   ; preds = %entry
+  %3 = bitcast %struct.S* %this.adjusted to i8**
+  %memptr.vtable = load i8** %3
+  %4 = sub i64 %memptr.ptr, 1
+  %5 = getelementptr i8* %memptr.vtable, i64 %4
+  %6 = bitcast i8* %5 to void (%struct.S*)**
+  %memptr.virtualfn = load void (%struct.S*)** %6
+  br label %memptr.end
+
+memptr.nonvirtual:                                ; preds = %entry
+  %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to void (%struct.S*)*
+  br label %memptr.end
+
+memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
+  %7 = phi void (%struct.S*)* [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
+  call void %7(%struct.S* %this.adjusted)
+  ret void
+}



From eli.friedman at gmail.com  Mon Aug 15 20:28:22 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 01:28:22 -0000
Subject: [llvm-commits] [llvm] r137702 - in /llvm/trunk:
 lib/Transforms/IPO/FunctionAttrs.cpp
 test/Transforms/FunctionAttrs/atomic.ll
Message-ID: <20110816012822.8A48D2A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 20:28:22 2011
New Revision: 137702

URL: http://llvm.org/viewvc/llvm-project?rev=137702&view=rev
Log:
Revert a bit of r137667; the logic in question can safely handle atomic load/store.


Added:
    llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll
Modified:
    llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp

Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=137702&r1=137701&r2=137702&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Aug 15 20:28:22 2011
@@ -163,15 +163,15 @@
           ReadsMemory = true;
         continue;
       } else if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
-        // Ignore non-volatile loads from local memory.
-        if (LI->isUnordered()) {
+        // Ignore non-volatile loads from local memory. (Atomic is okay here.)
+        if (!LI->isVolatile()) {
           AliasAnalysis::Location Loc = AA->getLocation(LI);
           if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true))
             continue;
         }
       } else if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
-        // Ignore non-volatile stores to local memory.
-        if (SI->isUnordered()) {
+        // Ignore non-volatile stores to local memory. (Atomic is okay here.)
+        if (!SI->isVolatile()) {
           AliasAnalysis::Location Loc = AA->getLocation(SI);
           if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true))
             continue;

Added: llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll?rev=137702&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll (added)
+++ llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll Mon Aug 15 20:28:22 2011
@@ -0,0 +1,21 @@
+; RUN: opt -basicaa -functionattrs -S < %s | FileCheck %s
+
+; Atomic load/store to local doesn't affect whether a function is
+; readnone/readonly.
+define i32 @test1(i32 %x) uwtable ssp {
+; CHECK: define i32 @test1(i32 %x) uwtable readnone ssp {
+entry:
+  %x.addr = alloca i32, align 4
+  store atomic i32 %x, i32* %x.addr seq_cst, align 4
+  %r = load atomic i32* %x.addr seq_cst, align 4
+  ret i32 %r
+}
+
+; A function with an Acquire load is not readonly.
+define i32 @test2(i32* %x) uwtable ssp {
+; CHECK: define i32 @test2(i32 %x) uwtable ssp {
+entry:
+  %r = load atomic i32* %x seq_cst, align 4
+  ret i32 %r
+}
+



From eli.friedman at gmail.com  Mon Aug 15 20:42:57 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 01:42:57 -0000
Subject: [llvm-commits] [llvm] r137703 -
	/llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll
Message-ID: <20110816014257.23FA62A6C12C@llvm.org>

Author: efriedma
Date: Mon Aug 15 20:42:56 2011
New Revision: 137703

URL: http://llvm.org/viewvc/llvm-project?rev=137703&view=rev
Log:
Fix test.


Modified:
    llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll

Modified: llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll?rev=137703&r1=137702&r2=137703&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll (original)
+++ llvm/trunk/test/Transforms/FunctionAttrs/atomic.ll Mon Aug 15 20:42:56 2011
@@ -13,7 +13,7 @@
 
 ; A function with an Acquire load is not readonly.
 define i32 @test2(i32* %x) uwtable ssp {
-; CHECK: define i32 @test2(i32 %x) uwtable ssp {
+; CHECK: define i32 @test2(i32* nocapture %x) uwtable ssp {
 entry:
   %r = load atomic i32* %x seq_cst, align 4
   ret i32 %r



From ahatanak at gmail.com  Mon Aug 15 21:15:03 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 16 Aug 2011 02:15:03 -0000
Subject: [llvm-commits] [llvm] r137706 - in /llvm/trunk/lib/Target/Mips:
 MipsMCInstLower.cpp MipsMCInstLower.h
Message-ID: <20110816021503.A55E52A6C12C@llvm.org>

Author: ahatanak
Date: Mon Aug 15 21:15:03 2011
New Revision: 137706

URL: http://llvm.org/viewvc/llvm-project?rev=137706&view=rev
Log:
Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.  

Modified:
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.h

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=137706&r1=137705&r2=137706&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Mon Aug 15 21:15:03 2011
@@ -29,10 +29,10 @@
   : Ctx(mf.getContext()), Mang(mang), AsmPrinter(asmprinter) {}
 
 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
-                                              MachineOperandType MOTy) const {
+                                              MachineOperandType MOTy,
+                                              unsigned Offset) const {
   MipsMCSymbolRefExpr::VariantKind Kind;
   const MCSymbol *Symbol;
-  int Offset = 0;
 
   switch(MO.getTargetFlags()) {
   default:                  assert(0 && "Invalid target flag!");
@@ -72,7 +72,7 @@
     case MachineOperand::MO_ConstantPoolIndex:
       Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
       if (MO.getOffset())
-        Offset = MO.getOffset();  
+        Offset += MO.getOffset();  
       break;
 
     default:
@@ -109,7 +109,7 @@
     case MachineOperand::MO_JumpTableIndex:
     case MachineOperand::MO_ConstantPoolIndex:
     case MachineOperand::MO_BlockAddress:
-      MCOp = LowerSymbolOperand(MO, MOTy);
+      MCOp = LowerSymbolOperand(MO, MOTy, 0);
       break;
     }
     

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=137706&r1=137705&r2=137706&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Mon Aug 15 21:15:03 2011
@@ -36,7 +36,7 @@
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
-                               MachineOperandType MOTy) const;
+                               MachineOperandType MOTy, unsigned Offset) const;
 };
 }
 



From ahatanak at gmail.com  Mon Aug 15 21:21:03 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 16 Aug 2011 02:21:03 -0000
Subject: [llvm-commits] [llvm] r137707 - in /llvm/trunk/lib/Target/Mips:
 MipsMCInstLower.cpp MipsMCInstLower.h
Message-ID: <20110816022103.EE3782A6C12C@llvm.org>

Author: ahatanak
Date: Mon Aug 15 21:21:03 2011
New Revision: 137707

URL: http://llvm.org/viewvc/llvm-project?rev=137707&view=rev
Log:
Define function MipsMCInstLower::LowerOperand.  

Modified:
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.h

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=137707&r1=137706&r2=137707&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Mon Aug 15 21:21:03 2011
@@ -83,36 +83,39 @@
                                                            Ctx));
 }
 
+MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const {
+  MachineOperandType MOTy = MO.getType();
+  
+  switch (MOTy) {
+  default:
+    assert(0 && "unknown operand type");
+    break;
+  case MachineOperand::MO_Register:
+    // Ignore all implicit register operands.
+    if (MO.isImplicit()) break;
+    return MCOperand::CreateReg(MO.getReg());
+  case MachineOperand::MO_Immediate:
+    return MCOperand::CreateImm(MO.getImm());
+  case MachineOperand::MO_MachineBasicBlock:
+  case MachineOperand::MO_GlobalAddress:
+  case MachineOperand::MO_ExternalSymbol:
+  case MachineOperand::MO_JumpTableIndex:
+  case MachineOperand::MO_ConstantPoolIndex:
+  case MachineOperand::MO_BlockAddress:
+    return LowerSymbolOperand(MO, MOTy, 0);
+ }
+
+  return MCOperand();
+}
+
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
   
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    MCOperand MCOp;
-    MachineOperandType MOTy = MO.getType();
+    MCOperand MCOp = LowerOperand(MO);
 
-    switch (MOTy) {
-    default:
-      MI->dump();
-      llvm_unreachable("unknown operand type");
-    case MachineOperand::MO_Register:
-      // Ignore all implicit register operands.
-      if (MO.isImplicit()) continue;
-      MCOp = MCOperand::CreateReg(MO.getReg());
-      break;
-    case MachineOperand::MO_Immediate:
-      MCOp = MCOperand::CreateImm(MO.getImm());
-      break;
-    case MachineOperand::MO_MachineBasicBlock:
-    case MachineOperand::MO_GlobalAddress:
-    case MachineOperand::MO_ExternalSymbol:
-    case MachineOperand::MO_JumpTableIndex:
-    case MachineOperand::MO_ConstantPoolIndex:
-    case MachineOperand::MO_BlockAddress:
-      MCOp = LowerSymbolOperand(MO, MOTy, 0);
-      break;
-    }
-    
-    OutMI.addOperand(MCOp);
+    if (MCOp.isValid())
+      OutMI.addOperand(MCOp);
   }
 }

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=137707&r1=137706&r2=137707&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Mon Aug 15 21:21:03 2011
@@ -37,6 +37,7 @@
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
                                MachineOperandType MOTy, unsigned Offset) const;
+  MCOperand LowerOperand(const MachineOperand& MO) const;
 };
 }
 



From ahatanak at gmail.com  Mon Aug 15 22:51:51 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 16 Aug 2011 03:51:51 -0000
Subject: [llvm-commits] [llvm] r137711 - in /llvm/trunk:
 lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp
 lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsInstrInfo.cpp
 lib/Target/Mips/MipsMCInstLower.cpp lib/Target/Mips/MipsMCInstLower.h
 test/CodeGen/Mips/select.ll
Message-ID: <20110816035151.658D12A6C12C@llvm.org>

Author: ahatanak
Date: Mon Aug 15 22:51:51 2011
New Revision: 137711

URL: http://llvm.org/viewvc/llvm-project?rev=137711&view=rev
Log:
Fix handling of double precision loads and stores when Mips1 is targeted.  

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.


Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
    llvm/trunk/test/CodeGen/Mips/select.ll

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon Aug 15 22:51:51 2011
@@ -18,6 +18,7 @@
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
 #include "MipsMCInstLower.h"
+#include "MipsMCSymbolRefExpr.h"
 #include "InstPrinter/MipsInstPrinter.h"
 #include "llvm/BasicBlock.h"
 #include "llvm/Instructions.h"
@@ -36,6 +37,7 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/raw_ostream.h"
@@ -53,9 +55,26 @@
   }
 
   MipsMCInstLower MCInstLowering(Mang, *MF, *this);
+  unsigned Opc = MI->getOpcode();
+
+  // If target is Mips1, expand double precision load/store to two single
+  // precision loads/stores (and delay slot if MI is a load).
+  if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
+    SmallVector<MCInst, 4> MCInsts;
+    const unsigned* SubReg = 
+      TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
+    MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
+                                          Subtarget->isLittle(), SubReg);
+    
+    for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
+         I != MCInsts.end(); ++I)
+      OutStreamer.EmitInstruction(*I);
+
+    return;
+  }
+
   MCInst TmpInst0;
   MCInstLowering.Lower(MI, TmpInst0);
-  unsigned Opc = MI->getOpcode();
   
   // Convert aligned loads/stores to their unaligned counterparts.
   // FIXME: expand other unaligned memory accesses too.

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Aug 15 22:51:51 2011
@@ -86,9 +86,6 @@
   // Complex Pattern.
   bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
 
-  SDNode *SelectLoadFp64(SDNode *N);
-  SDNode *SelectStoreFp64(SDNode *N);
-
   // getI32Imm - Return a target constant with the specified
   // value, of type i32.
   inline SDValue getI32Imm(unsigned Imm) {
@@ -184,130 +181,6 @@
   return true;
 }
 
-SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
-  MVT::SimpleValueType NVT =
-    N->getValueType(0).getSimpleVT().SimpleTy;
-
-  if (!Subtarget.isMips1() || NVT != MVT::f64)
-    return NULL;
-
-  LoadSDNode *LN = cast<LoadSDNode>(N);
-  if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
-      LN->getAddressingMode() != ISD::UNINDEXED)
-    return NULL;
-
-  SDValue Chain = N->getOperand(0);
-  SDValue N1 = N->getOperand(1);
-  SDValue Offset0, Offset1, Base;
-
-  if (!SelectAddr(N1, Base, Offset0) ||
-      N1.getValueType() != MVT::i32)
-    return NULL;
-
-  MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
-  MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
-  DebugLoc dl = N->getDebugLoc();
-
-  // The second load should start after for 4 bytes.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
-    Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
-  else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
-    Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
-                                            MVT::i32,
-                                            CP->getAlignment(),
-                                            CP->getOffset()+4,
-                                            CP->getTargetFlags());
-  else
-    return NULL;
-
-  // Choose the offsets depending on the endianess
-  if (TM.getTargetData()->isBigEndian())
-    std::swap(Offset0, Offset1);
-
-  // Instead of:
-  //    ldc $f0, X($3)
-  // Generate:
-  //    lwc $f0, X($3)
-  //    lwc $f1, X+4($3)
-  SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
-                                       MVT::Other, Base, Offset0, Chain);
-  SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
-                                                 dl, NVT), 0);
-  SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
-                            MVT::f64, Undef, SDValue(LD0, 0));
-
-  SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
-                                       MVT::Other, Base, Offset1, SDValue(LD0, 1));
-  SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
-                            MVT::f64, I0, SDValue(LD1, 0));
-
-  ReplaceUses(SDValue(N, 0), I1);
-  ReplaceUses(SDValue(N, 1), Chain);
-  cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
-  cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
-  return I1.getNode();
-}
-
-SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
-
-  if (!Subtarget.isMips1() ||
-      N->getOperand(1).getValueType() != MVT::f64)
-    return NULL;
-
-  SDValue Chain = N->getOperand(0);
-
-  StoreSDNode *SN = cast<StoreSDNode>(N);
-  if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
-    return NULL;
-
-  SDValue N1 = N->getOperand(1);
-  SDValue N2 = N->getOperand(2);
-  SDValue Offset0, Offset1, Base;
-
-  if (!SelectAddr(N2, Base, Offset0) ||
-      N1.getValueType() != MVT::f64 ||
-      N2.getValueType() != MVT::i32)
-    return NULL;
-
-  MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
-  MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
-  DebugLoc dl = N->getDebugLoc();
-
-  // Get the even and odd part from the f64 register
-  SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
-                                                 dl, MVT::f32, N1);
-  SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
-                                                 dl, MVT::f32, N1);
-
-  // The second store should start after for 4 bytes.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
-    Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
-  else
-    return NULL;
-
-  // Choose the offsets depending on the endianess
-  if (TM.getTargetData()->isBigEndian())
-    std::swap(Offset0, Offset1);
-
-  // Instead of:
-  //    sdc $f0, X($3)
-  // Generate:
-  //    swc $f0, X($3)
-  //    swc $f1, X+4($3)
-  SDValue Ops0[] = { FPEven, Base, Offset0, Chain };
-  Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
-                                       MVT::Other, Ops0, 4), 0);
-  cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
-
-  SDValue Ops1[] = { FPOdd, Base, Offset1, Chain };
-  Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
-                                       MVT::Other, Ops1, 4), 0);
-  cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
-
-  ReplaceUses(SDValue(N, 0), Chain);
-  return Chain.getNode();
-}
-
 /// Select instructions not customized! Used for
 /// expanded, promoted and normal instructions
 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
@@ -423,18 +296,6 @@
       break;
     }
 
-    case ISD::LOAD:
-      if (SDNode *ResNode = SelectLoadFp64(Node))
-        return ResNode;
-      // Other cases are autogenerated.
-      break;
-
-    case ISD::STORE:
-      if (SDNode *ResNode = SelectStoreFp64(Node))
-        return ResNode;
-      // Other cases are autogenerated.
-      break;
-
     case MipsISD::ThreadPointer: {
       unsigned SrcReg = Mips::HWR29;
       unsigned DestReg = Mips::V1;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Aug 15 22:51:51 2011
@@ -190,7 +190,7 @@
                    "mov.d\t$fd, $fs", []>;
 
 /// Floating Point Memory Instructions
-let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
+let Predicates = [IsNotSingleFloat] in {
   def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
                  "ldc1\t$ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Aug 15 22:51:51 2011
@@ -175,21 +175,9 @@
     BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
                                         .addFrameIndex(FI).addImm(0);
   else if (RC == Mips::AFGR64RegisterClass) {
-    if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
-      BuildMI(MBB, I, DL, get(Mips::SDC1))
-        .addReg(SrcReg, getKillRegState(isKill))
-        .addFrameIndex(FI).addImm(0);
-    } else {
-      const TargetRegisterInfo *TRI =
-        MBB.getParent()->getTarget().getRegisterInfo();
-      const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
-      BuildMI(MBB, I, DL, get(Mips::SWC1))
-        .addReg(SubSet[0], getKillRegState(isKill))
-        .addFrameIndex(FI).addImm(0);
-      BuildMI(MBB, I, DL, get(Mips::SWC1))
-        .addReg(SubSet[1], getKillRegState(isKill))
-        .addFrameIndex(FI).addImm(4);
-    }
+    BuildMI(MBB, I, DL, get(Mips::SDC1))
+      .addReg(SrcReg, getKillRegState(isKill))
+      .addFrameIndex(FI).addImm(0);
   } else
     llvm_unreachable("Register class not handled!");
 }
@@ -208,17 +196,7 @@
   else if (RC == Mips::FGR32RegisterClass)
     BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0);
   else if (RC == Mips::AFGR64RegisterClass) {
-    if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
-      BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0);
-    } else {
-      const TargetRegisterInfo *TRI =
-        MBB.getParent()->getTarget().getRegisterInfo();
-      const unsigned *SubSet = TRI->getSubRegisters(DestReg);
-      BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
-        .addFrameIndex(FI).addImm(0);
-      BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
-        .addFrameIndex(FI).addImm(4);
-    }
+    BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0);
   } else
     llvm_unreachable("Register class not handled!");
 }

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Mon Aug 15 22:51:51 2011
@@ -83,6 +83,50 @@
                                                            Ctx));
 }
 
+// If target is Mips1, expand double precision load/store to two single
+// precision loads/stores.
+// 
+//  ldc1 $f0, lo($CPI0_0)($5) gets expanded to the following two instructions:
+//  (little endian)
+//   lwc1 $f0, lo($CPI0_0)($5) and
+//   lwc1 $f1, lo($CPI0_0+4)($5)
+//  (big endian)
+//   lwc1 $f1, lo($CPI0_0)($5) and
+//   lwc1 $f0, lo($CPI0_0+4)($5)
+void MipsMCInstLower::LowerMips1F64LoadStore(const MachineInstr *MI,
+                                             unsigned Opc,
+                                             SmallVector<MCInst, 4>& MCInsts,
+                                             bool isLittle,
+                                             const unsigned *SubReg) const {
+  MCInst InstLo, InstHi, DelaySlot;
+  unsigned SingleOpc = (Opc == Mips::LDC1 ? Mips::LWC1 : Mips::SWC1);
+  unsigned RegLo = isLittle ? *SubReg : *(SubReg + 1);
+  unsigned RegHi = isLittle ? *(SubReg + 1) : *SubReg;
+  const MachineOperand &MO1 = MI->getOperand(1);
+  const MachineOperand &MO2 = MI->getOperand(2);
+
+  InstLo.setOpcode(SingleOpc);
+  InstLo.addOperand(MCOperand::CreateReg(RegLo));
+  InstLo.addOperand(LowerOperand(MO1));
+  InstLo.addOperand(LowerOperand(MO2));
+  MCInsts.push_back(InstLo);
+
+  InstHi.setOpcode(SingleOpc);
+  InstHi.addOperand(MCOperand::CreateReg(RegHi));
+  InstHi.addOperand(LowerOperand(MO1));
+  if (MO2.isImm())// The offset of addr operand is an immediate: e.g. 0($sp)
+    InstHi.addOperand(MCOperand::CreateImm(MO2.getImm() + 4));
+  else// Otherwise, the offset must be a symbol: e.g. lo($CPI0_0)($5)
+    InstHi.addOperand(LowerSymbolOperand(MO2, MO2.getType(), 4));
+  MCInsts.push_back(InstHi);
+
+  // Need to insert a NOP in LWC1's delay slot.
+  if (SingleOpc == Mips::LWC1) {
+    DelaySlot.setOpcode(Mips::NOP);
+    MCInsts.push_back(DelaySlot);
+  }
+}
+
 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const {
   MachineOperandType MOTy = MO.getType();
   

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Mon Aug 15 22:51:51 2011
@@ -9,6 +9,7 @@
 
 #ifndef MIPSMCINSTLOWER_H
 #define MIPSMCINSTLOWER_H
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Support/Compiler.h"
 
@@ -34,6 +35,9 @@
   MipsMCInstLower(Mangler *mang, const MachineFunction &MF,
                   MipsAsmPrinter &asmprinter);  
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
+  void LowerMips1F64LoadStore(const MachineInstr *MI, unsigned Opc,
+                              SmallVector<MCInst, 4>& MCInsts,
+                              bool isLittle, const unsigned *SubReg) const;
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
                                MachineOperandType MOTy, unsigned Offset) const;

Modified: llvm/trunk/test/CodeGen/Mips/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=137711&r1=137710&r2=137711&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/select.ll Mon Aug 15 22:51:51 2011
@@ -25,7 +25,7 @@
 define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
 entry:
 ; CHECK-MIPS32R2: movn.d
-; CHECK-MIPS1: beq
+; CHECK-MIPS1: bne
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, double %f0, double %f1
   ret double %cond



From isanbard at gmail.com  Mon Aug 15 23:52:55 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 04:52:55 -0000
Subject: [llvm-commits] [llvm] r137712 - in /llvm/trunk/lib:
 Analysis/ScalarEvolutionExpander.cpp
 Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
 Transforms/Instrumentation/GCOVProfiling.cpp
Message-ID: <20110816045255.8F40D2A6C12C@llvm.org>

Author: void
Date: Mon Aug 15 23:52:55 2011
New Revision: 137712

URL: http://llvm.org/viewvc/llvm-project?rev=137712&view=rev
Log:
A few places where we want to skip the landingpad instruction for insertion.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=137712&r1=137711&r2=137712&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Aug 15 23:52:55 2011
@@ -1323,8 +1323,11 @@
       // If the SCEV is computable at this level, insert it into the header
       // after the PHIs (and after any other instructions that we've inserted
       // there) so that it is guaranteed to dominate any user inside the loop.
-      if (L && SE.hasComputableLoopEvolution(S, L) && !PostIncLoops.count(L))
+      if (L && SE.hasComputableLoopEvolution(S, L) && !PostIncLoops.count(L)) {
         InsertPt = L->getHeader()->getFirstNonPHI();
+        if (isa<LandingPadInst>(InsertPt))
+          InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
+      }
       while (isInsertedInstruction(InsertPt) || isa<DbgInfoIntrinsic>(InsertPt))
         InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
       break;

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=137712&r1=137711&r2=137712&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Aug 15 23:52:55 2011
@@ -601,6 +601,7 @@
   // Advance to a place where it is safe to insert the new store and
   // insert it.
   BBI = DestBB->getFirstNonPHI();
+  if (isa<LandingPadInst>(BBI)) ++BBI;
   StoreInst *NewSI = new StoreInst(MergedVal, SI.getOperand(1),
                                    SI.isVolatile(),
                                    SI.getAlignment(),

Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137712&r1=137711&r2=137712&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Mon Aug 15 23:52:55 2011
@@ -505,7 +505,9 @@
       }
       for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
         // call runtime to perform increment
-        IRBuilder<> Builder(ComplexEdgeSuccs[i+1]->getFirstNonPHI());
+        BasicBlock::iterator InsertPt = ComplexEdgeSuccs[i+1]->getFirstNonPHI();
+        if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
+        IRBuilder<> Builder(InsertPt);
         Value *CounterPtrArray =
             Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,
                                                i * ComplexEdgePreds.size());



From baldrick at free.fr  Tue Aug 16 01:44:50 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 16 Aug 2011 08:44:50 +0200
Subject: [llvm-commits] [llvm] r137642 -
	/llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <20110815201051.736AD2A6C12C@llvm.org>
References: <20110815201051.736AD2A6C12C@llvm.org>
Message-ID: <4E4A11E2.3080905@free.fr>

Hi Bill,

> The "landingpad" instruction will never be "trivially" dead.

since mayHaveSideEffects() should return true for a landingpad instruction,
this shouldn't be needed: isInstructionTriviallyDead should already return
false.

Ciao, Duncan.

>
> Modified:
>      llvm/trunk/lib/Transforms/Utils/Local.cpp
>
> Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=137642&r1=137641&r2=137642&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Aug 15 15:10:51 2011
> @@ -226,6 +226,10 @@
>   bool llvm::isInstructionTriviallyDead(Instruction *I) {
>     if (!I->use_empty() || isa<TerminatorInst>(I)) return false;
>
> +  // We don't want the landingpad instruction removed by anything this general.
> +  if (isa<LandingPadInst>(I))
> +    return false;
> +
>     // We don't want debug info removed by anything this general, unless
>     // debug info is empty.
>     if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(I)) {
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From james.molloy at arm.com  Tue Aug 16 04:18:20 2011
From: james.molloy at arm.com (James Molloy)
Date: Tue, 16 Aug 2011 10:18:20 +0100
Subject: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
	UNPREDICTABLE insns as soft errors
Message-ID: <003601cc5bf5$712dbdc0$53893940$@molloy@arm.com>

Hi,

 

As discussed on llvm-dev recently, this patch adds support for
"soft-failing" on disassembly of certain ARM instructions.

 

Certain instructions are marked as "UNPREDICTABLE" in the ARMARM - the
disassembly of these instructions may still have value however, especially
to a debugger or debugging code generated by another toolchain.

 

This patch promotes the return value of all Decode* operations in the ARM
disassembly to a ternary value (Success, Unpredictable, Fail) and touches a
lot of the error handling code to perform status demotion from Success to
Unpredictable, and returning early on Fail. It also touches the
FixedLenDecoderEmitter to facilitate the same changes in autogenerated code.

 

The major changelist is:

.         Add a new type "DecodeStatus", local to ARMDisassembler.cpp, and
add a macro CHECK(S, X) that will possibly demote a DecodeStatus S based on
a function X's return value, and exit early if the value becomes "Fail".

.         Modify the return value of Decode* from bool to "DecodeStatus",
modify "if(!X()) return false;" to "CHECK(S, X());", assuming a local
accumulator "DecodeStatus S = Success;".

.         Parameterise FixedLenDecoderEmitter to take as extra (optional)
arguments:

o   The return value of the functions to emit (default "bool")

o    "Guard" prefix and postfix to wrap any function call that may fail
(default "if (!" and ") return false;" respectively)

o   Value to return if everything went OK (default "true")

o   Value to return on failure (default "false")

o   Any extra local variables to add (default "")

.         These defaults maintain the current behaviour of
FixedLenDecoderEmitter. ARM/Thumb has been special cased in
DisassemblerEmitter.cpp.

 

The patch as is does not change the user-seen behaviour of the disassembler
at all. I'm still not sure the best way to expose this information to the
user.

 

AFAIK, Intel or most other architectures don't have the same concept as ARM
of a valid but unpredictable instruction. I'm therefore fearful of changing
MCDisassembler.h to cope with it. At the moment I have an alternate
getInstruction() function that also takes a bool& to which it writes if the
insn was predictable or not.

 

The problem with this obviously is that it requires the user to #include
<ARMDisassembler.h>, which is impossible in the general case as it is a
hidden header.

 

I can see three options, none of which being particularly elegant:

 

.         Make ARMDisassembler.h a public header so the user can
cast<ARMDisassembler> and access an alternate getInstruction() function.

.         Add a bool* parameter to getInstruction() for UNPREDICTABLE;
default is NULL and the other backends ignore it.

.         Add an "wasInsnUnpredictable()" function to MCDisassembler, which
returns false for all other backends and only the ARM backend deals with.
Nastily non-reentrant.

.         ??? An alternative.

 

What would you suggest?

 

Cheers,

 

James
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From 6yearold at gmail.com  Tue Aug 16 05:20:01 2011
From: 6yearold at gmail.com (arrowdodger)
Date: Tue, 16 Aug 2011 14:20:01 +0400
Subject: [llvm-commits] [PATCH] Rename LLVM_MULTITHREADED define and fix
	build without threads
In-Reply-To: <CALH631=mpBYXOECFAQPMoR-dOfcejxOVSo7vHJEDXwvghiio6Q@mail.gmail.com>
References: <CALH631mq9YC+3c1h61eySqK=sqSTQ01+Y5Cj3Y4UxWMG42HeoQ@mail.gmail.com>
	<CALH631=mpBYXOECFAQPMoR-dOfcejxOVSo7vHJEDXwvghiio6Q@mail.gmail.com>
Message-ID: <CALH631kR=eQ7Y=wr84Js2QtW0kK1e5roWiMNpgZLX33VHFWfKw@mail.gmail.com>

On Thu, Aug 11, 2011 at 11:36 AM, arrowdodger <6yearold at gmail.com> wrote:

> On Sat, Aug 6, 2011 at 2:21 PM, arrowdodger <6yearold at gmail.com> wrote:
>
>> Hi, there is LLVM_MULTITHREADED define which is actually indicates
>> presence of atomic builtins in the host system. Such name may confuse
>> developers in future and already confused someone at
>> lib/Support/Threading.cpp - he used this define to check whether LLVM is
>> built with threading support. This mistake is currently blocking
>> single-threaded build on Unix.
>>
>> This patch do following things:
>> 1. Rename LLVM_MULTITHREADED to LLVM_HAVE_ATOMICS in CMake checking code
>> and configure.ac, fix description of this option.
>> 2. Replaces all uses of old define with new one.
>> 3. Fix lib/Support/Threading.cpp file by using ENABLE_THREADS define
>> instead of LLVM_MULTITHREADED.
>>
>
>
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From grosser at fim.uni-passau.de  Tue Aug 16 05:33:13 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 16 Aug 2011 10:33:13 -0000
Subject: [llvm-commits] [zorg] r137713 -
	/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py
Message-ID: <20110816103313.A5CC32A6C12C@llvm.org>

Author: grosser
Date: Tue Aug 16 05:33:13 2011
New Revision: 137713

URL: http://llvm.org/viewvc/llvm-project?rev=137713&view=rev
Log:
PollyBuilder: Disable colors in cmake build

Modified:
    zorg/trunk/zorg/buildbot/builders/PollyBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=137713&r1=137712&r2=137713&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Tue Aug 16 05:33:13 2011
@@ -113,8 +113,10 @@
                                workdir="."))
     cloogpath = WithProperties("-DCMAKE_PREFIX_PATH=%%(builddir)s/%s"
                                 % cloog_installdir)
+    cmakeCommand = ["cmake", "../%s" %llvm_srcdir, cloogpath,
+		    "-DCMAKE_COLOR_MAKEFILE=OFF"]
     f.addStep(ShellCommand(name="cmake-configure",
-                               command=["cmake", "../%s" %llvm_srcdir, cloogpath],
+                               command=cmakeCommand,
                                haltOnFailure=False,
                                description=["cmake configure"],
                                workdir=llvm_objdir))



From geek4civic at gmail.com  Tue Aug 16 06:10:54 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 16 Aug 2011 11:10:54 -0000
Subject: [llvm-commits] [llvm] r137715 -
	/llvm/trunk/cmake/modules/FindBison.cmake
Message-ID: <20110816111054.6F7E62A6C12C@llvm.org>

Author: chapuni
Date: Tue Aug 16 06:10:54 2011
New Revision: 137715

URL: http://llvm.org/viewvc/llvm-project?rev=137715&view=rev
Log:
cmake/modules/FindBison.cmake: It must be unneeded any more.

Removed:
    llvm/trunk/cmake/modules/FindBison.cmake

Removed: llvm/trunk/cmake/modules/FindBison.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/FindBison.cmake?rev=137714&view=auto
==============================================================================
--- llvm/trunk/cmake/modules/FindBison.cmake (original)
+++ llvm/trunk/cmake/modules/FindBison.cmake (removed)
@@ -1,52 +0,0 @@
-# - Try to find Bison
-# Once done this will define
-#
-#  BISON_FOUND - system has Bison
-#  BISON_EXECUTABLE - path of the bison executable
-#  BISON_VERSION - the version string, like "2.5.31"
-#
-
-MACRO(FIND_BISON)
-	FIND_PROGRAM(BISON_EXECUTABLE NAMES bison)
-
-	IF(BISON_EXECUTABLE)
-		SET(BISON_FOUND TRUE)
-
-		EXECUTE_PROCESS(COMMAND ${BISON_EXECUTABLE} --version
-			OUTPUT_VARIABLE _BISON_VERSION
-		)
-		string (REGEX MATCH "[0-9]+\\.[0-9]+\\.[0-9]+" BISON_VERSION "${_bison_VERSION}")
-	ENDIF(BISON_EXECUTABLE)
-
-	IF(BISON_FOUND)
-	  IF(NOT Bison_FIND_QUIETLY)
-		MESSAGE(STATUS "Found Bison: ${BISON_EXECUTABLE}")
-	  ENDIF(NOT Bison_FIND_QUIETLY)
-	ELSE(BISON_FOUND)
-	  IF(Bison_FIND_REQUIRED)
-		MESSAGE(FATAL_ERROR "Could not find Bison")
-	  ENDIF(Bison_FIND_REQUIRED)
-	ENDIF(BISON_FOUND)
-ENDMACRO(FIND_BISON)
-
-MACRO(BISON_GENERATOR _PREFIX _Y_INPUT _H_OUTPUT _CPP_OUTPUT)
-	IF(BISON_EXECUTABLE)
-		GET_FILENAME_COMPONENT(_Y_DIR ${_Y_INPUT} PATH)
-		ADD_CUSTOM_COMMAND(
-			OUTPUT  ${_CPP_OUTPUT}
-			OUTPUT  ${_H_OUTPUT}
-			DEPENDS ${_Y_INPUT}
-			COMMAND ${BISON_EXECUTABLE}
-			ARGS
-				-p ${_PREFIX} -o"${_CPP_OUTPUT}"
-				--defines="${_H_OUTPUT}" ${_Y_INPUT}
-			WORKING_DIRECTORY ${_Y_DIR}
-		)
-		SET_SOURCE_FILES_PROPERTIES(
-			${_CPP_OUTPUT} ${_H_OUTPUT}
-			GENERATED
-		)
-	ELSE(BISON_EXECUTABLE)
-		MESSAGE(SEND_ERROR "Can't find bison program, and it's required")
-	ENDIF(BISON_EXECUTABLE)
-ENDMACRO(BISON_GENERATOR)



From rafael.espindola at gmail.com  Tue Aug 16 08:53:50 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 16 Aug 2011 13:53:50 -0000
Subject: [llvm-commits] [llvm] r137716 -
	/llvm/trunk/include/llvm/MC/MCValue.h
Message-ID: <20110816135350.307522A6C12C@llvm.org>

Author: rafael
Date: Tue Aug 16 08:53:50 2011
New Revision: 137716

URL: http://llvm.org/viewvc/llvm-project?rev=137716&view=rev
Log:
Remove unimplemented method. Fixes PR10658.
Thanks to Jonas Gafele for noticing.

Modified:
    llvm/trunk/include/llvm/MC/MCValue.h

Modified: llvm/trunk/include/llvm/MC/MCValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCValue.h?rev=137716&r1=137715&r2=137716&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCValue.h (original)
+++ llvm/trunk/include/llvm/MC/MCValue.h Tue Aug 16 08:53:50 2011
@@ -46,16 +46,6 @@
   /// isAbsolute - Is this an absolute (as opposed to relocatable) value.
   bool isAbsolute() const { return !SymA && !SymB; }
 
-  /// getAssociatedSection - For relocatable values, return the section the
-  /// value is associated with.
-  ///
-  /// @result - The value's associated section, or null for external or constant
-  /// values.
-  //
-  // FIXME: Switch to a tagged section, so this can return the tagged section
-  // value.
-  const MCSection *getAssociatedSection() const;
-
   /// print - Print the value to the stream \arg OS.
   void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
 



From csdavec at swan.ac.uk  Tue Aug 16 08:58:42 2011
From: csdavec at swan.ac.uk (David Chisnall)
Date: Tue, 16 Aug 2011 13:58:42 -0000
Subject: [llvm-commits] [llvm] r137717 - in /llvm/trunk:
 include/llvm/Transforms/IPO/PassManagerBuilder.h
 lib/Transforms/IPO/PassManagerBuilder.cpp
Message-ID: <20110816135842.2871D2A6C12C@llvm.org>

Author: theraven
Date: Tue Aug 16 08:58:41 2011
New Revision: 137717

URL: http://llvm.org/viewvc/llvm-project?rev=137717&view=rev
Log:
Add a mechanism for optimisation plugins to register passes that all front ends can use without needing to be aware of the plugin (or the plugin be aware of the front end).

Before 3.0, I'd like to add a mechanism for automatically loading a set of plugins from a config file.  API suggestions welcome...


Modified:
    llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.h
    llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp

Modified: llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.h?rev=137717&r1=137716&r2=137717&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.h (original)
+++ llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.h Tue Aug 16 08:58:41 2011
@@ -98,6 +98,10 @@
 public:
   PassManagerBuilder();
   ~PassManagerBuilder();
+  /// Adds an extension that will be used by all PassManagerBuilder instances.
+  /// This is intended to be used by plugins, to register a set of
+  /// optimisations to run automatically.
+  static void addGlobalExtension(ExtensionPointTy Ty, ExtensionFn Fn);
   void addExtension(ExtensionPointTy Ty, ExtensionFn Fn);
 
 private:
@@ -115,6 +119,15 @@
   void populateLTOPassManager(PassManagerBase &PM, bool Internalize,
                               bool RunInliner);
 };
-
+/// Registers a function for adding a standard set of passes.  This should be
+/// used by optimizer plugins to allow all front ends to transparently use
+/// them.  Create a static instance of this class in your plugin, providing a
+/// private function that the PassManagerBuilder can use to add your passes.
+struct RegisterStandardPasses {
+  RegisterStandardPasses(PassManagerBuilder::ExtensionPointTy Ty,
+                         PassManagerBuilder::ExtensionFn Fn) {
+    PassManagerBuilder::addGlobalExtension(Ty, Fn);
+  }
+};
 } // end namespace llvm
 #endif

Modified: llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp?rev=137717&r1=137716&r2=137717&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp Tue Aug 16 08:58:41 2011
@@ -25,6 +25,8 @@
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/IPO.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/ManagedStatic.h"
 
 using namespace llvm;
 
@@ -43,12 +45,25 @@
   delete Inliner;
 }
 
+/// Set of global extensions, automatically added as part of the standard set.
+static ManagedStatic<SmallVector<std::pair<PassManagerBuilder::ExtensionPointTy,
+   PassManagerBuilder::ExtensionFn>, 8> > GlobalExtensions;
+
+void PassManagerBuilder::addGlobalExtension(
+    PassManagerBuilder::ExtensionPointTy Ty,
+    PassManagerBuilder::ExtensionFn Fn) {
+  GlobalExtensions->push_back(std::make_pair(Ty, Fn));
+}
+
 void PassManagerBuilder::addExtension(ExtensionPointTy Ty, ExtensionFn Fn) {
   Extensions.push_back(std::make_pair(Ty, Fn));
 }
 
 void PassManagerBuilder::addExtensionsToPM(ExtensionPointTy ETy,
                                            PassManagerBase &PM) const {
+  for (unsigned i = 0, e = GlobalExtensions->size(); i != e; ++i)
+    if ((*GlobalExtensions)[i].first == ETy)
+      (*GlobalExtensions)[i].second(*this, PM);
   for (unsigned i = 0, e = Extensions.size(); i != e; ++i)
     if (Extensions[i].first == ETy)
       Extensions[i].second(*this, PM);



From baldrick at free.fr  Tue Aug 16 09:08:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 16 Aug 2011 14:08:18 -0000
Subject: [llvm-commits] [dragonegg] r137718 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110816140818.97F702A6C12C@llvm.org>

Author: baldrick
Date: Tue Aug 16 09:08:18 2011
New Revision: 137718

URL: http://llvm.org/viewvc/llvm-project?rev=137718&view=rev
Log:
Do not default initialize fields of a QUAL_UNION that are not
present.  This is theoretical since default initializing these
beasts doesn't make a lot of sense, and the only language that
supports them (Ada) only does explicit initialization using a
non-qualified version of the type.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=137718&r1=137717&r2=137718&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Tue Aug 16 09:08:18 2011
@@ -1083,8 +1083,13 @@
       assert(TREE_CODE(field) == FIELD_DECL && "Lang data not freed?");
       // Ignore fields with variable or unknown position since they cannot be
       // default initialized.
-      if (OffsetIsLLVMCompatible(field))
-        Fields.push_back(field);
+      if (!OffsetIsLLVMCompatible(field))
+        continue;
+      // Skip fields that are known not to be present.
+      if (TREE_CODE(TREE_TYPE(exp)) == QUAL_UNION_TYPE &&
+          integer_zerop(DECL_QUALIFIER(field)))
+        continue; 
+      Fields.push_back(field);
     }
 
     // Process the fields in reverse order.  This is for the benefit of union



From nadav.rotem at intel.com  Tue Aug 16 09:34:29 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 16 Aug 2011 14:34:29 -0000
Subject: [llvm-commits] [llvm] r137719 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <20110816143429.DAB9F2A6C12C@llvm.org>

Author: nadav
Date: Tue Aug 16 09:34:29 2011
New Revision: 137719

URL: http://llvm.org/viewvc/llvm-project?rev=137719&view=rev
Log:
Revert r137562 because it caused PR10674

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=137719&r1=137718&r2=137719&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 16 09:34:29 2011
@@ -928,13 +928,6 @@
   assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
          "APInt size does not match type size!");
 
-  // In some cases the vector type is legal but the element type is illegal.
-  // In this case, promote the inserted value. The type does not need to match
-  // the vector element type. Any extra bits introduced will be
-  // truncated away.
-  if (VT.isVector())
-    EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
-
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);



From james.molloy at arm.com  Tue Aug 16 10:42:22 2011
From: james.molloy at arm.com (James Molloy)
Date: Tue, 16 Aug 2011 16:42:22 +0100
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
	<00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
Message-ID: <003c01cc5c2b$178568f0$46903ad0$@molloy@arm.com>

Hi Jim,

Attached is the modified patch, which adds 4 new MC tests testing for
thumb1, thumb2, arm pre 6t2 and arm post 6t2.

Cheers,

James

> -----Original Message-----
> From: Jim Grosbach [mailto:grosbach at apple.com]
> Sent: 15 August 2011 19:27
> To: James Molloy
> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
> 
> 
> On Aug 15, 2011, at 11:08 AM, James Molloy wrote:
> 
> > Hi Jim,
> >
> > Kristof is out of office for a few weeks, so I'll be taking over
> dealing with this patch.
> >
> > I'll change the code to include MCSubtargetInfo.h as you suggest. I'm
> not sure about what to do with testcases, because Kristof apparently
> found broken behaviour in another part of the MC (for which he's added
> a FIXME) that will stop a normal test from exhibiting the correct
> behaviour - see the first email in the chain for a better description
> of that.
> 
> Ah, right. Forgot about that part. Fixing the mode setting bit
> shouldn't be very invasive, I would hope. I haven't looked at that in
> detail recently, though, I confess.
> 
> In any case, I don't think that will prevent testcases. It just makes
> it not work to have them all be in a single source file (which we
> probably don't want anyway. One file for thumb and one file for ARM
> seems cleaner).
> 
> For example, we can get thumb padding with something like:
> $ cat x.s
> .thumb_func _foo
> .code 16
> _foo:
>         mov r0, r1
>         .align 4
>         mov r0, r2
> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> $ otool -vt x.o
> x.o:
> (__TEXT,__text) section
> _foo:
> 00000000	    4608	mov	r0, r1
> 00000002	    bf00	nop
> 00000004	    bf00	nop
> 00000006	    bf00	nop
> 00000008	    bf00	nop
> 0000000a	    bf00	nop
> 0000000c	    bf00	nop
> 0000000e	    bf00	nop
> 00000010	    4610	mov	r0, r2
> 
> And ARM padding with something like:
> $ cat x.s
> _foo:
>         mov r0, r1
>         .align 4
>         mov r0, r2
> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> $ otool -vt x.o
> x.o:
> (__TEXT,__text) section
> _foo:
> 00000000	e1a00001	mov	r0, r1
> 00000004	e1a00000	nop			(mov r0,r0)
> 00000008	e1a00000	nop			(mov r0,r0)
> 0000000c	e1a00000	nop			(mov r0,r0)
> 00000010	e1a00002	mov	r0, r2
> 
> The tests would want to use macho-dump, not otool, of course, for
> platform independence.
> 
> -Jim
> 
> 
> 
> > He was loath to have his first patch to the list be a large and
> contentious one, as he thinks it will be if he fixes the other
> brokenness immediately. What do you suggest?
> >
> > My suggestion would be to add tests but mark them XFAIL for now -
> would this be acceptable?
> >
> > Cheers,
> >
> > James
> >
> >
> >
> > On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com> wrote:
> >
> >> Hi Kristof,
> >>
> >> This is a lot closer. Using Target/TargetSubtargetInfo.h is a
> layering violation, however. Nothing in the MC layer, which includes
> the AsmBackend, should reference anything in the Target layer. In this
> case, just include MC/MCSubtargetInfo.h directly, instead.
> >>
> >> Also, please add test cases to the LLVM MC tests (in test/MC/ARM) to
> verify that this is doing what you expect. If you're not already
> familiar with it, there are some examples in there (prefetch.ll is a
> good one) for how to use the -check-prefix option FileCheck for this
> sort of conditional behaviour.
> >>
> >> Thanks again!
> >>
> >> -Jim
> >>
> >>
> >> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
> >>
> >>> Hi Jim,
> >>>
> >>> Thanks to have a look!
> >>>
> >>> 1.  I need the exact functionality provided by
> ARMSubTarget::HasV6T2Ops.
> >>> Therefore, in trying not to reinvent the wheel, and
> >>> to avoid code duplication, I'm trying to use
> ARMSubTarget::HasV6T2Ops. I
> >>> think I've found a way to create an ARMSubTarget object from the
> Triple, so
> >>> that it doesn't have to be passed across a lot of interfaces. The
> patch now
> >>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see
> attachment).
> >>> Since it no longer touches Clang, I dropped the cfe-commits list.
> Could you
> >>> have another look and see if this patch is closer to being
> acceptable?
> >>>
> >>> 2. I've created the following bug report:
> >>> http://llvm.org/bugs/show_bug.cgi?id=10632
> >>>
> >>>
> >>> Thanks,
> >>>
> >>> Kristof
> >>>
> >>> -----Original Message-----
> >>> From: Jim Grosbach [mailto:grosbach at apple.com]
> >>> Sent: 10 August 2011 00:08
> >>> To: Kristof Beyls
> >>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
> >>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
> backend.
> >>>
> >>> Hi Kristof,
> >>>
> >>> Thanks for looking at this.
> >>>
> >>> 1. You should be able to derive the needed information from the
> Triple,
> >>> which is already passed in. There's already some code there that
> does
> >>> something similar to set the CPU Subtype correctly for Darwin MachO
> files.
> >>> See the factory method createARMAsmBackend() for details. There
> shouldn't be
> >>> any need to change the top level constructors or the target-
> independent
> >>> bits.
> >>>
> >>> 2. That sounds like a nasty bug. A bugzilla with a test case would
> be great.
> >>>
> >>> -Jim
> >>>
> >>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
> >>>
> >>>> Hi,
> >>>>
> >>>> With the attached patch, I'm trying to fix a FIXME in the ARM
> backend.
> >>> This
> >>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into
> account the
> >>>> version of the ARM architecture that is being targeted. For
> versions
> >>> before
> >>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as MOV
> r0,r0
> >>> (in
> >>>> ARM
> >>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than
> ARMv6T2, the
> >>>> encoding for the NOP instruction is created.
> >>>>
> >>>> I have a few questions about this patch:
> >>>>
> >>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out
> which ARM
> >>>> sub-target it compiles for, I had to adapt the
> >>> Target::MCAsmBackendCtorTy
> >>>> to
> >>>> also pass on an MCSubtargetInfo argument. Is this the best way to
> get
> >>>> sub-target information to the ARMAsmBackend object?
> >>>> (this change results in a few function signature changes in the
> >>>> ARM, PowerPC, X86 and MBlaze backends).
> >>>>
> >>>> 2. It's hard to create test cases to test this properly, since I
> think
> >>>> that there is another bug in lib/MC/MCAssembler.cpp, where
> processing
> >>>> an alignment fragment results in calling
> ARMAsmBackend::WriteNopData,
> >>> but
> >>>> without putting the ARMAsmBackend in the right ARM or Thumb state.
> >>>> Therefore, e.g. when processing an assembler file with .align
> directives
> >>>> in the middle of a Thumb code section, still ARM NOP encodings are
> >>>> generated instead of Thumb NOP encodings.
> >>>> Question 2a: Is it OK to write a FIXME to indicate this
> brokenness?
> >>>> Should
> >>>> I also file a bugzilla issue?
> >>>> Question 2b: Is it OK to leave that fix for a later, separate,
> patch?
> >>> For
> >>>> that fix, it will be easier to create good test cases that will
> also
> >>> test
> >>>> this patch.
> >>>>
> >>>> Thanks,
> >>>>
> >>>> Kristof
> >>>>
> >>>> PS. I'm cc-ing to the cfe-commits list because the change in
> >>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang
> too, see
> >>>> attached file
> >>>
> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_no
> p_enc
> >>> oding.patch>_______________________________________________
> >>>> llvm-commits mailing list
> >>>> llvm-commits at cs.uiuc.edu
> >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >>>
> >>>
> >>> <llvm_arm_nop_encoding_v2.patch>
> >>
> >>
> >>
> >
> > -- IMPORTANT NOTICE: The contents of this email and any attachments
> are confidential and may also be privileged. If you are not the
> intended recipient, please notify the sender immediately and do not
> disclose the contents to any other person, use it for any purpose, or
> store or copy the information in any medium.  Thank you.
> >
> 
> 
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From james.molloy at arm.com  Tue Aug 16 10:59:02 2011
From: james.molloy at arm.com (James Molloy)
Date: Tue, 16 Aug 2011 16:59:02 +0100
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <003c01cc5c2b$178568f0$46903ad0$@molloy@arm.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>	<00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
	<003c01cc5c2b$178568f0$46903ad0$@molloy@arm.com>
Message-ID: <004001cc5c2d$6b2851f0$4178f5d0$@molloy@arm.com>

Hi,

Sorry, this clang patch, identical to that attached to the original issue,
is also required.

James

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of James Molloy
> Sent: 16 August 2011 16:42
> To: 'Jim Grosbach'
> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
> 
> Hi Jim,
> 
> Attached is the modified patch, which adds 4 new MC tests testing for
> thumb1, thumb2, arm pre 6t2 and arm post 6t2.
> 
> Cheers,
> 
> James
> 
> > -----Original Message-----
> > From: Jim Grosbach [mailto:grosbach at apple.com]
> > Sent: 15 August 2011 19:27
> > To: James Molloy
> > Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
> > Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
> >
> >
> > On Aug 15, 2011, at 11:08 AM, James Molloy wrote:
> >
> > > Hi Jim,
> > >
> > > Kristof is out of office for a few weeks, so I'll be taking over
> > dealing with this patch.
> > >
> > > I'll change the code to include MCSubtargetInfo.h as you suggest.
> I'm
> > not sure about what to do with testcases, because Kristof apparently
> > found broken behaviour in another part of the MC (for which he's
> added
> > a FIXME) that will stop a normal test from exhibiting the correct
> > behaviour - see the first email in the chain for a better description
> > of that.
> >
> > Ah, right. Forgot about that part. Fixing the mode setting bit
> > shouldn't be very invasive, I would hope. I haven't looked at that in
> > detail recently, though, I confess.
> >
> > In any case, I don't think that will prevent testcases. It just makes
> > it not work to have them all be in a single source file (which we
> > probably don't want anyway. One file for thumb and one file for ARM
> > seems cleaner).
> >
> > For example, we can get thumb padding with something like:
> > $ cat x.s
> > .thumb_func _foo
> > .code 16
> > _foo:
> >         mov r0, r1
> >         .align 4
> >         mov r0, r2
> > $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> > $ otool -vt x.o
> > x.o:
> > (__TEXT,__text) section
> > _foo:
> > 00000000	    4608	mov	r0, r1
> > 00000002	    bf00	nop
> > 00000004	    bf00	nop
> > 00000006	    bf00	nop
> > 00000008	    bf00	nop
> > 0000000a	    bf00	nop
> > 0000000c	    bf00	nop
> > 0000000e	    bf00	nop
> > 00000010	    4610	mov	r0, r2
> >
> > And ARM padding with something like:
> > $ cat x.s
> > _foo:
> >         mov r0, r1
> >         .align 4
> >         mov r0, r2
> > $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> > $ otool -vt x.o
> > x.o:
> > (__TEXT,__text) section
> > _foo:
> > 00000000	e1a00001	mov	r0, r1
> > 00000004	e1a00000	nop			(mov r0,r0)
> > 00000008	e1a00000	nop			(mov r0,r0)
> > 0000000c	e1a00000	nop			(mov r0,r0)
> > 00000010	e1a00002	mov	r0, r2
> >
> > The tests would want to use macho-dump, not otool, of course, for
> > platform independence.
> >
> > -Jim
> >
> >
> >
> > > He was loath to have his first patch to the list be a large and
> > contentious one, as he thinks it will be if he fixes the other
> > brokenness immediately. What do you suggest?
> > >
> > > My suggestion would be to add tests but mark them XFAIL for now -
> > would this be acceptable?
> > >
> > > Cheers,
> > >
> > > James
> > >
> > >
> > >
> > > On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com>
> wrote:
> > >
> > >> Hi Kristof,
> > >>
> > >> This is a lot closer. Using Target/TargetSubtargetInfo.h is a
> > layering violation, however. Nothing in the MC layer, which includes
> > the AsmBackend, should reference anything in the Target layer. In
> this
> > case, just include MC/MCSubtargetInfo.h directly, instead.
> > >>
> > >> Also, please add test cases to the LLVM MC tests (in test/MC/ARM)
> to
> > verify that this is doing what you expect. If you're not already
> > familiar with it, there are some examples in there (prefetch.ll is a
> > good one) for how to use the -check-prefix option FileCheck for this
> > sort of conditional behaviour.
> > >>
> > >> Thanks again!
> > >>
> > >> -Jim
> > >>
> > >>
> > >> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
> > >>
> > >>> Hi Jim,
> > >>>
> > >>> Thanks to have a look!
> > >>>
> > >>> 1.  I need the exact functionality provided by
> > ARMSubTarget::HasV6T2Ops.
> > >>> Therefore, in trying not to reinvent the wheel, and
> > >>> to avoid code duplication, I'm trying to use
> > ARMSubTarget::HasV6T2Ops. I
> > >>> think I've found a way to create an ARMSubTarget object from the
> > Triple, so
> > >>> that it doesn't have to be passed across a lot of interfaces. The
> > patch now
> > >>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see
> > attachment).
> > >>> Since it no longer touches Clang, I dropped the cfe-commits list.
> > Could you
> > >>> have another look and see if this patch is closer to being
> > acceptable?
> > >>>
> > >>> 2. I've created the following bug report:
> > >>> http://llvm.org/bugs/show_bug.cgi?id=10632
> > >>>
> > >>>
> > >>> Thanks,
> > >>>
> > >>> Kristof
> > >>>
> > >>> -----Original Message-----
> > >>> From: Jim Grosbach [mailto:grosbach at apple.com]
> > >>> Sent: 10 August 2011 00:08
> > >>> To: Kristof Beyls
> > >>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
> > >>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
> > backend.
> > >>>
> > >>> Hi Kristof,
> > >>>
> > >>> Thanks for looking at this.
> > >>>
> > >>> 1. You should be able to derive the needed information from the
> > Triple,
> > >>> which is already passed in. There's already some code there that
> > does
> > >>> something similar to set the CPU Subtype correctly for Darwin
> MachO
> > files.
> > >>> See the factory method createARMAsmBackend() for details. There
> > shouldn't be
> > >>> any need to change the top level constructors or the target-
> > independent
> > >>> bits.
> > >>>
> > >>> 2. That sounds like a nasty bug. A bugzilla with a test case
> would
> > be great.
> > >>>
> > >>> -Jim
> > >>>
> > >>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
> > >>>
> > >>>> Hi,
> > >>>>
> > >>>> With the attached patch, I'm trying to fix a FIXME in the ARM
> > backend.
> > >>> This
> > >>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into
> > account the
> > >>>> version of the ARM architecture that is being targeted. For
> > versions
> > >>> before
> > >>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as
> MOV
> > r0,r0
> > >>> (in
> > >>>> ARM
> > >>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than
> > ARMv6T2, the
> > >>>> encoding for the NOP instruction is created.
> > >>>>
> > >>>> I have a few questions about this patch:
> > >>>>
> > >>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out
> > which ARM
> > >>>> sub-target it compiles for, I had to adapt the
> > >>> Target::MCAsmBackendCtorTy
> > >>>> to
> > >>>> also pass on an MCSubtargetInfo argument. Is this the best way
> to
> > get
> > >>>> sub-target information to the ARMAsmBackend object?
> > >>>> (this change results in a few function signature changes in the
> > >>>> ARM, PowerPC, X86 and MBlaze backends).
> > >>>>
> > >>>> 2. It's hard to create test cases to test this properly, since I
> > think
> > >>>> that there is another bug in lib/MC/MCAssembler.cpp, where
> > processing
> > >>>> an alignment fragment results in calling
> > ARMAsmBackend::WriteNopData,
> > >>> but
> > >>>> without putting the ARMAsmBackend in the right ARM or Thumb
> state.
> > >>>> Therefore, e.g. when processing an assembler file with .align
> > directives
> > >>>> in the middle of a Thumb code section, still ARM NOP encodings
> are
> > >>>> generated instead of Thumb NOP encodings.
> > >>>> Question 2a: Is it OK to write a FIXME to indicate this
> > brokenness?
> > >>>> Should
> > >>>> I also file a bugzilla issue?
> > >>>> Question 2b: Is it OK to leave that fix for a later, separate,
> > patch?
> > >>> For
> > >>>> that fix, it will be easier to create good test cases that will
> > also
> > >>> test
> > >>>> this patch.
> > >>>>
> > >>>> Thanks,
> > >>>>
> > >>>> Kristof
> > >>>>
> > >>>> PS. I'm cc-ing to the cfe-commits list because the change in
> > >>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang
> > too, see
> > >>>> attached file
> > >>>
> >
> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_no
> > p_enc
> > >>> oding.patch>_______________________________________________
> > >>>> llvm-commits mailing list
> > >>>> llvm-commits at cs.uiuc.edu
> > >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > >>>
> > >>>
> > >>> <llvm_arm_nop_encoding_v2.patch>
> > >>
> > >>
> > >>
> > >
> > > -- IMPORTANT NOTICE: The contents of this email and any attachments
> > are confidential and may also be privileged. If you are not the
> > intended recipient, please notify the sender immediately and do not
> > disclose the contents to any other person, use it for any purpose, or
> > store or copy the information in any medium.  Thank you.
> > >
> >
> >
-------------- next part --------------
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From criswell at cs.uiuc.edu  Tue Aug 16 11:01:48 2011
From: criswell at cs.uiuc.edu (John Criswell)
Date: Tue, 16 Aug 2011 11:01:48 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/index.html
Message-ID: <201108161601.p7GG1mCu021318@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

index.html updated: 1.4 -> 1.5
---
Log message:

Added announcement of menagerie going live.
Fixed typo.


---
Diffs of the changes:  (+2 -2)

 index.html |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


Index: llvm-www/safecode/menagerie/index.html
diff -u llvm-www/safecode/menagerie/index.html:1.4 llvm-www/safecode/menagerie/index.html:1.5
--- llvm-www/safecode/menagerie/index.html:1.4	Fri Jun 25 11:02:32 2010
+++ llvm-www/safecode/menagerie/index.html	Tue Aug 16 11:01:16 2011
@@ -56,7 +56,7 @@
 
       <ul>
         <li>
-        June 9, 2010: Started creation of the menagerie.
+        August 9, 2011: The menagerie goes live!
         </li>
       </ul>
 
@@ -70,7 +70,7 @@
 
         <p>
         In an attempt to organize the vast literature on the topic, I have
-        created "sub-"menageries that collect together papers on similar
+        created "sub-menageries" that collect together papers on similar
         topics.  Organization is a tricky thing (just ask the guy who
         discovered the platypus), so I suggest perusing the menagerie to get a
         feel for what is inside.




From criswell at cs.uiuc.edu  Tue Aug 16 11:09:31 2011
From: criswell at cs.uiuc.edu (John Criswell)
Date: Tue, 16 Aug 2011 11:09:31 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/index.html
	attacks.html
Message-ID: <201108161609.p7GG9VaX021774@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

index.html updated: 1.5 -> 1.6
attacks.html updated: 1.7 -> 1.8
---
Log message:

Added Brumley paper on hardening exploits into ROP exploits.


---
Diffs of the changes:  (+18 -0)

 attacks.html |   13 +++++++++++++
 index.html   |    5 +++++
 2 files changed, 18 insertions(+)


Index: llvm-www/safecode/menagerie/index.html
diff -u llvm-www/safecode/menagerie/index.html:1.5 llvm-www/safecode/menagerie/index.html:1.6
--- llvm-www/safecode/menagerie/index.html:1.5	Tue Aug 16 11:01:16 2011
+++ llvm-www/safecode/menagerie/index.html	Tue Aug 16 11:09:19 2011
@@ -56,6 +56,11 @@
 
       <ul>
         <li>
+        August 16, 2011: Added Edward Schwartz et. al.'s paper to the
+        <a href="attacks.html">Memory Safety Attacks</a> menagerie.
+        </li>
+
+        <li>
         August 9, 2011: The menagerie goes live!
         </li>
       </ul>


Index: llvm-www/safecode/menagerie/attacks.html
diff -u llvm-www/safecode/menagerie/attacks.html:1.7 llvm-www/safecode/menagerie/attacks.html:1.8
--- llvm-www/safecode/menagerie/attacks.html:1.7	Fri Jul  2 14:15:39 2010
+++ llvm-www/safecode/menagerie/attacks.html	Tue Aug 16 11:09:19 2011
@@ -82,6 +82,19 @@
 				<ul>
 
         <li>
+        <a href="http://www.usenix.org/events/sec11/tech/full_papers/Schwartz.pdf">
+        <b>Q: Exploit Hardening Made Easy</b></a>
+        <br>
+        Edward J. Schwartz, Thanassis Avgerinos, and David Brumley
+        <br>
+        <i>Proceedings of the Twentieth USENIX Security Symposium</i>,
+        San Francisco, CA, August 2011.
+        <br>
+        </li>
+
+        <br>
+
+        <li>
         <a href="https://www.usenix.org/events/sec09/tech/full_papers/hund.pdf">
         <b>
         Return-Oriented Rookits: Bypassing Kernel Code Integrity Protection




From criswell at cs.uiuc.edu  Tue Aug 16 11:09:35 2011
From: criswell at cs.uiuc.edu (John Criswell)
Date: Tue, 16 Aug 2011 11:09:35 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/footer.incl
Message-ID: <201108161609.p7GG9Z22021781@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

footer.incl updated: 1.3 -> 1.4
---
Log message:

Updated copyright year to 2011.


---
Diffs of the changes:  (+1 -1)

 footer.incl |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


Index: llvm-www/safecode/menagerie/footer.incl
diff -u llvm-www/safecode/menagerie/footer.incl:1.3 llvm-www/safecode/menagerie/footer.incl:1.4
--- llvm-www/safecode/menagerie/footer.incl:1.3	Fri Jun 25 11:50:28 2010
+++ llvm-www/safecode/menagerie/footer.incl	Tue Aug 16 11:08:53 2011
@@ -1,7 +1,7 @@
 <!-- footer starts here -->
 <div class="footer">
   <p>	
-  &copy; 2010 <a href="http://www.illinois.edu">University of Illinois</a>
+  &copy; 2010-2011 <a href="http://www.illinois.edu">University of Illinois</a>
   &nbsp;&nbsp;&nbsp;&nbsp;
 
   <a href="http://www.bluewebtemplates.com/" title="Website Templates">website templates</a> by <a href="http://www.styleshout.com/">styleshout</a>




From grosbach at apple.com  Tue Aug 16 11:11:07 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 09:11:07 -0700
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <003c01cc5c2b$178568f0$46903ad0$%molloy@arm.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
	<00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
	<003c01cc5c2b$178568f0$46903ad0$%molloy@arm.com>
Message-ID: <58414B2C-9532-4C72-8676-DF196EDD3BCC@apple.com>

Hi James,

This patch switches back to adding the SubtargetInfo to the API outside of the ARM target. Can you elaborate a bit on why? If it's necessary, that's fine, I just don't want to change the interfaces if we don't need to.

-Jim

On Aug 16, 2011, at 8:42 AM, James Molloy wrote:

> Hi Jim,
> 
> Attached is the modified patch, which adds 4 new MC tests testing for
> thumb1, thumb2, arm pre 6t2 and arm post 6t2.
> 
> Cheers,
> 
> James
> 
>> -----Original Message-----
>> From: Jim Grosbach [mailto:grosbach at apple.com]
>> Sent: 15 August 2011 19:27
>> To: James Molloy
>> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
>> 
>> 
>> On Aug 15, 2011, at 11:08 AM, James Molloy wrote:
>> 
>>> Hi Jim,
>>> 
>>> Kristof is out of office for a few weeks, so I'll be taking over
>> dealing with this patch.
>>> 
>>> I'll change the code to include MCSubtargetInfo.h as you suggest. I'm
>> not sure about what to do with testcases, because Kristof apparently
>> found broken behaviour in another part of the MC (for which he's added
>> a FIXME) that will stop a normal test from exhibiting the correct
>> behaviour - see the first email in the chain for a better description
>> of that.
>> 
>> Ah, right. Forgot about that part. Fixing the mode setting bit
>> shouldn't be very invasive, I would hope. I haven't looked at that in
>> detail recently, though, I confess.
>> 
>> In any case, I don't think that will prevent testcases. It just makes
>> it not work to have them all be in a single source file (which we
>> probably don't want anyway. One file for thumb and one file for ARM
>> seems cleaner).
>> 
>> For example, we can get thumb padding with something like:
>> $ cat x.s
>> .thumb_func _foo
>> .code 16
>> _foo:
>>        mov r0, r1
>>        .align 4
>>        mov r0, r2
>> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
>> $ otool -vt x.o
>> x.o:
>> (__TEXT,__text) section
>> _foo:
>> 00000000	    4608	mov	r0, r1
>> 00000002	    bf00	nop
>> 00000004	    bf00	nop
>> 00000006	    bf00	nop
>> 00000008	    bf00	nop
>> 0000000a	    bf00	nop
>> 0000000c	    bf00	nop
>> 0000000e	    bf00	nop
>> 00000010	    4610	mov	r0, r2
>> 
>> And ARM padding with something like:
>> $ cat x.s
>> _foo:
>>        mov r0, r1
>>        .align 4
>>        mov r0, r2
>> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
>> $ otool -vt x.o
>> x.o:
>> (__TEXT,__text) section
>> _foo:
>> 00000000	e1a00001	mov	r0, r1
>> 00000004	e1a00000	nop			(mov r0,r0)
>> 00000008	e1a00000	nop			(mov r0,r0)
>> 0000000c	e1a00000	nop			(mov r0,r0)
>> 00000010	e1a00002	mov	r0, r2
>> 
>> The tests would want to use macho-dump, not otool, of course, for
>> platform independence.
>> 
>> -Jim
>> 
>> 
>> 
>>> He was loath to have his first patch to the list be a large and
>> contentious one, as he thinks it will be if he fixes the other
>> brokenness immediately. What do you suggest?
>>> 
>>> My suggestion would be to add tests but mark them XFAIL for now -
>> would this be acceptable?
>>> 
>>> Cheers,
>>> 
>>> James
>>> 
>>> 
>>> 
>>> On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com> wrote:
>>> 
>>>> Hi Kristof,
>>>> 
>>>> This is a lot closer. Using Target/TargetSubtargetInfo.h is a
>> layering violation, however. Nothing in the MC layer, which includes
>> the AsmBackend, should reference anything in the Target layer. In this
>> case, just include MC/MCSubtargetInfo.h directly, instead.
>>>> 
>>>> Also, please add test cases to the LLVM MC tests (in test/MC/ARM) to
>> verify that this is doing what you expect. If you're not already
>> familiar with it, there are some examples in there (prefetch.ll is a
>> good one) for how to use the -check-prefix option FileCheck for this
>> sort of conditional behaviour.
>>>> 
>>>> Thanks again!
>>>> 
>>>> -Jim
>>>> 
>>>> 
>>>> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
>>>> 
>>>>> Hi Jim,
>>>>> 
>>>>> Thanks to have a look!
>>>>> 
>>>>> 1.  I need the exact functionality provided by
>> ARMSubTarget::HasV6T2Ops.
>>>>> Therefore, in trying not to reinvent the wheel, and
>>>>> to avoid code duplication, I'm trying to use
>> ARMSubTarget::HasV6T2Ops. I
>>>>> think I've found a way to create an ARMSubTarget object from the
>> Triple, so
>>>>> that it doesn't have to be passed across a lot of interfaces. The
>> patch now
>>>>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see
>> attachment).
>>>>> Since it no longer touches Clang, I dropped the cfe-commits list.
>> Could you
>>>>> have another look and see if this patch is closer to being
>> acceptable?
>>>>> 
>>>>> 2. I've created the following bug report:
>>>>> http://llvm.org/bugs/show_bug.cgi?id=10632
>>>>> 
>>>>> 
>>>>> Thanks,
>>>>> 
>>>>> Kristof
>>>>> 
>>>>> -----Original Message-----
>>>>> From: Jim Grosbach [mailto:grosbach at apple.com]
>>>>> Sent: 10 August 2011 00:08
>>>>> To: Kristof Beyls
>>>>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
>>>>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
>> backend.
>>>>> 
>>>>> Hi Kristof,
>>>>> 
>>>>> Thanks for looking at this.
>>>>> 
>>>>> 1. You should be able to derive the needed information from the
>> Triple,
>>>>> which is already passed in. There's already some code there that
>> does
>>>>> something similar to set the CPU Subtype correctly for Darwin MachO
>> files.
>>>>> See the factory method createARMAsmBackend() for details. There
>> shouldn't be
>>>>> any need to change the top level constructors or the target-
>> independent
>>>>> bits.
>>>>> 
>>>>> 2. That sounds like a nasty bug. A bugzilla with a test case would
>> be great.
>>>>> 
>>>>> -Jim
>>>>> 
>>>>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
>>>>> 
>>>>>> Hi,
>>>>>> 
>>>>>> With the attached patch, I'm trying to fix a FIXME in the ARM
>> backend.
>>>>> This
>>>>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into
>> account the
>>>>>> version of the ARM architecture that is being targeted. For
>> versions
>>>>> before
>>>>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as MOV
>> r0,r0
>>>>> (in
>>>>>> ARM
>>>>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than
>> ARMv6T2, the
>>>>>> encoding for the NOP instruction is created.
>>>>>> 
>>>>>> I have a few questions about this patch:
>>>>>> 
>>>>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out
>> which ARM
>>>>>> sub-target it compiles for, I had to adapt the
>>>>> Target::MCAsmBackendCtorTy
>>>>>> to
>>>>>> also pass on an MCSubtargetInfo argument. Is this the best way to
>> get
>>>>>> sub-target information to the ARMAsmBackend object?
>>>>>> (this change results in a few function signature changes in the
>>>>>> ARM, PowerPC, X86 and MBlaze backends).
>>>>>> 
>>>>>> 2. It's hard to create test cases to test this properly, since I
>> think
>>>>>> that there is another bug in lib/MC/MCAssembler.cpp, where
>> processing
>>>>>> an alignment fragment results in calling
>> ARMAsmBackend::WriteNopData,
>>>>> but
>>>>>> without putting the ARMAsmBackend in the right ARM or Thumb state.
>>>>>> Therefore, e.g. when processing an assembler file with .align
>> directives
>>>>>> in the middle of a Thumb code section, still ARM NOP encodings are
>>>>>> generated instead of Thumb NOP encodings.
>>>>>> Question 2a: Is it OK to write a FIXME to indicate this
>> brokenness?
>>>>>> Should
>>>>>> I also file a bugzilla issue?
>>>>>> Question 2b: Is it OK to leave that fix for a later, separate,
>> patch?
>>>>> For
>>>>>> that fix, it will be easier to create good test cases that will
>> also
>>>>> test
>>>>>> this patch.
>>>>>> 
>>>>>> Thanks,
>>>>>> 
>>>>>> Kristof
>>>>>> 
>>>>>> PS. I'm cc-ing to the cfe-commits list because the change in
>>>>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang
>> too, see
>>>>>> attached file
>>>>> 
>> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_no
>> p_enc
>>>>> oding.patch>_______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>> 
>>>>> 
>>>>> <llvm_arm_nop_encoding_v2.patch>
>>>> 
>>>> 
>>>> 
>>> 
>>> -- IMPORTANT NOTICE: The contents of this email and any attachments
>> are confidential and may also be privileged. If you are not the
>> intended recipient, please notify the sender immediately and do not
>> disclose the contents to any other person, use it for any purpose, or
>> store or copy the information in any medium.  Thank you.
>>> 
>> 
>> 
> <nop.patch>


From james.molloy at arm.com  Tue Aug 16 11:38:06 2011
From: james.molloy at arm.com (James Molloy)
Date: Tue, 16 Aug 2011 17:38:06 +0100
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <58414B2C-9532-4C72-8676-DF196EDD3BCC@apple.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
	<00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
	<003c01cc5c2b$178568f0$46903ad0$%molloy@arm.com>
	<58414B2C-9532-4C72-8676-DF196EDD3BCC@apple.com>
Message-ID: <004401cc5c32$e08aba50$a1a02ef0$@molloy@arm.com>

Hi Jim,

The elaboration is that it appears Kristof didn't correctly update our
internal bug tracking system with his altered patch based on your last
review.

I've now taken the patch as it was last sent to the list and updated it to
change the #include and add tests as mentioned. I believe that the patch now
no longer requires any changes to clang either.

Apologies,

James

> -----Original Message-----
> From: Jim Grosbach [mailto:grosbach at apple.com]
> Sent: 16 August 2011 17:11
> To: James Molloy
> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
> 
> Hi James,
> 
> This patch switches back to adding the SubtargetInfo to the API outside
> of the ARM target. Can you elaborate a bit on why? If it's necessary,
> that's fine, I just don't want to change the interfaces if we don't
> need to.
> 
> -Jim
> 
> On Aug 16, 2011, at 8:42 AM, James Molloy wrote:
> 
> > Hi Jim,
> >
> > Attached is the modified patch, which adds 4 new MC tests testing for
> > thumb1, thumb2, arm pre 6t2 and arm post 6t2.
> >
> > Cheers,
> >
> > James
> >
> >> -----Original Message-----
> >> From: Jim Grosbach [mailto:grosbach at apple.com]
> >> Sent: 15 August 2011 19:27
> >> To: James Molloy
> >> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
> >> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
> backend.
> >>
> >>
> >> On Aug 15, 2011, at 11:08 AM, James Molloy wrote:
> >>
> >>> Hi Jim,
> >>>
> >>> Kristof is out of office for a few weeks, so I'll be taking over
> >> dealing with this patch.
> >>>
> >>> I'll change the code to include MCSubtargetInfo.h as you suggest.
> I'm
> >> not sure about what to do with testcases, because Kristof apparently
> >> found broken behaviour in another part of the MC (for which he's
> added
> >> a FIXME) that will stop a normal test from exhibiting the correct
> >> behaviour - see the first email in the chain for a better
> description
> >> of that.
> >>
> >> Ah, right. Forgot about that part. Fixing the mode setting bit
> >> shouldn't be very invasive, I would hope. I haven't looked at that
> in
> >> detail recently, though, I confess.
> >>
> >> In any case, I don't think that will prevent testcases. It just
> makes
> >> it not work to have them all be in a single source file (which we
> >> probably don't want anyway. One file for thumb and one file for ARM
> >> seems cleaner).
> >>
> >> For example, we can get thumb padding with something like:
> >> $ cat x.s
> >> .thumb_func _foo
> >> .code 16
> >> _foo:
> >>        mov r0, r1
> >>        .align 4
> >>        mov r0, r2
> >> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> >> $ otool -vt x.o
> >> x.o:
> >> (__TEXT,__text) section
> >> _foo:
> >> 00000000	    4608	mov	r0, r1
> >> 00000002	    bf00	nop
> >> 00000004	    bf00	nop
> >> 00000006	    bf00	nop
> >> 00000008	    bf00	nop
> >> 0000000a	    bf00	nop
> >> 0000000c	    bf00	nop
> >> 0000000e	    bf00	nop
> >> 00000010	    4610	mov	r0, r2
> >>
> >> And ARM padding with something like:
> >> $ cat x.s
> >> _foo:
> >>        mov r0, r1
> >>        .align 4
> >>        mov r0, r2
> >> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
> >> $ otool -vt x.o
> >> x.o:
> >> (__TEXT,__text) section
> >> _foo:
> >> 00000000	e1a00001	mov	r0, r1
> >> 00000004	e1a00000	nop			(mov r0,r0)
> >> 00000008	e1a00000	nop			(mov r0,r0)
> >> 0000000c	e1a00000	nop			(mov r0,r0)
> >> 00000010	e1a00002	mov	r0, r2
> >>
> >> The tests would want to use macho-dump, not otool, of course, for
> >> platform independence.
> >>
> >> -Jim
> >>
> >>
> >>
> >>> He was loath to have his first patch to the list be a large and
> >> contentious one, as he thinks it will be if he fixes the other
> >> brokenness immediately. What do you suggest?
> >>>
> >>> My suggestion would be to add tests but mark them XFAIL for now -
> >> would this be acceptable?
> >>>
> >>> Cheers,
> >>>
> >>> James
> >>>
> >>>
> >>>
> >>> On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com>
> wrote:
> >>>
> >>>> Hi Kristof,
> >>>>
> >>>> This is a lot closer. Using Target/TargetSubtargetInfo.h is a
> >> layering violation, however. Nothing in the MC layer, which includes
> >> the AsmBackend, should reference anything in the Target layer. In
> this
> >> case, just include MC/MCSubtargetInfo.h directly, instead.
> >>>>
> >>>> Also, please add test cases to the LLVM MC tests (in test/MC/ARM)
> to
> >> verify that this is doing what you expect. If you're not already
> >> familiar with it, there are some examples in there (prefetch.ll is a
> >> good one) for how to use the -check-prefix option FileCheck for this
> >> sort of conditional behaviour.
> >>>>
> >>>> Thanks again!
> >>>>
> >>>> -Jim
> >>>>
> >>>>
> >>>> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
> >>>>
> >>>>> Hi Jim,
> >>>>>
> >>>>> Thanks to have a look!
> >>>>>
> >>>>> 1.  I need the exact functionality provided by
> >> ARMSubTarget::HasV6T2Ops.
> >>>>> Therefore, in trying not to reinvent the wheel, and
> >>>>> to avoid code duplication, I'm trying to use
> >> ARMSubTarget::HasV6T2Ops. I
> >>>>> think I've found a way to create an ARMSubTarget object from the
> >> Triple, so
> >>>>> that it doesn't have to be passed across a lot of interfaces. The
> >> patch now
> >>>>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see
> >> attachment).
> >>>>> Since it no longer touches Clang, I dropped the cfe-commits list.
> >> Could you
> >>>>> have another look and see if this patch is closer to being
> >> acceptable?
> >>>>>
> >>>>> 2. I've created the following bug report:
> >>>>> http://llvm.org/bugs/show_bug.cgi?id=10632
> >>>>>
> >>>>>
> >>>>> Thanks,
> >>>>>
> >>>>> Kristof
> >>>>>
> >>>>> -----Original Message-----
> >>>>> From: Jim Grosbach [mailto:grosbach at apple.com]
> >>>>> Sent: 10 August 2011 00:08
> >>>>> To: Kristof Beyls
> >>>>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
> >>>>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
> >> backend.
> >>>>>
> >>>>> Hi Kristof,
> >>>>>
> >>>>> Thanks for looking at this.
> >>>>>
> >>>>> 1. You should be able to derive the needed information from the
> >> Triple,
> >>>>> which is already passed in. There's already some code there that
> >> does
> >>>>> something similar to set the CPU Subtype correctly for Darwin
> MachO
> >> files.
> >>>>> See the factory method createARMAsmBackend() for details. There
> >> shouldn't be
> >>>>> any need to change the top level constructors or the target-
> >> independent
> >>>>> bits.
> >>>>>
> >>>>> 2. That sounds like a nasty bug. A bugzilla with a test case
> would
> >> be great.
> >>>>>
> >>>>> -Jim
> >>>>>
> >>>>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
> >>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>> With the attached patch, I'm trying to fix a FIXME in the ARM
> >> backend.
> >>>>> This
> >>>>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into
> >> account the
> >>>>>> version of the ARM architecture that is being targeted. For
> >> versions
> >>>>> before
> >>>>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as
> MOV
> >> r0,r0
> >>>>> (in
> >>>>>> ARM
> >>>>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than
> >> ARMv6T2, the
> >>>>>> encoding for the NOP instruction is created.
> >>>>>>
> >>>>>> I have a few questions about this patch:
> >>>>>>
> >>>>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out
> >> which ARM
> >>>>>> sub-target it compiles for, I had to adapt the
> >>>>> Target::MCAsmBackendCtorTy
> >>>>>> to
> >>>>>> also pass on an MCSubtargetInfo argument. Is this the best way
> to
> >> get
> >>>>>> sub-target information to the ARMAsmBackend object?
> >>>>>> (this change results in a few function signature changes in the
> >>>>>> ARM, PowerPC, X86 and MBlaze backends).
> >>>>>>
> >>>>>> 2. It's hard to create test cases to test this properly, since I
> >> think
> >>>>>> that there is another bug in lib/MC/MCAssembler.cpp, where
> >> processing
> >>>>>> an alignment fragment results in calling
> >> ARMAsmBackend::WriteNopData,
> >>>>> but
> >>>>>> without putting the ARMAsmBackend in the right ARM or Thumb
> state.
> >>>>>> Therefore, e.g. when processing an assembler file with .align
> >> directives
> >>>>>> in the middle of a Thumb code section, still ARM NOP encodings
> are
> >>>>>> generated instead of Thumb NOP encodings.
> >>>>>> Question 2a: Is it OK to write a FIXME to indicate this
> >> brokenness?
> >>>>>> Should
> >>>>>> I also file a bugzilla issue?
> >>>>>> Question 2b: Is it OK to leave that fix for a later, separate,
> >> patch?
> >>>>> For
> >>>>>> that fix, it will be easier to create good test cases that will
> >> also
> >>>>> test
> >>>>>> this patch.
> >>>>>>
> >>>>>> Thanks,
> >>>>>>
> >>>>>> Kristof
> >>>>>>
> >>>>>> PS. I'm cc-ing to the cfe-commits list because the change in
> >>>>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang
> >> too, see
> >>>>>> attached file
> >>>>>
> >>
> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_no
> >> p_enc
> >>>>> oding.patch>_______________________________________________
> >>>>>> llvm-commits mailing list
> >>>>>> llvm-commits at cs.uiuc.edu
> >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >>>>>
> >>>>>
> >>>>> <llvm_arm_nop_encoding_v2.patch>
> >>>>
> >>>>
> >>>>
> >>>
> >>> -- IMPORTANT NOTICE: The contents of this email and any attachments
> >> are confidential and may also be privileged. If you are not the
> >> intended recipient, please notify the sender immediately and do not
> >> disclose the contents to any other person, use it for any purpose,
> or
> >> store or copy the information in any medium.  Thank you.
> >>>
> >>
> >>
> > <nop.patch>
> 
> 
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From grosbach at apple.com  Tue Aug 16 11:38:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 16:38:17 -0000
Subject: [llvm-commits] [llvm] r137721 -
	/llvm/trunk/include/llvm/MC/MCInstrDesc.h
Message-ID: <20110816163817.B143C2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 11:38:17 2011
New Revision: 137721

URL: http://llvm.org/viewvc/llvm-project?rev=137721&view=rev
Log:
Tidy up. Trailing whitespace.

Modified:
    llvm/trunk/include/llvm/MC/MCInstrDesc.h

Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=137721&r1=137720&r2=137721&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Tue Aug 16 11:38:17 2011
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file defines the MCOperandInfo and MCInstrDesc classes, which
-// are used to describe target instructions and their operands. 
+// are used to describe target instructions and their operands.
 //
 //===----------------------------------------------------------------------===//
 
@@ -22,14 +22,14 @@
 //===----------------------------------------------------------------------===//
 // Machine Operand Flags and Description
 //===----------------------------------------------------------------------===//
-  
+
 namespace MCOI {
   // Operand constraints
   enum OperandConstraint {
     TIED_TO = 0,    // Must be allocated the same register as.
     EARLY_CLOBBER   // Operand is an early clobber register operand
   };
-  
+
   /// OperandFlags - These are flags set on operands, but should be considered
   /// private, all access should go through the MCOperandInfo accessors.
   /// See the accessors for a description of what these are.
@@ -54,15 +54,15 @@
 ///
 class MCOperandInfo {
 public:
-  /// RegClass - This specifies the register class enumeration of the operand 
+  /// RegClass - This specifies the register class enumeration of the operand
   /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
   /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
   /// get a dynamic register class.
   short RegClass;
-  
+
   /// Flags - These are flags from the MCOI::OperandFlags enum.
   unsigned short Flags;
-  
+
   /// Lower 16 bits are used to specify which constraints are set. The higher 16
   /// bits are used to specify the value of constraints (4 bits each).
   unsigned Constraints;
@@ -70,21 +70,21 @@
   /// OperandType - Information about the type of the operand.
   MCOI::OperandType OperandType;
   /// Currently no other information.
-  
+
   /// isLookupPtrRegClass - Set if this operand is a pointer value and it
   /// requires a callback to look up its register class.
   bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);}
-  
+
   /// isPredicate - Set if this is one of the operands that made up of
   /// the predicate operand that controls an isPredicable() instruction.
   bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
-  
+
   /// isOptionalDef - Set if this operand is a optional def.
   ///
   bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
 };
 
-  
+
 //===----------------------------------------------------------------------===//
 // Machine Instruction Flags and Description
 //===----------------------------------------------------------------------===//
@@ -158,13 +158,13 @@
   unsigned getOpcode() const {
     return Opcode;
   }
-  
+
   /// getName - Return the name of the record in the .td file for this
   /// instruction, for example "ADD8ri".
   const char *getName() const {
     return Name;
   }
-  
+
   /// getNumOperands - Return the number of declared MachineOperands for this
   /// MachineInstruction.  Note that variadic (isVariadic() returns true)
   /// instructions may have additional operands at the end of the list, and note
@@ -173,15 +173,15 @@
   unsigned getNumOperands() const {
     return NumOperands;
   }
-  
+
   /// getNumDefs - Return the number of MachineOperands that are register
-  /// definitions.  Register definitions always occur at the start of the 
+  /// definitions.  Register definitions always occur at the start of the
   /// machine operand list.  This is the number of "outs" in the .td file,
   /// and does not include implicit defs.
   unsigned getNumDefs() const {
     return NumDefs;
   }
-  
+
   /// isVariadic - Return true if this instruction can have a variable number of
   /// operands.  In this case, the variable operands will be after the normal
   /// operands but before the implicit definitions and uses (if any are
@@ -189,13 +189,13 @@
   bool isVariadic() const {
     return Flags & (1 << MCID::Variadic);
   }
-  
+
   /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
   /// ARM instructions which can set condition code if 's' bit is set.
   bool hasOptionalDef() const {
     return Flags & (1 << MCID::HasOptionalDef);
   }
-  
+
   /// getImplicitUses - Return a list of registers that are potentially
   /// read by any instance of this machine instruction.  For example, on X86,
   /// the "adc" instruction adds two register operands and adds the carry bit in
@@ -208,7 +208,7 @@
   const unsigned *getImplicitUses() const {
     return ImplicitUses;
   }
-      
+
   /// getNumImplicitUses - Return the number of implicit uses this instruction
   /// has.
   unsigned getNumImplicitUses() const {
@@ -231,7 +231,7 @@
   const unsigned *getImplicitDefs() const {
     return ImplicitDefs;
   }
-  
+
   /// getNumImplicitDefs - Return the number of implicit defs this instruction
   /// has.
   unsigned getNumImplicitDefs() const {
@@ -240,7 +240,7 @@
     for (; ImplicitDefs[i]; ++i) /*empty*/;
     return i;
   }
-  
+
   /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
   /// uses the specified physical register.
   bool hasImplicitUseOfPhysReg(unsigned Reg) const {
@@ -249,7 +249,7 @@
         if (*ImpUses == Reg) return true;
     return false;
   }
-  
+
   /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
   /// defines the specified physical register.
   bool hasImplicitDefOfPhysReg(unsigned Reg) const {
@@ -267,7 +267,7 @@
   unsigned getSchedClass() const {
     return SchedClass;
   }
-  
+
   /// getSize - Return the number of bytes in the encoding of this instruction,
   /// or zero if the encoding size cannot be known from the opcode.
   unsigned getSize() const {
@@ -277,18 +277,18 @@
   bool isReturn() const {
     return Flags & (1 << MCID::Return);
   }
-  
+
   bool isCall() const {
     return Flags & (1 << MCID::Call);
   }
-  
+
   /// isBarrier - Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
   bool isBarrier() const {
     return Flags & (1 << MCID::Barrier);
   }
-  
+
   /// isTerminator - Returns true if this instruction part of the terminator for
   /// a basic block.  Typically this is things like return and branch
   /// instructions.
@@ -298,7 +298,7 @@
   bool isTerminator() const {
     return Flags & (1 << MCID::Terminator);
   }
-  
+
   /// isBranch - Returns true if this is a conditional, unconditional, or
   /// indirect branch.  Predicates below can be used to discriminate between
   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
@@ -320,7 +320,7 @@
   bool isConditionalBranch() const {
     return isBranch() & !isBarrier() & !isIndirectBranch();
   }
-  
+
   /// isUnconditionalBranch - Return true if this is a branch which always
   /// transfers control flow to some other block.  The
   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
@@ -328,7 +328,7 @@
   bool isUnconditionalBranch() const {
     return isBranch() & isBarrier() & !isIndirectBranch();
   }
-  
+
   // isPredicable - Return true if this instruction has a predicate operand that
   // controls execution.  It may be set to 'always', or may be set to other
   /// values.   There are various methods in TargetInstrInfo that can be used to
@@ -336,14 +336,14 @@
   bool isPredicable() const {
     return Flags & (1 << MCID::Predicable);
   }
-  
+
   /// isCompare - Return true if this instruction is a comparison.
   bool isCompare() const {
     return Flags & (1 << MCID::Compare);
   }
-  
+
   /// isMoveImmediate - Return true if this instruction is a move immediate
-  /// (including conditional moves) instruction. 
+  /// (including conditional moves) instruction.
   bool isMoveImmediate() const {
     return Flags & (1 << MCID::MoveImm);
   }
@@ -353,20 +353,20 @@
   bool isBitcast() const {
     return Flags & (1 << MCID::Bitcast);
   }
-  
+
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.
   bool isNotDuplicable() const {
     return Flags & (1 << MCID::NotDuplicable);
   }
-  
+
   /// hasDelaySlot - Returns true if the specified instruction has a delay slot
   /// which must be filled by the code generator.
   bool hasDelaySlot() const {
     return Flags & (1 << MCID::DelaySlot);
   }
-  
+
   /// canFoldAsLoad - Return true for instructions that can be folded as
   /// memory operands in other instructions. The most common use for this
   /// is instructions that are simple loads from memory that don't modify
@@ -378,7 +378,7 @@
   bool canFoldAsLoad() const {
     return Flags & (1 << MCID::FoldableAsLoad);
   }
-  
+
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis
   //===--------------------------------------------------------------------===//
@@ -389,8 +389,8 @@
   bool mayLoad() const {
     return Flags & (1 << MCID::MayLoad);
   }
-  
-  
+
+
   /// mayStore - Return true if this instruction could possibly modify memory.
   /// Instructions with this flag set are not necessarily simple store
   /// instructions, they may store a modified value based on their operands, or
@@ -398,7 +398,7 @@
   bool mayStore() const {
     return Flags & (1 << MCID::MayStore);
   }
-  
+
   /// hasUnmodeledSideEffects - Return true if this instruction has side
   /// effects that are not modeled by other flags.  This does not return true
   /// for instructions whose effects are captured by:
@@ -415,14 +415,14 @@
   bool hasUnmodeledSideEffects() const {
     return Flags & (1 << MCID::UnmodeledSideEffects);
   }
-  
+
   //===--------------------------------------------------------------------===//
   // Flags that indicate whether an instruction can be modified by a method.
   //===--------------------------------------------------------------------===//
-  
+
   /// isCommutable - Return true if this may be a 2- or 3-address
   /// instruction (of the form "X = op Y, Z, ..."), which produces the same
-  /// result if Y and Z are exchanged.  If this flag is set, then the 
+  /// result if Y and Z are exchanged.  If this flag is set, then the
   /// TargetInstrInfo::commuteInstruction method may be used to hack on the
   /// instruction.
   ///
@@ -433,7 +433,7 @@
   bool isCommutable() const {
     return Flags & (1 << MCID::Commutable);
   }
-  
+
   /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
   /// which can be changed into a 3-address instruction if needed.  Doing this
   /// transformation can be profitable in the register allocator, because it
@@ -451,11 +451,11 @@
   bool isConvertibleTo3Addr() const {
     return Flags & (1 << MCID::ConvertibleTo3Addr);
   }
-  
+
   /// usesCustomInsertionHook - Return true if this instruction requires
   /// custom insertion support when the DAG scheduler is inserting it into a
   /// machine basic block.  If this is true for the instruction, it basically
-  /// means that it is a pseudo instruction used at SelectionDAG time that is 
+  /// means that it is a pseudo instruction used at SelectionDAG time that is
   /// expanded out into magic code by the target when MachineInstrs are formed.
   ///
   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
@@ -463,7 +463,7 @@
   bool usesCustomInsertionHook() const {
     return Flags & (1 << MCID::UsesCustomInserter);
   }
-  
+
   /// isRematerializable - Returns true if this instruction is a candidate for
   /// remat.  This flag is deprecated, please don't use it anymore.  If this
   /// flag is set, the isReallyTriviallyReMaterializable() method is called to



From grosbach at apple.com  Tue Aug 16 12:06:20 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 17:06:20 -0000
Subject: [llvm-commits] [llvm] r137723 - in /llvm/trunk:
 lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
 test/MC/ARM/nop-armv4-padding.s test/MC/ARM/nop-armv6t2-padding.s
 test/MC/ARM/nop-thumb-padding.s test/MC/ARM/nop-thumb2-padding.s
Message-ID: <20110816170620.C7C5B2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 12:06:20 2011
New Revision: 137723

URL: http://llvm.org/viewvc/llvm-project?rev=137723&view=rev
Log:
ARM .align NOP padding uses different encoding pre-ARMv6.

Patch by Kristof Beyls and James Malloy.

Added:
    llvm/trunk/test/MC/ARM/nop-armv4-padding.s
    llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
    llvm/trunk/test/MC/ARM/nop-thumb-padding.s
    llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=137723&r1=137722&r2=137723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Tue Aug 16 12:06:20 2011
@@ -7,6 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "MCTargetDesc/ARMFixupKinds.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
@@ -20,6 +21,7 @@
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Object/MachOFormat.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -35,12 +37,23 @@
 };
 
 class ARMAsmBackend : public MCAsmBackend {
+  const MCSubtargetInfo* STI;
   bool isThumbMode;  // Currently emitting Thumb code.
 public:
-  ARMAsmBackend(const Target &T) : MCAsmBackend(), isThumbMode(false) {}
+  ARMAsmBackend(const Target &T, const StringRef TT)
+    : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
+      isThumbMode(false) {}
+
+  ~ARMAsmBackend() {
+    delete STI;
+  }
 
   unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
 
+  bool hasNOP() const {
+    return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
+  }
+
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
     const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
 // This table *must* be in the order that the fixup_* kinds are defined in
@@ -122,20 +135,28 @@
 }
 
 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
+  const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
+  const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
+  const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
+  const uint32_t ARMv6T2_NopEncoding = 0xe3207800; // NOP
   if (isThumb()) {
-    // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
-    // use 0x46c0 (which is a 'mov r8, r8' insn).
+    const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
+                                          : Thumb1_16bitNopEncoding;
     uint64_t NumNops = Count / 2;
     for (uint64_t i = 0; i != NumNops; ++i)
-      OW->Write16(0xbf00);
+      OW->Write16(nopEncoding);
     if (Count & 1)
       OW->Write8(0);
     return true;
   }
   // ARM mode
+  const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
+                                        : ARMv4_NopEncoding;
   uint64_t NumNops = Count / 4;
   for (uint64_t i = 0; i != NumNops; ++i)
-    OW->Write32(0xe1a00000);
+    OW->Write32(nopEncoding);
+  // FIXME: should this function return false when unable to write exactly
+  // 'Count' bytes with NOP encodings?
   switch (Count % 4) {
   default: break; // No leftover bytes to write
   case 1: OW->Write8(0); break;
@@ -381,8 +402,9 @@
 class ELFARMAsmBackend : public ARMAsmBackend {
 public:
   Triple::OSType OSType;
-  ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
-    : ARMAsmBackend(T), OSType(_OSType) { }
+  ELFARMAsmBackend(const Target &T, const StringRef TT,
+                   Triple::OSType _OSType)
+    : ARMAsmBackend(T, TT), OSType(_OSType) { }
 
   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value) const;
@@ -413,8 +435,9 @@
 class DarwinARMAsmBackend : public ARMAsmBackend {
 public:
   const object::mach::CPUSubtypeARM Subtype;
-  DarwinARMAsmBackend(const Target &T, object::mach::CPUSubtypeARM st)
-    : ARMAsmBackend(T), Subtype(st) { }
+  DarwinARMAsmBackend(const Target &T, const StringRef TT,
+                      object::mach::CPUSubtypeARM st)
+    : ARMAsmBackend(T, TT), Subtype(st) { }
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
     return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
@@ -497,18 +520,18 @@
   if (TheTriple.isOSDarwin()) {
     if (TheTriple.getArchName() == "armv4t" ||
         TheTriple.getArchName() == "thumbv4t")
-      return new DarwinARMAsmBackend(T, object::mach::CSARM_V4T);
+      return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
     else if (TheTriple.getArchName() == "armv5e" ||
         TheTriple.getArchName() == "thumbv5e")
-      return new DarwinARMAsmBackend(T, object::mach::CSARM_V5TEJ);
+      return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
     else if (TheTriple.getArchName() == "armv6" ||
         TheTriple.getArchName() == "thumbv6")
-      return new DarwinARMAsmBackend(T, object::mach::CSARM_V6);
-    return new DarwinARMAsmBackend(T, object::mach::CSARM_V7);
+      return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
+    return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
   }
 
   if (TheTriple.isOSWindows())
     assert(0 && "Windows not supported on ARM");
 
-  return new ELFARMAsmBackend(T, Triple(TT).getOS());
+  return new ELFARMAsmBackend(T, TT, Triple(TT).getOS());
 }

Added: llvm/trunk/test/MC/ARM/nop-armv4-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-armv4-padding.s?rev=137723&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-armv4-padding.s (added)
+++ llvm/trunk/test/MC/ARM/nop-armv4-padding.s Tue Aug 16 12:06:20 2011
@@ -0,0 +1,10 @@
+@ RUN: llvm-mc -triple armv4-apple-darwin %s -filetype=obj -o %t.obj
+@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
+@ RUN: FileCheck %s < %t.dump
+
+x:
+      add r0, r1, r2
+      .align 4
+      add r0, r1, r2
+
+@ CHECK: ('_section_data', '020081e0 00001a0e 00001a0e 00001a0e 020081e0')

Added: llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s?rev=137723&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s (added)
+++ llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s Tue Aug 16 12:06:20 2011
@@ -0,0 +1,10 @@
+@ RUN: llvm-mc -triple armv6t2-apple-darwin %s -filetype=obj -o %t.obj
+@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
+@ RUN: FileCheck %s < %t.dump
+
+x:
+      add r0, r1, r2
+      .align 4
+      add r0, r1, r2
+
+@ CHECK: ('_section_data', '020081e0 007820e3 007820e3 007820e3 020081e0')

Added: llvm/trunk/test/MC/ARM/nop-thumb-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb-padding.s?rev=137723&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb-padding.s (added)
+++ llvm/trunk/test/MC/ARM/nop-thumb-padding.s Tue Aug 16 12:06:20 2011
@@ -0,0 +1,12 @@
+@ RUN: llvm-mc -triple armv6-apple-darwin %s -filetype=obj -o %t.obj
+@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
+@ RUN: FileCheck %s < %t.dump
+
+.thumb_func x
+.code 16
+x:
+      add r0, r1, r2
+      .align 4
+      add r0, r1, r2
+
+@ CHECK: ('_section_data', '8818c046 c046c046 c046c046 c046c046 8818')

Added: llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb2-padding.s?rev=137723&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb2-padding.s (added)
+++ llvm/trunk/test/MC/ARM/nop-thumb2-padding.s Tue Aug 16 12:06:20 2011
@@ -0,0 +1,12 @@
+@ RUN: llvm-mc -triple armv7-apple-darwin %s -filetype=obj -o %t.obj
+@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump
+@ RUN: FileCheck %s < %t.dump
+
+.thumb_func x
+.code 16
+x:
+      add r0, r1, r2
+      .align 4
+      add r0, r1, r2
+
+@ CHECK: ('_section_data', '881800bf 00bf00bf 00bf00bf 00bf00bf 8818')



From grosbach at apple.com  Tue Aug 16 12:07:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 10:07:45 -0700
Subject: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
In-Reply-To: <004401cc5c32$e08aba50$a1a02ef0$%molloy@arm.com>
References: <001001cc55d2$c1c4e020$454ea060$%beyls@arm.com>
	<B95424DA-E2EF-4A27-BC12-944238A19EA1@apple.com>
	<000001cc5763$35a7ccf0$a0f766d0$%beyls@arm.com>
	<AB46D348-FAFE-4FAB-8566-5DA0B4C15ED4@apple.com>
	<912B5987-E3EB-4CA2-A257-4412B89DBBFC@arm.com>
	<00D5EE2E-A95F-42AE-8839-1304465E8034@apple.com>
	<003c01cc5c2b$178568f0$46903ad0$%molloy@arm.com>
	<58414B2C-9532-4C72-8676-DF196EDD3BCC@apple.com>
	<004401cc5c32$e08aba50$a1a02ef0$%molloy@arm.com>
Message-ID: <7B4C285E-D932-4E53-A208-414034B8D3AE@apple.com>

Hi James,

No worries. I just wanted to make sure I wasn't missing something.

Applied in r137723.

Thanks again!

-Jim
On Aug 16, 2011, at 9:38 AM, James Molloy wrote:

> Hi Jim,
> 
> The elaboration is that it appears Kristof didn't correctly update our
> internal bug tracking system with his altered patch based on your last
> review.
> 
> I've now taken the patch as it was last sent to the list and updated it to
> change the #include and add tests as mentioned. I believe that the patch now
> no longer requires any changes to clang either.
> 
> Apologies,
> 
> James
> 
>> -----Original Message-----
>> From: Jim Grosbach [mailto:grosbach at apple.com]
>> Sent: 16 August 2011 17:11
>> To: James Molloy
>> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM backend.
>> 
>> Hi James,
>> 
>> This patch switches back to adding the SubtargetInfo to the API outside
>> of the ARM target. Can you elaborate a bit on why? If it's necessary,
>> that's fine, I just don't want to change the interfaces if we don't
>> need to.
>> 
>> -Jim
>> 
>> On Aug 16, 2011, at 8:42 AM, James Molloy wrote:
>> 
>>> Hi Jim,
>>> 
>>> Attached is the modified patch, which adds 4 new MC tests testing for
>>> thumb1, thumb2, arm pre 6t2 and arm post 6t2.
>>> 
>>> Cheers,
>>> 
>>> James
>>> 
>>>> -----Original Message-----
>>>> From: Jim Grosbach [mailto:grosbach at apple.com]
>>>> Sent: 15 August 2011 19:27
>>>> To: James Molloy
>>>> Cc: Kristof Beyls; llvm-commits at cs.uiuc.edu
>>>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
>> backend.
>>>> 
>>>> 
>>>> On Aug 15, 2011, at 11:08 AM, James Molloy wrote:
>>>> 
>>>>> Hi Jim,
>>>>> 
>>>>> Kristof is out of office for a few weeks, so I'll be taking over
>>>> dealing with this patch.
>>>>> 
>>>>> I'll change the code to include MCSubtargetInfo.h as you suggest.
>> I'm
>>>> not sure about what to do with testcases, because Kristof apparently
>>>> found broken behaviour in another part of the MC (for which he's
>> added
>>>> a FIXME) that will stop a normal test from exhibiting the correct
>>>> behaviour - see the first email in the chain for a better
>> description
>>>> of that.
>>>> 
>>>> Ah, right. Forgot about that part. Fixing the mode setting bit
>>>> shouldn't be very invasive, I would hope. I haven't looked at that
>> in
>>>> detail recently, though, I confess.
>>>> 
>>>> In any case, I don't think that will prevent testcases. It just
>> makes
>>>> it not work to have them all be in a single source file (which we
>>>> probably don't want anyway. One file for thumb and one file for ARM
>>>> seems cleaner).
>>>> 
>>>> For example, we can get thumb padding with something like:
>>>> $ cat x.s
>>>> .thumb_func _foo
>>>> .code 16
>>>> _foo:
>>>>       mov r0, r1
>>>>       .align 4
>>>>       mov r0, r2
>>>> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
>>>> $ otool -vt x.o
>>>> x.o:
>>>> (__TEXT,__text) section
>>>> _foo:
>>>> 00000000	    4608	mov	r0, r1
>>>> 00000002	    bf00	nop
>>>> 00000004	    bf00	nop
>>>> 00000006	    bf00	nop
>>>> 00000008	    bf00	nop
>>>> 0000000a	    bf00	nop
>>>> 0000000c	    bf00	nop
>>>> 0000000e	    bf00	nop
>>>> 00000010	    4610	mov	r0, r2
>>>> 
>>>> And ARM padding with something like:
>>>> $ cat x.s
>>>> _foo:
>>>>       mov r0, r1
>>>>       .align 4
>>>>       mov r0, r2
>>>> $ llvm-mc -triple=armv4-apple-darwin x.s -filetype=obj -o x.o
>>>> $ otool -vt x.o
>>>> x.o:
>>>> (__TEXT,__text) section
>>>> _foo:
>>>> 00000000	e1a00001	mov	r0, r1
>>>> 00000004	e1a00000	nop			(mov r0,r0)
>>>> 00000008	e1a00000	nop			(mov r0,r0)
>>>> 0000000c	e1a00000	nop			(mov r0,r0)
>>>> 00000010	e1a00002	mov	r0, r2
>>>> 
>>>> The tests would want to use macho-dump, not otool, of course, for
>>>> platform independence.
>>>> 
>>>> -Jim
>>>> 
>>>> 
>>>> 
>>>>> He was loath to have his first patch to the list be a large and
>>>> contentious one, as he thinks it will be if he fixes the other
>>>> brokenness immediately. What do you suggest?
>>>>> 
>>>>> My suggestion would be to add tests but mark them XFAIL for now -
>>>> would this be acceptable?
>>>>> 
>>>>> Cheers,
>>>>> 
>>>>> James
>>>>> 
>>>>> 
>>>>> 
>>>>> On 15 Aug 2011, at 18:47, "Jim Grosbach" <grosbach at apple.com>
>> wrote:
>>>>> 
>>>>>> Hi Kristof,
>>>>>> 
>>>>>> This is a lot closer. Using Target/TargetSubtargetInfo.h is a
>>>> layering violation, however. Nothing in the MC layer, which includes
>>>> the AsmBackend, should reference anything in the Target layer. In
>> this
>>>> case, just include MC/MCSubtargetInfo.h directly, instead.
>>>>>> 
>>>>>> Also, please add test cases to the LLVM MC tests (in test/MC/ARM)
>> to
>>>> verify that this is doing what you expect. If you're not already
>>>> familiar with it, there are some examples in there (prefetch.ll is a
>>>> good one) for how to use the -check-prefix option FileCheck for this
>>>> sort of conditional behaviour.
>>>>>> 
>>>>>> Thanks again!
>>>>>> 
>>>>>> -Jim
>>>>>> 
>>>>>> 
>>>>>> On Aug 10, 2011, at 6:41 AM, Kristof Beyls wrote:
>>>>>> 
>>>>>>> Hi Jim,
>>>>>>> 
>>>>>>> Thanks to have a look!
>>>>>>> 
>>>>>>> 1.  I need the exact functionality provided by
>>>> ARMSubTarget::HasV6T2Ops.
>>>>>>> Therefore, in trying not to reinvent the wheel, and
>>>>>>> to avoid code duplication, I'm trying to use
>>>> ARMSubTarget::HasV6T2Ops. I
>>>>>>> think I've found a way to create an ARMSubTarget object from the
>>>> Triple, so
>>>>>>> that it doesn't have to be passed across a lot of interfaces. The
>>>> patch now
>>>>>>> only changes lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (see
>>>> attachment).
>>>>>>> Since it no longer touches Clang, I dropped the cfe-commits list.
>>>> Could you
>>>>>>> have another look and see if this patch is closer to being
>>>> acceptable?
>>>>>>> 
>>>>>>> 2. I've created the following bug report:
>>>>>>> http://llvm.org/bugs/show_bug.cgi?id=10632
>>>>>>> 
>>>>>>> 
>>>>>>> Thanks,
>>>>>>> 
>>>>>>> Kristof
>>>>>>> 
>>>>>>> -----Original Message-----
>>>>>>> From: Jim Grosbach [mailto:grosbach at apple.com]
>>>>>>> Sent: 10 August 2011 00:08
>>>>>>> To: Kristof Beyls
>>>>>>> Cc: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
>>>>>>> Subject: Re: [llvm-commits] [PATCH] Fix NOP encodings in ARM
>>>> backend.
>>>>>>> 
>>>>>>> Hi Kristof,
>>>>>>> 
>>>>>>> Thanks for looking at this.
>>>>>>> 
>>>>>>> 1. You should be able to derive the needed information from the
>>>> Triple,
>>>>>>> which is already passed in. There's already some code there that
>>>> does
>>>>>>> something similar to set the CPU Subtype correctly for Darwin
>> MachO
>>>> files.
>>>>>>> See the factory method createARMAsmBackend() for details. There
>>>> shouldn't be
>>>>>>> any need to change the top level constructors or the target-
>>>> independent
>>>>>>> bits.
>>>>>>> 
>>>>>>> 2. That sounds like a nasty bug. A bugzilla with a test case
>> would
>>>> be great.
>>>>>>> 
>>>>>>> -Jim
>>>>>>> 
>>>>>>> On Aug 8, 2011, at 6:54 AM, Kristof Beyls wrote:
>>>>>>> 
>>>>>>>> Hi,
>>>>>>>> 
>>>>>>>> With the attached patch, I'm trying to fix a FIXME in the ARM
>>>> backend.
>>>>>>> This
>>>>>>>> patch fixes ARMAsmBackend::WriteNopData, so that it takes into
>>>> account the
>>>>>>>> version of the ARM architecture that is being targeted. For
>>>> versions
>>>>>>> before
>>>>>>>> ARMv6T2, there is no NOP instruction, and NOPs are encoded as
>> MOV
>>>> r0,r0
>>>>>>> (in
>>>>>>>> ARM
>>>>>>>> mode) or MOV r8,r8 (in Thumb mode). For targets later than
>>>> ARMv6T2, the
>>>>>>>> encoding for the NOP instruction is created.
>>>>>>>> 
>>>>>>>> I have a few questions about this patch:
>>>>>>>> 
>>>>>>>> 1. To make sure that ARMAsmBackend::WriteNopData can figure out
>>>> which ARM
>>>>>>>> sub-target it compiles for, I had to adapt the
>>>>>>> Target::MCAsmBackendCtorTy
>>>>>>>> to
>>>>>>>> also pass on an MCSubtargetInfo argument. Is this the best way
>> to
>>>> get
>>>>>>>> sub-target information to the ARMAsmBackend object?
>>>>>>>> (this change results in a few function signature changes in the
>>>>>>>> ARM, PowerPC, X86 and MBlaze backends).
>>>>>>>> 
>>>>>>>> 2. It's hard to create test cases to test this properly, since I
>>>> think
>>>>>>>> that there is another bug in lib/MC/MCAssembler.cpp, where
>>>> processing
>>>>>>>> an alignment fragment results in calling
>>>> ARMAsmBackend::WriteNopData,
>>>>>>> but
>>>>>>>> without putting the ARMAsmBackend in the right ARM or Thumb
>> state.
>>>>>>>> Therefore, e.g. when processing an assembler file with .align
>>>> directives
>>>>>>>> in the middle of a Thumb code section, still ARM NOP encodings
>> are
>>>>>>>> generated instead of Thumb NOP encodings.
>>>>>>>> Question 2a: Is it OK to write a FIXME to indicate this
>>>> brokenness?
>>>>>>>> Should
>>>>>>>> I also file a bugzilla issue?
>>>>>>>> Question 2b: Is it OK to leave that fix for a later, separate,
>>>> patch?
>>>>>>> For
>>>>>>>> that fix, it will be easier to create good test cases that will
>>>> also
>>>>>>> test
>>>>>>>> this patch.
>>>>>>>> 
>>>>>>>> Thanks,
>>>>>>>> 
>>>>>>>> Kristof
>>>>>>>> 
>>>>>>>> PS. I'm cc-ing to the cfe-commits list because the change in
>>>>>>>> Target::MCAsmBackendCtorTy requires 2 lines to change in Clang
>>>> too, see
>>>>>>>> attached file
>>>>>>> 
>>>> 
>> clang_arm_nop_encoding.patch.<llvm_arm_nop_encoding.patch><clang_arm_no
>>>> p_enc
>>>>>>> oding.patch>_______________________________________________
>>>>>>>> llvm-commits mailing list
>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>> 
>>>>>>> 
>>>>>>> <llvm_arm_nop_encoding_v2.patch>
>>>>>> 
>>>>>> 
>>>>>> 
>>>>> 
>>>>> -- IMPORTANT NOTICE: The contents of this email and any attachments
>>>> are confidential and may also be privileged. If you are not the
>>>> intended recipient, please notify the sender immediately and do not
>>>> disclose the contents to any other person, use it for any purpose,
>> or
>>>> store or copy the information in any medium.  Thank you.
>>>>> 
>>>> 
>>>> 
>>> <nop.patch>
>> 
>> 
> <nop.v2.patch>


From ahatanak at gmail.com  Tue Aug 16 12:32:01 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 16 Aug 2011 17:32:01 -0000
Subject: [llvm-commits] [llvm] r137725 -
	/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
Message-ID: <20110816173201.B9C3D2A6C12C@llvm.org>

Author: ahatanak
Date: Tue Aug 16 12:32:01 2011
New Revision: 137725

URL: http://llvm.org/viewvc/llvm-project?rev=137725&view=rev
Log:
Add test case for r137711.

Added:
    llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll

Added: llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll?rev=137725&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll Tue Aug 16 12:32:01 2011
@@ -0,0 +1,36 @@
+; RUN: llc  < %s -march=mipsel  | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc  < %s -march=mips  | FileCheck %s -check-prefix=CHECK-EB
+
+ at g1 = common global double 0.000000e+00, align 8
+ at g2 = common global double 0.000000e+00, align 8
+
+define double @foo0(double %d0) nounwind {
+entry:
+; CHECK-EL: lw  $[[R0:[0-9]+]], %got($CPI0_0)
+; CHECK-EL: lwc1  $f[[R1:[0-9]+]], %lo($CPI0_0)($[[R0]])
+; CHECK-EL: lwc1  $f{{[0-9]+}}, %lo($CPI0_0+4)($[[R0]])
+; CHECK-EL: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
+; CHECK-EL: lw  $[[R3:[0-9]+]], %got(g1)
+; CHECK-EL: swc1  $f[[R2]], 0($[[R3]])
+; CHECK-EL: swc1  $f{{[0-9]+}}, 4($[[R3]])
+; CHECK-EL: lw  $[[R4:[0-9]+]], %got(g2)
+; CHECK-EL: lwc1  $f0, 0($[[R4]])
+; CHECK-EL: lwc1  $f1, 4($[[R4]])
+
+; CHECK-EB: lw  $[[R0:[0-9]+]], %got($CPI0_0)
+; CHECK-EB: lwc1  $f{{[0-9]+}}, %lo($CPI0_0)($[[R0]])
+; CHECK-EB: lwc1  $f[[R1:[0-9]+]], %lo($CPI0_0+4)($[[R0]])
+; CHECK-EB: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
+; CHECK-EB: lw  $[[R3:[0-9]+]], %got(g1)
+; CHECK-EB: swc1  $f{{[0-9]+}}, 0($[[R3]])
+; CHECK-EB: swc1  $f[[R2]], 4($[[R3]])
+; CHECK-EB: lw  $[[R4:[0-9]+]], %got(g2)
+; CHECK-EB: lwc1  $f1, 0($[[R4]])
+; CHECK-EB: lwc1  $f0, 4($[[R4]])
+
+  %add = fadd double %d0, 2.000000e+00
+  store double %add, double* @g1, align 8
+  %tmp1 = load double* @g2, align 8
+  ret double %tmp1
+}
+



From rjmccall at apple.com  Tue Aug 16 12:32:57 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 16 Aug 2011 10:32:57 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <4E4A11E2.3080905@free.fr>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
Message-ID: <3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>

On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>> The "landingpad" instruction will never be "trivially" dead.
> 
> since mayHaveSideEffects() should return true for a landingpad instruction,
> this shouldn't be needed: isInstructionTriviallyDead should already return
> false.

I don't understand where you and Bill are going with this.  landingpad
does not have side-effects, not does it read or write "visible" memory.
I'm aware that SjLj's lowering involves memory accesses, but it's to
unaliased, private memory.

I guess it's okay, if a bit weird and unfortunate, to describe landingpad
as having side-effects in order to get various optimizations to do the
right thing without custom modification.  But if that's what you're doing,
you should document it that way.  In the abstract machine, landingpad
has no side-effects and does not access memory.

John.

From dpatel at apple.com  Tue Aug 16 12:41:41 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 16 Aug 2011 17:41:41 -0000
Subject: [llvm-commits] [llvm] r137728 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20110816174141.625D42A6C12C@llvm.org>

Author: dpatel
Date: Tue Aug 16 12:41:41 2011
New Revision: 137728

URL: http://llvm.org/viewvc/llvm-project?rev=137728&view=rev
Log:
Remove unnecessary version check.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137728&r1=137727&r2=137728&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 16 12:41:41 2011
@@ -617,8 +617,7 @@
   for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
          E = DbgFinder.global_variable_end(); I != E; ++I) {
     const MDNode *N = *I;
-    if (DIGlobalVariable(N).getVersion() <= LLVMDebugVersion9)
-      constructGlobalVariableDIE(getCompileUnit(N), N);
+    constructGlobalVariableDIE(getCompileUnit(N), N);
   }
   
   // Create DIEs for each subprogram.



From rjmccall at apple.com  Tue Aug 16 12:46:57 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 16 Aug 2011 10:46:57 -0700
Subject: [llvm-commits] [llvm] r137691 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
In-Reply-To: <CAJdarcHa0ypWKRCnJOL4JeHYTe9oygi8ue55+9xAv65_62jWXQ@mail.gmail.com>
References: <20110815235928.32C022A6C12C@llvm.org>
	<EA68500F-4A9D-44E4-8CAD-704EADBAEFB2@apple.com>
	<CAJdarcHa0ypWKRCnJOL4JeHYTe9oygi8ue55+9xAv65_62jWXQ@mail.gmail.com>
Message-ID: <919ECF6D-EFBB-458F-B5F0-8707D26F8565@apple.com>

On Aug 15, 2011, at 5:25 PM, Eli Friedman wrote:
> On Mon, Aug 15, 2011 at 5:18 PM, Bill Wendling <wendling at apple.com> wrote:
>> The changes look okay, but I have a question about this comment:
>> 
>>> +      // Note that deleting LandingPad's here is in fact okay, although it
>>> +      // involves a bit of subtle reasoning. If this inst is a LandingPad,
>>> +      // all the predecessors of this block will be the unwind edges of Invokes,
>>> +      // and we can therefore guaranteed this block will be erased.
>> 
>> I'm not sure what you're trying to get at here. If we have a landing pad instruction followed by an unreachable, that landing pad would be a "terminate" landing pad. I.e., we expect the personality function to call the 'terminate' function. In fact, I initially wanted something like this:
>> 
>> bb1:
>>  invoke ...
>>     to label %normal unwind to %unwind
>> 
>> unwind:
>>  %val = landingpad { i8*, i32 }, personality ...
>>            terminate
>>  unreachable
>> 
>> In which case we would not be able to delete the landingpad instruction. I would still like to implement something akin to this, as it's a useful optimization.
>> 
>> My point is that removing landingpad instructions is very tricky, and should be done only if all of the invokes unwinding to the landing pad have been removed or converted into 'call's. :-)
> 
> What the code currently does is if there is a landingpad followed by
> an unreachable, it will remove the block and change all invokes
> referring to it into calls.  From what you're saying, it sounds like
> that is correct, but we won't want to do it once we have terminate?

Bill is incorrect;  terminate should not involve landing pads with
empty, unreachable bodies.  That should only be produceable with
undefined behavior in a cleanup;  as usual, in that case we are
not constrained to deliver any particular behavior.  Erasing the
landing pad seems fine, and you could even mark the call nounwind
if the selector is total.

Whether that optimization is actually worth an enormous drop in
debuggability is a different question.

John.

From echristo at apple.com  Tue Aug 16 12:46:44 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 16 Aug 2011 17:46:44 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r137729 -
	/llvm-gcc-4.2/trunk/build_gcc
Message-ID: <20110816174644.BFC112A6C12C@llvm.org>

Author: echristo
Date: Tue Aug 16 12:46:44 2011
New Revision: 137729

URL: http://llvm.org/viewvc/llvm-project?rev=137729&view=rev
Log:
Lots of clang as the new black.

Modified:
    llvm-gcc-4.2/trunk/build_gcc

Modified: llvm-gcc-4.2/trunk/build_gcc
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=137729&r1=137728&r2=137729&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/build_gcc (original)
+++ llvm-gcc-4.2/trunk/build_gcc Tue Aug 16 12:46:44 2011
@@ -258,12 +258,12 @@
 # LLVM LOCAL end
 
 # If the user has set CC or CXX, respect their wishes.  If not,
-# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not
+# compile with clang/clang++ if available; if LLVM is not
 # available, fall back to usual GCC/G++ default.
 savedPATH=$PATH ; PATH="/Developer/usr/bin:$PATH"
-XTMPCC=$(which llvm-gcc)
+XTMPCC=$(which clang)
 if [ x$CC  = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC  forcedCC=1  ; fi
-XTMPCC=$(which llvm-g++)
+XTMPCC=$(which clang++)
 if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC forcedCXX=1 ; fi
 PATH=$savedPATH
 unset XTMPCC savedPATH



From nlewycky at google.com  Tue Aug 16 12:51:03 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Tue, 16 Aug 2011 10:51:03 -0700
Subject: [llvm-commits] [llvm] r137712 - in /llvm/trunk/lib:
 Analysis/ScalarEvolutionExpander.cpp
 Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
 Transforms/Instrumentation/GCOVProfiling.cpp
In-Reply-To: <20110816045255.8F40D2A6C12C@llvm.org>
References: <20110816045255.8F40D2A6C12C@llvm.org>
Message-ID: <CADbEz-gP8mZqKbQa06Lxz6D3S8VkReKcvhfsffMqY=rKYnxCFQ@mail.gmail.com>

On 15 August 2011 21:52, Bill Wendling <isanbard at gmail.com> wrote:

> Author: void
> Date: Mon Aug 15 23:52:55 2011
> New Revision: 137712
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137712&view=rev
> Log:
> A few places where we want to skip the landingpad instruction for
> insertion.
>
> Modified:
>    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
>    llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
>    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
>
> Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=137712&r1=137711&r2=137712&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
> +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Aug 15 23:52:55
> 2011
> @@ -1323,8 +1323,11 @@
>       // If the SCEV is computable at this level, insert it into the header
>       // after the PHIs (and after any other instructions that we've
> inserted
>       // there) so that it is guaranteed to dominate any user inside the
> loop.
> -      if (L && SE.hasComputableLoopEvolution(S, L) &&
> !PostIncLoops.count(L))
> +      if (L && SE.hasComputableLoopEvolution(S, L) &&
> !PostIncLoops.count(L)) {
>         InsertPt = L->getHeader()->getFirstNonPHI();
> +        if (isa<LandingPadInst>(InsertPt))
> +          InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
> +      }
>       while (isInsertedInstruction(InsertPt) ||
> isa<DbgInfoIntrinsic>(InsertPt))
>         InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
>       break;
>
> Modified:
> llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=137712&r1=137711&r2=137712&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
> (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
> Mon Aug 15 23:52:55 2011
> @@ -601,6 +601,7 @@
>   // Advance to a place where it is safe to insert the new store and
>   // insert it.
>   BBI = DestBB->getFirstNonPHI();
> +  if (isa<LandingPadInst>(BBI)) ++BBI;
>   StoreInst *NewSI = new StoreInst(MergedVal, SI.getOperand(1),
>                                    SI.isVolatile(),
>                                    SI.getAlignment(),
>
> Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137712&r1=137711&r2=137712&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
> +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Mon Aug 15
> 23:52:55 2011
> @@ -505,7 +505,9 @@
>       }
>       for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
>         // call runtime to perform increment
> -        IRBuilder<> Builder(ComplexEdgeSuccs[i+1]->getFirstNonPHI());
> +        BasicBlock::iterator InsertPt =
> ComplexEdgeSuccs[i+1]->getFirstNonPHI();
> +        if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
> +        IRBuilder<> Builder(InsertPt);
>

How about a method like getFirstNonPHI() but that skips landingpad called
getFirstInsertPoint? The comment for such a method would be that it returns
the earliest insertpt that does not have an ordering constraint in the IR?

Nick


>         Value *CounterPtrArray =
>             Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,
>                                                i *
> ComplexEdgePreds.size());
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From bruno.cardoso at gmail.com  Tue Aug 16 13:21:54 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 16 Aug 2011 18:21:54 -0000
Subject: [llvm-commits] [llvm] r137733 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-basic.ll
Message-ID: <20110816182154.E9F172A6C12C@llvm.org>

Author: bruno
Date: Tue Aug 16 13:21:54 2011
New Revision: 137733

URL: http://llvm.org/viewvc/llvm-project?rev=137733&view=rev
Log:
Instead of always leaving the work to the generic legalizer when
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-basic.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137733&r1=137732&r2=137733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 16 13:21:54 2011
@@ -3027,6 +3027,17 @@
   return (Val < 0) || (Val >= Low && Val < Hi);
 }
 
+/// isUndefOrInRange - Return true if every element in Mask, begining
+/// from position Pos and ending in Pos+Size, falls within the specified
+/// range (L, L+Pos]. or is undef.
+static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
+                             int Pos, int Size, int Low, int Hi) {
+  for (int i = Pos, e = Pos+Size; i != e; ++i)
+    if (!isUndefOrInRange(Mask[i], Low, Hi))
+      return false;
+  return true;
+}
+
 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
 /// specified value.
 static bool isUndefOrEqual(int Val, int CmpVal) {
@@ -5666,10 +5677,95 @@
                                              OpVT, SrcOp)));
 }
 
+/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
+/// shuffle node referes to only one lane in the sources.
+static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
+  EVT VT = SVOp->getValueType(0);
+  int NumElems = VT.getVectorNumElements();
+  int HalfSize = NumElems/2;
+  SmallVector<int, 16> M;
+  SVOp->getMask(M);
+  bool MatchA = false, MatchB = false;
+
+  for (int l = 0; l < NumElems*2; l += HalfSize) {
+    if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
+      MatchA = true;
+      break;
+    }
+  }
+
+  for (int l = 0; l < NumElems*2; l += HalfSize) {
+    if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
+      MatchB = true;
+      break;
+    }
+  }
+
+  return MatchA && MatchB;
+}
+
 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
 /// which could not be matched by any known target speficic shuffle
 static SDValue
 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
+  if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
+    // If each half of a vector shuffle node referes to only one lane in the
+    // source vectors, extract each used 128-bit lane and shuffle them using
+    // 128-bit shuffles. Then, concatenate the results. Otherwise leave
+    // the work to the legalizer.
+    DebugLoc dl = SVOp->getDebugLoc();
+    EVT VT = SVOp->getValueType(0);
+    int NumElems = VT.getVectorNumElements();
+    int HalfSize = NumElems/2;
+
+    // Extract the reference for each half
+    int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
+    int FstVecOpNum = 0, SndVecOpNum = 0;
+    for (int i = 0; i < HalfSize; ++i) {
+      int Elt = SVOp->getMaskElt(i);
+      if (SVOp->getMaskElt(i) < 0)
+        continue;
+      FstVecOpNum = Elt/NumElems;
+      FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
+      break;
+    }
+    for (int i = HalfSize; i < NumElems; ++i) {
+      int Elt = SVOp->getMaskElt(i);
+      if (SVOp->getMaskElt(i) < 0)
+        continue;
+      SndVecOpNum = Elt/NumElems;
+      SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
+      break;
+    }
+
+    // Extract the subvectors
+    SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
+                      DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
+    SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
+                      DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
+
+    // Generate 128-bit shuffles
+    SmallVector<int, 16> MaskV1, MaskV2;
+    for (int i = 0; i < HalfSize; ++i) {
+      int Elt = SVOp->getMaskElt(i);
+      MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
+    }
+    for (int i = HalfSize; i < NumElems; ++i) {
+      int Elt = SVOp->getMaskElt(i);
+      MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
+    }
+
+    EVT NVT = V1.getValueType();
+    V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
+    V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
+
+    // Concatenate the result back
+    SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
+                                   DAG.getConstant(0, MVT::i32), DAG, dl);
+    return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
+                              DAG, dl);
+  }
+
   return SDValue();
 }
 

Modified: llvm/trunk/test/CodeGen/X86/avx-basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=137733&r1=137732&r2=137733&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-basic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-basic.ll Tue Aug 16 13:21:54 2011
@@ -50,3 +50,46 @@
   %shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
   ret <4 x i64> %shuffle
 }
+
+;;;
+;;; Check that some 256-bit vectors are xformed into 128 ops
+; CHECK: _A
+; CHECK: vshufpd $1
+; CHECK-NEXT: vextractf128 $1
+; CHECK-NEXT: vshufpd $1
+; CHECK-NEXT: vinsertf128 $1
+define <4 x i64> @A(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6>
+  ret <4 x i64> %shuffle
+}
+
+; CHECK: vpunpckhqdq
+; CHECK-NEXT: vextractf128  $1
+; CHECK-NEXT: movlhps
+; CHECK-NEXT: vinsertf128 $1
+define <4 x i64> @B(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 undef, i32 undef, i32 6>
+  ret <4 x i64> %shuffle
+}
+
+; CHECK: movlhps
+; CHECK-NEXT: vextractf128  $1
+; CHECK-NEXT: movlhps
+; CHECK-NEXT: vinsertf128 $1
+define <4 x i64> @C(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 undef, i32 0, i32 undef, i32 6>
+  ret <4 x i64> %shuffle
+}
+
+; CHECK: vpshufd $-96
+; CHECK: vpshufd $-6
+; CHECK: vinsertf128 $1
+define <8 x i32> @D(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 10, i32 10, i32 11, i32 11>
+  ret <8 x i32> %shuffle
+}
+



From anton at korobeynikov.info  Tue Aug 16 13:22:48 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Tue, 16 Aug 2011 22:22:48 +0400
Subject: [llvm-commits] [PATCH] CrashRecoveryContext.cpp Win32 support
In-Reply-To: <CAAt6xTuSP9yLLaXuu8CjPfMgkj7k--vrMv8Wo5wvLhV6fHY2VQ@mail.gmail.com>
References: <CAAt6xTtrnZMDaBwYtNYz=SymNssyNWcN9RhXSgr4mN8StMwgdQ@mail.gmail.com>
	<CADiQthOCqtc5CZ+uwncJdvwBN6OEYBRmSh0sVspmWaPE_ifEpw@mail.gmail.com>
	<CAAt6xTuZiRH-jjDvcrf-c8sjNjbQ=eH2QtfnG2udW7pOCTkv1A@mail.gmail.com>
	<CAAt6xTuSP9yLLaXuu8CjPfMgkj7k--vrMv8Wo5wvLhV6fHY2VQ@mail.gmail.com>
Message-ID: <CA+Ov9+nNHAcddTGJTd1XvYnUBy8S+4oQjZz9GWV51si-LgXW4g@mail.gmail.com>

> I've made the modifications and tested them out in Visual Studio 2010
> and MinGW, and they appear to work in my tests. ?I've attached the
> revised patch.
>
> If there are any questions or problems, please let me know.
LGTM

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From baldrick at free.fr  Tue Aug 16 13:25:17 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 16 Aug 2011 20:25:17 +0200
Subject: [llvm-commits] [llvm] r137642 -
	/llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
Message-ID: <4E4AB60D.2090707@free.fr>

Hi John,

On 16/08/11 19:32, John McCall wrote:
> On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>>> The "landingpad" instruction will never be "trivially" dead.
>>
>> since mayHaveSideEffects() should return true for a landingpad instruction,
>> this shouldn't be needed: isInstructionTriviallyDead should already return
>> false.
>
> I don't understand where you and Bill are going with this.  landingpad
> does not have side-effects, not does it read or write "visible" memory.

mayReadMemory isn't only about reading visible memory.  The fact that the
landing pad instruction manages to return (typically) a different exception
object each time it executes is enough to put it in the mayReadMemory camp.
That said, I'm not so hot about stating that it writes memory, since
semantically it doesn't (unlike reading memory).  However it seems more
convenient to artificially say it writes memory, or has side-effects,
rather than add special case landing pad logic all over the place to
get much the same effect.

> I'm aware that SjLj's lowering involves memory accesses, but it's to
> unaliased, private memory.

I agree with this.
>
> I guess it's okay, if a bit weird and unfortunate, to describe landingpad
> as having side-effects in order to get various optimizations to do the
> right thing without custom modification.  But if that's what you're doing,
> you should document it that way.  In the abstract machine, landingpad
> has no side-effects and does not access memory.

As mentioned above, semantically it does access memory.  Otherwise it would
be like a readnone function call, returning the same value every time.  But
it doesn't return the same value every time.  Ergo it reads memory.

Ciao, Duncan.

From grosbach at apple.com  Tue Aug 16 13:31:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 18:31:36 -0000
Subject: [llvm-commits] [llvm] r137734 -
	/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
Message-ID: <20110816183136.6BAB32A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 13:31:36 2011
New Revision: 137734

URL: http://llvm.org/viewvc/llvm-project?rev=137734&view=rev
Log:
Remove unused forward declaration.

Modified:
    llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h

Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=137734&r1=137733&r2=137734&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Tue Aug 16 13:31:36 2011
@@ -17,7 +17,6 @@
 namespace llvm {
 class MCAsmLexer;
 class MCInst;
-class Target;
 
 /// AsmToken - Target independent representation for an assembler token.
 class AsmToken {



From grosbach at apple.com  Tue Aug 16 13:33:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 18:33:50 -0000
Subject: [llvm-commits] [llvm] r137735 - in /llvm/trunk:
 include/llvm/MC/MCParser/MCAsmParser.h
 lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
 lib/MC/MCDisassembler/EDDisassembler.cpp lib/MC/MCParser/AsmParser.cpp
 tools/llvm-mc/llvm-mc.cpp tools/lto/LTOModule.cpp
Message-ID: <20110816183350.326BC2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 13:33:49 2011
New Revision: 137735

URL: http://llvm.org/viewvc/llvm-project?rev=137735&view=rev
Log:
Remove unused Target argument from AsmParser construction methods.

The argument is unused, and is a layering violation in any case.

Modified:
    llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
    llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp
    llvm/trunk/tools/lto/LTOModule.cpp

Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Tue Aug 16 13:33:49 2011
@@ -24,7 +24,6 @@
 class SMLoc;
 class SourceMgr;
 class StringRef;
-class Target;
 class Twine;
 
 /// MCAsmParser - Generic assembler parser interface, for use by target specific
@@ -131,7 +130,7 @@
 };
 
 /// \brief Create an MCAsmParser instance.
-MCAsmParser *createMCAsmParser(const Target &, SourceMgr &, MCContext &,
+MCAsmParser *createMCAsmParser(SourceMgr &, MCContext &,
                                MCStreamer &, const MCAsmInfo &);
 
 } // End llvm namespace

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Tue Aug 16 13:33:49 2011
@@ -109,7 +109,7 @@
   // Tell SrcMgr about this buffer, it takes ownership of the buffer.
   SrcMgr.AddNewSourceBuffer(Buffer, SMLoc());
 
-  OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr,
+  OwningPtr<MCAsmParser> Parser(createMCAsmParser(SrcMgr,
                                                   OutContext, OutStreamer,
                                                   *MAI));
 

Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Tue Aug 16 13:33:49 2011
@@ -362,7 +362,7 @@
   sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
   MCContext context(*AsmInfo, *MRI, NULL);
   OwningPtr<MCStreamer> streamer(createNullStreamer(context));
-  OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr,
+  OwningPtr<MCAsmParser> genericParser(createMCAsmParser(sourceMgr,
                                                          context, *streamer,
                                                          *AsmInfo));
 

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Tue Aug 16 13:33:49 2011
@@ -116,7 +116,7 @@
   unsigned HadError : 1;
 
 public:
-  AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
+  AsmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
             const MCAsmInfo &MAI);
   ~AsmParser();
 
@@ -338,7 +338,7 @@
 
 enum { DEFAULT_ADDRSPACE = 0 };
 
-AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx,
+AsmParser::AsmParser(SourceMgr &_SM, MCContext &_Ctx,
                      MCStreamer &_Out, const MCAsmInfo &_MAI)
   : Lexer(_MAI), Ctx(_Ctx), Out(_Out), MAI(_MAI), SrcMgr(_SM),
     GenericParser(new GenericAsmParser), PlatformParser(0),
@@ -2713,8 +2713,8 @@
 
 
 /// \brief Create an MCAsmParser instance.
-MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM,
+MCAsmParser *llvm::createMCAsmParser(SourceMgr &SM,
                                      MCContext &C, MCStreamer &Out,
                                      const MCAsmInfo &MAI) {
-  return new AsmParser(T, SM, C, Out, MAI);
+  return new AsmParser(SM, C, Out, MAI);
 }

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Aug 16 13:33:49 2011
@@ -413,8 +413,8 @@
     Str.reset(createLoggingStreamer(Str.take(), errs()));
   }
 
-  OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
-                                                   *Str.get(), *MAI));
+  OwningPtr<MCAsmParser> Parser(createMCAsmParser(SrcMgr, Ctx,
+                                                  *Str.get(), *MAI));
   OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(*STI, *Parser));
   if (!TAP) {
     errs() << ProgName

Modified: llvm/trunk/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=137735&r1=137734&r2=137735&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.cpp (original)
+++ llvm/trunk/tools/lto/LTOModule.cpp Tue Aug 16 13:33:49 2011
@@ -619,7 +619,7 @@
   MemoryBuffer *Buffer = MemoryBuffer::getMemBuffer(inlineAsm);
   SourceMgr SrcMgr;
   SrcMgr.AddNewSourceBuffer(Buffer, SMLoc());
-  OwningPtr<MCAsmParser> Parser(createMCAsmParser(_target->getTarget(), SrcMgr,
+  OwningPtr<MCAsmParser> Parser(createMCAsmParser(SrcMgr,
                                                   Context, *Streamer,
                                                   *_target->getMCAsmInfo()));
   OwningPtr<MCSubtargetInfo> STI(_target->getTarget().



From wendling at apple.com  Tue Aug 16 13:38:15 2011
From: wendling at apple.com (Bill Wendling)
Date: Tue, 16 Aug 2011 11:38:15 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <4E4AB60D.2090707@free.fr>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
Message-ID: <9DCF66C6-EEAC-4867-AB0D-68D15CD9F34B@apple.com>

On Aug 16, 2011, at 11:25 AM, Duncan Sands wrote:

> Hi John,
> 
> On 16/08/11 19:32, John McCall wrote:
>> On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>>>> The "landingpad" instruction will never be "trivially" dead.
>>> 
>>> since mayHaveSideEffects() should return true for a landingpad instruction,
>>> this shouldn't be needed: isInstructionTriviallyDead should already return
>>> false.
>> 
>> I don't understand where you and Bill are going with this.  landingpad
>> does not have side-effects, not does it read or write "visible" memory.
> 
> mayReadMemory isn't only about reading visible memory.  The fact that the
> landing pad instruction manages to return (typically) a different exception
> object each time it executes is enough to put it in the mayReadMemory camp.
> That said, I'm not so hot about stating that it writes memory, since
> semantically it doesn't (unlike reading memory).  However it seems more
> convenient to artificially say it writes memory, or has side-effects,
> rather than add special case landing pad logic all over the place to
> get much the same effect.
> 
>> I'm aware that SjLj's lowering involves memory accesses, but it's to
>> unaliased, private memory.
> 
> I agree with this.
>> 
>> I guess it's okay, if a bit weird and unfortunate, to describe landingpad
>> as having side-effects in order to get various optimizations to do the
>> right thing without custom modification.  But if that's what you're doing,
>> you should document it that way.  In the abstract machine, landingpad
>> has no side-effects and does not access memory.
> 
> As mentioned above, semantically it does access memory.  Otherwise it would
> be like a readnone function call, returning the same value every time.  But
> it doesn't return the same value every time.  Ergo it reads memory.
> 
I convinced myself that Duncan was correct with roughly his arguments here. And also that the landingpad is expressing values gotten from an external code path, which obviously reads and writes memory. Marking it thus is not incorrect in that view.

-bw



From rjmccall at apple.com  Tue Aug 16 13:43:19 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 16 Aug 2011 11:43:19 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <4E4AB60D.2090707@free.fr>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
Message-ID: <E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>


On Aug 16, 2011, at 11:25 AM, Duncan Sands wrote:

> Hi John,
> 
> On 16/08/11 19:32, John McCall wrote:
>> On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>>>> The "landingpad" instruction will never be "trivially" dead.
>>> 
>>> since mayHaveSideEffects() should return true for a landingpad instruction,
>>> this shouldn't be needed: isInstructionTriviallyDead should already return
>>> false.
>> 
>> I don't understand where you and Bill are going with this.  landingpad
>> does not have side-effects, not does it read or write "visible" memory.
> 
> mayReadMemory isn't only about reading visible memory.  The fact that the
> landing pad instruction manages to return (typically) a different exception
> object each time it executes is enough to put it in the mayReadMemory camp.
> That said, I'm not so hot about stating that it writes memory, since
> semantically it doesn't (unlike reading memory).  However it seems more
> convenient to artificially say it writes memory, or has side-effects,
> rather than add special case landing pad logic all over the place to
> get much the same effect.

I'm skeptical that there's really a common abstraction here.  landingpad
instructions, by their nature, must be immune to code motion optimizations.
However, they are never read or write hazards.  What other instruction
behaves this way?  It's closest to a phi.  Does a phi "read memory"?  The
question doesn't really make sense ? anyone asking the question
probably just needs to know specifically that it's dealing with a phi.

I understand that some clients will not need special logic if you just
make landingpad claim to have arbitrary side-effects, but that has
costs, too, like decreasing the potential for optimization of any code
with EH in it.  And it's not like you don't have to specifically consider
landingpad instructions for each and every case anyway, because of
the special placement restrictions.

John.

From resistor at mac.com  Tue Aug 16 13:44:30 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 16 Aug 2011 11:44:30 -0700
Subject: [llvm-commits] [PATCH] Enhance ARMDisassembler to
	report	UNPREDICTABLE insns as soft errors
In-Reply-To: <003601cc5bf5$712dbdc0$53893940$%molloy@arm.com>
References: <003601cc5bf5$712dbdc0$53893940$%molloy@arm.com>
Message-ID: <8A075D8D-31BF-4073-9C31-BC843CD1A727@mac.com>

Hi James,

My 2? are that I think it makes sense to expose DecodeStatus as part of MCDisassembler.  I don't know that any other targets use it offhand, but a "plausible but illegal" soft failure is at least a conceptually target-independent result.  Then we could just change the return type of getInstruction() to return a DecodeStatus.  At worst, ARM can be the only target that returns an Unpredictable result in practice.

I suspect going this way will simplify the implementation (you'll get rid of at least one of the FixedLenDecoderEmitter parameters) without complicating other targets.   Does anyone else with an interest in the MCDisassembler care?

Other than that decision, which we should resolve one way or another before applying it, you patch looks great.

--Owen

On Aug 16, 2011, at 2:18 AM, James Molloy wrote:

> Hi,
>  
> As discussed on llvm-dev recently, this patch adds support for ?soft-failing? on disassembly of certain ARM instructions.
>  
> Certain instructions are marked as ?UNPREDICTABLE? in the ARMARM ? the disassembly of these instructions may still have value however, especially to a debugger or debugging code generated by another toolchain.
>  
> This patch promotes the return value of all Decode* operations in the ARM disassembly to a ternary value (Success, Unpredictable, Fail) and touches a lot of the error handling code to perform status demotion from Success to Unpredictable, and returning early on Fail. It also touches the FixedLenDecoderEmitter to facilitate the same changes in autogenerated code.
>  
> The major changelist is:
> ?         Add a new type ?DecodeStatus?, local to ARMDisassembler.cpp, and add a macro CHECK(S, X) that will possibly demote a DecodeStatus S based on a function X?s return value, and exit early if the value becomes ?Fail?.
> ?         Modify the return value of Decode* from bool to ?DecodeStatus?, modify ?if(!X()) return false;? to ?CHECK(S, X());?, assuming a local accumulator ?DecodeStatus S = Success;?.
> ?         Parameterise FixedLenDecoderEmitter to take as extra (optional) arguments:
> o   The return value of the functions to emit (default ?bool?)
> o    ?Guard? prefix and postfix to wrap any function call that may fail (default ?if (!? and ?) return false;? respectively)
> o   Value to return if everything went OK (default ?true?)
> o   Value to return on failure (default ?false?)
> o   Any extra local variables to add (default ??)
> ?         These defaults maintain the current behaviour of FixedLenDecoderEmitter. ARM/Thumb has been special cased in DisassemblerEmitter.cpp.
>  
> The patch as is does not change the user-seen behaviour of the disassembler at all. I?m still not sure the best way to expose this information to the user.
>  
> AFAIK, Intel or most other architectures don't have the same concept as ARM of a valid but unpredictable instruction. I'm therefore fearful of changing MCDisassembler.h to cope with it. At the moment I have an alternate getInstruction() function that also takes a bool& to which it writes if the insn was predictable or not.
>  
> The problem with this obviously is that it requires the user to #include <ARMDisassembler.h>, which is impossible in the general case as it is a hidden header.
>  
> I can see three options, none of which being particularly elegant:
>  
> ?         Make ARMDisassembler.h a public header so the user can cast<ARMDisassembler> and access an alternate getInstruction() function.
> ?         Add a bool* parameter to getInstruction() for UNPREDICTABLE; default is NULL and the other backends ignore it.
> ?         Add an "wasInsnUnpredictable()" function to MCDisassembler, which returns false for all other backends and only the ARM backend deals with. Nastily non-reentrant.
> ?         ??? An alternative.
>  
> What would you suggest?
>  
> Cheers,
>  
> James
> <unpredictable.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From dnicacios at gmail.com  Tue Aug 16 13:54:41 2011
From: dnicacios at gmail.com (=?ISO-8859-1?Q?Daniel_Nic=E1cio?=)
Date: Tue, 16 Aug 2011 11:54:41 -0700
Subject: [llvm-commits] [PATCH] AndOrXor Chain Optimization
In-Reply-To: <CADP2NNFmqxxVnkKv76WVZUsb++RafadtWm6vWnYSGded_kVC5A@mail.gmail.com>
References: <CADP2NNELWKQPdzH+MH1d1w-nFUf_vGrbKqzK4DT5mODsEkw23A@mail.gmail.com>
	<CAJdarcF_iToH1Ckn48WnnvLSry-y39RnEKZqseeV6whkk9qNXA@mail.gmail.com>
	<CADP2NNFmqxxVnkKv76WVZUsb++RafadtWm6vWnYSGded_kVC5A@mail.gmail.com>
Message-ID: <CADP2NNE8e3E9x3_PBC7de7V8mC3RM3u65ZU_a2Hb=KrFf_AEoQ@mail.gmail.com>

ping

Updated patch with revision 137728

2011/8/5 Daniel Nic?cio <dnicacios at gmail.com>

> New unified diff file attached.
>
> Daniel Nicacio
>
>
> 2011/8/4 Eli Friedman <eli.friedman at gmail.com>
>
>> 2011/8/4 Daniel Nic?cio <dnicacios at gmail.com>
>>
>>>  Hi, this patch increments the instcombiner pass.
>>> It adds a new XOR, OR, AND optimization, trying to find a chain of
>>> logical instructions (xor, and, or) operating on different bits of the same
>>> word. If this chain is found, it is collapsed into a single logical
>>> instruction.
>>> The figure below shows a generic example:
>>>
>>> Any comments and critics are welcome.
>>>
>>
>> Please attach a single diff containing all the changes, and please use
>> "svn diff" or some other tool that makes a unified diff.
>>
>> -Eli
>>
>
>
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From James.Molloy at arm.com  Tue Aug 16 13:56:12 2011
From: James.Molloy at arm.com (James Molloy)
Date: Tue, 16 Aug 2011 19:56:12 +0100
Subject: [llvm-commits] [PATCH] Enhance ARMDisassembler to
	report	UNPREDICTABLE insns as soft errors
In-Reply-To: <8A075D8D-31BF-4073-9C31-BC843CD1A727@mac.com>
References: <003601cc5bf5$712dbdc0$53893940$%molloy@arm.com>,
	<8A075D8D-31BF-4073-9C31-BC843CD1A727@mac.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133D6@GEORGE.Emea.Arm.com>

Hi Owen,

Thanks. That does seem the most logical thing to do - I suppose I'm just used to open source projects where changing an abstraction can lead to violent uproar on mailing lists :)

I'll wait for anyone to pipe up about the MCDisassembler change then adapt my patch.

Thanks,

James
________________________________________
From: Owen Anderson [resistor at mac.com]
Sent: 16 August 2011 19:44
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Enhance ARMDisassembler to report   UNPREDICTABLE insns as soft errors

Hi James,

My 2? are that I think it makes sense to expose DecodeStatus as part of MCDisassembler.  I don't know that any other targets use it offhand, but a "plausible but illegal" soft failure is at least a conceptually target-independent result.  Then we could just change the return type of getInstruction() to return a DecodeStatus.  At worst, ARM can be the only target that returns an Unpredictable result in practice.

I suspect going this way will simplify the implementation (you'll get rid of at least one of the FixedLenDecoderEmitter parameters) without complicating other targets.   Does anyone else with an interest in the MCDisassembler care?

Other than that decision, which we should resolve one way or another before applying it, you patch looks great.

--Owen

On Aug 16, 2011, at 2:18 AM, James Molloy wrote:

Hi,

As discussed on llvm-dev recently, this patch adds support for ?soft-failing? on disassembly of certain ARM instructions.

Certain instructions are marked as ?UNPREDICTABLE? in the ARMARM ? the disassembly of these instructions may still have value however, especially to a debugger or debugging code generated by another toolchain.

This patch promotes the return value of all Decode* operations in the ARM disassembly to a ternary value (Success, Unpredictable, Fail) and touches a lot of the error handling code to perform status demotion from Success to Unpredictable, and returning early on Fail. It also touches the FixedLenDecoderEmitter to facilitate the same changes in autogenerated code.

The major changelist is:
?         Add a new type ?DecodeStatus?, local to ARMDisassembler.cpp, and add a macro CHECK(S, X) that will possibly demote a DecodeStatus S based on a function X?s return value, and exit early if the value becomes ?Fail?.
?         Modify the return value of Decode* from bool to ?DecodeStatus?, modify ?if(!X()) return false;? to ?CHECK(S, X());?, assuming a local accumulator ?DecodeStatus S = Success;?.
?         Parameterise FixedLenDecoderEmitter to take as extra (optional) arguments:
o   The return value of the functions to emit (default ?bool?)
o    ?Guard? prefix and postfix to wrap any function call that may fail (default ?if (!? and ?) return false;? respectively)
o   Value to return if everything went OK (default ?true?)
o   Value to return on failure (default ?false?)
o   Any extra local variables to add (default ??)
?         These defaults maintain the current behaviour of FixedLenDecoderEmitter. ARM/Thumb has been special cased in DisassemblerEmitter.cpp.

The patch as is does not change the user-seen behaviour of the disassembler at all. I?m still not sure the best way to expose this information to the user.

AFAIK, Intel or most other architectures don't have the same concept as ARM of a valid but unpredictable instruction. I'm therefore fearful of changing MCDisassembler.h to cope with it. At the moment I have an alternate getInstruction() function that also takes a bool& to which it writes if the insn was predictable or not.

The problem with this obviously is that it requires the user to #include <ARMDisassembler.h>, which is impossible in the general case as it is a hidden header.

I can see three options, none of which being particularly elegant:

?         Make ARMDisassembler.h a public header so the user can cast<ARMDisassembler> and access an alternate getInstruction() function.
?         Add a bool* parameter to getInstruction() for UNPREDICTABLE; default is NULL and the other backends ignore it.
?         Add an "wasInsnUnpredictable()" function to MCDisassembler, which returns false for all other backends and only the ARM backend deals with. Nastily non-reentrant.
?         ??? An alternative.

What would you suggest?

Cheers,

James
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From criswell at illinois.edu  Tue Aug 16 14:00:47 2011
From: criswell at illinois.edu (John Criswell)
Date: Tue, 16 Aug 2011 14:00:47 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/footer.incl
In-Reply-To: <201108161609.p7GG9Z22021781@maute.cs.uiuc.edu>
References: <201108161609.p7GG9Z22021781@maute.cs.uiuc.edu>
Message-ID: <4E4ABE5F.3060503@illinois.edu>

Dear All,

Sorry for the non-LLVM project commit.  This web page happens to be in 
the same CVS repository as the old LLVM web site, so commits are still 
auto-emailed to llvm-commits.

I'm moving our web sites over to various Subversion repositories, so 
changes to this web site won't be showing up here anymore.

-- John T.

On 8/16/11 11:09 AM, John Criswell wrote:
>
> Changes in directory llvm-www/safecode/menagerie:
>
> footer.incl updated: 1.3 ->  1.4
> ---
> Log message:
>
> Updated copyright year to 2011.
>
>
> ---
> Diffs of the changes:  (+1 -1)
>
>   footer.incl |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
>
> Index: llvm-www/safecode/menagerie/footer.incl
> diff -u llvm-www/safecode/menagerie/footer.incl:1.3 llvm-www/safecode/menagerie/footer.incl:1.4
> --- llvm-www/safecode/menagerie/footer.incl:1.3	Fri Jun 25 11:50:28 2010
> +++ llvm-www/safecode/menagerie/footer.incl	Tue Aug 16 11:08:53 2011
> @@ -1,7 +1,7 @@
>   <!-- footer starts here -->
>   <div class="footer">
>     <p>	
> -&copy; 2010<a href="http://www.illinois.edu">University of Illinois</a>
> +&copy; 2010-2011<a href="http://www.illinois.edu">University of Illinois</a>
>     &nbsp;&nbsp;&nbsp;&nbsp;
>
>     <a href="http://www.bluewebtemplates.com/" title="Website Templates">website templates</a>  by<a href="http://www.styleshout.com/">styleshout</a>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From wendling at apple.com  Tue Aug 16 14:04:57 2011
From: wendling at apple.com (Bill Wendling)
Date: Tue, 16 Aug 2011 12:04:57 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
	<E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
Message-ID: <CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>

On Aug 16, 2011, at 11:43 AM, John McCall wrote:
> On Aug 16, 2011, at 11:25 AM, Duncan Sands wrote:
>> On 16/08/11 19:32, John McCall wrote:
>>> On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>>>>> The "landingpad" instruction will never be "trivially" dead.
>>>> 
>>>> since mayHaveSideEffects() should return true for a landingpad instruction,
>>>> this shouldn't be needed: isInstructionTriviallyDead should already return
>>>> false.
>>> 
>>> I don't understand where you and Bill are going with this.  landingpad
>>> does not have side-effects, not does it read or write "visible" memory.
>> 
>> mayReadMemory isn't only about reading visible memory.  The fact that the
>> landing pad instruction manages to return (typically) a different exception
>> object each time it executes is enough to put it in the mayReadMemory camp.
>> That said, I'm not so hot about stating that it writes memory, since
>> semantically it doesn't (unlike reading memory).  However it seems more
>> convenient to artificially say it writes memory, or has side-effects,
>> rather than add special case landing pad logic all over the place to
>> get much the same effect.
> 
> I'm skeptical that there's really a common abstraction here.  landingpad
> instructions, by their nature, must be immune to code motion optimizations.
> However, they are never read or write hazards.  What other instruction
> behaves this way?  It's closest to a phi.  Does a phi "read memory"?  The
> question doesn't really make sense ? anyone asking the question
> probably just needs to know specifically that it's dealing with a phi.
> 
> I understand that some clients will not need special logic if you just
> make landingpad claim to have arbitrary side-effects, but that has
> costs, too, like decreasing the potential for optimization of any code
> with EH in it.  And it's not like you don't have to specifically consider
> landingpad instructions for each and every case anyway, because of
> the special placement restrictions.
> 

It may be close to a PHI node, but it's not the same. The PHI node has a specific definition and semantics in SSA form. By definition, it doesn't read or write memory. The landingpad instruction is trying to embody all of what happens on the edge between the invoke and the landing pad. Some of those events do read and write memory. We're still allowed to move instructions which may read from or write to memory around, it just requires a bit of extra care. As it is, the instructions which can be moved into the landing pad past the landingpad instruction are rather light-weight instructions which don't read from memory anyway (this is because they're being sunk below an invoke). I'm skeptical that this will adversely affect optimizations for most code.

-bw



From krasin at google.com  Tue Aug 16 14:14:51 2011
From: krasin at google.com (Ivan Krasin)
Date: Tue, 16 Aug 2011 12:14:51 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
Message-ID: <CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>

Eric,

could you please take another look?

Ivan

On Mon, Aug 15, 2011 at 2:29 PM, Ivan Krasin <krasin at google.com> wrote:
> On Thu, Aug 11, 2011 at 3:20 PM, Eric Christopher <echristo at apple.com> wrote:
>>
>> On Aug 10, 2011, at 4:01 PM, Ivan Krasin wrote:
>>
>> <flush-local-value-map.patch>
>>
>> In general I think the patch is OK. ?A few requests:
>> ? ?MachineInstr *LastLocalValue;
>> + ?MachineInstr *OrigLocalValue;
>> ?.
>> ? ?// Start out as null, meaining no local-value instructions have
>> ? ?// been emitted.
>> - ?LastLocalValue = 0;
>> + ?OrigLocalValue = 0;
>> A lot of the code you've changed hasn't had any comments written or updated
>> for the new behavior. It'd be good to get an updated description of how the
>> LocalValueMap is working and how it interacts with constants.
> I have renamed OrigLocalValue to EmitStartPt which is (I believe) less
> confusing naming, since it points to the place in the block where it's
> allowed to start emitting instructions.
>
>> In particular:
>> + ?if (!isa<IntrinsicInst>(F))
>> + ? ?flushLocalValueMap();
>> +
>> Here. The location of this here doesn't make a whole lot of sense and it'd
>> be good if you could explain it.
> I've added the explanation. Thanks for the suggestion.
>
>> A better way to do this would be, as Jakob suggested, use the LocalValueMap
>> as a storage for constants and locations that you've used them in the block
>> and then emit all of the constants at that point rather than this weird
>> flushing mechanism.
> I've tried to do that. It slows down -O0 build which is unacceptable.
> The problem is that we have to emit all local values to the start of
> the block, store last use for each of them and spread them through the
> block once the processing of the block is done. It makes it slower...
> So, I would prefer to stay with the patch that makes all the metrics
> slightly better on average (code size/stack size/compile time). Is it
> fine with you?
>
> Please, find the updated patch attached.
>
> Ivan Krasin
>
>> -eric
>


From rjmccall at apple.com  Tue Aug 16 15:06:29 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 16 Aug 2011 13:06:29 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
	<E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
	<CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>
Message-ID: <E4C3B135-C7D4-43DB-81C2-94D03CDFA287@apple.com>


On Aug 16, 2011, at 12:04 PM, Bill Wendling wrote:

> On Aug 16, 2011, at 11:43 AM, John McCall wrote:
>> On Aug 16, 2011, at 11:25 AM, Duncan Sands wrote:
>>> On 16/08/11 19:32, John McCall wrote:
>>>> On Aug 15, 2011, at 11:44 PM, Duncan Sands wrote:
>>>>>> The "landingpad" instruction will never be "trivially" dead.
>>>>> 
>>>>> since mayHaveSideEffects() should return true for a landingpad instruction,
>>>>> this shouldn't be needed: isInstructionTriviallyDead should already return
>>>>> false.
>>>> 
>>>> I don't understand where you and Bill are going with this.  landingpad
>>>> does not have side-effects, not does it read or write "visible" memory.
>>> 
>>> mayReadMemory isn't only about reading visible memory.  The fact that the
>>> landing pad instruction manages to return (typically) a different exception
>>> object each time it executes is enough to put it in the mayReadMemory camp.
>>> That said, I'm not so hot about stating that it writes memory, since
>>> semantically it doesn't (unlike reading memory).  However it seems more
>>> convenient to artificially say it writes memory, or has side-effects,
>>> rather than add special case landing pad logic all over the place to
>>> get much the same effect.
>> 
>> I'm skeptical that there's really a common abstraction here.  landingpad
>> instructions, by their nature, must be immune to code motion optimizations.
>> However, they are never read or write hazards.  What other instruction
>> behaves this way?  It's closest to a phi.  Does a phi "read memory"?  The
>> question doesn't really make sense ? anyone asking the question
>> probably just needs to know specifically that it's dealing with a phi.
>> 
>> I understand that some clients will not need special logic if you just
>> make landingpad claim to have arbitrary side-effects, but that has
>> costs, too, like decreasing the potential for optimization of any code
>> with EH in it.  And it's not like you don't have to specifically consider
>> landingpad instructions for each and every case anyway, because of
>> the special placement restrictions.
>> 
> 
> It may be close to a PHI node, but it's not the same.

I'm not saying it's exactly like a PHI node, I'm saying it has the same
property of not having a meaningful response to mayReadMemory().

> The landingpad instruction is trying to embody all of what happens on the edge between the invoke and the landing pad. Some of those events do read and write memory.

This is not an appropriate way of thinking about the instruction.  What
happens during unwinding inheres to the abnormal edge out of a call,
regardless of whether there's a landing pad or whether that landing
pad is actually visited during unwinding.

This is exactly the sort of thing that makes me think that hacking
mayReadMemory() is not the appropriate solution.

> We're still allowed to move instructions which may read from or write to memory around, it just requires a bit of extra care. As it is, the instructions which can be moved into the landing pad past the landingpad instruction are rather light-weight instructions which don't read from memory anyway (this is because they're being sunk below an invoke). I'm skeptical that this will adversely affect optimizations for most code.

I'm mostly worried that you're trying to get around doing the actual
correctness work by making general routines inhibit optimization
in all the cases you can think of off the top of your head.

John.

From grosbach at apple.com  Tue Aug 16 15:12:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 20:12:36 -0000
Subject: [llvm-commits] [llvm] r137742 -
	/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
Message-ID: <20110816201236.2A04D2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 15:12:35 2011
New Revision: 137742

URL: http://llvm.org/viewvc/llvm-project?rev=137742&view=rev
Log:
Prefer diagnostics from target predicate in asm matcher.

Modified:
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=137742&r1=137741&r2=137742&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Aug 16 15:12:35 2011
@@ -2349,6 +2349,7 @@
 
   OS << "  // Some state to try to produce better error messages.\n";
   OS << "  bool HadMatchOtherThanFeatures = false;\n";
+  OS << "  bool HadMatchOtherThanPredicate = false;\n";
   OS << "  unsigned RetCode = Match_InvalidOperand;\n";
   OS << "  // Set ErrorInfo to the operand that mismatches if it is\n";
   OS << "  // wrong for all instances of the instruction.\n";
@@ -2413,6 +2414,7 @@
      << " Match_Success) {\n"
      << "      Inst.clear();\n"
      << "      RetCode = MatchResult;\n"
+     << "      HadMatchOtherThanPredicate = true;\n"
      << "      continue;\n"
      << "    }\n\n";
 
@@ -2426,8 +2428,9 @@
   OS << "  }\n\n";
 
   OS << "  // Okay, we had no match.  Try to return a useful error code.\n";
-  OS << "  if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
-  OS << "  return RetCode;\n";
+  OS << "  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)";
+  OS << " return RetCode;\n";
+  OS << "  return Match_MissingFeature;\n";
   OS << "}\n\n";
 
   if (Info.OperandMatchInfo.size())



From wendling at apple.com  Tue Aug 16 15:22:42 2011
From: wendling at apple.com (Bill Wendling)
Date: Tue, 16 Aug 2011 13:22:42 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <E4C3B135-C7D4-43DB-81C2-94D03CDFA287@apple.com>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
	<E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
	<CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>
	<E4C3B135-C7D4-43DB-81C2-94D03CDFA287@apple.com>
Message-ID: <3662CABE-D544-4DBF-A000-DF50662BAEB9@apple.com>

On Aug 16, 2011, at 1:06 PM, John McCall wrote:

>> The landingpad instruction is trying to embody all of what happens on the edge between the invoke and the landing pad. Some of those events do read and write memory.
> 
> This is not an appropriate way of thinking about the instruction.  What
> happens during unwinding inheres to the abnormal edge out of a call,
> regardless of whether there's a landing pad or whether that landing
> pad is actually visited during unwinding.
> 
> This is exactly the sort of thing that makes me think that hacking
> mayReadMemory() is not the appropriate solution.
> 
I disagree. I think it's appropriate to think of this instruction as embodying the events that happen along the abnormal edge. If you consider a regular call, it's used without regard to whether the call may actually return or whether an exception will cause the program to continue at a function up the call stack. The landingpad is analogous.

>> We're still allowed to move instructions which may read from or write to memory around, it just requires a bit of extra care. As it is, the instructions which can be moved into the landing pad past the landingpad instruction are rather light-weight instructions which don't read from memory anyway (this is because they're being sunk below an invoke). I'm skeptical that this will adversely affect optimizations for most code.
> 
> I'm mostly worried that you're trying to get around doing the actual
> correctness work by making general routines inhibit optimization
> in all the cases you can think of off the top of your head.
> 
John, I have thought about this carefully, and this isn't a decision I made without consideration. I appreciate your concern about marking these instructions as reading/writing memory. I simply don't share it. I'm not trying to get around correctness work.

-bw


From isanbard at gmail.com  Tue Aug 16 15:41:17 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 20:41:17 -0000
Subject: [llvm-commits] [llvm] r137743 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20110816204117.6A5102A6C12C@llvm.org>

Author: void
Date: Tue Aug 16 15:41:17 2011
New Revision: 137743

URL: http://llvm.org/viewvc/llvm-project?rev=137743&view=rev
Log:
I think there was some confusion about what I meant. :-) Replacing the comment.


Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=137743&r1=137742&r2=137743&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Aug 16 15:41:17 2011
@@ -2266,7 +2266,10 @@
                  !isa<LandingPadInst>(BBI)) {
         break;
       }
-      // FIXME: Handling of LandingPadInst (landingpad) is suspicious.
+      // Note that deleting LandingPad's here is in fact okay, although it
+      // involves a bit of subtle reasoning. If this inst is a LandingPad,
+      // all the predecessors of this block will be the unwind edges of Invokes,
+      // and we can therefore guarantee this block will be erased.
     }
 
     // Delete this instruction (any uses are guaranteed to be dead)



From isanbard at gmail.com  Tue Aug 16 15:42:53 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 20:42:53 -0000
Subject: [llvm-commits] [llvm] r137744 - in /llvm/trunk:
 include/llvm/BasicBlock.h lib/VMCore/BasicBlock.cpp
Message-ID: <20110816204253.162F22A6C12C@llvm.org>

Author: void
Date: Tue Aug 16 15:42:52 2011
New Revision: 137744

URL: http://llvm.org/viewvc/llvm-project?rev=137744&view=rev
Log:
Add getFirstInsertionPt() method.

getFirstInsertionPt() returns an iterator to the first insertion point in a
basic block. This is after all PHIs and any other instruction which is required
to be at the top of the basic block (like LandingPadInst).

Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/lib/VMCore/BasicBlock.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=137744&r1=137743&r2=137744&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Tue Aug 16 15:42:52 2011
@@ -145,6 +145,15 @@
     return const_cast<BasicBlock*>(this)->getFirstNonPHIOrDbgOrLifetime();
   }
 
+  /// getFirstInsertionPt - Returns an iterator to the first instruction in this
+  /// block that is suitable for inserting a non-PHI instruction. In particular,
+  /// it skips all PHIs and LandingPad instructions. Returns 0 if there are no
+  /// non-PHI instructions.
+  iterator getFirstInsertionPt();
+  const_iterator getFirstInsertionPt() const {
+    return const_cast<BasicBlock*>(this)->getFirstInsertionPt();
+  }
+
   /// removeFromParent - This method unlinks 'this' from the containing
   /// function, but does not delete it.
   ///

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=137744&r1=137743&r2=137744&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Tue Aug 16 15:42:52 2011
@@ -167,6 +167,12 @@
   return &*i;
 }
 
+BasicBlock::iterator BasicBlock::getFirstInsertionPt() {
+  iterator InsertPt = getFirstNonPHI();
+  if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
+  return InsertPt;
+}
+
 void BasicBlock::dropAllReferences() {
   for(iterator I = begin(), E = end(); I != E; ++I)
     I->dropAllReferences();



From isanbard at gmail.com  Tue Aug 16 15:44:29 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 13:44:29 -0700
Subject: [llvm-commits] [llvm] r137712 - in /llvm/trunk/lib:
	Analysis/ScalarEvolutionExpander.cpp
	Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
	Transforms/Instrumentation/GCOVProfiling.cpp
In-Reply-To: <CADbEz-gP8mZqKbQa06Lxz6D3S8VkReKcvhfsffMqY=rKYnxCFQ@mail.gmail.com>
References: <20110816045255.8F40D2A6C12C@llvm.org>
	<CADbEz-gP8mZqKbQa06Lxz6D3S8VkReKcvhfsffMqY=rKYnxCFQ@mail.gmail.com>
Message-ID: <D2F463A7-241F-46C1-BF0C-EB745B785184@gmail.com>

On Aug 16, 2011, at 10:51 AM, Nick Lewycky wrote:
>         // call runtime to perform increment
> -        IRBuilder<> Builder(ComplexEdgeSuccs[i+1]->getFirstNonPHI());
> +        BasicBlock::iterator InsertPt = ComplexEdgeSuccs[i+1]->getFirstNonPHI();
> +        if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
> +        IRBuilder<> Builder(InsertPt);
> 
> How about a method like getFirstNonPHI() but that skips landingpad called getFirstInsertPoint? The comment for such a method would be that it returns the earliest insertpt that does not have an ordering constraint in the IR?
> 
Not a bad idea. :)

-bw



From isanbard at gmail.com  Tue Aug 16 15:45:24 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 20:45:24 -0000
Subject: [llvm-commits] [llvm] r137745 - in /llvm/trunk/lib:
 Analysis/ScalarEvolutionExpander.cpp
 Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
 Transforms/InstCombine/InstructionCombining.cpp
 Transforms/Instrumentation/GCOVProfiling.cpp
 Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20110816204524.6AD7A2A6C12C@llvm.org>

Author: void
Date: Tue Aug 16 15:45:24 2011
New Revision: 137745

URL: http://llvm.org/viewvc/llvm-project?rev=137745&view=rev
Log:
Use the getFirstInsertionPt() method instead of getFirstNonPHI + an 'isa<>'
check for a LandingPadInst.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=137745&r1=137744&r2=137745&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Aug 16 15:45:24 2011
@@ -1323,11 +1323,8 @@
       // If the SCEV is computable at this level, insert it into the header
       // after the PHIs (and after any other instructions that we've inserted
       // there) so that it is guaranteed to dominate any user inside the loop.
-      if (L && SE.hasComputableLoopEvolution(S, L) && !PostIncLoops.count(L)) {
-        InsertPt = L->getHeader()->getFirstNonPHI();
-        if (isa<LandingPadInst>(InsertPt))
-          InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
-      }
+      if (L && SE.hasComputableLoopEvolution(S, L) && !PostIncLoops.count(L))
+        InsertPt = L->getHeader()->getFirstInsertionPt();
       while (isInsertedInstruction(InsertPt) || isa<DbgInfoIntrinsic>(InsertPt))
         InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
       break;

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=137745&r1=137744&r2=137745&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Tue Aug 16 15:45:24 2011
@@ -600,8 +600,7 @@
   
   // Advance to a place where it is safe to insert the new store and
   // insert it.
-  BBI = DestBB->getFirstNonPHI();
-  if (isa<LandingPadInst>(BBI)) ++BBI;
+  BBI = DestBB->getFirstInsertionPt();
   StoreInst *NewSI = new StoreInst(MergedVal, SI.getOperand(1),
                                    SI.isVolatile(),
                                    SI.getAlignment(),

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137745&r1=137744&r2=137745&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue Aug 16 15:45:24 2011
@@ -1435,8 +1435,7 @@
         return false;
   }
 
-  BasicBlock::iterator InsertPos = DestBlock->getFirstNonPHI();
-  if (isa<LandingPadInst>(InsertPos)) ++InsertPos; // Skip landingpad inst.
+  BasicBlock::iterator InsertPos = DestBlock->getFirstInsertionPt();
   I->moveBefore(InsertPos);
   ++NumSunkInst;
   return true;

Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137745&r1=137744&r2=137745&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Tue Aug 16 15:45:24 2011
@@ -505,8 +505,8 @@
       }
       for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
         // call runtime to perform increment
-        BasicBlock::iterator InsertPt = ComplexEdgeSuccs[i+1]->getFirstNonPHI();
-        if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
+        BasicBlock::iterator InsertPt =
+          ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
         IRBuilder<> Builder(InsertPt);
         Value *CounterPtrArray =
             Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137745&r1=137744&r2=137745&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Aug 16 15:45:24 2011
@@ -410,9 +410,7 @@
     CastInst *&InsertedCast = InsertedCasts[UserBB];
 
     if (!InsertedCast) {
-      BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
-      if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
-
+      BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
       InsertedCast =
         CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
                          InsertPt);
@@ -468,8 +466,7 @@
     CmpInst *&InsertedCmp = InsertedCmps[UserBB];
 
     if (!InsertedCmp) {
-      BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
-      if (isa<LandingPadInst>(InsertPt)) ++InsertPt; // Skip landingpad inst.
+      BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
       InsertedCmp =
         CmpInst::Create(CI->getOpcode(),
                         CI->getPredicate(),  CI->getOperand(0),
@@ -561,13 +558,10 @@
           (DVI->getParent() != VI->getParent() || DT->dominates(DVI, VI))) {
         DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI);
         DVI->removeFromParent();
-        if (isa<PHINode>(VI)) {
-          BasicBlock::iterator InsertPt = VI->getParent()->getFirstNonPHI();
-          if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
-          DVI->insertBefore(InsertPt);
-        } else {
+        if (isa<PHINode>(VI))
+          DVI->insertBefore(VI->getParent()->getFirstInsertionPt());
+        else
           DVI->insertAfter(VI);
-        }
         return true;
       }
 
@@ -1063,8 +1057,7 @@
     Instruction *&InsertedTrunc = InsertedTruncs[UserBB];
 
     if (!InsertedTrunc) {
-      BasicBlock::iterator InsertPt = UserBB->getFirstNonPHI();
-      if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
+      BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
       InsertedTrunc = new TruncInst(I, Src->getType(), "", InsertPt);
     }
 



From grosbach at apple.com  Tue Aug 16 15:45:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 20:45:50 -0000
Subject: [llvm-commits] [llvm] r137746 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h test/MC/ARM/mode-switch.s
 test/MC/ARM/nop-thumb-padding.s test/MC/ARM/nop-thumb2-padding.s
Message-ID: <20110816204550.DE94E2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 15:45:50 2011
New Revision: 137746

URL: http://llvm.org/viewvc/llvm-project?rev=137746&view=rev
Log:
ARM thumb assembly parsing for arithmetic flag setting instructions.

Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
    llvm/trunk/test/MC/ARM/mode-switch.s
    llvm/trunk/test/MC/ARM/nop-thumb-padding.s
    llvm/trunk/test/MC/ARM/nop-thumb2-padding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Aug 16 15:45:50 2011
@@ -236,6 +236,10 @@
   Domain D = d;
   bit isUnaryDataProc = 0;
   bit canXformTo16Bit = 0;
+  // The instruction is a 16-bit flag setting Thumb instruction. Used
+  // by the parser to determine whether to require the 'S' suffix on the
+  // mnemonic (when not in an IT block) or preclude it (when in an IT block).
+  bit thumbArithFlagSetting = 0;
 
   // If this is a pseudo instruction, mark it isCodeGenOnly.
   let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
@@ -247,6 +251,7 @@
   let TSFlags{13}    = isUnaryDataProc;
   let TSFlags{14}    = canXformTo16Bit;
   let TSFlags{17-15} = D.Value;
+  let TSFlags{18}    = thumbArithFlagSetting;
 
   let Constraints = cstr;
   let Itinerary = itin;
@@ -895,6 +900,7 @@
   let InOperandList = !con(iops, (ins pred:$p));
   let AsmString = !strconcat(opc, "${s}${p}", asm);
   let Pattern = pattern;
+  let thumbArithFlagSetting = 1;
   list<Predicate> Predicates = [IsThumb, IsThumb1Only];
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 15:45:50 2011
@@ -78,6 +78,9 @@
   bool isThumbOne() const {
     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
   }
+  bool isThumbTwo() const {
+    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
+  }
   void SwitchMode() {
     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
     setAvailableFeatures(FB);
@@ -146,6 +149,10 @@
                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
 
 public:
+  enum ARMMatchResultTy {
+    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY
+  };
+
   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
     : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
     MCAsmParserExtension::Initialize(_Parser);
@@ -160,6 +167,8 @@
                         SmallVectorImpl<MCParsedAsmOperand*> &Operands);
   bool ParseDirective(AsmToken DirectiveID);
 
+  unsigned checkTargetMatchPredicate(MCInst &Inst);
+
   bool MatchAndEmitInstruction(SMLoc IDLoc,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                                MCStreamer &Out);
@@ -2975,6 +2984,44 @@
   }
 }
 
+// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
+// the ARMInsts array) instead. Getting that here requires awkward
+// API changes, though. Better way?
+namespace llvm {
+extern MCInstrDesc ARMInsts[];
+}
+static MCInstrDesc &getInstDesc(unsigned Opcode) {
+  return ARMInsts[Opcode];
+}
+
+unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
+  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
+  // suffix depending on whether they're in an IT block or not.
+  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
+    assert(MCID.hasOptionalDef() &&
+           "optionally flag setting instruction missing optional def operand");
+    assert(MCID.NumOperands == Inst.getNumOperands() &&
+           "operand count mismatch!");
+    // Find the optional-def operand (cc_out).
+    unsigned OpNo;
+    for (OpNo = 0;
+         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
+         ++OpNo)
+      ;
+    // If we're parsing Thumb1, reject it completely.
+    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
+      return Match_MnemonicFail;
+    // If we're parsing Thumb2, which form is legal depends on whether we're
+    // in an IT block.
+    // FIXME: We don't yet do IT blocks, so just always consider it to be
+    // that we aren't in one until we do.
+    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
+      return Match_RequiresITBlock;
+  }
+  return Match_Success;
+}
+
 bool ARMAsmParser::
 MatchAndEmitInstruction(SMLoc IDLoc,
                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
@@ -3013,9 +3060,11 @@
     return Error(ErrorLoc, "invalid operand for instruction");
   }
   case Match_MnemonicFail:
-    return Error(IDLoc, "unrecognized instruction mnemonic");
+    return Error(IDLoc, "invalid instruction");
   case Match_ConversionFail:
     return Error(IDLoc, "unable to convert operands to instruction");
+  case Match_RequiresITBlock:
+    return Error(IDLoc, "instruction only valid inside IT block");
   }
 
   llvm_unreachable("Implement any new match types added!");

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Tue Aug 16 15:45:50 2011
@@ -384,6 +384,12 @@
     // a 16-bit Thumb instruction if certain conditions are met.
     Xform16Bit    = 1 << 14,
 
+    // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
+    // instruction. Used by the parser to determine whether to require the 'S'
+    // suffix on the mnemonic (when not in an IT block) or preclude it (when
+    // in an IT block).
+    ThumbArithFlagSetting = 1 << 18,
+
     //===------------------------------------------------------------------===//
     // Code domain.
     DomainShift   = 15,

Modified: llvm/trunk/test/MC/ARM/mode-switch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mode-switch.s (original)
+++ llvm/trunk/test/MC/ARM/mode-switch.s Tue Aug 16 15:45:50 2011
@@ -4,14 +4,14 @@
 
 .code 16
 
-@ CHECK:	add.w	r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
+@ CHECK: add.w	r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
 	add.w	r0, r0, r1
 
 .code 32
-@ CHECK:	add	r0, r0, r1              @ encoding: [0x01,0x00,0x80,0xe0]
+@ CHECK: add	r0, r0, r1              @ encoding: [0x01,0x00,0x80,0xe0]
 	add	r0, r0, r1
 
 .code 16
-@ CHECK:	add	r0, r0, r1              @ encoding: [0x40,0x18]
-        
-        add     r0, r0, r1
+@ CHECK: adds	r0, r0, r1              @ encoding: [0x40,0x18]
+
+        adds    r0, r0, r1

Modified: llvm/trunk/test/MC/ARM/nop-thumb-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb-padding.s?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-thumb-padding.s Tue Aug 16 15:45:50 2011
@@ -5,8 +5,8 @@
 .thumb_func x
 .code 16
 x:
-      add r0, r1, r2
+      adds r0, r1, r2
       .align 4
-      add r0, r1, r2
+      adds r0, r1, r2
 
 @ CHECK: ('_section_data', '8818c046 c046c046 c046c046 c046c046 8818')

Modified: llvm/trunk/test/MC/ARM/nop-thumb2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-thumb2-padding.s?rev=137746&r1=137745&r2=137746&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-thumb2-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-thumb2-padding.s Tue Aug 16 15:45:50 2011
@@ -5,8 +5,8 @@
 .thumb_func x
 .code 16
 x:
-      add r0, r1, r2
+      adds r0, r1, r2
       .align 4
-      add r0, r1, r2
+      adds r0, r1, r2
 
 @ CHECK: ('_section_data', '881800bf 00bf00bf 00bf00bf 00bf00bf 8818')



From grosbach at apple.com  Tue Aug 16 15:55:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 20:55:41 -0000
Subject: [llvm-commits] [llvm] r137747 -
	/llvm/trunk/test/MC/ARM/mode-switch.s
Message-ID: <20110816205541.56D7C2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 15:55:41 2011
New Revision: 137747

URL: http://llvm.org/viewvc/llvm-project?rev=137747&view=rev
Log:
Tidy up formatting.

Modified:
    llvm/trunk/test/MC/ARM/mode-switch.s

Modified: llvm/trunk/test/MC/ARM/mode-switch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mode-switch.s?rev=137747&r1=137746&r2=137747&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mode-switch.s (original)
+++ llvm/trunk/test/MC/ARM/mode-switch.s Tue Aug 16 15:55:41 2011
@@ -1,17 +1,15 @@
 @ Test ARM / Thumb mode switching with .code
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple armv7-unknown-unknown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding <%s | FileCheck %s
 
 .code 16
-
-@ CHECK: add.w	r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
 	add.w	r0, r0, r1
+@ CHECK: add.w	r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
 
 .code 32
-@ CHECK: add	r0, r0, r1              @ encoding: [0x01,0x00,0x80,0xe0]
 	add	r0, r0, r1
+@ CHECK: add	r0, r0, r1              @ encoding: [0x01,0x00,0x80,0xe0]
 
 .code 16
-@ CHECK: adds	r0, r0, r1              @ encoding: [0x40,0x18]
-
         adds    r0, r0, r1
+@ CHECK: adds	r0, r0, r1              @ encoding: [0x40,0x18]



From dpatel at apple.com  Tue Aug 16 16:00:05 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 16 Aug 2011 21:00:05 -0000
Subject: [llvm-commits] [llvm] r137751 -
	/llvm/trunk/include/llvm/Support/Dwarf.h
Message-ID: <20110816210005.462EF2A6C12C@llvm.org>

Author: dpatel
Date: Tue Aug 16 16:00:05 2011
New Revision: 137751

URL: http://llvm.org/viewvc/llvm-project?rev=137751&view=rev
Log:
Increment debug info version to accommodate upcoming change in debug info node structure.

Modified:
    llvm/trunk/include/llvm/Support/Dwarf.h

Modified: llvm/trunk/include/llvm/Support/Dwarf.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Dwarf.h?rev=137751&r1=137750&r2=137751&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Dwarf.h (original)
+++ llvm/trunk/include/llvm/Support/Dwarf.h Tue Aug 16 16:00:05 2011
@@ -22,7 +22,8 @@
 // Debug info constants.
 
 enum {
-  LLVMDebugVersion = (10 << 16),        // Current version of debug information.
+  LLVMDebugVersion = (11 << 16),        // Current version of debug information.
+  LLVMDebugVersion10 = (10 << 16),      // Constant for version 10.
   LLVMDebugVersion9 = (9 << 16),        // Constant for version 9.
   LLVMDebugVersion8 = (8 << 16),        // Constant for version 8.
   LLVMDebugVersion7 = (7 << 16),        // Constant for version 7.



From dpatel at apple.com  Tue Aug 16 16:03:27 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 16 Aug 2011 21:03:27 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r137753 -
	/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
Message-ID: <20110816210327.1562D2A6C12C@llvm.org>

Author: dpatel
Date: Tue Aug 16 16:03:26 2011
New Revision: 137753

URL: http://llvm.org/viewvc/llvm-project?rev=137753&view=rev
Log:
DIBuilder is moving forward to reduce in memory use by MDNodes. However, DIFactory does not emit debug info in updated form.
Use LLVMDebugVersion10 directly here so that debug info nodes produced by DIFactory do not claim to adhere newer structure.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=137753&r1=137752&r2=137753&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Aug 16 16:03:26 2011
@@ -1474,7 +1474,10 @@
 Constant *DIFactory::GetTagConstant(unsigned TAG) {
   assert((TAG & LLVMDebugVersionMask) == 0 &&
          "Tag too large for debug encoding!");
-  return ConstantInt::get(Type::getInt32Ty(VMContext), TAG | LLVMDebugVersion);
+  // llvm has moved forward. DIFactory does not emit debug info in updated form.
+  // Use LLVMDebugVersion10 directly here.
+  return ConstantInt::get(Type::getInt32Ty(VMContext), 
+                          TAG | LLVMDebugVersion10);
 }
 
 //===----------------------------------------------------------------------===//



From dpatel at apple.com  Tue Aug 16 16:08:03 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 16 Aug 2011 14:08:03 -0700
Subject: [llvm-commits] Fwd: [llvm-gcc-4.2] r137753 -
 /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
References: <20110816210327.1562D2A6C12C@llvm.org>
Message-ID: <02D638C1-3C28-4A8E-AB4D-2F1E3B1B5C50@apple.com>

Dragon-egg developers,

Please apply this patch to dragon-egg also.
Thanks!
-
Devang

Begin forwarded message:

> From: Devang Patel <dpatel at apple.com>
> Date: August 16, 2011 2:03:27 PM PDT
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm-gcc-4.2] r137753 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
> 
> Author: dpatel
> Date: Tue Aug 16 16:03:26 2011
> New Revision: 137753
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137753&view=rev
> Log:
> DIBuilder is moving forward to reduce in memory use by MDNodes. However, DIFactory does not emit debug info in updated form.
> Use LLVMDebugVersion10 directly here so that debug info nodes produced by DIFactory do not claim to adhere newer structure.
> 
> Modified:
>    llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
> 
> Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=137753&r1=137752&r2=137753&view=diff
> ==============================================================================
> --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original)
> +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Aug 16 16:03:26 2011
> @@ -1474,7 +1474,10 @@
> Constant *DIFactory::GetTagConstant(unsigned TAG) {
>   assert((TAG & LLVMDebugVersionMask) == 0 &&
>          "Tag too large for debug encoding!");
> -  return ConstantInt::get(Type::getInt32Ty(VMContext), TAG | LLVMDebugVersion);
> +  // llvm has moved forward. DIFactory does not emit debug info in updated form.
> +  // Use LLVMDebugVersion10 directly here.
> +  return ConstantInt::get(Type::getInt32Ty(VMContext), 
> +                          TAG | LLVMDebugVersion10);
> }
> 
> //===----------------------------------------------------------------------===//
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From grosbach at apple.com  Tue Aug 16 16:11:21 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 21:11:21 -0000
Subject: [llvm-commits] [llvm] r137754 -
	/llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110816211121.8104D2A6C12D@llvm.org>

Author: grosbach
Date: Tue Aug 16 16:11:21 2011
New Revision: 137754

URL: http://llvm.org/viewvc/llvm-project?rev=137754&view=rev
Log:
Add testcase for r137746.

Added:
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Added: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=137754&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (added)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug 16 16:11:21 2011
@@ -0,0 +1,10 @@
+@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+@ Check for various assembly diagnostic messages on invalid input.
+
+@ ADD instruction w/o 'S' suffix.
+        add r1, r2, r3
+@ CHECK-ERRORS: error: invalid instruction
+@ CHECK-ERRORS:         add r1, r2, r3
+@ CHECK-ERRORS:         ^



From eli.friedman at gmail.com  Tue Aug 16 16:12:35 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 21:12:35 -0000
Subject: [llvm-commits] [llvm] r137755 - in /llvm/trunk:
 lib/Transforms/Scalar/SCCP.cpp test/Transforms/SCCP/switch.ll
Message-ID: <20110816211235.D548B2A6C12D@llvm.org>

Author: efriedma
Date: Tue Aug 16 16:12:35 2011
New Revision: 137755

URL: http://llvm.org/viewvc/llvm-project?rev=137755&view=rev
Log:
Minor bug in SCCP found by inspection.  (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.)


Added:
    llvm/trunk/test/Transforms/SCCP/switch.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=137755&r1=137754&r2=137755&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Tue Aug 16 16:12:35 2011
@@ -582,6 +582,10 @@
   }
   
   if (SwitchInst *SI = dyn_cast<SwitchInst>(&TI)) {
+    if (TI.getNumSuccessors() < 2) {
+      Succs[0] = true;
+      return;
+    }
     LatticeVal SCValue = getValueState(SI->getCondition());
     ConstantInt *CI = SCValue.getConstantInt();
     
@@ -642,6 +646,9 @@
     return true;
   
   if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) {
+    if (SI->getNumSuccessors() < 2)
+      return true;
+
     LatticeVal SCValue = getValueState(SI->getCondition());
     ConstantInt *CI = SCValue.getConstantInt();
     

Added: llvm/trunk/test/Transforms/SCCP/switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/switch.ll?rev=137755&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SCCP/switch.ll (added)
+++ llvm/trunk/test/Transforms/SCCP/switch.ll Tue Aug 16 16:12:35 2011
@@ -0,0 +1,13 @@
+; RUN: opt -S -sccp < %s | FileCheck %s
+
+; Make sure we always consider the default edge executable for a switch
+; with no cases.
+declare void @foo()
+define void @test1() {
+; CHECK: define void @test1
+; CHECK: call void @foo()
+  switch i32 undef, label %d []
+d:
+  call void @foo()
+  ret void
+}



From grosbach at apple.com  Tue Aug 16 16:12:37 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 21:12:37 -0000
Subject: [llvm-commits] [llvm] r137756 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110816211237.BCE712A6C12E@llvm.org>

Author: grosbach
Date: Tue Aug 16 16:12:37 2011
New Revision: 137756

URL: http://llvm.org/viewvc/llvm-project?rev=137756&view=rev
Log:
Move some logic into a helper function and expand the commentary.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137756&r1=137755&r2=137756&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 16:12:37 2011
@@ -147,6 +147,8 @@
                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
   void processInstruction(MCInst &Inst,
                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
+  bool shouldOmitCCOutOperand(StringRef Mnemonic,
+                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
 
 public:
   enum ARMMatchResultTy {
@@ -2739,6 +2741,25 @@
       CanAcceptPredicationCode = false;
 }
 
+bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
+                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+
+  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
+  // another does not. Specifically, the MOVW instruction does not. So we
+  // special case it here and remove the defaulted (non-setting) cc_out
+  // operand if that's the instruction we're trying to match.
+  //
+  // We do this as post-processing of the explicit operands rather than just
+  // conditionally adding the cc_out in the first place because we need
+  // to check the type of the parsed immediate operand.
+  if (Mnemonic == "mov" && Operands.size() > 4 &&
+      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
+      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
+      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
+    return true;
+  return false;
+}
+
 /// Parse an arm instruction mnemonic followed by its operands.
 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
@@ -2845,19 +2866,13 @@
 
   Parser.Lex(); // Consume the EndOfStatement
 
-
-  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
-  // another does not. Specifically, the MOVW instruction does not. So we
-  // special case it here and remove the defaulted (non-setting) cc_out
-  // operand if that's the instruction we're trying to match.
-  //
-  // We do this post-processing of the explicit operands rather than just
-  // conditionally adding the cc_out in the first place because we need
-  // to check the type of the parsed immediate operand.
-  if (Mnemonic == "mov" && Operands.size() > 4 &&
-      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
-      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
-      static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
+  // Some instructions, mostly Thumb, have forms for the same mnemonic that
+  // do and don't have a cc_out optional-def operand. With some spot-checks
+  // of the operand list, we can figure out which variant we're trying to
+  // parse and adjust accordingly before actually matching. Reason number
+  // #317 the table driven matcher doesn't fit well with the ARM instruction
+  // set.
+  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
     Operands.erase(Operands.begin() + 1);
     delete Op;



From isanbard at gmail.com  Tue Aug 16 16:15:50 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 16 Aug 2011 21:15:50 -0000
Subject: [llvm-commits] [llvm] r137757 -
	/llvm/trunk/lib/VMCore/Instruction.cpp
Message-ID: <20110816211550.E23742A6C12C@llvm.org>

Author: void
Date: Tue Aug 16 16:15:50 2011
New Revision: 137757

URL: http://llvm.org/viewvc/llvm-project?rev=137757&view=rev
Log:
The resume instruction may throw. Return 'true' in this case.

Modified:
    llvm/trunk/lib/VMCore/Instruction.cpp

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=137757&r1=137756&r2=137757&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Tue Aug 16 16:15:50 2011
@@ -357,7 +357,7 @@
 bool Instruction::mayThrow() const {
   if (const CallInst *CI = dyn_cast<CallInst>(this))
     return !CI->doesNotThrow();
-  return false;
+  return isa<ResumeInst>(this);
 }
 
 /// isAssociative - Return true if the instruction is associative:



From grosbach at apple.com  Tue Aug 16 16:34:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 21:34:08 -0000
Subject: [llvm-commits] [llvm] r137759 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110816213408.3C5202A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 16:34:08 2011
New Revision: 137759

URL: http://llvm.org/viewvc/llvm-project?rev=137759&view=rev
Log:
Thumb assembly parsing and encoding for ADD(register) instruction.

Added:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137759&r1=137758&r2=137759&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 16:34:08 2011
@@ -2757,6 +2757,15 @@
       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
     return true;
+
+  // Register-register 'add' for thumb does not have a cc_out operand
+  // when there are only two register operands.
+  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
+      static_cast<ARMOperand*>(Operands[3])->isReg() &&
+      static_cast<ARMOperand*>(Operands[4])->isReg() &&
+      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
+    return true;
+
   return false;
 }
 

Added: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137759&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (added)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 16 16:34:08 2011
@@ -0,0 +1,21 @@
+@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
+  .syntax unified
+  .globl _func
+
+@ Check that the assembler can handle the documented syntax from the ARM ARM.
+@ For complex constructs like shifter operands, check more thoroughly for them
+@ once then spot check that following instructions accept the form generally.
+@ This gives us good coverage while keeping the overall size of the test
+@ more reasonable.
+
+_func:
+@ CHECK: _func
+
+ at ------------------------------------------------------------------------------
+@ ADD (register)
+ at ------------------------------------------------------------------------------
+        adds r1, r2, r3
+        add r2, r8
+
+@ CHECK: adds	r1, r2, r3              @ encoding: [0xd1,0x18]
+@ CHECK: add	r2, r8                  @ encoding: [0x42,0x44]



From grosbach at apple.com  Tue Aug 16 16:42:31 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 21:42:31 -0000
Subject: [llvm-commits] [llvm] r137774 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110816214231.E63952A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 16:42:31 2011
New Revision: 137774

URL: http://llvm.org/viewvc/llvm-project?rev=137774&view=rev
Log:
Add missing exit for 'case'.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137774&r1=137773&r2=137774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 16:42:31 2011
@@ -2962,6 +2962,7 @@
     if (widthm1 >= 32 - lsb)
       return Error(Operands[5]->getStartLoc(),
                    "bitfield width must be in range [1,32-lsb]");
+    return false;
   }
   }
 



From echristo at apple.com  Tue Aug 16 16:46:25 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 16 Aug 2011 21:46:25 -0000
Subject: [llvm-commits] [llvm] r137775 - /llvm/trunk/test/FrontendC++/
Message-ID: <20110816214625.71F1D2A6C12C@llvm.org>

Author: echristo
Date: Tue Aug 16 16:46:25 2011
New Revision: 137775

URL: http://llvm.org/viewvc/llvm-project?rev=137775&view=rev
Log:
Remove tests that have been obsoleted or migrated to clang/optimizer tests.

Removed:
    llvm/trunk/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp
    llvm/trunk/test/FrontendC++/2010-05-10-Var-DbgInfo.cpp
    llvm/trunk/test/FrontendC++/2010-05-11-alwaysinlineinstantiation.cpp
    llvm/trunk/test/FrontendC++/2010-05-12-PtrToMember-Dbg.cpp
    llvm/trunk/test/FrontendC++/2010-06-21-LocalVarDbg.cpp
    llvm/trunk/test/FrontendC++/2010-06-22-BitfieldInit.cpp
    llvm/trunk/test/FrontendC++/2010-06-22-ZeroBitfield.cpp
    llvm/trunk/test/FrontendC++/2010-07-19-nowarn.cpp
    llvm/trunk/test/FrontendC++/2010-07-23-DeclLoc.cpp
    llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp
    llvm/trunk/test/FrontendC++/alignstack.cpp
    llvm/trunk/test/FrontendC++/integration-O2.cpp
    llvm/trunk/test/FrontendC++/m64-ptr.cpp
    llvm/trunk/test/FrontendC++/member-alignment.cpp
    llvm/trunk/test/FrontendC++/ptr-to-method-devirt.cpp
    llvm/trunk/test/FrontendC++/thunk-linkonce-odr.cpp
    llvm/trunk/test/FrontendC++/varargs.cpp
    llvm/trunk/test/FrontendC++/weak-external.cpp
    llvm/trunk/test/FrontendC++/x86-64-abi-sret-vs-2word-struct-param.cpp

Removed: llvm/trunk/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-04-30-OptimizedMethod-Dbg.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp (removed)
@@ -1,18 +0,0 @@
-// RUN: %llvmgcc -g -S -O2 %s -o - | FileCheck %s
-
-class foo {
-public:
-      int bar(int x);
-      static int baz(int x);
-};
-
-int foo::bar(int x) {
-  // CHECK: {{i32 [0-9]+, i1 true(, i[0-9]+ [^\}]+[}]|[}]) ; \[ DW_TAG_subprogram \]}}
-    return x*4 + 1;
-}
-
-int foo::baz(int x) {
-  // CHECK: {{i32 [0-9]+, i1 true(, i[0-9]+ [^\},]+[}]|[}]) ; \[ DW_TAG_subprogram \]}}
-    return x*4 + 1;
-}
-

Removed: llvm/trunk/test/FrontendC++/2010-05-10-Var-DbgInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-05-10-Var-DbgInfo.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-05-10-Var-DbgInfo.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-05-10-Var-DbgInfo.cpp (removed)
@@ -1,43 +0,0 @@
-// RUN: %llvmgcc -S -O0 -g %s -o /dev/null
-// PR 7104
-
-struct A {
-  int Ai;
-}; 
-
-struct B : public A {}; 
-struct C : public B {}; 
-
-const char * f(int C::*){ return ""; } 
-int f(int B::*) { return 1; } 
-
-struct D : public C {}; 
-
-const char * g(int B::*){ return ""; } 
-int g(int D::*) { return 1; } 
-
-void test() 
-{
-  int i = f(&A::Ai);
-
-  const char * str = g(&A::Ai);
-}
-
-// conversion of B::* to C::* is better than conversion of A::* to C::*
-typedef void (A::*pmfa)();
-typedef void (B::*pmfb)();
-typedef void (C::*pmfc)();
-
-struct X {
-  operator pmfa();
-  operator pmfb();
-};
-
-
-void g(pmfc);
-
-void test2(X x) 
-{
-  g(x);
-}
-

Removed: llvm/trunk/test/FrontendC++/2010-05-11-alwaysinlineinstantiation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-05-11-alwaysinlineinstantiation.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-05-11-alwaysinlineinstantiation.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-05-11-alwaysinlineinstantiation.cpp (removed)
@@ -1,31 +0,0 @@
-// RUN: %llvmgxx -xc++ %s -S -o - | not grep ZN12basic_stringIcEC1Ev
-// RUN: %llvmgxx -xc++ %s -S -o - | grep ZN12basic_stringIcED1Ev | count 2
-
-template<class charT> 
-class basic_string
-{
-public:
-	basic_string();
-	~basic_string();
-};
-
-template <class charT>
-__attribute__ ((__visibility__("hidden"), __always_inline__)) inline
-basic_string<charT>::basic_string()
-{
-}
-
-template <class charT>
-inline
-basic_string<charT>::~basic_string()
-{
-}
-
-typedef basic_string<char> string;
-
-extern template class basic_string<char>;
-
-int main()
-{
-	string s;
-}

Removed: llvm/trunk/test/FrontendC++/2010-05-12-PtrToMember-Dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-05-12-PtrToMember-Dbg.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-05-12-PtrToMember-Dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-05-12-PtrToMember-Dbg.cpp (removed)
@@ -1,17 +0,0 @@
-//RUN: %llvmgxx -O0 -S -g -o - %s | grep DW_TAG_auto_variable
-class Foo
-{
- public:
-  int x;
-  int y;
-  Foo (int i, int j) { x = i; y = j; }
-};
-
-
-Foo foo(10, 11);
-
-int main() {
-  int Foo::* pmi = &Foo::y;
-  return foo.*pmi;
-}
-

Removed: llvm/trunk/test/FrontendC++/2010-06-21-LocalVarDbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-06-21-LocalVarDbg.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-06-21-LocalVarDbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-06-21-LocalVarDbg.cpp (removed)
@@ -1,13 +0,0 @@
-// RUN: %llvmgxx -g -Os -S %s -o - | llvm-as -disable-output
-// Do not use function name to create named metadata used to hold
-// local variable info. For example. llvm.dbg.lv.~A is an invalid name.
-class A {
-public:
-  ~A() { int i = 0; i++; }
-};
-
-int foo(int i) {
-  A a;
-  return 0;
-}
-

Removed: llvm/trunk/test/FrontendC++/2010-06-22-BitfieldInit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-06-22-BitfieldInit.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-06-22-BitfieldInit.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-06-22-BitfieldInit.cpp (removed)
@@ -1,20 +0,0 @@
-// RUN: %llvmgxx -g -S %s
-struct TEST2
-{
-  int subid:32;
-  int :0;
-};
-
-typedef struct _TEST3
-{
-  TEST2 foo;
-  TEST2 foo2;
-} TEST3;
-
-TEST3 test =
-  {
-    {0},
-    {0}
-  };
-
-int main() { return 0; }

Removed: llvm/trunk/test/FrontendC++/2010-06-22-ZeroBitfield.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-06-22-ZeroBitfield.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-06-22-ZeroBitfield.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-06-22-ZeroBitfield.cpp (removed)
@@ -1,5 +0,0 @@
-// RUN: %llvmgxx -g -S %s
-struct s8_0 { unsigned : 0; };
-struct s8_1 { double x; };
-struct s8 { s8_0 a; s8_1 b; };
-s8 f8() { return s8(); }

Removed: llvm/trunk/test/FrontendC++/2010-07-19-nowarn.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-07-19-nowarn.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-07-19-nowarn.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-07-19-nowarn.cpp (removed)
@@ -1,21 +0,0 @@
-// RUN: %llvmgcc %s -S -m32 -fasm-blocks -o /dev/null
-// This should not warn about unreferenced label. 8195660.
-// XFAIL: *
-// XTARGET: x86,i386,i686
-
-void quarterAsm(int array[], int len)
-{
-  __asm
-  {
-    mov esi, array;
-    mov ecx, len;
-    shr ecx, 2;
-loop:
-    movdqa xmm0, [esi];
-    psrad xmm0, 2;
-    movdqa [esi], xmm0;
-    add esi, 16;
-    sub ecx, 1;
-    jnz loop;
-  }
-}

Removed: llvm/trunk/test/FrontendC++/2010-07-23-DeclLoc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-07-23-DeclLoc.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-07-23-DeclLoc.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-07-23-DeclLoc.cpp (removed)
@@ -1,86 +0,0 @@
-// RUN: %llvmgxx -S -g %s -o - | FileCheck %s
-// Require the template function declaration refer to the correct filename.
-// First, locate the function decl in metadata, and pluck out the file handle:
-// CHECK: {{extract_dwarf_data_from_header.*extract_dwarf_data_from_header.*extract_dwarf_data_from_header.*[^ ]+", metadata !}}[[filehandle:[0-9]+]],
-// Second: Require that filehandle refer to the correct filename:
-// CHECK: {{^!}}[[filehandle]] = metadata {{![{].*}} metadata !"decl_should_be_here.hpp",
-typedef long unsigned int __darwin_size_t;
-typedef __darwin_size_t size_t;
-typedef unsigned char uint8_t;
-typedef unsigned int uint32_t;
-typedef unsigned long long uint64_t;
-namespace std {
-  template<typename _Tp>   class auto_ptr   {
-    _Tp* _M_ptr;
-  public:
-    typedef _Tp element_type;
-    auto_ptr(element_type* __p = 0) throw() : _M_ptr(__p) {    }
-    element_type&     operator*() const throw()     {    }
-  };
-}
-class Pointer32 {
-public:
-  typedef uint32_t ptr_t;
-  typedef uint32_t size_t;
-};
-class Pointer64 {
-public:
-  typedef uint64_t ptr_t;
-  typedef uint64_t size_t;
-};
-class BigEndian {};
-class LittleEndian {};
-template <typename _SIZE, typename _ENDIANNESS> class SizeAndEndianness {
-public:
-  typedef _SIZE SIZE;
-};
-typedef SizeAndEndianness<Pointer32, LittleEndian> ISA32Little;
-typedef SizeAndEndianness<Pointer32, BigEndian> ISA32Big;
-typedef SizeAndEndianness<Pointer64, LittleEndian> ISA64Little;
-typedef SizeAndEndianness<Pointer64, BigEndian> ISA64Big;
-template <typename SIZE> class TRange {
-protected:
-  typename SIZE::ptr_t _location;
-  typename SIZE::size_t _length;
-  TRange(typename SIZE::ptr_t location, typename SIZE::size_t length) : _location(location), _length(length) {  }
-};
-template <typename SIZE, typename T> class TRangeValue : public TRange<SIZE> {
-  T _value;
-public:
-  TRangeValue(typename SIZE::ptr_t location, typename SIZE::size_t length, T value) : TRange<SIZE>(location, length), _value(value) {};
-};
-template <typename SIZE> class TAddressRelocator {};
-class CSCppSymbolOwner{};
-class CSCppSymbolOwnerData{};
-template <typename SIZE> class TRawSymbolOwnerData
-{
-  TRangeValue< SIZE, uint8_t* > _TEXT_text_section;
-  const char* _dsym_path;
-  uint32_t _dylib_current_version;
-  uint32_t _dylib_compatibility_version;
-public:
-  TRawSymbolOwnerData() :
-    _TEXT_text_section(0, 0, __null), _dsym_path(__null), _dylib_current_version(0), _dylib_compatibility_version(0) {}
-};
-template <typename SIZE_AND_ENDIANNESS> class TExtendedMachOHeader {};
-# 16 "decl_should_be_here.hpp"
-template <typename SIZE_AND_ENDIANNESS> void extract_dwarf_data_from_header(TExtendedMachOHeader<SIZE_AND_ENDIANNESS>& header,
-                                                                            TRawSymbolOwnerData<typename SIZE_AND_ENDIANNESS::SIZE>& symbol_owner_data,
-                                                                            TAddressRelocator<typename SIZE_AND_ENDIANNESS::SIZE>* address_relocator) {}
-struct CSCppSymbolOwnerHashFunctor {
-  size_t operator()(const CSCppSymbolOwner& symbol_owner) const {
-# 97 "wrong_place_for_decl.cpp"
-  }
-};
-template <typename SIZE_AND_ENDIANNESS> CSCppSymbolOwnerData* create_symbol_owner_data_arch_specific(CSCppSymbolOwner* symbol_owner, const char* dsym_path) {
-  typedef typename SIZE_AND_ENDIANNESS::SIZE SIZE;
-  std::auto_ptr< TRawSymbolOwnerData<SIZE> > data(new TRawSymbolOwnerData<SIZE>());
-  std::auto_ptr< TExtendedMachOHeader<SIZE_AND_ENDIANNESS> > header;
-  extract_dwarf_data_from_header(*header, *data, (TAddressRelocator<typename SIZE_AND_ENDIANNESS::SIZE>*)__null);
-}
-CSCppSymbolOwnerData* create_symbol_owner_data2(CSCppSymbolOwner* symbol_owner, const char* dsym_path) {
-  create_symbol_owner_data_arch_specific< ISA32Little >(symbol_owner, dsym_path);
-  create_symbol_owner_data_arch_specific< ISA32Big >(symbol_owner, dsym_path);
-  create_symbol_owner_data_arch_specific< ISA64Little >(symbol_owner, dsym_path);
-  create_symbol_owner_data_arch_specific< ISA64Big >(symbol_owner, dsym_path);
-}

Removed: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-08-31-ByValArg.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (removed)
@@ -1,53 +0,0 @@
-// This regression test checks byval arguments' debug info.
-// Radar 8367011
-// RUN: %llvmgcc -S -O0 -g %s -o - | \
-// RUN:    llc --disable-cfi --disable-fp-elim -o %t.s -O0 -relocation-model=pic
-// RUN: %compile_c %t.s -o %t.o
-// RUN: %link %t.o -o %t.exe
-// RUN: echo {break get\nrun\np missing_arg.b} > %t.in 
-// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \
-// RUN:   grep {1 = 4242}
-
-// XTARGET: x86_64-apple-darwin
-
-class EVT {
-public:
-  int a;
-  int b;
-  int c;
-};
-
-class VAL {
-public:
-  int x;
-  int y;
-};
-void foo(EVT e);
-EVT bar();
-
-void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) {
-//CHECK: .ascii "missing_arg"
-  EVT e = bar();
-  if (dl == n)
-    foo(missing_arg);
-}
-
-
-EVT bar() {
-	EVT e;
-	return e;
-}
-
-void foo(EVT e) {}
-
-int main(){
-	VAL v;
-	EVT ma;
-	ma.a = 1;
-	ma.b = 4242;
-	ma.c = 3;
-	int i = 42;	
-	get (&i, 1, v, &v, 2, ma);
-	return 0;
-}
-

Removed: llvm/trunk/test/FrontendC++/alignstack.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/alignstack.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/alignstack.cpp (original)
+++ llvm/trunk/test/FrontendC++/alignstack.cpp (removed)
@@ -1,23 +0,0 @@
-// RUN: %llvmgxx %s -fasm-blocks -S -o - | FileCheck %s
-// Complicated expression as jump target
-// XFAIL: *
-// XTARGET: x86,i386,i686,darwin
-
-void Method3()
-{
-// CHECK: Method3
-// CHECK-NOT: alignstack
-    asm("foo:");
-// CHECK: return
-}
-
-void Method4()
-{
-// CHECK: Method4
-// CHECK: alignstack
-  asm {
-    bar:
-  }
-// CHECK: return
-}
-

Removed: llvm/trunk/test/FrontendC++/integration-O2.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/integration-O2.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/integration-O2.cpp (original)
+++ llvm/trunk/test/FrontendC++/integration-O2.cpp (removed)
@@ -1,19 +0,0 @@
-// RUN: %llvmgxx %s -O2 -S -o - | FileCheck %s
-
-// This test verifies that we get expected codegen out of the -O2 optimization
-// level from the full optimizer.
-
-
-
-// Verify that ipsccp is running and can eliminate globals.
-static int test1g = 42;
-void test1f1() {
-  if (test1g == 0) test1g = 0;
-}
-int test1f2() {
-  return test1g;
-}
-
-// CHECK: @_Z7test1f2v()
-// CHECK: entry:
-// CHECK-NEXT: ret i32 42

Removed: llvm/trunk/test/FrontendC++/m64-ptr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/m64-ptr.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/m64-ptr.cpp (original)
+++ llvm/trunk/test/FrontendC++/m64-ptr.cpp (removed)
@@ -1,19 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | FileCheck %s
-// XFAIL: powerpc-apple-darwin
-
-// Make sure pointers are passed as pointers, not converted to int.
-// The first load should be of type i8** in either 32 or 64 bit mode.
-// This formerly happened on x86-64, 7375899.
-
-class StringRef {
-public:
-  const char *Data;
-  long Len;
-};
-void foo(StringRef X);
-void bar(StringRef &A) {
-// CHECK: @_Z3barR9StringRef
-// CHECK: load i8**
-  foo(A);
-// CHECK: ret void
-}

Removed: llvm/trunk/test/FrontendC++/member-alignment.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/member-alignment.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/member-alignment.cpp (original)
+++ llvm/trunk/test/FrontendC++/member-alignment.cpp (removed)
@@ -1,20 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | FileCheck %s
-// XFAIL: arm,powerpc
-
-// rdar://7268289
-
-class t {
-public:
-  virtual void foo(void);
-  void bar(void);
-};
-
-void
-t::bar(void) {
-// CHECK: _ZN1t3barEv{{.*}} align 2
-}
-
-void
-t::foo(void) {
-// CHECK: _ZN1t3fooEv{{.*}} align 2
-}

Removed: llvm/trunk/test/FrontendC++/ptr-to-method-devirt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/ptr-to-method-devirt.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/ptr-to-method-devirt.cpp (original)
+++ llvm/trunk/test/FrontendC++/ptr-to-method-devirt.cpp (removed)
@@ -1,15 +0,0 @@
-// PR1602
-// RUN: %llvmgxx -S %s -o - -O3 | not grep ptrtoint
-// RUN: %llvmgxx -S %s -o - -O3 | not grep getelementptr
-// RUN: %llvmgxx -S %s -o - -O3 | grep bitcast
-
-
-struct S { virtual void f(); };
-
-typedef void (S::*P)(void);
-
-const P p = &S::f; 
-
-void g(S s) {
-   (s.*p)();
- }

Removed: llvm/trunk/test/FrontendC++/thunk-linkonce-odr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/thunk-linkonce-odr.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/thunk-linkonce-odr.cpp (original)
+++ llvm/trunk/test/FrontendC++/thunk-linkonce-odr.cpp (removed)
@@ -1,33 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | FileCheck %s
-// <rdar://problem/7929157> & <rdar://problem/8104369>
-
-struct A {
-  virtual int f() { return 1; }
-};
-
-struct B {
-  virtual int f() { return 2; }
-};
-
-struct C : A, B {
-  virtual int f() { return 3; }
-};
-
-struct D : C {
-  virtual int f() { return 4; }
-};
-
-static int f(D* d) {
-  B* b = d;
-  return b->f();
-};
-
-int g() {
-  D d;
-  return f(&d);
-}
-
-// Thunks should be marked as "linkonce ODR" not "weak".
-//
-// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1C1fEv
-// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1D1fEv

Removed: llvm/trunk/test/FrontendC++/varargs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/varargs.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/varargs.cpp (original)
+++ llvm/trunk/test/FrontendC++/varargs.cpp (removed)
@@ -1,19 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | FileCheck %s
-// rdar://7309675
-// PR4678
-
-// test1 should be compmiled to be a varargs function in the IR even 
-// though there is no way to do a va_begin.  Otherwise, the optimizer
-// will warn about 'dropped arguments' at the call site.
-
-// CHECK: define i32 @_Z5test1z(...)
-int test1(...) {
-  return -1;
-}
-
-// CHECK: call i32 (...)* @_Z5test1z(i32 0)
-void test() {
-  test1(0);
-}
-
-

Removed: llvm/trunk/test/FrontendC++/weak-external.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/weak-external.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/weak-external.cpp (original)
+++ llvm/trunk/test/FrontendC++/weak-external.cpp (removed)
@@ -1,17 +0,0 @@
-// RUN: %llvmgxx %s -S -O2 -o - | not grep {_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag}
-// PR4262
-
-// The "basic_string" extern template instantiation declaration is supposed to
-// suppress the implicit instantiation of non-inline member functions. Make sure
-// that we suppress the implicit instantiation of non-inline member functions
-// defined out-of-line. That we aren't instantiating the basic_string
-// constructor when we shouldn't be. Such an instantiation forces the implicit
-// instantiation of _S_construct<const char*>. Since _S_construct is a member
-// template, it's instantiation is *not* suppressed (despite being in
-// basic_string<char>), so we would emit it as a weak definition.
-
-#include <stdexcept>
-
-void dummysymbol() {
-  throw(std::runtime_error("string"));
-}

Removed: llvm/trunk/test/FrontendC++/x86-64-abi-sret-vs-2word-struct-param.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/x86-64-abi-sret-vs-2word-struct-param.cpp?rev=137774&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/x86-64-abi-sret-vs-2word-struct-param.cpp (original)
+++ llvm/trunk/test/FrontendC++/x86-64-abi-sret-vs-2word-struct-param.cpp (removed)
@@ -1,27 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep byval | count 2
-// XTARGET: x86
-// PR4242
-// (PR 4242 bug is on 64-bit only, test passes on x86-32 as well)
-
-struct S {
-    void* data[3];
-};
-
-struct T {
-    void* data[2];
-};
-
-extern "C" S fail(int, int, int, int, T t, void* p) {
-    S s;
-    s.data[0] = t.data[0];
-    s.data[1] = t.data[1];
-    s.data[2] = p;
-    return s;
-}
-
-extern "C" S* succeed(S* sret, int, int, int, int, T t, void* p) {
-    sret->data[0] = t.data[0];
-    sret->data[1] = t.data[1];
-    sret->data[2] = p;
-    return sret;
-}



From eli.friedman at gmail.com  Tue Aug 16 17:06:31 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 22:06:31 -0000
Subject: [llvm-commits] [llvm] r137777 - in /llvm/trunk:
 lib/Transforms/Scalar/SCCP.cpp test/Transforms/SCCP/undef-resolve.ll
Message-ID: <20110816220631.C442A2A6C12C@llvm.org>

Author: efriedma
Date: Tue Aug 16 17:06:31 2011
New Revision: 137777

URL: http://llvm.org/viewvc/llvm-project?rev=137777&view=rev
Log:
A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop
making random bad assumptions about instructions which are not explicitly listed.  

Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".


Modified:
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/test/Transforms/SCCP/undef-resolve.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=137777&r1=137776&r2=137777&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Tue Aug 16 17:06:31 2011
@@ -1445,54 +1445,78 @@
         }
         continue;
       }
-      
+
       LatticeVal &LV = getValueState(I);
       if (!LV.isUndefined()) continue;
 
-      // No instructions using structs need disambiguation.
-      if (I->getOperand(0)->getType()->isStructTy())
-        continue;
-
-      // Get the lattice values of the first two operands for use below.
       LatticeVal Op0LV = getValueState(I->getOperand(0));
       LatticeVal Op1LV;
-      if (I->getNumOperands() == 2) {
-        // No instructions using structs need disambiguation.
-        if (I->getOperand(1)->getType()->isStructTy())
-          continue;
-        
-        // If this is a two-operand instruction, and if both operands are
-        // undefs, the result stays undef.
+      if (I->getNumOperands() == 2)
         Op1LV = getValueState(I->getOperand(1));
-        if (Op0LV.isUndefined() && Op1LV.isUndefined())
-          continue;
-      }
-      
       // If this is an instructions whose result is defined even if the input is
       // not fully defined, propagate the information.
       Type *ITy = I->getType();
       switch (I->getOpcode()) {
-      default: break;          // Leave the instruction as an undef.
+      case Instruction::ExtractValue:
+        break; // Extract of undef -> undef
+      case Instruction::Add:
+      case Instruction::Sub:
+      case Instruction::Trunc:
+      case Instruction::FPTrunc:
+      case Instruction::BitCast:
+        break; // Any undef -> undef
+      case Instruction::FSub:
+      case Instruction::FAdd:
+      case Instruction::FMul:
+      case Instruction::FDiv:
+      case Instruction::FRem:
+        // Floating-point binary operation: be conservative.
+        if (Op0LV.isUndefined() && Op1LV.isUndefined())
+          markForcedConstant(I, Constant::getNullValue(ITy));
+        else
+          markOverdefined(I);
+        return true;
       case Instruction::ZExt:
-        // After a zero extend, we know the top part is zero.  SExt doesn't have
-        // to be handled here, because we don't know whether the top part is 1's
-        // or 0's.
-      case Instruction::SIToFP:  // some FP values are not possible, just use 0.
-      case Instruction::UIToFP:  // some FP values are not possible, just use 0.
+      case Instruction::SExt:
+      case Instruction::FPToUI:
+      case Instruction::FPToSI:
+      case Instruction::FPExt:
+      case Instruction::PtrToInt:
+      case Instruction::IntToPtr:
+      case Instruction::SIToFP:
+      case Instruction::UIToFP:
+        // undef -> 0; some outputs are impossible
         markForcedConstant(I, Constant::getNullValue(ITy));
         return true;
       case Instruction::Mul:
       case Instruction::And:
+        // Both operands undef -> undef
+        if (Op0LV.isUndefined() && Op1LV.isUndefined())
+          break;
         // undef * X -> 0.   X could be zero.
         // undef & X -> 0.   X could be zero.
         markForcedConstant(I, Constant::getNullValue(ITy));
         return true;
 
       case Instruction::Or:
+        // Both operands undef -> undef
+        if (Op0LV.isUndefined() && Op1LV.isUndefined())
+          break;
         // undef | X -> -1.   X could be -1.
         markForcedConstant(I, Constant::getAllOnesValue(ITy));
         return true;
 
+      case Instruction::Xor:
+        // undef ^ undef -> 0; strictly speaking, this is not strictly
+        // necessary, but we try to be nice to people who expect this
+        // behavior in simple cases
+        if (Op0LV.isUndefined() && Op1LV.isUndefined()) {
+          markForcedConstant(I, Constant::getNullValue(ITy));
+          return true;
+        }
+        // undef ^ X -> undef
+        break;
+
       case Instruction::SDiv:
       case Instruction::UDiv:
       case Instruction::SRem:
@@ -1507,26 +1531,24 @@
         return true;
         
       case Instruction::AShr:
-        // undef >>s X -> undef.  No change.
-        if (Op0LV.isUndefined()) break;
-        
-        // X >>s undef -> X.  X could be 0, X could have the high-bit known set.
-        if (Op0LV.isConstant())
-          markForcedConstant(I, Op0LV.getConstant());
-        else
-          markOverdefined(I);
+        // X >>a undef -> undef.
+        if (Op1LV.isUndefined()) break;
+
+        // undef >>a X -> all ones
+        markForcedConstant(I, Constant::getAllOnesValue(ITy));
         return true;
       case Instruction::LShr:
       case Instruction::Shl:
-        // undef >> X -> undef.  No change.
-        // undef << X -> undef.  No change.
-        if (Op0LV.isUndefined()) break;
-        
-        // X >> undef -> 0.  X could be 0.
-        // X << undef -> 0.  X could be 0.
+        // X << undef -> undef.
+        // X >> undef -> undef.
+        if (Op1LV.isUndefined()) break;
+
+        // undef << X -> 0
+        // undef >> X -> 0
         markForcedConstant(I, Constant::getNullValue(ITy));
         return true;
       case Instruction::Select:
+        Op1LV = getValueState(I->getOperand(1));
         // undef ? X : Y  -> X or Y.  There could be commonality between X/Y.
         if (Op0LV.isUndefined()) {
           if (!Op1LV.isConstant())  // Pick the constant one if there is any.
@@ -1546,9 +1568,19 @@
         else
           markOverdefined(I);
         return true;
-      case Instruction::Call:
-        // If a call has an undef result, it is because it is constant foldable
-        // but one of the inputs was undef.  Just force the result to
+      case Instruction::Load:
+        // A load here means one of two things: a load of undef from a global,
+        // a load from an unknown pointer.  Either way, having it return undef
+        // is okay.
+        break;
+      case Instruction::ICmp:
+        // X == undef -> undef.  Other comparisons get more complicated.
+        if (cast<ICmpInst>(I)->isEquality())
+          break;
+        markOverdefined(I);
+        return true;
+      default:
+        // If we don't know what should happen here, conservatively mark it
         // overdefined.
         markOverdefined(I);
         return true;

Modified: llvm/trunk/test/Transforms/SCCP/undef-resolve.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/undef-resolve.ll?rev=137777&r1=137776&r2=137777&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SCCP/undef-resolve.ll (original)
+++ llvm/trunk/test/Transforms/SCCP/undef-resolve.ll Tue Aug 16 17:06:31 2011
@@ -104,3 +104,60 @@
 bb1:                                              ; preds = %bb1.us-lcssa, %bb1.us-lcssa.us
   ret i32 0
 }
+
+; Make sure SCCP honors the xor "idiom"
+; rdar://9956541
+define i32 @test3() {
+  %t = xor i32 undef, undef
+  ret i32 %t
+; CHECK: @test3
+; CHECK: ret i32 0
+}
+
+; Be conservative with FP ops
+define double @test4(double %x) {
+  %t = fadd double %x, undef
+  ret double %t
+; CHECK: @test4
+; CHECK: fadd double %x, undef
+}
+
+; Make sure casts produce a possible value
+define i32 @test5() {
+  %t = sext i8 undef to i32
+  ret i32 %t
+; CHECK: @test5
+; CHECK: ret i32 0
+}
+
+; Make sure ashr produces a possible value
+define i32 @test6() {
+  %t = ashr i32 undef, 31
+  ret i32 %t
+; CHECK: @test6
+; CHECK: ret i32 -1
+}
+
+; Make sure lshr produces a possible value
+define i32 @test7() {
+  %t = lshr i32 undef, 31
+  ret i32 %t
+; CHECK: @test7
+; CHECK: ret i32 0
+}
+
+; icmp eq with undef simplifies to undef
+define i1 @test8() {
+  %t = icmp eq i32 undef, -1
+  ret i1 %t
+; CHECK: @test8
+; CHECK: ret i1 undef
+}
+
+; Make sure we don't conclude that relational comparisons simplify to undef
+define i1 @test9() {
+  %t = icmp ugt i32 undef, -1
+  ret i1 %t
+; CHECK: @test9
+; CHECK: icmp ugt
+}



From echristo at apple.com  Tue Aug 16 17:10:32 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 16 Aug 2011 15:10:32 -0700
Subject: [llvm-commits] [llvm] r137777 - in /llvm/trunk:
 lib/Transforms/Scalar/SCCP.cpp test/Transforms/SCCP/undef-resolve.ll
In-Reply-To: <20110816220631.C442A2A6C12C@llvm.org>
References: <20110816220631.C442A2A6C12C@llvm.org>
Message-ID: <59604F7E-F5C1-41DB-929B-C99D4F469F4C@apple.com>


On Aug 16, 2011, at 3:06 PM, Eli Friedman wrote:

> Includes fix for rdar://9956541, a version of "undef ^ undef should return
> 0 because it's easier than arguing with users".

Beautiful.

-eric
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From dpatel at apple.com  Tue Aug 16 17:09:44 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 16 Aug 2011 22:09:44 -0000
Subject: [llvm-commits] [llvm] r137778 - in /llvm/trunk:
 docs/SourceLevelDebugging.html include/llvm/Analysis/DIBuilder.h
 include/llvm/Analysis/DebugInfo.h lib/Analysis/DIBuilder.cpp
 lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h
Message-ID: <20110816220944.57CAA2A6C12D@llvm.org>

Author: dpatel
Date: Tue Aug 16 17:09:43 2011
New Revision: 137778

URL: http://llvm.org/viewvc/llvm-project?rev=137778&view=rev
Log:
Until now all debug info MDNodes referred to a root MDNode, a compile unit. This simplified handling of these needs in dwarf writer.  However, one side effect of this is that during link time optimization all these MDNodes are _not_ uniqued. In other words there will be N number of MDNodes describing "int", "char" and all other types, which would suddenly grow when each object file starts using libraries like STL.

MDNodes graph structure such that compiler unit keeps track of important MDNodes and update dwarf writer to process mdnodes top-down instead of bottom up.


Modified:
    llvm/trunk/docs/SourceLevelDebugging.html
    llvm/trunk/include/llvm/Analysis/DIBuilder.h
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DIBuilder.cpp
    llvm/trunk/lib/Analysis/DebugInfo.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Tue Aug 16 17:09:43 2011
@@ -355,7 +355,7 @@
              ;; (DW_TAG_file_type)
   metadata,  ;; Source file name
   metadata,  ;; Source file directory (includes trailing slash)
-  metadata   ;; Reference to compile unit where defined
+  metadata   ;; Unused
 }
 </pre>
 </div>
@@ -365,8 +365,7 @@
    provide context for source line correspondence. </p>
 
 <p>Each input file is encoded as a separate file descriptor in LLVM debugging
-   information output. Each file descriptor would be defined using a 
-   compile unit. </p>
+   information output. </p>
 
 </div>
 
@@ -485,7 +484,7 @@
 !4 = metadata !{
   i32,      ;; Tag = 36 + <a href="#LLVMDebugVersion">LLVMDebugVersion</a> 
             ;; (DW_TAG_base_type)
-  metadata, ;; Reference to context (typically a compile unit)
+  metadata, ;; Reference to context 
   metadata, ;; Name (may be "" for anonymous types)
   metadata, ;; Reference to file where defined (may be NULL)
   i32,      ;; Line number where defined (may be 0)
@@ -500,7 +499,7 @@
 
 <p>These descriptors define primitive types used in the code. Example int, bool
    and float.  The context provides the scope of the type, which is usually the
-   top level.  Since basic types are not usually user defined the compile unit
+   top level.  Since basic types are not usually user defined the context
    and line number can be left as NULL and 0.  The size, alignment and offset
    are expressed in bits and can be 64 bit values.  The alignment is used to
    round the offset when embedded in a
@@ -585,7 +584,7 @@
    the <a href="#format_derived_type">derived type</a>. </p>
 
 <p><a href="#format_derived_type">Derived type</a> location can be determined
-   from the compile unit and line number.  The size, alignment and offset are
+   from the context and line number.  The size, alignment and offset are
    expressed in bits and can be 64 bit values.  The alignment is used to round
    the offset when embedded in a <a href="#format_composite_type">composite
    type</a> (example to keep float doubles on 64 bit boundaries.) The offset is
@@ -675,7 +674,7 @@
    the formal arguments to the subroutine.</p>
 
 <p><a href="#format_composite_type">Composite type</a> location can be
-   determined from the compile unit and line number.  The size, alignment and
+   determined from the context and line number.  The size, alignment and
    offset are expressed in bits and can be 64 bit values.  The alignment is used
    to round the offset when embedded in
    a <a href="#format_composite_type">composite type</a> (as an example, to keep
@@ -774,7 +773,7 @@
    has no source correspondent.</p>
 
 <p>The context is either the subprogram or block where the variable is defined.
-   Name the source variable name.  Compile unit and line indicate where the
+   Name the source variable name.  Context and line indicate where the
    variable was defined. Type descriptor defines the declared type of the
    variable.</p>
 

Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original)
+++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Tue Aug 16 17:09:43 2011
@@ -48,9 +48,19 @@
     LLVMContext & VMContext;
     MDNode *TheCU;
 
+    MDNode *TempEnumTypes;
+    MDNode *TempRetainTypes;
+    MDNode *TempSubprograms;
+    MDNode *TempGVs;
+
     Function *DeclareFn;     // llvm.dbg.declare
     Function *ValueFn;       // llvm.dbg.value
 
+    SmallVector<Value *, 4> AllEnumTypes;
+    SmallVector<Value *, 4> AllRetainTypes;
+    SmallVector<Value *, 4> AllSubprograms;
+    SmallVector<Value *, 4> AllGVs;
+
     DIBuilder(const DIBuilder &);       // DO NOT IMPLEMENT
     void operator=(const DIBuilder &);  // DO NOT IMPLEMENT
 

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Aug 16 17:09:43 2011
@@ -182,6 +182,11 @@
     StringRef getFlags() const       { return getStringField(8);   }
     unsigned getRunTimeVersion() const { return getUnsignedField(9); }
 
+    DIArray getEnumTypes() const;
+    DIArray getRetainedTypes() const;
+    DIArray getSubprograms() const;
+    DIArray getGlobalVariables() const;
+
     /// Verify - Verify that a compile unit is well formed.
     bool Verify() const;
 
@@ -201,7 +206,10 @@
     }
     StringRef getFilename() const  { return getStringField(1);   }
     StringRef getDirectory() const { return getStringField(2);   }
-    DICompileUnit getCompileUnit() const{ return getFieldAs<DICompileUnit>(3); }
+    DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10  && "Invalid CompileUnit!");
+      return getFieldAs<DICompileUnit>(3); 
+    }
   };
 
   /// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X,Y}').
@@ -237,6 +245,7 @@
     DIScope getContext() const          { return getFieldAs<DIScope>(1); }
     StringRef getName() const           { return getStringField(2);     }
     DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit!");
      if (getVersion() == llvm::LLVMDebugVersion7)
        return getFieldAs<DICompileUnit>(3);
      
@@ -450,6 +459,7 @@
     StringRef getDisplayName() const  { return getStringField(4); }
     StringRef getLinkageName() const  { return getStringField(5); }
     DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit!");
       if (getVersion() == llvm::LLVMDebugVersion7)
         return getFieldAs<DICompileUnit>(6);
 
@@ -560,6 +570,7 @@
     StringRef getDisplayName() const  { return getStringField(4); }
     StringRef getLinkageName() const  { return getStringField(5); }
     DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit!");
       if (getVersion() == llvm::LLVMDebugVersion7)
         return getFieldAs<DICompileUnit>(6);
 
@@ -595,6 +606,7 @@
     DIScope getContext() const          { return getFieldAs<DIScope>(1); }
     StringRef getName() const           { return getStringField(2);     }
     DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit!");
       if (getVersion() == llvm::LLVMDebugVersion7)
         return getFieldAs<DICompileUnit>(3);
 
@@ -687,6 +699,7 @@
       return getFieldAs<DIFile>(3).getFilename();
     }
     DICompileUnit getCompileUnit() const{ 
+      assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit!");
       if (getVersion() == llvm::LLVMDebugVersion7)
         return getFieldAs<DICompileUnit>(3);
 

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Tue Aug 16 17:09:43 2011
@@ -29,10 +29,30 @@
 }
 
 DIBuilder::DIBuilder(Module &m)
-  : M(m), VMContext(M.getContext()), TheCU(0), DeclareFn(0), ValueFn(0) {}
+  : M(m), VMContext(M.getContext()), TheCU(0), TempEnumTypes(0), 
+    TempRetainTypes(0), TempSubprograms(0), TempGVs(0), DeclareFn(0), ValueFn(0)
+{}
 
 /// finalize - Construct any deferred debug info descriptors.
 void DIBuilder::finalize() {
+  DIArray Enums = getOrCreateArray(AllEnumTypes);
+  DIType(TempEnumTypes).replaceAllUsesWith(Enums);
+
+  DIArray RetainTypes = getOrCreateArray(AllRetainTypes);
+  DIType(TempRetainTypes).replaceAllUsesWith(RetainTypes);
+
+  DIArray SPs = getOrCreateArray(AllSubprograms);
+  DIType(TempSubprograms).replaceAllUsesWith(SPs);
+
+  DIArray GVs = getOrCreateArray(AllGVs);
+  DIType(TempGVs).replaceAllUsesWith(GVs);
+}
+
+/// getNonCompileUnitScope - If N is compile unit return NULL otherwise return N.
+static MDNode *getNonCompileUnitScope(MDNode *N) {
+  if (DIDescriptor(N).isCompileUnit())
+    return NULL;
+  return N;
 }
 
 /// createCompileUnit - A CompileUnit provides an anchor for all debugging
@@ -41,6 +61,23 @@
                                   StringRef Directory, StringRef Producer, 
                                   bool isOptimized, StringRef Flags, 
                                   unsigned RunTimeVer) {
+  Value *TElts[] = { GetTagConstant(VMContext, DW_TAG_base_type) };
+  TempEnumTypes = MDNode::getTemporary(VMContext, TElts);
+  Value *THElts[] = { TempEnumTypes };
+  MDNode *EnumHolder = MDNode::get(VMContext, THElts);
+
+  TempRetainTypes = MDNode::getTemporary(VMContext, TElts);
+  Value *TRElts[] = { TempRetainTypes };
+  MDNode *RetainHolder = MDNode::get(VMContext, TRElts);
+
+  TempSubprograms = MDNode::getTemporary(VMContext, TElts);
+  Value *TSElts[] = { TempSubprograms };
+  MDNode *SPHolder = MDNode::get(VMContext, TSElts);
+
+  TempGVs = MDNode::getTemporary(VMContext, TElts);
+  Value *TVElts[] = { TempGVs };
+  MDNode *GVHolder = MDNode::get(VMContext, TVElts);
+
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_compile_unit),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
@@ -52,7 +89,11 @@
     ConstantInt::get(Type::getInt1Ty(VMContext), true), // isMain
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
     MDString::get(VMContext, Flags),
-    ConstantInt::get(Type::getInt32Ty(VMContext), RunTimeVer)
+    ConstantInt::get(Type::getInt32Ty(VMContext), RunTimeVer),
+    EnumHolder,
+    RetainHolder,
+    SPHolder,
+    GVHolder
   };
   TheCU = DICompileUnit(MDNode::get(VMContext, Elts));
 
@@ -69,7 +110,7 @@
     GetTagConstant(VMContext, dwarf::DW_TAG_file_type),
     MDString::get(VMContext, Filename),
     MDString::get(VMContext, Directory),
-    TheCU
+    NULL // TheCU
   };
   return DIFile(MDNode::get(VMContext, Elts));
 }
@@ -93,7 +134,7 @@
   // offset and flags are always empty here.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_base_type),
-    TheCU,
+    NULL, //TheCU,
     MDString::get(VMContext, Name),
     NULL, // Filename
     ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line
@@ -112,7 +153,7 @@
   // Qualified types are encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, Tag),
-    TheCU,
+    NULL, //TheCU,
     MDString::get(VMContext, StringRef()), // Empty name.
     NULL, // Filename
     ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line
@@ -131,7 +172,7 @@
   // Pointer types are encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_pointer_type),
-    TheCU,
+    NULL, //TheCU,
     MDString::get(VMContext, Name),
     NULL, // Filename
     ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line
@@ -149,7 +190,7 @@
   // References are encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_reference_type),
-    TheCU,
+    NULL, //TheCU,
     NULL, // Name
     NULL, // Filename
     ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line
@@ -169,7 +210,7 @@
   assert(Ty.Verify() && "Invalid typedef type!");
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_typedef),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNo),
@@ -231,7 +272,7 @@
   // TAG_member is encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_member),
-    Scope,
+    getNonCompileUnitScope(Scope),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -256,7 +297,7 @@
   // TAG_member is encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_member),
-    File, // Or TheCU ? Ty ?
+    getNonCompileUnitScope(File),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -283,7 +324,7 @@
  // TAG_class_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_class_type),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -308,7 +349,7 @@
                                        unsigned ColumnNo) {
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_template_type_parameter),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     Ty,
     File,
@@ -327,7 +368,7 @@
                                         unsigned ColumnNo) {
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_template_value_parameter),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     Ty,
     ConstantInt::get(Type::getInt64Ty(VMContext), Val),
@@ -347,7 +388,7 @@
  // TAG_structure_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_structure_type),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -372,7 +413,7 @@
   // TAG_union_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_union_type),
-    Scope,
+    getNonCompileUnitScope(Scope),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -393,7 +434,7 @@
   // TAG_subroutine_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subroutine_type),
-    File,
+    getNonCompileUnitScope(File),
     MDString::get(VMContext, ""),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), 0),
@@ -418,7 +459,7 @@
   // TAG_enumeration_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_enumeration_type),
-    Scope,
+    getNonCompileUnitScope(Scope),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),
@@ -432,8 +473,7 @@
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.enum");
-  NMD->addOperand(Node);
+  AllEnumTypes.push_back(Node);
   return DIType(Node);
 }
 
@@ -443,9 +483,9 @@
   // TAG_array_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_array_type),
-    TheCU,
+    NULL, //TheCU,
     MDString::get(VMContext, ""),
-    TheCU,
+    NULL, //TheCU,
     ConstantInt::get(Type::getInt32Ty(VMContext), 0),
     ConstantInt::get(Type::getInt64Ty(VMContext), Size),
     ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits),
@@ -465,9 +505,9 @@
   // TAG_vector_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_vector_type),
-    TheCU,
+    NULL, //TheCU,
     MDString::get(VMContext, ""),
-    TheCU,
+    NULL, //TheCU,
     ConstantInt::get(Type::getInt32Ty(VMContext), 0),
     ConstantInt::get(Type::getInt64Ty(VMContext), Size),
     ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits),
@@ -508,8 +548,7 @@
 /// retainType - Retain DIType in a module even if it is not referenced 
 /// through debug info anchors.
 void DIBuilder::retainType(DIType T) {
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.ty");
-  NMD->addOperand(T);
+  AllRetainTypes.push_back(T);
 }
 
 /// createUnspecifiedParameter - Create unspeicified type descriptor
@@ -536,7 +575,7 @@
   // use here as long as DIType accepts it.
   Value *Elts[] = {
     GetTagConstant(VMContext, DW_TAG_base_type),
-    F.getCompileUnit(),
+    TheCU,
     NULL,
     F
   };
@@ -572,7 +611,7 @@
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_variable),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
-    TheCU,
+    NULL, // TheCU,
     MDString::get(VMContext, Name),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, Name),
@@ -584,9 +623,7 @@
     Val
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
-  // Create a named metadata so that we do not lose this mdnode.
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.gv");
-  NMD->addOperand(Node);
+  AllGVs.push_back(Node);
   return DIGlobalVariable(Node);
 }
 
@@ -599,7 +636,7 @@
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_variable),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, LinkageName),
@@ -611,9 +648,7 @@
     Val
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
-  // Create a named metadata so that we do not lose this mdnode.
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.gv");
-  NMD->addOperand(Node);
+  AllGVs.push_back(Node);
   return DIGlobalVariable(Node);
 }
 
@@ -625,7 +660,7 @@
                                           unsigned ArgNo) {
   Value *Elts[] = {
     GetTagConstant(VMContext, Tag),
-    Scope,
+    getNonCompileUnitScope(Scope),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24))),
@@ -660,7 +695,7 @@
                                             unsigned ArgNo) {
   SmallVector<Value *, 15> Elts;
   Elts.push_back(GetTagConstant(VMContext, Tag));
-  Elts.push_back(Scope);
+  Elts.push_back(getNonCompileUnitScope(Scope)),
   Elts.push_back(MDString::get(VMContext, Name));
   Elts.push_back(F);
   Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), (LineNo | (ArgNo << 24))));
@@ -686,7 +721,7 @@
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, LinkageName),
@@ -707,8 +742,7 @@
   MDNode *Node = MDNode::get(VMContext, Elts);
 
   // Create a named metadata so that we do not lose this mdnode.
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.sp");
-  NMD->addOperand(Node);
+  AllSubprograms.push_back(Node);
   return DISubprogram(Node);
 }
 
@@ -729,7 +763,7 @@
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
-    Context,
+    getNonCompileUnitScope(Context),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, Name),
     MDString::get(VMContext, LinkageName),
@@ -747,10 +781,6 @@
     TParam,
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
-
-  // Create a named metadata so that we do not lose this mdnode.
-  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.sp");
-  NMD->addOperand(Node);
   return DISubprogram(Node);
 }
 
@@ -760,7 +790,7 @@
                                        DIFile File, unsigned LineNo) {
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_namespace),
-    Scope,
+    getNonCompileUnitScope(Scope),
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)
@@ -774,7 +804,7 @@
   static unsigned int unique_id = 0;
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_lexical_block),
-    Scope,
+    getNonCompileUnitScope(Scope),
     ConstantInt::get(Type::getInt32Ty(VMContext), Line),
     ConstantInt::get(Type::getInt32Ty(VMContext), Col),
     File,

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Aug 16 17:09:43 2011
@@ -359,7 +359,7 @@
 bool DIType::Verify() const {
   if (!DbgNode)
     return false;
-  if (!getContext().Verify())
+  if (getContext() && !getContext().Verify())
     return false;
   unsigned Tag = getTag();
   if (!isBasicType() && Tag != dwarf::DW_TAG_const_type &&
@@ -386,12 +386,9 @@
 bool DICompositeType::Verify() const {
   if (!DbgNode)
     return false;
-  if (!getContext().Verify())
+  if (getContext() && !getContext().Verify())
     return false;
 
-  DICompileUnit CU = getCompileUnit();
-  if (!CU.Verify())
-    return false;
   return true;
 }
 
@@ -400,11 +397,7 @@
   if (!DbgNode)
     return false;
 
-  if (!getContext().Verify())
-    return false;
-
-  DICompileUnit CU = getCompileUnit();
-  if (!CU.Verify())
+  if (getContext() && !getContext().Verify())
     return false;
 
   DICompositeType Ty = getType();
@@ -421,11 +414,7 @@
   if (getDisplayName().empty())
     return false;
 
-  if (!getContext().Verify())
-    return false;
-
-  DICompileUnit CU = getCompileUnit();
-  if (!CU.Verify())
+  if (getContext() && !getContext().Verify())
     return false;
 
   DIType Ty = getType();
@@ -443,10 +432,7 @@
   if (!DbgNode)
     return false;
 
-  if (!getContext().Verify())
-    return false;
-
-  if (!getCompileUnit().Verify())
+  if (getContext() && !getContext().Verify())
     return false;
 
   DIType Ty = getType();
@@ -470,8 +456,6 @@
     return false;
   if (getName().empty())
     return false;
-  if (!getCompileUnit().Verify())
-    return false;
   return true;
 }
 
@@ -566,6 +550,47 @@
   return StringRef();
 }
 
+DIArray DICompileUnit::getEnumTypes() const {
+  if (!DbgNode || DbgNode->getNumOperands() < 14)
+    return DIArray();
+
+  if (MDNode *N = dyn_cast_or_null<MDNode>(DbgNode->getOperand(10)))
+    if (MDNode *A = dyn_cast_or_null<MDNode>(N->getOperand(0)))
+      return DIArray(A);
+  return DIArray();
+}
+
+DIArray DICompileUnit::getRetainedTypes() const {
+  if (!DbgNode || DbgNode->getNumOperands() < 14)
+    return DIArray();
+
+  if (MDNode *N = dyn_cast_or_null<MDNode>(DbgNode->getOperand(11)))
+    if (MDNode *A = dyn_cast_or_null<MDNode>(N->getOperand(0)))
+      return DIArray(A);
+  return DIArray();
+}
+
+DIArray DICompileUnit::getSubprograms() const {
+  if (!DbgNode || DbgNode->getNumOperands() < 14)
+    return DIArray();
+
+  if (MDNode *N = dyn_cast_or_null<MDNode>(DbgNode->getOperand(12)))
+    if (MDNode *A = dyn_cast_or_null<MDNode>(N->getOperand(0)))
+      return DIArray(A);
+  return DIArray();
+}
+
+
+DIArray DICompileUnit::getGlobalVariables() const {
+  if (!DbgNode || DbgNode->getNumOperands() < 14)
+    return DIArray();
+
+  if (MDNode *N = dyn_cast_or_null<MDNode>(DbgNode->getOperand(13)))
+    if (MDNode *A = dyn_cast_or_null<MDNode>(N->getOperand(0)))
+      return DIArray(A);
+  return DIArray();
+}
+
 //===----------------------------------------------------------------------===//
 // DIDescriptor: dump routines for all descriptors.
 //===----------------------------------------------------------------------===//
@@ -597,7 +622,6 @@
   OS << " [" << dwarf::TagString(Tag) << "] ";
 
   // TODO : Print context
-  getCompileUnit().print(OS);
   OS << " ["
          << "line " << getLineNumber() << ", "
          << getSizeInBits() << " bits, "
@@ -653,7 +677,6 @@
   OS << " [" << dwarf::TagString(Tag) << "] ";
 
   // TODO : Print context
-  getCompileUnit().print(OS);
   OS << " [" << getLineNumber() << "] ";
 
   if (isLocalToUnit())
@@ -676,7 +699,6 @@
   OS << " [" << dwarf::TagString(Tag) << "] ";
 
   // TODO : Print context
-  getCompileUnit().print(OS);
   OS << " [" << getLineNumber() << "] ";
 
   if (isLocalToUnit())
@@ -732,7 +754,6 @@
   if (!Res.empty())
     OS << " [" << Res << "] ";
 
-  getCompileUnit().print(OS);
   OS << " [" << getLineNumber() << "] ";
   getType().print(OS);
   OS << "\n";

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue Aug 16 17:09:43 2011
@@ -577,7 +577,10 @@
 
 /// getOrCreateTypeDIE - Find existing DIE or create new DIE for the
 /// given DIType.
-DIE *CompileUnit::getOrCreateTypeDIE(DIType Ty) {
+DIE *CompileUnit::getOrCreateTypeDIE(const MDNode *TyNode) {
+  DIType Ty(TyNode);
+  if (!Ty.Verify())
+    return NULL;
   DIE *TyDIE = getDIE(Ty);
   if (TyDIE)
     return TyDIE;
@@ -629,7 +632,8 @@
 void CompileUnit::addGlobalType(DIType Ty) {
   DIDescriptor Context = Ty.getContext();
   if (Ty.isCompositeType() && !Ty.getName().empty() && !Ty.isForwardDecl() 
-      && (Context.isCompileUnit() || Context.isFile() || Context.isNameSpace()))
+      && (!Context || Context.isCompileUnit() || Context.isFile() 
+          || Context.isNameSpace()))
     if (DIEEntry *Entry = getDIEEntry(Ty))
       GlobalTypes[Ty.getName()] = Entry->getEntry();
 }
@@ -1358,7 +1362,7 @@
     addUInt(MemberDie, dwarf::DW_AT_accessibility, dwarf::DW_FORM_flag,
             dwarf::DW_ACCESS_private);
   // Otherwise C++ member and base classes are considered public.
-  else if (DT.getCompileUnit().getLanguage() == dwarf::DW_LANG_C_plus_plus)
+  else 
     addUInt(MemberDie, dwarf::DW_AT_accessibility, dwarf::DW_FORM_flag,
             dwarf::DW_ACCESS_public);
   if (DT.isVirtual())

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Tue Aug 16 17:09:43 2011
@@ -236,7 +236,7 @@
 
   /// getOrCreateTypeDIE - Find existing DIE or create new DIE for the
   /// given DIType.
-  DIE *getOrCreateTypeDIE(DIType Ty);
+  DIE *getOrCreateTypeDIE(const MDNode *N);
 
   /// getOrCreateTemplateTypeParameterDIE - Find existing DIE or create new DIE 
   /// for the given DITemplateTypeParameter.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 16 17:09:43 2011
@@ -465,7 +465,7 @@
 
 /// constructCompileUnit - Create new CompileUnit for the given
 /// metadata node with tag DW_TAG_compile_unit.
-void DwarfDebug::constructCompileUnit(const MDNode *N) {
+CompileUnit *DwarfDebug::constructCompileUnit(const MDNode *N) {
   DICompileUnit DIUnit(N);
   StringRef FN = DIUnit.getFilename();
   StringRef Dir = DIUnit.getDirectory();
@@ -507,35 +507,7 @@
   if (!FirstCU)
     FirstCU = NewCU;
   CUMap.insert(std::make_pair(N, NewCU));
-}
-
-/// getCompileUnit - Get CompileUnit DIE.
-CompileUnit *DwarfDebug::getCompileUnit(const MDNode *N) const {
-  assert (N && "Invalid DwarfDebug::getCompileUnit argument!");
-  DIDescriptor D(N);
-  const MDNode *CUNode = NULL;
-  if (D.isCompileUnit())
-    CUNode = N;
-  else if (D.isSubprogram())
-    CUNode = DISubprogram(N).getCompileUnit();
-  else if (D.isType())
-    CUNode = DIType(N).getCompileUnit();
-  else if (D.isGlobalVariable())
-    CUNode = DIGlobalVariable(N).getCompileUnit();
-  else if (D.isVariable())
-    CUNode = DIVariable(N).getCompileUnit();
-  else if (D.isNameSpace())
-    CUNode = DINameSpace(N).getCompileUnit();
-  else if (D.isFile())
-    CUNode = DIFile(N).getCompileUnit();
-  else
-    return FirstCU;
-
-  DenseMap<const MDNode *, CompileUnit *>::const_iterator I
-    = CUMap.find(CUNode);
-  if (I == CUMap.end())
-    return FirstCU;
-  return I->second;
+  return NewCU;
 }
 
 /// constructGlobalVariableDIE - Construct global variable DIE.
@@ -571,22 +543,39 @@
   // Expose as global.
   TheCU->addGlobal(SP.getName(), SubprogramDie);
 
+  SPMap[N] = TheCU;
   return;
 }
 
 /// collectInfoFromNamedMDNodes - Collect debug info from named mdnodes such
 /// as llvm.dbg.enum and llvm.dbg.ty
 void DwarfDebug::collectInfoFromNamedMDNodes(Module *M) {
+  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.sp"))
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+      const MDNode *N = NMD->getOperand(i);
+      if (CompileUnit *CU = CUMap.lookup(DISubprogram(N).getCompileUnit()))
+        constructSubprogramDIE(CU, N);
+    }
+  
+  if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.gv"))
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+      const MDNode *N = NMD->getOperand(i);
+      if (CompileUnit *CU = CUMap.lookup(DIGlobalVariable(N).getCompileUnit()))
+        constructGlobalVariableDIE(CU, N);
+    }
+  
   if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.enum"))
     for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
       DIType Ty(NMD->getOperand(i));
-      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
+      if (CompileUnit *CU = CUMap.lookup(Ty.getCompileUnit()))
+        CU->getOrCreateTypeDIE(Ty);
     }
   
   if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.ty"))
     for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
       DIType Ty(NMD->getOperand(i));
-      getCompileUnit(Ty)->getOrCreateTypeDIE(Ty);
+      if (CompileUnit *CU = CUMap.lookup(Ty.getCompileUnit()))
+        CU->getOrCreateTypeDIE(Ty);
     }
 }
 
@@ -617,14 +606,16 @@
   for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
          E = DbgFinder.global_variable_end(); I != E; ++I) {
     const MDNode *N = *I;
-    constructGlobalVariableDIE(getCompileUnit(N), N);
+    if (CompileUnit *CU = CUMap.lookup(DIGlobalVariable(N).getCompileUnit()))
+      constructGlobalVariableDIE(CU, N);
   }
-  
+    
   // Create DIEs for each subprogram.
   for (DebugInfoFinder::iterator I = DbgFinder.subprogram_begin(),
          E = DbgFinder.subprogram_end(); I != E; ++I) {
     const MDNode *N = *I;
-    constructSubprogramDIE(getCompileUnit(N), N);
+    if (CompileUnit *CU = CUMap.lookup(DISubprogram(N).getCompileUnit()))
+      constructSubprogramDIE(CU, N);
   }
 
   return HasDebugInfo;
@@ -641,29 +632,22 @@
   // module using debug info finder to collect debug info.
   NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
   if (CU_Nodes) {
-
-    NamedMDNode *GV_Nodes = M->getNamedMetadata("llvm.dbg.gv");
-    NamedMDNode *SP_Nodes = M->getNamedMetadata("llvm.dbg.sp");
-    if (!GV_Nodes && !SP_Nodes)
-      // If there are not any global variables or any functions then
-      // there is not any debug info in this module.
-      return;
-
-    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i)
-      constructCompileUnit(CU_Nodes->getOperand(i));
-
-    if (GV_Nodes)
-      for (unsigned i = 0, e = GV_Nodes->getNumOperands(); i != e; ++i) {
-        const MDNode *N = GV_Nodes->getOperand(i);
-        constructGlobalVariableDIE(getCompileUnit(N), N);
-      }
-
-    if (SP_Nodes)
-      for (unsigned i = 0, e = SP_Nodes->getNumOperands(); i != e; ++i) {
-        const MDNode *N = SP_Nodes->getOperand(i);
-        constructSubprogramDIE(getCompileUnit(N), N);
-      }
-    
+    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
+      DICompileUnit CUNode(CU_Nodes->getOperand(i));
+      CompileUnit *CU = constructCompileUnit(CUNode);
+      DIArray GVs = CUNode.getGlobalVariables();
+      for (unsigned i = 0, e = GVs.getNumElements(); i != e; ++i)
+        constructGlobalVariableDIE(CU, GVs.getElement(i));
+      DIArray SPs = CUNode.getSubprograms();
+      for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i)
+        constructSubprogramDIE(CU, SPs.getElement(i));
+      DIArray EnumTypes = CUNode.getEnumTypes();
+      for (unsigned i = 0, e = EnumTypes.getNumElements(); i != e; ++i)
+        CU->getOrCreateTypeDIE(EnumTypes.getElement(i));
+      DIArray RetainedTypes = CUNode.getRetainedTypes();
+      for (unsigned i = 0, e = RetainedTypes.getNumElements(); i != e; ++i)
+        CU->getOrCreateTypeDIE(RetainedTypes.getElement(i));
+    }
   } else if (!collectLegacyDebugInfo(M))
     return;
 
@@ -685,39 +669,44 @@
   if (!FirstCU) return;
   const Module *M = MMI->getModule();
   DenseMap<const MDNode *, LexicalScope *> DeadFnScopeMap;
-  if (NamedMDNode *AllSPs = M->getNamedMetadata("llvm.dbg.sp")) {
-    for (unsigned SI = 0, SE = AllSPs->getNumOperands(); SI != SE; ++SI) {
-      if (ProcessedSPNodes.count(AllSPs->getOperand(SI)) != 0) continue;
-      DISubprogram SP(AllSPs->getOperand(SI));
-      if (!SP.Verify()) continue;
 
-      // Collect info for variables that were optimized out.
-      if (!SP.isDefinition()) continue;
-      StringRef FName = SP.getLinkageName();
-      if (FName.empty())
-        FName = SP.getName();
-      NamedMDNode *NMD = getFnSpecificMDNode(*(MMI->getModule()), FName);
-      if (!NMD) continue;
-      unsigned E = NMD->getNumOperands();
-      if (!E) continue;
-      LexicalScope *Scope = new LexicalScope(NULL, DIDescriptor(SP), NULL, 
-                                             false);
-      DeadFnScopeMap[SP] = Scope;
-      SmallVector<DbgVariable, 8> Variables;
-      for (unsigned I = 0; I != E; ++I) {
-        DIVariable DV(NMD->getOperand(I));
-        if (!DV.Verify()) continue;
-        Variables.push_back(DbgVariable(DV, NULL));
-      }
-
-      // Construct subprogram DIE and add variables DIEs.
-      CompileUnit *SPCU = getCompileUnit(SP);
-      constructSubprogramDIE(SPCU, SP);
-      DIE *ScopeDIE = SPCU->getDIE(SP);
-      for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
-        if (DIE *VariableDIE = 
-            SPCU->constructVariableDIE(&Variables[i], Scope->isAbstractScope()))
-          ScopeDIE->addChild(VariableDIE);
+  // Collect info for variables that were optimized out.
+  if (NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu")) {
+    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
+      DICompileUnit TheCU(CU_Nodes->getOperand(i));
+      DIArray Subprograms = TheCU.getSubprograms();
+      for (unsigned i = 0, e = Subprograms.getNumElements(); i != e; ++i) {
+        DISubprogram SP(Subprograms.getElement(i));
+        if (ProcessedSPNodes.count(SP) != 0) continue;
+        if (!SP.Verify()) continue;
+        if (!SP.isDefinition()) continue;
+        StringRef FName = SP.getLinkageName();
+        if (FName.empty())
+          FName = SP.getName();
+        NamedMDNode *NMD = getFnSpecificMDNode(*(MMI->getModule()), FName);
+        if (!NMD) continue;
+        unsigned E = NMD->getNumOperands();
+        if (!E) continue;
+        LexicalScope *Scope = 
+          new LexicalScope(NULL, DIDescriptor(SP), NULL, false);
+        DeadFnScopeMap[SP] = Scope;
+        
+        // Construct subprogram DIE and add variables DIEs.
+        SmallVector<DbgVariable, 8> Variables;
+        for (unsigned I = 0; I != E; ++I) {
+          DIVariable DV(NMD->getOperand(I));
+          if (!DV.Verify()) continue;
+          Variables.push_back(DbgVariable(DV, NULL));
+        }
+        CompileUnit *SPCU = CUMap.lookup(TheCU);
+        assert (SPCU && "Unable to find Compile Unit!");
+        constructSubprogramDIE(SPCU, SP);
+        DIE *ScopeDIE = SPCU->getDIE(SP);
+        for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
+          if (DIE *VariableDIE = 
+              SPCU->constructVariableDIE(&Variables[i], Scope->isAbstractScope()))
+            ScopeDIE->addChild(VariableDIE);
+        }
       }
     }
   }
@@ -784,6 +773,7 @@
 
   // clean up.
   DeleteContainerSeconds(DeadFnScopeMap);
+  SPMap.clear();
   for (DenseMap<const MDNode *, CompileUnit *>::iterator I = CUMap.begin(),
          E = CUMap.end(); I != E; ++I)
     delete I->second;
@@ -1333,7 +1323,8 @@
   collectVariableInfo(MF, ProcessedVars);
   
   LexicalScope *FnScope = LScopes.getCurrentFunctionScope();
-  CompileUnit *TheCU = getCompileUnit(FnScope->getScopeNode());
+  CompileUnit *TheCU = SPMap.lookup(FnScope->getScopeNode());
+  assert (TheCU && "Unable to find compile unit!");
 
   // Construct abstract scopes.
   ArrayRef<LexicalScope *> AList = LScopes.getAbstractScopesList();

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=137778&r1=137777&r2=137778&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Aug 16 17:09:43 2011
@@ -192,8 +192,13 @@
   //
 
   CompileUnit *FirstCU;
+
+  /// Maps MDNode with its corresponding CompileUnit.
   DenseMap <const MDNode *, CompileUnit *> CUMap;
 
+  /// Maps subprogram MDNode with its corresponding CompileUnit.
+  DenseMap <const MDNode *, CompileUnit *> SPMap;
+
   /// AbbreviationsSet - Used to uniquely define abbreviations.
   ///
   FoldingSet<DIEAbbrev> AbbreviationsSet;
@@ -410,10 +415,7 @@
 
   /// constructCompileUnit - Create new CompileUnit for the given 
   /// metadata node with tag DW_TAG_compile_unit.
-  void constructCompileUnit(const MDNode *N);
-
-  /// getCompielUnit - Get CompileUnit DIE.
-  CompileUnit *getCompileUnit(const MDNode *N) const;
+  CompileUnit *constructCompileUnit(const MDNode *N);
 
   /// constructGlobalVariableDIE - Construct global variable DIE.
   void constructGlobalVariableDIE(CompileUnit *TheCU, const MDNode *N);



From grosbach at apple.com  Tue Aug 16 17:20:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 22:20:01 -0000
Subject: [llvm-commits] [llvm] r137779 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseRegisterInfo.h
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110816222001.6A8A72A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 17:20:01 2011
New Revision: 137779

URL: http://llvm.org/viewvc/llvm-project?rev=137779&view=rev
Log:
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=137779&r1=137778&r2=137779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Tue Aug 16 17:20:01 2011
@@ -33,19 +33,6 @@
   };
 }
 
-/// isARMLowRegister - Returns true if the register is low register r0-r7.
-///
-static inline bool isARMLowRegister(unsigned Reg) {
-  using namespace ARM;
-  switch (Reg) {
-  case R0:  case R1:  case R2:  case R3:
-  case R4:  case R5:  case R6:  case R7:
-    return true;
-  default:
-    return false;
-  }
-}
-
 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
 /// or a stack/pc register that we should push/pop.
 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137779&r1=137778&r2=137779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 17:20:01 2011
@@ -81,6 +81,9 @@
   bool isThumbTwo() const {
     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
   }
+  bool hasV6Ops() const {
+    return STI.getFeatureBits() & ARM::HasV6Ops;
+  }
   void SwitchMode() {
     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
     setAvailableFeatures(FB);
@@ -152,7 +155,9 @@
 
 public:
   enum ARMMatchResultTy {
-    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY
+    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
+    Match_RequiresV6,
+    Match_RequiresThumb2
   };
 
   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
@@ -2714,6 +2719,8 @@
       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
       Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
       Mnemonic == "eor" || Mnemonic == "smlal" ||
+      // FIXME: We need a better way. This really confused Thumb2
+      // parsing for 'mov'.
       (Mnemonic == "mov" && !isThumbOne())) {
     CanAcceptCarrySet = true;
   } else {
@@ -3022,7 +3029,8 @@
 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
   // suffix depending on whether they're in an IT block or not.
-  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+  unsigned Opc = Inst.getOpcode();
+  MCInstrDesc &MCID = getInstDesc(Opc);
   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
     assert(MCID.hasOptionalDef() &&
            "optionally flag setting instruction missing optional def operand");
@@ -3044,6 +3052,17 @@
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
       return Match_RequiresITBlock;
   }
+  // Some high-register supporting Thumb1 encodings only allow both registers
+  // to be from r0-r7 when in Thumb2.
+  else if (Opc == ARM::tADDhirr && isThumbOne() &&
+           isARMLowRegister(Inst.getOperand(1).getReg()) &&
+           isARMLowRegister(Inst.getOperand(2).getReg()))
+    return Match_RequiresThumb2;
+  // Others only require ARMv6 or later.
+  else if (Opc == ARM::tMOVr && isThumbOne() &&
+           isARMLowRegister(Inst.getOperand(0).getReg()) &&
+           isARMLowRegister(Inst.getOperand(1).getReg()))
+    return Match_RequiresV6;
   return Match_Success;
 }
 
@@ -3090,6 +3109,10 @@
     return Error(IDLoc, "unable to convert operands to instruction");
   case Match_RequiresITBlock:
     return Error(IDLoc, "instruction only valid inside IT block");
+  case Match_RequiresV6:
+    return Error(IDLoc, "instruction variant requires ARMv6 or later");
+  case Match_RequiresThumb2:
+    return Error(IDLoc, "instruction variant requires Thumb2");
   }
 
   llvm_unreachable("Implement any new match types added!");

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=137779&r1=137778&r2=137779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Tue Aug 16 17:20:01 2011
@@ -188,6 +188,19 @@
   }
 }
 
+/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
+///
+static inline bool isARMLowRegister(unsigned Reg) {
+  using namespace ARM;
+  switch (Reg) {
+  case R0:  case R1:  case R2:  case R3:
+  case R4:  case R5:  case R6:  case R7:
+    return true;
+  default:
+    return false;
+  }
+}
+
 /// ARMII - This namespace holds all of the target specific flags that
 /// instruction info tracks.
 ///

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=137779&r1=137778&r2=137779&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug 16 17:20:01 2011
@@ -8,3 +8,13 @@
 @ CHECK-ERRORS: error: invalid instruction
 @ CHECK-ERRORS:         add r1, r2, r3
 @ CHECK-ERRORS:         ^
+
+@ Instructions which require v6+ for both registers to be low regs.
+        add r2, r3
+        mov r2, r3
+@ CHECK-ERRORS: error: instruction variant requires Thumb2
+@ CHECK-ERRORS:         add r2, r3
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: instruction variant requires ARMv6 or later
+@ CHECK-ERRORS:         mov r2, r3
+@ CHECK-ERRORS:         ^



From eli.friedman at gmail.com  Tue Aug 16 17:38:34 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 22:38:34 -0000
Subject: [llvm-commits] [llvm] r137781 -
	/llvm/trunk/lib/Analysis/InstructionSimplify.cpp
Message-ID: <20110816223834.4ABE72A6C12C@llvm.org>

Author: efriedma
Date: Tue Aug 16 17:38:34 2011
New Revision: 137781

URL: http://llvm.org/viewvc/llvm-project?rev=137781&view=rev
Log:
Extend the undef ^ undef idiom once more.  No testcase: I can't figure out how to actually trigger the codepath in question at the moment, but it might get exposed in the future.


Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=137781&r1=137780&r2=137781&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Aug 16 17:38:34 2011
@@ -1348,6 +1348,11 @@
     std::swap(Op0, Op1);
   }
 
+  // A ^ A = 0
+  // Do this first so that we catch the undef ^ undef "idiom".
+  if (Op0 == Op1)
+    return Constant::getNullValue(Op0->getType());
+
   // A ^ undef -> undef
   if (match(Op1, m_Undef()))
     return Op1;
@@ -1356,10 +1361,6 @@
   if (match(Op1, m_Zero()))
     return Op0;
 
-  // A ^ A = 0
-  if (Op0 == Op1)
-    return Constant::getNullValue(Op0->getType());
-
   // A ^ ~A  =  ~A ^ A  =  -1
   if (match(Op0, m_Not(m_Specific(Op1))) ||
       match(Op1, m_Not(m_Specific(Op0))))



From eli.friedman at gmail.com  Tue Aug 16 17:47:04 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 15:47:04 -0700
Subject: [llvm-commits] [PATCH] AndOrXor Chain Optimization
In-Reply-To: <CADP2NNE8e3E9x3_PBC7de7V8mC3RM3u65ZU_a2Hb=KrFf_AEoQ@mail.gmail.com>
References: <CADP2NNELWKQPdzH+MH1d1w-nFUf_vGrbKqzK4DT5mODsEkw23A@mail.gmail.com>
	<CAJdarcF_iToH1Ckn48WnnvLSry-y39RnEKZqseeV6whkk9qNXA@mail.gmail.com>
	<CADP2NNFmqxxVnkKv76WVZUsb++RafadtWm6vWnYSGded_kVC5A@mail.gmail.com>
	<CADP2NNE8e3E9x3_PBC7de7V8mC3RM3u65ZU_a2Hb=KrFf_AEoQ@mail.gmail.com>
Message-ID: <CAJdarcGUPt_OEe6A2hNkTXxUk0Uq_pzKakVdEduBOd+SuK-x9A@mail.gmail.com>

2011/8/16 Daniel Nic?cio <dnicacios at gmail.com>:
> ping
> Updated patch with revision 137728

This is a lot of code for a rather obscure optimization; I don't see
how it is worthwhile.

-Eli

> 2011/8/5 Daniel Nic?cio <dnicacios at gmail.com>
>>
>> New unified diff file attached.
>> Daniel Nicacio
>>
>> 2011/8/4 Eli Friedman <eli.friedman at gmail.com>
>>>
>>> 2011/8/4 Daniel Nic?cio <dnicacios at gmail.com>
>>>>
>>>> Hi, this patch increments the instcombiner pass.
>>>> It adds a new XOR, OR, AND optimization, trying to find a chain of
>>>> logical instructions (xor, and, or) operating on different bits of the same
>>>> word. If this chain is found, it is collapsed into a single logical
>>>> instruction.
>>>> The figure below shows a generic example:
>>>> Any comments and critics are welcome.
>>>
>>> Please attach a single diff containing all the changes, and please use
>>> "svn diff" or some other tool that makes a unified diff.
>>> -Eli
>
>


From eli.friedman at gmail.com  Tue Aug 16 18:29:17 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 16 Aug 2011 23:29:17 -0000
Subject: [llvm-commits] [llvm] r137786 -
	/llvm/trunk/test/Transforms/InstCombine/atomic.ll
Message-ID: <20110816232917.417962A6C12C@llvm.org>

Author: efriedma
Date: Tue Aug 16 18:29:17 2011
New Revision: 137786

URL: http://llvm.org/viewvc/llvm-project?rev=137786&view=rev
Log:
An additional atomic test; related to r137662.


Modified:
    llvm/trunk/test/Transforms/InstCombine/atomic.ll

Modified: llvm/trunk/test/Transforms/InstCombine/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/atomic.ll?rev=137786&r1=137785&r2=137786&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/atomic.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/atomic.ll Tue Aug 16 18:29:17 2011
@@ -13,3 +13,12 @@
   ret i32* %r
 }
 
+define i32 @test2(i32* %p) {
+; CHECK: define i32 @test2
+; CHECK: %x = load atomic i32* %p seq_cst, align 4
+; CHECK: shl i32 %x, 1
+  %x = load atomic i32* %p seq_cst, align 4
+  %y = load i32* %p, align 4
+  %z = add i32 %x, %y
+  ret i32 %z
+}



From resistor at mac.com  Tue Aug 16 18:45:44 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 16 Aug 2011 23:45:44 -0000
Subject: [llvm-commits] [llvm] r137787 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td Disassembler/ARMDisassembler.cpp
Message-ID: <20110816234544.421372A6C12C@llvm.org>

Author: resistor
Date: Tue Aug 16 18:45:44 2011
New Revision: 137787

URL: http://llvm.org/viewvc/llvm-project?rev=137787&view=rev
Log:
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137787&r1=137786&r2=137787&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Aug 16 18:45:44 2011
@@ -902,6 +902,7 @@
   let Pattern = pattern;
   let thumbArithFlagSetting = 1;
   list<Predicate> Predicates = [IsThumb, IsThumb1Only];
+  let DecoderNamespace = "ThumbSBit";
 }
 
 class T1sI<dag oops, dag iops, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137787&r1=137786&r2=137787&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 16 18:45:44 2011
@@ -417,6 +417,14 @@
   bool result = decodeThumbInstruction16(MI, insn16, Address, this);
   if (result) {
     Size = 2;
+    AddThumbPredicate(MI);
+    return true;
+  }
+
+  MI.clear();
+  result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
+  if (result) {
+    Size = 2;
     bool InITBlock = !ITBlock.empty();
     AddThumbPredicate(MI);
     AddThumb1SBit(MI, InITBlock);



From grosbach at apple.com  Tue Aug 16 18:57:34 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 16 Aug 2011 23:57:34 -0000
Subject: [llvm-commits] [llvm] r137788 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110816235734.BF9AB2A6C12C@llvm.org>

Author: grosbach
Date: Tue Aug 16 18:57:34 2011
New Revision: 137788

URL: http://llvm.org/viewvc/llvm-project?rev=137788&view=rev
Log:
Thumb ADD(immediate) parsing support.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137788&r1=137787&r2=137788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 16 18:57:34 2011
@@ -849,7 +849,7 @@
 
 // Add immediate
 def tADDi3 :                    // A8.6.4 T1
-  T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
+  T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                    IIC_iALUi,
                    "add", "\t$Rd, $Rm, $imm3",
                    [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
@@ -858,8 +858,8 @@
 }
 
 def tADDi8 :                    // A8.6.4 T2
-  T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
-                    IIC_iALUi,
+  T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
+                    (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                     "add", "\t$Rdn, $imm8",
                     [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137788&r1=137787&r2=137788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 16 18:57:34 2011
@@ -3013,6 +3013,11 @@
       Inst = TmpInst;
     }
     break;
+  case ARM::tADDi8:
+    // If the immediate is in the range 0-7, we really wanted tADDi3.
+    if (Inst.getOperand(3).getImm() < 8)
+      Inst.setOpcode(ARM::tADDi3);
+    break;
   }
 }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137788&r1=137787&r2=137788&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 16 18:57:34 2011
@@ -12,10 +12,22 @@
 @ CHECK: _func
 
 @------------------------------------------------------------------------------
+@ ADD (immediate)
+ at ------------------------------------------------------------------------------
+        adds r1, r2, #3
+        adds r2, #3
+        adds r2, #8
+
+@ CHECK: adds	r1, r2, #3              @ encoding: [0xd1,0x1c]
+@ CHECK: adds	r2, r2, #3              @ encoding: [0xd2,0x1c]
+@ CHECK: adds	r2, #8                  @ encoding: [0x08,0x32]
+
+
+ at ------------------------------------------------------------------------------
 @ ADD (register)
 @------------------------------------------------------------------------------
         adds r1, r2, r3
         add r2, r8
 
 @ CHECK: adds	r1, r2, r3              @ encoding: [0xd1,0x18]
-@ CHECK: add	r2, r8                  @ encoding: [0x42,0x44]
+  CHECK: add	r2, r8                  @ encoding: [0x42,0x44]



From jediknil at belkadan.com  Tue Aug 16 19:29:32 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 00:29:32 -0000
Subject: [llvm-commits] [llvm] r137791 - in /llvm/trunk:
 include/llvm/Support/DynamicLibrary.h lib/Support/DynamicLibrary.cpp
 lib/Support/Windows/DynamicLibrary.inc
Message-ID: <20110817002932.A04612A6C12C@llvm.org>

Author: jrose
Date: Tue Aug 16 19:29:32 2011
New Revision: 137791

URL: http://llvm.org/viewvc/llvm-project?rev=137791&view=rev
Log:
Use DynamicLibrary instances as a way to get symbols from a specific library. Preparation for upcoming (preliminary) support for plugins for the static analyzer.

Modified:
    llvm/trunk/include/llvm/Support/DynamicLibrary.h
    llvm/trunk/lib/Support/DynamicLibrary.cpp
    llvm/trunk/lib/Support/Windows/DynamicLibrary.inc

Modified: llvm/trunk/include/llvm/Support/DynamicLibrary.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DynamicLibrary.h?rev=137791&r1=137790&r2=137791&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/DynamicLibrary.h (original)
+++ llvm/trunk/include/llvm/Support/DynamicLibrary.h Tue Aug 16 19:29:32 2011
@@ -28,36 +28,57 @@
   /// It also allows for symbols to be defined which don't live in any library,
   /// but rather the main program itself, useful on Windows where the main
   /// executable cannot be searched.
+  ///
+  /// Note: there is currently no interface for temporarily loading a library,
+  /// or for unloading libraries when the LLVM library is unloaded.
   class DynamicLibrary {
-    DynamicLibrary(); // DO NOT IMPLEMENT
+    // Opaque data used to interface with OS-specific dynamic library handling.
+    void *Data;
+
+    explicit DynamicLibrary(void *data = 0) : Data(data) {}
   public:
-    /// This function allows a library to be loaded without instantiating a
-    /// DynamicLibrary object. Consequently, it is marked as being permanent
-    /// and will only be unloaded when the program terminates.  This returns
-    /// false on success or returns true and fills in *ErrMsg on failure.
-    /// @brief Open a dynamic library permanently.
-    ///
-    /// NOTE: This function is not thread safe.
+    /// Returns true if the object refers to a valid library.
+    bool isValid() { return Data != 0; }
+
+    /// Searches through the library for the symbol \p symbolName. If it is
+    /// found, the address of that symbol is returned. If not, NULL is returned.
+    /// Note that NULL will also be returned if the library failed to load.
+    /// Use isValid() to distinguish these cases if it is important.
+    /// Note that this will \e not search symbols explicitly registered by
+    /// AddSymbol().
+    void *getAddressOfSymbol(const char *symbolName);
+
+    /// This function permanently loads the dynamic library at the given path.
+    /// The library will only be unloaded when the program terminates.
+    /// This returns a valid DynamicLibrary instance on success and an invalid
+    /// instance on failure (see isValid()). \p *errMsg will only be modified
+    /// if the library fails to load.
     ///
-    static bool LoadLibraryPermanently(const char *filename,
-                                       std::string *ErrMsg = 0);
+    /// It is safe to call this function multiple times for the same library.
+    /// @brief Open a dynamic library permanently.
+    static DynamicLibrary getPermanentLibrary(const char *filename,
+                                              std::string *errMsg = 0);
+
+    /// This function permanently loads the dynamic library at the given path.
+    /// Use this instead of getPermanentLibrary() when you won't need to get
+    /// symbols from the library itself.
+    ///
+    /// It is safe to call this function multiple times for the same library.
+    static bool LoadLibraryPermanently(const char *Filename,
+                                       std::string *ErrMsg = 0) {
+      return !getPermanentLibrary(Filename, ErrMsg).isValid();
+    }
 
     /// This function will search through all previously loaded dynamic
-    /// libraries for the symbol \p symbolName. If it is found, the addressof
+    /// libraries for the symbol \p symbolName. If it is found, the address of
     /// that symbol is returned. If not, null is returned. Note that this will
-    /// search permanently loaded libraries (LoadLibraryPermanently) as well
-    /// as ephemerally loaded libraries (constructors).
+    /// search permanently loaded libraries (getPermanentLibrary()) as well
+    /// as explicitly registered symbols (AddSymbol()).
     /// @throws std::string on error.
     /// @brief Search through libraries for address of a symbol
-    ///
-    /// NOTE: This function is not thread safe.
-    ///
     static void *SearchForAddressOfSymbol(const char *symbolName);
 
     /// @brief Convenience function for C++ophiles.
-    ///
-    /// NOTE: This function is not thread safe.
-    ///
     static void *SearchForAddressOfSymbol(const std::string &symbolName) {
       return SearchForAddressOfSymbol(symbolName.c_str());
     }
@@ -66,18 +87,7 @@
     /// value \p symbolValue.  These symbols are searched before any
     /// libraries.
     /// @brief Add searchable symbol/value pair.
-    ///
-    /// NOTE: This function is not thread safe.
-    ///
-    static void AddSymbol(const char *symbolName, void *symbolValue);
-
-    /// @brief Convenience function for C++ophiles.
-    ///
-    /// NOTE: This function is not thread safe.
-    ///
-    static void AddSymbol(const std::string &symbolName, void *symbolValue) {
-      AddSymbol(symbolName.c_str(), symbolValue);
-    }
+    static void AddSymbol(StringRef symbolName, void *symbolValue);
   };
 
 } // End sys namespace

Modified: llvm/trunk/lib/Support/DynamicLibrary.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/DynamicLibrary.cpp?rev=137791&r1=137790&r2=137791&view=diff
==============================================================================
--- llvm/trunk/lib/Support/DynamicLibrary.cpp (original)
+++ llvm/trunk/lib/Support/DynamicLibrary.cpp Tue Aug 16 19:29:32 2011
@@ -9,28 +9,26 @@
 //
 //  This header file implements the operating system DynamicLibrary concept.
 //
-// FIXME: This file leaks the ExplicitSymbols and OpenedHandles vector, and is
-// not thread safe!
+// FIXME: This file leaks ExplicitSymbols and OpenedHandles!
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/DenseSet.h"
 #include "llvm/Support/DynamicLibrary.h"
 #include "llvm/Support/Mutex.h"
 #include "llvm/Config/config.h"
 #include <cstdio>
 #include <cstring>
-#include <map>
-#include <vector>
 
 // Collection of symbol name/value pairs to be searched prior to any libraries.
-static std::map<std::string, void*> *ExplicitSymbols = 0;
+static llvm::StringMap<void *> *ExplicitSymbols = 0;
 
 namespace {
 
 struct ExplicitSymbolsDeleter {
   ~ExplicitSymbolsDeleter() {
-    if (ExplicitSymbols)
-      delete ExplicitSymbols;
+    delete ExplicitSymbols;
   }
 };
 
@@ -38,10 +36,17 @@
 
 static ExplicitSymbolsDeleter Dummy;
 
-void llvm::sys::DynamicLibrary::AddSymbol(const char* symbolName,
+
+static llvm::sys::SmartMutex<true>& getMutex() {
+  static llvm::sys::SmartMutex<true> HandlesMutex;
+  return HandlesMutex;
+}
+
+void llvm::sys::DynamicLibrary::AddSymbol(StringRef symbolName,
                                           void *symbolValue) {
+  SmartScopedLock<true> lock(getMutex());
   if (ExplicitSymbols == 0)
-    ExplicitSymbols = new std::map<std::string, void*>();
+    ExplicitSymbols = new llvm::StringMap<void*>();
   (*ExplicitSymbols)[symbolName] = symbolValue;
 }
 
@@ -61,66 +66,77 @@
 //===          independent code.
 //===----------------------------------------------------------------------===//
 
-static std::vector<void *> *OpenedHandles = 0;
-
-
-static SmartMutex<true>& getMutex() {
-  static SmartMutex<true> HandlesMutex;
-  return HandlesMutex;
-}
-
+static DenseSet<void *> *OpenedHandles = 0;
 
-bool DynamicLibrary::LoadLibraryPermanently(const char *Filename,
-                                            std::string *ErrMsg) {
-  void *H = dlopen(Filename, RTLD_LAZY|RTLD_GLOBAL);
-  if (H == 0) {
-    if (ErrMsg) *ErrMsg = dlerror();
-    return true;
+DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename,
+                                                   std::string *errMsg) {
+  void *handle = dlopen(filename, RTLD_LAZY|RTLD_GLOBAL);
+  if (handle == 0) {
+    if (errMsg) *errMsg = dlerror();
+    return DynamicLibrary();
   }
+
 #ifdef __CYGWIN__
   // Cygwin searches symbols only in the main
   // with the handle of dlopen(NULL, RTLD_GLOBAL).
-  if (Filename == NULL)
-    H = RTLD_DEFAULT;
+  if (filename == NULL)
+    handle = RTLD_DEFAULT;
 #endif
-  SmartScopedLock<true> Lock(getMutex());
+
+  SmartScopedLock<true> lock(getMutex());
   if (OpenedHandles == 0)
-    OpenedHandles = new std::vector<void *>();
-  OpenedHandles->push_back(H);
-  return false;
+    OpenedHandles = new DenseSet<void *>();
+
+  // If we've already loaded this library, dlclose() the handle in order to
+  // keep the internal refcount at +1.
+  if (!OpenedHandles->insert(handle).second)
+    dlclose(handle);
+
+  return DynamicLibrary(handle);
+}
+
+void *DynamicLibrary::getAddressOfSymbol(const char *symbolName) {
+  if (!isValid())
+    return NULL;
+  return dlsym(Data, symbolName);
 }
+
 #else
 
 using namespace llvm;
 using namespace llvm::sys;
 
-bool DynamicLibrary::LoadLibraryPermanently(const char *Filename,
-                                            std::string *ErrMsg) {
-  if (ErrMsg) *ErrMsg = "dlopen() not supported on this platform";
-  return true;
+DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename,
+                                                   std::string *errMsg) {
+  if (errMsg) *errMsg = "dlopen() not supported on this platform";
+  return DynamicLibrary();
 }
+
+void *DynamicLibrary::getAddressOfSymbol(const char *symbolName) {
+  return NULL;
+}
+
 #endif
 
 namespace llvm {
 void *SearchForAddressOfSpecialSymbol(const char* symbolName);
 }
 
-void* DynamicLibrary::SearchForAddressOfSymbol(const char* symbolName) {
+void* DynamicLibrary::SearchForAddressOfSymbol(const char *symbolName) {
+  SmartScopedLock<true> Lock(getMutex());
+
   // First check symbols added via AddSymbol().
   if (ExplicitSymbols) {
-    std::map<std::string, void *>::iterator I =
-      ExplicitSymbols->find(symbolName);
-    std::map<std::string, void *>::iterator E = ExplicitSymbols->end();
+    StringMap<void *>::iterator i = ExplicitSymbols->find(symbolName);
 
-    if (I != E)
-      return I->second;
+    if (i != ExplicitSymbols->end())
+      return i->second;
   }
 
 #if HAVE_DLFCN_H
   // Now search the libraries.
-  SmartScopedLock<true> Lock(getMutex());
   if (OpenedHandles) {
-    for (std::vector<void *>::iterator I = OpenedHandles->begin(),
+    for (DenseSet<void *>::iterator I = OpenedHandles->begin(),
          E = OpenedHandles->end(); I != E; ++I) {
       //lt_ptr ptr = lt_dlsym(*I, symbolName);
       void *ptr = dlsym(*I, symbolName);

Modified: llvm/trunk/lib/Support/Windows/DynamicLibrary.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/DynamicLibrary.inc?rev=137791&r1=137790&r2=137791&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Windows/DynamicLibrary.inc (original)
+++ llvm/trunk/lib/Support/Windows/DynamicLibrary.inc Tue Aug 16 19:29:32 2011
@@ -39,7 +39,7 @@
 //===          and must not be UNIX code.
 //===----------------------------------------------------------------------===//
 
-static std::vector<HMODULE> OpenedHandles;
+static DenseSet<HMODULE> *OpenedHandles;
 
 extern "C" {
 
@@ -63,30 +63,43 @@
 #endif
         stricmp(ModuleName, "msvcrt20") != 0 &&
         stricmp(ModuleName, "msvcrt40") != 0) {
-      OpenedHandles.push_back((HMODULE)ModuleBase);
+      OpenedHandles->push_back((HMODULE)ModuleBase);
     }
     return TRUE;
   }
 }
 
-bool DynamicLibrary::LoadLibraryPermanently(const char *filename,
-                                            std::string *ErrMsg) {
-  if (filename) {
-    HMODULE a_handle = LoadLibrary(filename);
-
-    if (a_handle == 0)
-      return MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
-
-    OpenedHandles.push_back(a_handle);
-  } else {
-    // When no file is specified, enumerate all DLLs and EXEs in the
-    // process.
+DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename,
+                                                   std::string *errMsg) {
+  if (!filename) {
+    // When no file is specified, enumerate all DLLs and EXEs in the process.
+    SmartScopedLock<true> lock(getMutex());
+    if (OpenedHandles == 0)
+      OpenedHandles = new DenseSet<HMODULE>();
+
     EnumerateLoadedModules(GetCurrentProcess(), ELM_Callback, 0);
+    // Dummy library that represents "search all handles".
+    // This is mostly to ensure that the return value still shows up as "valid".
+    return DynamicLibrary(&OpenedHandles);
+  }
+  
+  HMODULE a_handle = LoadLibrary(filename);
+
+  if (a_handle == 0) {
+    MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
+    return DynamicLibrary();
   }
 
-  // Because we don't remember the handle, we will never free it; hence,
-  // it is loaded permanently.
-  return false;
+  SmartScopedLock<true> lock(getMutex());
+  if (OpenedHandles == 0)
+    OpenedHandles = new DenseSet<HMODULE>();
+
+  // If we've already loaded this library, FreeLibrary() the handle in order to
+  // keep the internal refcount at +1.
+  if (!OpenedHandles->insert(a_handle).second)
+    FreeLibrary(a_handle);
+
+  return DynamicLibrary(a_handle);
 }
 
 // Stack probing routines are in the support library (e.g. libgcc), but we don't
@@ -101,21 +114,24 @@
 #undef EXPLICIT_SYMBOL2
 
 void* DynamicLibrary::SearchForAddressOfSymbol(const char* symbolName) {
+  SmartScopedLock<true> Lock(getMutex());
+
   // First check symbols added via AddSymbol().
   if (ExplicitSymbols) {
-    std::map<std::string, void *>::iterator I =
-      ExplicitSymbols->find(symbolName);
-    std::map<std::string, void *>::iterator E = ExplicitSymbols->end();
-    if (I != E)
-      return I->second;
+    StringMap<void *>::iterator i = ExplicitSymbols->find(symbolName);
+
+    if (i != ExplicitSymbols->end())
+      return i->second;
   }
 
   // Now search the libraries.
-  for (std::vector<HMODULE>::iterator I = OpenedHandles.begin(),
-       E = OpenedHandles.end(); I != E; ++I) {
-    FARPROC ptr = GetProcAddress((HMODULE)*I, symbolName);
-    if (ptr) {
-      return (void *)(intptr_t)ptr;
+  if (OpenedHandles) {
+    for (DenseSet<HMODULE>::iterator I = OpenedHandles->begin(),
+         E = OpenedHandles->end(); I != E; ++I) {
+      FARPROC ptr = GetProcAddress((HMODULE)*I, symbolName);
+      if (ptr) {
+        return (void *)(intptr_t)ptr;
+      }
     }
   }
 
@@ -134,4 +150,14 @@
   return 0;
 }
 
+
+void *DynamicLibrary::getAddressOfSymbol(const char *symbolName) {
+  if (!isValid())
+    return NULL;
+  if (Data == &OpenedHandles)
+    return SearchForAddressOfSymbol(symbolName);
+  return (void *)(intptr_t)GetProcAddress((HMODULE)Data, symbolName);
+}
+
+
 }



From pichet2000 at gmail.com  Tue Aug 16 19:57:20 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Tue, 16 Aug 2011 20:57:20 -0400
Subject: [llvm-commits] [llvm] r137791 - in /llvm/trunk:
 include/llvm/Support/DynamicLibrary.h lib/Support/DynamicLibrary.cpp
 lib/Support/Windows/DynamicLibrary.inc
In-Reply-To: <20110817002932.A04612A6C12C@llvm.org>
References: <20110817002932.A04612A6C12C@llvm.org>
Message-ID: <CAH_MvcUucLH77oquJbvwYvY1bRuLLoWFhSMZ_c=VgSzSR5nu2Q@mail.gmail.com>

hi,

 2 compile errors on Windows:

On Tue, Aug 16, 2011 at 8:29 PM, Jordy Rose <jediknil at belkadan.com> wrote:
> Author: jrose
> Date: Tue Aug 16 19:29:32 2011
> New Revision: 137791
>
> ?extern "C" {
>
> @@ -63,30 +63,43 @@
> ?#endif
> ? ? ? ? stricmp(ModuleName, "msvcrt20") != 0 &&
> ? ? ? ? stricmp(ModuleName, "msvcrt40") != 0) {
> - ? ? ?OpenedHandles.push_back((HMODULE)ModuleBase);
> + ? ? ?OpenedHandles->push_back((HMODULE)ModuleBase);

A DenseSet doesn't have push_back, use insert.


> ? ? return TRUE;
> ? }
> ?}
>
> -bool DynamicLibrary::LoadLibraryPermanently(const char *filename,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?std::string *ErrMsg) {
> - ?if (filename) {
> - ? ?HMODULE a_handle = LoadLibrary(filename);
> -
> - ? ?if (a_handle == 0)
> - ? ? ?return MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
> -
> - ? ?OpenedHandles.push_back(a_handle);
> - ?} else {
> - ? ?// When no file is specified, enumerate all DLLs and EXEs in the
> - ? ?// process.
> +DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? std::string *errMsg) {
> + ?if (!filename) {
> + ? ?// When no file is specified, enumerate all DLLs and EXEs in the process.
> + ? ?SmartScopedLock<true> lock(getMutex());
> + ? ?if (OpenedHandles == 0)
> + ? ? ?OpenedHandles = new DenseSet<HMODULE>();
> +
> ? ? EnumerateLoadedModules(GetCurrentProcess(), ELM_Callback, 0);
> + ? ?// Dummy library that represents "search all handles".
> + ? ?// This is mostly to ensure that the return value still shows up as "valid".
> + ? ?return DynamicLibrary(&OpenedHandles);
> + ?}
> +
> + ?HMODULE a_handle = LoadLibrary(filename);
> +
> + ?if (a_handle == 0) {
> + ? ?MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");

errMsg


From jediknil at belkadan.com  Tue Aug 16 20:00:37 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Tue, 16 Aug 2011 18:00:37 -0700
Subject: [llvm-commits] [llvm] r137791 - in /llvm/trunk:
	include/llvm/Support/DynamicLibrary.h lib/Support/DynamicLibrary.cpp
	lib/Support/Windows/DynamicLibrary.inc
In-Reply-To: <CAH_MvcUucLH77oquJbvwYvY1bRuLLoWFhSMZ_c=VgSzSR5nu2Q@mail.gmail.com>
References: <20110817002932.A04612A6C12C@llvm.org>
	<CAH_MvcUucLH77oquJbvwYvY1bRuLLoWFhSMZ_c=VgSzSR5nu2Q@mail.gmail.com>
Message-ID: <5EBB125A-DD81-43DE-BB40-4D8D71F01151@belkadan.com>

Thanks...I don't have a Windows box to test on and made the edits blind. I know that's not a great idea... >_<


On Aug 16, 2011, at 17:57, Francois Pichet wrote:

> hi,
> 
> 2 compile errors on Windows:
> 
> On Tue, Aug 16, 2011 at 8:29 PM, Jordy Rose <jediknil at belkadan.com> wrote:
>> Author: jrose
>> Date: Tue Aug 16 19:29:32 2011
>> New Revision: 137791
>> 
>>  extern "C" {
>> 
>> @@ -63,30 +63,43 @@
>>  #endif
>>         stricmp(ModuleName, "msvcrt20") != 0 &&
>>         stricmp(ModuleName, "msvcrt40") != 0) {
>> -      OpenedHandles.push_back((HMODULE)ModuleBase);
>> +      OpenedHandles->push_back((HMODULE)ModuleBase);
> 
> A DenseSet doesn't have push_back, use insert.
> 
> 
>>     return TRUE;
>>   }
>>  }
>> 
>> -bool DynamicLibrary::LoadLibraryPermanently(const char *filename,
>> -                                            std::string *ErrMsg) {
>> -  if (filename) {
>> -    HMODULE a_handle = LoadLibrary(filename);
>> -
>> -    if (a_handle == 0)
>> -      return MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
>> -
>> -    OpenedHandles.push_back(a_handle);
>> -  } else {
>> -    // When no file is specified, enumerate all DLLs and EXEs in the
>> -    // process.
>> +DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename,
>> +                                                   std::string *errMsg) {
>> +  if (!filename) {
>> +    // When no file is specified, enumerate all DLLs and EXEs in the process.
>> +    SmartScopedLock<true> lock(getMutex());
>> +    if (OpenedHandles == 0)
>> +      OpenedHandles = new DenseSet<HMODULE>();
>> +
>>     EnumerateLoadedModules(GetCurrentProcess(), ELM_Callback, 0);
>> +    // Dummy library that represents "search all handles".
>> +    // This is mostly to ensure that the return value still shows up as "valid".
>> +    return DynamicLibrary(&OpenedHandles);
>> +  }
>> +
>> +  HMODULE a_handle = LoadLibrary(filename);
>> +
>> +  if (a_handle == 0) {
>> +    MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
> 
> errMsg



From jediknil at belkadan.com  Tue Aug 16 19:59:50 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 00:59:50 -0000
Subject: [llvm-commits] [llvm] r137798 -
	/llvm/trunk/lib/Support/Windows/DynamicLibrary.inc
Message-ID: <20110817005950.63BC42A6C12C@llvm.org>

Author: jrose
Date: Tue Aug 16 19:59:50 2011
New Revision: 137798

URL: http://llvm.org/viewvc/llvm-project?rev=137798&view=rev
Log:
Unbork Windows build. Thanks, Francois.

Modified:
    llvm/trunk/lib/Support/Windows/DynamicLibrary.inc

Modified: llvm/trunk/lib/Support/Windows/DynamicLibrary.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/DynamicLibrary.inc?rev=137798&r1=137797&r2=137798&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Windows/DynamicLibrary.inc (original)
+++ llvm/trunk/lib/Support/Windows/DynamicLibrary.inc Tue Aug 16 19:59:50 2011
@@ -63,7 +63,7 @@
 #endif
         stricmp(ModuleName, "msvcrt20") != 0 &&
         stricmp(ModuleName, "msvcrt40") != 0) {
-      OpenedHandles->push_back((HMODULE)ModuleBase);
+      OpenedHandles->insert((HMODULE)ModuleBase);
     }
     return TRUE;
   }
@@ -86,7 +86,7 @@
   HMODULE a_handle = LoadLibrary(filename);
 
   if (a_handle == 0) {
-    MakeErrMsg(ErrMsg, std::string(filename) + ": Can't open : ");
+    MakeErrMsg(errMsg, std::string(filename) + ": Can't open : ");
     return DynamicLibrary();
   }
 



From geek4civic at gmail.com  Tue Aug 16 20:28:30 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 17 Aug 2011 01:28:30 -0000
Subject: [llvm-commits] [llvm] r137800 -
	/llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
Message-ID: <20110817012830.A804B2A6C12C@llvm.org>

Author: chapuni
Date: Tue Aug 16 20:28:30 2011
New Revision: 137800

URL: http://llvm.org/viewvc/llvm-project?rev=137800&view=rev
Log:
CMake: [MSVC] Suppress C4551 'function call missing argument list'.

(void)static_func; it is used as idiom in llvm source tree to suppress "Unused static function" warnings.

Modified:
    llvm/trunk/cmake/modules/HandleLLVMOptions.cmake

Modified: llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/HandleLLVMOptions.cmake?rev=137800&r1=137799&r2=137800&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/HandleLLVMOptions.cmake (original)
+++ llvm/trunk/cmake/modules/HandleLLVMOptions.cmake Tue Aug 16 20:28:30 2011
@@ -155,6 +155,7 @@
     -wd4351 # Suppress 'new behavior: elements of array 'array' will be default initialized'
     -wd4355 # Suppress ''this' : used in base member initializer list'
     -wd4503 # Suppress ''identifier' : decorated name length exceeded, name was truncated'
+    -wd4551 # Suppress 'function call missing argument list'
     -wd4624 # Suppress ''derived class' : destructor could not be generated because a base class destructor is inaccessible'
     -wd4715 # Suppress ''function' : not all control paths return a value'
     -wd4800 # Suppress ''type' : forcing value to bool 'true' or 'false' (performance warning)'



From ahatanak at gmail.com  Tue Aug 16 21:05:42 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 02:05:42 -0000
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
Message-ID: <20110817020542.79CAE2A6C12C@llvm.org>

Author: ahatanak
Date: Tue Aug 16 21:05:42 2011
New Revision: 137804

URL: http://llvm.org/viewvc/llvm-project?rev=137804&view=rev
Log:
Add support for ext and ins.

Added:
    llvm/trunk/test/CodeGen/Mips/extins.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137804&r1=137803&r2=137804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 16 21:05:42 2011
@@ -35,6 +35,24 @@
 #include "llvm/Support/ErrorHandling.h"
 using namespace llvm;
 
+namespace {
+  // If I is a shifted mask, set the size (Size) and the first bit of the 
+  // mask (Pos), and return true.
+  bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
+                     uint64_t &Size) {
+    assert(SizeInBits == 32 || SizeInBits == 64);
+    bool Is32Bits = (SizeInBits == 32);
+
+    if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
+        (!Is32Bits && !isShiftedMask_64(I)))
+      return false;
+
+    Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
+    Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
+    return true;
+  }
+}
+
 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
@@ -62,6 +80,8 @@
   case MipsISD::WrapperPIC:        return "MipsISD::WrapperPIC";
   case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
   case MipsISD::Sync:              return "MipsISD::Sync";
+  case MipsISD::Ext:               return "MipsISD::Ext";
+  case MipsISD::Ins:               return "MipsISD::Ins";
   default:                         return NULL;
   }
 }
@@ -111,6 +131,8 @@
   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Custom);
   setOperationAction(ISD::VASTART,            MVT::Other, Custom);
+  setOperationAction(ISD::AND,                MVT::i32,   Custom);
+  setOperationAction(ISD::OR,                 MVT::i32,   Custom);
 
   setOperationAction(ISD::SDIV, MVT::i32, Expand);
   setOperationAction(ISD::SREM, MVT::i32, Expand);
@@ -539,6 +561,8 @@
     case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
     case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
     case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
+    case ISD::AND:                return LowerAND(Op, DAG);
+    case ISD::OR:                 return LowerOR(Op, DAG);
   }
   return SDValue();
 }
@@ -1556,6 +1580,98 @@
                      DAG.getConstant(SType, MVT::i32));
 }
 
+SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
+  // Pattern match EXT.
+  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
+  //  => ext $dst, $src, size, pos
+  if (!Subtarget->isMips32r2())
+    return Op;
+
+  SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
+  
+  // Op's first operand must be a shift right.
+  if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
+    return Op;
+
+  // The second operand of the shift must be an immediate.
+  uint64_t Pos;
+  ConstantSDNode *CN;
+  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
+    return Op;
+  
+  Pos = CN->getZExtValue();
+
+  uint64_t SMPos, SMSize;
+  // Op's second operand must be a shifted mask.
+  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
+      !IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
+    return Op;
+
+  // Return if the shifted mask does not start at bit 0 or the sum of its size
+  // and Pos exceeds the word's size.
+  if (SMPos != 0 || Pos + SMSize > 32)
+    return Op;
+
+  return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
+                     ShiftRight.getOperand(0),
+                     DAG.getConstant(SMSize, MVT::i32),
+                     DAG.getConstant(Pos, MVT::i32));
+}
+
+SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
+  // Pattern match INS.
+  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
+  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1 
+  //  => ins $dst, $src, size, pos
+  if (!Subtarget->isMips32r2())
+    return Op;
+
+  SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
+  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
+  ConstantSDNode *CN;
+
+  // See if Op's first operand matches (and $src1 , mask0).
+  if (And0.getOpcode() != ISD::AND)
+    return Op;
+
+  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
+      !IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
+    return Op;
+
+  // See if Op's second operand matches (and (shl $src, pos), mask1).
+  if (And1.getOpcode() != ISD::AND)
+    return Op;
+  
+  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
+      !IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
+                     SMSize1))
+    return Op;
+
+  // The shift masks must have the same position and size.
+  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
+    return Op;
+
+  SDValue Shl = And1.getOperand(0);
+  if (Shl.getOpcode() != ISD::SHL)
+    return Op;
+
+  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
+    return Op;
+
+  unsigned Shamt = CN->getZExtValue();
+
+  // Return if the shift amount and the first bit position of mask are not the
+  // same.  
+  if (Shamt != SMPos0)
+    return Op;
+  
+  return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
+                     Shl.getOperand(0),
+                     DAG.getConstant(SMSize0, MVT::i32),
+                     DAG.getConstant(SMPos0, MVT::i32),
+                     And0.getOperand(0));  
+}
+
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137804&r1=137803&r2=137804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Aug 16 21:05:42 2011
@@ -83,7 +83,10 @@
 
       DynAlloc,
 
-      Sync
+      Sync,
+
+      Ext,
+      Ins
     };
   }
 
@@ -134,6 +137,8 @@
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
+    SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
+    SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
 
     virtual SDValue
       LowerFormalArguments(SDValue Chain,

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137804&r1=137803&r2=137804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Aug 16 21:05:42 2011
@@ -102,6 +102,28 @@
   let Inst{25-0} = addr;
 }
 
+// Ext and Ins
+class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
+             list<dag> pattern, InstrItinClass itin>:
+  MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
+           pattern, itin>
+{
+  bits<5>  rt;
+  bits<5>  rs;
+  bits<5>  sz;
+  bits<5>  pos;
+  bits<6>  funct;
+
+  let opcode = 0x1f;
+  let funct  = _funct;
+
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = sz;
+  let Inst{10-6}  = pos;
+  let Inst{5-0}   = funct;
+}
+
 //===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137804&r1=137803&r2=137804&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Aug 16 21:05:42 2011
@@ -43,6 +43,12 @@
                                                SDTCisVT<1, iPTR>]>;
 def SDT_Sync             : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 
+def SDT_Ext : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
+                                   SDTCisInt<2>, SDTCisSameAs<2, 3>]>;
+def SDT_Ins : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
+                                   SDTCisInt<2>, SDTCisSameAs<2, 3>,
+                                   SDTCisSameAs<0, 4>]>;
+
 // Call
 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
                          [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
@@ -109,6 +115,9 @@
 
 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
 
+def MipsExt :  SDNode<"MipsISD::Ext", SDT_Ext>;
+def MipsIns :  SDNode<"MipsISD::Ins", SDT_Ins>;
+
 //===----------------------------------------------------------------------===//
 // Mips Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
@@ -661,6 +670,23 @@
 
 def RDHWR : ReadHardware;
 
+let Predicates = [IsMips32r2] in {
+  def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
+                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
+                   [(set CPURegs:$dst,
+                     (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
+                   NoItinerary>;
+  let Constraints = "$src1 = $dst" in
+  def Ins : ExtIns<0b000100, "ins",
+                   (outs CPURegs:$dst),
+                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
+                    CPURegs:$src1),
+                   [(set CPURegs:$dst,
+                     (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
+                      CPURegs:$src1))],
+                   NoItinerary>;
+}
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//

Added: llvm/trunk/test/CodeGen/Mips/extins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/extins.ll?rev=137804&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/extins.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/extins.ll Tue Aug 16 21:05:42 2011
@@ -0,0 +1,21 @@
+; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+
+define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
+entry:
+; CHECK: ext ${{[0-9]+}}, $4, 5, 9
+  %shr = lshr i32 %s, 5
+  %and = and i32 %shr, 511
+  ret i32 %and
+}
+
+define void @ins2_5_9(i32 %s, i32* nocapture %d) nounwind {
+entry:
+; CHECK: ins ${{[0-9]+}}, $4, 5, 9
+  %and = shl i32 %s, 5
+  %shl = and i32 %and, 16352
+  %tmp3 = load i32* %d, align 4
+  %and5 = and i32 %tmp3, -16353
+  %or = or i32 %and5, %shl
+  store i32 %or, i32* %d, align 4
+  ret void
+}



From bruno.cardoso at gmail.com  Tue Aug 16 21:29:18 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 16 Aug 2011 19:29:18 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <20110817020542.79CAE2A6C12C@llvm.org>
References: <20110817020542.79CAE2A6C12C@llvm.org>
Message-ID: <CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>

Hi Akira,

This is more appropriate as a target specific DAGCombine than regular
lowering. Can you please move the logic to do that?
Also, I don't see how ExtIns is different from FR class. Can you
change it to inherit from it instead? This would be better once we
have MC based object code emission, mips is simple enough that we can
emit the binaries easily based only on the basic formats.

Thanks

On Tue, Aug 16, 2011 at 7:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Tue Aug 16 21:05:42 2011
> New Revision: 137804
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137804&view=rev
> Log:
> Add support for ext and ins.
>
> Added:
> ? ?llvm/trunk/test/CodeGen/Mips/extins.ll
> Modified:
> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137804&r1=137803&r2=137804&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 16 21:05:42 2011
> @@ -35,6 +35,24 @@
> ?#include "llvm/Support/ErrorHandling.h"
> ?using namespace llvm;
>
> +namespace {
> + ?// If I is a shifted mask, set the size (Size) and the first bit of the
> + ?// mask (Pos), and return true.
> + ?bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
> + ? ? ? ? ? ? ? ? ? ? uint64_t &Size) {
> + ? ?assert(SizeInBits == 32 || SizeInBits == 64);
> + ? ?bool Is32Bits = (SizeInBits == 32);
> +
> + ? ?if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
> + ? ? ? ?(!Is32Bits && !isShiftedMask_64(I)))
> + ? ? ?return false;
> +
> + ? ?Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
> + ? ?Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
> + ? ?return true;
> + ?}
> +}
> +
> ?const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
> ? switch (Opcode) {
> ? case MipsISD::JmpLink: ? ? ? ? ? return "MipsISD::JmpLink";
> @@ -62,6 +80,8 @@
> ? case MipsISD::WrapperPIC: ? ? ? ?return "MipsISD::WrapperPIC";
> ? case MipsISD::DynAlloc: ? ? ? ? ?return "MipsISD::DynAlloc";
> ? case MipsISD::Sync: ? ? ? ? ? ? ?return "MipsISD::Sync";
> + ?case MipsISD::Ext: ? ? ? ? ? ? ? return "MipsISD::Ext";
> + ?case MipsISD::Ins: ? ? ? ? ? ? ? return "MipsISD::Ins";
> ? default: ? ? ? ? ? ? ? ? ? ? ? ? return NULL;
> ? }
> ?}
> @@ -111,6 +131,8 @@
> ? setOperationAction(ISD::BRCOND, ? ? ? ? ? ? MVT::Other, Custom);
> ? setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, ? Custom);
> ? setOperationAction(ISD::VASTART, ? ? ? ? ? ?MVT::Other, Custom);
> + ?setOperationAction(ISD::AND, ? ? ? ? ? ? ? ?MVT::i32, ? Custom);
> + ?setOperationAction(ISD::OR, ? ? ? ? ? ? ? ? MVT::i32, ? Custom);
>
> ? setOperationAction(ISD::SDIV, MVT::i32, Expand);
> ? setOperationAction(ISD::SREM, MVT::i32, Expand);
> @@ -539,6 +561,8 @@
> ? ? case ISD::FRAMEADDR: ? ? ? ? ?return LowerFRAMEADDR(Op, DAG);
> ? ? case ISD::MEMBARRIER: ? ? ? ? return LowerMEMBARRIER(Op, DAG);
> ? ? case ISD::ATOMIC_FENCE: ? ? ? return LowerATOMIC_FENCE(Op, DAG);
> + ? ?case ISD::AND: ? ? ? ? ? ? ? ?return LowerAND(Op, DAG);
> + ? ?case ISD::OR: ? ? ? ? ? ? ? ? return LowerOR(Op, DAG);
> ? }
> ? return SDValue();
> ?}
> @@ -1556,6 +1580,98 @@
> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SType, MVT::i32));
> ?}
>
> +SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
> + ?// Pattern match EXT.
> + ?// ?$dst = and ((sra or srl) $src , pos), (2**size - 1)
> + ?// ?=> ext $dst, $src, size, pos
> + ?if (!Subtarget->isMips32r2())
> + ? ?return Op;
> +
> + ?SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
> +
> + ?// Op's first operand must be a shift right.
> + ?if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
> + ? ?return Op;
> +
> + ?// The second operand of the shift must be an immediate.
> + ?uint64_t Pos;
> + ?ConstantSDNode *CN;
> + ?if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
> + ? ?return Op;
> +
> + ?Pos = CN->getZExtValue();
> +
> + ?uint64_t SMPos, SMSize;
> + ?// Op's second operand must be a shifted mask.
> + ?if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
> + ? ? ?!IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
> + ? ?return Op;
> +
> + ?// Return if the shifted mask does not start at bit 0 or the sum of its size
> + ?// and Pos exceeds the word's size.
> + ?if (SMPos != 0 || Pos + SMSize > 32)
> + ? ?return Op;
> +
> + ?return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
> + ? ? ? ? ? ? ? ? ? ? ShiftRight.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
> +}
> +
> +SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
> + ?// Pattern match INS.
> + ?// ?$dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
> + ?// ?where mask1 = (2**size - 1) << pos, mask0 = ~mask1
> + ?// ?=> ins $dst, $src, size, pos
> + ?if (!Subtarget->isMips32r2())
> + ? ?return Op;
> +
> + ?SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
> + ?uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
> + ?ConstantSDNode *CN;
> +
> + ?// See if Op's first operand matches (and $src1 , mask0).
> + ?if (And0.getOpcode() != ISD::AND)
> + ? ?return Op;
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
> + ? ? ?!IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
> + ? ?return Op;
> +
> + ?// See if Op's second operand matches (and (shl $src, pos), mask1).
> + ?if (And1.getOpcode() != ISD::AND)
> + ? ?return Op;
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
> + ? ? ?!IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
> + ? ? ? ? ? ? ? ? ? ? SMSize1))
> + ? ?return Op;
> +
> + ?// The shift masks must have the same position and size.
> + ?if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
> + ? ?return Op;
> +
> + ?SDValue Shl = And1.getOperand(0);
> + ?if (Shl.getOpcode() != ISD::SHL)
> + ? ?return Op;
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
> + ? ?return Op;
> +
> + ?unsigned Shamt = CN->getZExtValue();
> +
> + ?// Return if the shift amount and the first bit position of mask are not the
> + ?// same.
> + ?if (Shamt != SMPos0)
> + ? ?return Op;
> +
> + ?return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
> + ? ? ? ? ? ? ? ? ? ? Shl.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMPos0, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? And0.getOperand(0));
> +}
> +
> ?//===----------------------------------------------------------------------===//
> ?// ? ? ? ? ? ? ? ? ? ? ?Calling Convention Implementation
> ?//===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137804&r1=137803&r2=137804&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Aug 16 21:05:42 2011
> @@ -83,7 +83,10 @@
>
> ? ? ? DynAlloc,
>
> - ? ? ?Sync
> + ? ? ?Sync,
> +
> + ? ? ?Ext,
> + ? ? ?Ins
> ? ? };
> ? }
>
> @@ -134,6 +137,8 @@
> ? ? SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
> ? ? SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
> + ? ?SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
> + ? ?SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
>
> ? ? virtual SDValue
> ? ? ? LowerFormalArguments(SDValue Chain,
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137804&r1=137803&r2=137804&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Aug 16 21:05:42 2011
> @@ -102,6 +102,28 @@
> ? let Inst{25-0} = addr;
> ?}
>
> +// Ext and Ins
> +class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
> + ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
> + ?MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
> + ? ? ? ? ? pattern, itin>
> +{
> + ?bits<5> ?rt;
> + ?bits<5> ?rs;
> + ?bits<5> ?sz;
> + ?bits<5> ?pos;
> + ?bits<6> ?funct;
> +
> + ?let opcode = 0x1f;
> + ?let funct ?= _funct;
> +
> + ?let Inst{25-21} = rs;
> + ?let Inst{20-16} = rt;
> + ?let Inst{15-11} = sz;
> + ?let Inst{10-6} ?= pos;
> + ?let Inst{5-0} ? = funct;
> +}
> +
> ?//===----------------------------------------------------------------------===//
> ?//
> ?// ?FLOATING POINT INSTRUCTION FORMATS
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137804&r1=137803&r2=137804&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Aug 16 21:05:42 2011
> @@ -43,6 +43,12 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisVT<1, iPTR>]>;
> ?def SDT_Sync ? ? ? ? ? ? : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
>
> +def SDT_Ext : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>]>;
> +def SDT_Ins : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0, 4>]>;
> +
> ?// Call
> ?def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
> ? ? ? ? ? ? ? ? ? ? ? ? ?[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
> @@ -109,6 +115,9 @@
>
> ?def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
>
> +def MipsExt : ?SDNode<"MipsISD::Ext", SDT_Ext>;
> +def MipsIns : ?SDNode<"MipsISD::Ins", SDT_Ins>;
> +
> ?//===----------------------------------------------------------------------===//
> ?// Mips Instruction Predicate Definitions.
> ?//===----------------------------------------------------------------------===//
> @@ -661,6 +670,23 @@
>
> ?def RDHWR : ReadHardware;
>
> +let Predicates = [IsMips32r2] in {
> + ?def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
> + ? ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
> + ? ? ? ? ? ? ? ? ? NoItinerary>;
> + ?let Constraints = "$src1 = $dst" in
> + ?def Ins : ExtIns<0b000100, "ins",
> + ? ? ? ? ? ? ? ? ? (outs CPURegs:$dst),
> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src1),
> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
> + ? ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
> + ? ? ? ? ? ? ? ? ? ? ?CPURegs:$src1))],
> + ? ? ? ? ? ? ? ? ? NoItinerary>;
> +}
> +
> ?//===----------------------------------------------------------------------===//
> ?// ?Arbitrary patterns that map to one or more instructions
> ?//===----------------------------------------------------------------------===//
>
> Added: llvm/trunk/test/CodeGen/Mips/extins.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/extins.ll?rev=137804&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/extins.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/extins.ll Tue Aug 16 21:05:42 2011
> @@ -0,0 +1,21 @@
> +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
> +
> +define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
> +entry:
> +; CHECK: ext ${{[0-9]+}}, $4, 5, 9
> + ?%shr = lshr i32 %s, 5
> + ?%and = and i32 %shr, 511
> + ?ret i32 %and
> +}
> +
> +define void @ins2_5_9(i32 %s, i32* nocapture %d) nounwind {
> +entry:
> +; CHECK: ins ${{[0-9]+}}, $4, 5, 9
> + ?%and = shl i32 %s, 5
> + ?%shl = and i32 %and, 16352
> + ?%tmp3 = load i32* %d, align 4
> + ?%and5 = and i32 %tmp3, -16353
> + ?%or = or i32 %and5, %shl
> + ?store i32 %or, i32* %d, align 4
> + ?ret void
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Tue Aug 16 21:29:07 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 02:29:07 -0000
Subject: [llvm-commits] [llvm] r137806 - /llvm/trunk/utils/vim/llvm.vim
Message-ID: <20110817022907.DC0652A6C12C@llvm.org>

Author: bruno
Date: Tue Aug 16 21:29:07 2011
New Revision: 137806

URL: http://llvm.org/viewvc/llvm-project?rev=137806&view=rev
Log:
Update uwtable vim color!

Modified:
    llvm/trunk/utils/vim/llvm.vim

Modified: llvm/trunk/utils/vim/llvm.vim
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/vim/llvm.vim?rev=137806&r1=137805&r2=137806&view=diff
==============================================================================
--- llvm/trunk/utils/vim/llvm.vim (original)
+++ llvm/trunk/utils/vim/llvm.vim Tue Aug 16 21:29:07 2011
@@ -51,7 +51,7 @@
 syn keyword llvmKeyword x86_stdcallcc x86_fastcallcc
 syn keyword llvmKeyword ptx_kernel ptx_device
 syn keyword llvmKeyword signext zeroext inreg sret nounwind noreturn
-syn keyword llvmKeyword nocapture byval nest readnone readonly noalias
+syn keyword llvmKeyword nocapture byval nest readnone readonly noalias uwtable
 syn keyword llvmKeyword inlinehint noinline alwaysinline optsize ssp sspreq
 syn keyword llvmKeyword noredzone noimplicitfloat naked alignstack
 syn keyword llvmKeyword module asm align tail to



From bruno.cardoso at gmail.com  Tue Aug 16 21:29:10 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 02:29:10 -0000
Subject: [llvm-commits] [llvm] r137807 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-splat.ll
Message-ID: <20110817022911.16AC42A6C12D@llvm.org>

Author: bruno
Date: Tue Aug 16 21:29:10 2011
New Revision: 137807

URL: http://llvm.org/viewvc/llvm-project?rev=137807&view=rev
Log:
Now that we have a canonical way to handle 256-bit splats:
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-splat.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137807&r1=137806&r2=137807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 16 21:29:10 2011
@@ -4205,34 +4205,6 @@
   return DAG.getNode(ISD::BITCAST, dl, VT, V);
 }
 
-/// PromoteVectorToScalarSplat - Since there's no native support for
-/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector +
-/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the
-/// shuffle before the insertion, this yields less instructions in the end.
-static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV,
-                                          SelectionDAG &DAG) {
-  EVT SrcVT = SV->getValueType(0);
-  SDValue V1 = SV->getOperand(0);
-  DebugLoc dl = SV->getDebugLoc();
-  int NumElems = SrcVT.getVectorNumElements();
-
-  assert(SrcVT.is256BitVector() && "unknown howto handle vector type");
-  assert(SV->isSplat() && "shuffle must be a splat");
-
-  int SplatIdx = SV->getSplatIndex();
-  const int Mask[4] = { SplatIdx, SplatIdx, SplatIdx, SplatIdx };
-
-  EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
-                             NumElems/2);
-  SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1),
-                                     DAG.getUNDEF(SVT), Mask);
-  SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1,
-                                    DAG.getConstant(0, MVT::i32), DAG, dl);
-
-  return Insert128BitVector(InsV, SV1,
-                       DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
-}
-
 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
 /// v8i32, v16i16 or v32i8 to v8f32.
 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
@@ -6199,16 +6171,6 @@
     if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
       return Op;
 
-    // Since there's no native support for scalar_to_vector for 256-bit AVX, a
-    // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this
-    // idiom and do the shuffle before the insertion, this yields less
-    // instructions in the end.
-    if (VT.is256BitVector() &&
-        V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
-        V1.getOperand(0).getOpcode() == ISD::UNDEF &&
-        V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR)
-      return PromoteVectorToScalarSplat(SVOp, DAG);
-
     // Handle splats by matching through known shuffle masks
     if (VT.is128BitVector() && NumElem <= 4)
       return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=137807&r1=137806&r2=137807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Tue Aug 16 21:29:10 2011
@@ -24,8 +24,8 @@
 }
 
 ; CHECK: vmovd
-; CHECK-NEXT: movlhps
 ; CHECK-NEXT: vinsertf128 $1
+; CHECK-NEXT: vpermilps $0
 define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
 entry:
   %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
@@ -35,8 +35,8 @@
   ret <4 x i64> %vecinit6.i
 }
 
-; CHECK: vshufpd
-; CHECK-NEXT: vinsertf128 $1
+; CHECK: vinsertf128 $1
+; CHECK-NEXT: vpermilps $0
 define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
 entry:
   %vecinit.i = insertelement <4 x double> undef, double %q, i32 0
@@ -78,8 +78,8 @@
   ret <8 x float> %load_broadcast12281250
 }
 
-; CHECK: vpshufd  $0
-; CHECK-NEXT: vinsertf128 $1
+; CHECK: vinsertf128 $1
+; CHECK-NEXT: vpermilps $0
 define <8 x float> @funcF(i32* %ptr) nounwind {
   %val = load i32* %ptr, align 4
   %ret6 = insertelement <8 x i32> undef, i32 %val, i32 6



From bruno.cardoso at gmail.com  Tue Aug 16 21:29:13 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 02:29:13 -0000
Subject: [llvm-commits] [llvm] r137808 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110817022913.6497B2A6C12E@llvm.org>

Author: bruno
Date: Tue Aug 16 21:29:13 2011
New Revision: 137808

URL: http://llvm.org/viewvc/llvm-project?rev=137808&view=rev
Log:
Update comments about vector splat handling in x86

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137808&r1=137807&r2=137808&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 16 21:29:13 2011
@@ -4205,8 +4205,7 @@
   return DAG.getNode(ISD::BITCAST, dl, VT, V);
 }
 
-/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
-/// v8i32, v16i16 or v32i8 to v8f32.
+/// PromoteSplat - Splat is promoted to target supported vector shuffles.
 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
   EVT SrcVT = SV->getValueType(0);
   SDValue V1 = SV->getOperand(0);
@@ -4225,7 +4224,11 @@
       EltNo -= NumElems/2;
   }
 
-  // Make this 128-bit vector duplicate i8 and i16 elements
+  // All i16 and i8 vector types can't be used directly by a generic shuffle
+  // instruction because the target has no such instruction. Generate shuffles
+  // which repeat i16 and i8 several times until they fit in i32, and then can
+  // be manipulated by target suported shuffles. After the insertion of the
+  // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
   EVT EltVT = SrcVT.getVectorElementType();
   if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16))
     V1 = PromoteSplati8i16(V1, DAG, EltNo);
@@ -6175,11 +6178,7 @@
     if (VT.is128BitVector() && NumElem <= 4)
       return SDValue();
 
-    // All i16 and i8 vector types can't be used directly by a generic shuffle
-    // instruction because the target has no such instruction. Generate shuffles
-    // which repeat i16 and i8 several times until they fit in i32, and then can
-    // be manipulated by target suported shuffles. After the insertion of the
-    // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
+    // All remaning splats are promoted to target supported vector shuffles.
     return PromoteSplat(SVOp, DAG);
   }
 



From bruno.cardoso at gmail.com  Tue Aug 16 21:29:15 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 02:29:15 -0000
Subject: [llvm-commits] [llvm] r137809 -
	/llvm/trunk/test/CodeGen/X86/avx-splat.ll
Message-ID: <20110817022915.A909A2A6C12C@llvm.org>

Author: bruno
Date: Tue Aug 16 21:29:15 2011
New Revision: 137809

URL: http://llvm.org/viewvc/llvm-project?rev=137809&view=rev
Log:
Update test to not use the scalar type to splat from a load

Modified:
    llvm/trunk/test/CodeGen/X86/avx-splat.ll

Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=137809&r1=137808&r2=137809&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Tue Aug 16 21:29:15 2011
@@ -80,8 +80,7 @@
 
 ; CHECK: vinsertf128 $1
 ; CHECK-NEXT: vpermilps $0
-define <8 x float> @funcF(i32* %ptr) nounwind {
-  %val = load i32* %ptr, align 4
+define <8 x float> @funcF(i32 %val) nounwind {
   %ret6 = insertelement <8 x i32> undef, i32 %val, i32 6
   %ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
   %tmp = bitcast <8 x i32> %ret7 to <8 x float>



From bruno.cardoso at gmail.com  Tue Aug 16 21:29:19 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 02:29:19 -0000
Subject: [llvm-commits] [llvm] r137810 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx-vbroadcast.ll
Message-ID: <20110817022919.6E5912A6C12F@llvm.org>

Author: bruno
Date: Tue Aug 16 21:29:19 2011
New Revision: 137810

URL: http://llvm.org/viewvc/llvm-project?rev=137810&view=rev
Log:
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

Added:
    llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137810&r1=137809&r2=137810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 16 21:29:19 2011
@@ -6151,6 +6151,48 @@
   return 0;
 }
 
+/// isVectorBroadcast - Check if the node chain is suitable to be xformed to
+/// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
+/// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
+static bool isVectorBroadcast(SDValue &Op) {
+  EVT VT = Op.getValueType();
+  bool Is256 = VT.getSizeInBits() == 256;
+
+  assert((VT.getSizeInBits() == 128 || Is256) &&
+         "Unsupported type for vbroadcast node");
+
+  SDValue V = Op;
+  if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
+    V = V.getOperand(0);
+
+  if (Is256 && !(V.hasOneUse() &&
+                 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
+                 V.getOperand(0).getOpcode() == ISD::UNDEF))
+    return false;
+
+  if (Is256)
+    V = V.getOperand(1);
+  if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
+    return false;
+
+  // Check the source scalar_to_vector type. 256-bit broadcasts are
+  // supported for 32/64-bit sizes, while 128-bit ones are only supported
+  // for 32-bit scalars.
+  unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
+  if (ScalarSize != 32 && ScalarSize != 64)
+    return false;
+  if (!Is256 && ScalarSize == 64)
+    return false;
+
+  V = V.getOperand(0);
+  if (!MayFoldLoad(V))
+    return false;
+
+  // Return the load node
+  Op = V;
+  return true;
+}
+
 static
 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
                                const TargetLowering &TLI,
@@ -6174,6 +6216,10 @@
     if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
       return Op;
 
+    // Use vbroadcast whenever the splat comes from a foldable load
+    if (Subtarget->hasAVX() && isVectorBroadcast(V1))
+      return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
+
     // Handle splats by matching through known shuffle masks
     if (VT.is128BitVector() && NumElem <= 4)
       return SDValue();
@@ -10189,6 +10235,7 @@
   case X86ISD::PUNPCKHWD:          return "X86ISD::PUNPCKHWD";
   case X86ISD::PUNPCKHDQ:          return "X86ISD::PUNPCKHDQ";
   case X86ISD::PUNPCKHQDQ:         return "X86ISD::PUNPCKHQDQ";
+  case X86ISD::VBROADCAST:         return "X86ISD::VBROADCAST";
   case X86ISD::VPERMILPS:          return "X86ISD::VPERMILPS";
   case X86ISD::VPERMILPSY:         return "X86ISD::VPERMILPSY";
   case X86ISD::VPERMILPD:          return "X86ISD::VPERMILPD";

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=137810&r1=137809&r2=137810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Aug 16 21:29:19 2011
@@ -276,6 +276,7 @@
       VPERMILPD,
       VPERMILPDY,
       VPERM2F128,
+      VBROADCAST,
 
       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
       // according to %al. An operator is needed so that this can be expanded

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=137810&r1=137809&r2=137810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Aug 16 21:29:19 2011
@@ -109,6 +109,8 @@
 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                  SDTCisSameAs<0,2>, SDTCisInt<3>]>;
 
+def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
+
 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
 
 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
@@ -160,6 +162,8 @@
 
 def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
 
+def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
+
 //===----------------------------------------------------------------------===//
 // SSE Complex Patterns
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=137810&r1=137809&r2=137810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 16 21:29:19 2011
@@ -5474,6 +5474,20 @@
 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
           (VBROADCASTF128 addr:$src)>;
 
+def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VBROADCASTSSY addr:$src)>;
+def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
+          (VBROADCASTSD addr:$src)>;
+def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
+          (VBROADCASTSSY addr:$src)>;
+def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
+          (VBROADCASTSD addr:$src)>;
+
+def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
+          (VBROADCASTSS addr:$src)>;
+def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VBROADCASTSS addr:$src)>;
+
 //===----------------------------------------------------------------------===//
 // VINSERTF128 - Insert packed floating-point values
 //

Added: llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll?rev=137810&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll Tue Aug 16 21:29:19 2011
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; XFAIL: *
+
+; xfail this file for now because of PR8156, when it gets solved merge this with avx-splat.ll
+
+; CHECK: vbroadcastsd (%
+define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i64* %ptr, align 8
+  %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+  %vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
+  %vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
+  %vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
+  ret <4 x i64> %vecinit6.i
+}
+
+; CHECK: vbroadcastss (%
+define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i32* %ptr, align 4
+  %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
+  %vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
+  %vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
+  %vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
+  ret <8 x i32> %vecinit6.i
+}
+
+; CHECK: vbroadcastsd (%
+define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load double* %ptr, align 8
+  %vecinit.i = insertelement <4 x double> undef, double %q, i32 0
+  %vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
+  %vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
+  %vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
+  ret <4 x double> %vecinit6.i
+}
+
+; CHECK: vbroadcastss (%
+define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load float* %ptr, align 4
+  %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
+  %vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
+  %vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
+  %vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
+  ret <8 x float> %vecinit6.i
+}
+
+;;;; 128-bit versions
+
+; CHECK: vbroadcastss (%
+define <4 x float> @E(float* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load float* %ptr, align 4
+  %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+  %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
+  %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
+  %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
+  ret <4 x float> %vecinit6.i
+}
+
+; CHECK: vbroadcastss (%
+define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i32* %ptr, align 4
+  %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
+  %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
+  %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
+  %vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %q, i32 3
+  ret <4 x i32> %vecinit6.i
+}
+
+; Unsupported vbroadcasts
+
+; CHECK: _G
+; CHECK-NOT: vbroadcastsd (%
+define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i64* %ptr, align 8
+  %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
+  %vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
+  ret <2 x i64> %vecinit2.i
+}



From ahatanak at gmail.com  Tue Aug 16 22:13:59 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 16 Aug 2011 20:13:59 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
Message-ID: <CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>

Okay, I will make the changes tomorrow.

Thank you for your comments.

On Tue, Aug 16, 2011 at 7:29 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> Hi Akira,
>
> This is more appropriate as a target specific DAGCombine than regular
> lowering. Can you please move the logic to do that?
> Also, I don't see how ExtIns is different from FR class. Can you
> change it to inherit from it instead? This would be better once we
> have MC based object code emission, mips is simple enough that we can
> emit the binaries easily based only on the basic formats.
>
> Thanks
>
> On Tue, Aug 16, 2011 at 7:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>> Author: ahatanak
>> Date: Tue Aug 16 21:05:42 2011
>> New Revision: 137804
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=137804&view=rev
>> Log:
>> Add support for ext and ins.
>>
>> Added:
>> ? ?llvm/trunk/test/CodeGen/Mips/extins.ll
>> Modified:
>> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.h
>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137804&r1=137803&r2=137804&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 16 21:05:42 2011
>> @@ -35,6 +35,24 @@
>> ?#include "llvm/Support/ErrorHandling.h"
>> ?using namespace llvm;
>>
>> +namespace {
>> + ?// If I is a shifted mask, set the size (Size) and the first bit of the
>> + ?// mask (Pos), and return true.
>> + ?bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
>> + ? ? ? ? ? ? ? ? ? ? uint64_t &Size) {
>> + ? ?assert(SizeInBits == 32 || SizeInBits == 64);
>> + ? ?bool Is32Bits = (SizeInBits == 32);
>> +
>> + ? ?if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
>> + ? ? ? ?(!Is32Bits && !isShiftedMask_64(I)))
>> + ? ? ?return false;
>> +
>> + ? ?Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
>> + ? ?Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
>> + ? ?return true;
>> + ?}
>> +}
>> +
>> ?const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
>> ? switch (Opcode) {
>> ? case MipsISD::JmpLink: ? ? ? ? ? return "MipsISD::JmpLink";
>> @@ -62,6 +80,8 @@
>> ? case MipsISD::WrapperPIC: ? ? ? ?return "MipsISD::WrapperPIC";
>> ? case MipsISD::DynAlloc: ? ? ? ? ?return "MipsISD::DynAlloc";
>> ? case MipsISD::Sync: ? ? ? ? ? ? ?return "MipsISD::Sync";
>> + ?case MipsISD::Ext: ? ? ? ? ? ? ? return "MipsISD::Ext";
>> + ?case MipsISD::Ins: ? ? ? ? ? ? ? return "MipsISD::Ins";
>> ? default: ? ? ? ? ? ? ? ? ? ? ? ? return NULL;
>> ? }
>> ?}
>> @@ -111,6 +131,8 @@
>> ? setOperationAction(ISD::BRCOND, ? ? ? ? ? ? MVT::Other, Custom);
>> ? setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, ? Custom);
>> ? setOperationAction(ISD::VASTART, ? ? ? ? ? ?MVT::Other, Custom);
>> + ?setOperationAction(ISD::AND, ? ? ? ? ? ? ? ?MVT::i32, ? Custom);
>> + ?setOperationAction(ISD::OR, ? ? ? ? ? ? ? ? MVT::i32, ? Custom);
>>
>> ? setOperationAction(ISD::SDIV, MVT::i32, Expand);
>> ? setOperationAction(ISD::SREM, MVT::i32, Expand);
>> @@ -539,6 +561,8 @@
>> ? ? case ISD::FRAMEADDR: ? ? ? ? ?return LowerFRAMEADDR(Op, DAG);
>> ? ? case ISD::MEMBARRIER: ? ? ? ? return LowerMEMBARRIER(Op, DAG);
>> ? ? case ISD::ATOMIC_FENCE: ? ? ? return LowerATOMIC_FENCE(Op, DAG);
>> + ? ?case ISD::AND: ? ? ? ? ? ? ? ?return LowerAND(Op, DAG);
>> + ? ?case ISD::OR: ? ? ? ? ? ? ? ? return LowerOR(Op, DAG);
>> ? }
>> ? return SDValue();
>> ?}
>> @@ -1556,6 +1580,98 @@
>> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SType, MVT::i32));
>> ?}
>>
>> +SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
>> + ?// Pattern match EXT.
>> + ?// ?$dst = and ((sra or srl) $src , pos), (2**size - 1)
>> + ?// ?=> ext $dst, $src, size, pos
>> + ?if (!Subtarget->isMips32r2())
>> + ? ?return Op;
>> +
>> + ?SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
>> +
>> + ?// Op's first operand must be a shift right.
>> + ?if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
>> + ? ?return Op;
>> +
>> + ?// The second operand of the shift must be an immediate.
>> + ?uint64_t Pos;
>> + ?ConstantSDNode *CN;
>> + ?if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
>> + ? ?return Op;
>> +
>> + ?Pos = CN->getZExtValue();
>> +
>> + ?uint64_t SMPos, SMSize;
>> + ?// Op's second operand must be a shifted mask.
>> + ?if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
>> + ? ? ?!IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
>> + ? ?return Op;
>> +
>> + ?// Return if the shifted mask does not start at bit 0 or the sum of its size
>> + ?// and Pos exceeds the word's size.
>> + ?if (SMPos != 0 || Pos + SMSize > 32)
>> + ? ?return Op;
>> +
>> + ?return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
>> + ? ? ? ? ? ? ? ? ? ? ShiftRight.getOperand(0),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
>> +}
>> +
>> +SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
>> + ?// Pattern match INS.
>> + ?// ?$dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
>> + ?// ?where mask1 = (2**size - 1) << pos, mask0 = ~mask1
>> + ?// ?=> ins $dst, $src, size, pos
>> + ?if (!Subtarget->isMips32r2())
>> + ? ?return Op;
>> +
>> + ?SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
>> + ?uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
>> + ?ConstantSDNode *CN;
>> +
>> + ?// See if Op's first operand matches (and $src1 , mask0).
>> + ?if (And0.getOpcode() != ISD::AND)
>> + ? ?return Op;
>> +
>> + ?if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
>> + ? ? ?!IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
>> + ? ?return Op;
>> +
>> + ?// See if Op's second operand matches (and (shl $src, pos), mask1).
>> + ?if (And1.getOpcode() != ISD::AND)
>> + ? ?return Op;
>> +
>> + ?if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
>> + ? ? ?!IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
>> + ? ? ? ? ? ? ? ? ? ? SMSize1))
>> + ? ?return Op;
>> +
>> + ?// The shift masks must have the same position and size.
>> + ?if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
>> + ? ?return Op;
>> +
>> + ?SDValue Shl = And1.getOperand(0);
>> + ?if (Shl.getOpcode() != ISD::SHL)
>> + ? ?return Op;
>> +
>> + ?if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
>> + ? ?return Op;
>> +
>> + ?unsigned Shamt = CN->getZExtValue();
>> +
>> + ?// Return if the shift amount and the first bit position of mask are not the
>> + ?// same.
>> + ?if (Shamt != SMPos0)
>> + ? ?return Op;
>> +
>> + ?return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
>> + ? ? ? ? ? ? ? ? ? ? Shl.getOperand(0),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMPos0, MVT::i32),
>> + ? ? ? ? ? ? ? ? ? ? And0.getOperand(0));
>> +}
>> +
>> ?//===----------------------------------------------------------------------===//
>> ?// ? ? ? ? ? ? ? ? ? ? ?Calling Convention Implementation
>> ?//===----------------------------------------------------------------------===//
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137804&r1=137803&r2=137804&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Aug 16 21:05:42 2011
>> @@ -83,7 +83,10 @@
>>
>> ? ? ? DynAlloc,
>>
>> - ? ? ?Sync
>> + ? ? ?Sync,
>> +
>> + ? ? ?Ext,
>> + ? ? ?Ins
>> ? ? };
>> ? }
>>
>> @@ -134,6 +137,8 @@
>> ? ? SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
>> ? ? SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
>> ? ? SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
>> + ? ?SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
>> + ? ?SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
>>
>> ? ? virtual SDValue
>> ? ? ? LowerFormalArguments(SDValue Chain,
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137804&r1=137803&r2=137804&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Aug 16 21:05:42 2011
>> @@ -102,6 +102,28 @@
>> ? let Inst{25-0} = addr;
>> ?}
>>
>> +// Ext and Ins
>> +class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
>> + ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>> + ?MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
>> + ? ? ? ? ? pattern, itin>
>> +{
>> + ?bits<5> ?rt;
>> + ?bits<5> ?rs;
>> + ?bits<5> ?sz;
>> + ?bits<5> ?pos;
>> + ?bits<6> ?funct;
>> +
>> + ?let opcode = 0x1f;
>> + ?let funct ?= _funct;
>> +
>> + ?let Inst{25-21} = rs;
>> + ?let Inst{20-16} = rt;
>> + ?let Inst{15-11} = sz;
>> + ?let Inst{10-6} ?= pos;
>> + ?let Inst{5-0} ? = funct;
>> +}
>> +
>> ?//===----------------------------------------------------------------------===//
>> ?//
>> ?// ?FLOATING POINT INSTRUCTION FORMATS
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137804&r1=137803&r2=137804&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Aug 16 21:05:42 2011
>> @@ -43,6 +43,12 @@
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisVT<1, iPTR>]>;
>> ?def SDT_Sync ? ? ? ? ? ? : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
>>
>> +def SDT_Ext : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>]>;
>> +def SDT_Ins : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0, 4>]>;
>> +
>> ?// Call
>> ?def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
>> ? ? ? ? ? ? ? ? ? ? ? ? ?[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
>> @@ -109,6 +115,9 @@
>>
>> ?def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
>>
>> +def MipsExt : ?SDNode<"MipsISD::Ext", SDT_Ext>;
>> +def MipsIns : ?SDNode<"MipsISD::Ins", SDT_Ins>;
>> +
>> ?//===----------------------------------------------------------------------===//
>> ?// Mips Instruction Predicate Definitions.
>> ?//===----------------------------------------------------------------------===//
>> @@ -661,6 +670,23 @@
>>
>> ?def RDHWR : ReadHardware;
>>
>> +let Predicates = [IsMips32r2] in {
>> + ?def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
>> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
>> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>> + ? ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
>> + ? ? ? ? ? ? ? ? ? NoItinerary>;
>> + ?let Constraints = "$src1 = $dst" in
>> + ?def Ins : ExtIns<0b000100, "ins",
>> + ? ? ? ? ? ? ? ? ? (outs CPURegs:$dst),
>> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
>> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src1),
>> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>> + ? ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
>> + ? ? ? ? ? ? ? ? ? ? ?CPURegs:$src1))],
>> + ? ? ? ? ? ? ? ? ? NoItinerary>;
>> +}
>> +
>> ?//===----------------------------------------------------------------------===//
>> ?// ?Arbitrary patterns that map to one or more instructions
>> ?//===----------------------------------------------------------------------===//
>>
>> Added: llvm/trunk/test/CodeGen/Mips/extins.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/extins.ll?rev=137804&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Mips/extins.ll (added)
>> +++ llvm/trunk/test/CodeGen/Mips/extins.ll Tue Aug 16 21:05:42 2011
>> @@ -0,0 +1,21 @@
>> +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
>> +
>> +define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
>> +entry:
>> +; CHECK: ext ${{[0-9]+}}, $4, 5, 9
>> + ?%shr = lshr i32 %s, 5
>> + ?%and = and i32 %shr, 511
>> + ?ret i32 %and
>> +}
>> +
>> +define void @ins2_5_9(i32 %s, i32* nocapture %d) nounwind {
>> +entry:
>> +; CHECK: ins ${{[0-9]+}}, $4, 5, 9
>> + ?%and = shl i32 %s, 5
>> + ?%shl = and i32 %and, 16352
>> + ?%tmp3 = load i32* %d, align 4
>> + ?%and5 = and i32 %tmp3, -16353
>> + ?%or = or i32 %and5, %shl
>> + ?store i32 %or, i32* %d, align 4
>> + ?ret void
>> +}
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
>
>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>


From baldrick at free.fr  Wed Aug 17 01:09:14 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 08:09:14 +0200
Subject: [llvm-commits] [llvm] r137781 -
	/llvm/trunk/lib/Analysis/InstructionSimplify.cpp
In-Reply-To: <20110816223834.4ABE72A6C12C@llvm.org>
References: <20110816223834.4ABE72A6C12C@llvm.org>
Message-ID: <4E4B5B0A.3030707@free.fr>

Hi Eli,

> Extend the undef ^ undef idiom once more.  No testcase: I can't figure out how to actually trigger the codepath in question at the moment, but it might get exposed in the future.

if both Op0 and Op1 are undef, then this will have been done already in the
constant folding logic at the start of the function.  So I think this change
is pointless.

Ciao, Duncan.

>
>
> Modified:
>      llvm/trunk/lib/Analysis/InstructionSimplify.cpp
>
> Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=137781&r1=137780&r2=137781&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
> +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Aug 16 17:38:34 2011
> @@ -1348,6 +1348,11 @@
>       std::swap(Op0, Op1);
>     }
>
> +  // A ^ A = 0
> +  // Do this first so that we catch the undef ^ undef "idiom".
> +  if (Op0 == Op1)
> +    return Constant::getNullValue(Op0->getType());
> +
>     // A ^ undef ->  undef
>     if (match(Op1, m_Undef()))
>       return Op1;
> @@ -1356,10 +1361,6 @@
>     if (match(Op1, m_Zero()))
>       return Op0;
>
> -  // A ^ A = 0
> -  if (Op0 == Op1)
> -    return Constant::getNullValue(Op0->getType());
> -
>     // A ^ ~A  =  ~A ^ A  =  -1
>     if (match(Op0, m_Not(m_Specific(Op1))) ||
>         match(Op1, m_Not(m_Specific(Op0))))
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Wed Aug 17 01:21:23 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 06:21:23 -0000
Subject: [llvm-commits] [dragonegg] r137815 -
	/dragonegg/trunk/src/Convert.cpp
Message-ID: <20110817062123.DA7F92A6C12C@llvm.org>

Author: baldrick
Date: Wed Aug 17 01:21:23 2011
New Revision: 137815

URL: http://llvm.org/viewvc/llvm-project?rev=137815&view=rev
Log:
Fix thinko: GetFieldIndex returns INT_MAX if there is no such index,
not INT_MIN.

Modified:
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=137815&r1=137814&r2=137815&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Wed Aug 17 01:21:23 2011
@@ -1456,7 +1456,7 @@
         return TooCostly;
       // If there is no corresponding LLVM field then something funky is going
       // on - just give up.
-      if (GetFieldIndex(Field, Ty) == INT_MIN)
+      if (GetFieldIndex(Field, Ty) == INT_MAX)
         return TooCostly;
       TotalCost += CostOfAccessingAllElements(TREE_TYPE(Field));
       if (TotalCost >= TooCostly)
@@ -1504,7 +1504,7 @@
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
       // Get the address of the field.
       int FieldIdx = GetFieldIndex(Field, Ty);
-      assert(FieldIdx != INT_MIN && "Should not be copying if no LLVM field!");
+      assert(FieldIdx != INT_MAX && "Should not be copying if no LLVM field!");
       Value *DestFieldPtr = Builder.CreateStructGEP(DestLoc.Ptr, FieldIdx);
       Value *SrcFieldPtr = Builder.CreateStructGEP(SrcLoc.Ptr, FieldIdx);
 
@@ -1598,7 +1598,7 @@
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
       // Get the address of the field.
       int FieldIdx = GetFieldIndex(Field, Ty);
-      assert(FieldIdx != INT_MIN && "Should not be zeroing if no LLVM field!");
+      assert(FieldIdx != INT_MAX && "Should not be zeroing if no LLVM field!");
       Value *FieldPtr = Builder.CreateStructGEP(DestLoc.Ptr, FieldIdx);
 
       // Compute the field's alignment.



From baldrick at free.fr  Wed Aug 17 02:39:27 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 07:39:27 -0000
Subject: [llvm-commits] [dragonegg] r137817 - /dragonegg/trunk/src/Debug.cpp
Message-ID: <20110817073927.B72FD2A6C12D@llvm.org>

Author: baldrick
Date: Wed Aug 17 02:39:27 2011
New Revision: 137817

URL: http://llvm.org/viewvc/llvm-project?rev=137817&view=rev
Log:
Port commit 137753 (dpatel) from llvm-gcc.  Original commit message:
DIBuilder is moving forward to reduce in memory use by MDNodes. However, DIFactory does not emit debug info in updated form.
Use LLVMDebugVersion10 directly here so that debug info nodes produced by DIFactory do not claim to adhere newer structure.


Modified:
    dragonegg/trunk/src/Debug.cpp

Modified: dragonegg/trunk/src/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=137817&r1=137816&r2=137817&view=diff
==============================================================================
--- dragonegg/trunk/src/Debug.cpp (original)
+++ dragonegg/trunk/src/Debug.cpp Wed Aug 17 02:39:27 2011
@@ -1167,7 +1167,10 @@
 Constant *DIFactory::GetTagConstant(unsigned TAG) {
   assert((TAG & LLVMDebugVersionMask) == 0 &&
          "Tag too large for debug encoding!");
-  return ConstantInt::get(Type::getInt32Ty(VMContext), TAG | LLVMDebugVersion);
+  // llvm has moved forward. DIFactory does not emit debug info in updated form.
+  // Use LLVMDebugVersion10 directly here.
+  return ConstantInt::get(Type::getInt32Ty(VMContext), 
+                          TAG | LLVMDebugVersion10);
 }
 
 //===----------------------------------------------------------------------===//



From baldrick at free.fr  Wed Aug 17 02:44:50 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 09:44:50 +0200
Subject: [llvm-commits] Fwd: [llvm-gcc-4.2] r137753 -
	/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
In-Reply-To: <02D638C1-3C28-4A8E-AB4D-2F1E3B1B5C50@apple.com>
References: <20110816210327.1562D2A6C12C@llvm.org>
	<02D638C1-3C28-4A8E-AB4D-2F1E3B1B5C50@apple.com>
Message-ID: <4E4B7172.5020505@free.fr>

Thanks Devang - hopefully this will bring the builders back to life!

Ciao, Duncan.

On 16/08/11 23:08, Devang Patel wrote:
> Dragon-egg developers,
>
> Please apply this patch to dragon-egg also.
> Thanks!
> -
> Devang
>
> Begin forwarded message:
>
>> *From: *Devang Patel <dpatel at apple.com <mailto:dpatel at apple.com>>
>> *Date: *August 16, 2011 2:03:27 PM PDT
>> *To: *llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>> *Subject: **[llvm-commits] [llvm-gcc-4.2] r137753 -
>> /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp*
>>
>> Author: dpatel
>> Date: Tue Aug 16 16:03:26 2011
>> New Revision: 137753
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=137753&view=rev
>> <http://llvm.org/viewvc/llvm-project?rev=137753&view=rev>
>> Log:
>> DIBuilder is moving forward to reduce in memory use by MDNodes. However,
>> DIFactory does not emit debug info in updated form.
>> Use LLVMDebugVersion10 directly here so that debug info nodes produced by
>> DIFactory do not claim to adhere newer structure.
>>
>> Modified:
>> llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
>>
>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=137753&r1=137752&r2=137753&view=diff
>> <http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=137753&r1=137752&r2=137753&view=diff>
>> ==============================================================================
>> --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original)
>> +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Tue Aug 16 16:03:26 2011
>> @@ -1474,7 +1474,10 @@
>> Constant *DIFactory::GetTagConstant(unsigned TAG) {
>> assert((TAG & LLVMDebugVersionMask) == 0 &&
>> "Tag too large for debug encoding!");
>> - return ConstantInt::get(Type::getInt32Ty(VMContext), TAG | LLVMDebugVersion);
>> + // llvm has moved forward. DIFactory does not emit debug info in updated form.
>> + // Use LLVMDebugVersion10 directly here.
>> + return ConstantInt::get(Type::getInt32Ty(VMContext),
>> + TAG | LLVMDebugVersion10);
>> }
>>
>> //===----------------------------------------------------------------------===//
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From baldrick at free.fr  Wed Aug 17 02:49:32 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 07:49:32 -0000
Subject: [llvm-commits] [dragonegg] r137818 -
	/dragonegg/trunk/src/Convert.cpp
Message-ID: <20110817074933.0C0F62A6C12D@llvm.org>

Author: baldrick
Date: Wed Aug 17 02:49:32 2011
New Revision: 137818

URL: http://llvm.org/viewvc/llvm-project?rev=137818&view=rev
Log:
The Ada front-end likes to stick zero sized fields in structures.
We may or may not represent these fields in the LLVM type.  If we
don't then previously we would refuse to do element by element
struct copies because of that.  Instead just ignore such fields.
Also, the Ada front-end likes to preemptively mark fields as being
bitfields, even if they are not really.  So use a more sophisticated
bitfield test.

Modified:
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=137818&r1=137817&r2=137818&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Wed Aug 17 02:49:32 2011
@@ -1451,8 +1451,12 @@
     unsigned TotalCost = 0;
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
       assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
+      // Ignore fields of size zero.  This way, we don't give up just because
+      // there is a size zero field that is not represented in the LLVM type.
+      if (integer_zerop(DECL_SIZE(Field)))
+        continue;
       // Bitfields are too hard - give up.
-      if (DECL_BIT_FIELD(Field))
+      if (isBitfield(Field))
         return TooCostly;
       // If there is no corresponding LLVM field then something funky is going
       // on - just give up.
@@ -1502,6 +1506,9 @@
 
     // Copy each field in turn.
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
+      // Ignore fields of size zero.
+      if (integer_zerop(DECL_SIZE(Field)))
+        continue;
       // Get the address of the field.
       int FieldIdx = GetFieldIndex(Field, Ty);
       assert(FieldIdx != INT_MAX && "Should not be copying if no LLVM field!");
@@ -1596,6 +1603,9 @@
 
     // Zero each field in turn.
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
+      // Ignore fields of size zero.
+      if (integer_zerop(DECL_SIZE(Field)))
+        continue;
       // Get the address of the field.
       int FieldIdx = GetFieldIndex(Field, Ty);
       assert(FieldIdx != INT_MAX && "Should not be zeroing if no LLVM field!");



From baldrick at free.fr  Wed Aug 17 05:53:31 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 10:53:31 -0000
Subject: [llvm-commits] [dragonegg] r137824 -
	/dragonegg/trunk/src/Convert.cpp
Message-ID: <20110817105331.82FCD2A6C12C@llvm.org>

Author: baldrick
Date: Wed Aug 17 05:53:31 2011
New Revision: 137824

URL: http://llvm.org/viewvc/llvm-project?rev=137824&view=rev
Log:
Now that we test the field size to see if it is non-zero it is
also necessary to check that the field has a size (previously
this was not needed explicitly since it would be check later
by the recursion).  Also, allow an element-by-element memset/
memcpy that works on four elements or less (previously it was
three elements or less).

Modified:
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=137824&r1=137823&r2=137824&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Wed Aug 17 05:53:31 2011
@@ -1451,6 +1451,10 @@
     unsigned TotalCost = 0;
     for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
       assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
+      // If the field has no size, for example because it is a C-style variable
+      // length array, then just give up.
+      if (!DECL_SIZE(Field))
+        return TooCostly;
       // Ignore fields of size zero.  This way, we don't give up just because
       // there is a size zero field that is not represented in the LLVM type.
       if (integer_zerop(DECL_SIZE(Field)))
@@ -1565,7 +1569,7 @@
 }
 
 #ifndef TARGET_DRAGONEGG_MEMCPY_COST
-#define TARGET_DRAGONEGG_MEMCPY_COST 4
+#define TARGET_DRAGONEGG_MEMCPY_COST 5
 #endif
 
 /// EmitAggregateCopy - Copy the elements from SrcLoc to DestLoc, using the
@@ -1650,7 +1654,7 @@
 }
 
 #ifndef TARGET_DRAGONEGG_MEMSET_COST
-#define TARGET_DRAGONEGG_MEMSET_COST 4
+#define TARGET_DRAGONEGG_MEMSET_COST 5
 #endif
 
 /// EmitAggregateZero - Zero the elements of DestLoc.



From James.Molloy at arm.com  Wed Aug 17 06:54:49 2011
From: James.Molloy at arm.com (James Molloy)
Date: Wed, 17 Aug 2011 12:54:49 +0100
Subject: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
 UNPREDICTABLE insns as soft errors
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA473757133D6@GEORGE.Emea.Arm.com>
References: <003601cc5bf5$712dbdc0$53893940$%molloy@arm.com>,
	<8A075D8D-31BF-4073-9C31-BC843CD1A727@mac.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133D6@GEORGE.Emea.Arm.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA4737580E87D@GEORGE.Emea.Arm.com>

Hi,

New patch attached. Changelog from previous:

  * DecodeStatus promoted to MCDisassembler.h. "Unpredictable" renamed to "SoftFail" to be more target-agnostic.
  * FixedLenDecoderEmitter now is not parameterised by return type, although the guards and OK/Fail parameters remain.
  * llvm-mc adapted to now print a warning above the disassembly on soft fail. Example:

$ /work/llvm-cmake2/build/bin/./llvm-mc --disassemble /work/llvm-cmake2/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt -triple=arm-apple-darwin9    [12:06]
/work/llvm-cmake2/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt:10:1: warning: potentially undefined instruction encoding
0x05 0x70 0xd7 0xe6
^
        ldrb    r7, [r7], r5

  * invalid-LDRB_POST-arm.txt -> unpredictable-LDRB_POST-arm.txt and updated to look for the soft fail warning.

Hopefully this should be ready for committing. Should apply cleanly on ToT at now: r137824.

Cheers,

James

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of James Molloy
> Sent: 16 August 2011 19:56
> To: Owen Anderson
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
> UNPREDICTABLE insns as soft errors
>
> Hi Owen,
>
> Thanks. That does seem the most logical thing to do - I suppose I'm
> just used to open source projects where changing an abstraction can
> lead to violent uproar on mailing lists :)
>
> I'll wait for anyone to pipe up about the MCDisassembler change then
> adapt my patch.
>
> Thanks,
>
> James
> ________________________________________
> From: Owen Anderson [resistor at mac.com]
> Sent: 16 August 2011 19:44
> To: James Molloy
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
> UNPREDICTABLE insns as soft errors
>
> Hi James,
>
> My 2? are that I think it makes sense to expose DecodeStatus as part of
> MCDisassembler.  I don't know that any other targets use it offhand,
> but a "plausible but illegal" soft failure is at least a conceptually
> target-independent result.  Then we could just change the return type
> of getInstruction() to return a DecodeStatus.  At worst, ARM can be the
> only target that returns an Unpredictable result in practice.
>
> I suspect going this way will simplify the implementation (you'll get
> rid of at least one of the FixedLenDecoderEmitter parameters) without
> complicating other targets.   Does anyone else with an interest in the
> MCDisassembler care?
>
> Other than that decision, which we should resolve one way or another
> before applying it, you patch looks great.
>
> --Owen
>
> On Aug 16, 2011, at 2:18 AM, James Molloy wrote:
>
> Hi,
>
> As discussed on llvm-dev recently, this patch adds support for "soft-
> failing" on disassembly of certain ARM instructions.
>
> Certain instructions are marked as "UNPREDICTABLE" in the ARMARM - the
> disassembly of these instructions may still have value however,
> especially to a debugger or debugging code generated by another
> toolchain.
>
> This patch promotes the return value of all Decode* operations in the
> ARM disassembly to a ternary value (Success, Unpredictable, Fail) and
> touches a lot of the error handling code to perform status demotion
> from Success to Unpredictable, and returning early on Fail. It also
> touches the FixedLenDecoderEmitter to facilitate the same changes in
> autogenerated code.
>
> The major changelist is:
> *         Add a new type "DecodeStatus", local to ARMDisassembler.cpp,
> and add a macro CHECK(S, X) that will possibly demote a DecodeStatus S
> based on a function X's return value, and exit early if the value
> becomes "Fail".
> *         Modify the return value of Decode* from bool to
> "DecodeStatus", modify "if(!X()) return false;" to "CHECK(S, X());",
> assuming a local accumulator "DecodeStatus S = Success;".
> *         Parameterise FixedLenDecoderEmitter to take as extra
> (optional) arguments:
> o   The return value of the functions to emit (default "bool")
> o    "Guard" prefix and postfix to wrap any function call that may fail
> (default "if (!" and ") return false;" respectively)
> o   Value to return if everything went OK (default "true")
> o   Value to return on failure (default "false")
> o   Any extra local variables to add (default "")
> *         These defaults maintain the current behaviour of
> FixedLenDecoderEmitter. ARM/Thumb has been special cased in
> DisassemblerEmitter.cpp.
>
> The patch as is does not change the user-seen behaviour of the
> disassembler at all. I'm still not sure the best way to expose this
> information to the user.
>
> AFAIK, Intel or most other architectures don't have the same concept as
> ARM of a valid but unpredictable instruction. I'm therefore fearful of
> changing MCDisassembler.h to cope with it. At the moment I have an
> alternate getInstruction() function that also takes a bool& to which it
> writes if the insn was predictable or not.
>
> The problem with this obviously is that it requires the user to
> #include <ARMDisassembler.h>, which is impossible in the general case
> as it is a hidden header.
>
> I can see three options, none of which being particularly elegant:
>
> *         Make ARMDisassembler.h a public header so the user can
> cast<ARMDisassembler> and access an alternate getInstruction()
> function.
> *         Add a bool* parameter to getInstruction() for UNPREDICTABLE;
> default is NULL and the other backends ignore it.
> *         Add an "wasInsnUnpredictable()" function to MCDisassembler,
> which returns false for all other backends and only the ARM backend
> deals with. Nastily non-reentrant.
> *         ??? An alternative.
>
> What would you suggest?
>
> Cheers,
>
> James
> <unpredictable.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy
> the information in any medium.  Thank you.
>
>
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


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From geek4civic at gmail.com  Wed Aug 17 07:00:27 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 17 Aug 2011 21:00:27 +0900
Subject: [llvm-commits] [llvm] r137791 - in /llvm/trunk:
 include/llvm/Support/DynamicLibrary.h lib/Support/DynamicLibrary.cpp
 lib/Support/Windows/DynamicLibrary.inc
In-Reply-To: <20110817002932.A04612A6C12C@llvm.org>
References: <20110817002932.A04612A6C12C@llvm.org>
Message-ID: <CADiQthN3LP042RGLEnW+Js5OWWf10mOk1B3BMK3_Vo-f7Oj8xw@mail.gmail.com>

Good evening, Jordy.

WTF Cygwin! On Cygwin, RTLD_DEFAULT is NULL. Then,
DynamicLibrary::isValid() says Data(==RTLD_DEFAULT) might be invalid.

A suggested patch is here. Feel free to modify and apply it. :)

...Takumi
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From Micah.Villmow at amd.com  Wed Aug 17 10:36:39 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 10:36:39 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>

Forgot to send to llvm-commits.

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] AMDIL Target Triple patch
> 
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
> 
> Micah
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From justin.holewinski at gmail.com  Wed Aug 17 11:01:41 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 17 Aug 2011 12:01:41 -0400
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
Message-ID: <CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com>wrote:

> Forgot to send to llvm-commits.
>

Is the entire AMDIL back-end coming to LLVM ToT?


>
> > -----Original Message-----
> > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> > On Behalf Of Villmow, Micah
> > Sent: Wednesday, August 17, 2011 8:29 AM
> > To: llvmdev at cs.uiuc.edu
> > Subject: [LLVMdev] AMDIL Target Triple patch
> >
> > Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> > to LLVM.
> > I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> > next.
> >
> > Micah
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


-- 

Thanks,

Justin Holewinski
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From Micah.Villmow at amd.com  Wed Aug 17 11:07:42 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 11:07:42 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>



From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:02 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:
Forgot to send to llvm-commits.

Is the entire AMDIL back-end coming to LLVM ToT?
[Villmow, Micah] Yes, it is going through internal code review now. However, it will be posted for LLVM 2.9
first as that is what we are building against internally. After that, when I get time as I'm pretty busy, I will
update it for TOT.


> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu>]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
> Subject: [LLVMdev] AMDIL Target Triple patch
>
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
>
> Micah

_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



--
Thanks,

Justin Holewinski

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From tobias at grosser.es  Wed Aug 17 11:23:20 2011
From: tobias at grosser.es (Tobias Grosser)
Date: Wed, 17 Aug 2011 17:23:20 +0100
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
Message-ID: <4E4BEAF8.40606@grosser.es>

On 08/17/2011 05:07 PM, Villmow, Micah wrote:
> Is the entire AMDIL back-end coming to LLVM ToT?
>
> */[Villmow, Micah] Yes, it is going through internal code review now.
> However, it will be posted for LLVM 2.9 /*
>
> */first as that is what we are building against internally. After that,
> when I get time as I?m pretty busy, I will /*
>
> */update it for TOT./*

Hey,

this is great news. Thanks a lot for sharing this Micah.

Tobi

From justin.holewinski at gmail.com  Wed Aug 17 11:31:46 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 17 Aug 2011 12:31:46 -0400
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
Message-ID: <CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>

On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote:

> ** **
>
> ** **
>
> *From:* llvm-commits-bounces at cs.uiuc.edu [mailto:
> llvm-commits-bounces at cs.uiuc.edu] *On Behalf Of *Justin Holewinski
> *Sent:* Wednesday, August 17, 2011 9:02 AM
> *To:* Villmow, Micah
> *Cc:* llvm-commits
> *Subject:* Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch****
>
> ** **
>
> On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com>
> wrote:****
>
> Forgot to send to llvm-commits.****
>
> ** **
>
> Is the entire AMDIL back-end coming to LLVM ToT?****
>
> *[Villmow, Micah] Yes, it is going through internal code review now.
> However, it will be posted for LLVM 2.9 *
>
> *first as that is what we are building against internally. After that,
> when I get time as I?m pretty busy, I will *
>
> *update it for TOT.*
>

Awesome!

How will this integrate with the AMD APP SDK?  From what I understand, CAL
(and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.
 Is this going to somehow integrate with the AMD OpenCL implementation?


> ****
>
>  ****
>
>
> > -----Original Message-----
> > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> > On Behalf Of Villmow, Micah
> > Sent: Wednesday, August 17, 2011 8:29 AM
> > To: llvmdev at cs.uiuc.edu
> > Subject: [LLVMdev] AMDIL Target Triple patch****
>
> >
> > Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> > to LLVM.
> > I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> > next.
> >
> > Micah****
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits****
>
>
>
> ****
>
> ** **
>
> -- ****
>
> Thanks,****
>
> ** **
>
> Justin Holewinski****
>
> ** **
>



-- 

Thanks,

Justin Holewinski
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From Micah.Villmow at amd.com  Wed Aug 17 11:41:03 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 11:41:03 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>



From: Justin Holewinski [mailto:justin.holewinski at gmail.com]
Sent: Wednesday, August 17, 2011 9:32 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu> [mailto:llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu>] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:02 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:
Forgot to send to llvm-commits.

Is the entire AMDIL back-end coming to LLVM ToT?
[Villmow, Micah] Yes, it is going through internal code review now. However, it will be posted for LLVM 2.9
first as that is what we are building against internally. After that, when I get time as I'm pretty busy, I will
update it for TOT.

Awesome!

How will this integrate with the AMD APP SDK?  From what I understand, CAL (and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.  Is this going to somehow integrate with the AMD OpenCL implementation?
[Villmow, Micah] All I can say is that this is outside of the scope of the APP SDK. This is mainly to allow others to take advantage of targeting AMDIL from their own compilers and to see how
we implemented things using LLVM for a non-x86 like target.



> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu>]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
> Subject: [LLVMdev] AMDIL Target Triple patch
>
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
>
> Micah

_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski

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From justin.holewinski at gmail.com  Wed Aug 17 11:46:39 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 17 Aug 2011 12:46:39 -0400
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>
Message-ID: <CAJgxuaeQywnBVMtRsw-_nzj5cjCoevRamt-d5xcn-iNb=vm7Hg@mail.gmail.com>

On Wed, Aug 17, 2011 at 12:41 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote:

> ** **
>
> ** **
>
> *From:* Justin Holewinski [mailto:justin.holewinski at gmail.com]
> *Sent:* Wednesday, August 17, 2011 9:32 AM
>
> *To:* Villmow, Micah
> *Cc:* llvm-commits
> *Subject:* Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch****
>
> ** **
>
> On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com>
> wrote:****
>
>  ****
>
>  ****
>
> *From:* llvm-commits-bounces at cs.uiuc.edu [mailto:
> llvm-commits-bounces at cs.uiuc.edu] *On Behalf Of *Justin Holewinski
> *Sent:* Wednesday, August 17, 2011 9:02 AM
> *To:* Villmow, Micah
> *Cc:* llvm-commits
> *Subject:* Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch****
>
>  ****
>
> On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com>
> wrote:****
>
> Forgot to send to llvm-commits.****
>
>  ****
>
> Is the entire AMDIL back-end coming to LLVM ToT?****
>
> *[Villmow, Micah] Yes, it is going through internal code review now.
> However, it will be posted for LLVM 2.9 *****
>
> *first as that is what we are building against internally. After that,
> when I get time as I?m pretty busy, I will *****
>
> *update it for TOT.*****
>
> ** **
>
> Awesome!****
>
> ** **
>
> How will this integrate with the AMD APP SDK?  From what I understand, CAL
> (and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.
>  Is this going to somehow integrate with the AMD OpenCL implementation?***
> *
>
> *[Villmow, Micah] All I can say is that this is outside of the scope of
> the APP SDK. This is mainly to allow others to take advantage of targeting
> AMDIL from their own compilers and to see how*
>
> *we implemented things using LLVM for a non-x86 like target.*
>

So assuming I generate AMDIL using this back-end, then what?  How can I
execute it on real AMD hardware?


> ****
>
>  ****
>
>  ****
>
>
> > -----Original Message-----
> > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> > On Behalf Of Villmow, Micah
> > Sent: Wednesday, August 17, 2011 8:29 AM
> > To: llvmdev at cs.uiuc.edu
> > Subject: [LLVMdev] AMDIL Target Triple patch****
>
> >
> > Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> > to LLVM.
> > I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> > next.
> >
> > Micah****
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits****
>
>
>
> ****
>
>  ****
>
> -- ****
>
> Thanks,****
>
>  ****
>
> Justin Holewinski****
>
>  ****
>
>
>
> ****
>
> ** **
>
> -- ****
>
> Thanks,****
>
> ** **
>
> Justin Holewinski****
>
> ** **
>



-- 

Thanks,

Justin Holewinski
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From Micah.Villmow at amd.com  Wed Aug 17 12:06:12 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 12:06:12 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <CAJgxuaeQywnBVMtRsw-_nzj5cjCoevRamt-d5xcn-iNb=vm7Hg@mail.gmail.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>
	<CAJgxuaeQywnBVMtRsw-_nzj5cjCoevRamt-d5xcn-iNb=vm7Hg@mail.gmail.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE32CD@sausexmbp02.amd.com>



From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:47 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:41 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: Justin Holewinski [mailto:justin.holewinski at gmail.com<mailto:justin.holewinski at gmail.com>]
Sent: Wednesday, August 17, 2011 9:32 AM

To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu> [mailto:llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu>] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:02 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:
Forgot to send to llvm-commits.

Is the entire AMDIL back-end coming to LLVM ToT?
[Villmow, Micah] Yes, it is going through internal code review now. However, it will be posted for LLVM 2.9
first as that is what we are building against internally. After that, when I get time as I'm pretty busy, I will
update it for TOT.

Awesome!

How will this integrate with the AMD APP SDK?  From what I understand, CAL (and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.  Is this going to somehow integrate with the AMD OpenCL implementation?
[Villmow, Micah] All I can say is that this is outside of the scope of the APP SDK. This is mainly to allow others to take advantage of targeting AMDIL from their own compilers and to see how
we implemented things using LLVM for a non-x86 like target.

So assuming I generate AMDIL using this back-end, then what?  How can I execute it on real AMD hardware?
[Villmow, Micah] One way is to create an OpenCL binary using the output of AMDIL and load it into OpenCL. Another approach is to write a small runtime shim that converts from a compilation unit containing multiple kernels into single kernel per compilation unit and then use the CAL API to generate a CAL binary.  Our first step is to get the source code out there, and then based on feedback see what the next step can be to make it more useful.




> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu>]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
> Subject: [LLVMdev] AMDIL Target Triple patch
>
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
>
> Micah

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--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski

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From ahatanak at gmail.com  Wed Aug 17 12:25:13 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 10:25:13 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
Message-ID: <CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>

Encoding of instruction "ext $dst, $src, $pos, $size" looks like this:

field31-26, field25-21, field20-16, field15-11, field10-6, field5-0
31,           $src,          $dst,         $size,       $pos,       0

The FR format binds the operands in the following order,
(rd:field15-11), (rs:field25-21), (rt:field20-16), (shamt:field10-6)

so if I want to use the FR format to define "ext $dst, $src, $pos,
$size", the operands need to be given in the following order:

$size, $src, $dst, $pos

Is it possible to do so? In the format of FR, (dag outs) appears
before (dag ins).

On Tue, Aug 16, 2011 at 8:13 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Okay, I will make the changes tomorrow.
>
> Thank you for your comments.
>
> On Tue, Aug 16, 2011 at 7:29 PM, Bruno Cardoso Lopes
> <bruno.cardoso at gmail.com> wrote:
>> Hi Akira,
>>
>> This is more appropriate as a target specific DAGCombine than regular
>> lowering. Can you please move the logic to do that?
>> Also, I don't see how ExtIns is different from FR class. Can you
>> change it to inherit from it instead? This would be better once we
>> have MC based object code emission, mips is simple enough that we can
>> emit the binaries easily based only on the basic formats.
>>
>> Thanks
>>
>> On Tue, Aug 16, 2011 at 7:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>> Author: ahatanak
>>> Date: Tue Aug 16 21:05:42 2011
>>> New Revision: 137804
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=137804&view=rev
>>> Log:
>>> Add support for ext and ins.
>>>
>>> Added:
>>> ? ?llvm/trunk/test/CodeGen/Mips/extins.ll
>>> Modified:
>>> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>>> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.h
>>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137804&r1=137803&r2=137804&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 16 21:05:42 2011
>>> @@ -35,6 +35,24 @@
>>> ?#include "llvm/Support/ErrorHandling.h"
>>> ?using namespace llvm;
>>>
>>> +namespace {
>>> + ?// If I is a shifted mask, set the size (Size) and the first bit of the
>>> + ?// mask (Pos), and return true.
>>> + ?bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
>>> + ? ? ? ? ? ? ? ? ? ? uint64_t &Size) {
>>> + ? ?assert(SizeInBits == 32 || SizeInBits == 64);
>>> + ? ?bool Is32Bits = (SizeInBits == 32);
>>> +
>>> + ? ?if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
>>> + ? ? ? ?(!Is32Bits && !isShiftedMask_64(I)))
>>> + ? ? ?return false;
>>> +
>>> + ? ?Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
>>> + ? ?Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
>>> + ? ?return true;
>>> + ?}
>>> +}
>>> +
>>> ?const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
>>> ? switch (Opcode) {
>>> ? case MipsISD::JmpLink: ? ? ? ? ? return "MipsISD::JmpLink";
>>> @@ -62,6 +80,8 @@
>>> ? case MipsISD::WrapperPIC: ? ? ? ?return "MipsISD::WrapperPIC";
>>> ? case MipsISD::DynAlloc: ? ? ? ? ?return "MipsISD::DynAlloc";
>>> ? case MipsISD::Sync: ? ? ? ? ? ? ?return "MipsISD::Sync";
>>> + ?case MipsISD::Ext: ? ? ? ? ? ? ? return "MipsISD::Ext";
>>> + ?case MipsISD::Ins: ? ? ? ? ? ? ? return "MipsISD::Ins";
>>> ? default: ? ? ? ? ? ? ? ? ? ? ? ? return NULL;
>>> ? }
>>> ?}
>>> @@ -111,6 +131,8 @@
>>> ? setOperationAction(ISD::BRCOND, ? ? ? ? ? ? MVT::Other, Custom);
>>> ? setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, ? Custom);
>>> ? setOperationAction(ISD::VASTART, ? ? ? ? ? ?MVT::Other, Custom);
>>> + ?setOperationAction(ISD::AND, ? ? ? ? ? ? ? ?MVT::i32, ? Custom);
>>> + ?setOperationAction(ISD::OR, ? ? ? ? ? ? ? ? MVT::i32, ? Custom);
>>>
>>> ? setOperationAction(ISD::SDIV, MVT::i32, Expand);
>>> ? setOperationAction(ISD::SREM, MVT::i32, Expand);
>>> @@ -539,6 +561,8 @@
>>> ? ? case ISD::FRAMEADDR: ? ? ? ? ?return LowerFRAMEADDR(Op, DAG);
>>> ? ? case ISD::MEMBARRIER: ? ? ? ? return LowerMEMBARRIER(Op, DAG);
>>> ? ? case ISD::ATOMIC_FENCE: ? ? ? return LowerATOMIC_FENCE(Op, DAG);
>>> + ? ?case ISD::AND: ? ? ? ? ? ? ? ?return LowerAND(Op, DAG);
>>> + ? ?case ISD::OR: ? ? ? ? ? ? ? ? return LowerOR(Op, DAG);
>>> ? }
>>> ? return SDValue();
>>> ?}
>>> @@ -1556,6 +1580,98 @@
>>> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SType, MVT::i32));
>>> ?}
>>>
>>> +SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
>>> + ?// Pattern match EXT.
>>> + ?// ?$dst = and ((sra or srl) $src , pos), (2**size - 1)
>>> + ?// ?=> ext $dst, $src, size, pos
>>> + ?if (!Subtarget->isMips32r2())
>>> + ? ?return Op;
>>> +
>>> + ?SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
>>> +
>>> + ?// Op's first operand must be a shift right.
>>> + ?if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
>>> + ? ?return Op;
>>> +
>>> + ?// The second operand of the shift must be an immediate.
>>> + ?uint64_t Pos;
>>> + ?ConstantSDNode *CN;
>>> + ?if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
>>> + ? ?return Op;
>>> +
>>> + ?Pos = CN->getZExtValue();
>>> +
>>> + ?uint64_t SMPos, SMSize;
>>> + ?// Op's second operand must be a shifted mask.
>>> + ?if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
>>> + ? ? ?!IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
>>> + ? ?return Op;
>>> +
>>> + ?// Return if the shifted mask does not start at bit 0 or the sum of its size
>>> + ?// and Pos exceeds the word's size.
>>> + ?if (SMPos != 0 || Pos + SMSize > 32)
>>> + ? ?return Op;
>>> +
>>> + ?return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
>>> + ? ? ? ? ? ? ? ? ? ? ShiftRight.getOperand(0),
>>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
>>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
>>> +}
>>> +
>>> +SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
>>> + ?// Pattern match INS.
>>> + ?// ?$dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
>>> + ?// ?where mask1 = (2**size - 1) << pos, mask0 = ~mask1
>>> + ?// ?=> ins $dst, $src, size, pos
>>> + ?if (!Subtarget->isMips32r2())
>>> + ? ?return Op;
>>> +
>>> + ?SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
>>> + ?uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
>>> + ?ConstantSDNode *CN;
>>> +
>>> + ?// See if Op's first operand matches (and $src1 , mask0).
>>> + ?if (And0.getOpcode() != ISD::AND)
>>> + ? ?return Op;
>>> +
>>> + ?if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
>>> + ? ? ?!IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
>>> + ? ?return Op;
>>> +
>>> + ?// See if Op's second operand matches (and (shl $src, pos), mask1).
>>> + ?if (And1.getOpcode() != ISD::AND)
>>> + ? ?return Op;
>>> +
>>> + ?if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
>>> + ? ? ?!IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
>>> + ? ? ? ? ? ? ? ? ? ? SMSize1))
>>> + ? ?return Op;
>>> +
>>> + ?// The shift masks must have the same position and size.
>>> + ?if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
>>> + ? ?return Op;
>>> +
>>> + ?SDValue Shl = And1.getOperand(0);
>>> + ?if (Shl.getOpcode() != ISD::SHL)
>>> + ? ?return Op;
>>> +
>>> + ?if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
>>> + ? ?return Op;
>>> +
>>> + ?unsigned Shamt = CN->getZExtValue();
>>> +
>>> + ?// Return if the shift amount and the first bit position of mask are not the
>>> + ?// same.
>>> + ?if (Shamt != SMPos0)
>>> + ? ?return Op;
>>> +
>>> + ?return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
>>> + ? ? ? ? ? ? ? ? ? ? Shl.getOperand(0),
>>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
>>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMPos0, MVT::i32),
>>> + ? ? ? ? ? ? ? ? ? ? And0.getOperand(0));
>>> +}
>>> +
>>> ?//===----------------------------------------------------------------------===//
>>> ?// ? ? ? ? ? ? ? ? ? ? ?Calling Convention Implementation
>>> ?//===----------------------------------------------------------------------===//
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137804&r1=137803&r2=137804&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Aug 16 21:05:42 2011
>>> @@ -83,7 +83,10 @@
>>>
>>> ? ? ? DynAlloc,
>>>
>>> - ? ? ?Sync
>>> + ? ? ?Sync,
>>> +
>>> + ? ? ?Ext,
>>> + ? ? ?Ins
>>> ? ? };
>>> ? }
>>>
>>> @@ -134,6 +137,8 @@
>>> ? ? SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
>>> ? ? SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
>>> ? ? SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
>>> + ? ?SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
>>> + ? ?SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
>>>
>>> ? ? virtual SDValue
>>> ? ? ? LowerFormalArguments(SDValue Chain,
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137804&r1=137803&r2=137804&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Aug 16 21:05:42 2011
>>> @@ -102,6 +102,28 @@
>>> ? let Inst{25-0} = addr;
>>> ?}
>>>
>>> +// Ext and Ins
>>> +class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
>>> + ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>>> + ?MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
>>> + ? ? ? ? ? pattern, itin>
>>> +{
>>> + ?bits<5> ?rt;
>>> + ?bits<5> ?rs;
>>> + ?bits<5> ?sz;
>>> + ?bits<5> ?pos;
>>> + ?bits<6> ?funct;
>>> +
>>> + ?let opcode = 0x1f;
>>> + ?let funct ?= _funct;
>>> +
>>> + ?let Inst{25-21} = rs;
>>> + ?let Inst{20-16} = rt;
>>> + ?let Inst{15-11} = sz;
>>> + ?let Inst{10-6} ?= pos;
>>> + ?let Inst{5-0} ? = funct;
>>> +}
>>> +
>>> ?//===----------------------------------------------------------------------===//
>>> ?//
>>> ?// ?FLOATING POINT INSTRUCTION FORMATS
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137804&r1=137803&r2=137804&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Aug 16 21:05:42 2011
>>> @@ -43,6 +43,12 @@
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisVT<1, iPTR>]>;
>>> ?def SDT_Sync ? ? ? ? ? ? : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
>>>
>>> +def SDT_Ext : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>]>;
>>> +def SDT_Ins : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisInt<2>, SDTCisSameAs<2, 3>,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0, 4>]>;
>>> +
>>> ?// Call
>>> ?def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ?[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
>>> @@ -109,6 +115,9 @@
>>>
>>> ?def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
>>>
>>> +def MipsExt : ?SDNode<"MipsISD::Ext", SDT_Ext>;
>>> +def MipsIns : ?SDNode<"MipsISD::Ins", SDT_Ins>;
>>> +
>>> ?//===----------------------------------------------------------------------===//
>>> ?// Mips Instruction Predicate Definitions.
>>> ?//===----------------------------------------------------------------------===//
>>> @@ -661,6 +670,23 @@
>>>
>>> ?def RDHWR : ReadHardware;
>>>
>>> +let Predicates = [IsMips32r2] in {
>>> + ?def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
>>> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
>>> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>>> + ? ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
>>> + ? ? ? ? ? ? ? ? ? NoItinerary>;
>>> + ?let Constraints = "$src1 = $dst" in
>>> + ?def Ins : ExtIns<0b000100, "ins",
>>> + ? ? ? ? ? ? ? ? ? (outs CPURegs:$dst),
>>> + ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
>>> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src1),
>>> + ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>>> + ? ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
>>> + ? ? ? ? ? ? ? ? ? ? ?CPURegs:$src1))],
>>> + ? ? ? ? ? ? ? ? ? NoItinerary>;
>>> +}
>>> +
>>> ?//===----------------------------------------------------------------------===//
>>> ?// ?Arbitrary patterns that map to one or more instructions
>>> ?//===----------------------------------------------------------------------===//
>>>
>>> Added: llvm/trunk/test/CodeGen/Mips/extins.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/extins.ll?rev=137804&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/Mips/extins.ll (added)
>>> +++ llvm/trunk/test/CodeGen/Mips/extins.ll Tue Aug 16 21:05:42 2011
>>> @@ -0,0 +1,21 @@
>>> +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
>>> +
>>> +define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
>>> +entry:
>>> +; CHECK: ext ${{[0-9]+}}, $4, 5, 9
>>> + ?%shr = lshr i32 %s, 5
>>> + ?%and = and i32 %shr, 511
>>> + ?ret i32 %and
>>> +}
>>> +
>>> +define void @ins2_5_9(i32 %s, i32* nocapture %d) nounwind {
>>> +entry:
>>> +; CHECK: ins ${{[0-9]+}}, $4, 5, 9
>>> + ?%and = shl i32 %s, 5
>>> + ?%shl = and i32 %and, 16352
>>> + ?%tmp3 = load i32* %d, align 4
>>> + ?%and5 = and i32 %tmp3, -16353
>>> + ?%or = or i32 %and5, %shl
>>> + ?store i32 %or, i32* %d, align 4
>>> + ?ret void
>>> +}
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>
>>
>>
>> --
>> Bruno Cardoso Lopes
>> http://www.brunocardoso.cc
>>
>


From resistor at mac.com  Wed Aug 17 12:44:16 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 17 Aug 2011 17:44:16 -0000
Subject: [llvm-commits] [llvm] r137830 - in /llvm/trunk: include/llvm/MC/
 lib/Target/ARM/Disassembler/ lib/Target/MBlaze/Disassembler/
 lib/Target/X86/Disassembler/ test/MC/Disassembler/ARM/ tools/llvm-mc/
 utils/TableGen/
Message-ID: <20110817174416.558E12A6C12C@llvm.org>

Author: resistor
Date: Wed Aug 17 12:44:15 2011
New Revision: 137830

URL: http://llvm.org/viewvc/llvm-project?rev=137830&view=rev
Log:
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid.  Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

Modified:
    llvm/trunk/include/llvm/MC/MCDisassembler.h
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
    llvm/trunk/tools/llvm-mc/Disassembler.cpp
    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h

Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCDisassembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Aug 17 12:44:15 2011
@@ -25,6 +25,34 @@
 ///   and provides an array of assembly instructions.
 class MCDisassembler {
 public:
+  /// Ternary decode status. Most backends will just use Fail and
+  /// Success, however some have a concept of an instruction with
+  /// understandable semantics but which is architecturally
+  /// incorrect. An example of this is ARM UNPREDICTABLE instructions
+  /// which are disassemblable but cause undefined behaviour.
+  ///
+  /// Because it makes sense to disassemble these instructions, there
+  /// is a "soft fail" failure mode that indicates the MCInst& is
+  /// valid but architecturally incorrect.
+  ///
+  /// The enum numbers are deliberately chosen such that reduction
+  /// from Success->SoftFail ->Fail can be done with a simple
+  /// bitwise-AND:
+  ///
+  ///   LEFT & TOP =  | Success       Unpredictable   Fail
+  ///   --------------+-----------------------------------
+  ///   Success       | Success       Unpredictable   Fail
+  ///   Unpredictable | Unpredictable Unpredictable   Fail
+  ///   Fail          | Fail          Fail            Fail
+  ///
+  /// An easy way of encoding this is as 0b11, 0b01, 0b00 for
+  /// Success, SoftFail, Fail respectively.
+  enum DecodeStatus {
+    Fail = 0,
+    SoftFail = 1,
+    Success = 3
+  };
+
   /// Constructor     - Performs initial setup for the disassembler.
   MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {}
   
@@ -41,8 +69,11 @@
   /// @param address  - The address, in the memory space of region, of the first
   ///                   byte of the instruction.
   /// @param vStream  - The stream to print warnings and diagnostic messages on.
-  /// @return         - True if the instruction is valid; false otherwise.
-  virtual bool          getInstruction(MCInst& instr,
+  /// @return         - MCDisassembler::Success if the instruction is valid,
+  ///                   MCDisassembler::SoftFail if the instruction was 
+  ///                                            disassemblable but invalid,
+  ///                   MCDisassembler::Fail if the instruction was invalid.
+  virtual DecodeStatus  getInstruction(MCInst& instr,
                                        uint64_t& size,
                                        const MemoryObject &region,
                                        uint64_t address,

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 12:44:15 2011
@@ -24,188 +24,201 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 
+// Pull DecodeStatus and its enum values into the global namespace.
+typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
+#define Success llvm::MCDisassembler::Success
+#define Unpredictable llvm::MCDisassembler::SoftFail
+#define Fail llvm::MCDisassembler::Fail
+
+// Helper macro to perform setwise reduction of the current running status
+// and another status, and return if the new status is Fail.
+#define CHECK(S,X) do {                           \
+    S = (DecodeStatus) ((int)S & (X));            \
+    if (S == Fail) return Fail;                   \
+  } while(0)
+
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
-static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 
-static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 
-static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 
-static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
+static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
                                                   unsigned Insn,
                                                   uint64_t Adddress,
                                                   const void *Decoder);
-static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 
 
-static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
+static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
                                uint64_t Address, const void *Decoder);
-static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
@@ -230,15 +243,14 @@
   return instInfoARM;
 }
 
-
-bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
-                                     const MemoryObject &Region,
-                                     uint64_t Address,raw_ostream &os) const {
+DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+                                             const MemoryObject &Region,
+                                             uint64_t Address,raw_ostream &os) const {
   uint8_t bytes[4];
 
   // We want to read exactly 4 bytes of data.
   if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
-    return false;
+    return Fail;
 
   // Encoded as a small-endian 32-bit word in the stream.
   uint32_t insn = (bytes[3] << 24) |
@@ -247,10 +259,10 @@
                   (bytes[0] <<  0);
 
   // Calling the auto-generated decoder function.
-  bool result = decodeARMInstruction32(MI, insn, Address, this);
-  if (result) {
+  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
+  if (result != Fail) {
     Size = 4;
-    return true;
+    return result;
   }
 
   // Instructions that are shared between ARM and Thumb modes.
@@ -258,53 +270,53 @@
   // fact that we fail to encode a few instructions properly for Thumb.
   MI.clear();
   result = decodeCommonInstruction32(MI, insn, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
-    return true;
+    return result;
   }
 
   // VFP and NEON instructions, similarly, are shared between ARM
   // and Thumb modes.
   MI.clear();
   result = decodeVFPInstruction32(MI, insn, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeNEONDataInstruction32(MI, insn, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
     // definitions with Thumb2 where these instructions are predicable.
-    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
-    return true;
+    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+    return result;
   }
 
   MI.clear();
   result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
     // definitions with Thumb2 where these instructions are predicable.
-    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
-    return true;
+    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+    return result;
   }
 
   MI.clear();
   result = decodeNEONDupInstruction32(MI, insn, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
     // definitions with Thumb2 where these instructions are predicable.
-    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
-    return true;
+    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+    return result;
   }
 
   MI.clear();
 
-  return false;
+  return Fail;
 }
 
 namespace llvm {
@@ -403,22 +415,21 @@
   }
 }
 
-
-bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
-                                       const MemoryObject &Region,
-                                       uint64_t Address,raw_ostream &os) const {
+DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+                                               const MemoryObject &Region,
+                                               uint64_t Address,raw_ostream &os) const {
   uint8_t bytes[4];
 
   // We want to read exactly 2 bytes of data.
   if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
-    return false;
+    return Fail;
 
   uint16_t insn16 = (bytes[1] << 8) | bytes[0];
-  bool result = decodeThumbInstruction16(MI, insn16, Address, this);
-  if (result) {
+  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
+  if (result != Fail) {
     Size = 2;
     AddThumbPredicate(MI);
-    return true;
+    return result;
   }
 
   MI.clear();
@@ -428,12 +439,12 @@
     bool InITBlock = !ITBlock.empty();
     AddThumbPredicate(MI);
     AddThumb1SBit(MI, InITBlock);
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeThumb2Instruction16(MI, insn16, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 2;
     AddThumbPredicate(MI);
 
@@ -456,12 +467,12 @@
       ITBlock.push_back(firstcond);
     }
 
-    return true;
+    return result;
   }
 
   // We want to read exactly 4 bytes of data.
   if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
-    return false;
+    return Fail;
 
   uint32_t insn32 = (bytes[3] <<  8) |
                     (bytes[2] <<  0) |
@@ -469,44 +480,44 @@
                     (bytes[0] << 16);
   MI.clear();
   result = decodeThumbInstruction32(MI, insn32, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     bool InITBlock = ITBlock.size();
     AddThumbPredicate(MI);
     AddThumb1SBit(MI, InITBlock);
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeThumb2Instruction32(MI, insn32, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     AddThumbPredicate(MI);
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeCommonInstruction32(MI, insn32, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     AddThumbPredicate(MI);
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeVFPInstruction32(MI, insn32, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     UpdateThumbVFPPredicate(MI);
-    return true;
+    return result;
   }
 
   MI.clear();
   result = decodeNEONDupInstruction32(MI, insn32, Address, this);
-  if (result) {
+  if (result != Fail) {
     Size = 4;
     AddThumbPredicate(MI);
-    return true;
+    return result;
   }
 
   if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
@@ -515,10 +526,10 @@
     NEONLdStInsn &= 0xF0FFFFFF;
     NEONLdStInsn |= 0x04000000;
     result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
-    if (result) {
+    if (result != Fail) {
       Size = 4;
       AddThumbPredicate(MI);
-      return true;
+      return result;
     }
   }
 
@@ -529,14 +540,14 @@
     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
     result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
-    if (result) {
+    if (result != Fail) {
       Size = 4;
       AddThumbPredicate(MI);
-      return true;
+      return result;
     }
   }
 
-  return false;
+  return Fail;
 }
 
 
@@ -554,30 +565,30 @@
   ARM::R12, ARM::SP, ARM::LR, ARM::PC
 };
 
-static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 15)
-    return false;
+    return Fail;
 
   unsigned Register = GPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::CreateReg(Register));
-  return true;
+  return Success;
 }
 
-static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                        uint64_t Address, const void *Decoder) {
-  if (RegNo == 15) return false;
+  if (RegNo == 15) return Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 7)
-    return false;
+    return Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   unsigned Register = 0;
   switch (RegNo) {
@@ -600,16 +611,16 @@
       Register = ARM::R12;
       break;
     default:
-      return false;
+      return Fail;
     }
 
   Inst.addOperand(MCOperand::CreateReg(Register));
-  return true;
+  return Success;
 }
 
-static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
-  if (RegNo == 13 || RegNo == 15) return false;
+  if (RegNo == 13 || RegNo == 15) return Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
@@ -624,14 +635,14 @@
     ARM::S28, ARM::S29, ARM::S30, ARM::S31
 };
 
-static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 31)
-    return false;
+    return Fail;
 
   unsigned Register = SPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::CreateReg(Register));
-  return true;
+  return Success;
 }
 
 static const unsigned DPRDecoderTable[] = { 
@@ -645,27 +656,27 @@
     ARM::D28, ARM::D29, ARM::D30, ARM::D31
 };
 
-static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 31)
-    return false;
+    return Fail;
 
   unsigned Register = DPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::CreateReg(Register));
-  return true;
+  return Success;
 }
 
-static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 7)
-    return false;
+    return Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 15)
-    return false;
+    return Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
@@ -677,65 +688,66 @@
 };
 
 
-static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 31)
-    return false;
+    return Fail;
   RegNo >>= 1;
 
   unsigned Register = QPRDecoderTable[RegNo];
   Inst.addOperand(MCOperand::CreateReg(Register));
-  return true;
+  return Success;
 }
 
-static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
-  if (Val == 0xF) return false;
+  if (Val == 0xF) return Fail;
   // AL predicate is not allowed on Thumb1 branches.
   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
-    return false;
+    return Fail;
   Inst.addOperand(MCOperand::CreateImm(Val));
   if (Val == ARMCC::AL) {
     Inst.addOperand(MCOperand::CreateReg(0));
   } else
     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
-  return true;
+  return Success;
 }
 
-static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   if (Val)
     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
   else
     Inst.addOperand(MCOperand::CreateReg(0));
-  return true;
+  return Success;
 }
 
-static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   uint32_t imm = Val & 0xFF;
   uint32_t rot = (Val & 0xF00) >> 7;
   uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
   Inst.addOperand(MCOperand::CreateImm(rot_imm));
-  return true;
+  return Success;
 }
 
-static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   Val <<= 2;
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
-  return true;
+  return Success;
 }
 
-static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
 
   unsigned Rm = fieldFromInstruction32(Val, 0, 4);
   unsigned type = fieldFromInstruction32(Val, 5, 2);
   unsigned imm = fieldFromInstruction32(Val, 7, 5);
 
   // Register-immediate
-  if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
 
   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
   switch (type) {
@@ -759,19 +771,20 @@
   unsigned Op = Shift | (imm << 3);
   Inst.addOperand(MCOperand::CreateImm(Op));
 
-  return true;
+  return S;
 }
 
-static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
 
   unsigned Rm = fieldFromInstruction32(Val, 0, 4);
   unsigned type = fieldFromInstruction32(Val, 5, 2);
   unsigned Rs = fieldFromInstruction32(Val, 8, 4);
 
   // Register-register
-  if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
-  if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
 
   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
   switch (type) {
@@ -791,49 +804,55 @@
 
   Inst.addOperand(MCOperand::CreateImm(Shift));
 
-  return true;
+  return S;
 }
 
-static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   // Empty register lists are not allowed.
-  if (CountPopulation_32(Val) == 0) return false;
+  if (CountPopulation_32(Val) == 0) return Fail;
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
-      if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
     }
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Vd = fieldFromInstruction32(Val, 8, 4);
   unsigned regs = Val & 0xFF;
 
-  if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
+  CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
   for (unsigned i = 0; i < (regs - 1); ++i) {
-    if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
+    CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Vd = fieldFromInstruction32(Val, 8, 4);
   unsigned regs = (Val & 0xFF) / 2;
 
-  if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
   for (unsigned i = 0; i < (regs - 1); ++i) {
-    if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
+    CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
                                       uint64_t Address, const void *Decoder) {
   // This operand encodes a mask of contiguous zeros between a specified MSB
   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
@@ -845,11 +864,13 @@
   uint32_t msb_mask = (1 << (msb+1)) - 1;
   uint32_t lsb_mask = (1 << lsb) - 1;
   Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
-  return true;
+  return Success;
 }
 
-static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
   unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
   unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
@@ -875,7 +896,7 @@
     case ARM::STCL_POST:
     case ARM::STCL_OPTION:
       if (coproc == 0xA || coproc == 0xB)
-        return false;
+        return Fail;
       break;
     default:
       break;
@@ -883,7 +904,7 @@
 
   Inst.addOperand(MCOperand::CreateImm(coproc));
   Inst.addOperand(MCOperand::CreateImm(CRd));
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   switch (Inst.getOpcode()) {
     case ARM::LDC_OPTION:
     case ARM::LDCL_OPTION:
@@ -952,17 +973,19 @@
     case ARM::STCL_PRE:
     case ARM::STCL_POST:
     case ARM::STCL_OPTION:
-      if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+      CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
       break;
     default:
       break;
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
@@ -982,13 +1005,13 @@
     case ARM::STRT_POST_IMM:
     case ARM::STRBT_POST_REG:
     case ARM::STRBT_POST_IMM:
-      if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
       break;
     default:
       break;
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
 
   // On loads, the writeback operand comes after Rt.
   switch (Inst.getOpcode()) {
@@ -1002,14 +1025,13 @@
     case ARM::LDRBT_POST_IMM:
     case ARM::LDRT_POST_REG:
     case ARM::LDRT_POST_IMM:
-      if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-        return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
       break;
     default:
       break;
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
 
   ARM_AM::AddrOpc Op = ARM_AM::add;
   if (!fieldFromInstruction32(Insn, 23, 1))
@@ -1022,10 +1044,10 @@
   else if (!P && writeback)
     idx_mode = ARMII::IndexModePost;
 
-  if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE
+  if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
 
   if (reg) {
-    if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
     switch( fieldFromInstruction32(Insn, 5, 2)) {
       case 0:
@@ -1041,7 +1063,7 @@
         Opc = ARM_AM::ror;
         break;
       default:
-        return false;
+        return Fail;
     }
     unsigned amt = fieldFromInstruction32(Insn, 7, 5);
     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
@@ -1053,13 +1075,15 @@
     Inst.addOperand(MCOperand::CreateImm(tmp));
   }
 
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 13, 4);
   unsigned Rm = fieldFromInstruction32(Val,  0, 4);
   unsigned type = fieldFromInstruction32(Val, 5, 2);
@@ -1082,8 +1106,8 @@
       break;
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   unsigned shift;
   if (U)
     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
@@ -1091,11 +1115,13 @@
     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
   Inst.addOperand(MCOperand::CreateImm(shift));
 
-  return true;
+  return S;
 }
 
-static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
@@ -1116,7 +1142,7 @@
     case ARM::LDRD:
     case ARM::LDRD_PRE:
     case ARM::LDRD_POST:
-      if (Rt & 0x1) return false;
+      if (Rt & 0x1) return Fail;
       break;
   default:
     break;
@@ -1136,16 +1162,14 @@
     case ARM::STRH:
     case ARM::STRH_PRE:
     case ARM::STRH_POST:
-      if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-        return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
       break;
     default:
       break;
     }
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
   switch (Inst.getOpcode()) {
     case ARM::STRD:
     case ARM::STRD_PRE:
@@ -1153,8 +1177,7 @@
     case ARM::LDRD:
     case ARM::LDRD_PRE:
     case ARM::LDRD_POST:
-      if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))
-        return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
       break;
     default:
       break;
@@ -1177,33 +1200,32 @@
     case ARM::LDRSB_POST:
     case ARM::LDRHTr:
     case ARM::LDRSBTr:
-      if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-        return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
       break;
     default:
       break;
     }
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
 
   if (type) {
     Inst.addOperand(MCOperand::CreateReg(0));
     Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
   } else {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
     Inst.addOperand(MCOperand::CreateImm(U));
   }
 
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned mode = fieldFromInstruction32(Insn, 23, 2);
 
@@ -1223,14 +1245,16 @@
   }
 
   Inst.addOperand(MCOperand::CreateImm(mode));
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
+static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
                                   unsigned Insn,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
   unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
@@ -1265,16 +1289,15 @@
     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)   ||
-      !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)   || // Tied
-      !DecodePredicateOperand(Inst, pred, Address, Decoder) ||
-      !DecodeRegListOperand(Inst, reglist, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+  CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
   unsigned imod = fieldFromInstruction32(Insn, 18, 2);
   unsigned M = fieldFromInstruction32(Insn, 17, 1);
@@ -1282,30 +1305,32 @@
   unsigned mode = fieldFromInstruction32(Insn, 0, 5);
 
   // imod == '01' --> UNPREDICTABLE
-  if (imod == 1) return false;
+  if (imod == 1) return Fail;
 
   if (M && mode && imod && iflags) {
     Inst.setOpcode(ARM::CPS3p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return true;
+    return Success;
   } else if (!mode && !M) {
     Inst.setOpcode(ARM::CPS2p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
-    return true;
+    return Success;
   } else if (!imod && !iflags && M) {
     Inst.setOpcode(ARM::CPS1p);
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return true;
+    return Success;
   }
 
-  return false;
+  return Fail;
 }
 
-static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
@@ -1315,57 +1340,60 @@
   if (pred == 0xF)
     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
-  if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) ||
-      !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) ||
-      !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) ||
-      !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
+  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
 
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
                            uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned add = fieldFromInstruction32(Val, 12, 1);
   unsigned imm = fieldFromInstruction32(Val, 0, 12);
   unsigned Rn = fieldFromInstruction32(Val, 13, 4);
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
 
   if (!add) imm *= -1;
   if (imm == 0 && !add) imm = INT32_MIN;
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return S;
 }
 
-static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 9, 4);
   unsigned U = fieldFromInstruction32(Val, 8, 1);
   unsigned imm = fieldFromInstruction32(Val, 0, 8);
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
 
   if (U)
     Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
   else
     Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
 
-  return true;
+  return S;
 }
 
-static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
 }
 
-static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
   unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
 
@@ -1373,39 +1401,42 @@
     Inst.setOpcode(ARM::BLXi);
     imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
     Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
-    return true;
+    return S;
   }
 
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(64 - Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rm = fieldFromInstruction32(Val, 0, 4);
   unsigned align = fieldFromInstruction32(Val, 4, 2);
 
-  if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   if (!align)
     Inst.addOperand(MCOperand::CreateImm(0));
   else
     Inst.addOperand(MCOperand::CreateImm(4 << align));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned wb = fieldFromInstruction32(Insn, 16, 4);
@@ -1414,7 +1445,7 @@
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
 
   // First output register
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
 
   // Second output register
   switch (Inst.getOpcode()) {
@@ -1466,7 +1497,7 @@
     case ARM::VLD4d8_UPD:
     case ARM::VLD4d16_UPD:
     case ARM::VLD4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
       break;
     case ARM::VLD2b8:
     case ARM::VLD2b16:
@@ -1486,7 +1517,7 @@
     case ARM::VLD4q8_UPD:
     case ARM::VLD4q16_UPD:
     case ARM::VLD4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
     default:
       break;
   }
@@ -1527,7 +1558,7 @@
     case ARM::VLD4d8_UPD:
     case ARM::VLD4d16_UPD:
     case ARM::VLD4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
       break;
     case ARM::VLD3q8:
     case ARM::VLD3q16:
@@ -1541,7 +1572,7 @@
     case ARM::VLD4q8_UPD:
     case ARM::VLD4q16_UPD:
     case ARM::VLD4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
       break;
     default:
       break;
@@ -1569,7 +1600,7 @@
     case ARM::VLD4d8_UPD:
     case ARM::VLD4d16_UPD:
     case ARM::VLD4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
       break;
     case ARM::VLD4q8:
     case ARM::VLD4q16:
@@ -1577,7 +1608,7 @@
     case ARM::VLD4q8_UPD:
     case ARM::VLD4q16_UPD:
     case ARM::VLD4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
       break;
     default:
       break;
@@ -1622,28 +1653,29 @@
     case ARM::VLD4q8_UPD:
     case ARM::VLD4q16_UPD:
     case ARM::VLD4q32_UPD:
-      if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
       break;
     default:
       break;
   }
 
   // AddrMode6 Base (register+alignment)
-  if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
 
   // AddrMode6 Offset (register)
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned wb = fieldFromInstruction32(Insn, 16, 4);
@@ -1690,25 +1722,24 @@
     case ARM::VST4q8_UPD:
     case ARM::VST4q16_UPD:
     case ARM::VST4q32_UPD:
-      if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder))
-        return false;
+      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
       break;
     default:
       break;
   }
 
   // AddrMode6 Base (register+alignment)
-  if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
 
   // AddrMode6 Offset (register)
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
   // First input register
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
 
   // Second input register
   switch (Inst.getOpcode()) {
@@ -1760,7 +1791,7 @@
     case ARM::VST4d8_UPD:
     case ARM::VST4d16_UPD:
     case ARM::VST4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
       break;
     case ARM::VST2b8:
     case ARM::VST2b16:
@@ -1780,7 +1811,7 @@
     case ARM::VST4q8_UPD:
     case ARM::VST4q16_UPD:
     case ARM::VST4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
       break;
     default:
       break;
@@ -1822,7 +1853,7 @@
     case ARM::VST4d8_UPD:
     case ARM::VST4d16_UPD:
     case ARM::VST4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
       break;
     case ARM::VST3q8:
     case ARM::VST3q16:
@@ -1836,7 +1867,7 @@
     case ARM::VST4q8_UPD:
     case ARM::VST4q16_UPD:
     case ARM::VST4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
       break;
     default:
       break;
@@ -1864,7 +1895,7 @@
     case ARM::VST4d8_UPD:
     case ARM::VST4d16_UPD:
     case ARM::VST4d32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
       break;
     case ARM::VST4q8:
     case ARM::VST4q16:
@@ -1872,17 +1903,19 @@
     case ARM::VST4q8_UPD:
     case ARM::VST4q16_UPD:
     case ARM::VST4q32_UPD:
-      if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
       break;
     default:
       break;
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -1893,28 +1926,30 @@
 
   align *= (1 << size);
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   if (regs == 2) {
-    if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
+    CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
   }
   if (Rm == 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
 
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -1924,54 +1959,57 @@
   unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
   align *= 2*size;
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
   if (Rm == 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
 
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)          ||
-      !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) ||
-      !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))
-    return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
   if (Rm == 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(0));
 
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -1993,29 +2031,30 @@
     }
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)            ||
-      !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)   ||
-      !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) ||
-      !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))
-    return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
   if (Rm == 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
 
   if (Rm == 0xD)
     Inst.addOperand(MCOperand::CreateReg(0));
   else if (Rm != 0xF) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned imm = fieldFromInstruction32(Insn, 0, 4);
@@ -2026,9 +2065,9 @@
   unsigned Q = fieldFromInstruction32(Insn, 6, 1);
 
   if (Q) {
-    if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+    CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
   } else {
-    if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   }
 
   Inst.addOperand(MCOperand::CreateImm(imm));
@@ -2038,62 +2077,66 @@
     case ARM::VORRiv2i32:
     case ARM::VBICiv4i16:
     case ARM::VBICiv2i32:
-      if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+      CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
       break;
     case ARM::VORRiv8i16:
     case ARM::VORRiv4i32:
     case ARM::VBICiv8i16:
     case ARM::VBICiv4i32:
-      if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+      CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
       break;
     default:
       break;
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
   unsigned size = fieldFromInstruction32(Insn, 18, 2);
 
-  if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(8 << size));
 
-  return true;
+  return S;
 }
 
-static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(8 - Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(16 - Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(32 - Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(64 - Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -2103,21 +2146,21 @@
   unsigned op = fieldFromInstruction32(Insn, 6, 1);
   unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   if (op) {
-    if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback
+    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
   }
 
   for (unsigned i = 0; i < length; ++i) {
-    if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false;
+    CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
                             uint64_t Address, const void *Decoder) {
   // The immediate needs to be a fully instantiated float.  However, the
   // auto-generated decoder is only able to fill in some of the bits
@@ -2139,102 +2182,110 @@
   fp_conv.integer |= (~b & 0x1) << 30;
 
   Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                                      uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned dst = fieldFromInstruction16(Insn, 8, 3);
   unsigned imm = fieldFromInstruction16(Insn, 0, 8);
 
-  if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false;
+  CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
 
   if (Inst.getOpcode() == ARM::tADR)
     Inst.addOperand(MCOperand::CreateReg(ARM::PC));
   else if (Inst.getOpcode() == ARM::tADDrSPi)
     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
   else
-    return false;
+    return Fail;
 
   Inst.addOperand(MCOperand::CreateImm(imm));
-  return true;
+  return S;
 }
 
-static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
-  return true;
+  return Success;
 }
 
-static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 0, 3);
   unsigned Rm = fieldFromInstruction32(Val, 3, 3);
 
-  if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) ||
-      !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))
-    return false;
+  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 0, 3);
   unsigned imm = fieldFromInstruction32(Val, 3, 5);
 
-  if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return S;
 }
 
-static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(Val << 2));
 
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
   Inst.addOperand(MCOperand::CreateImm(Val << 2));
 
-  return true;
+  return Success;
 }
 
-static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 6, 4);
   unsigned Rm = fieldFromInstruction32(Val, 2, 4);
   unsigned imm = fieldFromInstruction32(Val, 0, 2);
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
-      !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return S;
 }
 
-static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   if (Inst.getOpcode() != ARM::t2PLDs) {
     unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
-    if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
   }
 
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -2257,57 +2308,60 @@
         Inst.addOperand(MCOperand::CreateReg(ARM::PC));
         break;
       default:
-        return false;
+        return Fail;
     }
 
     int imm = fieldFromInstruction32(Insn, 0, 12);
     if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
     Inst.addOperand(MCOperand::CreateImm(imm));
 
-    return true;
+    return S;
   }
 
   unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
   addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
   addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
-  DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder);
+  CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
                            uint64_t Address, const void *Decoder) {
   int imm = Val & 0xFF;
   if (!(Val & 0x100)) imm *= -1;
   Inst.addOperand(MCOperand::CreateImm(imm << 2));
 
-  return true;
+  return Success;
 }
 
-static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 9, 4);
   unsigned imm = fieldFromInstruction32(Val, 0, 9);
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
-      !DecodeT2Imm8S4(Inst, imm, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
                          uint64_t Address, const void *Decoder) {
   int imm = Val & 0xFF;
   if (!(Val & 0x100)) imm *= -1;
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return Success;
 }
 
 
-static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 9, 4);
   unsigned imm = fieldFromInstruction32(Val, 0, 9);
 
@@ -2324,27 +2378,28 @@
       break;
   }
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
-      !DecodeT2Imm8(Inst, imm, Address, Decoder))
-    return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Val, 13, 4);
   unsigned imm = fieldFromInstruction32(Val, 0, 12);
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
                                 uint64_t Address, const void *Decoder) {
   unsigned imm = fieldFromInstruction16(Insn, 0, 7);
 
@@ -2352,30 +2407,32 @@
   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
   Inst.addOperand(MCOperand::CreateImm(imm));
 
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
                                 uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   if (Inst.getOpcode() == ARM::tADDrSP) {
     unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
     Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
 
-    if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
-    if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
   } else if (Inst.getOpcode() == ARM::tADDspr) {
     unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
 
     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
     Inst.addOperand(MCOperand::CreateReg(ARM::SP));
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  return true;
+  return S;
 }
 
-static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
+static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
                            uint64_t Address, const void *Decoder) {
   unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
   unsigned flags = fieldFromInstruction16(Insn, 0, 3);
@@ -2383,52 +2440,55 @@
   Inst.addOperand(MCOperand::CreateImm(imod));
   Inst.addOperand(MCOperand::CreateImm(flags));
 
-  return true;
+  return Success;
 }
 
-static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
                              uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned add = fieldFromInstruction32(Insn, 4, 1);
 
-  if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
   Inst.addOperand(MCOperand::CreateImm(add));
 
-  return true;
+  return S;
 }
 
-static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
-  return true;
+  return Success;
 }
 
-static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder) {
   if (Val == 0xA || Val == 0xB)
-    return false;
+    return Fail;
 
   Inst.addOperand(MCOperand::CreateImm(Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
                              uint64_t Address, const void *Decoder) {
   if (Val == 0)
     Inst.addOperand(MCOperand::CreateImm(32));
   else
     Inst.addOperand(MCOperand::CreateImm(Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
                                        uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned pred = fieldFromInstruction32(Insn, 22, 4);
   if (pred == 0xE || pred == 0xF) {
     unsigned opc = fieldFromInstruction32(Insn, 4, 2);
     switch (opc) {
       default:
-        return false;
+        return Fail;
       case 0:
         Inst.setOpcode(ARM::t2DSB);
         break;
@@ -2437,7 +2497,7 @@
         break;
       case 2:
         Inst.setOpcode(ARM::t2ISB);
-        return true;
+        return Success;
     }
 
     unsigned imm = fieldFromInstruction32(Insn, 0, 4);
@@ -2450,17 +2510,16 @@
   brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
   brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
 
-  if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) ||
-      !DecodePredicateOperand(Inst, pred, Address, Decoder))
-    return false;
+  CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
 // Decode a shifted immediate operand.  These basically consist
 // of an 8-bit value, and a 4-bit directive that specifies either
 // a splat operation or a rotation.
-static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
                           uint64_t Address, const void *Decoder) {
   unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
   if (ctrl == 0) {
@@ -2488,26 +2547,26 @@
     Inst.addOperand(MCOperand::CreateImm(imm));
   }
 
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                         uint64_t Address, const void *Decoder){
   Inst.addOperand(MCOperand::CreateImm(Val << 1));
-  return true;
+  return Success;
 }
 
-static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                        uint64_t Address, const void *Decoder){
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
-  return true;
+  return Success;
 }
 
-static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   switch (Val) {
   default:
-    return false;
+    return Fail;
   case 0xF: // SY
   case 0xE: // ST
   case 0xB: // ISH
@@ -2520,55 +2579,61 @@
   }
 
   Inst.addOperand(MCOperand::CreateImm(Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
                           uint64_t Address, const void *Decoder) {
-  if (!Val) return false;
+  if (!Val) return Fail;
   Inst.addOperand(MCOperand::CreateImm(Val));
-  return true;
+  return Success;
 }
 
-static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
                                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
 
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
                                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
 
-  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
-  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
+  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
+  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
 
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
                             uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
   unsigned imm = fieldFromInstruction32(Insn, 0, 12);
@@ -2576,18 +2641,20 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
-  if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false;
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
                             uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
   unsigned imm = fieldFromInstruction32(Insn, 0, 12);
@@ -2595,18 +2662,20 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
 
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
-  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
-  if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false;
-  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
+  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2617,47 +2686,47 @@
   unsigned index = 0;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 5, 3);
       break;
     case 1:
       if (fieldFromInstruction32(Insn, 5, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 6, 2);
       if (fieldFromInstruction32(Insn, 4, 1))
         align = 2;
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 6, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 4, 2) != 0)
         align = 4;
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2668,47 +2737,47 @@
   unsigned index = 0;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 5, 3);
       break;
     case 1:
       if (fieldFromInstruction32(Insn, 5, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 6, 2);
       if (fieldFromInstruction32(Insn, 4, 1))
         align = 2;
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 6, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 4, 2) != 0)
         align = 4;
   }
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2720,7 +2789,7 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       index = fieldFromInstruction32(Insn, 5, 3);
       if (fieldFromInstruction32(Insn, 4, 1))
@@ -2735,7 +2804,7 @@
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 5, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 4, 1) != 0)
         align = 8;
@@ -2744,28 +2813,28 @@
       break;
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2777,7 +2846,7 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       index = fieldFromInstruction32(Insn, 5, 3);
       if (fieldFromInstruction32(Insn, 4, 1))
@@ -2792,7 +2861,7 @@
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 5, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 4, 1) != 0)
         align = 8;
@@ -2802,26 +2871,26 @@
   }
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2833,53 +2902,53 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 5, 3);
       break;
     case 1:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 6, 2);
       if (fieldFromInstruction32(Insn, 5, 1))
         inc = 2;
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 4, 2))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 6, 1))
         inc = 2;
       break;
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2891,22 +2960,22 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 5, 3);
       break;
     case 1:
       if (fieldFromInstruction32(Insn, 4, 1))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 6, 2);
       if (fieldFromInstruction32(Insn, 5, 1))
         inc = 2;
       break;
     case 2:
       if (fieldFromInstruction32(Insn, 4, 2))
-        return false; // UNDEFINED
+        return Fail; // UNDEFINED
       index = fieldFromInstruction32(Insn, 7, 1);
       if (fieldFromInstruction32(Insn, 6, 1))
         inc = 2;
@@ -2914,27 +2983,27 @@
   }
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
 
-static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2946,7 +3015,7 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
         align = 4;
@@ -2968,33 +3037,33 @@
       break;
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 
-static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
                          uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -3006,7 +3075,7 @@
   unsigned inc = 1;
   switch (size) {
     default:
-      return false;
+      return Fail;
     case 0:
       if (fieldFromInstruction32(Insn, 4, 1))
         align = 4;
@@ -3029,22 +3098,20 @@
   }
 
   if (Rm != 0xF) { // Writeback
-    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
-  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
   if (Rm != 0xF && Rm != 0xD) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
-      return false;
+    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
   }
 
-  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
-  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(index));
 
-  return true;
+  return S;
 }
 

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h Wed Aug 17 12:44:15 2011
@@ -40,11 +40,11 @@
   }
 
   /// getInstruction - See MCDisassembler.
-  bool getInstruction(MCInst &instr,
-                      uint64_t &size,
-                      const MemoryObject &region,
-                      uint64_t address,
-                      raw_ostream &vStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream) const;
 
   /// getEDInfo - See MCDisassembler.
   EDInstInfo *getEDInfo() const;
@@ -64,11 +64,11 @@
   }
 
   /// getInstruction - See MCDisassembler.
-  bool getInstruction(MCInst &instr,
-                      uint64_t &size,
-                      const MemoryObject &region,
-                      uint64_t address,
-                      raw_ostream &vStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream) const;
 
   /// getEDInfo - See MCDisassembler.
   EDInstInfo *getEDInfo() const;

Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Aug 17 12:44:15 2011
@@ -493,7 +493,7 @@
 // Public interface for the disassembler
 //
 
-bool MBlazeDisassembler::getInstruction(MCInst &instr,
+MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
                                         uint64_t &size,
                                         const MemoryObject &region,
                                         uint64_t address,
@@ -508,7 +508,7 @@
 
   // We want to read exactly 4 bytes of data.
   if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read < 4)
-    return false;
+    return Fail;
 
   // Encoded as a big-endian 32-bit word in the stream.
   insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0);
@@ -517,7 +517,7 @@
   // that it is a valid instruction.
   unsigned opcode = getOPCODE(insn);
   if (opcode == UNSUPPORTED)
-    return false;
+    return Fail;
 
   instr.setOpcode(opcode);
 
@@ -529,11 +529,11 @@
   uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
   switch ((tsFlags & MBlazeII::FormMask)) {
   default: 
-    return false;
+    return Fail;
 
   case MBlazeII::FRRRR:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RB));
     instr.addOperand(MCOperand::CreateReg(RA));
@@ -541,7 +541,7 @@
 
   case MBlazeII::FRRR:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RA));
     instr.addOperand(MCOperand::CreateReg(RB));
@@ -550,23 +550,23 @@
   case MBlazeII::FRI:
     switch (opcode) {
     default: 
-      return false;
+      return Fail;
     case MBlaze::MFS:
       if (RD == UNSUPPORTED)
-        return false;
+        return Fail;
       instr.addOperand(MCOperand::CreateReg(RD));
       instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
       break;
     case MBlaze::MTS:
       if (RA == UNSUPPORTED)
-        return false;
+        return Fail;
       instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
       instr.addOperand(MCOperand::CreateReg(RA));
       break;
     case MBlaze::MSRSET:
     case MBlaze::MSRCLR:
       if (RD == UNSUPPORTED)
-        return false;
+        return Fail;
       instr.addOperand(MCOperand::CreateReg(RD));
       instr.addOperand(MCOperand::CreateImm(insn&0x7FFF));
       break;
@@ -575,7 +575,7 @@
 
   case MBlazeII::FRRI:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RA));
     switch (opcode) {
@@ -592,35 +592,35 @@
 
   case MBlazeII::FCRR:
     if (RA == UNSUPPORTED || RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RA));
     instr.addOperand(MCOperand::CreateReg(RB));
     break;
 
   case MBlazeII::FCRI:
     if (RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RA));
     instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
     break;
 
   case MBlazeII::FRCR:
     if (RD == UNSUPPORTED || RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RB));
     break;
 
   case MBlazeII::FRCI:
     if (RD == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
     break;
 
   case MBlazeII::FCCR:
     if (RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RB));
     break;
 
@@ -630,7 +630,7 @@
 
   case MBlazeII::FRRCI:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RA));
     instr.addOperand(MCOperand::CreateImm(getSHT(insn)));
@@ -638,35 +638,35 @@
 
   case MBlazeII::FRRC:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RA));
     break;
 
   case MBlazeII::FRCX:
     if (RD == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
     break;
 
   case MBlazeII::FRCS:
     if (RD == UNSUPPORTED || RS == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateReg(RS));
     break;
 
   case MBlazeII::FCRCS:
     if (RS == UNSUPPORTED || RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RS));
     instr.addOperand(MCOperand::CreateReg(RA));
     break;
 
   case MBlazeII::FCRCX:
     if (RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RA));
     instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
     break;
@@ -677,13 +677,13 @@
 
   case MBlazeII::FCR:
     if (RB == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RB));
     break;
 
   case MBlazeII::FRIR:
     if (RD == UNSUPPORTED || RA == UNSUPPORTED)
-      return false;
+      return Fail;
     instr.addOperand(MCOperand::CreateReg(RD));
     instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
     instr.addOperand(MCOperand::CreateReg(RA));
@@ -693,7 +693,7 @@
   // We always consume 4 bytes of data on success
   size = 4;
 
-  return true;
+  return Success;
 }
 
 static MCDisassembler *createMBlazeDisassembler(const Target &T) {

Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Aug 17 12:44:15 2011
@@ -40,7 +40,7 @@
   }
 
   /// getInstruction - See MCDisassembler.
-  bool getInstruction(MCInst &instr,
+  MCDisassembler::DecodeStatus getInstruction(MCInst &instr,
                       uint64_t &size,
                       const MemoryObject &region,
                       uint64_t address,

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug 17 12:44:15 2011
@@ -106,11 +106,12 @@
 // Public interface for the disassembler
 //
 
-bool X86GenericDisassembler::getInstruction(MCInst &instr,
-                                            uint64_t &size,
-                                            const MemoryObject &region,
-                                            uint64_t address,
-                                            raw_ostream &vStream) const {
+MCDisassembler::DecodeStatus
+X86GenericDisassembler::getInstruction(MCInst &instr,
+                                       uint64_t &size,
+                                       const MemoryObject &region,
+                                       uint64_t address,
+                                       raw_ostream &vStream) const {
   InternalInstruction internalInstr;
   
   int ret = decodeInstruction(&internalInstr,
@@ -123,11 +124,11 @@
 
   if (ret) {
     size = internalInstr.readerCursor - address;
-    return false;
+    return Fail;
   }
   else {
     size = internalInstr.length;
-    return !translateInstruction(instr, internalInstr);
+    return (!translateInstruction(instr, internalInstr)) ? Success : Fail;
   }
 }
 

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Aug 17 12:44:15 2011
@@ -112,11 +112,11 @@
   ~X86GenericDisassembler();
 
   /// getInstruction - See MCDisassembler.
-  bool getInstruction(MCInst &instr,
-                      uint64_t &size,
-                      const MemoryObject &region,
-                      uint64_t address,
-                      raw_ostream &vStream) const;
+  DecodeStatus getInstruction(MCInst &instr,
+                              uint64_t &size,
+                              const MemoryObject &region,
+                              uint64_t address,
+                              raw_ostream &vStream) const;
 
   /// getEDInfo - See MCDisassembler.
   EDInstInfo *getEDInfo() const;

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Wed Aug 17 12:44:15 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
 
 # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0

Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original)
+++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 17 12:44:15 2011
@@ -65,15 +65,26 @@
   for (Index = 0; Index < Bytes.size(); Index += Size) {
     MCInst Inst;
 
-    if (DisAsm.getInstruction(Inst, Size, memoryObject, Index,
-                               /*REMOVE*/ nulls())) {
-      Printer.printInst(&Inst, Out);
-      Out << "\n";
-    } else {
+    MCDisassembler::DecodeStatus S;
+    S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
+                              /*REMOVE*/ nulls());
+    switch (S) {
+    case MCDisassembler::Fail:
       SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
                       "invalid instruction encoding", "warning");
       if (Size == 0)
         Size = 1; // skip illegible bytes
+      break;
+
+    case MCDisassembler::SoftFail:
+      SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
+                      "potentially undefined instruction encoding", "warning");
+      // Fall through
+
+    case MCDisassembler::Success:
+      Printer.printInst(&Inst, Out);
+      Out << "\n";
+      break;
     }
   }
 

Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Aug 17 12:44:15 2011
@@ -128,5 +128,15 @@
     return;
   }
 
+  // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
+  if (Target.getName() == "ARM" ||
+      Target.getName() == "Thumb") {
+    FixedLenDecoderEmitter(Records,
+                           "CHECK(S, ", ");",
+                           "S", "Fail",
+                           "DecodeStatus S = Success;\n(void)S;").run(OS);
+    return;
+  }
+
   FixedLenDecoderEmitter(Records).run(OS);
 }

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Aug 17 12:44:15 2011
@@ -238,19 +238,24 @@
   // Width of instructions
   unsigned BitWidth;
 
+  // Parent emitter
+  const FixedLenDecoderEmitter *Emitter;
+
 public:
   FilterChooser(const FilterChooser &FC) :
     AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes),
       Operands(FC.Operands), Filters(FC.Filters),
       FilterBitValues(FC.FilterBitValues), Parent(FC.Parent),
-      BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { }
+    BestIndex(FC.BestIndex), BitWidth(FC.BitWidth),
+    Emitter(FC.Emitter) { }
 
   FilterChooser(const std::vector<const CodeGenInstruction*> &Insts,
                 const std::vector<unsigned> &IDs,
     std::map<unsigned, std::vector<OperandInfo> > &Ops,
-                unsigned BW) :
+                unsigned BW,
+                const FixedLenDecoderEmitter *E) :
       AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
-      Parent(NULL), BestIndex(-1), BitWidth(BW) {
+      Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) {
     for (unsigned i = 0; i < BitWidth; ++i)
       FilterBitValues.push_back(BIT_UNFILTERED);
 
@@ -264,7 +269,8 @@
                 FilterChooser &parent) :
       AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
       Filters(), FilterBitValues(ParentFilterBitValues),
-      Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) {
+      Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth),
+      Emitter(parent.Emitter) {
     doFilter();
   }
 
@@ -563,17 +569,17 @@
 void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation,
                             std::string Namespace) {
   o.indent(Indentation) <<
-    "static bool decode" << Namespace << "Instruction" << BitWidth
+    "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction" << BitWidth
     << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, "
     << "const void *Decoder) {\n";
-  o.indent(Indentation) << "  unsigned tmp = 0;\n  (void)tmp;\n";
+  o.indent(Indentation) << "  unsigned tmp = 0;\n  (void)tmp;\n" << Emitter->Locals << "\n";
 
   ++Indentation; ++Indentation;
   // Emits code to decode the instructions.
   emit(o, Indentation);
 
   o << '\n';
-  o.indent(Indentation) << "return false;\n";
+  o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n";
   --Indentation; --Indentation;
 
   o.indent(Indentation) << "}\n";
@@ -744,8 +750,8 @@
   }
 
   if (Decoder != "")
-    o.indent(Indentation) << "  if (!" << Decoder
-                          << "(MI, tmp, Address, Decoder)) return false;\n";
+    o.indent(Indentation) << "  " << Emitter->GuardPrefix << Decoder
+                          << "(MI, tmp, Address, Decoder)" << Emitter->GuardPostfix << "\n";
   else
     o.indent(Indentation) << "  MI.addOperand(MCOperand::CreateImm(tmp));\n";
 
@@ -776,15 +782,15 @@
          I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
       // If a custom instruction decoder was specified, use that.
       if (I->numFields() == 0 && I->Decoder.size()) {
-        o.indent(Indentation) << "  if (!" << I->Decoder
-                              << "(MI, insn, Address, Decoder)) return false;\n";
+        o.indent(Indentation) << "  " << Emitter->GuardPrefix << I->Decoder
+                              << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n";
         break;
       }
 
       emitBinaryParser(o, Indentation, *I);
     }
 
-    o.indent(Indentation) << "  return true; // " << nameWithID(Opc)
+    o.indent(Indentation) << "  return " << Emitter->ReturnOK << "; // " << nameWithID(Opc)
                           << '\n';
     o.indent(Indentation) << "}\n";
     return true;
@@ -821,14 +827,14 @@
        I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
     // If a custom instruction decoder was specified, use that.
     if (I->numFields() == 0 && I->Decoder.size()) {
-      o.indent(Indentation) << "  if (!" << I->Decoder
-                            << "(MI, insn, Address, Decoder)) return false;\n";
+      o.indent(Indentation) << "  " << Emitter->GuardPrefix << I->Decoder
+                            << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n";
       break;
     }
 
     emitBinaryParser(o, Indentation, *I);
   }
-  o.indent(Indentation) << "  return true; // " << nameWithID(Opc)
+  o.indent(Indentation) << "  return " << Emitter->ReturnOK << "; // " << nameWithID(Opc)
                         << '\n';
   o.indent(Indentation) << "}\n";
 
@@ -1426,7 +1432,7 @@
 
     // Emit the decoder for this namespace+width combination.
     FilterChooser FC(NumberedInstructions, I->second, Operands,
-                     8*I->first.second);
+                     8*I->first.second, this);
     FC.emitTop(o, 0, I->first.first);
   }
 

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=137830&r1=137829&r2=137830&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Aug 17 12:44:15 2011
@@ -49,9 +49,16 @@
 
 class FixedLenDecoderEmitter : public TableGenBackend {
 public:
-  FixedLenDecoderEmitter(RecordKeeper &R) :
+  FixedLenDecoderEmitter(RecordKeeper &R,
+                         std::string GPrefix  = "if (",
+                         std::string GPostfix = " == MCDisassembler::Fail) return MCDisassembler::Fail;",
+                         std::string ROK      = "MCDisassembler::Success",
+                         std::string RFail    = "MCDisassembler::Fail",
+                         std::string L        = "") :
     Records(R), Target(R),
-    NumberedInstructions(Target.getInstructionsByEnumValue()) {}
+    NumberedInstructions(Target.getInstructionsByEnumValue()),
+    GuardPrefix(GPrefix), GuardPostfix(GPostfix),
+    ReturnOK(ROK), ReturnFail(RFail), Locals(L) {}
 
   // run - Output the code emitter
   void run(raw_ostream &o);
@@ -62,7 +69,10 @@
   std::vector<const CodeGenInstruction*> NumberedInstructions;
   std::vector<unsigned> Opcodes;
   std::map<unsigned, std::vector<OperandInfo> > Operands;
-
+public:
+  std::string GuardPrefix, GuardPostfix;
+  std::string ReturnOK, ReturnFail;
+  std::string Locals;
 };
 
 } // end llvm namespace



From resistor at mac.com  Wed Aug 17 12:45:39 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 17 Aug 2011 10:45:39 -0700
Subject: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
 UNPREDICTABLE insns as soft errors
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA4737580E87D@GEORGE.Emea.Arm.com>
References: <003601cc5bf5$712dbdc0$53893940$%molloy@arm.com>
	<8A075D8D-31BF-4073-9C31-BC843CD1A727@mac.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133D6@GEORGE.Emea.Arm.com>
	<F01D8B85CFF58440B2A13965FBA90CA4737580E87D@GEORGE.Emea.Arm.com>
Message-ID: <2D85E78D-F2EF-4801-9C94-8B6F3891A21D@mac.com>

Thanks James!

Applied in r137830.

--Owen

On Aug 17, 2011, at 4:54 AM, James Molloy wrote:

> Hi,
> 
> New patch attached. Changelog from previous:
> 
>  * DecodeStatus promoted to MCDisassembler.h. "Unpredictable" renamed to "SoftFail" to be more target-agnostic.
>  * FixedLenDecoderEmitter now is not parameterised by return type, although the guards and OK/Fail parameters remain.
>  * llvm-mc adapted to now print a warning above the disassembly on soft fail. Example:
> 
> $ /work/llvm-cmake2/build/bin/./llvm-mc --disassemble /work/llvm-cmake2/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt -triple=arm-apple-darwin9    [12:06]
> /work/llvm-cmake2/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt:10:1: warning: potentially undefined instruction encoding
> 0x05 0x70 0xd7 0xe6
> ^
>        ldrb    r7, [r7], r5
> 
>  * invalid-LDRB_POST-arm.txt -> unpredictable-LDRB_POST-arm.txt and updated to look for the soft fail warning.
> 
> Hopefully this should be ready for committing. Should apply cleanly on ToT at now: r137824.
> 
> Cheers,
> 
> James
> 
>> -----Original Message-----
>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
>> bounces at cs.uiuc.edu] On Behalf Of James Molloy
>> Sent: 16 August 2011 19:56
>> To: Owen Anderson
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
>> UNPREDICTABLE insns as soft errors
>> 
>> Hi Owen,
>> 
>> Thanks. That does seem the most logical thing to do - I suppose I'm
>> just used to open source projects where changing an abstraction can
>> lead to violent uproar on mailing lists :)
>> 
>> I'll wait for anyone to pipe up about the MCDisassembler change then
>> adapt my patch.
>> 
>> Thanks,
>> 
>> James
>> ________________________________________
>> From: Owen Anderson [resistor at mac.com]
>> Sent: 16 August 2011 19:44
>> To: James Molloy
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Enhance ARMDisassembler to report
>> UNPREDICTABLE insns as soft errors
>> 
>> Hi James,
>> 
>> My 2? are that I think it makes sense to expose DecodeStatus as part of
>> MCDisassembler.  I don't know that any other targets use it offhand,
>> but a "plausible but illegal" soft failure is at least a conceptually
>> target-independent result.  Then we could just change the return type
>> of getInstruction() to return a DecodeStatus.  At worst, ARM can be the
>> only target that returns an Unpredictable result in practice.
>> 
>> I suspect going this way will simplify the implementation (you'll get
>> rid of at least one of the FixedLenDecoderEmitter parameters) without
>> complicating other targets.   Does anyone else with an interest in the
>> MCDisassembler care?
>> 
>> Other than that decision, which we should resolve one way or another
>> before applying it, you patch looks great.
>> 
>> --Owen
>> 
>> On Aug 16, 2011, at 2:18 AM, James Molloy wrote:
>> 
>> Hi,
>> 
>> As discussed on llvm-dev recently, this patch adds support for "soft-
>> failing" on disassembly of certain ARM instructions.
>> 
>> Certain instructions are marked as "UNPREDICTABLE" in the ARMARM - the
>> disassembly of these instructions may still have value however,
>> especially to a debugger or debugging code generated by another
>> toolchain.
>> 
>> This patch promotes the return value of all Decode* operations in the
>> ARM disassembly to a ternary value (Success, Unpredictable, Fail) and
>> touches a lot of the error handling code to perform status demotion
>> from Success to Unpredictable, and returning early on Fail. It also
>> touches the FixedLenDecoderEmitter to facilitate the same changes in
>> autogenerated code.
>> 
>> The major changelist is:
>> *         Add a new type "DecodeStatus", local to ARMDisassembler.cpp,
>> and add a macro CHECK(S, X) that will possibly demote a DecodeStatus S
>> based on a function X's return value, and exit early if the value
>> becomes "Fail".
>> *         Modify the return value of Decode* from bool to
>> "DecodeStatus", modify "if(!X()) return false;" to "CHECK(S, X());",
>> assuming a local accumulator "DecodeStatus S = Success;".
>> *         Parameterise FixedLenDecoderEmitter to take as extra
>> (optional) arguments:
>> o   The return value of the functions to emit (default "bool")
>> o    "Guard" prefix and postfix to wrap any function call that may fail
>> (default "if (!" and ") return false;" respectively)
>> o   Value to return if everything went OK (default "true")
>> o   Value to return on failure (default "false")
>> o   Any extra local variables to add (default "")
>> *         These defaults maintain the current behaviour of
>> FixedLenDecoderEmitter. ARM/Thumb has been special cased in
>> DisassemblerEmitter.cpp.
>> 
>> The patch as is does not change the user-seen behaviour of the
>> disassembler at all. I'm still not sure the best way to expose this
>> information to the user.
>> 
>> AFAIK, Intel or most other architectures don't have the same concept as
>> ARM of a valid but unpredictable instruction. I'm therefore fearful of
>> changing MCDisassembler.h to cope with it. At the moment I have an
>> alternate getInstruction() function that also takes a bool& to which it
>> writes if the insn was predictable or not.
>> 
>> The problem with this obviously is that it requires the user to
>> #include <ARMDisassembler.h>, which is impossible in the general case
>> as it is a hidden header.
>> 
>> I can see three options, none of which being particularly elegant:
>> 
>> *         Make ARMDisassembler.h a public header so the user can
>> cast<ARMDisassembler> and access an alternate getInstruction()
>> function.
>> *         Add a bool* parameter to getInstruction() for UNPREDICTABLE;
>> default is NULL and the other backends ignore it.
>> *         Add an "wasInsnUnpredictable()" function to MCDisassembler,
>> which returns false for all other backends and only the ARM backend
>> deals with. Nastily non-reentrant.
>> *         ??? An alternative.
>> 
>> What would you suggest?
>> 
>> Cheers,
>> 
>> James
>> <unpredictable.patch>_______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy
>> the information in any medium.  Thank you.
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.<unpredictable.v2.patch>



From ahatanak at gmail.com  Wed Aug 17 12:45:08 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 17:45:08 -0000
Subject: [llvm-commits] [llvm] r137831 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsISelLowering.h
Message-ID: <20110817174508.E11A82A6C12C@llvm.org>

Author: ahatanak
Date: Wed Aug 17 12:45:08 2011
New Revision: 137831

URL: http://llvm.org/viewvc/llvm-project?rev=137831&view=rev
Log:
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137831&r1=137830&r2=137831&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 12:45:08 2011
@@ -131,8 +131,6 @@
   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Custom);
   setOperationAction(ISD::VASTART,            MVT::Other, Custom);
-  setOperationAction(ISD::AND,                MVT::i32,   Custom);
-  setOperationAction(ISD::OR,                 MVT::i32,   Custom);
 
   setOperationAction(ISD::SDIV, MVT::i32, Expand);
   setOperationAction(ISD::SREM, MVT::i32, Expand);
@@ -207,6 +205,8 @@
   setTargetDAGCombine(ISD::SDIVREM);
   setTargetDAGCombine(ISD::UDIVREM);
   setTargetDAGCombine(ISD::SETCC);
+  setTargetDAGCombine(ISD::AND);
+  setTargetDAGCombine(ISD::OR);
 
   setMinFunctionAlignment(2);
 
@@ -522,6 +522,102 @@
   return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
 }
 
+static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 const MipsSubtarget* Subtarget) {
+  // Pattern match EXT.
+  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
+  //  => ext $dst, $src, size, pos
+  if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
+    return SDValue();
+
+  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
+  
+  // Op's first operand must be a shift right.
+  if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
+    return SDValue();
+
+  // The second operand of the shift must be an immediate.
+  uint64_t Pos;
+  ConstantSDNode *CN;
+  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
+    return SDValue();
+  
+  Pos = CN->getZExtValue();
+
+  uint64_t SMPos, SMSize;
+  // Op's second operand must be a shifted mask.
+  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
+      !IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
+    return SDValue();
+
+  // Return if the shifted mask does not start at bit 0 or the sum of its size
+  // and Pos exceeds the word's size.
+  if (SMPos != 0 || Pos + SMSize > 32)
+    return SDValue();
+
+  return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
+                     ShiftRight.getOperand(0),
+                     DAG.getConstant(SMSize, MVT::i32),
+                     DAG.getConstant(Pos, MVT::i32));
+}
+  
+static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                const MipsSubtarget* Subtarget) {
+  // Pattern match INS.
+  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
+  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1 
+  //  => ins $dst, $src, size, pos, $src1
+  if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
+    return SDValue();
+
+  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
+  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
+  ConstantSDNode *CN;
+
+  // See if Op's first operand matches (and $src1 , mask0).
+  if (And0.getOpcode() != ISD::AND)
+    return SDValue();
+
+  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
+      !IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
+    return SDValue();
+
+  // See if Op's second operand matches (and (shl $src, pos), mask1).
+  if (And1.getOpcode() != ISD::AND)
+    return SDValue();
+  
+  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
+      !IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
+                     SMSize1))
+    return SDValue();
+
+  // The shift masks must have the same position and size.
+  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
+    return SDValue();
+
+  SDValue Shl = And1.getOperand(0);
+  if (Shl.getOpcode() != ISD::SHL)
+    return SDValue();
+
+  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
+    return SDValue();
+
+  unsigned Shamt = CN->getZExtValue();
+
+  // Return if the shift amount and the first bit position of mask are not the
+  // same.  
+  if (Shamt != SMPos0)
+    return SDValue();
+  
+  return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
+                     Shl.getOperand(0),
+                     DAG.getConstant(SMSize0, MVT::i32),
+                     DAG.getConstant(SMPos0, MVT::i32),
+                     And0.getOperand(0));  
+}
+  
 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
   const {
   SelectionDAG &DAG = DCI.DAG;
@@ -538,6 +634,10 @@
     return PerformDivRemCombine(N, DAG, DCI, Subtarget);
   case ISD::SETCC:
     return PerformSETCCCombine(N, DAG, DCI, Subtarget);
+  case ISD::AND:
+    return PerformANDCombine(N, DAG, DCI, Subtarget);
+  case ISD::OR:
+    return PerformORCombine(N, DAG, DCI, Subtarget);
   }
 
   return SDValue();
@@ -561,8 +661,6 @@
     case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
     case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
     case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
-    case ISD::AND:                return LowerAND(Op, DAG);
-    case ISD::OR:                 return LowerOR(Op, DAG);
   }
   return SDValue();
 }
@@ -1580,98 +1678,6 @@
                      DAG.getConstant(SType, MVT::i32));
 }
 
-SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
-  // Pattern match EXT.
-  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
-  //  => ext $dst, $src, size, pos
-  if (!Subtarget->isMips32r2())
-    return Op;
-
-  SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
-  
-  // Op's first operand must be a shift right.
-  if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
-    return Op;
-
-  // The second operand of the shift must be an immediate.
-  uint64_t Pos;
-  ConstantSDNode *CN;
-  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
-    return Op;
-  
-  Pos = CN->getZExtValue();
-
-  uint64_t SMPos, SMSize;
-  // Op's second operand must be a shifted mask.
-  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
-      !IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
-    return Op;
-
-  // Return if the shifted mask does not start at bit 0 or the sum of its size
-  // and Pos exceeds the word's size.
-  if (SMPos != 0 || Pos + SMSize > 32)
-    return Op;
-
-  return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
-                     ShiftRight.getOperand(0),
-                     DAG.getConstant(SMSize, MVT::i32),
-                     DAG.getConstant(Pos, MVT::i32));
-}
-
-SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
-  // Pattern match INS.
-  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
-  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1 
-  //  => ins $dst, $src, size, pos
-  if (!Subtarget->isMips32r2())
-    return Op;
-
-  SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
-  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
-  ConstantSDNode *CN;
-
-  // See if Op's first operand matches (and $src1 , mask0).
-  if (And0.getOpcode() != ISD::AND)
-    return Op;
-
-  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
-      !IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
-    return Op;
-
-  // See if Op's second operand matches (and (shl $src, pos), mask1).
-  if (And1.getOpcode() != ISD::AND)
-    return Op;
-  
-  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
-      !IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
-                     SMSize1))
-    return Op;
-
-  // The shift masks must have the same position and size.
-  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
-    return Op;
-
-  SDValue Shl = And1.getOperand(0);
-  if (Shl.getOpcode() != ISD::SHL)
-    return Op;
-
-  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
-    return Op;
-
-  unsigned Shamt = CN->getZExtValue();
-
-  // Return if the shift amount and the first bit position of mask are not the
-  // same.  
-  if (Shamt != SMPos0)
-    return Op;
-  
-  return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
-                     Shl.getOperand(0),
-                     DAG.getConstant(SMSize0, MVT::i32),
-                     DAG.getConstant(SMPos0, MVT::i32),
-                     And0.getOperand(0));  
-}
-
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137831&r1=137830&r2=137831&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Aug 17 12:45:08 2011
@@ -137,8 +137,6 @@
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
-    SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
-    SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
 
     virtual SDValue
       LowerFormalArguments(SDValue Chain,



From grosbach at apple.com  Wed Aug 17 12:46:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 17:46:01 -0000
Subject: [llvm-commits] [llvm] r137832 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817174601.986792A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 12:46:01 2011
New Revision: 137832

URL: http://llvm.org/viewvc/llvm-project?rev=137832&view=rev
Log:
Add missing '@' delimiter.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137832&r1=137831&r2=137832&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 12:46:01 2011
@@ -30,4 +30,4 @@
         add r2, r8
 
 @ CHECK: adds	r1, r2, r3              @ encoding: [0xd1,0x18]
-  CHECK: add	r2, r8                  @ encoding: [0x42,0x44]
+@ CHECK: add	r2, r8                  @ encoding: [0x42,0x44]



From wendling at apple.com  Wed Aug 17 12:50:06 2011
From: wendling at apple.com (Bill Wendling)
Date: Wed, 17 Aug 2011 10:50:06 -0700
Subject: [llvm-commits] [PATCH] DWARF EH Prepare for the New EH
In-Reply-To: <FE861719-0915-4664-B9FA-46DE5945269D@apple.com>
References: <FE861719-0915-4664-B9FA-46DE5945269D@apple.com>
Message-ID: <A8271C5C-58BD-48C9-A0B0-0E9162340862@apple.com>

Ping?

-bw

On Aug 15, 2011, at 1:31 AM, Bill Wendling wrote:

> This is a patch for the DwarfEHPrepare.cpp file to support the new EH model. It's very straight-forward. Any 'resume' instruction in the function is turned into a call to the appropriate "_Unwind_Resume()". The rest of the module isn't needed (and will be removed once we switch over) because of the lovely invariants. :-)
> 
> Please review and let me know if you have any comments.
> 
> -bw
> 
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_______________________________________________
> 
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Wed Aug 17 12:55:28 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 17:55:28 -0000
Subject: [llvm-commits] [llvm] r137833 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817175528.970432A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 12:55:28 2011
New Revision: 137833

URL: http://llvm.org/viewvc/llvm-project?rev=137833&view=rev
Log:
Thumb assembly parsing and encoding for ADC(register) instruction.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137833&r1=137832&r2=137833&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 12:55:28 2011
@@ -12,6 +12,14 @@
 @ CHECK: _func
 
 @------------------------------------------------------------------------------
+@ ADC (register)
+ at ------------------------------------------------------------------------------
+        adcs r4, r6
+
+@ CHECK: adcs	r4, r6                  @ encoding: [0x74,0x41]
+
+
+ at ------------------------------------------------------------------------------
 @ ADD (immediate)
 @------------------------------------------------------------------------------
         adds r1, r2, #3



From bruno.cardoso at gmail.com  Wed Aug 17 13:08:35 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 11:08:35 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
Message-ID: <CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>

Hi,

> Encoding of instruction "ext $dst, $src, $pos, $size" looks like this:
>
> field31-26, field25-21, field20-16, field15-11, field10-6, field5-0
> 31, ? ? ? ? ? $src, ? ? ? ? ?$dst, ? ? ? ? $size, ? ? ? $pos, ? ? ? 0
>
> The FR format binds the operands in the following order,
> (rd:field15-11), (rs:field25-21), (rt:field20-16), (shamt:field10-6)
>
> so if I want to use the FR format to define "ext $dst, $src, $pos,
> $size", the operands need to be given in the following order:
>
> $size, $src, $dst, $pos
>
> Is it possible to do so? In the format of FR, (dag outs) appears
> before (dag ins).

The format FR doesn't specify any constraints about the dags outs and
ins, but only with the encoding. In your ExtIns class which will
inherit from FR, you can assign the new encoding as for example:

let shamt = pos
let rd = size
...

One more thing, please use $rs and $rt directly, instead of $src and
$dst, this is actually what we should in all places.
Thanks

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Wed Aug 17 13:09:11 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 11:09:11 -0700
Subject: [llvm-commits] [llvm] r137831 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsISelLowering.h
In-Reply-To: <20110817174508.E11A82A6C12C@llvm.org>
References: <20110817174508.E11A82A6C12C@llvm.org>
Message-ID: <CACk9FxaN65n4N6UavZnn7_2KP3G1Y605odOXOp_KMcO_E2Zkhw@mail.gmail.com>

Thanks Akira!

On Wed, Aug 17, 2011 at 10:45 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Wed Aug 17 12:45:08 2011
> New Revision: 137831
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137831&view=rev
> Log:
> Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
>
>
> Modified:
> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.h
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137831&r1=137830&r2=137831&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 12:45:08 2011
> @@ -131,8 +131,6 @@
> ? setOperationAction(ISD::BRCOND, ? ? ? ? ? ? MVT::Other, Custom);
> ? setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, ? Custom);
> ? setOperationAction(ISD::VASTART, ? ? ? ? ? ?MVT::Other, Custom);
> - ?setOperationAction(ISD::AND, ? ? ? ? ? ? ? ?MVT::i32, ? Custom);
> - ?setOperationAction(ISD::OR, ? ? ? ? ? ? ? ? MVT::i32, ? Custom);
>
> ? setOperationAction(ISD::SDIV, MVT::i32, Expand);
> ? setOperationAction(ISD::SREM, MVT::i32, Expand);
> @@ -207,6 +205,8 @@
> ? setTargetDAGCombine(ISD::SDIVREM);
> ? setTargetDAGCombine(ISD::UDIVREM);
> ? setTargetDAGCombine(ISD::SETCC);
> + ?setTargetDAGCombine(ISD::AND);
> + ?setTargetDAGCombine(ISD::OR);
>
> ? setMinFunctionAlignment(2);
>
> @@ -522,6 +522,102 @@
> ? return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
> ?}
>
> +static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetLowering::DAGCombinerInfo &DCI,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MipsSubtarget* Subtarget) {
> + ?// Pattern match EXT.
> + ?// ?$dst = and ((sra or srl) $src , pos), (2**size - 1)
> + ?// ?=> ext $dst, $src, size, pos
> + ?if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
> + ? ?return SDValue();
> +
> + ?SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
> +
> + ?// Op's first operand must be a shift right.
> + ?if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
> + ? ?return SDValue();
> +
> + ?// The second operand of the shift must be an immediate.
> + ?uint64_t Pos;
> + ?ConstantSDNode *CN;
> + ?if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
> + ? ?return SDValue();
> +
> + ?Pos = CN->getZExtValue();
> +
> + ?uint64_t SMPos, SMSize;
> + ?// Op's second operand must be a shifted mask.
> + ?if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
> + ? ? ?!IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
> + ? ?return SDValue();
> +
> + ?// Return if the shifted mask does not start at bit 0 or the sum of its size
> + ?// and Pos exceeds the word's size.
> + ?if (SMPos != 0 || Pos + SMSize > 32)
> + ? ?return SDValue();
> +
> + ?return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
> + ? ? ? ? ? ? ? ? ? ? ShiftRight.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
> +}
> +
> +static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?TargetLowering::DAGCombinerInfo &DCI,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MipsSubtarget* Subtarget) {
> + ?// Pattern match INS.
> + ?// ?$dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
> + ?// ?where mask1 = (2**size - 1) << pos, mask0 = ~mask1
> + ?// ?=> ins $dst, $src, size, pos, $src1
> + ?if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2())
> + ? ?return SDValue();
> +
> + ?SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
> + ?uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
> + ?ConstantSDNode *CN;
> +
> + ?// See if Op's first operand matches (and $src1 , mask0).
> + ?if (And0.getOpcode() != ISD::AND)
> + ? ?return SDValue();
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
> + ? ? ?!IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
> + ? ?return SDValue();
> +
> + ?// See if Op's second operand matches (and (shl $src, pos), mask1).
> + ?if (And1.getOpcode() != ISD::AND)
> + ? ?return SDValue();
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
> + ? ? ?!IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
> + ? ? ? ? ? ? ? ? ? ? SMSize1))
> + ? ?return SDValue();
> +
> + ?// The shift masks must have the same position and size.
> + ?if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
> + ? ?return SDValue();
> +
> + ?SDValue Shl = And1.getOperand(0);
> + ?if (Shl.getOpcode() != ISD::SHL)
> + ? ?return SDValue();
> +
> + ?if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
> + ? ?return SDValue();
> +
> + ?unsigned Shamt = CN->getZExtValue();
> +
> + ?// Return if the shift amount and the first bit position of mask are not the
> + ?// same.
> + ?if (Shamt != SMPos0)
> + ? ?return SDValue();
> +
> + ?return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
> + ? ? ? ? ? ? ? ? ? ? Shl.getOperand(0),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMPos0, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? And0.getOperand(0));
> +}
> +
> ?SDValue ?MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
> ? const {
> ? SelectionDAG &DAG = DCI.DAG;
> @@ -538,6 +634,10 @@
> ? ? return PerformDivRemCombine(N, DAG, DCI, Subtarget);
> ? case ISD::SETCC:
> ? ? return PerformSETCCCombine(N, DAG, DCI, Subtarget);
> + ?case ISD::AND:
> + ? ?return PerformANDCombine(N, DAG, DCI, Subtarget);
> + ?case ISD::OR:
> + ? ?return PerformORCombine(N, DAG, DCI, Subtarget);
> ? }
>
> ? return SDValue();
> @@ -561,8 +661,6 @@
> ? ? case ISD::FRAMEADDR: ? ? ? ? ?return LowerFRAMEADDR(Op, DAG);
> ? ? case ISD::MEMBARRIER: ? ? ? ? return LowerMEMBARRIER(Op, DAG);
> ? ? case ISD::ATOMIC_FENCE: ? ? ? return LowerATOMIC_FENCE(Op, DAG);
> - ? ?case ISD::AND: ? ? ? ? ? ? ? ?return LowerAND(Op, DAG);
> - ? ?case ISD::OR: ? ? ? ? ? ? ? ? return LowerOR(Op, DAG);
> ? }
> ? return SDValue();
> ?}
> @@ -1580,98 +1678,6 @@
> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SType, MVT::i32));
> ?}
>
> -SDValue MipsTargetLowering::LowerAND(SDValue Op, SelectionDAG& DAG) const {
> - ?// Pattern match EXT.
> - ?// ?$dst = and ((sra or srl) $src , pos), (2**size - 1)
> - ?// ?=> ext $dst, $src, size, pos
> - ?if (!Subtarget->isMips32r2())
> - ? ?return Op;
> -
> - ?SDValue ShiftRight = Op.getOperand(0), Mask = Op.getOperand(1);
> -
> - ?// Op's first operand must be a shift right.
> - ?if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
> - ? ?return Op;
> -
> - ?// The second operand of the shift must be an immediate.
> - ?uint64_t Pos;
> - ?ConstantSDNode *CN;
> - ?if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
> - ? ?return Op;
> -
> - ?Pos = CN->getZExtValue();
> -
> - ?uint64_t SMPos, SMSize;
> - ?// Op's second operand must be a shifted mask.
> - ?if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
> - ? ? ?!IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
> - ? ?return Op;
> -
> - ?// Return if the shifted mask does not start at bit 0 or the sum of its size
> - ?// and Pos exceeds the word's size.
> - ?if (SMPos != 0 || Pos + SMSize > 32)
> - ? ?return Op;
> -
> - ?return DAG.getNode(MipsISD::Ext, Op.getDebugLoc(), MVT::i32,
> - ? ? ? ? ? ? ? ? ? ? ShiftRight.getOperand(0),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
> -}
> -
> -SDValue MipsTargetLowering::LowerOR(SDValue Op, SelectionDAG& DAG) const {
> - ?// Pattern match INS.
> - ?// ?$dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
> - ?// ?where mask1 = (2**size - 1) << pos, mask0 = ~mask1
> - ?// ?=> ins $dst, $src, size, pos
> - ?if (!Subtarget->isMips32r2())
> - ? ?return Op;
> -
> - ?SDValue And0 = Op.getOperand(0), And1 = Op.getOperand(1);
> - ?uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
> - ?ConstantSDNode *CN;
> -
> - ?// See if Op's first operand matches (and $src1 , mask0).
> - ?if (And0.getOpcode() != ISD::AND)
> - ? ?return Op;
> -
> - ?if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
> - ? ? ?!IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
> - ? ?return Op;
> -
> - ?// See if Op's second operand matches (and (shl $src, pos), mask1).
> - ?if (And1.getOpcode() != ISD::AND)
> - ? ?return Op;
> -
> - ?if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
> - ? ? ?!IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
> - ? ? ? ? ? ? ? ? ? ? SMSize1))
> - ? ?return Op;
> -
> - ?// The shift masks must have the same position and size.
> - ?if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
> - ? ?return Op;
> -
> - ?SDValue Shl = And1.getOperand(0);
> - ?if (Shl.getOpcode() != ISD::SHL)
> - ? ?return Op;
> -
> - ?if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
> - ? ?return Op;
> -
> - ?unsigned Shamt = CN->getZExtValue();
> -
> - ?// Return if the shift amount and the first bit position of mask are not the
> - ?// same.
> - ?if (Shamt != SMPos0)
> - ? ?return Op;
> -
> - ?return DAG.getNode(MipsISD::Ins, Op.getDebugLoc(), MVT::i32,
> - ? ? ? ? ? ? ? ? ? ? Shl.getOperand(0),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMPos0, MVT::i32),
> - ? ? ? ? ? ? ? ? ? ? And0.getOperand(0));
> -}
> -
> ?//===----------------------------------------------------------------------===//
> ?// ? ? ? ? ? ? ? ? ? ? ?Calling Convention Implementation
> ?//===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=137831&r1=137830&r2=137831&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Aug 17 12:45:08 2011
> @@ -137,8 +137,6 @@
> ? ? SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
> ? ? SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
> - ? ?SDValue LowerAND(SDValue Op, SelectionDAG& DAG) const;
> - ? ?SDValue LowerOR(SDValue Op, SelectionDAG& DAG) const;
>
> ? ? virtual SDValue
> ? ? ? LowerFormalArguments(SDValue Chain,
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bob.wilson at apple.com  Wed Aug 17 13:09:59 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 17 Aug 2011 18:09:59 -0000
Subject: [llvm-commits] [compiler-rt] r137835 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20110817180959.2D5DA2A6C12C@llvm.org>

Author: bwilson
Date: Wed Aug 17 13:09:59 2011
New Revision: 137835

URL: http://llvm.org/viewvc/llvm-project?rev=137835&view=rev
Log:
Add the ARM VFP variants to the cc_kext libraries for armv6 and armv7.
Radar 9959402.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=137835&r1=137834&r2=137835&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Wed Aug 17 13:09:59 2011
@@ -215,8 +215,42 @@
 	unorddf2 \
 	unordsf2
 
-FUNCTIONS.cc_kext.armv6 := $(CCKEXT_ARM_FUNCTIONS)
-FUNCTIONS.cc_kext.armv7 := $(CCKEXT_ARM_FUNCTIONS)
+CCKEXT_ARMVFP_FUNCTIONS := $(CCKEXT_ARM_FUNCTIONS) \
+	adddf3vfp \
+	addsf3vfp \
+	divdf3vfp \
+	divsf3vfp \
+	eqdf2vfp \
+	eqsf2vfp \
+	extendsfdf2vfp \
+	fixdfsivfp \
+	fixsfsivfp \
+	fixunsdfsivfp \
+	fixunssfsivfp \
+	floatsidfvfp \
+	floatsisfvfp \
+	floatunssidfvfp \
+	floatunssisfvfp \
+	gedf2vfp \
+	gesf2vfp \
+	gtdf2vfp \
+	gtsf2vfp \
+	ledf2vfp \
+	lesf2vfp \
+	ltdf2vfp \
+	ltsf2vfp \
+	muldf3vfp \
+	mulsf3vfp \
+	nedf2vfp \
+	nesf2vfp \
+	subdf3vfp \
+	subsf3vfp \
+	truncdfsf2vfp \
+	unorddf2vfp \
+	unordsf2vfp
+
+FUNCTIONS.cc_kext.armv6 := $(CCKEXT_ARMVFP_FUNCTIONS)
+FUNCTIONS.cc_kext.armv7 := $(CCKEXT_ARMVFP_FUNCTIONS)
 
 CCKEXT_X86_FUNCTIONS := $(CCKEXT_COMMON_FUNCTIONS) \
 	divxc3 \



From eli.friedman at gmail.com  Wed Aug 17 13:10:44 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 17 Aug 2011 18:10:44 -0000
Subject: [llvm-commits] [llvm] r137836 - in /llvm/trunk:
 lib/Transforms/Scalar/SCCP.cpp test/Transforms/SCCP/undef-resolve.ll
Message-ID: <20110817181044.19BEB2A6C12C@llvm.org>

Author: efriedma
Date: Wed Aug 17 13:10:43 2011
New Revision: 137836

URL: http://llvm.org/viewvc/llvm-project?rev=137836&view=rev
Log:
Silly mistake from r137777; restore significant isStructTy() checks.  While here, be a bit more defensive
with unknown instructions.

Fixes PR10687.


Modified:
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/test/Transforms/SCCP/undef-resolve.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=137836&r1=137835&r2=137836&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Wed Aug 17 13:10:43 2011
@@ -1436,7 +1436,7 @@
         // Only a few things that can be structs matter for undef.  Just send
         // all their results to overdefined.  We could be more precise than this
         // but it isn't worth bothering.
-        if (isa<CallInst>(I) || isa<SelectInst>(I)) {
+        if (!isa<ExtractValueInst>(I) && !isa<InsertValueInst>(I)) {
           for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
             LatticeVal &LV = getStructValueState(I, i);
             if (LV.isUndefined())
@@ -1449,16 +1449,31 @@
       LatticeVal &LV = getValueState(I);
       if (!LV.isUndefined()) continue;
 
+      // extractvalue is safe; check here because the argument is a struct.
+      if (isa<ExtractValueInst>(I))
+        continue;
+
+      // Compute the operand LatticeVals, for convenience below.
+      // Anything taking a struct is conservatively assumed to require
+      // overdefined markings.
+      if (I->getOperand(0)->getType()->isStructTy()) {
+        markOverdefined(I);
+        return true;
+      }
       LatticeVal Op0LV = getValueState(I->getOperand(0));
       LatticeVal Op1LV;
-      if (I->getNumOperands() == 2)
+      if (I->getNumOperands() == 2) {
+        if (I->getOperand(1)->getType()->isStructTy()) {
+          markOverdefined(I);
+          return true;
+        }
+
         Op1LV = getValueState(I->getOperand(1));
+      }
       // If this is an instructions whose result is defined even if the input is
       // not fully defined, propagate the information.
       Type *ITy = I->getType();
       switch (I->getOpcode()) {
-      case Instruction::ExtractValue:
-        break; // Extract of undef -> undef
       case Instruction::Add:
       case Instruction::Sub:
       case Instruction::Trunc:

Modified: llvm/trunk/test/Transforms/SCCP/undef-resolve.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/undef-resolve.ll?rev=137836&r1=137835&r2=137836&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SCCP/undef-resolve.ll (original)
+++ llvm/trunk/test/Transforms/SCCP/undef-resolve.ll Wed Aug 17 13:10:43 2011
@@ -161,3 +161,12 @@
 ; CHECK: @test9
 ; CHECK: icmp ugt
 }
+
+; Make sure we handle extractvalue
+define i64 @test10() { 
+entry:
+  %e = extractvalue { i64, i64 } undef, 1
+  ret i64 %e
+; CHECK: @test10
+; CHECK: ret i64 undef
+}



From resistor at mac.com  Wed Aug 17 13:14:48 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 17 Aug 2011 18:14:48 -0000
Subject: [llvm-commits] [llvm] r137838 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20110817181448.5134A2A6C12C@llvm.org>

Author: resistor
Date: Wed Aug 17 13:14:48 2011
New Revision: 137838

URL: http://llvm.org/viewvc/llvm-project?rev=137838&view=rev
Log:
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137838&r1=137837&r2=137838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 13:14:48 2011
@@ -329,17 +329,18 @@
 // that as a post-pass.
 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
+  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
   MCInst::iterator I = MI.begin();
-  for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
+  for (unsigned i = 0; i < NumOps; ++i, ++I) {
+    if (I == MI.end()) break;
     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
+      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
       MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
       return;
     }
   }
 
-  if (OpInfo[MI.size()].isOptionalDef() &&
-      OpInfo[MI.size()].RegClass == ARM::CCRRegClassID)
-    MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+  MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
 }
 
 // Most Thumb instructions don't have explicit predicates in the
@@ -367,8 +368,10 @@
     CC = ARMCC::AL;
 
   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
+  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
   MCInst::iterator I = MI.begin();
-  for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
+  for (unsigned i = 0; i < NumOps; ++i, ++I) {
+    if (I == MI.end()) break;
     if (OpInfo[i].isPredicate()) {
       I = MI.insert(I, MCOperand::CreateImm(CC));
       ++I;
@@ -380,11 +383,12 @@
     }
   }
 
-  MI.insert(MI.end(), MCOperand::CreateImm(CC));
+  I = MI.insert(I, MCOperand::CreateImm(CC));
+  ++I;
   if (CC == ARMCC::AL)
-    MI.insert(MI.end(), MCOperand::CreateReg(0));
+    MI.insert(I, MCOperand::CreateReg(0));
   else
-    MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR));
+    MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
 }
 
 // Thumb VFP instructions are a special case.  Because we share their



From resistor at mac.com  Wed Aug 17 13:21:37 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 17 Aug 2011 18:21:37 -0000
Subject: [llvm-commits] [llvm] r137840 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
Message-ID: <20110817182137.0E2402A6C12C@llvm.org>

Author: resistor
Date: Wed Aug 17 13:21:36 2011
New Revision: 137840

URL: http://llvm.org/viewvc/llvm-project?rev=137840&view=rev
Log:
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Added: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=137840&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Wed Aug 17 13:21:36 2011
@@ -0,0 +1,30 @@
+# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# ADC (register)
+#------------------------------------------------------------------------------
+# CHECK: adcs r4, r6
+
+0x74 0x41
+
+
+#------------------------------------------------------------------------------
+# ADD (immediate)
+#------------------------------------------------------------------------------
+# CHECK: adds r1, r2, #3
+# CHECK: adds r2, r2, #3
+# CHECK: adds r2, #8
+
+0xd1 0x1c
+0xd2 0x1c
+0x08 0x32
+
+
+#------------------------------------------------------------------------------
+# ADD (register)
+#------------------------------------------------------------------------------
+# CHECK: adds r1, r2, r3
+# CHECK: add r2, r8
+
+0xd1 0x18
+0x42 0x44



From jediknil at belkadan.com  Wed Aug 17 13:22:45 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 11:22:45 -0700
Subject: [llvm-commits] [llvm] r137791 - in /llvm/trunk:
	include/llvm/Support/DynamicLibrary.h lib/Support/DynamicLibrary.cpp
	lib/Support/Windows/DynamicLibrary.inc
In-Reply-To: <CADiQthN3LP042RGLEnW+Js5OWWf10mOk1B3BMK3_Vo-f7Oj8xw@mail.gmail.com>
References: <20110817002932.A04612A6C12C@llvm.org>
	<CADiQthN3LP042RGLEnW+Js5OWWf10mOk1B3BMK3_Vo-f7Oj8xw@mail.gmail.com>
Message-ID: <3CCA29E1-7FA1-46F6-8211-82EBA571AF89@belkadan.com>


On Aug 17, 2011, at 5:00, NAKAMURA Takumi wrote:

> WTF Cygwin! On Cygwin, RTLD_DEFAULT is NULL. Then,
> DynamicLibrary::isValid() says Data(==RTLD_DEFAULT) might be invalid.

Ah...right. I made sure the (already-existing) logic for getPermanentLibrary() was correct here, but didn't think about what effect it would have on the instance later.


> A suggested patch is here. Feel free to modify and apply it. :)

I'm wary of using (void *)(-1) because someday someone might decide that (void *)(-1) is a great way to represent RTLD_NEXT. I'll use an existing address instead.

Thanks for catching this!
Jordy

From jediknil at belkadan.com  Wed Aug 17 13:23:17 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 18:23:17 -0000
Subject: [llvm-commits] [llvm] r137841 -
	/llvm/trunk/include/llvm/Support/DynamicLibrary.h
Message-ID: <20110817182317.67D992A6C12C@llvm.org>

Author: jrose
Date: Wed Aug 17 13:23:17 2011
New Revision: 137841

URL: http://llvm.org/viewvc/llvm-project?rev=137841&view=rev
Log:
Don't use NULL to represent an invalid library; Cygwin uses this for RTLD_DEFAULT. Caught by Takumi.

Modified:
    llvm/trunk/include/llvm/Support/DynamicLibrary.h

Modified: llvm/trunk/include/llvm/Support/DynamicLibrary.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DynamicLibrary.h?rev=137841&r1=137840&r2=137841&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/DynamicLibrary.h (original)
+++ llvm/trunk/include/llvm/Support/DynamicLibrary.h Wed Aug 17 13:23:17 2011
@@ -32,13 +32,18 @@
   /// Note: there is currently no interface for temporarily loading a library,
   /// or for unloading libraries when the LLVM library is unloaded.
   class DynamicLibrary {
+    // Placeholder whose address represents an invalid library.
+    // We use this instead of NULL or a pointer-int pair because the OS library
+    // might define 0 or 1 to be "special" handles, such as "search all".
+    static const char Invalid;
+
     // Opaque data used to interface with OS-specific dynamic library handling.
     void *Data;
 
-    explicit DynamicLibrary(void *data = 0) : Data(data) {}
+    explicit DynamicLibrary(void *data = &Invalid) : Data(data) {}
   public:
     /// Returns true if the object refers to a valid library.
-    bool isValid() { return Data != 0; }
+    bool isValid() { return Data != &Invalid; }
 
     /// Searches through the library for the symbol \p symbolName. If it is
     /// found, the address of that symbol is returned. If not, NULL is returned.



From jediknil at belkadan.com  Wed Aug 17 13:28:14 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 18:28:14 -0000
Subject: [llvm-commits] [llvm] r137843 -
	/llvm/trunk/include/llvm/Support/DynamicLibrary.h
Message-ID: <20110817182814.999CE2A6C12C@llvm.org>

Author: jrose
Date: Wed Aug 17 13:28:14 2011
New Revision: 137843

URL: http://llvm.org/viewvc/llvm-project?rev=137843&view=rev
Log:
...and make sure DynamicLibrary builds by removing "const" from the Invalid placeholder.

Modified:
    llvm/trunk/include/llvm/Support/DynamicLibrary.h

Modified: llvm/trunk/include/llvm/Support/DynamicLibrary.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DynamicLibrary.h?rev=137843&r1=137842&r2=137843&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/DynamicLibrary.h (original)
+++ llvm/trunk/include/llvm/Support/DynamicLibrary.h Wed Aug 17 13:28:14 2011
@@ -35,7 +35,7 @@
     // Placeholder whose address represents an invalid library.
     // We use this instead of NULL or a pointer-int pair because the OS library
     // might define 0 or 1 to be "special" handles, such as "search all".
-    static const char Invalid;
+    static char Invalid;
 
     // Opaque data used to interface with OS-specific dynamic library handling.
     void *Data;



From benny.kra at googlemail.com  Wed Aug 17 13:36:17 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Wed, 17 Aug 2011 11:36:17 -0700
Subject: [llvm-commits] [llvm] r137843 -
	/llvm/trunk/include/llvm/Support/DynamicLibrary.h
In-Reply-To: <20110817182814.999CE2A6C12C@llvm.org>
References: <20110817182814.999CE2A6C12C@llvm.org>
Message-ID: <CAL3drCokyQe-qQvJ2MN3-pBs17d1Ci3mY2qveo7NY7iPqMvyYQ@mail.gmail.com>

On Wed, Aug 17, 2011 at 11:28, Jordy Rose <jediknil at belkadan.com> wrote:
> Author: jrose
> Date: Wed Aug 17 13:28:14 2011
> New Revision: 137843
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137843&view=rev
> Log:
> ...and make sure DynamicLibrary builds by removing "const" from the Invalid placeholder.
>
> Modified:
> ? ?llvm/trunk/include/llvm/Support/DynamicLibrary.h
>
> Modified: llvm/trunk/include/llvm/Support/DynamicLibrary.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DynamicLibrary.h?rev=137843&r1=137842&r2=137843&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/DynamicLibrary.h (original)
> +++ llvm/trunk/include/llvm/Support/DynamicLibrary.h Wed Aug 17 13:28:14 2011
> @@ -35,7 +35,7 @@
> ? ? // Placeholder whose address represents an invalid library.
> ? ? // We use this instead of NULL or a pointer-int pair because the OS library
> ? ? // might define 0 or 1 to be "special" handles, such as "search all".
> - ? ?static const char Invalid;
> + ? ?static char Invalid;

You also have to define it in a .cpp file, otherwise linking will fail.

- Ben


From jediknil at belkadan.com  Wed Aug 17 13:38:42 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 18:38:42 -0000
Subject: [llvm-commits] [llvm] r137844 -
	/llvm/trunk/lib/Support/DynamicLibrary.cpp
Message-ID: <20110817183842.436682A6C12C@llvm.org>

Author: jrose
Date: Wed Aug 17 13:38:42 2011
New Revision: 137844

URL: http://llvm.org/viewvc/llvm-project?rev=137844&view=rev
Log:
Static fields require an out-of-line definition. Fix DynamicLibrary for real.

Modified:
    llvm/trunk/lib/Support/DynamicLibrary.cpp

Modified: llvm/trunk/lib/Support/DynamicLibrary.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/DynamicLibrary.cpp?rev=137844&r1=137843&r2=137844&view=diff
==============================================================================
--- llvm/trunk/lib/Support/DynamicLibrary.cpp (original)
+++ llvm/trunk/lib/Support/DynamicLibrary.cpp Wed Aug 17 13:38:42 2011
@@ -50,6 +50,8 @@
   (*ExplicitSymbols)[symbolName] = symbolValue;
 }
 
+char llvm::sys::DynamicLibrary::Invalid = 0;
+
 #ifdef LLVM_ON_WIN32
 
 #include "Windows/DynamicLibrary.inc"



From dpatel at apple.com  Wed Aug 17 13:38:44 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 18:38:44 -0000
Subject: [llvm-commits] [llvm] r137845 -
	/llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
Message-ID: <20110817183844.A7EC92A6C12D@llvm.org>

Author: dpatel
Date: Wed Aug 17 13:38:44 2011
New Revision: 137845

URL: http://llvm.org/viewvc/llvm-project?rev=137845&view=rev
Log:
Robustify test.

Modified:
    llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp

Modified: llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-02-17-DbgArtificialArg.cpp?rev=137845&r1=137844&r2=137845&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp Wed Aug 17 13:38:44 2011
@@ -1,5 +1,4 @@
-// RUN: %llvmgcc -g -S %s -o - | FileCheck %s
-// Here, second to last argument "i32 64" indicates that artificial type is set.                                               
+// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o - | %llc -asm-verbose | FileCheck %s
 // Test to artificial attribute attahed to "this" pointer type.
 // Radar 7655792 and 7655002
 
@@ -10,7 +9,12 @@
 
 int foo() {
   A a;
-  // Matching "i32 64, metadata !<number>} ; [ DW_TAG_pointer_type ]"
-  // CHECK: i32 64, metadata {{![0-9]+\} ; \[ DW_TAG_pointer_type \]}}
+//CHECK:        .ascii   "this"                 ## DW_AT_name
+//CHECK-NEXT:        .byte   0
+//CHECK-NEXT:        ## DW_AT_decl_file
+//CHECK-NEXT:        ## DW_AT_decl_line
+//CHECK-NEXT:        ## DW_AT_type
+//CHECK-NEXT:        ## DW_AT_artificial
+
   return a.fn1(1);
 }



From dpatel at apple.com  Wed Aug 17 13:39:13 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 18:39:13 -0000
Subject: [llvm-commits] [llvm] r137846 -
 /llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m
Message-ID: <20110817183913.364982A6C12C@llvm.org>

Author: dpatel
Date: Wed Aug 17 13:39:13 2011
New Revision: 137846

URL: http://llvm.org/viewvc/llvm-project?rev=137846&view=rev
Log:
Remove superficial test.

Removed:
    llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m

Removed: llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m?rev=137845&view=auto
==============================================================================
--- llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m (original)
+++ llvm/trunk/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgcc -S -O0 -g %s -o - | grep DW_TAG_variable | count 1
-
-// Do not emit debug info for unnamed builtin CFString variable.
- at interface Foo
- at end
-Foo *FooName = @"FooBar";



From clattner at apple.com  Wed Aug 17 13:40:31 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 11:40:31 -0700
Subject: [llvm-commits] [PATCH] AndOrXor Chain Optimization
In-Reply-To: <CAJdarcGUPt_OEe6A2hNkTXxUk0Uq_pzKakVdEduBOd+SuK-x9A@mail.gmail.com>
References: <CADP2NNELWKQPdzH+MH1d1w-nFUf_vGrbKqzK4DT5mODsEkw23A@mail.gmail.com>
	<CAJdarcF_iToH1Ckn48WnnvLSry-y39RnEKZqseeV6whkk9qNXA@mail.gmail.com>
	<CADP2NNFmqxxVnkKv76WVZUsb++RafadtWm6vWnYSGded_kVC5A@mail.gmail.com>
	<CADP2NNE8e3E9x3_PBC7de7V8mC3RM3u65ZU_a2Hb=KrFf_AEoQ@mail.gmail.com>
	<CAJdarcGUPt_OEe6A2hNkTXxUk0Uq_pzKakVdEduBOd+SuK-x9A@mail.gmail.com>
Message-ID: <98DF4F70-9268-4C5E-9C7F-998460405BB4@apple.com>


On Aug 16, 2011, at 3:47 PM, Eli Friedman wrote:

> 2011/8/16 Daniel Nic?cio <dnicacios at gmail.com>:
>> ping
>> Updated patch with revision 137728
> 
> This is a lot of code for a rather obscure optimization; I don't see
> how it is worthwhile.

I agree.  Does this actually speed up a known program, or is this just a theoretical exercise?

-Chris

> -Eli
> 
>> 2011/8/5 Daniel Nic?cio <dnicacios at gmail.com>
>>> 
>>> New unified diff file attached.
>>> Daniel Nicacio
>>> 
>>> 2011/8/4 Eli Friedman <eli.friedman at gmail.com>
>>>> 
>>>> 2011/8/4 Daniel Nic?cio <dnicacios at gmail.com>
>>>>> 
>>>>> Hi, this patch increments the instcombiner pass.
>>>>> It adds a new XOR, OR, AND optimization, trying to find a chain of
>>>>> logical instructions (xor, and, or) operating on different bits of the same
>>>>> word. If this chain is found, it is collapsed into a single logical
>>>>> instruction.
>>>>> The figure below shows a generic example:
>>>>> Any comments and critics are welcome.
>>>> 
>>>> Please attach a single diff containing all the changes, and please use
>>>> "svn diff" or some other tool that makes a unified diff.
>>>> -Eli
>> 
>> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From jediknil at belkadan.com  Wed Aug 17 13:41:52 2011
From: jediknil at belkadan.com (Jordy Rose)
Date: Wed, 17 Aug 2011 11:41:52 -0700
Subject: [llvm-commits] [llvm] r137843 -
	/llvm/trunk/include/llvm/Support/DynamicLibrary.h
References: <01D149E1-C751-41AC-9404-73B9D65028B2@belkadan.com>
Message-ID: <3BA06D17-2763-4FF9-A114-5924EB256923@belkadan.com>

Just caught this, thanks. Need to stop committing just because one file builds...I get twitchy when something's broken and today it's made me break more things. :-(


On Aug 17, 2011, at 11:28, Jordy Rose wrote:

> Author: jrose
> Date: Wed Aug 17 13:28:14 2011
> New Revision: 137843
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137843&view=rev
> Log:
> ...and make sure DynamicLibrary builds by removing "const" from the Invalid placeholder.
> 
> Modified:
>   llvm/trunk/include/llvm/Support/DynamicLibrary.h
> 
> Modified: llvm/trunk/include/llvm/Support/DynamicLibrary.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DynamicLibrary.h?rev=137843&r1=137842&r2=137843&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/DynamicLibrary.h (original)
> +++ llvm/trunk/include/llvm/Support/DynamicLibrary.h Wed Aug 17 13:28:14 2011
> @@ -35,7 +35,7 @@
>    // Placeholder whose address represents an invalid library.
>    // We use this instead of NULL or a pointer-int pair because the OS library
>    // might define 0 or 1 to be "special" handles, such as "search all".
> -    static const char Invalid;
> +    static char Invalid;
> 
>    // Opaque data used to interface with OS-specific dynamic library handling.
>    void *Data;
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Wed Aug 17 13:42:05 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 11:42:05 -0700
Subject: [llvm-commits] [llvm] r137777 - in /llvm/trunk:
 lib/Transforms/Scalar/SCCP.cpp test/Transforms/SCCP/undef-resolve.ll
In-Reply-To: <20110816220631.C442A2A6C12C@llvm.org>
References: <20110816220631.C442A2A6C12C@llvm.org>
Message-ID: <D23EE8F3-68A2-4607-9F37-F94F7E907A42@apple.com>


On Aug 16, 2011, at 3:06 PM, Eli Friedman wrote:

> Author: efriedma
> Date: Tue Aug 16 17:06:31 2011
> New Revision: 137777
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137777&view=rev
> Log:
> A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop
> making random bad assumptions about instructions which are not explicitly listed.  
> 
> Includes fix for rdar://9956541, a version of "undef ^ undef should return
> 0 because it's easier than arguing with users".

Thanks Eli.  That's a hilarious and completely accurate way of looking at this :)

-Chris

From clattner at apple.com  Wed Aug 17 13:43:52 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 11:43:52 -0700
Subject: [llvm-commits] [llvm] r137744 - in /llvm/trunk:
 include/llvm/BasicBlock.h lib/VMCore/BasicBlock.cpp
In-Reply-To: <20110816204253.162F22A6C12C@llvm.org>
References: <20110816204253.162F22A6C12C@llvm.org>
Message-ID: <FB8574A7-0535-49A7-8EF4-4DC1A7F99CF6@apple.com>


On Aug 16, 2011, at 1:42 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Aug 16 15:42:52 2011
> New Revision: 137744
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137744&view=rev
> Log:
> Add getFirstInsertionPt() method.
> 
> getFirstInsertionPt() returns an iterator to the first insertion point in a
> basic block. This is after all PHIs and any other instruction which is required
> to be at the top of the basic block (like LandingPadInst).

Cool

> +++ llvm/trunk/include/llvm/BasicBlock.h Tue Aug 16 15:42:52 2011
> @@ -145,6 +145,15 @@
>     return const_cast<BasicBlock*>(this)->getFirstNonPHIOrDbgOrLifetime();
>   }
> 
> +  /// getFirstInsertionPt - Returns an iterator to the first instruction in this
> +  /// block that is suitable for inserting a non-PHI instruction. In particular,
> +  /// it skips all PHIs and LandingPad instructions. Returns 0 if there are no
> +  /// non-PHI instructions.

The last sentence doesn't make sense.

-Chris

> +  iterator getFirstInsertionPt();
> +  const_iterator getFirstInsertionPt() const {
> +    return const_cast<BasicBlock*>(this)->getFirstInsertionPt();
> +  }
> +
>   /// removeFromParent - This method unlinks 'this' from the containing
>   /// function, but does not delete it.
>   ///
> 
> Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=137744&r1=137743&r2=137744&view=diff
> ==============================================================================
> --- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
> +++ llvm/trunk/lib/VMCore/BasicBlock.cpp Tue Aug 16 15:42:52 2011
> @@ -167,6 +167,12 @@
>   return &*i;
> }
> 
> +BasicBlock::iterator BasicBlock::getFirstInsertionPt() {
> +  iterator InsertPt = getFirstNonPHI();
> +  if (isa<LandingPadInst>(InsertPt)) ++InsertPt;
> +  return InsertPt;
> +}
> +
> void BasicBlock::dropAllReferences() {
>   for(iterator I = begin(), E = end(); I != E; ++I)
>     I->dropAllReferences();
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dpatel at apple.com  Wed Aug 17 13:48:29 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 18:48:29 -0000
Subject: [llvm-commits] [llvm] r137847 -
	/llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
Message-ID: <20110817184829.136DA2A6C12C@llvm.org>

Author: dpatel
Date: Wed Aug 17 13:48:28 2011
New Revision: 137847

URL: http://llvm.org/viewvc/llvm-project?rev=137847&view=rev
Log:
Fix test case.

Modified:
    llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp

Modified: llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-02-17-DbgArtificialArg.cpp?rev=137847&r1=137846&r2=137847&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp Wed Aug 17 13:48:28 2011
@@ -1,4 +1,5 @@
-// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o - | %llc -asm-verbose | FileCheck %s
+// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o %t
+// RUN: llc -asm-verbose < %t | FileCheck %s
 // Test to artificial attribute attahed to "this" pointer type.
 // Radar 7655792 and 7655002
 



From ahatanak at gmail.com  Wed Aug 17 13:49:18 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 18:49:18 -0000
Subject: [llvm-commits] [llvm] r137848 - in /llvm/trunk/lib/Target/Mips:
 MipsAsmPrinter.cpp MipsISelLowering.cpp MipsInstrInfo.td
Message-ID: <20110817184918.B52CF2A6C12C@llvm.org>

Author: ahatanak
Date: Wed Aug 17 13:49:18 2011
New Revision: 137848

URL: http://llvm.org/viewvc/llvm-project?rev=137848&view=rev
Log:
Add support for half-word unaligned loads and stores.


Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=137848&r1=137847&r2=137848&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Wed Aug 17 13:49:18 2011
@@ -77,17 +77,28 @@
   MCInstLowering.Lower(MI, TmpInst0);
   
   // Convert aligned loads/stores to their unaligned counterparts.
-  // FIXME: expand other unaligned memory accesses too.
-  if ((Opc == Mips::LW || Opc == Mips::SW) && !MI->memoperands_empty() &&
-      (*MI->memoperands_begin())->getAlignment() < 4) {
-    MCInst Directive;
-    Directive.setOpcode(Mips::MACRO);
-    OutStreamer.EmitInstruction(Directive);
-    TmpInst0.setOpcode(Opc == Mips::LW ? Mips::ULW : Mips::USW);
-    OutStreamer.EmitInstruction(TmpInst0);
-    Directive.setOpcode(Mips::NOMACRO);
-    OutStreamer.EmitInstruction(Directive);
-    return;
+  if (!MI->memoperands_empty()) {
+    unsigned NaturalAlignment, UnalignedOpc;
+    
+    switch (Opc) {
+    case Mips::LW:  NaturalAlignment = 4; UnalignedOpc = Mips::ULW;  break;
+    case Mips::SW:  NaturalAlignment = 4; UnalignedOpc = Mips::USW;  break;
+    case Mips::LH:  NaturalAlignment = 2; UnalignedOpc = Mips::ULH;  break;
+    case Mips::LHu: NaturalAlignment = 2; UnalignedOpc = Mips::ULHu; break;
+    case Mips::SH:  NaturalAlignment = 2; UnalignedOpc = Mips::USH;  break;
+    default:        NaturalAlignment = 0;
+    }
+
+    if ((*MI->memoperands_begin())->getAlignment() < NaturalAlignment) {
+      MCInst Directive;
+      Directive.setOpcode(Mips::MACRO);
+      OutStreamer.EmitInstruction(Directive);
+      TmpInst0.setOpcode(UnalignedOpc);
+      OutStreamer.EmitInstruction(TmpInst0);
+      Directive.setOpcode(Mips::NOMACRO);
+      OutStreamer.EmitInstruction(Directive);
+      return;
+    }
   }
 
   OutStreamer.EmitInstruction(TmpInst0);

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137848&r1=137847&r2=137848&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 13:49:18 2011
@@ -218,8 +218,8 @@
 }
 
 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
-  // FIXME: allow unaligned memory accesses for other types too.
-  return VT.getSimpleVT().SimpleTy == MVT::i32; 
+  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
+  return SVT == MVT::i32 || SVT == MVT::i16; 
 }
 
 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137848&r1=137847&r2=137848&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 17 13:49:18 2011
@@ -483,12 +483,18 @@
   def ATOMIC_CMP_SWAP_I32  : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
 }
 
-// Unaligned memory load and store.
+// Unaligned loads and stores.
 // Replaces LW or SW during MCInstLowering if memory access is unaligned.
 def ULW :
   MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulw\t$dst, $addr", []>;
+def ULH :
+  MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulh\t$dst, $addr", []>;
+def ULHu :
+  MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulhu\t$dst, $addr", []>;
 def USW : 
   MipsPseudo<(outs), (ins CPURegs:$dst, mem:$addr), "usw\t$dst, $addr", []>;
+def USH : 
+  MipsPseudo<(outs), (ins CPURegs:$dst, mem:$addr), "ush\t$dst, $addr", []>;
 
 //===----------------------------------------------------------------------===//
 // Instruction definition



From eli.friedman at gmail.com  Wed Aug 17 14:31:49 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 17 Aug 2011 19:31:49 -0000
Subject: [llvm-commits] [llvm] r137853 -
	/llvm/trunk/lib/Analysis/InstructionSimplify.cpp
Message-ID: <20110817193149.C51C72A6C12C@llvm.org>

Author: efriedma
Date: Wed Aug 17 14:31:49 2011
New Revision: 137853

URL: http://llvm.org/viewvc/llvm-project?rev=137853&view=rev
Log:
Revert r137781; I agree with Duncan's comment that the situation in question is clearly impossible given the current structure of the code.


Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=137853&r1=137852&r2=137853&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Aug 17 14:31:49 2011
@@ -1348,11 +1348,6 @@
     std::swap(Op0, Op1);
   }
 
-  // A ^ A = 0
-  // Do this first so that we catch the undef ^ undef "idiom".
-  if (Op0 == Op1)
-    return Constant::getNullValue(Op0->getType());
-
   // A ^ undef -> undef
   if (match(Op1, m_Undef()))
     return Op1;
@@ -1361,6 +1356,10 @@
   if (match(Op1, m_Zero()))
     return Op0;
 
+  // A ^ A = 0
+  if (Op0 == Op1)
+    return Constant::getNullValue(Op0->getType());
+
   // A ^ ~A  =  ~A ^ A  =  -1
   if (match(Op0, m_Not(m_Specific(Op1))) ||
       match(Op1, m_Not(m_Specific(Op0))))



From isanbard at gmail.com  Wed Aug 17 14:33:27 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 19:33:27 -0000
Subject: [llvm-commits] [llvm] r137854 -
	/llvm/trunk/include/llvm/BasicBlock.h
Message-ID: <20110817193327.A74A42A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 14:33:27 2011
New Revision: 137854

URL: http://llvm.org/viewvc/llvm-project?rev=137854&view=rev
Log:
Remove unneeded sentence.

Modified:
    llvm/trunk/include/llvm/BasicBlock.h

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=137854&r1=137853&r2=137854&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Wed Aug 17 14:33:27 2011
@@ -147,8 +147,7 @@
 
   /// getFirstInsertionPt - Returns an iterator to the first instruction in this
   /// block that is suitable for inserting a non-PHI instruction. In particular,
-  /// it skips all PHIs and LandingPad instructions. Returns 0 if there are no
-  /// non-PHI instructions.
+  /// it skips all PHIs and LandingPad instructions.
   iterator getFirstInsertionPt();
   const_iterator getFirstInsertionPt() const {
     return const_cast<BasicBlock*>(this)->getFirstInsertionPt();



From isanbard at gmail.com  Wed Aug 17 14:34:58 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 12:34:58 -0700
Subject: [llvm-commits] [llvm] r137744 - in /llvm/trunk:
 include/llvm/BasicBlock.h lib/VMCore/BasicBlock.cpp
In-Reply-To: <FB8574A7-0535-49A7-8EF4-4DC1A7F99CF6@apple.com>
References: <20110816204253.162F22A6C12C@llvm.org>
	<FB8574A7-0535-49A7-8EF4-4DC1A7F99CF6@apple.com>
Message-ID: <A51B74D7-64BE-46DE-B607-76D5F1F361F4@gmail.com>

On Aug 17, 2011, at 11:43 AM, Chris Lattner wrote:

>> +++ llvm/trunk/include/llvm/BasicBlock.h Tue Aug 16 15:42:52 2011
>> @@ -145,6 +145,15 @@
>>    return const_cast<BasicBlock*>(this)->getFirstNonPHIOrDbgOrLifetime();
>>  }
>> 
>> +  /// getFirstInsertionPt - Returns an iterator to the first instruction in this
>> +  /// block that is suitable for inserting a non-PHI instruction. In particular,
>> +  /// it skips all PHIs and LandingPad instructions. Returns 0 if there are no
>> +  /// non-PHI instructions.
> 
> The last sentence doesn't make sense.
> 
I was copying what was in getFirstNonPHI's comment. But it doesn't look right in this context.

-bw



From echristo at apple.com  Wed Aug 17 14:39:41 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 17 Aug 2011 12:39:41 -0700
Subject: [llvm-commits] [llvm] r137845 -
 /llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
In-Reply-To: <20110817183844.A7EC92A6C12D@llvm.org>
References: <20110817183844.A7EC92A6C12D@llvm.org>
Message-ID: <9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>


On Aug 17, 2011, at 11:38 AM, Devang Patel wrote:

> Author: dpatel
> Date: Wed Aug 17 13:38:44 2011
> New Revision: 137845
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137845&view=rev
> Log:
> Robustify test.
> 
> Modified:
>    llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
> 
> Modified: llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-02-17-DbgArtificialArg.cpp?rev=137845&r1=137844&r2=137845&view=diff
> ==============================================================================
> --- llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (original)
> +++ llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp Wed Aug 17 13:38:44 2011
> @@ -1,5 +1,4 @@
> -// RUN: %llvmgcc -g -S %s -o - | FileCheck %s
> -// Here, second to last argument "i32 64" indicates that artificial type is set.                                               
> +// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o - | %llc -asm-verbose | FileCheck %s
> // Test to artificial attribute attahed to "this" pointer type.
> // Radar 7655792 and 7655002
> 
> @@ -10,7 +9,12 @@
> 
> int foo() {
>   A a;
> -  // Matching "i32 64, metadata !<number>} ; [ DW_TAG_pointer_type ]"
> -  // CHECK: i32 64, metadata {{![0-9]+\} ; \[ DW_TAG_pointer_type \]}}
> +//CHECK:        .ascii   "this"                 ## DW_AT_name
> +//CHECK-NEXT:        .byte   0
> +//CHECK-NEXT:        ## DW_AT_decl_file
> +//CHECK-NEXT:        ## DW_AT_decl_line
> +//CHECK-NEXT:        ## DW_AT_type
> +//CHECK-NEXT:        ## DW_AT_artificial
> +
>   return a.fn1(1);
> }
> 

What, in particular, are you trying to test with this test? I.e. can you break it up into backend portions when you already have the front end emitting what you want and test the front end separately to make sure it's emitting what you want?

I say this because I'm getting rid of all these tests and a run line this complicated puts it at the top of my "delete this test" line instead of the "try to figure out how to migrate this test" line.

-eric

From isanbard at gmail.com  Wed Aug 17 14:48:49 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 19:48:49 -0000
Subject: [llvm-commits] [llvm] r137855 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20110817194849.A71D02A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 14:48:49 2011
New Revision: 137855

URL: http://llvm.org/viewvc/llvm-project?rev=137855&view=rev
Log:
Modify for the new EH scheme.

Things are much saner now. We no longer need to modify the laning pads, because
of the invariants we impose upon them. The only thing DwarfEHPrepare needs to do
is convert the 'resume' instruction into a call to '_Unwind_Resume'.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=137855&r1=137854&r2=137855&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Wed Aug 17 14:48:49 2011
@@ -63,6 +63,8 @@
     typedef SmallPtrSet<BasicBlock*, 8> BBSet;
     BBSet LandingPads;
 
+    bool InsertUnwindResumeCalls();
+
     bool NormalizeLandingPads();
     bool LowerUnwindsAndResumes();
     bool MoveExceptionValueCalls();
@@ -658,13 +660,67 @@
   return CallInst::Create(ExceptionValueIntrinsic, "eh.value.call", Start);
 }
 
+/// InsertUnwindResumeCalls - Convert the ResumeInsts that are still present
+/// into calls to the appropriate _Unwind_Resume function.
+bool DwarfEHPrepare::InsertUnwindResumeCalls() {
+  SmallVector<ResumeInst*, 16> Resumes;
+  for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I)
+    for (BasicBlock::iterator II = I->begin(), IE = I->end(); II != IE; ++II)
+      if (ResumeInst *RI = dyn_cast<ResumeInst>(II))
+        Resumes.push_back(RI);
+
+  if (Resumes.empty())
+    return false;
+
+  // Find the rewind function if we didn't already.
+  if (!RewindFunction) {
+    LLVMContext &Ctx = Resumes[0]->getContext();
+    FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx),
+                                          Type::getInt8PtrTy(Ctx), false);
+    const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME);
+    RewindFunction = F->getParent()->getOrInsertFunction(RewindName, FTy);
+  }
+
+  // Create the basic block where the _Unwind_Resume call will live.
+  LLVMContext &Ctx = F->getContext();
+  BasicBlock *UnwindBB = BasicBlock::Create(Ctx, "unwind_resume", F);
+  PHINode *PN = PHINode::Create(Type::getInt8PtrTy(Ctx), Resumes.size(),
+                                "exn.obj", UnwindBB);
+
+  // Extract the exception object from the ResumeInst and add it to the PHI node
+  // that feeds the _Unwind_Resume call.
+  for (SmallVectorImpl<ResumeInst*>::iterator
+         I = Resumes.begin(), E = Resumes.end(); I != E; ++I) {
+    ResumeInst *RI = *I;
+    BranchInst::Create(UnwindBB, RI->getParent());
+    ExtractValueInst *ExnObj = ExtractValueInst::Create(RI->getOperand(0),
+                                                        0, "exn.obj", RI);
+    PN->addIncoming(ExnObj, RI->getParent());
+    RI->eraseFromParent();
+  }
+
+  // Call the function.
+  CallInst *CI = CallInst::Create(RewindFunction, PN, "", UnwindBB);
+  CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
+
+  // We never expect _Unwind_Resume to return.
+  new UnreachableInst(Ctx, UnwindBB);
+  return true;
+}
+
 bool DwarfEHPrepare::runOnFunction(Function &Fn) {
   bool Changed = false;
 
   // Initialize internal state.
-  DT = &getAnalysis<DominatorTree>();
+  DT = &getAnalysis<DominatorTree>(); // FIXME: We won't need this with the new EH.
   F = &Fn;
 
+  if (InsertUnwindResumeCalls()) {
+    // FIXME: The reset of this function can go once the new EH is done.
+    LandingPads.clear();
+    return true;
+  }
+
   // Ensure that only unwind edges end at landing pads (a landing pad is a
   // basic block where an invoke unwind edge ends).
   Changed |= NormalizeLandingPads();



From baldrick at free.fr  Wed Aug 17 14:51:20 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 17 Aug 2011 21:51:20 +0200
Subject: [llvm-commits] [llvm] r137642 -
	/llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <3662CABE-D544-4DBF-A000-DF50662BAEB9@apple.com>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
	<E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
	<CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>
	<E4C3B135-C7D4-43DB-81C2-94D03CDFA287@apple.com>
	<3662CABE-D544-4DBF-A000-DF50662BAEB9@apple.com>
Message-ID: <4E4C1BB8.6010008@free.fr>

Hi Bill, after thinking about this some more I'm starting to agree with John.
It is true that if you invoke a function that throws in a loop, then each
time the landing pad returns a different exception.  But that is because the
called function F is allocating a different exception each time.  Thus F is
not a readonly function :)  However you can imagine a situation in which
exception data has been preallocated, and a readonly function F throws the
same exception each time it is called.  Then the landing pad would return the
same exception each time [*].  In short, it is not the landing pad that is
reading/writing memory, it is the called function.  Indeed the exception
mechanism can be seen as just an alternative way of returning from the function.
Then the landing pad instruction is just like a way of talking about the
returned result, and thus doesn't really do anything (this is vaguely analogous
to a phi node :)), let alone read or write memory.

For example, suppose F can be hoisted out of a loop (eg: because it is readonly
and the loop logic can prove it must execute the same every time).  Then the
landing pad instruction should be hoistable too.  So I'm thinking that stopping
the loop optimizers doing things to landing pad instructions (beyond getting
them to preserve the landing pad invariants) is wrong in general.

Ciao, Duncan.

[*] OK, the unwinder does write stuff into the exception data, but I'm not sure
that matters since semantically this is invisible.

>> This is not an appropriate way of thinking about the instruction.  What
>> happens during unwinding inheres to the abnormal edge out of a call,
>> regardless of whether there's a landing pad or whether that landing
>> pad is actually visited during unwinding.
>>
>> This is exactly the sort of thing that makes me think that hacking
>> mayReadMemory() is not the appropriate solution.
>>
> I disagree. I think it's appropriate to think of this instruction as embodying the events that happen along the abnormal edge. If you consider a regular call, it's used without regard to whether the call may actually return or whether an exception will cause the program to continue at a function up the call stack. The landingpad is analogous.
>
>>> We're still allowed to move instructions which may read from or write to memory around, it just requires a bit of extra care. As it is, the instructions which can be moved into the landing pad past the landingpad instruction are rather light-weight instructions which don't read from memory anyway (this is because they're being sunk below an invoke). I'm skeptical that this will adversely affect optimizations for most code.
>>
>> I'm mostly worried that you're trying to get around doing the actual
>> correctness work by making general routines inhibit optimization
>> in all the cases you can think of off the top of your head.
>>
> John, I have thought about this carefully, and this isn't a decision I made without consideration. I appreciate your concern about marking these instructions as reading/writing memory. I simply don't share it. I'm not trying to get around correctness work.
>
> -bw
>


From grosbach at apple.com  Wed Aug 17 14:53:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 19:53:53 -0000
Subject: [llvm-commits] [llvm] r137856 -
	/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
Message-ID: <20110817195353.9FDFD2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 14:53:53 2011
New Revision: 137856

URL: http://llvm.org/viewvc/llvm-project?rev=137856&view=rev
Log:
Tidy up.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=137856&r1=137855&r2=137856&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Aug 17 14:53:53 2011
@@ -264,8 +264,7 @@
       if (NeedPred)
         MIB = AddDefaultPred(MIB);
       MIB.setMIFlags(MIFlags);
-    }
-    else {
+    } else {
       bool isKill = BaseReg != ARM::SP;
       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
       if (NeedCC)



From grosbach at apple.com  Wed Aug 17 14:55:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 19:55:51 -0000
Subject: [llvm-commits] [llvm] r137857 -
	/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
Message-ID: <20110817195551.B10962A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 14:55:51 2011
New Revision: 137857

URL: http://llvm.org/viewvc/llvm-project?rev=137857&view=rev
Log:
80 columns.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=137857&r1=137856&r2=137857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Aug 17 14:55:51 2011
@@ -240,7 +240,8 @@
       Bytes -= ThisVal;
       const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
       const MachineInstrBuilder MIB =
-        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags));
+        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
+                         .setMIFlags(MIFlags));
       AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
     } else {
       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)



From dpatel at apple.com  Wed Aug 17 14:56:53 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 12:56:53 -0700
Subject: [llvm-commits] [llvm] r137845 -
 /llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
In-Reply-To: <9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>
References: <20110817183844.A7EC92A6C12D@llvm.org>
	<9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>
Message-ID: <B9EA6510-F86B-48D5-8CEC-8DFBAE382DDC@apple.com>


On Aug 17, 2011, at 12:39 PM, Eric Christopher wrote:

> 
> On Aug 17, 2011, at 11:38 AM, Devang Patel wrote:
> 
>> Author: dpatel
>> Date: Wed Aug 17 13:38:44 2011
>> New Revision: 137845
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137845&view=rev
>> Log:
>> Robustify test.
>> 
>> Modified:
>>   llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
>> 
>> Modified: llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-02-17-DbgArtificialArg.cpp?rev=137845&r1=137844&r2=137845&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (original)
>> +++ llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp Wed Aug 17 13:38:44 2011
>> @@ -1,5 +1,4 @@
>> -// RUN: %llvmgcc -g -S %s -o - | FileCheck %s
>> -// Here, second to last argument "i32 64" indicates that artificial type is set.                                               
>> +// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o - | %llc -asm-verbose | FileCheck %s
>> // Test to artificial attribute attahed to "this" pointer type.
>> // Radar 7655792 and 7655002
>> 
>> @@ -10,7 +9,12 @@
>> 
>> int foo() {
>>  A a;
>> -  // Matching "i32 64, metadata !<number>} ; [ DW_TAG_pointer_type ]"
>> -  // CHECK: i32 64, metadata {{![0-9]+\} ; \[ DW_TAG_pointer_type \]}}
>> +//CHECK:        .ascii   "this"                 ## DW_AT_name
>> +//CHECK-NEXT:        .byte   0
>> +//CHECK-NEXT:        ## DW_AT_decl_file
>> +//CHECK-NEXT:        ## DW_AT_decl_line
>> +//CHECK-NEXT:        ## DW_AT_type
>> +//CHECK-NEXT:        ## DW_AT_artificial
>> +
>>  return a.fn1(1);
>> }
>> 
> 
> What, in particular, are you trying to test with this test? I.e. can you break it up into backend portions when you already have the front end emitting what you want and test the front end separately to make sure it's emitting what you want?
> 
> I say this because I'm getting rid of all these tests and a run line this complicated puts it at the top of my "delete this test" line instead of the "try to figure out how to migrate this test" line.
> 

The test was originally written for a FE bug fix. Checking an metadata element value to be non-zero is fragile when metadata node structure changes. However, checking output assembly ensures that "this" is marked artificial.

-
Devang

From echristo at apple.com  Wed Aug 17 14:58:28 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 17 Aug 2011 12:58:28 -0700
Subject: [llvm-commits] [llvm] r137845 -
 /llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
In-Reply-To: <B9EA6510-F86B-48D5-8CEC-8DFBAE382DDC@apple.com>
References: <20110817183844.A7EC92A6C12D@llvm.org>
	<9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>
	<B9EA6510-F86B-48D5-8CEC-8DFBAE382DDC@apple.com>
Message-ID: <3AFE7D3D-FE66-4ED6-8D65-70EACFBEB316@apple.com>

> 
> The test was originally written for a FE bug fix. Checking an metadata element value to be non-zero is fragile when metadata node structure changes. However, checking output assembly ensures that "this" is marked artificial.

? That totally doesn't answer the question though :)

I can't see any reason why you'd need to have this go through the entire compile sequence for a test. How about this: what patch was this change testing?

-eric

From dpatel at apple.com  Wed Aug 17 15:07:00 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 13:07:00 -0700
Subject: [llvm-commits] [llvm] r137845 -
 /llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
In-Reply-To: <3AFE7D3D-FE66-4ED6-8D65-70EACFBEB316@apple.com>
References: <20110817183844.A7EC92A6C12D@llvm.org>
	<9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>
	<B9EA6510-F86B-48D5-8CEC-8DFBAE382DDC@apple.com>
	<3AFE7D3D-FE66-4ED6-8D65-70EACFBEB316@apple.com>
Message-ID: <85F25390-1DB0-4179-B6CB-F976CAE5727A@apple.com>


On Aug 17, 2011, at 12:58 PM, Eric Christopher wrote:

> How about this: what patch was this change testing?

I answered, what is the original intent of the test (also included as a comment in test case from day one). Today, I noticed that .ll printed by llvm-gcc is not including  metadata tags (e.g. "DW_TAG_pointer_type") in comments. Since the is meant to check is "artificial" bit on the debug info I updated it to check final .s output.

-
Devang

From echristo at apple.com  Wed Aug 17 15:17:05 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 17 Aug 2011 13:17:05 -0700
Subject: [llvm-commits] [llvm] r137845 -
 /llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
In-Reply-To: <85F25390-1DB0-4179-B6CB-F976CAE5727A@apple.com>
References: <20110817183844.A7EC92A6C12D@llvm.org>
	<9E6E1333-29A9-4374-855A-F775A5347A4D@apple.com>
	<B9EA6510-F86B-48D5-8CEC-8DFBAE382DDC@apple.com>
	<3AFE7D3D-FE66-4ED6-8D65-70EACFBEB316@apple.com>
	<85F25390-1DB0-4179-B6CB-F976CAE5727A@apple.com>
Message-ID: <18EE7B02-C879-48F1-8D92-86F2F766D74E@apple.com>


On Aug 17, 2011, at 1:07 PM, Devang Patel wrote:

> 
> On Aug 17, 2011, at 12:58 PM, Eric Christopher wrote:
> 
>> How about this: what patch was this change testing?
> 
> I answered, what is the original intent of the test (also included as a comment in test case from day one). Today, I noticed that .ll printed by llvm-gcc is not including  metadata tags (e.g. "DW_TAG_pointer_type") in comments. Since the is meant to check is "artificial" bit on the debug info I updated it to check final .s output.

So the original intent of the test is to test that the output of the compiler is correct for metadata tags. Can you add the comment then in llvm-gcc as opposed to testing a set of things that doesn't make sense for a frontend test as well as splitting it out into a separate backend test to test that the artificial bit on the debug info is set with the output that you're expecting from the front end? That way it's tested in both places, but separately as more of a unit test.

-eric

From wendling at apple.com  Wed Aug 17 15:32:38 2011
From: wendling at apple.com (Bill Wendling)
Date: Wed, 17 Aug 2011 13:32:38 -0700
Subject: [llvm-commits] [llvm] r137642 -
 /llvm/trunk/lib/Transforms/Utils/Local.cpp
In-Reply-To: <4E4C1BB8.6010008@free.fr>
References: <20110815201051.736AD2A6C12C@llvm.org> <4E4A11E2.3080905@free.fr>
	<3B26CDC7-65F1-4056-9B81-BAD410B5C8A9@apple.com>
	<4E4AB60D.2090707@free.fr>
	<E017F34A-06C7-4B10-9157-B2DC3186DD8D@apple.com>
	<CCE345B7-00F2-4242-83FC-EB910D1D105C@apple.com>
	<E4C3B135-C7D4-43DB-81C2-94D03CDFA287@apple.com>
	<3662CABE-D544-4DBF-A000-DF50662BAEB9@apple.com>
	<4E4C1BB8.6010008@free.fr>
Message-ID: <A9E120D3-43BC-4CAC-9392-9CDC87466805@apple.com>

On Aug 17, 2011, at 12:51 PM, Duncan Sands wrote:

> Hi Bill, after thinking about this some more I'm starting to agree with John.
> It is true that if you invoke a function that throws in a loop, then each
> time the landing pad returns a different exception.  But that is because the
> called function F is allocating a different exception each time.  Thus F is
> not a readonly function :)  However you can imagine a situation in which
> exception data has been preallocated, and a readonly function F throws the
> same exception each time it is called.  Then the landing pad would return the
> same exception each time [*].  In short, it is not the landing pad that is
> reading/writing memory, it is the called function.  Indeed the exception
> mechanism can be seen as just an alternative way of returning from the function.
> Then the landing pad instruction is just like a way of talking about the
> returned result, and thus doesn't really do anything (this is vaguely analogous
> to a phi node :)), let alone read or write memory.
> 
Well, the functions say *may* read or write memory, not that they necessarily do. :)

> For example, suppose F can be hoisted out of a loop (eg: because it is readonly
> and the loop logic can prove it must execute the same every time).  Then the
> landing pad instruction should be hoistable too.  So I'm thinking that stopping
> the loop optimizers doing things to landing pad instructions (beyond getting
> them to preserve the landing pad invariants) is wrong in general.
> 
In this case, once the invoke to F is out of the loop, it's unwind edge will be also, and so will the 'landingpad' instruction.

But let's back up for a second. There's an obvious disparity between what I think of as the semantics of this instruction and what John and you think of as the semantics. As I explained earlier, to me it's meant to embody all of the actions that took place in the "no man's land" between the invoke and it's landing pad. I think of it this way because I want to try to capture in the CFG something which is not easy to capture at all: non-local behavior. Or as you put it an alternative way of returning from the function.

>From what I've been able to gather, you and John are looking at this instruction as *only* an instruction, which happens to be associated with the events that took place on the abnormal edge, but which doesn't embody those actions. Is that a fair assessment?

-bw


From grosbach at apple.com  Wed Aug 17 15:35:57 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 20:35:57 -0000
Subject: [llvm-commits] [llvm] r137861 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817203557.77D8E2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 15:35:57 2011
New Revision: 137861

URL: http://llvm.org/viewvc/llvm-project?rev=137861&view=rev
Log:
Add a couple of FIXMEs.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137861&r1=137860&r2=137861&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 15:35:57 2011
@@ -39,3 +39,11 @@
 
 @ CHECK: adds	r1, r2, r3              @ encoding: [0xd1,0x18]
 @ CHECK: add	r2, r8                  @ encoding: [0x42,0x44]
+
+
+ at ------------------------------------------------------------------------------
+@ FIXME: ADD (SP plus immediate)
+ at ------------------------------------------------------------------------------
+ at ------------------------------------------------------------------------------
+@ FIXME: ADD (SP plus register)
+ at ------------------------------------------------------------------------------



From isanbard at gmail.com  Wed Aug 17 15:36:44 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 20:36:44 -0000
Subject: [llvm-commits] [llvm] r137863 - in /llvm/trunk/lib:
 Analysis/LoopInfo.cpp Transforms/InstCombine/InstructionCombining.cpp
 VMCore/Instruction.cpp
Message-ID: <20110817203644.8FBD32A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 15:36:44 2011
New Revision: 137863

URL: http://llvm.org/viewvc/llvm-project?rev=137863&view=rev
Log:
Revert r137655. There is some question about whether the 'landingpad'
instruction should be marked as potentially reading and/or writing memory.

Modified:
    llvm/trunk/lib/Analysis/LoopInfo.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
    llvm/trunk/lib/VMCore/Instruction.cpp

Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=137863&r1=137862&r2=137863&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopInfo.cpp Wed Aug 17 15:36:44 2011
@@ -99,6 +99,9 @@
     return false;
   if (I->mayReadFromMemory())
     return false;
+  // The landingpad instruction is immobile.
+  if (isa<LandingPadInst>(I))
+    return false;
   // Determine the insertion point, unless one was given.
   if (!InsertPt) {
     BasicBlock *Preheader = getLoopPreheader();

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=137863&r1=137862&r2=137863&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Wed Aug 17 15:36:44 2011
@@ -1418,7 +1418,8 @@
   assert(I->hasOneUse() && "Invariants didn't hold!");
 
   // Cannot move control-flow-involving, volatile loads, vaarg, etc.
-  if (isa<PHINode>(I) || I->mayHaveSideEffects() || isa<TerminatorInst>(I))
+  if (isa<PHINode>(I) || isa<LandingPadInst>(I) || I->mayHaveSideEffects() ||
+      isa<TerminatorInst>(I))
     return false;
 
   // Do not sink alloca instructions out of the entry block.

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=137863&r1=137862&r2=137863&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Wed Aug 17 15:36:44 2011
@@ -320,7 +320,6 @@
   case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
-  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->doesNotAccessMemory();
@@ -341,7 +340,6 @@
   case Instruction::VAArg:
   case Instruction::AtomicCmpXchg:
   case Instruction::AtomicRMW:
-  case Instruction::LandingPad:
     return true;
   case Instruction::Call:
     return !cast<CallInst>(this)->onlyReadsMemory();



From grosbach at apple.com  Wed Aug 17 15:37:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 20:37:40 -0000
Subject: [llvm-commits] [llvm] r137864 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/select.ll
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817203740.C14B42A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 15:37:40 2011
New Revision: 137864

URL: http://llvm.org/viewvc/llvm-project?rev=137864&view=rev
Log:
Thumb assembly parsing and encoding for ADR.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/CodeGen/ARM/select.ll
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137864&r1=137863&r2=137864&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 17 15:37:40 2011
@@ -1189,7 +1189,7 @@
 // assembler.
 
 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
-               IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
+               IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
                T1Encoding<{1,0,1,0,0,?}> {
   bits<3> Rd;
   bits<8> addr;

Modified: llvm/trunk/test/CodeGen/ARM/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=137864&r1=137863&r2=137864&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select.ll Wed Aug 17 15:37:40 2011
@@ -81,7 +81,7 @@
 ; CHECK-NEON-NEXT: cmp    r0, [[REGISTER_1]]
 ; CHECK-NEON-NEXT: it     eq
 ; CHECK-NEON-NEXT: moveq  [[REGISTER_2]], #4
-; CHECK-NEON-NEXT: adr    [[REGISTER_3:r[0-9]+]], #LCPI
+; CHECK-NEON-NEXT: adr    [[REGISTER_3:r[0-9]+]], LCPI
 ; CHECK-NEON-NEXT: ldr
 ; CHECK-NEON:      bx
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137864&r1=137863&r2=137864&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 15:37:40 2011
@@ -47,3 +47,12 @@
 @------------------------------------------------------------------------------
 @ FIXME: ADD (SP plus register)
 @------------------------------------------------------------------------------
+
+
+ at ------------------------------------------------------------------------------
+@ ADR
+ at ------------------------------------------------------------------------------
+        adr r2, _baz
+
+@ CHECK: adr	r2, _baz                @ encoding: [A,0xa2]
+            @   fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10



From ahatanak at gmail.com  Wed Aug 17 15:54:02 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 13:54:02 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
Message-ID: <CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>

Please see the attached patch.

I couldn't find a way to have pos and size appear in the right hand
side as you suggested, but tblgen produces the correct binding.
Is this what you had in mind?

On Wed, Aug 17, 2011 at 11:08 AM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> Hi,
>
>> Encoding of instruction "ext $dst, $src, $pos, $size" looks like this:
>>
>> field31-26, field25-21, field20-16, field15-11, field10-6, field5-0
>> 31, ? ? ? ? ? $src, ? ? ? ? ?$dst, ? ? ? ? $size, ? ? ? $pos, ? ? ? 0
>>
>> The FR format binds the operands in the following order,
>> (rd:field15-11), (rs:field25-21), (rt:field20-16), (shamt:field10-6)
>>
>> so if I want to use the FR format to define "ext $dst, $src, $pos,
>> $size", the operands need to be given in the following order:
>>
>> $size, $src, $dst, $pos
>>
>> Is it possible to do so? In the format of FR, (dag outs) appears
>> before (dag ins).
>
> The format FR doesn't specify any constraints about the dags outs and
> ins, but only with the encoding. In your ExtIns class which will
> inherit from FR, you can assign the new encoding as for example:
>
> let shamt = pos
> let rd = size
> ...
>
> One more thing, please use $rs and $rt directly, instead of $src and
> $dst, this is actually what we should in all places.
> Thanks
>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>
-------------- next part --------------
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From grosbach at apple.com  Wed Aug 17 16:01:11 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 21:01:11 -0000
Subject: [llvm-commits] [llvm] r137865 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20110817210111.538C52A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 16:01:11 2011
New Revision: 137865

URL: http://llvm.org/viewvc/llvm-project?rev=137865&view=rev
Log:
Fix predicate for imm1_32

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137865&r1=137864&r2=137865&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Aug 17 16:01:11 2011
@@ -583,7 +583,10 @@
   return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
 }]>;
 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
-def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }],
+def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
+   uint64_t Imm = N->getZExtValue();
+   return Imm > 0 && Imm <= 32;
+ }],
     imm1_32_XFORM> {
   let PrintMethod = "printImmPlusOneOperand";
   let ParserMatchClass = Imm1_32AsmOperand;



From isanbard at gmail.com  Wed Aug 17 16:04:05 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:04:05 -0000
Subject: [llvm-commits] [llvm] r137866 -
	/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
Message-ID: <20110817210405.C007C2A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:04:05 2011
New Revision: 137866

URL: http://llvm.org/viewvc/llvm-project?rev=137866&view=rev
Log:
Assert that we aren't trying to split the critical edge of a landing pad. Doing
so requires more care than this generic algorithm should handle.

Modified:
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=137866&r1=137865&r2=137866&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Wed Aug 17 16:04:05 2011
@@ -176,6 +176,11 @@
   BasicBlock *TIBB = TI->getParent();
   BasicBlock *DestBB = TI->getSuccessor(SuccNum);
 
+  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
+  // it in this generic function.
+  assert(!DestBB->isLandingPad() &&
+         "Cannot split critical edge to a landing pad block!");
+
   // Create a new basic block, linking it into the CFG.
   BasicBlock *NewBB = BasicBlock::Create(TI->getContext(),
                       TIBB->getName() + "." + DestBB->getName() + "_crit_edge");



From bruno.cardoso at gmail.com  Wed Aug 17 16:15:52 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 14:15:52 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
Message-ID: <CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>

Hi,

On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Please see the attached patch.
>
> I couldn't find a way to have pos and size appear in the right hand
> side as you suggested, but tblgen produces the correct binding.
> Is this what you had in mind?

No. I think you got the wrong idea. My suggestion is something like:

class ExtIns<bits<6> _funct, string instr_asm, dag ins,
             list<dag> pattern, InstrItinClass itin>:
  FR<...> {
  bits<5> pos;
  bits<5> size;
  bits<5> dst
  let rt = dst;
  let shamt = pos;
  let rd = size;
 ....
}

def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
                 [(set CPURegs:$rt,
                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
                 NoItinerary>;

This will automatically bind "pos" to "bits<5> pos", and so on.
Advantage? The encoding is done automatically, no need to right custom
encoding functions... Take a look at ARMInstrInfo.td for tons of
examples.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From isanbard at gmail.com  Wed Aug 17 16:20:43 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:20:43 -0000
Subject: [llvm-commits] [llvm] r137871 -
	/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
Message-ID: <20110817212043.E35392A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:20:43 2011
New Revision: 137871

URL: http://llvm.org/viewvc/llvm-project?rev=137871&view=rev
Log:
Don't optimize the landing pad exit block.

One way to exit the loop is through an unwind edge. However, that may involve
splitting the critical edge of the landing pad, which is non-trivial. Prevent
the transformation from rewriting the landing pad exit loop block.

Modified:
    llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=137871&r1=137870&r2=137871&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Wed Aug 17 16:20:43 2011
@@ -398,6 +398,9 @@
 /// blocks.  This method is used to split exit blocks that have predecessors
 /// outside of the loop.
 BasicBlock *LoopSimplify::RewriteLoopExitBlock(Loop *L, BasicBlock *Exit) {
+  // Don't split a landing pad block.
+  if (Exit->isLandingPad()) return 0;
+
   SmallVector<BasicBlock*, 8> LoopBlocks;
   for (pred_iterator I = pred_begin(Exit), E = pred_end(Exit); I != E; ++I) {
     BasicBlock *P = *I;
@@ -746,18 +749,29 @@
     (void)HasIndBrPred;
   }
 
-  // Indirectbr can interfere with exit block canonicalization.
+  // Indirectbr and LandingPad can interfere with exit block canonicalization.
   if (!L->hasDedicatedExits()) {
     bool HasIndBrExiting = false;
+    bool HasLPadExiting = false;
     SmallVector<BasicBlock*, 8> ExitingBlocks;
     L->getExitingBlocks(ExitingBlocks);
-    for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i)
+    for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) {
       if (isa<IndirectBrInst>((ExitingBlocks[i])->getTerminator())) {
         HasIndBrExiting = true;
         break;
       }
-    assert(HasIndBrExiting &&
+      if (const InvokeInst *II =
+          dyn_cast<InvokeInst>(ExitingBlocks[i]->getTerminator())) {
+        if (L->contains(II->getNormalDest()) &&
+            !L->contains(II->getUnwindDest())) {
+          HasLPadExiting = true;
+          break;
+        }
+      }
+    }
+
+    assert((HasIndBrExiting || HasLPadExiting) &&
            "LoopSimplify has no excuse for missing exit block info!");
-    (void)HasIndBrExiting;
+    (void)HasIndBrExiting; (void)HasLPadExiting;
   }
 }



From isanbard at gmail.com  Wed Aug 17 16:21:31 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:21:31 -0000
Subject: [llvm-commits] [llvm] r137872 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110817212131.E03942A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:21:31 2011
New Revision: 137872

URL: http://llvm.org/viewvc/llvm-project?rev=137872&view=rev
Log:
Increment the insertion iterator to beyond the landingpad instruction.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137872&r1=137871&r2=137872&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Wed Aug 17 16:21:31 2011
@@ -287,7 +287,7 @@
 ///
 BasicBlock *llvm::SplitBlock(BasicBlock *Old, Instruction *SplitPt, Pass *P) {
   BasicBlock::iterator SplitIt = SplitPt;
-  while (isa<PHINode>(SplitIt))
+  while (isa<PHINode>(SplitIt) || isa<LandingPadInst>(SplitIt))
     ++SplitIt;
   BasicBlock *New = Old->splitBasicBlock(SplitIt, Old->getName()+".split");
 



From isanbard at gmail.com  Wed Aug 17 16:25:14 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:25:14 -0000
Subject: [llvm-commits] [llvm] r137873 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20110817212514.DF8DD2A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:25:14 2011
New Revision: 137873

URL: http://llvm.org/viewvc/llvm-project?rev=137873&view=rev
Log:
Add the body of 'visitLandingPad'.

This generates the SDNodes for the new exception handling scheme. It takes the
two values coming from the landingpad instruction and assigns them to the
EXCEPTIONADDR and EHSELECTION nodes.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=137873&r1=137872&r2=137873&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Aug 17 16:25:14 2011
@@ -1814,6 +1814,45 @@
   llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
 }
 
+void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
+  assert(FuncInfo.MBB->isLandingPad() &&
+         "Call to landingpad not in landing pad!");
+
+  MachineBasicBlock *MBB = FuncInfo.MBB;
+  MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
+  AddLandingPadInfo(LP, MMI, MBB);
+
+  SmallVector<EVT, 2> ValueVTs;
+  ComputeValueVTs(TLI, LP.getType(), ValueVTs);
+
+  // Insert the EXCEPTIONADDR instruction.
+  assert(FuncInfo.MBB->isLandingPad() &&
+         "Call to eh.exception not in landing pad!");
+  SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+  SDValue Ops[2];
+  Ops[0] = DAG.getRoot();
+  SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
+  SDValue Chain = Op1.getValue(1);
+
+  // Insert the EHSELECTION instruction.
+  VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+  Ops[0] = Op1;
+  Ops[1] = Chain;
+  SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
+  Chain = Op2.getValue(1);
+  Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
+
+  Ops[0] = Op1;
+  Ops[1] = Op2;
+  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+                            DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
+                            &Ops[0], 2);
+
+  std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
+  setValue(&LP, RetPair.first);
+  DAG.setRoot(RetPair.second);
+}
+
 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
 /// small case ranges).
 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
@@ -2985,9 +3024,6 @@
                            &Values[0], NumValValues));
 }
 
-void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &I) {
-}
-
 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
   SDValue N = getValue(I.getOperand(0));
   Type *Ty = I.getOperand(0)->getType();



From isanbard at gmail.com  Wed Aug 17 16:28:05 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:28:05 -0000
Subject: [llvm-commits] [llvm] r137875 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20110817212805.6E5842A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:28:05 2011
New Revision: 137875

URL: http://llvm.org/viewvc/llvm-project?rev=137875&view=rev
Log:
Revert patch. Forgot a dependent commit.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=137875&r1=137874&r2=137875&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Aug 17 16:28:05 2011
@@ -1814,45 +1814,6 @@
   llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
 }
 
-void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
-  assert(FuncInfo.MBB->isLandingPad() &&
-         "Call to landingpad not in landing pad!");
-
-  MachineBasicBlock *MBB = FuncInfo.MBB;
-  MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
-  AddLandingPadInfo(LP, MMI, MBB);
-
-  SmallVector<EVT, 2> ValueVTs;
-  ComputeValueVTs(TLI, LP.getType(), ValueVTs);
-
-  // Insert the EXCEPTIONADDR instruction.
-  assert(FuncInfo.MBB->isLandingPad() &&
-         "Call to eh.exception not in landing pad!");
-  SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
-  SDValue Ops[2];
-  Ops[0] = DAG.getRoot();
-  SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
-  SDValue Chain = Op1.getValue(1);
-
-  // Insert the EHSELECTION instruction.
-  VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
-  Ops[0] = Op1;
-  Ops[1] = Chain;
-  SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
-  Chain = Op2.getValue(1);
-  Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
-
-  Ops[0] = Op1;
-  Ops[1] = Op2;
-  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
-                            DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
-                            &Ops[0], 2);
-
-  std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
-  setValue(&LP, RetPair.first);
-  DAG.setRoot(RetPair.second);
-}
-
 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
 /// small case ranges).
 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
@@ -3024,6 +2985,9 @@
                            &Values[0], NumValValues));
 }
 
+void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &I) {
+}
+
 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
   SDValue N = getValue(I.getOperand(0));
   Type *Ty = I.getOperand(0)->getType();



From grosbach at apple.com  Wed Aug 17 16:31:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 14:31:23 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
	<CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
Message-ID: <C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>


On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:

> Hi,
> 
> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>> Please see the attached patch.
>> 
>> I couldn't find a way to have pos and size appear in the right hand
>> side as you suggested, but tblgen produces the correct binding.
>> Is this what you had in mind?
> 
> No. I think you got the wrong idea. My suggestion is something like:
> 
> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>             list<dag> pattern, InstrItinClass itin>:
>  FR<...> {
>  bits<5> pos;
>  bits<5> size;
>  bits<5> dst
>  let rt = dst;
>  let shamt = pos;
>  let rd = size;
> ....
> }
> 
> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>                 [(set CPURegs:$rt,
>                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>                 NoItinerary>;
> 
> This will automatically bind "pos" to "bits<5> pos", and so on.
> Advantage? The encoding is done automatically, no need to right custom
> encoding functions... Take a look at ARMInstrInfo.td for tons of
> examples.

+1

This is exactly right.

From isanbard at gmail.com  Wed Aug 17 16:32:02 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:32:02 -0000
Subject: [llvm-commits] [llvm] r137876 -
	/llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Message-ID: <20110817213202.A5B3D2A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:32:02 2011
New Revision: 137876

URL: http://llvm.org/viewvc/llvm-project?rev=137876&view=rev
Log:
Disable PRE for landing pads.

PRE needs the landing pads to have their critical edges split. Doing this for a
landing pad is non-trivial. Abandon the attempt to perform PRE when we come
across a landing pad. (Reviewed by Owen!)

Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=137876&r1=137875&r2=137876&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Aug 17 16:32:02 2011
@@ -1446,8 +1446,8 @@
   for (unsigned i = 0, e = UnavailableBlocks.size(); i != e; ++i)
     Blockers.insert(UnavailableBlocks[i]);
 
-  // Lets find first basic block with more than one predecessor.  Walk backwards
-  // through predecessors if needed.
+  // Let's find the first basic block with more than one predecessor.  Walk
+  // backwards through predecessors if needed.
   BasicBlock *LoadBB = LI->getParent();
   BasicBlock *TmpBB = LoadBB;
 
@@ -1519,10 +1519,19 @@
               << Pred->getName() << "': " << *LI << '\n');
         return false;
       }
+
+      if (LoadBB->isLandingPad()) {
+        DEBUG(dbgs()
+              << "COULD NOT PRE LOAD BECAUSE OF LANDING PAD CRITICAL EDGE '"
+              << Pred->getName() << "': " << *LI << '\n');
+        return false;
+      }
+
       unsigned SuccNum = GetSuccessorNumber(Pred, LoadBB);
       NeedToSplit.push_back(std::make_pair(Pred->getTerminator(), SuccNum));
     }
   }
+
   if (!NeedToSplit.empty()) {
     toSplit.append(NeedToSplit.begin(), NeedToSplit.end());
     return false;
@@ -2071,6 +2080,9 @@
     // Nothing to PRE in the entry block.
     if (CurrentBlock == &F.getEntryBlock()) continue;
 
+    // Don't perform PRE on a landing pad.
+    if (CurrentBlock->isLandingPad()) continue;
+
     for (BasicBlock::iterator BI = CurrentBlock->begin(),
          BE = CurrentBlock->end(); BI != BE; ) {
       Instruction *CurInst = BI++;



From ahatanak at gmail.com  Wed Aug 17 16:44:14 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 14:44:14 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
	<CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
	<C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>
Message-ID: <CAB297QykqZZ8a8mBo4eWj2wm_8-jQT++SgAiTqtfS-wR7dxStw@mail.gmail.com>

Is this okay?

On Wed, Aug 17, 2011 at 2:31 PM, Jim Grosbach <grosbach at apple.com> wrote:
>
> On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:
>
>> Hi,
>>
>> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>> Please see the attached patch.
>>>
>>> I couldn't find a way to have pos and size appear in the right hand
>>> side as you suggested, but tblgen produces the correct binding.
>>> Is this what you had in mind?
>>
>> No. I think you got the wrong idea. My suggestion is something like:
>>
>> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>> ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>> ?FR<...> {
>> ?bits<5> pos;
>> ?bits<5> size;
>> ?bits<5> dst
>> ?let rt = dst;
>> ?let shamt = pos;
>> ?let rd = size;
>> ....
>> }
>>
>> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>> ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>> ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>> ? ? ? ? ? ? ? ? NoItinerary>;
>>
>> This will automatically bind "pos" to "bits<5> pos", and so on.
>> Advantage? The encoding is done automatically, no need to right custom
>> encoding functions... Take a look at ARMInstrInfo.td for tons of
>> examples.
>
> +1
>
> This is exactly right.
>
-------------- next part --------------
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From bruno.cardoso at gmail.com  Wed Aug 17 16:51:14 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 14:51:14 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CAB297QykqZZ8a8mBo4eWj2wm_8-jQT++SgAiTqtfS-wR7dxStw@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
	<CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
	<C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>
	<CAB297QykqZZ8a8mBo4eWj2wm_8-jQT++SgAiTqtfS-wR7dxStw@mail.gmail.com>
Message-ID: <CACk9FxY38MQvAsNoeWjSM9ggLcdB5K65ncDGdswRV37h7AD_0Q@mail.gmail.com>

What about:

"CPURegs:$src1" ?

It doesn't seems to be encoded. Btw, I'm not following, what is this
operand about? It isn't part of the asm string! Can you explain?

On Wed, Aug 17, 2011 at 2:44 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Is this okay?
>
> On Wed, Aug 17, 2011 at 2:31 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>
>> On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:
>>
>>> Hi,
>>>
>>> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>>> Please see the attached patch.
>>>>
>>>> I couldn't find a way to have pos and size appear in the right hand
>>>> side as you suggested, but tblgen produces the correct binding.
>>>> Is this what you had in mind?
>>>
>>> No. I think you got the wrong idea. My suggestion is something like:
>>>
>>> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>>> ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>>> ?FR<...> {
>>> ?bits<5> pos;
>>> ?bits<5> size;
>>> ?bits<5> dst
>>> ?let rt = dst;
>>> ?let shamt = pos;
>>> ?let rd = size;
>>> ....
>>> }
>>>
>>> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>>> ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>>> ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>>> ? ? ? ? ? ? ? ? NoItinerary>;
>>>
>>> This will automatically bind "pos" to "bits<5> pos", and so on.
>>> Advantage? The encoding is done automatically, no need to right custom
>>> encoding functions... Take a look at ARMInstrInfo.td for tons of
>>> examples.
>>
>> +1
>>
>> This is exactly right.
>>
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From grosbach at apple.com  Wed Aug 17 16:51:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 21:51:27 -0000
Subject: [llvm-commits] [llvm] r137879 - in /llvm/trunk/lib/Target/ARM:
 ARMCodeEmitter.cpp ARMInstrThumb.td ARMInstrThumb2.td
 AsmParser/ARMAsmParser.cpp Disassembler/ARMDisassembler.cpp
 InstPrinter/ARMInstPrinter.cpp InstPrinter/ARMInstPrinter.h
 MCTargetDesc/ARMMCCodeEmitter.cpp
Message-ID: <20110817215128.1A19A2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 16:51:27 2011
New Revision: 137879

URL: http://llvm.org/viewvc/llvm-project?rev=137879&view=rev
Log:
ARM clean up the imm_sr operand class representation.

Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Aug 17 16:51:27 2011
@@ -236,8 +236,6 @@
       const {return 0; }
     uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
       const { return 0; }
-    unsigned getThumbSRImmOpValue(const MachineInstr &MI, unsigned OpIdx)
-      const { return 0; }
 
     unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
       const {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 17 16:51:27 2011
@@ -19,11 +19,17 @@
                       [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                        SDNPVariadic]>;
 
-def imm_sr : Operand<i32>, ImmLeaf<i32, [{
+def imm_sr_XFORM: SDNodeXForm<imm, [{
+  unsigned Imm = N->getZExtValue();
+  return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
+}]>;
+def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
+def imm_sr : Operand<i32>, PatLeaf<(imm), [{
+  uint64_t Imm = N->getZExtValue();
   return Imm > 0 && Imm <= 32;
-}]> {
-  let EncoderMethod = "getThumbSRImmOpValue";
-  let DecoderMethod = "DecodeThumbSRImm";
+}], imm_sr_XFORM> {
+  let PrintMethod = "printThumbSRImm";
+  let ParserMatchClass = ThumbSRImmAsmOperand;
 }
 
 def imm_neg_XFORM : SDNodeXForm<imm, [{

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 17 16:51:27 2011
@@ -771,7 +771,7 @@
    def ri : T2sTwoRegShiftImm<
                  (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
                  opc, ".w\t$Rd, $Rm, $imm",
-                 [(set rGPR:$Rd, (opnode rGPR:$Rm, ty:$imm))]> {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-21} = 0b010010;
      let Inst{19-16} = 0b1111; // Rn

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 16:51:27 2011
@@ -482,6 +482,14 @@
     int64_t Value = CE->getValue();
     return Value >= 0 && Value <= 0xffffff;
   }
+  bool isImmThumbSR() const {
+    if (Kind != Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value > 0 && Value < 33;
+  }
   bool isPKHLSLImm() const {
     if (Kind != Immediate)
       return false;
@@ -794,6 +802,15 @@
     addExpr(Inst, getImm());
   }
 
+  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The constant encodes as the immediate, except for 32, which encodes as
+    // zero.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Imm = CE->getValue();
+    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
+  }
+
   void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 16:51:27 2011
@@ -210,8 +210,6 @@
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
-                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
@@ -2474,15 +2472,6 @@
   return Success;
 }
 
-static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
-                             uint64_t Address, const void *Decoder) {
-  if (Val == 0)
-    Inst.addOperand(MCOperand::CreateImm(32));
-  else
-    Inst.addOperand(MCOperand::CreateImm(Val));
-  return Success;
-}
-
 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
                                        uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Aug 17 16:51:27 2011
@@ -639,7 +639,13 @@
 
 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
                                             raw_ostream &O) {
-  O << "#" <<  MI->getOperand(OpNum).getImm() * 4;
+  O << "#" << MI->getOperand(OpNum).getImm() * 4;
+}
+
+void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
+                                     raw_ostream &O) {
+  unsigned Imm = MI->getOperand(OpNum).getImm();
+  O << "#" << (Imm == 0 ? 32 : Imm);
 }
 
 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Aug 17 16:51:27 2011
@@ -74,6 +74,7 @@
   void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 
   void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
                                    raw_ostream &O);

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=137879&r1=137878&r2=137879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Aug 17 16:51:27 2011
@@ -443,16 +443,6 @@
   return isAdd;
 }
 
-uint32_t ARMMCCodeEmitter::
-getThumbSRImmOpValue(const MCInst &MI, unsigned OpIdx,
-                        SmallVectorImpl<MCFixup> &Fixups) const {
-  const MCOperand &MO = MI.getOperand(OpIdx);
-  assert(MO.isImm() && "Expected constant shift!");
-  int val = MO.getImm();
-  return (val == 32) ? 0 : val;
-}
-
-
 /// getBranchTargetOpValue - Helper function to get the branch target operand,
 /// which is either an immediate or requires a fixup.
 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,



From ahatanak at gmail.com  Wed Aug 17 16:56:27 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 14:56:27 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CACk9FxY38MQvAsNoeWjSM9ggLcdB5K65ncDGdswRV37h7AD_0Q@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
	<CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
	<C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>
	<CAB297QykqZZ8a8mBo4eWj2wm_8-jQT++SgAiTqtfS-wR7dxStw@mail.gmail.com>
	<CACk9FxY38MQvAsNoeWjSM9ggLcdB5K65ncDGdswRV37h7AD_0Q@mail.gmail.com>
Message-ID: <CAB297QxzCjYZUxErSW_YWQLiMO2wJdyptM6gxoTm-vgBsGpNpA@mail.gmail.com>

$src1 is supposed to be tied to destination $rt. I just realized I
coded this incorrectly in the definition of INS. It should be like
this:
let Constraints = "$src1 = $rt" in

INS inserts part of $rs to $rt (or $src1), so $rt is both a source and
destination.

On Wed, Aug 17, 2011 at 2:51 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> What about:
>
> "CPURegs:$src1" ?
>
> It doesn't seems to be encoded. Btw, I'm not following, what is this
> operand about? It isn't part of the asm string! Can you explain?
>
> On Wed, Aug 17, 2011 at 2:44 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>> Is this okay?
>>
>> On Wed, Aug 17, 2011 at 2:31 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>>
>>> On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:
>>>
>>>> Hi,
>>>>
>>>> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>>>> Please see the attached patch.
>>>>>
>>>>> I couldn't find a way to have pos and size appear in the right hand
>>>>> side as you suggested, but tblgen produces the correct binding.
>>>>> Is this what you had in mind?
>>>>
>>>> No. I think you got the wrong idea. My suggestion is something like:
>>>>
>>>> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>>>> ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>>>> ?FR<...> {
>>>> ?bits<5> pos;
>>>> ?bits<5> size;
>>>> ?bits<5> dst
>>>> ?let rt = dst;
>>>> ?let shamt = pos;
>>>> ?let rd = size;
>>>> ....
>>>> }
>>>>
>>>> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>>>> ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>>>> ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>>>> ? ? ? ? ? ? ? ? NoItinerary>;
>>>>
>>>> This will automatically bind "pos" to "bits<5> pos", and so on.
>>>> Advantage? The encoding is done automatically, no need to right custom
>>>> encoding functions... Take a look at ARMInstrInfo.td for tons of
>>>> examples.
>>>
>>> +1
>>>
>>> This is exactly right.
>>>
>>
>
>
>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>


From isanbard at gmail.com  Wed Aug 17 16:56:44 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 17 Aug 2011 21:56:44 -0000
Subject: [llvm-commits] [llvm] r137880 - in /llvm/trunk:
 include/llvm/CodeGen/FunctionLoweringInfo.h
 lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20110817215644.EBDF22A6C12C@llvm.org>

Author: void
Date: Wed Aug 17 16:56:44 2011
New Revision: 137880

URL: http://llvm.org/viewvc/llvm-project?rev=137880&view=rev
Log:
Add the support in code-gen for the landingpad instruction lowering.

The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION
SDNodes. The information from the landingpad instruction is harvested by the
'AddLandingPadInfo' function. The new EH uses the current EH scheme in the
back-end. This will change once we switch over to the new scheme. (Reviewed by
Jakob!)

Modified:
    llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=137880&r1=137879&r2=137880&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Wed Aug 17 16:56:44 2011
@@ -221,6 +221,11 @@
 void CopyCatchInfo(const BasicBlock *SuccBB, const BasicBlock *LPad,
                    MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
 
+/// AddLandingPadInfo - Extract the exception handling information from the
+/// landingpad instruction and add them to the specified machine module info.
+void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
+                       MachineBasicBlock *MBB);
+
 } // end namespace llvm
 
 #endif

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=137880&r1=137879&r2=137880&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Aug 17 16:56:44 2011
@@ -454,3 +454,34 @@
       break;
   }
 }
+
+/// AddLandingPadInfo - Extract the exception handling information from the
+/// landingpad instruction and add them to the specified machine module info.
+void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
+                             MachineBasicBlock *MBB) {
+  MMI.addPersonality(MBB,
+                     cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
+
+  if (I.isCleanup())
+    MMI.addCleanup(MBB);
+
+  // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
+  //        but we need to do it this way because of how the DWARF EH emitter
+  //        processes the clauses.
+  for (unsigned i = I.getNumClauses(); i != 0; --i) {
+    Value *Val = I.getClause(i - 1);
+    if (I.isCatch(i - 1)) {
+      MMI.addCatchTypeInfo(MBB,
+                           dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
+    } else {
+      // Add filters in a list.
+      Constant *CVal = cast<Constant>(Val);
+      SmallVector<const GlobalVariable*, 4> FilterList;
+      for (User::op_iterator
+             II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
+        FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
+
+      MMI.addFilterTypeInfo(MBB, FilterList);
+    }
+  }
+}

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=137880&r1=137879&r2=137880&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Aug 17 16:56:44 2011
@@ -1814,6 +1814,45 @@
   llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
 }
 
+void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
+  assert(FuncInfo.MBB->isLandingPad() &&
+         "Call to landingpad not in landing pad!");
+
+  MachineBasicBlock *MBB = FuncInfo.MBB;
+  MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
+  AddLandingPadInfo(LP, MMI, MBB);
+
+  SmallVector<EVT, 2> ValueVTs;
+  ComputeValueVTs(TLI, LP.getType(), ValueVTs);
+
+  // Insert the EXCEPTIONADDR instruction.
+  assert(FuncInfo.MBB->isLandingPad() &&
+         "Call to eh.exception not in landing pad!");
+  SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+  SDValue Ops[2];
+  Ops[0] = DAG.getRoot();
+  SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
+  SDValue Chain = Op1.getValue(1);
+
+  // Insert the EHSELECTION instruction.
+  VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+  Ops[0] = Op1;
+  Ops[1] = Chain;
+  SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
+  Chain = Op2.getValue(1);
+  Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
+
+  Ops[0] = Op1;
+  Ops[1] = Op2;
+  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
+                            DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
+                            &Ops[0], 2);
+
+  std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
+  setValue(&LP, RetPair.first);
+  DAG.setRoot(RetPair.second);
+}
+
 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
 /// small case ranges).
 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
@@ -2985,9 +3024,6 @@
                            &Values[0], NumValValues));
 }
 
-void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &I) {
-}
-
 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
   SDValue N = getValue(I.getOperand(0));
   Type *Ty = I.getOperand(0)->getType();



From grosbach at apple.com  Wed Aug 17 16:58:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 21:58:19 -0000
Subject: [llvm-commits] [llvm] r137881 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20110817215819.1DB892A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 16:58:18 2011
New Revision: 137881

URL: http://llvm.org/viewvc/llvm-project?rev=137881&view=rev
Log:
Tidy up. 80 columns.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137881&r1=137880&r2=137881&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 16:58:18 2011
@@ -41,8 +41,9 @@
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
+                                               unsigned RegNo, uint64_t Address,
+                                               const void *Decoder);
 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
@@ -55,8 +56,10 @@
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
+                                                unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder);
 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 
@@ -79,11 +82,13 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
+                                                  unsigned Insn,
+                                                  uint64_t Address,
+                                                  const void *Decoder);
 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
@@ -104,7 +109,7 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
@@ -122,7 +127,7 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
@@ -214,7 +219,7 @@
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
@@ -243,7 +248,8 @@
 
 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                              const MemoryObject &Region,
-                                             uint64_t Address,raw_ostream &os) const {
+                                             uint64_t Address,
+                                             raw_ostream &os) const {
   uint8_t bytes[4];
 
   // We want to read exactly 4 bytes of data.
@@ -419,7 +425,8 @@
 
 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                const MemoryObject &Region,
-                                               uint64_t Address,raw_ostream &os) const {
+                                               uint64_t Address,
+                                               raw_ostream &os) const {
   uint8_t bytes[4];
 
   // We want to read exactly 2 bytes of data.
@@ -577,8 +584,9 @@
   return Success;
 }
 
-static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                       uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+                           uint64_t Address, const void *Decoder) {
   if (RegNo == 15) return Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
@@ -626,7 +634,7 @@
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static const unsigned SPRDecoderTable[] = { 
+static const unsigned SPRDecoderTable[] = {
      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
@@ -647,7 +655,7 @@
   return Success;
 }
 
-static const unsigned DPRDecoderTable[] = { 
+static const unsigned DPRDecoderTable[] = {
      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
@@ -675,14 +683,15 @@
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                   uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+                            uint64_t Address, const void *Decoder) {
   if (RegNo > 15)
     return Fail;
   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static const unsigned QPRDecoderTable[] = { 
+static const unsigned QPRDecoderTable[] = {
      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
@@ -859,7 +868,7 @@
   // This operand encodes a mask of contiguous zeros between a specified MSB
   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
   // the mask of all bits LSB-and-lower, and then xor them to create
-  // the mask of that's all ones on [msb, lsb].  Finally we not it to 
+  // the mask of that's all ones on [msb, lsb].  Finally we not it to
   // create the final mask.
   unsigned msb = fieldFromInstruction32(Val, 5, 5);
   unsigned lsb = fieldFromInstruction32(Val, 0, 5);
@@ -984,8 +993,9 @@
   return S;
 }
 
-static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
+                              uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
@@ -1120,8 +1130,9 @@
   return S;
 }
 
-static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
-                                  uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
@@ -1392,8 +1403,9 @@
   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
 }
 
-static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
@@ -2053,8 +2065,9 @@
   return S;
 }
 
-static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
+                            uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
@@ -2472,8 +2485,9 @@
   return Success;
 }
 
-static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
-                                       uint64_t Address, const void *Decoder) {
+static DecodeStatus
+DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned pred = fieldFromInstruction32(Insn, 22, 4);
@@ -2543,8 +2557,9 @@
   return Success;
 }
 
-static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
-                                        uint64_t Address, const void *Decoder){
+static DecodeStatus
+DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
+                            uint64_t Address, const void *Decoder){
   Inst.addOperand(MCOperand::CreateImm(Val << 1));
   return Success;
 }
@@ -2583,7 +2598,7 @@
 }
 
 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
-                                          uint64_t Address, const void *Decoder) {
+                                        uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
   unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
@@ -2602,7 +2617,7 @@
 
 
 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
-                                          uint64_t Address, const void *Decoder) {
+                                         uint64_t Address, const void *Decoder){
   DecodeStatus S = Success;
 
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);



From Micah.Villmow at amd.com  Wed Aug 17 16:59:24 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 16:59:24 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE32CD@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>
	<CAJgxuaeQywnBVMtRsw-_nzj5cjCoevRamt-d5xcn-iNb=vm7Hg@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32CD@sausexmbp02.amd.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE3357@sausexmbp02.amd.com>

Here is a patch that is against TOT.

From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Wednesday, August 17, 2011 10:06 AM
To: Justin Holewinski
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch



From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:47 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:41 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: Justin Holewinski [mailto:justin.holewinski at gmail.com<mailto:justin.holewinski at gmail.com>]
Sent: Wednesday, August 17, 2011 9:32 AM

To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu> [mailto:llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu>] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:02 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:
Forgot to send to llvm-commits.

Is the entire AMDIL back-end coming to LLVM ToT?
[Villmow, Micah] Yes, it is going through internal code review now. However, it will be posted for LLVM 2.9
first as that is what we are building against internally. After that, when I get time as I'm pretty busy, I will
update it for TOT.

Awesome!

How will this integrate with the AMD APP SDK?  From what I understand, CAL (and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.  Is this going to somehow integrate with the AMD OpenCL implementation?
[Villmow, Micah] All I can say is that this is outside of the scope of the APP SDK. This is mainly to allow others to take advantage of targeting AMDIL from their own compilers and to see how
we implemented things using LLVM for a non-x86 like target.

So assuming I generate AMDIL using this back-end, then what?  How can I execute it on real AMD hardware?
[Villmow, Micah] One way is to create an OpenCL binary using the output of AMDIL and load it into OpenCL. Another approach is to write a small runtime shim that converts from a compilation unit containing multiple kernels into single kernel per compilation unit and then use the CAL API to generate a CAL binary.  Our first step is to get the source code out there, and then based on feedback see what the next step can be to make it more useful.




> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu>]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
> Subject: [LLVMdev] AMDIL Target Triple patch
>
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
>
> Micah

_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski

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From bruno.cardoso at gmail.com  Wed Aug 17 17:10:02 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 15:10:02 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <CAB297QxzCjYZUxErSW_YWQLiMO2wJdyptM6gxoTm-vgBsGpNpA@mail.gmail.com>
References: <20110817020542.79CAE2A6C12C@llvm.org>
	<CACk9Fxb8ZCntfsPkrXPRsMGPHq_mhwEJNge_cF40B3FBo9+nLA@mail.gmail.com>
	<CAB297QwQ=PsFuqaRV6_yAFZAJXQj-kJaZdwUo1m9-EdfYqQ+EA@mail.gmail.com>
	<CAB297Qy4djK+ubWEm2NJn6+GY9_zTmo8th8LCdM7u8-B5zNjoA@mail.gmail.com>
	<CACk9FxabfUNW2v6TM2ktEfdt7o9L2x+zR2TQaRNDpO8rvHy9Sg@mail.gmail.com>
	<CAB297Qxz7o0V2YCMqMaNUefA9v0cXXBPpFUSwjEFu5O+T5_QOw@mail.gmail.com>
	<CACk9FxZj2mujxCtFOzGfh8uea-BNX6999pXYY0b2F+MhRp3sEQ@mail.gmail.com>
	<C572DBA0-2E9F-4BE3-91A9-C9408CA0C097@apple.com>
	<CAB297QykqZZ8a8mBo4eWj2wm_8-jQT++SgAiTqtfS-wR7dxStw@mail.gmail.com>
	<CACk9FxY38MQvAsNoeWjSM9ggLcdB5K65ncDGdswRV37h7AD_0Q@mail.gmail.com>
	<CAB297QxzCjYZUxErSW_YWQLiMO2wJdyptM6gxoTm-vgBsGpNpA@mail.gmail.com>
Message-ID: <CACk9Fxboi+J73xN49fnaQcfqN-cv2Otu=STUfeYezMQA5ObXCA@mail.gmail.com>

Nice! Could you please just rename it "$src"? Just go ahead and
commit. Thanks for explanations!

On Wed, Aug 17, 2011 at 2:56 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> $src1 is supposed to be tied to destination $rt. I just realized I
> coded this incorrectly in the definition of INS. It should be like
> this:
> let Constraints = "$src1 = $rt" in
>
> INS inserts part of $rs to $rt (or $src1), so $rt is both a source and
> destination.
>
> On Wed, Aug 17, 2011 at 2:51 PM, Bruno Cardoso Lopes
> <bruno.cardoso at gmail.com> wrote:
>> What about:
>>
>> "CPURegs:$src1" ?
>>
>> It doesn't seems to be encoded. Btw, I'm not following, what is this
>> operand about? It isn't part of the asm string! Can you explain?
>>
>> On Wed, Aug 17, 2011 at 2:44 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>> Is this okay?
>>>
>>> On Wed, Aug 17, 2011 at 2:31 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>>>
>>>> On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>>>>> Please see the attached patch.
>>>>>>
>>>>>> I couldn't find a way to have pos and size appear in the right hand
>>>>>> side as you suggested, but tblgen produces the correct binding.
>>>>>> Is this what you had in mind?
>>>>>
>>>>> No. I think you got the wrong idea. My suggestion is something like:
>>>>>
>>>>> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>>>>> ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>>>>> ?FR<...> {
>>>>> ?bits<5> pos;
>>>>> ?bits<5> size;
>>>>> ?bits<5> dst
>>>>> ?let rt = dst;
>>>>> ?let shamt = pos;
>>>>> ?let rd = size;
>>>>> ....
>>>>> }
>>>>>
>>>>> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>>>>> ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>>>>> ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>>>>> ? ? ? ? ? ? ? ? NoItinerary>;
>>>>>
>>>>> This will automatically bind "pos" to "bits<5> pos", and so on.
>>>>> Advantage? The encoding is done automatically, no need to right custom
>>>>> encoding functions... Take a look at ARMInstrInfo.td for tons of
>>>>> examples.
>>>>
>>>> +1
>>>>
>>>> This is exactly right.
>>>>
>>>
>>
>>
>>
>> --
>> Bruno Cardoso Lopes
>> http://www.brunocardoso.cc
>>
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Wed Aug 17 17:12:20 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 22:12:20 -0000
Subject: [llvm-commits] [llvm] r137885 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shift.ll
Message-ID: <20110817221220.CEB632A6C12C@llvm.org>

Author: bruno
Date: Wed Aug 17 17:12:20 2011
New Revision: 137885

URL: http://llvm.org/viewvc/llvm-project?rev=137885&view=rev
Log:
Fix PR10688. Add support for spliting 256-bit vector shifts when the
shift amount is variable

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-shift.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137885&r1=137884&r2=137885&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 17 17:12:20 2011
@@ -9449,17 +9449,26 @@
                                      DAG, dl);
 
     // Recreate the shift amount vectors
-    SmallVector<SDValue, 4> Amt1Csts;
-    SmallVector<SDValue, 4> Amt2Csts;
-    for (int i = 0; i < NumElems/2; ++i)
-      Amt1Csts.push_back(Amt->getOperand(i));
-    for (int i = NumElems/2; i < NumElems; ++i)
-      Amt2Csts.push_back(Amt->getOperand(i));
-
-    SDValue Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
-                               &Amt1Csts[0], NumElems/2);
-    SDValue Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
-                               &Amt2Csts[0], NumElems/2);
+    SDValue Amt1, Amt2;
+    if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
+      // Constant shift amount
+      SmallVector<SDValue, 4> Amt1Csts;
+      SmallVector<SDValue, 4> Amt2Csts;
+      for (int i = 0; i < NumElems/2; ++i)
+        Amt1Csts.push_back(Amt->getOperand(i));
+      for (int i = NumElems/2; i < NumElems; ++i)
+        Amt2Csts.push_back(Amt->getOperand(i));
+
+      Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
+                                 &Amt1Csts[0], NumElems/2);
+      Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
+                                 &Amt2Csts[0], NumElems/2);
+    } else {
+      // Variable shift amount
+      Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
+      Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
+                                 DAG, dl);
+    }
 
     // Issue new vector shifts for the smaller types
     V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);

Modified: llvm/trunk/test/CodeGen/X86/avx-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shift.ll?rev=137885&r1=137884&r2=137885&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-shift.ll Wed Aug 17 17:12:20 2011
@@ -62,3 +62,14 @@
   ret <16 x i16> %s
 }
 
+;;; Support variable shifts
+; CHECK: _vshift08
+; CHECK: vextractf128 $1
+; CHECK: vpslld $23
+; CHECK: vextractf128 $1
+; CHECK: vpslld $23
+define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
+  %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
+  ret <8 x i32> %bitop
+}
+



From eli.friedman at gmail.com  Wed Aug 17 17:22:24 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 17 Aug 2011 22:22:24 -0000
Subject: [llvm-commits] [llvm] r137888 - in /llvm/trunk:
 lib/Transforms/Scalar/DeadStoreElimination.cpp
 lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/MemCpyOptimizer.cpp
 test/Transforms/DeadStoreElimination/atomic.ll
 test/Transforms/GVN/atomic.ll test/Transforms/MemCpyOpt/atomic.ll
Message-ID: <20110817222224.749CE2A6C12C@llvm.org>

Author: efriedma
Date: Wed Aug 17 17:22:24 2011
New Revision: 137888

URL: http://llvm.org/viewvc/llvm-project?rev=137888&view=rev
Log:
Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt).


Added:
    llvm/trunk/test/Transforms/DeadStoreElimination/atomic.ll
    llvm/trunk/test/Transforms/GVN/atomic.ll
    llvm/trunk/test/Transforms/MemCpyOpt/atomic.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=137888&r1=137887&r2=137888&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Wed Aug 17 17:22:24 2011
@@ -213,9 +213,9 @@
 /// isRemovable - If the value of this instruction and the memory it writes to
 /// is unused, may we delete this instruction?
 static bool isRemovable(Instruction *I) {
-  // Don't remove volatile stores.
+  // Don't remove volatile/atomic stores.
   if (StoreInst *SI = dyn_cast<StoreInst>(I))
-    return !SI->isVolatile();
+    return SI->isUnordered();
   
   IntrinsicInst *II = cast<IntrinsicInst>(I);
   switch (II->getIntrinsicID()) {
@@ -447,7 +447,7 @@
     if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
       if (LoadInst *DepLoad = dyn_cast<LoadInst>(InstDep.getInst())) {
         if (SI->getPointerOperand() == DepLoad->getPointerOperand() &&
-            SI->getOperand(0) == DepLoad && !SI->isVolatile()) {
+            SI->getOperand(0) == DepLoad && isRemovable(SI)) {
           DEBUG(dbgs() << "DSE: Remove Store Of Load from same pointer:\n  "
                        << "LOAD: " << *DepLoad << "\n  STORE: " << *SI << '\n');
           
@@ -670,6 +670,8 @@
     
     // If we encounter a use of the pointer, it is no longer considered dead
     if (LoadInst *L = dyn_cast<LoadInst>(BBI)) {
+      if (!L->isUnordered()) // Be conservative with atomic/volatile load
+        break;
       LoadedLoc = AA->getLocation(L);
     } else if (VAArgInst *V = dyn_cast<VAArgInst>(BBI)) {
       LoadedLoc = AA->getLocation(V);

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=137888&r1=137887&r2=137888&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Aug 17 17:22:24 2011
@@ -982,8 +982,8 @@
   unsigned SrcValSize = TD.getTypeStoreSize(SrcVal->getType());
   unsigned LoadSize = TD.getTypeStoreSize(LoadTy);
   if (Offset+LoadSize > SrcValSize) {
-    assert(!SrcVal->isVolatile() && "Cannot widen volatile load!");
-    assert(isa<IntegerType>(SrcVal->getType())&&"Can't widen non-integer load");
+    assert(SrcVal->isSimple() && "Cannot widen volatile/atomic load!");
+    assert(SrcVal->getType()->isIntegerTy() && "Can't widen non-integer load");
     // If we have a load/load clobber an DepLI can be widened to cover this
     // load, then we should widen it to the next power of 2 size big enough!
     unsigned NewLoadSize = Offset+LoadSize;
@@ -1669,7 +1669,7 @@
   if (!MD)
     return false;
 
-  if (L->isVolatile())
+  if (!L->isSimple())
     return false;
 
   if (L->use_empty()) {

Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=137888&r1=137887&r2=137888&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Wed Aug 17 17:22:24 2011
@@ -384,7 +384,7 @@
     
     if (StoreInst *NextStore = dyn_cast<StoreInst>(BI)) {
       // If this is a store, see if we can merge it in.
-      if (NextStore->isVolatile()) break;
+      if (!NextStore->isSimple()) break;
     
       // Check to see if this stored value is of the same byte-splattable value.
       if (ByteVal != isBytewiseValue(NextStore->getOperand(0)))
@@ -479,7 +479,7 @@
 
 
 bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator &BBI) {
-  if (SI->isVolatile()) return false;
+  if (!SI->isSimple()) return false;
   
   if (TD == 0) return false;
 
@@ -487,7 +487,7 @@
   // happen to be using a load-store pair to implement it, rather than
   // a memcpy.
   if (LoadInst *LI = dyn_cast<LoadInst>(SI->getOperand(0))) {
-    if (!LI->isVolatile() && LI->hasOneUse() &&
+    if (LI->isSimple() && LI->hasOneUse() &&
         LI->getParent() == SI->getParent()) {
       MemDepResult ldep = MD->getDependency(LI);
       CallInst *C = 0;

Added: llvm/trunk/test/Transforms/DeadStoreElimination/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/atomic.ll?rev=137888&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/DeadStoreElimination/atomic.ll (added)
+++ llvm/trunk/test/Transforms/DeadStoreElimination/atomic.ll Wed Aug 17 17:22:24 2011
@@ -0,0 +1,107 @@
+; RUN: opt -basicaa -dse -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+; Sanity tests for atomic stores.
+; Note that it turns out essentially every transformation DSE does is legal on
+; atomic ops, just some transformations are not allowed across them. 
+
+ at x = common global i32 0, align 4
+ at y = common global i32 0, align 4
+
+declare void @randomop(i32*)
+
+; DSE across unordered store (allowed)
+define void @test1()  nounwind uwtable ssp {
+; CHECK: test1
+; CHECK-NOT: store i32 0
+; CHECK: store i32 1
+entry:
+  store i32 0, i32* @x
+  store atomic i32 0, i32* @y unordered, align 4
+  store i32 1, i32* @x
+  ret void
+}
+
+; DSE across seq_cst load (allowed in theory; not implemented ATM)
+define i32 @test2()  nounwind uwtable ssp {
+; CHECK: test2
+; CHECK: store i32 0
+; CHECK: store i32 1
+entry:
+  store i32 0, i32* @x
+  %x = load atomic i32* @y seq_cst, align 4
+  store i32 1, i32* @x
+  ret i32 %x
+}
+
+; DSE across seq_cst store (store before atomic store must not be removed)
+define void @test3()  nounwind uwtable ssp {
+; CHECK: test3
+; CHECK: store i32
+; CHECK: store atomic i32 2
+entry:
+  store i32 0, i32* @x
+  store atomic i32 2, i32* @y seq_cst, align 4
+  store i32 1, i32* @x
+  ret void
+}
+
+; DSE remove unordered store (allowed)
+define void @test4()  nounwind uwtable ssp {
+; CHECK: test4
+; CHECK-NOT: store atomic
+; CHECK: store i32 1
+entry:
+  store atomic i32 0, i32* @x unordered, align 4
+  store i32 1, i32* @x
+  ret void
+}
+
+; DSE unordered store overwriting non-atomic store (allowed)
+define void @test5()  nounwind uwtable ssp {
+; CHECK: test5
+; CHECK: store atomic i32 1
+entry:
+  store i32 0, i32* @x
+  store atomic i32 1, i32* @x unordered, align 4
+  ret void
+}
+
+; DSE no-op unordered atomic store (allowed)
+define void @test6()  nounwind uwtable ssp {
+; CHECK: test6
+; CHECK-NOT: store
+; CHECK: ret void
+entry:
+  %x = load atomic i32* @x unordered, align 4
+  store atomic i32 %x, i32* @x unordered, align 4
+  ret void
+}
+
+; DSE seq_cst store (be conservative; DSE doesn't have infrastructure
+; to reason about atomic operations).
+define void @test7()  nounwind uwtable ssp {
+; CHECK: test7
+; CHECK: store atomic 
+entry:
+  %a = alloca i32
+  store atomic i32 0, i32* %a seq_cst, align 4
+  ret void
+}
+
+; DSE and seq_cst load (be conservative; DSE doesn't have infrastructure
+; to reason about atomic operations).
+define i32 @test8()  nounwind uwtable ssp {
+; CHECK: test8
+; CHECK: store
+; CHECK: load atomic 
+entry:
+  %a = alloca i32
+  call void @randomop(i32* %a)
+  store i32 0, i32* %a, align 4
+  %x = load atomic i32* @x seq_cst, align 4
+  ret i32 %x
+}
+

Added: llvm/trunk/test/Transforms/GVN/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/atomic.ll?rev=137888&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GVN/atomic.ll (added)
+++ llvm/trunk/test/Transforms/GVN/atomic.ll Wed Aug 17 17:22:24 2011
@@ -0,0 +1,80 @@
+; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+ at x = common global i32 0, align 4
+ at y = common global i32 0, align 4
+
+; GVN across unordered store (allowed)
+define i32 @test1() nounwind uwtable ssp {
+; CHECK: test1
+; CHECK: add i32 %x, %x
+entry:
+  %x = load i32* @y
+  store atomic i32 %x, i32* @x unordered, align 4
+  %y = load i32* @y
+  %z = add i32 %x, %y
+  ret i32 %z
+}
+
+; GVN across seq_cst store (allowed in theory; not implemented ATM)
+define i32 @test2() nounwind uwtable ssp {
+; CHECK: test2
+; CHECK: add i32 %x, %y
+entry:
+  %x = load i32* @y
+  store atomic i32 %x, i32* @x seq_cst, align 4
+  %y = load i32* @y
+  %z = add i32 %x, %y
+  ret i32 %z
+}
+
+; GVN across unordered load (allowed)
+define i32 @test3() nounwind uwtable ssp {
+; CHECK: test3
+; CHECK: add i32 %x, %x
+entry:
+  %x = load i32* @y
+  %y = load atomic i32* @x unordered, align 4
+  %z = load i32* @y
+  %a = add i32 %x, %z
+  %b = add i32 %y, %a
+  ret i32 %b
+}
+
+; GVN across acquire load (load after atomic load must not be removed)
+define i32 @test4() nounwind uwtable ssp {
+; CHECK: test4
+; CHECK: load atomic i32* @x
+; CHECK: load i32* @y
+entry:
+  %x = load i32* @y
+  %y = load atomic i32* @x seq_cst, align 4
+  %x2 = load i32* @y
+  %x3 = add i32 %x, %x2
+  %y2 = add i32 %y, %x3
+  ret i32 %y2
+}
+
+; GVN load to unordered load (allowed)
+define i32 @test5() nounwind uwtable ssp {
+; CHECK: test5
+; CHECK: add i32 %x, %x
+entry:
+  %x = load atomic i32* @x unordered, align 4
+  %y = load i32* @x
+  %z = add i32 %x, %y
+  ret i32 %z
+}
+
+; GVN unordered load to load (unordered load must not be removed)
+define i32 @test6() nounwind uwtable ssp {
+; CHECK: test6
+; CHECK: load atomic i32* @x unordered
+entry:
+  %x = load i32* @x
+  %x2 = load atomic i32* @x unordered, align 4
+  %x3 = add i32 %x, %x2
+  ret i32 %x3
+}

Added: llvm/trunk/test/Transforms/MemCpyOpt/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/atomic.ll?rev=137888&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/MemCpyOpt/atomic.ll (added)
+++ llvm/trunk/test/Transforms/MemCpyOpt/atomic.ll Wed Aug 17 17:22:24 2011
@@ -0,0 +1,41 @@
+; RUN: opt -basicaa -memcpyopt -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+ at x = global i32 0
+
+declare void @otherf(i32*)
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+
+; memcpyopt should not touch atomic ops
+define void @test1() nounwind uwtable ssp {
+; CHECK: test1
+; CHECK: store atomic
+  %x = alloca [101 x i32], align 16
+  %bc = bitcast [101 x i32]* %x to i8*
+  call void @llvm.memset.p0i8.i64(i8* %bc, i8 0, i64 400, i32 16, i1 false)
+  %gep1 = getelementptr inbounds [101 x i32]* %x, i32 0, i32 100
+  store atomic i32 0, i32* %gep1 unordered, align 4
+  %gep2 = getelementptr inbounds [101 x i32]* %x, i32 0, i32 0
+  call void @otherf(i32* %gep2)
+  ret void
+}
+
+; memcpyopt across unordered store
+define void @test2() nounwind uwtable ssp {
+; CHECK: test2
+; CHECK: call
+; CHECK-NEXT: store atomic
+; CHECK-NEXT: call
+  %old = alloca i32
+  %new = alloca i32
+  call void @otherf(i32* nocapture %old)
+  store atomic i32 0, i32* @x unordered, align 4
+  %v = load i32* %old
+  store i32 %v, i32* %new
+  call void @otherf(i32* nocapture %new)  
+  ret void
+}
+



From krasin at chromium.org  Wed Aug 17 17:26:38 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 17 Aug 2011 15:26:38 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
	config.sub from GNU mainline
Message-ID: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>

Hi llvm team,

This patch updates autoconfig/config.{sub,guess} to the latest version
from the GNU upstream: git://git.savannah.gnu.org/config.git

1. It eliminates a local LLVM patch for auroraux (because, the
mainline config.sub has already got support of auroraux)
2. It adds several new recognized target cpus and operating systems
(in particular, PNaCl)

Please, let me know if it's fine to commit.

Ivan Krasin

From krasin at chromium.org  Wed Aug 17 17:28:06 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 17 Aug 2011 15:28:06 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
	config.sub from GNU mainline
In-Reply-To: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
Message-ID: <CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>

Err: missed the patch.
Please, find it attached to this message.

Also, you can take a look at the patch online:
http://codereview.chromium.org/7676009/

Thanks,
Ivan Krasin
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From grosbach at apple.com  Wed Aug 17 17:49:10 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 22:49:10 -0000
Subject: [llvm-commits] [llvm] r137889 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110817224910.3167F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 17:49:09 2011
New Revision: 137889

URL: http://llvm.org/viewvc/llvm-project?rev=137889&view=rev
Log:
Thumb assembly parsing and encoding for ASR.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137889&r1=137888&r2=137889&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 17:49:09 2011
@@ -2693,7 +2693,7 @@
   // Next, determine if we have a carry setting bit. We explicitly ignore all
   // the instructions we know end in 's'.
   if (Mnemonic.endswith("s") &&
-      !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
+      !(Mnemonic == "cps" || Mnemonic == "mls" ||
         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137889&r1=137888&r2=137889&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 17:49:09 2011
@@ -56,3 +56,23 @@
 
 @ CHECK: adr	r2, _baz                @ encoding: [A,0xa2]
             @   fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
+
+
+ at ------------------------------------------------------------------------------
+@ ASR (immediate)
+ at ------------------------------------------------------------------------------
+        asrs r2, r3, #32
+        asrs r2, r3, #5
+        asrs r2, r3, #1
+
+@ CHECK: asrs	r2, r3, #32             @ encoding: [0x1a,0x10]
+@ CHECK: asrs	r2, r3, #5              @ encoding: [0x5a,0x11]
+@ CHECK: asrs	r2, r3, #1              @ encoding: [0x5a,0x10]
+
+
+ at ------------------------------------------------------------------------------
+@ ASR (register)
+ at ------------------------------------------------------------------------------
+        asrs r5, r2
+
+@ CHECK: asrs	r5, r2                  @ encoding: [0x15,0x41]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=137889&r1=137888&r2=137889&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Wed Aug 17 17:49:09 2011
@@ -18,3 +18,14 @@
 @ CHECK-ERRORS: error: instruction variant requires ARMv6 or later
 @ CHECK-ERRORS:         mov r2, r3
 @ CHECK-ERRORS:         ^
+
+
+@ Out of range immediates for ASR instruction.
+        asrs r2, r3, #33
+        asrs r2, r3, #0
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS:         asrs r2, r3, #33
+@ CHECK-ERRORS:                      ^
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS:         asrs r2, r3, #0
+@ CHECK-ERRORS:                      ^



From dpatel at apple.com  Wed Aug 17 17:49:39 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 17 Aug 2011 22:49:39 -0000
Subject: [llvm-commits] [llvm] r137890 -
	/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Message-ID: <20110817224939.2C5532A6C12C@llvm.org>

Author: dpatel
Date: Wed Aug 17 17:49:38 2011
New Revision: 137890

URL: http://llvm.org/viewvc/llvm-project?rev=137890&view=rev
Log:
Do not use DebugInfoFinder. Extract debug info directly from llvm.dbg.cu named mdnode.

Modified:
    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137890&r1=137889&r2=137890&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Wed Aug 17 17:49:38 2011
@@ -60,11 +60,11 @@
     bool runOnModule(Module &M);
 
     // Create the GCNO files for the Module based on DebugInfo.
-    void emitGCNO(DebugInfoFinder &DIF);
+    void emitGCNO();
 
     // Modify the program to track transitions along edges and call into the
     // profiling runtime to emit .gcda files when run.
-    bool emitProfileArcs(DebugInfoFinder &DIF);
+    bool emitProfileArcs();
 
     // Get pointers to the functions in the runtime library.
     Constant *getStartFileFunc();
@@ -86,8 +86,7 @@
 
     // Add the function to write out all our counters to the global destructor
     // list.
-    void insertCounterWriteout(DebugInfoFinder &,
-                               SmallVector<std::pair<GlobalVariable *,
+    void insertCounterWriteout(SmallVector<std::pair<GlobalVariable *,
                                                      MDNode *>, 8> &);
 
     std::string mangleName(DICompileUnit CU, std::string NewStem);
@@ -353,66 +352,66 @@
   this->M = &M;
   Ctx = &M.getContext();
 
-  DebugInfoFinder DIF;
-  DIF.processModule(M);
-
-  if (EmitNotes) emitGCNO(DIF);
-  if (EmitData) return emitProfileArcs(DIF);
+  if (EmitNotes) emitGCNO();
+  if (EmitData) return emitProfileArcs();
   return false;
 }
 
-void GCOVProfiler::emitGCNO(DebugInfoFinder &DIF) {
+void GCOVProfiler::emitGCNO() {
   DenseMap<const MDNode *, raw_fd_ostream *> GcnoFiles;
-  for (DebugInfoFinder::iterator I = DIF.compile_unit_begin(),
-           E = DIF.compile_unit_end(); I != E; ++I) {
-    // Each compile unit gets its own .gcno file. This means that whether we run
-    // this pass over the original .o's as they're produced, or run it after
-    // LTO, we'll generate the same .gcno files.
-
-    DICompileUnit CU(*I);
-    raw_fd_ostream *&out = GcnoFiles[CU];
-    std::string ErrorInfo;
-    out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
-                             raw_fd_ostream::F_Binary);
-    if (!Use402Format)
-      out->write("oncg*404MVLL", 12);
-    else
-      out->write("oncg*204MVLL", 12);
-  }
-
-  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
-           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
-    DISubprogram SP(*SPI);
-    raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
-
-    Function *F = SP.getFunction();
-    if (!F) continue;
-    GCOVFunction Func(SP, os, Use402Format);
-
-    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
-      GCOVBlock &Block = Func.getBlock(BB);
-      TerminatorInst *TI = BB->getTerminator();
-      if (int successors = TI->getNumSuccessors()) {
-        for (int i = 0; i != successors; ++i) {
-          Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
+  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
+  if (CU_Nodes) {
+    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
+      // Each compile unit gets its own .gcno file. This means that whether we run
+      // this pass over the original .o's as they're produced, or run it after
+      // LTO, we'll generate the same .gcno files.
+      
+      DICompileUnit CU(CU_Nodes->getOperand(i));
+      raw_fd_ostream *&out = GcnoFiles[CU];
+      std::string ErrorInfo;
+      out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
+                               raw_fd_ostream::F_Binary);
+      if (!Use402Format)
+        out->write("oncg*404MVLL", 12);
+      else
+        out->write("oncg*204MVLL", 12);
+  
+      DIArray SPs = CU.getSubprograms();
+      for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
+        DISubprogram SP(SPs.getElement(i));
+        if (!SP.Verify()) continue;
+        raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
+        
+        Function *F = SP.getFunction();
+        if (!F) continue;
+        GCOVFunction Func(SP, os, Use402Format);
+        
+        for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+          GCOVBlock &Block = Func.getBlock(BB);
+          TerminatorInst *TI = BB->getTerminator();
+          if (int successors = TI->getNumSuccessors()) {
+            for (int i = 0; i != successors; ++i) {
+              Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
+            }
+          } else if (isa<ReturnInst>(TI)) {
+            Block.addEdge(Func.getReturnBlock());
+          }
+          
+          uint32_t Line = 0;
+          for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
+            const DebugLoc &Loc = I->getDebugLoc();
+            if (Loc.isUnknown()) continue;
+            if (Line == Loc.getLine()) continue;
+            Line = Loc.getLine();
+            if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
+            
+            GCOVLines &Lines = Block.getFile(SP.getFilename());
+            Lines.addLine(Loc.getLine());
+          }
         }
-      } else if (isa<ReturnInst>(TI)) {
-        Block.addEdge(Func.getReturnBlock());
-      }
-
-      uint32_t Line = 0;
-      for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
-        const DebugLoc &Loc = I->getDebugLoc();
-        if (Loc.isUnknown()) continue;
-        if (Line == Loc.getLine()) continue;
-        Line = Loc.getLine();
-        if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
-
-        GCOVLines &Lines = Block.getFile(SP.getFilename());
-        Lines.addLine(Loc.getLine());
+        Func.writeOut();
       }
     }
-    Func.writeOut();
   }
 
   for (DenseMap<const MDNode *, raw_fd_ostream *>::iterator
@@ -424,104 +423,107 @@
   }
 }
 
-bool GCOVProfiler::emitProfileArcs(DebugInfoFinder &DIF) {
-  if (DIF.subprogram_begin() == DIF.subprogram_end())
-    return false;
-
-  SmallVector<std::pair<GlobalVariable *, MDNode *>, 8> CountersBySP;
-  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
-           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
-    DISubprogram SP(*SPI);
-    Function *F = SP.getFunction();
-    if (!F) continue;
-
-    unsigned Edges = 0;
-    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
-      TerminatorInst *TI = BB->getTerminator();
-      if (isa<ReturnInst>(TI))
-        ++Edges;
-      else
-        Edges += TI->getNumSuccessors();
-    }
-
-    ArrayType *CounterTy =
+bool GCOVProfiler::emitProfileArcs() {
+  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
+  if (!CU_Nodes) return false;
+
+  bool Result = false;  
+  for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
+    DICompileUnit CU(CU_Nodes->getOperand(i));
+    DIArray SPs = CU.getSubprograms();
+    SmallVector<std::pair<GlobalVariable *, MDNode *>, 8> CountersBySP;
+    for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
+      DISubprogram SP(SPs.getElement(i));
+      if (!SP.Verify()) continue;
+      Function *F = SP.getFunction();
+      if (!F) continue;
+      if (!Result) Result = true;
+      unsigned Edges = 0;
+      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+        TerminatorInst *TI = BB->getTerminator();
+        if (isa<ReturnInst>(TI))
+          ++Edges;
+        else
+          Edges += TI->getNumSuccessors();
+      }
+      
+      ArrayType *CounterTy =
         ArrayType::get(Type::getInt64Ty(*Ctx), Edges);
-    GlobalVariable *Counters =
+      GlobalVariable *Counters =
         new GlobalVariable(*M, CounterTy, false,
                            GlobalValue::InternalLinkage,
                            Constant::getNullValue(CounterTy),
                            "__llvm_gcov_ctr", 0, false, 0);
-    CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
-
-    UniqueVector<BasicBlock *> ComplexEdgePreds;
-    UniqueVector<BasicBlock *> ComplexEdgeSuccs;
-
-    unsigned Edge = 0;
-    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
-      TerminatorInst *TI = BB->getTerminator();
-      int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
-      if (Successors) {
-        IRBuilder<> Builder(TI);
-
-        if (Successors == 1) {
-          Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
-                                                              Edge);
-          Value *Count = Builder.CreateLoad(Counter);
-          Count = Builder.CreateAdd(Count,
-                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
-          Builder.CreateStore(Count, Counter);
-        } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
-          Value *Sel = Builder.CreateSelect(
+      CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
+      
+      UniqueVector<BasicBlock *> ComplexEdgePreds;
+      UniqueVector<BasicBlock *> ComplexEdgeSuccs;
+      
+      unsigned Edge = 0;
+      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+        TerminatorInst *TI = BB->getTerminator();
+        int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
+        if (Successors) {
+          IRBuilder<> Builder(TI);
+          
+          if (Successors == 1) {
+            Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
+                                                                Edge);
+            Value *Count = Builder.CreateLoad(Counter);
+            Count = Builder.CreateAdd(Count,
+                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
+            Builder.CreateStore(Count, Counter);
+          } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
+            Value *Sel = Builder.CreateSelect(
               BI->getCondition(),
               ConstantInt::get(Type::getInt64Ty(*Ctx), Edge),
               ConstantInt::get(Type::getInt64Ty(*Ctx), Edge + 1));
-          SmallVector<Value *, 2> Idx;
-          Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
-          Idx.push_back(Sel);
-          Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
-          Value *Count = Builder.CreateLoad(Counter);
-          Count = Builder.CreateAdd(Count,
-                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
-          Builder.CreateStore(Count, Counter);
-        } else {
-          ComplexEdgePreds.insert(BB);
-          for (int i = 0; i != Successors; ++i)
-            ComplexEdgeSuccs.insert(TI->getSuccessor(i));
+            SmallVector<Value *, 2> Idx;
+            Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
+            Idx.push_back(Sel);
+            Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
+            Value *Count = Builder.CreateLoad(Counter);
+            Count = Builder.CreateAdd(Count,
+                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
+            Builder.CreateStore(Count, Counter);
+          } else {
+            ComplexEdgePreds.insert(BB);
+            for (int i = 0; i != Successors; ++i)
+              ComplexEdgeSuccs.insert(TI->getSuccessor(i));
+          }
+          Edge += Successors;
         }
-        Edge += Successors;
       }
-    }
-
-    if (!ComplexEdgePreds.empty()) {
-      GlobalVariable *EdgeTable =
+      
+      if (!ComplexEdgePreds.empty()) {
+        GlobalVariable *EdgeTable =
           buildEdgeLookupTable(F, Counters,
                                ComplexEdgePreds, ComplexEdgeSuccs);
-      GlobalVariable *EdgeState = getEdgeStateValue();
-
-      Type *Int32Ty = Type::getInt32Ty(*Ctx);
-      for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
-        IRBuilder<> Builder(ComplexEdgePreds[i+1]->getTerminator());
-        Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
-      }
-      for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
-        // call runtime to perform increment
-        BasicBlock::iterator InsertPt =
-          ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
-        IRBuilder<> Builder(InsertPt);
-        Value *CounterPtrArray =
+        GlobalVariable *EdgeState = getEdgeStateValue();
+        
+        Type *Int32Ty = Type::getInt32Ty(*Ctx);
+        for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
+          IRBuilder<> Builder(ComplexEdgePreds[i+1]->getTerminator());
+          Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
+        }
+        for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
+          // call runtime to perform increment
+          BasicBlock::iterator InsertPt =
+            ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
+          IRBuilder<> Builder(InsertPt);
+          Value *CounterPtrArray =
             Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,
                                                i * ComplexEdgePreds.size());
-        Builder.CreateCall2(getIncrementIndirectCounterFunc(),
-                            EdgeState, CounterPtrArray);
-        // clear the predecessor number
-        Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
+          Builder.CreateCall2(getIncrementIndirectCounterFunc(),
+                              EdgeState, CounterPtrArray);
+          // clear the predecessor number
+          Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
+        }
       }
     }
+    insertCounterWriteout(CountersBySP);
   }
-
-  insertCounterWriteout(DIF, CountersBySP);
-
-  return true;
+  return Result;
 }
 
 // All edges with successors that aren't branches are "complex", because it
@@ -627,7 +629,6 @@
 }
 
 void GCOVProfiler::insertCounterWriteout(
-    DebugInfoFinder &DIF,
     SmallVector<std::pair<GlobalVariable *, MDNode *>, 8> &CountersBySP) {
   FunctionType *WriteoutFTy =
       FunctionType::get(Type::getVoidTy(*Ctx), false);
@@ -643,29 +644,31 @@
   Constant *EmitArcs = getEmitArcsFunc();
   Constant *EndFile = getEndFileFunc();
 
-  for (DebugInfoFinder::iterator CUI = DIF.compile_unit_begin(),
-           CUE = DIF.compile_unit_end(); CUI != CUE; ++CUI) {
-    DICompileUnit compile_unit(*CUI);
-    std::string FilenameGcda = mangleName(compile_unit, "gcda");
-    Builder.CreateCall(StartFile,
-                       Builder.CreateGlobalStringPtr(FilenameGcda));
-    for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
+  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
+  if (CU_Nodes) {
+    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
+      DICompileUnit compile_unit(CU_Nodes->getOperand(i));
+      std::string FilenameGcda = mangleName(compile_unit, "gcda");
+      Builder.CreateCall(StartFile,
+                         Builder.CreateGlobalStringPtr(FilenameGcda));
+      for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
              I = CountersBySP.begin(), E = CountersBySP.end();
-         I != E; ++I) {
-      DISubprogram SP(I->second);
-      intptr_t ident = reinterpret_cast<intptr_t>(I->second);
-      Builder.CreateCall2(EmitFunction,
-                          ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
-                          Builder.CreateGlobalStringPtr(SP.getName()));
-                                                        
-      GlobalVariable *GV = I->first;
-      unsigned Arcs =
+           I != E; ++I) {
+        DISubprogram SP(I->second);
+        intptr_t ident = reinterpret_cast<intptr_t>(I->second);
+        Builder.CreateCall2(EmitFunction,
+                            ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
+                            Builder.CreateGlobalStringPtr(SP.getName()));
+        
+        GlobalVariable *GV = I->first;
+        unsigned Arcs =
           cast<ArrayType>(GV->getType()->getElementType())->getNumElements();
-      Builder.CreateCall2(EmitArcs,
-                          ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
-                          Builder.CreateConstGEP2_64(GV, 0, 0));
+        Builder.CreateCall2(EmitArcs,
+                            ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
+                            Builder.CreateConstGEP2_64(GV, 0, 0));
+      }
+      Builder.CreateCall(EndFile);
     }
-    Builder.CreateCall(EndFile);
   }
   Builder.CreateRetVoid();
 



From grosbach at apple.com  Wed Aug 17 17:57:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 22:57:40 -0000
Subject: [llvm-commits] [llvm] r137891 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817225740.35F092A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 17:57:40 2011
New Revision: 137891

URL: http://llvm.org/viewvc/llvm-project?rev=137891&view=rev
Log:
Thumb assembly parsing and encoding for B.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137891&r1=137890&r2=137891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 17:57:40 2011
@@ -3035,6 +3035,10 @@
     if (Inst.getOperand(3).getImm() < 8)
       Inst.setOpcode(ARM::tADDi3);
     break;
+  case ARM::tBcc:
+    // If the conditional is AL, we really want tB.
+    if (Inst.getOperand(1).getImm() == ARMCC::AL)
+      Inst.setOpcode(ARM::tB);
   }
 }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137891&r1=137890&r2=137891&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 17:57:40 2011
@@ -76,3 +76,15 @@
         asrs r5, r2
 
 @ CHECK: asrs	r5, r2                  @ encoding: [0x15,0x41]
+
+
+ at ------------------------------------------------------------------------------
+@ B
+ at ------------------------------------------------------------------------------
+        b _baz
+        beq _bar
+
+@ CHECK: b	_baz                    @ encoding: [A,0xe0'A']
+             @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
+@ CHECK: beq	_bar                    @ encoding: [A,0xd0]
+             @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc



From ahatanak at gmail.com  Wed Aug 17 17:59:46 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 22:59:46 -0000
Subject: [llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td
Message-ID: <20110817225946.BB2F92A6C12C@llvm.org>

Author: ahatanak
Date: Wed Aug 17 17:59:46 2011
New Revision: 137892

URL: http://llvm.org/viewvc/llvm-project?rev=137892&view=rev
Log:
Changed definition of EXT and INS per Bruno's comments.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137892&r1=137891&r2=137892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 17:59:46 2011
@@ -558,8 +558,8 @@
 
   return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
                      ShiftRight.getOperand(0),
-                     DAG.getConstant(SMSize, MVT::i32),
-                     DAG.getConstant(Pos, MVT::i32));
+                     DAG.getConstant(Pos, MVT::i32),
+                     DAG.getConstant(SMSize, MVT::i32));
 }
   
 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
@@ -613,8 +613,8 @@
   
   return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
                      Shl.getOperand(0),
-                     DAG.getConstant(SMSize0, MVT::i32),
                      DAG.getConstant(SMPos0, MVT::i32),
+                     DAG.getConstant(SMSize0, MVT::i32),
                      And0.getOperand(0));  
 }
   

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137892&r1=137891&r2=137892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Aug 17 17:59:46 2011
@@ -102,28 +102,6 @@
   let Inst{25-0} = addr;
 }
 
-// Ext and Ins
-class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
-             list<dag> pattern, InstrItinClass itin>:
-  MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
-           pattern, itin>
-{
-  bits<5>  rt;
-  bits<5>  rs;
-  bits<5>  sz;
-  bits<5>  pos;
-  bits<6>  funct;
-
-  let opcode = 0x1f;
-  let funct  = _funct;
-
-  let Inst{25-21} = rs;
-  let Inst{20-16} = rt;
-  let Inst{15-11} = sz;
-  let Inst{10-6}  = pos;
-  let Inst{5-0}   = funct;
-}
-
 //===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137892&r1=137891&r2=137892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 17 17:59:46 2011
@@ -405,6 +405,19 @@
   let shamt = 0;
 }
 
+// Ext and Ins
+class ExtIns<bits<6> _funct, string instr_asm, dag ins,
+             list<dag> pattern, InstrItinClass itin>:
+  FR<0x1f, _funct, (outs CPURegs:$rt), ins,
+     !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
+  bits<5> src;
+  bits<5> pos;
+  bits<5> size;
+  let rs = src;
+  let rd = size;
+  let shamt = pos;
+}
+
 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
 class Atomic2Ops<PatFrag Op, string Opstr> :
   MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
@@ -677,20 +690,19 @@
 def RDHWR : ReadHardware;
 
 let Predicates = [IsMips32r2] in {
-  def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
-                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
-                   [(set CPURegs:$dst,
-                     (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
-                   NoItinerary>;
-  let Constraints = "$src1 = $dst" in
-  def Ins : ExtIns<0b000100, "ins",
-                   (outs CPURegs:$dst),
-                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
-                    CPURegs:$src1),
-                   [(set CPURegs:$dst,
-                     (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
-                      CPURegs:$src1))],
-                   NoItinerary>;
+
+def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
+                 [(set CPURegs:$rt, 
+                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
+                 NoItinerary>;
+
+let Constraints = "$src = $rt" in
+def INS : ExtIns<4, "ins",
+                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
+                 [(set CPURegs:$rt, 
+                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
+                    CPURegs:$src))],
+                 NoItinerary>;
 }
 
 //===----------------------------------------------------------------------===//



From grosbach at apple.com  Wed Aug 17 18:00:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 23:00:53 -0000
Subject: [llvm-commits] [llvm] r137895 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110817230053.6A7F42A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 18:00:53 2011
New Revision: 137895

URL: http://llvm.org/viewvc/llvm-project?rev=137895&view=rev
Log:
ARM assembly parsing and encoding test for BIC.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137895&r1=137894&r2=137895&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 18:00:53 2011
@@ -88,3 +88,11 @@
              @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
 @ CHECK: beq	_bar                    @ encoding: [A,0xd0]
              @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
+
+
+ at ------------------------------------------------------------------------------
+@ BICS
+ at ------------------------------------------------------------------------------
+        bics r1, r6
+
+@ CHECK: bics	r1, r6                  @ encoding: [0xb1,0x43]



From bruno.cardoso at gmail.com  Wed Aug 17 18:07:09 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 16:07:09 -0700
Subject: [llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td
In-Reply-To: <20110817225946.BB2F92A6C12C@llvm.org>
References: <20110817225946.BB2F92A6C12C@llvm.org>
Message-ID: <CACk9FxbaV91TxqrfEaAFtcC0gWCZi6rQ4EfpOckjTBDAeM=Qxg@mail.gmail.com>

On Wed, Aug 17, 2011 at 3:59 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Wed Aug 17 17:59:46 2011
> New Revision: 137892
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137892&view=rev
> Log:
> Changed definition of EXT and INS per Bruno's comments.
>
>
> Modified:
> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 17:59:46 2011
> @@ -558,8 +558,8 @@
>
> ? return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
> ? ? ? ? ? ? ? ? ? ? ?ShiftRight.getOperand(0),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32));
> ?}
>
> ?static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
> @@ -613,8 +613,8 @@
>
> ? return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
> ? ? ? ? ? ? ? ? ? ? ?Shl.getOperand(0),
> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SMPos0, MVT::i32),
> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
> ? ? ? ? ? ? ? ? ? ? ?And0.getOperand(0));
> ?}
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Aug 17 17:59:46 2011
> @@ -102,28 +102,6 @@
> ? let Inst{25-0} = addr;
> ?}
>
> -// Ext and Ins
> -class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
> - ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
> - ?MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
> - ? ? ? ? ? pattern, itin>
> -{
> - ?bits<5> ?rt;
> - ?bits<5> ?rs;
> - ?bits<5> ?sz;
> - ?bits<5> ?pos;
> - ?bits<6> ?funct;
> -
> - ?let opcode = 0x1f;
> - ?let funct ?= _funct;
> -
> - ?let Inst{25-21} = rs;
> - ?let Inst{20-16} = rt;
> - ?let Inst{15-11} = sz;
> - ?let Inst{10-6} ?= pos;
> - ?let Inst{5-0} ? = funct;
> -}
> -
> ?//===----------------------------------------------------------------------===//
> ?//
> ?// ?FLOATING POINT INSTRUCTION FORMATS
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 17 17:59:46 2011
> @@ -405,6 +405,19 @@
> ? let shamt = 0;
> ?}
>
> +// Ext and Ins
> +class ExtIns<bits<6> _funct, string instr_asm, dag ins,
> + ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
> + ?FR<0x1f, _funct, (outs CPURegs:$rt), ins,
> + ? ? !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
> + ?bits<5> src;
> + ?bits<5> pos;
> + ?bits<5> size;
> + ?let rs = src;
> + ?let rd = size;
> + ?let shamt = pos;
> +}
> +

If "$src = $rt" why are you encoding it in "rs" ?

> ?// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
> ?class Atomic2Ops<PatFrag Op, string Opstr> :
> ? MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
> @@ -677,20 +690,19 @@
> ?def RDHWR : ReadHardware;
>
> ?let Predicates = [IsMips32r2] in {
> - ?def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
> - ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
> - ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
> - ? ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
> - ? ? ? ? ? ? ? ? ? NoItinerary>;
> - ?let Constraints = "$src1 = $dst" in
> - ?def Ins : ExtIns<0b000100, "ins",
> - ? ? ? ? ? ? ? ? ? (outs CPURegs:$dst),
> - ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
> - ? ? ? ? ? ? ? ? ? ?CPURegs:$src1),
> - ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
> - ? ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
> - ? ? ? ? ? ? ? ? ? ? ?CPURegs:$src1))],
> - ? ? ? ? ? ? ? ? ? NoItinerary>;
> +
> +def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
> + ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
> + ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
> + ? ? ? ? ? ? ? ? NoItinerary>;
> +
> +let Constraints = "$src = $rt" in
> +def INS : ExtIns<4, "ins",
> + ? ? ? ? ? ? ? ? (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
> + ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
> + ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src))],
> + ? ? ? ? ? ? ? ? NoItinerary>;
> ?}
>
> ?//===----------------------------------------------------------------------===//
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From grosbach at apple.com  Wed Aug 17 18:08:57 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 23:08:57 -0000
Subject: [llvm-commits] [llvm] r137897 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20110817230857.6236E2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 18:08:57 2011
New Revision: 137897

URL: http://llvm.org/viewvc/llvm-project?rev=137897&view=rev
Log:
Clean up patterns for Thumb1 system instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137897&r1=137896&r2=137897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 17 18:08:57 2011
@@ -216,39 +216,33 @@
             Requires<[IsThumb, IsThumb1Only]>;
 }
 
-// T1Disassembly - A simple class to make encoding some disassembly patterns
-// easier and less verbose.
-class T1Disassembly<bits<2> op1, bits<8> op2>
+class T1SystemEncoding<bits<8> opc>
   : T1Encoding<0b101111> {
-  let Inst{9-8} = op1;
-  let Inst{7-0} = op2;
+  let Inst{9-8} = 0b11;
+  let Inst{7-0} = opc;
 }
 
-def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
-                [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b11, 0x00>; // A8.6.110
+def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
+           T1SystemEncoding<0x00>; // A8.6.110
 
-def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
-                  [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b11, 0x10>; // A8.6.410
+def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
+           T1SystemEncoding<0x10>; // A8.6.410
 
-def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
-                [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b11, 0x20>; // A8.6.408
+def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
+           T1SystemEncoding<0x20>; // A8.6.408
 
-def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
-                [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b11, 0x30>; // A8.6.409
+def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
+           T1SystemEncoding<0x30>; // A8.6.409
 
-def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
-                [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b11, 0x40>; // A8.6.157
+def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
+           T1SystemEncoding<0x40>; // A8.6.157
 
-// The i32imm operand $val can be used by a debugger to store more information
+// The imm operand $val can be used by a debugger to store more information
 // about the breakpoint.
-def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
-                [/* For disassembly only; pattern left blank */]>,
-           T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
+def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
+                []>,
+           T1Encoding<0b101111> {
+  let Inst{9-8} = 0b10;
   // A8.6.22
   bits<8> val;
   let Inst{7-0} = val;



From grosbach at apple.com  Wed Aug 17 18:11:13 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 23:11:13 -0000
Subject: [llvm-commits] [llvm] r137898 - in /llvm/trunk/test/MC/ARM:
 basic-thumb-instructions.s thumb-diagnostics.s
Message-ID: <20110817231113.A23952A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 18:11:13 2011
New Revision: 137898

URL: http://llvm.org/viewvc/llvm-project?rev=137898&view=rev
Log:
ARM assembly parsing and encoding test for BKPT.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137898&r1=137897&r2=137898&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 17 18:11:13 2011
@@ -96,3 +96,13 @@
         bics r1, r6
 
 @ CHECK: bics	r1, r6                  @ encoding: [0xb1,0x43]
+
+
+ at ------------------------------------------------------------------------------
+@ BKPT
+ at ------------------------------------------------------------------------------
+        bkpt #0
+        bkpt #255
+
+@ CHECK: bkpt	#0                      @ encoding: [0x00,0xbe]
+@ CHECK: bkpt	#255                    @ encoding: [0xff,0xbe]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=137898&r1=137897&r2=137898&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Wed Aug 17 18:11:13 2011
@@ -29,3 +29,13 @@
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         asrs r2, r3, #0
 @ CHECK-ERRORS:                      ^
+
+@ Out of range immediates for BKPT instruction.
+        bkpt #256
+        bkpt #-1
+error: invalid operand for instruction
+        bkpt #256
+             ^
+error: invalid operand for instruction
+        bkpt #-1
+             ^



From ahatanak at gmail.com  Wed Aug 17 18:16:05 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 16:16:05 -0700
Subject: [llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td
In-Reply-To: <CACk9FxbaV91TxqrfEaAFtcC0gWCZi6rQ4EfpOckjTBDAeM=Qxg@mail.gmail.com>
References: <20110817225946.BB2F92A6C12C@llvm.org>
	<CACk9FxbaV91TxqrfEaAFtcC0gWCZi6rQ4EfpOckjTBDAeM=Qxg@mail.gmail.com>
Message-ID: <CAB297QwQ=77WW7_U3o-YhqNeTpcmsLaMN7it13BF8tA8t14vLg@mail.gmail.com>

src has nothing to do with the fifth operand of INS. It is the bit
field newly defined in class ExtIns ( bits<5> src), which gets bound
to field rs defined in class FR.

On Wed, Aug 17, 2011 at 4:07 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> On Wed, Aug 17, 2011 at 3:59 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>> Author: ahatanak
>> Date: Wed Aug 17 17:59:46 2011
>> New Revision: 137892
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=137892&view=rev
>> Log:
>> Changed definition of EXT and INS per Bruno's comments.
>>
>>
>> Modified:
>> ? ?llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137892&r1=137891&r2=137892&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 17:59:46 2011
>> @@ -558,8 +558,8 @@
>>
>> ? return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
>> ? ? ? ? ? ? ? ? ? ? ?ShiftRight.getOperand(0),
>> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32),
>> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32));
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Pos, MVT::i32),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize, MVT::i32));
>> ?}
>>
>> ?static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
>> @@ -613,8 +613,8 @@
>>
>> ? return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
>> ? ? ? ? ? ? ? ? ? ? ?Shl.getOperand(0),
>> - ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
>> ? ? ? ? ? ? ? ? ? ? ?DAG.getConstant(SMPos0, MVT::i32),
>> + ? ? ? ? ? ? ? ? ? ? DAG.getConstant(SMSize0, MVT::i32),
>> ? ? ? ? ? ? ? ? ? ? ?And0.getOperand(0));
>> ?}
>>
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137892&r1=137891&r2=137892&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Aug 17 17:59:46 2011
>> @@ -102,28 +102,6 @@
>> ? let Inst{25-0} = addr;
>> ?}
>>
>> -// Ext and Ins
>> -class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
>> - ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>> - ?MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
>> - ? ? ? ? ? pattern, itin>
>> -{
>> - ?bits<5> ?rt;
>> - ?bits<5> ?rs;
>> - ?bits<5> ?sz;
>> - ?bits<5> ?pos;
>> - ?bits<6> ?funct;
>> -
>> - ?let opcode = 0x1f;
>> - ?let funct ?= _funct;
>> -
>> - ?let Inst{25-21} = rs;
>> - ?let Inst{20-16} = rt;
>> - ?let Inst{15-11} = sz;
>> - ?let Inst{10-6} ?= pos;
>> - ?let Inst{5-0} ? = funct;
>> -}
>> -
>> ?//===----------------------------------------------------------------------===//
>> ?//
>> ?// ?FLOATING POINT INSTRUCTION FORMATS
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137892&r1=137891&r2=137892&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 17 17:59:46 2011
>> @@ -405,6 +405,19 @@
>> ? let shamt = 0;
>> ?}
>>
>> +// Ext and Ins
>> +class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>> + ? ? ? ? ? ? list<dag> pattern, InstrItinClass itin>:
>> + ?FR<0x1f, _funct, (outs CPURegs:$rt), ins,
>> + ? ? !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
>> + ?bits<5> src;
>> + ?bits<5> pos;
>> + ?bits<5> size;
>> + ?let rs = src;
>> + ?let rd = size;
>> + ?let shamt = pos;
>> +}
>> +
>
> If "$src = $rt" why are you encoding it in "rs" ?
>
>> ?// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
>> ?class Atomic2Ops<PatFrag Op, string Opstr> :
>> ? MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
>> @@ -677,20 +690,19 @@
>> ?def RDHWR : ReadHardware;
>>
>> ?let Predicates = [IsMips32r2] in {
>> - ?def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
>> - ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
>> - ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>> - ? ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
>> - ? ? ? ? ? ? ? ? ? NoItinerary>;
>> - ?let Constraints = "$src1 = $dst" in
>> - ?def Ins : ExtIns<0b000100, "ins",
>> - ? ? ? ? ? ? ? ? ? (outs CPURegs:$dst),
>> - ? ? ? ? ? ? ? ? ? (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
>> - ? ? ? ? ? ? ? ? ? ?CPURegs:$src1),
>> - ? ? ? ? ? ? ? ? ? [(set CPURegs:$dst,
>> - ? ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
>> - ? ? ? ? ? ? ? ? ? ? ?CPURegs:$src1))],
>> - ? ? ? ? ? ? ? ? ? NoItinerary>;
>> +
>> +def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
>> + ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>> + ? ? ? ? ? ? ? ? ? (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>> + ? ? ? ? ? ? ? ? NoItinerary>;
>> +
>> +let Constraints = "$src = $rt" in
>> +def INS : ExtIns<4, "ins",
>> + ? ? ? ? ? ? ? ? (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
>> + ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
>> + ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
>> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src))],
>> + ? ? ? ? ? ? ? ? NoItinerary>;
>> ?}
>>
>> ?//===----------------------------------------------------------------------===//
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
>
>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>


From grosbach at apple.com  Wed Aug 17 18:23:07 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 17 Aug 2011 23:23:07 -0000
Subject: [llvm-commits] [llvm] r137900 -
	/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
Message-ID: <20110817232307.BF1AC2A6C12C@llvm.org>

Author: grosbach
Date: Wed Aug 17 18:23:07 2011
New Revision: 137900

URL: http://llvm.org/viewvc/llvm-project?rev=137900&view=rev
Log:
Remove extraneous newline from operand print method. PR10569.

Modified:
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=137900&r1=137899&r2=137900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Aug 17 18:23:07 2011
@@ -900,8 +900,8 @@
   O << ", ror #";
   switch (Imm) {
   default: assert (0 && "illegal ror immediate!");
-  case 1: O << "8\n"; break;
-  case 2: O << "16\n"; break;
-  case 3: O << "24\n"; break;
+  case 1: O << "8"; break;
+  case 2: O << "16"; break;
+  case 3: O << "24"; break;
   }
 }



From bruno.cardoso at gmail.com  Wed Aug 17 18:28:33 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 17 Aug 2011 16:28:33 -0700
Subject: [llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td
In-Reply-To: <CAB297QwQ=77WW7_U3o-YhqNeTpcmsLaMN7it13BF8tA8t14vLg@mail.gmail.com>
References: <20110817225946.BB2F92A6C12C@llvm.org>
	<CACk9FxbaV91TxqrfEaAFtcC0gWCZi6rQ4EfpOckjTBDAeM=Qxg@mail.gmail.com>
	<CAB297QwQ=77WW7_U3o-YhqNeTpcmsLaMN7it13BF8tA8t14vLg@mail.gmail.com>
Message-ID: <CACk9FxYLmPdA_DhCSVjg7u2iY+-ZPhWbAMyHrrVfRvXn5avACg@mail.gmail.com>

> src has nothing to do with the fifth operand of INS. It is the bit
> field newly defined in class ExtIns ( bits<5> src), which gets bound
> to field rs defined in class FR.

This is exactly why I'm asking. "bits<5> src" gets bounded to "rs",
but "CPURegs:$rs" is also getting bounded to it. There's something
wrong here, cause why would you wanna bind another field to "rs" if
you already have CPURegs:$rs? Got it?

+def INS : ExtIns<4, "ins",
+                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
+                 [(set CPURegs:$rt,
+                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
+                    CPURegs:$src))],
+                 NoItinerary>;


-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From resistor at mac.com  Wed Aug 17 18:37:33 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 17 Aug 2011 23:37:33 -0000
Subject: [llvm-commits] [llvm] r137902 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
Message-ID: <20110817233733.C133B2A6C12D@llvm.org>

Author: resistor
Date: Wed Aug 17 18:37:33 2011
New Revision: 137902

URL: http://llvm.org/viewvc/llvm-project?rev=137902&view=rev
Log:
Port new Thumb1 encoding tests over to decoding tests.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=137902&r1=137901&r2=137902&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Wed Aug 17 18:37:33 2011
@@ -28,3 +28,40 @@
 
 0xd1 0x18
 0x42 0x44
+
+#------------------------------------------------------------------------------
+# ASR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: asrs r2, r3, #32
+# CHECK: asrs r2, r3, #5
+# CHECK: asrs r2, r3, #1
+
+0x1a 0x10
+0x5a 0x11
+0x5a 0x10
+
+
+#------------------------------------------------------------------------------
+# ASR (register)
+#------------------------------------------------------------------------------
+# CHECK: asrs r5, r2
+
+0x15 0x41
+
+#------------------------------------------------------------------------------
+# BICS
+#------------------------------------------------------------------------------
+# CHECK: bics r1, r6
+
+0xb1 0x43
+
+
+#------------------------------------------------------------------------------
+# BKPT
+#------------------------------------------------------------------------------
+# CHECK: bkpt #0
+# CHECK: bkpt #255
+
+0x00 0xbe
+0xff 0xbe
+



From ahatanak at gmail.com  Wed Aug 17 18:39:41 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Wed, 17 Aug 2011 16:39:41 -0700
Subject: [llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td
In-Reply-To: <CACk9FxYLmPdA_DhCSVjg7u2iY+-ZPhWbAMyHrrVfRvXn5avACg@mail.gmail.com>
References: <20110817225946.BB2F92A6C12C@llvm.org>
	<CACk9FxbaV91TxqrfEaAFtcC0gWCZi6rQ4EfpOckjTBDAeM=Qxg@mail.gmail.com>
	<CAB297QwQ=77WW7_U3o-YhqNeTpcmsLaMN7it13BF8tA8t14vLg@mail.gmail.com>
	<CACk9FxYLmPdA_DhCSVjg7u2iY+-ZPhWbAMyHrrVfRvXn5avACg@mail.gmail.com>
Message-ID: <CAB297QyQWza1Qhuai1zLmETmPPZbDKMNiV=k7cuEwdNCN0Vcdg@mail.gmail.com>

I am not sure if I got your point.

Definition of INS:
INS (outs CPURegs:$rt), (ins CPURegs:$rs, uimm16:$pos, uimm16:$size,
CPURegs:$src);

This is the output of "tblgen Mips.td":
def INS {       // Instruction MipsInst FR ExtIns
  field bits<32> Inst = { 0, 1, 1, 1, 1, 1, src{4}, src{3}, src{2},
src{1}, src{0}, rt{4}, rt{3}, rt{2}, rt{1}, rt{0}, size{4}, size{3},
size{2}, size{1}, size{0}, pos{4}, pos{3}, pos{2}, pos{1}, pos{0}, 0,
0, 0, 1, 0, 0 };
...
  bits<5> rd = { size{4}, size{3}, size{2}, size{1}, size{0} };
  bits<5> rs = { src{4}, src{3}, src{2}, src{1}, src{0} };
  bits<5> rt = { ?, ?, ?, ?, ? };
  bits<5> shamt = { pos{4}, pos{3}, pos{2}, pos{1}, pos{0} };
  bits<6> funct = { ExtIns:_funct{5}, ExtIns:_funct{4},
ExtIns:_funct{3}, ExtIns:_funct{2},   ExtIns:_funct{1},
ExtIns:_funct{0} };
  bits<5> src = { ?, ?, ?, ?, ? };
  bits<5> pos = { ?, ?, ?, ?, ? };
  bits<5> size = { ?, ?, ?, ?, ? };

CPURegs:$rs is bound to "bits<5> src", which in turn is bound to bits<5> rs.
Is this a problem? If it is, I am not sure how to fix this.

On Wed, Aug 17, 2011 at 4:28 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
>> src has nothing to do with the fifth operand of INS. It is the bit
>> field newly defined in class ExtIns ( bits<5> src), which gets bound
>> to field rs defined in class FR.
>
> This is exactly why I'm asking. "bits<5> src" gets bounded to "rs",
> but "CPURegs:$rs" is also getting bounded to it. There's something
> wrong here, cause why would you wanna bind another field to "rs" if
> you already have CPURegs:$rs? Got it?
>
> +def INS : ExtIns<4, "ins",
> + ? ? ? ? ? ? ? ? (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
> + ? ? ? ? ? ? ? ? [(set CPURegs:$rt,
> + ? ? ? ? ? ? ? ? ? (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
> + ? ? ? ? ? ? ? ? ? ?CPURegs:$src))],
> + ? ? ? ? ? ? ? ? NoItinerary>;
>
>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>


From geek4civic at gmail.com  Wed Aug 17 18:49:37 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 18 Aug 2011 08:49:37 +0900
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
Message-ID: <CADiQthMTXZqX2pR_Tuudt_5u-18k3fiwwt+LVBbhAt5DxfgCVg@mail.gmail.com>

Micah, good morning.

> [Villmow, Micah] Yes, it is going through internal code review now. However,
> it will be posted for LLVM 2.9
>
> first as that is what we are building against internally. After that, when I
> get time as I?m pretty busy, I will
> update it for TOT.

Good to hear. btw, do you, AMD, have mc-elf emitter for your BIF?

...Takumi


From Micah.Villmow at amd.com  Wed Aug 17 18:53:16 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Wed, 17 Aug 2011 18:53:16 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <CADiQthMTXZqX2pR_Tuudt_5u-18k3fiwwt+LVBbhAt5DxfgCVg@mail.gmail.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CADiQthMTXZqX2pR_Tuudt_5u-18k3fiwwt+LVBbhAt5DxfgCVg@mail.gmail.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE3381@sausexmbp02.amd.com>



> -----Original Message-----
> From: NAKAMURA Takumi [mailto:geek4civic at gmail.com]
> Sent: Wednesday, August 17, 2011 4:50 PM
> To: Villmow, Micah
> Cc: llvm-commits
> Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
> 
> Micah, good morning.
> 
> > [Villmow, Micah] Yes, it is going through internal code review now.
> However,
> > it will be posted for LLVM 2.9
> >
> > first as that is what we are building against internally. After that,
> when I
> > get time as I'm pretty busy, I will
> > update it for TOT.
> 
> Good to hear. btw, do you, AMD, have mc-elf emitter for your BIF?
[Villmow, Micah] Not yet.
> 
> ...Takumi




From clattner at apple.com  Wed Aug 17 19:48:55 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 17:48:55 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
Message-ID: <26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>


On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:

> Err: missed the patch.
> Please, find it attached to this message.
> 
> Also, you can take a look at the patch online:
> http://codereview.chromium.org/7676009/

Hi Ivan,

Hopefully dumb question: what are the licensing implications of this?  Is the new autoconf goop GPL3?

-Chris

From clattner at apple.com  Wed Aug 17 19:47:36 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 17:47:36 -0700
Subject: [llvm-commits] [llvm] r137891 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
In-Reply-To: <20110817225740.35F092A6C12C@llvm.org>
References: <20110817225740.35F092A6C12C@llvm.org>
Message-ID: <D127BCB2-BA43-4F56-9327-5CE3AB822BE5@apple.com>


On Aug 17, 2011, at 3:57 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Wed Aug 17 17:57:40 2011
> New Revision: 137891
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137891&view=rev
> Log:
> Thumb assembly parsing and encoding for B.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137891&r1=137890&r2=137891&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 17:57:40 2011
> @@ -3035,6 +3035,10 @@
>     if (Inst.getOperand(3).getImm() < 8)
>       Inst.setOpcode(ARM::tADDi3);
>     break;
> +  case ARM::tBcc:
> +    // If the conditional is AL, we really want tB.
> +    if (Inst.getOperand(1).getImm() == ARMCC::AL)
> +      Inst.setOpcode(ARM::tB);
>   }
> }

Not necessary for correctness, but please add a break;

-Chris


From dpatel at apple.com  Wed Aug 17 19:50:51 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 00:50:51 -0000
Subject: [llvm-commits] [llvm] r137908 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20110818005051.AF85F2A6C12C@llvm.org>

Author: dpatel
Date: Wed Aug 17 19:50:51 2011
New Revision: 137908

URL: http://llvm.org/viewvc/llvm-project?rev=137908&view=rev
Log:
Dramatically speedup codegen prepare by a) avoiding use of dominator tree and b) doing a separate pass over dbg.value instructions.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=137908&r1=137907&r2=137908&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed Aug 17 19:50:51 2011
@@ -58,6 +58,7 @@
 STATISTIC(NumExtsMoved,  "Number of [s|z]ext instructions combined with loads");
 STATISTIC(NumExtUses,    "Number of uses of [s|z]ext instructions optimized");
 STATISTIC(NumRetsDup,    "Number of return instructions duplicated");
+STATISTIC(NumDbgValueMoved, "Number of debug value instructions moved");
 
 static cl::opt<bool> DisableBranchOpts(
   "disable-cgp-branch-opts", cl::Hidden, cl::init(false),
@@ -110,6 +111,7 @@
     bool MoveExtToFormExtLoad(Instruction *I);
     bool OptimizeExtUses(Instruction *I);
     bool DupRetToEnableTailCallOpts(ReturnInst *RI);
+    bool PlaceDbgValues(Function &F);
   };
 }
 
@@ -132,6 +134,11 @@
   // unconditional branch.
   EverMadeChange |= EliminateMostlyEmptyBlocks(F);
 
+  // llvm.dbg.value is far away from the value then iSel may not be able
+  // handle it properly. iSel will drop llvm.dbg.value if it can not 
+  // find a node corresponding to the value.
+  EverMadeChange |= PlaceDbgValues(F);
+
   bool MadeChange = true;
   while (MadeChange) {
     MadeChange = false;
@@ -549,22 +556,6 @@
   // From here on out we're working with named functions.
   if (CI->getCalledFunction() == 0) return false;
 
-  // llvm.dbg.value is far away from the value then iSel may not be able
-  // handle it properly. iSel will drop llvm.dbg.value if it can not 
-  // find a node corresponding to the value.
-  if (DbgValueInst *DVI = dyn_cast<DbgValueInst>(CI))
-    if (Instruction *VI = dyn_cast_or_null<Instruction>(DVI->getValue()))
-      if (!VI->isTerminator() &&
-          (DVI->getParent() != VI->getParent() || DT->dominates(DVI, VI))) {
-        DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI);
-        DVI->removeFromParent();
-        if (isa<PHINode>(VI))
-          DVI->insertBefore(VI->getParent()->getFirstInsertionPt());
-        else
-          DVI->insertAfter(VI);
-        return true;
-      }
-
   // We'll need TargetData from here on out.
   const TargetData *TD = TLI ? TLI->getTargetData() : 0;
   if (!TD) return false;
@@ -1156,3 +1147,34 @@
 
   return MadeChange;
 }
+
+// llvm.dbg.value is far away from the value then iSel may not be able
+// handle it properly. iSel will drop llvm.dbg.value if it can not 
+// find a node corresponding to the value.
+bool CodeGenPrepare::PlaceDbgValues(Function &F) {
+  bool MadeChange = false;
+  for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I) {
+    Instruction *PrevNonDbgInst = NULL;
+    for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {
+      Instruction *Insn = BI; ++BI;
+      DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn);
+      if (!DVI) {
+        PrevNonDbgInst = Insn;
+        continue;
+      }
+
+      Instruction *VI = dyn_cast_or_null<Instruction>(DVI->getValue());
+      if (VI && VI != PrevNonDbgInst && !VI->isTerminator()) {
+        DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI);
+        DVI->removeFromParent();
+        if (isa<PHINode>(VI))
+          DVI->insertBefore(VI->getParent()->getFirstInsertionPt());
+        else
+          DVI->insertAfter(VI);
+        MadeChange = true;
+        ++NumDbgValueMoved;
+      }
+    }
+  }
+  return MadeChange;
+}



From krasin at google.com  Wed Aug 17 19:53:16 2011
From: krasin at google.com (Ivan Krasin)
Date: Wed, 17 Aug 2011 17:53:16 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
Message-ID: <CAOei5RfYuT_W9VqL3PNx=TRwxfFKhUK=otXSzdk5fqH+3MRWbg@mail.gmail.com>

On Wed, Aug 17, 2011 at 5:48 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>
>> Err: missed the patch.
>> Please, find it attached to this message.
>>
>> Also, you can take a look at the patch online:
>> http://codereview.chromium.org/7676009/
>
> Hi Ivan,
>
> Hopefully dumb question: what are the licensing implications of this? ?Is the new autoconf goop GPL3?

Hi Chris,

I think that the best thing I can do is to add Roland McGrath to this
thread, who has made the interesting to me change to GNU config.sub.
I'm not very strong in the licensing questions, but I agree that it's
extremely important.

Thanks,
Ivan Krasin


>
> -Chris
>


From criswell at illinois.edu  Wed Aug 17 20:04:54 2011
From: criswell at illinois.edu (John Criswell)
Date: Wed, 17 Aug 2011 20:04:54 -0500
Subject: [llvm-commits] Patch to Fix Compilation Error of LTO on Linux
Message-ID: <4E4C6536.3050807@illinois.edu>

Dear All,

The attached patch fixes a warning when compiling libLTO on Linux.  
Basically, there's a "return NULL" in a function returning bool.

I don't actually know what this function does or what its return value 
means, so I'm submitting it for review before commit.

-- John T.

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From echristo at apple.com  Wed Aug 17 20:09:42 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 17 Aug 2011 18:09:42 -0700
Subject: [llvm-commits] Patch to Fix Compilation Error of LTO on Linux
In-Reply-To: <4E4C6536.3050807@illinois.edu>
References: <4E4C6536.3050807@illinois.edu>
Message-ID: <B6AC6B22-6ADB-4E1A-9842-BBC95C2406C5@apple.com>


On Aug 17, 2011, at 6:04 PM, John Criswell wrote:

> when compiling libLTO on Linux.  Basically, there's a "return NULL" in a function returning bool.

I believe you want to return true here since there's an error.

Thanks!

-eric
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From criswell at illinois.edu  Wed Aug 17 20:12:48 2011
From: criswell at illinois.edu (John Criswell)
Date: Wed, 17 Aug 2011 20:12:48 -0500
Subject: [llvm-commits] Patch to Fix Compilation Error of LTO on Linux
In-Reply-To: <B6AC6B22-6ADB-4E1A-9842-BBC95C2406C5@apple.com>
References: <4E4C6536.3050807@illinois.edu>
	<B6AC6B22-6ADB-4E1A-9842-BBC95C2406C5@apple.com>
Message-ID: <4E4C6710.7000105@illinois.edu>

On 8/17/11 8:09 PM, Eric Christopher wrote:
>
> On Aug 17, 2011, at 6:04 PM, John Criswell wrote:
>
>> when compiling libLTO on Linux.  Basically, there's a "return NULL" 
>> in a function returning bool.
>
> I believe you want to return true here since there's an error.

Ah.  Indeed.

I'll go ahead and fix it and commit.

-- John T.

>
> Thanks!
>
> -eric

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From criswell at uiuc.edu  Wed Aug 17 20:19:05 2011
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 18 Aug 2011 01:19:05 -0000
Subject: [llvm-commits] [llvm] r137913 -
	/llvm/trunk/tools/lto/LTOCodeGenerator.cpp
Message-ID: <20110818011905.CFD152A6C12C@llvm.org>

Author: criswell
Date: Wed Aug 17 20:19:05 2011
New Revision: 137913

URL: http://llvm.org/viewvc/llvm-project?rev=137913&view=rev
Log:
Fixed compilation warning on Linux by fixing the type of a return value.

Modified:
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=137913&r1=137912&r2=137913&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Aug 17 20:19:05 2011
@@ -193,7 +193,7 @@
   bool genResult = false;
   tool_output_file objFile(uniqueObjPath.c_str(), errMsg);
   if (!errMsg.empty())
-    return NULL;
+    return true;
   genResult = this->generateObjectFile(objFile.os(), errMsg);
   objFile.os().close();
   if (objFile.os().has_error()) {



From krasin at chromium.org  Wed Aug 17 20:27:41 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 17 Aug 2011 18:27:41 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5RfYuT_W9VqL3PNx=TRwxfFKhUK=otXSzdk5fqH+3MRWbg@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<CAOei5RfYuT_W9VqL3PNx=TRwxfFKhUK=otXSzdk5fqH+3MRWbg@mail.gmail.com>
Message-ID: <CAOei5ReBLLekCj_auNG1n=MxxsSm4qGL=ny_RBcLoAxK7vxbew@mail.gmail.com>

Also, the license headers in config.sub/config.guess say it's GPL 2 or
newer. So, if you want to stick with GPL 2, it's clearly fine.

You can take a look at the newest config.sub here:
http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD

On Wed, Aug 17, 2011 at 5:53 PM, Ivan Krasin <krasin at google.com> wrote:
> On Wed, Aug 17, 2011 at 5:48 PM, Chris Lattner <clattner at apple.com> wrote:
>>
>> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>>
>>> Err: missed the patch.
>>> Please, find it attached to this message.
>>>
>>> Also, you can take a look at the patch online:
>>> http://codereview.chromium.org/7676009/
>>
>> Hi Ivan,
>>
>> Hopefully dumb question: what are the licensing implications of this? ?Is the new autoconf goop GPL3?
>
> Hi Chris,
>
> I think that the best thing I can do is to add Roland McGrath to this
> thread, who has made the interesting to me change to GNU config.sub.
> I'm not very strong in the licensing questions, but I agree that it's
> extremely important.
>
> Thanks,
> Ivan Krasin
>
>
>>
>> -Chris
>>
>


From bruno.cardoso at gmail.com  Wed Aug 17 21:11:34 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 18 Aug 2011 02:11:34 -0000
Subject: [llvm-commits] [llvm] r137919 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-logic.ll
Message-ID: <20110818021134.9ADD82A6C12C@llvm.org>

Author: bruno
Date: Wed Aug 17 21:11:34 2011
New Revision: 137919

URL: http://llvm.org/viewvc/llvm-project?rev=137919&view=rev
Log:
Cleanup vector logical ops in AVX and add use int versions for simple
v2i64

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx-logic.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=137919&r1=137918&r2=137919&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 17 21:11:34 2011
@@ -1613,21 +1613,22 @@
 ///
 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
                                    SDNode OpNode> {
-  let Pattern = []<dag> in {
-    defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
-         !strconcat(OpcodeStr, "ps"), f128mem,
-         [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
-         [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
-                                   (memopv2i64 addr:$src2)))], 0>, VEX_4V;
-
-    defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
-         !strconcat(OpcodeStr, "pd"), f128mem,
-         [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
-                                   (bc_v2i64 (v2f64 VR128:$src2))))],
-         [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
-                                   (memopv2i64 addr:$src2)))], 0>,
-                                                   OpSize, VEX_4V;
-  }
+  // In AVX no need to add a pattern for 128-bit logical rr ps, because they
+  // are all promoted to v2i64, and the patterns are covered by the int
+  // version. This is needed in SSE only, because v2i64 isn't supported on
+  // SSE1, but only on SSE2.
+  defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
+       !strconcat(OpcodeStr, "ps"), f128mem, [],
+       [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
+                                 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
+
+  defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
+       !strconcat(OpcodeStr, "pd"), f128mem,
+       [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
+                                 (bc_v2i64 (v2f64 VR128:$src2))))],
+       [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
+                                 (memopv2i64 addr:$src2)))], 0>,
+                                                 OpSize, VEX_4V;
   let Constraints = "$src1 = $dst" in {
     defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
          !strconcat(OpcodeStr, "ps"), f128mem,
@@ -2546,15 +2547,14 @@
   def VPANDNrr : PDI<0xDF, MRMSrcReg,
                     (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
-                                              VR128:$src2)))]>, VEX_4V;
+                    [(set VR128:$dst,
+                          (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
 
   def VPANDNrm : PDI<0xDF, MRMSrcMem,
                     (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
-                                              (memopv2i64 addr:$src2))))]>,
-                                              VEX_4V;
+                    [(set VR128:$dst, (X86andnp VR128:$src1,
+                                            (memopv2i64 addr:$src2)))]>, VEX_4V;
 }
 }
 

Modified: llvm/trunk/test/CodeGen/X86/avx-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-logic.ll?rev=137919&r1=137918&r2=137919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-logic.ll Wed Aug 17 21:11:34 2011
@@ -159,3 +159,21 @@
   %2 = bitcast <8 x i32> %and.i to <8 x float>
   ret <8 x float> %2
 }
+
+;;; Test that basic 2 x i64 logic use the integer version on AVX
+
+; CHECK: vpandn  %xmm
+define <2 x i64> @vpandn(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+entry:
+  %y = xor <2 x i64> %a, <i64 -1, i64 -1>
+  %x = and <2 x i64> %a, %y
+  ret <2 x i64> %x
+}
+
+; CHECK: vpand %xmm
+define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
+entry:
+  %x = and <2 x i64> %a, %b
+  ret <2 x i64> %x
+}
+



From delesley at google.com  Wed Aug 17 17:52:13 2011
From: delesley at google.com (Delesley Hutchins)
Date: Wed, 17 Aug 2011 15:52:13 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
Message-ID: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>

This patch adds a topological sort routine for indexed graphs to
llvm/ADT.  This sort routine is currently used to traverse CFGs in
Clang when doing thread safety analysis (patch to be released
shortly).

Link to current code review:  http://codereview.appspot.com/4865045/

 -DeLesley

P.S.  Please cc me directly in any replies.

-- 
DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315
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From supertri at google.com  Wed Aug 17 18:07:08 2011
From: supertri at google.com (Caitlin Sadowski)
Date: Wed, 17 Aug 2011 16:07:08 -0700
Subject: [llvm-commits] small patch: adding support for a variadic list of
 expressions to the Clang attribute tablegen
Message-ID: <CAG2ZtayLh5yHQ-FTzTWBPH9nbrMMtSXnYcg9NbFJ2NicW+engg@mail.gmail.com>

Dear llvm-commits,

Here is a small patch I would like to commit that adds support for a
variadic list of expressions for attribute arguments. I will need this
support for the thread safety analysis, since some attributes contain
multiple arguments of multiple types. Let me know as soon as
convenient if you have any concerns with this patch.

Cheers,

Caitlin
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From eli.friedman at gmail.com  Wed Aug 17 21:57:18 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 17 Aug 2011 19:57:18 -0700
Subject: [llvm-commits] small patch: adding support for a variadic list
 of expressions to the Clang attribute tablegen
In-Reply-To: <CAG2ZtayLh5yHQ-FTzTWBPH9nbrMMtSXnYcg9NbFJ2NicW+engg@mail.gmail.com>
References: <CAG2ZtayLh5yHQ-FTzTWBPH9nbrMMtSXnYcg9NbFJ2NicW+engg@mail.gmail.com>
Message-ID: <CAJdarcGQ5=+hWKOGKegWmu3AvBz51hihs85_NJFDOcX2D2MwsA@mail.gmail.com>

On Wed, Aug 17, 2011 at 4:07 PM, Caitlin Sadowski <supertri at google.com> wrote:
> Dear llvm-commits,
>
> Here is a small patch I would like to commit that adds support for a
> variadic list of expressions for attribute arguments. I will need this
> support for the thread safety analysis, since some attributes contain
> multiple arguments of multiple types. Let me know as soon as
> convenient if you have any concerns with this patch.

Please send patches for that code to cfe-commits; despite the location
in the repository, it's essentially clang code.

-Eli

From nicholas at mxc.ca  Wed Aug 17 22:28:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 17 Aug 2011 20:28:27 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
Message-ID: <4E4C86DB.6020308@mxc.ca>

Chris Lattner wrote:
>
> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>
>> Err: missed the patch.
>> Please, find it attached to this message.
>>
>> Also, you can take a look at the patch online:
>> http://codereview.chromium.org/7676009/
>
> Hi Ivan,
>
> Hopefully dumb question: what are the licensing implications of this?  Is the new autoconf goop GPL3?

No, they're still GPLv2. The diffs make it clear that the license block 
at the top of the files haven't changed.

Nick

From nicholas at mxc.ca  Wed Aug 17 22:30:12 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 17 Aug 2011 20:30:12 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
Message-ID: <4E4C8744.7070905@mxc.ca>

Ivan Krasin wrote:
> Err: missed the patch.
> Please, find it attached to this message.
>
> Also, you can take a look at the patch online:
> http://codereview.chromium.org/7676009/

This drops r132627 to add support for PPC64 on FreeBSD. Roman, why isn't 
that upstream? Should Ivan merge that in to this integrate?

Nick

From stoklund at 2pi.dk  Wed Aug 17 22:56:43 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 17 Aug 2011 20:56:43 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
Message-ID: <40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>


On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:

> This patch adds a topological sort routine for indexed graphs to
> llvm/ADT.  This sort routine is currently used to traverse CFGs in
> Clang when doing thread safety analysis (patch to be released
> shortly).

Could you explain why we need this in addition to include/llvm/ADT/PostOrderIterator.h?

Thanks,
/jakob



From baldrick at free.fr  Wed Aug 17 23:04:22 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 04:04:22 -0000
Subject: [llvm-commits] [dragonegg] r137922 - /dragonegg/trunk/src/Types.cpp
Message-ID: <20110818040422.948592A6C12C@llvm.org>

Author: baldrick
Date: Wed Aug 17 23:04:22 2011
New Revision: 137922

URL: http://llvm.org/viewvc/llvm-project?rev=137922&view=rev
Log:
Completely rewrite how record and union types are converted, considerably
simplifying the code (see the diffstat below).  The same logic is now used
for records and unions (this is needed to handle Fortran equivalences, which
are unions where fields can start at non-zero offsets; support for this was
hacked in before).  Also, bitfields and non-bitfields are handled the same
way by doing everything at the bit level.  Two things to note: (1) currently
zero sized fields never turn up in the LLVM type.  It would be easy enough
to have them turn up, but I'm still pondering this.  (2) In the case of C++
classes involved in multiple inheritance, and other such cases where the
end of a type has to be lopped off, the lopped off type gets replaced with
a bunch of bytes.  As the bit lopped off is usually padding, it would be
nicer to just drop the padding.  This is a possible future improvement; in
any case it is no worse than was done before.

 Types.cpp |  930 ++++++++++++++------------------------------------------------
 1 file changed, 224 insertions(+), 706 deletions(-)


Modified:
    dragonegg/trunk/src/Types.cpp

Modified: dragonegg/trunk/src/Types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=137922&r1=137921&r2=137922&view=diff
==============================================================================
--- dragonegg/trunk/src/Types.cpp (original)
+++ dragonegg/trunk/src/Types.cpp Wed Aug 17 23:04:22 2011
@@ -25,6 +25,8 @@
 #include "dragonegg/ABI.h"
 #include "dragonegg/Cache.h"
 #include "dragonegg/Types.h"
+#include "dragonegg/ADT/IntervalList.h"
+#include "dragonegg/ADT/Range.h"
 
 // LLVM headers
 #include "llvm/Module.h"
@@ -261,6 +263,10 @@
   if (!STy)
     return set_decl_index(decl, INT_MAX);
 
+  // If this is an empty struct then there is no corresponding LLVM field.
+  if (STy->element_begin() == STy->element_end())
+    return set_decl_index(decl, INT_MAX);
+
   // If the field declaration is at a variable or humongous offset then there
   // can be no corresponding LLVM field.
   if (!OffsetIsLLVMCompatible(decl))
@@ -831,734 +837,246 @@
   return FunctionType::get(RetTy, ArgTypes, isVarArg);
 }
 
-//===----------------------------------------------------------------------===//
-//                      RECORD/Struct Conversion Routines
-//===----------------------------------------------------------------------===//
+typedef Range<uint64_t> BitRange;
 
-/// StructTypeConversionInfo - A temporary structure that is used when
-/// translating a RECORD_TYPE to an LLVM type.
+/// TypedRange - A type that applies to a range of bits.  Any part of the type
+/// outside of the range is discarded.  The range may be bigger than the type
+/// in which case any extra bits have an undefined type.
 namespace {
 
-  struct StructTypeConversionInfo {
-    std::vector<Type*> Elements;
-    std::vector<uint64_t> ElementOffsetInBytes;
-    std::vector<uint64_t> ElementSizeInBytes;
-    std::vector<bool> PaddingElement; // True if field is used for padding
-    const TargetData &TD;
-    unsigned GCCStructAlignmentInBytes;
-    bool Packed; // True if struct is packed
-    bool AllBitFields; // True if all struct fields are bit fields
-    bool LastFieldStartsAtNonByteBoundry;
-    unsigned ExtraBitsAvailable; // Non-zero if last field is bit field and it
-                                 // does not use all allocated bits
-
-    StructTypeConversionInfo(TargetMachine &TM, unsigned GCCAlign, bool P)
-      : TD(*TM.getTargetData()), GCCStructAlignmentInBytes(GCCAlign),
-        Packed(P), AllBitFields(true), LastFieldStartsAtNonByteBoundry(false),
-        ExtraBitsAvailable(0) {}
-
-    void lastFieldStartsAtNonByteBoundry(bool value) {
-      LastFieldStartsAtNonByteBoundry = value;
-    }
-
-    void extraBitsAvailable (unsigned E) {
-      ExtraBitsAvailable = E;
-    }
-
-    bool isPacked() { return Packed; }
-
-    void markAsPacked() {
-      Packed = true;
-    }
-
-    void allFieldsAreNotBitFields() {
-      AllBitFields = false;
-      // Next field is not a bitfield.
-      LastFieldStartsAtNonByteBoundry = false;
-    }
-
-    unsigned getGCCStructAlignmentInBytes() const {
-      return GCCStructAlignmentInBytes;
-    }
-
-    /// getTypeAlignment - Return the alignment of the specified type in bytes.
-    ///
-    unsigned getTypeAlignment(Type *Ty) const {
-      return Packed ? 1 : TD.getABITypeAlignment(Ty);
-    }
-
-    /// getTypeSize - Return the size of the specified type in bytes.
-    ///
-    uint64_t getTypeSize(Type *Ty) const {
-      return TD.getTypeAllocSize(Ty);
-    }
-
-    /// fillInLLVMType - Return the LLVM type for the specified object.
-    ///
-    void fillInLLVMType(StructType *STy) const {
-      // Use Packed type if Packed is set or all struct fields are bitfields.
-      // Empty struct is not packed unless packed is set.
-      STy->setBody(Elements, Packed || (!Elements.empty() && AllBitFields));
-    }
-
-    /// getAlignmentAsLLVMStruct - Return the alignment of this struct if it were
-    /// converted to an LLVM type.
-    uint64_t getAlignmentAsLLVMStruct() const {
-      if (Packed || AllBitFields) return 1;
-      unsigned MaxAlign = 1;
-      for (unsigned i = 0, e = Elements.size(); i != e; ++i)
-        MaxAlign = std::max(MaxAlign, getTypeAlignment(Elements[i]));
-      return MaxAlign;
-    }
-
-    /// getSizeAsLLVMStruct - Return the size of this struct if it were converted
-    /// to an LLVM type.  This is the end of last element push an alignment pad at
-    /// the end.
-    uint64_t getSizeAsLLVMStruct() const {
-      if (Elements.empty()) return 0;
-      unsigned MaxAlign = getAlignmentAsLLVMStruct();
-      uint64_t Size = ElementOffsetInBytes.back()+ElementSizeInBytes.back();
-      return (Size+MaxAlign-1) & ~(MaxAlign-1);
-    }
-
-    // If this is a Packed struct and ExtraBitsAvailable is not zero then
-    // remove Extra bytes if ExtraBitsAvailable > 8.
-    void RemoveExtraBytes () {
-
-      unsigned NoOfBytesToRemove = ExtraBitsAvailable/8;
-
-      if (!Packed && !AllBitFields)
-        return;
-
-      if (NoOfBytesToRemove == 0)
-        return;
-
-      Type *LastType = Elements.back();
-      unsigned PadBytes = 0;
-
-      if (LastType->isIntegerTy(8))
-        PadBytes = 1 - NoOfBytesToRemove;
-      else if (LastType->isIntegerTy(16))
-        PadBytes = 2 - NoOfBytesToRemove;
-      else if (LastType->isIntegerTy(32))
-        PadBytes = 4 - NoOfBytesToRemove;
-      else if (LastType->isIntegerTy(64))
-        PadBytes = 8 - NoOfBytesToRemove;
-      else
-        return;
-
-      assert (PadBytes > 0 && "Unable to remove extra bytes");
-
-      // Update last element type and size, element offset is unchanged.
-      Type *Pad =  ArrayType::get(Type::getInt8Ty(Context), PadBytes);
-      unsigned OriginalSize = ElementSizeInBytes.back();
-      Elements.pop_back();
-      Elements.push_back(Pad);
-
-      ElementSizeInBytes.pop_back();
-      ElementSizeInBytes.push_back(OriginalSize - NoOfBytesToRemove);
-    }
-
-    /// ResizeLastElementIfOverlapsWith - If the last element in the struct
-    /// includes the specified byte, remove it. Return true struct
-    /// layout is sized properly. Return false if unable to handle ByteOffset.
-    /// In this case caller should redo this struct as a packed structure.
-    bool ResizeLastElementIfOverlapsWith(uint64_t ByteOffset, tree /*Field*/,
-                                         Type *Ty) {
-      Type *SavedTy = NULL;
-
-      if (!Elements.empty()) {
-        assert(ElementOffsetInBytes.back() <= ByteOffset &&
-               "Cannot go backwards in struct");
-
-        SavedTy = Elements.back();
-        if (ElementOffsetInBytes.back()+ElementSizeInBytes.back() > ByteOffset) {
-          // The last element overlapped with this one, remove it.
-          uint64_t PoppedOffset = ElementOffsetInBytes.back();
-          Elements.pop_back();
-          ElementOffsetInBytes.pop_back();
-          ElementSizeInBytes.pop_back();
-          PaddingElement.pop_back();
-          uint64_t EndOffset = getNewElementByteOffset(1);
-          if (EndOffset < PoppedOffset) {
-            // Make sure that some field starts at the position of the
-            // field we just popped.  Otherwise we might end up with a
-            // gcc non-bitfield being mapped to an LLVM field with a
-            // different offset.
-            Type *Pad = Type::getInt8Ty(Context);
-            if (PoppedOffset != EndOffset + 1)
-              Pad = ArrayType::get(Pad, PoppedOffset - EndOffset);
-            addElement(Pad, EndOffset, PoppedOffset - EndOffset);
-          }
-        }
-      }
-
-      // Get the LLVM type for the field.  If this field is a bitfield, use the
-      // declared type, not the shrunk-to-fit type that GCC gives us in TREE_TYPE.
-      unsigned ByteAlignment = getTypeAlignment(Ty);
-      uint64_t NextByteOffset = getNewElementByteOffset(ByteAlignment);
-      if (NextByteOffset > ByteOffset ||
-          ByteAlignment > getGCCStructAlignmentInBytes()) {
-        // LLVM disagrees as to where this field should go in the natural field
-        // ordering.  Therefore convert to a packed struct and try again.
-        return false;
-      }
-
-      // If alignment won't round us up to the right boundary, insert explicit
-      // padding.
-      if (NextByteOffset < ByteOffset) {
-        uint64_t CurOffset = getNewElementByteOffset(1);
-        Type *Pad = Type::getInt8Ty(Context);
-        if (SavedTy && LastFieldStartsAtNonByteBoundry)
-          // We want to reuse SavedType to access this bit field.
-          // e.g. struct __attribute__((packed)) {
-          //  unsigned int A,
-          //  unsigned short B : 6,
-          //                 C : 15;
-          //  char D; };
-          //  In this example, previous field is C and D is current field.
-          addElement(SavedTy, CurOffset, ByteOffset - CurOffset);
-        else if (ByteOffset - CurOffset != 1)
-          Pad = ArrayType::get(Pad, ByteOffset - CurOffset);
-        addElement(Pad, CurOffset, ByteOffset - CurOffset);
-      }
-      return true;
-    }
-
-    /// FieldNo - Remove the specified field and all of the fields that come after
-    /// it.
-    void RemoveFieldsAfter(unsigned FieldNo) {
-      Elements.erase(Elements.begin()+FieldNo, Elements.end());
-      ElementOffsetInBytes.erase(ElementOffsetInBytes.begin()+FieldNo,
-                                 ElementOffsetInBytes.end());
-      ElementSizeInBytes.erase(ElementSizeInBytes.begin()+FieldNo,
-                               ElementSizeInBytes.end());
-      PaddingElement.erase(PaddingElement.begin()+FieldNo,
-                           PaddingElement.end());
-    }
-
-    /// getNewElementByteOffset - If we add a new element with the specified
-    /// alignment, what byte offset will it land at?
-    uint64_t getNewElementByteOffset(unsigned ByteAlignment) {
-      if (Elements.empty()) return 0;
-      uint64_t LastElementEnd =
-        ElementOffsetInBytes.back() + ElementSizeInBytes.back();
-
-      return (LastElementEnd+ByteAlignment-1) & ~(ByteAlignment-1);
-    }
-
-    /// addElement - Add an element to the structure with the specified type,
-    /// offset and size.
-    void addElement(Type *Ty, uint64_t Offset, uint64_t Size,
-                    bool ExtraPadding = false) {
-      Elements.push_back(Ty);
-      ElementOffsetInBytes.push_back(Offset);
-      ElementSizeInBytes.push_back(Size);
-      PaddingElement.push_back(ExtraPadding);
-      lastFieldStartsAtNonByteBoundry(false);
-      ExtraBitsAvailable = 0;
-    }
-
-    /// getFieldEndOffsetInBytes - Return the byte offset of the byte immediately
-    /// after the specified field.  For example, if FieldNo is 0 and the field
-    /// is 4 bytes in size, this will return 4.
-    uint64_t getFieldEndOffsetInBytes(unsigned FieldNo) const {
-      assert(FieldNo < ElementOffsetInBytes.size() && "Invalid field #!");
-      return ElementOffsetInBytes[FieldNo]+ElementSizeInBytes[FieldNo];
-    }
-
-    /// getEndUnallocatedByte - Return the first byte that isn't allocated at the
-    /// end of a structure.  For example, for {}, it's 0, for {int} it is 4, for
-    /// {int,short}, it is 6.
-    uint64_t getEndUnallocatedByte() const {
-      if (ElementOffsetInBytes.empty()) return 0;
-      return getFieldEndOffsetInBytes(ElementOffsetInBytes.size()-1);
-    }
-
-    void addNewBitField(uint64_t Size, uint64_t Extra,
-                        uint64_t FirstUnallocatedByte);
-
-    void dump() const;
-  };
-
-} // Unnamed namespace.
-
-// Add new element which is a bit field. Size is not the size of bit field,
-// but size of bits required to determine type of new Field which will be
-// used to access this bit field.
-// If possible, allocate a field with room for Size+Extra bits.
-void StructTypeConversionInfo::addNewBitField(uint64_t Size, uint64_t Extra,
-                                              uint64_t FirstUnallocatedByte) {
-
-  // Figure out the LLVM type that we will use for the new field.
-  // Note, Size is not necessarily size of the new field. It indicates
-  // additional bits required after FirstunallocatedByte to cover new field.
-  Type *NewFieldTy = 0;
-
-  // First try an ABI-aligned field including (some of) the Extra bits.
-  // This field must satisfy Size <= w && w <= XSize.
-  uint64_t XSize = Size + Extra;
-  for (unsigned w = NextPowerOf2(std::min(UINT64_C(64), XSize))/2;
-       w >= Size && w >= 8; w /= 2) {
-    if (TD.isIllegalInteger(w))
-      continue;
-    // Would a w-sized integer field be aligned here?
-    const unsigned a = TD.getABIIntegerTypeAlignment(w);
-    if (FirstUnallocatedByte & (a-1) || a > getGCCStructAlignmentInBytes())
-      continue;
-    // OK, use w-sized integer.
-    NewFieldTy = IntegerType::get(Context, w);
-    break;
-  }
-
-  // Try an integer field that holds Size bits.
-  if (!NewFieldTy) {
-    if (Size <= 8)
-      NewFieldTy = Type::getInt8Ty(Context);
-    else if (Size <= 16)
-      NewFieldTy = Type::getInt16Ty(Context);
-    else if (Size <= 32)
-      NewFieldTy = Type::getInt32Ty(Context);
-    else {
-      assert(Size <= 64 && "Bitfield too large!");
-      NewFieldTy = Type::getInt64Ty(Context);
-    }
-  }
-
-  // Check that the alignment of NewFieldTy won't cause a gap in the structure!
-  unsigned ByteAlignment = getTypeAlignment(NewFieldTy);
-  if (FirstUnallocatedByte & (ByteAlignment-1) ||
-      ByteAlignment > getGCCStructAlignmentInBytes()) {
-    // Instead of inserting a nice whole field, insert a small array of ubytes.
-    NewFieldTy = ArrayType::get(Type::getInt8Ty(Context), (Size+7)/8);
-  }
-
-  // Finally, add the new field.
-  addElement(NewFieldTy, FirstUnallocatedByte, getTypeSize(NewFieldTy));
-  ExtraBitsAvailable = NewFieldTy->getPrimitiveSizeInBits() - Size;
-}
-
-void StructTypeConversionInfo::dump() const {
-  raw_ostream &OS = outs();
-  OS << "Info has " << Elements.size() << " fields:\n";
-  for (unsigned i = 0, e = Elements.size(); i != e; ++i) {
-    OS << "  Offset = " << ElementOffsetInBytes[i]
-       << " Size = " << ElementSizeInBytes[i]
-       << " Type = " << *Elements[i] << "\n";
-  }
-  OS.flush();
-}
-
-/// DecodeStructBitField - This method decodes the specified bit-field, adding
-/// or updating the specified StructTypeConversionInfo to reflect it.
-///
-/// Note that in general, we cannot produce a good covering of struct fields for
-/// bitfields.  As such, we only make sure that all bits in a struct that
-/// correspond to a bitfield are represented in the LLVM struct with
-/// (potentially multiple) integer fields of integer type.  This ensures that
-/// initialized globals with bitfields can have the initializers for the
-/// bitfields specified.
-static void DecodeStructBitField(tree Field, StructTypeConversionInfo &Info) {
-  unsigned FieldSizeInBits = TREE_INT_CST_LOW(DECL_SIZE(Field));
-
-  if (FieldSizeInBits == 0)   // Ignore 'int:0', which just affects layout.
-    return;
-
-  // Get the starting offset in the record.
-  uint64_t StartOffsetInBits = getFieldOffsetInBits(Field);
-  uint64_t EndBitOffset    = FieldSizeInBits+StartOffsetInBits;
-
-  // If the last inserted LLVM field completely contains this bitfield, just
-  // ignore this field.
-  if (!Info.Elements.empty()) {
-    uint64_t LastFieldBitOffset = Info.ElementOffsetInBytes.back()*8;
-    unsigned LastFieldBitSize   = Info.ElementSizeInBytes.back()*8;
-    assert(LastFieldBitOffset <= StartOffsetInBits &&
-           "This bitfield isn't part of the last field!");
-    if (EndBitOffset <= LastFieldBitOffset+LastFieldBitSize &&
-        LastFieldBitOffset+LastFieldBitSize >= StartOffsetInBits) {
-      // Already contained in previous field. Update remaining extra bits that
-      // are available.
-      Info.extraBitsAvailable(Info.getEndUnallocatedByte()*8 - EndBitOffset);
-      return;
-    }
-  }
-
-  // Otherwise, this bitfield lives (potentially) partially in the preceding
-  // field and in fields that exist after it.  Add integer-typed fields to the
-  // LLVM struct such that there are no holes in the struct where the bitfield
-  // is: these holes would make it impossible to statically initialize a global
-  // of this type that has an initializer for the bitfield.
-
-  // We want the integer-typed fields as large as possible up to the machine
-  // word size. If there are more bitfields following this one, try to include
-  // them in the same field.
-
-  // Calculate the total number of bits in the continuous group of bitfields
-  // following this one. This is the number of bits that addNewBitField should
-  // try to include.
-  unsigned ExtraSizeInBits = 0;
-  tree LastBitField = 0;
-  for (tree f = TREE_CHAIN(Field); f; f = TREE_CHAIN(f)) {
-    assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
-    if (TREE_CODE(DECL_FIELD_OFFSET(f)) != INTEGER_CST)
-      break;
-    if (isBitfield(f))
-      LastBitField = f;
-    else {
-      // We can use all this bits up to the next non-bitfield.
-      LastBitField = 0;
-      ExtraSizeInBits = getFieldOffsetInBits(f) - EndBitOffset;
-      break;
-    }
-  }
-  // Record ended in a bitfield? Use all of the last byte.
-  if (LastBitField)
-    ExtraSizeInBits = RoundUpToAlignment(getFieldOffsetInBits(LastBitField) +
-      TREE_INT_CST_LOW(DECL_SIZE(LastBitField)), 8) - EndBitOffset;
-
-  // Compute the number of bits that we need to add to this struct to cover
-  // this field.
-  uint64_t FirstUnallocatedByte = Info.getEndUnallocatedByte();
-  uint64_t StartOffsetFromByteBoundry = StartOffsetInBits & 7;
-
-  if (StartOffsetInBits < FirstUnallocatedByte*8) {
-
-    uint64_t AvailableBits = FirstUnallocatedByte * 8 - StartOffsetInBits;
-    // This field's starting point is already allocated.
-    if (StartOffsetFromByteBoundry == 0) {
-      // This field starts at byte boundary. Need to allocate space
-      // for additional bytes not yet allocated.
-      unsigned NumBitsToAdd = FieldSizeInBits - AvailableBits;
-      Info.addNewBitField(NumBitsToAdd, ExtraSizeInBits, FirstUnallocatedByte);
-      return;
-    }
-
-    // Otherwise, this field's starting point is inside previously used byte.
-    // This happens with Packed bit fields. In this case one LLVM Field is
-    // used to access previous field and current field.
-    unsigned prevFieldTypeSizeInBits =
-      Info.ElementSizeInBytes[Info.Elements.size() - 1] * 8;
-
-    unsigned NumBitsRequired = prevFieldTypeSizeInBits
-      + (FieldSizeInBits - AvailableBits);
-
-    if (NumBitsRequired > 64) {
-      // Use bits from previous field.
-      NumBitsRequired = FieldSizeInBits - AvailableBits;
-    } else {
-      // If type used to access previous field is not large enough then
-      // remove previous field and insert new field that is large enough to
-      // hold both fields.
-      Info.RemoveFieldsAfter(Info.Elements.size() - 1);
-      for (unsigned idx = 0; idx < (prevFieldTypeSizeInBits/8); ++idx)
-        FirstUnallocatedByte--;
-    }
-    Info.addNewBitField(NumBitsRequired, ExtraSizeInBits, FirstUnallocatedByte);
-    // Do this after adding Field.
-    Info.lastFieldStartsAtNonByteBoundry(true);
-    return;
-  }
-
-  if (StartOffsetInBits > FirstUnallocatedByte*8) {
-    // If there is padding between the last field and the struct, insert
-    // explicit bytes into the field to represent it.
-    unsigned PadBytes = 0;
-    unsigned PadBits = 0;
-    if (StartOffsetFromByteBoundry != 0) {
-      // New field does not start at byte boundary.
-      PadBits = StartOffsetInBits - (FirstUnallocatedByte*8);
-      PadBytes = PadBits/8;
-      PadBits = PadBits - PadBytes*8;
-    } else
-      PadBytes = StartOffsetInBits/8-FirstUnallocatedByte;
-
-    if (PadBytes) {
-      Type *Pad = Type::getInt8Ty(Context);
-      if (PadBytes != 1)
-        Pad = ArrayType::get(Pad, PadBytes);
-      Info.addElement(Pad, FirstUnallocatedByte, PadBytes);
-    }
-
-    FirstUnallocatedByte = StartOffsetInBits/8;
-    // This field will use some of the bits from this PadBytes, if
-    // starting offset is not at byte boundary.
-    if (StartOffsetFromByteBoundry != 0)
-      FieldSizeInBits += PadBits;
-  }
-
-  // Now, Field starts at FirstUnallocatedByte and everything is aligned.
-  Info.addNewBitField(FieldSizeInBits, ExtraSizeInBits, FirstUnallocatedByte);
-}
-
-/// DecodeStructFields - This method decodes the specified field, if it is a
-/// FIELD_DECL, adding or updating the specified StructTypeConversionInfo to
-/// reflect it.  Return true if field is decoded correctly. Otherwise return
-/// false.
-static bool DecodeStructFields(tree Field, StructTypeConversionInfo &Info) {
-  // Handle bit-fields specially.
-  if (isBitfield(Field)) {
-    // If this field is forcing packed llvm struct then retry entire struct
-    // layout.
-    if (!Info.isPacked()) {
-      // Unnamed bitfield type does not contribute in struct alignment
-      // computations. Use packed llvm structure in such cases.
-      if (!DECL_NAME(Field))
-        return false;
-      // If this field is packed then the struct may need padding fields
-      // before this field.
-      if (DECL_PACKED(Field))
-        return false;
-      // If Field has user defined alignment and it does not match Ty alignment
-      // then convert to a packed struct and try again.
-      if (TYPE_USER_ALIGN(TREE_TYPE(Field))) {
-        Type *Ty = ConvertType(TREE_TYPE(Field));
-        if (TYPE_ALIGN(TREE_TYPE(Field)) !=
-            8 * Info.getTypeAlignment(Ty))
-          return false;
-      }
-    }
-    DecodeStructBitField(Field, Info);
-    return true;
+class TypedRange {
+  BitRange R;      // The range of bits occupied by the type.
+  Type *Ty;        // The type.  May be null if the range is empty.
+  uint64_t Starts; // The first bit of the type is positioned at this offset.
+
+  TypedRange(BitRange r, Type *t, uint64_t starts) :
+    R(r), Ty(t), Starts(starts) {
+    assert((R.empty() || Ty) && "Need type when range not empty!");
+  }
+
+  /// isSafeToReturnContentsDirectly - Return whether the current value for the
+  /// type properly represents the bits in the range and so can be handed to the
+  /// user as is.
+  bool isSafeToReturnContentsDirectly(const TargetData &TD) const {
+    // If there is no type (allowed when the range is empty) then one needs to
+    // be created.
+    if (!Ty)
+      return false;
+    // If the first bit of the type is not the first bit of the range then it
+    // needs to be displaced before being passed to the user.
+    if (!R.empty() && R.getFirst() != Starts)
+      return false;
+    // If the type is wider than the range then it needs to be truncated before
+    // being passed to the user.
+    uint64_t AllocBits = TD.getTypeAllocSizeInBits(Ty);
+    return AllocBits <= R.getWidth();
+  }
+
+public:
+  /// get - Use the given type for the range [first, last).
+  static TypedRange get(uint64_t first, uint64_t last, Type *Ty) {
+    return TypedRange(BitRange(first, last), Ty, first);
+  }
+
+  // Copy assignment operator.
+  TypedRange &operator=(const TypedRange &other) {
+    R = other.R; Ty = other.Ty; Starts = other.Starts;
+    return *this;
+  }
+
+  /// getRange - Return the range occupied by this field.
+  BitRange getRange() const { return R; }
+
+  /// ChangeRangeTo - Change the range occupied by this field.
+  void ChangeRangeTo(BitRange r) { R = r; }
+
+  /// JoinWith - Form the union of this field with another field (which must be
+  /// disjoint from this one).  After this the range will be the convex hull of
+  /// the ranges of the two fields.
+  void JoinWith(const TypedRange &S);
+
+  /// extractContents - Return the contained bits as a type which covers every
+  /// defined bit in the range, yet is guaranteed to have alloc size no larger
+  /// than the width of the range.  Unlike the other methods for this class this
+  /// one requires that the width of the range be a multiple of an address unit,
+  /// which usually means a multiple of 8.
+  Type *extractContents(const TargetData &TD) {
+    /// If the current value for the type can be used to represent the bits in
+    /// the range then just return it.
+    if (isSafeToReturnContentsDirectly(TD))
+      return Ty;
+    // If the range is empty then return a type with zero size.
+    if (R.empty()) {
+      // Return an empty array.  Remember the returned value as an optimization
+      // in case we are called again.
+      Ty = GetUnitType(Context, 0);
+      assert(isSafeToReturnContentsDirectly(TD) && "Unit over aligned?");
+      return Ty;
+    }
+    // Represent the range using an array of bytes.  Remember the returned type
+    // as an optimization in case we are called again.
+    // TODO: If the type only needs to be truncated and has struct or array type
+    // then we could try to do the truncation by dropping or modifying the last
+    // elements of the type, maybe yielding something less horrible.
+    assert(R.getWidth() % BITS_PER_UNIT == 0 && "Boundaries not aligned?");
+    uint64_t Units = R.getWidth() / BITS_PER_UNIT;
+    Ty = GetUnitType(Context, Units);
+    Starts = R.getFirst();
+    assert(isSafeToReturnContentsDirectly(TD) && "Unit over aligned?");
+    return Ty;
   }
+};
 
-  Info.allFieldsAreNotBitFields();
-
-  // Get the starting offset in the record.
-  uint64_t StartOffsetInBits = getFieldOffsetInBits(Field);
-  assert((StartOffsetInBits & 7) == 0 && "Non-bit-field has non-byte offset!");
-  uint64_t StartOffsetInBytes = StartOffsetInBits/8;
-
-  Type *Ty = ConvertType(TREE_TYPE(Field));
+} // Unnamed namespace.
 
-  // If this field is packed then the struct may need padding fields
-  // before this field.
-  if (DECL_PACKED(Field) && !Info.isPacked())
-    return false;
-  // Pop any previous elements out of the struct if they overlap with this one.
-  // This can happen when the C++ front-end overlaps fields with tail padding in
-  // C++ classes.
-  else if (!Info.ResizeLastElementIfOverlapsWith(StartOffsetInBytes, Field, Ty)) {
-    // LLVM disagrees as to where this field should go in the natural field
-    // ordering.  Therefore convert to a packed struct and try again.
-    return false;
-  }
-  else if (TYPE_USER_ALIGN(TREE_TYPE(Field))
-           && (unsigned)DECL_ALIGN(Field) != 8 * Info.getTypeAlignment(Ty)
-           && !Info.isPacked()) {
-    // If Field has user defined alignment and it does not match Ty alignment
-    // then convert to a packed struct and try again.
-    return false;
-  } else
-    // At this point, we know that adding the element will happen at the right
-    // offset.  Add it.
-    Info.addElement(Ty, StartOffsetInBytes, Info.getTypeSize(Ty));
-  return true;
+/// JoinWith - Form the union of this field with another field (which must be
+/// disjoint from this one).  After this the range will be the convex hull of
+/// the ranges of the two fields.
+void TypedRange::JoinWith(const TypedRange &S) {
+  // Use an integer type that covers both ranges.  Turning everything into an
+  // integer like this is pretty nasty, but as we only get here for bitfields
+  // it is fairly harmless.
+  R = R.Join(S.R);
+  Ty = R.empty() ? 0 : IntegerType::get(Context, R.getWidth());
+  Starts = R.empty() ? 0 : R.getFirst();
 }
 
-/// UnionHasOnlyZeroOffsets - Check if a union type has only members with
-/// offsets that are zero, e.g., no Fortran equivalences.
-static bool UnionHasOnlyZeroOffsets(tree type) {
-  for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
-    assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
-    if (!OffsetIsLLVMCompatible(Field))
-      return false;
-    if (getFieldOffsetInBits(Field) != 0)
-      return false;
-  }
-  return true;
-}
+static Type *ConvertRecord(tree type) {
+  // FIXME: This new logic, especially the handling of bitfields, is untested
+  // and probably wrong on big-endian machines.
+  assert(TYPE_SIZE(type) && "Incomplete types should be handled elsewhere!");
 
-/// SelectUnionMember - Find the union member with the largest aligment.  If
-/// there are multiple types with the same alignment, select the one with
-/// the largest size. If the type with max. align is smaller than other types,
-/// then we will add padding later on anyway to match union size.
-static void SelectUnionMember(tree type, StructTypeConversionInfo &Info) {
-  bool FindBiggest = TREE_CODE(type) != QUAL_UNION_TYPE;
-
-  Type *UnionTy = 0;
-  tree UnionField = 0;
-  unsigned MinAlign = ~0U;
-  uint64_t BestSize = FindBiggest ? 0 : ~(uint64_t)0;
-  for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
-    assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
-    assert(DECL_FIELD_OFFSET(Field) && integer_zerop(DECL_FIELD_OFFSET(Field))
-           && "Union with non-zero offset?");
+  IntervalList<TypedRange, uint64_t, 8> Layout;
+  const TargetData &TD = getTargetData();
 
+  // Get the size of the type in bits.  If the type has variable or ginormous
+  // size then it is convenient to pretend it is "infinitely" big.
+  uint64_t TypeSize = isInt64(TYPE_SIZE(type), true) ?
+    getInt64(TYPE_SIZE(type), true) : ~0UL;
+
+  // Record all interesting fields so they can easily be visited backwards.
+  SmallVector<tree, 16> Fields;
+  for (tree field = TYPE_FIELDS(type); field; field = TREE_CHAIN(field)) {
+    assert(TREE_CODE(field) == FIELD_DECL && "Lang data not freed?");
+    // Ignore fields with variable or unknown position since they cannot be
+    // represented by the LLVM type system.
+    if (!OffsetIsLLVMCompatible(field))
+      continue;
     // Skip fields that are known not to be present.
     if (TREE_CODE(type) == QUAL_UNION_TYPE &&
-        integer_zerop(DECL_QUALIFIER(Field)))
+        integer_zerop(DECL_QUALIFIER(field)))
       continue;
-
-    tree TheGccTy = TREE_TYPE(Field);
-
-    // Skip zero-length bitfields.  These are only used for setting the
-    // alignment.
-    if (DECL_BIT_FIELD(Field) && DECL_SIZE(Field) &&
-        integer_zerop(DECL_SIZE(Field)))
-      continue;
-
-    Type *TheTy = ConvertType(TheGccTy);
-    unsigned Align = Info.getTypeAlignment(TheTy);
-    uint64_t Size  = Info.getTypeSize(TheTy);
-
-    // Select TheTy as union type if it is the biggest/smallest field (depending
-    // on the value of FindBiggest).  If more than one field achieves this size
-    // then choose the least aligned.
-    if ((Size == BestSize && Align < MinAlign) ||
-        (FindBiggest && Size > BestSize) ||
-        (!FindBiggest && Size < BestSize)) {
-      UnionTy = TheTy;
-      UnionField = Field;
-      BestSize = Size;
-      MinAlign = Align;
-    }
-
-    // Skip remaining fields if this one is known to be present.
-    if (TREE_CODE(type) == QUAL_UNION_TYPE &&
-        integer_onep(DECL_QUALIFIER(Field)))
-      break;
+    Fields.push_back(field);
   }
 
-  if (UnionTy) {            // Not an empty union.
-    if (8 * Info.getTypeAlignment(UnionTy) > TYPE_ALIGN(type))
-      Info.markAsPacked();
-
-    if (isBitfield(UnionField)) {
-      unsigned FieldSizeInBits = TREE_INT_CST_LOW(DECL_SIZE(UnionField));
-      Info.addNewBitField(FieldSizeInBits, 0, 0);
+  // Process the fields in reverse order.  This is for the benefit of union
+  // types since it means that a zero constant of the LLVM type will fully
+  // initialize the first union member, which is needed if the zero constant
+  // is to be used as the default value for the union type.
+  for (SmallVector<tree, 16>::reverse_iterator I = Fields.rbegin(),
+       E = Fields.rend(); I != E; ++I) {
+    tree field = *I;
+    uint64_t FirstBit = getFieldOffsetInBits(field);
+    assert(FirstBit <= TypeSize && "Field off end of type!");
+    // Determine the width of the field.
+    uint64_t BitWidth;
+    Type *FieldTy = ConvertType(TREE_TYPE(field));
+    if (isInt64(DECL_SIZE(field), true)) {
+      // The field has a size and it is a constant, so use it.  Note that
+      // this size may be smaller than the type size.  For example, if the
+      // next field starts inside alignment padding at the end of this one
+      // then DECL_SIZE will be the size with the padding used by the next
+      // field not included.
+      BitWidth = getInt64(DECL_SIZE(field), true);
     } else {
-      Info.allFieldsAreNotBitFields();
-      Info.addElement(UnionTy, 0, Info.getTypeSize(UnionTy));
+      // If the field has variable or unknown size then use the size of the
+      // LLVM type instead as it gives the minimum size the field may have.
+      assert(FieldTy->isSized() && "Type field has no size!");
+      BitWidth = TD.getTypeAllocSizeInBits(FieldTy);
+      if (FirstBit + BitWidth > TypeSize)
+        BitWidth = TypeSize - FirstBit;
+    }
+    uint64_t LastBit = FirstBit + BitWidth;
+
+    // Set the type of the range of bits occupied by the field to the LLVM type
+    // for the field.
+    Layout.AddInterval(TypedRange::get(FirstBit, LastBit, FieldTy));
+  }
+
+  // Force all fields to begin and end on a byte boundary.  This automagically
+  // takes care of bitfields.
+  Layout.AlignBoundaries(BITS_PER_UNIT);
+
+  // Determine whether to return a packed struct type.  If returning an ordinary
+  // struct would result in a type that is more aligned than the GCC type then
+  // return a packed struct instead.  If a field's alignment would make it start
+  // after its desired position then also use a packed struct type.
+  bool Pack = false;
+  unsigned MaxAlign = TYPE_ALIGN(type);
+  for (unsigned i = 0, e = Layout.getNumIntervals(); i != e; ++i) {
+    TypedRange F = Layout.getInterval(i);
+    uint64_t First = F.getRange().getFirst();
+    Type *Ty = F.extractContents(TD);
+    unsigned Alignment = TD.getABITypeAlignment(Ty) * 8;
+    if (Alignment > MaxAlign || First % Alignment) {
+      Pack = true;
+      break;
     }
   }
-}
 
-/// ConvertRECORD - Convert a RECORD_TYPE, UNION_TYPE or QUAL_UNION_TYPE to
-/// an LLVM type.
-// A note on C++ virtual base class layout.  Consider the following example:
-// class A { public: int i0; };
-// class B : public virtual A { public: int i1; };
-// class C : public virtual A { public: int i2; };
-// class D : public virtual B, public virtual C { public: int i3; };
-//
-// The TYPE nodes gcc builds for classes represent that class as it looks
-// standing alone.  Thus B is size 12 and looks like { vptr; i2; baseclass A; }
-// However, this is not the layout used when that class is a base class for
-// some other class, yet the same TYPE node is still used.  D in the above has
-// both a BINFO list entry and a FIELD that reference type B, but the virtual
-// base class A within B is not allocated in that case; B-within-D is only
-// size 8.  The correct size is in the FIELD node (does not match the size
-// in its child TYPE node.)  The fields to be omitted from the child TYPE,
-// as far as I can tell, are always the last ones; but also, there is a
-// TYPE_DECL node sitting in the middle of the FIELD list separating virtual
-// base classes from everything else.
-//
-// Similarly, a nonvirtual base class which has virtual base classes might
-// not contain those virtual base classes when used as a nonvirtual base class.
-// There is seemingly no way to detect this except for the size differential.
-//
-// For LLVM purposes, we build a new type for B-within-D that
-// has the correct size and layout for that usage.
-static Type *ConvertRECORD(tree type) {
-  assert(TYPE_SIZE(type) && "Incomplete types should be handled elsewhere!");
-
-  assert(getCachedType(type) && isa<StructType>(getCachedType(type)) &&
-         cast<StructType>(getCachedType(type))->isOpaque() &&
-         "Incorrect placeholder for struct type!");
-
-  // Record those fields which will be converted to LLVM fields.
-  SmallVector<std::pair<tree, uint64_t>, 32> Fields;
-  for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
-    assert(TREE_CODE(Field) == FIELD_DECL && "Lang data not freed?");
-    if (OffsetIsLLVMCompatible(Field))
-      Fields.push_back(std::make_pair(Field, getFieldOffsetInBits(Field)));
-  }
-
-  // The fields are almost always sorted, but occasionally not.  Sort them by
-  // field offset.
-  for (unsigned i = 1, e = Fields.size(); i < e; i++)
-    for (unsigned j = i; j && Fields[j].second < Fields[j-1].second; j--)
-      std::swap(Fields[j], Fields[j-1]);
-
-  StructTypeConversionInfo *Info =
-    new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN(type) / 8,
-                                 TYPE_PACKED(type));
-
-  // Convert over all of the elements of the struct.
-  // Workaround to get Fortran EQUIVALENCE working.
-  // TODO: Unify record and union logic and handle this optimally.
-  bool HasOnlyZeroOffsets = TREE_CODE(type) != RECORD_TYPE &&
-    UnionHasOnlyZeroOffsets(type);
-  if (HasOnlyZeroOffsets) {
-    SelectUnionMember(type, *Info);
-  } else {
-    // Convert over all of the elements of the struct.
-    bool retryAsPackedStruct = false;
-    for (unsigned i = 0, e = Fields.size(); i < e; i++)
-      if (DecodeStructFields(Fields[i].first, *Info) == false) {
-        retryAsPackedStruct = true;
-        break;
+  // Create the elements that will make up the struct type.  As well as the
+  // fields themselves there may also be padding elements.
+  std::vector<Type*> Elts;
+  Elts.reserve(Layout.getNumIntervals());
+  uint64_t EndOfPrevious = 0; // Offset of first bit after previous element.
+  for (unsigned i = 0, e = Layout.getNumIntervals(); i != e; ++i) {
+    TypedRange F = Layout.getInterval(i);
+    uint64_t First = F.getRange().getFirst();
+    Type *Ty = F.extractContents(TD);
+    assert(EndOfPrevious <= First && "Previous field too big!");
+
+    // If there is a gap then we may need to fill it with padding.
+    if (First > EndOfPrevious) {
+      // There is a gap between the end of the previous field and the start of
+      // this one.  The alignment of the field contents may mean that it will
+      // start at the right offset anyway, but if not then insert padding.
+      bool NeedPadding = true;
+      if (!Pack) {
+        // If the field's alignment will take care of the gap then there is no
+        // need for padding.
+        unsigned Alignment = TD.getABITypeAlignment(Ty) * 8;
+        if (First == (EndOfPrevious + Alignment - 1) / Alignment * Alignment)
+          NeedPadding = false;
       }
-
-    if (retryAsPackedStruct) {
-      delete Info;
-      Info = new StructTypeConversionInfo(*TheTarget, TYPE_ALIGN(type) / 8,
-                                          true);
-      for (unsigned i = 0, e = Fields.size(); i < e; i++)
-        if (DecodeStructFields(Fields[i].first, *Info) == false) {
-          assert(0 && "Unable to decode struct fields.");
-        }
-    }
-  }
-
-  // Insert tail padding if the LLVM struct requires explicit tail padding to
-  // be the same size as the GCC struct or union.  This handles, e.g., "{}" in
-  // C++, and cases where a union has larger alignment than the largest member
-  // does.
-  if (TYPE_SIZE(type) && TREE_CODE(TYPE_SIZE(type)) == INTEGER_CST) {
-    uint64_t GCCTypeSize = getInt64(TYPE_SIZE_UNIT(type), true);
-    uint64_t LLVMStructSize = Info->getSizeAsLLVMStruct();
-
-    if (LLVMStructSize > GCCTypeSize) {
-      Info->RemoveExtraBytes();
-      LLVMStructSize = Info->getSizeAsLLVMStruct();
-    }
-
-    if (LLVMStructSize != GCCTypeSize) {
-      assert(LLVMStructSize < GCCTypeSize &&
-             "LLVM type size doesn't match GCC type size!");
-      uint64_t LLVMLastElementEnd = Info->getNewElementByteOffset(1);
-
-      // If only one byte is needed then insert i8.
-      if (GCCTypeSize-LLVMLastElementEnd == 1)
-        Info->addElement(Type::getInt8Ty(Context), 1, 1);
-      else {
-        if (((GCCTypeSize-LLVMStructSize) % 4) == 0 &&
-            (Info->getAlignmentAsLLVMStruct() %
-             Info->getTypeAlignment(Type::getInt32Ty(Context))) == 0) {
-          // Insert array of i32.
-          unsigned Int32ArraySize = (GCCTypeSize-LLVMStructSize) / 4;
-          Type *PadTy =
-            ArrayType::get(Type::getInt32Ty(Context), Int32ArraySize);
-          Info->addElement(PadTy, GCCTypeSize - LLVMLastElementEnd,
-                           Int32ArraySize, true /* Padding Element */);
-        } else {
-          Type *PadTy = ArrayType::get(Type::getInt8Ty(Context),
-                                             GCCTypeSize-LLVMStructSize);
-          Info->addElement(PadTy, GCCTypeSize - LLVMLastElementEnd,
-                           GCCTypeSize - LLVMLastElementEnd,
-                           true /* Padding Element */);
-        }
+      if (NeedPadding) {
+        // Fill the gap with an array of bytes.
+        assert((First - EndOfPrevious) % BITS_PER_UNIT == 0 &&
+               "Non-unit field boundaries!");
+        uint64_t Units = (First - EndOfPrevious) / BITS_PER_UNIT;
+        Elts.push_back(GetUnitType(Context, Units));
       }
     }
-  } else
-    Info->RemoveExtraBytes();
-
-  StructType *ResultTy = cast<StructType>(getCachedType(type));
-  Info->fillInLLVMType(ResultTy);
 
-  return ResultTy;
+    // Append the field.
+    Elts.push_back(Ty);
+    EndOfPrevious = First + TD.getTypeAllocSizeInBits(Ty);
+  }
+
+  // If the GCC type has a sensible size then we guarantee that LLVM type has
+  // the same size.  If needed, append padding to ensure this.
+  if (TypeSize != ~0UL && EndOfPrevious < TypeSize) {
+    assert((TypeSize - EndOfPrevious) % BITS_PER_UNIT == 0 &&
+           "Non-unit type size?");
+    uint64_t Units = (TypeSize - EndOfPrevious) / BITS_PER_UNIT;
+    Elts.push_back(GetUnitType(Context, Units));
+  }
+
+  // OK, we're done.  Add the fields to the struct type and return it.
+  Type *STy = getCachedType(type);
+  assert(STy && isa<StructType>(STy) && cast<StructType>(STy)->isOpaque() &&
+         "Incorrect placeholder for struct type!");
+  cast<StructType>(STy)->setBody(Elts, Pack);
+  return STy;
 }
 
 /// mayRecurse - Return true if converting this type may require breaking a
@@ -1848,7 +1366,7 @@
   case QUAL_UNION_TYPE:
   case RECORD_TYPE:
   case UNION_TYPE:
-    return llvm_set_type(type, ConvertRECORD(type));
+    return llvm_set_type(type, ConvertRecord(type));
 
   case POINTER_TYPE:
   case REFERENCE_TYPE: {



From krasin at google.com  Wed Aug 17 23:13:33 2011
From: krasin at google.com (Ivan Krasin)
Date: Wed, 17 Aug 2011 21:13:33 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <4E4C8744.7070905@mxc.ca>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<4E4C8744.7070905@mxc.ca>
Message-ID: <CAOei5RcKrjQA8cUW9jTgfrgWnK8qnhfppQtAmnYEjDUF4kRvTA@mail.gmail.com>

Nick, thanks for the catch.

Please, find the updated patch attached. Also, I've updated the patch
at http://codereview.chromium.org/7676009/

Roman, do you think it makes sense to push into the mainline GNU config.guess?

Ivan


On Wed, Aug 17, 2011 at 8:30 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Ivan Krasin wrote:
>>
>> Err: missed the patch.
>> Please, find it attached to this message.
>>
>> Also, you can take a look at the patch online:
>> http://codereview.chromium.org/7676009/
>
> This drops r132627 to add support for PPC64 on FreeBSD. Roman, why isn't
> that upstream? Should Ivan merge that in to this integrate?
>
> Nick
>
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From chandlerc at google.com  Wed Aug 17 23:17:13 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Wed, 17 Aug 2011 21:17:13 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
Message-ID: <CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>

On Wed, Aug 17, 2011 at 8:56 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

>
> On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:
>
> > This patch adds a topological sort routine for indexed graphs to
> > llvm/ADT.  This sort routine is currently used to traverse CFGs in
> > Clang when doing thread safety analysis (patch to be released
> > shortly).
>
> Could you explain why we need this in addition to
> include/llvm/ADT/PostOrderIterator.h?
>

FYI, I'm not terribly familiar w/ PostOrderIterator (so maybe it would
actually serve here), but JSYK, the motivating use case is in a Clang
patch:
http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20110815/045262.html
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From nicholas at mxc.ca  Wed Aug 17 23:33:20 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 17 Aug 2011 21:33:20 -0700
Subject: [llvm-commits] [llvm] r137890
	-	/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
In-Reply-To: <20110817224939.2C5532A6C12C@llvm.org>
References: <20110817224939.2C5532A6C12C@llvm.org>
Message-ID: <4E4C9610.1020409@mxc.ca>

Devang Patel wrote:
> Author: dpatel
> Date: Wed Aug 17 17:49:38 2011
> New Revision: 137890
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137890&view=rev
> Log:
> Do not use DebugInfoFinder. Extract debug info directly from llvm.dbg.cu named mdnode.

Hi Devang,

This all still crashes on all programs because GCOVProfiling still tries 
to use SP.getCompileUnit() which is now an assert when called.

How can I tie a function/subprogram to the translation-unit/compile-unit 
it came from? The purpose is to ensure that after merging multiple .bc 
files, we still emit the individual .gcno/.gcda files -- one for each 
original .o file -- as we would have before.

Nick

>
> Modified:
>      llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
>
> Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137890&r1=137889&r2=137890&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
> +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Wed Aug 17 17:49:38 2011
> @@ -60,11 +60,11 @@
>       bool runOnModule(Module&M);
>
>       // Create the GCNO files for the Module based on DebugInfo.
> -    void emitGCNO(DebugInfoFinder&DIF);
> +    void emitGCNO();
>
>       // Modify the program to track transitions along edges and call into the
>       // profiling runtime to emit .gcda files when run.
> -    bool emitProfileArcs(DebugInfoFinder&DIF);
> +    bool emitProfileArcs();
>
>       // Get pointers to the functions in the runtime library.
>       Constant *getStartFileFunc();
> @@ -86,8 +86,7 @@
>
>       // Add the function to write out all our counters to the global destructor
>       // list.
> -    void insertCounterWriteout(DebugInfoFinder&,
> -                               SmallVector<std::pair<GlobalVariable *,
> +    void insertCounterWriteout(SmallVector<std::pair<GlobalVariable *,
>                                                        MDNode *>, 8>  &);
>
>       std::string mangleName(DICompileUnit CU, std::string NewStem);
> @@ -353,66 +352,66 @@
>     this->M =&M;
>     Ctx =&M.getContext();
>
> -  DebugInfoFinder DIF;
> -  DIF.processModule(M);
> -
> -  if (EmitNotes) emitGCNO(DIF);
> -  if (EmitData) return emitProfileArcs(DIF);
> +  if (EmitNotes) emitGCNO();
> +  if (EmitData) return emitProfileArcs();
>     return false;
>   }
>
> -void GCOVProfiler::emitGCNO(DebugInfoFinder&DIF) {
> +void GCOVProfiler::emitGCNO() {
>     DenseMap<const MDNode *, raw_fd_ostream *>  GcnoFiles;
> -  for (DebugInfoFinder::iterator I = DIF.compile_unit_begin(),
> -           E = DIF.compile_unit_end(); I != E; ++I) {
> -    // Each compile unit gets its own .gcno file. This means that whether we run
> -    // this pass over the original .o's as they're produced, or run it after
> -    // LTO, we'll generate the same .gcno files.
> -
> -    DICompileUnit CU(*I);
> -    raw_fd_ostream *&out = GcnoFiles[CU];
> -    std::string ErrorInfo;
> -    out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
> -                             raw_fd_ostream::F_Binary);
> -    if (!Use402Format)
> -      out->write("oncg*404MVLL", 12);
> -    else
> -      out->write("oncg*204MVLL", 12);
> -  }
> -
> -  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
> -           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
> -    DISubprogram SP(*SPI);
> -    raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
> -
> -    Function *F = SP.getFunction();
> -    if (!F) continue;
> -    GCOVFunction Func(SP, os, Use402Format);
> -
> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> -      GCOVBlock&Block = Func.getBlock(BB);
> -      TerminatorInst *TI = BB->getTerminator();
> -      if (int successors = TI->getNumSuccessors()) {
> -        for (int i = 0; i != successors; ++i) {
> -          Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
> +  if (CU_Nodes) {
> +    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
> +      // Each compile unit gets its own .gcno file. This means that whether we run
> +      // this pass over the original .o's as they're produced, or run it after
> +      // LTO, we'll generate the same .gcno files.
> +
> +      DICompileUnit CU(CU_Nodes->getOperand(i));
> +      raw_fd_ostream *&out = GcnoFiles[CU];
> +      std::string ErrorInfo;
> +      out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
> +                               raw_fd_ostream::F_Binary);
> +      if (!Use402Format)
> +        out->write("oncg*404MVLL", 12);
> +      else
> +        out->write("oncg*204MVLL", 12);
> +
> +      DIArray SPs = CU.getSubprograms();
> +      for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
> +        DISubprogram SP(SPs.getElement(i));
> +        if (!SP.Verify()) continue;
> +        raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
> +
> +        Function *F = SP.getFunction();
> +        if (!F) continue;
> +        GCOVFunction Func(SP, os, Use402Format);
> +
> +        for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> +          GCOVBlock&Block = Func.getBlock(BB);
> +          TerminatorInst *TI = BB->getTerminator();
> +          if (int successors = TI->getNumSuccessors()) {
> +            for (int i = 0; i != successors; ++i) {
> +              Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
> +            }
> +          } else if (isa<ReturnInst>(TI)) {
> +            Block.addEdge(Func.getReturnBlock());
> +          }
> +
> +          uint32_t Line = 0;
> +          for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
> +            const DebugLoc&Loc = I->getDebugLoc();
> +            if (Loc.isUnknown()) continue;
> +            if (Line == Loc.getLine()) continue;
> +            Line = Loc.getLine();
> +            if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
> +
> +            GCOVLines&Lines = Block.getFile(SP.getFilename());
> +            Lines.addLine(Loc.getLine());
> +          }
>           }
> -      } else if (isa<ReturnInst>(TI)) {
> -        Block.addEdge(Func.getReturnBlock());
> -      }
> -
> -      uint32_t Line = 0;
> -      for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
> -        const DebugLoc&Loc = I->getDebugLoc();
> -        if (Loc.isUnknown()) continue;
> -        if (Line == Loc.getLine()) continue;
> -        Line = Loc.getLine();
> -        if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
> -
> -        GCOVLines&Lines = Block.getFile(SP.getFilename());
> -        Lines.addLine(Loc.getLine());
> +        Func.writeOut();
>         }
>       }
> -    Func.writeOut();
>     }
>
>     for (DenseMap<const MDNode *, raw_fd_ostream *>::iterator
> @@ -424,104 +423,107 @@
>     }
>   }
>
> -bool GCOVProfiler::emitProfileArcs(DebugInfoFinder&DIF) {
> -  if (DIF.subprogram_begin() == DIF.subprogram_end())
> -    return false;
> -
> -  SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  CountersBySP;
> -  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
> -           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
> -    DISubprogram SP(*SPI);
> -    Function *F = SP.getFunction();
> -    if (!F) continue;
> -
> -    unsigned Edges = 0;
> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> -      TerminatorInst *TI = BB->getTerminator();
> -      if (isa<ReturnInst>(TI))
> -        ++Edges;
> -      else
> -        Edges += TI->getNumSuccessors();
> -    }
> -
> -    ArrayType *CounterTy =
> +bool GCOVProfiler::emitProfileArcs() {
> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
> +  if (!CU_Nodes) return false;
> +
> +  bool Result = false;
> +  for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
> +    DICompileUnit CU(CU_Nodes->getOperand(i));
> +    DIArray SPs = CU.getSubprograms();
> +    SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  CountersBySP;
> +    for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
> +      DISubprogram SP(SPs.getElement(i));
> +      if (!SP.Verify()) continue;
> +      Function *F = SP.getFunction();
> +      if (!F) continue;
> +      if (!Result) Result = true;
> +      unsigned Edges = 0;
> +      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> +        TerminatorInst *TI = BB->getTerminator();
> +        if (isa<ReturnInst>(TI))
> +          ++Edges;
> +        else
> +          Edges += TI->getNumSuccessors();
> +      }
> +
> +      ArrayType *CounterTy =
>           ArrayType::get(Type::getInt64Ty(*Ctx), Edges);
> -    GlobalVariable *Counters =
> +      GlobalVariable *Counters =
>           new GlobalVariable(*M, CounterTy, false,
>                              GlobalValue::InternalLinkage,
>                              Constant::getNullValue(CounterTy),
>                              "__llvm_gcov_ctr", 0, false, 0);
> -    CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
> -
> -    UniqueVector<BasicBlock *>  ComplexEdgePreds;
> -    UniqueVector<BasicBlock *>  ComplexEdgeSuccs;
> -
> -    unsigned Edge = 0;
> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> -      TerminatorInst *TI = BB->getTerminator();
> -      int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
> -      if (Successors) {
> -        IRBuilder<>  Builder(TI);
> -
> -        if (Successors == 1) {
> -          Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
> -                                                              Edge);
> -          Value *Count = Builder.CreateLoad(Counter);
> -          Count = Builder.CreateAdd(Count,
> -                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
> -          Builder.CreateStore(Count, Counter);
> -        } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
> -          Value *Sel = Builder.CreateSelect(
> +      CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
> +
> +      UniqueVector<BasicBlock *>  ComplexEdgePreds;
> +      UniqueVector<BasicBlock *>  ComplexEdgeSuccs;
> +
> +      unsigned Edge = 0;
> +      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
> +        TerminatorInst *TI = BB->getTerminator();
> +        int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
> +        if (Successors) {
> +          IRBuilder<>  Builder(TI);
> +
> +          if (Successors == 1) {
> +            Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
> +                                                                Edge);
> +            Value *Count = Builder.CreateLoad(Counter);
> +            Count = Builder.CreateAdd(Count,
> +                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
> +            Builder.CreateStore(Count, Counter);
> +          } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
> +            Value *Sel = Builder.CreateSelect(
>                 BI->getCondition(),
>                 ConstantInt::get(Type::getInt64Ty(*Ctx), Edge),
>                 ConstantInt::get(Type::getInt64Ty(*Ctx), Edge + 1));
> -          SmallVector<Value *, 2>  Idx;
> -          Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
> -          Idx.push_back(Sel);
> -          Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
> -          Value *Count = Builder.CreateLoad(Counter);
> -          Count = Builder.CreateAdd(Count,
> -                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
> -          Builder.CreateStore(Count, Counter);
> -        } else {
> -          ComplexEdgePreds.insert(BB);
> -          for (int i = 0; i != Successors; ++i)
> -            ComplexEdgeSuccs.insert(TI->getSuccessor(i));
> +            SmallVector<Value *, 2>  Idx;
> +            Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
> +            Idx.push_back(Sel);
> +            Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
> +            Value *Count = Builder.CreateLoad(Counter);
> +            Count = Builder.CreateAdd(Count,
> +                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
> +            Builder.CreateStore(Count, Counter);
> +          } else {
> +            ComplexEdgePreds.insert(BB);
> +            for (int i = 0; i != Successors; ++i)
> +              ComplexEdgeSuccs.insert(TI->getSuccessor(i));
> +          }
> +          Edge += Successors;
>           }
> -        Edge += Successors;
>         }
> -    }
> -
> -    if (!ComplexEdgePreds.empty()) {
> -      GlobalVariable *EdgeTable =
> +
> +      if (!ComplexEdgePreds.empty()) {
> +        GlobalVariable *EdgeTable =
>             buildEdgeLookupTable(F, Counters,
>                                  ComplexEdgePreds, ComplexEdgeSuccs);
> -      GlobalVariable *EdgeState = getEdgeStateValue();
> -
> -      Type *Int32Ty = Type::getInt32Ty(*Ctx);
> -      for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
> -        IRBuilder<>  Builder(ComplexEdgePreds[i+1]->getTerminator());
> -        Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
> -      }
> -      for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
> -        // call runtime to perform increment
> -        BasicBlock::iterator InsertPt =
> -          ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
> -        IRBuilder<>  Builder(InsertPt);
> -        Value *CounterPtrArray =
> +        GlobalVariable *EdgeState = getEdgeStateValue();
> +
> +        Type *Int32Ty = Type::getInt32Ty(*Ctx);
> +        for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
> +          IRBuilder<>  Builder(ComplexEdgePreds[i+1]->getTerminator());
> +          Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
> +        }
> +        for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
> +          // call runtime to perform increment
> +          BasicBlock::iterator InsertPt =
> +            ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
> +          IRBuilder<>  Builder(InsertPt);
> +          Value *CounterPtrArray =
>               Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,
>                                                  i * ComplexEdgePreds.size());
> -        Builder.CreateCall2(getIncrementIndirectCounterFunc(),
> -                            EdgeState, CounterPtrArray);
> -        // clear the predecessor number
> -        Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
> +          Builder.CreateCall2(getIncrementIndirectCounterFunc(),
> +                              EdgeState, CounterPtrArray);
> +          // clear the predecessor number
> +          Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
> +        }
>         }
>       }
> +    insertCounterWriteout(CountersBySP);
>     }
> -
> -  insertCounterWriteout(DIF, CountersBySP);
> -
> -  return true;
> +  return Result;
>   }
>
>   // All edges with successors that aren't branches are "complex", because it
> @@ -627,7 +629,6 @@
>   }
>
>   void GCOVProfiler::insertCounterWriteout(
> -    DebugInfoFinder&DIF,
>       SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  &CountersBySP) {
>     FunctionType *WriteoutFTy =
>         FunctionType::get(Type::getVoidTy(*Ctx), false);
> @@ -643,29 +644,31 @@
>     Constant *EmitArcs = getEmitArcsFunc();
>     Constant *EndFile = getEndFileFunc();
>
> -  for (DebugInfoFinder::iterator CUI = DIF.compile_unit_begin(),
> -           CUE = DIF.compile_unit_end(); CUI != CUE; ++CUI) {
> -    DICompileUnit compile_unit(*CUI);
> -    std::string FilenameGcda = mangleName(compile_unit, "gcda");
> -    Builder.CreateCall(StartFile,
> -                       Builder.CreateGlobalStringPtr(FilenameGcda));
> -    for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
> +  if (CU_Nodes) {
> +    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
> +      DICompileUnit compile_unit(CU_Nodes->getOperand(i));
> +      std::string FilenameGcda = mangleName(compile_unit, "gcda");
> +      Builder.CreateCall(StartFile,
> +                         Builder.CreateGlobalStringPtr(FilenameGcda));
> +      for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
>                I = CountersBySP.begin(), E = CountersBySP.end();
> -         I != E; ++I) {
> -      DISubprogram SP(I->second);
> -      intptr_t ident = reinterpret_cast<intptr_t>(I->second);
> -      Builder.CreateCall2(EmitFunction,
> -                          ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
> -                          Builder.CreateGlobalStringPtr(SP.getName()));
> -
> -      GlobalVariable *GV = I->first;
> -      unsigned Arcs =
> +           I != E; ++I) {
> +        DISubprogram SP(I->second);
> +        intptr_t ident = reinterpret_cast<intptr_t>(I->second);
> +        Builder.CreateCall2(EmitFunction,
> +                            ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
> +                            Builder.CreateGlobalStringPtr(SP.getName()));
> +
> +        GlobalVariable *GV = I->first;
> +        unsigned Arcs =
>             cast<ArrayType>(GV->getType()->getElementType())->getNumElements();
> -      Builder.CreateCall2(EmitArcs,
> -                          ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
> -                          Builder.CreateConstGEP2_64(GV, 0, 0));
> +        Builder.CreateCall2(EmitArcs,
> +                            ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
> +                            Builder.CreateConstGEP2_64(GV, 0, 0));
> +      }
> +      Builder.CreateCall(EndFile);
>       }
> -    Builder.CreateCall(EndFile);
>     }
>     Builder.CreateRetVoid();
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From baldrick at free.fr  Wed Aug 17 23:33:42 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 04:33:42 -0000
Subject: [llvm-commits] [dragonegg] r137924 - /dragonegg/trunk/README
Message-ID: <20110818043342.DF8E12A6C12C@llvm.org>

Author: baldrick
Date: Wed Aug 17 23:33:42 2011
New Revision: 137924

URL: http://llvm.org/viewvc/llvm-project?rev=137924&view=rev
Log:
Explain that enabling the GCC optimizers disables the most LLVM IR optimizers
by default.

Modified:
    dragonegg/trunk/README

Modified: dragonegg/trunk/README
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/README?rev=137924&r1=137923&r2=137924&view=diff
==============================================================================
--- dragonegg/trunk/README (original)
+++ dragonegg/trunk/README Wed Aug 17 23:33:42 2011
@@ -111,8 +111,10 @@
   to change this, disassociating the LLVM optimization level from the GCC one.
 
 -fplugin-arg-dragonegg-enable-gcc-optzns
-  Run the GCC tree optimizers as well as the LLVM IR optimizers.  Only early GCC
-  optimizations are performed.  Normally all GCC optimizations are disabled.
+  Run the GCC tree optimizers rather than the LLVM IR optimizers (normally all
+  GCC optimizations are disabled).  This disables the LLVM IR optimizers, except
+  for a small set of cleanup passes (to override this and run the usual set of
+  LLVM IR optimizers, use the -fplugin-arg-dragonegg-llvm-ir-optimize option).
 
 -fplugin-arg-dragonegg-save-gcc-output
   GCC assembler output is normally redirected to /dev/null so that it doesn't



From stoklund at 2pi.dk  Thu Aug 18 00:00:10 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 17 Aug 2011 22:00:10 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
Message-ID: <0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>


On Aug 17, 2011, at 9:17 PM, Chandler Carruth wrote:

> On Wed, Aug 17, 2011 at 8:56 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> 
> On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:
> 
> > This patch adds a topological sort routine for indexed graphs to
> > llvm/ADT.  This sort routine is currently used to traverse CFGs in
> > Clang when doing thread safety analysis (patch to be released
> > shortly).
> 
> Could you explain why we need this in addition to include/llvm/ADT/PostOrderIterator.h?
> 
> FYI, I'm not terribly familiar w/ PostOrderIterator (so maybe it would actually serve here), but JSYK, the motivating use case is in a Clang patch: http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20110815/045262.html

I see.

AFAICT, the existing RPO iterator will give you the exact same ordering of blocks, at least it will give you a topo-sort of the graph after removing back-edges.

You can detect back-edges by keeping track of visited blocks in a BitVector as you iterate through the RPO.

/jakob

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From isanbard at gmail.com  Thu Aug 18 00:25:24 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 05:25:24 -0000
Subject: [llvm-commits] [llvm] r137926 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110818052524.2068B2A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 00:25:23 2011
New Revision: 137926

URL: http://llvm.org/viewvc/llvm-project?rev=137926&view=rev
Log:
Split out the analysis updating code into a helper function. No intended
functionality change.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137926&r1=137925&r2=137926&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 00:25:23 2011
@@ -314,6 +314,79 @@
   return New;
 }
 
+namespace {
+
+/// UpdateAnalysisInformation - Update DominatorTree, LoopInfo, and LCCSA
+/// analysis information.
+void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB,
+                               BasicBlock *const *Preds,
+                               unsigned NumPreds, Pass *P, bool &HasLoopExit) {
+  if (!P) return;
+
+  LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>();
+  Loop *L = LI ? LI->getLoopFor(OldBB) : 0;
+  bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
+
+  // If we need to preserve loop analyses, collect some information about how
+  // this split will affect loops.
+  bool IsLoopEntry = !!L;
+  bool SplitMakesNewLoopHeader = false;
+  if (LI) {
+    for (unsigned i = 0; i != NumPreds; ++i) {
+      // If we need to preserve LCSSA, determine if any of the preds is a loop
+      // exit.
+      if (PreserveLCSSA)
+        if (Loop *PL = LI->getLoopFor(Preds[i]))
+          if (!PL->contains(OldBB))
+            HasLoopExit = true;
+
+      // If we need to preserve LoopInfo, note whether any of the preds crosses
+      // an interesting loop boundary.
+      if (!L) continue;
+      if (L->contains(Preds[i]))
+        IsLoopEntry = false;
+      else
+        SplitMakesNewLoopHeader = true;
+    }
+  }
+
+  // Update dominator tree if available.
+  DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
+  if (DT)
+    DT->splitBlock(NewBB);
+
+  if (!L) return;
+
+  if (IsLoopEntry) {
+    // Add the new block to the nearest enclosing loop (and not an adjacent
+    // loop). To find this, examine each of the predecessors and determine which
+    // loops enclose them, and select the most-nested loop which contains the
+    // loop containing the block being split.
+    Loop *InnermostPredLoop = 0;
+    for (unsigned i = 0; i != NumPreds; ++i)
+      if (Loop *PredLoop = LI->getLoopFor(Preds[i])) {
+        // Seek a loop which actually contains the block being split (to avoid
+        // adjacent loops).
+        while (PredLoop && !PredLoop->contains(OldBB))
+          PredLoop = PredLoop->getParentLoop();
+
+        // Select the most-nested of these loops which contains the block.
+        if (PredLoop && PredLoop->contains(OldBB) &&
+            (!InnermostPredLoop ||
+             InnermostPredLoop->getLoopDepth() < PredLoop->getLoopDepth()))
+          InnermostPredLoop = PredLoop;
+      }
+
+    if (InnermostPredLoop)
+      InnermostPredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
+  } else {
+    L->addBasicBlockToLoop(NewBB, LI->getBase());
+    if (SplitMakesNewLoopHeader)
+      L->moveToHeader(NewBB);
+  }
+}
+
+} // end anonymous namespace
 
 /// SplitBlockPredecessors - This method transforms BB by introducing a new
 /// basic block into the function, and moving some of the predecessors of BB to
@@ -337,48 +410,16 @@
   // The new block unconditionally branches to the old block.
   BranchInst *BI = BranchInst::Create(BB, NewBB);
   
-  LoopInfo *LI = P ? P->getAnalysisIfAvailable<LoopInfo>() : 0;
-  Loop *L = LI ? LI->getLoopFor(BB) : 0;
-  bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
-
   // Move the edges from Preds to point to NewBB instead of BB.
-  // While here, if we need to preserve loop analyses, collect
-  // some information about how this split will affect loops.
-  bool HasLoopExit = false;
-  bool IsLoopEntry = !!L;
-  bool SplitMakesNewLoopHeader = false;
   for (unsigned i = 0; i != NumPreds; ++i) {
     // This is slightly more strict than necessary; the minimum requirement
     // is that there be no more than one indirectbr branching to BB. And
     // all BlockAddress uses would need to be updated.
     assert(!isa<IndirectBrInst>(Preds[i]->getTerminator()) &&
            "Cannot split an edge from an IndirectBrInst");
-
     Preds[i]->getTerminator()->replaceUsesOfWith(BB, NewBB);
-
-    if (LI) {
-      // If we need to preserve LCSSA, determine if any of
-      // the preds is a loop exit.
-      if (PreserveLCSSA)
-        if (Loop *PL = LI->getLoopFor(Preds[i]))
-          if (!PL->contains(BB))
-            HasLoopExit = true;
-      // If we need to preserve LoopInfo, note whether any of the
-      // preds crosses an interesting loop boundary.
-      if (L) {
-        if (L->contains(Preds[i]))
-          IsLoopEntry = false;
-        else
-          SplitMakesNewLoopHeader = true;
-      }
-    }
   }
 
-  // Update dominator tree if available.
-  DominatorTree *DT = P ? P->getAnalysisIfAvailable<DominatorTree>() : 0;
-  if (DT)
-    DT->splitBlock(NewBB);
-
   // Insert a new PHI node into NewBB for every PHI node in BB and that new PHI
   // node becomes an incoming value for BB's phi node.  However, if the Preds
   // list is empty, we need to insert dummy entries into the PHI nodes in BB to
@@ -390,38 +431,12 @@
     return NewBB;
   }
 
-  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
+  // Update DominatorTree, LoopInfo, and LCCSA analysis information.
+  bool HasLoopExit = false;
+  UpdateAnalysisInformation(BB, NewBB, Preds, NumPreds, P, HasLoopExit);
 
-  if (L) {
-    if (IsLoopEntry) {
-      // Add the new block to the nearest enclosing loop (and not an
-      // adjacent loop). To find this, examine each of the predecessors and
-      // determine which loops enclose them, and select the most-nested loop
-      // which contains the loop containing the block being split.
-      Loop *InnermostPredLoop = 0;
-      for (unsigned i = 0; i != NumPreds; ++i)
-        if (Loop *PredLoop = LI->getLoopFor(Preds[i])) {
-          // Seek a loop which actually contains the block being split (to
-          // avoid adjacent loops).
-          while (PredLoop && !PredLoop->contains(BB))
-            PredLoop = PredLoop->getParentLoop();
-          // Select the most-nested of these loops which contains the block.
-          if (PredLoop &&
-              PredLoop->contains(BB) &&
-              (!InnermostPredLoop ||
-               InnermostPredLoop->getLoopDepth() < PredLoop->getLoopDepth()))
-            InnermostPredLoop = PredLoop;
-        }
-      if (InnermostPredLoop)
-        InnermostPredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
-    } else {
-      L->addBasicBlockToLoop(NewBB, LI->getBase());
-      if (SplitMakesNewLoopHeader)
-        L->moveToHeader(NewBB);
-    }
-  }
-  
   // Otherwise, create a new PHI node in NewBB for each PHI node in BB.
+  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
   for (BasicBlock::iterator I = BB->begin(); isa<PHINode>(I); ) {
     PHINode *PN = cast<PHINode>(I++);
     
@@ -462,7 +477,7 @@
     // edge.
     PN->addIncoming(InVal, NewBB);
   }
-  
+
   return NewBB;
 }
 



From clattner at apple.com  Thu Aug 18 01:06:13 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 23:06:13 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <4E4C86DB.6020308@mxc.ca>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<4E4C86DB.6020308@mxc.ca>
Message-ID: <7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>


On Aug 17, 2011, at 8:28 PM, Nick Lewycky wrote:

> Chris Lattner wrote:
>> 
>> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>> 
>>> Err: missed the patch.
>>> Please, find it attached to this message.
>>> 
>>> Also, you can take a look at the patch online:
>>> http://codereview.chromium.org/7676009/
>> 
>> Hi Ivan,
>> 
>> Hopefully dumb question: what are the licensing implications of this?  Is the new autoconf goop GPL3?
> 
> No, they're still GPLv2. The diffs make it clear that the license block at the top of the files haven't changed.

Great, thanks.

-Chris


From clattner at apple.com  Thu Aug 18 01:07:32 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 23:07:32 -0700
Subject: [llvm-commits] [llvm] r137926 -
 /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
In-Reply-To: <20110818052524.2068B2A6C12C@llvm.org>
References: <20110818052524.2068B2A6C12C@llvm.org>
Message-ID: <A78FA5D7-3E9B-4CA2-8AE9-738F8EFF229F@apple.com>


On Aug 17, 2011, at 10:25 PM, Bill Wendling wrote:

> Author: void
> Date: Thu Aug 18 00:25:23 2011
> New Revision: 137926
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137926&view=rev
> Log:
> Split out the analysis updating code into a helper function. No intended
> functionality change.

Hi Bill,

Please use static for functions, not anonymous namespaces.
http://llvm.org/docs/CodingStandards.html#micro_anonns

-Chris

> 
> Modified:
>    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137926&r1=137925&r2=137926&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 00:25:23 2011
> @@ -314,6 +314,79 @@
>   return New;
> }
> 
> +namespace {
> +
> +/// UpdateAnalysisInformation - Update DominatorTree, LoopInfo, and LCCSA
> +/// analysis information.
> +void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB,
> +                               BasicBlock *const *Preds,
> +                               unsigned NumPreds, Pass *P, bool &HasLoopExit) {
> +  if (!P) return;
> +
> +  LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>();
> +  Loop *L = LI ? LI->getLoopFor(OldBB) : 0;
> +  bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
> +
> +  // If we need to preserve loop analyses, collect some information about how
> +  // this split will affect loops.
> +  bool IsLoopEntry = !!L;
> +  bool SplitMakesNewLoopHeader = false;
> +  if (LI) {
> +    for (unsigned i = 0; i != NumPreds; ++i) {
> +      // If we need to preserve LCSSA, determine if any of the preds is a loop
> +      // exit.
> +      if (PreserveLCSSA)
> +        if (Loop *PL = LI->getLoopFor(Preds[i]))
> +          if (!PL->contains(OldBB))
> +            HasLoopExit = true;
> +
> +      // If we need to preserve LoopInfo, note whether any of the preds crosses
> +      // an interesting loop boundary.
> +      if (!L) continue;
> +      if (L->contains(Preds[i]))
> +        IsLoopEntry = false;
> +      else
> +        SplitMakesNewLoopHeader = true;
> +    }
> +  }
> +
> +  // Update dominator tree if available.
> +  DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
> +  if (DT)
> +    DT->splitBlock(NewBB);
> +
> +  if (!L) return;
> +
> +  if (IsLoopEntry) {
> +    // Add the new block to the nearest enclosing loop (and not an adjacent
> +    // loop). To find this, examine each of the predecessors and determine which
> +    // loops enclose them, and select the most-nested loop which contains the
> +    // loop containing the block being split.
> +    Loop *InnermostPredLoop = 0;
> +    for (unsigned i = 0; i != NumPreds; ++i)
> +      if (Loop *PredLoop = LI->getLoopFor(Preds[i])) {
> +        // Seek a loop which actually contains the block being split (to avoid
> +        // adjacent loops).
> +        while (PredLoop && !PredLoop->contains(OldBB))
> +          PredLoop = PredLoop->getParentLoop();
> +
> +        // Select the most-nested of these loops which contains the block.
> +        if (PredLoop && PredLoop->contains(OldBB) &&
> +            (!InnermostPredLoop ||
> +             InnermostPredLoop->getLoopDepth() < PredLoop->getLoopDepth()))
> +          InnermostPredLoop = PredLoop;
> +      }
> +
> +    if (InnermostPredLoop)
> +      InnermostPredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
> +  } else {
> +    L->addBasicBlockToLoop(NewBB, LI->getBase());
> +    if (SplitMakesNewLoopHeader)
> +      L->moveToHeader(NewBB);
> +  }
> +}
> +
> +} // end anonymous namespace
> 
> /// SplitBlockPredecessors - This method transforms BB by introducing a new
> /// basic block into the function, and moving some of the predecessors of BB to
> @@ -337,48 +410,16 @@
>   // The new block unconditionally branches to the old block.
>   BranchInst *BI = BranchInst::Create(BB, NewBB);
> 
> -  LoopInfo *LI = P ? P->getAnalysisIfAvailable<LoopInfo>() : 0;
> -  Loop *L = LI ? LI->getLoopFor(BB) : 0;
> -  bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
> -
>   // Move the edges from Preds to point to NewBB instead of BB.
> -  // While here, if we need to preserve loop analyses, collect
> -  // some information about how this split will affect loops.
> -  bool HasLoopExit = false;
> -  bool IsLoopEntry = !!L;
> -  bool SplitMakesNewLoopHeader = false;
>   for (unsigned i = 0; i != NumPreds; ++i) {
>     // This is slightly more strict than necessary; the minimum requirement
>     // is that there be no more than one indirectbr branching to BB. And
>     // all BlockAddress uses would need to be updated.
>     assert(!isa<IndirectBrInst>(Preds[i]->getTerminator()) &&
>            "Cannot split an edge from an IndirectBrInst");
> -
>     Preds[i]->getTerminator()->replaceUsesOfWith(BB, NewBB);
> -
> -    if (LI) {
> -      // If we need to preserve LCSSA, determine if any of
> -      // the preds is a loop exit.
> -      if (PreserveLCSSA)
> -        if (Loop *PL = LI->getLoopFor(Preds[i]))
> -          if (!PL->contains(BB))
> -            HasLoopExit = true;
> -      // If we need to preserve LoopInfo, note whether any of the
> -      // preds crosses an interesting loop boundary.
> -      if (L) {
> -        if (L->contains(Preds[i]))
> -          IsLoopEntry = false;
> -        else
> -          SplitMakesNewLoopHeader = true;
> -      }
> -    }
>   }
> 
> -  // Update dominator tree if available.
> -  DominatorTree *DT = P ? P->getAnalysisIfAvailable<DominatorTree>() : 0;
> -  if (DT)
> -    DT->splitBlock(NewBB);
> -
>   // Insert a new PHI node into NewBB for every PHI node in BB and that new PHI
>   // node becomes an incoming value for BB's phi node.  However, if the Preds
>   // list is empty, we need to insert dummy entries into the PHI nodes in BB to
> @@ -390,38 +431,12 @@
>     return NewBB;
>   }
> 
> -  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
> +  // Update DominatorTree, LoopInfo, and LCCSA analysis information.
> +  bool HasLoopExit = false;
> +  UpdateAnalysisInformation(BB, NewBB, Preds, NumPreds, P, HasLoopExit);
> 
> -  if (L) {
> -    if (IsLoopEntry) {
> -      // Add the new block to the nearest enclosing loop (and not an
> -      // adjacent loop). To find this, examine each of the predecessors and
> -      // determine which loops enclose them, and select the most-nested loop
> -      // which contains the loop containing the block being split.
> -      Loop *InnermostPredLoop = 0;
> -      for (unsigned i = 0; i != NumPreds; ++i)
> -        if (Loop *PredLoop = LI->getLoopFor(Preds[i])) {
> -          // Seek a loop which actually contains the block being split (to
> -          // avoid adjacent loops).
> -          while (PredLoop && !PredLoop->contains(BB))
> -            PredLoop = PredLoop->getParentLoop();
> -          // Select the most-nested of these loops which contains the block.
> -          if (PredLoop &&
> -              PredLoop->contains(BB) &&
> -              (!InnermostPredLoop ||
> -               InnermostPredLoop->getLoopDepth() < PredLoop->getLoopDepth()))
> -            InnermostPredLoop = PredLoop;
> -        }
> -      if (InnermostPredLoop)
> -        InnermostPredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
> -    } else {
> -      L->addBasicBlockToLoop(NewBB, LI->getBase());
> -      if (SplitMakesNewLoopHeader)
> -        L->moveToHeader(NewBB);
> -    }
> -  }
> -  
>   // Otherwise, create a new PHI node in NewBB for each PHI node in BB.
> +  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
>   for (BasicBlock::iterator I = BB->begin(); isa<PHINode>(I); ) {
>     PHINode *PN = cast<PHINode>(I++);
> 
> @@ -462,7 +477,7 @@
>     // edge.
>     PN->addIncoming(InVal, NewBB);
>   }
> -  
> +
>   return NewBB;
> }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosser at fim.uni-passau.de  Thu Aug 18 01:29:25 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 06:29:25 -0000
Subject: [llvm-commits] [polly] r137927 -
	/polly/trunk/lib/Analysis/TempScopInfo.cpp
Message-ID: <20110818062926.0C5022A6C12C@llvm.org>

Author: grosser
Date: Thu Aug 18 01:29:25 2011
New Revision: 137927

URL: http://llvm.org/viewvc/llvm-project?rev=137927&view=rev
Log:
TempScopInfo: Improve formatiing

Modified:
    polly/trunk/lib/Analysis/TempScopInfo.cpp

Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=137927&r1=137926&r2=137927&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/TempScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/TempScopInfo.cpp Thu Aug 18 01:29:25 2011
@@ -297,21 +297,24 @@
 void TempScopInfo::buildAccessFunctions(Region &R, ParamSetType &Params,
                                         BasicBlock &BB) {
   AccFuncSetType Functions;
+
   for (BasicBlock::iterator I = BB.begin(), E = --BB.end(); I != E; ++I) {
     Instruction &Inst = *I;
     if (isa<LoadInst>(&Inst) || isa<StoreInst>(&Inst)) {
-      // Create the SCEVAffFunc.
-      if (LoadInst *ld = dyn_cast<LoadInst>(&Inst)) {
-        unsigned size = TD->getTypeStoreSize(ld->getType());
-        Functions.push_back(
-          std::make_pair(SCEVAffFunc(SCEVAffFunc::ReadMem, size), &Inst));
-      } else {//Else it must be a StoreInst.
-        StoreInst *st = cast<StoreInst>(&Inst);
-        unsigned size = TD->getTypeStoreSize(st->getValueOperand()->getType());
-        Functions.push_back(
-          std::make_pair(SCEVAffFunc(SCEVAffFunc::WriteMem, size), &Inst));
+      unsigned Size;
+      enum SCEVAffFunc::SCEVAffFuncType Type;
+
+      if (LoadInst *Load = dyn_cast<LoadInst>(&Inst)) {
+        Size = TD->getTypeStoreSize(Load->getType());
+        Type = SCEVAffFunc::ReadMem;
+      } else {
+        StoreInst *Store = cast<StoreInst>(&Inst);
+        Size = TD->getTypeStoreSize(Store->getValueOperand()->getType());
+        Type = SCEVAffFunc::WriteMem;
       }
 
+      Functions.push_back(std::make_pair(SCEVAffFunc(Type, Size), &Inst));
+
       Value *Ptr = getPointerOperand(Inst);
       buildAffineFunction(SE->getSCEV(Ptr), Functions.back().first, R, Params);
     }



From grosser at fim.uni-passau.de  Thu Aug 18 01:31:43 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 06:31:43 -0000
Subject: [llvm-commits] [polly] r137928 - in /polly/trunk:
 include/polly/TempScopInfo.h lib/Analysis/TempScopInfo.cpp
Message-ID: <20110818063143.40F262A6C12C@llvm.org>

Author: grosser
Date: Thu Aug 18 01:31:43 2011
New Revision: 137928

URL: http://llvm.org/viewvc/llvm-project?rev=137928&view=rev
Log:
TempSCoP: Store SCEV a SCEVAffFunc was derived from

Modified:
    polly/trunk/include/polly/TempScopInfo.h
    polly/trunk/lib/Analysis/TempScopInfo.cpp

Modified: polly/trunk/include/polly/TempScopInfo.h
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=137928&r1=137927&r2=137928&view=diff
==============================================================================
--- polly/trunk/include/polly/TempScopInfo.h (original)
+++ polly/trunk/include/polly/TempScopInfo.h Thu Aug 18 01:31:43 2011
@@ -46,6 +46,14 @@
   LnrTransSet LnrTrans;
 
 public:
+  // The scalar evolution expression from which we derived this affine
+  // expression.
+  //
+  // We will use it to directly translation from scalar expressions to the
+  // corresponding isl objects. As soon as this finished, most of SCEVAffFunc
+  // can be removed.
+  const SCEV *OriginalSCEV;
+
   // The type of the scev affine function
   enum SCEVAffFuncType {
     None = 0,
@@ -72,11 +80,10 @@
 
   /// @brief Create a new SCEV affine function with memory access type or
   ///        condition type
-
-  explicit SCEVAffFunc(SCEVAffFuncType Type, unsigned elemBytes = 0,
-                       Value* baseAddr = 0)
-    : TransComp(0), BaseAddr(baseAddr), ElemBytes(elemBytes),
-      FuncType(Type), has_sign(true) {}
+  explicit SCEVAffFunc(SCEVAffFuncType Type, const SCEV *OriginalSCEV,
+                       unsigned elemBytes = 0)
+    : TransComp(0), OriginalSCEV(OriginalSCEV), BaseAddr(0),
+      ElemBytes(elemBytes), FuncType(Type), has_sign(true) {}
 
   /// @brief Construct a new SCEVAffFunc from a SCEV
   ///

Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=137928&r1=137927&r2=137928&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/TempScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/TempScopInfo.cpp Thu Aug 18 01:31:43 2011
@@ -42,6 +42,8 @@
   assert(S && "S can not be null!");
   assert(!isa<SCEVCouldNotCompute>(S) && "Non affine function in Scop");
 
+  OriginalSCEV = S;
+
   for (AffineSCEVIterator I = affine_begin(S, SE), E = affine_end();
        I != E; ++I) {
     // The constant part must be a SCEVConstant.
@@ -294,7 +296,7 @@
   return false;
 }
 
-void TempScopInfo::buildAccessFunctions(Region &R, ParamSetType &Params,
+void TempScopInfo::buildAccessFunctions(Region &R, ParamSetType &Parameter,
                                         BasicBlock &BB) {
   AccFuncSetType Functions;
 
@@ -313,10 +315,11 @@
         Type = SCEVAffFunc::WriteMem;
       }
 
-      Functions.push_back(std::make_pair(SCEVAffFunc(Type, Size), &Inst));
+      const SCEV *AccessFunction = SE->getSCEV(getPointerOperand(Inst));
+      Functions.push_back(
+        std::make_pair(SCEVAffFunc(Type, AccessFunction, Size), &Inst));
 
-      Value *Ptr = getPointerOperand(Inst);
-      buildAffineFunction(SE->getSCEV(Ptr), Functions.back().first, R, Params);
+      buildAffineFunction(AccessFunction, Functions.back().first, R, Parameter);
     }
   }
 
@@ -341,8 +344,8 @@
     if (LoopBounds.find(L) != LoopBounds.end())
       continue;
 
-    LoopBounds[L] = SCEVAffFunc(SCEVAffFunc::Eq);
     const SCEV *LoopCount = SE->getBackedgeTakenCount(L);
+    LoopBounds[L] = SCEVAffFunc(SCEVAffFunc::Eq, LoopCount);
     buildAffineFunction(LoopCount, LoopBounds[L], Scop.getMaxRegion(),
                         Scop.getParamSet());
 



From grosser at fim.uni-passau.de  Thu Aug 18 01:31:46 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 06:31:46 -0000
Subject: [llvm-commits] [polly] r137929 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20110818063146.D45842A6C12D@llvm.org>

Author: grosser
Date: Thu Aug 18 01:31:46 2011
New Revision: 137929

URL: http://llvm.org/viewvc/llvm-project?rev=137929&view=rev
Log:
ScopInfo: Simplify code

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=137929&r1=137928&r2=137929&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Aug 18 01:31:46 2011
@@ -111,7 +111,7 @@
 //===----------------------------------------------------------------------===//
 
 MemoryAccess::~MemoryAccess() {
-  isl_map_free(getAccessFunction());
+  isl_map_free(AccessRelation);
   isl_map_free(newAccessRelation);
 }
 



From grosser at fim.uni-passau.de  Thu Aug 18 01:31:50 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 06:31:50 -0000
Subject: [llvm-commits] [polly] r137930 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20110818063150.8E4722A6C12C@llvm.org>

Author: grosser
Date: Thu Aug 18 01:31:50 2011
New Revision: 137930

URL: http://llvm.org/viewvc/llvm-project?rev=137930&view=rev
Log:
ScopInfo: Build isl_pw_aff directly from SCEV.

Do not use AffFunc to derive the affine expressions, but use isl_pw_aff to
analyze the original SCEV directly. This will allow several simplifications in
follow up patches, with the final goal of removing AffFunc completely.

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=137930&r1=137929&r2=137930&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Aug 18 01:31:50 2011
@@ -38,6 +38,8 @@
 #include "isl/constraint.h"
 #include "isl/set.h"
 #include "isl/map.h"
+#include "isl/aff.h"
+#include "isl/printer.h"
 #include <sstream>
 #include <string>
 #include <vector>
@@ -48,65 +50,261 @@
 STATISTIC(ScopFound,  "Number of valid Scops");
 STATISTIC(RichScopFound,   "Number of Scops containing a loop");
 
+/// Convert an int into a string.
+static std::string convertInt(int number)
+{
+  if (number == 0)
+    return "0";
+  std::string temp = "";
+  std::string returnvalue = "";
+  while (number > 0)
+  {
+    temp += number % 10 + 48;
+    number /= 10;
+  }
+  for (unsigned i = 0; i < temp.length(); i++)
+    returnvalue+=temp[temp.length() - i - 1];
+  return returnvalue;
+}
+
+static isl_map *map_remove_dim_ids(isl_map *map) {
+  isl_ctx *ctx = isl_map_get_ctx(map);
+  int numParams = isl_map_n_param(map);
+  isl_printer *p = isl_printer_to_str(ctx);
+  char *str;
+
+  p = isl_printer_set_output_format (p, ISL_FORMAT_EXT_POLYLIB);
+  p = isl_printer_print_map(p, map);
+  isl_map_free (map);
+
+  str = isl_printer_get_str (p);
+  map = isl_map_read_from_str (ctx, str, numParams);
+  free (str);
+  isl_printer_free (p);
+  return map;
+}
+
+/// Translate a SCEVExpression into an isl_pw_aff object.
+struct SCEVAffinator : public SCEVVisitor<SCEVAffinator, isl_pw_aff*> {
+private:
+  isl_ctx *ctx;
+  int NbLoopDims;
+  const Scop *scop;
+
+  /// baseAdress is set if we analyze a memory access. It holds the base address
+  /// of this memory access.
+  const Value *baseAddress;
+
+public:
+  static isl_pw_aff *getPwAff(const ScopStmt *stmt, const SCEV *scev,
+                              const Value *baseAddress) {
+    SCEVAffinator Affinator(stmt, baseAddress);
+    return Affinator.visit(scev);
+  }
 
-//===----------------------------------------------------------------------===//
-static void setCoefficient(const SCEV *Coeff, mpz_t v, bool negative,
-                           bool isSigned = true) {
-  if (Coeff) {
-    const SCEVConstant *C = dyn_cast<SCEVConstant>(Coeff);
-    const APInt &CI = C->getValue()->getValue();
-    MPZ_from_APInt(v, negative ? (-CI) : CI, isSigned);
-  } else
-    isl_int_set_si(v, 0);
-}
+  isl_pw_aff *visit(const SCEV *scev) {
+    // In case the scev is contained in our list of parameters, we do not
+    // further analyze this expression, but create a new parameter in the
+    // isl_pw_aff. This allows us to treat subexpressions that we cannot
+    // translate into an piecewise affine expression, as constant parameters of
+    // the piecewise affine expression.
+    int i = 0;
+    for (Scop::const_param_iterator PI = scop->param_begin(),
+         PE = scop->param_end(); PI != PE; ++PI) {
+      if (*PI == scev) {
+        isl_id *ID = isl_id_alloc(ctx, ("p" + convertInt(i)).c_str(),
+                                  (void *) scev);
+        isl_dim *Dim = isl_dim_set_alloc(ctx, 1, NbLoopDims);
+        Dim = isl_dim_set_dim_id(Dim, isl_dim_param, 0, ID);
+
+        isl_set *Domain = isl_set_universe(isl_dim_copy(Dim));
+        isl_aff *Affine = isl_aff_zero(isl_local_space_from_dim(Dim));
+        Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1);
+
+        return isl_pw_aff_alloc(Domain, Affine);
+      }
+      i++;
+    }
 
-static isl_map *getValueOf(const SCEVAffFunc &AffFunc,
-                           const ScopStmt *Statement, isl_dim *dim) {
+    return SCEVVisitor<SCEVAffinator, isl_pw_aff*>::visit(scev);
+  }
 
-  const SmallVectorImpl<const SCEV*> &Params =
-    Statement->getParent()->getParams();
-  unsigned num_in = Statement->getNumIterators(), num_param = Params.size();
+  SCEVAffinator(const ScopStmt *stmt, const Value *baseAddress) :
+    ctx(stmt->getParent()->getCtx()),
+    NbLoopDims(stmt->getNumIterators()),
+    scop(stmt->getParent()),
+    baseAddress(baseAddress) {};
 
-  const char *dimname = isl_dim_get_tuple_name(dim, isl_dim_set);
-  dim = isl_dim_alloc(isl_dim_get_ctx(dim), num_param,
-                      isl_dim_size(dim, isl_dim_set), 1);
-  dim = isl_dim_set_tuple_name(dim, isl_dim_in, dimname);
+  __isl_give isl_pw_aff *visitConstant(const SCEVConstant *Constant) {
+    ConstantInt *Value = Constant->getValue();
+    isl_int v;
+    isl_int_init(v);
 
-  assert((AffFunc.getType() == SCEVAffFunc::Eq
-          || AffFunc.getType() == SCEVAffFunc::ReadMem
-          || AffFunc.getType() == SCEVAffFunc::WriteMem)
-          && "AffFunc is not an equality");
+    // LLVM does not define if an integer value is interpreted as a signed or
+    // unsigned value. Hence, without further information, it is unknown how
+    // this value needs to be converted to GMP. At the moment, we only support
+    // signed operations. So we just interpret it as signed. Later, there are
+    // two options:
+    //
+    // 1. We always interpret any value as signed and convert the values on
+    //    demand.
+    // 2. We pass down the signedness of the calculation and use it to interpret
+    //    this constant correctly.
+    MPZ_from_APInt(v, Value->getValue(), /* isSigned */ true);
+
+    isl_dim *dim = isl_dim_set_alloc(ctx, 0, NbLoopDims);
+    isl_local_space *ls = isl_local_space_from_dim(isl_dim_copy(dim));
+    isl_aff *Affine = isl_aff_zero(ls);
+    isl_set *Domain = isl_set_universe(dim);
 
-  isl_constraint *c = isl_equality_alloc(isl_dim_copy(dim));
+    Affine = isl_aff_add_constant(Affine, v);
+    isl_int_clear(v);
 
-  isl_int v;
-  isl_int_init(v);
+    return isl_pw_aff_alloc(Domain, Affine);
+  }
 
-  // Set single output dimension.
-  isl_int_set_si(v, -1);
-  isl_constraint_set_coefficient(c, isl_dim_out, 0, v);
+  __isl_give isl_pw_aff *visitTruncateExpr(const SCEVTruncateExpr* Expr) {
+    assert(0 && "Not yet supported");
+  }
 
-  // Set the coefficient for induction variables.
-  for (unsigned i = 0, e = num_in; i != e; ++i) {
-    setCoefficient(AffFunc.getCoeff(Statement->getSCEVForDimension(i)), v,
-                   false, AffFunc.isSigned());
-    isl_constraint_set_coefficient(c, isl_dim_in, i, v);
+  __isl_give isl_pw_aff *visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
+    assert(0 && "Not yet supported");
   }
 
-  // Set the coefficient of parameters
-  for (unsigned i = 0, e = num_param; i != e; ++i) {
-    setCoefficient(AffFunc.getCoeff(Params[i]), v, false, AffFunc.isSigned());
-    isl_constraint_set_coefficient(c, isl_dim_param, i, v);
+  __isl_give isl_pw_aff *visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
+    // Assuming the value is signed, a sign extension is basically a noop.
+    // TODO: Reconsider this as soon as we support unsigned values.
+    return visit(Expr->getOperand());
   }
 
-  // Set the constant.
-  setCoefficient(AffFunc.getTransComp(), v, false, AffFunc.isSigned());
-  isl_constraint_set_constant(c, v);
-  isl_int_clear(v);
+  __isl_give isl_pw_aff *visitAddExpr(const SCEVAddExpr* Expr) {
+    isl_pw_aff *Sum = visit(Expr->getOperand(0));
+
+    for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
+      isl_pw_aff *NextSummand = visit(Expr->getOperand(i));
+      Sum = isl_pw_aff_add(Sum, NextSummand);
+    }
+
+    // TODO: Check for NSW and NUW.
+
+    return Sum;
+  }
+
+  __isl_give isl_pw_aff *visitMulExpr(const SCEVMulExpr* Expr) {
+    isl_pw_aff *Product = visit(Expr->getOperand(0));
+
+    for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
+      isl_pw_aff *NextOperand = visit(Expr->getOperand(i));
+
+      if (!isl_pw_aff_is_cst(Product) && !isl_pw_aff_is_cst(NextOperand)) {
+        isl_pw_aff_free(Product);
+        isl_pw_aff_free(NextOperand);
+        return NULL;
+      }
 
-  isl_basic_map *BasicMap = isl_basic_map_universe(isl_dim_copy(dim));
-  BasicMap = isl_basic_map_add_constraint(BasicMap, c);
-  return isl_map_from_basic_map(BasicMap);
+      Product = isl_pw_aff_mul(Product, NextOperand);
+    }
+
+    // TODO: Check for NSW and NUW.
+    return Product;
+  }
+
+  __isl_give isl_pw_aff *visitUDivExpr(const SCEVUDivExpr* Expr) {
+    assert(0 && "Not yet supported");
+  }
+
+  int getLoopDepth(const Loop *L) {
+    Loop *outerLoop =
+      scop->getRegion().outermostLoopInRegion(const_cast<Loop*>(L));
+    return L->getLoopDepth() - outerLoop->getLoopDepth();
+  }
+
+  __isl_give isl_pw_aff *visitAddRecExpr(const SCEVAddRecExpr* Expr) {
+    assert(Expr->isAffine() && "Only affine AddRecurrences allowed");
+
+    isl_pw_aff *Start = visit(Expr->getStart());
+    isl_pw_aff *Step = visit(Expr->getOperand(1));
+    isl_dim *Dim = isl_dim_set_alloc (ctx, 0, NbLoopDims);
+    isl_local_space *LocalSpace = isl_local_space_from_dim (Dim);
+
+    int loopDimension = getLoopDepth(Expr->getLoop());
+
+    isl_aff *LAff = isl_aff_set_coefficient_si (isl_aff_zero (LocalSpace),
+                                                isl_dim_set, loopDimension, 1);
+    isl_pw_aff *LPwAff = isl_pw_aff_from_aff(LAff);
+
+    // TODO: Do we need to check for NSW and NUW?
+    return isl_pw_aff_add(Start, isl_pw_aff_mul(Step, LPwAff));
+  }
+
+  __isl_give isl_pw_aff *visitSMaxExpr(const SCEVSMaxExpr* Expr) {
+    isl_pw_aff *Max = visit(Expr->getOperand(0));
+
+    for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
+      isl_pw_aff *NextOperand = visit(Expr->getOperand(i));
+      Max = isl_pw_aff_max(Max, NextOperand);
+    }
+
+    return Max;
+  }
+
+  __isl_give isl_pw_aff *visitUMaxExpr(const SCEVUMaxExpr* Expr) {
+    assert(0 && "Not yet supported");
+  }
+
+  __isl_give isl_pw_aff *visitUnknown(const SCEVUnknown* Expr) {
+    Value *Value = Expr->getValue();
+
+    isl_dim *Dim;
+
+    /// If baseAddress is set, we ignore its Value object in the scev and do not
+    /// add it to the isl_pw_aff. This is because it is regarded as defining the
+    /// name of an array, in contrast to its array subscript.
+    if (baseAddress != Value) {
+      isl_id *ID = isl_id_alloc(ctx, Value->getNameStr().c_str(), Value);
+      Dim = isl_dim_set_alloc(ctx, 1, NbLoopDims);
+      Dim = isl_dim_set_dim_id(Dim, isl_dim_param, 0, ID);
+    } else {
+      Dim = isl_dim_set_alloc(ctx, 0, NbLoopDims);
+    }
+
+    isl_set *Domain = isl_set_universe(isl_dim_copy(Dim));
+    isl_aff *Affine = isl_aff_zero(isl_local_space_from_dim(Dim));
+
+    if (baseAddress != Value)
+      Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1);
+
+    return isl_pw_aff_alloc(Domain, Affine);
+  }
+};
+
+static isl_map *getValueOf(const SCEVAffFunc &AffFunc,
+                           const ScopStmt *Statement, isl_dim *dim) {
+  assert((AffFunc.getType() == SCEVAffFunc::Eq
+          || AffFunc.getType() == SCEVAffFunc::ReadMem
+          || AffFunc.getType() == SCEVAffFunc::WriteMem)
+          && "AffFunc is not an equality");
+  isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV,
+                                               AffFunc.getBaseAddr());
+  isl_map *Map = isl_map_from_pw_aff(Affine);
+  isl_dim *CtxDim = isl_set_get_dim(Statement->getParent()->getContext());
+
+  int i = 0;
+  for (Scop::const_param_iterator PI = Statement->getParent()->param_begin(),
+       PE = Statement->getParent()->param_end(); PI != PE; ++PI) {
+    const SCEV *scev = *PI;
+    isl_id *id = isl_id_alloc(isl_dim_get_ctx(CtxDim),
+                              ("p" + convertInt(i)).c_str(),
+                              (void *) scev);
+    CtxDim = isl_dim_set_dim_id(CtxDim, isl_dim_param, i, id);
+    i++;
+  }
+
+  isl_map_align_params(Map, CtxDim);
+  const char *dimname = isl_dim_get_tuple_name(dim, isl_dim_set);
+  Map = map_remove_dim_ids(Map);
+  Map = isl_map_set_tuple_name(Map, isl_dim_in, dimname);
+  return Map;
 }
 //===----------------------------------------------------------------------===//
 



From krasin at google.com  Thu Aug 18 01:38:19 2011
From: krasin at google.com (Ivan Krasin)
Date: Wed, 17 Aug 2011 23:38:19 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<4E4C86DB.6020308@mxc.ca>
	<7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>
Message-ID: <CAOei5Rdc4Pm_Mmg8wJgS_0YrZosrnhnHY7kqGeJWxChjxpd9kw@mail.gmail.com>

Chris,

is it fine to commit? (I assume that "Great, thanks" was an approval,
but I'd like to double check)

Ivan

On Wed, Aug 17, 2011 at 11:06 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Aug 17, 2011, at 8:28 PM, Nick Lewycky wrote:
>
>> Chris Lattner wrote:
>>>
>>> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>>>
>>>> Err: missed the patch.
>>>> Please, find it attached to this message.
>>>>
>>>> Also, you can take a look at the patch online:
>>>> http://codereview.chromium.org/7676009/
>>>
>>> Hi Ivan,
>>>
>>> Hopefully dumb question: what are the licensing implications of this? ?Is the new autoconf goop GPL3?
>>
>> No, they're still GPLv2. The diffs make it clear that the license block at the top of the files haven't changed.
>
> Great, thanks.
>
> -Chris
>
>


From clattner at apple.com  Thu Aug 18 01:39:13 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 17 Aug 2011 23:39:13 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5Rdc4Pm_Mmg8wJgS_0YrZosrnhnHY7kqGeJWxChjxpd9kw@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<4E4C86DB.6020308@mxc.ca>
	<7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>
	<CAOei5Rdc4Pm_Mmg8wJgS_0YrZosrnhnHY7kqGeJWxChjxpd9kw@mail.gmail.com>
Message-ID: <40963BAC-E345-48ED-9C1E-2BDCC004AEF5@apple.com>

I'm not capable of reviewing the actual patch, but I don't object to it.  Someone who knows autoconf should approve it (Eric?)

-Chris

On Aug 17, 2011, at 11:38 PM, Ivan Krasin wrote:

> Chris,
> 
> is it fine to commit? (I assume that "Great, thanks" was an approval,
> but I'd like to double check)
> 
> Ivan
> 
> On Wed, Aug 17, 2011 at 11:06 PM, Chris Lattner <clattner at apple.com> wrote:
>> 
>> On Aug 17, 2011, at 8:28 PM, Nick Lewycky wrote:
>> 
>>> Chris Lattner wrote:
>>>> 
>>>> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>>>> 
>>>>> Err: missed the patch.
>>>>> Please, find it attached to this message.
>>>>> 
>>>>> Also, you can take a look at the patch online:
>>>>> http://codereview.chromium.org/7676009/
>>>> 
>>>> Hi Ivan,
>>>> 
>>>> Hopefully dumb question: what are the licensing implications of this?  Is the new autoconf goop GPL3?
>>> 
>>> No, they're still GPLv2. The diffs make it clear that the license block at the top of the files haven't changed.
>> 
>> Great, thanks.
>> 
>> -Chris
>> 
>> 


From rdivacky at freebsd.org  Thu Aug 18 02:10:37 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Thu, 18 Aug 2011 09:10:37 +0200
Subject: [llvm-commits] Update to latest versions of config.guess and
	config.sub from GNU mainline
In-Reply-To: <CAOei5RcKrjQA8cUW9jTgfrgWnK8qnhfppQtAmnYEjDUF4kRvTA@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<4E4C8744.7070905@mxc.ca>
	<CAOei5RcKrjQA8cUW9jTgfrgWnK8qnhfppQtAmnYEjDUF4kRvTA@mail.gmail.com>
Message-ID: <20110818071037.GA74140@freebsd.org>

Nathan (the PPC64/FreeBSD guy)

should this change:

Index: autoconf/config.guess
===================================================================
--- autoconf/config.guess       (revision 132626)
+++ autoconf/config.guess       (revision 132627)
@@ -789,13 +789,12 @@
        echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
        exit ;;
     *:FreeBSD:*:*)
+        UNAME_PROCESSOR=`/usr/bin/uname -p`
        case ${UNAME_MACHINE} in
-           pc98)
-               echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
            amd64)
                echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
            *)
-               echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+               echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
        esac
        exit ;;
     i*:CYGWIN*:*)

go upstream to the mainline GNU config.guess?

On Wed, Aug 17, 2011 at 09:13:33PM -0700, Ivan Krasin wrote:
> Nick, thanks for the catch.
> 
> Please, find the updated patch attached. Also, I've updated the patch
> at http://codereview.chromium.org/7676009/
> 
> Roman, do you think it makes sense to push into the mainline GNU config.guess?
> 
> Ivan
> 
> 
> On Wed, Aug 17, 2011 at 8:30 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> > Ivan Krasin wrote:
> >>
> >> Err: missed the patch.
> >> Please, find it attached to this message.
> >>
> >> Also, you can take a look at the patch online:
> >> http://codereview.chromium.org/7676009/
> >
> > This drops r132627 to add support for PPC64 on FreeBSD. Roman, why isn't
> > that upstream? Should Ivan merge that in to this integrate?
> >
> > Nick
> >



From grosser at fim.uni-passau.de  Thu Aug 18 02:51:37 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 07:51:37 -0000
Subject: [llvm-commits] [polly] r137931 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20110818075137.851112A6C12D@llvm.org>

Author: grosser
Date: Thu Aug 18 02:51:37 2011
New Revision: 137931

URL: http://llvm.org/viewvc/llvm-project?rev=137931&view=rev
Log:
ScopInfo: Create all isl data structures with dimension ids

At the moment, we still remove the ids after all data structures are created,
as later passes do not yet support ids. This limitation will be removed later.

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=137931&r1=137930&r2=137931&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Aug 18 02:51:37 2011
@@ -67,21 +67,46 @@
   return returnvalue;
 }
 
+static isl_set *set_remove_dim_ids(isl_set *set) {
+  isl_ctx *ctx = isl_set_get_ctx(set);
+  int numParams = isl_set_n_param(set);
+  isl_printer *p = isl_printer_to_str(ctx);
+  isl_set *new_set;
+  char *str;
+  const char *name = isl_set_get_tuple_name(set);
+
+  p = isl_printer_set_output_format (p, ISL_FORMAT_EXT_POLYLIB);
+  p = isl_printer_print_set(p, set);
+
+  str = isl_printer_get_str (p);
+  new_set = isl_set_read_from_str (ctx, str, numParams);
+  new_set = isl_set_set_tuple_name(new_set, name);
+  free (str);
+  isl_set_free (set);
+  isl_printer_free (p);
+  return new_set;
+}
+
 static isl_map *map_remove_dim_ids(isl_map *map) {
   isl_ctx *ctx = isl_map_get_ctx(map);
   int numParams = isl_map_n_param(map);
   isl_printer *p = isl_printer_to_str(ctx);
   char *str;
+  isl_map *new_map;
+  const char *name_in = isl_map_get_tuple_name(map, isl_dim_in);
+  const char *name_out = isl_map_get_tuple_name(map, isl_dim_out);
 
   p = isl_printer_set_output_format (p, ISL_FORMAT_EXT_POLYLIB);
   p = isl_printer_print_map(p, map);
-  isl_map_free (map);
 
   str = isl_printer_get_str (p);
-  map = isl_map_read_from_str (ctx, str, numParams);
+  new_map = isl_map_read_from_str (ctx, str, numParams);
+  new_map = isl_map_set_tuple_name(new_map, isl_dim_in, name_in);
+  new_map = isl_map_set_tuple_name(new_map, isl_dim_out, name_out);
+  isl_map_free (map);
   free (str);
   isl_printer_free (p);
-  return map;
+  return new_map;
 }
 
 /// Translate a SCEVExpression into an isl_pw_aff object.
@@ -289,20 +314,8 @@
   isl_map *Map = isl_map_from_pw_aff(Affine);
   isl_dim *CtxDim = isl_set_get_dim(Statement->getParent()->getContext());
 
-  int i = 0;
-  for (Scop::const_param_iterator PI = Statement->getParent()->param_begin(),
-       PE = Statement->getParent()->param_end(); PI != PE; ++PI) {
-    const SCEV *scev = *PI;
-    isl_id *id = isl_id_alloc(isl_dim_get_ctx(CtxDim),
-                              ("p" + convertInt(i)).c_str(),
-                              (void *) scev);
-    CtxDim = isl_dim_set_dim_id(CtxDim, isl_dim_param, i, id);
-    i++;
-  }
-
   isl_map_align_params(Map, CtxDim);
   const char *dimname = isl_dim_get_tuple_name(dim, isl_dim_set);
-  Map = map_remove_dim_ids(Map);
   Map = isl_map_set_tuple_name(Map, isl_dim_in, dimname);
   return Map;
 }
@@ -372,7 +385,7 @@
 
   // Devide the access function by the size of the elements in the function.
   isl_dim *dim2 = isl_dim_alloc(Statement->getIslContext(),
-                                    Statement->getNumParams(), 1, 1);
+                                0, 1, 1);
   isl_basic_map *bmap = isl_basic_map_universe(isl_dim_copy(dim2));
   isl_constraint *c = isl_equality_alloc(dim2);
   isl_int v;
@@ -385,10 +398,16 @@
   bmap = isl_basic_map_add_constraint(bmap, c);
   isl_map* dataSizeMap = isl_map_from_basic_map(bmap);
 
+  isl_dim *Model = isl_set_get_dim(Statement->getParent()->getContext());
+  dataSizeMap = isl_map_align_params(dataSizeMap, Model);
+
   AccessRelation = isl_map_apply_range(AccessRelation, dataSizeMap);
 
   AccessRelation = isl_map_set_tuple_name(AccessRelation, isl_dim_out,
                                           getBaseName().c_str());
+
+  // FIXME: Temporarily remove dimension ids.
+  AccessRelation = map_remove_dim_ids(AccessRelation);
 }
 
 MemoryAccess::MemoryAccess(const Value *BaseAddress, ScopStmt *Statement) {
@@ -600,26 +619,25 @@
   }
 }
 
-static isl_map *MapValueToLHS(isl_ctx *Context, unsigned ParameterNumber) {
+static isl_map *MapValueToLHS(isl_dim *Model) {
   std::string MapString;
   isl_map *Map;
 
   MapString = "{[i0] -> [i0, o1]}";
-  Map = isl_map_read_from_str(Context, MapString.c_str(), -1);
-  return isl_map_add_dims(Map, isl_dim_param, ParameterNumber);
+  Map = isl_map_read_from_str(isl_dim_get_ctx(Model), MapString.c_str(), -1);
+  return isl_map_align_params(Map, Model);
 }
 
-static isl_map *MapValueToRHS(isl_ctx *Context, unsigned ParameterNumber) {
+static isl_map *MapValueToRHS(isl_dim *Model) {
   std::string MapString;
   isl_map *Map;
 
   MapString = "{[i0] -> [o0, i0]}";
-  Map = isl_map_read_from_str(Context, MapString.c_str(), -1);
-  return isl_map_add_dims(Map, isl_dim_param, ParameterNumber);
+  Map = isl_map_read_from_str(isl_dim_get_ctx(Model), MapString.c_str(), -1);
+  return isl_map_align_params(Map, Model);
 }
 
-static isl_set *getComparison(isl_ctx *Context, const ICmpInst::Predicate Pred,
-                              unsigned ParameterNumber) {
+static isl_set *getComparison(isl_dim *Model, const ICmpInst::Predicate Pred) {
   std::string SetString;
 
   switch (Pred) {
@@ -657,23 +675,23 @@
     llvm_unreachable("Non integer predicate not supported");
   }
 
-  isl_set *Set = isl_set_read_from_str(Context, SetString.c_str(), -1);
-  return isl_set_add_dims(Set, isl_dim_param, ParameterNumber);
+  isl_set *Set = isl_set_read_from_str(isl_dim_get_ctx(Model),
+                                       SetString.c_str(), -1);
+  return isl_set_align_params(Set, Model);
 }
 
 static isl_set *compareValues(isl_map *LeftValue, isl_map *RightValue,
                               const ICmpInst::Predicate Predicate) {
-  isl_ctx *Context = isl_map_get_ctx(LeftValue);
-  unsigned NumberOfParameters = isl_map_n_param(LeftValue);
+  isl_dim *Model = isl_map_get_dim(LeftValue);
 
-  isl_map *MapToLHS = MapValueToLHS(Context, NumberOfParameters);
-  isl_map *MapToRHS = MapValueToRHS(Context, NumberOfParameters);
+  isl_map *MapToLHS = MapValueToLHS(isl_dim_copy(Model));
+  isl_map *MapToRHS = MapValueToRHS(isl_dim_copy(Model));
 
   isl_map *LeftValueAtLHS = isl_map_apply_range(LeftValue, MapToLHS);
   isl_map *RightValueAtRHS = isl_map_apply_range(RightValue, MapToRHS);
 
   isl_map *BothValues = isl_map_intersect(LeftValueAtLHS, RightValueAtRHS);
-  isl_set *Comparison = getComparison(Context, Predicate, NumberOfParameters);
+  isl_set *Comparison = getComparison(isl_dim_copy(Model), Predicate);
 
   isl_map *ComparedValues = isl_map_intersect_range(BothValues, Comparison);
   return isl_map_domain(ComparedValues);
@@ -689,8 +707,7 @@
 isl_set *ScopStmt::toUpperLoopBound(const SCEVAffFunc &UpperBound, isl_dim *dim,
 				    unsigned BoundedDimension) const {
   // Set output dimension to bounded dimension.
-  isl_dim *RHSDim = isl_dim_alloc(Parent.getCtx(), getNumParams(),
-                                  getNumIterators(), 1);
+  isl_dim *RHSDim = isl_dim_alloc(Parent.getCtx(), 0, getNumIterators(), 1);
   RHSDim = isl_dim_set_tuple_name(RHSDim, isl_dim_in, getBaseName());
   isl_constraint *c = isl_equality_alloc(isl_dim_copy(RHSDim));
   isl_int v;
@@ -704,6 +721,8 @@
   bmap = isl_basic_map_add_constraint(bmap, c);
 
   isl_map *LHSValue = isl_map_from_basic_map(bmap);
+  isl_dim *Model = isl_set_get_dim(getParent()->getContext());
+  LHSValue = isl_map_align_params(LHSValue, Model);
 
   isl_map *RHSValue = getValueOf(UpperBound, this, dim);
 
@@ -711,11 +730,12 @@
 }
 
 void ScopStmt::buildIterationDomainFromLoops(TempScop &tempScop) {
-  isl_dim *dim = isl_dim_set_alloc(Parent.getCtx(), getNumParams(),
+  isl_dim *dim = isl_dim_set_alloc(Parent.getCtx(), 0,
                                    getNumIterators());
   dim = isl_dim_set_tuple_name(dim, isl_dim_set, getBaseName());
 
   Domain = isl_set_universe(isl_dim_copy(dim));
+  Domain = isl_set_align_params(Domain, isl_set_get_dim(Parent.getContext()));
 
   isl_int v;
   isl_int_init(v);
@@ -797,6 +817,10 @@
   buildAccesses(tempScop, CurRegion);
 
   IsReduction = tempScop.is_Reduction(*BB);
+
+  // FIXME: Temporarily remove dimension ids.
+  Scattering = map_remove_dim_ids(Scattering);
+  Domain = set_remove_dim_ids(Domain);
 }
 
 ScopStmt::ScopStmt(Scop &parent, SmallVectorImpl<unsigned> &Scatter)
@@ -953,6 +977,17 @@
 
   isl_dim *dim = isl_dim_set_alloc(ctx, getNumParams(), 0);
 
+  int i = 0;
+  for (ParamSetType::iterator PI = Params.begin(), PE = Params.end();
+       PI != PE; ++PI) {
+    const SCEV *scev = *PI;
+    isl_id *id = isl_id_alloc(ctx,
+                              ("p" + convertInt(i)).c_str(),
+                              (void *) scev);
+    dim = isl_dim_set_dim_id(dim, isl_dim_param, i, id);
+    i++;
+  }
+
   // TODO: Insert relations between parameters.
   // TODO: Insert constraints on parameters.
   Context = isl_set_universe (dim);
@@ -967,6 +1002,9 @@
   buildScop(tempScop, getRegion(), NestLoops, Scatter, LI);
   Stmts.push_back(new ScopStmt(*this, Scatter));
 
+  // FIXME: Temporarily remove dimension ids
+  Context = set_remove_dim_ids(Context);
+
   assert(NestLoops.empty() && "NestLoops not empty at top level!");
 }
 



From grosser at fim.uni-passau.de  Thu Aug 18 02:51:41 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 18 Aug 2011 07:51:41 -0000
Subject: [llvm-commits] [polly] r137932 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20110818075141.139CE2A6C12E@llvm.org>

Author: grosser
Date: Thu Aug 18 02:51:40 2011
New Revision: 137932

URL: http://llvm.org/viewvc/llvm-project?rev=137932&view=rev
Log:
ScopInfo: Remove adhoc comparision of affine expressions

Until today, we compared two affine expressions by defining two maps describing
them, creating an union of those maps, adding constraints that do the comparison
and projecting out unneeded dimensions.

This was simplified to using the isl_pw_aff representation of the affine
expressions and using the relevant isl functions to compare them.

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=137932&r1=137931&r2=137932&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Aug 18 02:51:40 2011
@@ -619,114 +619,60 @@
   }
 }
 
-static isl_map *MapValueToLHS(isl_dim *Model) {
-  std::string MapString;
-  isl_map *Map;
-
-  MapString = "{[i0] -> [i0, o1]}";
-  Map = isl_map_read_from_str(isl_dim_get_ctx(Model), MapString.c_str(), -1);
-  return isl_map_align_params(Map, Model);
-}
-
-static isl_map *MapValueToRHS(isl_dim *Model) {
-  std::string MapString;
-  isl_map *Map;
-
-  MapString = "{[i0] -> [o0, i0]}";
-  Map = isl_map_read_from_str(isl_dim_get_ctx(Model), MapString.c_str(), -1);
-  return isl_map_align_params(Map, Model);
-}
+isl_set *ScopStmt::toConditionSet(const Comparison &Comp, isl_dim *dim) const {
+  isl_pw_aff *LHS = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV,
+                                            0);
+  isl_pw_aff *RHS = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV,
+                                            0);
 
-static isl_set *getComparison(isl_dim *Model, const ICmpInst::Predicate Pred) {
-  std::string SetString;
+  isl_set *set;
 
-  switch (Pred) {
+  switch (Comp.getPred()) {
   case ICmpInst::ICMP_EQ:
-    SetString = "{[i0, i1] : i0 = i1}";
+    set = isl_pw_aff_eq_set(LHS, RHS);
     break;
   case ICmpInst::ICMP_NE:
-    SetString = "{[i0, i1] : i0 + 1 <= i1; [i0, i1] : i0 - 1 >= i1}";
+    set = isl_pw_aff_ne_set(LHS, RHS);
     break;
   case ICmpInst::ICMP_SLT:
-    SetString = "{[i0, i1] : i0 + 1 <= i1}";
-    break;
-  case ICmpInst::ICMP_ULT:
-    SetString = "{[i0, i1] : i0 + 1 <= i1}";
-    break;
-  case ICmpInst::ICMP_SGT:
-    SetString = "{[i0, i1] : i0 >= i1 + 1}";
-    break;
-  case ICmpInst::ICMP_UGT:
-    SetString = "{[i0, i1] : i0 >= i1 + 1}";
+    set = isl_pw_aff_lt_set(LHS, RHS);
     break;
   case ICmpInst::ICMP_SLE:
-    SetString = "{[i0, i1] : i0 <= i1}";
+    set = isl_pw_aff_le_set(LHS, RHS);
     break;
-  case ICmpInst::ICMP_ULE:
-    SetString = "{[i0, i1] : i0 <= i1}";
+  case ICmpInst::ICMP_SGT:
+    set = isl_pw_aff_gt_set(LHS, RHS);
     break;
   case ICmpInst::ICMP_SGE:
-    SetString = "{[i0, i1] : i0 >= i1}";
+    set = isl_pw_aff_ge_set(LHS, RHS);
     break;
+  case ICmpInst::ICMP_ULT:
+  case ICmpInst::ICMP_UGT:
+  case ICmpInst::ICMP_ULE:
   case ICmpInst::ICMP_UGE:
-    SetString = "{[i0, i1] : i0 >= i1}";
-    break;
+    llvm_unreachable("Unsigned comparisons not yet supported");
   default:
     llvm_unreachable("Non integer predicate not supported");
   }
 
-  isl_set *Set = isl_set_read_from_str(isl_dim_get_ctx(Model),
-                                       SetString.c_str(), -1);
-  return isl_set_align_params(Set, Model);
-}
-
-static isl_set *compareValues(isl_map *LeftValue, isl_map *RightValue,
-                              const ICmpInst::Predicate Predicate) {
-  isl_dim *Model = isl_map_get_dim(LeftValue);
-
-  isl_map *MapToLHS = MapValueToLHS(isl_dim_copy(Model));
-  isl_map *MapToRHS = MapValueToRHS(isl_dim_copy(Model));
-
-  isl_map *LeftValueAtLHS = isl_map_apply_range(LeftValue, MapToLHS);
-  isl_map *RightValueAtRHS = isl_map_apply_range(RightValue, MapToRHS);
-
-  isl_map *BothValues = isl_map_intersect(LeftValueAtLHS, RightValueAtRHS);
-  isl_set *Comparison = getComparison(isl_dim_copy(Model), Predicate);
-
-  isl_map *ComparedValues = isl_map_intersect_range(BothValues, Comparison);
-  return isl_map_domain(ComparedValues);
-}
-
-isl_set *ScopStmt::toConditionSet(const Comparison &Comp, isl_dim *dim) const {
-  isl_map *LHSValue = getValueOf(*Comp.getLHS(), this, dim);
-  isl_map *RHSValue = getValueOf(*Comp.getRHS(), this, dim);
+  set = isl_set_set_tuple_name(set, isl_dim_get_tuple_name(dim, isl_dim_set));
 
-  return compareValues(LHSValue, RHSValue, Comp.getPred());
+  return set;
 }
 
-isl_set *ScopStmt::toUpperLoopBound(const SCEVAffFunc &UpperBound, isl_dim *dim,
+isl_set *ScopStmt::toUpperLoopBound(const SCEVAffFunc &UpperBound, isl_dim *Dim,
 				    unsigned BoundedDimension) const {
-  // Set output dimension to bounded dimension.
-  isl_dim *RHSDim = isl_dim_alloc(Parent.getCtx(), 0, getNumIterators(), 1);
-  RHSDim = isl_dim_set_tuple_name(RHSDim, isl_dim_in, getBaseName());
-  isl_constraint *c = isl_equality_alloc(isl_dim_copy(RHSDim));
-  isl_int v;
-  isl_int_init(v);
-  isl_int_set_si(v, 1);
-  isl_constraint_set_coefficient(c, isl_dim_in, BoundedDimension, v);
-  isl_int_set_si(v, -1);
-  isl_constraint_set_coefficient(c, isl_dim_out, 0, v);
-  isl_int_clear(v);
-  isl_basic_map *bmap = isl_basic_map_universe(RHSDim);
-  bmap = isl_basic_map_add_constraint(bmap, c);
-
-  isl_map *LHSValue = isl_map_from_basic_map(bmap);
-  isl_dim *Model = isl_set_get_dim(getParent()->getContext());
-  LHSValue = isl_map_align_params(LHSValue, Model);
-
-  isl_map *RHSValue = getValueOf(UpperBound, this, dim);
-
-  return compareValues(LHSValue, RHSValue, ICmpInst::ICMP_SLE);
+  // FIXME: We should choose a consistent scheme of when to name the dimensions.
+  isl_dim *UnnamedDim = isl_dim_copy(Dim);
+  UnnamedDim = isl_dim_set_tuple_name(UnnamedDim, isl_dim_set, 0);
+  isl_local_space *LocalSpace = isl_local_space_from_dim (UnnamedDim);
+  isl_aff *LAff = isl_aff_set_coefficient_si (isl_aff_zero (LocalSpace),
+                                              isl_dim_set, BoundedDimension, 1);
+  isl_pw_aff *BoundedDim = isl_pw_aff_from_aff(LAff);
+  isl_pw_aff *Bound = SCEVAffinator::getPwAff(this, UpperBound.OriginalSCEV, 0);
+  isl_set *set = isl_pw_aff_le_set(BoundedDim, Bound);
+  set = isl_set_set_tuple_name(set, isl_dim_get_tuple_name(Dim, isl_dim_set));
+  return set;
 }
 
 void ScopStmt::buildIterationDomainFromLoops(TempScop &tempScop) {



From baldrick at free.fr  Thu Aug 18 03:13:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 08:13:18 -0000
Subject: [llvm-commits] [llvm] r137933 -
	/llvm/trunk/lib/AsmParser/LLParser.cpp
Message-ID: <20110818081319.02B1B2A6C12D@llvm.org>

Author: baldrick
Date: Thu Aug 18 03:13:18 2011
New Revision: 137933

URL: http://llvm.org/viewvc/llvm-project?rev=137933&view=rev
Log:
Remove unused variable.

Modified:
    llvm/trunk/lib/AsmParser/LLParser.cpp

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=137933&r1=137932&r2=137933&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Aug 18 03:13:18 2011
@@ -3519,7 +3519,6 @@
 bool LLParser::ParseLandingPad(Instruction *&Inst, PerFunctionState &PFS) {
   Type *Ty = 0; LocTy TyLoc;
   Value *PersFn; LocTy PersFnLoc;
-  LocTy LPLoc = Lex.getLoc();
 
   if (ParseType(Ty, TyLoc) ||
       ParseToken(lltok::kw_personality, "expected 'personality'") ||



From baldrick at free.fr  Thu Aug 18 06:47:00 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 11:47:00 -0000
Subject: [llvm-commits] [dragonegg] r137936 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110818114700.986E82A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 06:47:00 2011
New Revision: 137936

URL: http://llvm.org/viewvc/llvm-project?rev=137936&view=rev
Log:
Use linker private linkage rather than private linkage for constants.
I have no idea what the difference is, I am just following clang.
While there, mark these constants "unnamed_addr" if constant merging
is enabled.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=137936&r1=137935&r2=137936&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Thu Aug 18 06:47:00 2011
@@ -1398,12 +1398,13 @@
 
   // Create a new global variable.
   Slot = new GlobalVariable(*TheModule, Init->getType(), true,
-                            GlobalVariable::PrivateLinkage, Init, ".cst");
+                            GlobalVariable::LinkerPrivateLinkage, Init, ".cst");
   unsigned align = TYPE_ALIGN(TREE_TYPE(exp));
 #ifdef CONSTANT_ALIGNMENT
   align = CONSTANT_ALIGNMENT(exp, align);
 #endif
   Slot->setAlignment(align);
+  Slot->setUnnamedAddr(flag_merge_constants);
 
   return Slot;
 }



From baldrick at free.fr  Thu Aug 18 06:48:30 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 11:48:30 -0000
Subject: [llvm-commits] [dragonegg] r137937 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20110818114830.E5E992A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 06:48:30 2011
New Revision: 137937

URL: http://llvm.org/viewvc/llvm-project?rev=137937&view=rev
Log:
Mark constant globals "unnamed_addr", enabing constant merging, when doing
so is clearly safe.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=137937&r1=137936&r2=137937&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Thu Aug 18 06:48:30 2011
@@ -886,6 +886,14 @@
   TARGET_ADJUST_LLVM_LINKAGE(GV, decl);
 #endif /* TARGET_ADJUST_LLVM_LINKAGE */
 
+  // If this is a constant that never has its address taken then allow it to be
+  // merged with other constants (C and C++ say that different variables should
+  // have different addresses, which is why this is only correct if the address
+  // is not taken).  However if -fmerge-all-constants was specified then allow
+  // merging even if the address was taken.
+  GV->setUnnamedAddr(GV->isConstant() && (flag_merge_constants >= 2 ||
+                                          !TREE_ADDRESSABLE(decl)));
+
   handleVisibility(decl, GV);
 
   // Set the section for the global.



From richard at xmos.com  Thu Aug 18 08:00:48 2011
From: richard at xmos.com (Richard Osborne)
Date: Thu, 18 Aug 2011 13:00:48 -0000
Subject: [llvm-commits] [llvm] r137938 - in /llvm/trunk:
 include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td
 test/CodeGen/XCore/misc-intrinsics.ll test/CodeGen/XCore/resources.ll
Message-ID: <20110818130049.0B1BC2A6C12C@llvm.org>

Author: friedgold
Date: Thu Aug 18 08:00:48 2011
New Revision: 137938

URL: http://llvm.org/viewvc/llvm-project?rev=137938&view=rev
Log:
Add intrinsics for SETEV, GETED, GETET.

Modified:
    llvm/trunk/include/llvm/IntrinsicsXCore.td
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
    llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll
    llvm/trunk/test/CodeGen/XCore/resources.ll

Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=137938&r1=137937&r2=137938&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsXCore.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsXCore.td Thu Aug 18 08:00:48 2011
@@ -24,6 +24,8 @@
   def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
   def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
   def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;
+  def int_xcore_geted : Intrinsic<[llvm_i32_ty],[]>;
+  def int_xcore_getet : Intrinsic<[llvm_i32_ty],[]>;
   def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;
   def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;
 
@@ -66,6 +68,8 @@
                                   [NoCapture<0>]>;
   def int_xcore_setv : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty],
                                  [NoCapture<0>]>;
+  def int_xcore_setev : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty],
+                                  [NoCapture<0>]>;
   def int_xcore_eeu : Intrinsic<[],[llvm_anyptr_ty], [NoCapture<0>]>;
   def int_xcore_setclk : Intrinsic<[],[llvm_anyptr_ty, llvm_anyptr_ty],
                                    [NoCapture<0>, NoCapture<1>]>;

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=137938&r1=137937&r2=137938&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Thu Aug 18 08:00:48 2011
@@ -995,10 +995,15 @@
                "freer res[$r]",
                [(int_xcore_freer GRRegs:$r)]>;
 
-let Uses=[R11] in
+let Uses=[R11] in {
 def SETV_1r : _F1R<(outs), (ins GRRegs:$r),
-               "setv res[$r], r11",
-               [(int_xcore_setv GRRegs:$r, R11)]>;
+                   "setv res[$r], r11",
+                   [(int_xcore_setv GRRegs:$r, R11)]>;
+
+def SETEV_1r : _F1R<(outs), (ins GRRegs:$r),
+                    "setev res[$r], r11",
+                    [(int_xcore_setev GRRegs:$r, R11)]>;
+}
 
 def EEU_1r : _F1R<(outs), (ins GRRegs:$r),
                "eeu res[$r]",
@@ -1006,15 +1011,24 @@
 
 // Zero operand short
 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
-// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
+// stet, getkep, getksp, setkep, getid, kret, dcall, dret,
 // dentsp, drestsp
 
 def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>;
 
-let Defs = [R11] in
+let Defs = [R11] in {
 def GETID_0R : _F0R<(outs), (ins),
-                 "get r11, id",
-                 [(set R11, (int_xcore_getid))]>;
+                    "get r11, id",
+                    [(set R11, (int_xcore_getid))]>;
+
+def GETED_0R : _F0R<(outs), (ins),
+                    "get r11, ed",
+                    [(set R11, (int_xcore_geted))]>;
+
+def GETET_0R : _F0R<(outs), (ins),
+                    "get r11, et",
+                    [(set R11, (int_xcore_getet))]>;
+}
 
 def SSYNC_0r : _F0R<(outs), (ins),
                     "ssync",

Modified: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll?rev=137938&r1=137937&r2=137938&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Thu Aug 18 08:00:48 2011
@@ -6,6 +6,8 @@
 declare %0 @llvm.xcore.crc8(i32, i32, i32)
 declare i32 @llvm.xcore.zext(i32, i32)
 declare i32 @llvm.xcore.sext(i32, i32)
+declare i32 @llvm.xcore.geted()
+declare i32 @llvm.xcore.getet()
 
 define i32 @bitrev(i32 %val) {
 ; CHECK: bitrev:
@@ -55,3 +57,19 @@
 	%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
 	ret i32 %result
 }
+
+define i32 @geted() {
+; CHECK: geted:
+; CHECK: get r11, ed
+; CHECK-NEXT: mov r0, r11
+	%result = call i32 @llvm.xcore.geted()
+	ret i32 %result
+}
+
+define i32 @getet() {
+; CHECK: getet:
+; CHECK: get r11, et
+; CHECK-NEXT: mov r0, r11
+	%result = call i32 @llvm.xcore.getet()
+	ret i32 %result
+}

Modified: llvm/trunk/test/CodeGen/XCore/resources.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/resources.ll?rev=137938&r1=137937&r2=137938&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/resources.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/resources.ll Thu Aug 18 08:00:48 2011
@@ -20,6 +20,7 @@
 declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
+declare void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
 declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
 declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
@@ -175,6 +176,14 @@
 	ret void
 }
 
+define void @setev(i8 addrspace(1)* %r, i8* %p) {
+; CHECK: setev:
+; CHECK: mov r11, r1
+; CHECK-NEXT: setev res[r0], r11
+	call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
+	ret void
+}
+
 define void @eeu(i8 addrspace(1)* %r) {
 ; CHECK: eeu:
 ; CHECK: eeu res[r0]



From renato.golin at arm.com  Thu Aug 18 08:21:05 2011
From: renato.golin at arm.com (Renato Golin)
Date: Thu, 18 Aug 2011 14:21:05 +0100
Subject: [llvm-commits] [PATCH] EH table comments
Message-ID: <CAPH-gfdGNW2L6BxLCMW+VrJ__aF7RDDajf9G-G4tC39kb43yYw@mail.gmail.com>

Hi,

I'm digging the ARM EHABI status in the DwarfException implementation
and I don't want to send too much in a go.

Here's a clean up I did to add the comments of each declaration follow
it, making it easier to read and compare to GCC's result.

Nothing too fancy, but also helps other EH tables...

-- 
cheers,
--renato
-------------- next part --------------
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From nwhitehorn at freebsd.org  Thu Aug 18 09:53:55 2011
From: nwhitehorn at freebsd.org (Nathan Whitehorn)
Date: Thu, 18 Aug 2011 09:53:55 -0500
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <20110818071037.GA74140@freebsd.org>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<4E4C8744.7070905@mxc.ca>
	<CAOei5RcKrjQA8cUW9jTgfrgWnK8qnhfppQtAmnYEjDUF4kRvTA@mail.gmail.com>
	<20110818071037.GA74140@freebsd.org>
Message-ID: <4E4D2783.2060808@freebsd.org>

Yes, I believe so. This is also important for our various ARM and MIPS 
architectures (and simplifies the PC98 case in the patch).
-Nathan

On 08/18/11 02:10, Roman Divacky wrote:
> Nathan (the PPC64/FreeBSD guy)
>
> should this change:
>
> Index: autoconf/config.guess
> ===================================================================
> --- autoconf/config.guess       (revision 132626)
> +++ autoconf/config.guess       (revision 132627)
> @@ -789,13 +789,12 @@
>          echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
>          exit ;;
>       *:FreeBSD:*:*)
> +        UNAME_PROCESSOR=`/usr/bin/uname -p`
>          case ${UNAME_MACHINE} in
> -           pc98)
> -               echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
>              amd64)
>                  echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
>              *)
> -               echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
> +               echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
>          esac
>          exit ;;
>       i*:CYGWIN*:*)
>
> go upstream to the mainline GNU config.guess?
>
> On Wed, Aug 17, 2011 at 09:13:33PM -0700, Ivan Krasin wrote:
>> Nick, thanks for the catch.
>>
>> Please, find the updated patch attached. Also, I've updated the patch
>> at http://codereview.chromium.org/7676009/
>>
>> Roman, do you think it makes sense to push into the mainline GNU config.guess?
>>
>> Ivan
>>
>>
>> On Wed, Aug 17, 2011 at 8:30 PM, Nick Lewycky<nicholas at mxc.ca>  wrote:
>>> Ivan Krasin wrote:
>>>> Err: missed the patch.
>>>> Please, find it attached to this message.
>>>>
>>>> Also, you can take a look at the patch online:
>>>> http://codereview.chromium.org/7676009/
>>> This drops r132627 to add support for PPC64 on FreeBSD. Roman, why isn't
>>> that upstream? Should Ivan merge that in to this integrate?
>>>
>>> Nick
>>>
>


From grosbach at apple.com  Thu Aug 18 11:08:39 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 16:08:39 -0000
Subject: [llvm-commits] [llvm] r137941 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110818160839.6B36C2A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 11:08:39 2011
New Revision: 137941

URL: http://llvm.org/viewvc/llvm-project?rev=137941&view=rev
Log:
Add missing 'break'.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137941&r1=137940&r2=137941&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 18 11:08:39 2011
@@ -3039,6 +3039,7 @@
     // If the conditional is AL, we really want tB.
     if (Inst.getOperand(1).getImm() == ARMCC::AL)
       Inst.setOpcode(ARM::tB);
+    break;
   }
 }
 



From grosbach at apple.com  Thu Aug 18 11:10:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 09:10:04 -0700
Subject: [llvm-commits] [llvm] r137891 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
In-Reply-To: <D127BCB2-BA43-4F56-9327-5CE3AB822BE5@apple.com>
References: <20110817225740.35F092A6C12C@llvm.org>
	<D127BCB2-BA43-4F56-9327-5CE3AB822BE5@apple.com>
Message-ID: <4FC872C1-BE20-4DBE-88DB-06615203FF49@apple.com>


On Aug 17, 2011, at 5:47 PM, Chris Lattner wrote:

> 
> On Aug 17, 2011, at 3:57 PM, Jim Grosbach wrote:
> 
>> Author: grosbach
>> Date: Wed Aug 17 17:57:40 2011
>> New Revision: 137891
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137891&view=rev
>> Log:
>> Thumb assembly parsing and encoding for B.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>   llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
>> 
>> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137891&r1=137890&r2=137891&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 17:57:40 2011
>> @@ -3035,6 +3035,10 @@
>>    if (Inst.getOperand(3).getImm() < 8)
>>      Inst.setOpcode(ARM::tADDi3);
>>    break;
>> +  case ARM::tBcc:
>> +    // If the conditional is AL, we really want tB.
>> +    if (Inst.getOperand(1).getImm() == ARMCC::AL)
>> +      Inst.setOpcode(ARM::tB);
>>  }
>> }
> 
> Not necessary for correctness, but please add a break;

Eep. Sorry about that. Fixed in r137941.

From baldrick at free.fr  Thu Aug 18 11:12:48 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 16:12:48 -0000
Subject: [llvm-commits] [dragonegg] r137942 - /dragonegg/trunk/src/Types.cpp
Message-ID: <20110818161248.48E622A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 11:12:48 2011
New Revision: 137942

URL: http://llvm.org/viewvc/llvm-project?rev=137942&view=rev
Log:
Tighten up sanity checks on types: if the GCC type has a size, assert
that the LLVM type has a size (as before, if the sizes are constant
then it is checked that they are equal).  Now that the record/union
conversion logic has been rewritten also check that the alignment of
the LLVM type does not exceed the alignment of the GCC type.

Modified:
    dragonegg/trunk/src/Types.cpp

Modified: dragonegg/trunk/src/Types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=137942&r1=137941&r2=137942&view=diff
==============================================================================
--- dragonegg/trunk/src/Types.cpp (original)
+++ dragonegg/trunk/src/Types.cpp Thu Aug 18 11:12:48 2011
@@ -315,6 +315,8 @@
 /// turned by ConvertType into an LLVM type of the same size (i.e. TYPE_SIZE the
 /// same as getTypeAllocSizeInBits).
 bool isSizeCompatible(tree type) {
+  if (TREE_CODE(type) == FUNCTION_TYPE || TREE_CODE(type) == METHOD_TYPE)
+    return false;
   return isInt64(TYPE_SIZE(type), true);
 }
 
@@ -330,20 +332,40 @@
   assert(TYPE_P(Tr) && "Expected a gcc type!");
 
 #ifndef NDEBUG
-  // Check that the LLVM and GCC types have the same size, or, if the type has
-  // variable size, that the LLVM type is not bigger than any possible value of
-  // the GCC type.
-  if (Ty->isSized() && isSizeCompatible(Tr)) {
-    uint64_t LLVMSize = getTargetData().getTypeAllocSizeInBits(Ty);
-    if (getInt64(TYPE_SIZE(Tr), true) != LLVMSize) {
-      errs() << "GCC: ";
-      debug_tree(Tr);
-      errs() << "LLVM: ";
-      Ty->print(errs());
-      errs() << " (" << LLVMSize << " bits)\n";
-      DieAbjectly("LLVM type size doesn't match GCC type size!");
+  bool Mismatch = false;
+  // Check that the LLVM and GCC types really do have the same size when we say
+  // they do.
+  if (isSizeCompatible(Tr)) {
+    if (!Ty->isSized()) {
+      Mismatch = true;
+      errs() << "No size\n";
+    } else {
+      uint64_t GCCSize = getInt64(TYPE_SIZE(Tr), true);
+      uint64_t LLVMSize = getTargetData().getTypeAllocSizeInBits(Ty);
+      if (LLVMSize != GCCSize) {
+        errs() << "GCC size: " << GCCSize << "; LLVM size: " << LLVMSize
+          << "\n";
+        Mismatch = true;
+      }
     }
   }
+  // Check that the LLVM type has the same alignment or less than the GCC type.
+  if (Ty->isSized()) {
+    unsigned GCCAlign = TYPE_ALIGN(Tr);
+    unsigned LLVMAlign = getTargetData().getABITypeAlignment(Ty) * 8;
+    if (LLVMAlign > GCCAlign) {
+      errs() << "GCC align: " << GCCAlign << "; LLVM align: " << LLVMAlign
+        << "\n";
+      Mismatch = true;
+    }
+  }
+  if (Mismatch) {
+    errs() << "GCC: ";
+    debug_tree(Tr);
+    errs() << "LLVM: ";
+    Ty->print(errs());
+    DieAbjectly("\nLLVM type doesn't represent GCC type!");
+  }
 #endif
 
   setCachedType(Tr, Ty);
@@ -1513,7 +1535,9 @@
       }
       // Otherwise register a placeholder for this type.
       Ty = StructType::create(Context, getDescriptiveName(some_type));
-      llvm_set_type(some_type, Ty);
+      // Associate the placeholder with the GCC type without sanity checking
+      // since the type sizes won't match yet.
+      setCachedType(some_type, Ty);
     }
 
     // Now convert every type in the SCC, filling in the placeholders created



From bruno.cardoso at gmail.com  Thu Aug 18 11:30:49 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 18 Aug 2011 16:30:49 -0000
Subject: [llvm-commits] [llvm] r137943 -
	/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Message-ID: <20110818163049.C6DA22A6C12C@llvm.org>

Author: bruno
Date: Thu Aug 18 11:30:49 2011
New Revision: 137943

URL: http://llvm.org/viewvc/llvm-project?rev=137943&view=rev
Log:
Clenup and fix encoding for Mips ins and ext instruction

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137943&r1=137942&r2=137943&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Aug 18 11:30:49 2011
@@ -406,15 +406,13 @@
 }
 
 // Ext and Ins
-class ExtIns<bits<6> _funct, string instr_asm, dag ins,
+class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
              list<dag> pattern, InstrItinClass itin>:
-  FR<0x1f, _funct, (outs CPURegs:$rt), ins,
-     !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
-  bits<5> src;
+  FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
+     pattern, itin>, Requires<[IsMips32r2]> {
   bits<5> pos;
-  bits<5> size;
-  let rs = src;
-  let rd = size;
+  bits<5> sz;
+  let rd = sz;
   let shamt = pos;
 }
 
@@ -689,21 +687,19 @@
 
 def RDHWR : ReadHardware;
 
-let Predicates = [IsMips32r2] in {
-
-def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
-                 [(set CPURegs:$rt, 
-                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
+def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
+                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
+                 [(set CPURegs:$rt,
+                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
                  NoItinerary>;
 
 let Constraints = "$src = $rt" in
-def INS : ExtIns<4, "ins",
-                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
-                 [(set CPURegs:$rt, 
-                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
+def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
+                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
+                 [(set CPURegs:$rt,
+                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
                     CPURegs:$src))],
                  NoItinerary>;
-}
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions



From grosbach at apple.com  Thu Aug 18 11:50:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 16:50:45 -0000
Subject: [llvm-commits] [llvm] r137946 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20110818165045.7B0D72A6C12D@llvm.org>

Author: grosbach
Date: Thu Aug 18 11:50:45 2011
New Revision: 137946

URL: http://llvm.org/viewvc/llvm-project?rev=137946&view=rev
Log:
80 columns.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137946&r1=137945&r2=137946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Aug 18 11:50:45 2011
@@ -392,7 +392,7 @@
 
   // ARMv5T and above, also used for Thumb2
   def tBLXi : TIx2<0b11110, 0b11, 0,
-                   (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
+                 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
                    "blx${p}\t$func",
                    [(ARMcall tglobaladdr:$func)]>,
               Requires<[IsThumb, HasV5T, IsNotDarwin]> {



From supertri at google.com  Thu Aug 18 11:54:06 2011
From: supertri at google.com (Caitlin Sadowski)
Date: Thu, 18 Aug 2011 09:54:06 -0700
Subject: [llvm-commits] small patch: adding support for a variadic list
 of expressions to the Clang attribute tablegen (Eli Friedman)
Message-ID: <CAG2Ztay_umvB++hCWnJnfgAaotkeoqCzwvFMYOCYhjpjwEYzYg@mail.gmail.com>

> Date: Wed, 17 Aug 2011 19:57:18 -0700
> From: Eli Friedman <eli.friedman at gmail.com>
> Subject: Re: [llvm-commits] small patch: adding support for a variadic
> ? ? ? ?list of expressions to the Clang attribute tablegen
> To: Caitlin Sadowski <supertri at google.com>
> Cc: llvm-commits at cs.uiuc.edu
> Message-ID:
> ? ? ? ?<CAJdarcGQ5=+hWKOGKegWmu3AvBz51hihs85_NJFDOcX2D2MwsA at mail.gmail.com>
> Content-Type: text/plain; charset=ISO-8859-1
>
> On Wed, Aug 17, 2011 at 4:07 PM, Caitlin Sadowski <supertri at google.com> wrote:
>> Dear llvm-commits,
>>
>> Here is a small patch I would like to commit that adds support for a
>> variadic list of expressions for attribute arguments. I will need this
>> support for the thread safety analysis, since some attributes contain
>> multiple arguments of multiple types. Let me know as soon as
>> convenient if you have any concerns with this patch.
>
> Please send patches for that code to cfe-commits; despite the location
> in the repository, it's essentially clang code.
>
> -Eli

Good to know; already sent to cfe-commits.

Cheers,

Caitlin


From grosbach at apple.com  Thu Aug 18 11:57:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 16:57:50 -0000
Subject: [llvm-commits] [llvm] r137947 -
	/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
Message-ID: <20110818165751.075D62A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 11:57:50 2011
New Revision: 137947

URL: http://llvm.org/viewvc/llvm-project?rev=137947&view=rev
Log:
ARM Thumb blx instruction fixup has same data range as bl.

These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=137947&r1=137946&r2=137947&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Thu Aug 18 11:57:50 2011
@@ -77,7 +77,7 @@
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_br",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bl",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_blx",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bcc",     0,             8,  MCFixupKindInfo::FKF_IsPCRel },



From bob.wilson at apple.com  Thu Aug 18 11:59:50 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 18 Aug 2011 09:59:50 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r137729
	-	/llvm-gcc-4.2/trunk/build_gcc
In-Reply-To: <20110816174644.BFC112A6C12C@llvm.org>
References: <20110816174644.BFC112A6C12C@llvm.org>
Message-ID: <22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>

My nightly tester failed to build llvm-gcc last night due to this.  You need the "gnu89" change, e.g., svn r137181, as well.  Please fix.

On Aug 16, 2011, at 10:46 AM, Eric Christopher wrote:

> Author: echristo
> Date: Tue Aug 16 12:46:44 2011
> New Revision: 137729
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=137729&view=rev
> Log:
> Lots of clang as the new black.
> 
> Modified:
>    llvm-gcc-4.2/trunk/build_gcc
> 
> Modified: llvm-gcc-4.2/trunk/build_gcc
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=137729&r1=137728&r2=137729&view=diff
> ==============================================================================
> --- llvm-gcc-4.2/trunk/build_gcc (original)
> +++ llvm-gcc-4.2/trunk/build_gcc Tue Aug 16 12:46:44 2011
> @@ -258,12 +258,12 @@
> # LLVM LOCAL end
> 
> # If the user has set CC or CXX, respect their wishes.  If not,
> -# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not
> +# compile with clang/clang++ if available; if LLVM is not
> # available, fall back to usual GCC/G++ default.
> savedPATH=$PATH ; PATH="/Developer/usr/bin:$PATH"
> -XTMPCC=$(which llvm-gcc)
> +XTMPCC=$(which clang)
> if [ x$CC  = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC  forcedCC=1  ; fi
> -XTMPCC=$(which llvm-g++)
> +XTMPCC=$(which clang++)
> if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC forcedCXX=1 ; fi
> PATH=$savedPATH
> unset XTMPCC savedPATH
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Thu Aug 18 12:00:09 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 17:00:09 -0000
Subject: [llvm-commits] [llvm] r137948 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110818170009.682542A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 12:00:09 2011
New Revision: 137948

URL: http://llvm.org/viewvc/llvm-project?rev=137948&view=rev
Log:
ARM assembly parsing and encoding test for BL/BLX (immediate).

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137948&r1=137947&r2=137948&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 12:00:09 2011
@@ -106,3 +106,15 @@
 
 @ CHECK: bkpt	#0                      @ encoding: [0x00,0xbe]
 @ CHECK: bkpt	#255                    @ encoding: [0xff,0xbe]
+
+
+ at ------------------------------------------------------------------------------
+@ BL/BLX (immediate)
+ at ------------------------------------------------------------------------------
+        bl _bar
+        blx _baz
+
+@ CHECK: bl	_bar                    @ encoding: [A,0xf0'A',A,0xf8'A']
+             @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
+@ CHECK: blx	_baz                    @ encoding: [A,0xf0'A',A,0xe8'A']
+             @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx



From delesley at google.com  Thu Aug 18 12:03:17 2011
From: delesley at google.com (Delesley Hutchins)
Date: Thu, 18 Aug 2011 10:03:17 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
Message-ID: <CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>

AFAICT, the RPO iterator does not do what we need.  For example,
assume we have the following graph (pardon the bad ASCII graphics):

   /---> (2) ----------\
(1)                     --> (5)
   \---> (3) ---> (4)--/

I believe the RPO iterator will traverse this graph as 5-2-4-3-1,
which is a standard depth-first post-order traversal.

What we want is a topological traversal, which is 1-2-3-4-5; every
predecessor of a node must be traversed before the node itself.
Notice that a topological traversal is neither depth-first (that would
be 1-2-5-3-4), nor breadth-first (1-2-3-5-4); we want to ensure that 2
and 4 are traversed before 5.

This patch does three things to achieve the topological traversal:
(1) Depth-first traversal to identify back-edges and assign depths.
(2) Sort nodes according to depth.
(3) Traversal of the sorted list of nodes.

  -DeLesley

On Wed, Aug 17, 2011 at 10:00 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Aug 17, 2011, at 9:17 PM, Chandler Carruth wrote:
>
> On Wed, Aug 17, 2011 at 8:56 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
> wrote:
>>
>> On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:
>>
>> > This patch adds a topological sort routine for indexed graphs to
>> > llvm/ADT. ?This sort routine is currently used to traverse CFGs in
>> > Clang when doing thread safety analysis (patch to be released
>> > shortly).
>>
>> Could you explain why we need this in addition to
>> include/llvm/ADT/PostOrderIterator.h?
>
> FYI, I'm not terribly familiar w/ PostOrderIterator (so maybe it would
> actually serve here), but JSYK, the motivating use case is in a Clang
> patch:?http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20110815/045262.html
>
> I see.
> AFAICT, the existing RPO iterator will give you the exact same ordering of
> blocks, at least it will give you a topo-sort of the graph after removing
> back-edges.
> You can detect back-edges by keeping track of visited blocks in a BitVector
> as you iterate through the RPO.
> /jakob
>



-- 
DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315


From grosbach at apple.com  Thu Aug 18 12:02:28 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 17:02:28 -0000
Subject: [llvm-commits] [llvm] r137949 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110818170228.E5E832A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 12:02:28 2011
New Revision: 137949

URL: http://llvm.org/viewvc/llvm-project?rev=137949&view=rev
Log:
ARM assembly parsing and encoding test for BX/BLX (register).

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137949&r1=137948&r2=137949&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 12:02:28 2011
@@ -118,3 +118,19 @@
              @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
 @ CHECK: blx	_baz                    @ encoding: [A,0xf0'A',A,0xe8'A']
              @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
+
+
+ at ------------------------------------------------------------------------------
+@ BLX (register)
+ at ------------------------------------------------------------------------------
+        blx r4
+
+@ CHECK: blx	r4                      @ encoding: [0xa0,0x47]
+
+
+ at ------------------------------------------------------------------------------
+@ BX
+ at ------------------------------------------------------------------------------
+        bx r2
+
+@ CHECK: bx	r2                      @ encoding: [0x10,0x47]



From echristo at apple.com  Thu Aug 18 12:06:10 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 10:06:10 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r137729 -
 /llvm-gcc-4.2/trunk/build_gcc
In-Reply-To: <22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>
References: <20110816174644.BFC112A6C12C@llvm.org>
	<22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>
Message-ID: <B47B218D-1DDB-418C-8B64-8358FA3CF1DD@apple.com>


On Aug 18, 2011, at 9:59 AM, Bob Wilson wrote:

> My nightly tester failed to build llvm-gcc last night due to this.  You need the "gnu89" change, e.g., svn r137181, as well.  Please fix.

You mean what I'd already committed as 137183? What was the failure?

-eric

From echristo at apple.com  Thu Aug 18 12:07:51 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 10:07:51 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r137729 -
 /llvm-gcc-4.2/trunk/build_gcc
In-Reply-To: <B47B218D-1DDB-418C-8B64-8358FA3CF1DD@apple.com>
References: <20110816174644.BFC112A6C12C@llvm.org>
	<22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>
	<B47B218D-1DDB-418C-8B64-8358FA3CF1DD@apple.com>
Message-ID: <1085535D-20A8-49B1-A349-415CEFA752FD@apple.com>


On Aug 18, 2011, at 10:06 AM, Eric Christopher wrote:

> 
> On Aug 18, 2011, at 9:59 AM, Bob Wilson wrote:
> 
>> My nightly tester failed to build llvm-gcc last night due to this.  You need the "gnu89" change, e.g., svn r137181, as well.  Please fix.
> 
> You mean what I'd already committed as 137183? What was the failure?

Ah. Bet I know. Remove the BOOTSTRAP= from the end of your buildit line.

-eric

From chandlerc at google.com  Thu Aug 18 12:17:39 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 18 Aug 2011 10:17:39 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
	<CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
Message-ID: <CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>

On Thu, Aug 18, 2011 at 10:03 AM, Delesley Hutchins <delesley at google.com>wrote:

> AFAICT, the RPO iterator does not do what we need.  For example,
> assume we have the following graph (pardon the bad ASCII graphics):
>
>   /---> (2) ----------\
> (1)                     --> (5)
>   \---> (3) ---> (4)--/
>
> I believe the RPO iterator will traverse this graph as 5-2-4-3-1,
> which is a standard depth-first post-order traversal.
>
> What we want is a topological traversal, which is 1-2-3-4-5; every
> predecessor of a node must be traversed before the node itself.
>

What about the reverse of the RPO violates this constraint? 1-3-4-2-5 looks
like it satisfies your constraint. I think Jakub is aware that we would have
to reverse the order, and was just claiming that such a reversed order
satisfied the constraints of a topological ordering.


> Notice that a topological traversal is neither depth-first (that would
> be 1-2-5-3-4), nor breadth-first (1-2-3-5-4); we want to ensure that 2
> and 4 are traversed before 5.
>
> This patch does three things to achieve the topological traversal:
> (1) Depth-first traversal to identify back-edges and assign depths.
> (2) Sort nodes according to depth.
> (3) Traversal of the sorted list of nodes.
>
>  -DeLesley
>
> On Wed, Aug 17, 2011 at 10:00 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
> wrote:
> >
> > On Aug 17, 2011, at 9:17 PM, Chandler Carruth wrote:
> >
> > On Wed, Aug 17, 2011 at 8:56 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
> > wrote:
> >>
> >> On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:
> >>
> >> > This patch adds a topological sort routine for indexed graphs to
> >> > llvm/ADT.  This sort routine is currently used to traverse CFGs in
> >> > Clang when doing thread safety analysis (patch to be released
> >> > shortly).
> >>
> >> Could you explain why we need this in addition to
> >> include/llvm/ADT/PostOrderIterator.h?
> >
> > FYI, I'm not terribly familiar w/ PostOrderIterator (so maybe it would
> > actually serve here), but JSYK, the motivating use case is in a Clang
> > patch:
> http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20110815/045262.html
> >
> > I see.
> > AFAICT, the existing RPO iterator will give you the exact same ordering
> of
> > blocks, at least it will give you a topo-sort of the graph after removing
> > back-edges.
> > You can detect back-edges by keeping track of visited blocks in a
> BitVector
> > as you iterate through the RPO.
> > /jakob
> >
>
>
>
> --
> DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315
>
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From baldrick at free.fr  Thu Aug 18 12:20:31 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 17:20:31 -0000
Subject: [llvm-commits] [dragonegg] r137950 - /dragonegg/trunk/src/Types.cpp
Message-ID: <20110818172031.9360A2A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 12:20:31 2011
New Revision: 137950

URL: http://llvm.org/viewvc/llvm-project?rev=137950&view=rev
Log:
When joining with an size zero type, discard the size zero type.
Currently this doesn't do anything since we don't consider size
zero types in the first place.

Modified:
    dragonegg/trunk/src/Types.cpp

Modified: dragonegg/trunk/src/Types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=137950&r1=137949&r2=137950&view=diff
==============================================================================
--- dragonegg/trunk/src/Types.cpp (original)
+++ dragonegg/trunk/src/Types.cpp Thu Aug 18 12:20:31 2011
@@ -955,12 +955,18 @@
 /// disjoint from this one).  After this the range will be the convex hull of
 /// the ranges of the two fields.
 void TypedRange::JoinWith(const TypedRange &S) {
+  if (S.R.empty())
+    return;
+  if (R.empty()) {
+    *this = S;
+    return;
+  }
   // Use an integer type that covers both ranges.  Turning everything into an
   // integer like this is pretty nasty, but as we only get here for bitfields
   // it is fairly harmless.
   R = R.Join(S.R);
-  Ty = R.empty() ? 0 : IntegerType::get(Context, R.getWidth());
-  Starts = R.empty() ? 0 : R.getFirst();
+  Ty = IntegerType::get(Context, R.getWidth());
+  Starts = R.getFirst();
 }
 
 static Type *ConvertRecord(tree type) {



From bob.wilson at apple.com  Thu Aug 18 12:23:00 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 18 Aug 2011 10:23:00 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r137729	-
 /llvm-gcc-4.2/trunk/build_gcc
In-Reply-To: <22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>
References: <20110816174644.BFC112A6C12C@llvm.org>
	<22F2BBE8-A131-41DE-9BBC-38B19BDB34D5@apple.com>
Message-ID: <A234C355-EFC0-4D69-B8DB-1D5D58D9B391@apple.com>


On Aug 18, 2011, at 9:59 AM, Bob Wilson wrote:

> My nightly tester failed to build llvm-gcc last night due to this.  You need the "gnu89" change, e.g., svn r137181, as well.  Please fix.

Oh, never mind.  Eric pointed out to me that I was running the build in an unsupported way.  I see the "gnu89" change now.

> 
> On Aug 16, 2011, at 10:46 AM, Eric Christopher wrote:
> 
>> Author: echristo
>> Date: Tue Aug 16 12:46:44 2011
>> New Revision: 137729
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137729&view=rev
>> Log:
>> Lots of clang as the new black.
>> 
>> Modified:
>>   llvm-gcc-4.2/trunk/build_gcc
>> 
>> Modified: llvm-gcc-4.2/trunk/build_gcc
>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=137729&r1=137728&r2=137729&view=diff
>> ==============================================================================
>> --- llvm-gcc-4.2/trunk/build_gcc (original)
>> +++ llvm-gcc-4.2/trunk/build_gcc Tue Aug 16 12:46:44 2011
>> @@ -258,12 +258,12 @@
>> # LLVM LOCAL end
>> 
>> # If the user has set CC or CXX, respect their wishes.  If not,
>> -# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not
>> +# compile with clang/clang++ if available; if LLVM is not
>> # available, fall back to usual GCC/G++ default.
>> savedPATH=$PATH ; PATH="/Developer/usr/bin:$PATH"
>> -XTMPCC=$(which llvm-gcc)
>> +XTMPCC=$(which clang)
>> if [ x$CC  = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC  forcedCC=1  ; fi
>> -XTMPCC=$(which llvm-g++)
>> +XTMPCC=$(which clang++)
>> if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC forcedCXX=1 ; fi
>> PATH=$savedPATH
>> unset XTMPCC savedPATH
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Thu Aug 18 12:23:34 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 17:23:34 -0000
Subject: [llvm-commits] [dragonegg] r137951 - /dragonegg/trunk/src/Types.cpp
Message-ID: <20110818172335.0B4512A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 12:23:34 2011
New Revision: 137951

URL: http://llvm.org/viewvc/llvm-project?rev=137951&view=rev
Log:
Disable an extra check I added this morning - it fails when
building GCC.

Modified:
    dragonegg/trunk/src/Types.cpp

Modified: dragonegg/trunk/src/Types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=137951&r1=137950&r2=137951&view=diff
==============================================================================
--- dragonegg/trunk/src/Types.cpp (original)
+++ dragonegg/trunk/src/Types.cpp Thu Aug 18 12:23:34 2011
@@ -350,15 +350,17 @@
     }
   }
   // Check that the LLVM type has the same alignment or less than the GCC type.
-  if (Ty->isSized()) {
-    unsigned GCCAlign = TYPE_ALIGN(Tr);
-    unsigned LLVMAlign = getTargetData().getABITypeAlignment(Ty) * 8;
-    if (LLVMAlign > GCCAlign) {
-      errs() << "GCC align: " << GCCAlign << "; LLVM align: " << LLVMAlign
-        << "\n";
-      Mismatch = true;
-    }
-  }
+// FIXME: Reduce LLVM array alignment when the GCC array has a small alignment
+// (due to an alignment clause?), then turn this back on.
+//  if (Ty->isSized()) {
+//    unsigned GCCAlign = TYPE_ALIGN(Tr);
+//    unsigned LLVMAlign = getTargetData().getABITypeAlignment(Ty) * 8;
+//    if (LLVMAlign > GCCAlign) {
+//      errs() << "GCC align: " << GCCAlign << "; LLVM align: " << LLVMAlign
+//        << "\n";
+//      Mismatch = true;
+//    }
+//  }
   if (Mismatch) {
     errs() << "GCC: ";
     debug_tree(Tr);



From dpatel at apple.com  Thu Aug 18 12:24:05 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 10:24:05 -0700
Subject: [llvm-commits] [llvm] r137890 -
 /llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
In-Reply-To: <4E4C9610.1020409@mxc.ca>
References: <20110817224939.2C5532A6C12C@llvm.org> <4E4C9610.1020409@mxc.ca>
Message-ID: <57C0B6AE-0C78-4373-97E9-30EF809429D1@apple.com>

Nick,

On Aug 17, 2011, at 9:33 PM, Nick Lewycky wrote:

> Devang Patel wrote:
>> Author: dpatel
>> Date: Wed Aug 17 17:49:38 2011
>> New Revision: 137890
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137890&view=rev
>> Log:
>> Do not use DebugInfoFinder. Extract debug info directly from llvm.dbg.cu named mdnode.
> 
> Hi Devang,
> 
> This all still crashes on all programs because GCOVProfiling still tries to use SP.getCompileUnit() which is now an assert when called.
> 
> How can I tie a function/subprogram to the translation-unit/compile-unit it came from?

Now, compile-unit keeps track of its subprograms (earlier, each subprogram used to keep a pointer to its compile unit).  You can use DIcompileUnit::getSubprograms() to get all subprograms in a compile unit. The purpose of this change is to let llvm linker unique debug info MDNodes to significantly reduce memory pressure during LTO.

> The purpose is to ensure that after merging multiple .bc files, we still emit the individual .gcno/.gcda files -- one for each original .o file -- as we would have before.
> 
> Nick
> 
>> 
>> Modified:
>>     llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
>> 
>> Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137890&r1=137889&r2=137890&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Wed Aug 17 17:49:38 2011
>> @@ -60,11 +60,11 @@
>>      bool runOnModule(Module&M);
>> 
>>      // Create the GCNO files for the Module based on DebugInfo.
>> -    void emitGCNO(DebugInfoFinder&DIF);
>> +    void emitGCNO();
>> 
>>      // Modify the program to track transitions along edges and call into the
>>      // profiling runtime to emit .gcda files when run.
>> -    bool emitProfileArcs(DebugInfoFinder&DIF);
>> +    bool emitProfileArcs();
>> 
>>      // Get pointers to the functions in the runtime library.
>>      Constant *getStartFileFunc();
>> @@ -86,8 +86,7 @@
>> 
>>      // Add the function to write out all our counters to the global destructor
>>      // list.
>> -    void insertCounterWriteout(DebugInfoFinder&,
>> -                               SmallVector<std::pair<GlobalVariable *,
>> +    void insertCounterWriteout(SmallVector<std::pair<GlobalVariable *,
>>                                                       MDNode *>, 8>  &);
>> 
>>      std::string mangleName(DICompileUnit CU, std::string NewStem);
>> @@ -353,66 +352,66 @@
>>    this->M =&M;
>>    Ctx =&M.getContext();
>> 
>> -  DebugInfoFinder DIF;
>> -  DIF.processModule(M);
>> -
>> -  if (EmitNotes) emitGCNO(DIF);
>> -  if (EmitData) return emitProfileArcs(DIF);
>> +  if (EmitNotes) emitGCNO();
>> +  if (EmitData) return emitProfileArcs();
>>    return false;
>>  }
>> 
>> -void GCOVProfiler::emitGCNO(DebugInfoFinder&DIF) {
>> +void GCOVProfiler::emitGCNO() {
>>    DenseMap<const MDNode *, raw_fd_ostream *>  GcnoFiles;
>> -  for (DebugInfoFinder::iterator I = DIF.compile_unit_begin(),
>> -           E = DIF.compile_unit_end(); I != E; ++I) {
>> -    // Each compile unit gets its own .gcno file. This means that whether we run
>> -    // this pass over the original .o's as they're produced, or run it after
>> -    // LTO, we'll generate the same .gcno files.
>> -
>> -    DICompileUnit CU(*I);
>> -    raw_fd_ostream *&out = GcnoFiles[CU];
>> -    std::string ErrorInfo;
>> -    out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
>> -                             raw_fd_ostream::F_Binary);
>> -    if (!Use402Format)
>> -      out->write("oncg*404MVLL", 12);
>> -    else
>> -      out->write("oncg*204MVLL", 12);
>> -  }
>> -
>> -  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
>> -           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
>> -    DISubprogram SP(*SPI);
>> -    raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
>> -
>> -    Function *F = SP.getFunction();
>> -    if (!F) continue;
>> -    GCOVFunction Func(SP, os, Use402Format);
>> -
>> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> -      GCOVBlock&Block = Func.getBlock(BB);
>> -      TerminatorInst *TI = BB->getTerminator();
>> -      if (int successors = TI->getNumSuccessors()) {
>> -        for (int i = 0; i != successors; ++i) {
>> -          Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
>> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
>> +  if (CU_Nodes) {
>> +    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
>> +      // Each compile unit gets its own .gcno file. This means that whether we run
>> +      // this pass over the original .o's as they're produced, or run it after
>> +      // LTO, we'll generate the same .gcno files.
>> +
>> +      DICompileUnit CU(CU_Nodes->getOperand(i));
>> +      raw_fd_ostream *&out = GcnoFiles[CU];
>> +      std::string ErrorInfo;
>> +      out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo,
>> +                               raw_fd_ostream::F_Binary);
>> +      if (!Use402Format)
>> +        out->write("oncg*404MVLL", 12);
>> +      else
>> +        out->write("oncg*204MVLL", 12);
>> +
>> +      DIArray SPs = CU.getSubprograms();
>> +      for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
>> +        DISubprogram SP(SPs.getElement(i));
>> +        if (!SP.Verify()) continue;
>> +        raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
>> +
>> +        Function *F = SP.getFunction();
>> +        if (!F) continue;
>> +        GCOVFunction Func(SP, os, Use402Format);
>> +
>> +        for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> +          GCOVBlock&Block = Func.getBlock(BB);
>> +          TerminatorInst *TI = BB->getTerminator();
>> +          if (int successors = TI->getNumSuccessors()) {
>> +            for (int i = 0; i != successors; ++i) {
>> +              Block.addEdge(Func.getBlock(TI->getSuccessor(i)));
>> +            }
>> +          } else if (isa<ReturnInst>(TI)) {
>> +            Block.addEdge(Func.getReturnBlock());
>> +          }
>> +
>> +          uint32_t Line = 0;
>> +          for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
>> +            const DebugLoc&Loc = I->getDebugLoc();
>> +            if (Loc.isUnknown()) continue;
>> +            if (Line == Loc.getLine()) continue;
>> +            Line = Loc.getLine();
>> +            if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
>> +
>> +            GCOVLines&Lines = Block.getFile(SP.getFilename());
>> +            Lines.addLine(Loc.getLine());
>> +          }
>>          }
>> -      } else if (isa<ReturnInst>(TI)) {
>> -        Block.addEdge(Func.getReturnBlock());
>> -      }
>> -
>> -      uint32_t Line = 0;
>> -      for (BasicBlock::iterator I = BB->begin(), IE = BB->end(); I != IE; ++I) {
>> -        const DebugLoc&Loc = I->getDebugLoc();
>> -        if (Loc.isUnknown()) continue;
>> -        if (Line == Loc.getLine()) continue;
>> -        Line = Loc.getLine();
>> -        if (SP != findSubprogram(DIScope(Loc.getScope(*Ctx)))) continue;
>> -
>> -        GCOVLines&Lines = Block.getFile(SP.getFilename());
>> -        Lines.addLine(Loc.getLine());
>> +        Func.writeOut();
>>        }
>>      }
>> -    Func.writeOut();
>>    }
>> 
>>    for (DenseMap<const MDNode *, raw_fd_ostream *>::iterator
>> @@ -424,104 +423,107 @@
>>    }
>>  }
>> 
>> -bool GCOVProfiler::emitProfileArcs(DebugInfoFinder&DIF) {
>> -  if (DIF.subprogram_begin() == DIF.subprogram_end())
>> -    return false;
>> -
>> -  SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  CountersBySP;
>> -  for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(),
>> -           SPE = DIF.subprogram_end(); SPI != SPE; ++SPI) {
>> -    DISubprogram SP(*SPI);
>> -    Function *F = SP.getFunction();
>> -    if (!F) continue;
>> -
>> -    unsigned Edges = 0;
>> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> -      TerminatorInst *TI = BB->getTerminator();
>> -      if (isa<ReturnInst>(TI))
>> -        ++Edges;
>> -      else
>> -        Edges += TI->getNumSuccessors();
>> -    }
>> -
>> -    ArrayType *CounterTy =
>> +bool GCOVProfiler::emitProfileArcs() {
>> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
>> +  if (!CU_Nodes) return false;
>> +
>> +  bool Result = false;
>> +  for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
>> +    DICompileUnit CU(CU_Nodes->getOperand(i));
>> +    DIArray SPs = CU.getSubprograms();
>> +    SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  CountersBySP;
>> +    for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
>> +      DISubprogram SP(SPs.getElement(i));
>> +      if (!SP.Verify()) continue;
>> +      Function *F = SP.getFunction();
>> +      if (!F) continue;
>> +      if (!Result) Result = true;
>> +      unsigned Edges = 0;
>> +      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> +        TerminatorInst *TI = BB->getTerminator();
>> +        if (isa<ReturnInst>(TI))
>> +          ++Edges;
>> +        else
>> +          Edges += TI->getNumSuccessors();
>> +      }
>> +
>> +      ArrayType *CounterTy =
>>          ArrayType::get(Type::getInt64Ty(*Ctx), Edges);
>> -    GlobalVariable *Counters =
>> +      GlobalVariable *Counters =
>>          new GlobalVariable(*M, CounterTy, false,
>>                             GlobalValue::InternalLinkage,
>>                             Constant::getNullValue(CounterTy),
>>                             "__llvm_gcov_ctr", 0, false, 0);
>> -    CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
>> -
>> -    UniqueVector<BasicBlock *>  ComplexEdgePreds;
>> -    UniqueVector<BasicBlock *>  ComplexEdgeSuccs;
>> -
>> -    unsigned Edge = 0;
>> -    for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> -      TerminatorInst *TI = BB->getTerminator();
>> -      int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
>> -      if (Successors) {
>> -        IRBuilder<>  Builder(TI);
>> -
>> -        if (Successors == 1) {
>> -          Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
>> -                                                              Edge);
>> -          Value *Count = Builder.CreateLoad(Counter);
>> -          Count = Builder.CreateAdd(Count,
>> -                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
>> -          Builder.CreateStore(Count, Counter);
>> -        } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
>> -          Value *Sel = Builder.CreateSelect(
>> +      CountersBySP.push_back(std::make_pair(Counters, (MDNode*)SP));
>> +
>> +      UniqueVector<BasicBlock *>  ComplexEdgePreds;
>> +      UniqueVector<BasicBlock *>  ComplexEdgeSuccs;
>> +
>> +      unsigned Edge = 0;
>> +      for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
>> +        TerminatorInst *TI = BB->getTerminator();
>> +        int Successors = isa<ReturnInst>(TI) ? 1 : TI->getNumSuccessors();
>> +        if (Successors) {
>> +          IRBuilder<>  Builder(TI);
>> +
>> +          if (Successors == 1) {
>> +            Value *Counter = Builder.CreateConstInBoundsGEP2_64(Counters, 0,
>> +                                                                Edge);
>> +            Value *Count = Builder.CreateLoad(Counter);
>> +            Count = Builder.CreateAdd(Count,
>> +                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
>> +            Builder.CreateStore(Count, Counter);
>> +          } else if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
>> +            Value *Sel = Builder.CreateSelect(
>>                BI->getCondition(),
>>                ConstantInt::get(Type::getInt64Ty(*Ctx), Edge),
>>                ConstantInt::get(Type::getInt64Ty(*Ctx), Edge + 1));
>> -          SmallVector<Value *, 2>  Idx;
>> -          Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
>> -          Idx.push_back(Sel);
>> -          Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
>> -          Value *Count = Builder.CreateLoad(Counter);
>> -          Count = Builder.CreateAdd(Count,
>> -                                    ConstantInt::get(Type::getInt64Ty(*Ctx),1));
>> -          Builder.CreateStore(Count, Counter);
>> -        } else {
>> -          ComplexEdgePreds.insert(BB);
>> -          for (int i = 0; i != Successors; ++i)
>> -            ComplexEdgeSuccs.insert(TI->getSuccessor(i));
>> +            SmallVector<Value *, 2>  Idx;
>> +            Idx.push_back(Constant::getNullValue(Type::getInt64Ty(*Ctx)));
>> +            Idx.push_back(Sel);
>> +            Value *Counter = Builder.CreateInBoundsGEP(Counters, Idx);
>> +            Value *Count = Builder.CreateLoad(Counter);
>> +            Count = Builder.CreateAdd(Count,
>> +                                      ConstantInt::get(Type::getInt64Ty(*Ctx),1));
>> +            Builder.CreateStore(Count, Counter);
>> +          } else {
>> +            ComplexEdgePreds.insert(BB);
>> +            for (int i = 0; i != Successors; ++i)
>> +              ComplexEdgeSuccs.insert(TI->getSuccessor(i));
>> +          }
>> +          Edge += Successors;
>>          }
>> -        Edge += Successors;
>>        }
>> -    }
>> -
>> -    if (!ComplexEdgePreds.empty()) {
>> -      GlobalVariable *EdgeTable =
>> +
>> +      if (!ComplexEdgePreds.empty()) {
>> +        GlobalVariable *EdgeTable =
>>            buildEdgeLookupTable(F, Counters,
>>                                 ComplexEdgePreds, ComplexEdgeSuccs);
>> -      GlobalVariable *EdgeState = getEdgeStateValue();
>> -
>> -      Type *Int32Ty = Type::getInt32Ty(*Ctx);
>> -      for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
>> -        IRBuilder<>  Builder(ComplexEdgePreds[i+1]->getTerminator());
>> -        Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
>> -      }
>> -      for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
>> -        // call runtime to perform increment
>> -        BasicBlock::iterator InsertPt =
>> -          ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
>> -        IRBuilder<>  Builder(InsertPt);
>> -        Value *CounterPtrArray =
>> +        GlobalVariable *EdgeState = getEdgeStateValue();
>> +
>> +        Type *Int32Ty = Type::getInt32Ty(*Ctx);
>> +        for (int i = 0, e = ComplexEdgePreds.size(); i != e; ++i) {
>> +          IRBuilder<>  Builder(ComplexEdgePreds[i+1]->getTerminator());
>> +          Builder.CreateStore(ConstantInt::get(Int32Ty, i), EdgeState);
>> +        }
>> +        for (int i = 0, e = ComplexEdgeSuccs.size(); i != e; ++i) {
>> +          // call runtime to perform increment
>> +          BasicBlock::iterator InsertPt =
>> +            ComplexEdgeSuccs[i+1]->getFirstInsertionPt();
>> +          IRBuilder<>  Builder(InsertPt);
>> +          Value *CounterPtrArray =
>>              Builder.CreateConstInBoundsGEP2_64(EdgeTable, 0,
>>                                                 i * ComplexEdgePreds.size());
>> -        Builder.CreateCall2(getIncrementIndirectCounterFunc(),
>> -                            EdgeState, CounterPtrArray);
>> -        // clear the predecessor number
>> -        Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
>> +          Builder.CreateCall2(getIncrementIndirectCounterFunc(),
>> +                              EdgeState, CounterPtrArray);
>> +          // clear the predecessor number
>> +          Builder.CreateStore(ConstantInt::get(Int32Ty, 0xffffffff), EdgeState);
>> +        }
>>        }
>>      }
>> +    insertCounterWriteout(CountersBySP);
>>    }
>> -
>> -  insertCounterWriteout(DIF, CountersBySP);
>> -
>> -  return true;
>> +  return Result;
>>  }
>> 
>>  // All edges with successors that aren't branches are "complex", because it
>> @@ -627,7 +629,6 @@
>>  }
>> 
>>  void GCOVProfiler::insertCounterWriteout(
>> -    DebugInfoFinder&DIF,
>>      SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>  &CountersBySP) {
>>    FunctionType *WriteoutFTy =
>>        FunctionType::get(Type::getVoidTy(*Ctx), false);
>> @@ -643,29 +644,31 @@
>>    Constant *EmitArcs = getEmitArcsFunc();
>>    Constant *EndFile = getEndFileFunc();
>> 
>> -  for (DebugInfoFinder::iterator CUI = DIF.compile_unit_begin(),
>> -           CUE = DIF.compile_unit_end(); CUI != CUE; ++CUI) {
>> -    DICompileUnit compile_unit(*CUI);
>> -    std::string FilenameGcda = mangleName(compile_unit, "gcda");
>> -    Builder.CreateCall(StartFile,
>> -                       Builder.CreateGlobalStringPtr(FilenameGcda));
>> -    for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
>> +  NamedMDNode *CU_Nodes = M->getNamedMetadata("llvm.dbg.cu");
>> +  if (CU_Nodes) {
>> +    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) {
>> +      DICompileUnit compile_unit(CU_Nodes->getOperand(i));
>> +      std::string FilenameGcda = mangleName(compile_unit, "gcda");
>> +      Builder.CreateCall(StartFile,
>> +                         Builder.CreateGlobalStringPtr(FilenameGcda));
>> +      for (SmallVector<std::pair<GlobalVariable *, MDNode *>, 8>::iterator
>>               I = CountersBySP.begin(), E = CountersBySP.end();
>> -         I != E; ++I) {
>> -      DISubprogram SP(I->second);
>> -      intptr_t ident = reinterpret_cast<intptr_t>(I->second);
>> -      Builder.CreateCall2(EmitFunction,
>> -                          ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
>> -                          Builder.CreateGlobalStringPtr(SP.getName()));
>> -
>> -      GlobalVariable *GV = I->first;
>> -      unsigned Arcs =
>> +           I != E; ++I) {
>> +        DISubprogram SP(I->second);
>> +        intptr_t ident = reinterpret_cast<intptr_t>(I->second);
>> +        Builder.CreateCall2(EmitFunction,
>> +                            ConstantInt::get(Type::getInt32Ty(*Ctx), ident),
>> +                            Builder.CreateGlobalStringPtr(SP.getName()));
>> +
>> +        GlobalVariable *GV = I->first;
>> +        unsigned Arcs =
>>            cast<ArrayType>(GV->getType()->getElementType())->getNumElements();
>> -      Builder.CreateCall2(EmitArcs,
>> -                          ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
>> -                          Builder.CreateConstGEP2_64(GV, 0, 0));
>> +        Builder.CreateCall2(EmitArcs,
>> +                            ConstantInt::get(Type::getInt32Ty(*Ctx), Arcs),
>> +                            Builder.CreateConstGEP2_64(GV, 0, 0));
>> +      }
>> +      Builder.CreateCall(EndFile);
>>      }
>> -    Builder.CreateCall(EndFile);
>>    }
>>    Builder.CreateRetVoid();
>> 
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 


From stoklund at 2pi.dk  Thu Aug 18 12:28:55 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 18 Aug 2011 10:28:55 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
 llvm/ADT
In-Reply-To: <CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
	<CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
	<CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
Message-ID: <C8F7CFBC-6F80-4BBE-9F37-7E3EDAECD964@2pi.dk>


On Aug 18, 2011, at 10:17 AM, Chandler Carruth wrote:

> On Thu, Aug 18, 2011 at 10:03 AM, Delesley Hutchins <delesley at google.com> wrote:
> AFAICT, the RPO iterator does not do what we need.  For example,
> assume we have the following graph (pardon the bad ASCII graphics):
> 
>   /---> (2) ----------\
> (1)                     --> (5)
>   \---> (3) ---> (4)--/
> 
> I believe the RPO iterator will traverse this graph as 5-2-4-3-1,
> which is a standard depth-first post-order traversal.
> 
> What we want is a topological traversal, which is 1-2-3-4-5; every
> predecessor of a node must be traversed before the node itself.
> 
> What about the reverse of the RPO violates this constraint? 1-3-4-2-5 looks like it satisfies your constraint. I think Jakub is aware that we would have to reverse the order, and was just claiming that such a reversed order satisfied the constraints of a topological ordering.

Right, the 'R' in RPO stands for 'reverse'. Sorry if that wasn't clear.

See the ReversePostOrderTraversal class in the PostOrderIterator.h header file.

Given a DAG, it is easy to see that A --> B implies A > B in the DFS post-order. Thus, A < B in the reverse post-order.

/jakob

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From sabre at nondot.org  Thu Aug 18 12:39:28 2011
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 18 Aug 2011 17:39:28 -0000
Subject: [llvm-commits] [llvm] r137953 - in /llvm/trunk:
 include/llvm/DerivedTypes.h lib/VMCore/Type.cpp
Message-ID: <20110818173929.092C82A6C12C@llvm.org>

Author: lattner
Date: Thu Aug 18 12:39:28 2011
New Revision: 137953

URL: http://llvm.org/viewvc/llvm-project?rev=137953&view=rev
Log:
Rip out the old StructType APIs as warned about on llvmdev last week.

Modified:
    llvm/trunk/include/llvm/DerivedTypes.h
    llvm/trunk/lib/VMCore/Type.cpp

Modified: llvm/trunk/include/llvm/DerivedTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=137953&r1=137952&r2=137953&view=diff
==============================================================================
--- llvm/trunk/include/llvm/DerivedTypes.h (original)
+++ llvm/trunk/include/llvm/DerivedTypes.h Thu Aug 18 12:39:28 2011
@@ -224,20 +224,6 @@
   static StructType *create(LLVMContext &Context, ArrayRef<Type*> Elements);
   static StructType *create(StringRef Name, Type *elt1, ...) END_WITH_NULL;
 
-#if 1
-  // FIXME: Remove these.
-  bool isAnonymous() const {return (getSubclassData() & SCDB_IsLiteral) != 0;}
-  static StructType *createNamed(LLVMContext &Context,
-                                 StringRef Name);
-  
-  static StructType *createNamed(StringRef Name, ArrayRef<Type*> Elements,
-                                 bool isPacked = false);
-  static StructType *createNamed(LLVMContext &Context, StringRef Name,
-                                 ArrayRef<Type*> Elements,
-                                 bool isPacked = false);
-  static StructType *createNamed(StringRef Name, Type *elt1, ...) END_WITH_NULL;
-#endif
-  
   /// StructType::get - This static method is the primary way to create a
   /// literal StructType.
   static StructType *get(LLVMContext &Context, ArrayRef<Type*> Elements,

Modified: llvm/trunk/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=137953&r1=137952&r2=137953&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Type.cpp (original)
+++ llvm/trunk/lib/VMCore/Type.cpp Thu Aug 18 12:39:28 2011
@@ -521,44 +521,6 @@
 }
 
 
-#if 1
-
-StructType *StructType::createNamed(LLVMContext &Context, StringRef Name,
-                                    ArrayRef<Type*> Elements, bool isPacked) {
-  StructType *ST = createNamed(Context, Name);
-  ST->setBody(Elements, isPacked);
-  return ST;
-}
-
-StructType *StructType::createNamed(LLVMContext &Context, StringRef Name) {
-  StructType *ST = new (Context.pImpl->TypeAllocator) StructType(Context);
-  if (!Name.empty())
-    ST->setName(Name);
-  return ST;
-}
-
-
-StructType *StructType::createNamed(StringRef Name, ArrayRef<Type*> Elements,
-                                    bool isPacked) {
-  assert(!Elements.empty() &&
-         "This method may not be invoked with an empty list");
-  return createNamed(Elements[0]->getContext(), Name, Elements, isPacked);
-}
-
-StructType *StructType::createNamed(StringRef Name, Type *type, ...) {
-  assert(type != 0 && "Cannot create a struct type with no elements with this");
-  LLVMContext &Ctx = type->getContext();
-  va_list ap;
-  SmallVector<llvm::Type*, 8> StructFields;
-  va_start(ap, type);
-  while (type) {
-    StructFields.push_back(type);
-    type = va_arg(ap, llvm::Type*);
-  }
-  return llvm::StructType::createNamed(Ctx, Name, StructFields);
-}
-#endif
-
 StringRef StructType::getName() const {
   assert(!isLiteral() && "Literal structs never have names");
   if (SymbolTableEntry == 0) return StringRef();



From resistor at mac.com  Thu Aug 18 12:43:53 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 17:43:53 -0000
Subject: [llvm-commits] [llvm] r137954 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
Message-ID: <20110818174353.2653C2A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 12:43:52 2011
New Revision: 137954

URL: http://llvm.org/viewvc/llvm-project?rev=137954&view=rev
Log:
Port over BL/BLX to disassembly tests.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=137954&r1=137953&r2=137954&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Thu Aug 18 12:43:52 2011
@@ -19,7 +19,6 @@
 0xd2 0x1c
 0x08 0x32
 
-
 #------------------------------------------------------------------------------
 # ADD (register)
 #------------------------------------------------------------------------------
@@ -40,7 +39,6 @@
 0x5a 0x11
 0x5a 0x10
 
-
 #------------------------------------------------------------------------------
 # ASR (register)
 #------------------------------------------------------------------------------
@@ -55,7 +53,6 @@
 
 0xb1 0x43
 
-
 #------------------------------------------------------------------------------
 # BKPT
 #------------------------------------------------------------------------------
@@ -65,3 +62,17 @@
 0x00 0xbe
 0xff 0xbe
 
+#------------------------------------------------------------------------------
+# BLX (register)
+#------------------------------------------------------------------------------
+# CHECK: blx r4
+
+0xa0 0x47
+
+#------------------------------------------------------------------------------
+# BX
+#------------------------------------------------------------------------------
+# CHECK: bx r2
+
+0x10 0x47
+



From delesley at google.com  Thu Aug 18 12:50:19 2011
From: delesley at google.com (Delesley Hutchins)
Date: Thu, 18 Aug 2011 10:50:19 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
	<CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
	<CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
Message-ID: <CAF6KqwX1jbd3ZszhbDEFC9NXE=LWSLj3azQvfQBDH2GPtQzJyQ@mail.gmail.com>

Good point.  Yes, the RPO iterator (not PO iterator -- my bad) does
seem to do what we need.  The ordering is slightly different, but it
obeys the same constraints.  Moreover, the efficiency of RPO is
somewhat better, since it does not attempt to track depth so
precisely.  I am withdrawing the patch.

  -DeLesley

On Thu, Aug 18, 2011 at 10:17 AM, Chandler Carruth <chandlerc at google.com> wrote:
> On Thu, Aug 18, 2011 at 10:03 AM, Delesley Hutchins <delesley at google.com>
> wrote:
>>
>> AFAICT, the RPO iterator does not do what we need. ?For example,
>> assume we have the following graph (pardon the bad ASCII graphics):
>>
>> ? /---> (2) ----------\
>> (1) ? ? ? ? ? ? ? ? ? ? --> (5)
>> ? \---> (3) ---> (4)--/
>>
>> I believe the RPO iterator will traverse this graph as 5-2-4-3-1,
>> which is a standard depth-first post-order traversal.
>>
>> What we want is a topological traversal, which is 1-2-3-4-5; every
>> predecessor of a node must be traversed before the node itself.
>
> What about the reverse of the RPO violates this constraint? 1-3-4-2-5 looks
> like it satisfies your constraint. I think Jakub is aware that we would have
> to reverse the order, and was just claiming that such a reversed order
> satisfied the constraints of a topological ordering.
>
>>
>> Notice that a topological traversal is neither depth-first (that would
>> be 1-2-5-3-4), nor breadth-first (1-2-3-5-4); we want to ensure that 2
>> and 4 are traversed before 5.
>>
>> This patch does three things to achieve the topological traversal:
>> (1) Depth-first traversal to identify back-edges and assign depths.
>> (2) Sort nodes according to depth.
>> (3) Traversal of the sorted list of nodes.
>>
>> ?-DeLesley
>>
>> On Wed, Aug 17, 2011 at 10:00 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
>> wrote:
>> >
>> > On Aug 17, 2011, at 9:17 PM, Chandler Carruth wrote:
>> >
>> > On Wed, Aug 17, 2011 at 8:56 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
>> > wrote:
>> >>
>> >> On Aug 17, 2011, at 3:52 PM, Delesley Hutchins wrote:
>> >>
>> >> > This patch adds a topological sort routine for indexed graphs to
>> >> > llvm/ADT. ?This sort routine is currently used to traverse CFGs in
>> >> > Clang when doing thread safety analysis (patch to be released
>> >> > shortly).
>> >>
>> >> Could you explain why we need this in addition to
>> >> include/llvm/ADT/PostOrderIterator.h?
>> >
>> > FYI, I'm not terribly familiar w/ PostOrderIterator (so maybe it would
>> > actually serve here), but JSYK, the motivating use case is in a Clang
>> >
>> > patch:?http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20110815/045262.html
>> >
>> > I see.
>> > AFAICT, the existing RPO iterator will give you the exact same ordering
>> > of
>> > blocks, at least it will give you a topo-sort of the graph after
>> > removing
>> > back-edges.
>> > You can detect back-edges by keeping track of visited blocks in a
>> > BitVector
>> > as you iterate through the RPO.
>> > /jakob
>> >
>>
>>
>>
>> --
>> DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315
>
>



-- 
DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315


From grosbach at apple.com  Thu Aug 18 12:51:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 17:51:36 -0000
Subject: [llvm-commits] [llvm] r137956 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrThumb.td ARMInstrThumb2.td
Message-ID: <20110818175136.45B5C2A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 12:51:36 2011
New Revision: 137956

URL: http://llvm.org/viewvc/llvm-project?rev=137956&view=rev
Log:
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137956&r1=137955&r2=137956&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Aug 18 12:51:36 2011
@@ -490,31 +490,6 @@
   let Inst{7-0} = target;
 }
 
-// Compare and branch on zero / non-zero
-let isBranch = 1, isTerminator = 1 in {
-  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
-                  "cbz\t$Rn, $target", []>,
-              T1Misc<{0,0,?,1,?,?,?}> {
-    // A8.6.27
-    bits<6> target;
-    bits<3> Rn;
-    let Inst{9}   = target{5};
-    let Inst{7-3} = target{4-0};
-    let Inst{2-0} = Rn;
-  }
-
-  def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
-                  "cbnz\t$Rn, $target", []>,
-              T1Misc<{1,0,?,1,?,?,?}> {
-    // A8.6.27
-    bits<6> target;
-    bits<3> Rn;
-    let Inst{9}   = target{5};
-    let Inst{7-3} = target{4-0};
-    let Inst{2-0} = Rn;
-  }
-}
-
 // Tail calls
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
   // Darwin versions.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=137956&r1=137955&r2=137956&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Aug 18 12:51:36 2011
@@ -3052,6 +3052,34 @@
   let Inst{19-16} = func;
 }
 
+// Compare and branch on zero / non-zero
+let isBranch = 1, isTerminator = 1 in {
+  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
+                  "cbz\t$Rn, $target", []>,
+              T1Misc<{0,0,?,1,?,?,?}>,
+              Requires<[IsThumb2]> {
+    // A8.6.27
+    bits<6> target;
+    bits<3> Rn;
+    let Inst{9}   = target{5};
+    let Inst{7-3} = target{4-0};
+    let Inst{2-0} = Rn;
+  }
+
+  def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
+                  "cbnz\t$Rn, $target", []>,
+              T1Misc<{1,0,?,1,?,?,?}>,
+              Requires<[IsThumb2]> {
+    // A8.6.27
+    bits<6> target;
+    bits<3> Rn;
+    let Inst{9}   = target{5};
+    let Inst{7-3} = target{4-0};
+    let Inst{2-0} = Rn;
+  }
+}
+
+
 // Change Processor State is a system instruction -- for disassembly and
 // parsing only.
 // FIXME: Since the asm parser has currently no clean way to handle optional



From grosbach at apple.com  Thu Aug 18 12:55:03 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 17:55:03 -0000
Subject: [llvm-commits] [llvm] r137957 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110818175503.A7EA02A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 12:55:03 2011
New Revision: 137957

URL: http://llvm.org/viewvc/llvm-project?rev=137957&view=rev
Log:
Thumb assembly parsing and encoding test for CMN.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137957&r1=137956&r2=137957&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 12:55:03 2011
@@ -134,3 +134,13 @@
         bx r2
 
 @ CHECK: bx	r2                      @ encoding: [0x10,0x47]
+
+
+ at ------------------------------------------------------------------------------
+@ CMN
+ at ------------------------------------------------------------------------------
+
+        cmn r5, r1
+
+@ CHECK: cmn	r5, r1                  @ encoding: [0xcd,0x42]
+



From isanbard at gmail.com  Thu Aug 18 12:57:40 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 10:57:40 -0700
Subject: [llvm-commits] [llvm] r137926 -
 /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
In-Reply-To: <A78FA5D7-3E9B-4CA2-8AE9-738F8EFF229F@apple.com>
References: <20110818052524.2068B2A6C12C@llvm.org>
	<A78FA5D7-3E9B-4CA2-8AE9-738F8EFF229F@apple.com>
Message-ID: <EA16219C-D846-4DC1-9568-0F0F6AAA0ECA@gmail.com>

On Aug 17, 2011, at 11:07 PM, Chris Lattner wrote:

> 
> On Aug 17, 2011, at 10:25 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Thu Aug 18 00:25:23 2011
>> New Revision: 137926
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=137926&view=rev
>> Log:
>> Split out the analysis updating code into a helper function. No intended
>> functionality change.
> 
> Hi Bill,
> 
> Please use static for functions, not anonymous namespaces.
> http://llvm.org/docs/CodingStandards.html#micro_anonns
> 
Ah! Okay. Sorry. :-)

-bw



From isanbard at gmail.com  Thu Aug 18 12:57:57 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 17:57:57 -0000
Subject: [llvm-commits] [llvm] r137959 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110818175757.3BCAF2A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 12:57:57 2011
New Revision: 137959

URL: http://llvm.org/viewvc/llvm-project?rev=137959&view=rev
Log:
Use static instead of anonymous namespace.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137959&r1=137958&r2=137959&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 12:57:57 2011
@@ -314,13 +314,12 @@
   return New;
 }
 
-namespace {
-
 /// UpdateAnalysisInformation - Update DominatorTree, LoopInfo, and LCCSA
 /// analysis information.
-void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB,
-                               BasicBlock *const *Preds,
-                               unsigned NumPreds, Pass *P, bool &HasLoopExit) {
+static void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB,
+                                      BasicBlock *const *Preds,
+                                      unsigned NumPreds, Pass *P,
+                                      bool &HasLoopExit) {
   if (!P) return;
 
   LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>();
@@ -386,8 +385,6 @@
   }
 }
 
-} // end anonymous namespace
-
 /// SplitBlockPredecessors - This method transforms BB by introducing a new
 /// basic block into the function, and moving some of the predecessors of BB to
 /// be predecessors of the new block.  The new predecessors are indicated by the



From james.molloy at arm.com  Thu Aug 18 13:03:02 2011
From: james.molloy at arm.com (James Molloy)
Date: Thu, 18 Aug 2011 18:03:02 -0000
Subject: [llvm-commits] [llvm] r137960 -
	/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt
Message-ID: <20110818180302.7CB332A6C12C@llvm.org>

Author: jamesm
Date: Thu Aug 18 13:03:02 2011
New Revision: 137960

URL: http://llvm.org/viewvc/llvm-project?rev=137960&view=rev
Log:
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt?rev=137960&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt Thu Aug 18 13:03:02 2011
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X|
+# -------------------------------------------------------------------------------------------------
+# 
+# A8.6.68 LDRD (register)
+# if Rt{0} = 1 then UNDEFINED;
+0xd0 0x10 0x00 0x00



From baldrick at free.fr  Thu Aug 18 13:07:33 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 18 Aug 2011 18:07:33 -0000
Subject: [llvm-commits] [dragonegg] r137962 -
	/dragonegg/trunk/src/Constants.cpp
Message-ID: <20110818180733.88AAC2A6C12C@llvm.org>

Author: baldrick
Date: Thu Aug 18 13:07:33 2011
New Revision: 137962

URL: http://llvm.org/viewvc/llvm-project?rev=137962&view=rev
Log:
When having trouble because the constant doesn't fit well in
the range of bits it is supposed to fill, immediately fall
back to turning it into a bunch of bytes, rather than first
trying to turn it into a (possibly giant) integer.  There
doesn't seem to be much advantage to using an integer, and
avoiding funky integers means PR10641 trouble is avoided.

Modified:
    dragonegg/trunk/src/Constants.cpp

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=137962&r1=137961&r2=137962&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Thu Aug 18 13:07:33 2011
@@ -1028,21 +1028,16 @@
       assert(isSafeToReturnContentsDirectly(TD) && "Unit over aligned?");
       return C;
     }
-    assert(R.getWidth() % BITS_PER_UNIT == 0 && "Boundaries not aligned?");
-    unsigned Units = R.getWidth() / BITS_PER_UNIT;
-    // Turn the contents into a bunch of bits.  Remember the returned value as
+    // Turn the contents into a bunch of bytes.  Remember the returned value as
     // an optimization in case we are called again.
     // TODO: If the contents only need to be truncated and have struct or array
     // type then we could try to do the truncation by dropping or modifying the
     // last elements of the constant, maybe yielding something less horrible.
-    C = getAsBits();
+    assert(R.getWidth() % BITS_PER_UNIT == 0 && "Boundaries not aligned?");
+    unsigned Units = R.getWidth() / BITS_PER_UNIT;
+    C = InterpretAsType(C, GetUnitType(Context, Units), R.getFirst() - Starts,
+                        Folder);
     Starts = R.getFirst();
-    if (isSafeToReturnContentsDirectly(TD))
-      return C;
-    // The integer type used to hold the bits was too big (for example an i24
-    // typically occupies 32 bits so is too big for a range of 24 bits).  Turn
-    // it into an array of bytes instead.
-    C = InterpretAsType(C, GetUnitType(Context, Units), 0, Folder);
     assert(isSafeToReturnContentsDirectly(TD) && "Unit over aligned?");
     return C;
   }
@@ -1054,6 +1049,12 @@
 /// disjoint from this one).  After this the range will be the convex hull of
 /// the ranges of the two fields.
 void FieldContents::JoinWith(const FieldContents &S) {
+  if (S.R.empty())
+    return;
+  if (R.empty()) {
+    *this = S;
+    return;
+  }
   // Consider the contents of the fields to be bunches of bits and paste them
   // together.  This can result in a nasty integer constant expression, but as
   // we only get here for bitfields that's mostly harmless.



From grosbach at apple.com  Thu Aug 18 13:08:30 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 18:08:30 -0000
Subject: [llvm-commits] [llvm] r137963 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110818180830.204B42A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 13:08:29 2011
New Revision: 137963

URL: http://llvm.org/viewvc/llvm-project?rev=137963&view=rev
Log:
Thumb assembly parsing and encoding for CMP.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137963&r1=137962&r2=137963&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Aug 18 13:08:29 2011
@@ -910,7 +910,7 @@
 
 // CMP immediate
 let isCompare = 1, Defs = [CPSR] in {
-def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
+def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
                   "cmp", "\t$Rn, $imm8",
                   [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
              T1General<{1,0,1,?,?}> {

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137963&r1=137962&r2=137963&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 13:08:29 2011
@@ -144,3 +144,14 @@
 
 @ CHECK: cmn	r5, r1                  @ encoding: [0xcd,0x42]
 
+
+ at ------------------------------------------------------------------------------
+@ CMP
+ at ------------------------------------------------------------------------------
+        cmp r6, #32
+        cmp r3, r4
+        cmp r8, r1
+
+@ CHECK: cmp	r6, #32                 @ encoding: [0x20,0x2e]
+@ CHECK: cmp	r3, r4                  @ encoding: [0xa3,0x42]
+@ CHECK: cmp	r8, r1                  @ encoding: [0x88,0x45]



From mcgrathr at google.com  Thu Aug 18 11:11:33 2011
From: mcgrathr at google.com (Roland McGrath)
Date: Thu, 18 Aug 2011 09:11:33 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5ReBLLekCj_auNG1n=MxxsSm4qGL=ny_RBcLoAxK7vxbew@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<CAOei5RfYuT_W9VqL3PNx=TRwxfFKhUK=otXSzdk5fqH+3MRWbg@mail.gmail.com>
	<CAOei5ReBLLekCj_auNG1n=MxxsSm4qGL=ny_RBcLoAxK7vxbew@mail.gmail.com>
Message-ID: <CAB=4xhq+S6RgPcz98oEorvDNpa-fOZXZOZyo6C=djCbTG6JAKQ@mail.gmail.com>

The license on config.sub and config.guess is still GPLv2+.  But it hardly
matters.  That license applies only to the script itself, no matter what
package you include it in.  Since there is no binary form of a shell
script, and even if there were, you don't include these things in anything
you produce, only in the source distribution of your package, effectively
the only requirement of the license is that you include a copy of the GPLv2
in your source distribution.

Furthermore, both these files have a special exception that exempts you
from even that if you are using an Autoconf-generated configure script:

# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.


Thanks,
Roland

From grosbach at apple.com  Thu Aug 18 13:10:38 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 18:10:38 -0000
Subject: [llvm-commits] [llvm] r137964 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110818181038.DCF022A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 13:10:38 2011
New Revision: 137964

URL: http://llvm.org/viewvc/llvm-project?rev=137964&view=rev
Log:
Thumb assembly parsing and encoding for EOR.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137964&r1=137963&r2=137964&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 13:10:38 2011
@@ -155,3 +155,10 @@
 @ CHECK: cmp	r6, #32                 @ encoding: [0x20,0x2e]
 @ CHECK: cmp	r3, r4                  @ encoding: [0xa3,0x42]
 @ CHECK: cmp	r8, r1                  @ encoding: [0x88,0x45]
+
+ at ------------------------------------------------------------------------------
+@ EOR
+ at ------------------------------------------------------------------------------
+        eors r4, r5
+
+@ CHECK: eors	r4, r5                  @ encoding: [0x6c,0x40]



From bruno.cardoso at gmail.com  Thu Aug 18 13:33:29 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 18 Aug 2011 11:33:29 -0700
Subject: [llvm-commits] [llvm] r137804 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td
 test/CodeGen/Mips/extins.ll
In-Reply-To: <20110817020542.79CAE2A6C12C@llvm.org>
References: <20110817020542.79CAE2A6C12C@llvm.org>
Message-ID: <CACk9FxYrbVSkgx54Oqj-s14ibKbk4QwOefbwqoqET-2XDo+SmA@mail.gmail.com>

Hi,

> +namespace {
> + ?// If I is a shifted mask, set the size (Size) and the first bit of the
> + ?// mask (Pos), and return true.
> + ?bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
> + ? ? ? ? ? ? ? ? ? ? uint64_t &Size) {
> + ? ?assert(SizeInBits == 32 || SizeInBits == 64);
> + ? ?bool Is32Bits = (SizeInBits == 32);
> +
> + ? ?if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
> + ? ? ? ?(!Is32Bits && !isShiftedMask_64(I)))
> + ? ? ?return false;
> +
> + ? ?Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
> + ? ?Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
> + ? ?return true;
> + ?}
> +}
> +

Inspired by Chris recent reply:
Please use static for functions, not anonymous namespaces.
http://llvm.org/docs/CodingStandards.html#micro_anonns

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From dpatel at apple.com  Thu Aug 18 13:40:49 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 18:40:49 -0000
Subject: [llvm-commits] [llvm] r137968 - in /llvm/trunk/test/Linker:
 2011-08-18-unique-debug-type.ll 2011-08-18-unique-debug-type2.ll
Message-ID: <20110818184049.39D922A6C12C@llvm.org>

Author: dpatel
Date: Thu Aug 18 13:40:49 2011
New Revision: 137968

URL: http://llvm.org/viewvc/llvm-project?rev=137968&view=rev
Log:
Add test to check type uniquing.

Added:
    llvm/trunk/test/Linker/2011-08-18-unique-debug-type.ll
    llvm/trunk/test/Linker/2011-08-18-unique-debug-type2.ll

Added: llvm/trunk/test/Linker/2011-08-18-unique-debug-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-18-unique-debug-type.ll?rev=137968&view=auto
==============================================================================
--- llvm/trunk/test/Linker/2011-08-18-unique-debug-type.ll (added)
+++ llvm/trunk/test/Linker/2011-08-18-unique-debug-type.ll Thu Aug 18 13:40:49 2011
@@ -0,0 +1,26 @@
+
+; RUN: llvm-link %s %p/2011-08-18-unique-debug-type2.ll -S -o - | grep "int" | count 1
+; Test to check only one MDNode for "int" after linking.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+define i32 @foo() nounwind uwtable ssp {
+entry:
+  ret i32 1, !dbg !10
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"one.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @foo, null, null} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !"one.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{metadata !9}
+!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 1, i32 13, metadata !11, null}
+!11 = metadata !{i32 720907, metadata !5, i32 1, i32 11, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+

Added: llvm/trunk/test/Linker/2011-08-18-unique-debug-type2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-18-unique-debug-type2.ll?rev=137968&view=auto
==============================================================================
--- llvm/trunk/test/Linker/2011-08-18-unique-debug-type2.ll (added)
+++ llvm/trunk/test/Linker/2011-08-18-unique-debug-type2.ll Thu Aug 18 13:40:49 2011
@@ -0,0 +1,25 @@
+; This file is for use with 2011-08-10-unique-debug-type.ll
+; RUN: true
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+define i32 @bar() nounwind uwtable ssp {
+entry:
+  ret i32 2, !dbg !10
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"two.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @bar, null, null} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !"two.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{metadata !9}
+!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 1, i32 13, metadata !11, null}
+!11 = metadata !{i32 720907, metadata !5, i32 1, i32 11, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]



From dpatel at apple.com  Thu Aug 18 13:50:25 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 18:50:25 -0000
Subject: [llvm-commits] [llvm] r137969 - in /llvm/trunk/test/Linker:
 2011-08-18-unique-class-type.ll 2011-08-18-unique-class-type2.ll
Message-ID: <20110818185025.76C632A6C12C@llvm.org>

Author: dpatel
Date: Thu Aug 18 13:50:25 2011
New Revision: 137969

URL: http://llvm.org/viewvc/llvm-project?rev=137969&view=rev
Log:
Add another test.

Added:
    llvm/trunk/test/Linker/2011-08-18-unique-class-type.ll
    llvm/trunk/test/Linker/2011-08-18-unique-class-type2.ll

Added: llvm/trunk/test/Linker/2011-08-18-unique-class-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-18-unique-class-type.ll?rev=137969&view=auto
==============================================================================
--- llvm/trunk/test/Linker/2011-08-18-unique-class-type.ll (added)
+++ llvm/trunk/test/Linker/2011-08-18-unique-class-type.ll Thu Aug 18 13:50:25 2011
@@ -0,0 +1,35 @@
+; RUN: llvm-link %s %p/2011-08-18-unique-class-type2.ll -S -o - | grep DW_TAG_class_type | count 1
+; Test to check there is only one MDNode for class A after linking.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+%"class.N1::A" = type { i8 }
+
+define void @_Z3fooN2N11AE() nounwind uwtable ssp {
+entry:
+  %mya = alloca %"class.N1::A", align 1
+  call void @llvm.dbg.declare(metadata !{%"class.N1::A"* %mya}, metadata !9), !dbg !13
+  ret void, !dbg !14
+}
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 4, metadata !"n1.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooN2N11AE", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3fooN2N11AE, null, null} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !"n1.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{null}
+!9 = metadata !{i32 721153, metadata !5, metadata !"mya", metadata !6, i32 16777220, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
+!10 = metadata !{i32 720898, metadata !11, metadata !"A", metadata !12, i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
+!11 = metadata !{i32 720953, null, metadata !"N1", metadata !12, i32 2} ; [ DW_TAG_namespace ]
+!12 = metadata !{i32 720937, metadata !"./n.h", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!13 = metadata !{i32 4, i32 12, metadata !5, null}
+!14 = metadata !{i32 4, i32 18, metadata !15, null}
+!15 = metadata !{i32 720907, metadata !5, i32 4, i32 17, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]

Added: llvm/trunk/test/Linker/2011-08-18-unique-class-type2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-18-unique-class-type2.ll?rev=137969&view=auto
==============================================================================
--- llvm/trunk/test/Linker/2011-08-18-unique-class-type2.ll (added)
+++ llvm/trunk/test/Linker/2011-08-18-unique-class-type2.ll Thu Aug 18 13:50:25 2011
@@ -0,0 +1,35 @@
+; This file is for use with 2011-08-10-unique-class-type.ll
+; RUN: true
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+%"class.N1::A" = type { i8 }
+
+define void @_Z3barN2N11AE() nounwind uwtable ssp {
+entry:
+  %youra = alloca %"class.N1::A", align 1
+  call void @llvm.dbg.declare(metadata !{%"class.N1::A"* %youra}, metadata !9), !dbg !13
+  ret void, !dbg !14
+}
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 4, metadata !"n2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"_Z3barN2N11AE", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3barN2N11AE, null, null} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !"n2.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{null}
+!9 = metadata !{i32 721153, metadata !5, metadata !"youra", metadata !6, i32 16777220, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
+!10 = metadata !{i32 720898, metadata !11, metadata !"A", metadata !12, i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
+!11 = metadata !{i32 720953, null, metadata !"N1", metadata !12, i32 2} ; [ DW_TAG_namespace ]
+!12 = metadata !{i32 720937, metadata !"./n.h", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!13 = metadata !{i32 4, i32 12, metadata !5, null}
+!14 = metadata !{i32 4, i32 20, metadata !15, null}
+!15 = metadata !{i32 720907, metadata !5, i32 4, i32 19, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]



From chandlerc at google.com  Thu Aug 18 13:52:33 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 18 Aug 2011 11:52:33 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAF6KqwX1jbd3ZszhbDEFC9NXE=LWSLj3azQvfQBDH2GPtQzJyQ@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
	<CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
	<CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
	<CAF6KqwX1jbd3ZszhbDEFC9NXE=LWSLj3azQvfQBDH2GPtQzJyQ@mail.gmail.com>
Message-ID: <CAGCO0KgRvF0=x6fV-GVBGLsbgC1sGaCXnjVeFVGpQ7g50K1fpw@mail.gmail.com>

On Thu, Aug 18, 2011 at 10:50 AM, Delesley Hutchins <delesley at google.com>wrote:

> Good point.  Yes, the RPO iterator (not PO iterator -- my bad) does
> seem to do what we need.  The ordering is slightly different, but it
> obeys the same constraints.  Moreover, the efficiency of RPO is
> somewhat better, since it does not attempt to track depth so
> precisely.  I am withdrawing the patch.
>

Would it make sense to provide a more convenient topological-ordering
interface that is actually implemented in terms of RPO traversal, and maybe
also provides a convenient API for backedge tracking?
-------------- next part --------------
An HTML attachment was scrubbed...
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From nicholas at mxc.ca  Thu Aug 18 14:07:42 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 18 Aug 2011 19:07:42 -0000
Subject: [llvm-commits] [llvm] r137972 -
	/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Message-ID: <20110818190742.350722A6C12C@llvm.org>

Author: nicholas
Date: Thu Aug 18 14:07:42 2011
New Revision: 137972

URL: http://llvm.org/viewvc/llvm-project?rev=137972&view=rev
Log:
The edge from DISubprogram to DICompileUnit has been removed in recent versions
of debug info.

Modified:
    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=137972&r1=137971&r2=137972&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Thu Aug 18 14:07:42 2011
@@ -380,7 +380,7 @@
       for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
         DISubprogram SP(SPs.getElement(i));
         if (!SP.Verify()) continue;
-        raw_fd_ostream *&os = GcnoFiles[SP.getCompileUnit()];
+        raw_fd_ostream *&os = GcnoFiles[CU];
         
         Function *F = SP.getFunction();
         if (!F) continue;



From delesley at google.com  Thu Aug 18 14:56:56 2011
From: delesley at google.com (Delesley Hutchins)
Date: Thu, 18 Aug 2011 12:56:56 -0700
Subject: [llvm-commits] [PATCH] Added topological graph sort routine to
	llvm/ADT
In-Reply-To: <CAGCO0KgRvF0=x6fV-GVBGLsbgC1sGaCXnjVeFVGpQ7g50K1fpw@mail.gmail.com>
References: <CAF6KqwWNLVdBGrOmxkKLUMWRMbs2uW8hz82K+YgHKL5rpZqpbg@mail.gmail.com>
	<40EA6105-32C8-417F-9045-3D9CFA0CB424@2pi.dk>
	<CAGCO0Ki5BVZ8VRnCfmOj0ceMOTY8h31rXrb+40Q_9z1LhpzUHA@mail.gmail.com>
	<0390CECE-8D17-4685-B646-7ADC389B7FA2@2pi.dk>
	<CAF6KqwW9qSNhFViQo19q48OgE5upXXtmp29evBpk7TYE0MJm_Q@mail.gmail.com>
	<CAGCO0KiC9YF5yPbkoF3K_dQkWQ-DmcsaXjD6rzV7o4CnYDsVag@mail.gmail.com>
	<CAF6KqwX1jbd3ZszhbDEFC9NXE=LWSLj3azQvfQBDH2GPtQzJyQ@mail.gmail.com>
	<CAGCO0KgRvF0=x6fV-GVBGLsbgC1sGaCXnjVeFVGpQ7g50K1fpw@mail.gmail.com>
Message-ID: <CAF6KqwVj=-r24kjokzhDK5UE4srcZALfvA86teb7iMCww0WNdg@mail.gmail.com>

I am specializing RPO for CFGBlocks, because CFGBlocks allow me to use
a BitVector as a set, rather than the default SmallPtrSet.  Other than
that, though, I don't see much need for a fancy interface; once you
have the ordering, detecting back edges is trivial.

  -DeLesley

On Thu, Aug 18, 2011 at 11:52 AM, Chandler Carruth <chandlerc at google.com> wrote:
> On Thu, Aug 18, 2011 at 10:50 AM, Delesley Hutchins <delesley at google.com>
> wrote:
>>
>> Good point. ?Yes, the RPO iterator (not PO iterator -- my bad) does
>> seem to do what we need. ?The ordering is slightly different, but it
>> obeys the same constraints. ?Moreover, the efficiency of RPO is
>> somewhat better, since it does not attempt to track depth so
>> precisely. ?I am withdrawing the patch.
>
> Would it make sense to provide a more convenient topological-ordering
> interface that is actually implemented in terms of RPO traversal, and maybe
> also provides a convenient API for backedge tracking?



-- 
DeLesley Hutchins | Software Engineer | delesley at google.com | 505-206-0315


From resistor at mac.com  Thu Aug 18 15:05:07 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 20:05:07 -0000
Subject: [llvm-commits] [llvm] r137974 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
Message-ID: <20110818200507.1BFA22A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 15:05:06 2011
New Revision: 137974

URL: http://llvm.org/viewvc/llvm-project?rev=137974&view=rev
Log:
More Thumb1 decoding tests.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=137974&r1=137973&r2=137974&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Thu Aug 18 15:05:06 2011
@@ -76,3 +76,28 @@
 
 0x10 0x47
 
+#------------------------------------------------------------------------------
+# CMN
+#------------------------------------------------------------------------------
+# CHECK: cmn r5, r1
+
+0xcd 0x42
+
+#------------------------------------------------------------------------------
+# CMP
+#------------------------------------------------------------------------------
+# CHECK: cmp r6, #32
+# CHECK: cmp r3, r4
+# CHECK: cmp r8, r1
+
+0x20 0x2e
+0xa3 0x42
+0x88 0x45
+
+#------------------------------------------------------------------------------
+# EOR
+#------------------------------------------------------------------------------
+# CHECK: eors r4, r5
+
+0x6c 0x40
+



From ahatanak at gmail.com  Thu Aug 18 15:07:42 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Thu, 18 Aug 2011 20:07:42 -0000
Subject: [llvm-commits] [llvm] r137975 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20110818200742.EBEB12A6C12C@llvm.org>

Author: ahatanak
Date: Thu Aug 18 15:07:42 2011
New Revision: 137975

URL: http://llvm.org/viewvc/llvm-project?rev=137975&view=rev
Log:
Make IsShiftedMask a static function rather than defining it in an
anonymous namespace.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137975&r1=137974&r2=137975&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 18 15:07:42 2011
@@ -35,22 +35,20 @@
 #include "llvm/Support/ErrorHandling.h"
 using namespace llvm;
 
-namespace {
-  // If I is a shifted mask, set the size (Size) and the first bit of the 
-  // mask (Pos), and return true.
-  bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
-                     uint64_t &Size) {
-    assert(SizeInBits == 32 || SizeInBits == 64);
-    bool Is32Bits = (SizeInBits == 32);
-
-    if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
-        (!Is32Bits && !isShiftedMask_64(I)))
-      return false;
+// If I is a shifted mask, set the size (Size) and the first bit of the 
+// mask (Pos), and return true.
+static bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
+                          uint64_t &Size) {
+  assert(SizeInBits == 32 || SizeInBits == 64);
+  bool Is32Bits = (SizeInBits == 32);
 
-    Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
-    Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
-    return true;
-  }
+  if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
+      (!Is32Bits && !isShiftedMask_64(I)))
+    return false;
+
+  Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
+  Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
+  return true;
 }
 
 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {



From krasin at chromium.org  Thu Aug 18 15:10:00 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 13:10:00 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <40963BAC-E345-48ED-9C1E-2BDCC004AEF5@apple.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<4E4C86DB.6020308@mxc.ca>
	<7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>
	<CAOei5Rdc4Pm_Mmg8wJgS_0YrZosrnhnHY7kqGeJWxChjxpd9kw@mail.gmail.com>
	<40963BAC-E345-48ED-9C1E-2BDCC004AEF5@apple.com>
Message-ID: <CAOei5RevjuujPpjCFmwApUq0e=0QX=ibmtSqPJ5is7bBCxhVcw@mail.gmail.com>

On Wed, Aug 17, 2011 at 11:39 PM, Chris Lattner <clattner at apple.com> wrote:
> I'm not capable of reviewing the actual patch, but I don't object to it. ?Someone who knows autoconf should approve it (Eric?)
Eric,

could you please take a look?

Thanks in advance,
Ivan Krasin

>
> -Chris
>
> On Aug 17, 2011, at 11:38 PM, Ivan Krasin wrote:
>
>> Chris,
>>
>> is it fine to commit? (I assume that "Great, thanks" was an approval,
>> but I'd like to double check)
>>
>> Ivan
>>
>> On Wed, Aug 17, 2011 at 11:06 PM, Chris Lattner <clattner at apple.com> wrote:
>>>
>>> On Aug 17, 2011, at 8:28 PM, Nick Lewycky wrote:
>>>
>>>> Chris Lattner wrote:
>>>>>
>>>>> On Aug 17, 2011, at 3:28 PM, Ivan Krasin wrote:
>>>>>
>>>>>> Err: missed the patch.
>>>>>> Please, find it attached to this message.
>>>>>>
>>>>>> Also, you can take a look at the patch online:
>>>>>> http://codereview.chromium.org/7676009/
>>>>>
>>>>> Hi Ivan,
>>>>>
>>>>> Hopefully dumb question: what are the licensing implications of this? ?Is the new autoconf goop GPL3?
>>>>
>>>> No, they're still GPLv2. The diffs make it clear that the license block at the top of the files haven't changed.
>>>
>>> Great, thanks.
>>>
>>> -Chris
>>>
>>>
>
>


From krasin at google.com  Thu Aug 18 15:12:30 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 18 Aug 2011 13:12:30 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
Message-ID: <CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>

Friendly ping :)

On Tue, Aug 16, 2011 at 12:14 PM, Ivan Krasin <krasin at google.com> wrote:
> Eric,
>
> could you please take another look?
>
> Ivan
>
> On Mon, Aug 15, 2011 at 2:29 PM, Ivan Krasin <krasin at google.com> wrote:
>> On Thu, Aug 11, 2011 at 3:20 PM, Eric Christopher <echristo at apple.com> wrote:
>>>
>>> On Aug 10, 2011, at 4:01 PM, Ivan Krasin wrote:
>>>
>>> <flush-local-value-map.patch>
>>>
>>> In general I think the patch is OK. ?A few requests:
>>> ? ?MachineInstr *LastLocalValue;
>>> + ?MachineInstr *OrigLocalValue;
>>> ?.
>>> ? ?// Start out as null, meaining no local-value instructions have
>>> ? ?// been emitted.
>>> - ?LastLocalValue = 0;
>>> + ?OrigLocalValue = 0;
>>> A lot of the code you've changed hasn't had any comments written or updated
>>> for the new behavior. It'd be good to get an updated description of how the
>>> LocalValueMap is working and how it interacts with constants.
>> I have renamed OrigLocalValue to EmitStartPt which is (I believe) less
>> confusing naming, since it points to the place in the block where it's
>> allowed to start emitting instructions.
>>
>>> In particular:
>>> + ?if (!isa<IntrinsicInst>(F))
>>> + ? ?flushLocalValueMap();
>>> +
>>> Here. The location of this here doesn't make a whole lot of sense and it'd
>>> be good if you could explain it.
>> I've added the explanation. Thanks for the suggestion.
>>
>>> A better way to do this would be, as Jakob suggested, use the LocalValueMap
>>> as a storage for constants and locations that you've used them in the block
>>> and then emit all of the constants at that point rather than this weird
>>> flushing mechanism.
>> I've tried to do that. It slows down -O0 build which is unacceptable.
>> The problem is that we have to emit all local values to the start of
>> the block, store last use for each of them and spread them through the
>> block once the processing of the block is done. It makes it slower...
>> So, I would prefer to stay with the patch that makes all the metrics
>> slightly better on average (code size/stack size/compile time). Is it
>> fine with you?
>>
>> Please, find the updated patch attached.
>>
>> Ivan Krasin
>>
>>> -eric
>>
>


From echristo at apple.com  Thu Aug 18 15:14:44 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 13:14:44 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
Message-ID: <FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>

:) Almost there.

Can you describe the full algorithm in the few lines before the declaration of LastLocalValue and EmitStartPt?

The rationale for the built-in is fine.

-eric

On Aug 18, 2011, at 1:12 PM, Ivan Krasin wrote:

> Friendly ping :)
> 
> On Tue, Aug 16, 2011 at 12:14 PM, Ivan Krasin <krasin at google.com> wrote:
>> Eric,
>> 
>> could you please take another look?
>> 
>> Ivan
>> 
>> On Mon, Aug 15, 2011 at 2:29 PM, Ivan Krasin <krasin at google.com> wrote:
>>> On Thu, Aug 11, 2011 at 3:20 PM, Eric Christopher <echristo at apple.com> wrote:
>>>> 
>>>> On Aug 10, 2011, at 4:01 PM, Ivan Krasin wrote:
>>>> 
>>>> <flush-local-value-map.patch>
>>>> 
>>>> In general I think the patch is OK.  A few requests:
>>>>    MachineInstr *LastLocalValue;
>>>> +  MachineInstr *OrigLocalValue;
>>>> ?.
>>>>    // Start out as null, meaining no local-value instructions have
>>>>    // been emitted.
>>>> -  LastLocalValue = 0;
>>>> +  OrigLocalValue = 0;
>>>> A lot of the code you've changed hasn't had any comments written or updated
>>>> for the new behavior. It'd be good to get an updated description of how the
>>>> LocalValueMap is working and how it interacts with constants.
>>> I have renamed OrigLocalValue to EmitStartPt which is (I believe) less
>>> confusing naming, since it points to the place in the block where it's
>>> allowed to start emitting instructions.
>>> 
>>>> In particular:
>>>> +  if (!isa<IntrinsicInst>(F))
>>>> +    flushLocalValueMap();
>>>> +
>>>> Here. The location of this here doesn't make a whole lot of sense and it'd
>>>> be good if you could explain it.
>>> I've added the explanation. Thanks for the suggestion.
>>> 
>>>> A better way to do this would be, as Jakob suggested, use the LocalValueMap
>>>> as a storage for constants and locations that you've used them in the block
>>>> and then emit all of the constants at that point rather than this weird
>>>> flushing mechanism.
>>> I've tried to do that. It slows down -O0 build which is unacceptable.
>>> The problem is that we have to emit all local values to the start of
>>> the block, store last use for each of them and spread them through the
>>> block once the processing of the block is done. It makes it slower...
>>> So, I would prefer to stay with the patch that makes all the metrics
>>> slightly better on average (code size/stack size/compile time). Is it
>>> fine with you?
>>> 
>>> Please, find the updated patch attached.
>>> 
>>> Ivan Krasin
>>> 
>>>> -eric
>>> 
>> 



From echristo at apple.com  Thu Aug 18 15:28:42 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 13:28:42 -0700
Subject: [llvm-commits] Update to latest versions of config.guess and
 config.sub from GNU mainline
In-Reply-To: <CAOei5RevjuujPpjCFmwApUq0e=0QX=ibmtSqPJ5is7bBCxhVcw@mail.gmail.com>
References: <CAOei5Rc8hjvFt=tH4uo=GsvVidV35rPfNCkiYV5djx5oz6WgvQ@mail.gmail.com>
	<CAOei5Re8AW8a0zV=PmiKb27XBsLNKMoTNrR2mcMHpJA=XHAw4Q@mail.gmail.com>
	<26E6FC58-E9B8-4933-95AA-8B5EB6DDBDDC@apple.com>
	<4E4C86DB.6020308@mxc.ca>
	<7EDE96A0-F7EC-405A-9FEE-0A67A67BFCB3@apple.com>
	<CAOei5Rdc4Pm_Mmg8wJgS_0YrZosrnhnHY7kqGeJWxChjxpd9kw@mail.gmail.com>
	<40963BAC-E345-48ED-9C1E-2BDCC004AEF5@apple.com>
	<CAOei5RevjuujPpjCFmwApUq0e=0QX=ibmtSqPJ5is7bBCxhVcw@mail.gmail.com>
Message-ID: <7D2775CF-D77D-4D5A-AEA9-19DA7B9EBDAE@apple.com>


On Aug 18, 2011, at 1:10 PM, Ivan Krasin wrote:

> On Wed, Aug 17, 2011 at 11:39 PM, Chris Lattner <clattner at apple.com> wrote:
>> I'm not capable of reviewing the actual patch, but I don't object to it.  Someone who knows autoconf should approve it (Eric?)
> Eric,
> 
> could you please take a look?


Yes, this is fine.

-eric

From isanbard at gmail.com  Thu Aug 18 15:39:32 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 20:39:32 -0000
Subject: [llvm-commits] [llvm] r137978 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110818203932.309152A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 15:39:32 2011
New Revision: 137978

URL: http://llvm.org/viewvc/llvm-project?rev=137978&view=rev
Log:
Use this fantzy ArrayRef thing to pass in the list of predecessors.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137978&r1=137977&r2=137978&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 15:39:32 2011
@@ -317,9 +317,8 @@
 /// UpdateAnalysisInformation - Update DominatorTree, LoopInfo, and LCCSA
 /// analysis information.
 static void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB,
-                                      BasicBlock *const *Preds,
-                                      unsigned NumPreds, Pass *P,
-                                      bool &HasLoopExit) {
+                                      ArrayRef<BasicBlock *> Preds,
+                                      Pass *P, bool &HasLoopExit) {
   if (!P) return;
 
   LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>();
@@ -331,18 +330,20 @@
   bool IsLoopEntry = !!L;
   bool SplitMakesNewLoopHeader = false;
   if (LI) {
-    for (unsigned i = 0; i != NumPreds; ++i) {
+    for (ArrayRef<BasicBlock*>::iterator
+           i = Preds.begin(), e = Preds.end(); i != e; ++i) {
+      BasicBlock *Pred = *i;
       // If we need to preserve LCSSA, determine if any of the preds is a loop
       // exit.
       if (PreserveLCSSA)
-        if (Loop *PL = LI->getLoopFor(Preds[i]))
+        if (Loop *PL = LI->getLoopFor(Pred))
           if (!PL->contains(OldBB))
             HasLoopExit = true;
 
       // If we need to preserve LoopInfo, note whether any of the preds crosses
       // an interesting loop boundary.
       if (!L) continue;
-      if (L->contains(Preds[i]))
+      if (L->contains(Pred))
         IsLoopEntry = false;
       else
         SplitMakesNewLoopHeader = true;
@@ -362,8 +363,10 @@
     // loops enclose them, and select the most-nested loop which contains the
     // loop containing the block being split.
     Loop *InnermostPredLoop = 0;
-    for (unsigned i = 0; i != NumPreds; ++i)
-      if (Loop *PredLoop = LI->getLoopFor(Preds[i])) {
+    for (ArrayRef<BasicBlock*>::iterator
+           i = Preds.begin(), e = Preds.end(); i != e; ++i) {
+      BasicBlock *Pred = *i;
+      if (Loop *PredLoop = LI->getLoopFor(Pred)) {
         // Seek a loop which actually contains the block being split (to avoid
         // adjacent loops).
         while (PredLoop && !PredLoop->contains(OldBB))
@@ -375,6 +378,7 @@
              InnermostPredLoop->getLoopDepth() < PredLoop->getLoopDepth()))
           InnermostPredLoop = PredLoop;
       }
+    }
 
     if (InnermostPredLoop)
       InnermostPredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
@@ -430,7 +434,8 @@
 
   // Update DominatorTree, LoopInfo, and LCCSA analysis information.
   bool HasLoopExit = false;
-  UpdateAnalysisInformation(BB, NewBB, Preds, NumPreds, P, HasLoopExit);
+  UpdateAnalysisInformation(BB, NewBB, ArrayRef<BasicBlock*>(Preds, NumPreds),
+                            P, HasLoopExit);
 
   // Otherwise, create a new PHI node in NewBB for each PHI node in BB.
   AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;



From isanbard at gmail.com  Thu Aug 18 15:51:04 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 20:51:04 -0000
Subject: [llvm-commits] [llvm] r137979 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110818205104.A8A462A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 15:51:04 2011
New Revision: 137979

URL: http://llvm.org/viewvc/llvm-project?rev=137979&view=rev
Log:
Split out the updating of PHI nodes after splitting the BB into a separate
function.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=137979&r1=137978&r2=137979&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 15:51:04 2011
@@ -389,6 +389,56 @@
   }
 }
 
+/// UpdatePHINodes - Update the PHI nodes in OrigBB to include the values coming
+/// from NewBB. This also updates AliasAnalysis, if available.
+static void UpdatePHINodes(BasicBlock *OrigBB, BasicBlock *NewBB,
+                           ArrayRef<BasicBlock*> Preds, BranchInst *BI,
+                           Pass *P, bool HasLoopExit) {
+  // Otherwise, create a new PHI node in NewBB for each PHI node in OrigBB.
+  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
+  for (BasicBlock::iterator I = OrigBB->begin(); isa<PHINode>(I); ) {
+    PHINode *PN = cast<PHINode>(I++);
+
+    // Check to see if all of the values coming in are the same.  If so, we
+    // don't need to create a new PHI node, unless it's needed for LCSSA.
+    Value *InVal = 0;
+    if (!HasLoopExit) {
+      InVal = PN->getIncomingValueForBlock(Preds[0]);
+      for (unsigned i = 1, e = Preds.size(); i != e; ++i)
+        if (InVal != PN->getIncomingValueForBlock(Preds[i])) {
+          InVal = 0;
+          break;
+        }
+    }
+
+    if (InVal) {
+      // If all incoming values for the new PHI would be the same, just don't
+      // make a new PHI.  Instead, just remove the incoming values from the old
+      // PHI.
+      for (unsigned i = 0, e = Preds.size(); i != e; ++i)
+        PN->removeIncomingValue(Preds[i], false);
+    } else {
+      // If the values coming into the block are not the same, we need a PHI.
+      // Create the new PHI node, insert it into NewBB at the end of the block
+      PHINode *NewPHI =
+        PHINode::Create(PN->getType(), Preds.size(), PN->getName() + ".ph", BI);
+      if (AA) AA->copyValue(PN, NewPHI);
+      
+      // Move all of the PHI values for 'Preds' to the new PHI.
+      for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
+        Value *V = PN->removeIncomingValue(Preds[i], false);
+        NewPHI->addIncoming(V, Preds[i]);
+      }
+
+      InVal = NewPHI;
+    }
+
+    // Add an incoming value to the PHI node in the loop for the preheader
+    // edge.
+    PN->addIncoming(InVal, NewBB);
+  }
+}
+
 /// SplitBlockPredecessors - This method transforms BB by introducing a new
 /// basic block into the function, and moving some of the predecessors of BB to
 /// be predecessors of the new block.  The new predecessors are indicated by the
@@ -437,49 +487,9 @@
   UpdateAnalysisInformation(BB, NewBB, ArrayRef<BasicBlock*>(Preds, NumPreds),
                             P, HasLoopExit);
 
-  // Otherwise, create a new PHI node in NewBB for each PHI node in BB.
-  AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
-  for (BasicBlock::iterator I = BB->begin(); isa<PHINode>(I); ) {
-    PHINode *PN = cast<PHINode>(I++);
-    
-    // Check to see if all of the values coming in are the same.  If so, we
-    // don't need to create a new PHI node, unless it's needed for LCSSA.
-    Value *InVal = 0;
-    if (!HasLoopExit) {
-      InVal = PN->getIncomingValueForBlock(Preds[0]);
-      for (unsigned i = 1; i != NumPreds; ++i)
-        if (InVal != PN->getIncomingValueForBlock(Preds[i])) {
-          InVal = 0;
-          break;
-        }
-    }
-
-    if (InVal) {
-      // If all incoming values for the new PHI would be the same, just don't
-      // make a new PHI.  Instead, just remove the incoming values from the old
-      // PHI.
-      for (unsigned i = 0; i != NumPreds; ++i)
-        PN->removeIncomingValue(Preds[i], false);
-    } else {
-      // If the values coming into the block are not the same, we need a PHI.
-      // Create the new PHI node, insert it into NewBB at the end of the block
-      PHINode *NewPHI =
-        PHINode::Create(PN->getType(), NumPreds, PN->getName()+".ph", BI);
-      if (AA) AA->copyValue(PN, NewPHI);
-      
-      // Move all of the PHI values for 'Preds' to the new PHI.
-      for (unsigned i = 0; i != NumPreds; ++i) {
-        Value *V = PN->removeIncomingValue(Preds[i], false);
-        NewPHI->addIncoming(V, Preds[i]);
-      }
-      InVal = NewPHI;
-    }
-    
-    // Add an incoming value to the PHI node in the loop for the preheader
-    // edge.
-    PN->addIncoming(InVal, NewBB);
-  }
-
+  // Update the PHI nodes in BB with the values coming from NewBB.
+  UpdatePHINodes(BB, NewBB, ArrayRef<BasicBlock*>(Preds, NumPreds), BI,
+                 P, HasLoopExit);
   return NewBB;
 }
 



From anton at korobeynikov.info  Thu Aug 18 16:03:20 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Fri, 19 Aug 2011 01:03:20 +0400
Subject: [llvm-commits] [PATCH] EH table comments
In-Reply-To: <CAPH-gfdGNW2L6BxLCMW+VrJ__aF7RDDajf9G-G4tC39kb43yYw@mail.gmail.com>
References: <CAPH-gfdGNW2L6BxLCMW+VrJ__aF7RDDajf9G-G4tC39kb43yYw@mail.gmail.com>
Message-ID: <CA+Ov9+kkJB89=Uj=7L3TzrMEBaMKmHj4+UTd9CdTwZ6YXOLtLg@mail.gmail.com>

Hi Renato,

> Here's a clean up I did to add the comments of each declaration follow
> it, making it easier to read and compare to GCC's result.
Looks good to me.


-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From isanbard at gmail.com  Thu Aug 18 16:10:01 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 21:10:01 -0000
Subject: [llvm-commits] [llvm] r137981 -
	/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
Message-ID: <20110818211001.7E2002A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 16:10:01 2011
New Revision: 137981

URL: http://llvm.org/viewvc/llvm-project?rev=137981&view=rev
Log:
Revert r137871. The loop simplify pass should require all exits from a loop that
aren't from an indirect branch need to be dominated by the loop header.

Modified:
    llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=137981&r1=137980&r2=137981&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Thu Aug 18 16:10:01 2011
@@ -398,9 +398,6 @@
 /// blocks.  This method is used to split exit blocks that have predecessors
 /// outside of the loop.
 BasicBlock *LoopSimplify::RewriteLoopExitBlock(Loop *L, BasicBlock *Exit) {
-  // Don't split a landing pad block.
-  if (Exit->isLandingPad()) return 0;
-
   SmallVector<BasicBlock*, 8> LoopBlocks;
   for (pred_iterator I = pred_begin(Exit), E = pred_end(Exit); I != E; ++I) {
     BasicBlock *P = *I;
@@ -749,10 +746,9 @@
     (void)HasIndBrPred;
   }
 
-  // Indirectbr and LandingPad can interfere with exit block canonicalization.
+  // Indirectbr can interfere with exit block canonicalization.
   if (!L->hasDedicatedExits()) {
     bool HasIndBrExiting = false;
-    bool HasLPadExiting = false;
     SmallVector<BasicBlock*, 8> ExitingBlocks;
     L->getExitingBlocks(ExitingBlocks);
     for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) {
@@ -760,18 +756,10 @@
         HasIndBrExiting = true;
         break;
       }
-      if (const InvokeInst *II =
-          dyn_cast<InvokeInst>(ExitingBlocks[i]->getTerminator())) {
-        if (L->contains(II->getNormalDest()) &&
-            !L->contains(II->getUnwindDest())) {
-          HasLPadExiting = true;
-          break;
-        }
-      }
     }
 
-    assert((HasIndBrExiting || HasLPadExiting) &&
+    assert(HasIndBrExiting &&
            "LoopSimplify has no excuse for missing exit block info!");
-    (void)HasIndBrExiting; (void)HasLPadExiting;
+    (void)HasIndBrExiting;
   }
 }



From krasin at chromium.org  Thu Aug 18 16:23:18 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 21:23:18 -0000
Subject: [llvm-commits] [llvm] r137984 - in /llvm/trunk/autoconf:
	config.guess config.sub
Message-ID: <20110818212318.E23FD2A6C12C@llvm.org>

Author: krasin
Date: Thu Aug 18 16:23:18 2011
New Revision: 137984

URL: http://llvm.org/viewvc/llvm-project?rev=137984&view=rev
Log:
Update autoconfig/config.{sub,guess} to the latest version
from the GNU upstream: git://git.savannah.gnu.org/config.git

1. It eliminates a local LLVM patch for auroraux (because, the
mainline config.sub has already got support of auroraux)
2. It adds several new recognized target cpus and operating systems
(in particular, PNaCl)


Modified:
    llvm/trunk/autoconf/config.guess
    llvm/trunk/autoconf/config.sub

Modified: llvm/trunk/autoconf/config.guess
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.guess?rev=137984&r1=137983&r2=137984&view=diff
==============================================================================
--- llvm/trunk/autoconf/config.guess (original)
+++ llvm/trunk/autoconf/config.guess Thu Aug 18 16:23:18 2011
@@ -1,10 +1,10 @@
 #! /bin/sh
 # Attempt to guess a canonical system name.
 #   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
-#   Free Software Foundation, Inc.
+#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
+#   2011 Free Software Foundation, Inc.
 
-timestamp='2009-09-18'
+timestamp='2011-08-17'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
@@ -56,8 +56,9 @@
 GNU config.guess ($timestamp)
 
 Originally written by Per Bothner.
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free
+Software Foundation, Inc.
 
 This is free software; see the source for copying conditions.  There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -180,7 +181,7 @@
 		fi
 		;;
 	    *)
-	        os=netbsd
+		os=netbsd
 		;;
 	esac
 	# The OS release
@@ -223,7 +224,7 @@
 		UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
 		;;
 	*5.*)
-	        UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
+		UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
 		;;
 	esac
 	# According to Compaq, /usr/sbin/psrinfo has been available on
@@ -269,7 +270,10 @@
 	# A Xn.n version is an unreleased experimental baselevel.
 	# 1.2 uses "1.2" for uname -r.
 	echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
-	exit ;;
+	# Reset EXIT trap before exiting to avoid spurious non-zero exit code.
+	exitcode=$?
+	trap '' 0
+	exit $exitcode ;;
     Alpha\ *:Windows_NT*:*)
 	# How do we know it's Interix rather than the generic POSIX subsystem?
 	# Should we change UNAME_MACHINE based on the output of uname instead
@@ -295,7 +299,7 @@
 	echo s390-ibm-zvmoe
 	exit ;;
     *:OS400:*:*)
-        echo powerpc-ibm-os400
+	echo powerpc-ibm-os400
 	exit ;;
     arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
 	echo arm-acorn-riscix${UNAME_RELEASE}
@@ -334,8 +338,7 @@
 	echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
 	exit ;;
     i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*)
-	AUX_ARCH="i386"
-	echo ${AUX_ARCH}-pc-auroraux`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	echo i386-pc-auroraux${UNAME_RELEASE}
 	exit ;;
     i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*)
 	eval $set_cc_for_build
@@ -395,23 +398,23 @@
     # MiNT.  But MiNT is downward compatible to TOS, so this should
     # be no problem.
     atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)
-        echo m68k-atari-mint${UNAME_RELEASE}
+	echo m68k-atari-mint${UNAME_RELEASE}
 	exit ;;
     atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)
 	echo m68k-atari-mint${UNAME_RELEASE}
-        exit ;;
+	exit ;;
     *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)
-        echo m68k-atari-mint${UNAME_RELEASE}
+	echo m68k-atari-mint${UNAME_RELEASE}
 	exit ;;
     milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)
-        echo m68k-milan-mint${UNAME_RELEASE}
-        exit ;;
+	echo m68k-milan-mint${UNAME_RELEASE}
+	exit ;;
     hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)
-        echo m68k-hades-mint${UNAME_RELEASE}
-        exit ;;
+	echo m68k-hades-mint${UNAME_RELEASE}
+	exit ;;
     *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)
-        echo m68k-unknown-mint${UNAME_RELEASE}
-        exit ;;
+	echo m68k-unknown-mint${UNAME_RELEASE}
+	exit ;;
     m68k:machten:*:*)
 	echo m68k-apple-machten${UNAME_RELEASE}
 	exit ;;
@@ -481,8 +484,8 @@
 	echo m88k-motorola-sysv3
 	exit ;;
     AViiON:dgux:*:*)
-        # DG/UX returns AViiON for all architectures
-        UNAME_PROCESSOR=`/usr/bin/uname -p`
+	# DG/UX returns AViiON for all architectures
+	UNAME_PROCESSOR=`/usr/bin/uname -p`
 	if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ]
 	then
 	    if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \
@@ -495,7 +498,7 @@
 	else
 	    echo i586-dg-dgux${UNAME_RELEASE}
 	fi
- 	exit ;;
+	exit ;;
     M88*:DolphinOS:*:*)	# DolphinOS (SVR3)
 	echo m88k-dolphin-sysv3
 	exit ;;
@@ -552,7 +555,7 @@
 		echo rs6000-ibm-aix3.2
 	fi
 	exit ;;
-    *:AIX:*:[456])
+    *:AIX:*:[4567])
 	IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'`
 	if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then
 		IBM_ARCH=rs6000
@@ -595,52 +598,52 @@
 	    9000/[678][0-9][0-9])
 		if [ -x /usr/bin/getconf ]; then
 		    sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null`
-                    sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null`
-                    case "${sc_cpu_version}" in
-                      523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0
-                      528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1
-                      532)                      # CPU_PA_RISC2_0
-                        case "${sc_kernel_bits}" in
-                          32) HP_ARCH="hppa2.0n" ;;
-                          64) HP_ARCH="hppa2.0w" ;;
+		    sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null`
+		    case "${sc_cpu_version}" in
+		      523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0
+		      528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1
+		      532)                      # CPU_PA_RISC2_0
+			case "${sc_kernel_bits}" in
+			  32) HP_ARCH="hppa2.0n" ;;
+			  64) HP_ARCH="hppa2.0w" ;;
 			  '') HP_ARCH="hppa2.0" ;;   # HP-UX 10.20
-                        esac ;;
-                    esac
+			esac ;;
+		    esac
 		fi
 		if [ "${HP_ARCH}" = "" ]; then
 		    eval $set_cc_for_build
-		    sed 's/^              //' << EOF >$dummy.c
+		    sed 's/^		//' << EOF >$dummy.c
 
-              #define _HPUX_SOURCE
-              #include <stdlib.h>
-              #include <unistd.h>
-
-              int main ()
-              {
-              #if defined(_SC_KERNEL_BITS)
-                  long bits = sysconf(_SC_KERNEL_BITS);
-              #endif
-                  long cpu  = sysconf (_SC_CPU_VERSION);
-
-                  switch (cpu)
-              	{
-              	case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
-              	case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
-              	case CPU_PA_RISC2_0:
-              #if defined(_SC_KERNEL_BITS)
-              	    switch (bits)
-              		{
-              		case 64: puts ("hppa2.0w"); break;
-              		case 32: puts ("hppa2.0n"); break;
-              		default: puts ("hppa2.0"); break;
-              		} break;
-              #else  /* !defined(_SC_KERNEL_BITS) */
-              	    puts ("hppa2.0"); break;
-              #endif
-              	default: puts ("hppa1.0"); break;
-              	}
-                  exit (0);
-              }
+		#define _HPUX_SOURCE
+		#include <stdlib.h>
+		#include <unistd.h>
+
+		int main ()
+		{
+		#if defined(_SC_KERNEL_BITS)
+		    long bits = sysconf(_SC_KERNEL_BITS);
+		#endif
+		    long cpu  = sysconf (_SC_CPU_VERSION);
+
+		    switch (cpu)
+			{
+			case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
+			case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
+			case CPU_PA_RISC2_0:
+		#if defined(_SC_KERNEL_BITS)
+			    switch (bits)
+				{
+				case 64: puts ("hppa2.0w"); break;
+				case 32: puts ("hppa2.0n"); break;
+				default: puts ("hppa2.0"); break;
+				} break;
+		#else  /* !defined(_SC_KERNEL_BITS) */
+			    puts ("hppa2.0"); break;
+		#endif
+			default: puts ("hppa1.0"); break;
+			}
+		    exit (0);
+		}
 EOF
 		    (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy`
 		    test -z "$HP_ARCH" && HP_ARCH=hppa
@@ -731,22 +734,22 @@
 	exit ;;
     C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
 	echo c1-convex-bsd
-        exit ;;
+	exit ;;
     C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)
 	if getsysinfo -f scalar_acc
 	then echo c32-convex-bsd
 	else echo c2-convex-bsd
 	fi
-        exit ;;
+	exit ;;
     C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)
 	echo c34-convex-bsd
-        exit ;;
+	exit ;;
     C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)
 	echo c38-convex-bsd
-        exit ;;
+	exit ;;
     C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)
 	echo c4-convex-bsd
-        exit ;;
+	exit ;;
     CRAY*Y-MP:*:*:*)
 	echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
 	exit ;;
@@ -770,14 +773,14 @@
 	exit ;;
     F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*)
 	FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
-        FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
-        FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
-        echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
-        exit ;;
+	FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
+	FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
+	echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+	exit ;;
     5000:UNIX_System_V:4.*:*)
-        FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
-        FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'`
-        echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+	FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
+	FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'`
+	echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
 	exit ;;
     i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*)
 	echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
@@ -789,7 +792,7 @@
 	echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
 	exit ;;
     *:FreeBSD:*:*)
-        UNAME_PROCESSOR=`/usr/bin/uname -p`
+	UNAME_PROCESSOR=`/usr/bin/uname -p`
 	case ${UNAME_MACHINE} in
 	    amd64)
 		echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
@@ -804,18 +807,18 @@
 	echo ${UNAME_MACHINE}-pc-mingw32
 	exit ;;
     i*:windows32*:*)
-    	# uname -m includes "-pc" on this system.
-    	echo ${UNAME_MACHINE}-mingw32
+	# uname -m includes "-pc" on this system.
+	echo ${UNAME_MACHINE}-mingw32
 	exit ;;
     i*:PW*:*)
 	echo ${UNAME_MACHINE}-pc-pw32
 	exit ;;
-    *:Interix*:[3456]*)
-    	case ${UNAME_MACHINE} in
+    *:Interix*:*)
+	case ${UNAME_MACHINE} in
 	    x86)
 		echo i586-pc-interix${UNAME_RELEASE}
 		exit ;;
-	    EM64T | authenticamd | genuineintel)
+	    authenticamd | genuineintel | EM64T)
 		echo x86_64-unknown-interix${UNAME_RELEASE}
 		exit ;;
 	    IA64)
@@ -866,7 +869,7 @@
 	  EV6)   UNAME_MACHINE=alphaev6 ;;
 	  EV67)  UNAME_MACHINE=alphaev67 ;;
 	  EV68*) UNAME_MACHINE=alphaev68 ;;
-        esac
+	esac
 	objdump --private-headers /bin/sh | grep -q ld.so.1
 	if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
 	echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
@@ -878,7 +881,13 @@
 	then
 	    echo ${UNAME_MACHINE}-unknown-linux-gnu
 	else
-	    echo ${UNAME_MACHINE}-unknown-linux-gnueabi
+	    if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \
+		| grep -q __ARM_PCS_VFP
+	    then
+		echo ${UNAME_MACHINE}-unknown-linux-gnueabi
+	    else
+		echo ${UNAME_MACHINE}-unknown-linux-gnueabihf
+	    fi
 	fi
 	exit ;;
     avr32*:Linux:*:*)
@@ -891,10 +900,18 @@
 	echo crisv32-axis-linux-gnu
 	exit ;;
     frv:Linux:*:*)
-    	echo frv-unknown-linux-gnu
+	echo frv-unknown-linux-gnu
 	exit ;;
     i*86:Linux:*:*)
-	echo ${UNAME_MACHINE}-pc-linux-gnu
+	LIBC=gnu
+	eval $set_cc_for_build
+	sed 's/^	//' << EOF >$dummy.c
+	#ifdef __dietlibc__
+	LIBC=dietlibc
+	#endif
+EOF
+	eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'`
+	echo "${UNAME_MACHINE}-pc-linux-${LIBC}"
 	exit ;;
     ia64:Linux:*:*)
 	echo ${UNAME_MACHINE}-unknown-linux-gnu
@@ -921,11 +938,7 @@
 	#endif
 	#endif
 EOF
-	eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
-	    /^CPU/{
-		s: ::g
-		p
-	    }'`"
+	eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`
 	test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }
 	;;
     or32:Linux:*:*)
@@ -955,7 +968,7 @@
 	echo ${UNAME_MACHINE}-ibm-linux
 	exit ;;
     sh64*:Linux:*:*)
-    	echo ${UNAME_MACHINE}-unknown-linux-gnu
+	echo ${UNAME_MACHINE}-unknown-linux-gnu
 	exit ;;
     sh*:Linux:*:*)
 	echo ${UNAME_MACHINE}-unknown-linux-gnu
@@ -963,6 +976,9 @@
     sparc:Linux:*:* | sparc64:Linux:*:*)
 	echo ${UNAME_MACHINE}-unknown-linux-gnu
 	exit ;;
+    tile*:Linux:*:*)
+	echo ${UNAME_MACHINE}-unknown-linux-gnu
+	exit ;;
     vax:Linux:*:*)
 	echo ${UNAME_MACHINE}-dec-linux-gnu
 	exit ;;
@@ -970,7 +986,7 @@
 	echo x86_64-unknown-linux-gnu
 	exit ;;
     xtensa*:Linux:*:*)
-    	echo ${UNAME_MACHINE}-unknown-linux-gnu
+	echo ${UNAME_MACHINE}-unknown-linux-gnu
 	exit ;;
     i*86:DYNIX/ptx:4*:*)
 	# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
@@ -979,11 +995,11 @@
 	echo i386-sequent-sysv4
 	exit ;;
     i*86:UNIX_SV:4.2MP:2.*)
-        # Unixware is an offshoot of SVR4, but it has its own version
-        # number series starting with 2...
-        # I am not positive that other SVR4 systems won't match this,
+	# Unixware is an offshoot of SVR4, but it has its own version
+	# number series starting with 2...
+	# I am not positive that other SVR4 systems won't match this,
 	# I just have to hope.  -- rms.
-        # Use sysv4.2uw... so that sysv4* matches it.
+	# Use sysv4.2uw... so that sysv4* matches it.
 	echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION}
 	exit ;;
     i*86:OS/2:*:*)
@@ -1015,7 +1031,7 @@
 	fi
 	exit ;;
     i*86:*:5:[678]*)
-    	# UnixWare 7.x, OpenUNIX and OpenServer 6.
+	# UnixWare 7.x, OpenUNIX and OpenServer 6.
 	case `/bin/uname -X | grep "^Machine"` in
 	    *486*)	     UNAME_MACHINE=i486 ;;
 	    *Pentium)	     UNAME_MACHINE=i586 ;;
@@ -1043,13 +1059,13 @@
 	exit ;;
     pc:*:*:*)
 	# Left here for compatibility:
-        # uname -m prints for DJGPP always 'pc', but it prints nothing about
-        # the processor, so we play safe by assuming i586.
+	# uname -m prints for DJGPP always 'pc', but it prints nothing about
+	# the processor, so we play safe by assuming i586.
 	# Note: whatever this is, it MUST be the same as what config.sub
 	# prints for the "djgpp" host, or else GDB configury will decide that
 	# this is a cross-build.
 	echo i586-pc-msdosdjgpp
-        exit ;;
+	exit ;;
     Intel:Mach:3*:*)
 	echo i386-pc-mach3
 	exit ;;
@@ -1084,8 +1100,8 @@
 	/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
 	  && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
     3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)
-        /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
-          && { echo i486-ncr-sysv4; exit; } ;;
+	/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+	  && { echo i486-ncr-sysv4; exit; } ;;
     NCR*:*:4.2:* | MPRAS*:*:4.2:*)
 	OS_REL='.3'
 	test -r /etc/.relid \
@@ -1128,10 +1144,10 @@
 		echo ns32k-sni-sysv
 	fi
 	exit ;;
-    PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort
-                      # says <Richard.M.Bartel at ccMail.Census.GOV>
-        echo i586-unisys-sysv4
-        exit ;;
+    PENTIUM:*:4.0*:*)	# Unisys `ClearPath HMP IX 4000' SVR4/MP effort
+			# says <Richard.M.Bartel at ccMail.Census.GOV>
+	echo i586-unisys-sysv4
+	exit ;;
     *:UNIX_System_V:4*:FTX*)
 	# From Gerald Hewes <hewes at openmarket.com>.
 	# How about differentiating between stratus architectures? -djm
@@ -1157,11 +1173,11 @@
 	exit ;;
     R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
 	if [ -d /usr/nec ]; then
-	        echo mips-nec-sysv${UNAME_RELEASE}
+		echo mips-nec-sysv${UNAME_RELEASE}
 	else
-	        echo mips-unknown-sysv${UNAME_RELEASE}
+		echo mips-unknown-sysv${UNAME_RELEASE}
 	fi
-        exit ;;
+	exit ;;
     BeBox:BeOS:*:*)	# BeOS running on hardware made by Be, PPC only.
 	echo powerpc-be-beos
 	exit ;;
@@ -1226,6 +1242,9 @@
     *:QNX:*:4*)
 	echo i386-pc-qnx
 	exit ;;
+    NEO-?:NONSTOP_KERNEL:*:*)
+	echo neo-tandem-nsk${UNAME_RELEASE}
+	exit ;;
     NSE-?:NONSTOP_KERNEL:*:*)
 	echo nse-tandem-nsk${UNAME_RELEASE}
 	exit ;;
@@ -1271,13 +1290,13 @@
 	echo pdp10-unknown-its
 	exit ;;
     SEI:*:*:SEIUX)
-        echo mips-sei-seiux${UNAME_RELEASE}
+	echo mips-sei-seiux${UNAME_RELEASE}
 	exit ;;
     *:DragonFly:*:*)
 	echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
 	exit ;;
     *:*VMS:*:*)
-    	UNAME_MACHINE=`(uname -p) 2>/dev/null`
+	UNAME_MACHINE=`(uname -p) 2>/dev/null`
 	case "${UNAME_MACHINE}" in
 	    A*) echo alpha-dec-vms ; exit ;;
 	    I*) echo ia64-dec-vms ; exit ;;
@@ -1317,11 +1336,11 @@
 #include <sys/param.h>
   printf ("m68k-sony-newsos%s\n",
 #ifdef NEWSOS4
-          "4"
+	"4"
 #else
-	  ""
+	""
 #endif
-         ); exit (0);
+	); exit (0);
 #endif
 #endif
 

Modified: llvm/trunk/autoconf/config.sub
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.sub?rev=137984&r1=137983&r2=137984&view=diff
==============================================================================
--- llvm/trunk/autoconf/config.sub (original)
+++ llvm/trunk/autoconf/config.sub Thu Aug 18 16:23:18 2011
@@ -1,10 +1,10 @@
 #! /bin/sh
 # Configuration validation subroutine script.
 #   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
-#   Free Software Foundation, Inc.
+#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
+#   2011 Free Software Foundation, Inc.
 
-timestamp='2009-08-19'
+timestamp='2011-08-15'
 
 # This file is (in principle) common to ALL GNU software.
 # The presence of a machine in this file suggests that SOME GNU software
@@ -75,8 +75,9 @@
 version="\
 GNU config.sub ($timestamp)
 
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free
+Software Foundation, Inc.
 
 This is free software; see the source for copying conditions.  There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -123,8 +124,9 @@
 # Here we must recognize all the valid KERNEL-OS combinations.
 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
 case $maybe_os in
-  nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
-  uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
+  linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
+  knetbsd*-gnu* | netbsd*-gnu* | \
   kopensolaris*-gnu* | \
   storm-chaos* | os2-emx* | rtmk-nova*)
     os=-$maybe_os
@@ -156,8 +158,8 @@
 		os=
 		basic_machine=$1
 		;;
-        -bluegene*)
-	        os=-cnk
+	-bluegene*)
+		os=-cnk
 		;;
 	-sim | -cisco | -oki | -wec | -winbond)
 		os=
@@ -173,10 +175,10 @@
 		os=-chorusos
 		basic_machine=$1
 		;;
- 	-chorusrdb)
- 		os=-chorusrdb
+	-chorusrdb)
+		os=-chorusrdb
 		basic_machine=$1
- 		;;
+		;;
 	-hiux*)
 		os=-hiuxwe2
 		;;
@@ -244,6 +246,7 @@
 	# Recognize the basic CPU types without company name.
 	# Some are omitted here because they have special meanings below.
 	1750a | 580 \
+	| 32e[bl] | 64e[bl] \
 	| a29k \
 	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
 	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
@@ -281,26 +284,39 @@
 	| moxie \
 	| mt \
 	| msp430 \
+	| nds32 | nds32le | nds32be \
 	| nios | nios2 \
 	| ns16k | ns32k \
+	| open8 \
 	| or32 \
 	| pdp10 | pdp11 | pj | pjl \
-	| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+	| powerpc | powerpc64 | powerpc64le | powerpcle \
 	| pyramid \
+	| rx \
 	| score \
 	| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
 	| sh64 | sh64le \
 	| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
 	| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
-	| spu | strongarm \
-	| tahoe | thumb | tic4x | tic80 | tron \
-	| v850 | v850e \
+	| spu \
+	| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
+	| ubicom32 \
+	| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
 	| we32k \
-	| x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
+	| x86 | xc16x | xstormy16 | xtensa \
 	| z8k | z80)
 		basic_machine=$basic_machine-unknown
 		;;
-	m6811 | m68hc11 | m6812 | m68hc12)
+	c54x)
+		basic_machine=tic54x-unknown
+		;;
+	c55x)
+		basic_machine=tic55x-unknown
+		;;
+	c6x)
+		basic_machine=tic6x-unknown
+		;;
+	m6811 | m68hc11 | m6812 | m68hc12 | picochip)
 		# Motorola 68HC11/12.
 		basic_machine=$basic_machine-unknown
 		os=-none
@@ -311,6 +327,18 @@
 		basic_machine=mt-unknown
 		;;
 
+	strongarm | thumb | xscale)
+		basic_machine=arm-unknown
+		;;
+
+	xscaleeb)
+		basic_machine=armeb-unknown
+		;;
+
+	xscaleel)
+		basic_machine=armel-unknown
+		;;
+
 	# We use `pc' rather than `unknown'
 	# because (1) that's what they normally are, and
 	# (2) the word "unknown" tends to confuse beginning users.
@@ -324,6 +352,7 @@
 		;;
 	# Recognize the basic CPU types with company name.
 	580-* \
+	| 32e[bl]-* | 64e[bl]-* \
 	| a29k-* \
 	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
 	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
@@ -331,7 +360,7 @@
 	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
 	| avr-* | avr32-* \
 	| bfin-* | bs2000-* \
-	| c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
+	| c[123]* | c30-* | [cjt]90-* | c4x-* \
 	| clipper-* | craynv-* | cydra-* \
 	| d10v-* | d30v-* | dlx-* \
 	| elxsi-* \
@@ -365,24 +394,29 @@
 	| mmix-* \
 	| mt-* \
 	| msp430-* \
+	| nds32-* | nds32le-* | nds32be-* \
 	| nios-* | nios2-* \
 	| none-* | np1-* | ns16k-* | ns32k-* \
+	| open8-* \
 	| orion-* \
 	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
-	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
 	| pyramid-* \
-	| romp-* | rs6000-* \
+	| romp-* | rs6000-* | rx-* \
 	| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
 	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
 	| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
 	| sparclite-* \
-	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
-	| tahoe-* | thumb-* \
-	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
+	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+	| tahoe-* \
+	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+	| tile*-* \
 	| tron-* \
-	| v850-* | v850e-* | vax-* \
+	| ubicom32-* \
+	| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
+	| vax-* \
 	| we32k-* \
-	| x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
+	| x86-* | x86_64-* | xc16x-* | xps100-* \
 	| xstormy16-* | xtensa*-* \
 	| ymp-* \
 	| z8k-* | z80-*)
@@ -407,7 +441,7 @@
 		basic_machine=a29k-amd
 		os=-udi
 		;;
-    	abacus)
+	abacus)
 		basic_machine=abacus-unknown
 		;;
 	adobe68k)
@@ -477,11 +511,20 @@
 		basic_machine=powerpc-ibm
 		os=-cnk
 		;;
+	c54x-*)
+		basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c55x-*)
+		basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c6x-*)
+		basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	c90)
 		basic_machine=c90-cray
 		os=-unicos
 		;;
-        cegcc)
+	cegcc)
 		basic_machine=arm-unknown
 		os=-cegcc
 		;;
@@ -513,7 +556,7 @@
 		basic_machine=craynv-cray
 		os=-unicosmp
 		;;
-	cr16)
+	cr16 | cr16-*)
 		basic_machine=cr16-unknown
 		os=-elf
 		;;
@@ -729,7 +772,7 @@
 		basic_machine=ns32k-utek
 		os=-sysv
 		;;
-        microblaze)
+	microblaze)
 		basic_machine=microblaze-xilinx
 		;;
 	mingw32)
@@ -772,6 +815,10 @@
 		basic_machine=i370-ibm
 		os=-mvs
 		;;
+	nacl)
+		basic_machine=32el-unknown
+		os=-nacl
+		;;
 	ncr3000)
 		basic_machine=i486-ncr
 		os=-sysv4
@@ -836,6 +883,12 @@
 	np1)
 		basic_machine=np1-gould
 		;;
+	neo-tandem)
+		basic_machine=neo-tandem
+		;;
+	nse-tandem)
+		basic_machine=nse-tandem
+		;;
 	nsr-tandem)
 		basic_machine=nsr-tandem
 		;;
@@ -918,9 +971,10 @@
 		;;
 	power)	basic_machine=power-ibm
 		;;
-	ppc)	basic_machine=powerpc-unknown
+	ppc | ppcbe)	basic_machine=powerpc-unknown
 		;;
-	ppc-*)	basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+	ppc-* | ppcbe-*)
+		basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	ppcle | powerpclittle | ppc-le | powerpc-little)
 		basic_machine=powerpcle-unknown
@@ -1014,6 +1068,9 @@
 		basic_machine=i860-stratus
 		os=-sysv4
 		;;
+	strongarm-* | thumb-*)
+		basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	sun2)
 		basic_machine=m68000-sun
 		;;
@@ -1070,20 +1127,8 @@
 		basic_machine=t90-cray
 		os=-unicos
 		;;
-	tic54x | c54x*)
-		basic_machine=tic54x-unknown
-		os=-coff
-		;;
-	tic55x | c55x*)
-		basic_machine=tic55x-unknown
-		os=-coff
-		;;
-	tic6x | c6x*)
-		basic_machine=tic6x-unknown
-		os=-coff
-		;;
 	tile*)
-		basic_machine=tile-unknown
+		basic_machine=$basic_machine-unknown
 		os=-linux-gnu
 		;;
 	tx39)
@@ -1153,6 +1198,9 @@
 	xps | xps100)
 		basic_machine=xps100-honeywell
 		;;
+	xscale-* | xscalee[bl]-*)
+		basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'`
+		;;
 	ymp)
 		basic_machine=ymp-cray
 		os=-unicos
@@ -1250,15 +1298,15 @@
 if [ x"$os" != x"" ]
 then
 case $os in
-        # First match some system type aliases
-        # that might get confused with valid system types.
+	# First match some system type aliases
+	# that might get confused with valid system types.
 	# -solaris* is a basic system type, with this one exception.
-	-solaris1 | -solaris1.*)
-		os=`echo $os | sed -e 's|solaris1|sunos4|'`
-		;;
 	-auroraux)
 		os=-auroraux
 		;;
+	-solaris1 | -solaris1.*)
+		os=`echo $os | sed -e 's|solaris1|sunos4|'`
+		;;
 	-solaris)
 		os=-solaris2
 		;;
@@ -1277,8 +1325,8 @@
 	# -sysv* is not here because it comes later, after sysvr4.
 	-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
 	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
-	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* | -sym* \
-	      | -kopensolaris* \
+	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
+	      | -sym* | -kopensolaris* \
 	      | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
 	      | -aos* | -aros* \
 	      | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
@@ -1291,7 +1339,8 @@
 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
 	      | -chorusos* | -chorusrdb* | -cegcc* \
 	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
-	      | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
+	      | -mingw32* | -linux-gnu* | -linux-android* \
+	      | -linux-newlib* | -linux-uclibc* \
 	      | -uxpv* | -beos* | -mpeix* | -udk* \
 	      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
 	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
@@ -1299,7 +1348,7 @@
 	      | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
 	      | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
 	      | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
-	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops*)
+	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es*)
 	# Remember, each alternative MUST END IN *, to match a version number.
 		;;
 	-qnx*)
@@ -1338,7 +1387,7 @@
 	-opened*)
 		os=-openedition
 		;;
-        -os400*)
+	-os400*)
 		os=-os400
 		;;
 	-wince*)
@@ -1387,7 +1436,7 @@
 	-sinix*)
 		os=-sysv4
 		;;
-        -tpf*)
+	-tpf*)
 		os=-tpf
 		;;
 	-triton*)
@@ -1432,6 +1481,8 @@
 	-dicos*)
 		os=-dicos
 		;;
+	-nacl*)
+		;;
 	-none)
 		;;
 	*)
@@ -1454,10 +1505,10 @@
 # system, and we'll never get to this point.
 
 case $basic_machine in
-        score-*)
+	score-*)
 		os=-elf
 		;;
-        spu-*)
+	spu-*)
 		os=-elf
 		;;
 	*-acorn)
@@ -1469,8 +1520,17 @@
 	arm*-semi)
 		os=-aout
 		;;
-        c4x-* | tic4x-*)
-        	os=-coff
+	c4x-* | tic4x-*)
+		os=-coff
+		;;
+	tic54x-*)
+		os=-coff
+		;;
+	tic55x-*)
+		os=-coff
+		;;
+	tic6x-*)
+		os=-coff
 		;;
 	# This must come before the *-dec entry.
 	pdp10-*)
@@ -1497,7 +1557,7 @@
 	m68*-cisco)
 		os=-aout
 		;;
-        mep-*)
+	mep-*)
 		os=-elf
 		;;
 	mips*-cisco)
@@ -1524,7 +1584,7 @@
 	*-ibm)
 		os=-aix
 		;;
-    	*-knuth)
+	*-knuth)
 		os=-mmixware
 		;;
 	*-wec)



From gohman at apple.com  Thu Aug 18 16:27:42 2011
From: gohman at apple.com (Dan Gohman)
Date: Thu, 18 Aug 2011 21:27:42 -0000
Subject: [llvm-commits] [llvm] r137985 -
	/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
Message-ID: <20110818212742.61C202A6C12C@llvm.org>

Author: djg
Date: Thu Aug 18 16:27:42 2011
New Revision: 137985

URL: http://llvm.org/viewvc/llvm-project?rev=137985&view=rev
Log:
Make it clear that this code is iterating in reverse order through the array.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=137985&r1=137984&r2=137985&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Thu Aug 18 16:27:42 2011
@@ -2596,8 +2596,9 @@
     Order.push_back(Stack.pop_back_val().first);
   }
   bool BottomUpNestingDetected = false;
-  while (!Order.empty()) {
-    BasicBlock *BB = Order.pop_back_val();
+  for (SmallVectorImpl<BasicBlock *>::const_reverse_iterator I =
+         Order.rbegin(), E = Order.rend(); I != E; ++I) {
+    BasicBlock *BB = *I;
     BottomUpNestingDetected |= VisitBottomUp(BB, BBStates, Retains);
   }
 



From grosbach at apple.com  Thu Aug 18 16:50:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 18 Aug 2011 21:50:53 -0000
Subject: [llvm-commits] [llvm] r137986 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 test/CodeGen/Thumb2/thumb2-ldm.ll test/MC/ARM/basic-thumb-instructions.s
 test/MC/ARM/thumb-diagnostics.s test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110818215053.EE31C2A6C12C@llvm.org>

Author: grosbach
Date: Thu Aug 18 16:50:53 2011
New Revision: 137986

URL: http://llvm.org/viewvc/llvm-project?rev=137986&view=rev
Log:
Thumb assembly parsing and encoding for LDM instruction.

Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Aug 18 16:50:53 2011
@@ -683,8 +683,8 @@
                            InstrItinClass itin_upd, bits<6> T1Enc,
                            bit L_bit, string baseOpc> {
   def IA :
-    T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-        itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
+    T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
+        itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
        T1Encoding<T1Enc> {
     bits<3> Rn;
     bits<8> regs;
@@ -696,7 +696,7 @@
     InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 
                  "$Rn = $wb", itin_upd>,
     PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
-                       GPR:$Rn, pred:$p, reglist:$regs)> {
+                       tGPR:$Rn, pred:$p, reglist:$regs)> {
     let Size = 2;
     let OutOperandList = (outs GPR:$wb);
     let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
@@ -720,6 +720,11 @@
 
 } // neverHasSideEffects
 
+def : InstAlias<"ldm${p} $Rn!, $regs",
+                (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
+        Requires<[IsThumb, IsThumb1Only]>;
+
+
 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
                IIC_iPop,

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 18 16:50:53 2011
@@ -2988,6 +2988,29 @@
                    "bitfield width must be in range [1,32-lsb]");
     return false;
   }
+  case ARM::tLDMIA: {
+    // Thumb LDM instructions are writeback iff the base register is not
+    // in the register list.
+    unsigned Rn = Inst.getOperand(0).getReg();
+    bool doesWriteback = true;
+    for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
+      unsigned Reg = Inst.getOperand(i).getReg();
+      if (Reg == Rn)
+        doesWriteback = false;
+      // Anything other than a low register isn't legal here.
+      if (getARMRegisterNumbering(Reg) > 7)
+        return Error(Operands[4]->getStartLoc(),
+                     "registers must be in range r0-r7");
+    }
+    // If we should have writeback, then there should be a '!' token.
+    if (doesWriteback &&
+        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
+         static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
+      return Error(Operands[2]->getStartLoc(),
+                   "writeback operator '!' expected");
+
+    break;
+  }
   }
 
   return false;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Thu Aug 18 16:50:53 2011
@@ -155,9 +155,9 @@
     }
 
     if (Opcode == ARM::tLDMIA)
-      O << "\tldmia";
+      O << "\tldm";
     else if (Opcode == ARM::tSTMIA)
-      O << "\tstmia";
+      O << "\tstm";
     else
       llvm_unreachable("Unknown opcode!");
 

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ldm.ll Thu Aug 18 16:50:53 2011
@@ -15,7 +15,7 @@
 define i32 @t2() {
 ; CHECK: t2:
 ; CHECK: push {r7, lr}
-; CHECK: ldmia
+; CHECK: ldm
 ; CHECK: pop {r7, pc}
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
         %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Thu Aug 18 16:50:53 2011
@@ -162,3 +162,15 @@
         eors r4, r5
 
 @ CHECK: eors	r4, r5                  @ encoding: [0x6c,0x40]
+
+
+ at ------------------------------------------------------------------------------
+@ LDM
+ at ------------------------------------------------------------------------------
+        ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
+        ldm r2!, {r1, r3, r4, r5, r7}
+        ldm r1, {r1}
+
+@ CHECK: ldm	r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
+@ CHECK: ldm	r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
+@ CHECK: ldm	r1, {r1}                @ encoding: [0x02,0xc9]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Thu Aug 18 16:50:53 2011
@@ -39,3 +39,13 @@
 error: invalid operand for instruction
         bkpt #-1
              ^
+
+@ Invalid writeback and register lists for LDM
+        ldm r2!, {r5, r8}
+        ldm r2, {r5, r7}
+@ CHECK-ERRORS: error: registers must be in range r0-r7
+@ CHECK-ERRORS:         ldm r2!, {r5, r8}
+@ CHECK-ERRORS:                  ^
+@ CHECK-ERRORS: error: writeback operator '!' expected
+@ CHECK-ERRORS:         ldm r2, {r5, r7}
+@ CHECK-ERRORS:             ^

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=137986&r1=137985&r2=137986&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Thu Aug 18 16:50:53 2011
@@ -27,7 +27,7 @@
 # CHECK:	cmn.w	r0, #31
 0x10 0xf1 0x1f 0x0f
 
-# CHECK:	ldmia	r0!, {r1}
+# CHECK:	ldm	r0!, {r1}
 0x02 0xc8
 
 # CHECK:	ldr	r5, #432
@@ -112,7 +112,7 @@
 # CHECK:	lsleq	r1, r0, #28
 0x01 0x07
 
-# CHECK:	stmiane	r0!, {r1, r2, r3}
+# CHECK:	stmne	r0!, {r1, r2, r3}
 0x0e 0xc0
 
 # IT block end
@@ -146,13 +146,13 @@
 # CHECK:	stmdb.w	sp, {r0, r2, r3, r8, r11, lr}
 0x0d 0xe9 0x0d 0x49
 
-# CHECK:	stmia	r5!, {r0, r1, r2, r3, r4}
+# CHECK:	stm	r5!, {r0, r1, r2, r3, r4}
 0x1f 0xc5
 
-# CHECK:	ldmia	r5, {r0, r1, r2, r3, r4, r5}
+# CHECK:	ldm	r5, {r0, r1, r2, r3, r4, r5}
 0x3f 0xcd
 
-# CHECK:	ldmia	r5!, {r0, r1, r2, r3, r4}
+# CHECK:	ldm	r5!, {r0, r1, r2, r3, r4}
 0x1f 0xcd
 
 # CHECK:	addw	r0, pc, #1050



From krasin at chromium.org  Thu Aug 18 16:57:29 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 14:57:29 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
	<FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
Message-ID: <CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>

Eric,

I have added comments before declarations of LastLocalValue and EmitStartPt.
Please find the patch attached or http://codereview.chromium.org/7612002/

Ivan Krasin

On Thu, Aug 18, 2011 at 1:14 PM, Eric Christopher <echristo at apple.com> wrote:
> :) Almost there.
>
> Can you describe the full algorithm in the few lines before the declaration of LastLocalValue and EmitStartPt?
>
> The rationale for the built-in is fine.
>
> -eric
>
> On Aug 18, 2011, at 1:12 PM, Ivan Krasin wrote:
>
>> Friendly ping :)
>>
>> On Tue, Aug 16, 2011 at 12:14 PM, Ivan Krasin <krasin at google.com> wrote:
>>> Eric,
>>>
>>> could you please take another look?
>>>
>>> Ivan
>>>
>>> On Mon, Aug 15, 2011 at 2:29 PM, Ivan Krasin <krasin at google.com> wrote:
>>>> On Thu, Aug 11, 2011 at 3:20 PM, Eric Christopher <echristo at apple.com> wrote:
>>>>>
>>>>> On Aug 10, 2011, at 4:01 PM, Ivan Krasin wrote:
>>>>>
>>>>> <flush-local-value-map.patch>
>>>>>
>>>>> In general I think the patch is OK. ?A few requests:
>>>>> ? ?MachineInstr *LastLocalValue;
>>>>> + ?MachineInstr *OrigLocalValue;
>>>>> ?.
>>>>> ? ?// Start out as null, meaining no local-value instructions have
>>>>> ? ?// been emitted.
>>>>> - ?LastLocalValue = 0;
>>>>> + ?OrigLocalValue = 0;
>>>>> A lot of the code you've changed hasn't had any comments written or updated
>>>>> for the new behavior. It'd be good to get an updated description of how the
>>>>> LocalValueMap is working and how it interacts with constants.
>>>> I have renamed OrigLocalValue to EmitStartPt which is (I believe) less
>>>> confusing naming, since it points to the place in the block where it's
>>>> allowed to start emitting instructions.
>>>>
>>>>> In particular:
>>>>> + ?if (!isa<IntrinsicInst>(F))
>>>>> + ? ?flushLocalValueMap();
>>>>> +
>>>>> Here. The location of this here doesn't make a whole lot of sense and it'd
>>>>> be good if you could explain it.
>>>> I've added the explanation. Thanks for the suggestion.
>>>>
>>>>> A better way to do this would be, as Jakob suggested, use the LocalValueMap
>>>>> as a storage for constants and locations that you've used them in the block
>>>>> and then emit all of the constants at that point rather than this weird
>>>>> flushing mechanism.
>>>> I've tried to do that. It slows down -O0 build which is unacceptable.
>>>> The problem is that we have to emit all local values to the start of
>>>> the block, store last use for each of them and spread them through the
>>>> block once the processing of the block is done. It makes it slower...
>>>> So, I would prefer to stay with the patch that makes all the metrics
>>>> slightly better on average (code size/stack size/compile time). Is it
>>>> fine with you?
>>>>
>>>> Please, find the updated patch attached.
>>>>
>>>> Ivan Krasin
>>>>
>>>>> -eric
>>>>
>>>
>
>
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From echristo at apple.com  Thu Aug 18 16:58:22 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 14:58:22 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
	<FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
	<CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
Message-ID: <170718C3-F0DD-4E76-8764-E9E7E6FBED4E@apple.com>


On Aug 18, 2011, at 2:57 PM, Ivan Krasin wrote:

> Eric,
> 
> I have added comments before declarations of LastLocalValue and EmitStartPt.
> Please find the patch attached or http://codereview.chromium.org/7612002/

Looks good. Thanks.

-eric

From stoklund at 2pi.dk  Thu Aug 18 17:01:21 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 18 Aug 2011 15:01:21 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
	<FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
	<CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
Message-ID: <147DBC2A-E219-4732-956F-1C358512AB8B@2pi.dk>


On Aug 18, 2011, at 2:57 PM, Ivan Krasin wrote:

> Eric,
> 
> I have added comments before declarations of LastLocalValue and EmitStartPt.
> Please find the patch attached or http://codereview.chromium.org/7612002/

+  /// flus\hLocalValueMap - clears LocalValueMap and moves the area for the

Spurious backslash.

/jakob


From krasin at google.com  Thu Aug 18 17:05:20 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 18 Aug 2011 15:05:20 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <147DBC2A-E219-4732-956F-1C358512AB8B@2pi.dk>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
	<FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
	<CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
	<147DBC2A-E219-4732-956F-1C358512AB8B@2pi.dk>
Message-ID: <CAOei5ReC3rAk98pKLVHd5ti0CqK9dsN5LSYVrJxnAg+n86kWBg@mail.gmail.com>

Thanks, the typo is fixed.

On Thu, Aug 18, 2011 at 3:01 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Aug 18, 2011, at 2:57 PM, Ivan Krasin wrote:
>
>> Eric,
>>
>> I have added comments before declarations of LastLocalValue and EmitStartPt.
>> Please find the patch attached or http://codereview.chromium.org/7612002/
>
> + ?/// flus\hLocalValueMap - clears LocalValueMap and moves the area for the
>
> Spurious backslash.
>
> /jakob
>
>
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From krasin at chromium.org  Thu Aug 18 17:06:11 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 22:06:11 -0000
Subject: [llvm-commits] [llvm] r137993 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
 test/CodeGen/ARM/debug-info-blocks.ll test/CodeGen/X86/fast-isel-x86-64.ll
Message-ID: <20110818220611.211602A6C12C@llvm.org>

Author: krasin
Date: Thu Aug 18 17:06:10 2011
New Revision: 137993

URL: http://llvm.org/viewvc/llvm-project?rev=137993&view=rev
Log:
FastISel: avoid function calls between the materialization of the constant and its use.


Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=137993&r1=137992&r2=137993&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Aug 18 17:06:10 2011
@@ -54,8 +54,18 @@
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
   const TargetRegisterInfo &TRI;
+
+  /// The position of the last instruction for materializing constants
+  /// for use in the current block. It resets to EmitStartPt when it
+  /// makes sense (for example, it's usually profitable to avoid function
+  /// calls between the definition and the use)
   MachineInstr *LastLocalValue;
 
+  /// The top most instruction in the current block that is allowed for
+  /// emitting local variables. LastLocalValue resets to EmitStartPt when
+  /// it makes sense (for example, on function calls)
+  MachineInstr *EmitStartPt;
+
 public:
   /// getLastLocalValue - Return the position of the last instruction
   /// emitted for materializing constants for use in the current block.
@@ -63,7 +73,10 @@
 
   /// setLastLocalValue - Update the position of the last instruction
   /// emitted for materializing constants for use in the current block.
-  void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
+  void setLastLocalValue(MachineInstr *I) {
+    EmitStartPt = I;
+    LastLocalValue = I;
+  }
 
   /// startNewBlock - Set the current block to which generated machine
   /// instructions will be appended, and clear the local CSE map.
@@ -358,6 +371,11 @@
   /// be materialized with new instructions.
   unsigned materializeRegForValue(const Value *V, MVT VT);
 
+  /// flushLocalValueMap - clears LocalValueMap and moves the area for the
+  /// new local variables to the beginning of the block. It helps to avoid
+  /// spilling cached variables across heavy instructions like calls.
+  void flushLocalValueMap();
+
   /// hasTrivialKill - Test whether the given value has exactly one use.
   bool hasTrivialKill(const Value *V) const;
 };

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=137993&r1=137992&r2=137993&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Aug 18 17:06:10 2011
@@ -66,17 +66,22 @@
 void FastISel::startNewBlock() {
   LocalValueMap.clear();
 
-  // Start out as null, meaining no local-value instructions have
-  // been emitted.
-  LastLocalValue = 0;
+  EmitStartPt = 0;
 
-  // Advance the last local value past any EH_LABEL instructions.
+  // Advance the emit start point past any EH_LABEL instructions.
   MachineBasicBlock::iterator
     I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
   while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
-    LastLocalValue = I;
+    EmitStartPt = I;
     ++I;
   }
+  LastLocalValue = EmitStartPt;
+}
+
+void FastISel::flushLocalValueMap() {
+  LocalValueMap.clear();
+  LastLocalValue = EmitStartPt;
+  recomputeInsertPt();
 }
 
 bool FastISel::hasTrivialKill(const Value *V) const {
@@ -645,6 +650,16 @@
   }
   }
 
+  // Usually, it does not make sense to initialize a value,
+  // make an unrelated function call and use the value, because
+  // it tends to be spilled on the stack. So, we move the pointer
+  // to the last local value to the beginning of the block, so that
+  // all the values which have already been materialized,
+  // appear after the call. It also makes sense to skip intrinsics
+  // since they tend to be inlined.
+  if (!isa<IntrinsicInst>(F))
+    flushLocalValueMap();
+
   // An arbitrary call. Bail.
   return false;
 }

Modified: llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=137993&r1=137992&r2=137993&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll Thu Aug 18 17:06:10 2011
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 < %s | FileCheck %s
-; CHECK: @DEBUG_VALUE: mydata <- [sp+#8]+#0
+; CHECK: @DEBUG_VALUE: mydata <- [sp+#4]+#0
 ; Radar 9331779
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-macosx10.7.0"

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll?rev=137993&r1=137992&r2=137993&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll Thu Aug 18 17:06:10 2011
@@ -259,4 +259,27 @@
 ; CHECK: test21:
 ; CHECK-NOT: pxor
 ; CHECK: movsd	LCPI
-}
\ No newline at end of file
+}
+
+; Check that immediate arguments to a function
+; do not cause massive spilling and are used
+; as immediates just before the call.
+define void @test22() nounwind {
+entry:
+  call void @foo22(i32 0)
+  call void @foo22(i32 1)
+  call void @foo22(i32 2)
+  call void @foo22(i32 3)
+  ret void
+; CHECK: test22:
+; CHECK: movl	$0, %edi
+; CHECK: callq	_foo22
+; CHECK: movl	$1, %edi
+; CHECK: callq	_foo22
+; CHECK: movl	$2, %edi
+; CHECK: callq	_foo22
+; CHECK: movl	$3, %edi
+; CHECK: callq	_foo22
+}
+
+declare void @foo22(i32)



From krasin at google.com  Thu Aug 18 17:07:27 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 18 Aug 2011 15:07:27 -0700
Subject: [llvm-commits] X86 FastISel: Emit immediate call arguments
 locally to save stack size when compiling with -O0
In-Reply-To: <CAOei5ReC3rAk98pKLVHd5ti0CqK9dsN5LSYVrJxnAg+n86kWBg@mail.gmail.com>
References: <CANsZN1F5JZcmLEsJ8hw07nhfhRAL18FDBE_dm=M4eWRGUhwFzA@mail.gmail.com>
	<6E62C135-64F3-43C4-8C33-19CB9679FBD2@2pi.dk>
	<CAOei5RcNzNTbWy5rZ7ji-7JfBwbF-UpWNHZ8WOp6XQr7Ssdeiw@mail.gmail.com>
	<DD407F18-490D-49E1-BE35-D7BA8E1CFD56@2pi.dk>
	<CAOei5ReV7E2-v7Q_i=iN_TG1H7vtuqVeZxdfSvK7B7ZBAfhU8w@mail.gmail.com>
	<729D9CF6-3563-4841-A45A-469DF60B756D@2pi.dk>
	<CAOei5Rc5J28GC5fRdTRzMcHKQ0qKHtF1j2C4w5qrDzTfOoZ=aA@mail.gmail.com>
	<8781F92F-0D05-4FEA-9B96-31682D952E6E@apple.com>
	<CAOei5RcskfE0z38sz_7X+UNy=2+h_vX99UOnqoWMLNwKFEk2zQ@mail.gmail.com>
	<CAOei5RdhvpbrPRNjSEzEzrCFQwuBMq4ofobKRP2c-rx3QfwcOQ@mail.gmail.com>
	<CAOei5Rcw-cZ3KA7XgcqJ-OvNs8cQsD=SM=+uAVQKn39ve8Jzqg@mail.gmail.com>
	<FECC2DCB-FB80-4258-8D86-197EB41B7EFC@apple.com>
	<CAOei5RfRVgYyK_42_sRwCqY1w_VifUpRtS_bBM8upSSE-DJMAg@mail.gmail.com>
	<147DBC2A-E219-4732-956F-1C358512AB8B@2pi.dk>
	<CAOei5ReC3rAk98pKLVHd5ti0CqK9dsN5LSYVrJxnAg+n86kWBg@mail.gmail.com>
Message-ID: <CAOei5Rf8T5DpL2-+MQ-5-Fo9vR4V5Fmz6Nn52Z2sG1=VSZR2zw@mail.gmail.com>

Committed as r137993.

On Thu, Aug 18, 2011 at 3:05 PM, Ivan Krasin <krasin at google.com> wrote:
> Thanks, the typo is fixed.
>
> On Thu, Aug 18, 2011 at 3:01 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>>
>> On Aug 18, 2011, at 2:57 PM, Ivan Krasin wrote:
>>
>>> Eric,
>>>
>>> I have added comments before declarations of LastLocalValue and EmitStartPt.
>>> Please find the patch attached or http://codereview.chromium.org/7612002/
>>
>> + ?/// flus\hLocalValueMap - clears LocalValueMap and moves the area for the
>>
>> Spurious backslash.
>>
>> /jakob
>>
>>
>


From resistor at mac.com  Thu Aug 18 17:11:02 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 22:11:02 -0000
Subject: [llvm-commits] [llvm] r137995 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
Message-ID: <20110818221102.A125C2A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 17:11:02 2011
New Revision: 137995

URL: http://llvm.org/viewvc/llvm-project?rev=137995&view=rev
Log:
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137995&r1=137994&r2=137995&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 18 17:11:02 2011
@@ -1317,27 +1317,34 @@
   unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
   unsigned mode = fieldFromInstruction32(Insn, 0, 5);
 
+  DecodeStatus S = Success;
+
   // imod == '01' --> UNPREDICTABLE
-  if (imod == 1) return Fail;
+  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
+  // return failure here.  The '01' imod value is unprintable, so there's
+  // nothing useful we could do even if we returned UNPREDICTABLE.
+
+  if (imod == 1) CHECK(S, Fail);
 
-  if (M && mode && imod && iflags) {
+  if (imod && M) {
     Inst.setOpcode(ARM::CPS3p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return Success;
-  } else if (!mode && !M) {
+  } else if (imod && !M) {
     Inst.setOpcode(ARM::CPS2p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
-    return Success;
-  } else if (!imod && !iflags && M) {
+    if (mode) CHECK(S, Unpredictable);
+  } else if (!imod && M) {
     Inst.setOpcode(ARM::CPS1p);
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return Success;
-  }
+    if (iflags) CHECK(S, Unpredictable);
+  } else
+    // imod == '00' && M == '0' --> UNPREDICTABLE
+    CHECK(S, Unpredictable);
 
-  return Fail;
+  return S;
 }
 
 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
@@ -2649,7 +2656,7 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
 
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
@@ -2670,7 +2677,7 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
 
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt?rev=137995&r1=137994&r2=137995&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt Thu Aug 18 17:11:02 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
 
 # invalid (imod, M, iflags) combination
 0x93 0x1c 0x02 0xf1



From resistor at mac.com  Thu Aug 18 17:15:25 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 22:15:25 -0000
Subject: [llvm-commits] [llvm] r137997 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20110818221525.40FCE2A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 17:15:25 2011
New Revision: 137997

URL: http://llvm.org/viewvc/llvm-project?rev=137997&view=rev
Log:
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137997&r1=137996&r2=137997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 18 17:15:25 2011
@@ -1340,9 +1340,12 @@
     Inst.setOpcode(ARM::CPS1p);
     Inst.addOperand(MCOperand::CreateImm(mode));
     if (iflags) CHECK(S, Unpredictable);
-  } else
+  } else {
     // imod == '00' && M == '0' --> UNPREDICTABLE
+    Inst.setOpcode(ARM::CPS1p);
+    Inst.addOperand(MCOperand::CreateImm(mode));
     CHECK(S, Unpredictable);
+  }
 
   return S;
 }



From krasin at chromium.org  Thu Aug 18 17:20:55 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 15:20:55 -0700
Subject: [llvm-commits] [PATCH]Add NativeClient operating system support
Message-ID: <CAOei5RdLyvQWVhOog2DKjutEmjRAEujGprh1yjibNE4i0dZGhw@mail.gmail.com>

Hi llvm team,

this patch adds support of NativeClient (*-*-nacl) OS support to LLVM.
It's already supported in autoconf/config.sub.

Please find the patch attached or online:
http://codereview.chromium.org/7484050/

The motivation for this change is to start upstreaming PNaCl work. The
whole set of patches include llvm backends (i686, x86_64, ARM),
llvm-gcc (probably, would not be upstreamed because it's deprecated)
and clang (the work has been just started, the amount of changes is
going to be low and the most of the work is expected to be done close
to the mainline).

Please, let me know if it's fine to commit this patch.

Thanks in advance,
Ivan Krasin
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From dpatel at apple.com  Thu Aug 18 17:21:51 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 22:21:51 -0000
Subject: [llvm-commits] [llvm] r137998 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Message-ID: <20110818222151.1055C2A6C12C@llvm.org>

Author: dpatel
Date: Thu Aug 18 17:21:50 2011
New Revision: 137998

URL: http://llvm.org/viewvc/llvm-project?rev=137998&view=rev
Log:
Add new DIE into the map asap.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=137998&r1=137997&r2=137998&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Aug 18 17:21:50 2011
@@ -1030,26 +1030,26 @@
 
 /// createGlobalVariableDIE - create global variable DIE.
 void CompileUnit::createGlobalVariableDIE(const MDNode *N) {
-  DIGlobalVariable GV(N);
-
   // Check for pre-existence.
-  if (getDIE(GV))
+  if (getDIE(N))
     return;
 
-  DIType GTy = GV.getType();
+  DIGlobalVariable GV(N);
   DIE *VariableDIE = new DIE(GV.getTag());
-
-  bool isGlobalVariable = GV.getGlobal() != NULL;
+  // Add to map.
+  insertDIE(N, VariableDIE);
 
   // Add name.
   addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
                    GV.getDisplayName());
   StringRef LinkageName = GV.getLinkageName();
+  bool isGlobalVariable = GV.getGlobal() != NULL;
   if (!LinkageName.empty() && isGlobalVariable)
     addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name, 
                      dwarf::DW_FORM_string,
                      getRealLinkageName(LinkageName));
   // Add type.
+  DIType GTy = GV.getType();
   addType(VariableDIE, GTy);
 
   // Add scoping info.
@@ -1060,8 +1060,6 @@
   }
   // Add line number info.
   addSourceLine(VariableDIE, GV);
-  // Add to map.
-  insertDIE(N, VariableDIE);
   // Add to context owner.
   DIDescriptor GVContext = GV.getContext();
   addToContextOwner(VariableDIE, GVContext);



From resistor at mac.com  Thu Aug 18 17:31:18 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 22:31:18 -0000
Subject: [llvm-commits] [llvm] r138000 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110818223118.275092A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 17:31:17 2011
New Revision: 138000

URL: http://llvm.org/viewvc/llvm-project?rev=138000&view=rev
Log:
Fix the decoding of RFE instruction.  RFEs have the load bit set, while SRSs have it unset.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138000&r1=137999&r2=138000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 18 17:31:17 2011
@@ -1274,31 +1274,65 @@
 
   if (pred == 0xF) {
     switch (Inst.getOpcode()) {
-      case ARM::STMDA:
+      case ARM::LDMDA:
         Inst.setOpcode(ARM::RFEDA);
         break;
-      case ARM::STMDA_UPD:
+      case ARM::LDMDA_UPD:
         Inst.setOpcode(ARM::RFEDA_UPD);
         break;
-      case ARM::STMDB:
+      case ARM::LDMDB:
         Inst.setOpcode(ARM::RFEDB);
         break;
-      case ARM::STMDB_UPD:
+      case ARM::LDMDB_UPD:
         Inst.setOpcode(ARM::RFEDB_UPD);
         break;
-      case ARM::STMIA:
+      case ARM::LDMIA:
         Inst.setOpcode(ARM::RFEIA);
         break;
-      case ARM::STMIA_UPD:
+      case ARM::LDMIA_UPD:
         Inst.setOpcode(ARM::RFEIA_UPD);
         break;
-      case ARM::STMIB:
+      case ARM::LDMIB:
         Inst.setOpcode(ARM::RFEIB);
         break;
-      case ARM::STMIB_UPD:
+      case ARM::LDMIB_UPD:
         Inst.setOpcode(ARM::RFEIB_UPD);
         break;
+      case ARM::STMDA:
+        Inst.setOpcode(ARM::SRSDA);
+        break;
+      case ARM::STMDA_UPD:
+        Inst.setOpcode(ARM::SRSDA_UPD);
+        break;
+      case ARM::STMDB:
+        Inst.setOpcode(ARM::SRSDB);
+        break;
+      case ARM::STMDB_UPD:
+        Inst.setOpcode(ARM::SRSDB_UPD);
+        break;
+      case ARM::STMIA:
+        Inst.setOpcode(ARM::SRSIA);
+        break;
+      case ARM::STMIA_UPD:
+        Inst.setOpcode(ARM::SRSIA_UPD);
+        break;
+      case ARM::STMIB:
+        Inst.setOpcode(ARM::SRSIB);
+        break;
+      case ARM::STMIB_UPD:
+        Inst.setOpcode(ARM::SRSIB_UPD);
+        break;
+      default:
+        CHECK(S, Fail);
     }
+
+    // For stores (which become SRS's, the only operand is the mode.
+    if (fieldFromInstruction32(Insn, 20, 1) == 0) {
+      Inst.addOperand(
+          MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
+      return S;
+    }
+
     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
   }
 

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=138000&r1=137999&r2=138000&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Aug 18 17:31:17 2011
@@ -311,3 +311,6 @@
 
 # CHECK:         strheq  r0, [r0, -r0]
 0xb0 0x00 0x00 0x01
+
+# CHECK: rfedb	#4!
+0x14 0x0 0x32 0xf9



From echristo at apple.com  Thu Aug 18 17:37:42 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 18 Aug 2011 15:37:42 -0700
Subject: [llvm-commits] [PATCH]Add NativeClient operating system support
In-Reply-To: <CAOei5RdLyvQWVhOog2DKjutEmjRAEujGprh1yjibNE4i0dZGhw@mail.gmail.com>
References: <CAOei5RdLyvQWVhOog2DKjutEmjRAEujGprh1yjibNE4i0dZGhw@mail.gmail.com>
Message-ID: <C4308583-731D-484F-88B6-9E470A4ADD8B@apple.com>


On Aug 18, 2011, at 3:20 PM, Ivan Krasin wrote:

> Please, let me know if it's fine to commit this patch.

Yep.

-eric
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From resistor at mac.com  Thu Aug 18 17:47:45 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 18 Aug 2011 22:47:45 -0000
Subject: [llvm-commits] [llvm] r138003 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110818224745.1193C2A6C12C@llvm.org>

Author: resistor
Date: Thu Aug 18 17:47:44 2011
New Revision: 138003

URL: http://llvm.org/viewvc/llvm-project?rev=138003&view=rev
Log:
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138003&r1=138002&r2=138003&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 18 17:47:44 2011
@@ -927,6 +927,8 @@
     case ARM::STC2L_OPTION:
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -946,6 +948,8 @@
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       imm |= U << 8;
     case ARM::LDC_OPTION:
     case ARM::LDCL_OPTION:

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=138003&r1=138002&r2=138003&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Aug 18 17:47:44 2011
@@ -314,3 +314,6 @@
 
 # CHECK: rfedb	#4!
 0x14 0x0 0x32 0xf9
+
+# CHECK: stc2l	p0, cr0, [r2], #-96
+0x18 0x0 0x62 0xfc



From krasin at chromium.org  Thu Aug 18 17:54:21 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 18 Aug 2011 22:54:21 -0000
Subject: [llvm-commits] [llvm] r138005 - in /llvm/trunk:
 autoconf/configure.ac configure include/llvm/ADT/Triple.h
 lib/Support/Triple.cpp
Message-ID: <20110818225421.6331A2A6C12C@llvm.org>

Author: krasin
Date: Thu Aug 18 17:54:21 2011
New Revision: 138005

URL: http://llvm.org/viewvc/llvm-project?rev=138005&view=rev
Log:
Add NativeClient operating system support.

This patch adds support of NativeClient (*-*-nacl) OS support to LLVM.
It's already supported in autoconf/config.sub.

The motivation for this change is to start upstreaming PNaCl work. The
whole set of patches include llvm backends (i686, x86_64, ARM),
llvm-gcc (probably, would not be upstreamed because it's deprecated)
and clang (the work has been just started, the amount of changes is
going to be low and the most of the work is expected to be done close
to the mainline).



Modified:
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure
    llvm/trunk/include/llvm/ADT/Triple.h
    llvm/trunk/lib/Support/Triple.cpp

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=138005&r1=138004&r2=138005&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Thu Aug 18 17:54:21 2011
@@ -299,6 +299,8 @@
     llvm_cv_target_os_type="Haiku" ;;
   *-*-rtems*)
     llvm_cv_target_os_type="RTEMS" ;;
+  *-*-nacl*)
+    llvm_cv_target_os_type="NativeClient" ;;
   *-unknown-eabi*)
     llvm_cv_target_os_type="Freestanding" ;;
   *)

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=138005&r1=138004&r2=138005&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Thu Aug 18 17:54:21 2011
@@ -2341,6 +2341,8 @@
     llvm_cv_target_os_type="Haiku" ;;
   *-*-rtems*)
     llvm_cv_target_os_type="RTEMS" ;;
+  *-*-nacl*)
+    llvm_cv_target_os_type="NativeClient" ;;
   *-unknown-eabi*)
     llvm_cv_target_os_type="Freestanding" ;;
   *)

Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=138005&r1=138004&r2=138005&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Thu Aug 18 17:54:21 2011
@@ -94,7 +94,8 @@
     Win32,
     Haiku,
     Minix,
-    RTEMS
+    RTEMS,
+    NativeClient
   };
   enum EnvironmentType {
     UnknownEnvironment,

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=138005&r1=138004&r2=138005&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Thu Aug 18 17:54:21 2011
@@ -110,6 +110,7 @@
   case Haiku: return "haiku";
   case Minix: return "minix";
   case RTEMS: return "rtems";
+  case NativeClient: return "nacl";
   }
 
   return "<invalid>";



From krasin at google.com  Thu Aug 18 17:55:35 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 18 Aug 2011 15:55:35 -0700
Subject: [llvm-commits] [PATCH]Add NativeClient operating system support
In-Reply-To: <C4308583-731D-484F-88B6-9E470A4ADD8B@apple.com>
References: <CAOei5RdLyvQWVhOog2DKjutEmjRAEujGprh1yjibNE4i0dZGhw@mail.gmail.com>
	<C4308583-731D-484F-88B6-9E470A4ADD8B@apple.com>
Message-ID: <CAOei5RdB9b1U-HtPZW8pnbdNEpfaTSBfZL-RzADNF5e_mr7GLA@mail.gmail.com>

Thanks!
Committed as r138005.

On Thu, Aug 18, 2011 at 3:37 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Aug 18, 2011, at 3:20 PM, Ivan Krasin wrote:
>
> Please, let me know if it's fine to commit this patch.
>
> Yep.
> -eric

From dpatel at apple.com  Thu Aug 18 18:17:55 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 23:17:55 -0000
Subject: [llvm-commits] [llvm] r138006 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfDebug.cpp
 DwarfDebug.h
Message-ID: <20110818231755.98CFB2A6C12C@llvm.org>

Author: dpatel
Date: Thu Aug 18 18:17:55 2011
New Revision: 138006

URL: http://llvm.org/viewvc/llvm-project?rev=138006&view=rev
Log:
Eliminate unnecessary forwarding function.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=138006&r1=138005&r2=138006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Aug 18 18:17:55 2011
@@ -1035,6 +1035,9 @@
     return;
 
   DIGlobalVariable GV(N);
+  if (!GV.Verify())
+    return;
+
   DIE *VariableDIE = new DIE(GV.getTag());
   // Add to map.
   insertDIE(N, VariableDIE);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=138006&r1=138005&r2=138006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Aug 18 18:17:55 2011
@@ -510,19 +510,6 @@
   return NewCU;
 }
 
-/// constructGlobalVariableDIE - Construct global variable DIE.
-void DwarfDebug::constructGlobalVariableDIE(CompileUnit *TheCU,
-                                            const MDNode *N) {
-  DIGlobalVariable GV(N);
-
-  // If debug information is malformed then ignore it.
-  if (GV.Verify() == false)
-    return;
-
-  TheCU->createGlobalVariableDIE(N);
-  return;
-}
-
 /// construct SubprogramDIE - Construct subprogram DIE.
 void DwarfDebug::constructSubprogramDIE(CompileUnit *TheCU, 
                                         const MDNode *N) {
@@ -561,7 +548,7 @@
     for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
       const MDNode *N = NMD->getOperand(i);
       if (CompileUnit *CU = CUMap.lookup(DIGlobalVariable(N).getCompileUnit()))
-        constructGlobalVariableDIE(CU, N);
+        CU->createGlobalVariableDIE(N);
     }
   
   if (NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.enum"))
@@ -607,7 +594,7 @@
          E = DbgFinder.global_variable_end(); I != E; ++I) {
     const MDNode *N = *I;
     if (CompileUnit *CU = CUMap.lookup(DIGlobalVariable(N).getCompileUnit()))
-      constructGlobalVariableDIE(CU, N);
+      CU->createGlobalVariableDIE(N);
   }
     
   // Create DIEs for each subprogram.
@@ -637,7 +624,7 @@
       CompileUnit *CU = constructCompileUnit(CUNode);
       DIArray GVs = CUNode.getGlobalVariables();
       for (unsigned i = 0, e = GVs.getNumElements(); i != e; ++i)
-        constructGlobalVariableDIE(CU, GVs.getElement(i));
+        CU->createGlobalVariableDIE(GVs.getElement(i));
       DIArray SPs = CUNode.getSubprograms();
       for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i)
         constructSubprogramDIE(CU, SPs.getElement(i));

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=138006&r1=138005&r2=138006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Aug 18 18:17:55 2011
@@ -417,9 +417,6 @@
   /// metadata node with tag DW_TAG_compile_unit.
   CompileUnit *constructCompileUnit(const MDNode *N);
 
-  /// constructGlobalVariableDIE - Construct global variable DIE.
-  void constructGlobalVariableDIE(CompileUnit *TheCU, const MDNode *N);
-
   /// construct SubprogramDIE - Construct subprogram DIE.
   void constructSubprogramDIE(CompileUnit *TheCU, const MDNode *N);
 



From ahatanak at gmail.com  Thu Aug 18 18:39:37 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Thu, 18 Aug 2011 23:39:37 -0000
Subject: [llvm-commits] [llvm] r138007 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/unalignedload.ll
Message-ID: <20110818233937.597122A6C12C@llvm.org>

Author: ahatanak
Date: Thu Aug 18 18:39:37 2011
New Revision: 138007

URL: http://llvm.org/viewvc/llvm-project?rev=138007&view=rev
Log:
Use subword loads instead of a 4-byte load when the size of a structure (or a
piece of it) that is being passed by value is smaller than a word.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/unalignedload.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=138007&r1=138006&r2=138007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Aug 18 18:39:37 2011
@@ -1805,43 +1805,90 @@
               SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
               MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
               const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
-              MVT PtrType) {
-  unsigned FirstWord = VA.getLocMemOffset() / 4;
-  unsigned NumWords = (Flags.getByValSize() + 3) / 4;
-  unsigned LastWord = FirstWord + NumWords;
-  unsigned CurWord;
+              MVT PtrType, bool isLittle) {
+  unsigned LocMemOffset = VA.getLocMemOffset();
+  unsigned Offset = 0;
+  uint32_t RemainingSize = Flags.getByValSize();
   unsigned ByValAlign = Flags.getByValAlign();
 
-  // copy the first 4 words of byval arg to registers A0 - A3
-  for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize);
-       ++CurWord) {
+  // Copy the first 4 words of byval arg to registers A0 - A3.
+  // FIXME: Use a stricter alignment if it enables better optimization in passes
+  //        run later.
+  for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
+       Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
     SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
-                                  DAG.getConstant((CurWord - FirstWord) * 4,
-                                                  MVT::i32));
+                                  DAG.getConstant(Offset, MVT::i32));
     SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
                                   MachinePointerInfo(),
                                   false, false, std::min(ByValAlign,
                                                          (unsigned )4));
     MemOpChains.push_back(LoadVal.getValue(1));
-    unsigned DstReg = O32IntRegs[CurWord];
+    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
     RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
   }
 
-  // copy remaining part of byval arg to stack.
-  if (CurWord < LastWord) {
-    unsigned SizeInBytes = (LastWord - CurWord) * 4;
-    SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
-                              DAG.getConstant((CurWord - FirstWord) * 4,
-                                              MVT::i32));
-    LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true);
-    SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
-    Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
-                          DAG.getConstant(SizeInBytes, MVT::i32),
-                          /*Align*/ByValAlign,
-                          /*isVolatile=*/false, /*AlwaysInline=*/false,
-                          MachinePointerInfo(0), MachinePointerInfo(0));
-    MemOpChains.push_back(Chain);
+  if (RemainingSize == 0)
+    return;
+
+  // If there still is a register available for argument passing, write the
+  // remaining part of the structure to it using subword loads and shifts.
+  if (LocMemOffset < 4 * 4) {
+    assert(RemainingSize <= 3 && RemainingSize >= 1 &&
+           "There must be one to three bytes remaining.");
+    unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
+    SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
+                                  DAG.getConstant(Offset, MVT::i32));
+    unsigned Alignment = std::min(ByValAlign, (unsigned )4);
+    SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
+                                     LoadPtr, MachinePointerInfo(),
+                                     MVT::getIntegerVT(LoadSize * 8), false,
+                                     false, Alignment);
+    MemOpChains.push_back(LoadVal.getValue(1));
+
+    // If target is big endian, shift it to the most significant half-word or
+    // byte.
+    if (!isLittle)
+      LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
+                            DAG.getConstant(32 - LoadSize * 8, MVT::i32));
+
+    Offset += LoadSize;
+    RemainingSize -= LoadSize;
+
+    // Read second subword if necessary.
+    if (RemainingSize != 0)  {
+      assert(RemainingSize == 1 && "There must be one byte remaining.");
+      LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 
+                            DAG.getConstant(Offset, MVT::i32));
+      unsigned Alignment = std::min(ByValAlign, (unsigned )2);
+      SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
+                                       LoadPtr, MachinePointerInfo(),
+                                       MVT::i8, false, false, Alignment);
+      MemOpChains.push_back(Subword.getValue(1));
+      // Insert the loaded byte to LoadVal.
+      // FIXME: Use INS if supported by target.
+      unsigned ShiftAmt = isLittle ? 16 : 8;
+      SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
+                                  DAG.getConstant(ShiftAmt, MVT::i32));
+      LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
+    }
+
+    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
+    RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
+    return;
   }
+
+  // Create a fixed object on stack at offset LocMemOffset and copy
+  // remaining part of byval arg to it using memcpy.
+  SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
+                            DAG.getConstant(Offset, MVT::i32));
+  LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
+  SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
+  Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
+                        DAG.getConstant(RemainingSize, MVT::i32),
+                        std::min(ByValAlign, (unsigned)4),
+                        /*isVolatile=*/false, /*AlwaysInline=*/false,
+                        MachinePointerInfo(0), MachinePointerInfo(0));
+  MemOpChains.push_back(Chain);
 }
 
 /// LowerCall - functions arguments are copied from virtual regs to
@@ -1974,7 +2021,7 @@
       assert(Flags.getByValSize() &&
              "ByVal args of size 0 should have been ignored by front-end.");
       WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg,
-                    VA, Flags, getPointerTy());
+                    VA, Flags, getPointerTy(), Subtarget->isLittle());
       continue;
     }
 

Modified: llvm/trunk/test/CodeGen/Mips/unalignedload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/unalignedload.ll?rev=138007&r1=138006&r2=138007&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/unalignedload.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/unalignedload.ll Thu Aug 18 18:39:37 2011
@@ -1,16 +1,41 @@
-; RUN: llc -march=mips < %s | FileCheck %s
-
+; RUN: llc  < %s -march=mipsel  | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc  < %s -march=mips    | FileCheck %s -check-prefix=CHECK-EB
 %struct.S2 = type { %struct.S1, %struct.S1 }
 %struct.S1 = type { i8, i8 }
+%struct.S4 = type { [7 x i8] }
 
 @s2 = common global %struct.S2 zeroinitializer, align 1
+ at s4 = common global %struct.S4 zeroinitializer, align 1
 
 define void @foo1() nounwind {
 entry:
-; CHECK: ulw  ${{[0-9]+}}, 2
+; CHECK-EL: lw  $25, %call16(foo2)
+; CHECK-EL: ulhu  $4, 2
+; CHECK-EL: lw  $[[R0:[0-9]+]], %got(s4)
+; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
+; CHECK-EL: ulhu  $[[R2:[0-9]+]], 4($[[R0]])
+; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16
+; CHECK-EL: ulw $4, 0($[[R0]])
+; CHECK-EL: lw  $25, %call16(foo4)
+; CHECK-EL: or  $5, $[[R2]], $[[R3]]
+
+; CHECK-EB: ulhu  $[[R0:[0-9]+]], 2
+; CHECK-EB: lw  $25, %call16(foo2)
+; CHECK-EB: sll $4, $[[R0]], 16
+; CHECK-EB: lw  $[[R1:[0-9]+]], %got(s4)
+; CHECK-EB: ulhu  $[[R2:[0-9]+]], 4($[[R1]])
+; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
+; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
+; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8
+; CHECK-EB: ulw $4, 0($[[R1]])
+; CHECK-EB: lw  $25, %call16(foo4)
+; CHECK-EB: or  $5, $[[R4]], $[[R5]]
 
   tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
+  tail call void @foo4(%struct.S4* byval @s4) nounwind
   ret void
 }
 
 declare void @foo2(%struct.S1* byval)
+
+declare void @foo4(%struct.S4* byval)



From isanbard at gmail.com  Thu Aug 18 18:42:37 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 18 Aug 2011 23:42:37 -0000
Subject: [llvm-commits] [llvm] r138008 -
	/llvm/trunk/lib/Transforms/Scalar/LICM.cpp
Message-ID: <20110818234237.1C3242A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 18:42:36 2011
New Revision: 138008

URL: http://llvm.org/viewvc/llvm-project?rev=138008&view=rev
Log:
Use 'getFirstInsertionPt' when trying to insert new instructions during LICM.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LICM.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=138008&r1=138007&r2=138008&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Thu Aug 18 18:42:36 2011
@@ -466,7 +466,7 @@
     } else {
       // Move the instruction to the start of the exit block, after any PHI
       // nodes in it.
-      I.moveBefore(ExitBlocks[0]->getFirstNonPHI());
+      I.moveBefore(ExitBlocks[0]->getFirstInsertionPt());
 
       // This instruction is no longer in the AST for the current loop, because
       // we just sunk it out of the loop.  If we just sunk it into an outer
@@ -509,7 +509,7 @@
       continue;
 
     // Insert the code after the last PHI node.
-    BasicBlock::iterator InsertPt = ExitBlock->getFirstNonPHI();
+    BasicBlock::iterator InsertPt = ExitBlock->getFirstInsertionPt();
 
     // If this is the first exit block processed, just move the original
     // instruction, otherwise clone the original instruction and insert
@@ -644,7 +644,7 @@
       for (unsigned i = 0, e = LoopExitBlocks.size(); i != e; ++i) {
         BasicBlock *ExitBlock = LoopExitBlocks[i];
         Value *LiveInValue = SSA.GetValueInMiddleOfBlock(ExitBlock);
-        Instruction *InsertPos = ExitBlock->getFirstNonPHI();
+        Instruction *InsertPos = ExitBlock->getFirstInsertionPt();
         StoreInst *NewSI = new StoreInst(LiveInValue, SomePtr, InsertPos);
         NewSI->setAlignment(Alignment);
         NewSI->setDebugLoc(DL);



From renato.golin at arm.com  Thu Aug 18 18:43:15 2011
From: renato.golin at arm.com (Renato Golin)
Date: Thu, 18 Aug 2011 23:43:15 -0000
Subject: [llvm-commits] [llvm] r138009 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
Message-ID: <20110818234315.144CC2A6C12C@llvm.org>

Author: rengolin
Date: Thu Aug 18 18:43:14 2011
New Revision: 138009

URL: http://llvm.org/viewvc/llvm-project?rev=138009&view=rev
Log:
add the comments of each declaration follow it, making it easier to read and compare to GCC's result.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=138009&r1=138008&r2=138009&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Thu Aug 18 18:43:14 2011
@@ -526,29 +526,26 @@
          I = CallSites.begin(), E = CallSites.end(); I != E; ++I, ++idx) {
       const CallSiteEntry &S = *I;
 
+      // Offset of the landing pad, counted in 16-byte bundles relative to the
+      // @LPStart address.
       if (VerboseAsm) {
-        // Emit comments that decode the call site.
         Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
                                     llvm::utostr(idx) + " <<");
         Asm->OutStreamer.AddComment(Twine("  On exception at call site ") +
                                     llvm::utostr(idx));
+      }
+      Asm->EmitULEB128(idx);
 
+      // Offset of the first associated action record, relative to the start of
+      // the action table. This value is biased by 1 (1 indicates the start of
+      // the action table), and 0 indicates that there are no actions.
+      if (VerboseAsm) {
         if (S.Action == 0)
           Asm->OutStreamer.AddComment("  Action: cleanup");
         else
           Asm->OutStreamer.AddComment(Twine("  Action: ") +
                                       llvm::utostr((S.Action - 1) / 2 + 1));
-
-        Asm->OutStreamer.AddBlankLine();
       }
-
-      // Offset of the landing pad, counted in 16-byte bundles relative to the
-      // @LPStart address.
-      Asm->EmitULEB128(idx);
-
-      // Offset of the first associated action record, relative to the start of
-      // the action table. This value is biased by 1 (1 indicates the start of
-      // the action table), and 0 indicates that there are no actions.
       Asm->EmitULEB128(S.Action);
     }
   } else {
@@ -594,46 +591,43 @@
       if (EndLabel == 0)
         EndLabel = Asm->GetTempSymbol("eh_func_end", Asm->getFunctionNumber());
 
-      if (VerboseAsm) {
-        // Emit comments that decode the call site.
-        Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
-                                    llvm::utostr(++Entry) + " <<");
-        Asm->OutStreamer.AddComment(Twine("  Call between ") +
-                                    BeginLabel->getName() + " and " +
-                                    EndLabel->getName());
-
-        if (!S.PadLabel) {
-          Asm->OutStreamer.AddComment("    has no landing pad");
-        } else {
-          Asm->OutStreamer.AddComment(Twine("    jumps to ") +
-                                      S.PadLabel->getName());
-
-          if (S.Action == 0)
-            Asm->OutStreamer.AddComment("  On action: cleanup");
-          else
-            Asm->OutStreamer.AddComment(Twine("  On action: ") +
-                                        llvm::utostr((S.Action - 1) / 2 + 1));
-        }
-
-        Asm->OutStreamer.AddBlankLine();
-      }
 
       // Offset of the call site relative to the previous call site, counted in
       // number of 16-byte bundles. The first call site is counted relative to
       // the start of the procedure fragment.
+      if (VerboseAsm)
+        Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
+                                    llvm::utostr(++Entry) + " <<");
       Asm->EmitLabelDifference(BeginLabel, EHFuncBeginSym, 4);
+      if (VerboseAsm)
+        Asm->OutStreamer.AddComment(Twine("  Call between ") +
+                                    BeginLabel->getName() + " and " +
+                                    EndLabel->getName());
       Asm->EmitLabelDifference(EndLabel, BeginLabel, 4);
 
       // Offset of the landing pad, counted in 16-byte bundles relative to the
       // @LPStart address.
-      if (!S.PadLabel)
+      if (!S.PadLabel) {
+        if (VerboseAsm)
+          Asm->OutStreamer.AddComment("    has no landing pad");
         Asm->OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
-      else
+      } else {
+        if (VerboseAsm)
+          Asm->OutStreamer.AddComment(Twine("    jumps to ") +
+                                      S.PadLabel->getName());
         Asm->EmitLabelDifference(S.PadLabel, EHFuncBeginSym, 4);
+      }
 
       // Offset of the first associated action record, relative to the start of
       // the action table. This value is biased by 1 (1 indicates the start of
       // the action table), and 0 indicates that there are no actions.
+      if (VerboseAsm) {
+        if (S.Action == 0)
+          Asm->OutStreamer.AddComment("  On action: cleanup");
+        else
+          Asm->OutStreamer.AddComment(Twine("  On action: ") +
+                                      llvm::utostr((S.Action - 1) / 2 + 1));
+      }
       Asm->EmitULEB128(S.Action);
     }
   }
@@ -648,13 +642,27 @@
       // Emit comments that decode the action table.
       Asm->OutStreamer.AddComment(Twine(">> Action Record ") +
                                   llvm::utostr(++Entry) + " <<");
+    }
+
+    // Type Filter
+    //
+    //   Used by the runtime to match the type of the thrown exception to the
+    //   type of the catch clauses or the types in the exception specification.
+    if (VerboseAsm) {
       if (Action.ValueForTypeID >= 0)
         Asm->OutStreamer.AddComment(Twine("  Catch TypeInfo ") +
                                     llvm::itostr(Action.ValueForTypeID));
       else 
         Asm->OutStreamer.AddComment(Twine("  Filter TypeInfo ") +
                                     llvm::itostr(Action.ValueForTypeID));
+    }
+    Asm->EmitSLEB128(Action.ValueForTypeID);
 
+    // Action Record
+    //
+    //   Self-relative signed displacement in bytes of the next action record,
+    //   or 0 if there is no next action record.
+    if (VerboseAsm) {
       if (Action.NextAction == 0) {
         Asm->OutStreamer.AddComment("  No further actions");
       } else {
@@ -662,20 +670,7 @@
         Asm->OutStreamer.AddComment(Twine("  Continue to action ") +
                                     llvm::utostr(NextAction));
       }
-
-      Asm->OutStreamer.AddBlankLine();
     }
-
-    // Type Filter
-    //
-    //   Used by the runtime to match the type of the thrown exception to the
-    //   type of the catch clauses or the types in the exception specification.
-    Asm->EmitSLEB128(Action.ValueForTypeID);
-
-    // Action Record
-    //
-    //   Self-relative signed displacement in bytes of the next action record,
-    //   or 0 if there is no next action record.
     Asm->EmitSLEB128(Action.NextAction);
   }
 



From dpatel at apple.com  Thu Aug 18 18:50:57 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 18 Aug 2011 23:50:57 -0000
Subject: [llvm-commits] [llvm] r138010 -
	/llvm/trunk/lib/Analysis/DIBuilder.cpp
Message-ID: <20110818235057.9B5442A6C12C@llvm.org>

Author: dpatel
Date: Thu Aug 18 18:50:57 2011
New Revision: 138010

URL: http://llvm.org/viewvc/llvm-project?rev=138010&view=rev
Log:
There is no need to add file as context for subroutine type. The subroutine type does not need any context.

Modified:
    llvm/trunk/lib/Analysis/DIBuilder.cpp

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=138010&r1=138009&r2=138010&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Thu Aug 18 18:50:57 2011
@@ -434,9 +434,9 @@
   // TAG_subroutine_type is encoded in DICompositeType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subroutine_type),
-    getNonCompileUnitScope(File),
+    llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
     MDString::get(VMContext, ""),
-    File,
+    llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
     ConstantInt::get(Type::getInt32Ty(VMContext), 0),
     ConstantInt::get(Type::getInt64Ty(VMContext), 0),
     ConstantInt::get(Type::getInt64Ty(VMContext), 0),



From bruno.cardoso at gmail.com  Thu Aug 18 18:59:21 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 18 Aug 2011 23:59:21 -0000
Subject: [llvm-commits] [llvm] r138012 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20110818235921.8CA902A6C12D@llvm.org>

Author: bruno
Date: Thu Aug 18 18:59:21 2011
New Revision: 138012

URL: http://llvm.org/viewvc/llvm-project?rev=138012&view=rev
Log:
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.

Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.

There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138012&r1=138011&r2=138012&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 18 18:59:21 2011
@@ -1840,23 +1840,17 @@
 }
 
 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
-multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
-                              SDNode OpNode, Intrinsic F32Int> {
+multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
   def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
                 !strconcat(OpcodeStr,
                            "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
-  def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
+  def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
                 !strconcat(OpcodeStr,
-                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                []>, XS, Requires<[HasAVX, OptForSize]>;
-  def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                !strconcat(OpcodeStr,
-                           "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
-                [(set VR128:$dst, (F32Int VR128:$src))]>;
-  def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
+                (ins ssmem:$src1, VR128:$src2),
                 !strconcat(OpcodeStr,
-                           "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
-                [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
 }
 
 /// sse1_fp_unop_p - SSE1 unops in packed form.
@@ -1921,21 +1915,17 @@
 }
 
 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
-multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
-                              SDNode OpNode, Intrinsic F64Int> {
+multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
   def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
                !strconcat(OpcodeStr,
                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
-  def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
-               (ins FR64:$src1, f64mem:$src2),
+  def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
+               !strconcat(OpcodeStr,
+                          "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
+               (ins VR128:$src1, sdmem:$src2),
                !strconcat(OpcodeStr,
                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
-  def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-           !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
-           [(set VR128:$dst, (F64Int VR128:$src))]>;
-  def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
-           !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
-           [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
 }
 
 /// sse2_fp_unop_p - SSE2 unops in vector forms.
@@ -1983,9 +1973,8 @@
 
 let Predicates = [HasAVX] in {
   // Square root.
-  defm VSQRT  : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
-                sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
-                VEX_4V;
+  defm VSQRT  : sse1_fp_unop_s_avx<0x51, "vsqrt">,
+                sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
 
   defm VSQRT  : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
                 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
@@ -1999,15 +1988,13 @@
 
   // Reciprocal approximations. Note that these typically require refinement
   // in order to obtain suitable precision.
-  defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
-                                   int_x86_sse_rsqrt_ss>, VEX_4V;
+  defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
   defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
                 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
                 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
                 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
 
-  defm VRCP   : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
-                                   VEX_4V;
+  defm VRCP   : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
   defm VRCP   : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
                 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
                 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
@@ -2016,15 +2003,61 @@
 
 def : Pat<(f32 (fsqrt FR32:$src)),
           (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
+def : Pat<(f32 (fsqrt (load addr:$src))),
+          (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
+          Requires<[HasAVX, OptForSize]>;
 def : Pat<(f64 (fsqrt FR64:$src)),
           (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
 def : Pat<(f64 (fsqrt (load addr:$src))),
           (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
           Requires<[HasAVX, OptForSize]>;
-def : Pat<(f32 (fsqrt (load addr:$src))),
-          (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
+
+def : Pat<(f32 (X86frsqrt FR32:$src)),
+          (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
+def : Pat<(f32 (X86frsqrt (load addr:$src))),
+          (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
           Requires<[HasAVX, OptForSize]>;
 
+def : Pat<(f32 (X86frcp FR32:$src)),
+          (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
+def : Pat<(f32 (X86frcp (load addr:$src))),
+          (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
+          Requires<[HasAVX, OptForSize]>;
+
+let Predicates = [HasAVX] in {
+def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
+          (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
+              (VSQRTSSr (f32 (IMPLICIT_DEF)),
+                        (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
+              sub_ss)>;
+def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
+          (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
+
+def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
+          (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
+              (VSQRTSDr (f64 (IMPLICIT_DEF)),
+                        (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
+              sub_sd)>;
+def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
+          (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
+
+def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
+          (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
+              (VRSQRTSSr (f32 (IMPLICIT_DEF)),
+                        (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
+              sub_ss)>;
+def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
+          (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
+
+def : Pat<(int_x86_sse_rcp_ss VR128:$src),
+          (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
+              (VRCPSSr (f32 (IMPLICIT_DEF)),
+                       (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
+              sub_ss)>;
+def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
+          (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
+}
+
 // Square root.
 defm SQRT  : sse1_fp_unop_s<0x51, "sqrt",  fsqrt, int_x86_sse_sqrt_ss>,
              sse1_fp_unop_p<0x51, "sqrt",  fsqrt>,



From isanbard at gmail.com  Thu Aug 18 19:05:40 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 19 Aug 2011 00:05:40 -0000
Subject: [llvm-commits] [llvm] r138014 - in /llvm/trunk:
 include/llvm/Transforms/Utils/BasicBlockUtils.h
 lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110819000540.D39452A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 19:05:40 2011
New Revision: 138014

URL: http://llvm.org/viewvc/llvm-project?rev=138014&view=rev
Log:
Add SplitLandingPadPredecessors().

SplitLandingPadPredecessors is similar to SplitBlockPredecessors in that it
splits the current block and attaches a set of predecessors to the new basic
block. However, it differs from SplitBlockPredecessors in that it's specifically
designed to handle landing pad blocks.

Two new basic blocks are created: one that is has the vector of predecessors as
its predecessors and one that has the remaining predecessors as its
predecessors. Those two new blocks then receive a cloned copy of the landingpad
instruction from the original block. The landingpad instructions are joined in a
PHI, etc. Like SplitBlockPredecessors, it updates the LLVM IR, AliasAnalysis,
DominatorTree, DominanceFrontier, LoopInfo, and LCCSA analyses.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h?rev=138014&r1=138013&r2=138014&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h Thu Aug 18 19:05:40 2011
@@ -174,6 +174,23 @@
                                    unsigned NumPreds, const char *Suffix,
                                    Pass *P = 0);
 
+/// SplitLandingPadPredecessors - This method transforms the landing pad,
+/// OrigBB, by introducing two new basic blocks into the function. One of those
+/// new basic blocks gets the predecessors listed in Preds. The other basic
+/// block gets the remaining predecessors of OrigBB. The landingpad instruction
+/// OrigBB is clone into both of the new basic blocks. The new blocks are given
+/// the suffixes 'Suffix1' and 'Suffix2', and are returned in the NewBBs vector.
+/// 
+/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
+/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses. In particular,
+/// it does not preserve LoopSimplify (because it's complicated to handle the
+/// case where one of the edges being split is an exit of a loop with other
+/// exits).
+/// 
+void SplitLandingPadPredecessors(BasicBlock *OrigBB,ArrayRef<BasicBlock*> Preds,
+                                 const char *Suffix, const char *Suffix2,
+                                 Pass *P, SmallVectorImpl<BasicBlock*> &NewBBs);
+
 /// FoldReturnIntoUncondBranch - This method duplicates the specified return
 /// instruction into a predecessor which ends in an unconditional branch. If
 /// the return instruction returns a value defined by a PHI, propagate the

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=138014&r1=138013&r2=138014&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Aug 18 19:05:40 2011
@@ -323,16 +323,17 @@
 
   LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>();
   Loop *L = LI ? LI->getLoopFor(OldBB) : 0;
-  bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
 
   // If we need to preserve loop analyses, collect some information about how
   // this split will affect loops.
   bool IsLoopEntry = !!L;
   bool SplitMakesNewLoopHeader = false;
   if (LI) {
+    bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
     for (ArrayRef<BasicBlock*>::iterator
            i = Preds.begin(), e = Preds.end(); i != e; ++i) {
       BasicBlock *Pred = *i;
+
       // If we need to preserve LCSSA, determine if any of the preds is a loop
       // exit.
       if (PreserveLCSSA)
@@ -493,6 +494,99 @@
   return NewBB;
 }
 
+/// SplitLandingPadPredecessors - This method transforms the landing pad,
+/// OrigBB, by introducing two new basic blocks into the function. One of those
+/// new basic blocks gets the predecessors listed in Preds. The other basic
+/// block gets the remaining predecessors of OrigBB. The landingpad instruction
+/// OrigBB is clone into both of the new basic blocks. The new blocks are given
+/// the suffixes 'Suffix1' and 'Suffix2', and are returned in the NewBBs vector.
+/// 
+/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
+/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses. In particular,
+/// it does not preserve LoopSimplify (because it's complicated to handle the
+/// case where one of the edges being split is an exit of a loop with other
+/// exits).
+/// 
+void llvm::SplitLandingPadPredecessors(BasicBlock *OrigBB,
+                                       ArrayRef<BasicBlock*> Preds,
+                                       const char *Suffix1, const char *Suffix2,
+                                       Pass *P,
+                                       SmallVectorImpl<BasicBlock*> &NewBBs) {
+  assert(OrigBB->isLandingPad() && "Trying to split a non-landing pad!");
+
+  // Create a new basic block for OrigBB's predecessors listed in Preds. Insert
+  // it right before the original block.
+  BasicBlock *NewBB1 = BasicBlock::Create(OrigBB->getContext(),
+                                          OrigBB->getName() + Suffix1,
+                                          OrigBB->getParent(), OrigBB);
+  NewBBs.push_back(NewBB1);
+
+  // The new block unconditionally branches to the old block.
+  BranchInst *BI1 = BranchInst::Create(OrigBB, NewBB1);
+
+  // Move the edges from Preds to point to NewBB1 instead of OrigBB.
+  for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
+    // This is slightly more strict than necessary; the minimum requirement
+    // is that there be no more than one indirectbr branching to BB. And
+    // all BlockAddress uses would need to be updated.
+    assert(!isa<IndirectBrInst>(Preds[i]->getTerminator()) &&
+           "Cannot split an edge from an IndirectBrInst");
+    Preds[i]->getTerminator()->replaceUsesOfWith(OrigBB, NewBB1);
+  }
+
+  // Update DominatorTree, LoopInfo, and LCCSA analysis information.
+  bool HasLoopExit = false;
+  UpdateAnalysisInformation(OrigBB, NewBB1, Preds, P, HasLoopExit);
+
+  // Update the PHI nodes in OrigBB with the values coming from NewBB1.
+  UpdatePHINodes(OrigBB, NewBB1, Preds, BI1, P, HasLoopExit);
+
+  // Create another basic block for the rest of OrigBB's predecessors.
+  BasicBlock *NewBB2 = BasicBlock::Create(OrigBB->getContext(),
+                                          OrigBB->getName() + Suffix2,
+                                          OrigBB->getParent(), OrigBB);
+  NewBBs.push_back(NewBB2);
+
+  // The new block unconditionally branches to the old block.
+  BranchInst *BI2 = BranchInst::Create(OrigBB, NewBB2);
+
+  // Move the remaining edges from OrigBB to point to NewBB2.
+  SmallVector<BasicBlock*, 8> NewBB2Preds;
+  for (pred_iterator i = pred_begin(OrigBB), e = pred_end(OrigBB);
+       i != e; ) {
+    BasicBlock *Pred = *i++;
+    if (Pred == NewBB1 || Pred == NewBB2 ) continue;
+    assert(!isa<IndirectBrInst>(Pred->getTerminator()) &&
+           "Cannot split an edge from an IndirectBrInst");
+    Pred->getTerminator()->replaceUsesOfWith(OrigBB, NewBB2);
+    NewBB2Preds.push_back(Pred);
+    e = pred_end(OrigBB);
+  }
+
+  // Update DominatorTree, LoopInfo, and LCCSA analysis information.
+  HasLoopExit = false;
+  UpdateAnalysisInformation(OrigBB, NewBB2, NewBB2Preds, P, HasLoopExit);
+
+  // Update the PHI nodes in OrigBB with the values coming from NewBB2.
+  UpdatePHINodes(OrigBB, NewBB2, NewBB2Preds, BI2, P, HasLoopExit);
+
+  LandingPadInst *LPad = OrigBB->getLandingPadInst();
+  Instruction *Clone1 = LPad->clone();
+  Clone1->setName(Twine("lpad") + Suffix1);
+  NewBB1->getInstList().insert(NewBB1->getFirstInsertionPt(), Clone1);
+
+  Instruction *Clone2 = LPad->clone();
+  Clone2->setName(Twine("lpad") + Suffix2);
+  NewBB2->getInstList().insert(NewBB2->getFirstInsertionPt(), Clone2);
+
+  // Create a PHI node for the two cloned landingpad instructions.
+  PHINode *PN = PHINode::Create(LPad->getType(), 2, "lpad.phi", LPad);
+  PN->addIncoming(Clone1, NewBB1);
+  PN->addIncoming(Clone2, NewBB2);
+  LPad->replaceAllUsesWith(PN);
+  LPad->eraseFromParent();
+}
+
 /// FindFunctionBackedges - Analyze the specified function to find all of the
 /// loop backedges in the function and return them.  This is a relatively cheap
 /// (compared to computing dominators and loop info) analysis.



From isanbard at gmail.com  Thu Aug 18 19:09:22 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 19 Aug 2011 00:09:22 -0000
Subject: [llvm-commits] [llvm] r138015 -
	/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
Message-ID: <20110819000922.341652A6C12C@llvm.org>

Author: void
Date: Thu Aug 18 19:09:22 2011
New Revision: 138015

URL: http://llvm.org/viewvc/llvm-project?rev=138015&view=rev
Log:
Intelligently split the landing pad block.

We have to be careful when splitting the landing pad block, because the
landingpad instruction is required to remain as the first non-PHI of an invoke's
unwind edge. To retain this, we split the block into two blocks, moving the
predecessors within the loop to one block and the remaining predecessors to the
other. The landingpad instruction is cloned into the new blocks.

Modified:
    llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=138015&r1=138014&r2=138015&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Thu Aug 18 19:09:22 2011
@@ -410,13 +410,24 @@
   }
 
   assert(!LoopBlocks.empty() && "No edges coming in from outside the loop?");
-  BasicBlock *NewBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
-                                             LoopBlocks.size(), ".loopexit",
-                                             this);
+  BasicBlock *NewExitBB = 0;
+
+  if (Exit->isLandingPad()) {
+    SmallVector<BasicBlock*, 2> NewBBs;
+    SplitLandingPadPredecessors(Exit, ArrayRef<BasicBlock*>(&LoopBlocks[0],
+                                                            LoopBlocks.size()),
+                                ".loopexit", ".nonloopexit",
+                                this, NewBBs);
+    NewExitBB = NewBBs[0];
+  } else {
+    NewExitBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
+                                       LoopBlocks.size(), ".loopexit",
+                                       this);
+  }
 
   DEBUG(dbgs() << "LoopSimplify: Creating dedicated exit block "
-               << NewBB->getName() << "\n");
-  return NewBB;
+               << NewExitBB->getName() << "\n");
+  return NewExitBB;
 }
 
 /// AddBlockAndPredsToSet - Add the specified block, and all of its



From gohman at apple.com  Thu Aug 18 19:26:36 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 19 Aug 2011 00:26:36 -0000
Subject: [llvm-commits] [llvm] r138016 - in /llvm/trunk:
 lib/Transforms/Scalar/ObjCARC.cpp test/Transforms/ObjCARC/basic.ll
Message-ID: <20110819002636.E3D082A6C12C@llvm.org>

Author: djg
Date: Thu Aug 18 19:26:36 2011
New Revision: 138016

URL: http://llvm.org/viewvc/llvm-project?rev=138016&view=rev
Log:
Track a retain+release nesting level independently of the
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
    llvm/trunk/test/Transforms/ObjCARC/basic.ll

Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=138016&r1=138015&r2=138016&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Thu Aug 18 19:26:36 2011
@@ -877,7 +877,9 @@
 // usually can't sink them past other calls, which would be the main
 // case where it would be useful.
 
-/// TODO: The pointer returned from objc_loadWeakRetained is retained.
+// TODO: The pointer returned from objc_loadWeakRetained is retained.
+
+// TODO: Delete release+retain pairs (rare).
 
 #include "llvm/GlobalAlias.h"
 #include "llvm/Constants.h"
@@ -1124,13 +1126,19 @@
   /// retain-decrement-use-release sequence or release-use-decrement-retain
   /// reverese sequence.
   struct RRInfo {
-    /// KnownIncremented - After an objc_retain, the reference count of the
-    /// referenced object is known to be positive. Similarly, before an
-    /// objc_release, the reference count of the referenced object is known to
-    /// be positive. If there are retain-release pairs in code regions where the
-    /// retain count is known to be positive, they can be eliminated, regardless
-    /// of any side effects between them.
-    bool KnownIncremented;
+    /// KnownSafe - After an objc_retain, the reference count of the referenced
+    /// object is known to be positive. Similarly, before an objc_release, the
+    /// reference count of the referenced object is known to be positive. If
+    /// there are retain-release pairs in code regions where the retain count
+    /// is known to be positive, they can be eliminated, regardless of any side
+    /// effects between them.
+    ///
+    /// Also, a retain+release pair nested within another retain+release
+    /// pair all on the known same pointer value can be eliminated, regardless
+    /// of any intervening side effects.
+    ///
+    /// KnownSafe is true when either of these conditions is satisfied.
+    bool KnownSafe;
 
     /// IsRetainBlock - True if the Calls are objc_retainBlock calls (as
     /// opposed to objc_retain calls).
@@ -1153,7 +1161,7 @@
     SmallPtrSet<Instruction *, 2> ReverseInsertPts;
 
     RRInfo() :
-      KnownIncremented(false), IsRetainBlock(false), IsTailCallRelease(false),
+      KnownSafe(false), IsRetainBlock(false), IsTailCallRelease(false),
       ReleaseMetadata(0) {}
 
     void clear();
@@ -1161,7 +1169,7 @@
 }
 
 void RRInfo::clear() {
-  KnownIncremented = false;
+  KnownSafe = false;
   IsRetainBlock = false;
   IsTailCallRelease = false;
   ReleaseMetadata = 0;
@@ -1176,6 +1184,9 @@
     /// RefCount - The known minimum number of reference count increments.
     unsigned RefCount;
 
+    /// NestCount - The known minimum level of retain+release nesting.
+    unsigned NestCount;
+
     /// Seq - The current position in the sequence.
     Sequence Seq;
 
@@ -1184,7 +1195,7 @@
     /// TODO: Encapsulate this better.
     RRInfo RRI;
 
-    PtrState() : RefCount(0), Seq(S_None) {}
+    PtrState() : RefCount(0), NestCount(0), Seq(S_None) {}
 
     void SetAtLeastOneRefCount()  {
       if (RefCount == 0) RefCount = 1;
@@ -1202,6 +1213,18 @@
       return RefCount > 0;
     }
 
+    void IncrementNestCount() {
+      if (NestCount != UINT_MAX) ++NestCount;
+    }
+
+    void DecrementNestCount() {
+      if (NestCount != 0) --NestCount;
+    }
+
+    bool IsKnownNested() const {
+      return NestCount > 0;
+    }
+
     void SetSeq(Sequence NewSeq) {
       Seq = NewSeq;
     }
@@ -1233,6 +1256,7 @@
 PtrState::Merge(const PtrState &Other, bool TopDown) {
   Seq = MergeSeqs(Seq, Other.Seq, TopDown);
   RefCount = std::min(RefCount, Other.RefCount);
+  NestCount = std::min(NestCount, Other.NestCount);
 
   // We can't merge a plain objc_retain with an objc_retainBlock.
   if (RRI.IsRetainBlock != Other.RRI.IsRetainBlock)
@@ -1245,7 +1269,7 @@
     if (RRI.ReleaseMetadata != Other.RRI.ReleaseMetadata)
       RRI.ReleaseMetadata = 0;
 
-    RRI.KnownIncremented = RRI.KnownIncremented && Other.RRI.KnownIncremented;
+    RRI.KnownSafe = RRI.KnownSafe && Other.RRI.KnownSafe;
     RRI.IsTailCallRelease = RRI.IsTailCallRelease && Other.RRI.IsTailCallRelease;
     RRI.Calls.insert(Other.RRI.Calls.begin(), Other.RRI.Calls.end());
     RRI.ReverseInsertPts.insert(Other.RRI.ReverseInsertPts.begin(),
@@ -2166,7 +2190,7 @@
         switch (SuccS.GetSeq()) {
         case S_None:
         case S_CanRelease: {
-          if (!S.RRI.KnownIncremented && !SuccS.RRI.KnownIncremented)
+          if (!S.RRI.KnownSafe && !SuccS.RRI.KnownSafe)
             S.ClearSequenceProgress();
           continue;
         }
@@ -2176,7 +2200,7 @@
         case S_Stop:
         case S_Release:
         case S_MovableRelease:
-          if (!S.RRI.KnownIncremented && !SuccS.RRI.KnownIncremented)
+          if (!S.RRI.KnownSafe && !SuccS.RRI.KnownSafe)
             AllSuccsHaveSame = false;
           break;
         case S_Retain:
@@ -2199,7 +2223,7 @@
         PtrState &SuccS = BBStates[*SI].getPtrBottomUpState(Arg);
         switch (SuccS.GetSeq()) {
         case S_None: {
-          if (!S.RRI.KnownIncremented && !SuccS.RRI.KnownIncremented)
+          if (!S.RRI.KnownSafe && !SuccS.RRI.KnownSafe)
             S.ClearSequenceProgress();
           continue;
         }
@@ -2210,7 +2234,7 @@
         case S_Release:
         case S_MovableRelease:
         case S_Use:
-          if (!S.RRI.KnownIncremented && !SuccS.RRI.KnownIncremented)
+          if (!S.RRI.KnownSafe && !SuccS.RRI.KnownSafe)
             AllSuccsHaveSame = false;
           break;
         case S_Retain:
@@ -2285,11 +2309,12 @@
 
       S.SetSeqToRelease(Inst->getMetadata(ImpreciseReleaseMDKind));
       S.RRI.clear();
-      S.RRI.KnownIncremented = S.IsKnownIncremented();
+      S.RRI.KnownSafe = S.IsKnownNested() || S.IsKnownIncremented();
       S.RRI.IsTailCallRelease = cast<CallInst>(Inst)->isTailCall();
       S.RRI.Calls.insert(Inst);
 
       S.IncrementRefCount();
+      S.IncrementNestCount();
       break;
     }
     case IC_RetainBlock:
@@ -2300,6 +2325,7 @@
       PtrState &S = MyStates.getPtrBottomUpState(Arg);
       S.DecrementRefCount();
       S.SetAtLeastOneRefCount();
+      S.DecrementNestCount();
 
       switch (S.GetSeq()) {
       case S_Stop:
@@ -2322,7 +2348,7 @@
       case S_Retain:
         llvm_unreachable("bottom-up pointer in retain state!");
       }
-      break;
+      continue;
     }
     case IC_AutoreleasepoolPop:
       // Conservatively, clear MyStates for all known pointers.
@@ -2346,11 +2372,9 @@
       PtrState &S = MI->second;
       Sequence Seq = S.GetSeq();
 
-      // Check for possible releases. Note that we don't have to update
-      // S's RefCount because any reference count modifications would be
-      // done through a different provenance.
-      if (!IsRetain(Class) && Class != IC_RetainBlock &&
-          CanAlterRefCount(Inst, Ptr, PA, Class))
+      // Check for possible releases.
+      if (CanAlterRefCount(Inst, Ptr, PA, Class)) {
+        S.DecrementRefCount();
         switch (Seq) {
         case S_Use:
           S.SetSeq(S_CanRelease);
@@ -2364,6 +2388,7 @@
         case S_Retain:
           llvm_unreachable("bottom-up pointer in retain state!");
         }
+      }
 
       // Check for possible direct uses.
       switch (Seq) {
@@ -2464,19 +2489,23 @@
         S.SetSeq(S_Retain);
         S.RRI.clear();
         S.RRI.IsRetainBlock = Class == IC_RetainBlock;
-        S.RRI.KnownIncremented = S.IsKnownIncremented();
+        // Don't check S.IsKnownIncremented() here because it's not
+        // sufficient.
+        S.RRI.KnownSafe = S.IsKnownNested();
         S.RRI.Calls.insert(Inst);
       }
 
       S.SetAtLeastOneRefCount();
       S.IncrementRefCount();
-      break;
+      S.IncrementNestCount();
+      continue;
     }
     case IC_Release: {
       Arg = GetObjCArg(Inst);
 
       PtrState &S = MyStates.getPtrTopDownState(Arg);
       S.DecrementRefCount();
+      S.DecrementNestCount();
 
       switch (S.GetSeq()) {
       case S_Retain:
@@ -2520,11 +2549,9 @@
       PtrState &S = MI->second;
       Sequence Seq = S.GetSeq();
 
-      // Check for possible releases. Note that we don't have to update
-      // S's RefCount because any reference count modifications would be
-      // done through a different provenance.
-      if (!IsRetain(Class) && Class != IC_RetainBlock &&
-          CanAlterRefCount(Inst, Ptr, PA, Class))
+      // Check for possible releases.
+      if (CanAlterRefCount(Inst, Ptr, PA, Class)) {
+        S.DecrementRefCount();
         switch (Seq) {
         case S_Retain:
           S.SetSeq(S_CanRelease);
@@ -2544,6 +2571,7 @@
         case S_MovableRelease:
           llvm_unreachable("top-down pointer in release state!");
         }
+      }
 
       // Check for possible direct uses.
       switch (Seq) {
@@ -2718,7 +2746,7 @@
 
     // If a pair happens in a region where it is known that the reference count
     // is already incremented, we can similarly ignore possible decrements.
-    bool KnownIncrementedTD = true, KnownIncrementedBU = true;
+    bool KnownSafeTD = true, KnownSafeBU = true;
 
     // Connect the dots between the top-down-collected RetainsToMove and
     // bottom-up-collected ReleasesToMove to form sets of related calls.
@@ -2738,7 +2766,7 @@
         MapVector<Value *, RRInfo>::const_iterator It = Retains.find(NewRetain);
         assert(It != Retains.end());
         const RRInfo &NewRetainRRI = It->second;
-        KnownIncrementedTD &= NewRetainRRI.KnownIncremented;
+        KnownSafeTD &= NewRetainRRI.KnownSafe;
         for (SmallPtrSet<Instruction *, 2>::const_iterator
              LI = NewRetainRRI.Calls.begin(),
              LE = NewRetainRRI.Calls.end(); LI != LE; ++LI) {
@@ -2794,7 +2822,7 @@
           Releases.find(NewRelease);
         assert(It != Releases.end());
         const RRInfo &NewReleaseRRI = It->second;
-        KnownIncrementedBU &= NewReleaseRRI.KnownIncremented;
+        KnownSafeBU &= NewReleaseRRI.KnownSafe;
         for (SmallPtrSet<Instruction *, 2>::const_iterator
              LI = NewReleaseRRI.Calls.begin(),
              LE = NewReleaseRRI.Calls.end(); LI != LE; ++LI) {
@@ -2842,9 +2870,9 @@
       if (NewRetains.empty()) break;
     }
 
-    // If the pointer is known incremented, we can safely delete the pair
-    // regardless of what's between them.
-    if (KnownIncrementedTD || KnownIncrementedBU) {
+    // If the pointer is known incremented or nested, we can safely delete the
+    // pair regardless of what's between them.
+    if (KnownSafeTD || KnownSafeBU) {
       RetainsToMove.ReverseInsertPts.clear();
       ReleasesToMove.ReverseInsertPts.clear();
       NewCount = 0;

Modified: llvm/trunk/test/Transforms/ObjCARC/basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/basic.ll?rev=138016&r1=138015&r2=138016&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/ObjCARC/basic.ll (original)
+++ llvm/trunk/test/Transforms/ObjCARC/basic.ll Thu Aug 18 19:26:36 2011
@@ -1569,6 +1569,74 @@
   ret void
 }
 
+; When there are adjacent retain+release pairs, the first one is
+; known unnecessary because the presence of the second one means that
+; the first one won't be deleting the object.
+
+; CHECK:      define void @test57(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %x) nounwind
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @objc_release(i8* %x) nounwind
+; CHECK-NEXT:   ret void
+; CHECK-NEXT: }
+define void @test57(i8* %x) nounwind {
+entry:
+  call i8* @objc_retain(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
+  call i8* @objc_retain(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
+  ret void
+}
+
+; An adjacent retain+release pair is sufficient even if it will be
+; removed itself.
+
+; CHECK:      define void @test58(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   ret void
+; CHECK-NEXT: }
+define void @test58(i8* %x) nounwind {
+entry:
+  call i8* @objc_retain(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
+  call i8* @objc_retain(i8* %x) nounwind
+  call void @objc_release(i8* %x) nounwind
+  ret void
+}
+
+; Don't delete the second retain+release pair in an adjacent set.
+
+; CHECK:      define void @test59(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %x) nounwind
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @use_pointer(i8* %x)
+; CHECK-NEXT:   call void @objc_release(i8* %x) nounwind
+; CHECK-NEXT:   ret void
+; CHECK-NEXT: }
+define void @test59(i8* %x) nounwind {
+entry:
+  %a = call i8* @objc_retain(i8* %x) nounwind
+  call void @objc_release(i8* %x) nounwind
+  %b = call i8* @objc_retain(i8* %x) nounwind
+  call void @use_pointer(i8* %x)
+  call void @use_pointer(i8* %x)
+  call void @objc_release(i8* %x) nounwind
+  ret void
+}
+
 declare void @bar(i32 ()*)
 
 ; A few real-world testcases.



From stoklund at 2pi.dk  Thu Aug 18 19:30:17 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 00:30:17 -0000
Subject: [llvm-commits] [llvm] r138018 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
Message-ID: <20110819003017.AB8AE2A6C12D@llvm.org>

Author: stoklund
Date: Thu Aug 18 19:30:17 2011
New Revision: 138018

URL: http://llvm.org/viewvc/llvm-project?rev=138018&view=rev
Log:
Don't treat a partial <def,undef> operand as a read.

Normally, a partial register def is treated as reading the
super-register unless it also defines the full register like this:

  %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def>

This patch also uses the <undef> flag on partial defs to recognize
non-reading operands:

  %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit

This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses
would treat a coalesced copy as still reading the register, extending
the live range artificially.

My test case only works when I disable DCE so a dead copy is left for
RegisterCoalescer, so I am not including it.

<rdar://problem/9967101>

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=138018&r1=138017&r2=138018&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Aug 18 19:30:17 2011
@@ -901,7 +901,8 @@
       Ops->push_back(i);
     if (MO.isUse())
       Use |= !MO.isUndef();
-    else if (MO.getSubReg())
+    else if (MO.getSubReg() && !MO.isUndef())
+      // A partial <def,undef> doesn't count as reading the register.
       PartDef = true;
     else
       FullDef = true;



From eli.friedman at gmail.com  Thu Aug 18 19:50:28 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 18 Aug 2011 17:50:28 -0700
Subject: [llvm-commits] [PATCH] Atomic load/store support in CodeGen
Message-ID: <CAJdarcHPZz6+m59HYjKvTeY+xRZeFB4nSO8zyvuO-+G++JOzNw@mail.gmail.com>

Attached.  Any review comments or more general thoughts appreciated.
Also, any comments on legalization for atomics would be appreciated;
it's kind of messy at the moment...

-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp	(revision 137997)
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp	(working copy)
@@ -432,7 +432,9 @@
   case ISD::ATOMIC_LOAD_MIN:
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX: {
+  case ISD::ATOMIC_LOAD_UMAX:
+  case ISD::ATOMIC_LOAD:
+  case ISD::ATOMIC_STORE: {
     const AtomicSDNode *AT = cast<AtomicSDNode>(N);
     ID.AddInteger(AT->getMemoryVT().getRawBits());
     ID.AddInteger(AT->getRawSubclassData());
@@ -3904,12 +3906,14 @@
           Opcode == ISD::ATOMIC_LOAD_MAX ||
           Opcode == ISD::ATOMIC_LOAD_UMIN ||
           Opcode == ISD::ATOMIC_LOAD_UMAX ||
-          Opcode == ISD::ATOMIC_SWAP) &&
+          Opcode == ISD::ATOMIC_SWAP ||
+          Opcode == ISD::ATOMIC_STORE) &&
          "Invalid Atomic Op");
 
   EVT VT = Val.getValueType();
 
-  SDVTList VTs = getVTList(VT, MVT::Other);
+  SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
+                                               getVTList(VT, MVT::Other);
   FoldingSetNodeID ID;
   ID.AddInteger(MemVT.getRawBits());
   SDValue Ops[] = {Chain, Ptr, Val};
@@ -3927,6 +3931,55 @@
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
+                                EVT VT, SDValue Chain,
+                                SDValue Ptr,
+                                const Value* PtrVal,
+                                unsigned Alignment,
+                                AtomicOrdering Ordering,
+                                SynchronizationScope SynchScope) {
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getEVTAlignment(MemVT);
+
+  MachineFunction &MF = getMachineFunction();
+  unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
+
+  // For now, atomics are considered to be volatile always.
+  Flags |= MachineMemOperand::MOVolatile;
+
+  MachineMemOperand *MMO =
+    MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
+                            MemVT.getStoreSize(), Alignment);
+
+  return getAtomic(Opcode, dl, MemVT, VT, Chain, Ptr, MMO,
+                   Ordering, SynchScope);
+}
+
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
+                                EVT VT, SDValue Chain,
+                                SDValue Ptr,
+                                MachineMemOperand *MMO,
+                                AtomicOrdering Ordering,
+                                SynchronizationScope SynchScope) {
+  assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
+
+  SDVTList VTs = getVTList(VT, MVT::Other);
+  FoldingSetNodeID ID;
+  ID.AddInteger(MemVT.getRawBits());
+  SDValue Ops[] = {Chain, Ptr};
+  AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
+  void* IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+    cast<AtomicSDNode>(E)->refineAlignment(MMO);
+    return SDValue(E, 0);
+  }
+  SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain,
+                                               Ptr, MMO, Ordering, SynchScope);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
                                      DebugLoc dl) {
@@ -5795,6 +5848,8 @@
   case ISD::ATOMIC_LOAD_MAX:    return "AtomicLoadMax";
   case ISD::ATOMIC_LOAD_UMIN:   return "AtomicLoadUMin";
   case ISD::ATOMIC_LOAD_UMAX:   return "AtomicLoadUMax";
+  case ISD::ATOMIC_LOAD:        return "AtomicLoad";
+  case ISD::ATOMIC_STORE:       return "AtomicStore";
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
   case ISD::SRCVALUE:      return "SrcValue";
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	(revision 137997)
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	(working copy)
@@ -3149,6 +3149,9 @@
 }
 
 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
+  if (I.isAtomic())
+    return visitAtomicLoad(I);
+
   const Value *SV = I.getOperand(0);
   SDValue Ptr = getValue(SV);
 
@@ -3226,6 +3229,9 @@
 }
 
 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
+  if (I.isAtomic())
+    return visitAtomicStore(I);
+
   const Value *SrcV = I.getOperand(0);
   const Value *PtrV = I.getOperand(1);
 
@@ -3277,6 +3283,7 @@
 }
 
 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
+                                    SynchronizationScope Scope,
                                     bool Before, DebugLoc dl,
                                     SelectionDAG &DAG,
                                     const TargetLowering &TLI) {
@@ -3294,19 +3301,21 @@
   }
   SDValue Ops[3];
   Ops[0] = Chain;
-  Ops[1] = DAG.getConstant(SequentiallyConsistent, TLI.getPointerTy());
-  Ops[2] = DAG.getConstant(Order, TLI.getPointerTy());
+  Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
+  Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
   return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
 }
 
 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
   DebugLoc dl = getCurDebugLoc();
   AtomicOrdering Order = I.getOrdering();
+  SynchronizationScope Scope = I.getSynchScope();
 
   SDValue InChain = getRoot();
 
   if (TLI.getInsertFencesForAtomic())
-    InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI);
+    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
+                                   DAG, TLI);
 
   SDValue L =
     DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
@@ -3316,12 +3325,14 @@
                   getValue(I.getCompareOperand()),
                   getValue(I.getNewValOperand()),
                   MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
-                  I.getOrdering(), I.getSynchScope());
+                  TLI.getInsertFencesForAtomic() ? Monotonic : Order,
+                  Scope);
 
   SDValue OutChain = L.getValue(1);
 
   if (TLI.getInsertFencesForAtomic())
-    OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI);
+    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
+                                    DAG, TLI);
 
   setValue(&I, L);
   DAG.setRoot(OutChain);
@@ -3345,11 +3356,13 @@
   case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
   }
   AtomicOrdering Order = I.getOrdering();
+  SynchronizationScope Scope = I.getSynchScope();
 
   SDValue InChain = getRoot();
 
   if (TLI.getInsertFencesForAtomic())
-    InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI);
+    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
+                                   DAG, TLI);
 
   SDValue L =
     DAG.getAtomic(NT, dl,
@@ -3359,12 +3372,13 @@
                   getValue(I.getValOperand()),
                   I.getPointerOperand(), 0 /* Alignment */,
                   TLI.getInsertFencesForAtomic() ? Monotonic : Order,
-                  I.getSynchScope());
+                  Scope);
 
   SDValue OutChain = L.getValue(1);
 
   if (TLI.getInsertFencesForAtomic())
-    OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI);
+    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
+                                    DAG, TLI);
 
   setValue(&I, L);
   DAG.setRoot(OutChain);
@@ -3379,6 +3393,65 @@
   DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
 }
 
+void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
+  DebugLoc dl = getCurDebugLoc();
+  AtomicOrdering Order = I.getOrdering();
+  SynchronizationScope Scope = I.getSynchScope();
+
+  SDValue InChain = getRoot();
+
+  if (TLI.getInsertFencesForAtomic())
+    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
+                                   DAG, TLI);
+
+  EVT VT = EVT::getEVT(I.getType());
+
+  SDValue L =
+    DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
+                  getValue(I.getPointerOperand()),
+                  I.getPointerOperand(), I.getAlignment(),
+                  TLI.getInsertFencesForAtomic() ? Monotonic : Order,
+                  Scope);
+
+  SDValue OutChain = L.getValue(1);
+
+  if (TLI.getInsertFencesForAtomic())
+    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
+                                    DAG, TLI);
+
+  setValue(&I, L);
+  DAG.setRoot(OutChain);
+}
+
+void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
+  DebugLoc dl = getCurDebugLoc();
+
+  AtomicOrdering Order = I.getOrdering();
+  SynchronizationScope Scope = I.getSynchScope();
+
+  SDValue InChain = getRoot();
+
+  if (TLI.getInsertFencesForAtomic())
+    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
+                                   DAG, TLI);
+
+  SDValue OutChain =
+    DAG.getAtomic(ISD::ATOMIC_STORE, dl,
+                  getValue(I.getValueOperand()).getValueType().getSimpleVT(),
+                  InChain,
+                  getValue(I.getPointerOperand()),
+                  getValue(I.getValueOperand()),
+                  I.getPointerOperand(), I.getAlignment(),
+                  TLI.getInsertFencesForAtomic() ? Monotonic : Order,
+                  Scope);
+
+  if (TLI.getInsertFencesForAtomic())
+    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
+                                    DAG, TLI);
+
+  DAG.setRoot(OutChain);
+}
+
 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
 /// node.
 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	(revision 137997)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	(working copy)
@@ -819,6 +819,11 @@
     Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
     break;
   }
+  case ISD::ATOMIC_STORE: {
+    EVT MemType = cast<AtomicSDNode>(Node)->getMemoryVT();
+    Action = TLI.getOperationAction(Node->getOpcode(), MemType);
+    break;
+  }
   case ISD::SELECT_CC:
   case ISD::SETCC:
   case ISD::BR_CC: {
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h	(revision 137997)
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h	(working copy)
@@ -526,7 +526,9 @@
   void visitPHI(const PHINode &I);
   void visitCall(const CallInst &I);
   bool visitMemCmpCall(const CallInst &I);
-  
+  void visitAtomicLoad(const LoadInst &I);
+  void visitAtomicStore(const StoreInst &I);
+
   void visitInlineAsm(ImmutableCallSite CS);
   const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
   void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
Index: include/llvm/CodeGen/SelectionDAGNodes.h
===================================================================
--- include/llvm/CodeGen/SelectionDAGNodes.h	(revision 137997)
+++ include/llvm/CodeGen/SelectionDAGNodes.h	(working copy)
@@ -976,6 +976,8 @@
            N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
            N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
            N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
+           N->getOpcode() == ISD::ATOMIC_LOAD         ||
+           N->getOpcode() == ISD::ATOMIC_STORE        ||
            N->isTargetMemoryOpcode();
   }
 };
@@ -1025,6 +1027,14 @@
     InitAtomic(Ordering, SynchScope);
     InitOperands(Ops, Chain, Ptr, Val);
   }
+  AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
+               SDValue Chain, SDValue Ptr,
+               MachineMemOperand *MMO,
+               AtomicOrdering Ordering, SynchronizationScope SynchScope)
+    : MemSDNode(Opc, dl, VTL, MemVT, MMO) {
+    InitAtomic(Ordering, SynchScope);
+    InitOperands(Ops, Chain, Ptr);
+  }
 
   const SDValue &getBasePtr() const { return getOperand(1); }
   const SDValue &getVal() const { return getOperand(2); }
@@ -1048,7 +1058,9 @@
            N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
            N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
            N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
-           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX;
+           N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
+           N->getOpcode() == ISD::ATOMIC_LOAD         ||
+           N->getOpcode() == ISD::ATOMIC_STORE;
   }
 };
 
Index: include/llvm/CodeGen/SelectionDAG.h
===================================================================
--- include/llvm/CodeGen/SelectionDAG.h	(revision 137997)
+++ include/llvm/CodeGen/SelectionDAG.h	(working copy)
@@ -598,16 +598,26 @@
                     AtomicOrdering Ordering,
                     SynchronizationScope SynchScope);
 
-  /// getAtomic - Gets a node for an atomic op, produces result and chain and
-  /// takes 2 operands.
+  /// getAtomic - Gets a node for an atomic op, produces result (if relevant)
+  /// and chain and takes 2 operands.
   SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
                     SDValue Ptr, SDValue Val, const Value* PtrVal,
+                    unsigned Alignment, AtomicOrdering Ordering,
+                    SynchronizationScope SynchScope);
+  SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
+                    SDValue Ptr, SDValue Val, MachineMemOperand *MMO,
+                    AtomicOrdering Ordering,
+                    SynchronizationScope SynchScope);
+
+  /// getAtomic - Gets a node for an atomic op, produces result and chain and
+  /// takes 1 operand.
+  SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT,
+                    SDValue Chain, SDValue Ptr, const Value* PtrVal,
                     unsigned Alignment,
                     AtomicOrdering Ordering,
                     SynchronizationScope SynchScope);
-  SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
-                    SDValue Ptr, SDValue Val,
-                    MachineMemOperand *MMO,
+  SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT,
+                    SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,
                     AtomicOrdering Ordering,
                     SynchronizationScope SynchScope);
 
Index: include/llvm/CodeGen/ISDOpcodes.h
===================================================================
--- include/llvm/CodeGen/ISDOpcodes.h	(revision 137997)
+++ include/llvm/CodeGen/ISDOpcodes.h	(working copy)
@@ -597,6 +597,9 @@
     // two integer constants: an AtomicOrdering and a SynchronizationScope.
     ATOMIC_FENCE,
 
+    ATOMIC_LOAD,
+    ATOMIC_STORE,
+
     // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
     // this corresponds to the atomic.lcs intrinsic.
     // cmp is compared to *ptr, and if equal, swap is stored in *ptr.
Index: include/llvm/Target/TargetSelectionDAG.td
===================================================================
--- include/llvm/Target/TargetSelectionDAG.td	(revision 137997)
+++ include/llvm/Target/TargetSelectionDAG.td	(working copy)
@@ -214,6 +214,12 @@
 def SDTAtomic2 : SDTypeProfile<1, 2, [
   SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
+def SDTAtomicStore : SDTypeProfile<0, 2, [
+  SDTCisPtrTy<0>, SDTCisInt<1>
+]>;
+def SDTAtomicLoad : SDTypeProfile<1, 1, [
+  SDTCisInt<0>, SDTCisPtrTy<1>
+]>;
 
 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
   SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
@@ -427,6 +433,10 @@
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load      : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_store     : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 
 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
 // and truncst (see below).
@@ -844,7 +854,29 @@
 defm atomic_load_max  : binary_atomic_op<atomic_load_max>;
 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
+defm atomic_store     : binary_atomic_op<atomic_store>;
 
+def atomic_load_8 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+}]>;
+def atomic_load_16 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+}]>;
+def atomic_load_32 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+}]>;
+def atomic_load_64 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Selection DAG CONVERT_RNDSAT patterns
 
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp	(revision 137997)
+++ lib/Target/X86/X86ISelLowering.cpp	(working copy)
@@ -464,6 +464,7 @@
     MVT VT = IntVTs[i];
     setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
     setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
+    setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
   }
 
   if (!Subtarget->is64Bit()) {
@@ -9894,6 +9895,26 @@
                        cast<AtomicSDNode>(Node)->getSynchScope());
 }
 
+static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
+  SDNode *Node = Op.getNode();
+  DebugLoc dl = Node->getDebugLoc();
+
+  // Convert seq_cst store -> xchg
+  if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent) {
+    SDValue Swap =  DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
+                                  cast<AtomicSDNode>(Node)->getMemoryVT(),
+                                   Node->getOperand(0),
+                                   Node->getOperand(1), Node->getOperand(2),
+                                   cast<AtomicSDNode>(Node)->getSrcValue(),
+                                   cast<AtomicSDNode>(Node)->getAlignment(),
+                                   cast<AtomicSDNode>(Node)->getOrdering(),
+                                   cast<AtomicSDNode>(Node)->getSynchScope());
+    return Swap.getValue(1);
+  }
+  // Other atomic stores have a simple pattern.
+  return Op;
+}
+
 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
   EVT VT = Op.getNode()->getValueType(0);
 
@@ -9930,6 +9951,7 @@
   case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op,DAG);
   case ISD::ATOMIC_CMP_SWAP:    return LowerCMP_SWAP(Op,DAG);
   case ISD::ATOMIC_LOAD_SUB:    return LowerLOAD_SUB(Op,DAG);
+  case ISD::ATOMIC_STORE:       return LowerATOMIC_STORE(Op,DAG);
   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
   case ISD::CONCAT_VECTORS:     return LowerCONCAT_VECTORS(Op, DAG);
   case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
Index: lib/Target/X86/X86InstrCompiler.td
===================================================================
--- lib/Target/X86/X86InstrCompiler.td	(revision 137997)
+++ lib/Target/X86/X86InstrCompiler.td	(working copy)
@@ -1691,3 +1691,17 @@
           (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
           (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
+
+def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>;
+def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>;
+def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>;
+def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>;
+
+def : Pat<(atomic_store_8 addr:$ptr, GR8:$val),
+          (MOV8mr addr:$ptr, GR8:$val)>;
+def : Pat<(atomic_store_16 addr:$ptr, GR16:$val),
+          (MOV16mr addr:$ptr, GR16:$val)>;
+def : Pat<(atomic_store_32 addr:$ptr, GR32:$val),
+          (MOV32mr addr:$ptr, GR32:$val)>;
+def : Pat<(atomic_store_64 addr:$ptr, GR64:$val),
+          (MOV64mr addr:$ptr, GR64:$val)>;

From chandlerc at google.com  Thu Aug 18 20:09:17 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 18 Aug 2011 18:09:17 -0700
Subject: [llvm-commits] [llvm] r138018 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
In-Reply-To: <20110819003017.AB8AE2A6C12D@llvm.org>
References: <20110819003017.AB8AE2A6C12D@llvm.org>
Message-ID: <CAGCO0Kj=m4ai1Ey7XZeWkT6PWGxJep4Lw=S0UEYEuVNSV2O_RA@mail.gmail.com>

On Thu, Aug 18, 2011 at 5:30 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

> My test case only works when I disable DCE so a dead copy is left for
> RegisterCoalescer, so I am not including it.
>

Why can't this be disabled with a flag for testing? We do that for the
middle end certainly...
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From wsumner at cs.purdue.edu  Thu Aug 18 19:00:41 2011
From: wsumner at cs.purdue.edu (Nick Sumner)
Date: Thu, 18 Aug 2011 20:00:41 -0400
Subject: [llvm-commits] [PATCH] Crash in SplitBlock with incomplete
	dominator information
Message-ID: <CALr3WLjhYyg+0+tgQ1Zfk9Nd=_oA-8XNGoy2tK34EvWO8MC7rw@mail.gmail.com>

Hi,

The attached patch fixes a crashing bug in SplitBlock when it is
called on a block with no dominator information even though dominators
were previously computed. This is originally from a bug report
(http://llvm.org/bugs/show_bug.cgi?id=10643), but I am cross-posting
to give it a record in the proper place until it can be committed.

One example of a program suffering from this:

#include <stdlib.h>
#include <stdio.h>

void foo() {
  exit(0);
  printf("No dominator info here\n");
}


thanks,
Nick Sumner
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From benny.kra at googlemail.com  Thu Aug 18 20:36:55 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 19 Aug 2011 01:36:55 -0000
Subject: [llvm-commits] [llvm] r138022 - in /llvm/trunk:
 include/llvm-c/Core.h lib/Analysis/Analysis.cpp lib/Transforms/IPO/IPO.cpp
Message-ID: <20110819013655.30A062A6C12C@llvm.org>

Author: d0k
Date: Thu Aug 18 20:36:54 2011
New Revision: 138022

URL: http://llvm.org/viewvc/llvm-project?rev=138022&view=rev
Log:
C API functions must be able to see their extern "C" definitions, or it will be impossible to call them from C.

Modified:
    llvm/trunk/include/llvm-c/Core.h
    llvm/trunk/lib/Analysis/Analysis.cpp
    llvm/trunk/lib/Transforms/IPO/IPO.cpp

Modified: llvm/trunk/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=138022&r1=138021&r2=138022&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Core.h (original)
+++ llvm/trunk/include/llvm-c/Core.h Thu Aug 18 20:36:54 2011
@@ -834,6 +834,9 @@
                              LLVMValueRef *Args, unsigned NumArgs,
                              LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
                              const char *Name);
+LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
+                                 LLVMValueRef PersFn, unsigned NumClauses,
+                                 const char *Name);
 LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn);
 LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
 

Modified: llvm/trunk/lib/Analysis/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=138022&r1=138021&r2=138022&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Analysis.cpp (original)
+++ llvm/trunk/lib/Analysis/Analysis.cpp Thu Aug 18 20:36:54 2011
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm-c/Analysis.h"
+#include "llvm-c/Initialization.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Analysis/Verifier.h"
 #include <cstring>

Modified: llvm/trunk/lib/Transforms/IPO/IPO.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPO.cpp?rev=138022&r1=138021&r2=138022&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/IPO.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/IPO.cpp Thu Aug 18 20:36:54 2011
@@ -13,6 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm-c/Initialization.h"
 #include "llvm-c/Transforms/IPO.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/PassManager.h"



From benny.kra at googlemail.com  Thu Aug 18 20:42:18 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 19 Aug 2011 01:42:18 -0000
Subject: [llvm-commits] [llvm] r138025 - in /llvm/trunk/lib:
 Analysis/LoopInfo.cpp CodeGen/RegAllocGreedy.cpp CodeGen/ScheduleDAG.cpp
 Target/ARM/ARMExpandPseudoInsts.cpp Transforms/Scalar/LowerAtomic.cpp
Message-ID: <20110819014219.03BFD2A6C12C@llvm.org>

Author: d0k
Date: Thu Aug 18 20:42:18 2011
New Revision: 138025

URL: http://llvm.org/viewvc/llvm-project?rev=138025&view=rev
Log:
Make a bunch of symbols private.

Modified:
    llvm/trunk/lib/Analysis/LoopInfo.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp

Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=138025&r1=138024&r2=138025&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopInfo.cpp Thu Aug 18 20:42:18 2011
@@ -390,6 +390,7 @@
 // UnloopUpdater implementation
 //
 
+namespace {
 /// Find the new parent loop for all blocks within the "unloop" whose last
 /// backedges has just been removed.
 class UnloopUpdater {
@@ -421,6 +422,7 @@
 protected:
   Loop *getNearestLoop(BasicBlock *BB, Loop *BBLoop);
 };
+} // end anonymous namespace
 
 /// updateBlockParents - Update the parent loop for all blocks that are directly
 /// contained within the original "unloop".

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=138025&r1=138024&r2=138025&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Thu Aug 18 20:42:18 2011
@@ -51,7 +51,7 @@
 STATISTIC(NumLocalSplits,  "Number of split local live ranges");
 STATISTIC(NumEvicted,      "Number of interferences evicted");
 
-cl::opt<bool> CompactRegions("compact-regions", cl::init(true));
+static cl::opt<bool> CompactRegions("compact-regions", cl::init(true));
 
 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
                                        createGreedyRegisterAllocator);

Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=138025&r1=138024&r2=138025&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Thu Aug 18 20:42:18 2011
@@ -26,7 +26,7 @@
 using namespace llvm;
 
 #ifndef NDEBUG
-cl::opt<bool> StressSchedOpt(
+static cl::opt<bool> StressSchedOpt(
   "stress-sched", cl::Hidden, cl::init(false),
   cl::desc("Stress test instruction scheduling"));
 #endif

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=138025&r1=138024&r2=138025&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Aug 18 20:42:18 2011
@@ -30,7 +30,7 @@
 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
 using namespace llvm;
 
-cl::opt<bool>
+static cl::opt<bool>
 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
                 cl::desc("Verify machine code after expanding ARM pseudos"));
 

Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=138025&r1=138024&r2=138025&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Thu Aug 18 20:42:18 2011
@@ -115,7 +115,7 @@
   return true;
 }
 
-bool LowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
+static bool LowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
   IRBuilder<> Builder(CXI->getParent(), CXI);
   Value *Ptr = CXI->getPointerOperand();
   Value *Cmp = CXI->getCompareOperand();
@@ -131,7 +131,7 @@
   return true;
 }
 
-bool LowerAtomicRMWInst(AtomicRMWInst *RMWI) {
+static bool LowerAtomicRMWInst(AtomicRMWInst *RMWI) {
   IRBuilder<> Builder(RMWI->getParent(), RMWI);
   Value *Ptr = RMWI->getPointerOperand();
   Value *Val = RMWI->getValOperand();



From wendling at apple.com  Thu Aug 18 20:44:10 2011
From: wendling at apple.com (Bill Wendling)
Date: Thu, 18 Aug 2011 18:44:10 -0700
Subject: [llvm-commits] [llvm] r138022 - in /llvm/trunk:
 include/llvm-c/Core.h lib/Analysis/Analysis.cpp lib/Transforms/IPO/IPO.cpp
In-Reply-To: <20110819013655.30A062A6C12C@llvm.org>
References: <20110819013655.30A062A6C12C@llvm.org>
Message-ID: <D5E2E94A-EF83-4F35-932E-BA6984503D36@apple.com>

n Aug 18, 2011, at 6:36 PM, Benjamin Kramer wrote:

> Author: d0k
> Date: Thu Aug 18 20:36:54 2011
> New Revision: 138022
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138022&view=rev
> Log:
> C API functions must be able to see their extern "C" definitions, or it will be impossible to call them from C.
> 
> Modified:
>    llvm/trunk/include/llvm-c/Core.h
>    llvm/trunk/lib/Analysis/Analysis.cpp
>    llvm/trunk/lib/Transforms/IPO/IPO.cpp
> 
> Modified: llvm/trunk/include/llvm-c/Core.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=138022&r1=138021&r2=138022&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm-c/Core.h (original)
> +++ llvm/trunk/include/llvm-c/Core.h Thu Aug 18 20:36:54 2011
> @@ -834,6 +834,9 @@
>                              LLVMValueRef *Args, unsigned NumArgs,
>                              LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
>                              const char *Name);
> +LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
> +                                 LLVMValueRef PersFn, unsigned NumClauses,
> +                                 const char *Name);
> LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn);
> LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
> 
I don't know how I missed this...>.>

Thanks!
-bw


From stoklund at 2pi.dk  Thu Aug 18 20:56:36 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 18 Aug 2011 18:56:36 -0700
Subject: [llvm-commits] [llvm] r138018 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
In-Reply-To: <CAGCO0Kj=m4ai1Ey7XZeWkT6PWGxJep4Lw=S0UEYEuVNSV2O_RA@mail.gmail.com>
References: <20110819003017.AB8AE2A6C12D@llvm.org>
	<CAGCO0Kj=m4ai1Ey7XZeWkT6PWGxJep4Lw=S0UEYEuVNSV2O_RA@mail.gmail.com>
Message-ID: <814103D0-97DF-4BE6-8B64-836FBE0EA3AB@2pi.dk>


On Aug 18, 2011, at 6:09 PM, Chandler Carruth wrote:

> On Thu, Aug 18, 2011 at 5:30 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> My test case only works when I disable DCE so a dead copy is left for
> RegisterCoalescer, so I am not including it.
> 
> Why can't this be disabled with a flag for testing? We do that for the middle end certainly...

You are right, there should be a flag. I'll add it.

/jakob

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From stoklund at 2pi.dk  Thu Aug 18 21:05:35 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 02:05:35 -0000
Subject: [llvm-commits] [llvm] r138028 -
	/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Message-ID: <20110819020535.5C3CD2A6C12C@llvm.org>

Author: stoklund
Date: Thu Aug 18 21:05:35 2011
New Revision: 138028

URL: http://llvm.org/viewvc/llvm-project?rev=138028&view=rev
Log:
Add llc flags to disable machine DCE and CSE.

This is useful for unit tests.

Modified:
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=138028&r1=138027&r2=138028&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Aug 18 21:05:35 2011
@@ -57,8 +57,12 @@
     cl::desc("Disable code placement"));
 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
     cl::desc("Disable Stack Slot Coloring"));
+static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
+    cl::desc("Disable Machine Dead Code Elimination"));
 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
     cl::desc("Disable Machine LICM"));
+static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
+    cl::desc("Disable Machine Common Subexpression Elimination"));
 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
     cl::Hidden,
     cl::desc("Disable Machine LICM"));
@@ -398,12 +402,14 @@
     // there is one known exception: lowered code for arguments that are only
     // used by tail calls, where the tail calls reuse the incoming stack
     // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
-    PM.add(createDeadMachineInstructionElimPass());
+    if (!DisableMachineDCE)
+      PM.add(createDeadMachineInstructionElimPass());
     printAndVerify(PM, "After codegen DCE pass");
 
     if (!DisableMachineLICM)
       PM.add(createMachineLICMPass());
-    PM.add(createMachineCSEPass());
+    if (!DisableMachineCSE)
+      PM.add(createMachineCSEPass());
     if (!DisableMachineSink)
       PM.add(createMachineSinkingPass());
     printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");



From bruno.cardoso at gmail.com  Thu Aug 18 21:23:56 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 19 Aug 2011 02:23:56 -0000
Subject: [llvm-commits] [llvm] r138029 - in /llvm/trunk:
 lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
 test/MC/X86/x86_64-avx-encoding.s
Message-ID: <20110819022356.A27992A6C12C@llvm.org>

Author: bruno
Date: Thu Aug 18 21:23:56 2011
New Revision: 138029

URL: http://llvm.org/viewvc/llvm-project?rev=138029&view=rev
Log:
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
implementation!

Modified:
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/X86/x86_64-avx-encoding.s

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=138029&r1=138028&r2=138029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Thu Aug 18 21:23:56 2011
@@ -533,9 +533,14 @@
       const MCOperand &MO = MI.getOperand(CurOp);
       if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
         VEX_B = 0x0;
-      if (!VEX_B && MO.isReg() &&
-          ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
-          X86II::isX86_64ExtendedReg(MO.getReg()))
+      // Only set VEX_X if the Index Register is extended
+      if (VEX_B || !MO.isReg())
+        continue;
+      if (!X86II::isX86_64ExtendedReg(MO.getReg()))
+        continue;
+      unsigned Frm = TSFlags & X86II::FormMask;
+      if ((Frm == X86II::MRMSrcMem && CurOp-1 == X86::AddrIndexReg) ||
+          (Frm == X86II::MRMDestMem && CurOp == X86::AddrIndexReg))
         VEX_X = 0x0;
     }
     break;

Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=138029&r1=138028&r2=138029&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Thu Aug 18 21:23:56 2011
@@ -3316,3 +3316,19 @@
 // CHECK: encoding: [0xc4,0x63,0x1d,0x4b,0xac,0x20,0xad,0xde,0x00,0x00,0xb0]
           vblendvpd  %ymm11, 0xdead(%rax,%riz), %ymm12, %ymm13
 
+// CHECK: vmovaps	%xmm3, (%r14,%r11)
+// CHECK: encoding: [0xc4,0x81,0x78,0x29,0x1c,0x1e]
+          vmovaps	%xmm3, (%r14,%r11)
+
+// CHECK: vmovaps	(%r14,%r11), %xmm3
+// CHECK: encoding: [0xc4,0x81,0x78,0x28,0x1c,0x1e]
+          vmovaps	(%r14,%r11), %xmm3
+
+// CHECK: vmovaps	%xmm3, (%r14,%rbx)
+// CHECK: encoding: [0xc4,0xc1,0x78,0x29,0x1c,0x1e]
+          vmovaps	%xmm3, (%r14,%rbx)
+
+// CHECK: vmovaps	(%r14,%rbx), %xmm3
+// CHECK: encoding: [0xc4,0xc1,0x78,0x28,0x1c,0x1e]
+          vmovaps	(%r14,%rbx), %xmm3
+



From stoklund at 2pi.dk  Thu Aug 18 23:30:24 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 04:30:24 -0000
Subject: [llvm-commits] [llvm] r138033 -
	/llvm/trunk/test/CodeGen/X86/coalescer-dce.ll
Message-ID: <20110819043024.D59A32A6C12C@llvm.org>

Author: stoklund
Date: Thu Aug 18 23:30:24 2011
New Revision: 138033

URL: http://llvm.org/viewvc/llvm-project?rev=138033&view=rev
Log:
Add test case for r138018.

Added:
    llvm/trunk/test/CodeGen/X86/coalescer-dce.ll

Added: llvm/trunk/test/CodeGen/X86/coalescer-dce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-dce.ll?rev=138033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/coalescer-dce.ll (added)
+++ llvm/trunk/test/CodeGen/X86/coalescer-dce.ll Thu Aug 18 23:30:24 2011
@@ -0,0 +1,80 @@
+; RUN: llc < %s -disable-fp-elim -disable-machine-dce -verify-coalescing
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+; This test case has a sub-register join followed by a remat:
+;
+; 256L    %vreg2<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg7
+;         Considering merging %vreg2 with %vreg7:sub_32bit
+;         Cross-class to GR64.
+;                 RHS = %vreg2 = [256d,272d:0)  0 at 256d
+;                 LHS = %vreg7 = [208d,256d:0)[304L,480L:0)  0 at 208d
+;                 updated: 272L   %vreg0<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg0 GR64:%vreg7
+;         Joined. Result = %vreg7 = [208d,272d:0)[304L,480L:0)  0 at 208d
+;
+; 272L    %vreg10:sub_32bit<def> = COPY %vreg7:sub_32bit<kill>, %vreg10<imp-def>; GR64:%vreg10,%vreg7
+;         Considering merging %vreg7 with %vreg10
+;                 RHS = %vreg7 = [208d,272d:0)[304L,480L:0)  0 at 208d
+;                 LHS = %vreg10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4)  0 at 352d 1 at 64L-phidef 2 at 16d-phikill 3 at 272d-phikill 4 at 400d
+; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %EFLAGS<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10
+; Shrink: %vreg7 = [208d,272d:0)[304L,480L:0)  0 at 208d
+;  live-in at 240L
+;  live-in at 416L
+;  live-in at 320L
+;  live-in at 304L
+; Shrunk: %vreg7 = [208d,256d:0)[304L,480L:0)  0 at 208d
+;
+; The COPY at 256L is rewritten as a partial def, and that would artificially
+; extend the live range of %vreg7 to end at 256d.  When the joined copy is
+; removed, -verify-coalescing complains about the dangling kill.
+;
+; <rdar://problem/9967101>
+
+define void @f1() nounwind uwtable ssp {
+bb:
+  br label %bb1
+
+bb1:
+  %tmp = phi i32 [ 0, %bb ], [ %tmp21, %bb20 ]
+  br label %bb2
+
+bb2:
+  br i1 undef, label %bb5, label %bb8
+
+bb4:
+  br i1 undef, label %bb2, label %bb20
+
+bb5:
+  br i1 undef, label %bb4, label %bb20
+
+bb8:
+  %tmp9 = phi i32 [ %tmp24, %bb23 ], [ 0, %bb2 ]
+  br i1 false, label %bb41, label %bb10
+
+bb10:
+  %tmp11 = sub nsw i32 %tmp9, %tmp
+  br i1 false, label %bb2, label %bb26
+
+bb20:
+  %tmp21 = phi i32 [ undef, %bb4 ], [ undef, %bb5 ], [ %tmp9, %bb27 ], [ undef, %bb32 ]
+  %tmp22 = phi i32 [ undef, %bb4 ], [ undef, %bb5 ], [ %tmp11, %bb27 ], [ undef, %bb32 ]
+  br label %bb1
+
+bb23:
+  %tmp24 = add nsw i32 %tmp9, 1
+  br label %bb8
+
+bb26:
+  br i1 undef, label %bb27, label %bb32
+
+bb27:
+  %tmp28 = zext i32 %tmp11 to i64
+  %tmp30 = icmp eq i64 undef, %tmp28
+  br i1 %tmp30, label %bb20, label %bb27
+
+bb32:
+  br i1 undef, label %bb20, label %bb23
+
+bb41:
+  ret void
+}



From craig.topper at gmail.com  Fri Aug 19 00:28:50 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Fri, 19 Aug 2011 05:28:50 -0000
Subject: [llvm-commits] [llvm] r138034 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/Disassembler/X86/simple-tests.txt
Message-ID: <20110819052850.6CDC72A6C12C@llvm.org>

Author: ctopper
Date: Fri Aug 19 00:28:50 2011
New Revision: 138034

URL: http://llvm.org/viewvc/llvm-project?rev=138034&view=rev
Log:
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138034&r1=138033&r2=138034&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Aug 19 00:28:50 2011
@@ -1585,10 +1585,10 @@
 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
                                        SDNode OpNode> {
   defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
-              FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
+              FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
 
   defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
-        FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
+        FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
 
   let Constraints = "$src1 = $dst" in {
     defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
@@ -1620,7 +1620,7 @@
   defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
        !strconcat(OpcodeStr, "ps"), f128mem, [],
        [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
-                                 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
+                                 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
 
   defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
        !strconcat(OpcodeStr, "pd"), f128mem,
@@ -1628,7 +1628,7 @@
                                  (bc_v2i64 (v2f64 VR128:$src2))))],
        [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
                                  (memopv2i64 addr:$src2)))], 0>,
-                                                 OpSize, VEX_4V;
+                                                 TB, OpSize, VEX_4V;
   let Constraints = "$src1 = $dst" in {
     defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
          !strconcat(OpcodeStr, "ps"), f128mem,
@@ -1653,7 +1653,7 @@
           !strconcat(OpcodeStr, "ps"), f256mem,
           [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
           [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
-                                    (memopv4i64 addr:$src2)))], 0>, VEX_4V;
+                                    (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
 
     defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
           !strconcat(OpcodeStr, "pd"), f256mem,
@@ -1661,7 +1661,7 @@
                                     (bc_v4i64 (v4f64 VR256:$src2))))],
           [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
                                     (memopv4i64 addr:$src2)))], 0>,
-                                    OpSize, VEX_4V;
+                                    TB, OpSize, VEX_4V;
 }
 
 // AVX 256-bit packed logical ops forms

Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=138034&r1=138033&r2=138034&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Fri Aug 19 00:28:50 2011
@@ -72,3 +72,9 @@
 
 # CHECK: vaddps	%ymm3, %ymm1, %ymm0
 0xc5 0xf4 0x58 0xc3
+
+# CHECK: vandpd	%ymm13, %ymm1, %ymm0
+0xc4 0xc1 0x75 0x54 0xc5
+
+# CHECK: vandps	%ymm3, %ymm1, %ymm0
+0xc5 0xf4 0x54 0xc3



From baldrick at free.fr  Fri Aug 19 00:52:38 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 19 Aug 2011 05:52:38 -0000
Subject: [llvm-commits] [dragonegg] r138035 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20110819055238.594EA2A6C12C@llvm.org>

Author: baldrick
Date: Fri Aug 19 00:52:38 2011
New Revision: 138035

URL: http://llvm.org/viewvc/llvm-project?rev=138035&view=rev
Log:
Set unnamed_addr also on globals that are not constant since they
may be proved constant later by the optimizers.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=138035&r1=138034&r2=138035&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Fri Aug 19 00:52:38 2011
@@ -886,13 +886,13 @@
   TARGET_ADJUST_LLVM_LINKAGE(GV, decl);
 #endif /* TARGET_ADJUST_LLVM_LINKAGE */
 
-  // If this is a constant that never has its address taken then allow it to be
-  // merged with other constants (C and C++ say that different variables should
+  // If this is a variable that never has its address taken then allow it to be
+  // merged with other variables (C and C++ say that different variables should
   // have different addresses, which is why this is only correct if the address
   // is not taken).  However if -fmerge-all-constants was specified then allow
-  // merging even if the address was taken.
-  GV->setUnnamedAddr(GV->isConstant() && (flag_merge_constants >= 2 ||
-                                          !TREE_ADDRESSABLE(decl)));
+  // merging even if the address was taken.  Note that merging will only happen
+  // if the global is constant or later proved to be constant by the optimizers.
+  GV->setUnnamedAddr(flag_merge_constants >= 2 || !TREE_ADDRESSABLE(decl));
 
   handleVisibility(decl, GV);
 



From jay.foad at gmail.com  Fri Aug 19 05:47:44 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Fri, 19 Aug 2011 11:47:44 +0100
Subject: [llvm-commits] PR10663: remove
	DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS
Message-ID: <CANd1uZkoxjG4ryjLbAuFoJJw+i-6EDHOf_UN_i_4Dt+MvMVm1w@mail.gmail.com>

http://llvm.org/bugs/show_bug.cgi?id=10663

The only difference between DEFINE_TRANSPARENT_OPERAND_ACCESSORS and
DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS seems to be in the way
they cast the value returned from getOperand():

- DTOA uses static_cast<>, which tolerates NULL operands
- DTCOA uses cast<>, which asserts that the cast is safe, but doesn't
tolerate NULL operands (hence the bug report)

The attached patch simplifies this by removing DTCOA and changing DTOA
to use cast_or_null<>, which gives the best of both worlds: it checks
that the cast is safe, and allows NULL operands.

Tested with "make all check-all", LLVM + Clang, and by manually
running the test case from the PR. (I have no idea how to add this
test case to the automatic test suite -- perhaps you could take care
of that, Duncan?)

OK to commit?

Thanks,
Jay.
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From kalle.raiskila at nokia.com  Fri Aug 19 05:50:24 2011
From: kalle.raiskila at nokia.com (Kalle Raiskila)
Date: Fri, 19 Aug 2011 10:50:24 -0000
Subject: [llvm-commits] [llvm] r138037 -
	/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
Message-ID: <20110819105024.F07932A6C12C@llvm.org>

Author: kraiskil
Date: Fri Aug 19 05:50:24 2011
New Revision: 138037

URL: http://llvm.org/viewvc/llvm-project?rev=138037&view=rev
Log:
Have SPU backend use the external TCE scheduler, if the library is loaded as a
module.

Patch by Pekka J??skel?inen.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=138037&r1=138036&r2=138037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Fri Aug 19 05:50:24 2011
@@ -17,6 +17,7 @@
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/Target/TargetRegistry.h"
+#include "llvm/Support/DynamicLibrary.h"
 
 using namespace llvm;
 
@@ -59,6 +60,16 @@
 bool SPUTargetMachine::
 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) 
 {
+
+  // load the TCE instruction scheduler, if available via
+  // loaded plugins
+  typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
+  BuilderFunc schedulerCreator = 
+      (BuilderFunc)llvm::sys::DynamicLibrary::SearchForAddressOfSymbol(
+          "createTCESchedulerPass");
+  if (schedulerCreator != NULL)
+      PM.add(schedulerCreator("cellspu"));
+
   //align instructions with nops/lnops for dual issue
   PM.add(createSPUNopFillerPass(*this));
   return true;



From jay.foad at gmail.com  Fri Aug 19 07:58:00 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Fri, 19 Aug 2011 13:58:00 +0100
Subject: [llvm-commits] r133708 strikes me again? - the case clang stalls
In-Reply-To: <CADiQthOjV1AbK_0+ndezoM6cp1zO8OR7-rJg6hyHJgBF-cCsqQ@mail.gmail.com>
References: <CADiQthN7w721yfMGTUbv24poBf-gFc7aDbakPZPBZxa3KKD8vA@mail.gmail.com>
	<CADiQthOVbeTYV3cZyU=mfdbxz9YcR_sHbzmQ2pzibm1__NC_EA@mail.gmail.com>
	<DAA72FA8-4A6D-4436-9306-A868CF44456A@apple.com>
	<CANd1uZk67T5XV=06-PeC5SwGHLd==7+65W0a_dWek022bZaR-g@mail.gmail.com>
	<CANd1uZmSDhzH4fJg-6EMr822Rg4R=Mcad4UBXcB08m7WpZfEBA@mail.gmail.com>
	<2B900B62-E852-4E5A-89C1-E5F0DBB44EA6@apple.com>
	<CADiQthOjV1AbK_0+ndezoM6cp1zO8OR7-rJg6hyHJgBF-cCsqQ@mail.gmail.com>
Message-ID: <CANd1uZkvWb_Fsw2Znk8O4cu_EC8ju8awt-RnH2qUBJH9oaVEHg@mail.gmail.com>

On 10 August 2011 00:42, NAKAMURA Takumi <geek4civic at gmail.com> wrote:
> Jay and John, I have committed Jay's in r137175, thank you!

Thanks Takumi. Sorry for breaking it!

Jay.

From criswell at uiuc.edu  Fri Aug 19 10:08:16 2011
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 19 Aug 2011 15:08:16 -0000
Subject: [llvm-commits] [poolalloc] r138039 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110819150816.475522A6C12C@llvm.org>

Author: criswell
Date: Fri Aug 19 10:08:16 2011
New Revision: 138039

URL: http://llvm.org/viewvc/llvm-project?rev=138039&view=rev
Log:
Updated the names of the SAFECode run-time functions.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138039&r1=138038&r2=138039&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Aug 19 10:08:16 2011
@@ -254,17 +254,31 @@
 
   
   // SAFECode Intrinsics
-  {"sc.lscheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.lscheckui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.lscheckalign", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.lscheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_register_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_unregister_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_register_global", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_unregister_global", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_register", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_unregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.pool_argvregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheck",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckui",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckalign",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+
+  {"poolcheck_debug",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckui_debug",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckalign_debug",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"poolcheckalignui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+
+  {"pool_register_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_register_global", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister_global", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_register", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_argvregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+
+  {"pool_register_stack_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister_stack_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_register_global_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister_global_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_register_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_unregister_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+
 
   // CIF Intrinsics
   {"__if_pool_get_label", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
@@ -578,10 +592,11 @@
     // Merge return values and checked pointer values for SAFECode run-time
     // checks.
     //
-    processRuntimeCheck (M, "sc.boundscheck", 2);
-    processRuntimeCheck (M, "sc.boundscheckui", 2);
-    processRuntimeCheck (M, "sc.exactcheck2", 1);
-    processRuntimeCheck (M, "sc.get_actual_val", 1);
+    processRuntimeCheck (M, "boundscheck", 2);
+    processRuntimeCheck (M, "boundscheckui", 2);
+    processRuntimeCheck (M, "exactcheck2", 1);
+    processRuntimeCheck (M, "fastlscheck", 1);
+    processRuntimeCheck (M, "pchk_getActualValue", 1);
   }
 
   //



From Micah.Villmow at amd.com  Fri Aug 19 10:47:37 2011
From: Micah.Villmow at amd.com (Villmow, Micah)
Date: Fri, 19 Aug 2011 10:47:37 -0500
Subject: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch
In-Reply-To: <D556DCBBC0EA924A9AC80003B62121120744AE3357@sausexmbp02.amd.com>
References: <D556DCBBC0EA924A9AC80003B62121120744AE329A@sausexmbp02.amd.com>
	<CAJgxuadb_g5G72nWtNkR2-wsTSay3oOtVz6iz7CoTiaRKD3doQ@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32AA@sausexmbp02.amd.com>
	<CAJgxuaeY5BJoqXLiFy+aRa_7p5S75ayDTjz=mu2cnQbXQYXVjA@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32BF@sausexmbp02.amd.com>
	<CAJgxuaeQywnBVMtRsw-_nzj5cjCoevRamt-d5xcn-iNb=vm7Hg@mail.gmail.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE32CD@sausexmbp02.amd.com>
	<D556DCBBC0EA924A9AC80003B62121120744AE3357@sausexmbp02.amd.com>
Message-ID: <D556DCBBC0EA924A9AC80003B62121120744AE3515@sausexmbp02.amd.com>

Ping...

From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Wednesday, August 17, 2011 2:59 PM
To: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

Here is a patch that is against TOT.

From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Wednesday, August 17, 2011 10:06 AM
To: Justin Holewinski
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch



From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:47 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:41 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: Justin Holewinski [mailto:justin.holewinski at gmail.com<mailto:justin.holewinski at gmail.com>]
Sent: Wednesday, August 17, 2011 9:32 AM

To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 12:07 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:


From: llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu> [mailto:llvm-commits-bounces at cs.uiuc.edu<mailto:llvm-commits-bounces at cs.uiuc.edu>] On Behalf Of Justin Holewinski
Sent: Wednesday, August 17, 2011 9:02 AM
To: Villmow, Micah
Cc: llvm-commits
Subject: Re: [llvm-commits] FW: [LLVMdev] AMDIL Target Triple patch

On Wed, Aug 17, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:
Forgot to send to llvm-commits.

Is the entire AMDIL back-end coming to LLVM ToT?
[Villmow, Micah] Yes, it is going through internal code review now. However, it will be posted for LLVM 2.9
first as that is what we are building against internally. After that, when I get time as I'm pretty busy, I will
update it for TOT.

Awesome!

How will this integrate with the AMD APP SDK?  From what I understand, CAL (and the ability to load/execute AMDIL) is deprecated as of AMD APP SDK 2.5.  Is this going to somehow integrate with the AMD OpenCL implementation?
[Villmow, Micah] All I can say is that this is outside of the scope of the APP SDK. This is mainly to allow others to take advantage of targeting AMDIL from their own compilers and to see how
we implemented things using LLVM for a non-x86 like target.

So assuming I generate AMDIL using this back-end, then what?  How can I execute it on real AMD hardware?
[Villmow, Micah] One way is to create an OpenCL binary using the output of AMDIL and load it into OpenCL. Another approach is to write a small runtime shim that converts from a compilation unit containing multiple kernels into single kernel per compilation unit and then use the CAL API to generate a CAL binary.  Our first step is to get the source code out there, and then based on feedback see what the next step can be to make it more useful.




> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu>]
> On Behalf Of Villmow, Micah
> Sent: Wednesday, August 17, 2011 8:29 AM
> To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
> Subject: [LLVMdev] AMDIL Target Triple patch
>
> Here is a patch for LLVM 2.9 that adds AMDIL as a valid target triple
> to LLVM.
> I'll get an updated patch for LLVM TOT if this doesn't patch cleanly
> next.
>
> Micah

_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski




--
Thanks,

Justin Holewinski

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From grosbach at apple.com  Fri Aug 19 11:29:37 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 09:29:37 -0700
Subject: [llvm-commits] [llvm] r138015 -
 /llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
In-Reply-To: <20110819000922.341652A6C12C@llvm.org>
References: <20110819000922.341652A6C12C@llvm.org>
Message-ID: <3A2A4B77-CA3B-440B-ADEE-1A614F39A72B@apple.com>

Hi Bill,

Does this logic will apply to the edge splitting in SjLjEHPrepare as well? If so, equivalent changes may need to be made there.

-Jim

On Aug 18, 2011, at 5:09 PM, Bill Wendling wrote:

> Author: void
> Date: Thu Aug 18 19:09:22 2011
> New Revision: 138015
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138015&view=rev
> Log:
> Intelligently split the landing pad block.
> 
> We have to be careful when splitting the landing pad block, because the
> landingpad instruction is required to remain as the first non-PHI of an invoke's
> unwind edge. To retain this, we split the block into two blocks, moving the
> predecessors within the loop to one block and the remaining predecessors to the
> other. The landingpad instruction is cloned into the new blocks.
> 
> Modified:
>    llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=138015&r1=138014&r2=138015&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Thu Aug 18 19:09:22 2011
> @@ -410,13 +410,24 @@
>   }
> 
>   assert(!LoopBlocks.empty() && "No edges coming in from outside the loop?");
> -  BasicBlock *NewBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
> -                                             LoopBlocks.size(), ".loopexit",
> -                                             this);
> +  BasicBlock *NewExitBB = 0;
> +
> +  if (Exit->isLandingPad()) {
> +    SmallVector<BasicBlock*, 2> NewBBs;
> +    SplitLandingPadPredecessors(Exit, ArrayRef<BasicBlock*>(&LoopBlocks[0],
> +                                                            LoopBlocks.size()),
> +                                ".loopexit", ".nonloopexit",
> +                                this, NewBBs);
> +    NewExitBB = NewBBs[0];
> +  } else {
> +    NewExitBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
> +                                       LoopBlocks.size(), ".loopexit",
> +                                       this);
> +  }
> 
>   DEBUG(dbgs() << "LoopSimplify: Creating dedicated exit block "
> -               << NewBB->getName() << "\n");
> -  return NewBB;
> +               << NewExitBB->getName() << "\n");
> +  return NewExitBB;
> }
> 
> /// AddBlockAndPredsToSet - Add the specified block, and all of its
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From criswell at uiuc.edu  Fri Aug 19 11:39:19 2011
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 19 Aug 2011 16:39:19 -0000
Subject: [llvm-commits] [poolalloc] r138041 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110819163919.CD22E2A6C12F@llvm.org>

Author: criswell
Date: Fri Aug 19 11:39:19 2011
New Revision: 138041

URL: http://llvm.org/viewvc/llvm-project?rev=138041&view=rev
Log:
Do not treat fastlscheck() like exactcheck2(); it does not have a pointer
return value.  Instead, treat it like poolcheck().

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138041&r1=138040&r2=138041&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Aug 19 11:39:19 2011
@@ -256,6 +256,7 @@
   // SAFECode Intrinsics
   {"poolcheck",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"poolcheckui",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"fastlscheck",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"poolcheckalign",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"poolcheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
 
@@ -595,7 +596,6 @@
     processRuntimeCheck (M, "boundscheck", 2);
     processRuntimeCheck (M, "boundscheckui", 2);
     processRuntimeCheck (M, "exactcheck2", 1);
-    processRuntimeCheck (M, "fastlscheck", 1);
     processRuntimeCheck (M, "pchk_getActualValue", 1);
   }
 



From grosbach at apple.com  Fri Aug 19 11:52:32 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 16:52:32 -0000
Subject: [llvm-commits] [llvm] r138042 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20110819165232.7938C2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 11:52:32 2011
New Revision: 138042

URL: http://llvm.org/viewvc/llvm-project?rev=138042&view=rev
Log:
Add explanatory comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138042&r1=138041&r2=138042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 11:52:32 2011
@@ -125,6 +125,11 @@
 
 // t_addrmode_rrs := reg + reg
 //
+// We use separate scaled versions because the Select* functions need
+// to explicitly check for a matching constant and return false here so that
+// the reg+imm forms will match instead. This is a horrible way to do that,
+// as it forces tight coupling between the methods, but it's how selectiondag
+// currently works.
 def t_addrmode_rrs1 : Operand<i32>,
                       ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
   let EncoderMethod = "getThumbAddrModeRegRegOpValue";



From criswell at uiuc.edu  Fri Aug 19 11:57:55 2011
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 19 Aug 2011 16:57:55 -0000
Subject: [llvm-commits] [llvm] r138043 - /llvm/trunk/docs/LangRef.html
Message-ID: <20110819165755.DADF32A6C12C@llvm.org>

Author: criswell
Date: Fri Aug 19 11:57:55 2011
New Revision: 138043

URL: http://llvm.org/viewvc/llvm-project?rev=138043&view=rev
Log:
Fixed some punctuation.  Sentences can be combined with semi-colons but not
commas.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=138043&r1=138042&r2=138043&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Fri Aug 19 11:57:55 2011
@@ -8396,7 +8396,7 @@
 <h5>Semantics:</h5>
 <p>This intrinsic allows annotation of local variables with arbitrary strings.
    This can be useful for special purpose optimizations that want to look for
-   these annotations.  These have no other defined use, they are ignored by code
+   these annotations.  These have no other defined use; they are ignored by code
    generation and optimization.</p>
 
 </div>
@@ -8432,7 +8432,7 @@
 <h5>Semantics:</h5>
 <p>This intrinsic allows annotations to be put on arbitrary expressions with
    arbitrary strings.  This can be useful for special purpose optimizations that
-   want to look for these annotations.  These have no other defined use, they
+   want to look for these annotations.  These have no other defined use; they
    are ignored by code generation and optimization.</p>
 
 </div>



From grosbach at apple.com  Fri Aug 19 12:55:24 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 17:55:24 -0000
Subject: [llvm-commits] [llvm] r138047 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819175524.615472A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 12:55:24 2011
New Revision: 138047

URL: http://llvm.org/viewvc/llvm-project?rev=138047&view=rev
Log:
Thumb assembly parsing and encoding for LDR(immediate) form T1.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138047&r1=138046&r2=138047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 12:55:24 2011
@@ -157,11 +157,13 @@
 
 // t_addrmode_is4 := reg + imm5 * 4
 //
+def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
 def t_addrmode_is4 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
   let EncoderMethod = "getAddrModeISOpValue";
   let DecoderMethod = "DecodeThumbAddrModeIS";
   let PrintMethod = "printThumbAddrModeImm5S4Operand";
+  let ParserMatchClass = t_addrmode_is4_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138047&r1=138046&r2=138047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 12:55:24 2011
@@ -616,7 +616,17 @@
     if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
         Mem.ShiftType != ARM_AM::no_shift)
       return false;
-    return true;
+    return isARMLowRegister(Mem.BaseRegNum) &&
+      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
+  }
+  bool isMemThumbRIs4() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+        !isARMLowRegister(Mem.BaseRegNum))
+      return false;
+    // Immediate offset, multiple of 4 in range [0, 124].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val < 125 && (Val % 4) == 0;
   }
   bool isMemImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
@@ -975,6 +985,13 @@
     Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
   }
 
+  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138047&r1=138046&r2=138047&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 12:55:24 2011
@@ -174,3 +174,16 @@
 @ CHECK: ldm	r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
 @ CHECK: ldm	r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
 @ CHECK: ldm	r1, {r1}                @ encoding: [0x02,0xc9]
+
+
+ at ------------------------------------------------------------------------------
+@ LDR (immediate)
+ at ------------------------------------------------------------------------------
+        ldr r1, [r5]
+        ldr r2, [r6, #32]
+        ldr r3, [r7, #124]
+
+@ CHECK: ldr	r1, [r5]                @ encoding: [0x29,0x68]
+@ CHECK: ldr	r2, [r6, #32]           @ encoding: [0x32,0x6a]
+@ CHECK: ldr	r3, [r7, #124]          @ encoding: [0xfb,0x6f]
+



From grosbach at apple.com  Fri Aug 19 12:57:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 17:57:23 -0000
Subject: [llvm-commits] [llvm] r138048 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110819175723.1F6BB2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 12:57:22 2011
New Revision: 138048

URL: http://llvm.org/viewvc/llvm-project?rev=138048&view=rev
Log:
Use helper function to check for low registers.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138048&r1=138047&r2=138048&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 12:57:22 2011
@@ -3015,7 +3015,7 @@
       if (Reg == Rn)
         doesWriteback = false;
       // Anything other than a low register isn't legal here.
-      if (getARMRegisterNumbering(Reg) > 7)
+      if (!isARMLowRegister(Reg))
         return Error(Operands[4]->getStartLoc(),
                      "registers must be in range r0-r7");
     }



From grosbach at apple.com  Fri Aug 19 13:13:48 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 18:13:48 -0000
Subject: [llvm-commits] [llvm] r138050 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819181348.80D2B2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 13:13:48 2011
New Revision: 138050

URL: http://llvm.org/viewvc/llvm-project?rev=138050&view=rev
Log:
Thumb assembly parsing and encoding for LDR(immediate) form T2.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138050&r1=138049&r2=138050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 13:13:48 2011
@@ -189,11 +189,13 @@
 
 // t_addrmode_sp := sp + imm8 * 4
 //
+def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
 def t_addrmode_sp : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
   let EncoderMethod = "getAddrModeThumbSPOpValue";
   let DecoderMethod = "DecodeThumbAddrModeSP";
   let PrintMethod = "printThumbAddrModeSPOperand";
+  let ParserMatchClass = t_addrmode_sp_asm_operand;
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138050&r1=138049&r2=138050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 13:13:48 2011
@@ -626,7 +626,15 @@
     // Immediate offset, multiple of 4 in range [0, 124].
     if (!Mem.OffsetImm) return true;
     int64_t Val = Mem.OffsetImm->getValue();
-    return Val >= 0 && Val < 125 && (Val % 4) == 0;
+    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
+  }
+  bool isMemThumbSPI() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
+      return false;
+    // Immediate offset, multiple of 4 in range [0, 1020].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
   }
   bool isMemImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
@@ -992,6 +1000,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138050&r1=138049&r2=138050&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:13:48 2011
@@ -182,8 +182,15 @@
         ldr r1, [r5]
         ldr r2, [r6, #32]
         ldr r3, [r7, #124]
+        ldr r1, [sp]
+        ldr r2, [sp, #24]
+        ldr r3, [sp, #1020]
+
 
 @ CHECK: ldr	r1, [r5]                @ encoding: [0x29,0x68]
 @ CHECK: ldr	r2, [r6, #32]           @ encoding: [0x32,0x6a]
 @ CHECK: ldr	r3, [r7, #124]          @ encoding: [0xfb,0x6f]
+@ CHECK: ldr	r1, [sp]                @ encoding: [0x00,0x99]
+@ CHECK: ldr	r2, [sp, #24]           @ encoding: [0x06,0x9a]
+@ CHECK: ldr	r3, [sp, #1020]         @ encoding: [0xff,0x9b]
 



From tonic at nondot.org  Fri Aug 19 13:18:18 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 18:18:18 -0000
Subject: [llvm-commits] [www] r138051 - in /www/trunk/devmtg/2011-11: ./
	index.html
Message-ID: <20110819181818.2B0892A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 13:18:17 2011
New Revision: 138051

URL: http://llvm.org/viewvc/llvm-project?rev=138051&view=rev
Log:
2011 Dev Meeting.

Added:
    www/trunk/devmtg/2011-11/
    www/trunk/devmtg/2011-11/index.html

Added: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138051&view=auto
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (added)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 13:18:17 2011
@@ -0,0 +1,105 @@
+<!--#include virtual="../../header.incl" -->
+
+<div class="www_sectiontitle">2011 LLVM Developers' Meeting</div>
+<table>
+	<tr><td valign="top">
+<ol>
+        <li><a href="#registration">Registration</a></li>
+        <li><a href="#location">Location</a></li>
+	<li><a href="#agenda">Agenda</a></li>
+        <li><a href="#dinner">Dinner</a></li>
+</ol>
+</td><td>
+<ul>
+  <li><b>What</b>: The fifth general meeting of LLVM Developers and Users.
+  </li>
+  <li><b>Why</b>: To get acquainted, learn how LLVM is used, and exchange 
+  ideas.</li>
+  <li><b>When</b>: November 18, 2011</li>
+  <li><b>Where</b>: San Jose, CA</li>
+</ul>
+</td></tr></table>
+
+<p align="center"><h2><b>SPONSORED BY: <a href="http://www.qualcomm.com/quicinc/">QuIC</a>, <a href="http://apple.com">Apple</a></b></h2></p>
+
+<p>The meeting serves as a forum for <a href="http://llvm.org">LLVM</a>,
+<a href="http://clang.llvm.org">Clang</a>, <a href="http://lldb.llvm.org">LLDB</a> and 
+other LLVM project developers and users to get acquainted, learn how LLVM is used, and 
+exchange ideas about LLVM and its (potential) applications. More broadly, we
+believe the event will be of particular interest to the following people:</p>
+
+<ul>
+<li>Active developers of projects in the LLVM Umbrella
+(LLVM core, Clang, LLDB, libc++, compiler_rt, klee, dragonegg, etc).</li>
+<li>Anyone interested in using these as part of another project.</li>
+<li>Compiler, programming language, and runtime enthusiasts.</li>
+<li>Those interested in using compiler and toolchain technology in novel 
+and interesting ways.</li>
+</ul>
+
+We also invite you to sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">official Developer Meeting mailing list</a> to be kept informed of updates concerning the meeting:
+
+<div class="www_sectiontitle" id="registration">Registration</div>
+
+<p><b>Registration details coming soon.</b></p>
+
+<!--<p>Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.</p>
+--!>
+
+<div class="www_sectiontitle" id="registration">Location</div>
+<p>Details coming soon.</p>
+<!--<p>The LLVM Developers' Meeting is held at the San Jose Hilton. Attendees may park at the hotel ($19 day self park, $24 valet) or in the numerous parking lots downtown.</p>
+
+<p><a href="ihttp://www1.hilton.com/en_US/hi/hotel/SJCSHHF-Hilton-San-Jose-California/index.do?brand_id=HI&brand_directory=/en/hi/&xch=734956531,V5XM3XEGN4WB2CSGBIY222Q">Hilton San Jose</a><br> 
+300 Almaden Boulevard <br>
+San Jose, CA 95110<br>
+</p>
+
+<p>
+<b>Directions From San Jose Airport</b><br>
+(Approximately 8 mins)<br>
+<table border=0><tr><td>
+Head southeast on Terminal Dr toward Airport Pkwy.<br> 
+Continue onto Airport Blvd.<br>
+Continue onto Angelo Way.<br>
+Slight left at Airport Blvd.<br>
+Slight left to stay on Airport Blvd.<br> 
+Turn right to merge onto CA-87 S toward I-280/Downtown.<br>
+Take exit 6A for Park Ave toward San Carlos St/CA-82.<br>
+Turn left at Park Ave. Take the 1st right onto Woz Way.<br>
+Turn left at W San Carlos St.<br>
+Take the 1st right onto S Almaden Blvd.<br>
+Make U Turn - Destination on the right<br>
+</td><td valign=top><img src="LLVMHotelMap.jpg"></td></tr></table>
+</p>
+-->
+
+<div class="www_sectiontitle" id="agenda">Agenda</div>
+<p>We are looking for speakers for this year's meeting. Topics should include any of the LLVM family of projects or new uses of those projects. If you are interested in presenting at this year's LLVM Developers' Meeting, please submit your talk proposal to us by <b>September 15, 2011</b> via the website:
+<a href="">http://www.llvm.org/devmtg/talk.php</a></p>
+ 
+<p>
+There will be 3 classes of sessions
+<ul><li>Keynote</li>
+<li>Technical</li>
+<li>Birds-of-a-feather (BoF).</li>
+</ul> 
+</p>
+<p>For examples from last year???s meeting, visit the following:
+<a href="http://llvm.org/devmtg/2010-11/">http://llvm.org/devmtg/2010-11/</a>
+</p>
+<div class="www_sectiontitle" id="dinner">Dinner</div>
+<p>Details coming soon.</p>
+</p>
+
+<!-- *********************************************************************** -->
+<hr>
+<address>
+  <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+  src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
+  <a href="http://validator.w3.org/check/referer"><img
+  src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"></a>
+<br>
+</address>
+
+<!--#include virtual="../../footer.incl" -->



From grosbach at apple.com  Fri Aug 19 13:20:48 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 18:20:48 -0000
Subject: [llvm-commits] [llvm] r138052 - in /llvm/trunk:
 lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819182048.8B8BB2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 13:20:48 2011
New Revision: 138052

URL: http://llvm.org/viewvc/llvm-project?rev=138052&view=rev
Log:
Thumb assembly parsing and encoding for LDR(literal).

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=138052&r1=138051&r2=138052&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Fri Aug 19 13:20:48 2011
@@ -79,7 +79,7 @@
 { "fixup_arm_thumb_bl",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_blx",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_cp",      0,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bcc",     0,             8,  MCFixupKindInfo::FKF_IsPCRel },
 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
 { "fixup_arm_movt_hi16",     0,            20,  0 },

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138052&r1=138051&r2=138052&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:20:48 2011
@@ -194,3 +194,11 @@
 @ CHECK: ldr	r2, [sp, #24]           @ encoding: [0x06,0x9a]
 @ CHECK: ldr	r3, [sp, #1020]         @ encoding: [0xff,0x9b]
 
+
+ at ------------------------------------------------------------------------------
+@ LDR (literal)
+ at ------------------------------------------------------------------------------
+        ldr r1, _foo
+
+@ CHECK: ldr	r1, _foo                @ encoding: [A,0x49]
+             @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp



From scallanan at apple.com  Fri Aug 19 13:23:06 2011
From: scallanan at apple.com (Sean Callanan)
Date: Fri, 19 Aug 2011 18:23:06 -0000
Subject: [llvm-commits] [llvm] r138053 -
	/llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp
Message-ID: <20110819182306.B56C12A6C12C@llvm.org>

Author: spyffe
Date: Fri Aug 19 13:23:06 2011
New Revision: 138053

URL: http://llvm.org/viewvc/llvm-project?rev=138053&view=rev
Log:
Fixed a memory bug in the MCDisassembler where
MCParsedAsmOperand objects were being leaked.

Modified:
    llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp

Modified: llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp?rev=138053&r1=138052&r2=138053&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp Fri Aug 19 13:23:06 2011
@@ -93,8 +93,12 @@
   SmallVector<AsmToken, 10> asmTokens;
   
   if (disassembler.parseInst(parsedOperands, asmTokens, str))
+  {
+    for (unsigned i = 0, e = parsedOperands.size(); i != e; ++i)
+      delete parsedOperands[i];
     return -1;
-  
+  }
+      
   SmallVectorImpl<MCParsedAsmOperand*>::iterator operandIterator;
   unsigned int operandIndex;
   SmallVectorImpl<AsmToken>::iterator tokenIterator;



From grosbach at apple.com  Fri Aug 19 13:25:24 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 11:25:24 -0700
Subject: [llvm-commits] [www] r138051 - in /www/trunk/devmtg/2011-11: ./
 index.html
In-Reply-To: <20110819181818.2B0892A6C12C@llvm.org>
References: <20110819181818.2B0892A6C12C@llvm.org>
Message-ID: <528C77A5-70E4-4530-91BB-29770449A7C2@apple.com>


On Aug 19, 2011, at 11:18 AM, Tanya Lattner wrote:

> Author: tbrethou
> Date: Fri Aug 19 13:18:17 2011
> New Revision: 138051
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138051&view=rev
> Log:
> 2011 Dev Meeting.
> 
> Added:
>    www/trunk/devmtg/2011-11/
>    www/trunk/devmtg/2011-11/index.html
> 
> Added: www/trunk/devmtg/2011-11/index.html
> URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138051&view=auto
> ==============================================================================
> --- www/trunk/devmtg/2011-11/index.html (added)
> +++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 13:18:17 2011
> @@ -0,0 +1,105 @@
> +<!--#include virtual="../../header.incl" -->
> +
> +<div class="www_sectiontitle">2011 LLVM Developers' Meeting</div>
> +<table>
> +	<tr><td valign="top">
> +<ol>
> +        <li><a href="#registration">Registration</a></li>
> +        <li><a href="#location">Location</a></li>
> +	<li><a href="#agenda">Agenda</a></li>
> +        <li><a href="#dinner">Dinner</a></li>
> +</ol>
> +</td><td>
> +<ul>
> +  <li><b>What</b>: The fifth general meeting of LLVM Developers and Users.
> +  </li>
> +  <li><b>Why</b>: To get acquainted, learn how LLVM is used, and exchange 
> +  ideas.</li>
> +  <li><b>When</b>: November 18, 2011</li>
> +  <li><b>Where</b>: San Jose, CA</li>
> +</ul>
> +</td></tr></table>
> +
> +<p align="center"><h2><b>SPONSORED BY: <a href="http://www.qualcomm.com/quicinc/">QuIC</a>, <a href="http://apple.com">Apple</a></b></h2></p>
> +
> +<p>The meeting serves as a forum for <a href="http://llvm.org">LLVM</a>,
> +<a href="http://clang.llvm.org">Clang</a>, <a href="http://lldb.llvm.org">LLDB</a> and 
> +other LLVM project developers and users to get acquainted, learn how LLVM is used, and 
> +exchange ideas about LLVM and its (potential) applications. More broadly, we
> +believe the event will be of particular interest to the following people:</p>
> +
> +<ul>
> +<li>Active developers of projects in the LLVM Umbrella
> +(LLVM core, Clang, LLDB, libc++, compiler_rt, klee, dragonegg, etc).</li>
> +<li>Anyone interested in using these as part of another project.</li>
> +<li>Compiler, programming language, and runtime enthusiasts.</li>
> +<li>Those interested in using compiler and toolchain technology in novel 
> +and interesting ways.</li>
> +</ul>
> +
> +We also invite you to sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">official Developer Meeting mailing list</a> to be kept informed of updates concerning the meeting:
> +
> +<div class="www_sectiontitle" id="registration">Registration</div>
> +
> +<p><b>Registration details coming soon.</b></p>
> +
> +<!--<p>Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.</p>
> +--!>
> +
> +<div class="www_sectiontitle" id="registration">Location</div>
> +<p>Details coming soon.</p>
> +<!--<p>The LLVM Developers' Meeting is held at the San Jose Hilton. Attendees may park at the hotel ($19 day self park, $24 valet) or in the numerous parking lots downtown.</p>
> +
> +<p><a href="ihttp://www1.hilton.com/en_US/hi/hotel/SJCSHHF-Hilton-San-Jose-California/index.do?brand_id=HI&brand_directory=/en/hi/&xch=734956531,V5XM3XEGN4WB2CSGBIY222Q">Hilton San Jose</a><br> 
> +300 Almaden Boulevard <br>
> +San Jose, CA 95110<br>
> +</p>
> +
> +<p>
> +<b>Directions From San Jose Airport</b><br>
> +(Approximately 8 mins)<br>
> +<table border=0><tr><td>
> +Head southeast on Terminal Dr toward Airport Pkwy.<br> 
> +Continue onto Airport Blvd.<br>
> +Continue onto Angelo Way.<br>
> +Slight left at Airport Blvd.<br>
> +Slight left to stay on Airport Blvd.<br> 
> +Turn right to merge onto CA-87 S toward I-280/Downtown.<br>
> +Take exit 6A for Park Ave toward San Carlos St/CA-82.<br>
> +Turn left at Park Ave. Take the 1st right onto Woz Way.<br>
> +Turn left at W San Carlos St.<br>
> +Take the 1st right onto S Almaden Blvd.<br>
> +Make U Turn - Destination on the right<br>
> +</td><td valign=top><img src="LLVMHotelMap.jpg"></td></tr></table>
> +</p>
> +-->
> +
> +<div class="www_sectiontitle" id="agenda">Agenda</div>
> +<p>We are looking for speakers for this year's meeting. Topics should include any of the LLVM family of projects or new uses of those projects. If you are interested in presenting at this year's LLVM Developers' Meeting, please submit your talk proposal to us by <b>September 15, 2011</b> via the website:
> +<a href="">http://www.llvm.org/devmtg/talk.php</a></p>
> + 
> +<p>
> +There will be 3 classes of sessions
> +<ul><li>Keynote</li>
> +<li>Technical</li>
> +<li>Birds-of-a-feather (BoF).</li>
> +</ul> 
> +</p>
> +<p>For examples from last year???s meeting, visit the following:

Character encoding for apostrophe.

> +<a href="http://llvm.org/devmtg/2010-11/">http://llvm.org/devmtg/2010-11/</a>
> +</p>
> +<div class="www_sectiontitle" id="dinner">Dinner</div>
> +<p>Details coming soon.</p>
> +</p>
> +
> +<!-- *********************************************************************** -->
> +<hr>
> +<address>
> +  <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
> +  src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
> +  <a href="http://validator.w3.org/check/referer"><img
> +  src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"></a>
> +<br>
> +</address>
> +
> +<!--#include virtual="../../footer.incl" -->
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From tonic at nondot.org  Fri Aug 19 13:28:42 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 18:28:42 -0000
Subject: [llvm-commits] [www] r138054 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819182842.3F4952A6C12E@llvm.org>

Author: tbrethou
Date: Fri Aug 19 13:28:42 2011
New Revision: 138054

URL: http://llvm.org/viewvc/llvm-project?rev=138054&view=rev
Log:
Fix a couple typos.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138054&r1=138053&r2=138054&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 13:28:42 2011
@@ -44,7 +44,7 @@
 <p><b>Registration details coming soon.</b></p>
 
 <!--<p>Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.</p>
---!>
+-->
 
 <div class="www_sectiontitle" id="registration">Location</div>
 <p>Details coming soon.</p>
@@ -85,7 +85,7 @@
 <li>Birds-of-a-feather (BoF).</li>
 </ul> 
 </p>
-<p>For examples from last year???s meeting, visit the following:
+<p>For examples from last year's meeting, visit the following:
 <a href="http://llvm.org/devmtg/2010-11/">http://llvm.org/devmtg/2010-11/</a>
 </p>
 <div class="www_sectiontitle" id="dinner">Dinner</div>



From tonic at nondot.org  Fri Aug 19 13:31:47 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 18:31:47 -0000
Subject: [llvm-commits] [www] r138055 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819183147.6A60D2A6C12E@llvm.org>

Author: tbrethou
Date: Fri Aug 19 13:31:47 2011
New Revision: 138055

URL: http://llvm.org/viewvc/llvm-project?rev=138055&view=rev
Log:
Change permissions.

Modified:
    www/trunk/devmtg/2011-11/index.html   (props changed)

Propchange: www/trunk/devmtg/2011-11/index.html
------------------------------------------------------------------------------
    svn:executable = *



From grosbach at apple.com  Fri Aug 19 13:35:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 18:35:06 -0000
Subject: [llvm-commits] [llvm] r138056 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819183506.2B1C12A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 13:35:06 2011
New Revision: 138056

URL: http://llvm.org/viewvc/llvm-project?rev=138056&view=rev
Log:
Thumb assembly parsing and encoding for LDR(register).

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138056&r1=138055&r2=138056&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:35:06 2011
@@ -202,3 +202,11 @@
 
 @ CHECK: ldr	r1, _foo                @ encoding: [A,0x49]
              @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
+
+
+ at ------------------------------------------------------------------------------
+@ LDR (register)
+ at ------------------------------------------------------------------------------
+        ldr r1, [r2, r3]
+
+@ CHECK: ldr	r1, [r2, r3]            @ encoding: [0xd1,0x58]



From ggreif at gmail.com  Fri Aug 19 13:36:22 2011
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 19 Aug 2011 15:36:22 -0300
Subject: [llvm-commits] PR10663: remove
	DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS
In-Reply-To: <CANd1uZkoxjG4ryjLbAuFoJJw+i-6EDHOf_UN_i_4Dt+MvMVm1w@mail.gmail.com>
References: <CANd1uZkoxjG4ryjLbAuFoJJw+i-6EDHOf_UN_i_4Dt+MvMVm1w@mail.gmail.com>
Message-ID: <CAK-hX0mosTgndHp5exKAmY_y9ORrJ3tCL2eqi0mACi4Txcob+g@mail.gmail.com>

Hi Jay,

as I commented in the PR, I prefer not to remove DTCOA, because before
they were introduced ConstantArray::getOperand() also returned
Constant*, not Value*.
So in certain situations you could introduce pessimizations to LLVM
and even get compile errors in out-of-tree code, which reiles on a
subclass pointer being returned.

OTOH, changing DTOA to use cast_or_null just as DTCOA seems like a
consistent idea.

Just my 2 cents :-)

    Gabor


On 8/19/11, Jay Foad <jay.foad at gmail.com> wrote:
> http://llvm.org/bugs/show_bug.cgi?id=10663
>
> The only difference between DEFINE_TRANSPARENT_OPERAND_ACCESSORS and
> DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS seems to be in the way
> they cast the value returned from getOperand():
>
> - DTOA uses static_cast<>, which tolerates NULL operands
> - DTCOA uses cast<>, which asserts that the cast is safe, but doesn't
> tolerate NULL operands (hence the bug report)
>
> The attached patch simplifies this by removing DTCOA and changing DTOA
> to use cast_or_null<>, which gives the best of both worlds: it checks
> that the cast is safe, and allows NULL operands.
>
> Tested with "make all check-all", LLVM + Clang, and by manually
> running the test case from the PR. (I have no idea how to add this
> test case to the automatic test suite -- perhaps you could take care
> of that, Duncan?)
>
> OK to commit?
>
> Thanks,
> Jay.
>

From tonic at nondot.org  Fri Aug 19 13:35:24 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 18:35:24 -0000
Subject: [llvm-commits] [www] r138057 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819183524.65FB42A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 13:35:24 2011
New Revision: 138057

URL: http://llvm.org/viewvc/llvm-project?rev=138057&view=rev
Log:
Add sponsorship details.
More typos.
Remove bold.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138057&r1=138056&r2=138057&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 13:35:24 2011
@@ -22,6 +22,8 @@
 
 <p align="center"><h2><b>SPONSORED BY: <a href="http://www.qualcomm.com/quicinc/">QuIC</a>, <a href="http://apple.com">Apple</a></b></h2></p>
 
+<p>We are eager to find companies to help cover travel expenses for speakers needing assistance. If your company is interested, please contact dkipping at qualcomm.com.</p>
+
 <p>The meeting serves as a forum for <a href="http://llvm.org">LLVM</a>,
 <a href="http://clang.llvm.org">Clang</a>, <a href="http://lldb.llvm.org">LLDB</a> and 
 other LLVM project developers and users to get acquainted, learn how LLVM is used, and 
@@ -37,11 +39,11 @@
 and interesting ways.</li>
 </ul>
 
-We also invite you to sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">official Developer Meeting mailing list</a> to be kept informed of updates concerning the meeting:
+We also invite you to sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">official Developer Meeting mailing list</a> to be kept informed of updates concerning the meeting.
 
 <div class="www_sectiontitle" id="registration">Registration</div>
 
-<p><b>Registration details coming soon.</b></p>
+<p>Registration details coming soon.</p>
 
 <!--<p>Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.</p>
 -->



From tonic at nondot.org  Fri Aug 19 13:36:40 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 18:36:40 -0000
Subject: [llvm-commits] [www] r138058 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819183641.045B82A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 13:36:40 2011
New Revision: 138058

URL: http://llvm.org/viewvc/llvm-project?rev=138058&view=rev
Log:
Add link.
Fix paragraph.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138058&r1=138057&r2=138058&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 13:36:40 2011
@@ -38,9 +38,9 @@
 <li>Those interested in using compiler and toolchain technology in novel 
 and interesting ways.</li>
 </ul>
-
+<p>
 We also invite you to sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">official Developer Meeting mailing list</a> to be kept informed of updates concerning the meeting.
-
+</p>
 <div class="www_sectiontitle" id="registration">Registration</div>
 
 <p>Registration details coming soon.</p>
@@ -78,7 +78,7 @@
 
 <div class="www_sectiontitle" id="agenda">Agenda</div>
 <p>We are looking for speakers for this year's meeting. Topics should include any of the LLVM family of projects or new uses of those projects. If you are interested in presenting at this year's LLVM Developers' Meeting, please submit your talk proposal to us by <b>September 15, 2011</b> via the website:
-<a href="">http://www.llvm.org/devmtg/talk.php</a></p>
+<a href="http://www.llvm.org/devmtg/talk.php">http://www.llvm.org/devmtg/talk.php</a></p>
  
 <p>
 There will be 3 classes of sessions



From grosbach at apple.com  Fri Aug 19 13:49:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 18:49:59 -0000
Subject: [llvm-commits] [llvm] r138059 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819184959.5F8DA2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 13:49:59 2011
New Revision: 138059

URL: http://llvm.org/viewvc/llvm-project?rev=138059&view=rev
Log:
Thumb assembly parsing and encoding for LDRB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 13:49:59 2011
@@ -179,11 +179,13 @@
 
 // t_addrmode_is1 := reg + imm5
 //
+def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
 def t_addrmode_is1 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
   let EncoderMethod = "getAddrModeISOpValue";
   let DecoderMethod = "DecodeThumbAddrModeIS";
   let PrintMethod = "printThumbAddrModeImm5S1Operand";
+  let ParserMatchClass = t_addrmode_is1_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 13:49:59 2011
@@ -628,6 +628,15 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
   }
+  bool isMemThumbRIs1() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+        !isARMLowRegister(Mem.BaseRegNum))
+      return false;
+    // Immediate offset in range [0, 31].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 31;
+  }
   bool isMemThumbSPI() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
       return false;
@@ -1000,6 +1009,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:49:59 2011
@@ -210,3 +210,23 @@
         ldr r1, [r2, r3]
 
 @ CHECK: ldr	r1, [r2, r3]            @ encoding: [0xd1,0x58]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRB (immediate)
+ at ------------------------------------------------------------------------------
+        ldrb r4, [r3]
+        ldrb r5, [r6, #0]
+        ldrb r6, [r7, #31]
+
+@ CHECK: ldrb	r4, [r3]                @ encoding: [0x1c,0x78]
+@ CHECK: ldrb	r5, [r6]                @ encoding: [0x35,0x78]
+@ CHECK: ldrb	r6, [r7, #31]           @ encoding: [0xfe,0x7f]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRB (register)
+ at ------------------------------------------------------------------------------
+        ldrb r6, [r4, r5]
+
+@ CHECK: ldrb	r6, [r4, r5]            @ encoding: [0x66,0x5d]



From grosbach at apple.com  Fri Aug 19 13:55:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 18:55:51 -0000
Subject: [llvm-commits] [llvm] r138060 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819185551.F3D972A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 13:55:51 2011
New Revision: 138060

URL: http://llvm.org/viewvc/llvm-project?rev=138060&view=rev
Log:
Thumb assembly parsing and encoding for LDRH.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138060&r1=138059&r2=138060&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 13:55:51 2011
@@ -169,11 +169,13 @@
 
 // t_addrmode_is2 := reg + imm5 * 2
 //
+def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
 def t_addrmode_is2 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
   let EncoderMethod = "getAddrModeISOpValue";
   let DecoderMethod = "DecodeThumbAddrModeIS";
   let PrintMethod = "printThumbAddrModeImm5S2Operand";
+  let ParserMatchClass = t_addrmode_is2_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138060&r1=138059&r2=138060&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 13:55:51 2011
@@ -628,6 +628,15 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
   }
+  bool isMemThumbRIs2() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+        !isARMLowRegister(Mem.BaseRegNum))
+      return false;
+    // Immediate offset, multiple of 4 in range [0, 62].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
+  }
   bool isMemThumbRIs1() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0 ||
         !isARMLowRegister(Mem.BaseRegNum))
@@ -1009,6 +1018,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138060&r1=138059&r2=138060&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:55:51 2011
@@ -230,3 +230,23 @@
         ldrb r6, [r4, r5]
 
 @ CHECK: ldrb	r6, [r4, r5]            @ encoding: [0x66,0x5d]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRH (immediate)
+ at ------------------------------------------------------------------------------
+        ldrh r3, [r3]
+        ldrh r4, [r6, #2]
+        ldrh r5, [r7, #62]
+
+@ CHECK: ldrh	r3, [r3]                @ encoding: [0x1b,0x88]
+@ CHECK: ldrh	r4, [r6, #2]            @ encoding: [0x74,0x88]
+@ CHECK: ldrh	r5, [r7, #62]           @ encoding: [0xfd,0x8f]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRH (register)
+ at ------------------------------------------------------------------------------
+        ldrh r6, [r2, r6]
+
+@ CHECK: ldrh	r6, [r2, r6]            @ encoding: [0x96,0x5b]



From grosbach at apple.com  Fri Aug 19 14:17:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:17:58 -0000
Subject: [llvm-commits] [llvm] r138061 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819191758.C6EB52A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:17:58 2011
New Revision: 138061

URL: http://llvm.org/viewvc/llvm-project?rev=138061&view=rev
Log:
Thumb assembly parsing and encoding for LDRSB and LDRSH.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138061&r1=138060&r2=138061&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 14:17:58 2011
@@ -120,6 +120,7 @@
   let EncoderMethod = "getThumbAddrModeRegRegOpValue";
   let PrintMethod = "printThumbAddrModeRROperand";
   let DecoderMethod = "DecodeThumbAddrModeRR";
+  let ParserMatchClass = t_addrmode_rr_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
 }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138061&r1=138060&r2=138061&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 14:17:58 2011
@@ -250,3 +250,13 @@
         ldrh r6, [r2, r6]
 
 @ CHECK: ldrh	r6, [r2, r6]            @ encoding: [0x96,0x5b]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRSB/LDRSH
+ at ------------------------------------------------------------------------------
+        ldrsb r6, [r2, r6]
+        ldrsh r3, [r7, r1]
+
+@ CHECK: ldrsb	r6, [r2, r6]            @ encoding: [0x96,0x57]
+@ CHECK: ldrsh	r3, [r7, r1]            @ encoding: [0x7b,0x5e]



From grosbach at apple.com  Fri Aug 19 14:29:26 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:29:26 -0000
Subject: [llvm-commits] [llvm] r138063 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110819192926.2503E2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:29:25 2011
New Revision: 138063

URL: http://llvm.org/viewvc/llvm-project?rev=138063&view=rev
Log:
Thumb assembly parsing and encoding for LSL(immediate).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 14:29:25 2011
@@ -970,7 +970,7 @@
 
 // LSL immediate
 def tLSLri :                    // A8.6.88
-  T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
+  T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
                    IIC_iMOVsi,
                    "lsl", "\t$Rd, $Rm, $imm5",
                    [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 14:29:25 2011
@@ -2728,7 +2728,7 @@
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
-      Mnemonic != "umlals" && Mnemonic != "umulls") {
+      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") {
     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
       .Case("eq", ARMCC::EQ)
       .Case("ne", ARMCC::NE)

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 14:29:25 2011
@@ -260,3 +260,13 @@
 
 @ CHECK: ldrsb	r6, [r2, r6]            @ encoding: [0x96,0x57]
 @ CHECK: ldrsh	r3, [r7, r1]            @ encoding: [0x7b,0x5e]
+
+
+ at ------------------------------------------------------------------------------
+@ LSL (immediate)
+ at ------------------------------------------------------------------------------
+        lsls r4, r5, #0
+        lsls r4, r5, #4
+
+@ CHECK: lsls	r4, r5, #0              @ encoding: [0x2c,0x00]
+@ CHECK: lsls	r4, r5, #4              @ encoding: [0x2c,0x01]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 14:29:25 2011
@@ -49,3 +49,14 @@
 @ CHECK-ERRORS: error: writeback operator '!' expected
 @ CHECK-ERRORS:         ldm r2, {r5, r7}
 @ CHECK-ERRORS:             ^
+
+
+@ Out of range immediates for LSL instruction.
+        lsls r4, r5, #-1
+        lsls r4, r5, #32
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS:         lsls r4, r5, #-1
+@ CHECK-ERRORS:                      ^
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS:         lsls r4, r5, #32
+@ CHECK-ERRORS:                      ^



From grosbach at apple.com  Fri Aug 19 14:30:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:30:58 -0000
Subject: [llvm-commits] [llvm] r138064 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819193058.6BD302A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:30:58 2011
New Revision: 138064

URL: http://llvm.org/viewvc/llvm-project?rev=138064&view=rev
Log:
Thumb assembly parsing and encoding for LSL(register).

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138064&r1=138063&r2=138064&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 14:30:58 2011
@@ -270,3 +270,11 @@
 
 @ CHECK: lsls	r4, r5, #0              @ encoding: [0x2c,0x00]
 @ CHECK: lsls	r4, r5, #4              @ encoding: [0x2c,0x01]
+
+
+ at ------------------------------------------------------------------------------
+@ LSL (register)
+ at ------------------------------------------------------------------------------
+        lsls r2, r6
+
+@ CHECK: lsls	r2, r6                  @ encoding: [0xb2,0x40]



From grosbach at apple.com  Fri Aug 19 14:34:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:34:23 -0000
Subject: [llvm-commits] [llvm] r138065 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819193423.1FC9C2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:34:22 2011
New Revision: 138065

URL: http://llvm.org/viewvc/llvm-project?rev=138065&view=rev
Log:
Thumb assembly parsing and encoding for LSR.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138065&r1=138064&r2=138065&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 14:34:22 2011
@@ -278,3 +278,21 @@
         lsls r2, r6
 
 @ CHECK: lsls	r2, r6                  @ encoding: [0xb2,0x40]
+
+
+ at ------------------------------------------------------------------------------
+@ LSR (immediate)
+ at ------------------------------------------------------------------------------
+        lsrs r1, r3, #1
+        lsrs r1, r3, #32
+
+@ CHECK: lsrs	r1, r3, #1              @ encoding: [0x59,0x08]
+@ CHECK: lsrs	r1, r3, #32             @ encoding: [0x19,0x08]
+
+
+ at ------------------------------------------------------------------------------
+@ LSR (register)
+ at ------------------------------------------------------------------------------
+        lsrs r2, r6
+
+@ CHECK: lsrs	r2, r6                  @ encoding: [0xf2,0x40]



From grosbach at apple.com  Fri Aug 19 14:41:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:41:46 -0000
Subject: [llvm-commits] [llvm] r138066 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20110819194146.A9DB42A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:41:46 2011
New Revision: 138066

URL: http://llvm.org/viewvc/llvm-project?rev=138066&view=rev
Log:
Tab characters.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138066&r1=138065&r2=138066&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 19 14:41:46 2011
@@ -161,7 +161,7 @@
   let EncoderMethod = "getCCOutOpValue";
   let PrintMethod = "printSBitModifierOperand";
   let ParserMatchClass = CCOutOperand;
-	let DecoderMethod = "DecodeCCOutOperand";
+  let DecoderMethod = "DecodeCCOutOperand";
 }
 
 // Same as cc_out except it defaults to setting CPSR.
@@ -169,7 +169,7 @@
   let EncoderMethod = "getCCOutOpValue";
   let PrintMethod = "printSBitModifierOperand";
   let ParserMatchClass = CCOutOperand;
-	let DecoderMethod = "DecodeCCOutOperand";
+  let DecoderMethod = "DecodeCCOutOperand";
 }
 
 // ARM special operands for disassembly only.



From jay.foad at gmail.com  Fri Aug 19 14:44:44 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Fri, 19 Aug 2011 20:44:44 +0100
Subject: [llvm-commits] PR10663: remove
	DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS
In-Reply-To: <CAK-hX0mosTgndHp5exKAmY_y9ORrJ3tCL2eqi0mACi4Txcob+g@mail.gmail.com>
References: <CANd1uZkoxjG4ryjLbAuFoJJw+i-6EDHOf_UN_i_4Dt+MvMVm1w@mail.gmail.com>
	<CAK-hX0mosTgndHp5exKAmY_y9ORrJ3tCL2eqi0mACi4Txcob+g@mail.gmail.com>
Message-ID: <CANd1uZmL+CJL0_dhS6Gk1tkEtOQj4xg4tsq2A=uC8HZZju_BgQ@mail.gmail.com>

Hi Gabor,

On 19 August 2011 19:36, Gabor Greif <ggreif at gmail.com> wrote:
> as I commented in the PR, I prefer not to remove DTCOA, because before
> they were introduced ConstantArray::getOperand() also returned
> Constant*, not Value*.

With my patch, ConstantArray::getOperand() still returns Constant*.

Jay.

From grosbach at apple.com  Fri Aug 19 14:53:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 19:53:51 -0000
Subject: [llvm-commits] [llvm] r138067 -
	/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20110819195351.4D18F2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 14:53:51 2011
New Revision: 138067

URL: http://llvm.org/viewvc/llvm-project?rev=138067&view=rev
Log:
Tidy up. Formatting.

Modified:
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=138067&r1=138066&r2=138067&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Aug 19 14:53:51 2011
@@ -432,8 +432,8 @@
 
     if (!T.getRegisterClass(InstOpRec)
         .contains(T.getRegBank().getReg(ADI->getDef())))
-      throw TGError(Loc, "fixed register " +ADI->getDef()->getName()
-                    + " is not a member of the " + InstOpRec->getName() +
+      throw TGError(Loc, "fixed register " + ADI->getDef()->getName() +
+                    " is not a member of the " + InstOpRec->getName() +
                     " register class!");
 
     if (!Result->getArgName(AliasOpNo).empty())



From isanbard at gmail.com  Fri Aug 19 14:58:04 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 19 Aug 2011 12:58:04 -0700
Subject: [llvm-commits] [llvm] r138015 -
 /llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
In-Reply-To: <3A2A4B77-CA3B-440B-ADEE-1A614F39A72B@apple.com>
References: <20110819000922.341652A6C12C@llvm.org>
	<3A2A4B77-CA3B-440B-ADEE-1A614F39A72B@apple.com>
Message-ID: <6ABFEBF5-CF1D-465D-B15E-A4B24D49E26B@gmail.com>

Hi Jim,

I'm going to be looking at the SjLjEHPrepare pass today. I don't think it needs all of the logic that we have here. I.e., it doesn't need to update the analysis passes (I don't think). So I might be able to create a "SplitLandingPadCriticalEdge" function for that.

-bw

On Aug 19, 2011, at 9:29 AM, Jim Grosbach wrote:

> Hi Bill,
> 
> Does this logic will apply to the edge splitting in SjLjEHPrepare as well? If so, equivalent changes may need to be made there.
> 
> -Jim
> 
> On Aug 18, 2011, at 5:09 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Thu Aug 18 19:09:22 2011
>> New Revision: 138015
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=138015&view=rev
>> Log:
>> Intelligently split the landing pad block.
>> 
>> We have to be careful when splitting the landing pad block, because the
>> landingpad instruction is required to remain as the first non-PHI of an invoke's
>> unwind edge. To retain this, we split the block into two blocks, moving the
>> predecessors within the loop to one block and the remaining predecessors to the
>> other. The landingpad instruction is cloned into the new blocks.
>> 
>> Modified:
>>   llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
>> 
>> Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=138015&r1=138014&r2=138015&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Thu Aug 18 19:09:22 2011
>> @@ -410,13 +410,24 @@
>>  }
>> 
>>  assert(!LoopBlocks.empty() && "No edges coming in from outside the loop?");
>> -  BasicBlock *NewBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
>> -                                             LoopBlocks.size(), ".loopexit",
>> -                                             this);
>> +  BasicBlock *NewExitBB = 0;
>> +
>> +  if (Exit->isLandingPad()) {
>> +    SmallVector<BasicBlock*, 2> NewBBs;
>> +    SplitLandingPadPredecessors(Exit, ArrayRef<BasicBlock*>(&LoopBlocks[0],
>> +                                                            LoopBlocks.size()),
>> +                                ".loopexit", ".nonloopexit",
>> +                                this, NewBBs);
>> +    NewExitBB = NewBBs[0];
>> +  } else {
>> +    NewExitBB = SplitBlockPredecessors(Exit, &LoopBlocks[0],
>> +                                       LoopBlocks.size(), ".loopexit",
>> +                                       this);
>> +  }
>> 
>>  DEBUG(dbgs() << "LoopSimplify: Creating dedicated exit block "
>> -               << NewBB->getName() << "\n");
>> -  return NewBB;
>> +               << NewExitBB->getName() << "\n");
>> +  return NewExitBB;
>> }
>> 
>> /// AddBlockAndPredsToSet - Add the specified block, and all of its
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From nicholas at mxc.ca  Fri Aug 19 15:14:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 19 Aug 2011 20:14:27 -0000
Subject: [llvm-commits] [llvm] r138068 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Message-ID: <20110819201428.0164A2A6C12C@llvm.org>

Author: nicholas
Date: Fri Aug 19 15:14:27 2011
New Revision: 138068

URL: http://llvm.org/viewvc/llvm-project?rev=138068&view=rev
Log:
This is not actually unreachable, so don't use llvm_unreachable for it. Since
the intent seems to be to terminate even in Release builds, just use abort()
directly.

If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is
#define'd to on newer GCCs) then the program is undefined.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=138068&r1=138067&r2=138068&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Aug 19 15:14:27 2011
@@ -43,8 +43,9 @@
     dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
     N->dump(&DAG);
     dbgs() << "\n";
+    dbgs() << "Do not know how to scalarize the result of this operator!\n";
 #endif
-    llvm_unreachable("Do not know how to scalarize the result of this operator!");
+    abort();
 
   case ISD::BITCAST:           R = ScalarizeVecRes_BITCAST(N); break;
   case ISD::BUILD_VECTOR:      R = N->getOperand(0); break;



From eli.friedman at gmail.com  Fri Aug 19 15:21:47 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 19 Aug 2011 13:21:47 -0700
Subject: [llvm-commits] [llvm] r138068 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
In-Reply-To: <20110819201428.0164A2A6C12C@llvm.org>
References: <20110819201428.0164A2A6C12C@llvm.org>
Message-ID: <CAJdarcG8-E_4_0maxnkoUaAHjWoY72LWbJ5k6mv-u-xjXYLwTA@mail.gmail.com>

On Fri, Aug 19, 2011 at 1:14 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Fri Aug 19 15:14:27 2011
> New Revision: 138068
>
> URL: http://llvm.org/viewvc/llvm-project?rev=138068&view=rev
> Log:
> This is not actually unreachable, so don't use llvm_unreachable for it. Since
> the intent seems to be to terminate even in Release builds, just use abort()
> directly.

report_fatal_error() is preferred over calling abort() directly.

-Eli

> If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is
> #define'd to on newer GCCs) then the program is undefined.
>
> Modified:
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=138068&r1=138067&r2=138068&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Aug 19 15:14:27 2011
> @@ -43,8 +43,9 @@
> ? ? dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
> ? ? N->dump(&DAG);
> ? ? dbgs() << "\n";
> + ? ?dbgs() << "Do not know how to scalarize the result of this operator!\n";
> ?#endif
> - ? ?llvm_unreachable("Do not know how to scalarize the result of this operator!");
> + ? ?abort();
>
> ? case ISD::BITCAST: ? ? ? ? ? R = ScalarizeVecRes_BITCAST(N); break;
> ? case ISD::BUILD_VECTOR: ? ? ?R = N->getOperand(0); break;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From ggreif at gmail.com  Fri Aug 19 15:25:19 2011
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 19 Aug 2011 17:25:19 -0300
Subject: [llvm-commits] PR10663: remove
	DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS
In-Reply-To: <CANd1uZmL+CJL0_dhS6Gk1tkEtOQj4xg4tsq2A=uC8HZZju_BgQ@mail.gmail.com>
References: <CANd1uZkoxjG4ryjLbAuFoJJw+i-6EDHOf_UN_i_4Dt+MvMVm1w@mail.gmail.com>
	<CAK-hX0mosTgndHp5exKAmY_y9ORrJ3tCL2eqi0mACi4Txcob+g@mail.gmail.com>
	<CANd1uZmL+CJL0_dhS6Gk1tkEtOQj4xg4tsq2A=uC8HZZju_BgQ@mail.gmail.com>
Message-ID: <CAK-hX0nPqEQrefr5uNSE-8X53dj+kkzUiAPngqYoC7kT0Qr1nA@mail.gmail.com>

Ahhhh, I guess I see:
you did not touch the DECLARE_* macros, but eliminated the redundant
DEFINE_T_CASTED_O_A one. I guess this is fine with me :-)

Cheers,

    Gabor


On 8/19/11, Jay Foad <jay.foad at gmail.com> wrote:
> Hi Gabor,
>
> On 19 August 2011 19:36, Gabor Greif <ggreif at gmail.com> wrote:
>> as I commented in the PR, I prefer not to remove DTCOA, because before
>> they were introduced ConstantArray::getOperand() also returned
>> Constant*, not Value*.
>
> With my patch, ConstantArray::getOperand() still returns Constant*.
>
> Jay.
>

From criswell at uiuc.edu  Fri Aug 19 15:26:00 2011
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 19 Aug 2011 20:26:00 -0000
Subject: [llvm-commits] [poolalloc] r138069 -
	/poolalloc/trunk/lib/DSA/Local.cpp
Message-ID: <20110819202600.909DF2A6C12C@llvm.org>

Author: criswell
Date: Fri Aug 19 15:26:00 2011
New Revision: 138069

URL: http://llvm.org/viewvc/llvm-project?rev=138069&view=rev
Log:
Added support for the memory use marker intrinsics:
llvm.lifetime.start
llvm.lifetime.end
llvm.invariant.start
llvm.invariant.end

Modified:
    poolalloc/trunk/lib/DSA/Local.cpp

Modified: poolalloc/trunk/lib/DSA/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=138069&r1=138068&r2=138069&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Local.cpp (original)
+++ poolalloc/trunk/lib/DSA/Local.cpp Fri Aug 19 15:26:00 2011
@@ -812,7 +812,20 @@
   N->setModifiedMarker()->setVAStartMarker();
 }
 
-/// returns true if the intrinsic is handled
+///
+/// Method: visitIntrinsic()
+///
+/// Description:
+///   Generate correct DSNodes for calls to LLVM intrinsic functions.
+///
+/// Inputs:
+///   CS - The CallSite representing the call or invoke to the intrinsic.
+///   F  - A pointer to the function called by the call site.
+///
+/// Return value:
+///   true  - This intrinsic is properly handled by this method.
+///   false - This intrinsic is not recognized by DSA.
+///
 bool GraphBuilder::visitIntrinsic(CallSite CS, Function *F) {
   ++NumIntrinsicCall;
   switch (F->getIntrinsicID()) {
@@ -942,6 +955,13 @@
     return true;
   }
 
+  // Process lifetime intrinsics
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end:
+  case Intrinsic::invariant_start:
+  case Intrinsic::invariant_end:
+    return true;
+
   default: {
     //ignore pointer free intrinsics
     if (!isa<PointerType>(F->getReturnType())) {



From grosbach at apple.com  Fri Aug 19 15:30:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 20:30:19 -0000
Subject: [llvm-commits] [llvm] r138072 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20110819203019.B059E2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 15:30:19 2011
New Revision: 138072

URL: http://llvm.org/viewvc/llvm-project?rev=138072&view=rev
Log:
Tidy up. Tab character.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138072&r1=138071&r2=138072&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 19 15:30:19 2011
@@ -152,7 +152,7 @@
                                      (ops (i32 14), (i32 zero_reg))> {
   let PrintMethod = "printPredicateOperand";
   let ParserMatchClass = CondCodeOperand;
-	let DecoderMethod = "DecodePredicateOperand";
+  let DecoderMethod = "DecodePredicateOperand";
 }
 
 // Conditional code result for instructions whose 's' bit is set, e.g. subs.



From grosbach at apple.com  Fri Aug 19 15:33:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 20:33:06 -0000
Subject: [llvm-commits] [llvm] r138073 -
	/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20110819203306.76E922A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 15:33:06 2011
New Revision: 138073

URL: http://llvm.org/viewvc/llvm-project?rev=138073&view=rev
Log:
Allow non zero_reg explicit values for OptionalDefOperands in aliases.

Modified:
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=138073&r1=138072&r2=138073&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Aug 19 15:33:06 2011
@@ -424,6 +424,13 @@
 
   // Handle explicit registers.
   if (ADI && ADI->getDef()->isSubClassOf("Register")) {
+    if (InstOpRec->isSubClassOf("OptionalDefOperand")) {
+      DagInit *DI = InstOpRec->getValueAsDag("MIOperandInfo");
+      // The operand info should only have a single (register) entry. We
+      // want the register class of it.
+      InstOpRec = dynamic_cast<DefInit*>(DI->getArg(0))->getDef();
+    }
+
     if (InstOpRec->isSubClassOf("RegisterOperand"))
       InstOpRec = InstOpRec->getValueAsDef("RegClass");
 



From grosbach at apple.com  Fri Aug 19 15:46:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 20:46:54 -0000
Subject: [llvm-commits] [llvm] r138076 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrThumb.td
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110819204654.ADD7A2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 15:46:54 2011
New Revision: 138076

URL: http://llvm.org/viewvc/llvm-project?rev=138076&view=rev
Log:
Thumb assembly parsing and encoding for MOV.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138076&r1=138075&r2=138076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Aug 19 15:46:54 2011
@@ -148,7 +148,7 @@
 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
 // register whose default is 0 (no register).
 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
-def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
+def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
                                      (ops (i32 14), (i32 zero_reg))> {
   let PrintMethod = "printPredicateOperand";
   let ParserMatchClass = CondCodeOperand;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138076&r1=138075&r2=138076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 15:46:54 2011
@@ -1014,6 +1014,11 @@
   let Inst{10-8} = Rd;
   let Inst{7-0}  = imm8;
 }
+// Because we have an explicit tMOVSr below, we need an alias to handle
+// the immediate "movs" form here. Blech.
+def : InstAlias <"movs $Rdn, $imm",
+                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
+        Requires<[IsThumb]>;
 
 // A7-73: MOV(2) - mov setting flag.
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138076&r1=138075&r2=138076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 15:46:54 2011
@@ -3173,7 +3173,7 @@
            isARMLowRegister(Inst.getOperand(2).getReg()))
     return Match_RequiresThumb2;
   // Others only require ARMv6 or later.
-  else if (Opc == ARM::tMOVr && isThumbOne() &&
+  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
            isARMLowRegister(Inst.getOperand(0).getReg()) &&
            isARMLowRegister(Inst.getOperand(1).getReg()))
     return Match_RequiresV6;

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138076&r1=138075&r2=138076&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 15:46:54 2011
@@ -296,3 +296,25 @@
         lsrs r2, r6
 
 @ CHECK: lsrs	r2, r6                  @ encoding: [0xf2,0x40]
+
+
+ at ------------------------------------------------------------------------------
+@ MOV (immediate)
+ at ------------------------------------------------------------------------------
+        movs r2, #0
+        movs r2, #255
+        movs r2, #23
+
+@ CHECK: movs	r2, #0                  @ encoding: [0x00,0x22]
+@ CHECK: movs	r2, #255                @ encoding: [0xff,0x22]
+@ CHECK: movs	r2, #23                 @ encoding: [0x17,0x22]
+
+
+ at ------------------------------------------------------------------------------
+@ MOV (register)
+ at ------------------------------------------------------------------------------
+        mov r3, r4
+        movs r1, r3
+
+@ CHECK: mov	r3, r4                  @ encoding: [0x23,0x46]
+@ CHECK: movs	r1, r3                  @ encoding: [0x19,0x00]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138076&r1=138075&r2=138076&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 15:46:54 2011
@@ -1,5 +1,7 @@
 @ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
 @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
 
 @ Check for various assembly diagnostic messages on invalid input.
 
@@ -15,9 +17,9 @@
 @ CHECK-ERRORS: error: instruction variant requires Thumb2
 @ CHECK-ERRORS:         add r2, r3
 @ CHECK-ERRORS:         ^
-@ CHECK-ERRORS: error: instruction variant requires ARMv6 or later
-@ CHECK-ERRORS:         mov r2, r3
-@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
+@ CHECK-ERRORS-V5:         mov r2, r3
+@ CHECK-ERRORS-V5:         ^
 
 
 @ Out of range immediates for ASR instruction.



From grosbach at apple.com  Fri Aug 19 15:48:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 20:48:54 -0000
Subject: [llvm-commits] [llvm] r138077 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819204854.683D92A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 15:48:54 2011
New Revision: 138077

URL: http://llvm.org/viewvc/llvm-project?rev=138077&view=rev
Log:
Add FIXME.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138077&r1=138076&r2=138077&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 15:48:54 2011
@@ -8,6 +8,9 @@
 @ This gives us good coverage while keeping the overall size of the test
 @ more reasonable.
 
+
+@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax.
+
 _func:
 @ CHECK: _func
 



From echristo at apple.com  Fri Aug 19 16:21:14 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:14 -0000
Subject: [llvm-commits] [llvm] r138082 -
	/llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp
Message-ID: <20110819212114.CB4182A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:14 2011
New Revision: 138082

URL: http://llvm.org/viewvc/llvm-project?rev=138082&view=rev
Log:
Move 2010-03-22-empty-baseclass.cpp from a frontend+opt test to just
an opt test.

Removed:
    llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp

Removed: llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-03-22-empty-baseclass.cpp?rev=138081&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp (removed)
@@ -1,134 +0,0 @@
-// RUN: %llvmgxx -S %s -o - -O2 | FileCheck %s
-namespace boost {
-  namespace detail {
-    template <typename T> struct cv_traits_imp {};
-    template <typename T> struct cv_traits_imp<T*> {typedef T unqualified_type;};
-  }
-}
-namespace mpl_ {}
-namespace boost {
-  namespace mpl {using namespace mpl_;}
-  template< typename T > struct remove_cv {typedef typename boost::detail::cv_traits_imp<T*>::unqualified_type type;};
-  namespace type_traits {
-    typedef char yes_type;
-    struct no_type {char padding[8];};
-  }
-}
-namespace mpl_ {
-  template< bool C_ > struct bool_;
-  typedef bool_<true> true_;
-  typedef bool_<false> false_;
-  template< bool C_ > struct bool_ {static const bool value = C_;};
-  template< typename T, T N > struct integral_c;
-}
-namespace boost{
-  template <class T, T val>   struct integral_constant :
-    public mpl::integral_c<T, val> {};
-  template<> struct integral_constant<bool,true> : public mpl::true_ {};
-  template<> struct integral_constant<bool,false> : public mpl::false_ {};
-  namespace type_traits {
-    template <bool b1, bool b2, bool b3 = false, bool b4 = false,
-              bool b5 = false, bool b6 = false, bool b7 = false> struct ice_or;
-    template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7>
-    struct ice_or {static const bool value = true; };
-    template <> struct ice_or<false, false, false, false, false, false, false>
-    {static const bool value = false;};
-    template <bool b1, bool b2, bool b3 = true, bool b4 = true, bool b5 = true,
-              bool b6 = true, bool b7 = true> struct ice_and;
-    template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7>
-    struct ice_and {static const bool value = false;};
-    template <> struct ice_and<true, true, true, true, true, true, true>
-    {static const bool value = true;};
-    template <bool b> struct ice_not {static const bool value = true;};
-  };
-  namespace detail {
-    template <typename T> struct is_union_impl {static const bool value = false;};
-  }
-  template< typename T > struct is_union :
-  ::boost::integral_constant<bool, ::boost::detail::is_union_impl<T>::value> {};
-  namespace detail {
-    template <class U> ::boost::type_traits::yes_type is_class_tester(void(U::*)(void));
-    template <class U> ::boost::type_traits::no_type is_class_tester(...);
-    template <typename T> struct is_class_impl {
-      static const bool value = (::boost::type_traits::ice_and< sizeof(is_class_tester<T>(0))
-                                 == sizeof(::boost::type_traits::yes_type),
-                                 ::boost::type_traits::ice_not< ::boost::is_union<T>::value >::value >::value);};
-}
-  template<typename T> struct is_class:
-  ::boost::integral_constant<bool,::boost::detail::is_class_impl<T>::value> {  };
-namespace detail {
-  template <typename T> struct empty_helper_t1: public T {int i[256];};
-  struct empty_helper_t2 {int i[256];};
-  template <typename T, bool is_a_class = false> struct empty_helper
-  {static const bool value = false;};
-  template <typename T> struct empty_helper<T, true>
-  {static const bool value = (sizeof(empty_helper_t1<T>) == sizeof(empty_helper_t2));};
-  template <typename T> struct is_empty_impl {
-    typedef typename remove_cv<T>::type cvt;
-    static const bool value = (::boost::type_traits::ice_or< ::boost::detail::empty_helper
-                               <cvt,::boost::is_class<T>::value>::value, false>::value);
-  };
-}
-template<typename T> struct is_empty:
-::boost::integral_constant<bool,::boost::detail::is_empty_impl<T>::value> {};
-template<typename T, typename U > struct is_same:
-::boost::integral_constant<bool,false> {};
-template<typename T> struct call_traits {typedef T& reference;};
-namespace details {
-  template <class T1, class T2, bool IsSame, bool FirstEmpty, bool SecondEmpty>
-  struct compressed_pair_switch;
-  template <class T1, class T2>
-  struct compressed_pair_switch<T1, T2, false, true, false>
-  {static const int value = 1;};
-  template <class T1, class T2, int Version> class compressed_pair_imp;
-  template <class T1, class T2> class compressed_pair_imp<T1, T2, 1>:
-  protected ::boost::remove_cv<T1>::type {
-  public:
-    typedef T1 first_type;
-    typedef T2 second_type;
-    typedef typename call_traits<first_type>::reference first_reference;
-    typedef typename call_traits<second_type>::reference second_reference;
-    first_reference first() {return *this;}
-    second_reference second() {return second_;}
-    second_type second_;
-  };
-}
-template <class T1, class T2> class compressed_pair:
-  private ::boost::details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch<
-                                                          T1, T2, ::boost::is_same<typename remove_cv<T1>::type,
-                                                                                   typename remove_cv<T2>::type>::value,
-                                                          ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value>
-  {
-  private:
-    typedef details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch<
-                                                   T1, T2, ::boost::is_same<typename remove_cv<T1>::type,
-                                                                            typename remove_cv<T2>::type>::value,
-                                                                              ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value> base;
-  public:
-    typedef T1 first_type;
-    typedef T2 second_type;
-    typedef typename call_traits<first_type>::reference first_reference;
-    typedef typename call_traits<second_type>::reference second_reference;
-    first_reference first() {return base::first();}
-    second_reference second() {return base::second();}
-  };
-}
-struct empty_base_t {};
-struct empty_t : empty_base_t {};
-typedef boost::compressed_pair<empty_t, int> data_t;
-extern "C" {int printf(const char * , ...);}
-extern "C" {void abort(void);}
-int main (int argc, char * const argv[]) {
-  data_t x;
-  x.second() = -3;
-  // This store should be elided:
-  x.first() = empty_t();
-  // If x.second() has been clobbered by the elided store, fail.
-  if (x.second() != -3) {
-    printf("x.second() was clobbered\n");
-    // CHECK-NOT: x.second() was clobbered
-    abort();
-  }
-  return 0;
-}
-// CHECK: ret i32



From echristo at apple.com  Fri Aug 19 16:21:20 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:20 -0000
Subject: [llvm-commits] [llvm] r138083 -
 /llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
Message-ID: <20110819212120.41EB52A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:20 2011
New Revision: 138083

URL: http://llvm.org/viewvc/llvm-project?rev=138083&view=rev
Log:
Add file.

Added:
    llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll

Added: llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll?rev=138083&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll (added)
+++ llvm/trunk/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll Fri Aug 19 16:21:20 2011
@@ -0,0 +1,162 @@
+; RUN: opt -O2 %s -S -o - | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin11.1"
+
+%"struct.boost::compressed_pair<empty_t,int>" = type { %"struct.boost::details::compressed_pair_imp<empty_t,int,1>" }
+%"struct.boost::details::compressed_pair_imp<empty_t,int,1>" = type { i32 }
+%struct.empty_base_t = type <{ i8 }>
+%struct.empty_t = type <{ i8 }>
+
+ at .str = private constant [25 x i8] c"x.second() was clobbered\00", align 1 ; <[25 x i8]*> [#uses=1]
+
+define i32 @main(i32 %argc, i8** %argv) ssp {
+entry:
+  %argc_addr = alloca i32, align 4                ; <i32*> [#uses=1]
+  %argv_addr = alloca i8**, align 8               ; <i8***> [#uses=1]
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %retval.1 = alloca i8                           ; <i8*> [#uses=2]
+  %1 = alloca %struct.empty_base_t                ; <%struct.empty_base_t*> [#uses=1]
+  %2 = alloca %struct.empty_base_t*               ; <%struct.empty_base_t**> [#uses=1]
+  %x = alloca %"struct.boost::compressed_pair<empty_t,int>" ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=3]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 %argc, i32* %argc_addr
+  store i8** %argv, i8*** %argv_addr
+  %3 = call i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <i32*> [#uses=1]
+  store i32 -3, i32* %3, align 4
+  %4 = call %struct.empty_base_t* @_ZN5boost15compressed_pairI7empty_tiE5firstEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <%struct.empty_base_t*> [#uses=1]
+  store %struct.empty_base_t* %4, %struct.empty_base_t** %2, align 8
+  call void @_ZN7empty_tC1Ev(%struct.empty_base_t* %1) nounwind
+  %5 = call i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <i32*> [#uses=1]
+  %6 = load i32* %5, align 4                      ; <i32> [#uses=1]
+  %7 = icmp ne i32 %6, -3                         ; <i1> [#uses=1]
+  %8 = zext i1 %7 to i8                           ; <i8> [#uses=1]
+  store i8 %8, i8* %retval.1, align 1
+  %9 = load i8* %retval.1, align 1                ; <i8> [#uses=1]
+  %toBool = icmp ne i8 %9, 0                      ; <i1> [#uses=1]
+  br i1 %toBool, label %bb, label %bb1
+
+bb:                                               ; preds = %entry
+  %10 = call i32 @puts(i8* getelementptr inbounds ([25 x i8]* @.str, i64 0, i64 0)) ; <i32> [#uses=0]
+  call void @abort() noreturn
+  unreachable
+
+bb1:                                              ; preds = %entry
+  store i32 0, i32* %0, align 4
+  %11 = load i32* %0, align 4                     ; <i32> [#uses=1]
+  store i32 %11, i32* %retval, align 4
+  br label %return
+
+; CHECK-NOT: x.second() was clobbered
+; CHECK: ret i32
+return:                                           ; preds = %bb1
+  %retval2 = load i32* %retval                    ; <i32> [#uses=1]
+  ret i32 %retval2
+}
+
+define linkonce_odr void @_ZN12empty_base_tC2Ev(%struct.empty_base_t* %this) nounwind ssp align 2 {
+entry:
+  %this_addr = alloca %struct.empty_base_t*, align 8 ; <%struct.empty_base_t**> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %struct.empty_base_t* %this, %struct.empty_base_t** %this_addr
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define linkonce_odr void @_ZN7empty_tC1Ev(%struct.empty_base_t* %this) nounwind ssp align 2 {
+entry:
+  %this_addr = alloca %struct.empty_base_t*, align 8 ; <%struct.empty_base_t**> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %struct.empty_base_t* %this, %struct.empty_base_t** %this_addr
+  %0 = load %struct.empty_base_t** %this_addr, align 8 ; <%struct.empty_base_t*> [#uses=1]
+  call void @_ZN12empty_base_tC2Ev(%struct.empty_base_t* %0) nounwind
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define linkonce_odr i32* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this) nounwind ssp align 2 {
+entry:
+  %this_addr = alloca %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"**> [#uses=2]
+  %retval = alloca i32*                           ; <i32**> [#uses=2]
+  %0 = alloca i32*                                ; <i32**> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
+  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32* %2, i32** %0, align 8
+  %3 = load i32** %0, align 8                     ; <i32*> [#uses=1]
+  store i32* %3, i32** %retval, align 8
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}
+
+define linkonce_odr i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %this) ssp align 2 {
+entry:
+  %this_addr = alloca %"struct.boost::compressed_pair<empty_t,int>"*, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"**> [#uses=2]
+  %retval = alloca i32*                           ; <i32**> [#uses=2]
+  %0 = alloca i32*                                ; <i32**> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
+  %1 = load %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %3 = call i32* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <i32*> [#uses=1]
+  store i32* %3, i32** %0, align 8
+  %4 = load i32** %0, align 8                     ; <i32*> [#uses=1]
+  store i32* %4, i32** %retval, align 8
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}
+
+define linkonce_odr %struct.empty_base_t* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this) nounwind ssp align 2 {
+entry:
+  %this_addr = alloca %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"**> [#uses=2]
+  %retval = alloca %struct.empty_base_t*          ; <%struct.empty_base_t**> [#uses=2]
+  %0 = alloca %struct.empty_base_t*               ; <%struct.empty_base_t**> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
+  %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %2 = bitcast %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1 to %struct.empty_base_t* ; <%struct.empty_base_t*> [#uses=1]
+  store %struct.empty_base_t* %2, %struct.empty_base_t** %0, align 8
+  %3 = load %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
+  store %struct.empty_base_t* %3, %struct.empty_base_t** %retval, align 8
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
+  ret %struct.empty_base_t* %retval1
+}
+
+define linkonce_odr %struct.empty_base_t* @_ZN5boost15compressed_pairI7empty_tiE5firstEv(%"struct.boost::compressed_pair<empty_t,int>"* %this) ssp align 2 {
+entry:
+  %this_addr = alloca %"struct.boost::compressed_pair<empty_t,int>"*, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"**> [#uses=2]
+  %retval = alloca %struct.empty_base_t*          ; <%struct.empty_base_t**> [#uses=2]
+  %0 = alloca %struct.empty_base_t*               ; <%struct.empty_base_t**> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
+  %1 = load %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
+  %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
+  %3 = call %struct.empty_base_t* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <%struct.empty_base_t*> [#uses=1]
+  store %struct.empty_base_t* %3, %struct.empty_base_t** %0, align 8
+  %4 = load %struct.empty_base_t** %0, align 8    ; <%struct.empty_base_t*> [#uses=1]
+  store %struct.empty_base_t* %4, %struct.empty_base_t** %retval, align 8
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load %struct.empty_base_t** %retval  ; <%struct.empty_base_t*> [#uses=1]
+  ret %struct.empty_base_t* %retval1
+}
+
+declare i32 @puts(i8*)
+
+declare void @abort() noreturn



From echristo at apple.com  Fri Aug 19 16:21:22 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:22 -0000
Subject: [llvm-commits] [llvm] r138084 -
	/llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
Message-ID: <20110819212122.20FCA2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:21 2011
New Revision: 138084

URL: http://llvm.org/viewvc/llvm-project?rev=138084&view=rev
Log:
Remove this test. There are other, duplicates, in the clang test suite.

Removed:
    llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp

Removed: llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-02-17-DbgArtificialArg.cpp?rev=138083&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp (removed)
@@ -1,21 +0,0 @@
-// RUN: %llvmgcc -g -S %s -dA -fverbose-asm -o %t
-// RUN: llc -asm-verbose < %t | FileCheck %s
-// Test to artificial attribute attahed to "this" pointer type.
-// Radar 7655792 and 7655002
-
-class A {
-public:
-  int fn1(int i) const { return i + 2; };
-};
-
-int foo() {
-  A a;
-//CHECK:        .ascii   "this"                 ## DW_AT_name
-//CHECK-NEXT:        .byte   0
-//CHECK-NEXT:        ## DW_AT_decl_file
-//CHECK-NEXT:        ## DW_AT_decl_line
-//CHECK-NEXT:        ## DW_AT_type
-//CHECK-NEXT:        ## DW_AT_artificial
-
-  return a.fn1(1);
-}



From echristo at apple.com  Fri Aug 19 16:21:24 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:24 -0000
Subject: [llvm-commits] [llvm] r138085 -
	/llvm/trunk/test/FrontendC++/2009-12-23-MissingSext.cpp
Message-ID: <20110819212124.3D96C2A6C12E@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:24 2011
New Revision: 138085

URL: http://llvm.org/viewvc/llvm-project?rev=138085&view=rev
Log:
Remove migrated test.

Removed:
    llvm/trunk/test/FrontendC++/2009-12-23-MissingSext.cpp

Removed: llvm/trunk/test/FrontendC++/2009-12-23-MissingSext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-12-23-MissingSext.cpp?rev=138084&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-12-23-MissingSext.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-12-23-MissingSext.cpp (removed)
@@ -1,16 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | FileCheck %s
-// The store of p.y into the temporary was not
-// getting extended to 32 bits, so uninitialized
-// bits of the temporary were used.  7366161.
-struct foo {
-  char x:8;
-  signed int y:24;
-};
-int bar(struct foo p, int x) {
-// CHECK: bar
-// CHECK: sext
-// CHECK: sext
-  x = (p.y > x ? x : p.y);
-  return x;
-// CHECK: return
-}



From echristo at apple.com  Fri Aug 19 16:21:26 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:26 -0000
Subject: [llvm-commits] [llvm] r138086 - in /llvm/trunk/test/FrontendC++:
 2009-09-09-packed-layout.cpp 2009-10-27-crash.cpp
Message-ID: <20110819212126.4E8332A6C12F@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:26 2011
New Revision: 138086

URL: http://llvm.org/viewvc/llvm-project?rev=138086&view=rev
Log:
Remove migrated tests.

Removed:
    llvm/trunk/test/FrontendC++/2009-09-09-packed-layout.cpp
    llvm/trunk/test/FrontendC++/2009-10-27-crash.cpp

Removed: llvm/trunk/test/FrontendC++/2009-09-09-packed-layout.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-09-09-packed-layout.cpp?rev=138085&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-09-09-packed-layout.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-09-09-packed-layout.cpp (removed)
@@ -1,18 +0,0 @@
-// RUN: %llvmgxx -S -m32 %s -o /dev/null
-class X { 
- public:
-  virtual ~X();
-  short y;
-};
-#pragma pack(push, 1)
-class Z : public X {
- public: enum { foo = ('x') };
- virtual int y() const;
-};
-#pragma pack(pop)
-class Y : public X {
-public: enum { foo = ('y'), bar = 0 };
-};
-X x;
-Y y;
-Z z;

Removed: llvm/trunk/test/FrontendC++/2009-10-27-crash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-10-27-crash.cpp?rev=138085&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-10-27-crash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-10-27-crash.cpp (removed)
@@ -1,43 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-// Radar 7328944
-
-typedef struct
-{
-	unsigned short a : 1;
-	unsigned short b : 2;
-	unsigned short c : 1;
-	unsigned short d : 1;
-	unsigned short e : 1;
-	unsigned short f : 1;
-	unsigned short g : 2;
-	unsigned short : 7;
-	union
-	{
-		struct
-		{
-			unsigned char h : 1;
-			unsigned char i : 1;
-			unsigned char j : 1;
-			unsigned char : 5;
-		};
-		struct
-		{
-			unsigned char k : 3;
-			unsigned char : 5;
-		};
-	};
-	unsigned char : 8;
-} tt;
-
-typedef struct
-{
- unsigned char s;
- tt t;
- unsigned int u;
-} ttt;
-
-ttt X = {
-    4,
-       { 0 },
-	55,
-};



From echristo at apple.com  Fri Aug 19 16:21:28 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:21:28 -0000
Subject: [llvm-commits] [llvm] r138087 -
	/llvm/trunk/test/FrontendC++/2009-09-04-modify-crash.cpp
Message-ID: <20110819212128.5117B2A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 16:21:28 2011
New Revision: 138087

URL: http://llvm.org/viewvc/llvm-project?rev=138087&view=rev
Log:
Remove 2009-09-04-modify-crash.cpp as clang doesn't support 32-bit kext.

Removed:
    llvm/trunk/test/FrontendC++/2009-09-04-modify-crash.cpp

Removed: llvm/trunk/test/FrontendC++/2009-09-04-modify-crash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-09-04-modify-crash.cpp?rev=138086&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-09-04-modify-crash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-09-04-modify-crash.cpp (removed)
@@ -1,7 +0,0 @@
-// RUN: %llvmgxx %s -fapple-kext -S -o -
-// The extra check in 71555 caused this to crash on Darwin X86
-// in an assert build.
-class foo {
- virtual ~foo ();
-};
-foo::~foo(){}



From nicholas at mxc.ca  Fri Aug 19 16:45:19 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 19 Aug 2011 21:45:19 -0000
Subject: [llvm-commits] [llvm] r138091 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Message-ID: <20110819214519.8A3082A6C12C@llvm.org>

Author: nicholas
Date: Fri Aug 19 16:45:19 2011
New Revision: 138091

URL: http://llvm.org/viewvc/llvm-project?rev=138091&view=rev
Log:
Eli points out that this is what report_fatal_error() is for.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=138091&r1=138090&r2=138091&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Aug 19 16:45:19 2011
@@ -45,7 +45,8 @@
     dbgs() << "\n";
     dbgs() << "Do not know how to scalarize the result of this operator!\n";
 #endif
-    abort();
+    report_fatal_error("Do not know how to scalarize the result of this "
+                       "operator!\n");
 
   case ISD::BITCAST:           R = ScalarizeVecRes_BITCAST(N); break;
   case ISD::BUILD_VECTOR:      R = N->getOperand(0); break;



From tonic at nondot.org  Fri Aug 19 16:47:32 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 21:47:32 -0000
Subject: [llvm-commits] [www] r138092 - /www/trunk/devmtg/students.php
Message-ID: <20110819214732.3DB1E2A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 16:47:32 2011
New Revision: 138092

URL: http://llvm.org/viewvc/llvm-project?rev=138092&view=rev
Log:
Update form.

Modified:
    www/trunk/devmtg/students.php

Modified: www/trunk/devmtg/students.php
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/students.php?rev=138092&r1=138091&r2=138092&view=diff
==============================================================================
--- www/trunk/devmtg/students.php (original)
+++ www/trunk/devmtg/students.php Fri Aug 19 16:47:32 2011
@@ -10,8 +10,8 @@
 
 function notify() {
 
-$to = "lattner at apple.com";
-$subject = "LLVM Dev Meeting Student & Active Contributor Funding Request";
+$to = "lattner at apple.com,clattner at apple.com,dkipping at qualcomm.com";
+$subject = "LLVM Dev Meeting Student, Presenter, and Active Contributor Funding Request";
 
 $body = '<html><body>';
 
@@ -44,7 +44,7 @@
 
 $body .= '</body></html>';
 
-$headers = 'From: tonic at nondot.org' . "\r\n";
+$headers = 'From: lattner at apple.com' . "\r\n";
 $headers .= 'Content-Type: text/html; charset="iso-8859-1"'."\n";
 mail($to, $subject, $body, $headers);
 
@@ -243,10 +243,7 @@
 ?>
 
 <div class="www_sectiontitle">LLVM Developers' Meeting - Student & Active Contributor Funding Request</div>
-
-<p>The deadline has passed.</p> 
 <?
-exit();
 
 if (isset($_POST['verify'])) {
   $formErrors = validateForm($_POST);



From tonic at nondot.org  Fri Aug 19 16:47:43 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 21:47:43 -0000
Subject: [llvm-commits] [www] r138093 - /www/trunk/devmtg/talk.php
Message-ID: <20110819214743.BF88B2A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 16:47:43 2011
New Revision: 138093

URL: http://llvm.org/viewvc/llvm-project?rev=138093&view=rev
Log:
Update form.

Modified:
    www/trunk/devmtg/talk.php

Modified: www/trunk/devmtg/talk.php
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/talk.php?rev=138093&r1=138092&r2=138093&view=diff
==============================================================================
--- www/trunk/devmtg/talk.php (original)
+++ www/trunk/devmtg/talk.php Fri Aug 19 16:47:43 2011
@@ -9,7 +9,7 @@
 
 function notify() {
 
-$to = "lattner at apple.com";
+$to = "lattner at apple.com,clattner at apple.com,dkipping at qualcomm.com";
 $subject = "LLVM Dev Meeting Talk Proposal";
 
 $body = '<html><body>';
@@ -21,6 +21,13 @@
 $body .= '<p>Title: ' . $_POST['title'] . '</p>';
 $body .= "<p>Summary: " . $_POST['summary'] . '</p>';
 
+if($_POST['talkType'] == 1)
+$talkType = "Talk";
+else if($_POST['talkType'] == 2)
+$talkType = "BOF";
+
+$body .= '<p>Type: ' . $talkType . '</p>';
+
 if($_POST['min'] == 1)
 $min =20;
 else if ($_POST['min'] == 2)
@@ -45,7 +52,7 @@
 
 $body .= '</body></html>';
 
-$headers = 'From: tonic at nondot.org' . "\r\n";
+$headers = 'From: lattner at apple.com' . "\r\n";
 $headers .= 'Content-Type: text/html; charset="iso-8859-1"'."\n";
 mail($to, $subject, $body, $headers);
 
@@ -58,9 +65,9 @@
 
 function processForm() {
   array_walk($_POST, 'my_escape_string');
-  $sql = "INSERT into presenters (lastName, firstName, organization, email, phone, title, summary, minLength, maxLength) VALUES('$_POST[last]', '$_POST[first]', '$_POST[org]', '$_POST[email]', '$_POST[phone]', '$_POST[title]', '$_POST[summary]','$_POST[min]', '$_POST[max]')";
+  $sql = "INSERT into presenters (lastName, firstName, organization, email, phone, title, summary, minLength, maxLength,talkType) VALUES('$_POST[last]', '$_POST[first]', '$_POST[org]', '$_POST[email]', '$_POST[phone]', '$_POST[title]', '$_POST[summary]','$_POST[min]', '$_POST[max]', '$_POST[talkType]')";
   mysql_query($sql) or die(mysql_error());
-print 'Congratulations! Your talk proposal for the LLVM Developers\' Meeting has been submitted. We will contact you once the agenda has been finalized. <p>Please sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">LLVM Developers\' Meeting mailing list</a> to receive announcements about the event.</p>';
+print 'Congratulations! Your talk proposal for the LLVM Developers\' Meeting has been submitted. We will contact you once the agenda has been finalized. <p>Please sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">LLVM Developers\' Meeting mailing list</a> to receive announcements about the event.</p><p>If you need funding support to present, please apply <a href="http://www.llvm.org/devmtg/sponsor.php">here</a> for sponsorsip.';
  notify();
 }
 
@@ -83,6 +90,9 @@
    if ($_POST['phone']=="")
      array_push($errors, "Phone number must be provided");
 
+   if ($_POST['talkType'] == "")
+     array_push($errors, "Please select Talk or BOF");
+
    if ($_POST['title'] == "")
      array_push($errors, "Please provide talk title");
 
@@ -181,15 +191,20 @@
 print '</td>';
 print '</tr>';
 print '</table>';
+print '<p>Select Talk or BOF: ';
+inputRadioCheck("talkType", $_POST, 1);
+print ' Talk ';
+inputRadioCheck("talkType", $_POST, 2);
+print ' BOF </p>';
 print '<p>Mininum talk length: ';
 inputList('min', $_POST);
 print '</p><p>Maximum talk length: ';
 inputList('max', $_POST);
-print '<p>Talk Title: </p>';
+print '<p>Talk/BOF Title: </p>';
 print '<p>';
 inputTextArea("title", 5, 60, $_POST);
 print '</p>';
-print '<p>Talk Summary: </p>';
+print '<p>Talk/BOF Summary: </p>';
 print '<p>';
 inputTextArea("summary", 10, 60, $_POST);
 print '</p>';
@@ -200,10 +215,8 @@
 ?>
 
 <div class="www_sectiontitle">LLVM Developers' Meeting - Talk Proposal</div>
-<p>
-The deadline to submit a talk proposal has passed. We hope you can make the meeting.</p>
+
 <?
-exit();
 
 if (isset($_POST['verify'])) {
   $formErrors = validateForm($_POST);



From tonic at nondot.org  Fri Aug 19 16:48:15 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 21:48:15 -0000
Subject: [llvm-commits] [www] r138094 - in /www/trunk/devmtg: sponsor.php
	students.php
Message-ID: <20110819214815.6B4492A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 16:48:15 2011
New Revision: 138094

URL: http://llvm.org/viewvc/llvm-project?rev=138094&view=rev
Log:
Rename form.

Added:
    www/trunk/devmtg/sponsor.php   (props changed)
      - copied unchanged from r138092, www/trunk/devmtg/students.php
Removed:
    www/trunk/devmtg/students.php

Propchange: www/trunk/devmtg/sponsor.php
------------------------------------------------------------------------------
    svn:mergeinfo = 

Removed: www/trunk/devmtg/students.php
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/students.php?rev=138093&view=auto
==============================================================================
--- www/trunk/devmtg/students.php (original)
+++ www/trunk/devmtg/students.php (removed)
@@ -1,264 +0,0 @@
- <?
- 
-// Database details. 
-include("connectDB.php");
-
-mysql_connect("127.0.0.1", $user, $password) or die(mysql_error());
-mysql_select_db($database);
-
-virtual("../header.incl");
-
-function notify() {
-
-$to = "lattner at apple.com,clattner at apple.com,dkipping at qualcomm.com";
-$subject = "LLVM Dev Meeting Student, Presenter, and Active Contributor Funding Request";
-
-$body = '<html><body>';
-
-$body .= '<p>Name: ' . $_POST['first'] . ' ' . $_POST['last'] . '</p>';
-$body .= '<p>School/Organization: ' . $_POST['school'] . '</p>';
-$body .= '<p>Email: ' . $_POST['email'] . '</p>';
-$body .= '<p>Location: ' . $_POST['location'] . '</p>';
-
-if($_POST['level'] == 1)
-$level = "Undergraduate";
-else if($_POST['level'] == 2)
-$level = "Graduate";
-else
-$level = "Not a student";
-
-$body .= '<p>Level: ' . $level . '</p>';
-
-if($_POST['type'] == 1)
-$type = "Partial";
-else
-$type = "Full";
-
-
-$body .= "<p>Funding Level: " . $type . '</p>';
-
-$body .= '<p>Estimated airfare cost: ' . $_POST['airfare'] . '</p>';
-$body .= '<p>Estimated loding cost: ' . $_POST['lodging'] . '</p>';
-$body .= '<p>Estimated other costs: ' . $_POST['other'] . '</p>';
-$body .= '<p>Reasons for needing funding: ' . $_POST['comments'] . '</p>';
-
-$body .= '</body></html>';
-
-$headers = 'From: lattner at apple.com' . "\r\n";
-$headers .= 'Content-Type: text/html; charset="iso-8859-1"'."\n";
-mail($to, $subject, $body, $headers);
-
-}
-
-
-function my_escape_string(&$item, $key) {
-  $item = mysql_real_escape_string($item);
-}
-
-function processForm() {
-  array_walk($_POST, 'my_escape_string');
-  $sql = "INSERT into students (lastName, firstName, school, email, level, location, airfare, lodging, other, type, comments) VALUES('$_POST[last]', '$_POST[first]', '$_POST[school]', '$_POST[email]', '$_POST[level]', '$_POST[location]','$_POST[airfare]', '$_POST[lodging]', '$_POST[other]', '$_POST[type]', '$_POST[comments]')";
-  mysql_query($sql) or die(mysql_error());
-print 'Your request for funding to attend the LLVM Developers\' Meeting has been submitted. We will contact you once funds have been allocated. <p>Please sign up for the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-devmeeting">LLVM Developers\' Meeting mailing list</a> to receive announcements about the event.</p>';
- notify();
-}
-
-function validateForm() {
-  $errors = array();
-  
-  // First name must be set.
-  if ($_POST['first'] == "")
-     array_push($errors, "First name must be provided");
-
-  if ($_POST['last'] == "") {
-     array_push($errors, "Last name must be provided");
-   }
-   if ($_POST['email'] == "")
-     array_push($errors, "Email must be provided");
-
-   if ($_POST['school'] == "")
-     array_push($errors, "School/Organization must be provided");
-
-   if ($_POST['location']=="")
-     array_push($errors, "Location must be provided");
-
-   if ($_POST['airfare'] == "")
-     array_push($errors, "Estimate airfare expense must be provided");
-   else {
-   if ($_POST['airfare'] != strval(intval($_POST['airfare']))) {
-      array_push($errors, "Estimate airfare expense must be an integer"); 
-    } 
-    }
-
-
-   if ($_POST['lodging'] == "")
-     array_push($errors, "Estimate lodging expense must be provided");
-   else {
-      if ($_POST['lodging'] != strval(intval($_POST['lodging']))) { 
-      array_push($errors, "Estimate lodging expense must be an integer");
-       }
-    }
-
-   if ($_POST['other'] == "")
-     array_push($errors, "Estimate other expense must be provided");
-   else {
-   if ($_POST['other'] != strval(intval($_POST['other']))) { 
-      array_push($errors, "Estimate other expense must be an integer");
-    }
-    }
-
-   if ($_POST['comments'] == "")
-     array_push($errors, "Please provide reasons for needing funding");
-
-   if ($_POST['level'] == "")
-     array_push($errors, "Please select type of student");
-
-   if ($_POST['type'] == "")
-     array_push($errors, "Please select type of support");
-
-  return $errors; 
-}
-
-// Print single line text box.
-function inputText($element_name, $size, $maxLength, $values) {
-     print '<input type="text" size=' . $size . '" maxlength="' . $maxlength . '" name="' . $element_name .'" value="';
-     print htmlentities($values[$element_name]) . '">';
-}
-
-// Print text area.
-function inputTextarea($element_name, $row, $column, $values) {
-     print '<textarea name="' . $element_name . '" rows="' . $row . '" cols="' . $column . '">';
-     print htmlentities($values[$element_name]) . '</textarea>';
-}
-
-// Print radio box.
-function inputRadiocheck($element_name,
-                         $values, $element_value) {
-     print '<input type="radio" name="' .
-           $element_name .'" value="' . $element_value . '" ';
-     if ($element_value == $values[$element_name]) {
-         print ' checked="checked"';
-     }
-     print '/>';
-}
-
-// Specific to our length drop down list.
-function inputList($name, $values) {
-  print '<select name="' . $name . '" >';
-  
-  if($values[$name] == 1) 
-     print '<option value="1" selected>20</option>';
-  else {
-     print '<option value="1">20</option>';
-  }
-  if($values[$name] == 2)
-     print '<option value="2" selected>30</option>';
-  else
-     print '<option value="2">30</option>';
-
-if($values[$name] == 3)
-     print '<option value="3" selected>40</option>';
-  else
-     print '<option value="3">40</option>';
-
-if($values[$name] == 4)
-     print '<option value="4" selected>60</option>';
-  else
-     print '<option value="4">60</option>';
-  print '</select>';
-}
-
-function showForm($errors) {
-
-if($errors) {
-print '<font color=red>';
-print '<p>Errors: </p>';
-print'</font><ul>';
-foreach ($errors as $i) {
-   print '<li>';
-   print $i;
-   print '</li>'; 
-}
-print '</ul>';
-}
-
-print '<form method="post" action="' . $_SERVER['PHP_SELF'] . '">';
-print '<table border=0>';
-print '<tr>';
-print '<td><b>First Name:</b> </td> <td>';
-inputText("first", 50, 50, $_POST);
-print '</td>';
-print '</tr>';
-print '<tr>';
-print '<td><b>Last Name:</b> </td> <td>';
-inputText("last", 50, 50, $_POST);
-print'</td>';
-print '</tr><tr>';
-print '<td><b>Email:</b> </td><td>';
-inputText("email", 50, 75, $_POST);
-print '</td>';
-print '</tr><tr>';
-print '<td><b>School/Organization:</b> </td><td>';
-inputText("school", 50, 100, $_POST);
-print '</td>';
-print '</tr><tr>';
-print '<td><b>Location:</b> </td><td>';
-inputText("location", 50, 100, $_POST);
-print '</td>';
-print '</tr><tr>';
-print '<td><b>Estimated airfare:</b> </td><td>';
-inputText("airfare", 50, 100, $_POST);
-print '</td>';
-print '</tr><tr>';
-print '<td><b>Estimated lodging:</b> </td><td>';
-inputText("lodging", 50, 100, $_POST);
-print '</td>';
-print '</tr><tr>';
-print '<td><b>Estimated other expenses:</b> </td><td>';
-inputText("other", 50, 100, $_POST);
-print '</td>';
-print '</tr>';
-print '</table>';
-print '<p>Type of student: ';
-inputRadioCheck("level", $_POST, 1);
-print ' Undergraduate ';
-inputRadioCheck("level", $_POST, 2);
-print ' Graduate ';
-inputRadioCheck("level", $_POST, 3);
-print ' Not a student</p>';
-print '<p>Amount of funding : ';
-inputRadioCheck("type", $_POST, 1);
-print ' Partial ';
-inputRadioCheck("type", $_POST, 2);
-print ' Full</p>';
-
-print '<p>Reasons for needing funding: </p>';
-print '<p>';
-inputTextArea("comments", 10, 60, $_POST);
-print '</p>';
-print '<p><input type="submit" name="Submit"></p>';
-print '<input type="hidden" name="verify" value="1"/>';
-print '</form>';
-}
-?>
-
-<div class="www_sectiontitle">LLVM Developers' Meeting - Student & Active Contributor Funding Request</div>
-<?
-
-if (isset($_POST['verify'])) {
-  $formErrors = validateForm($_POST);
-  if(!empty($formErrors)) {
-     showForm($formErrors);
-   }
-  else {
-    processForm();
-  }
-
-}
-else {
-   showForm('');
-}
-?>
-
-<?virtual("../footer.incl")
-?>



From echristo at apple.com  Fri Aug 19 16:51:39 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:51:39 -0000
Subject: [llvm-commits] [llvm] r138100 - in /llvm/trunk/test/FrontendC++:
 2009-06-16-DebugInfoCrash.cpp 2009-06-20-DarwinPPCLayout.cpp
 2009-06-30-ByrefBlock.cpp 2009-07-16-PrivateCopyConstructor.cpp
 2009-07-16-Using.cpp 2009-08-05-ZeroInitWidth.cpp
 2009-08-11-VectorRetTy.cpp
Message-ID: <20110819215139.427D12A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 16:51:39 2011
New Revision: 138100

URL: http://llvm.org/viewvc/llvm-project?rev=138100&view=rev
Log:
Remove tests migrated to clang.

Removed:
    llvm/trunk/test/FrontendC++/2009-06-16-DebugInfoCrash.cpp
    llvm/trunk/test/FrontendC++/2009-06-20-DarwinPPCLayout.cpp
    llvm/trunk/test/FrontendC++/2009-06-30-ByrefBlock.cpp
    llvm/trunk/test/FrontendC++/2009-07-16-PrivateCopyConstructor.cpp
    llvm/trunk/test/FrontendC++/2009-07-16-Using.cpp
    llvm/trunk/test/FrontendC++/2009-08-05-ZeroInitWidth.cpp
    llvm/trunk/test/FrontendC++/2009-08-11-VectorRetTy.cpp

Removed: llvm/trunk/test/FrontendC++/2009-06-16-DebugInfoCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-06-16-DebugInfoCrash.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-06-16-DebugInfoCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-06-16-DebugInfoCrash.cpp (removed)
@@ -1,10 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null -g
-// This crashes if we try to emit debug info for TEMPLATE_DECL members.
-template <class T> class K2PtrVectorBase {};
-template <class T> class K2Vector {};
-template <class U > class K2Vector<U*> : public K2PtrVectorBase<U*> {};
-class ScriptInfoManager {
-  void PostRegister() ;
-  template <class SI> short ReplaceExistingElement(K2Vector<SI*>& v);
-};
-void ScriptInfoManager::PostRegister() {}

Removed: llvm/trunk/test/FrontendC++/2009-06-20-DarwinPPCLayout.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-06-20-DarwinPPCLayout.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-06-20-DarwinPPCLayout.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-06-20-DarwinPPCLayout.cpp (removed)
@@ -1,32 +0,0 @@
-// RUN: %llvmgxx -S -m32 %s -o - | grep baz | grep global | grep {struct.bar}
-// RUN: %llvmgxx -S -m32 %s -o - | grep ccc | grep global | grep {struct.CC}
-// RUN: %llvmgxx -S -m32 %s -o - | grep quux | grep global | grep {struct.bar}
-// RUN: %llvmgxx -S -m32 %s -o - | grep foo | grep global | grep {struct.SRCFilter::FilterEntry}
-// RUN: %llvmgxx -S -m32 %s -o - | grep {struct.bar} | grep {1 x i32}
-// RUN: %llvmgxx -S -m32 %s -o - | grep {struct.CC} | grep {struct.payre<KBFP,float*} | grep {.base.32} | grep {1 x i32}
-// RUN: %llvmgxx -S -m32 %s -o - | grep {struct.SRCFilter::FilterEntry} | not grep {1 x i32}
-// XFAIL: *
-// XTARGET: powerpc-apple-darwin
-
-template<class _T1, class _T2>     struct payre     {
-  _T1 first;
-  _T2 second;
-  payre()       : first(), second() {    }
-};
-struct KBFP {
-  double mCutoffFrequency;
-};
-class SRCFilter {
-  struct FilterEntry: public payre<KBFP, float*>{};
-  static FilterEntry foo;
-};
-SRCFilter::FilterEntry SRCFilter::foo;    // 12 bytes
-payre<KBFP, float*> baz;                  // 16 bytes
-class CC {                                // 16 bytes
-  public: payre<KBFP, float*> x;          
-};
-class CC ccc;
-
-struct bar { KBFP x; float* y;};          // 16 bytes
-struct bar quux;
-

Removed: llvm/trunk/test/FrontendC++/2009-06-30-ByrefBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-06-30-ByrefBlock.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-06-30-ByrefBlock.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-06-30-ByrefBlock.cpp (removed)
@@ -1,11 +0,0 @@
-// Insure __block_holder_tmp is allocated on the stack.  Darwin only.
-// RUN: %llvmgxx %s -S -O2 -o - | egrep {__block_holder_tmp.*alloca}
-// XFAIL: *
-// XTARGET: darwin
-// <rdar://problem/5865221>
-// END.
-extern void fubar_dispatch_sync(void (^PP)(void));
-void fubar() {
-  __block void *voodoo;
- fubar_dispatch_sync(^(void){voodoo=0;});
-}

Removed: llvm/trunk/test/FrontendC++/2009-07-16-PrivateCopyConstructor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-07-16-PrivateCopyConstructor.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-07-16-PrivateCopyConstructor.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-07-16-PrivateCopyConstructor.cpp (removed)
@@ -1,15 +0,0 @@
-// RUN: %llvmgxx %s -S
-// XFAIL: darwin
-
-#include <set>
-
-class A {
-public:
-  A();
-private:
-  A(const A&);
-};
-void B()
-{
-  std::set<void *, A> foo;
-}

Removed: llvm/trunk/test/FrontendC++/2009-07-16-Using.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-07-16-Using.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-07-16-Using.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-07-16-Using.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-
-namespace A {
-  typedef int B;
-}
-struct B {
-};
-using ::A::B;

Removed: llvm/trunk/test/FrontendC++/2009-08-05-ZeroInitWidth.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-08-05-ZeroInitWidth.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-08-05-ZeroInitWidth.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-08-05-ZeroInitWidth.cpp (removed)
@@ -1,12 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-// rdar://7114564
-struct A {
-  unsigned long long : (sizeof(unsigned long long) * 8) - 16;
-};
-struct B {
-  A a;
-};
-struct B b = {
-  {}
-};
-

Removed: llvm/trunk/test/FrontendC++/2009-08-11-VectorRetTy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-08-11-VectorRetTy.cpp?rev=138099&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-08-11-VectorRetTy.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-08-11-VectorRetTy.cpp (removed)
@@ -1,13 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-// <rdar://problem/7096460>
-typedef void (*Func) ();
-typedef long long m64 __attribute__((__vector_size__(8), __may_alias__));
-static inline m64 __attribute__((__always_inline__, __nodebug__)) _mm_set1_pi16() {}
-template <class MM>
-static void Bork() {
-  const m64 mmx_0x00ff = _mm_set1_pi16();
-}
-struct A {};
-Func arr[] = {
-  Bork<A>
-};



From echristo at apple.com  Fri Aug 19 16:51:41 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 21:51:41 -0000
Subject: [llvm-commits] [llvm] r138101 -
 /llvm/trunk/test/FrontendC++/2009-05-04-PureConstNounwind.cpp
Message-ID: <20110819215141.47BB72A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 16:51:41 2011
New Revision: 138101

URL: http://llvm.org/viewvc/llvm-project?rev=138101&view=rev
Log:
Remove this test. The feature and test have already been migrated to clang.

Removed:
    llvm/trunk/test/FrontendC++/2009-05-04-PureConstNounwind.cpp

Removed: llvm/trunk/test/FrontendC++/2009-05-04-PureConstNounwind.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-05-04-PureConstNounwind.cpp?rev=138100&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-05-04-PureConstNounwind.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-05-04-PureConstNounwind.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep nounwind | count 4
-int c(void) __attribute__((const));
-int p(void) __attribute__((pure));
-int t(void);
-
-int f(void) {
-	return c() + p() + t();
-}



From isanbard at gmail.com  Fri Aug 19 16:52:06 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 19 Aug 2011 21:52:06 -0000
Subject: [llvm-commits] [llvm] r138102 -
	/llvm/trunk/lib/Transforms/Scalar/ADCE.cpp
Message-ID: <20110819215206.388A32A6C12C@llvm.org>

Author: void
Date: Fri Aug 19 16:52:06 2011
New Revision: 138102

URL: http://llvm.org/viewvc/llvm-project?rev=138102&view=rev
Log:
The landingpad instruction isn't dead simply because it's value isn't used.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ADCE.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ADCE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ADCE.cpp?rev=138102&r1=138101&r2=138102&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ADCE.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ADCE.cpp Fri Aug 19 16:52:06 2011
@@ -57,6 +57,7 @@
   for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I)
     if (isa<TerminatorInst>(I.getInstructionIterator()) ||
         isa<DbgInfoIntrinsic>(I.getInstructionIterator()) ||
+        isa<LandingPadInst>(I.getInstructionIterator()) ||
         I->mayHaveSideEffects()) {
       alive.insert(I.getInstructionIterator());
       worklist.push_back(I.getInstructionIterator());
@@ -65,7 +66,6 @@
   // Propagate liveness backwards to operands.
   while (!worklist.empty()) {
     Instruction* curr = worklist.pop_back_val();
-    
     for (Instruction::op_iterator OI = curr->op_begin(), OE = curr->op_end();
          OI != OE; ++OI)
       if (Instruction* Inst = dyn_cast<Instruction>(OI))



From tonic at nondot.org  Fri Aug 19 16:52:31 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 21:52:31 -0000
Subject: [llvm-commits] [www] r138103 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819215231.6044C2A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 16:52:31 2011
New Revision: 138103

URL: http://llvm.org/viewvc/llvm-project?rev=138103&view=rev
Log:
Add blurb about funding.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138103&r1=138102&r2=138103&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 16:52:31 2011
@@ -5,6 +5,7 @@
 	<tr><td valign="top">
 <ol>
         <li><a href="#registration">Registration</a></li>
+        <li><a href="#sponsor">Funding Assistance</a></li>
         <li><a href="#location">Location</a></li>
 	<li><a href="#agenda">Agenda</a></li>
         <li><a href="#dinner">Dinner</a></li>
@@ -48,6 +49,11 @@
 <!--<p>Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.</p>
 -->
 
+<div class="www_sectiontitle" id="sponsor">Funding Assistance</div>
+
+<p>In prior years companies have come forth to sponsor speakers, students, and active contributors in need of travel assistance and likely will do so again. If you need assistance, please submit your requst <a href="">here</a>. Note, those that receive funding maybe required to present at the meeting and may have additional requirements from their sponsor (i.e. writing a blog post, etc).
+</p> 
+
 <div class="www_sectiontitle" id="registration">Location</div>
 <p>Details coming soon.</p>
 <!--<p>The LLVM Developers' Meeting is held at the San Jose Hilton. Attendees may park at the hotel ($19 day self park, $24 valet) or in the numerous parking lots downtown.</p>



From tonic at nondot.org  Fri Aug 19 16:53:27 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 19 Aug 2011 21:53:27 -0000
Subject: [llvm-commits] [www] r138104 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20110819215327.2F0342A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 16:53:27 2011
New Revision: 138104

URL: http://llvm.org/viewvc/llvm-project?rev=138104&view=rev
Log:
Add link.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=138104&r1=138103&r2=138104&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Fri Aug 19 16:53:27 2011
@@ -51,7 +51,7 @@
 
 <div class="www_sectiontitle" id="sponsor">Funding Assistance</div>
 
-<p>In prior years companies have come forth to sponsor speakers, students, and active contributors in need of travel assistance and likely will do so again. If you need assistance, please submit your requst <a href="">here</a>. Note, those that receive funding maybe required to present at the meeting and may have additional requirements from their sponsor (i.e. writing a blog post, etc).
+<p>In prior years companies have come forth to sponsor speakers, students, and active contributors in need of travel assistance and likely will do so again. If you need assistance, please submit your requst <a href="http://llvm.org/devmtg/sponsor.php">here</a>. Note, those that receive funding maybe required to present at the meeting and may have additional requirements from their sponsor (i.e. writing a blog post, etc).
 </p> 
 
 <div class="www_sectiontitle" id="registration">Location</div>



From stoklund at 2pi.dk  Fri Aug 19 17:04:20 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 22:04:20 -0000
Subject: [llvm-commits] [llvm] r138107 -
	/llvm/trunk/include/llvm/ADT/IntervalMap.h
Message-ID: <20110819220420.10CC32A6C12C@llvm.org>

Author: stoklund
Date: Fri Aug 19 17:04:19 2011
New Revision: 138107

URL: http://llvm.org/viewvc/llvm-project?rev=138107&view=rev
Log:
Add IntervalMap::const_iterator::atBegin().

It returns true when operator--() can be called.

Modified:
    llvm/trunk/include/llvm/ADT/IntervalMap.h

Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=138107&r1=138106&r2=138107&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntervalMap.h (original)
+++ llvm/trunk/include/llvm/ADT/IntervalMap.h Fri Aug 19 17:04:19 2011
@@ -1335,6 +1335,9 @@
   /// valid - Return true if the current position is valid, false for end().
   bool valid() const { return path.valid(); }
 
+  /// atBegin - Return true if the current position is the first map entry.
+  bool atBegin() const { return path.atBegin(); }
+
   /// start - Return the beginning of the current interval.
   const KeyT &start() const { return unsafeStart(); }
 



From grosbach at apple.com  Fri Aug 19 17:07:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:07:46 -0000
Subject: [llvm-commits] [llvm] r138108 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110819220746.EF4922A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:07:46 2011
New Revision: 138108

URL: http://llvm.org/viewvc/llvm-project?rev=138108&view=rev
Log:
Thumb assembly parsing and encoding for MUL.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:07:46 2011
@@ -1049,10 +1049,20 @@
 // Multiply register
 let isCommutable = 1 in
 def tMUL :                      // A8.6.105 T1
-  T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
-                IIC_iMUL32,
-                "mul", "\t$Rdn, $Rm, $Rdn",
-                [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
+  Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
+           IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
+           [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
+      T1DataProcessing<0b1101> {
+  bits<3> Rd;
+  bits<3> Rn;
+  let Inst{5-3} = Rn;
+  let Inst{2-0} = Rd;
+  let AsmMatchConverter = "cvtThumbMultiply";
+}
+
+def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
+                                               pred:$p)>,
+          Requires<[IsThumb]>;
 
 // Move inverse register
 def tMVN :                      // A8.6.107

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 17:07:46 2011
@@ -145,6 +145,8 @@
                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
+                        const SmallVectorImpl<MCParsedAsmOperand*> &);
 
   bool validateInstruction(MCInst &Inst,
                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
@@ -2371,6 +2373,29 @@
   return true;
 }
 
+/// cvtThumbMultiple- Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
+           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // The second source operand must be the same register as the destination
+  // operand.
+  if (Operands.size() == 6 &&
+      ((ARMOperand*)Operands[3])->getReg() !=
+      ((ARMOperand*)Operands[5])->getReg()) {
+    Error(Operands[3]->getStartLoc(),
+          "destination register must match second source register");
+    return false;
+  }
+  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
+  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
+  Inst.addOperand(Inst.getOperand(0));
+  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
+
+  return true;
+}
 
 /// Parse an ARM memory expression, return false if successful else return true
 /// or an error.  The first token must be a '[' when called.
@@ -3220,7 +3245,8 @@
   case Match_MnemonicFail:
     return Error(IDLoc, "invalid instruction");
   case Match_ConversionFail:
-    return Error(IDLoc, "unable to convert operands to instruction");
+    // The converter function will have already emited a diagnostic.
+    return true;
   case Match_RequiresITBlock:
     return Error(IDLoc, "instruction only valid inside IT block");
   case Match_RequiresV6:

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 17:07:46 2011
@@ -321,3 +321,13 @@
 
 @ CHECK: mov	r3, r4                  @ encoding: [0x23,0x46]
 @ CHECK: movs	r1, r3                  @ encoding: [0x19,0x00]
+
+
+ at ------------------------------------------------------------------------------
+@ MUL
+ at ------------------------------------------------------------------------------
+        muls r1, r2, r1
+        muls r3, r4
+
+@ CHECK: muls	r1, r2, r1              @ encoding: [0x51,0x43]
+@ CHECK: muls	r3, r4, r3              @ encoding: [0x63,0x43]

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 17:07:46 2011
@@ -62,3 +62,9 @@
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         lsls r4, r5, #32
 @ CHECK-ERRORS:                      ^
+
+@ Mismatched source/destination operands for MUL instruction.
+        muls r1, r2, r3
+@ CHECK-ERRORS: error: destination register must match second source register
+@ CHECK-ERRORS:         muls r1, r2, r3
+@ CHECK-ERRORS:              ^



From grosbach at apple.com  Fri Aug 19 17:09:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:09:23 -0000
Subject: [llvm-commits] [llvm] r138109 -
	/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819220923.36B232A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:09:23 2011
New Revision: 138109

URL: http://llvm.org/viewvc/llvm-project?rev=138109&view=rev
Log:
Thumb assembly parsing and encoding for MVN.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138109&r1=138108&r2=138109&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 17:09:23 2011
@@ -331,3 +331,11 @@
 
 @ CHECK: muls	r1, r2, r1              @ encoding: [0x51,0x43]
 @ CHECK: muls	r3, r4, r3              @ encoding: [0x63,0x43]
+
+
+ at ------------------------------------------------------------------------------
+@ MVN
+ at ------------------------------------------------------------------------------
+        mvns r6, r3
+
+@ CHECK: mvns	r6, r3                  @ encoding: [0xde,0x43]



From echristo at apple.com  Fri Aug 19 17:17:09 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 22:17:09 -0000
Subject: [llvm-commits] [llvm] r138115 - in /llvm/trunk/test/FrontendC++:
 2008-01-12-VecInit.cpp 2008-05-07-CrazyOffsetOf.cpp
 2008-10-29-WrongOffset.cpp 2009-02-07-VolatileArrayRefHack.cpp
 2009-02-16-CtorNames-dbg.cpp 2009-03-17-dbg.cpp
 2009-04-21-DtorNames-dbg.cpp 2009-04-23-bool2.cpp
Message-ID: <20110819221709.4297A2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 17:17:09 2011
New Revision: 138115

URL: http://llvm.org/viewvc/llvm-project?rev=138115&view=rev
Log:
Remove tests migrated to clang or are unnecessary.

Removed:
    llvm/trunk/test/FrontendC++/2008-01-12-VecInit.cpp
    llvm/trunk/test/FrontendC++/2008-05-07-CrazyOffsetOf.cpp
    llvm/trunk/test/FrontendC++/2008-10-29-WrongOffset.cpp
    llvm/trunk/test/FrontendC++/2009-02-07-VolatileArrayRefHack.cpp
    llvm/trunk/test/FrontendC++/2009-02-16-CtorNames-dbg.cpp
    llvm/trunk/test/FrontendC++/2009-03-17-dbg.cpp
    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
    llvm/trunk/test/FrontendC++/2009-04-23-bool2.cpp

Removed: llvm/trunk/test/FrontendC++/2008-01-12-VecInit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2008-01-12-VecInit.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2008-01-12-VecInit.cpp (original)
+++ llvm/trunk/test/FrontendC++/2008-01-12-VecInit.cpp (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgcc -xc++ %s -S -o -
-// rdar://5685492
-
-typedef int __attribute__((vector_size(16))) v;
-v vt = {1, 2, 3, 4};
-

Removed: llvm/trunk/test/FrontendC++/2008-05-07-CrazyOffsetOf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2008-05-07-CrazyOffsetOf.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2008-05-07-CrazyOffsetOf.cpp (original)
+++ llvm/trunk/test/FrontendC++/2008-05-07-CrazyOffsetOf.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-// rdar://5914926
-
-struct bork {
-  struct bork *next_local;
-  char * query;
-};
-int offset =  (char *) &(((struct bork *) 0x10)->query) - (char *) 0x10;

Removed: llvm/trunk/test/FrontendC++/2008-10-29-WrongOffset.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2008-10-29-WrongOffset.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2008-10-29-WrongOffset.cpp (original)
+++ llvm/trunk/test/FrontendC++/2008-10-29-WrongOffset.cpp (removed)
@@ -1,489 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-// PR2917
-
-#include <complex>
-template < int Dim, class T, class EngineTag > class Engine;
-template < class Subject, class Sub1, bool SV > struct View1Implementation;
-template < class LayoutTag, class PatchTag > struct MultiPatch;
-template < class LayoutTag, class PatchTag, int Dim2 > struct MultiPatchView;
-template < class Engine, class SubDomain > struct NewEngine
-{
-};
-template < class T > class DomainTraits;
-template < class DomT, class T, int Dim > struct DomainTraitsDomain
-{
-  typedef DomT NewDomain1_t;
-};
-template < int Dim > class Interval;
-template < int Dim > class Loc;
-template < class DT > class DomainBase
-{
-};
-
-template < int Dim, class DT > class Domain:public DomainBase < DT >
-{
-};
-template < int Dim > struct DomainTraits <Interval < Dim >
-  >:public DomainTraitsDomain < Interval < Dim >, int, Dim >
-{
-  enum
-  {
-    singleValued = false
-  };
-};
-template < class T1 > struct NewDomain1
-{
-  typedef typename DomainTraits < T1 >::NewDomain1_t SliceType_t;
-};
-template < class Domain, class Sub > struct TemporaryNewDomain1
-{
-  typedef typename NewDomain1 < Sub >::SliceType_t SliceType_t;
-};
-template < int Dim > class Interval:public Domain < Dim,
-  DomainTraits < Interval < Dim > > >
-{
-};
-template < int Dim > class GuardLayers
-{
-};
-template < class T > class Observer
-{
-};
-
-template < class T > class Observable
-{
-private:T & observed_m;
-  int count_m;
-};
-
-class RefCounted
-{
-};
-template < class T > class RefCountedPtr
-{
-public:typedef RefCountedPtr < T > This_t;
-  RefCountedPtr (T * const pT):ptr_m (pT)
-  {
-  }
-  inline T *operator-> () const
-  {
-  }
-  T *ptr_m;
-};
-
-template < class Dom, class T > class DomainMap
-{
-};
-
-template < class LayoutTag, int Dim > struct MultiPatchLayoutTraits
-{
-};
-template < int Dim > class LayoutBaseData
-{
-public:typedef Interval < Dim > Domain_t;
-  Domain_t domain_m;
-};
-template < int Dim, class LBD > class LayoutBase
-{
-public:typedef LayoutBaseData < Dim > LayoutData_t;
-  typedef typename LayoutData_t::Domain_t Domain_t;
-  typedef GuardLayers < Dim > GuardLayers_t;
-  inline const Domain_t & domain () const
-  {
-    return pdata_m->domain_m;
-  }
-  inline const Domain_t & innerDomain () const
-  {
-  }
-  inline GuardLayers_t externalGuards () const
-  {
-  }
-  RefCountedPtr < LBD > pdata_m;
-};
-template < class Tag > struct Remote;
-struct Brick
-{
-};
-template < class Thing, class Sub > struct View1
-{
-};
-template < int Dim, class T, class LayoutTag,
-  class PatchTag > struct NewEngine <Engine < Dim, T, MultiPatch < LayoutTag,
-  PatchTag > >, Interval < Dim > >
-{
-  typedef Engine < Dim, T, MultiPatchView < LayoutTag, PatchTag,
-    Dim > >Type_t;
-};
-template < int Dim, class T, class LayoutTag, class PatchTag,
-  int Dim2 > struct NewEngine <Engine < Dim, T, MultiPatchView < LayoutTag,
-  PatchTag, Dim2 > >, Interval < Dim > >
-{
-  typedef Engine < Dim, T, MultiPatchView < LayoutTag, PatchTag,
-    Dim2 > >Type_t;
-};
-template < int Dim, class T, class LayoutTag,
-  class PatchTag > class Engine < Dim, T, MultiPatch < LayoutTag,
-  PatchTag > >:public Observer < typename MultiPatchLayoutTraits < LayoutTag,
-  Dim >::Layout_t >
-{
-public:typedef MultiPatch < LayoutTag, PatchTag > Tag_t;
-  typedef Interval < Dim > Domain_t;
-};
-template < int Dim, class T, class LayoutTag, class PatchTag,
-  int Dim2 > class Engine < Dim, T, MultiPatchView < LayoutTag, PatchTag,
-  Dim2 > >
-{
-public:typedef MultiPatchView < LayoutTag, PatchTag, Dim2 > Tag_t;
-  typedef Interval < Dim > Domain_t;
-  typedef T Element_t;
-  enum
-  {
-    dimensions = Dim
-  };
-};
-class Full;
-template < int Dim, class T = double, class EngineTag = Full > class Vector {
-};
-
-template < int Dim > inline Interval < Dim >
-shrinkRight (const Interval < Dim > &dom, int s)
-{
-}
-
-template < int Dim > class GridLayout;
-struct GridTag
-{
-};
-template < int Dim > struct MultiPatchLayoutTraits <GridTag, Dim >
-{
-  typedef GridLayout < Dim > Layout_t;
-};
-template < int Dim > class GridLayoutData:public LayoutBaseData < Dim >,
-  public RefCounted, public Observable < GridLayoutData < Dim > >
-{
-  typedef int AxisIndex_t;
-  mutable DomainMap < Interval < 1 >, AxisIndex_t > mapAloc_m[Dim];
-};
-template < int Dim > class GridLayout:public LayoutBase < Dim,
-  GridLayoutData < Dim > >, public Observable < GridLayout < Dim > >,
-  public Observer < GridLayoutData < Dim > >
-{
-public:typedef GridLayout < Dim > This_t;
-    GridLayout ();
-};
-template < class MeshTag, class T, class EngineTag > class Field;
-enum CenteringType
-{
-  VertexType, EdgeType, FaceType, CellType
-};
-enum ContinuityType
-{
-  Continuous = 0, Discontinuous
-};
-template < int Dim > class Centering
-{
-public:typedef Loc < Dim > Orientation;
-  inline int size () const
-  {
-  }
-};
-template < int Dim > const Centering < Dim >
-canonicalCentering (const enum CenteringType type,
-		    const enum ContinuityType discontinuous,
-		    const int dimension = 0);
-template < class Mesh, class T, class EngineTag > class FieldEngine
-{
-public:enum
-  {
-    dimensions = Mesh::dimensions
-  };
-  enum
-  {
-    Dim = dimensions
-  };
-  typedef Engine < Dim, T, EngineTag > Engine_t;
-  typedef typename Engine_t::Domain_t Domain_t;
-  typedef GuardLayers < Dim > GuardLayers_t;
-template < class Layout2 > FieldEngine (const Centering < Dim > &centering, const Layout2 & layout, const Mesh & mesh, int materials = 1):num_materials_m (materials), centering_m (centering),
-    stride_m (centering.size ()), physicalCellDomain_m (layout.domain ()),
-    guards_m (layout.externalGuards ()), mesh_m (mesh)
-  {
-  }
-  unsigned int num_materials_m;
-  Centering < Dim > centering_m;
-  int stride_m;
-  Domain_t physicalCellDomain_m;
-  GuardLayers_t guards_m;
-  Mesh mesh_m;
-};
-
-template < class Subject > class SubFieldView;
-template < class Mesh, class T,
-  class EngineTag > class SubFieldView < Field < Mesh, T, EngineTag > >
-{
-public:typedef Field < Mesh, T, EngineTag > Type_t;
-};
-
-template < int Dim, class Mesh, class Domain > struct NewMeshTag
-{
-  typedef Mesh Type_t;
-};
-template < class Mesh, class T, class EngineTag,
-  class Domain > struct View1Implementation <Field < Mesh, T, EngineTag >,
-  Domain, false >
-{
-  typedef Field < Mesh, T, EngineTag > Subject_t;
-  typedef typename Subject_t::Engine_t Engine_t;
-  typedef typename NewEngine < Engine_t, Domain >::Type_t NewEngine_t;
-  typedef typename NewEngine_t::Element_t NewT_t;
-  typedef typename NewEngine_t::Tag_t NewEngineTag_t;
-  typedef typename NewMeshTag < NewEngine_t::dimensions, Mesh,
-    Domain >::Type_t NewMeshTag_t;
-  typedef Field < NewMeshTag_t, NewT_t, NewEngineTag_t > Type_t;
-};
-template < class Mesh, class T, class EngineTag,
-  class Sub1 > struct View1 <Field < Mesh, T, EngineTag >, Sub1 >
-{
-  typedef Field < Mesh, T, EngineTag > Subject_t;
-  typedef typename Subject_t::Domain_t Domain_t;
-  typedef TemporaryNewDomain1 < Domain_t, Sub1 > NewDomain_t;
-  typedef typename NewDomain_t::SliceType_t SDomain_t;
-  enum
-  {
-    sv = DomainTraits < SDomain_t >::singleValued
-  };
-  typedef View1Implementation < Subject_t, SDomain_t, sv > Dispatch_t;
-  typedef typename Dispatch_t::Type_t Type_t;
-};
-template < class Mesh, class T = double, class EngineTag = Brick > class Field {
-public:typedef Mesh MeshTag_t;
-  typedef Mesh Mesh_t;
-  typedef Field < Mesh, T, EngineTag > This_t;
-  typedef FieldEngine < Mesh, T, EngineTag > FieldEngine_t;
-  enum
-  {
-    dimensions = FieldEngine_t::dimensions
-  };
-  typedef Engine < dimensions, T, EngineTag > Engine_t;
-  typedef typename Engine_t::Domain_t Domain_t;
-  typedef Centering < dimensions > Centering_t;
-  template < class Layout2 > Field (const Centering_t & centering,
-				    const Layout2 & layout,
-				    const Mesh_t &
-				    mesh):fieldEngine_m (centering, layout,
-							 mesh)
-  {
-  }
-  inline typename SubFieldView < This_t >::Type_t center (int c) const
-  {
-  }
-  inline typename View1 < This_t, Domain_t >::Type_t all () const
-  {
-  }
-  template < class T1 > const This_t & operator= (const T1 & rhs) const
-  {
-  }
-private:  FieldEngine_t fieldEngine_m;
-};
-
-struct UniformRectilinearTag
-{
-};
-struct CartesianTag
-{
-};
-template < class MeshTraits > struct CartesianURM;
-template < class MeshTraits > class UniformRectilinearMeshData;
-template < class MeshTraits > class UniformRectilinearMesh;
-template < int Dim, typename T = double, class MeshTag =
-  UniformRectilinearTag, class CoordinateSystemTag = CartesianTag, int CDim =
-  Dim > struct MeshTraits;
-template < int Dim, typename T, class MeshTag, class CoordinateSystemTag,
-  int CDim > struct MeshTraitsBase
-{
-  typedef MeshTraits < Dim, T, MeshTag, CoordinateSystemTag,
-    CDim > MeshTraits_t;
-  enum
-  {
-    dimensions = Dim
-  };
-  typedef Vector < CDim, T > PointType_t;
-};
-template < int Dim, typename T, int CDim > struct MeshTraits <Dim, T,
-  UniformRectilinearTag, CartesianTag, CDim >:public MeshTraitsBase < Dim, T,
-  UniformRectilinearTag, CartesianTag, CDim >
-{
-  typedef typename MeshTraitsBase < Dim, T, UniformRectilinearTag,
-    CartesianTag, CDim >::MeshTraits_t MeshTraits_t;
-  typedef CartesianURM < MeshTraits_t > CoordinateSystem_t;
-  typedef UniformRectilinearMeshData < MeshTraits_t > MeshData_t;
-  typedef UniformRectilinearMesh < MeshTraits_t > Mesh_t;
-  typedef Vector < CDim, T > SpacingsType_t;
-};
-template < int Dim > class NoMeshData:public RefCounted
-{
-public:NoMeshData ()
-  {
-  }
-  template < class Layout >
-    explicit NoMeshData (const Layout &
-			 layout):physicalVertexDomain_m (layout.
-							 innerDomain ()),
-    physicalCellDomain_m (shrinkRight (physicalVertexDomain_m, 1)),
-    totalVertexDomain_m (layout.domain ()),
-    totalCellDomain_m (shrinkRight (totalVertexDomain_m, 1))
-  {
-  }
-private:Interval < Dim > physicalVertexDomain_m, physicalCellDomain_m;
-  Interval < Dim > totalVertexDomain_m, totalCellDomain_m;
-};
-
-template < class MeshTraits > class UniformRectilinearMeshData:public NoMeshData <
-  MeshTraits::
-  dimensions >
-{
-public:typedef typename
-    MeshTraits::MeshData_t
-    MeshData_t;
-  typedef typename
-    MeshTraits::PointType_t
-    PointType_t;
-  typedef typename
-    MeshTraits::SpacingsType_t
-    SpacingsType_t;
-  enum
-  {
-    dimensions = MeshTraits::dimensions
-  };
-  template < class Layout > UniformRectilinearMeshData (const Layout & layout,
-							const PointType_t &
-							origin,
-							const SpacingsType_t &
-							spacings):
-    NoMeshData <
-  dimensions > (layout),
-  origin_m (origin),
-  spacings_m (spacings)
-  {
-  }
-private:PointType_t origin_m;
-  SpacingsType_t
-    spacings_m;
-};
-
-template < class MeshTraits > class UniformRectilinearMesh:public MeshTraits::
-  CoordinateSystem_t
-{
-public:typedef MeshTraits
-    MeshTraits_t;
-  typedef typename
-    MeshTraits::MeshData_t
-    MeshData_t;
-  typedef typename
-    MeshTraits::PointType_t
-    PointType_t;
-  typedef typename
-    MeshTraits::SpacingsType_t
-    SpacingsType_t;
-  enum
-  {
-    dimensions = MeshTraits::dimensions
-  };
-  template < class Layout >
-    inline UniformRectilinearMesh (const Layout & layout,
-				   const PointType_t & origin,
-				   const SpacingsType_t & spacings):
-  data_m (new MeshData_t (layout, origin, spacings))
-  {
-  }
-private:RefCountedPtr < MeshData_t > data_m;
-};
-
-template < class MeshTraits > struct GenericURM
-{
-};
-template < class MeshTraits > struct CartesianURM:
-  public
-  GenericURM <
-  MeshTraits >
-{
-};
-template < int
-  dim,
-  class
-  MeshTag = UniformRectilinearTag, class CoordinateSystemTag = CartesianTag > struct ParallelTraits {
-  enum
-  {
-    Dim = dim
-  };
-  typedef
-    GridLayout <
-    dim >
-    Layout_t;
-  typedef
-    MeshTraits <
-    dim, double,
-    MeshTag,
-    CoordinateSystemTag >
-    MeshTraits_t;
-  typedef typename
-    MeshTraits_t::Mesh_t
-    Mesh_t;
-  typedef
-    MultiPatch <
-    GridTag,
-    Remote <
-  Brick > >
-    Engine_t;
-};
-template < class ComputeTraits > struct RhalkTraits:
-  public
-  ComputeTraits
-{
-  typedef typename
-    ComputeTraits::Mesh_t
-    Mesh_t;
-  typedef typename
-    ComputeTraits::Engine_t
-    Engine_t;
-  enum
-  {
-    Dim = ComputeTraits::Dim
-  };
-  typedef
-    Centering <
-    Dim >
-    Centering_t;
-  typedef typename
-    Mesh_t::SpacingsType_t
-    Spacings_t;
-  typedef
-    Field <
-    Mesh_t, double,
-    Engine_t >
-    Scalar_t;
-};
-enum
-{
-  Dim = 3
-};
-typedef
-  RhalkTraits <
-  ParallelTraits <
-  Dim,
-  UniformRectilinearTag,
-CartesianTag > >
-  Traits_t;
-Vector < Dim > origin;
-Traits_t::Spacings_t spacings;
-int
-main (int argc, char **argv)
-{
-  Traits_t::Layout_t layout;
-  Traits_t::Mesh_t mesh (layout, origin, spacings);
-  Traits_t::Centering_t face =
-    canonicalCentering < Traits_t::Dim > (FaceType, Continuous);
-  Traits_t::Scalar_t v (face, layout, mesh);
-  for (int i = 0; i < Dim; ++i)
-    v.center (i).all () = std::numeric_limits < double >::signaling_NaN ();
-}

Removed: llvm/trunk/test/FrontendC++/2009-02-07-VolatileArrayRefHack.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-02-07-VolatileArrayRefHack.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-02-07-VolatileArrayRefHack.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-02-07-VolatileArrayRefHack.cpp (removed)
@@ -1,7 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep {load volatile}
-// PR3320
-
-void test(volatile int *a) {
-    // should be a volatile load.
-    a[0];
-}

Removed: llvm/trunk/test/FrontendC++/2009-02-16-CtorNames-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-02-16-CtorNames-dbg.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-02-16-CtorNames-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-02-16-CtorNames-dbg.cpp (removed)
@@ -1,10 +0,0 @@
-// RUN: %llvmgcc -S -g %s -o - | grep "\~A"
-class A {
-  int i;
-public:
-  A() { i = 0; }
- ~A() { i = 42; }
-};
-
-A a;
-

Removed: llvm/trunk/test/FrontendC++/2009-03-17-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-03-17-dbg.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-03-17-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-03-17-dbg.cpp (removed)
@@ -1,16 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null -g
-// XTARGET: darwin,linux
-// XFAIL: *
-template <typename T1,typename T2>
-inline void f(const T1&,const T2&) { }
-
-template <typename T1,typename T2,void F(const T1&,const T2&)>
-struct A {
-    template <typename T> void g(T& i) { }
-};
-
-int main() {
-    int i;
-    A<int,int,f> a;
-    a.g(i);
-}

Removed: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp (removed)
@@ -1,32 +0,0 @@
-// RUN: %llvmgcc -S -g %s -o - | llc --disable-cfi -O0 -o %t.s
-// RUN: %compile_c %t.s -o %t.o
-// PR4025
-
-template <typename _Tp> class vector
-{
-public:
-  ~vector ()
-  {
-  }
-};
-
-class Foo
-{
-  ~Foo();
-  class FooImpl *impl_;
-};
-
-namespace {
-  class Bar;
-}
-
-class FooImpl
-{
-  vector<Bar*> thing;
-};
-
-Foo::~Foo()
-{
-  delete impl_;
-}
-

Removed: llvm/trunk/test/FrontendC++/2009-04-23-bool2.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-23-bool2.cpp?rev=138114&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2009-04-23-bool2.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-04-23-bool2.cpp (removed)
@@ -1,15 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-// g++.old-deja/g++.jason/bool2.C from gcc testsuite.
-// Crashed before 67975 went in.
-struct F {
-  bool b1 : 1;
-  bool b2 : 7;
-};
-
-int main()
-{
-  F f = { true, true };
-
-  if (int (f.b1) != 1)
-    return 1;
-}



From grosbach at apple.com  Fri Aug 19 17:19:48 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:19:48 -0000
Subject: [llvm-commits] [llvm] r138116 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/avoid-cpsr-rmw.ll
 test/CodeGen/Thumb2/thumb2-mls.ll test/CodeGen/Thumb2/thumb2-mul.ll
Message-ID: <20110819221948.595D72A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:19:48 2011
New Revision: 138116

URL: http://llvm.org/viewvc/llvm-project?rev=138116&view=rev
Log:
Update tests.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138116&r1=138115&r2=138116&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:19:48 2011
@@ -1114,6 +1114,10 @@
                "rsb", "\t$Rd, $Rn, #0",
                [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
 
+def : InstAlias<"neg${s}${p} $Rd, $Rm",
+                (tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
+        Requires<[IsThumb]>;
+
 // Subtract with carry register
 let Uses = [CPSR] in
 def tSBC :                      // A8.6.151

Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=138116&r1=138115&r2=138116&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 17:19:48 2011
@@ -6,9 +6,9 @@
 define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
  entry:
 ; CHECK: t:
-; CHECK: muls r2, r3, r2
+; CHECK: muls r2, r2, r3
 ; CHECK-NEXT: mul  r0, r0, r1
-; CHECK-NEXT: muls r0, r2, r0
+; CHECK-NEXT: muls r0, r0, r2
   %0 = mul nsw i32 %a, %b
   %1 = mul nsw i32 %c, %d
   %2 = mul nsw i32 %0, %1

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll?rev=138116&r1=138115&r2=138116&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll Fri Aug 19 17:19:48 2011
@@ -15,5 +15,5 @@
     ret i32 %tmp2
 }
 ; CHECK: f2:
-; CHECK: 	muls	r0, r1
+; CHECK: 	muls	r0, r0, r1
 

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll?rev=138116&r1=138115&r2=138116&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll Fri Aug 19 17:19:48 2011
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32 %a, i32 %b, i32 %c) {
 ; CHECK: f1:
-; CHECK: muls r0, r1
+; CHECK: muls r0, r0, r1
     %tmp = mul i32 %a, %b
     ret i32 %tmp
 }



From echristo at apple.com  Fri Aug 19 17:26:06 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 22:26:06 -0000
Subject: [llvm-commits] [llvm] r138120 -
	/llvm/trunk/test/FrontendC++/2008-01-11-BadWarning.cpp
Message-ID: <20110819222606.DCBED2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 17:26:06 2011
New Revision: 138120

URL: http://llvm.org/viewvc/llvm-project?rev=138120&view=rev
Log:
Remove previously migrated test.

Removed:
    llvm/trunk/test/FrontendC++/2008-01-11-BadWarning.cpp

Removed: llvm/trunk/test/FrontendC++/2008-01-11-BadWarning.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2008-01-11-BadWarning.cpp?rev=138119&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2008-01-11-BadWarning.cpp (original)
+++ llvm/trunk/test/FrontendC++/2008-01-11-BadWarning.cpp (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgcc -xc++ %s -S -o /dev/null |& not grep warning
-// rdar://5683899
-void** f(void **Buckets, unsigned NumBuckets) {
-  return Buckets + NumBuckets;
-}
-



From echristo at apple.com  Fri Aug 19 17:26:09 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 22:26:09 -0000
Subject: [llvm-commits] [llvm] r138121 -
	/llvm/trunk/test/FrontendC++/2007-10-01-StructResize.cpp
Message-ID: <20110819222609.A42332A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 17:26:09 2011
New Revision: 138121

URL: http://llvm.org/viewvc/llvm-project?rev=138121&view=rev
Log:
Remove tests migrated to clang.

Removed:
    llvm/trunk/test/FrontendC++/2007-10-01-StructResize.cpp

Removed: llvm/trunk/test/FrontendC++/2007-10-01-StructResize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-10-01-StructResize.cpp?rev=138120&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-10-01-StructResize.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-10-01-StructResize.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-
-#pragma pack(4)
-
-struct Bork {
-  unsigned int f1 : 3;
-  unsigned int f2 : 30;
-};
-
-int Foo(Bork *hdr) {
-  hdr->f1 = 7;
-  hdr->f2 = 927;
-}
-



From bruno.cardoso at gmail.com  Fri Aug 19 17:27:29 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 19 Aug 2011 22:27:29 -0000
Subject: [llvm-commits] [llvm] r138123 - in /llvm/trunk:
 lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
 test/MC/X86/x86_64-avx-encoding.s
Message-ID: <20110819222729.BF8B92A6C12C@llvm.org>

Author: bruno
Date: Fri Aug 19 17:27:29 2011
New Revision: 138123

URL: http://llvm.org/viewvc/llvm-project?rev=138123&view=rev
Log:
Re-write part of VEX encoding logic, to be more easy to read! Also fix
a bug and add a testcase!

Modified:
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/X86/x86_64-avx-encoding.s

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=138123&r1=138122&r2=138123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Fri Aug 19 17:27:29 2011
@@ -492,76 +492,100 @@
       VEX_L = 1;
   }
 
-  unsigned NumOps = MI.getNumOperands();
+  // Classify VEX_B, VEX_4V, VEX_R, VEX_X
   unsigned CurOp = 0;
-  bool IsDestMem = false;
-
   switch (TSFlags & X86II::FormMask) {
   case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
-  case X86II::MRMDestMem:
-    IsDestMem = true;
-    // The important info for the VEX prefix is never beyond the address
-    // registers. Don't check beyond that.
-    NumOps = CurOp = X86::AddrNumOperands;
+  case X86II::MRMDestMem: {
+    // MRMDestMem instructions forms:
+    //  MemAddr, src1(ModR/M)
+    //  MemAddr, src1(VEX_4V), src2(ModR/M)
+    //  MemAddr, src1(ModR/M), imm8
+    //
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
+      VEX_B = 0x0;
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
+      VEX_X = 0x0;
+
+    CurOp = X86::AddrNumOperands;
+    if (HasVEX_4V)
+      VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
+
+    const MCOperand &MO = MI.getOperand(CurOp);
+    if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
+      VEX_R = 0x0;
+    break;
+  }
+  case X86II::MRMSrcMem: {
+    // MRMSrcMem instructions forms:
+    //  src1(ModR/M), MemAddr
+    //  src1(ModR/M), src2(VEX_4V), MemAddr
+    //  src1(ModR/M), MemAddr, imm8
+    //  src1(ModR/M), MemAddr, src2(VEX_I8IMM)
+    //
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
+      VEX_R = 0x0;
+
+    unsigned MemAddrOffset = 1;
+    if (HasVEX_4V) {
+      VEX_4V = getVEXRegisterEncoding(MI, 1);
+      MemAddrOffset++;
+    }
+
+    if (X86II::isX86_64ExtendedReg(
+               MI.getOperand(MemAddrOffset+X86::AddrBaseReg).getReg()))
+      VEX_B = 0x0;
+    if (X86II::isX86_64ExtendedReg(
+               MI.getOperand(MemAddrOffset+X86::AddrIndexReg).getReg()))
+      VEX_X = 0x0;
+    break;
+  }
   case X86II::MRM0m: case X86II::MRM1m:
   case X86II::MRM2m: case X86II::MRM3m:
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
-  case X86II::MRMSrcMem:
+    // MRM[0-9]m instructions forms:
+    //  MemAddr
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
+      VEX_B = 0x0;
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
+      VEX_X = 0x0;
+    break;
   case X86II::MRMSrcReg:
-    if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
-        X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+    // MRMSrcReg instructions forms:
+    //  dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
+    //  dst(ModR/M), src1(ModR/M)
+    //  dst(ModR/M), src1(ModR/M), imm8
+    //
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
       VEX_R = 0x0;
     CurOp++;
 
-    if (HasVEX_4V) {
-      VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
-      CurOp++;
-    }
-
-    // To only check operands before the memory address ones, start
-    // the search from the beginning
-    if (IsDestMem)
-      CurOp = 0;
-
-    // If the last register should be encoded in the immediate field
-    // do not use any bit from VEX prefix to this register, ignore it
-    if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
-      NumOps--;
-
-    for (; CurOp != NumOps; ++CurOp) {
-      const MCOperand &MO = MI.getOperand(CurOp);
-      if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
-        VEX_B = 0x0;
-      // Only set VEX_X if the Index Register is extended
-      if (VEX_B || !MO.isReg())
-        continue;
-      if (!X86II::isX86_64ExtendedReg(MO.getReg()))
-        continue;
-      unsigned Frm = TSFlags & X86II::FormMask;
-      if ((Frm == X86II::MRMSrcMem && CurOp-1 == X86::AddrIndexReg) ||
-          (Frm == X86II::MRMDestMem && CurOp == X86::AddrIndexReg))
-        VEX_X = 0x0;
-    }
-    break;
-  default: // MRMDestReg, MRM0r-MRM7r, RawFrm
-    if (!MI.getNumOperands())
-      break;
-
-    if (MI.getOperand(CurOp).isReg() &&
-        X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
-      VEX_B = 0;
-
     if (HasVEX_4V)
-      VEX_4V = getVEXRegisterEncoding(MI, CurOp);
-
-    CurOp++;
-    for (; CurOp != NumOps; ++CurOp) {
-      const MCOperand &MO = MI.getOperand(CurOp);
-      if (MO.isReg() && !HasVEX_4V &&
-          X86II::isX86_64ExtendedReg(MO.getReg()))
-        VEX_R = 0x0;
-    }
+      VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+      VEX_B = 0x0;
+    break;
+  case X86II::MRMDestReg:
+    // MRMDestReg instructions forms:
+    //  dst(ModR/M), src(ModR/M)
+    //  dst(ModR/M), src(ModR/M), imm8
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
+      VEX_B = 0x0;
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
+      VEX_R = 0x0;
+    break;
+  case X86II::MRM0r: case X86II::MRM1r:
+  case X86II::MRM2r: case X86II::MRM3r:
+  case X86II::MRM4r: case X86II::MRM5r:
+  case X86II::MRM6r: case X86II::MRM7r:
+    // MRM0r-MRM7r instructions forms:
+    //  dst(VEX_4V), src(ModR/M), imm8
+    VEX_4V = getVEXRegisterEncoding(MI, 0);
+    if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
+      VEX_B = 0x0;
+    break;
+  default: // RawFrm
     break;
   }
 

Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=138123&r1=138122&r2=138123&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Fri Aug 19 17:27:29 2011
@@ -3332,3 +3332,7 @@
 // CHECK: encoding: [0xc4,0xc1,0x78,0x28,0x1c,0x1e]
           vmovaps	(%r14,%rbx), %xmm3
 
+// CHECK: vmovaps %xmm3, (%rax,%r11)
+// CHECK: encoding: [0xc4,0xa1,0x78,0x29,0x1c,0x18]
+          vmovaps %xmm3, (%rax,%r11)
+



From grosbach at apple.com  Fri Aug 19 17:30:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:30:46 -0000
Subject: [llvm-commits] [llvm] r138124 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/thumb-diagnostics.s
Message-ID: <20110819223046.2F01D2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:30:46 2011
New Revision: 138124

URL: http://llvm.org/viewvc/llvm-project?rev=138124&view=rev
Log:
Be more lenient on tied operand matching for MUL.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138124&r1=138123&r2=138124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 17:30:46 2011
@@ -2382,16 +2382,23 @@
   // The second source operand must be the same register as the destination
   // operand.
   if (Operands.size() == 6 &&
-      ((ARMOperand*)Operands[3])->getReg() !=
-      ((ARMOperand*)Operands[5])->getReg()) {
+      (((ARMOperand*)Operands[3])->getReg() !=
+       ((ARMOperand*)Operands[5])->getReg()) &&
+      (((ARMOperand*)Operands[3])->getReg() !=
+       ((ARMOperand*)Operands[4])->getReg())) {
     Error(Operands[3]->getStartLoc(),
-          "destination register must match second source register");
+          "destination register must match source register");
     return false;
   }
   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
   ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
   ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
-  Inst.addOperand(Inst.getOperand(0));
+  // If we have a three-operand form, use that, else the second source operand
+  // is just the destination operand again.
+  if (Operands.size() == 6)
+    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
+  else
+    Inst.addOperand(Inst.getOperand(0));
   ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
 
   return true;

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138124&r1=138123&r2=138124&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 17:30:46 2011
@@ -65,6 +65,6 @@
 
 @ Mismatched source/destination operands for MUL instruction.
         muls r1, r2, r3
-@ CHECK-ERRORS: error: destination register must match second source register
+@ CHECK-ERRORS: error: destination register must match source register
 @ CHECK-ERRORS:         muls r1, r2, r3
 @ CHECK-ERRORS:              ^



From grosbach at apple.com  Fri Aug 19 17:30:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:30:58 -0000
Subject: [llvm-commits] [llvm] r138125 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20110819223058.4494E2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:30:58 2011
New Revision: 138125

URL: http://llvm.org/viewvc/llvm-project?rev=138125&view=rev
Log:
Fix NEG alias

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138125&r1=138124&r2=138125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:30:58 2011
@@ -1115,7 +1115,7 @@
                [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
 
 def : InstAlias<"neg${s}${p} $Rd, $Rm",
-                (tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
+                (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>,
         Requires<[IsThumb]>;
 
 // Subtract with carry register



From mcrosier at apple.com  Fri Aug 19 17:32:03 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 19 Aug 2011 15:32:03 -0700
Subject: [llvm-commits] [llvm] r138116 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/avoid-cpsr-rmw.ll
 test/CodeGen/Thumb2/thumb2-mls.ll test/CodeGen/Thumb2/thumb2-mul.ll
In-Reply-To: <20110819221948.595D72A6C12C@llvm.org>
References: <20110819221948.595D72A6C12C@llvm.org>
Message-ID: <0223045B-5634-4677-9F15-1AE1DFD4CD78@apple.com>

Hi Jim,
When building I see the following error:

Included from /Users/mcrosier/llvm-clean/llvm/lib/Target/ARM/ARMInstrInfo.td:4712:
/Users/mcrosier/llvm-clean/llvm/lib/Target/ARM/ARMInstrThumb.td:1117:1: error: error: unable to find operand: 's'
def : InstAlias<"neg${s}${p} $Rd, $Rm",
^

 Chad

On Aug 19, 2011, at 3:19 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Fri Aug 19 17:19:48 2011
> New Revision: 138116
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138116&view=rev
> Log:
> Update tests.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>    llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
>    llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
>    llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138116&r1=138115&r2=138116&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:19:48 2011
> @@ -1114,6 +1114,10 @@
>                "rsb", "\t$Rd, $Rn, #0",
>                [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
> 
> +def : InstAlias<"neg${s}${p} $Rd, $Rm",
> +                (tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
> +        Requires<[IsThumb]>;
> +
> // Subtract with carry register
> let Uses = [CPSR] in
> def tSBC :                      // A8.6.151
> 
> Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=138116&r1=138115&r2=138116&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 17:19:48 2011
> @@ -6,9 +6,9 @@
> define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
>  entry:
> ; CHECK: t:
> -; CHECK: muls r2, r3, r2
> +; CHECK: muls r2, r2, r3
> ; CHECK-NEXT: mul  r0, r0, r1
> -; CHECK-NEXT: muls r0, r2, r0
> +; CHECK-NEXT: muls r0, r0, r2
>   %0 = mul nsw i32 %a, %b
>   %1 = mul nsw i32 %c, %d
>   %2 = mul nsw i32 %0, %1
> 
> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll?rev=138116&r1=138115&r2=138116&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll Fri Aug 19 17:19:48 2011
> @@ -15,5 +15,5 @@
>     ret i32 %tmp2
> }
> ; CHECK: f2:
> -; CHECK: 	muls	r0, r1
> +; CHECK: 	muls	r0, r0, r1
> 
> 
> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll?rev=138116&r1=138115&r2=138116&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll Fri Aug 19 17:19:48 2011
> @@ -2,7 +2,7 @@
> 
> define i32 @f1(i32 %a, i32 %b, i32 %c) {
> ; CHECK: f1:
> -; CHECK: muls r0, r1
> +; CHECK: muls r0, r0, r1
>     %tmp = mul i32 %a, %b
>     ret i32 %tmp
> }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Fri Aug 19 17:33:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 15:33:50 -0700
Subject: [llvm-commits] [llvm] r138116 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/avoid-cpsr-rmw.ll
 test/CodeGen/Thumb2/thumb2-mls.ll test/CodeGen/Thumb2/thumb2-mul.ll
In-Reply-To: <0223045B-5634-4677-9F15-1AE1DFD4CD78@apple.com>
References: <20110819221948.595D72A6C12C@llvm.org>
	<0223045B-5634-4677-9F15-1AE1DFD4CD78@apple.com>
Message-ID: <2D4CF228-ACCD-4966-A909-C9EF8DAC700D@apple.com>

Yah. Sorry about that. That part wasn't quite ready to go in yet. Over-eager commit. Fixed in 138125.


On Aug 19, 2011, at 3:32 PM, Chad Rosier wrote:

> Hi Jim,
> When building I see the following error:
> 
> Included from /Users/mcrosier/llvm-clean/llvm/lib/Target/ARM/ARMInstrInfo.td:4712:
> /Users/mcrosier/llvm-clean/llvm/lib/Target/ARM/ARMInstrThumb.td:1117:1: error: error: unable to find operand: 's'
> def : InstAlias<"neg${s}${p} $Rd, $Rm",
> ^
> 
> Chad
> 
> On Aug 19, 2011, at 3:19 PM, Jim Grosbach wrote:
> 
>> Author: grosbach
>> Date: Fri Aug 19 17:19:48 2011
>> New Revision: 138116
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=138116&view=rev
>> Log:
>> Update tests.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>   llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
>>   llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
>>   llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138116&r1=138115&r2=138116&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:19:48 2011
>> @@ -1114,6 +1114,10 @@
>>               "rsb", "\t$Rd, $Rn, #0",
>>               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
>> 
>> +def : InstAlias<"neg${s}${p} $Rd, $Rm",
>> +                (tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
>> +        Requires<[IsThumb]>;
>> +
>> // Subtract with carry register
>> let Uses = [CPSR] in
>> def tSBC :                      // A8.6.151
>> 
>> Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=138116&r1=138115&r2=138116&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 17:19:48 2011
>> @@ -6,9 +6,9 @@
>> define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
>> entry:
>> ; CHECK: t:
>> -; CHECK: muls r2, r3, r2
>> +; CHECK: muls r2, r2, r3
>> ; CHECK-NEXT: mul  r0, r0, r1
>> -; CHECK-NEXT: muls r0, r2, r0
>> +; CHECK-NEXT: muls r0, r0, r2
>>  %0 = mul nsw i32 %a, %b
>>  %1 = mul nsw i32 %c, %d
>>  %2 = mul nsw i32 %0, %1
>> 
>> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll?rev=138116&r1=138115&r2=138116&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll (original)
>> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll Fri Aug 19 17:19:48 2011
>> @@ -15,5 +15,5 @@
>>    ret i32 %tmp2
>> }
>> ; CHECK: f2:
>> -; CHECK: 	muls	r0, r1
>> +; CHECK: 	muls	r0, r0, r1
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll?rev=138116&r1=138115&r2=138116&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll (original)
>> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mul.ll Fri Aug 19 17:19:48 2011
>> @@ -2,7 +2,7 @@
>> 
>> define i32 @f1(i32 %a, i32 %b, i32 %c) {
>> ; CHECK: f1:
>> -; CHECK: muls r0, r1
>> +; CHECK: muls r0, r0, r1
>>    %tmp = mul i32 %a, %b
>>    ret i32 %tmp
>> }
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From greened at obbligato.org  Fri Aug 19 17:35:34 2011
From: greened at obbligato.org (David A. Greene)
Date: Fri, 19 Aug 2011 17:35:34 -0500
Subject: [llvm-commits] [llvm] r137232 - in /llvm/trunk/utils/TableGen:
	Record.cpp Record.h TGParser.cpp
In-Reply-To: <nngty9iljtu.fsf@transit.us.cray.com> (David A. Greene's message
	of "Mon, 15 Aug 2011 11:29:17 -0500")
References: <20110810182747.24D1D2A6C12D@llvm.org>
	<FA7FB8AC-43A4-4ECC-B78E-799E252E7698@apple.com>
	<nng62m5nj38.fsf@transit.us.cray.com>
	<A7CCFD41-C0FF-45F3-A2A9-DA142A39ED15@apple.com>
	<nngliuznan1.fsf@transit.us.cray.com>
	<nngty9iljtu.fsf@transit.us.cray.com>
Message-ID: <nngd3g1c9mx.fsf@transit.us.cray.com>

greened at obbligato.org (David A. Greene) writes:

> greened at obbligato.org (David A. Greene) writes:
>
>> Fair enough.  Here's a moderately complex example.  Take HADDPD.  The
>> way we have this specified in our X86InstrSIMD.td file looks like
>> this:
>
> Ping?

Ping?

                                  -Dave

From benny.kra at googlemail.com  Fri Aug 19 17:39:31 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 19 Aug 2011 22:39:31 -0000
Subject: [llvm-commits] [llvm] r138130 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20110819223931.DD40A2A6C12C@llvm.org>

Author: d0k
Date: Fri Aug 19 17:39:31 2011
New Revision: 138130

URL: http://llvm.org/viewvc/llvm-project?rev=138130&view=rev
Log:
Roll back the rest of r126557. It's a hack that will break in some obscure cases.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=138130&r1=138129&r2=138130&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Aug 19 17:39:31 2011
@@ -1526,12 +1526,6 @@
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
 
-  // If both operands are null we know that carry out will always be false.
-  if (N0C && N0C->isNullValue() && N0 == N1)
-    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE,
-                                                             N->getDebugLoc(),
-                                                             MVT::Glue));
-
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),



From grosbach at apple.com  Fri Aug 19 17:51:03 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 22:51:03 -0000
Subject: [llvm-commits] [llvm] r138131 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb-instructions.s
Message-ID: <20110819225103.F11472A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 17:51:03 2011
New Revision: 138131

URL: http://llvm.org/viewvc/llvm-project?rev=138131&view=rev
Log:
Thumb assembly parsing and encoding for NEG.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138131&r1=138130&r2=138131&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 17:51:03 2011
@@ -2831,7 +2831,7 @@
       Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
       Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
-      Mnemonic == "eor" || Mnemonic == "smlal" ||
+      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
       // FIXME: We need a better way. This really confused Thumb2
       // parsing for 'mov'.
       (Mnemonic == "mov" && !isThumbOne())) {

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138131&r1=138130&r2=138131&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 17:51:03 2011
@@ -339,3 +339,11 @@
         mvns r6, r3
 
 @ CHECK: mvns	r6, r3                  @ encoding: [0xde,0x43]
+
+
+ at ------------------------------------------------------------------------------
+@ NEG
+ at ------------------------------------------------------------------------------
+        negs r3, r4
+
+@ CHECK: rsbs	r3, r4, #0              @ encoding: [0x63,0x42]



From ahatanak at gmail.com  Fri Aug 19 17:59:00 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 19 Aug 2011 22:59:00 -0000
Subject: [llvm-commits] [llvm] r138132 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20110819225901.076D02A6C12C@llvm.org>

Author: ahatanak
Date: Fri Aug 19 17:59:00 2011
New Revision: 138132

URL: http://llvm.org/viewvc/llvm-project?rev=138132&view=rev
Log:
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
needed for Mips32.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=138132&r1=138131&r2=138132&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Aug 19 17:59:00 2011
@@ -37,17 +37,13 @@
 
 // If I is a shifted mask, set the size (Size) and the first bit of the 
 // mask (Pos), and return true.
-static bool IsShiftedMask(uint64_t I, unsigned SizeInBits, uint64_t &Pos,
-                          uint64_t &Size) {
-  assert(SizeInBits == 32 || SizeInBits == 64);
-  bool Is32Bits = (SizeInBits == 32);
+// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).  
+static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
+  if (!isUInt<32>(I) || !isShiftedMask_32(I))
+     return false;
 
-  if ((Is32Bits == 32 && !isShiftedMask_32(I)) ||
-      (!Is32Bits && !isShiftedMask_64(I)))
-    return false;
-
-  Size = Is32Bits ? CountPopulation_32(I) : CountPopulation_64(I);
-  Pos = Is32Bits ? CountTrailingZeros_32(I) : CountTrailingZeros_64(I);
+  Size = CountPopulation_32(I);
+  Pos = CountTrailingZeros_32(I);
   return true;
 }
 
@@ -546,7 +542,7 @@
   uint64_t SMPos, SMSize;
   // Op's second operand must be a shifted mask.
   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
-      !IsShiftedMask(CN->getZExtValue(), 32, SMPos, SMSize))
+      !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
     return SDValue();
 
   // Return if the shifted mask does not start at bit 0 or the sum of its size
@@ -579,7 +575,7 @@
     return SDValue();
 
   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
-      !IsShiftedMask(~CN->getZExtValue(), 32, SMPos0, SMSize0))
+      !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
     return SDValue();
 
   // See if Op's second operand matches (and (shl $src, pos), mask1).
@@ -587,8 +583,7 @@
     return SDValue();
   
   if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
-      !IsShiftedMask(CN->getZExtValue(), CN->getValueSizeInBits(0), SMPos1,
-                     SMSize1))
+      !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
     return SDValue();
 
   // The shift masks must have the same position and size.



From stoklund at 2pi.dk  Fri Aug 19 18:01:36 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 16:01:36 -0700
Subject: [llvm-commits] [llvm] r138116 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/avoid-cpsr-rmw.ll
 test/CodeGen/Thumb2/thumb2-mls.ll test/CodeGen/Thumb2/thumb2-mul.ll
In-Reply-To: <20110819221948.595D72A6C12C@llvm.org>
References: <20110819221948.595D72A6C12C@llvm.org>
Message-ID: <32744960-3BCD-4D0A-9375-2AEC7F484A87@2pi.dk>


On Aug 19, 2011, at 3:19 PM, Jim Grosbach wrote:

> --- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 17:19:48 2011
> @@ -6,9 +6,9 @@
> define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
>  entry:
> ; CHECK: t:
> -; CHECK: muls r2, r3, r2
> +; CHECK: muls r2, r2, r3
> ; CHECK-NEXT: mul  r0, r0, r1
> -; CHECK-NEXT: muls r0, r2, r0
> +; CHECK-NEXT: muls r0, r0, r2
>   %0 = mul nsw i32 %a, %b
>   %1 = mul nsw i32 %c, %d
>   %2 = mul nsw i32 %0, %1

I don't think the temporaries are required to use r2 and r0 here. Please use FileCheck variables instead.

/jakob


From grosbach at apple.com  Fri Aug 19 18:05:00 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 16:05:00 -0700
Subject: [llvm-commits] [llvm] r138116 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td test/CodeGen/ARM/avoid-cpsr-rmw.ll
 test/CodeGen/Thumb2/thumb2-mls.ll test/CodeGen/Thumb2/thumb2-mul.ll
In-Reply-To: <32744960-3BCD-4D0A-9375-2AEC7F484A87@2pi.dk>
References: <20110819221948.595D72A6C12C@llvm.org>
	<32744960-3BCD-4D0A-9375-2AEC7F484A87@2pi.dk>
Message-ID: <E33E0BFE-9164-406E-9C85-CAAF93D6541B@apple.com>

On Aug 19, 2011, at 4:01 PM, Jakob Stoklund Olesen wrote:

> 
> On Aug 19, 2011, at 3:19 PM, Jim Grosbach wrote:
> 
>> --- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 17:19:48 2011
>> @@ -6,9 +6,9 @@
>> define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
>> entry:
>> ; CHECK: t:
>> -; CHECK: muls r2, r3, r2
>> +; CHECK: muls r2, r2, r3
>> ; CHECK-NEXT: mul  r0, r0, r1
>> -; CHECK-NEXT: muls r0, r2, r0
>> +; CHECK-NEXT: muls r0, r0, r2
>>  %0 = mul nsw i32 %a, %b
>>  %1 = mul nsw i32 %c, %d
>>  %2 = mul nsw i32 %0, %1
> 
> I don't think the temporaries are required to use r2 and r0 here. Please use FileCheck variables instead.


Not my test, so I didn't even look at that part. You're probably right. I'll see about cleaning that up while I'm poking around in there anyway.

-Jim

From echristo at apple.com  Fri Aug 19 18:08:41 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 23:08:41 -0000
Subject: [llvm-commits] [llvm] r138135 - /llvm/trunk/test/FrontendC++/
Message-ID: <20110819230842.0A3B32A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 18:08:41 2011
New Revision: 138135

URL: http://llvm.org/viewvc/llvm-project?rev=138135&view=rev
Log:
Remove obsolete or migrated tests.

Removed:
    llvm/trunk/test/FrontendC++/2007-01-06-ELF-Thunk-Sections.cpp
    llvm/trunk/test/FrontendC++/2007-01-06-PtrMethodInit.cpp
    llvm/trunk/test/FrontendC++/2007-03-27-FunctionVarRename.cpp
    llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFields-1.cpp
    llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap-2.cpp
    llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap.cpp
    llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsSmall.cpp
    llvm/trunk/test/FrontendC++/2007-04-05-StructPackedFieldUnpacked.cpp
    llvm/trunk/test/FrontendC++/2007-04-10-PackedUnion.cpp
    llvm/trunk/test/FrontendC++/2007-04-11-InlineStorageClassC++.cpp
    llvm/trunk/test/FrontendC++/2007-04-14-FNoBuiltin.cpp
    llvm/trunk/test/FrontendC++/2007-04-31-TryCatch.cpp
    llvm/trunk/test/FrontendC++/2007-05-03-VectorInit.cpp
    llvm/trunk/test/FrontendC++/2007-05-16-ReverseBitFieldCrash.cpp
    llvm/trunk/test/FrontendC++/2007-05-23-TryFinally.cpp
    llvm/trunk/test/FrontendC++/2007-07-04-NestedCatches.cpp
    llvm/trunk/test/FrontendC++/2007-07-29-RestrictPtrArg.cpp
    llvm/trunk/test/FrontendC++/2007-07-29-RestrictRefArg.cpp
    llvm/trunk/test/FrontendC++/2007-08-01-RestrictMethod.cpp
    llvm/trunk/test/FrontendC++/2007-09-10-RecursiveTypeResolution.cpp

Removed: llvm/trunk/test/FrontendC++/2007-01-06-ELF-Thunk-Sections.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-01-06-ELF-Thunk-Sections.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-01-06-ELF-Thunk-Sections.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-01-06-ELF-Thunk-Sections.cpp (removed)
@@ -1,49 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | not grep gnu.linkonce.
-// PR1085
-
-class 
-__attribute__((visibility("default"))) QGenericArgument
-{
-	public:inline QGenericArgument(const char *aName = 0, const void *aData = 0):_data(aData), _name(aName) {
-	}
-	private:const void *_data;
-	const char     *_name;
-};
-struct __attribute__ ((
-		       visibility("default"))) QMetaObject
-{
-	struct {
-	}
-	                d;
-};
-class 
-__attribute__((visibility("default"))) QObject
-{
-	virtual const QMetaObject *metaObject() const;
-};
-class 
-__attribute__((visibility("default"))) QPaintDevice
-{
-	public:enum PaintDeviceMetric {
-		PdmWidth = 1, PdmHeight, PdmWidthMM, PdmHeightMM, PdmNumColors, PdmDepth, PdmDpiX, PdmDpiY, PdmPhysicalDpiX, PdmPhysicalDpiY
-	};
-	virtual ~ QPaintDevice();
-	union {
-	}
-	                ct;
-};
-class 
-__attribute__((visibility("default"))) QWidget:public QObject, public QPaintDevice
-{
-};
-class 
-__attribute__((visibility("default"))) QDialog:public QWidget
-{
-};
-class           TopicChooser:public QDialog {
-	virtual const QMetaObject *metaObject() const;
-};
-const QMetaObject *TopicChooser::
-metaObject() const
-{
-}

Removed: llvm/trunk/test/FrontendC++/2007-01-06-PtrMethodInit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-01-06-PtrMethodInit.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-01-06-PtrMethodInit.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-01-06-PtrMethodInit.cpp (removed)
@@ -1,75 +0,0 @@
-// RUN: %llvmgxx %s -S -o -
-// PR1084
-
-extern "C"
-{
-  typedef unsigned char PRUint8;
-  typedef unsigned int PRUint32;
-}
-typedef PRUint32 nsresult;
-struct nsID
-{
-};
-typedef nsID nsIID;
-class nsISupports
-{
-};
-extern "C++"
-{
-  template < class T > struct nsCOMTypeInfo
-  {
-    static const nsIID & GetIID ()
-    {
-    }
-  };
-}
-
-class nsIDOMEvent:public nsISupports
-{
-};
-class nsIDOMEventListener:public nsISupports
-{
-public:static const nsIID & GetIID ()
-  {
-  }
-  virtual nsresult
-    __attribute__ ((regparm (0), cdecl)) HandleEvent (nsIDOMEvent * event) =
-    0;
-};
-class nsIDOMMouseListener:public nsIDOMEventListener
-{
-public:static const nsIID & GetIID ()
-  {
-    static const nsIID iid = {
-    };
-  }
-  virtual nsresult
-    __attribute__ ((regparm (0),
-		    cdecl)) MouseDown (nsIDOMEvent * aMouseEvent) = 0;
-};
-typedef
-typeof (&nsIDOMEventListener::HandleEvent)
-  GenericHandler;
-     struct EventDispatchData
-     {
-       PRUint32 message;
-       GenericHandler method;
-       PRUint8 bits;
-     };
-     struct EventTypeData
-     {
-       const EventDispatchData *events;
-       int numEvents;
-       const nsIID *iid;
-     };
-     static const EventDispatchData sMouseEvents[] = {
-       {
-	(300 + 2),
-	reinterpret_cast < GenericHandler > (&nsIDOMMouseListener::MouseDown),
-	0x01}
-     };
-static const EventTypeData sEventTypes[] = {
-  {
-   sMouseEvents, (sizeof (sMouseEvents) / sizeof (sMouseEvents[0])),
-   &nsCOMTypeInfo < nsIDOMMouseListener >::GetIID ()}
-};

Removed: llvm/trunk/test/FrontendC++/2007-03-27-FunctionVarRename.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-03-27-FunctionVarRename.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-03-27-FunctionVarRename.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-03-27-FunctionVarRename.cpp (removed)
@@ -1,17 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | not grep eprintf1
-// RUN: %llvmgxx %s -S -o - | grep eprintf
-
-// Only one eprintf should exist in the output
-
-extern "C" 
-void __eprintf();
-
-void foo() {
-
-  __eprintf();
-}
-
-void *bar() {
-  extern void *__eprintf;
-  return &__eprintf;
-}

Removed: llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFields-1.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-05-PackedBitFields-1.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFields-1.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFields-1.cpp (removed)
@@ -1,23 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-#ifdef PACKED
-#define P __attribute__((packed))
-#else
-#define P
-#endif
-
-struct P M_Packed { 
-  unsigned int l_Packed; 
-  unsigned short k_Packed : 6, 
-    i_Packed : 15,
-    j_Packed : 11;
-  
-}; 
-
-struct M_Packed sM_Packed; 
-
-int testM_Packed (void) { 
-  struct M_Packed x; 
-  return (x.i_Packed != 0);
-}
-      

Removed: llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap-2.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-05-PackedBitFieldsOverlap-2.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap-2.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap-2.cpp (removed)
@@ -1,24 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-#ifdef PACKED
-#define P __attribute__((packed))
-#else
-#define P
-#endif
-
-struct P M_Packed { 
-  unsigned long sorted : 1;
-  unsigned long from_array : 1;
-  unsigned long mixed_encoding : 1;
-  unsigned long encoding : 8;
-  unsigned long count : 21;
-
-}; 
-
-struct M_Packed sM_Packed; 
-
-int testM_Packed (void) { 
-  struct M_Packed x; 
-  return (x.count != 0);
-}
-      

Removed: llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-05-PackedBitFieldsOverlap.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsOverlap.cpp (removed)
@@ -1,24 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-
-#ifdef PACKED
-#define P __attribute__((packed))
-#else
-#define P
-#endif
-
-struct P M_Packed { 
-  unsigned int l_Packed; 
-  unsigned short k_Packed : 6, 
-    i_Packed : 15;
-  char c;
-  
-}; 
-
-struct M_Packed sM_Packed; 
-
-int testM_Packed (void) { 
-  struct M_Packed x; 
-  return (x.i_Packed != 0);
-}
-      

Removed: llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsSmall.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-05-PackedBitFieldsSmall.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsSmall.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-05-PackedBitFieldsSmall.cpp (removed)
@@ -1,27 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-
-#ifdef PACKED
-// This is an example where size of Packed struct is smaller then 
-// the size of bit field type.
-#define P __attribute__((packed))
-#else
-#define P
-#endif
-
-struct P M_Packed { 
-  unsigned long long X:50;
-  unsigned Y:2;
-}; 
-
-struct M_Packed sM_Packed; 
-
-int testM_Packed (void) { 
-  struct M_Packed x; 
-  return (0 != x.Y);
-}
-      
-int testM_Packed2 (void) { 
-  struct M_Packed x; 
-  return (0 != x.X);
-}

Removed: llvm/trunk/test/FrontendC++/2007-04-05-StructPackedFieldUnpacked.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-05-StructPackedFieldUnpacked.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-05-StructPackedFieldUnpacked.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-05-StructPackedFieldUnpacked.cpp (removed)
@@ -1,25 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-#ifdef PACKED
-#define P __attribute__((packed))
-#else
-#define P
-#endif
-
-struct UnPacked {
- 	int X;	
-	int Y;
-};
-
-struct P M_Packed { 
-  unsigned char A;
-  struct UnPacked B;
-}; 
-
-struct M_Packed sM_Packed; 
-
-int testM_Packed (void) { 
-  struct M_Packed x; 
-  return (x.B.Y != 0);
-}
-      

Removed: llvm/trunk/test/FrontendC++/2007-04-10-PackedUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-10-PackedUnion.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-10-PackedUnion.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-10-PackedUnion.cpp (removed)
@@ -1,41 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-extern "C" {
-
-#pragma pack(push, 2)
-  typedef struct ABC* abc;
-
-  struct ABCS {
-    float red;
-    float green;
-    float blue;
-    float alpha;
-  };
-
-  typedef void (*XYZ)();
-#pragma pack(pop)
-}
-
-
-union ABCU {
-  ABCS color;
-  XYZ bg;
-};
-
-struct AData {
-  ABCU data;
-};
-
-class L {
- public:
-  L() {}
-  L(const L& other);
-
- private:
-  AData fdata;
-};
-
-
-L::L(const L& other)
-{
-  fdata = other.fdata;
-}

Removed: llvm/trunk/test/FrontendC++/2007-04-11-InlineStorageClassC++.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-11-InlineStorageClassC%2B%2B.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-11-InlineStorageClassC++.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-11-InlineStorageClassC++.cpp (removed)
@@ -1,44 +0,0 @@
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xglobWeak | grep linkonce | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xextWeak | grep linkonce | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xWeaknoinline | grep weak | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xWeakextnoinline | grep weak | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xglobnoWeak | grep linkonce | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xstatnoWeak | grep internal | count 1
-// RUN: %llvmgxx %s -S -O0 -o - | grep define | \
-// RUN:   grep xextnoWeak | grep linkonce | count 1
-inline int xglobWeak(int) __attribute__((weak));
-inline int xglobWeak (int i) {
-  return i*2;
-}
-inline int xextWeak(int) __attribute__((weak));
-extern  inline int xextWeak (int i) {
-  return i*4;
-}
-int xWeaknoinline(int) __attribute__((weak));
-int xWeaknoinline(int i) {
-  return i*8;
-}
-int xWeakextnoinline(int) __attribute__((weak));
-extern int xWeakextnoinline(int i) {
-  return i*16;
-}
-inline int xglobnoWeak (int i) {
-  return i*32;
-}
-static inline int xstatnoWeak (int i) {
-  return i*64;
-}
-extern  inline int xextnoWeak (int i) {
-  return i*128;
-}
-int j(int y) {
-  return xglobnoWeak(y)+xstatnoWeak(y)+xextnoWeak(y)+
-        xglobWeak(y)+xextWeak(y)+
-        xWeakextnoinline(y)+xWeaknoinline(y);
-}

Removed: llvm/trunk/test/FrontendC++/2007-04-14-FNoBuiltin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-14-FNoBuiltin.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-14-FNoBuiltin.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-14-FNoBuiltin.cpp (removed)
@@ -1,7 +0,0 @@
-// RUN: %llvmgcc -S %s -O2 -fno-builtin -o - | grep call.*printf
-// Check that -fno-builtin is honored.
-
-extern "C" int printf(const char*, ...);
-void foo(const char *msg) {
-	printf("%s\n",msg);
-}

Removed: llvm/trunk/test/FrontendC++/2007-04-31-TryCatch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-04-31-TryCatch.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-04-31-TryCatch.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-04-31-TryCatch.cpp (removed)
@@ -1,12 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-
-#include <locale>
-
-namespace std 
-{
-  codecvt<char, char, mbstate_t>::
-  codecvt(size_t __refs)
-  : __codecvt_abstract_base<char, char, mbstate_t>(__refs),
-  _M_c_locale_codecvt(_S_get_c_locale())
-  { }
-}

Removed: llvm/trunk/test/FrontendC++/2007-05-03-VectorInit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-05-03-VectorInit.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-05-03-VectorInit.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-05-03-VectorInit.cpp (removed)
@@ -1,17 +0,0 @@
-// RUN: %llvmgxx %s -S -O0 -o - 
-// PR1378
-
-typedef float v4sf __attribute__((vector_size(16)));
-
-typedef v4sf float4;
-
-static float4 splat4(float a) 
-{
-  float4 tmp = {a,a,a,a};
-  return tmp;
-}
-
-float4 foo(float a)
-{
-  return splat4(a);
-}

Removed: llvm/trunk/test/FrontendC++/2007-05-16-ReverseBitFieldCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-05-16-ReverseBitFieldCrash.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-05-16-ReverseBitFieldCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-05-16-ReverseBitFieldCrash.cpp (removed)
@@ -1,24 +0,0 @@
-// RUN: %llvmgxx %s -S -o -
-
-#pragma reverse_bitfields on
-typedef unsigned long UINT32;
-
-extern void abort(void);
-
-typedef struct TestStruct
-{
-  long	first: 15,
-    second: 17;	
-} TestStruct;
-
-int main (int argc, char * const argv[]) {
-
-  TestStruct testStruct = {1, 0};
-  
-  UINT32 dw = *(UINT32 *)(&testStruct);
-  
-  if(!(dw & 0xFFFF))
-    abort ();
-
-  return 0;
-}

Removed: llvm/trunk/test/FrontendC++/2007-05-23-TryFinally.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-05-23-TryFinally.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-05-23-TryFinally.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-05-23-TryFinally.cpp (removed)
@@ -1,16 +0,0 @@
-// RUN: %llvmgxx %s -S -O2 -o - | ignore grep _Unwind_Resume | \
-// RUN:   wc -l | grep {\[23\]}
-
-struct One { };
-struct Two { };
-
-void handle_unexpected () {
-  try
-  {
-    throw;
-  }
-  catch (One &)
-  {
-    throw Two ();
-  }
-}

Removed: llvm/trunk/test/FrontendC++/2007-07-04-NestedCatches.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-07-04-NestedCatches.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-07-04-NestedCatches.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-07-04-NestedCatches.cpp (removed)
@@ -1,32 +0,0 @@
-// RUN: %llvmgxx %s -S -O2 -o - | \
-// RUN:   ignore grep {eh\.selector.*One.*Two.*Three.*Four.*Five.*Six.*null} | \
-// RUN:     wc -l | grep {\[01\]}
-
-extern void X(void);
-
-struct One   {};
-struct Two   {};
-struct Three {};
-struct Four  {};
-struct Five  {};
-struct Six   {};
-
-static void A(void) throw ()
-{
-  X();
-}
-
-static void B(void) throw (Two)
-{
-  try { A(); } catch (One) {}
-}
-
-static void C(void) throw (Six, Five)
-{
-  try { B(); } catch (Three) {} catch (Four) {}
-}
-
-int main ()
-{
-  try { C(); } catch (...) {}
-}

Removed: llvm/trunk/test/FrontendC++/2007-07-29-RestrictPtrArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-07-29-RestrictPtrArg.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-07-29-RestrictPtrArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-07-29-RestrictPtrArg.cpp (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep noalias
-
-void foo(int * __restrict myptr1, int * myptr2) {
-  myptr1[0] = 0;
-  myptr2[0] = 0;
-}

Removed: llvm/trunk/test/FrontendC++/2007-07-29-RestrictRefArg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-07-29-RestrictRefArg.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-07-29-RestrictRefArg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-07-29-RestrictRefArg.cpp (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep noalias
-
-void foo(int & __restrict myptr1, int & myptr2) {
-  myptr1 = 0;
-  myptr2 = 0;
-}

Removed: llvm/trunk/test/FrontendC++/2007-08-01-RestrictMethod.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-08-01-RestrictMethod.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-08-01-RestrictMethod.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-08-01-RestrictMethod.cpp (removed)
@@ -1,13 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | grep noalias
-
-
-class foo {
-  int member[4];
-  
-  void bar(int * a);
-  
-};
-
-void foo::bar(int * a) __restrict {
-  member[3] = *a;
-}

Removed: llvm/trunk/test/FrontendC++/2007-09-10-RecursiveTypeResolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-09-10-RecursiveTypeResolution.cpp?rev=138134&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-09-10-RecursiveTypeResolution.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-09-10-RecursiveTypeResolution.cpp (removed)
@@ -1,88 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-// PR1634
-
-namespace Manta
-{
-  class CallbackHandle
-  {
-  protected:virtual ~ CallbackHandle (void)
-    {
-    }
-  };
-template < typename Data1 > class CallbackBase_1Data:public CallbackHandle
-  {
-  };
-}
-
-namespace __gnu_cxx
-{
-  template < typename _Iterator, typename _Container >
-  class __normal_iterator
-  {
-    _Iterator _M_current;
-  };
-}
-
-namespace std
-{
-  template < typename _Tp > struct allocator
-  {
-    typedef _Tp *pointer;
-  };
-  template < typename _InputIterator,
-    typename _Tp > inline void find (_InputIterator __last,
-					       const _Tp & __val)
-  {
-  };
-}
-
-namespace Manta
-{
-  template < typename _Tp, typename _Alloc> struct _Vector_base
-  {
-    struct _Vector_impl
-    {
-      _Tp *_M_start;
-    };
-  public:
-    _Vector_impl _M_impl;
-  };
-  template < typename _Tp, typename _Alloc = std::allocator < _Tp > >
-  class vector:protected _Vector_base < _Tp,_Alloc >
-  {
-  public:
-    typedef __gnu_cxx::__normal_iterator < typename _Alloc::pointer,
-      vector < _Tp, _Alloc > > iterator;
-    iterator end ()
-    {
-    }
-  };
-  class MantaInterface
-  {
-  };
-  class RTRT
-  {
-    virtual CallbackHandle *registerTerminationCallback (CallbackBase_1Data <
-							 MantaInterface * >*);
-    virtual void unregisterCallback (CallbackHandle *);
-    typedef vector < CallbackBase_1Data < int >*>PRCallbackMapType;
-    PRCallbackMapType parallelPreRenderCallbacks;
-  };
-}
-using namespace Manta;
-CallbackHandle *
-RTRT::registerTerminationCallback (CallbackBase_1Data < MantaInterface * >*cb)
-{
-  return cb;
-}
-
-void
-RTRT::unregisterCallback (CallbackHandle * callback)
-{
-  {
-    typedef CallbackBase_1Data < int > callback_t;
-    callback_t *cb = static_cast < callback_t * >(callback);
-    find (parallelPreRenderCallbacks.end (), cb);
-  }
-}
-



From grosbach at apple.com  Fri Aug 19 18:10:31 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 23:10:31 -0000
Subject: [llvm-commits] [llvm] r138137 -
	/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
Message-ID: <20110819231031.51A7D2A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 18:10:31 2011
New Revision: 138137

URL: http://llvm.org/viewvc/llvm-project?rev=138137&view=rev
Log:
Use regex to remove false dependencies on register allocation.

Modified:
    llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll

Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=138137&r1=138136&r2=138137&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 18:10:31 2011
@@ -6,9 +6,9 @@
 define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
  entry:
 ; CHECK: t:
-; CHECK: muls r2, r2, r3
-; CHECK-NEXT: mul  r0, r0, r1
-; CHECK-NEXT: muls r0, r0, r2
+; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
+; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r0, r1
+; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
   %0 = mul nsw i32 %a, %b
   %1 = mul nsw i32 %c, %d
   %2 = mul nsw i32 %0, %1



From echristo at apple.com  Fri Aug 19 18:18:11 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 23:18:11 -0000
Subject: [llvm-commits] [llvm] r138140 -
	/llvm/trunk/test/FrontendC++/2007-01-02-UnboundedArray.cpp
Message-ID: <20110819231811.0E5BB2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 18:18:10 2011
New Revision: 138140

URL: http://llvm.org/viewvc/llvm-project?rev=138140&view=rev
Log:
Remove migrated test.

Removed:
    llvm/trunk/test/FrontendC++/2007-01-02-UnboundedArray.cpp

Removed: llvm/trunk/test/FrontendC++/2007-01-02-UnboundedArray.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2007-01-02-UnboundedArray.cpp?rev=138139&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2007-01-02-UnboundedArray.cpp (original)
+++ llvm/trunk/test/FrontendC++/2007-01-02-UnboundedArray.cpp (removed)
@@ -1,14 +0,0 @@
-// Make sure unbounded arrays compile with debug information.
-// 
-// RUN: %llvmgcc -O0 -S -g %s
-
-// PR1068
-
-struct Object {
-  char buffer[];
-};
-
-int main(int argc, char** argv) {
-  new Object;
-  return 0;
-}



From echristo at apple.com  Fri Aug 19 18:18:13 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 23:18:13 -0000
Subject: [llvm-commits] [llvm] r138141 -
	/llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
Message-ID: <20110819231813.0F4ED2A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 18:18:12 2011
New Revision: 138141

URL: http://llvm.org/viewvc/llvm-project?rev=138141&view=rev
Log:
Remove obsolete test.

Removed:
    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp

Removed: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=138140&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (removed)
@@ -1,22 +0,0 @@
-// This is a regression test on debug info to make sure that we can access 
-// qualified global names.
-// RUN: %llvmgcc -S -O0 -g %s -o - | \
-// RUN:   llc -disable-cfi --disable-fp-elim -o %t.s -O0
-// RUN: %compile_c %t.s -o %t.o
-// RUN: %link %t.o -o %t.exe
-// RUN: %llvmdsymutil %t.exe 
-// RUN: echo {break main\nrun\np Pubnames::pubname} > %t.in
-// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | grep {\$1 = 10}
-//
-// XFAIL: alpha,arm
-
-struct Pubnames {
-  static int pubname;
-};
-
-int Pubnames::pubname = 10;
-
-int main (int argc, char** argv) {
-  Pubnames p;
-  return 0;
-}



From stoklund at 2pi.dk  Fri Aug 19 18:21:02 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 19 Aug 2011 16:21:02 -0700
Subject: [llvm-commits] [llvm] r138137 -
 /llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
In-Reply-To: <20110819231031.51A7D2A6C12C@llvm.org>
References: <20110819231031.51A7D2A6C12C@llvm.org>
Message-ID: <5D2483A0-340E-443B-A0F4-0B86E79803C2@2pi.dk>


On Aug 19, 2011, at 4:10 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Fri Aug 19 18:10:31 2011
> New Revision: 138137
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138137&view=rev
> Log:
> Use regex to remove false dependencies on register allocation.
> 
> Modified:
>    llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
> 
> Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=138137&r1=138136&r2=138137&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Fri Aug 19 18:10:31 2011
> @@ -6,9 +6,9 @@
> define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
>  entry:
> ; CHECK: t:
> -; CHECK: muls r2, r2, r3
> -; CHECK-NEXT: mul  r0, r0, r1
> -; CHECK-NEXT: muls r0, r0, r2
> +; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
> +; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r0, r1
> +; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
>   %0 = mul nsw i32 %a, %b
>   %1 = mul nsw i32 %c, %d
>   %2 = mul nsw i32 %0, %1

Thanks!

/jakob


From grosbach at apple.com  Fri Aug 19 18:24:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 19 Aug 2011 23:24:36 -0000
Subject: [llvm-commits] [llvm] r138143 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb.s
Message-ID: <20110819232436.6FDB52A6C12C@llvm.org>

Author: grosbach
Date: Fri Aug 19 18:24:36 2011
New Revision: 138143

URL: http://llvm.org/viewvc/llvm-project?rev=138143&view=rev
Log:
Thumb parsing and encoding support for NOP.

The irony is not lost that this is not a completely trivial patchset.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
    llvm/trunk/test/MC/ARM/thumb.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138143&r1=138142&r2=138143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 18:24:36 2011
@@ -237,7 +237,8 @@
 }
 
 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
-           T1SystemEncoding<0x00>; // A8.6.110
+           T1SystemEncoding<0x00>, // A8.6.110
+        Requires<[IsThumb2]>;
 
 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
            T1SystemEncoding<0x10>; // A8.6.410
@@ -1382,3 +1383,8 @@
                   2, IIC_Br, [(brind GPR:$Rm)],
                   (tMOVr PC, GPR:$Rm, pred:$p)>;
 }
+
+
+// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
+// encoding is available on ARMv6K, but we don't differentiate that finely.
+def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138143&r1=138142&r2=138143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 18:24:36 2011
@@ -2846,6 +2846,7 @@
       Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
       Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
       Mnemonic == "setend" ||
+      (Mnemonic == "nop" && isThumbOne()) ||
       ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
       ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
         && !isThumb()) ||

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=138143&r1=138142&r2=138143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Fri Aug 19 18:24:36 2011
@@ -169,6 +169,13 @@
     return;
   }
 
+  // Thumb1 NOP
+  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
+      MI->getOperand(1).getReg() == ARM::R8) {
+    O << "\tnop";
+    return;
+  }
+
   printInstruction(MI, O);
 }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138143&r1=138142&r2=138143&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 18:24:36 2011
@@ -347,3 +347,11 @@
         negs r3, r4
 
 @ CHECK: rsbs	r3, r4, #0              @ encoding: [0x63,0x42]
+
+
+ at ------------------------------------------------------------------------------
+@ NOP
+ at ------------------------------------------------------------------------------
+        nop
+
+@ CHECK: nop                            @ encoding: [0xc0,0x46]

Modified: llvm/trunk/test/MC/ARM/thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb.s?rev=138143&r1=138142&r2=138143&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb.s (original)
+++ llvm/trunk/test/MC/ARM/thumb.s Fri Aug 19 18:24:36 2011
@@ -42,7 +42,7 @@
 @ CHECK: bkpt  #2                       @ encoding: [0x02,0xbe]
 
         nop
-@ CHECK: nop @ encoding: [0x00,0xbf]
+@ CHECK: nop @ encoding: [0xc0,0x46]
 
         wfe
         wfi



From dpatel at apple.com  Fri Aug 19 18:28:12 2011
From: dpatel at apple.com (Devang Patel)
Date: Fri, 19 Aug 2011 23:28:12 -0000
Subject: [llvm-commits] [llvm] r138145 - in /llvm/trunk:
 docs/SourceLevelDebugging.html include/llvm/Analysis/DebugInfo.h
 lib/Analysis/DIBuilder.cpp lib/Analysis/DebugInfo.cpp
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp test/CodeGen/ARM/debug-info-sreg2.ll
 test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
Message-ID: <20110819232812.6189B2A6C12C@llvm.org>

Author: dpatel
Date: Fri Aug 19 18:28:12 2011
New Revision: 138145

URL: http://llvm.org/viewvc/llvm-project?rev=138145&view=rev
Log:
Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly.

Modified:
    llvm/trunk/docs/SourceLevelDebugging.html
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DIBuilder.cpp
    llvm/trunk/lib/Analysis/DebugInfo.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
    llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Fri Aug 19 18:28:12 2011
@@ -433,6 +433,7 @@
   Function *,;; Pointer to LLVM function
   metadata, ;; Lists function template parameters
   metadata  ;; Function declaration descriptor
+  metadata  ;; List of function variables
 }
 </pre>
 </div>

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Fri Aug 19 18:28:12 2011
@@ -558,6 +558,8 @@
     DISubprogram getFunctionDeclaration() const {
       return getFieldAs<DISubprogram>(18);
     }
+    MDNode *getVariablesNodes() const;
+    DIArray getVariables() const;
   };
 
   /// DIGlobalVariable - This is a wrapper for a global variable.
@@ -736,11 +738,11 @@
 
   /// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable
   /// to hold function specific information.
-  NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, StringRef Name);
+  NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, DISubprogram SP);
 
   /// getFnSpecificMDNode - Return a NameMDNode, if available, that is 
   /// suitable to hold function specific information.
-  NamedMDNode *getFnSpecificMDNode(const Module &M, StringRef Name);
+  NamedMDNode *getFnSpecificMDNode(const Module &M, DISubprogram SP);
 
   /// createInlinedVariable - Create a new inlined variable based on current
   /// variable.

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Fri Aug 19 18:28:12 2011
@@ -43,6 +43,19 @@
 
   DIArray SPs = getOrCreateArray(AllSubprograms);
   DIType(TempSubprograms).replaceAllUsesWith(SPs);
+  for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) {
+    DISubprogram SP(SPs.getElement(i));
+    if (NamedMDNode *NMD = getFnSpecificMDNode(M, SP)) {
+      SmallVector<Value *, 4> Variables;
+      for (unsigned ii = 0, ee = NMD->getNumOperands(); ii != ee; ++ii)
+        Variables.push_back(NMD->getOperand(ii));
+      if (MDNode *Temp = SP.getVariablesNodes()) {
+        DIArray AV = getOrCreateArray(Variables);
+        DIType(Temp).replaceAllUsesWith(AV);
+      }
+      NMD->eraseFromParent();
+    }
+  }
 
   DIArray GVs = getOrCreateArray(AllGVs);
   DIType(TempGVs).replaceAllUsesWith(GVs);
@@ -674,13 +687,7 @@
     // to preserve variable info in such situation then stash it in a
     // named mdnode.
     DISubprogram Fn(getDISubprogram(Scope));
-    StringRef FName = "fn";
-    if (Fn.getFunction())
-      FName = Fn.getFunction()->getName();
-    char One = '\1';
-    if (FName.startswith(StringRef(&One, 1)))
-      FName = FName.substr(1);
-    NamedMDNode *FnLocals = getOrInsertFnSpecificMDNode(M, FName);
+    NamedMDNode *FnLocals = getOrInsertFnSpecificMDNode(M, Fn);
     FnLocals->addOperand(Node);
   }
   return DIVariable(Node);
@@ -718,6 +725,11 @@
                                        Function *Fn,
                                        MDNode *TParams,
                                        MDNode *Decl) {
+  Value *TElts[] = { GetTagConstant(VMContext, DW_TAG_base_type) };
+  MDNode *Temp = MDNode::getTemporary(VMContext, TElts);
+  Value *TVElts[] = { Temp };
+  MDNode *THolder = MDNode::get(VMContext, TVElts);
+
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
@@ -737,7 +749,8 @@
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
     Fn,
     TParams,
-    Decl
+    Decl,
+    THolder
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
 
@@ -760,6 +773,11 @@
                                      bool isOptimized,
                                      Function *Fn,
                                      MDNode *TParam) {
+  Value *TElts[] = { GetTagConstant(VMContext, DW_TAG_base_type) };
+  MDNode *Temp = MDNode::getTemporary(VMContext, TElts);
+  Value *TVElts[] = { Temp };
+  MDNode *THolder = MDNode::get(VMContext, TVElts);
+
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
@@ -779,6 +797,8 @@
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
     Fn,
     TParam,
+    llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
+    THolder
   };
   MDNode *Node = MDNode::get(VMContext, Elts);
   return DISubprogram(Node);

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Fri Aug 19 18:28:12 2011
@@ -512,6 +512,23 @@
   return 0;
 }
 
+MDNode *DISubprogram::getVariablesNodes() const {
+  if (!DbgNode || DbgNode->getNumOperands() <= 19)
+    return NULL;
+  if (MDNode *Temp = dyn_cast_or_null<MDNode>(DbgNode->getOperand(19)))
+    return dyn_cast_or_null<MDNode>(Temp->getOperand(0));
+  return NULL;
+}
+
+DIArray DISubprogram::getVariables() const {
+  if (!DbgNode || DbgNode->getNumOperands() <= 19)
+    return DIArray();
+  if (MDNode *T = dyn_cast_or_null<MDNode>(DbgNode->getOperand(19)))
+    if (MDNode *A = dyn_cast_or_null<MDNode>(T->getOperand(0)))
+      return DIArray(A);
+  return DIArray();
+}
+
 StringRef DIScope::getFilename() const {
   if (!DbgNode)
     return StringRef();
@@ -825,19 +842,34 @@
 
 /// getFnSpecificMDNode - Return a NameMDNode, if available, that is 
 /// suitable to hold function specific information.
-NamedMDNode *llvm::getFnSpecificMDNode(const Module &M, StringRef FuncName) {
+NamedMDNode *llvm::getFnSpecificMDNode(const Module &M, DISubprogram Fn) {
   SmallString<32> Name = StringRef("llvm.dbg.lv.");
-  fixupObjcLikeName(FuncName, Name);
-
+  StringRef FName = "fn";
+  if (Fn.getFunction())
+    FName = Fn.getFunction()->getName();
+  else
+    FName = Fn.getName();
+  char One = '\1';
+  if (FName.startswith(StringRef(&One, 1)))
+    FName = FName.substr(1);
+  fixupObjcLikeName(FName, Name);
   return M.getNamedMetadata(Name.str());
 }
 
 /// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable
 /// to hold function specific information.
-NamedMDNode *llvm::getOrInsertFnSpecificMDNode(Module &M, StringRef FuncName) {
+NamedMDNode *llvm::getOrInsertFnSpecificMDNode(Module &M, DISubprogram Fn) {
   SmallString<32> Name = StringRef("llvm.dbg.lv.");
-  fixupObjcLikeName(FuncName, Name);
-
+  StringRef FName = "fn";
+  if (Fn.getFunction())
+    FName = Fn.getFunction()->getName();
+  else
+    FName = Fn.getName();
+  char One = '\1';
+  if (FName.startswith(StringRef(&One, 1)))
+    FName = FName.substr(1);
+  fixupObjcLikeName(FName, Name);
+  
   return M.getOrInsertNamedMetadata(Name.str());
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Aug 19 18:28:12 2011
@@ -667,31 +667,24 @@
         if (ProcessedSPNodes.count(SP) != 0) continue;
         if (!SP.Verify()) continue;
         if (!SP.isDefinition()) continue;
-        StringRef FName = SP.getLinkageName();
-        if (FName.empty())
-          FName = SP.getName();
-        NamedMDNode *NMD = getFnSpecificMDNode(*(MMI->getModule()), FName);
-        if (!NMD) continue;
-        unsigned E = NMD->getNumOperands();
-        if (!E) continue;
+        DIArray Variables = SP.getVariables();
+        if (Variables.getNumElements() == 0) continue;
+
         LexicalScope *Scope = 
           new LexicalScope(NULL, DIDescriptor(SP), NULL, false);
         DeadFnScopeMap[SP] = Scope;
         
         // Construct subprogram DIE and add variables DIEs.
-        SmallVector<DbgVariable, 8> Variables;
-        for (unsigned I = 0; I != E; ++I) {
-          DIVariable DV(NMD->getOperand(I));
-          if (!DV.Verify()) continue;
-          Variables.push_back(DbgVariable(DV, NULL));
-        }
         CompileUnit *SPCU = CUMap.lookup(TheCU);
         assert (SPCU && "Unable to find Compile Unit!");
         constructSubprogramDIE(SPCU, SP);
         DIE *ScopeDIE = SPCU->getDIE(SP);
-        for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
+        for (unsigned vi = 0, ve = Variables.getNumElements(); vi != ve; ++vi) {
+          DIVariable DV(Variables.getElement(vi));
+          if (!DV.Verify()) continue;
+          DbgVariable *NewVar = new DbgVariable(DV, NULL);
           if (DIE *VariableDIE = 
-              SPCU->constructVariableDIE(&Variables[i], Scope->isAbstractScope()))
+              SPCU->constructVariableDIE(NewVar, Scope->isAbstractScope()))
             ScopeDIE->addChild(VariableDIE);
         }
       }
@@ -977,15 +970,14 @@
   }
 
   // Collect info for variables that were optimized out.
-  const Function *F = MF->getFunction();
-  if (NamedMDNode *NMD = getFnSpecificMDNode(*(F->getParent()), F->getName())) {
-    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
-      DIVariable DV(cast<MDNode>(NMD->getOperand(i)));
-      if (!DV || !Processed.insert(DV))
-        continue;
-      if (LexicalScope *Scope = LScopes.findLexicalScope(DV.getContext()))
-        addScopeVariable(Scope, new DbgVariable(DV, NULL));
-    }
+  LexicalScope *FnScope = LScopes.getCurrentFunctionScope();
+  DIArray Variables = DISubprogram(FnScope->getScopeNode()).getVariables();
+  for (unsigned i = 0, e = Variables.getNumElements(); i != e; ++i) {
+    DIVariable DV(Variables.getElement(i));
+    if (!DV || !DV.Verify() || !Processed.insert(DV))
+      continue;
+    if (LexicalScope *Scope = LScopes.findLexicalScope(DV.getContext()))
+      addScopeVariable(Scope, new DbgVariable(DV, NULL));
   }
 }
 
@@ -1320,18 +1312,13 @@
     DISubprogram SP(AScope->getScopeNode());
     if (SP.Verify()) {
       // Collect info for variables that were optimized out.
-      StringRef FName = SP.getLinkageName();
-      if (FName.empty())
-        FName = SP.getName();
-      if (NamedMDNode *NMD = 
-          getFnSpecificMDNode(*(MF->getFunction()->getParent()), FName)) {
-        for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
-          DIVariable DV(cast<MDNode>(NMD->getOperand(i)));
-          if (!DV || !ProcessedVars.insert(DV))
-            continue;
-          if (LexicalScope *Scope = LScopes.findAbstractScope(DV.getContext()))
-            addScopeVariable(Scope, new DbgVariable(DV, NULL));
-        }
+      DIArray Variables = SP.getVariables();
+      for (unsigned i = 0, e = Variables.getNumElements(); i != e; ++i) {
+        DIVariable DV(Variables.getElement(i));
+        if (!DV || !DV.Verify() || !ProcessedVars.insert(DV))
+          continue;
+        if (LexicalScope *Scope = LScopes.findAbstractScope(DV.getContext()))
+          addScopeVariable(Scope, new DbgVariable(DV, NULL));
       }
     }
     if (ProcessedSPNodes.count(AScope->getScopeNode()) == 0)

Modified: llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll Fri Aug 19 18:28:12 2011
@@ -6,8 +6,8 @@
 ;CHECK: Ldebug_loc0:
 ;CHECK-NEXT:        .long   Ltmp1
 ;CHECK-NEXT:        .long   Ltmp2
-;CHECK-NEXT: Lset9 = Ltmp10-Ltmp9                    @ Loc expr size
-;CHECK-NEXT:        .short  Lset9
+;CHECK-NEXT: Lset8 = Ltmp10-Ltmp9                    @ Loc expr size
+;CHECK-NEXT:        .short  Lset8
 ;CHECK-NEXT: Ltmp9:
 ;CHECK-NEXT:        .byte   144                     @ DW_OP_regx for S register
 

Modified: llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll?rev=138145&r1=138144&r2=138145&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll (original)
+++ llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll Fri Aug 19 18:28:12 2011
@@ -26,7 +26,7 @@
 !llvm.dbg.lv.foo = !{!9, !10}
 !llvm.dbg.gv = !{!16}
 
-!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !24} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 524329, metadata !"bar.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ]
 !2 = metadata !{i32 524305, i32 0, i32 1, metadata !"bar.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
@@ -50,3 +50,6 @@
 !21 = metadata !{i32 9, i32 0, metadata !11, metadata !17}
 !22 = metadata !{i32 11, i32 0, metadata !11, metadata !17}
 !23 = metadata !{i32 16, i32 0, metadata !18, null}
+!24 = metadata !{metadata !25}
+!25 = metadata !{metadata !9, metadata !10}
+



From grosser at fim.uni-passau.de  Fri Aug 19 18:34:28 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Fri, 19 Aug 2011 23:34:28 -0000
Subject: [llvm-commits] [polly] r138147 -
	/polly/trunk/lib/Analysis/ScopInfo.cpp
Message-ID: <20110819233428.3C8CD2A6C12C@llvm.org>

Author: grosser
Date: Fri Aug 19 18:34:28 2011
New Revision: 138147

URL: http://llvm.org/viewvc/llvm-project?rev=138147&view=rev
Log:
ScopInfo: Construct the accessrelations with isl_pw_aff

This simplifies the code quite a bit.

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=138147&r1=138146&r2=138147&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Fri Aug 19 18:34:28 2011
@@ -303,22 +303,6 @@
   }
 };
 
-static isl_map *getValueOf(const SCEVAffFunc &AffFunc,
-                           const ScopStmt *Statement, isl_dim *dim) {
-  assert((AffFunc.getType() == SCEVAffFunc::Eq
-          || AffFunc.getType() == SCEVAffFunc::ReadMem
-          || AffFunc.getType() == SCEVAffFunc::WriteMem)
-          && "AffFunc is not an equality");
-  isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV,
-                                               AffFunc.getBaseAddr());
-  isl_map *Map = isl_map_from_pw_aff(Affine);
-  isl_dim *CtxDim = isl_set_get_dim(Statement->getParent()->getContext());
-
-  isl_map_align_params(Map, CtxDim);
-  const char *dimname = isl_dim_get_tuple_name(dim, isl_dim_set);
-  Map = isl_map_set_tuple_name(Map, isl_dim_in, dimname);
-  return Map;
-}
 //===----------------------------------------------------------------------===//
 
 MemoryAccess::~MemoryAccess() {
@@ -376,36 +360,31 @@
 
   setBaseName();
 
-  isl_dim *dim = isl_dim_set_alloc(Statement->getIslContext(),
-                                   Statement->getNumParams(),
-                                   Statement->getNumIterators());
-  dim = isl_dim_set_tuple_name(dim, isl_dim_set, Statement->getBaseName());
-
-  AccessRelation = getValueOf(AffFunc, Statement, dim);
-
-  // Devide the access function by the size of the elements in the function.
-  isl_dim *dim2 = isl_dim_alloc(Statement->getIslContext(),
-                                0, 1, 1);
-  isl_basic_map *bmap = isl_basic_map_universe(isl_dim_copy(dim2));
-  isl_constraint *c = isl_equality_alloc(dim2);
+  isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV,
+                                               AffFunc.getBaseAddr());
+
+  // Devide the access function by the size of the elements in the array.
+  //
+  // A stride one array access in C expressed as A[i] is expressed in LLVM-IR
+  // as something like A[i * elementsize]. This hides the fact that two
+  // subsequent values of 'i' index two values that are stored next to each
+  // other in memory. By this devision we make this characteristic obvious
+  // again.
   isl_int v;
   isl_int_init(v);
-  isl_int_set_si(v, -1);
-  isl_constraint_set_coefficient(c, isl_dim_in, 0, v);
   isl_int_set_si(v, AffFunc.getElemSizeInBytes());
-  isl_constraint_set_coefficient(c, isl_dim_out, 0, v);
-
-  bmap = isl_basic_map_add_constraint(bmap, c);
-  isl_map* dataSizeMap = isl_map_from_basic_map(bmap);
-
-  isl_dim *Model = isl_set_get_dim(Statement->getParent()->getContext());
-  dataSizeMap = isl_map_align_params(dataSizeMap, Model);
-
-  AccessRelation = isl_map_apply_range(AccessRelation, dataSizeMap);
+  Affine = isl_pw_aff_scale_down(Affine, v);
+  isl_int_clear(v);
 
+  AccessRelation = isl_map_from_pw_aff(Affine);
+  AccessRelation = isl_map_set_tuple_name(AccessRelation, isl_dim_in,
+                                          Statement->getBaseName());
   AccessRelation = isl_map_set_tuple_name(AccessRelation, isl_dim_out,
                                           getBaseName().c_str());
 
+  isl_dim *Model = isl_set_get_dim(Statement->getParent()->getContext());
+  AccessRelation = isl_map_align_params(AccessRelation, Model);
+
   // FIXME: Temporarily remove dimension ids.
   AccessRelation = map_remove_dim_ids(AccessRelation);
 }



From echristo at apple.com  Fri Aug 19 18:41:50 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 19 Aug 2011 23:41:50 -0000
Subject: [llvm-commits] [llvm] r138149 - /llvm/trunk/test/FrontendC++/
Message-ID: <20110819234150.5213A2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 18:41:50 2011
New Revision: 138149

URL: http://llvm.org/viewvc/llvm-project?rev=138149&view=rev
Log:
Remove migrated or obsolete tests.

Removed:
    llvm/trunk/test/FrontendC++/2005-02-11-AnonymousUnion.cpp
    llvm/trunk/test/FrontendC++/2005-02-13-BadDynamicInit.cpp
    llvm/trunk/test/FrontendC++/2005-02-14-BitFieldOffset.cpp
    llvm/trunk/test/FrontendC++/2005-02-19-BitfieldStructCrash.cpp
    llvm/trunk/test/FrontendC++/2005-02-19-UnnamedVirtualThunkArgument.cpp
    llvm/trunk/test/FrontendC++/2005-02-20-BrokenReferenceTest.cpp
    llvm/trunk/test/FrontendC++/2005-02-27-PlacementArrayNewCrash.cpp
    llvm/trunk/test/FrontendC++/2005-07-21-VirtualBaseAccess.cpp
    llvm/trunk/test/FrontendC++/2006-03-01-GimplifyCrash.cpp
    llvm/trunk/test/FrontendC++/2006-03-06-C++RecurseCrash.cpp
    llvm/trunk/test/FrontendC++/2006-09-08-powi.cpp
    llvm/trunk/test/FrontendC++/2006-09-12-OpaqueStructCrash.cpp
    llvm/trunk/test/FrontendC++/2006-09-27-Debug-Protection.cpp
    llvm/trunk/test/FrontendC++/2006-10-30-ClassBitfield.cpp
    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
    llvm/trunk/test/FrontendC++/2006-11-20-GlobalSymbols.cpp
    llvm/trunk/test/FrontendC++/2006-11-30-ConstantExprCrash.cpp

Removed: llvm/trunk/test/FrontendC++/2005-02-11-AnonymousUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-11-AnonymousUnion.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-11-AnonymousUnion.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-11-AnonymousUnion.cpp (removed)
@@ -1,32 +0,0 @@
-// RUN: %llvmgxx %s -S -o -
-
-// Test anonymous union with members of the same size.
-int test1(float F) {
-  union {
-     float G;
-     int i;
-  };
-  G = F;
-  return i;
-}
-
-// test anonymous union with members of differing size.
-int test2(short F) {
-  volatile union {
-     short G;
-     int i;
-  };
-  G = F;
-  return i;
-}
-
-// Make sure that normal unions work.  duh :)
-volatile union U_t {
-  short S;
-  int i;
-} U;
-
-int test3(short s) {
-  U.S = s;
-  return U.i;
-}

Removed: llvm/trunk/test/FrontendC++/2005-02-13-BadDynamicInit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-13-BadDynamicInit.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-13-BadDynamicInit.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-13-BadDynamicInit.cpp (removed)
@@ -1,9 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | not grep llvm.global_ctors
-// This testcase corresponds to PR509
-struct Data {
-  unsigned *data;
-  unsigned array[1];
-};
-
-Data shared_null = { shared_null.array };
-

Removed: llvm/trunk/test/FrontendC++/2005-02-14-BitFieldOffset.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-14-BitFieldOffset.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-14-BitFieldOffset.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-14-BitFieldOffset.cpp (removed)
@@ -1,11 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | not grep {i32 6}
-
-struct QVectorTypedData {
-    int size;
-    unsigned int sharable : 1;
-    unsigned short array[1];
-};
-
-void foo(QVectorTypedData *X) {
-  X->array[0] = 123;
-}

Removed: llvm/trunk/test/FrontendC++/2005-02-19-BitfieldStructCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-19-BitfieldStructCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-19-BitfieldStructCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-19-BitfieldStructCrash.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-
-struct QChar {unsigned short X; QChar(unsigned short); } ;
-
-struct Command {
-        Command(QChar c) : c(c) {}
-        unsigned int type : 4;
-        QChar c;
-    };
-
-Command X(QChar('c'));
-
-void Foo(QChar );
-void bar() { Foo(X.c); }

Removed: llvm/trunk/test/FrontendC++/2005-02-19-UnnamedVirtualThunkArgument.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-19-UnnamedVirtualThunkArgument.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-19-UnnamedVirtualThunkArgument.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-19-UnnamedVirtualThunkArgument.cpp (removed)
@@ -1,22 +0,0 @@
-// RUN: %llvmgxx -S %s -o /dev/null
-
-struct Foo  {
-    Foo();
-    virtual ~Foo();
-};
-
-struct Bar  {
-    Bar();
-    virtual ~Bar();
-    virtual bool test(bool) const;
-};
-
-struct Baz : public Foo, public Bar  {
-    Baz();
-    virtual ~Baz();
-    virtual bool test(bool) const;
-};
-
-bool Baz::test(bool) const  {
-    return true;
-}

Removed: llvm/trunk/test/FrontendC++/2005-02-20-BrokenReferenceTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-20-BrokenReferenceTest.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-20-BrokenReferenceTest.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-20-BrokenReferenceTest.cpp (removed)
@@ -1,11 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-
-void test(unsigned char *b, int rb) {
-  typedef unsigned char imgfoo[10][rb];
-  imgfoo &br = *(imgfoo *)b;
-
-  br[0][0] = 1;
-
-  rb = br[0][0];
-}
-

Removed: llvm/trunk/test/FrontendC++/2005-02-27-PlacementArrayNewCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-02-27-PlacementArrayNewCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-02-27-PlacementArrayNewCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-02-27-PlacementArrayNewCrash.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-
-#include <new>
-typedef double Ty[4];
-
-void foo(Ty *XX) {
-  new(XX) Ty();
-}

Removed: llvm/trunk/test/FrontendC++/2005-07-21-VirtualBaseAccess.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-07-21-VirtualBaseAccess.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-07-21-VirtualBaseAccess.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-07-21-VirtualBaseAccess.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -xc++ %s -S -o - | opt -die -S | not grep cast
-
-void foo(int*);
-
-struct FOO {
-  int X;
-};
-
-struct BAR : virtual FOO { BAR(); };
-
-int testfn() {
-  BAR B;
-  foo(&B.X);
-}

Removed: llvm/trunk/test/FrontendC++/2006-03-01-GimplifyCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-03-01-GimplifyCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-03-01-GimplifyCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-03-01-GimplifyCrash.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -S %s -o -
-
-struct PrefMapElem {
-  virtual ~PrefMapElem(); 
-  unsigned int fPrefId;
-};
-
-int foo() {
-  PrefMapElem* fMap;
-  if (fMap[0].fPrefId == 1)
-    return 1;
-  
-  return 0;
-}

Removed: llvm/trunk/test/FrontendC++/2006-03-06-C++RecurseCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-03-06-C%2B%2BRecurseCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-03-06-C++RecurseCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-03-06-C++RecurseCrash.cpp (removed)
@@ -1,24 +0,0 @@
-// RUN: %llvmgcc %s -S -o -
-namespace std {
-  class exception { };
-
-  class type_info {
-  public:
-    virtual ~type_info();
-  };
-
-}
-
-namespace __cxxabiv1 {
-  class __si_class_type_info : public std::type_info {
-    ~__si_class_type_info();
-  };
-}
-
-class recursive_init: public std::exception {
-public:
-  virtual ~recursive_init() throw ();
-};
-
-recursive_init::~recursive_init() throw() { }
-

Removed: llvm/trunk/test/FrontendC++/2006-09-08-powi.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-09-08-powi.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-09-08-powi.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-09-08-powi.cpp (removed)
@@ -1,7 +0,0 @@
-// RUN: %llvmgxx -O3 -S -o - %s
-
-#include <cmath>
-
-double foo(double X, int Y) {
-  return std::pow(X, Y);
-}

Removed: llvm/trunk/test/FrontendC++/2006-09-12-OpaqueStructCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-09-12-OpaqueStructCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-09-12-OpaqueStructCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-09-12-OpaqueStructCrash.cpp (removed)
@@ -1,28 +0,0 @@
-// RUN: %llvmgxx -O3 -S -o - %s
-
-struct A {
-   virtual ~A();
-};
-
-template <typename Ty>
-struct B : public A {
-   ~B () { delete [] val; }
-private:
-     Ty* val;
-};
-
-template <typename Ty>
-struct C : public A {
-   C ();
-   ~C ();
-};
-
-template <typename Ty>
-struct D : public A {
-     D () {}
-   private:
-     B<C<Ty> > blocks;
-};
-
-template class D<double>;
-

Removed: llvm/trunk/test/FrontendC++/2006-09-27-Debug-Protection.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-09-27-Debug-Protection.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-09-27-Debug-Protection.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-09-27-Debug-Protection.cpp (removed)
@@ -1,12 +0,0 @@
-// RUN: %llvmgxx -O0 -S -g -o - %s | grep {i32 1,}
-// RUN: %llvmgxx -O0 -S -g -o - %s | grep {i32 2,}
-class A {
-public:
-  int x;
-protected:
-  int y;
-private:
-  int z;
-};
-
-A a;

Removed: llvm/trunk/test/FrontendC++/2006-10-30-ClassBitfield.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-10-30-ClassBitfield.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-10-30-ClassBitfield.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-10-30-ClassBitfield.cpp (removed)
@@ -1,16 +0,0 @@
-// RUN: %llvmgxx %s -S -o -
-// PR954
-
-struct _Refcount_Base   {
-  unsigned long _M_ref_count;
-  int _M_ref_count_lock;
-  _Refcount_Base() : _M_ref_count(0) {}
-};
-
-struct _Rope_RopeRep : public _Refcount_Base 
-{
-public:
-  int _M_tag:8; 
-};
-
-int foo(_Rope_RopeRep* r) { return r->_M_tag; }

Removed: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (removed)
@@ -1,38 +0,0 @@
-// This is a regression test on debug info to make sure that we can get a
-// meaningful stack trace from a C++ program.
-// RUN: %llvmgcc -S -O0 -g %s -o - | \
-// RUN:    llc --disable-cfi --disable-fp-elim -o %t.s -O0 -relocation-model=pic
-// RUN: %compile_c %t.s -o %t.o
-// RUN: %link %t.o -o %t.exe
-// RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in 
-// RN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \
-// RN:   grep {#0  DeepStack::deepest.*(this=.*,.*x=33)}
-// RN: gdb -q -batch -n -x %t.in %t.exe | \
-// RN:   grep {#7  0x.* in main.*(argc=\[12\],.*argv=.*)}
-
-// Only works on ppc (but not apple-darwin9), x86 and x86_64.  Should
-// generalize?
-// XAIL: alpha,arm,powerpc-apple-darwin9
-
-#include <stdlib.h>
-
-class DeepStack {
-  int seedVal;
-public:
-  DeepStack(int seed) : seedVal(seed) {}
-
-  int shallowest( int x ) { return shallower(x + 1); }
-  int shallower ( int x ) { return shallow(x + 2); }
-  int shallow   ( int x ) { return deep(x + 3); }
-  int deep      ( int x ) { return deeper(x + 4); }
-  int deeper    ( int x ) { return deepest(x + 6); }
-  int deepest   ( int x ) { return x + 7; }
-
-  int runit() { return shallowest(seedVal); }
-};
-
-int main ( int argc, char** argv) {
-
-  DeepStack DS9( (argc > 1 ? atoi(argv[1]) : 0) );
-  return DS9.runit();
-}

Removed: llvm/trunk/test/FrontendC++/2006-11-20-GlobalSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-20-GlobalSymbols.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-20-GlobalSymbols.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-20-GlobalSymbols.cpp (removed)
@@ -1,10 +0,0 @@
-// PR1013
-// Check to make sure debug symbols use the correct name for globals and
-// functions.  Will not assemble if it fails to.
-// RUN: %llvmgcc_only -O0 -g -c %s
-
-int foo __asm__("f\001oo");
-
-int bar() {
-  return foo;
-}

Removed: llvm/trunk/test/FrontendC++/2006-11-30-ConstantExprCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-ConstantExprCrash.cpp?rev=138148&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-30-ConstantExprCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-30-ConstantExprCrash.cpp (removed)
@@ -1,27 +0,0 @@
-// RUN: %llvmgxx %s -S -o -
-// PR1027
-
-struct sys_var {
-  unsigned name_length;
-
-  bool no_support_one_shot;
-  sys_var() {}
-};
-
-
-struct sys_var_thd : public sys_var {
-};
-
-extern sys_var_thd sys_auto_is_null;
-
-sys_var *getsys_variables() {
-  return &sys_auto_is_null;
-}
-
-sys_var *sys_variables = &sys_auto_is_null;
-
-
-
-
-
-



From isanbard at gmail.com  Fri Aug 19 18:46:30 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 19 Aug 2011 23:46:30 -0000
Subject: [llvm-commits] [llvm] r138153 -
	/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20110819234630.64E562A6C12C@llvm.org>

Author: void
Date: Fri Aug 19 18:46:30 2011
New Revision: 138153

URL: http://llvm.org/viewvc/llvm-project?rev=138153&view=rev
Log:
If we're splitting the landing pad block and assigning it only one predecessor,
then don't split it a second time, since that block will be dead.

Modified:
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=138153&r1=138152&r2=138153&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Fri Aug 19 18:46:30 2011
@@ -541,50 +541,64 @@
   // Update the PHI nodes in OrigBB with the values coming from NewBB1.
   UpdatePHINodes(OrigBB, NewBB1, Preds, BI1, P, HasLoopExit);
 
-  // Create another basic block for the rest of OrigBB's predecessors.
-  BasicBlock *NewBB2 = BasicBlock::Create(OrigBB->getContext(),
-                                          OrigBB->getName() + Suffix2,
-                                          OrigBB->getParent(), OrigBB);
-  NewBBs.push_back(NewBB2);
-
-  // The new block unconditionally branches to the old block.
-  BranchInst *BI2 = BranchInst::Create(OrigBB, NewBB2);
-
   // Move the remaining edges from OrigBB to point to NewBB2.
   SmallVector<BasicBlock*, 8> NewBB2Preds;
   for (pred_iterator i = pred_begin(OrigBB), e = pred_end(OrigBB);
        i != e; ) {
     BasicBlock *Pred = *i++;
-    if (Pred == NewBB1 || Pred == NewBB2 ) continue;
+    if (Pred == NewBB1) continue;
     assert(!isa<IndirectBrInst>(Pred->getTerminator()) &&
            "Cannot split an edge from an IndirectBrInst");
-    Pred->getTerminator()->replaceUsesOfWith(OrigBB, NewBB2);
     NewBB2Preds.push_back(Pred);
     e = pred_end(OrigBB);
   }
 
-  // Update DominatorTree, LoopInfo, and LCCSA analysis information.
-  HasLoopExit = false;
-  UpdateAnalysisInformation(OrigBB, NewBB2, NewBB2Preds, P, HasLoopExit);
+  BasicBlock *NewBB2 = 0;
+  if (!NewBB2Preds.empty()) {
+    // Create another basic block for the rest of OrigBB's predecessors.
+    NewBB2 = BasicBlock::Create(OrigBB->getContext(),
+                                OrigBB->getName() + Suffix2,
+                                OrigBB->getParent(), OrigBB);
+    NewBBs.push_back(NewBB2);
+
+    // The new block unconditionally branches to the old block.
+    BranchInst *BI2 = BranchInst::Create(OrigBB, NewBB2);
+
+    // Move the remaining edges from OrigBB to point to NewBB2.
+    for (SmallVectorImpl<BasicBlock*>::iterator
+           i = NewBB2Preds.begin(), e = NewBB2Preds.end(); i != e; ++i)
+      (*i)->getTerminator()->replaceUsesOfWith(OrigBB, NewBB2);
+
+    // Update DominatorTree, LoopInfo, and LCCSA analysis information.
+    HasLoopExit = false;
+    UpdateAnalysisInformation(OrigBB, NewBB2, NewBB2Preds, P, HasLoopExit);
 
-  // Update the PHI nodes in OrigBB with the values coming from NewBB2.
-  UpdatePHINodes(OrigBB, NewBB2, NewBB2Preds, BI2, P, HasLoopExit);
+    // Update the PHI nodes in OrigBB with the values coming from NewBB2.
+    UpdatePHINodes(OrigBB, NewBB2, NewBB2Preds, BI2, P, HasLoopExit);
+  }
 
   LandingPadInst *LPad = OrigBB->getLandingPadInst();
   Instruction *Clone1 = LPad->clone();
   Clone1->setName(Twine("lpad") + Suffix1);
   NewBB1->getInstList().insert(NewBB1->getFirstInsertionPt(), Clone1);
 
-  Instruction *Clone2 = LPad->clone();
-  Clone2->setName(Twine("lpad") + Suffix2);
-  NewBB2->getInstList().insert(NewBB2->getFirstInsertionPt(), Clone2);
-
-  // Create a PHI node for the two cloned landingpad instructions.
-  PHINode *PN = PHINode::Create(LPad->getType(), 2, "lpad.phi", LPad);
-  PN->addIncoming(Clone1, NewBB1);
-  PN->addIncoming(Clone2, NewBB2);
-  LPad->replaceAllUsesWith(PN);
-  LPad->eraseFromParent();
+  if (NewBB2) {
+    Instruction *Clone2 = LPad->clone();
+    Clone2->setName(Twine("lpad") + Suffix2);
+    NewBB2->getInstList().insert(NewBB2->getFirstInsertionPt(), Clone2);
+
+    // Create a PHI node for the two cloned landingpad instructions.
+    PHINode *PN = PHINode::Create(LPad->getType(), 2, "lpad.phi", LPad);
+    PN->addIncoming(Clone1, NewBB1);
+    PN->addIncoming(Clone2, NewBB2);
+    LPad->replaceAllUsesWith(PN);
+    LPad->eraseFromParent();
+  } else {
+    // There is no second clone. Just replace the landing pad with the first
+    // clone.
+    LPad->replaceAllUsesWith(Clone1);
+    LPad->eraseFromParent();
+  }
 }
 
 /// FindFunctionBackedges - Analyze the specified function to find all of the



From grosser at fim.uni-passau.de  Fri Aug 19 19:03:28 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Sat, 20 Aug 2011 00:03:28 -0000
Subject: [llvm-commits] [polly] r138155 - in /polly/trunk/lib/Analysis:
	Dependences.cpp ScopInfo.cpp
Message-ID: <20110820000328.2C26F2A6C12C@llvm.org>

Author: grosser
Date: Fri Aug 19 19:03:28 2011
New Revision: 138155

URL: http://llvm.org/viewvc/llvm-project?rev=138155&view=rev
Log:
ScopInfo/Dependences: Use parameter ids everywhere

Modified:
    polly/trunk/lib/Analysis/Dependences.cpp
    polly/trunk/lib/Analysis/ScopInfo.cpp

Modified: polly/trunk/lib/Analysis/Dependences.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/Dependences.cpp?rev=138155&r1=138154&r2=138155&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/Dependences.cpp (original)
+++ polly/trunk/lib/Analysis/Dependences.cpp Fri Aug 19 19:03:28 2011
@@ -52,7 +52,9 @@
 }
 
 bool Dependences::runOnScop(Scop &S) {
-  isl_dim *dim = isl_dim_alloc(S.getCtx(), S.getNumParams(), 0, 0);
+  isl_dim *dim = isl_dim_alloc(S.getCtx(), 0, 0, 0);
+  isl_dim *Model = isl_set_get_dim(S.getContext());
+  dim = isl_dim_align_params(dim, Model);
 
   if (sink)
     isl_union_map_free(sink);
@@ -153,10 +155,13 @@
   if (LegalityCheckDisabled)
     return true;
 
-  isl_dim *dim = isl_dim_alloc(S.getCtx(), S.getNumParams(), 0, 0);
+  isl_dim *dim = isl_dim_alloc(S.getCtx(), 0, 0, 0);
 
   isl_union_map *schedule = isl_union_map_empty(dim);
 
+  isl_dim *Model = isl_set_get_dim(S.getContext());
+  schedule = isl_union_map_align_params(schedule, Model);
+
   for (Scop::iterator SI = S.begin(), SE = S.end(); SI != SE; ++SI) {
     ScopStmt *Stmt = *SI;
 
@@ -230,9 +235,11 @@
 }
 
 isl_union_map* getCombinedScheduleForDim(Scop *scop, unsigned dimLevel) {
-  isl_dim *dim = isl_dim_alloc(scop->getCtx(), scop->getNumParams(), 0, 0);
+  isl_dim *dim = isl_dim_alloc(scop->getCtx(), 0, 0, 0);
 
   isl_union_map *schedule = isl_union_map_empty(dim);
+  isl_dim *Model = isl_set_get_dim(scop->getContext());
+  schedule = isl_union_map_align_params(schedule, Model);
 
   for (Scop::iterator SI = scop->begin(), SE = scop->end(); SI != SE; ++SI) {
     ScopStmt *Stmt = *SI;

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=138155&r1=138154&r2=138155&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Fri Aug 19 19:03:28 2011
@@ -67,48 +67,6 @@
   return returnvalue;
 }
 
-static isl_set *set_remove_dim_ids(isl_set *set) {
-  isl_ctx *ctx = isl_set_get_ctx(set);
-  int numParams = isl_set_n_param(set);
-  isl_printer *p = isl_printer_to_str(ctx);
-  isl_set *new_set;
-  char *str;
-  const char *name = isl_set_get_tuple_name(set);
-
-  p = isl_printer_set_output_format (p, ISL_FORMAT_EXT_POLYLIB);
-  p = isl_printer_print_set(p, set);
-
-  str = isl_printer_get_str (p);
-  new_set = isl_set_read_from_str (ctx, str, numParams);
-  new_set = isl_set_set_tuple_name(new_set, name);
-  free (str);
-  isl_set_free (set);
-  isl_printer_free (p);
-  return new_set;
-}
-
-static isl_map *map_remove_dim_ids(isl_map *map) {
-  isl_ctx *ctx = isl_map_get_ctx(map);
-  int numParams = isl_map_n_param(map);
-  isl_printer *p = isl_printer_to_str(ctx);
-  char *str;
-  isl_map *new_map;
-  const char *name_in = isl_map_get_tuple_name(map, isl_dim_in);
-  const char *name_out = isl_map_get_tuple_name(map, isl_dim_out);
-
-  p = isl_printer_set_output_format (p, ISL_FORMAT_EXT_POLYLIB);
-  p = isl_printer_print_map(p, map);
-
-  str = isl_printer_get_str (p);
-  new_map = isl_map_read_from_str (ctx, str, numParams);
-  new_map = isl_map_set_tuple_name(new_map, isl_dim_in, name_in);
-  new_map = isl_map_set_tuple_name(new_map, isl_dim_out, name_out);
-  isl_map_free (map);
-  free (str);
-  isl_printer_free (p);
-  return new_map;
-}
-
 /// Translate a SCEVExpression into an isl_pw_aff object.
 struct SCEVAffinator : public SCEVVisitor<SCEVAffinator, isl_pw_aff*> {
 private:
@@ -341,8 +299,7 @@
 }
 
 isl_basic_map *MemoryAccess::createBasicAccessMap(ScopStmt *Statement) {
-  isl_dim *dim = isl_dim_alloc(Statement->getIslContext(),
-                               Statement->getNumParams(),
+  isl_dim *dim = isl_dim_alloc(Statement->getIslContext(), 0,
                                Statement->getNumIterators(), 1);
   setBaseName();
 
@@ -384,9 +341,6 @@
 
   isl_dim *Model = isl_set_get_dim(Statement->getParent()->getContext());
   AccessRelation = isl_map_align_params(AccessRelation, Model);
-
-  // FIXME: Temporarily remove dimension ids.
-  AccessRelation = map_remove_dim_ids(AccessRelation);
 }
 
 MemoryAccess::MemoryAccess(const Value *BaseAddress, ScopStmt *Statement) {
@@ -397,6 +351,8 @@
 
   isl_basic_map *BasicAccessMap = createBasicAccessMap(Statement);
   AccessRelation = isl_map_from_basic_map(BasicAccessMap);
+  isl_dim *Model = isl_set_get_dim(Statement->getParent()->getContext());
+  AccessRelation = isl_map_align_params(AccessRelation, Model);
 }
 
 void MemoryAccess::print(raw_ostream &OS) const {
@@ -542,8 +498,7 @@
 void ScopStmt::buildScattering(SmallVectorImpl<unsigned> &Scatter) {
   unsigned NumberOfIterators = getNumIterators();
   unsigned ScatDim = Parent.getMaxLoopDepth() * 2 + 1;
-  isl_dim *dim = isl_dim_alloc(Parent.getCtx(), Parent.getNumParams(),
-                               NumberOfIterators, ScatDim);
+  isl_dim *dim = isl_dim_alloc(Parent.getCtx(), 0, NumberOfIterators, ScatDim);
   dim = isl_dim_set_tuple_name(dim, isl_dim_out, "scattering");
   dim = isl_dim_set_tuple_name(dim, isl_dim_in, getBaseName());
   isl_basic_map *bmap = isl_basic_map_universe(isl_dim_copy(dim));
@@ -586,6 +541,8 @@
   isl_int_clear(v);
   isl_dim_free(dim);
   Scattering = isl_map_from_basic_map(bmap);
+  isl_dim *Model = isl_set_get_dim(getParent()->getContext());
+  Scattering = isl_map_align_params(Scattering, Model);
 }
 
 void ScopStmt::buildAccesses(TempScop &tempScop, const Region &CurRegion) {
@@ -742,10 +699,6 @@
   buildAccesses(tempScop, CurRegion);
 
   IsReduction = tempScop.is_Reduction(*BB);
-
-  // FIXME: Temporarily remove dimension ids.
-  Scattering = map_remove_dim_ids(Scattering);
-  Domain = set_remove_dim_ids(Domain);
 }
 
 ScopStmt::ScopStmt(Scop &parent, SmallVectorImpl<unsigned> &Scatter)
@@ -757,13 +710,13 @@
   std::string IterationDomainString = "{[i0] : i0 = 0}";
   Domain = isl_set_read_from_str(Parent.getCtx(), IterationDomainString.c_str(),
                                  -1);
-  Domain = isl_set_add_dims(Domain, isl_dim_param, Parent.getNumParams());
   Domain = isl_set_set_tuple_name(Domain, getBaseName());
+  isl_dim *Model = isl_set_get_dim(getParent()->getContext());
+  Domain = isl_set_align_params(Domain, isl_dim_copy(Model));
 
   // Build scattering.
   unsigned ScatDim = Parent.getMaxLoopDepth() * 2 + 1;
-  isl_dim *dim = isl_dim_alloc(Parent.getCtx(), Parent.getNumParams(), 1,
-                               ScatDim);
+  isl_dim *dim = isl_dim_alloc(Parent.getCtx(), 0, 1, ScatDim);
   dim = isl_dim_set_tuple_name(dim, isl_dim_out, "scattering");
   dim = isl_dim_set_tuple_name(dim, isl_dim_in, getBaseName());
   isl_basic_map *bmap = isl_basic_map_universe(isl_dim_copy(dim));
@@ -782,6 +735,7 @@
   bmap = isl_basic_map_add_constraint(bmap, c);
   isl_int_clear(v);
   Scattering = isl_map_from_basic_map(bmap);
+  Scattering = isl_map_align_params(Scattering, Model);
 
   // Build memory accesses, use SetVector to keep the order of memory accesses
   // and prevent the same memory access inserted more than once.
@@ -927,9 +881,6 @@
   buildScop(tempScop, getRegion(), NestLoops, Scatter, LI);
   Stmts.push_back(new ScopStmt(*this, Scatter));
 
-  // FIXME: Temporarily remove dimension ids
-  Context = set_remove_dim_ids(Context);
-
   assert(NestLoops.empty() && "NestLoops not empty at top level!");
 }
 



From echristo at apple.com  Fri Aug 19 19:08:37 2011
From: echristo at apple.com (Eric Christopher)
Date: Sat, 20 Aug 2011 00:08:37 -0000
Subject: [llvm-commits] [llvm] r138156 - in /llvm/trunk/test/FrontendC++:
 2004-03-08-ReinterpretCastCopy.cpp 2004-03-09-UnmangledBuiltinMethods.cpp
 2004-03-15-CleanupsAndGotos.cpp 2004-06-08-LateTemplateInstantiation.cpp
 2004-09-27-CompilerCrash.cpp 2004-09-27-DidntEmitTemplate.cpp
 2004-11-27-EmitsUnusedInlineFunctions.cpp
 2004-11-27-ExceptionCleanupAssertion.cpp
 2004-11-27-FriendDefaultArgCrash.cpp
 2004-11-27-InlineAsmFunctionRedefinition.cpp
 2005-01-03-StaticInitializers.cpp
Message-ID: <20110820000837.3462F2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 19:08:36 2011
New Revision: 138156

URL: http://llvm.org/viewvc/llvm-project?rev=138156&view=rev
Log:
Remove migrated or obsolete tests.

Removed:
    llvm/trunk/test/FrontendC++/2004-03-08-ReinterpretCastCopy.cpp
    llvm/trunk/test/FrontendC++/2004-03-09-UnmangledBuiltinMethods.cpp
    llvm/trunk/test/FrontendC++/2004-03-15-CleanupsAndGotos.cpp
    llvm/trunk/test/FrontendC++/2004-06-08-LateTemplateInstantiation.cpp
    llvm/trunk/test/FrontendC++/2004-09-27-CompilerCrash.cpp
    llvm/trunk/test/FrontendC++/2004-09-27-DidntEmitTemplate.cpp
    llvm/trunk/test/FrontendC++/2004-11-27-EmitsUnusedInlineFunctions.cpp
    llvm/trunk/test/FrontendC++/2004-11-27-ExceptionCleanupAssertion.cpp
    llvm/trunk/test/FrontendC++/2004-11-27-FriendDefaultArgCrash.cpp
    llvm/trunk/test/FrontendC++/2004-11-27-InlineAsmFunctionRedefinition.cpp
    llvm/trunk/test/FrontendC++/2005-01-03-StaticInitializers.cpp

Removed: llvm/trunk/test/FrontendC++/2004-03-08-ReinterpretCastCopy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-03-08-ReinterpretCastCopy.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-03-08-ReinterpretCastCopy.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-03-08-ReinterpretCastCopy.cpp (removed)
@@ -1,21 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-struct A {
-  virtual void Method() = 0;
-};
-
-struct B : public A {
-  virtual void Method() { }
-};
-
-typedef void (A::*fn_type_a)(void);
-typedef void (B::*fn_type_b)(void);
-
-int main(int argc, char **argv)
-{
-  fn_type_a f = reinterpret_cast<fn_type_a>(&B::Method);
-  fn_type_b g = reinterpret_cast<fn_type_b>(f);
-  B b;
-  (b.*g)();
-  return 0;
-}

Removed: llvm/trunk/test/FrontendC++/2004-03-09-UnmangledBuiltinMethods.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-03-09-UnmangledBuiltinMethods.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-03-09-UnmangledBuiltinMethods.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-03-09-UnmangledBuiltinMethods.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgcc -xc++ -S -o - %s | grep _ZN11AccessFlags6strlenEv
-
-struct AccessFlags {
-  void strlen();
-};
-
-void AccessFlags::strlen() { }
-

Removed: llvm/trunk/test/FrontendC++/2004-03-15-CleanupsAndGotos.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-03-15-CleanupsAndGotos.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-03-15-CleanupsAndGotos.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-03-15-CleanupsAndGotos.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-// Testcase from Bug 291
-
-struct X {
-  ~X();
-};
-
-void foo() {
-  X v;
-
-TryAgain:
-  goto TryAgain;
-}

Removed: llvm/trunk/test/FrontendC++/2004-06-08-LateTemplateInstantiation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-06-08-LateTemplateInstantiation.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-06-08-LateTemplateInstantiation.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-06-08-LateTemplateInstantiation.cpp (removed)
@@ -1,19 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-
-
-template<typename Ty>
-struct normal_iterator {
-  int FIELD;
-};
-
-void foo(normal_iterator<int>);
-normal_iterator<int> baz();
-
-void bar() {
-  foo(baz());
-}
-
-void *bar2() {
-  return (void*)foo;
-}

Removed: llvm/trunk/test/FrontendC++/2004-09-27-CompilerCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-09-27-CompilerCrash.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-09-27-CompilerCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-09-27-CompilerCrash.cpp (removed)
@@ -1,13 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-struct Pass {} ;
-template<typename PassName>
-Pass *callDefaultCtor() { return new PassName(); }
-
-void foo(Pass *(*C)());
-
-#include <string>
-
-bool foo(std::string &X) {
-  return X.empty();
-}

Removed: llvm/trunk/test/FrontendC++/2004-09-27-DidntEmitTemplate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-09-27-DidntEmitTemplate.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-09-27-DidntEmitTemplate.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-09-27-DidntEmitTemplate.cpp (removed)
@@ -1,23 +0,0 @@
-// RUN: %llvmgxx -xc++ %s -S -o - | grep callDefaultCtor | \
-// RUN:   not grep declare
-
-// This is a testcase for LLVM PR445, which was a problem where the 
-// instantiation of callDefaultCtor was not being emitted correctly.
-
-struct Pass {};
-
-template<typename PassName>
-Pass *callDefaultCtor() { return new Pass(); }
-
-void foo(Pass *(*C)());
-
-struct basic_string {
-  bool empty() const { return true; }
-};
-
-
-bool foo2(basic_string &X) {
-  return X.empty();
-}
-void baz() { foo(callDefaultCtor<Pass>); }
-

Removed: llvm/trunk/test/FrontendC++/2004-11-27-EmitsUnusedInlineFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-11-27-EmitsUnusedInlineFunctions.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-11-27-EmitsUnusedInlineFunctions.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-11-27-EmitsUnusedInlineFunctions.cpp (removed)
@@ -1,7 +0,0 @@
-// The C++ front-end was emitting WAY too many inline functions.  This test
-// verifies that it does not emit the body of getchar, because it is not used.
-// This corresponds to PR459
-
-// RUN: %llvmgxx %s -S -o - | not grep {^i32 .getchar}
-
-#include <stdio.h>

Removed: llvm/trunk/test/FrontendC++/2004-11-27-ExceptionCleanupAssertion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-11-27-ExceptionCleanupAssertion.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-11-27-ExceptionCleanupAssertion.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-11-27-ExceptionCleanupAssertion.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-
-// This is PR421
-
-struct Strongbad {
-    Strongbad(const char *str );
-    ~Strongbad();
-    operator const char *() const;
-};
-
-void TheCheat () {
-  Strongbad foo(0);
-  Strongbad dirs[] = { Strongbad(0) + 1};
-}

Removed: llvm/trunk/test/FrontendC++/2004-11-27-FriendDefaultArgCrash.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-11-27-FriendDefaultArgCrash.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-11-27-FriendDefaultArgCrash.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-11-27-FriendDefaultArgCrash.cpp (removed)
@@ -1,9 +0,0 @@
-// RUN: %llvmgxx %s -o /dev/null -S
-
-// PR447
-
-namespace nm {
-  struct str {
-    friend int foo(int arg = 0);
-  };
-}

Removed: llvm/trunk/test/FrontendC++/2004-11-27-InlineAsmFunctionRedefinition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-11-27-InlineAsmFunctionRedefinition.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-11-27-InlineAsmFunctionRedefinition.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-11-27-InlineAsmFunctionRedefinition.cpp (removed)
@@ -1,26 +0,0 @@
-// RUN: %llvmgxx %s -S -o /dev/null
-
-// PR397
-
-struct stat { };
-struct stat64 { };
-
-extern "C" {
-
-extern int lstat(const char *, struct stat *) __asm__("lstat64");
-extern int lstat64(const char *, struct stat64 *);
-
-extern int __lxstat(int, const char *, struct stat *) __asm__("__lxstat64");
-extern int __lxstat64(int, const char *, struct stat64 *);
-
-extern __inline__ int lstat(const char *path, struct stat *statbuf) {
-    return __lxstat(3, path, statbuf);
-}
-extern __inline__ int lstat64(const char *path, struct stat64 *statbuf) {
-    return __lxstat64(3, path, statbuf);
-}
-}
-
-int do_one_file(void) {
-    return lstat(0, 0) + lstat64(0,0);
-}

Removed: llvm/trunk/test/FrontendC++/2005-01-03-StaticInitializers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2005-01-03-StaticInitializers.cpp?rev=138155&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2005-01-03-StaticInitializers.cpp (original)
+++ llvm/trunk/test/FrontendC++/2005-01-03-StaticInitializers.cpp (removed)
@@ -1,8 +0,0 @@
-// RUN: %llvmgxx %s -S -o - | not grep llvm.global_ctor
-
-struct S {
-  int  A[2];
-};
-
-int XX = (int)(long)&(((struct S*)0)->A[1]);
-



From tonic at nondot.org  Fri Aug 19 19:10:20 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 20 Aug 2011 00:10:20 -0000
Subject: [llvm-commits] [www] r138158 - in /www/trunk: devmtg/index.html
	index.html
Message-ID: <20110820001020.835DC2A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 19:10:20 2011
New Revision: 138158

URL: http://llvm.org/viewvc/llvm-project?rev=138158&view=rev
Log:
Add 2011 Dev Meeting info.

Modified:
    www/trunk/devmtg/index.html
    www/trunk/index.html

Modified: www/trunk/devmtg/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/index.html?rev=138158&r1=138157&r2=138158&view=diff
==============================================================================
--- www/trunk/devmtg/index.html (original)
+++ www/trunk/devmtg/index.html Fri Aug 19 19:10:20 2011
@@ -2,7 +2,9 @@
 
 <div class="www_sectiontitle">LLVM Developers' Meeting</div>
 
-<!-- <p>The upcoming developer's meeting is on <a href="http://www.llvm.org/devmtg/2010-11/">November 4, 2010.</a></p> -->
+<p>The upcoming developer's meeting is on <a href="http://www.llvm.org/devmtg/2011-11/">November 18, 2011.</a></p>
+
+<p>There is also the European LLVM User Group Meeting on <a href="http://llvm.org/devmtg/2011-09-16/">Sepntember 16, 2011</a></p>
 
 <p>We have had these meetings so far:</p>
 

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=138158&r1=138157&r2=138158&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Fri Aug 19 19:10:20 2011
@@ -146,6 +146,7 @@
 <p>Current:</p>
 <ul>
 <li><a href="http://llvm.org/devmtg/2011-09-16/">September 16, 2011 - European User Group Meeting</a></li>
+<li><a href="http://llvm.org/devmtg/2011-11/">November 18, 2011 - LLVM Developers' Meeting</a></li>
 </ul>
 <p>Proceedings from past meetings:</p>
 <ul>



From tonic at nondot.org  Fri Aug 19 19:14:22 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 20 Aug 2011 00:14:22 -0000
Subject: [llvm-commits] [www] r138160 - /www/trunk/index.html
Message-ID: <20110820001422.3E0FD2A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 19:14:22 2011
New Revision: 138160

URL: http://llvm.org/viewvc/llvm-project?rev=138160&view=rev
Log:
Force update.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=138160&r1=138159&r2=138160&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Fri Aug 19 19:14:22 2011
@@ -148,6 +148,7 @@
 <li><a href="http://llvm.org/devmtg/2011-09-16/">September 16, 2011 - European User Group Meeting</a></li>
 <li><a href="http://llvm.org/devmtg/2011-11/">November 18, 2011 - LLVM Developers' Meeting</a></li>
 </ul>
+
 <p>Proceedings from past meetings:</p>
 <ul>
 <li><a href="http://www.llvm.org/devmtg/2010-11/">November 2010</a></li>



From tonic at nondot.org  Fri Aug 19 19:15:15 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 20 Aug 2011 00:15:15 -0000
Subject: [llvm-commits] [www] r138161 - /www/trunk/devmtg/index.html
Message-ID: <20110820001515.EF6842A6C12C@llvm.org>

Author: tbrethou
Date: Fri Aug 19 19:15:15 2011
New Revision: 138161

URL: http://llvm.org/viewvc/llvm-project?rev=138161&view=rev
Log:
Fix September typo

Modified:
    www/trunk/devmtg/index.html

Modified: www/trunk/devmtg/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/index.html?rev=138161&r1=138160&r2=138161&view=diff
==============================================================================
--- www/trunk/devmtg/index.html (original)
+++ www/trunk/devmtg/index.html Fri Aug 19 19:15:15 2011
@@ -4,7 +4,7 @@
 
 <p>The upcoming developer's meeting is on <a href="http://www.llvm.org/devmtg/2011-11/">November 18, 2011.</a></p>
 
-<p>There is also the European LLVM User Group Meeting on <a href="http://llvm.org/devmtg/2011-09-16/">Sepntember 16, 2011</a></p>
+<p>There is also the European LLVM User Group Meeting on <a href="http://llvm.org/devmtg/2011-09-16/">September 16, 2011</a></p>
 
 <p>We have had these meetings so far:</p>
 



From mcrosier at apple.com  Fri Aug 19 19:17:25 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 20 Aug 2011 00:17:25 -0000
Subject: [llvm-commits] [llvm] r138163 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp
 test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
Message-ID: <20110820001725.627722A6C12C@llvm.org>

Author: mcrosier
Date: Fri Aug 19 19:17:25 2011
New Revision: 138163

URL: http://llvm.org/viewvc/llvm-project?rev=138163&view=rev
Log:
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Aug 19 19:17:25 2011
@@ -628,7 +628,7 @@
   bool SPRDest = ARM::SPRRegClass.contains(DestReg);
   bool SPRSrc  = ARM::SPRRegClass.contains(SrcReg);
 
-  unsigned Opc;
+  unsigned Opc = 0;
   if (SPRDest && SPRSrc) {
     Opc = ARM::VMOVS;
 
@@ -668,17 +668,38 @@
     Opc = ARM::VORRq;
   else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
     Opc = ARM::VMOVQQ;
-  else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
-    Opc = ARM::VMOVQQQQ;
-  else
-    llvm_unreachable("Impossible reg-to-reg copy");
 
-  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
-  MIB.addReg(SrcReg, getKillRegState(KillSrc));
-  if (Opc == ARM::VORRq)
+  if (Opc) {
+    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
     MIB.addReg(SrcReg, getKillRegState(KillSrc));
-  if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
-    AddDefaultPred(MIB);
+    if (Opc == ARM::VORRq)
+      MIB.addReg(SrcReg, getKillRegState(KillSrc));
+    if (Opc != ARM::VMOVQQ)
+      AddDefaultPred(MIB);
+    return;
+  }
+
+  // Expand the MOVQQQQ pseudo instruction in place.
+  if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
+    const TargetRegisterInfo *TRI = &getRegisterInfo();
+    assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
+    for (unsigned i = ARM::qsub_0, e = ARM::qsub_3 + 1; i != e; ++i) { 
+      unsigned Dst = TRI->getSubReg(DestReg, i);
+      unsigned Src = TRI->getSubReg(SrcReg, i);
+      MachineInstrBuilder Mov =
+        AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
+                       .addReg(Dst, RegState::Define)
+                       .addReg(Src, getKillRegState(KillSrc))
+                       .addReg(Src, getKillRegState(KillSrc)));
+      if (i == ARM::qsub_3) {
+        Mov->addRegisterDefined(DestReg, TRI);
+        if (KillSrc)
+          Mov->addRegisterKilled(SrcReg, TRI);
+      }
+    }
+    return;
+  }
+  llvm_unreachable("Impossible reg-to-reg copy");
 }
 
 static const

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Aug 19 19:17:25 2011
@@ -998,52 +998,6 @@
       return true;
     }
 
-    case ARM::VMOVQQQQ: {
-      unsigned DstReg = MI.getOperand(0).getReg();
-      bool DstIsDead = MI.getOperand(0).isDead();
-      unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
-      unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
-      unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
-      unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
-      unsigned SrcReg = MI.getOperand(1).getReg();
-      bool SrcIsKill = MI.getOperand(1).isKill();
-      unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
-      unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
-      unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
-      unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
-      MachineInstrBuilder Mov0 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst0,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src0, getKillRegState(SrcIsKill))
-                       .addReg(Src0, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov1 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst1,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src1, getKillRegState(SrcIsKill))
-                       .addReg(Src1, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov2 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst2,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src2, getKillRegState(SrcIsKill))
-                       .addReg(Src2, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov3 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst3,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src3, getKillRegState(SrcIsKill))
-                       .addReg(Src3, getKillRegState(SrcIsKill)));
-      TransferImpOps(MI, Mov0, Mov3);
-      MI.eraseFromParent();
-      return true;
-    }
-
     case ARM::VLDMQIA: {
       unsigned NewOpc = ARM::VLDMDIA;
       MachineInstrBuilder MIB =

Modified: llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll Fri Aug 19 19:17:25 2011
@@ -1,7 +1,6 @@
 ; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 -o -
-; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
-; Make sure that it gets expanded; otherwise, the compile fails when trying
-; to print the pseudo-instruction.
+; Make sure that the VMOVQQQQ pseudo instruction is handled properly
+; by codegen.
 
 define void @test_vmovqqqq_pseudo() nounwind ssp {
 entry:



From stoklund at 2pi.dk  Fri Aug 19 19:17:45 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 20 Aug 2011 00:17:45 -0000
Subject: [llvm-commits] [llvm] r138164 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20110820001745.EC0CB2A6C12C@llvm.org>

Author: stoklund
Date: Fri Aug 19 19:17:45 2011
New Revision: 138164

URL: http://llvm.org/viewvc/llvm-project?rev=138164&view=rev
Log:
Add <imp-def> operands to QQ and QQQQ stack loads.

This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138164&r1=138163&r2=138164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Aug 19 19:17:45 2011
@@ -930,7 +930,8 @@
         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
-              AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
+        MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
+        MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
       }
     } else
       llvm_unreachable("Unknown reg class!");
@@ -948,7 +949,8 @@
       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
-      AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
+      MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
+      MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
     } else
       llvm_unreachable("Unknown reg class!");
     break;



From echristo at apple.com  Fri Aug 19 19:17:58 2011
From: echristo at apple.com (Eric Christopher)
Date: Sat, 20 Aug 2011 00:17:58 -0000
Subject: [llvm-commits] [llvm] r138165 - in /llvm/trunk/test/FrontendC++:
 2003-11-02-WeakLinkage.cpp 2003-11-18-PtrMemConstantInitializer.cpp
 2003-11-25-ReturningOpaqueByValue.cpp
 2003-11-27-MultipleInheritanceThunk.cpp
 2003-11-29-DuplicatedCleanupTest.cpp 2003-12-08-ArrayOfPtrToMemberFunc.cpp
 2004-01-11-DynamicInitializedConstant.cpp dg.exp
Message-ID: <20110820001758.A6CAD2A6C12C@llvm.org>

Author: echristo
Date: Fri Aug 19 19:17:58 2011
New Revision: 138165

URL: http://llvm.org/viewvc/llvm-project?rev=138165&view=rev
Log:
Remove the rest of the files in FrontendC++ and the directory itself.

All tests have been updated and migrated into clang or were obsolete.

Removed:
    llvm/trunk/test/FrontendC++/2003-11-02-WeakLinkage.cpp
    llvm/trunk/test/FrontendC++/2003-11-18-PtrMemConstantInitializer.cpp
    llvm/trunk/test/FrontendC++/2003-11-25-ReturningOpaqueByValue.cpp
    llvm/trunk/test/FrontendC++/2003-11-27-MultipleInheritanceThunk.cpp
    llvm/trunk/test/FrontendC++/2003-11-29-DuplicatedCleanupTest.cpp
    llvm/trunk/test/FrontendC++/2003-12-08-ArrayOfPtrToMemberFunc.cpp
    llvm/trunk/test/FrontendC++/2004-01-11-DynamicInitializedConstant.cpp
    llvm/trunk/test/FrontendC++/dg.exp

Removed: llvm/trunk/test/FrontendC++/2003-11-02-WeakLinkage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-11-02-WeakLinkage.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-11-02-WeakLinkage.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-11-02-WeakLinkage.cpp (removed)
@@ -1,13 +0,0 @@
-// RUN: %llvmgcc -xc++ -S -o - %s | not grep weak
-// The template should compile to linkonce linkage, not weak linkage.
-
-template<class T>
-void thefunc();
-
-template<class T>
-inline void thefunc() {}
-
-void test() {
-  thefunc<int>();
-}
-

Removed: llvm/trunk/test/FrontendC++/2003-11-18-PtrMemConstantInitializer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-11-18-PtrMemConstantInitializer.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-11-18-PtrMemConstantInitializer.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-11-18-PtrMemConstantInitializer.cpp (removed)
@@ -1,14 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-struct Gfx {
-  void opMoveSetShowText();
-};
-
-struct Operator {
-  void (Gfx::*func)();
-};
-
-Operator opTab[] = {
-  {&Gfx::opMoveSetShowText},
-};
-

Removed: llvm/trunk/test/FrontendC++/2003-11-25-ReturningOpaqueByValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-11-25-ReturningOpaqueByValue.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-11-25-ReturningOpaqueByValue.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-11-25-ReturningOpaqueByValue.cpp (removed)
@@ -1,12 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-#include <vector>
-std::vector<int> my_method ();
-
-int
-main ()
-{
-  my_method ();
-  return 0;
-}
-

Removed: llvm/trunk/test/FrontendC++/2003-11-27-MultipleInheritanceThunk.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-11-27-MultipleInheritanceThunk.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-11-27-MultipleInheritanceThunk.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-11-27-MultipleInheritanceThunk.cpp (removed)
@@ -1,28 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-
-struct CallSite {
-  int X;
-
-  CallSite(const CallSite &CS);
-};
-
-struct AliasAnalysis {
-  int TD;
-
-  virtual int getModRefInfo(CallSite CS);
-};
-
-
-struct Pass {
-  int X;
-  virtual int foo();
-};
-
-struct AliasAnalysisCounter : public Pass, public AliasAnalysis {
-  int getModRefInfo(CallSite CS) {
-    return 0;
-  }
-};
-
-AliasAnalysisCounter AAC;

Removed: llvm/trunk/test/FrontendC++/2003-11-29-DuplicatedCleanupTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-11-29-DuplicatedCleanupTest.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-11-29-DuplicatedCleanupTest.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-11-29-DuplicatedCleanupTest.cpp (removed)
@@ -1,41 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-
-void doesntThrow() throw();
-struct F {
-  ~F() { doesntThrow(); }
-};
-
-void atest() {
-  F A;
-lab:
-  F B;
-  goto lab;
-}
-
-void test(int val) {
-label: {
-   F A;
-   F B;
-   if (val == 0) goto label;
-   if (val == 1) goto label;
-}
-}
-
-void test3(int val) {
-label: {
-   F A;
-   F B;
-   if (val == 0) { doesntThrow(); goto label; }
-   if (val == 1) { doesntThrow(); goto label; }
-}
-}
-
-void test4(int val) {
-label: {
-   F A;
-   F B;
-   if (val == 0) { F C; goto label; }
-   if (val == 1) { F D; goto label; }
-}
-}

Removed: llvm/trunk/test/FrontendC++/2003-12-08-ArrayOfPtrToMemberFunc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2003-12-08-ArrayOfPtrToMemberFunc.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2003-12-08-ArrayOfPtrToMemberFunc.cpp (original)
+++ llvm/trunk/test/FrontendC++/2003-12-08-ArrayOfPtrToMemberFunc.cpp (removed)
@@ -1,12 +0,0 @@
-// RUN: %llvmgxx -S %s -o - | llvm-as -o /dev/null
-
-struct Evil {
- void fun ();
-};
-int foo();
-typedef void (Evil::*memfunptr) ();
-static memfunptr jumpTable[] = { &Evil::fun };
-
-void Evil::fun() {
- (this->*jumpTable[foo()]) ();
-}

Removed: llvm/trunk/test/FrontendC++/2004-01-11-DynamicInitializedConstant.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2004-01-11-DynamicInitializedConstant.cpp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2004-01-11-DynamicInitializedConstant.cpp (original)
+++ llvm/trunk/test/FrontendC++/2004-01-11-DynamicInitializedConstant.cpp (removed)
@@ -1,6 +0,0 @@
-// RUN: %llvmgcc -xc++ -S -o - %s | not grep { constant }
-
-extern int X;
-const int Y = X;
-const int* foo() { return &Y; }
-

Removed: llvm/trunk/test/FrontendC++/dg.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/dg.exp?rev=138164&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/dg.exp (original)
+++ llvm/trunk/test/FrontendC++/dg.exp (removed)
@@ -1,5 +0,0 @@
-load_lib llvm.exp
-
-if [ llvm_gcc_supports c++ ] then {
-  RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
-}



From echristo at apple.com  Fri Aug 19 19:25:42 2011
From: echristo at apple.com (Eric Christopher)
Date: Sat, 20 Aug 2011 00:25:42 -0000
Subject: [llvm-commits] [llvm] r138168 - in /llvm/trunk/test/FrontendObjC++:
 2007-10-03-MetadataPointers.mm 2010-08-02-NonPODObjectValue.mm
 2010-08-04-Template.mm 2010-08-06-X.Y-syntax.mm dg.exp
Message-ID: <20110820002542.4F23E2A6C12D@llvm.org>

Author: echristo
Date: Fri Aug 19 19:25:42 2011
New Revision: 138168

URL: http://llvm.org/viewvc/llvm-project?rev=138168&view=rev
Log:
Remove tests that were either migrated to clang or are obsolete.

Removed:
    llvm/trunk/test/FrontendObjC++/2007-10-03-MetadataPointers.mm
    llvm/trunk/test/FrontendObjC++/2010-08-02-NonPODObjectValue.mm
    llvm/trunk/test/FrontendObjC++/2010-08-04-Template.mm
    llvm/trunk/test/FrontendObjC++/2010-08-06-X.Y-syntax.mm
    llvm/trunk/test/FrontendObjC++/dg.exp

Removed: llvm/trunk/test/FrontendObjC++/2007-10-03-MetadataPointers.mm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC%2B%2B/2007-10-03-MetadataPointers.mm?rev=138167&view=auto
==============================================================================
--- llvm/trunk/test/FrontendObjC++/2007-10-03-MetadataPointers.mm (original)
+++ llvm/trunk/test/FrontendObjC++/2007-10-03-MetadataPointers.mm (removed)
@@ -1,7 +0,0 @@
-// RUN: %llvmgcc -w -x objective-c++ -S %s -o /dev/null
-
- at class NSImage;
-void bork() {
-  NSImage *nsimage;
-  [nsimage release];
-}

Removed: llvm/trunk/test/FrontendObjC++/2010-08-02-NonPODObjectValue.mm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC%2B%2B/2010-08-02-NonPODObjectValue.mm?rev=138167&view=auto
==============================================================================
--- llvm/trunk/test/FrontendObjC++/2010-08-02-NonPODObjectValue.mm (original)
+++ llvm/trunk/test/FrontendObjC++/2010-08-02-NonPODObjectValue.mm (removed)
@@ -1,27 +0,0 @@
-// RUN: not %llvmgcc %s -S -o - |& FileCheck %s
-// This tests for a specific diagnostic in LLVM-GCC.
-// Clang compiles this correctly with no diagnostic,
-// ergo this test will fail with a Clang-based front-end.
-class TFENodeVector  {
-public:
- TFENodeVector(const TFENodeVector& inNodeVector);
- TFENodeVector();
-};
-
- at interface TWindowHistoryEntry  {}
- at property (assign, nonatomic) TFENodeVector targetPath;
- at end
-
- at implementation TWindowHistoryEntry
- at synthesize targetPath;
-- (void) initWithWindowController {
-   TWindowHistoryEntry* entry;
-   TFENodeVector newPath;
-   // CHECK: setting a C++ non-POD object value is not implemented
-#ifdef __clang__
-#error setting a C++ non-POD object value is not implemented
-#endif
-   entry.targetPath = newPath;
-   [entry setTargetPath:newPath];
-}
- at end

Removed: llvm/trunk/test/FrontendObjC++/2010-08-04-Template.mm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC%2B%2B/2010-08-04-Template.mm?rev=138167&view=auto
==============================================================================
--- llvm/trunk/test/FrontendObjC++/2010-08-04-Template.mm (original)
+++ llvm/trunk/test/FrontendObjC++/2010-08-04-Template.mm (removed)
@@ -1,10 +0,0 @@
-// RUN: %llvmgcc %s -S
-struct TRunSoon {
-  template <class P1> static void Post() {}
-};
-
- at implementation TPrivsTableViewMainController
-- (void) applyToEnclosed {
-  TRunSoon::Post<int>();
-}
- at end

Removed: llvm/trunk/test/FrontendObjC++/2010-08-06-X.Y-syntax.mm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC%2B%2B/2010-08-06-X.Y-syntax.mm?rev=138167&view=auto
==============================================================================
--- llvm/trunk/test/FrontendObjC++/2010-08-06-X.Y-syntax.mm (original)
+++ llvm/trunk/test/FrontendObjC++/2010-08-06-X.Y-syntax.mm (removed)
@@ -1,16 +0,0 @@
-// RUN: %l