From baldrick at free.fr Mon Aug 22 01:57:36 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 22 Aug 2011 06:57:36 -0000 Subject: [llvm-commits] [dragonegg] r138229 - /dragonegg/trunk/src/Types.cpp Message-ID: <20110822065736.879092A6C12C@llvm.org> Author: baldrick Date: Mon Aug 22 01:57:36 2011 New Revision: 138229 URL: http://llvm.org/viewvc/llvm-project?rev=138229&view=rev Log: Handle the case in which an array type has an alignment less than the element type. The gcc-4.5 optimizers sometimes produce this; the gcc-4.6 optimizers don't seem to, so it's probably a gcc-4.5 bug. Turn on the check that LLVM types have alignment equal to or less than the alignment of the corresponding GCC type. Modified: dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=138229&r1=138228&r2=138229&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Mon Aug 22 01:57:36 2011 @@ -321,11 +321,20 @@ return GetUnitType(C)->getPointerTo(AddrSpace); } +/// isSized - Return true if the GCC type has a size, perhaps variable. Note +/// that this returns false for function types, for which the GCC type size +/// doesn't represent anything useful for us. +static bool isSized(tree type) { + if (TREE_CODE(type) == FUNCTION_TYPE || TREE_CODE(type) == METHOD_TYPE) + return false; + return TYPE_SIZE(type); +} + /// isSizeCompatible - Return true if the specified gcc type is guaranteed to be /// turned by ConvertType into an LLVM type of the same size (i.e. TYPE_SIZE the /// same as getTypeAllocSizeInBits). bool isSizeCompatible(tree type) { - if (TREE_CODE(type) == FUNCTION_TYPE || TREE_CODE(type) == METHOD_TYPE) + if (!isSized(type)) return false; return isInt64(TYPE_SIZE(type), true); } @@ -335,52 +344,54 @@ // Matching LLVM types with GCC trees //===----------------------------------------------------------------------===// -// llvm_set_type - Associate an LLVM type with each TREE type. -// These are lazily computed by ConvertType. - -static Type *llvm_set_type(tree Tr, Type *Ty) { - assert(TYPE_P(Tr) && "Expected a gcc type!"); - +static Type *CheckTypeConversion(tree type, Type *Ty) { #ifndef NDEBUG bool Mismatch = false; + // If the GCC type has a size, check that the LLVM type does too. Note that + // the LLVM type may have a size when the GCC type does not. For example a + // C variable length array int[] may be converted into [0 x i32]. + if (isSized(type) && !Ty->isSized()) { + Mismatch = true; + errs() << "The GCC type has a size but the LLVM type does not!\n"; + } // Check that the LLVM and GCC types really do have the same size when we say // they do. - if (isSizeCompatible(Tr)) { - if (!Ty->isSized()) { + if (isSizeCompatible(type) && Ty->isSized()) { + uint64_t GCCSize = getInt64(TYPE_SIZE(type), true); + uint64_t LLVMSize = getTargetData().getTypeAllocSizeInBits(Ty); + if (LLVMSize != GCCSize) { Mismatch = true; - errs() << "No size\n"; - } else { - uint64_t GCCSize = getInt64(TYPE_SIZE(Tr), true); - uint64_t LLVMSize = getTargetData().getTypeAllocSizeInBits(Ty); - if (LLVMSize != GCCSize) { - errs() << "GCC size: " << GCCSize << "; LLVM size: " << LLVMSize - << "\n"; - Mismatch = true; - } + errs() << "GCC size: " << GCCSize << "; LLVM size: " << LLVMSize + << "!\n"; } } // Check that the LLVM type has the same alignment or less than the GCC type. -// FIXME: Reduce LLVM array alignment when the GCC array has a small alignment -// (due to an alignment clause?), then turn this back on. -// if (Ty->isSized()) { -// unsigned GCCAlign = TYPE_ALIGN(Tr); -// unsigned LLVMAlign = getTargetData().getABITypeAlignment(Ty) * 8; -// if (LLVMAlign > GCCAlign) { -// errs() << "GCC align: " << GCCAlign << "; LLVM align: " << LLVMAlign -// << "\n"; -// Mismatch = true; -// } -// } + if (Ty->isSized()) { + unsigned GCCAlign = TYPE_ALIGN(type); + unsigned LLVMAlign = getTargetData().getABITypeAlignment(Ty) * 8; + if (LLVMAlign > GCCAlign) { + Mismatch = true; + errs() << "GCC align: " << GCCAlign << "; LLVM align: " << LLVMAlign + << "\n"; + } + } if (Mismatch) { errs() << "GCC: "; - debug_tree(Tr); + debug_tree(type); errs() << "LLVM: "; Ty->print(errs()); DieAbjectly("\nLLVM type doesn't represent GCC type!"); } #endif - setCachedType(Tr, Ty); + return Ty; +} + +// RememberTypeConversion - Associate an LLVM type with a GCC type. +// These are lazily computed by ConvertType. +static Type *RememberTypeConversion(tree type, Type *Ty) { + CheckTypeConversion(type, Ty); + setCachedType(type, Ty); return Ty; } @@ -486,6 +497,10 @@ // Create the array type. Type *Ty = ArrayType::get(ElementTy, NumElements); + // If the array is underaligned, wrap it in a packed struct. + if (TYPE_ALIGN(type) < getTargetData().getABITypeAlignment(Ty) * 8) + Ty = StructType::get(Context, Ty, /*isPacked*/ true); + // If the user increased the alignment of the array element type, then the // size of the array is rounded up by that alignment even though the size // of the array element type is not (!). Correct for this if necessary by @@ -1295,25 +1310,25 @@ DieAbjectly("Unexpected type!", type); case ARRAY_TYPE: - return llvm_set_type(type, ConvertArrayTypeRecursive(type)); + return RememberTypeConversion(type, ConvertArrayTypeRecursive(type)); case FUNCTION_TYPE: case METHOD_TYPE: { CallingConv::ID CallingConv; AttrListPtr PAL; // No declaration to pass through, passing NULL. - return llvm_set_type(type, ConvertFunctionType(type, NULL, NULL, - CallingConv, PAL)); + return RememberTypeConversion(type, ConvertFunctionType(type, NULL, NULL, + CallingConv, PAL)); } case POINTER_TYPE: case REFERENCE_TYPE: - return llvm_set_type(type, ConvertPointerTypeRecursive(type)); + return RememberTypeConversion(type, ConvertPointerTypeRecursive(type)); case RECORD_TYPE: case UNION_TYPE: case QUAL_UNION_TYPE: - return llvm_set_type(type, ConvertRecordTypeRecursive(type)); + return RememberTypeConversion(type, ConvertRecordTypeRecursive(type)); } } @@ -1336,47 +1351,49 @@ // converted and we can safely return the result of the previous conversion. Type *Ty = getCachedType(type); assert(Ty && "Type not already converted!"); - return Ty; + return CheckTypeConversion(type, Ty); } case ENUMERAL_TYPE: // If the enum is incomplete return a placeholder type. if (!TYPE_SIZE(type)) - return Type::getInt32Ty(Context); + return CheckTypeConversion(type, GetUnitType(Context)); // Otherwise fall through. case BOOLEAN_TYPE: case INTEGER_TYPE: { uint64_t Size = getInt64(TYPE_SIZE(type), true); - return IntegerType::get(Context, Size); // Not worth caching. + // Caching the type conversion is not worth it. + return CheckTypeConversion(type, IntegerType::get(Context, Size)); } case COMPLEX_TYPE: { if (Type *Ty = getCachedType(type)) return Ty; Type *Ty = ConvertTypeNonRecursive(TYPE_MAIN_VARIANT(TREE_TYPE(type))); Ty = StructType::get(Ty, Ty, NULL); - return llvm_set_type(type, Ty); + return RememberTypeConversion(type, Ty); } case OFFSET_TYPE: // Handle OFFSET_TYPE specially. This is used for pointers to members, // which are really just integer offsets. Return the appropriate integer // type directly. - return getTargetData().getIntPtrType(Context); // Not worth caching. + // Caching the type conversion is not worth it. + return CheckTypeConversion(type, getTargetData().getIntPtrType(Context)); case REAL_TYPE: - // It is not worth caching the result of this type conversion. + // Caching the type conversion is not worth it. switch (TYPE_PRECISION(type)) { default: DieAbjectly("Unknown FP type!", type); - case 32: return Type::getFloatTy(Context); - case 64: return Type::getDoubleTy(Context); - case 80: return Type::getX86_FP80Ty(Context); + case 32: return CheckTypeConversion(type, Type::getFloatTy(Context)); + case 64: return CheckTypeConversion(type, Type::getDoubleTy(Context)); + case 80: return CheckTypeConversion(type, Type::getX86_FP80Ty(Context)); case 128: #ifdef TARGET_POWERPC - return Type::getPPC_FP128Ty(Context); + return CheckTypeConversion(type, Type::getPPC_FP128Ty(Context)); #else // IEEE quad precision. - return Type::getFP128Ty(Context); + return CheckTypeConversion(type, Type::getFP128Ty(Context)); #endif } @@ -1384,12 +1401,14 @@ case QUAL_UNION_TYPE: case UNION_TYPE: // If the type was already converted then return the already computed type. - if (Type *Ty = getCachedType(type)) return Ty; + if (Type *Ty = getCachedType(type)) + return CheckTypeConversion(type, Ty); // Otherwise this must be an incomplete type - return an opaque struct. assert(!TYPE_SIZE(type) && "Expected an incomplete type!"); - return llvm_set_type(type, StructType::create(Context, - getDescriptiveName(type))); + return RememberTypeConversion(type, + StructType::create(Context, + getDescriptiveName(type))); case VECTOR_TYPE: { if (Type *Ty = getCachedType(type)) return Ty; @@ -1401,11 +1420,12 @@ else Ty = ConvertTypeNonRecursive(TYPE_MAIN_VARIANT(TREE_TYPE(type))); Ty = VectorType::get(Ty, TYPE_VECTOR_SUBPARTS(type)); - return llvm_set_type(type, Ty); + return RememberTypeConversion(type, Ty); } case VOID_TYPE: - return Type::getVoidTy(Context); // Not worth caching. + // Caching the type conversion is not worth it. + return CheckTypeConversion(type, Type::getVoidTy(Context)); } } @@ -1584,7 +1604,7 @@ // SCC as the pointer (since the SCC contains more than one type). Type *PointeeTy = getCachedType(pointee); assert(PointeeTy && "Pointee not converted!"); - llvm_set_type(some_type, PointeeTy->getPointerTo()); + RememberTypeConversion(some_type, PointeeTy->getPointerTo()); } } } From jay.foad at gmail.com Mon Aug 22 04:37:03 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 22 Aug 2011 09:37:03 -0000 Subject: [llvm-commits] [llvm] r138230 - in /llvm/trunk/include/llvm: Constants.h GlobalAlias.h OperandTraits.h Message-ID: <20110822093703.C29192A6C12C@llvm.org> Author: foad Date: Mon Aug 22 04:37:03 2011 New Revision: 138230 URL: http://llvm.org/viewvc/llvm-project?rev=138230&view=rev Log: Remove DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS, folding its functionality into DEFINE_TRANSPARENT_OPERAND_ACCESSORS. A side-effect of this is that the operand accessors for Constants will tolerate NULL operands, fixing PR10663. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/include/llvm/GlobalAlias.h llvm/trunk/include/llvm/OperandTraits.h Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=138230&r1=138229&r2=138230&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Mon Aug 22 04:37:03 2011 @@ -390,7 +390,7 @@ public VariadicOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantArray, Constant) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantArray, Constant) //===----------------------------------------------------------------------===// // ConstantStruct - Constant Struct Declarations @@ -450,7 +450,7 @@ public VariadicOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantStruct, Constant) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantStruct, Constant) //===----------------------------------------------------------------------===// @@ -501,7 +501,7 @@ public VariadicOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantVector, Constant) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantVector, Constant) //===----------------------------------------------------------------------===// /// ConstantPointerNull - a constant pointer value that points to null @@ -575,7 +575,7 @@ public FixedNumOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(BlockAddress, Value) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BlockAddress, Value) //===----------------------------------------------------------------------===// @@ -884,7 +884,7 @@ public VariadicOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantExpr, Constant) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantExpr, Constant) //===----------------------------------------------------------------------===// /// UndefValue - 'undef' values are things that do not have specified contents. Modified: llvm/trunk/include/llvm/GlobalAlias.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalAlias.h?rev=138230&r1=138229&r2=138230&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalAlias.h (original) +++ llvm/trunk/include/llvm/GlobalAlias.h Mon Aug 22 04:37:03 2011 @@ -87,7 +87,7 @@ public FixedNumOperandTraits { }; -DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(GlobalAlias, Constant) +DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalAlias, Constant) } // End llvm namespace Modified: llvm/trunk/include/llvm/OperandTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/OperandTraits.h?rev=138230&r1=138229&r2=138230&view=diff ============================================================================== --- llvm/trunk/include/llvm/OperandTraits.h (original) +++ llvm/trunk/include/llvm/OperandTraits.h Mon Aug 22 04:37:03 2011 @@ -136,45 +136,8 @@ VALUECLASS *CLASS::getOperand(unsigned i_nocapture) const { \ assert(i_nocapture < OperandTraits::operands(this) \ && "getOperand() out of range!"); \ - return static_cast( \ - OperandTraits::op_begin(const_cast(this))[i_nocapture]); \ -} \ -void CLASS::setOperand(unsigned i_nocapture, VALUECLASS *Val_nocapture) { \ - assert(i_nocapture < OperandTraits::operands(this) \ - && "setOperand() out of range!"); \ - OperandTraits::op_begin(this)[i_nocapture] = Val_nocapture; \ -} \ -unsigned CLASS::getNumOperands() const { \ - return OperandTraits::operands(this); \ -} \ -template Use &CLASS::Op() { \ - return this->OpFrom(this); \ -} \ -template const Use &CLASS::Op() const { \ - return this->OpFrom(this); \ -} - - -/// Macro for generating out-of-class operand accessor -/// definitions with casted result -#define DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(CLASS, VALUECLASS) \ -CLASS::op_iterator CLASS::op_begin() { \ - return OperandTraits::op_begin(this); \ -} \ -CLASS::const_op_iterator CLASS::op_begin() const { \ - return OperandTraits::op_begin(const_cast(this)); \ -} \ -CLASS::op_iterator CLASS::op_end() { \ - return OperandTraits::op_end(this); \ -} \ -CLASS::const_op_iterator CLASS::op_end() const { \ - return OperandTraits::op_end(const_cast(this)); \ -} \ -VALUECLASS *CLASS::getOperand(unsigned i_nocapture) const { \ - assert(i_nocapture < OperandTraits::operands(this) \ - && "getOperand() out of range!"); \ - return cast( \ - OperandTraits::op_begin(const_cast(this))[i_nocapture]); \ + return cast_or_null( \ + OperandTraits::op_begin(const_cast(this))[i_nocapture].get()); \ } \ void CLASS::setOperand(unsigned i_nocapture, VALUECLASS *Val_nocapture) { \ assert(i_nocapture < OperandTraits::operands(this) \ From baldrick at free.fr Mon Aug 22 05:32:10 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 22 Aug 2011 10:32:10 -0000 Subject: [llvm-commits] [llvm] r138231 - in /llvm/trunk/test/Linker: 2011-08-22-ResolveAlias.ll 2011-08-22-ResolveAlias2.ll Message-ID: <20110822103210.261A22A6C12C@llvm.org> Author: baldrick Date: Mon Aug 22 05:32:09 2011 New Revision: 138231 URL: http://llvm.org/viewvc/llvm-project?rev=138231&view=rev Log: Testcase for PR10663. Added: llvm/trunk/test/Linker/2011-08-22-ResolveAlias.ll llvm/trunk/test/Linker/2011-08-22-ResolveAlias2.ll Added: llvm/trunk/test/Linker/2011-08-22-ResolveAlias.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-22-ResolveAlias.ll?rev=138231&view=auto ============================================================================== --- llvm/trunk/test/Linker/2011-08-22-ResolveAlias.ll (added) +++ llvm/trunk/test/Linker/2011-08-22-ResolveAlias.ll Mon Aug 22 05:32:09 2011 @@ -0,0 +1,89 @@ +; PR10663 +; RUN: llvm-link %s %p/2011-08-22-ResolveAlias2.ll + +%union.pthread_attr_t = type { [56 x i8] } +%union.pthread_mutex_t = type { [40 x i8] } +%struct.timespec = type { i64, i64 } +%union.pthread_mutexattr_t = type { [4 x i8] } +%union.pthread_cond_t = type { [48 x i8] } + + at _ZL20__gthrw_pthread_oncePiPFvvE = alias weak i32 (i32*, void ()*)* @pthread_once + at _ZL27__gthrw_pthread_getspecificj = alias weak i8* (i32)* @pthread_getspecific + at _ZL27__gthrw_pthread_setspecificjPKv = alias weak i32 (i32, i8*)* @pthread_setspecific + at _ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_ = alias weak i32 (i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*)* @pthread_create + at _ZL20__gthrw_pthread_joinmPPv = alias weak i32 (i64, i8**)* @pthread_join + at _ZL21__gthrw_pthread_equalmm = alias weak i32 (i64, i64)* @pthread_equal + at _ZL20__gthrw_pthread_selfv = alias weak i64 ()* @pthread_self + at _ZL22__gthrw_pthread_detachm = alias weak i32 (i64)* @pthread_detach + at _ZL22__gthrw_pthread_cancelm = alias weak i32 (i64)* @pthread_cancel + at _ZL19__gthrw_sched_yieldv = alias weak i32 ()* @sched_yield + at _ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_lock + at _ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_trylock + at _ZL31__gthrw_pthread_mutex_timedlockP15pthread_mutex_tPK8timespec = alias weak i32 (%union.pthread_mutex_t*, %struct.timespec*)* @pthread_mutex_timedlock + at _ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_unlock + at _ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutex_t*, %union.pthread_mutexattr_t*)* @pthread_mutex_init + at _ZL29__gthrw_pthread_mutex_destroyP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_destroy + at _ZL30__gthrw_pthread_cond_broadcastP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_broadcast + at _ZL27__gthrw_pthread_cond_signalP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_signal + at _ZL25__gthrw_pthread_cond_waitP14pthread_cond_tP15pthread_mutex_t = alias weak i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*)* @pthread_cond_wait + at _ZL30__gthrw_pthread_cond_timedwaitP14pthread_cond_tP15pthread_mutex_tPK8timespec = alias weak i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*)* @pthread_cond_timedwait + at _ZL28__gthrw_pthread_cond_destroyP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_destroy + at _ZL26__gthrw_pthread_key_createPjPFvPvE = alias weak i32 (i32*, void (i8*)*)* @pthread_key_create + at _ZL26__gthrw_pthread_key_deletej = alias weak i32 (i32)* @pthread_key_delete + at _ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_init + at _ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti = alias weak i32 (%union.pthread_mutexattr_t*, i32)* @pthread_mutexattr_settype + at _ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_destroy + +declare extern_weak i32 @pthread_once(i32*, void ()*) + +declare extern_weak i8* @pthread_getspecific(i32) + +declare extern_weak i32 @pthread_setspecific(i32, i8*) + +declare extern_weak i32 @pthread_create(i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*) + +declare extern_weak i32 @pthread_join(i64, i8**) + +declare extern_weak i32 @pthread_equal(i64, i64) + +declare extern_weak i64 @pthread_self() + +declare extern_weak i32 @pthread_detach(i64) + +declare extern_weak i32 @pthread_cancel(i64) + +declare extern_weak i32 @sched_yield() + +declare extern_weak i32 @pthread_mutex_lock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_trylock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_timedlock(%union.pthread_mutex_t*, %struct.timespec*) + +declare extern_weak i32 @pthread_mutex_unlock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_init(%union.pthread_mutex_t*, %union.pthread_mutexattr_t*) + +declare extern_weak i32 @pthread_mutex_destroy(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_cond_broadcast(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_cond_signal(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_cond_wait(%union.pthread_cond_t*, %union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_cond_timedwait(%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*) + +declare extern_weak i32 @pthread_cond_destroy(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_key_create(i32*, void (i8*)*) + +declare extern_weak i32 @pthread_key_delete(i32) + +declare extern_weak i32 @pthread_mutexattr_init(%union.pthread_mutexattr_t*) + +declare extern_weak i32 @pthread_mutexattr_settype(%union.pthread_mutexattr_t*, i32) + +declare extern_weak i32 @pthread_mutexattr_destroy(%union.pthread_mutexattr_t*) + +declare void @_GLOBAL__sub_I__ZN10BitBoard64coEv() nounwind uwtable Added: llvm/trunk/test/Linker/2011-08-22-ResolveAlias2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2011-08-22-ResolveAlias2.ll?rev=138231&view=auto ============================================================================== --- llvm/trunk/test/Linker/2011-08-22-ResolveAlias2.ll (added) +++ llvm/trunk/test/Linker/2011-08-22-ResolveAlias2.ll Mon Aug 22 05:32:09 2011 @@ -0,0 +1,92 @@ +; This file is used by 2011-08-22-ResolveAlias.ll +; RUN: true + +%struct.HexxagonBoard = type { %struct.BitBoard64, %struct.BitBoard64 } +%struct.BitBoard64 = type { i32, i32 } +%union.pthread_attr_t = type { [56 x i8] } +%union.pthread_mutex_t = type { [40 x i8] } +%struct.timespec = type { i64, i64 } +%union.pthread_mutexattr_t = type { [4 x i8] } +%union.pthread_cond_t = type { [48 x i8] } + + at _ZN13HexxagonBoardC1ERKS_ = alias void (%struct.HexxagonBoard*, %struct.HexxagonBoard*)* @_ZN13HexxagonBoardC2ERKS_ + at _ZL20__gthrw_pthread_oncePiPFvvE = alias weak i32 (i32*, void ()*)* @pthread_once + at _ZL27__gthrw_pthread_getspecificj = alias weak i8* (i32)* @pthread_getspecific + at _ZL27__gthrw_pthread_setspecificjPKv = alias weak i32 (i32, i8*)* @pthread_setspecific + at _ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_ = alias weak i32 (i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*)* @pthread_create + at _ZL20__gthrw_pthread_joinmPPv = alias weak i32 (i64, i8**)* @pthread_join + at _ZL21__gthrw_pthread_equalmm = alias weak i32 (i64, i64)* @pthread_equal + at _ZL20__gthrw_pthread_selfv = alias weak i64 ()* @pthread_self + at _ZL22__gthrw_pthread_detachm = alias weak i32 (i64)* @pthread_detach + at _ZL22__gthrw_pthread_cancelm = alias weak i32 (i64)* @pthread_cancel + at _ZL19__gthrw_sched_yieldv = alias weak i32 ()* @sched_yield + at _ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_lock + at _ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_trylock + at _ZL31__gthrw_pthread_mutex_timedlockP15pthread_mutex_tPK8timespec = alias weak i32 (%union.pthread_mutex_t*, %struct.timespec*)* @pthread_mutex_timedlock + at _ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_unlock + at _ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutex_t*, %union.pthread_mutexattr_t*)* @pthread_mutex_init + at _ZL29__gthrw_pthread_mutex_destroyP15pthread_mutex_t = alias weak i32 (%union.pthread_mutex_t*)* @pthread_mutex_destroy + at _ZL30__gthrw_pthread_cond_broadcastP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_broadcast + at _ZL27__gthrw_pthread_cond_signalP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_signal + at _ZL25__gthrw_pthread_cond_waitP14pthread_cond_tP15pthread_mutex_t = alias weak i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*)* @pthread_cond_wait + at _ZL30__gthrw_pthread_cond_timedwaitP14pthread_cond_tP15pthread_mutex_tPK8timespec = alias weak i32 (%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*)* @pthread_cond_timedwait + at _ZL28__gthrw_pthread_cond_destroyP14pthread_cond_t = alias weak i32 (%union.pthread_cond_t*)* @pthread_cond_destroy + at _ZL26__gthrw_pthread_key_createPjPFvPvE = alias weak i32 (i32*, void (i8*)*)* @pthread_key_create + at _ZL26__gthrw_pthread_key_deletej = alias weak i32 (i32)* @pthread_key_delete + at _ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_init + at _ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti = alias weak i32 (%union.pthread_mutexattr_t*, i32)* @pthread_mutexattr_settype + at _ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t = alias weak i32 (%union.pthread_mutexattr_t*)* @pthread_mutexattr_destroy + +declare void @_ZN13HexxagonBoardC2ERKS_(%struct.HexxagonBoard*, %struct.HexxagonBoard*) uwtable align 2 + +declare extern_weak i32 @pthread_once(i32*, void ()*) + +declare extern_weak i8* @pthread_getspecific(i32) + +declare extern_weak i32 @pthread_setspecific(i32, i8*) + +declare extern_weak i32 @pthread_create(i64*, %union.pthread_attr_t*, i8* (i8*)*, i8*) + +declare extern_weak i32 @pthread_join(i64, i8**) + +declare extern_weak i32 @pthread_equal(i64, i64) + +declare extern_weak i64 @pthread_self() + +declare extern_weak i32 @pthread_detach(i64) + +declare extern_weak i32 @pthread_cancel(i64) + +declare extern_weak i32 @sched_yield() + +declare extern_weak i32 @pthread_mutex_lock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_trylock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_timedlock(%union.pthread_mutex_t*, %struct.timespec*) + +declare extern_weak i32 @pthread_mutex_unlock(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_mutex_init(%union.pthread_mutex_t*, %union.pthread_mutexattr_t*) + +declare extern_weak i32 @pthread_mutex_destroy(%union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_cond_broadcast(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_cond_signal(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_cond_wait(%union.pthread_cond_t*, %union.pthread_mutex_t*) + +declare extern_weak i32 @pthread_cond_timedwait(%union.pthread_cond_t*, %union.pthread_mutex_t*, %struct.timespec*) + +declare extern_weak i32 @pthread_cond_destroy(%union.pthread_cond_t*) + +declare extern_weak i32 @pthread_key_create(i32*, void (i8*)*) + +declare extern_weak i32 @pthread_key_delete(i32) + +declare extern_weak i32 @pthread_mutexattr_init(%union.pthread_mutexattr_t*) + +declare extern_weak i32 @pthread_mutexattr_settype(%union.pthread_mutexattr_t*, i32) + +declare extern_weak i32 @pthread_mutexattr_destroy(%union.pthread_mutexattr_t*) From wdietz2 at illinois.edu Mon Aug 22 09:59:14 2011 From: wdietz2 at illinois.edu (Will Dietz) Date: Mon, 22 Aug 2011 14:59:14 -0000 Subject: [llvm-commits] [poolalloc] r138233 - /poolalloc/trunk/test/Makefile Message-ID: <20110822145914.92D7E2A6C12C@llvm.org> Author: wdietz2 Date: Mon Aug 22 09:59:14 2011 New Revision: 138233 URL: http://llvm.org/viewvc/llvm-project?rev=138233&view=rev Log: test/Makefile: Update shared library definitions drop lib- prefix. This naming convention change is because we're building them as loadable modules now. Modified: poolalloc/trunk/test/Makefile Modified: poolalloc/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/Makefile?rev=138233&r1=138232&r2=138233&view=diff ============================================================================== --- poolalloc/trunk/test/Makefile (original) +++ poolalloc/trunk/test/Makefile Mon Aug 22 09:59:14 2011 @@ -409,11 +409,11 @@ # Pathname to poolalloc object tree PADIR := $(PROJ_OBJ_ROOT) # Pathame to the DSA pass dynamic library -DSA_SO := $(PADIR)/$(BuildMode)/lib/libLLVMDataStructure$(SHLIBEXT) +DSA_SO := $(PADIR)/$(BuildMode)/lib/LLVMDataStructure$(SHLIBEXT) # Pathame to the Assist DSA pass dynamic library -ADSA_SO := $(PADIR)/$(BuildMode)/lib/libAssistDS$(SHLIBEXT) +ADSA_SO := $(PADIR)/$(BuildMode)/lib/AssistDS$(SHLIBEXT) # Pathname to the PA pass dynamic library -PA_SO := $(PADIR)/$(BuildMode)/lib/libpoolalloc$(SHLIBEXT) +PA_SO := $(PADIR)/$(BuildMode)/lib/poolalloc$(SHLIBEXT) DSAOPT := $(PROJ_OBJ_ROOT)/test/tools/dsaopt ADSAOPT := $(PROJ_OBJ_ROOT)/test/tools/adsaopt From rdivacky at freebsd.org Mon Aug 22 11:57:23 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 22 Aug 2011 18:57:23 +0200 Subject: [llvm-commits] [PATCH]: dont crash when printing PPC::MFCRpseudo comment Message-ID: <20110822165723.GA38194@freebsd.org> Hi, on PPC the MFCRpseudo instruction has 1 operand but the printer incorrectly tries to print the second operand as a comment, this patch fixes it: Index: PPCAsmPrinter.cpp =================================================================== --- PPCAsmPrinter.cpp (revision 138231) +++ PPCAsmPrinter.cpp (working copy) @@ -369,7 +369,7 @@ // Transform: %R3 = MFCRpseud %CR7 // Into: %R3 = MFCR ;; cr7 OutStreamer.AddComment(PPCInstPrinter:: - getRegisterName(MI->getOperand(1).getReg())); + getRegisterName(MI->getOperand(0).getReg())); TmpInst.setOpcode(PPC::MFCR); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); OutStreamer.EmitInstruction(TmpInst); OK to commit? roman From rdivacky at freebsd.org Mon Aug 22 12:26:27 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 22 Aug 2011 19:26:27 +0200 Subject: [llvm-commits] [PATCH]: dont crash when printing PPC::MFCRpseudo comment In-Reply-To: <20110822165723.GA38194@freebsd.org> References: <20110822165723.GA38194@freebsd.org> Message-ID: <20110822172627.GA41572@freebsd.org> sorry, the patch is completely wrong. I apology for the noise :( On Mon, Aug 22, 2011 at 06:57:23PM +0200, Roman Divacky wrote: > Hi, > > on PPC the MFCRpseudo instruction has 1 operand but the printer incorrectly > tries to print the second operand as a comment, this patch fixes it: > > Index: PPCAsmPrinter.cpp > =================================================================== > --- PPCAsmPrinter.cpp (revision 138231) > +++ PPCAsmPrinter.cpp (working copy) > @@ -369,7 +369,7 @@ > // Transform: %R3 = MFCRpseud %CR7 > // Into: %R3 = MFCR ;; cr7 > OutStreamer.AddComment(PPCInstPrinter:: > - getRegisterName(MI->getOperand(1).getReg())); > + getRegisterName(MI->getOperand(0).getReg())); > TmpInst.setOpcode(PPC::MFCR); > TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); > OutStreamer.EmitInstruction(TmpInst); > > > OK to commit? > > roman > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Aug 22 12:27:03 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Aug 2011 17:27:03 -0000 Subject: [llvm-commits] [llvm] r138241 - /llvm/trunk/test/Transforms/ObjCARC/basic.ll Message-ID: <20110822172703.260BC2A6C12C@llvm.org> Author: djg Date: Mon Aug 22 12:27:02 2011 New Revision: 138241 URL: http://llvm.org/viewvc/llvm-project?rev=138241&view=rev Log: Make a few tests slightly more strict. Modified: llvm/trunk/test/Transforms/ObjCARC/basic.ll Modified: llvm/trunk/test/Transforms/ObjCARC/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/basic.ll?rev=138241&r1=138240&r2=138241&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/basic.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/basic.ll Mon Aug 22 12:27:02 2011 @@ -353,13 +353,14 @@ ; CHECK: define void @test10( ; CHECK: @objc_retain(i8* %x) +; CHECK: @callee ; CHECK: @use_pointer ; CHECK: @objc_release ; CHECK: } define void @test10(i8* %x) nounwind { entry: %0 = call i8* @objc_retain(i8* %x) nounwind - call void @use_pointer(i8* %x) + call void @callee() call void @use_pointer(i8* %x) call void @objc_release(i8* %0) nounwind ret void @@ -768,7 +769,7 @@ define void @test23b(i8* %p) { entry: %0 = call i8* @objc_retainBlock(i8* %p) nounwind - call void @use_pointer(i8* %p) + call void @callee() call void @use_pointer(i8* %p) call void @objc_release(i8* %p) nounwind ret void From gohman at apple.com Mon Aug 22 12:29:11 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Aug 2011 17:29:11 -0000 Subject: [llvm-commits] [llvm] r138242 - in /llvm/trunk: lib/Transforms/Scalar/ObjCARC.cpp test/Transforms/ObjCARC/basic.ll Message-ID: <20110822172911.4D8F82A6C12C@llvm.org> Author: djg Date: Mon Aug 22 12:29:11 2011 New Revision: 138242 URL: http://llvm.org/viewvc/llvm-project?rev=138242&view=rev Log: Constant pointers to objects don't need reference counting. Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp llvm/trunk/test/Transforms/ObjCARC/basic.ll Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=138242&r1=138241&r2=138242&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Mon Aug 22 12:29:11 2011 @@ -515,6 +515,10 @@ const Value *Pointer = StripPointerCastsAndObjCCalls(LI->getPointerOperand()); if (const GlobalVariable *GV = dyn_cast(Pointer)) { + // A constant pointer can't be pointing to an object on the heap. It may + // be reference-counted, but it won't be deleted. + if (GV->isConstant()) + return true; StringRef Name = GV->getName(); // These special variables are known to hold values which are not // reference-counted pointers. @@ -2744,6 +2748,15 @@ // regardless of what possible decrements or uses lie between them. bool KnownSafe = isa(Arg) || isa(Arg); + // A constant pointer can't be pointing to an object on the heap. It may + // be reference-counted, but it won't be deleted. + if (const LoadInst *LI = dyn_cast(Arg)) + if (const GlobalVariable *GV = + dyn_cast( + StripPointerCastsAndObjCCalls(LI->getPointerOperand()))) + if (GV->isConstant()) + KnownSafe = true; + // If a pair happens in a region where it is known that the reference count // is already incremented, we can similarly ignore possible decrements. bool KnownSafeTD = true, KnownSafeBU = true; Modified: llvm/trunk/test/Transforms/ObjCARC/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/basic.ll?rev=138242&r1=138241&r2=138242&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/basic.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/basic.ll Mon Aug 22 12:29:11 2011 @@ -1638,6 +1638,39 @@ ret void } +; Constant pointers to objects don't need reference counting. + + at constptr = external constant i8* + at something = external global i8* + +; CHECK: define void @test60( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test60() { + %t = load i8** @constptr + %s = load i8** @something + call i8* @objc_retain(i8* %s) + call void @callee() + call void @use_pointer(i8* %t) + call void @objc_release(i8* %s) + ret void +} + +; Constant pointers to objects don't need to be considered related to other +; pointers. + +; CHECK: define void @test61( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test61() { + %t = load i8** @constptr + call i8* @objc_retain(i8* %t) + call void @callee() + call void @use_pointer(i8* %t) + call void @objc_release(i8* %t) + ret void +} + declare void @bar(i32 ()*) ; A few real-world testcases. From gohman at apple.com Mon Aug 22 12:29:38 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Aug 2011 17:29:38 -0000 Subject: [llvm-commits] [llvm] r138243 - /llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Message-ID: <20110822172938.0E8582A6C12C@llvm.org> Author: djg Date: Mon Aug 22 12:29:37 2011 New Revision: 138243 URL: http://llvm.org/viewvc/llvm-project?rev=138243&view=rev Log: Add a comment. Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=138243&r1=138242&r2=138243&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Mon Aug 22 12:29:37 2011 @@ -344,6 +344,10 @@ break; default: // For anything else, check all the operands. + // Note that this includes both operands of a Store: while the first + // operand isn't actually being dereferenced, it is being stored to + // memory where we can no longer track who might read it and dereference + // it, so we have to consider it potentially used. for (User::const_op_iterator OI = I->op_begin(), OE = I->op_end(); OI != OE; ++OI) if (IsPotentialUse(*OI)) From grosbach at apple.com Mon Aug 22 12:41:44 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 17:41:44 -0000 Subject: [llvm-commits] [llvm] r138245 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822174144.98C362A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 12:41:44 2011 New Revision: 138245 URL: http://llvm.org/viewvc/llvm-project?rev=138245&view=rev Log: Thumb assembly parsing and encoding for ORR. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138245&r1=138244&r2=138245&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 12:41:44 2011 @@ -355,3 +355,11 @@ nop @ CHECK: nop @ encoding: [0xc0,0x46] + + + at ------------------------------------------------------------------------------ +@ ORR + at ------------------------------------------------------------------------------ + orrs r3, r4 + +@ CHECK-ERRORS: orrs r3, r4 @ encoding: [0x23,0x43] From resistor at mac.com Mon Aug 22 12:56:58 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 17:56:58 -0000 Subject: [llvm-commits] [llvm] r138246 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110822175658.964D32A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 12:56:58 2011 New Revision: 138246 URL: http://llvm.org/viewvc/llvm-project?rev=138246&view=rev Log: Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138246&r1=138245&r2=138246&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 12:56:58 2011 @@ -2322,7 +2322,7 @@ static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateImm(Val << 2)); + Inst.addOperand(MCOperand::CreateImm(Val)); return Success; } Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138246&r1=138245&r2=138246&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Mon Aug 22 12:56:58 2011 @@ -101,3 +101,33 @@ 0x6c 0x40 +#------------------------------------------------------------------------------ +# LDM +#------------------------------------------------------------------------------ +# CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} +# CHECK: ldm r2!, {r1, r3, r4, r5, r7} +# CHECK: ldm r1, {r1} + +0xff 0xcb +0xba 0xca +0x02 0xc9 + + +#------------------------------------------------------------------------------ +# LDR (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldr r1, [r5] +# CHECK: ldr r2, [r6, #32] +# CHECK: ldr r3, [r7, #124] +# CHECK: ldr r1, [sp] +# CHECK: ldr r2, [sp, #24] +# CHECK: ldr r3, [sp, #1020] + + +0x29 0x68 +0x32 0x6a +0xfb 0x6f +0x00 0x99 +0x06 0x9a +0xff 0x9b + From grosbach at apple.com Mon Aug 22 13:04:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 18:04:24 -0000 Subject: [llvm-commits] [llvm] r138249 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb.td ARMInstrThumb2.td Message-ID: <20110822180424.82ABF2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 13:04:24 2011 New Revision: 138249 URL: http://llvm.org/viewvc/llvm-project?rev=138249&view=rev Log: Clean up predicates on ARM target instruction aliases. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138249&r1=138248&r2=138249&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 22 13:04:24 2011 @@ -219,9 +219,20 @@ } //===----------------------------------------------------------------------===// +// ARM Assembler alias templates. +// +class ARMInstAlias + : InstAlias, Requires<[IsARM]>; +class tInstAlias + : InstAlias, Requires<[IsThumb]>; +class t2InstAlias + : InstAlias, Requires<[IsThumb2]>; + +//===----------------------------------------------------------------------===// // ARM Instruction templates. // + class InstTemplate : Instruction { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138249&r1=138248&r2=138249&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 22 13:04:24 2011 @@ -4751,75 +4751,71 @@ // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the // shift amount is zero (i.e., unspecified). def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", - (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; + (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>, + Requires<[IsARM, HasV6]>; def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", - (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>; + (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>, + Requires<[IsARM, HasV6]>; // PUSH/POP aliases for STM/LDM -def : InstAlias<"push${p} $regs", - (STMDB_UPD SP, pred:$p, reglist:$regs)>; -def : InstAlias<"pop${p} $regs", - (LDMIA_UPD SP, pred:$p, reglist:$regs)>; +def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; +def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; // RSB two-operand forms (optional explicit destination operand) -def : InstAlias<"rsb${s}${p} $Rdn, $imm", - (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>, - Requires<[IsARM]>; -def : InstAlias<"rsb${s}${p} $Rdn, $Rm", - (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>, - Requires<[IsARM]>; -def : InstAlias<"rsb${s}${p} $Rdn, $shift", +def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm", + (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm", + (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, - cc_out:$s)>, Requires<[IsARM]>; -def : InstAlias<"rsb${s}${p} $Rdn, $shift", + cc_out:$s)>; +def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, - cc_out:$s)>, Requires<[IsARM]>; + cc_out:$s)>; // RSC two-operand forms (optional explicit destination operand) -def : InstAlias<"rsc${s}${p} $Rdn, $imm", - (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>, - Requires<[IsARM]>; -def : InstAlias<"rsc${s}${p} $Rdn, $Rm", - (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>, - Requires<[IsARM]>; -def : InstAlias<"rsc${s}${p} $Rdn, $shift", +def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm", + (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm", + (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, - cc_out:$s)>, Requires<[IsARM]>; -def : InstAlias<"rsc${s}${p} $Rdn, $shift", + cc_out:$s)>; +def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, - cc_out:$s)>, Requires<[IsARM]>; + cc_out:$s)>; // SSAT/USAT optional shift operand. -def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", +def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; -def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn", +def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; // Extend instruction optional rotate operand. -def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"sxtb${p} $Rd, $Rm", +def : ARMInstAlias<"sxtb${p} $Rd, $Rm", (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"sxtb16${p} $Rd, $Rm", +def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"sxth${p} $Rd, $Rm", +def : ARMInstAlias<"sxth${p} $Rd, $Rm", (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", +def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxtb${p} $Rd, $Rm", +def : ARMInstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxtb16${p} $Rd, $Rm", +def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; -def : InstAlias<"uxth${p} $Rd, $Rm", +def : ARMInstAlias<"uxth${p} $Rd, $Rm", (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138249&r1=138248&r2=138249&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 22 13:04:24 2011 @@ -1017,9 +1017,8 @@ } // Because we have an explicit tMOVSr below, we need an alias to handle // the immediate "movs" form here. Blech. -def : InstAlias <"movs $Rdn, $imm", - (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>, - Requires<[IsThumb]>; +def : tInstAlias <"movs $Rdn, $imm", + (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; // A7-73: MOV(2) - mov setting flag. @@ -1061,9 +1060,8 @@ let AsmMatchConverter = "cvtThumbMultiply"; } -def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, - pred:$p)>, - Requires<[IsThumb]>; +def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, + pred:$p)>; // Move inverse register def tMVN : // A8.6.107 @@ -1115,9 +1113,8 @@ "rsb", "\t$Rd, $Rn, #0", [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; -def : InstAlias<"neg${s}${p} $Rd, $Rm", - (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>, - Requires<[IsThumb]>; +def : tInstAlias<"neg${s}${p} $Rd, $Rm", + (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; // Subtract with carry register let Uses = [CPSR] in Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138249&r1=138248&r2=138249&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 13:04:24 2011 @@ -504,21 +504,18 @@ } // Assembly aliases for optional destination operand when it's the same // as the source operand. - def : InstAlias(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, - cc_out:$s)>, - Requires<[IsThumb2]>; - def : InstAlias; + def : t2InstAlias(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, - cc_out:$s)>, - Requires<[IsThumb2]>; - def : InstAlias; + def : t2InstAlias(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, - cc_out:$s)>, - Requires<[IsThumb2]>; + cc_out:$s)>; } /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need @@ -1557,9 +1554,8 @@ let Inst{15} = 0; } -def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, - pred:$p, cc_out:$s)>, - Requires<[IsThumb2]>; +def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, + pred:$p, cc_out:$s)>; let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, From resistor at mac.com Mon Aug 22 13:05:49 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 18:05:49 -0000 Subject: [llvm-commits] [llvm] r138250 - /llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110822180549.59B332A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 13:05:49 2011 New Revision: 138250 URL: http://llvm.org/viewvc/llvm-project?rev=138250&view=rev Log: Port another swathe of Thumb1 encoding tests over to decoding tests. Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138250&r1=138249&r2=138250&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Mon Aug 22 13:05:49 2011 @@ -131,3 +131,156 @@ 0x06 0x9a 0xff 0x9b +#------------------------------------------------------------------------------ +# LDR (register) +#------------------------------------------------------------------------------ +# CHECK: ldr r1, [r2, r3] + +0xd1 0x58 + + +#------------------------------------------------------------------------------ +# LDRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrb r4, [r3] +# CHECK: ldrb r5, [r6] +# CHECK: ldrb r6, [r7, #31] + +0x1c 0x78 +0x35 0x78 +0xfe 0x7f + + +#------------------------------------------------------------------------------ +# LDRB (register) +#------------------------------------------------------------------------------ +# CHECK: ldrb r6, [r4, r5] + +0x66 0x5d + + +#------------------------------------------------------------------------------ +# LDRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrh r3, [r3] +# CHECK: ldrh r4, [r6, #2] +# CHECK: ldrh r5, [r7, #62] + +0x1b 0x88 +0x74 0x88 +0xfd 0x8f + +#------------------------------------------------------------------------------ +# LDRH (register) +#------------------------------------------------------------------------------ +# CHECK: ldrh r6, [r2, r6] + +0x96 0x5b + + +#------------------------------------------------------------------------------ +# LDRSB/LDRSH +#------------------------------------------------------------------------------ +# CHECK: ldrsb r6, [r2, r6] +# CHECK: ldrsh r3, [r7, r1] + +0x96 0x57 +0x7b 0x5e + +#------------------------------------------------------------------------------ +# LSL (immediate) +#------------------------------------------------------------------------------ +# CHECK: movs r4, r5 +# CHECK: lsls r4, r5, #4 + +0x2c 0x00 +0x2c 0x01 + + +#------------------------------------------------------------------------------ +# LSL (register) +#------------------------------------------------------------------------------ +# CHECK: lsls r2, r6 + +0xb2 0x40 + + +#------------------------------------------------------------------------------ +# LSR (immediate) +#------------------------------------------------------------------------------ +# CHECK: lsrs r1, r3, #1 +# CHECK: lsrs r1, r3, #32 + +0x59 0x08 +0x19 0x08 + + +#------------------------------------------------------------------------------ +# LSR (register) +#------------------------------------------------------------------------------ +# CHECK: lsrs r2, r6 + +0xf2 0x40 + +#------------------------------------------------------------------------------ +# MOV (immediate) +#------------------------------------------------------------------------------ +# CHECK: movs r2, #0 +# CHECK: movs r2, #255 +# CHECK: movs r2, #23 + +0x00 0x22 +0xff 0x22 +0x17 0x22 + + +#------------------------------------------------------------------------------ +# MOV (register) +#------------------------------------------------------------------------------ +# CHECK: mov r3, r4 +# CHECK: movs r1, r3 + +0x23 0x46 +0x19 0x00 + + +#------------------------------------------------------------------------------ +# MUL +#------------------------------------------------------------------------------ +# CHECK: muls r1, r2, r1 +# CHECK: muls r3, r4 + +0x51 0x43 +0x63 0x43 + + +#------------------------------------------------------------------------------ +# MVN +#------------------------------------------------------------------------------ +# CHECK: mvns r6, r3 + +0xde 0x43 + +#------------------------------------------------------------------------------ +# NEG +#------------------------------------------------------------------------------ +# CHECK: rsbs r3, r4, #0 + +0x63 0x42 + + +#------------------------------------------------------------------------------ +# NOP +#------------------------------------------------------------------------------ +# CHECK: nop + +0xc0 0x46 + + +#------------------------------------------------------------------------------ +# ORR +#------------------------------------------------------------------------------ +# CHECK: orrs r3, r4 + +0x23 0x43 + From resistor at mac.com Mon Aug 22 13:22:06 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 18:22:06 -0000 Subject: [llvm-commits] [llvm] r138251 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neon.txt Message-ID: <20110822182207.03B702A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 13:22:06 2011 New Revision: 138251 URL: http://llvm.org/viewvc/llvm-project?rev=138251&view=rev Log: Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/neon.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138251&r1=138250&r2=138251&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 13:22:06 2011 @@ -1992,7 +1992,7 @@ if (regs == 2) { CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); } - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2023,7 +2023,7 @@ CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2052,7 +2052,7 @@ CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2097,7 +2097,7 @@ CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=138251&r1=138250&r2=138251&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 22 13:22:06 2011 @@ -1845,3 +1845,7 @@ # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] 0x4f 0x1b 0xc0 0xf4 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x0 0xc 0xa0 0xf4 +# CHECK: vld1.8 {d0[]}, [r0], r0 + From nicholas at mxc.ca Mon Aug 22 13:26:12 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 22 Aug 2011 18:26:12 -0000 Subject: [llvm-commits] [llvm] r138252 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Message-ID: <20110822182612.D0C3B2A6C12C@llvm.org> Author: nicholas Date: Mon Aug 22 13:26:12 2011 New Revision: 138252 URL: http://llvm.org/viewvc/llvm-project?rev=138252&view=rev Log: Be less redundant. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=138252&r1=138251&r2=138252&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Aug 22 13:26:12 2011 @@ -43,7 +43,6 @@ dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; N->dump(&DAG); dbgs() << "\n"; - dbgs() << "Do not know how to scalarize the result of this operator!\n"; #endif report_fatal_error("Do not know how to scalarize the result of this " "operator!\n"); From resistor at mac.com Mon Aug 22 13:42:13 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 18:42:13 -0000 Subject: [llvm-commits] [llvm] r138255 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neon.txt Message-ID: <20110822184213.CE5992A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 13:42:13 2011 New Revision: 138255 URL: http://llvm.org/viewvc/llvm-project?rev=138255&view=rev Log: Fix another batch of VLD/VST decoding crashes discovered by randomized testing. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/neon.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138255&r1=138254&r2=138255&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 13:42:13 2011 @@ -2769,8 +2769,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2819,8 +2822,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2876,8 +2882,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2931,8 +2940,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2989,8 +3001,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3043,8 +3058,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3103,8 +3121,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3158,8 +3179,11 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=138255&r1=138254&r2=138255&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 22 13:42:13 2011 @@ -1848,4 +1848,6 @@ 0x0 0xc 0xa0 0xf4 # CHECK: vld1.8 {d0[]}, [r0], r0 +0x0d 0x03 0x80 0xf4 +# CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! From isanbard at gmail.com Mon Aug 22 13:44:49 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 22 Aug 2011 18:44:49 -0000 Subject: [llvm-commits] [llvm] r138256 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110822184449.7BA3C2A6C12C@llvm.org> Author: void Date: Mon Aug 22 13:44:49 2011 New Revision: 138256 URL: http://llvm.org/viewvc/llvm-project?rev=138256&view=rev Log: Some whitespace fixes and #include reordering. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=138256&r1=138255&r2=138256&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Aug 22 13:44:49 2011 @@ -21,13 +21,13 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/Pass.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Support/Debug.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" #include using namespace llvm; @@ -37,9 +37,7 @@ namespace { class SjLjEHPass : public FunctionPass { - const TargetLowering *TLI; - Type *FunctionContextTy; Constant *RegisterFn; Constant *UnregisterFn; @@ -53,7 +51,6 @@ Constant *ExceptionFn; Constant *CallSiteFn; Constant *DispatchSetupFn; - Value *CallSite; public: static char ID; // Pass identification, replacement for typeid @@ -62,7 +59,7 @@ bool doInitialization(Module &M); bool runOnFunction(Function &F); - virtual void getAnalysisUsage(AnalysisUsage &AU) const { } + virtual void getAnalysisUsage(AnalysisUsage &AU) const {} const char *getPassName() const { return "SJLJ Exception Handling preparation"; } @@ -190,7 +187,7 @@ SplitCriticalEdge(II, 1, this); assert(!isa(II->getNormalDest()) && !isa(II->getUnwindDest()) && - "critical edge splitting left single entry phi nodes?"); + "Critical edge splitting left single entry phi nodes?"); } Function *F = Invokes.back()->getParent()->getParent(); From grosbach at apple.com Mon Aug 22 13:50:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 18:50:36 -0000 Subject: [llvm-commits] [llvm] r138258 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110822185036.C63672A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 13:50:36 2011 New Revision: 138258 URL: http://llvm.org/viewvc/llvm-project?rev=138258&view=rev Log: Tighten up ARM reglist validation a bit. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138258&r1=138257&r2=138258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 22 13:50:36 2011 @@ -24,6 +24,7 @@ #include "llvm/Target/TargetRegistry.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" @@ -1661,17 +1662,11 @@ Parser.Lex(); // Eat right curly brace token. // Verify the register list. - SmallVectorImpl >::const_iterator - RI = Registers.begin(), RE = Registers.end(); - - unsigned HighRegNum = getARMRegisterNumbering(RI->first); bool EmittedWarning = false; - - DenseMap RegMap; - RegMap[HighRegNum] = true; - - for (++RI; RI != RE; ++RI) { - const std::pair &RegInfo = *RI; + unsigned HighRegNum = 0; + BitVector RegMap(32); + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + const std::pair &RegInfo = Registers[i]; unsigned Reg = getARMRegisterNumbering(RegInfo.first); if (RegMap[Reg]) { @@ -1683,7 +1678,7 @@ Warning(RegInfo.second, "register not in ascending order in register list"); - RegMap[Reg] = true; + RegMap.set(Reg); HighRegNum = std::max(Reg, HighRegNum); } From jediknil at belkadan.com Mon Aug 22 14:01:52 2011 From: jediknil at belkadan.com (Jordy Rose) Date: Mon, 22 Aug 2011 19:01:52 -0000 Subject: [llvm-commits] [llvm] r138260 - in /llvm/trunk/lib/Support: DynamicLibrary.cpp Windows/DynamicLibrary.inc Message-ID: <20110822190152.D63592A6C12C@llvm.org> Author: jrose Date: Mon Aug 22 14:01:52 2011 New Revision: 138260 URL: http://llvm.org/viewvc/llvm-project?rev=138260&view=rev Log: Make DynamicLibrary thread-safe w/r/t call to dlerror() after dlopen(). PR10718 Modified: llvm/trunk/lib/Support/DynamicLibrary.cpp llvm/trunk/lib/Support/Windows/DynamicLibrary.inc Modified: llvm/trunk/lib/Support/DynamicLibrary.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/DynamicLibrary.cpp?rev=138260&r1=138259&r2=138260&view=diff ============================================================================== --- llvm/trunk/lib/Support/DynamicLibrary.cpp (original) +++ llvm/trunk/lib/Support/DynamicLibrary.cpp Mon Aug 22 14:01:52 2011 @@ -72,6 +72,8 @@ DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename, std::string *errMsg) { + SmartScopedLock lock(getMutex()); + void *handle = dlopen(filename, RTLD_LAZY|RTLD_GLOBAL); if (handle == 0) { if (errMsg) *errMsg = dlerror(); @@ -85,7 +87,6 @@ handle = RTLD_DEFAULT; #endif - SmartScopedLock lock(getMutex()); if (OpenedHandles == 0) OpenedHandles = new DenseSet(); Modified: llvm/trunk/lib/Support/Windows/DynamicLibrary.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/DynamicLibrary.inc?rev=138260&r1=138259&r2=138260&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/DynamicLibrary.inc (original) +++ llvm/trunk/lib/Support/Windows/DynamicLibrary.inc Mon Aug 22 14:01:52 2011 @@ -71,9 +71,10 @@ DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *filename, std::string *errMsg) { + SmartScopedLock lock(getMutex()); + if (!filename) { // When no file is specified, enumerate all DLLs and EXEs in the process. - SmartScopedLock lock(getMutex()); if (OpenedHandles == 0) OpenedHandles = new DenseSet(); @@ -90,7 +91,6 @@ return DynamicLibrary(); } - SmartScopedLock lock(getMutex()); if (OpenedHandles == 0) OpenedHandles = new DenseSet(); From resistor at mac.com Mon Aug 22 15:27:12 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 20:27:12 -0000 Subject: [llvm-commits] [llvm] r138269 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neon.txt Message-ID: <20110822202712.E61D72A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 15:27:12 2011 New Revision: 138269 URL: http://llvm.org/viewvc/llvm-project?rev=138269&view=rev Log: Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/neon.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=138269&r1=138268&r2=138269&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Aug 22 15:27:12 2011 @@ -521,6 +521,7 @@ // Some single precision VFP instructions may be executed on both NEON and VFP // pipelines. let D = VFPNeonDomain; + let DecoderMethod = "DecodeVMOVRRS"; } } // neverHasSideEffects @@ -559,6 +560,8 @@ // Some single precision VFP instructions may be executed on both NEON and VFP // pipelines. let D = VFPNeonDomain; + + let DecoderMethod = "DecodeVMOVSRR"; } // FMRDH: SPR -> GPR Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138269&r1=138268&r2=138269&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 15:27:12 2011 @@ -175,6 +175,10 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, @@ -3195,3 +3199,44 @@ return S; } +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + CHECK(S, Unpredictable); + + CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); + CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); + + return S; +} + +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + CHECK(S, Unpredictable); + + CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); + CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); + CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); + + return S; +} Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=138269&r1=138268&r2=138269&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 22 15:27:12 2011 @@ -1851,3 +1851,5 @@ 0x0d 0x03 0x80 0xf4 # CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! +0x3d 0x2a 0x5e 0x6c +# CHECK: vmovvs r2, lr, s29, s30 From bruno.cardoso at gmail.com Mon Aug 22 15:31:04 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 22 Aug 2011 20:31:04 -0000 Subject: [llvm-commits] [llvm] r138271 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-cmp.ll Message-ID: <20110822203104.959B12A6C12D@llvm.org> Author: bruno Date: Mon Aug 22 15:31:04 2011 New Revision: 138271 URL: http://llvm.org/viewvc/llvm-project?rev=138271&view=rev Log: Add support for breaking 256-bit int VETCC into two 128-bit ones, avoding scalarization of the compare. Reduces code from 59 to 6 instructions. Fix PR10712. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/avx-cmp.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138271&r1=138270&r2=138271&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 22 15:31:04 2011 @@ -8119,6 +8119,39 @@ DAG.getConstant(X86CC, MVT::i8), EFLAGS); } +// Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 +// ones, and then concatenate the result back. +static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getValueType(); + + assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC && + "Unsupported value type for operation"); + + int NumElems = VT.getVectorNumElements(); + DebugLoc dl = Op.getDebugLoc(); + SDValue CC = Op.getOperand(2); + SDValue Idx0 = DAG.getConstant(0, MVT::i32); + SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); + + // Extract the LHS vectors + SDValue LHS = Op.getOperand(0); + SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); + SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); + + // Extract the RHS vectors + SDValue RHS = Op.getOperand(1); + SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); + SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); + + // Issue the operation on the smaller types and concatenate the result back + MVT EltVT = VT.getVectorElementType().getSimpleVT(); + EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); + return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, + DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), + DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); +} + + SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue Cond; SDValue Op0 = Op.getOperand(0); @@ -8181,8 +8214,9 @@ return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); } + // Break 256-bit integer vector compare into smaller ones. if (!isFP && VT.getSizeInBits() == 256) - return SDValue(); + return Lower256IntVETCC(Op, DAG); // We are handling one of the integer comparisons here. Since SSE only has // GT and EQ comparisons for integer, swapping operands and multiple Modified: llvm/trunk/test/CodeGen/X86/avx-cmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cmp.ll?rev=138271&r1=138270&r2=138271&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-cmp.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-cmp.ll Mon Aug 22 15:31:04 2011 @@ -42,3 +42,14 @@ ret void } +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpgtd %xmm +; CHECK-NEXT: vpcmpgtd %xmm +; CHECK-NEXT: vinsertf128 $1 +define <8 x i32> @int256-cmp(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %bincmp = icmp slt <8 x i32> %i, %j + %x = sext <8 x i1> %bincmp to <8 x i32> + ret <8 x i32> %x +} + From bruno.cardoso at gmail.com Mon Aug 22 15:31:00 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 22 Aug 2011 20:31:00 -0000 Subject: [llvm-commits] [llvm] r138270 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110822203100.9D5552A6C12C@llvm.org> Author: bruno Date: Mon Aug 22 15:31:00 2011 New Revision: 138270 URL: http://llvm.org/viewvc/llvm-project?rev=138270&view=rev Log: Add 128-bit AVX codegen for PCMP* family of integer instructions Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138270&r1=138269&r2=138270&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 22 15:31:00 2011 @@ -2691,6 +2691,32 @@ 0>, VEX_4V; defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0, 0>, VEX_4V; + + def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)), + (VPCMPEQBrr VR128:$src1, VR128:$src2)>; + def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))), + (VPCMPEQBrm VR128:$src1, addr:$src2)>; + def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)), + (VPCMPEQWrr VR128:$src1, VR128:$src2)>; + def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))), + (VPCMPEQWrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)), + (VPCMPEQDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))), + (VPCMPEQDrm VR128:$src1, addr:$src2)>; + + def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)), + (VPCMPGTBrr VR128:$src1, VR128:$src2)>; + def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))), + (VPCMPGTBrm VR128:$src1, addr:$src2)>; + def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)), + (VPCMPGTWrr VR128:$src1, VR128:$src2)>; + def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))), + (VPCMPGTWrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)), + (VPCMPGTDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))), + (VPCMPGTDrm VR128:$src1, addr:$src2)>; } let Constraints = "$src1 = $dst" in { From resistor at mac.com Mon Aug 22 16:34:00 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 21:34:00 -0000 Subject: [llvm-commits] [llvm] r138273 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/Disassembler/ARM/neon.txt Message-ID: <20110822213401.078F42A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 16:34:00 2011 New Revision: 138273 URL: http://llvm.org/viewvc/llvm-project?rev=138273&view=rev Log: Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/MC/Disassembler/ARM/neon.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=138273&r1=138272&r2=138273&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Aug 22 16:34:00 2011 @@ -387,26 +387,26 @@ // Between half-precision and single-precision. For disassembly only. // FIXME: Verify encoding after integrated assembler is working. -def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a", +def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), + /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; def : ARMPat<(f32_to_f16 SPR:$a), (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; -def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a", +def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), + /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; def : ARMPat<(f16_to_f32 GPR:$a), (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; -def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a", +def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), + /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; -def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a", +def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), + /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=138273&r1=138272&r2=138273&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 22 16:34:00 2011 @@ -1853,3 +1853,6 @@ 0x3d 0x2a 0x5e 0x6c # CHECK: vmovvs r2, lr, s29, s30 + +0xe9 0x1a 0xb2 0x4e +# CHECK: vcvttmi.f32.f16 s2, s19 From eli.friedman at gmail.com Mon Aug 22 16:35:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 22 Aug 2011 21:35:28 -0000 Subject: [llvm-commits] [llvm] r138274 - in /llvm/trunk/docs: Atomics.html LangRef.html Message-ID: <20110822213528.29A982A6C12C@llvm.org> Author: efriedma Date: Mon Aug 22 16:35:27 2011 New Revision: 138274 URL: http://llvm.org/viewvc/llvm-project?rev=138274&view=rev Log: Some minor wording updates and cross-linking for atomic docs. Explicitly note that we don't try to portably define what volatile in LLVM IR means. Modified: llvm/trunk/docs/Atomics.html llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/Atomics.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Atomics.html?rev=138274&r1=138273&r2=138274&view=diff ============================================================================== --- llvm/trunk/docs/Atomics.html (original) +++ llvm/trunk/docs/Atomics.html Mon Aug 22 16:35:27 2011 @@ -121,9 +121,10 @@

However, LLVM is not allowed to transform the former to the latter: it could - introduce undefined behavior if another thread can access x at the same time. - (This example is particularly of interest because before the concurrency model - was implemented, LLVM would perform this transformation.)

+ indirectly introduce undefined behavior if another thread can access x at + the same time. (This example is particularly of interest because before the + concurrency model was implemented, LLVM would perform this + transformation.)

Note that speculative loads are allowed; a load which is part of a race returns undef, but does not have undefined @@ -177,7 +178,7 @@

In order to achieve a balance between performance and necessary guarantees, there are six levels of atomicity. They are listed in order of strength; each level includes all the guarantees of the previous level except for - Acquire/Release.

+ Acquire/Release. (See also LangRef.)

@@ -188,15 +189,15 @@

NotAtomic is the obvious, a load or store which is not atomic. (This isn't really a level of atomicity, but is listed here for comparison.) This is - essentially a regular load or store. If code accesses a memory location - from multiple threads at the same time, the resulting loads return - 'undef'.

+ essentially a regular load or store. If there is a race on a given memory + location, loads from that location return undef.

Relevant standard
This is intended to match shared variables in C/C++, and to be used in any other context where memory access is necessary, and - a race is impossible. + a race is impossible. (The precise definition is in + LangRef.)
Notes for frontends
The rule is essentially that all memory accessed with basic loads and stores by multiple threads should be protected by a lock or other Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=138274&r1=138273&r2=138274&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Aug 22 16:35:27 2011 @@ -1497,6 +1497,9 @@ ways to create them, and we define LLVM IR's behavior in their presence. This model is inspired by the C++0x memory model.

+

For a more informal introduction to this model, see the +LLVM Atomic Instructions and Concurrency Guide. +

We define a happens-before partial order as the least partial order that

    @@ -1533,7 +1536,12 @@

    Given that definition, Rbyte is defined as follows:

      -
    • If there is no write to the same byte that happens before +
    • If R is volatile, the result is target-dependent. (Volatile + is supposed to give guarantees which can support + sig_atomic_t in C/C++, and may be used for accesses to + addresses which do not behave like normal memory. It does not generally + provide cross-thread synchronization.) +
    • Otherwise, if there is no write to the same byte that happens before Rbyte, Rbyte returns undef for that byte.
    • Otherwise, if Rbyte may see exactly one write, @@ -1590,10 +1598,15 @@ that determines which other atomic instructions on the same address they synchronize with. These semantics are borrowed from Java and C++0x, but are somewhat more colloquial. If these descriptions aren't precise enough, -check those specs. fence instructions +check those specs (see spec references in the +atomics guide). +fence instructions treat these orderings somewhat differently since they don't take an address. See that instruction's documentation for details.

      +

      For a simpler introduction to the ordering constraints, see the +LLVM Atomic Instructions and Concurrency Guide.

      +
      unordered
      The set of values that can be read is governed by the happens-before @@ -1618,18 +1631,20 @@ monotonic (or stronger) operations on the same address. If an address is written monotonically by one thread, and other threads monotonically read that address repeatedly, the other threads must -eventually see the write. This is intended to model C++'s relaxed atomic -variables.
      +eventually see the write. This corresponds to the C++0x/C1x +memory_order_relaxed.
acquire
In addition to the guarantees of monotonic, if this operation reads a value written by a release atomic operation, it -synchronizes-with that operation.
+synchronizes-with that operation. This corresponds to the C++0x/C1x +memory_order_acquire.
release
In addition to the guarantees of monotonic, -a synchronizes-with edge may be formed by an acquire -operation.
+a synchronizes-with edge may be formed with an acquire +operation. This is intended to model C++'s memory_order_release.
acq_rel (acquire+release)
Acts as both an -acquire and release operation on its address.
+acquire and release operation on its address. +This corresponds to the C++0x/C1x memory_order_acq_rel.
seq_cst (sequentially consistent)
In addition to the guarantees of acq_rel (acquire for an operation which only reads, release @@ -1637,9 +1652,8 @@ sequentially-consistent operations on all addresses, which is consistent with the happens-before partial order and with the modification orders of all the affected addresses. Each sequentially-consistent read sees the last -preceding write to the same address in this global order. This is intended -to model C++'s sequentially-consistent atomic variables and Java's volatile -shared variables.
+preceding write to the same address in this global order. This corresponds +to the C++0x/C1x memory_order_seq_cst and Java volatile.

If an atomic operation is marked singlethread, From bob.wilson at apple.com Mon Aug 22 16:39:01 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Aug 2011 21:39:01 -0000 Subject: [llvm-commits] [compiler-rt] r138275 - /compiler-rt/trunk/make/platform/clang_darwin.mk Message-ID: <20110822213901.659E22A6C12C@llvm.org> Author: bwilson Date: Mon Aug 22 16:39:01 2011 New Revision: 138275 URL: http://llvm.org/viewvc/llvm-project?rev=138275&view=rev Log: Remove redundant flag: -mthumb is the default for armv7. Modified: compiler-rt/trunk/make/platform/clang_darwin.mk Modified: compiler-rt/trunk/make/platform/clang_darwin.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=138275&r1=138274&r2=138275&view=diff ============================================================================== --- compiler-rt/trunk/make/platform/clang_darwin.mk (original) +++ compiler-rt/trunk/make/platform/clang_darwin.mk Mon Aug 22 16:39:01 2011 @@ -86,7 +86,7 @@ CFLAGS.cc_kext.i386 := $(CFLAGS) $(X86_DEPLOYMENT_ARGS) CFLAGS.cc_kext.x86_64 := $(CFLAGS) $(X86_DEPLOYMENT_ARGS) CFLAGS.cc_kext.armv6 := $(CFLAGS) $(ARM_DEPLOYMENT_ARGS) -mthumb -CFLAGS.cc_kext.armv7 := $(CFLAGS) $(ARM_DEPLOYMENT_ARGS) -mthumb +CFLAGS.cc_kext.armv7 := $(CFLAGS) $(ARM_DEPLOYMENT_ARGS) FUNCTIONS.eprintf := eprintf FUNCTIONS.10.4 := eprintf floatundidf floatundisf floatundixf From bob.wilson at apple.com Mon Aug 22 16:49:47 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Aug 2011 21:49:47 -0000 Subject: [llvm-commits] [compiler-rt] r138277 - /compiler-rt/trunk/lib/assembly.h Message-ID: <20110822214947.F021C2A6C12C@llvm.org> Author: bwilson Date: Mon Aug 22 16:49:47 2011 New Revision: 138277 URL: http://llvm.org/viewvc/llvm-project?rev=138277&view=rev Log: Refactor DEFINE_COMPILERRT_FUNCTION. Modified: compiler-rt/trunk/lib/assembly.h Modified: compiler-rt/trunk/lib/assembly.h URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/assembly.h?rev=138277&r1=138276&r2=138277&view=diff ============================================================================== --- compiler-rt/trunk/lib/assembly.h (original) +++ compiler-rt/trunk/lib/assembly.h Mon Aug 22 16:49:47 2011 @@ -35,15 +35,16 @@ #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name) #ifdef VISIBILITY_HIDDEN -#define DEFINE_COMPILERRT_FUNCTION(name) \ - .globl SYMBOL_NAME(name) SEPARATOR \ - HIDDEN_DIRECTIVE SYMBOL_NAME(name) SEPARATOR \ - SYMBOL_NAME(name): +#define DECLARE_SYMBOL_VISIBILITY(name) \ + HIDDEN_DIRECTIVE SYMBOL_NAME(name) SEPARATOR #else +#define DECLARE_SYMBOL_VISIBILITY(name) +#endif + #define DEFINE_COMPILERRT_FUNCTION(name) \ .globl SYMBOL_NAME(name) SEPARATOR \ + DECLARE_SYMBOL_VISIBILITY(name) \ SYMBOL_NAME(name): -#endif #define DEFINE_COMPILERRT_PRIVATE_FUNCTION(name) \ .globl SYMBOL_NAME(name) SEPARATOR \ From grosbach at apple.com Mon Aug 22 17:00:18 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 22:00:18 -0000 Subject: [llvm-commits] [llvm] r138278 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110822220018.A3E702A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 17:00:18 2011 New Revision: 138278 URL: http://llvm.org/viewvc/llvm-project?rev=138278&view=rev Log: Temporarilly mark tMUL as not commutable. It's not playing nicely in the coalescer with the tied operand. Disable commutability for now while we figure out the deeper fix. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138278&r1=138277&r2=138278&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 22 17:00:18 2011 @@ -1047,7 +1047,7 @@ } // neverHasSideEffects // Multiply register -let isCommutable = 1 in +//let isCommutable = 1 in def tMUL : // A8.6.105 T1 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", From krasin at chromium.org Mon Aug 22 17:55:44 2011 From: krasin at chromium.org (Ivan Krasin) Date: Mon, 22 Aug 2011 15:55:44 -0700 Subject: [llvm-commits] [PATCH]Add nacl support to Triple::ParseOS Message-ID: Hi llvm team, the attached patch is the follow up to r138005. I have forgot to add a case for nacl into Triple::ParseOS. Please, let me know if it's fine to commit. Thanks in advance, Ivan Krasin -------------- next part -------------- A non-text attachment was scrubbed... Name: parse-nacl-os.patch Type: text/x-patch Size: 381 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/c1d2c656/attachment.bin From benny.kra at googlemail.com Mon Aug 22 17:55:32 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 22 Aug 2011 22:55:32 -0000 Subject: [llvm-commits] [llvm] r138285 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <20110822225532.E22A62A6C12C@llvm.org> Author: d0k Date: Mon Aug 22 17:55:32 2011 New Revision: 138285 URL: http://llvm.org/viewvc/llvm-project?rev=138285&view=rev Log: X86: Add some operand types required to identify calls. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=138285&r1=138284&r2=138285&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Aug 22 17:55:32 2011 @@ -405,11 +405,13 @@ def i64i32imm_pcrel : Operand { let PrintMethod = "print_pcrel_imm"; let ParserMatchClass = X86AbsMemAsmOperand; + let OperandType = "OPERAND_PCREL"; } // 64-bits but only 8 bits are significant. def i64i8imm : Operand { let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; } def lea64_32mem : Operand { From grosbach at apple.com Mon Aug 22 18:00:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:00:19 -0000 Subject: [llvm-commits] [llvm] r138286 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822230019.56BC82A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:00:19 2011 New Revision: 138286 URL: http://llvm.org/viewvc/llvm-project?rev=138286&view=rev Log: Thumb assembly parsing and encoding for POP. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138286&r1=138285&r2=138286&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:00:19 2011 @@ -363,3 +363,11 @@ orrs r3, r4 @ CHECK-ERRORS: orrs r3, r4 @ encoding: [0x23,0x43] + + + at ------------------------------------------------------------------------------ +@ POP + at ------------------------------------------------------------------------------ + pop {r2, r3, r6} + +@ CHECK: pop {r2, r3, r6} @ encoding: [0x4c,0xbc] From grosbach at apple.com Mon Aug 22 18:01:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:01:07 -0000 Subject: [llvm-commits] [llvm] r138287 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/thumb-diagnostics.s Message-ID: <20110822230107.C61E52A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:01:07 2011 New Revision: 138287 URL: http://llvm.org/viewvc/llvm-project?rev=138287&view=rev Log: Thumb assemmbly parsing diagnostic improvements for LDM. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138287&r1=138286&r2=138287&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 22 18:01:07 2011 @@ -3084,6 +3084,9 @@ // Thumb LDM instructions are writeback iff the base register is not // in the register list. unsigned Rn = Inst.getOperand(0).getReg(); + bool hasWritebackToken = + (static_cast(Operands[3])->isToken() && + static_cast(Operands[3])->getToken() == "!"); bool doesWriteback = true; for (unsigned i = 3; i < Inst.getNumOperands(); ++i) { unsigned Reg = Inst.getOperand(i).getReg(); @@ -3091,15 +3094,18 @@ doesWriteback = false; // Anything other than a low register isn't legal here. if (!isARMLowRegister(Reg)) - return Error(Operands[4]->getStartLoc(), + return Error(Operands[3 + hasWritebackToken]->getStartLoc(), "registers must be in range r0-r7"); } // If we should have writeback, then there should be a '!' token. - if (doesWriteback && - (!static_cast(Operands[3])->isToken() || - static_cast(Operands[3])->getToken() != "!")) + if (doesWriteback && !hasWritebackToken) return Error(Operands[2]->getStartLoc(), "writeback operator '!' expected"); + // Likewise, if we should not have writeback, there must not be a '!' + if (!doesWriteback && hasWritebackToken) + return Error(Operands[3]->getStartLoc(), + "writeback operator '!' not allowed when base register " + "in register list"); break; } Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138287&r1=138286&r2=138287&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Mon Aug 22 18:01:07 2011 @@ -45,12 +45,16 @@ @ Invalid writeback and register lists for LDM ldm r2!, {r5, r8} ldm r2, {r5, r7} + ldm r2!, {r2, r3, r4} @ CHECK-ERRORS: error: registers must be in range r0-r7 @ CHECK-ERRORS: ldm r2!, {r5, r8} @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: writeback operator '!' expected @ CHECK-ERRORS: ldm r2, {r5, r7} @ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list +@ CHECK-ERRORS: ldm r2!, {r2, r3} +@ CHECK-ERRORS: ^ @ Out of range immediates for LSL instruction. From echristo at apple.com Mon Aug 22 18:05:06 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 22 Aug 2011 16:05:06 -0700 Subject: [llvm-commits] [PATCH]Add nacl support to Triple::ParseOS In-Reply-To: References: Message-ID: <2531D794-3D31-4E06-BB81-C59F065E6563@apple.com> On Aug 22, 2011, at 3:55 PM, Ivan Krasin wrote: > OK. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/3ef68c03/attachment.html From grosbach at apple.com Mon Aug 22 18:04:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:04:27 -0000 Subject: [llvm-commits] [llvm] r138288 - /llvm/trunk/test/MC/ARM/thumb-diagnostics.s Message-ID: <20110822230427.290682A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:04:26 2011 New Revision: 138288 URL: http://llvm.org/viewvc/llvm-project?rev=138288&view=rev Log: Fix think-o. Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138288&r1=138287&r2=138288&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Mon Aug 22 18:04:26 2011 @@ -53,7 +53,7 @@ @ CHECK-ERRORS: ldm r2, {r5, r7} @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list -@ CHECK-ERRORS: ldm r2!, {r2, r3} +@ CHECK-ERRORS: ldm r2!, {r2, r3, r4} @ CHECK-ERRORS: ^ From evan.cheng at apple.com Mon Aug 22 18:04:56 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Aug 2011 23:04:56 -0000 Subject: [llvm-commits] [llvm] r138289 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Message-ID: <20110822230456.598B52A6C12C@llvm.org> Author: evancheng Date: Mon Aug 22 18:04:56 2011 New Revision: 138289 URL: http://llvm.org/viewvc/llvm-project?rev=138289&view=rev Log: Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-) Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=138289&r1=138288&r2=138289&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Aug 22 18:04:56 2011 @@ -74,23 +74,25 @@ assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && "This only knows how to commute register operands so far"); + unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; unsigned Reg1 = MI->getOperand(Idx1).getReg(); unsigned Reg2 = MI->getOperand(Idx2).getReg(); bool Reg1IsKill = MI->getOperand(Idx1).isKill(); bool Reg2IsKill = MI->getOperand(Idx2).isKill(); - bool ChangeReg0 = false; - if (HasDef && MI->getOperand(0).getReg() == Reg1) { - // Must be two address instruction! - assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && - "Expecting a two-address instruction!"); + // If destination is tied to either of the commuted source register, then + // it must be updated. + if (HasDef && Reg0 == Reg1 && + MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { Reg2IsKill = false; - ChangeReg0 = true; + Reg0 = Reg2; + } else if (HasDef && Reg0 == Reg2 && + MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { + Reg1IsKill = false; + Reg0 = Reg1; } if (NewMI) { // Create a new instruction. - unsigned Reg0 = HasDef - ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; MachineFunction &MF = *MI->getParent()->getParent(); if (HasDef) @@ -104,8 +106,8 @@ .addReg(Reg1, getKillRegState(Reg2IsKill)); } - if (ChangeReg0) - MI->getOperand(0).setReg(Reg2); + if (HasDef) + MI->getOperand(0).setReg(Reg0); MI->getOperand(Idx2).setReg(Reg1); MI->getOperand(Idx1).setReg(Reg2); MI->getOperand(Idx2).setIsKill(Reg1IsKill); From grosbach at apple.com Mon Aug 22 18:05:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:05:11 -0000 Subject: [llvm-commits] [llvm] r138290 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822230511.6C2412A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:05:11 2011 New Revision: 138290 URL: http://llvm.org/viewvc/llvm-project?rev=138290&view=rev Log: Thumb parsing and encoding for PUSH. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138290&r1=138289&r2=138290&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:05:11 2011 @@ -371,3 +371,11 @@ pop {r2, r3, r6} @ CHECK: pop {r2, r3, r6} @ encoding: [0x4c,0xbc] + + + at ------------------------------------------------------------------------------ +@ PUSH + at ------------------------------------------------------------------------------ + push {r1, r2, r7} + +@ CHECK: push {r1, r2, r7} @ encoding: [0x86,0xb4] From krasin at chromium.org Mon Aug 22 18:08:53 2011 From: krasin at chromium.org (Ivan Krasin) Date: Mon, 22 Aug 2011 23:08:53 -0000 Subject: [llvm-commits] [llvm] r138291 - /llvm/trunk/lib/Support/Triple.cpp Message-ID: <20110822230853.6FD0D2A6C12C@llvm.org> Author: krasin Date: Mon Aug 22 18:08:53 2011 New Revision: 138291 URL: http://llvm.org/viewvc/llvm-project?rev=138291&view=rev Log: Add NativeClient support to Triple::ParseOS. Modified: llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=138291&r1=138290&r2=138291&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Mon Aug 22 18:08:53 2011 @@ -356,6 +356,8 @@ return Minix; else if (OSName.startswith("rtems")) return RTEMS; + else if (OSName.startswith("nacl")) + return NativeClient; else return UnknownOS; } From krasin at google.com Mon Aug 22 18:10:18 2011 From: krasin at google.com (Ivan Krasin) Date: Mon, 22 Aug 2011 16:10:18 -0700 Subject: [llvm-commits] [PATCH]Add nacl support to Triple::ParseOS In-Reply-To: <2531D794-3D31-4E06-BB81-C59F065E6563@apple.com> References: <2531D794-3D31-4E06-BB81-C59F065E6563@apple.com> Message-ID: Thanks, Eric. Committed as r138291. On Mon, Aug 22, 2011 at 4:05 PM, Eric Christopher wrote: > > On Aug 22, 2011, at 3:55 PM, Ivan Krasin wrote: > > > > OK. > -eric From resistor at mac.com Mon Aug 22 18:10:16 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:10:16 -0000 Subject: [llvm-commits] [llvm] r138292 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110822231017.0A62C2A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 18:10:16 2011 New Revision: 138292 URL: http://llvm.org/viewvc/llvm-project?rev=138292&view=rev Log: Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138292&r1=138291&r2=138292&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 18:10:16 2011 @@ -29,6 +29,7 @@ let EncoderMethod = "getT2SORegOpValue"; let PrintMethod = "printT2SOOperand"; let MIOperandInfo = (ops rGPR, i32imm); + let DecoderMethod = "DecodeSORegImmOperand"; } // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138292&r1=138291&r2=138292&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 22 18:10:16 2011 @@ -274,3 +274,6 @@ # CHECK: ldrsh r1, [r0, r0] 0x01 0x5E + +# CHECK: and.w r5, r1, r10, ror #7 +0x1 0xea 0xfa 0x95 From grosbach at apple.com Mon Aug 22 18:13:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:13:54 -0000 Subject: [llvm-commits] [llvm] r138293 - /llvm/trunk/test/MC/ARM/reg-list.s Message-ID: <20110822231354.5F50B2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:13:54 2011 New Revision: 138293 URL: http://llvm.org/viewvc/llvm-project?rev=138293&view=rev Log: Tidy up. Trailing whitespace. Modified: llvm/trunk/test/MC/ARM/reg-list.s Modified: llvm/trunk/test/MC/ARM/reg-list.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/reg-list.s?rev=138293&r1=138292&r2=138293&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/reg-list.s (original) +++ llvm/trunk/test/MC/ARM/reg-list.s Mon Aug 22 18:13:54 2011 @@ -1,6 +1,6 @@ @ RUN: llvm-mc -triple thumb-apple-darwin10 -show-encoding < %s 2> %t | FileCheck %s @ RUN: FileCheck --check-prefix=CHECK-WARNINGS < %t %s - + push {r7, lr} @ CHECK-WARNINGS: register not in ascending order in register list From resistor at mac.com Mon Aug 22 18:16:48 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:16:48 -0000 Subject: [llvm-commits] [llvm] r138294 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110822231648.CD9ED2A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 18:16:48 2011 New Revision: 138294 URL: http://llvm.org/viewvc/llvm-project?rev=138294&view=rev Log: Match operand names to provide correct decoding for Thumb2 SMULL. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138294&r1=138293&r2=138294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 18:16:48 2011 @@ -2153,9 +2153,9 @@ let neverHasSideEffects = 1 in { let isCommutable = 1 in { def t2SMULL : T2MulLong<0b000, 0b0000, - (outs rGPR:$Rd, rGPR:$Ra), + (outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, - "smull", "\t$Rd, $Ra, $Rn, $Rm", []>; + "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; def t2UMULL : T2MulLong<0b010, 0b0000, (outs rGPR:$RdLo, rGPR:$RdHi), From grosbach at apple.com Mon Aug 22 18:17:34 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:17:34 -0000 Subject: [llvm-commits] [llvm] r138295 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/thumb-diagnostics.s Message-ID: <20110822231734.98B5B2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:17:34 2011 New Revision: 138295 URL: http://llvm.org/viewvc/llvm-project?rev=138295&view=rev Log: Improve error checking for tPUSH and tPOP register lists. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138295&r1=138294&r2=138295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 22 18:17:34 2011 @@ -3109,6 +3109,26 @@ break; } + case ARM::tPOP: { + for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { + unsigned Reg = Inst.getOperand(i).getReg(); + // Anything other than a low register isn't legal here. + if (!isARMLowRegister(Reg) && Reg != ARM::PC) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or pc"); + } + break; + } + case ARM::tPUSH: { + for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { + unsigned Reg = Inst.getOperand(i).getReg(); + // Anything other than a low register isn't legal here. + if (!isARMLowRegister(Reg) && Reg != ARM::LR) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or lr"); + } + break; + } } return false; Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138295&r1=138294&r2=138295&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Mon Aug 22 18:17:34 2011 @@ -57,6 +57,18 @@ @ CHECK-ERRORS: ^ +@ Invalid writeback and register lists for PUSH/POP + pop {r1, r2, r10} + push {r8, r9} +@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc +@ CHECK-ERRORS: pop {r1, r2, r10} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr +@ CHECK-ERRORS: push {r8, r9} +@ CHECK-ERRORS: ^ + + + @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 lsls r4, r5, #32 From geek4civic at gmail.com Mon Aug 22 18:22:05 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 22 Aug 2011 23:22:05 -0000 Subject: [llvm-commits] [llvm] r138297 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20110822232205.B9D482A6C12C@llvm.org> Author: chapuni Date: Mon Aug 22 18:22:05 2011 New Revision: 138297 URL: http://llvm.org/viewvc/llvm-project?rev=138297&view=rev Log: docs/ReleaseNotes.html: Mention that Windows 2000 will not be supported any more. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=138297&r1=138296&r2=138297&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Aug 22 18:22:05 2011 @@ -589,6 +589,14 @@ is still accepted, but is now considered deprecated. +

Windows (32-bit)

+
+
    +
  • On Win32(MinGW32 and MSVC), Windows 2000 will not be supported. + Windows XP or higher is required.
    • +
+
+ From resistor at mac.com Mon Aug 22 18:22:06 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:22:06 -0000 Subject: [llvm-commits] [llvm] r138298 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110822232206.3425F2A6C12D@llvm.org> Author: resistor Date: Mon Aug 22 18:22:05 2011 New Revision: 138298 URL: http://llvm.org/viewvc/llvm-project?rev=138298&view=rev Log: Match operand naming to allow correct decoding of t2LDRSH_POST. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138298&r1=138297&r2=138298&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 18:22:05 2011 @@ -1238,10 +1238,10 @@ AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn", []>; -def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn), +def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn), (ins GPR:$base, t2am_imm8_offset:$addr), AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, - "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn", + "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn", []>; } // mayLoad = 1, neverHasSideEffects = 1 Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138298&r1=138297&r2=138298&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 22 18:22:05 2011 @@ -277,3 +277,6 @@ # CHECK: and.w r5, r1, r10, ror #7 0x1 0xea 0xfa 0x95 + +# CHECK: ldrsh r6, [sp], #81 +0x3d 0xf9 0x51 0x6b From grosbach at apple.com Mon Aug 22 18:25:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 16:25:04 -0700 Subject: [llvm-commits] [llvm] r138289 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp In-Reply-To: <20110822230456.598B52A6C12C@llvm.org> References: <20110822230456.598B52A6C12C@llvm.org> Message-ID: <3930F884-0000-4570-9945-38C0DA87927F@apple.com> Hey Evan, Thanks for the fix. I'm open to suggestions on how to create a non-fragile test case for something like this. I can reduce the code that failed because of it easily enough, but that'll be pretty fragile such that changes in either isel or the register allocator would likely perturb it. The failure was detected by the nightly test suite. While not optimal, perhaps that's sufficient? -Jim On Aug 22, 2011, at 4:04 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Aug 22 18:04:56 2011 > New Revision: 138289 > > URL: http://llvm.org/viewvc/llvm-project?rev=138289&view=rev > Log: > Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-) > > Modified: > llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp > > Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=138289&r1=138288&r2=138289&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) > +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Aug 22 18:04:56 2011 > @@ -74,23 +74,25 @@ > > assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && > "This only knows how to commute register operands so far"); > + unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; > unsigned Reg1 = MI->getOperand(Idx1).getReg(); > unsigned Reg2 = MI->getOperand(Idx2).getReg(); > bool Reg1IsKill = MI->getOperand(Idx1).isKill(); > bool Reg2IsKill = MI->getOperand(Idx2).isKill(); > - bool ChangeReg0 = false; > - if (HasDef && MI->getOperand(0).getReg() == Reg1) { > - // Must be two address instruction! > - assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && > - "Expecting a two-address instruction!"); > + // If destination is tied to either of the commuted source register, then > + // it must be updated. > + if (HasDef && Reg0 == Reg1 && > + MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { > Reg2IsKill = false; > - ChangeReg0 = true; > + Reg0 = Reg2; > + } else if (HasDef && Reg0 == Reg2 && > + MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { > + Reg1IsKill = false; > + Reg0 = Reg1; > } > > if (NewMI) { > // Create a new instruction. > - unsigned Reg0 = HasDef > - ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; > bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; > MachineFunction &MF = *MI->getParent()->getParent(); > if (HasDef) > @@ -104,8 +106,8 @@ > .addReg(Reg1, getKillRegState(Reg2IsKill)); > } > > - if (ChangeReg0) > - MI->getOperand(0).setReg(Reg2); > + if (HasDef) > + MI->getOperand(0).setReg(Reg0); > MI->getOperand(Idx2).setReg(Reg1); > MI->getOperand(Idx1).setReg(Reg2); > MI->getOperand(Idx2).setIsKill(Reg1IsKill); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Mon Aug 22 18:25:49 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:25:49 -0000 Subject: [llvm-commits] [llvm] r138299 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110822232549.1C2BA2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:25:48 2011 New Revision: 138299 URL: http://llvm.org/viewvc/llvm-project?rev=138299&view=rev Log: Revert r138278 now that r138289 has fixed the root issue. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138299&r1=138298&r2=138299&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 22 18:25:48 2011 @@ -1047,7 +1047,7 @@ } // neverHasSideEffects // Multiply register -//let isCommutable = 1 in +let isCommutable = 1 in def tMUL : // A8.6.105 T1 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", From resistor at mac.com Mon Aug 22 18:27:47 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:27:47 -0000 Subject: [llvm-commits] [llvm] r138300 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110822232747.7B9AD2A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 18:27:47 2011 New Revision: 138300 URL: http://llvm.org/viewvc/llvm-project?rev=138300&view=rev Log: Correct operand naming of t2USAT16 to allow proper decoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138300&r1=138299&r2=138300&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 18:27:47 2011 @@ -1902,9 +1902,9 @@ let Inst{15} = 0; } -def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), +def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary, - "usat16", "\t$dst, $sat_imm, $Rn", + "usat16", "\t$Rd, $sat_imm, $Rn", [/* For disassembly only; pattern left blank */]>, Requires<[IsThumb2, HasThumb2DSP]> { let Inst{31-27} = 0b11110; Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138300&r1=138299&r2=138300&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 22 18:27:47 2011 @@ -280,3 +280,6 @@ # CHECK: ldrsh r6, [sp], #81 0x3d 0xf9 0x51 0x6b + +# CHECK: usat16 r4, #10, r1 +0xa1 0xf3 0x2a 0x4 From resistor at mac.com Mon Aug 22 18:31:45 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:31:45 -0000 Subject: [llvm-commits] [llvm] r138301 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110822233145.A27D22A6C12C@llvm.org> Author: resistor Date: Mon Aug 22 18:31:45 2011 New Revision: 138301 URL: http://llvm.org/viewvc/llvm-project?rev=138301&view=rev Log: t2SMLAD is a four-register instruction, not a three-register one. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138301&r1=138300&r2=138301&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 22 18:31:45 2011 @@ -2457,7 +2457,7 @@ Requires<[IsThumb2, HasThumb2DSP]> { let Inst{15-12} = 0b1111; } -def t2SMLAD : T2ThreeReg_mac< +def t2SMLAD : T2FourReg_mac< 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", "\t$Rd, $Rn, $Rm, $Ra", []>, Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138301&r1=138300&r2=138301&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Mon Aug 22 18:31:45 2011 @@ -283,3 +283,6 @@ # CHECK: usat16 r4, #10, r1 0xa1 0xf3 0x2a 0x4 + +# CHECK: smlad r5, r12, r8, r11 +0x2c 0xfb 0x8 0xb5 From isanbard at gmail.com Mon Aug 22 18:38:40 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 22 Aug 2011 23:38:40 -0000 Subject: [llvm-commits] [llvm] r138302 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110822233840.4F5562A6C12D@llvm.org> Author: void Date: Mon Aug 22 18:38:40 2011 New Revision: 138302 URL: http://llvm.org/viewvc/llvm-project?rev=138302&view=rev Log: Split the landing pad's edge. Then for all uses of a landingpad instruction's value, we insert a load of the exception object and selector object from memory, which is where it actually resides. If it's used by a PHI node, we follow that to where it is being used. Eventually, all landingpad instructions should have no uses. Any PHI nodes that were associated with those landingpads should be removed. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=138302&r1=138301&r2=138302&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Aug 22 18:38:40 2011 @@ -26,6 +26,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Support/Debug.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include @@ -52,6 +53,7 @@ Constant *CallSiteFn; Constant *DispatchSetupFn; Value *CallSite; + DenseMap LPadSuccMap; public: static char ID; // Pass identification, replacement for typeid explicit SjLjEHPass(const TargetLowering *tli = NULL) @@ -158,7 +160,12 @@ CallInst::Create(CallSiteFn, CallSiteNoC, "", II); // Add a switch case to our unwind block. - CatchSwitch->addCase(SwitchValC, II->getUnwindDest()); + if (BasicBlock *SuccBB = LPadSuccMap[II]) { + CatchSwitch->addCase(SwitchValC, SuccBB); + } else { + CatchSwitch->addCase(SwitchValC, II->getUnwindDest()); + } + // We still want this to look like an invoke so we emit the LSDA properly, // so we don't transform the invoke into a call here. } @@ -184,7 +191,17 @@ for (unsigned i = 0, e = Invokes.size(); i != e; ++i) { InvokeInst *II = Invokes[i]; SplitCriticalEdge(II, 0, this); - SplitCriticalEdge(II, 1, this); + + // FIXME: New EH - This if-condition will be always true in the new scheme. + if (II->getUnwindDest()->isLandingPad()) { + SmallVector NewBBs; + SplitLandingPadPredecessors(II->getUnwindDest(), II->getParent(), + ".1", ".2", this, NewBBs); + LPadSuccMap[II] = *succ_begin(NewBBs[0]); + } else { + SplitCriticalEdge(II, 1, this); + } + assert(!isa(II->getNormalDest()) && !isa(II->getUnwindDest()) && "Critical edge splitting left single entry phi nodes?"); @@ -296,6 +313,44 @@ } } +/// CreateLandingPadLoad - Load the exception handling values and insert them +/// into a structure. +static Instruction *CreateLandingPadLoad(Function &F, Value *ExnAddr, + Value *SelAddr, + BasicBlock::iterator InsertPt) { + Value *Exn = new LoadInst(ExnAddr, "exn", false, + InsertPt); + Type *Ty = Type::getInt8PtrTy(F.getContext()); + Exn = CastInst::Create(Instruction::IntToPtr, Exn, Ty, "", InsertPt); + Value *Sel = new LoadInst(SelAddr, "sel", false, InsertPt); + + Ty = StructType::get(Exn->getType(), Sel->getType(), NULL); + InsertValueInst *LPadVal = InsertValueInst::Create(llvm::UndefValue::get(Ty), + Exn, 0, + "lpad.val", InsertPt); + return InsertValueInst::Create(LPadVal, Sel, 1, "lpad.val", InsertPt); +} + +/// ReplaceLandingPadVal - Replace the landingpad instruction's value with a +/// load from the stored values (via CreateLandingPadLoad). This looks through +/// PHI nodes, and removes them if they are dead. +static void ReplaceLandingPadVal(Function &F, Instruction *Inst, Value *ExnAddr, + Value *SelAddr) { + if (Inst->use_empty()) return; + + while (!Inst->use_empty()) { + Instruction *I = cast(Inst->use_back()); + + if (PHINode *PN = dyn_cast(I)) { + ReplaceLandingPadVal(F, PN, ExnAddr, SelAddr); + if (PN->use_empty()) PN->eraseFromParent(); + continue; + } + + Inst->replaceAllUsesWith(CreateLandingPadLoad(F, ExnAddr, SelAddr, I)); + } +} + bool SjLjEHPass::insertSjLjEHSupport(Function &F) { SmallVector Returns; SmallVector Unwinds; @@ -350,6 +405,10 @@ } } else if (AllocaInst *AI = dyn_cast(I)) { JmpbufUpdatePoints.push_back(AI); + } else if (InvokeInst *II = dyn_cast(I)) { + // FIXME: This will be always non-NULL in the new EH. + if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst()) + if (!PersonalityFn) PersonalityFn = LPI->getPersonalityFn(); } } } @@ -368,6 +427,16 @@ // invoke's. splitLiveRangesAcrossInvokes(Invokes); + + SmallVector LandingPads; + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) { + if (InvokeInst *II = dyn_cast(BB->getTerminator())) + // FIXME: This will be always non-NULL in the new EH. + if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst()) + LandingPads.push_back(LPI); + } + + BasicBlock *EntryBB = F.begin(); // Create an alloca for the incoming jump buffer ptr and the new jump buffer // that needs to be restored on all exits from the function. This is an @@ -425,6 +494,9 @@ I->eraseFromParent(); } + for (unsigned i = 0, e = LandingPads.size(); i != e; ++i) + ReplaceLandingPadVal(F, LandingPads[i], ExceptionAddr, SelectorAddr); + // The entry block changes to have the eh.sjlj.setjmp, with a conditional // branch to a dispatch block for non-zero returns. If we return normally, // we're not handling an exception and just register the function context and From grosbach at apple.com Mon Aug 22 18:39:25 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:39:25 -0000 Subject: [llvm-commits] [llvm] r138303 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822233925.D85EE2A6C12D@llvm.org> Author: grosbach Date: Mon Aug 22 18:39:25 2011 New Revision: 138303 URL: http://llvm.org/viewvc/llvm-project?rev=138303&view=rev Log: Thumb parsing and encoding for REV/REV16/REVSH. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138303&r1=138302&r2=138303&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:39:25 2011 @@ -379,3 +379,15 @@ push {r1, r2, r7} @ CHECK: push {r1, r2, r7} @ encoding: [0x86,0xb4] + + + at ------------------------------------------------------------------------------ +@ REV/REV16/REVSH + at ------------------------------------------------------------------------------ + rev r6, r3 + rev16 r7, r2 + revsh r5, r1 + +@ CHECK: rev r6, r3 @ encoding: [0x1e,0xba] +@ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba] +@ CHECK: revsh r5, r1 @ encoding: [0xcd,0xba] From grosbach at apple.com Mon Aug 22 18:40:51 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:40:51 -0000 Subject: [llvm-commits] [llvm] r138304 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822234051.BB0572A6C12D@llvm.org> Author: grosbach Date: Mon Aug 22 18:40:51 2011 New Revision: 138304 URL: http://llvm.org/viewvc/llvm-project?rev=138304&view=rev Log: Thumb parsing and encoding for ROR. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138304&r1=138303&r2=138304&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:40:51 2011 @@ -391,3 +391,11 @@ @ CHECK: rev r6, r3 @ encoding: [0x1e,0xba] @ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba] @ CHECK: revsh r5, r1 @ encoding: [0xcd,0xba] + + + at ------------------------------------------------------------------------------ +@ ROR + at ------------------------------------------------------------------------------ + rors r2, r7 + +@ CHECK: rors r2, r7 @ encoding: [0xfa,0x41] From benny.kra at googlemail.com Mon Aug 22 18:41:41 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 22 Aug 2011 23:41:41 -0000 Subject: [llvm-commits] [llvm] r138305 - /llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Message-ID: <20110822234141.698EF2A6C12D@llvm.org> Author: d0k Date: Mon Aug 22 18:41:41 2011 New Revision: 138305 URL: http://llvm.org/viewvc/llvm-project?rev=138305&view=rev Log: Add an MCInstrAnalysis version of isCall. Modified: llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Modified: llvm/trunk/include/llvm/MC/MCInstrAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrAnalysis.h?rev=138305&r1=138304&r2=138305&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrAnalysis.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Mon Aug 22 18:41:41 2011 @@ -43,6 +43,10 @@ return Info->get(Inst.getOpcode()).isIndirectBranch(); } + virtual bool isCall(const MCInst &Inst) const { + return Info->get(Inst.getOpcode()).isCall(); + } + virtual bool isReturn(const MCInst &Inst) const { return Info->get(Inst.getOpcode()).isReturn(); } From resistor at mac.com Mon Aug 22 18:44:04 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Aug 2011 23:44:04 -0000 Subject: [llvm-commits] [llvm] r138306 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td Disassembler/ARMDisassembler.cpp Message-ID: <20110822234404.7E3F82A6C12D@llvm.org> Author: resistor Date: Mon Aug 22 18:44:04 2011 New Revision: 138306 URL: http://llvm.org/viewvc/llvm-project?rev=138306&view=rev Log: Reject invalid imod values in t2CPS instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138306&r1=138305&r2=138306&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 22 18:44:04 2011 @@ -134,6 +134,7 @@ // ARM imod and iflag operands, used only by the CPS instruction. def imod_op : Operand { let PrintMethod = "printCPSIMod"; + let DecoderMethod = "DecodeCPSIMod"; } def ProcIFlagsOperand : AsmOperandClass { Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138306&r1=138305&r2=138306&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 18:44:04 2011 @@ -179,7 +179,8 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); - +static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); @@ -3240,3 +3241,11 @@ return S; } + +static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + if (Val == 0x1) return Fail; + Inst.addOperand(MCOperand::CreateImm(Val)); + return Success; +} + From grosbach at apple.com Mon Aug 22 18:47:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:47:13 -0000 Subject: [llvm-commits] [llvm] r138308 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822234713.AB7C12A6C12D@llvm.org> Author: grosbach Date: Mon Aug 22 18:47:13 2011 New Revision: 138308 URL: http://llvm.org/viewvc/llvm-project?rev=138308&view=rev Log: Thumb parsing and encoding for RSB. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138308&r1=138307&r2=138308&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 22 18:47:13 2011 @@ -3029,6 +3029,19 @@ delete Op; } } + // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the + // end. Convert it to a token here. + if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && + static_cast(Operands[5])->isImm()) { + ARMOperand *Op = static_cast(Operands[5]); + const MCConstantExpr *CE = dyn_cast(Op->getImm()); + if (CE && CE->getValue() == 0) { + Operands.erase(Operands.begin() + 5); + Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); + delete Op; + } + } + return false; } Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138308&r1=138307&r2=138308&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:47:13 2011 @@ -399,3 +399,11 @@ rors r2, r7 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41] + + + at ------------------------------------------------------------------------------ +@ RSB + at ------------------------------------------------------------------------------ + rsbs r1, r3, #0 + + rsbs r1, r3, #0 @ encoding: [0x59,0x42] From grosbach at apple.com Mon Aug 22 18:55:59 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:55:59 -0000 Subject: [llvm-commits] [llvm] r138311 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822235559.1B3ED2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:55:58 2011 New Revision: 138311 URL: http://llvm.org/viewvc/llvm-project?rev=138311&view=rev Log: Thumb parsing and encoding for SBC. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138311&r1=138310&r2=138311&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 22 18:55:58 2011 @@ -2755,7 +2755,8 @@ // predicated but do have a carry-set and so weren't caught above. if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && - Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") { + Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && + Mnemonic != "sbcs") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138311&r1=138310&r2=138311&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:55:58 2011 @@ -406,4 +406,12 @@ @------------------------------------------------------------------------------ rsbs r1, r3, #0 - rsbs r1, r3, #0 @ encoding: [0x59,0x42] +@ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42] + + + at ------------------------------------------------------------------------------ +@ SBC + at ------------------------------------------------------------------------------ + sbcs r4, r3 + +@ CHECK: sbcs r4, r3 @ encoding: [0x9c,0x41] From grosbach at apple.com Mon Aug 22 18:58:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 22 Aug 2011 23:58:03 -0000 Subject: [llvm-commits] [llvm] r138312 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110822235803.2125A2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 22 18:58:02 2011 New Revision: 138312 URL: http://llvm.org/viewvc/llvm-project?rev=138312&view=rev Log: Thumb parsing and encoding for SETEND. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138312&r1=138311&r2=138312&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Mon Aug 22 18:58:02 2011 @@ -415,3 +415,13 @@ sbcs r4, r3 @ CHECK: sbcs r4, r3 @ encoding: [0x9c,0x41] + + + at ------------------------------------------------------------------------------ +@ SETEND + at ------------------------------------------------------------------------------ + setend be + setend le + +@ CHECK: setend be @ encoding: [0x58,0xb6] +@ CHECK: setend le @ encoding: [0x50,0xb6] From kcc at google.com Mon Aug 22 19:46:43 2011 From: kcc at google.com (Kostya Serebryany) Date: Mon, 22 Aug 2011 17:46:43 -0700 Subject: [llvm-commits] AddressSanitizer, first patch In-Reply-To: References: Message-ID: Hi, I've updated the patch after Nick's comments. http://codereview.appspot.com/4867059/ --kcc On Fri, Aug 19, 2011 at 11:14 AM, Kostya Serebryany wrote: > Hello llvm-commits, > > I would ask you to consider the following patch, which adds the basic > functionality of AddressSanitizer, a memory error detector. > > Quick description: > The tool finds stack and heap out-of-bound bugs and use-after-free bugs. > It consists of an LLVM instrumentation pass and a run-time library which > replaces malloc. > The LLVM pass instruments all memory accesses and inserts redzones around > stack objects and globals. > The run-time library inserts redzones around heap objects and handles > error reporting. > The slowdown introduced by the tool varies between 1.5x and 2.5x (on > CPU2006 the average is 1.73x). > > Until now the tool was developed as a separate project. > It has been quite successful at finding bugs for the Chromium browser > project > ( > http://blog.chromium.org/2011/06/testing-chromium-addresssanitizer-fast.html > ) > and other pieces of Google code. > > For the full description of the tool please read > http://code.google.com/p/address-sanitizer/wiki/AddressSanitizer > > http://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm > http://code.google.com/p/address-sanitizer/wiki/PerformanceNumbers > > > This patch adds the basic instrumentation functionality (w/o stack and > global redzones) and one test. > > If/when this patch is submitted, the following patches will follow: > clang/driver support (flags, etc) > stack/globals support > run-time librrary > integration tests > > The patch file is attached, or it can be viewed at > http://codereview.appspot.com/4867059/ > > Thanks, > > --kcc > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/4b7927c2/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: issue4867059_11001.diff Type: text/x-patch Size: 26659 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/4b7927c2/attachment.bin From bruno.cardoso at gmail.com Mon Aug 22 20:14:17 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 23 Aug 2011 01:14:17 -0000 Subject: [llvm-commits] [llvm] r138317 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86TargetMachine.cpp lib/Target/X86/X86VZeroUpper.cpp test/CodeGen/X86/avx-vzeroupper.ll Message-ID: <20110823011418.004A82A6C12C@llvm.org> Author: bruno Date: Mon Aug 22 20:14:17 2011 New Revision: 138317 URL: http://llvm.org/viewvc/llvm-project?rev=138317&view=rev Log: Introduce a pass to insert vzeroupper instructions to avoid AVX to SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper" llc command line option. This is only the first step (very naive and conservative one) to sketch out the idea, but proper DFA is coming next to allow smarter decisions. Comments and ideas now and in further commits will be very appreciated. Added: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=138317&r1=138316&r2=138317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Aug 22 20:14:17 2011 @@ -32,6 +32,7 @@ X86Subtarget.cpp X86TargetMachine.cpp X86TargetObjectFile.cpp + X86VZeroUpper.cpp ) if( CMAKE_CL_64 ) Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=138317&r1=138316&r2=138317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Mon Aug 22 20:14:17 2011 @@ -48,6 +48,11 @@ /// crossings. FunctionPass *createSSEDomainFixPass(); +/// createX86IssueVZeroUpperPass - This pass inserts AVX vzeroupper instructions +/// before each call to avoid transition penalty between functions encoded with +/// AVX and SSE. +FunctionPass *createX86IssueVZeroUpperPass(); + /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=138317&r1=138316&r2=138317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Aug 22 20:14:17 2011 @@ -16,6 +16,7 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" @@ -92,6 +93,16 @@ } //===----------------------------------------------------------------------===// +// Command line options for x86 +//===----------------------------------------------------------------------===// +bool UseVZeroUpper; + +static cl::opt +VZeroUpper("x86-use-vzeroupper", + cl::desc("Minimize AVX to SSE transition penalty"), + cl::location(UseVZeroUpper), cl::init(false)); + +//===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// @@ -125,6 +136,11 @@ PM.add(createSSEDomainFixPass()); return true; } + + if (Subtarget.hasAVX() && UseVZeroUpper) { + PM.add(createX86IssueVZeroUpperPass()); + return true; + } return false; } Added: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp?rev=138317&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp (added) +++ llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp Mon Aug 22 20:14:17 2011 @@ -0,0 +1,105 @@ +//===-- X86VZeroUpper.cpp - AVX vzeroupper instruction inserter -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the pass which inserts x86 AVX vzeroupper instructions +// before calls to SSE encoded functions. This avoids transition latency +// penalty when tranfering control between AVX encoded instructions and old +// SSE encoding mode. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "x86-codegen" +#include "X86.h" +#include "X86InstrInfo.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/GlobalValue.h" +#include "llvm/Target/TargetInstrInfo.h" +using namespace llvm; + +STATISTIC(NumVZU, "Number of vzeroupper instructions inserted"); + +namespace { + struct VZeroUpperInserter : public MachineFunctionPass { + static char ID; + VZeroUpperInserter() : MachineFunctionPass(ID) {} + + virtual bool runOnMachineFunction(MachineFunction &MF); + + bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); + + virtual const char *getPassName() const { return "X86 vzeroupper inserter";} + + private: + const TargetInstrInfo *TII; // Machine instruction info. + MachineBasicBlock *MBB; // Current basic block + }; + char VZeroUpperInserter::ID = 0; +} + +FunctionPass *llvm::createX86IssueVZeroUpperPass() { + return new VZeroUpperInserter(); +} + +/// runOnMachineFunction - Loop over all of the basic blocks, inserting +/// vzero upper instructions before function calls. +bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { + TII = MF.getTarget().getInstrInfo(); + bool Changed = false; + + // Process any unreachable blocks in arbitrary order now. + for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) + Changed |= processBasicBlock(MF, *BB); + + return Changed; +} + +bool isCallToModuleFn(const MachineInstr *MI) { + assert(MI->getDesc().isCall() && "Isn't a call instruction"); + + for (int i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + + if (!MO.isGlobal()) + continue; + + const GlobalValue *GV = MO.getGlobal(); + GlobalValue::LinkageTypes LT = GV->getLinkage(); + if (GV->isInternalLinkage(LT) || GV->isPrivateLinkage(LT) || + (GV->isExternalLinkage(LT) && !GV->isDeclaration())) + return true; + + return false; + } + return false; +} + +/// processBasicBlock - Loop over all of the instructions in the basic block, +/// inserting vzero upper instructions before function calls. +bool VZeroUpperInserter::processBasicBlock(MachineFunction &MF, + MachineBasicBlock &BB) { + bool Changed = false; + MBB = &BB; + + for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { + MachineInstr *MI = I; + DebugLoc dl = I->getDebugLoc(); + + // Insert a vzeroupper instruction before each control transfer + // to functions outside this module + if (MI->getDesc().isCall() && !isCallToModuleFn(MI)) { + BuildMI(*MBB, I, dl, TII->get(X86::VZEROUPPER)); + ++NumVZU; + } + } + + return Changed; +} Added: llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll?rev=138317&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-vzeroupper.ll Mon Aug 22 20:14:17 2011 @@ -0,0 +1,26 @@ +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +define <4 x float> @do_sse_local(<4 x float> %a) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <4 x float> %a, %a + ret <4 x float> %add.i +} + +; CHECK: _test00 +define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp { +entry: + %add.i = fadd <4 x float> %a, %b + ; CHECK: vzeroupper + ; CHECK-NEXT: callq _do_sse + %call3 = tail call <4 x float> @do_sse(<4 x float> %add.i) nounwind + %sub.i = fsub <4 x float> %call3, %add.i + ; CHECK-NOT: vzeroupper + ; CHECK: callq _do_sse_local + %call8 = tail call <4 x float> @do_sse_local(<4 x float> %sub.i) + ; CHECK: vzeroupper + ; CHECK-NEXT: jmp _do_sse + %call10 = tail call <4 x float> @do_sse(<4 x float> %call8) nounwind + ret <4 x float> %call10 +} + +declare <4 x float> @do_sse(<4 x float>) From geek4civic at gmail.com Mon Aug 22 22:39:59 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 12:39:59 +0900 Subject: [llvm-commits] [llvm] r138213 - /llvm/trunk/lib/Support/Windows/PathV2.inc In-Reply-To: References: <20110820213638.9E0D52A6C12C@llvm.org> Message-ID: 2011/8/21 Aaron Ballman : > On Sun, Aug 21, 2011 at 9:09 AM, NAKAMURA Takumi wrote: >>> + ?// First, check to see if this is a device namespace, which always >>> + ?// starts with \\.\, since device namespaces are not legal file paths. >>> + ?if (path.startswith("\\\\.\\")) >>> + ? ?return true; >> >> I am not sure, though, I am dubious "\\.\" would be handled here >> and other methods in PathV2 would be aware of "\\.\". I am sorry, I mistook and was confused "\\?\" and "\\.\" then. > Yes, \\.\ is one of those path namespaces that you don't see too > often. ?But it does definitely signify a namespace that's not a file > or folder in the traditional sense. ?Since we're already looking for > non-file devices like "con" and "com", supporting \\.\ seems logical > to me. > > Whether other methods in PathV2 would need to be updated for \\.\, > that's a good question. ?I was using this more as a safeguard, in case > it somehow snuck through. Makes sense. Someday we should add namespace-aware tests to unittests/Support/Path. >>> + ?// Then compare against the list of ancient reserved names >>> + ?for (size_t i = 0; i < sizeof(sReservedNames) / sizeof(const char *); ++i) { >>> + ? ?if (path.equals_lower(sReservedNames[i])) >>> + ? ? ?return true; >>> + ?} >> >> Nitpick: Shall we handle "x:\path\to\com9.txt" here? > > I could certainly add that. ?Do we link against shlwapi.lib (available > in Win2k and higher) so that I can use PathFindFileName? ?Or should I > prefer our filename function from PathV2.cpp (this one only worries me > in case we accidentally run into infinite loops at some point)? I think it would be enough to use PathV2 itself to parse path. Using shell api might be overkill (and useless). Note: "x:\path\to\com9.txt" is mapped to the device namespace. Why NTOS does not provide us namespace mapping API? :/ ...Takumi From geek4civic at gmail.com Mon Aug 22 22:45:22 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 12:45:22 +0900 Subject: [llvm-commits] [llvm] r138198 - /llvm/trunk/lib/Support/Windows/Windows.h In-Reply-To: References: <20110820063531.4DE432A6C12C@llvm.org> Message-ID: Anton, >> URL: http://llvm.org/viewvc/llvm-project?rev=138198&view=rev >> Log: >> lib/Support/Windows/Windows.h: Require at least Windows XP(5.1) API. We will not support Windows 2000 any more. > Will you please add a note to the docs? Added stub to ReleaseNotes in r138297. Thanks to point it out. ...Takumi From geek4civic at gmail.com Mon Aug 22 22:49:11 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 03:49:11 -0000 Subject: [llvm-commits] [llvm] r138319 - /llvm/trunk/lib/Support/Windows/Windows.h Message-ID: <20110823034911.743102A6C12C@llvm.org> Author: chapuni Date: Mon Aug 22 22:49:11 2011 New Revision: 138319 URL: http://llvm.org/viewvc/llvm-project?rev=138319&view=rev Log: lib/Support/Windows/Windows.h: Update required IE ver. 0x0600 should be enough for Windows XP. Modified: llvm/trunk/lib/Support/Windows/Windows.h Modified: llvm/trunk/lib/Support/Windows/Windows.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/Windows.h?rev=138319&r1=138318&r2=138319&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/Windows.h (original) +++ llvm/trunk/lib/Support/Windows/Windows.h Mon Aug 22 22:49:11 2011 @@ -21,7 +21,7 @@ // Require at least Windows XP(5.1) API. #define _WIN32_WINNT 0x0501 -#define _WIN32_IE 0x0500 // MinGW at it again. +#define _WIN32_IE 0x0600 // MinGW at it again. #define WIN32_LEAN_AND_MEAN #include "llvm/Config/config.h" // Get build system configuration settings From geek4civic at gmail.com Mon Aug 22 22:53:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 12:53:40 +0900 Subject: [llvm-commits] [PATCH] Updating the IE version specified in Windows.h In-Reply-To: References: Message-ID: 2011/8/22 Aaron Ballman : > Since we switched over to using Windows XP as the base version of > Windows we support, I've updated the IE version constant as well. ?IE6 > shipped with XP, but we were still specifying IE5. > > (You can verify this easily by looking at sdkddkver.h, there's a > section for IE <-> OS which defines the usual mappings.) Thanks. Updated in r138319. (Yeah, I forgot the past, ... which version of IE, Windows XP had...) I don't know, for now, what 0x0600 would provide us. :p ...Takumi From krasin at chromium.org Mon Aug 22 23:36:02 2011 From: krasin at chromium.org (Ivan Krasin) Date: Mon, 22 Aug 2011 21:36:02 -0700 Subject: [llvm-commits] [PATCH]Update config.sub, config.guess, regenerate configure Message-ID: Hi llvm team, this is the second update to config.sub, config.guess and configure. The motivation to do that: 1. Now, llvm would use the stock config.sub. Before that we had an uncommitted FreeBSD-related patch. Now, it has been upstreamed and comes back. It means that it would be easier to update these files in the next time (less magic knowledge) 2. Fix a typo for pseudo-CPUs: 32e[lb] -> [lb]e32, 64e[lb]->[lb]64. One of these CPUs is used for PNaCl and it was not really convenient to have a CPU that starts with a digit. Please, let me know if it's fine to commit. Thanks, Ivan Krasin From krasin at chromium.org Mon Aug 22 23:36:49 2011 From: krasin at chromium.org (Ivan Krasin) Date: Mon, 22 Aug 2011 21:36:49 -0700 Subject: [llvm-commits] [PATCH]Update config.sub, config.guess, regenerate configure In-Reply-To: References: Message-ID: As usuall, I've forgot to attach the patch. Please, find it here... On Mon, Aug 22, 2011 at 9:36 PM, Ivan Krasin wrote: > Hi llvm team, > > this is the second update to config.sub, config.guess and configure. > The motivation to do that: > > 1. Now, llvm would use the stock config.sub. Before that we had an > uncommitted FreeBSD-related patch. Now, it has been upstreamed and > comes back. It means that it would be easier to update these files in > the next time (less magic knowledge) > > 2. Fix a typo for pseudo-CPUs: 32e[lb] -> [lb]e32, 64e[lb]->[lb]64. > One of these CPUs is used for PNaCl and it was not really convenient > to have a CPU that starts with a digit. > > Please, let me know if it's fine to commit. > > Thanks, > Ivan Krasin > -------------- next part -------------- A non-text attachment was scrubbed... Name: config_sub_2011_Aug_22.patch Type: text/x-patch Size: 3351 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/a7a91f9a/attachment.bin From craig.topper at gmail.com Mon Aug 22 23:36:33 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 23 Aug 2011 04:36:33 -0000 Subject: [llvm-commits] [llvm] r138321 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-cmp.ll test/CodeGen/X86/avx-splat.ll Message-ID: <20110823043634.25E9A2A6C12C@llvm.org> Author: ctopper Date: Mon Aug 22 23:36:33 2011 New Revision: 138321 URL: http://llvm.org/viewvc/llvm-project?rev=138321&view=rev Log: Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-cmp.ll llvm/trunk/test/CodeGen/X86/avx-splat.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138321&r1=138320&r2=138321&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 22 23:36:33 2011 @@ -989,6 +989,8 @@ setOperationAction(ISD::SRA, MVT::v8i32, Custom); setOperationAction(ISD::SRA, MVT::v16i16, Custom); + setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); + setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); setOperationAction(ISD::VSETCC, MVT::v4i64, Custom); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138321&r1=138320&r2=138321&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 22 23:36:33 2011 @@ -4889,6 +4889,11 @@ 0>, VEX_4V; defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq, 0>, VEX_4V; + + def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)), + (VPCMPEQQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))), + (VPCMPEQQrm VR128:$src1, addr:$src2)>; } let Constraints = "$src1 = $dst" in { @@ -5099,9 +5104,16 @@ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; } -let Predicates = [HasAVX] in +let Predicates = [HasAVX] in { defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq, 0>, VEX_4V; + + def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), + (VPCMPGTQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), + (VPCMPGTQrm VR128:$src1, addr:$src2)>; +} + let Constraints = "$src1 = $dst" in defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>; @@ -5660,6 +5672,11 @@ def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; +def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))), + (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>; +def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))), + (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>; + //===----------------------------------------------------------------------===// // VMASKMOV - Conditional SIMD Packed Loads and Stores Modified: llvm/trunk/test/CodeGen/X86/avx-cmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cmp.ll?rev=138321&r1=138320&r2=138321&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-cmp.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-cmp.ll Mon Aug 22 23:36:33 2011 @@ -53,3 +53,80 @@ ret <8 x i32> %x } +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpgtq %xmm +; CHECK-NEXT: vpcmpgtq %xmm +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %bincmp = icmp slt <4 x i64> %i, %j + %x = sext <4 x i1> %bincmp to <4 x i64> + ret <4 x i64> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpgtw %xmm +; CHECK-NEXT: vpcmpgtw %xmm +; CHECK-NEXT: vinsertf128 $1 +define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %bincmp = icmp slt <16 x i16> %i, %j + %x = sext <16 x i1> %bincmp to <16 x i16> + ret <16 x i16> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpgtb %xmm +; CHECK-NEXT: vpcmpgtb %xmm +; CHECK-NEXT: vinsertf128 $1 +define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %bincmp = icmp slt <32 x i8> %i, %j + %x = sext <32 x i1> %bincmp to <32 x i8> + ret <32 x i8> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpeqd %xmm +; CHECK-NEXT: vpcmpeqd %xmm +; CHECK-NEXT: vinsertf128 $1 +define <8 x i32> @int256-cmpeq(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %bincmp = icmp eq <8 x i32> %i, %j + %x = sext <8 x i1> %bincmp to <8 x i32> + ret <8 x i32> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpeqq %xmm +; CHECK-NEXT: vpcmpeqq %xmm +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %bincmp = icmp eq <4 x i64> %i, %j + %x = sext <4 x i1> %bincmp to <4 x i64> + ret <4 x i64> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpeqw %xmm +; CHECK-NEXT: vpcmpeqw %xmm +; CHECK-NEXT: vinsertf128 $1 +define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %bincmp = icmp eq <16 x i16> %i, %j + %x = sext <16 x i1> %bincmp to <16 x i16> + ret <16 x i16> %x +} + +; CHECK: vextractf128 $1 +; CHECK: vextractf128 $1 +; CHECK-NEXT: vpcmpeqb %xmm +; CHECK-NEXT: vpcmpeqb %xmm +; CHECK-NEXT: vinsertf128 $1 +define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %bincmp = icmp eq <32 x i8> %i, %j + %x = sext <32 x i1> %bincmp to <32 x i8> + ret <32 x i8> %x +} + Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=138321&r1=138320&r2=138321&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Mon Aug 22 23:36:33 2011 @@ -1,10 +1,8 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s -; FIXME: use avx versions for punpcklbw, punpckhbw and punpckhwd -; CHECK: vextractf128 $0 -; CHECK-NEXT: punpcklbw -; CHECK-NEXT: punpckhbw +; CHECK: vpunpcklbw %xmm +; CHECK-NEXT: vpunpckhbw %xmm ; CHECK-NEXT: vinsertf128 $1 ; CHECK-NEXT: vpermilps $85 define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp { @@ -13,8 +11,7 @@ ret <32 x i8> %shuffle } -; CHECK: vextractf128 $0 -; CHECK-NEXT: punpckhwd +; CHECK: vpunpckhwd %xmm ; CHECK-NEXT: vinsertf128 $1 ; CHECK-NEXT: vpermilps $85 define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp { From bruno.cardoso at gmail.com Tue Aug 23 00:59:40 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 22 Aug 2011 22:59:40 -0700 Subject: [llvm-commits] [llvm] r138321 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-cmp.ll test/CodeGen/X86/avx-splat.ll In-Reply-To: <20110823043634.25E9A2A6C12C@llvm.org> References: <20110823043634.25E9A2A6C12C@llvm.org> Message-ID: Thanks Craig! On Mon, Aug 22, 2011 at 9:36 PM, Craig Topper wrote: > Author: ctopper > Date: Mon Aug 22 23:36:33 2011 > New Revision: 138321 > > URL: http://llvm.org/viewvc/llvm-project?rev=138321&view=rev > Log: > Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td > ? ?llvm/trunk/test/CodeGen/X86/avx-cmp.ll > ? ?llvm/trunk/test/CodeGen/X86/avx-splat.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138321&r1=138320&r2=138321&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 22 23:36:33 2011 > @@ -989,6 +989,8 @@ > ? ? setOperationAction(ISD::SRA, ? ? ? ? ? ? ? MVT::v8i32, Custom); > ? ? setOperationAction(ISD::SRA, ? ? ? ? ? ? ? MVT::v16i16, Custom); > > + ? ?setOperationAction(ISD::VSETCC, ? ? ? ? ? ?MVT::v32i8, Custom); > + ? ?setOperationAction(ISD::VSETCC, ? ? ? ? ? ?MVT::v16i16, Custom); > ? ? setOperationAction(ISD::VSETCC, ? ? ? ? ? ?MVT::v8i32, Custom); > ? ? setOperationAction(ISD::VSETCC, ? ? ? ? ? ?MVT::v4i64, Custom); > > > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138321&r1=138320&r2=138321&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 22 23:36:33 2011 > @@ -4889,6 +4889,11 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0>, VEX_4V; > ? defm VPMULDQ ? : SS41I_binop_rm_int<0x28, "vpmuldq", ? int_x86_sse41_pmuldq, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0>, VEX_4V; > + > + ?def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)), > + ? ? ? ? ? ?(VPCMPEQQrr VR128:$src1, VR128:$src2)>; > + ?def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))), > + ? ? ? ? ? ?(VPCMPEQQrm VR128:$src1, addr:$src2)>; > ?} > > ?let Constraints = "$src1 = $dst" in { > @@ -5099,9 +5104,16 @@ > ? ? ? ? ? (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; > ?} > > -let Predicates = [HasAVX] in > +let Predicates = [HasAVX] in { > ? defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0>, VEX_4V; > + > + ?def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), > + ? ? ? ? ? ?(VPCMPGTQrr VR128:$src1, VR128:$src2)>; > + ?def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), > + ? ? ? ? ? ?(VPCMPGTQrm VR128:$src1, addr:$src2)>; > +} > + > ?let Constraints = "$src1 = $dst" in > ? defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>; > > @@ -5660,6 +5672,11 @@ > ?def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), > ? ? ? ? ? (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; > > +def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))), > + ? ? ? ? ?(v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>; > +def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))), > + ? ? ? ? ?(v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>; > + > > ?//===----------------------------------------------------------------------===// > ?// VMASKMOV - Conditional SIMD Packed Loads and Stores > > Modified: llvm/trunk/test/CodeGen/X86/avx-cmp.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cmp.ll?rev=138321&r1=138320&r2=138321&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/avx-cmp.ll (original) > +++ llvm/trunk/test/CodeGen/X86/avx-cmp.ll Mon Aug 22 23:36:33 2011 > @@ -53,3 +53,80 @@ > ? ret <8 x i32> %x > ?} > > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpgtq ?%xmm > +; CHECK-NEXT: vpcmpgtq ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone { > + ?%bincmp = icmp slt <4 x i64> %i, %j > + ?%x = sext <4 x i1> %bincmp to <4 x i64> > + ?ret <4 x i64> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpgtw ?%xmm > +; CHECK-NEXT: vpcmpgtw ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone { > + ?%bincmp = icmp slt <16 x i16> %i, %j > + ?%x = sext <16 x i1> %bincmp to <16 x i16> > + ?ret <16 x i16> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpgtb ?%xmm > +; CHECK-NEXT: vpcmpgtb ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone { > + ?%bincmp = icmp slt <32 x i8> %i, %j > + ?%x = sext <32 x i1> %bincmp to <32 x i8> > + ?ret <32 x i8> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpeqd ?%xmm > +; CHECK-NEXT: vpcmpeqd ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <8 x i32> @int256-cmpeq(<8 x i32> %i, <8 x i32> %j) nounwind readnone { > + ?%bincmp = icmp eq <8 x i32> %i, %j > + ?%x = sext <8 x i1> %bincmp to <8 x i32> > + ?ret <8 x i32> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpeqq ?%xmm > +; CHECK-NEXT: vpcmpeqq ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { > + ?%bincmp = icmp eq <4 x i64> %i, %j > + ?%x = sext <4 x i1> %bincmp to <4 x i64> > + ?ret <4 x i64> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpeqw ?%xmm > +; CHECK-NEXT: vpcmpeqw ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone { > + ?%bincmp = icmp eq <16 x i16> %i, %j > + ?%x = sext <16 x i1> %bincmp to <16 x i16> > + ?ret <16 x i16> %x > +} > + > +; CHECK: vextractf128 ?$1 > +; CHECK: vextractf128 ?$1 > +; CHECK-NEXT: vpcmpeqb ?%xmm > +; CHECK-NEXT: vpcmpeqb ?%xmm > +; CHECK-NEXT: vinsertf128 $1 > +define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone { > + ?%bincmp = icmp eq <32 x i8> %i, %j > + ?%x = sext <32 x i1> %bincmp to <32 x i8> > + ?ret <32 x i8> %x > +} > + > > Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=138321&r1=138320&r2=138321&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original) > +++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Mon Aug 22 23:36:33 2011 > @@ -1,10 +1,8 @@ > ?; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s > > -; FIXME: use avx versions for punpcklbw, punpckhbw and punpckhwd > > -; CHECK: vextractf128 $0 > -; CHECK-NEXT: punpcklbw > -; CHECK-NEXT: punpckhbw > +; CHECK: vpunpcklbw %xmm > +; CHECK-NEXT: vpunpckhbw %xmm > ?; CHECK-NEXT: vinsertf128 $1 > ?; CHECK-NEXT: vpermilps $85 > ?define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp { > @@ -13,8 +11,7 @@ > ? ret <32 x i8> %shuffle > ?} > > -; CHECK: vextractf128 $0 > -; CHECK-NEXT: punpckhwd > +; CHECK: vpunpckhwd %xmm > ?; CHECK-NEXT: vinsertf128 $1 > ?; CHECK-NEXT: vpermilps $85 > ?define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From zwarich at apple.com Tue Aug 23 01:20:41 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 23 Aug 2011 06:20:41 -0000 Subject: [llvm-commits] [test-suite] r138322 - /test-suite/trunk/External/SPEC/CINT2000/Makefile Message-ID: <20110823062041.747982A6C12C@llvm.org> Author: zwarich Date: Tue Aug 23 01:20:41 2011 New Revision: 138322 URL: http://llvm.org/viewvc/llvm-project?rev=138322&view=rev Log: 176.gcc was disabled with Clang for a use of lvalue casts, but it is easy to patch yourself or get updated source from SPEC. I updated the Apple copy. Modified: test-suite/trunk/External/SPEC/CINT2000/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/Makefile?rev=138322&r1=138321&r2=138322&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/Makefile Tue Aug 23 01:20:41 2011 @@ -13,11 +13,6 @@ 256.bzip2 \ 300.twolf -# Disable 176.gcc when testing with Clang, which doesn't support lvalue casts. -ifdef CC_UNDER_TEST_IS_CLANG -PARALLEL_DIRS := $(filter-out 176.gcc, $(PARALLEL_DIRS)) -endif - # Get the $(ARCH) setting include $(LEVEL)/Makefile.config From echristo at apple.com Tue Aug 23 01:40:12 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 22 Aug 2011 23:40:12 -0700 Subject: [llvm-commits] [PATCH]Update config.sub, config.guess, regenerate configure In-Reply-To: References: Message-ID: <85C9C6AB-FD6D-4C44-B458-58F361AD49F7@apple.com> On Aug 22, 2011, at 9:36 PM, Ivan Krasin wrote: > OK. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/8bc6efcb/attachment.html From krasin at chromium.org Tue Aug 23 01:43:49 2011 From: krasin at chromium.org (Ivan Krasin) Date: Tue, 23 Aug 2011 06:43:49 -0000 Subject: [llvm-commits] [llvm] r138323 - in /llvm/trunk: autoconf/config.guess autoconf/config.sub configure Message-ID: <20110823064349.C540F2A6C12C@llvm.org> Author: krasin Date: Tue Aug 23 01:43:49 2011 New Revision: 138323 URL: http://llvm.org/viewvc/llvm-project?rev=138323&view=rev Log: Update config.sub, config.guess and configure. The motivation to do that: 1. Now, llvm would use the stock config.sub. Before that we had an uncommitted FreeBSD-related patch. Now, it has been upstreamed and comes back. It means that it would be easier to update these files in the next time (less magic knowledge) 2. Fix a typo for pseudo-CPUs: 32e[lb] -> [lb]e32, 64e[lb]->[lb]64. One of these CPUs is used for PNaCl and it was not really convenient to have a CPU that starts with a digit. Modified: llvm/trunk/autoconf/config.guess llvm/trunk/autoconf/config.sub llvm/trunk/configure Modified: llvm/trunk/autoconf/config.guess URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.guess?rev=138323&r1=138322&r2=138323&view=diff ============================================================================== --- llvm/trunk/autoconf/config.guess (original) +++ llvm/trunk/autoconf/config.guess Tue Aug 23 01:43:49 2011 @@ -4,7 +4,7 @@ # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, # 2011 Free Software Foundation, Inc. -timestamp='2011-08-17' +timestamp='2011-08-20' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -793,7 +793,7 @@ exit ;; *:FreeBSD:*:*) UNAME_PROCESSOR=`/usr/bin/uname -p` - case ${UNAME_MACHINE} in + case ${UNAME_PROCESSOR} in amd64) echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; *) Modified: llvm/trunk/autoconf/config.sub URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.sub?rev=138323&r1=138322&r2=138323&view=diff ============================================================================== --- llvm/trunk/autoconf/config.sub (original) +++ llvm/trunk/autoconf/config.sub Tue Aug 23 01:43:49 2011 @@ -4,7 +4,7 @@ # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, # 2011 Free Software Foundation, Inc. -timestamp='2011-08-15' +timestamp='2011-08-23' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software @@ -246,12 +246,12 @@ # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. 1750a | 580 \ - | 32e[bl] | 64e[bl] \ | a29k \ | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | am33_2.0 \ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ | bfin \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ @@ -259,6 +259,7 @@ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | ip2k | iq2000 \ + | le32 | le64 \ | lm32 \ | m32c | m32r | m32rle | m68000 | m68k | m88k \ | maxq | mb | microblaze | mcore | mep | metag \ @@ -352,13 +353,13 @@ ;; # Recognize the basic CPU types with company name. 580-* \ - | 32e[bl]-* | 64e[bl]-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* | avr32-* \ + | be32-* | be64-* \ | bfin-* | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* \ | clipper-* | craynv-* | cydra-* \ @@ -369,6 +370,7 @@ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* | iq2000-* \ + | le32-* | le64-* \ | lm32-* \ | m32c-* | m32r-* | m32rle-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ @@ -816,7 +818,7 @@ os=-mvs ;; nacl) - basic_machine=32el-unknown + basic_machine=le32-unknown os=-nacl ;; ncr3000) Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=138323&r1=138322&r2=138323&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Aug 23 01:43:49 2011 @@ -11614,7 +11614,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < This avoids costly scalarization. Unfortunately, there is no 128-bit byte multiply operation in X86 so I didn't break up MUL of v32i8. Fixes PR10711. -- ~Craig -------------- next part -------------- A non-text attachment was scrubbed... Name: op_lowering.patch Type: application/octet-stream Size: 8671 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110822/1034d5f7/attachment.obj From krasin at google.com Tue Aug 23 01:59:11 2011 From: krasin at google.com (Ivan Krasin) Date: Mon, 22 Aug 2011 23:59:11 -0700 Subject: [llvm-commits] [PATCH]Update config.sub, config.guess, regenerate configure In-Reply-To: <85C9C6AB-FD6D-4C44-B458-58F361AD49F7@apple.com> References: <85C9C6AB-FD6D-4C44-B458-58F361AD49F7@apple.com> Message-ID: Thanks. r138323. On Mon, Aug 22, 2011 at 11:40 PM, Eric Christopher wrote: > > On Aug 22, 2011, at 9:36 PM, Ivan Krasin wrote: > > > > OK. > -eric From nadav.rotem at intel.com Tue Aug 23 02:03:04 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Tue, 23 Aug 2011 10:03:04 +0300 Subject: [llvm-commits] [PATCH] Break 256-bit vector int add/sub/mul into two 128-bit operations In-Reply-To: References: Message-ID: <6594DDFF12B03D4E89690887C2486994029705F0F3@hasmsx504.ger.corp.intel.com> LGTM. -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper Sent: Tuesday, August 23, 2011 09:48 To: llvm-commits at cs.uiuc.edu; bruno.cardoso at gmail.com Subject: [llvm-commits] [PATCH] Break 256-bit vector int add/sub/mul into two 128-bit operations This avoids costly scalarization. Unfortunately, there is no 128-bit byte multiply operation in X86 so I didn't break up MUL of v32i8. Fixes PR10711. -- ~Craig --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From bruno.cardoso at gmail.com Tue Aug 23 02:12:18 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 23 Aug 2011 00:12:18 -0700 Subject: [llvm-commits] [PATCH] Break 256-bit vector int add/sub/mul into two 128-bit operations In-Reply-To: References: Message-ID: Hi Craig, Look great, just some minor stuff: 1) Place some asserts into LowerADD and LowerSUB before calling Lower256IntOp. 2) Remove the ISD::MUL,ADD,SUB assert from Lower256IntOp. 3) Rename Lower256IntOp to Lower256IntArith After fixing this please commit! On Mon, Aug 22, 2011 at 11:48 PM, Craig Topper wrote: > This avoids costly scalarization. Unfortunately, there is no 128-bit > byte multiply operation in X86 so I didn't break up MUL of v32i8. > Fixes PR10711. > > -- > ~Craig > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From krasin at chromium.org Tue Aug 23 02:15:55 2011 From: krasin at chromium.org (Ivan Krasin) Date: Tue, 23 Aug 2011 00:15:55 -0700 Subject: [llvm-commits] Add le32 arch support into Triple Message-ID: Hi llvm team! This patch adds support of le32 pseudo-cpu that stands for generic 32-bit little-endian CPU. PNaCl would use le32-unknown-nacl triple for generating platform-independent pexe (llvm bitcode based), x86_64-unknown-nacl, i686-unknown-nacl and armv7-unknown-nacl for the target-specific NaCl binaries (which would be translated from pexe). The next patch will add a clang target that would be able to generate PNaCl-compatible object files (and, it's expected that after that I will upstream the changes which would allow to get the full pexe programs from clang) Please, let me know if it's fine to commit this patch. Thanks in advance, Ivan Krasin -------------- next part -------------- A non-text attachment was scrubbed... Name: add_le32_cpu.patch Type: text/x-patch Size: 1382 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/c95bde52/attachment.bin From geek4civic at gmail.com Tue Aug 23 05:34:51 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 19:34:51 +0900 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References: Message-ID: Good evening, Aaron! About lib/Support/Windows/RWMutex.inc; - Would you like to try describing rwmutex on windows xp? Oh yeah, I don't have any Windows XP hosts any more. :( - I think, rather to refer to kernel32.dll, GetModuleHandle(NULL) would be more enough. How do you think? - It would be happier for us to have generic "delayed dll resolver" for NT5.1-unavailable entries. I think it might be the global ctor. How do you think? - How about to split RWMutexImpl to Windows XP and higher? - Could you consider unittests for rwmutex? Thanks to work on this! ...Takumi From geek4civic at gmail.com Tue Aug 23 05:58:08 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 23 Aug 2011 19:58:08 +0900 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References: Message-ID: Aaron, about Threading.diff, + (void)::WaitForSingleObject(param.evt, INFINITE); I guess thread object might be the signal object. You may wait for hThread. ...Takumi From grosser at fim.uni-passau.de Tue Aug 23 07:31:14 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 23 Aug 2011 12:31:14 -0000 Subject: [llvm-commits] [polly] r138325 - /polly/trunk/lib/ScheduleOptimizer.cpp Message-ID: <20110823123114.6F2852A6C12C@llvm.org> Author: grosser Date: Tue Aug 23 07:31:14 2011 New Revision: 138325 URL: http://llvm.org/viewvc/llvm-project?rev=138325&view=rev Log: ScheduleOptimizer: Fix some memory errors. This fixes reference counting if the schedule optimizer is used. Modified: polly/trunk/lib/ScheduleOptimizer.cpp Modified: polly/trunk/lib/ScheduleOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=138325&r1=138324&r2=138325&view=diff ============================================================================== --- polly/trunk/lib/ScheduleOptimizer.cpp (original) +++ polly/trunk/lib/ScheduleOptimizer.cpp Tue Aug 23 07:31:14 2011 @@ -97,6 +97,7 @@ isl_map *changeScatteringMap = isl_map_from_basic_map(changeScattering); stmt->setScattering(isl_map_apply_range(scattering, changeScatteringMap)); + isl_dim_free(dim); } } @@ -386,7 +387,8 @@ isl_union_set_from_set(domain)); isl_map *stmtSchedule; isl_union_map_foreach_map(stmtBand, getSingleMap, &stmtSchedule); - stmt->setScattering(stmtSchedule); + stmt->setScattering(isl_map_copy(stmtSchedule)); + isl_union_map_free(stmtBand); } isl_union_map_free(tiledSchedule); From grosser at fim.uni-passau.de Tue Aug 23 07:31:18 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 23 Aug 2011 12:31:18 -0000 Subject: [llvm-commits] [polly] r138326 - /polly/trunk/www/phonecall.html Message-ID: <20110823123118.165F42A6C12D@llvm.org> Author: grosser Date: Tue Aug 23 07:31:17 2011 New Revision: 138326 URL: http://llvm.org/viewvc/llvm-project?rev=138326&view=rev Log: Add information about polyhedral phone call. Added: polly/trunk/www/phonecall.html Added: polly/trunk/www/phonecall.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/phonecall.html?rev=138326&view=auto ============================================================================== --- polly/trunk/www/phonecall.html (added) +++ polly/trunk/www/phonecall.html Tue Aug 23 07:31:17 2011 @@ -0,0 +1,46 @@ + + + + + + Polly - Polyhedral Phone Call + + + + + +
+ +

Polly: Polyhedral Phone Call

+ + +

There are irregular phone calls to discuss polyhedral topics and + related projects. For this we use a conference service that can be + reached both through SIP clients and international dial in numbers.

+ +
    +
  • VoIP/SIP: sip:000777polyhedral at iptel.org
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+ + From criswell at uiuc.edu Tue Aug 23 09:47:13 2011 From: criswell at uiuc.edu (John Criswell) Date: Tue, 23 Aug 2011 14:47:13 -0000 Subject: [llvm-commits] [poolalloc] r138328 - /poolalloc/trunk/include/dsa/DSCallGraph.h Message-ID: <20110823144713.A0BA92A6C12C@llvm.org> Author: criswell Date: Tue Aug 23 09:47:13 2011 New Revision: 138328 URL: http://llvm.org/viewvc/llvm-project?rev=138328&view=rev Log: Removed cryptic comment about include cassert. Re-ordered includes to be as close to the LLVM convention as is currently possible. Modified: poolalloc/trunk/include/dsa/DSCallGraph.h Modified: poolalloc/trunk/include/dsa/DSCallGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSCallGraph.h?rev=138328&r1=138327&r2=138328&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSCallGraph.h (original) +++ poolalloc/trunk/include/dsa/DSCallGraph.h Tue Aug 23 09:47:13 2011 @@ -16,13 +16,12 @@ #include "dsa/svset.h" #include "dsa/keyiterator.h" -#include -//Fix in 2.8, EQC includes cassert -#include #include "llvm/ADT/EquivalenceClasses.h" #include "llvm/Support/CallSite.h" +#include +#include class DSCallGraph { public: From Micah.Villmow at amd.com Tue Aug 23 10:05:51 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Tue, 23 Aug 2011 10:05:51 -0500 Subject: [llvm-commits] Patch to fix typo in FastISelEmitter Message-ID: Found a problem with TableGen in where there is a typo in FastISelEmitter.cpp. Patch is attached. Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/5c43a41f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: FastISelEmitter_fpimm_typo.patch Type: application/octet-stream Size: 582 bytes Desc: FastISelEmitter_fpimm_typo.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/5c43a41f/attachment.obj From echristo at apple.com Tue Aug 23 10:42:35 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 15:42:35 -0000 Subject: [llvm-commits] [llvm] r138330 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp Message-ID: <20110823154236.063712A6C12C@llvm.org> Author: echristo Date: Tue Aug 23 10:42:35 2011 New Revision: 138330 URL: http://llvm.org/viewvc/llvm-project?rev=138330&view=rev Log: Fix fpimmm->fpimm typo. Patch by Micah Villmow! Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=138330&r1=138329&r2=138330&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Aug 23 10:42:35 2011 @@ -504,7 +504,7 @@ std::vector* PhysRegInputs = new std::vector(); if (InstPatNode->getOperator()->getName() == "imm" || - InstPatNode->getOperator()->getName() == "fpimmm") + InstPatNode->getOperator()->getName() == "fpimm") PhysRegInputs->push_back(""); else { // Compute the PhysRegs used by the given pattern, and check that From echristo at apple.com Tue Aug 23 10:44:23 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 08:44:23 -0700 Subject: [llvm-commits] Patch to fix typo in FastISelEmitter In-Reply-To: References: Message-ID: <5437B81A-2892-433D-A833-BAAA5580C18F@apple.com> On Aug 23, 2011, at 8:05 AM, Villmow, Micah wrote: > Found a problem with TableGen in where there is a typo in FastISelEmitter.cpp. Patch is attached. > > Thanks, > Micah > _______________________________________________ Applied here: [ghostwheel:llvm/utils/TableGen] echristo% svn ci Sending TableGen/FastISelEmitter.cpp Transmitting file data . Committed revision 138330. In the future please create patches off of the top level directory instead of just inside the last directory. Thanks! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/a3914911/attachment.html From echristo at apple.com Tue Aug 23 10:45:03 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 08:45:03 -0700 Subject: [llvm-commits] Add le32 arch support into Triple In-Reply-To: References: Message-ID: <411672AA-33B4-4B21-8DA0-E066707E6BD1@apple.com> On Aug 23, 2011, at 12:15 AM, Ivan Krasin wrote: > OK. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/88b12581/attachment.html From Micah.Villmow at amd.com Tue Aug 23 10:59:07 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Tue, 23 Aug 2011 10:59:07 -0500 Subject: [llvm-commits] Patch to fix typo in FastISelEmitter In-Reply-To: <5437B81A-2892-433D-A833-BAAA5580C18F@apple.com> References: <5437B81A-2892-433D-A833-BAAA5580C18F@apple.com> Message-ID: Gotcha! Thanks! From: Eric Christopher [mailto:echristo at apple.com] Sent: Tuesday, August 23, 2011 8:44 AM To: Villmow, Micah Cc: llvm-commits Subject: Re: [llvm-commits] Patch to fix typo in FastISelEmitter On Aug 23, 2011, at 8:05 AM, Villmow, Micah wrote: Found a problem with TableGen in where there is a typo in FastISelEmitter.cpp. Patch is attached. Thanks, Micah _______________________________________________ Applied here: [ghostwheel:llvm/utils/TableGen] echristo% svn ci Sending TableGen/FastISelEmitter.cpp Transmitting file data . Committed revision 138330. In the future please create patches off of the top level directory instead of just inside the last directory. Thanks! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/7305548f/attachment-0001.html From bob.wilson at apple.com Tue Aug 23 11:40:18 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 23 Aug 2011 16:40:18 -0000 Subject: [llvm-commits] [compiler-rt] r138332 - in /compiler-rt/trunk/lib/arm: adddf3vfp.S addsf3vfp.S divdf3vfp.S divsf3vfp.S eqdf2vfp.S eqsf2vfp.S extendsfdf2vfp.S fixdfsivfp.S fixsfsivfp.S fixunsdfsivfp.S fixunssfsivfp.S floatsidfvfp.S floatsisfvfp.S floatunssidfvfp.S floatunssisfvfp.S gedf2vfp.S gesf2vfp.S gtdf2vfp.S gtsf2vfp.S ledf2vfp.S lesf2vfp.S ltdf2vfp.S ltsf2vfp.S muldf3vfp.S mulsf3vfp.S nedf2vfp.S negdf2vfp.S negsf2vfp.S nesf2vfp.S subdf3vfp.S subsf3vfp.S truncdfsf2vfp.S unorddf2vfp.S unordsf2vfp.S Message-ID: <20110823164018.CD87F2A6C12C@llvm.org> Author: bwilson Date: Tue Aug 23 11:40:18 2011 New Revision: 138332 URL: http://llvm.org/viewvc/llvm-project?rev=138332&view=rev Log: Change ARM vfp assembly functions to use unified syntax. Modified: compiler-rt/trunk/lib/arm/adddf3vfp.S compiler-rt/trunk/lib/arm/addsf3vfp.S compiler-rt/trunk/lib/arm/divdf3vfp.S compiler-rt/trunk/lib/arm/divsf3vfp.S compiler-rt/trunk/lib/arm/eqdf2vfp.S compiler-rt/trunk/lib/arm/eqsf2vfp.S compiler-rt/trunk/lib/arm/extendsfdf2vfp.S compiler-rt/trunk/lib/arm/fixdfsivfp.S compiler-rt/trunk/lib/arm/fixsfsivfp.S compiler-rt/trunk/lib/arm/fixunsdfsivfp.S compiler-rt/trunk/lib/arm/fixunssfsivfp.S compiler-rt/trunk/lib/arm/floatsidfvfp.S compiler-rt/trunk/lib/arm/floatsisfvfp.S compiler-rt/trunk/lib/arm/floatunssidfvfp.S compiler-rt/trunk/lib/arm/floatunssisfvfp.S compiler-rt/trunk/lib/arm/gedf2vfp.S compiler-rt/trunk/lib/arm/gesf2vfp.S compiler-rt/trunk/lib/arm/gtdf2vfp.S compiler-rt/trunk/lib/arm/gtsf2vfp.S compiler-rt/trunk/lib/arm/ledf2vfp.S compiler-rt/trunk/lib/arm/lesf2vfp.S compiler-rt/trunk/lib/arm/ltdf2vfp.S compiler-rt/trunk/lib/arm/ltsf2vfp.S compiler-rt/trunk/lib/arm/muldf3vfp.S compiler-rt/trunk/lib/arm/mulsf3vfp.S compiler-rt/trunk/lib/arm/nedf2vfp.S compiler-rt/trunk/lib/arm/negdf2vfp.S compiler-rt/trunk/lib/arm/negsf2vfp.S compiler-rt/trunk/lib/arm/nesf2vfp.S compiler-rt/trunk/lib/arm/subdf3vfp.S compiler-rt/trunk/lib/arm/subsf3vfp.S compiler-rt/trunk/lib/arm/truncdfsf2vfp.S compiler-rt/trunk/lib/arm/unorddf2vfp.S compiler-rt/trunk/lib/arm/unordsf2vfp.S Modified: compiler-rt/trunk/lib/arm/adddf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/adddf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/adddf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/adddf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Adds two double precision floating point numbers using the Darwin // calling convention where double arguments are passsed in GPR pairs // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__adddf3vfp) - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 - faddd d6, d6, d7 - fmrrd r0, r1, d6 // move result back to r0/r1 pair + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 + vadd.f64 d6, d6, d7 + vmov r0, r1, d6 // move result back to r0/r1 pair bx lr Modified: compiler-rt/trunk/lib/arm/addsf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/addsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/addsf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/addsf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Adds two single precision floating point numbers using the Darwin // calling convention where single arguments are passsed in GPRs // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__addsf3vfp) - fmsr s14, r0 // move first param from r0 into float register - fmsr s15, r1 // move second param from r1 into float register - fadds s14, s14, s15 - fmrs r0, s14 // move result back to r0 + vmov s14, r0 // move first param from r0 into float register + vmov s15, r1 // move second param from r1 into float register + vadd.f32 s14, s14, s15 + vmov r0, s14 // move result back to r0 bx lr Modified: compiler-rt/trunk/lib/arm/divdf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/divdf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/divdf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/divdf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Divides two double precision floating point numbers using the Darwin // calling convention where double arguments are passsed in GPR pairs // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__divdf3vfp) - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 - fdivd d5, d6, d7 - fmrrd r0, r1, d5 // move result back to r0/r1 pair + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 + vdiv.f64 d5, d6, d7 + vmov r0, r1, d5 // move result back to r0/r1 pair bx lr Modified: compiler-rt/trunk/lib/arm/divsf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/divsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/divsf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/divsf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Divides two single precision floating point numbers using the Darwin // calling convention where single arguments are passsed like 32-bit ints. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__divsf3vfp) - fmsr s14, r0 // move first param from r0 into float register - fmsr s15, r1 // move second param from r1 into float register - fdivs s13, s14, s15 - fmrs r0, s13 // move result back to r0 + vmov s14, r0 // move first param from r0 into float register + vmov s15, r1 // move second param from r1 into float register + vdiv.f32 s13, s14, s15 + vmov r0, s13 // move result back to r0 bx lr Modified: compiler-rt/trunk/lib/arm/eqdf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/eqdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/eqdf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/eqdf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr moveq r0, #1 // set result register to 1 if equal movne r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/eqsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/eqsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/eqsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/eqsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__eqsf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr moveq r0, #1 // set result register to 1 if equal movne r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/extendsfdf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/extendsfdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/extendsfdf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/extendsfdf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a single precision parameter is // passed in a GPR and a double precision result is returned in R0/R1 pair. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp) - fmsr s15, r0 // load float register from R0 - fcvtds d7, s15 // convert single to double - fmrrd r0, r1, d7 // return result in r0/r1 pair + vmov s15, r0 // load float register from R0 + vcvt.f64.f32 d7, s15 // convert single to double + vmov r0, r1, d7 // return result in r0/r1 pair bx lr Modified: compiler-rt/trunk/lib/arm/fixdfsivfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixdfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/fixdfsivfp.S (original) +++ compiler-rt/trunk/lib/arm/fixdfsivfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a double precision parameter is // passed in GPR register pair. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp) - fmdrr d7, r0, r1 // load double register from R0/R1 - ftosizd s15, d7 // convert double to 32-bit int into s15 - fmrs r0, s15 // move s15 to result register + vmov d7, r0, r1 // load double register from R0/R1 + vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/fixsfsivfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixsfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/fixsfsivfp.S (original) +++ compiler-rt/trunk/lib/arm/fixsfsivfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a single precision parameter is // passed in a GPR.. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__fixsfsivfp) - fmsr s15, r0 // load float register from R0 - ftosizs s15, s15 // convert single to 32-bit int into s15 - fmrs r0, s15 // move s15 to result register + vmov s15, r0 // load float register from R0 + vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/fixunsdfsivfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixunsdfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/fixunsdfsivfp.S (original) +++ compiler-rt/trunk/lib/arm/fixunsdfsivfp.S Tue Aug 23 11:40:18 2011 @@ -17,9 +17,10 @@ // Uses Darwin calling convention where a double precision parameter is // passed in GPR register pair. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp) - fmdrr d7, r0, r1 // load double register from R0/R1 - ftouizd s15, d7 // convert double to 32-bit int into s15 - fmrs r0, s15 // move s15 to result register + vmov d7, r0, r1 // load double register from R0/R1 + vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/fixunssfsivfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixunssfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/fixunssfsivfp.S (original) +++ compiler-rt/trunk/lib/arm/fixunssfsivfp.S Tue Aug 23 11:40:18 2011 @@ -17,9 +17,10 @@ // Uses Darwin calling convention where a single precision parameter is // passed in a GPR.. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__fixunssfsivfp) - fmsr s15, r0 // load float register from R0 - ftouizs s15, s15 // convert single to 32-bit unsigned into s15 - fmrs r0, s15 // move s15 to result register + vmov s15, r0 // load float register from R0 + vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/floatsidfvfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatsidfvfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/floatsidfvfp.S (original) +++ compiler-rt/trunk/lib/arm/floatsidfvfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a double precision result is // return in GPR register pair. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp) - fmsr s15, r0 // move int to float register s15 - fsitod d7, s15 // convert 32-bit int in s15 to double in d7 - fmrrd r0, r1, d7 // move d7 to result register pair r0/r1 + vmov s15, r0 // move int to float register s15 + vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7 + vmov r0, r1, d7 // move d7 to result register pair r0/r1 bx lr Modified: compiler-rt/trunk/lib/arm/floatsisfvfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatsisfvfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/floatsisfvfp.S (original) +++ compiler-rt/trunk/lib/arm/floatsisfvfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a single precision result is // return in a GPR.. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__floatsisfvfp) - fmsr s15, r0 // move int to float register s15 - fsitos s15, s15 // convert 32-bit int in s15 to float in s15 - fmrs r0, s15 // move s15 to result register + vmov s15, r0 // move int to float register s15 + vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/floatunssidfvfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatunssidfvfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/floatunssidfvfp.S (original) +++ compiler-rt/trunk/lib/arm/floatunssidfvfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a double precision result is // return in GPR register pair. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp) - fmsr s15, r0 // move int to float register s15 - fuitod d7, s15 // convert 32-bit int in s15 to double in d7 - fmrrd r0, r1, d7 // move d7 to result register pair r0/r1 + vmov s15, r0 // move int to float register s15 + vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7 + vmov r0, r1, d7 // move d7 to result register pair r0/r1 bx lr Modified: compiler-rt/trunk/lib/arm/floatunssisfvfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatunssisfvfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/floatunssisfvfp.S (original) +++ compiler-rt/trunk/lib/arm/floatunssisfvfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a single precision result is // return in a GPR.. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__floatunssisfvfp) - fmsr s15, r0 // move int to float register s15 - fuitos s15, s15 // convert 32-bit int in s15 to float in s15 - fmrs r0, s15 // move s15 to result register + vmov s15, r0 // move int to float register s15 + vcvt.f32.u32 s15, s15 // convert 32-bit int in s15 to float in s15 + vmov r0, s15 // move s15 to result register bx lr Modified: compiler-rt/trunk/lib/arm/gedf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gedf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/gedf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/gedf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__gedf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movge r0, #1 // set result register to 1 if greater than or equal movlt r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/gesf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/gesf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/gesf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__gesf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movge r0, #1 // set result register to 1 if greater than or equal movlt r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/gtdf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gtdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/gtdf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/gtdf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__gtdf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movgt r0, #1 // set result register to 1 if equal movle r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/gtsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gtsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/gtsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/gtsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__gtsf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movgt r0, #1 // set result register to 1 if equal movle r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/ledf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ledf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/ledf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/ledf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__ledf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movls r0, #1 // set result register to 1 if equal movhi r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/lesf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/lesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/lesf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/lesf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__lesf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movls r0, #1 // set result register to 1 if equal movhi r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/ltdf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ltdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/ltdf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/ltdf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__ltdf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movmi r0, #1 // set result register to 1 if equal movpl r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/ltsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ltsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/ltsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/ltsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__ltsf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movmi r0, #1 // set result register to 1 if equal movpl r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/muldf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/muldf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/muldf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/muldf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Multiplies two double precision floating point numbers using the Darwin // calling convention where double arguments are passsed in GPR pairs // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__muldf3vfp) - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 - fmuld d6, d6, d7 - fmrrd r0, r1, d6 // move result back to r0/r1 pair + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 + vmul.f64 d6, d6, d7 + vmov r0, r1, d6 // move result back to r0/r1 pair bx lr Modified: compiler-rt/trunk/lib/arm/mulsf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/mulsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/mulsf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/mulsf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Multiplies two single precision floating point numbers using the Darwin // calling convention where single arguments are passsed like 32-bit ints. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__mulsf3vfp) - fmsr s14, r0 // move first param from r0 into float register - fmsr s15, r1 // move second param from r1 into float register - fmuls s13, s14, s15 - fmrs r0, s13 // move result back to r0 + vmov s14, r0 // move first param from r0 into float register + vmov s15, r1 // move second param from r1 into float register + vmul.f32 s13, s14, s15 + vmov r0, s13 // move result back to r0 bx lr Modified: compiler-rt/trunk/lib/arm/nedf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/nedf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/nedf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/nedf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__nedf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movne r0, #1 // set result register to 0 if unequal moveq r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/negdf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/negdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/negdf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/negdf2vfp.S Tue Aug 23 11:40:18 2011 @@ -15,6 +15,7 @@ // Returns the negation a double precision floating point numbers using the // Darwin calling convention where double arguments are passsed in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__negdf2vfp) eor r1, r1, #-2147483648 // flip sign bit on double in r0/r1 pair Modified: compiler-rt/trunk/lib/arm/negsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/negsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/negsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/negsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -15,6 +15,7 @@ // Returns the negation of a single precision floating point numbers using the // Darwin calling convention where single arguments are passsed like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__negsf2vfp) eor r0, r0, #-2147483648 // flip sign bit on float in r0 Modified: compiler-rt/trunk/lib/arm/nesf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/nesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/nesf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/nesf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__nesf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movne r0, #1 // set result register to 1 if unequal moveq r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/subdf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/subdf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/subdf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/subdf3vfp.S Tue Aug 23 11:40:18 2011 @@ -15,10 +15,11 @@ // Returns difference between two double precision floating point numbers using // the Darwin calling convention where double arguments are passsed in GPR pairs // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__subdf3vfp) - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 - fsubd d6, d6, d7 - fmrrd r0, r1, d6 // move result back to r0/r1 pair + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 + vsub.f64 d6, d6, d7 + vmov r0, r1, d6 // move result back to r0/r1 pair bx lr Modified: compiler-rt/trunk/lib/arm/subsf3vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/subsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/subsf3vfp.S (original) +++ compiler-rt/trunk/lib/arm/subsf3vfp.S Tue Aug 23 11:40:18 2011 @@ -16,10 +16,11 @@ // using the Darwin calling convention where single arguments are passsed // like 32-bit ints. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__subsf3vfp) - fmsr s14, r0 // move first param from r0 into float register - fmsr s15, r1 // move second param from r1 into float register - fsubs s14, s14, s15 - fmrs r0, s14 // move result back to r0 + vmov s14, r0 // move first param from r0 into float register + vmov s15, r1 // move second param from r1 into float register + vsub.f32 s14, s14, s15 + vmov r0, s14 // move result back to r0 bx lr Modified: compiler-rt/trunk/lib/arm/truncdfsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/truncdfsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/truncdfsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/truncdfsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,9 +16,10 @@ // Uses Darwin calling convention where a double precision parameter is // passed in a R0/R1 pair and a signle precision result is returned in R0. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__truncdfsf2vfp) - fmdrr d7, r0, r1 // load double from r0/r1 pair - fcvtsd s15, d7 // convert double to single (trucate precision) - fmrs r0, s15 // return result in r0 + vmov d7, r0, r1 // load double from r0/r1 pair + vcvt.f32.f64 s15, d7 // convert double to single (trucate precision) + vmov r0, s15 // return result in r0 bx lr Modified: compiler-rt/trunk/lib/arm/unorddf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/unorddf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/unorddf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/unorddf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where double precision arguments are passsed // like in GPR pairs. // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__unorddf2vfp) - fmdrr d6, r0, r1 // load r0/r1 pair in double register - fmdrr d7, r2, r3 // load r2/r3 pair in double register - fcmpd d6, d7 - fmstat + vmov d6, r0, r1 // load r0/r1 pair in double register + vmov d7, r2, r3 // load r2/r3 pair in double register + vcmp.f64 d6, d7 + vmrs apsr_nzcv, fpscr movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) movvc r0, #0 bx lr Modified: compiler-rt/trunk/lib/arm/unordsf2vfp.S URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/unordsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff ============================================================================== --- compiler-rt/trunk/lib/arm/unordsf2vfp.S (original) +++ compiler-rt/trunk/lib/arm/unordsf2vfp.S Tue Aug 23 11:40:18 2011 @@ -16,12 +16,13 @@ // Uses Darwin calling convention where single precision arguments are passsed // like 32-bit ints // + .syntax unified .align 2 DEFINE_COMPILERRT_FUNCTION(__unordsf2vfp) - fmsr s14, r0 // move from GPR 0 to float register - fmsr s15, r1 // move from GPR 1 to float register - fcmps s14, s15 - fmstat + vmov s14, r0 // move from GPR 0 to float register + vmov s15, r1 // move from GPR 1 to float register + vcmp.f32 s14, s15 + vmrs apsr_nzcv, fpscr movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) movvc r0, #0 bx lr From grosbach at apple.com Tue Aug 23 11:44:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 09:44:36 -0700 Subject: [llvm-commits] [compiler-rt] r138332 - in /compiler-rt/trunk/lib/arm: adddf3vfp.S addsf3vfp.S divdf3vfp.S divsf3vfp.S eqdf2vfp.S eqsf2vfp.S extendsfdf2vfp.S fixdfsivfp.S fixsfsivfp.S fixunsdfsivfp.S fixunssfsivfp.S floatsidfvfp.S floatsisfvfp.S floatunssidfvfp.S floatunssisfvfp.S gedf2vfp.S gesf2vfp.S gtdf2vfp.S gtsf2vfp.S ledf2vfp.S lesf2vfp.S ltdf2vfp.S ltsf2vfp.S muldf3vfp.S mulsf3vfp.S nedf2vfp.S negdf2vfp.S negsf2vfp.S nesf2vfp.S subdf3vfp.S subsf3vfp.S truncdfsf2vfp.S unorddf2vfp.S unordsf2vfp.S In-Reply-To: <20110823164018.CD87F2A6C12C@llvm.org> References: <20110823164018.CD87F2A6C12C@llvm.org> Message-ID: Excellent! Thanks, Bob. -Jim On Aug 23, 2011, at 9:40 AM, Bob Wilson wrote: > Author: bwilson > Date: Tue Aug 23 11:40:18 2011 > New Revision: 138332 > > URL: http://llvm.org/viewvc/llvm-project?rev=138332&view=rev > Log: > Change ARM vfp assembly functions to use unified syntax. > > Modified: > compiler-rt/trunk/lib/arm/adddf3vfp.S > compiler-rt/trunk/lib/arm/addsf3vfp.S > compiler-rt/trunk/lib/arm/divdf3vfp.S > compiler-rt/trunk/lib/arm/divsf3vfp.S > compiler-rt/trunk/lib/arm/eqdf2vfp.S > compiler-rt/trunk/lib/arm/eqsf2vfp.S > compiler-rt/trunk/lib/arm/extendsfdf2vfp.S > compiler-rt/trunk/lib/arm/fixdfsivfp.S > compiler-rt/trunk/lib/arm/fixsfsivfp.S > compiler-rt/trunk/lib/arm/fixunsdfsivfp.S > compiler-rt/trunk/lib/arm/fixunssfsivfp.S > compiler-rt/trunk/lib/arm/floatsidfvfp.S > compiler-rt/trunk/lib/arm/floatsisfvfp.S > compiler-rt/trunk/lib/arm/floatunssidfvfp.S > compiler-rt/trunk/lib/arm/floatunssisfvfp.S > compiler-rt/trunk/lib/arm/gedf2vfp.S > compiler-rt/trunk/lib/arm/gesf2vfp.S > compiler-rt/trunk/lib/arm/gtdf2vfp.S > compiler-rt/trunk/lib/arm/gtsf2vfp.S > compiler-rt/trunk/lib/arm/ledf2vfp.S > compiler-rt/trunk/lib/arm/lesf2vfp.S > compiler-rt/trunk/lib/arm/ltdf2vfp.S > compiler-rt/trunk/lib/arm/ltsf2vfp.S > compiler-rt/trunk/lib/arm/muldf3vfp.S > compiler-rt/trunk/lib/arm/mulsf3vfp.S > compiler-rt/trunk/lib/arm/nedf2vfp.S > compiler-rt/trunk/lib/arm/negdf2vfp.S > compiler-rt/trunk/lib/arm/negsf2vfp.S > compiler-rt/trunk/lib/arm/nesf2vfp.S > compiler-rt/trunk/lib/arm/subdf3vfp.S > compiler-rt/trunk/lib/arm/subsf3vfp.S > compiler-rt/trunk/lib/arm/truncdfsf2vfp.S > compiler-rt/trunk/lib/arm/unorddf2vfp.S > compiler-rt/trunk/lib/arm/unordsf2vfp.S > > Modified: compiler-rt/trunk/lib/arm/adddf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/adddf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/adddf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/adddf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Adds two double precision floating point numbers using the Darwin > // calling convention where double arguments are passsed in GPR pairs > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__adddf3vfp) > - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 > - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 > - faddd d6, d6, d7 > - fmrrd r0, r1, d6 // move result back to r0/r1 pair > + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 > + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 > + vadd.f64 d6, d6, d7 > + vmov r0, r1, d6 // move result back to r0/r1 pair > bx lr > > Modified: compiler-rt/trunk/lib/arm/addsf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/addsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/addsf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/addsf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Adds two single precision floating point numbers using the Darwin > // calling convention where single arguments are passsed in GPRs > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__addsf3vfp) > - fmsr s14, r0 // move first param from r0 into float register > - fmsr s15, r1 // move second param from r1 into float register > - fadds s14, s14, s15 > - fmrs r0, s14 // move result back to r0 > + vmov s14, r0 // move first param from r0 into float register > + vmov s15, r1 // move second param from r1 into float register > + vadd.f32 s14, s14, s15 > + vmov r0, s14 // move result back to r0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/divdf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/divdf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/divdf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/divdf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Divides two double precision floating point numbers using the Darwin > // calling convention where double arguments are passsed in GPR pairs > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__divdf3vfp) > - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 > - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 > - fdivd d5, d6, d7 > - fmrrd r0, r1, d5 // move result back to r0/r1 pair > + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 > + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 > + vdiv.f64 d5, d6, d7 > + vmov r0, r1, d5 // move result back to r0/r1 pair > bx lr > > Modified: compiler-rt/trunk/lib/arm/divsf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/divsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/divsf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/divsf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Divides two single precision floating point numbers using the Darwin > // calling convention where single arguments are passsed like 32-bit ints. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__divsf3vfp) > - fmsr s14, r0 // move first param from r0 into float register > - fmsr s15, r1 // move second param from r1 into float register > - fdivs s13, s14, s15 > - fmrs r0, s13 // move result back to r0 > + vmov s14, r0 // move first param from r0 into float register > + vmov s15, r1 // move second param from r1 into float register > + vdiv.f32 s13, s14, s15 > + vmov r0, s13 // move result back to r0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/eqdf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/eqdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/eqdf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/eqdf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > moveq r0, #1 // set result register to 1 if equal > movne r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/eqsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/eqsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/eqsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/eqsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__eqsf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > moveq r0, #1 // set result register to 1 if equal > movne r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/extendsfdf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/extendsfdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/extendsfdf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/extendsfdf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a single precision parameter is > // passed in a GPR and a double precision result is returned in R0/R1 pair. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp) > - fmsr s15, r0 // load float register from R0 > - fcvtds d7, s15 // convert single to double > - fmrrd r0, r1, d7 // return result in r0/r1 pair > + vmov s15, r0 // load float register from R0 > + vcvt.f64.f32 d7, s15 // convert single to double > + vmov r0, r1, d7 // return result in r0/r1 pair > bx lr > > Modified: compiler-rt/trunk/lib/arm/fixdfsivfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixdfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/fixdfsivfp.S (original) > +++ compiler-rt/trunk/lib/arm/fixdfsivfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a double precision parameter is > // passed in GPR register pair. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp) > - fmdrr d7, r0, r1 // load double register from R0/R1 > - ftosizd s15, d7 // convert double to 32-bit int into s15 > - fmrs r0, s15 // move s15 to result register > + vmov d7, r0, r1 // load double register from R0/R1 > + vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/fixsfsivfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixsfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/fixsfsivfp.S (original) > +++ compiler-rt/trunk/lib/arm/fixsfsivfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a single precision parameter is > // passed in a GPR.. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__fixsfsivfp) > - fmsr s15, r0 // load float register from R0 > - ftosizs s15, s15 // convert single to 32-bit int into s15 > - fmrs r0, s15 // move s15 to result register > + vmov s15, r0 // load float register from R0 > + vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/fixunsdfsivfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixunsdfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/fixunsdfsivfp.S (original) > +++ compiler-rt/trunk/lib/arm/fixunsdfsivfp.S Tue Aug 23 11:40:18 2011 > @@ -17,9 +17,10 @@ > // Uses Darwin calling convention where a double precision parameter is > // passed in GPR register pair. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp) > - fmdrr d7, r0, r1 // load double register from R0/R1 > - ftouizd s15, d7 // convert double to 32-bit int into s15 > - fmrs r0, s15 // move s15 to result register > + vmov d7, r0, r1 // load double register from R0/R1 > + vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/fixunssfsivfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/fixunssfsivfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/fixunssfsivfp.S (original) > +++ compiler-rt/trunk/lib/arm/fixunssfsivfp.S Tue Aug 23 11:40:18 2011 > @@ -17,9 +17,10 @@ > // Uses Darwin calling convention where a single precision parameter is > // passed in a GPR.. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__fixunssfsivfp) > - fmsr s15, r0 // load float register from R0 > - ftouizs s15, s15 // convert single to 32-bit unsigned into s15 > - fmrs r0, s15 // move s15 to result register > + vmov s15, r0 // load float register from R0 > + vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/floatsidfvfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatsidfvfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/floatsidfvfp.S (original) > +++ compiler-rt/trunk/lib/arm/floatsidfvfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a double precision result is > // return in GPR register pair. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp) > - fmsr s15, r0 // move int to float register s15 > - fsitod d7, s15 // convert 32-bit int in s15 to double in d7 > - fmrrd r0, r1, d7 // move d7 to result register pair r0/r1 > + vmov s15, r0 // move int to float register s15 > + vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7 > + vmov r0, r1, d7 // move d7 to result register pair r0/r1 > bx lr > > Modified: compiler-rt/trunk/lib/arm/floatsisfvfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatsisfvfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/floatsisfvfp.S (original) > +++ compiler-rt/trunk/lib/arm/floatsisfvfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a single precision result is > // return in a GPR.. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__floatsisfvfp) > - fmsr s15, r0 // move int to float register s15 > - fsitos s15, s15 // convert 32-bit int in s15 to float in s15 > - fmrs r0, s15 // move s15 to result register > + vmov s15, r0 // move int to float register s15 > + vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/floatunssidfvfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatunssidfvfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/floatunssidfvfp.S (original) > +++ compiler-rt/trunk/lib/arm/floatunssidfvfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a double precision result is > // return in GPR register pair. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp) > - fmsr s15, r0 // move int to float register s15 > - fuitod d7, s15 // convert 32-bit int in s15 to double in d7 > - fmrrd r0, r1, d7 // move d7 to result register pair r0/r1 > + vmov s15, r0 // move int to float register s15 > + vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7 > + vmov r0, r1, d7 // move d7 to result register pair r0/r1 > bx lr > > Modified: compiler-rt/trunk/lib/arm/floatunssisfvfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/floatunssisfvfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/floatunssisfvfp.S (original) > +++ compiler-rt/trunk/lib/arm/floatunssisfvfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a single precision result is > // return in a GPR.. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__floatunssisfvfp) > - fmsr s15, r0 // move int to float register s15 > - fuitos s15, s15 // convert 32-bit int in s15 to float in s15 > - fmrs r0, s15 // move s15 to result register > + vmov s15, r0 // move int to float register s15 > + vcvt.f32.u32 s15, s15 // convert 32-bit int in s15 to float in s15 > + vmov r0, s15 // move s15 to result register > bx lr > > Modified: compiler-rt/trunk/lib/arm/gedf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gedf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/gedf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/gedf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__gedf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movge r0, #1 // set result register to 1 if greater than or equal > movlt r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/gesf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/gesf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/gesf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__gesf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movge r0, #1 // set result register to 1 if greater than or equal > movlt r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/gtdf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gtdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/gtdf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/gtdf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__gtdf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movgt r0, #1 // set result register to 1 if equal > movle r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/gtsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/gtsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/gtsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/gtsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__gtsf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movgt r0, #1 // set result register to 1 if equal > movle r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/ledf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ledf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/ledf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/ledf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__ledf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movls r0, #1 // set result register to 1 if equal > movhi r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/lesf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/lesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/lesf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/lesf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__lesf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movls r0, #1 // set result register to 1 if equal > movhi r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/ltdf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ltdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/ltdf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/ltdf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__ltdf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movmi r0, #1 // set result register to 1 if equal > movpl r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/ltsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/ltsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/ltsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/ltsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__ltsf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movmi r0, #1 // set result register to 1 if equal > movpl r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/muldf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/muldf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/muldf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/muldf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Multiplies two double precision floating point numbers using the Darwin > // calling convention where double arguments are passsed in GPR pairs > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__muldf3vfp) > - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 > - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 > - fmuld d6, d6, d7 > - fmrrd r0, r1, d6 // move result back to r0/r1 pair > + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 > + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 > + vmul.f64 d6, d6, d7 > + vmov r0, r1, d6 // move result back to r0/r1 pair > bx lr > > Modified: compiler-rt/trunk/lib/arm/mulsf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/mulsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/mulsf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/mulsf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Multiplies two single precision floating point numbers using the Darwin > // calling convention where single arguments are passsed like 32-bit ints. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__mulsf3vfp) > - fmsr s14, r0 // move first param from r0 into float register > - fmsr s15, r1 // move second param from r1 into float register > - fmuls s13, s14, s15 > - fmrs r0, s13 // move result back to r0 > + vmov s14, r0 // move first param from r0 into float register > + vmov s15, r1 // move second param from r1 into float register > + vmul.f32 s13, s14, s15 > + vmov r0, s13 // move result back to r0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/nedf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/nedf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/nedf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/nedf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__nedf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movne r0, #1 // set result register to 0 if unequal > moveq r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/negdf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/negdf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/negdf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/negdf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,6 +15,7 @@ > // Returns the negation a double precision floating point numbers using the > // Darwin calling convention where double arguments are passsed in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__negdf2vfp) > eor r1, r1, #-2147483648 // flip sign bit on double in r0/r1 pair > > Modified: compiler-rt/trunk/lib/arm/negsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/negsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/negsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/negsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,6 +15,7 @@ > // Returns the negation of a single precision floating point numbers using the > // Darwin calling convention where single arguments are passsed like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__negsf2vfp) > eor r0, r0, #-2147483648 // flip sign bit on float in r0 > > Modified: compiler-rt/trunk/lib/arm/nesf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/nesf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/nesf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/nesf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__nesf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movne r0, #1 // set result register to 1 if unequal > moveq r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/subdf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/subdf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/subdf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/subdf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -15,10 +15,11 @@ > // Returns difference between two double precision floating point numbers using > // the Darwin calling convention where double arguments are passsed in GPR pairs > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__subdf3vfp) > - fmdrr d6, r0, r1 // move first param from r0/r1 pair into d6 > - fmdrr d7, r2, r3 // move second param from r2/r3 pair into d7 > - fsubd d6, d6, d7 > - fmrrd r0, r1, d6 // move result back to r0/r1 pair > + vmov d6, r0, r1 // move first param from r0/r1 pair into d6 > + vmov d7, r2, r3 // move second param from r2/r3 pair into d7 > + vsub.f64 d6, d6, d7 > + vmov r0, r1, d6 // move result back to r0/r1 pair > bx lr > > Modified: compiler-rt/trunk/lib/arm/subsf3vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/subsf3vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/subsf3vfp.S (original) > +++ compiler-rt/trunk/lib/arm/subsf3vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,10 +16,11 @@ > // using the Darwin calling convention where single arguments are passsed > // like 32-bit ints. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__subsf3vfp) > - fmsr s14, r0 // move first param from r0 into float register > - fmsr s15, r1 // move second param from r1 into float register > - fsubs s14, s14, s15 > - fmrs r0, s14 // move result back to r0 > + vmov s14, r0 // move first param from r0 into float register > + vmov s15, r1 // move second param from r1 into float register > + vsub.f32 s14, s14, s15 > + vmov r0, s14 // move result back to r0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/truncdfsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/truncdfsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/truncdfsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/truncdfsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,9 +16,10 @@ > // Uses Darwin calling convention where a double precision parameter is > // passed in a R0/R1 pair and a signle precision result is returned in R0. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__truncdfsf2vfp) > - fmdrr d7, r0, r1 // load double from r0/r1 pair > - fcvtsd s15, d7 // convert double to single (trucate precision) > - fmrs r0, s15 // return result in r0 > + vmov d7, r0, r1 // load double from r0/r1 pair > + vcvt.f32.f64 s15, d7 // convert double to single (trucate precision) > + vmov r0, s15 // return result in r0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/unorddf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/unorddf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/unorddf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/unorddf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where double precision arguments are passsed > // like in GPR pairs. > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__unorddf2vfp) > - fmdrr d6, r0, r1 // load r0/r1 pair in double register > - fmdrr d7, r2, r3 // load r2/r3 pair in double register > - fcmpd d6, d7 > - fmstat > + vmov d6, r0, r1 // load r0/r1 pair in double register > + vmov d7, r2, r3 // load r2/r3 pair in double register > + vcmp.f64 d6, d7 > + vmrs apsr_nzcv, fpscr > movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) > movvc r0, #0 > bx lr > > Modified: compiler-rt/trunk/lib/arm/unordsf2vfp.S > URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/unordsf2vfp.S?rev=138332&r1=138331&r2=138332&view=diff > ============================================================================== > --- compiler-rt/trunk/lib/arm/unordsf2vfp.S (original) > +++ compiler-rt/trunk/lib/arm/unordsf2vfp.S Tue Aug 23 11:40:18 2011 > @@ -16,12 +16,13 @@ > // Uses Darwin calling convention where single precision arguments are passsed > // like 32-bit ints > // > + .syntax unified > .align 2 > DEFINE_COMPILERRT_FUNCTION(__unordsf2vfp) > - fmsr s14, r0 // move from GPR 0 to float register > - fmsr s15, r1 // move from GPR 1 to float register > - fcmps s14, s15 > - fmstat > + vmov s14, r0 // move from GPR 0 to float register > + vmov s15, r1 // move from GPR 1 to float register > + vcmp.f32 s14, s15 > + vmrs apsr_nzcv, fpscr > movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) > movvc r0, #0 > bx lr > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From criswell at uiuc.edu Tue Aug 23 11:46:35 2011 From: criswell at uiuc.edu (John Criswell) Date: Tue, 23 Aug 2011 16:46:35 -0000 Subject: [llvm-commits] [poolalloc] r138333 - /poolalloc/trunk/lib/DSA/DSGraph.cpp Message-ID: <20110823164635.456382A6C12C@llvm.org> Author: criswell Date: Tue Aug 23 11:46:35 2011 New Revision: 138333 URL: http://llvm.org/viewvc/llvm-project?rev=138333&view=rev Log: Improved formatting of some comments for code used to mark DSNodes external. No functionality changes. Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=138333&r1=138332&r2=138333&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Tue Aug 23 11:46:35 2011 @@ -676,8 +676,13 @@ } } -// markExternalNode -- Marks the specified node, and all that's reachable from it, -// as external. Uses 'processedNodes' to track recursion. +// +// Function: markExternalNode() +// +// Description: +// Marks the specified node, and all that's reachable from it, as external. +// It uses 'processedNodes' to track recursion. +// static void markExternalNode(DSNode *N, DenseSet & processedNodes) { // Stop recursion if no node, or if node already processed if (N == 0 || processedNodes.count(N) ) return; @@ -706,8 +711,13 @@ markExternalNode(Call.getPtrArg(i).getNode(), processedNodes); } -// propagateExternal -- Walk the given DSGraph making sure that within this graph -// everything reachable from an already-external node is also marked External. +// +// Method: propagateExternal() +// +// Description: +// Walk the given DSGraph and ensure that, within this graph, +// everything reachable from a node marked External is also marked External. +// static void propagateExternal(DSGraph * G, DenseSet & processedNodes) { DSGraph::node_iterator I = G->node_begin(), E = G->node_end(); @@ -716,7 +726,13 @@ markExternalNode(&*I, processedNodes); } } -// computeIntPtrFlags -- mark all nodes that must get P2 flags due to type overlap + +// +// Method: computeIntPtrFlags() +// +// Description: +// Mark all nodes that must get P2 flags due to type overlap. +// void DSGraph::computeIntPtrFlags() { DSGraph::node_iterator I = node_begin(), E = node_end(); @@ -735,7 +751,8 @@ maskNodeTypes(~DSNode::ExternalNode); } - // Make sure that everything reachable from something already external is also external + // Make sure that everything reachable from something already external is + // also external propagateExternal(this, processedNodes); // If requested, we mark all functions (their formals) in this @@ -789,8 +806,9 @@ shouldBeMarkedExternal |= (*II)->isDeclaration(); } - // If this callsite can call external code, it better be the case that the pointer arguments - // and the return values are all marked external (and what's reachable from them) + // If this callsite can call external code, it better be the case that + // the pointer arguments and the return values are all marked external + // (and what's reachable from them) if (shouldBeMarkedExternal) { markExternal(*I, processedNodes); } From echristo at apple.com Tue Aug 23 11:47:16 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 09:47:16 -0700 Subject: [llvm-commits] [compiler-rt] r138332 - in /compiler-rt/trunk/lib/arm: adddf3vfp.S addsf3vfp.S divdf3vfp.S divsf3vfp.S eqdf2vfp.S eqsf2vfp.S extendsfdf2vfp.S fixdfsivfp.S fixsfsivfp.S fixunsdfsivfp.S fixunssfsivfp.S floatsidfvfp.S floatsisfvfp.S floatunssidfvfp.S floatunssisfvfp.S gedf2vfp.S gesf2vfp.S gtdf2vfp.S gtsf2vfp.S ledf2vfp.S lesf2vfp.S ltdf2vfp.S ltsf2vfp.S muldf3vfp.S mulsf3vfp.S nedf2vfp.S negdf2vfp.S negsf2vfp.S nesf2vfp.S subdf3vfp.S subsf3vfp.S truncdfsf2vfp.S unorddf2vfp.S unordsf2vfp.S In-Reply-To: <20110823164018.CD87F2A6C12C@llvm.org> References: <20110823164018.CD87F2A6C12C@llvm.org> Message-ID: On Aug 23, 2011, at 9:40 AM, Bob Wilson wrote: > Change ARM vfp assembly functions to use unified syntax. Nifty! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/3df92595/attachment.html From krasin at chromium.org Tue Aug 23 11:59:00 2011 From: krasin at chromium.org (Ivan Krasin) Date: Tue, 23 Aug 2011 16:59:00 -0000 Subject: [llvm-commits] [llvm] r138335 - in /llvm/trunk: include/llvm/ADT/Triple.h lib/Support/Triple.cpp Message-ID: <20110823165900.E02042A6C12C@llvm.org> Author: krasin Date: Tue Aug 23 11:59:00 2011 New Revision: 138335 URL: http://llvm.org/viewvc/llvm-project?rev=138335&view=rev Log: This patch adds support of le32 pseudo-cpu that stands for generic 32-bit little-endian CPU. Used by PNaCl and Emscripten. Modified: llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=138335&r1=138334&r2=138335&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Tue Aug 23 11:59:00 2011 @@ -63,6 +63,7 @@ mblaze, // MBlaze: mblaze ptx32, // PTX: ptx (32-bit) ptx64, // PTX: ptx (64-bit) + le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten) InvalidArch }; Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=138335&r1=138334&r2=138335&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Tue Aug 23 11:59:00 2011 @@ -38,6 +38,7 @@ case mblaze: return "mblaze"; case ptx32: return "ptx32"; case ptx64: return "ptx64"; + case le32: return "le32"; } return ""; @@ -72,6 +73,8 @@ case ptx32: return "ptx"; case ptx64: return "ptx"; + + case le32: return "le32"; } } @@ -171,6 +174,8 @@ return ptx32; if (Name == "ptx64") return ptx64; + if (Name == "le32") + return le32; return UnknownArch; } @@ -249,6 +254,8 @@ return "ptx32"; if (Str == "ptx64") return "ptx64"; + if (Str == "le32") + return "le32"; return NULL; } @@ -302,6 +309,8 @@ return ptx32; else if (ArchName == "ptx64") return ptx64; + else if (ArchName == "le32") + return le32; else return UnknownArch; } From krasin at google.com Tue Aug 23 12:00:19 2011 From: krasin at google.com (Ivan Krasin) Date: Tue, 23 Aug 2011 10:00:19 -0700 Subject: [llvm-commits] Add le32 arch support into Triple In-Reply-To: <411672AA-33B4-4B21-8DA0-E066707E6BD1@apple.com> References: <411672AA-33B4-4B21-8DA0-E066707E6BD1@apple.com> Message-ID: Thanks! r138335. On Tue, Aug 23, 2011 at 8:45 AM, Eric Christopher wrote: > > On Aug 23, 2011, at 12:15 AM, Ivan Krasin wrote: > > > > OK. > -eric From resistor at mac.com Tue Aug 23 12:26:35 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Aug 2011 17:26:35 -0000 Subject: [llvm-commits] [llvm] r138336 - /llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110823172635.98A6E2A6C12C@llvm.org> Author: resistor Date: Tue Aug 23 12:26:35 2011 New Revision: 138336 URL: http://llvm.org/viewvc/llvm-project?rev=138336&view=rev Log: Port more assemble tests over to disassembly tests. Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138336&r1=138335&r2=138336&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Tue Aug 23 12:26:35 2011 @@ -284,3 +284,62 @@ 0x23 0x43 +#------------------------------------------------------------------------------ +# POP +#------------------------------------------------------------------------------ +# CHECK: pop {r2, r3, r6} + +0x4c 0xbc + + +#------------------------------------------------------------------------------ +# PUSH +#------------------------------------------------------------------------------ +# CHECK: push {r1, r2, r7} + +0x86 0xb4 + + +#------------------------------------------------------------------------------ +# REV/REV16/REVSH +#------------------------------------------------------------------------------ +# CHECK: rev r6, r3 +# CHECK: rev16 r7, r2 +# CHECK: revsh r5, r1 + +0x1e 0xba +0x57 0xba +0xcd 0xba + + +#------------------------------------------------------------------------------ +# ROR +#------------------------------------------------------------------------------ +# CHECK: rors r2, r7 + +0xfa 0x41 + +#------------------------------------------------------------------------------ +# RSB +#------------------------------------------------------------------------------ +# CHECK: rsbs r1, r3, #0 + +0x59 0x42 + + +#------------------------------------------------------------------------------ +# SBC +#------------------------------------------------------------------------------ +# CHECK: sbcs r4, r3 + +0x9c 0x41 + + +#------------------------------------------------------------------------------ +# SETEND +#------------------------------------------------------------------------------ +# CHECK: setend be +# CHECK: setend le + +0x58 0xb6 +0x50 0xb6 From resistor at mac.com Tue Aug 23 12:37:32 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Aug 2011 17:37:32 -0000 Subject: [llvm-commits] [llvm] r138337 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110823173732.B616E2A6C12C@llvm.org> Author: resistor Date: Tue Aug 23 12:37:32 2011 New Revision: 138337 URL: http://llvm.org/viewvc/llvm-project?rev=138337&view=rev Log: Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138337&r1=138336&r2=138337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 23 12:37:32 2011 @@ -809,9 +809,9 @@ } // register def rr : T2TwoRegCmp< - (outs), (ins GPR:$lhs, rGPR:$rhs), iir, - opc, ".w\t$lhs, $rhs", - [(opnode GPR:$lhs, rGPR:$rhs)]> { + (outs), (ins GPR:$Rn, rGPR:$Rm), iir, + opc, ".w\t$Rn, $Rm", + [(opnode GPR:$Rn, rGPR:$Rm)]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -1001,9 +1001,9 @@ // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. class T2I_ext_rrot_uxtb16 opcod, string opc, PatFrag opnode> - : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), - IIC_iEXTr, opc, "\t$dst, $Rm$rot", - [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, + : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), + IIC_iEXTr, opc, "\t$Rd, $Rm$rot", + [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, Requires<[HasT2ExtractPack, IsThumb2]> { bits<2> rot; let Inst{31-27} = 0b11111; Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138337&r1=138336&r2=138337&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Aug 23 12:37:32 2011 @@ -286,3 +286,9 @@ # CHECK: smlad r5, r12, r8, r11 0x2c 0xfb 0x8 0xb5 + +# CHECK: teq.w r0, r11 +0x90 0xea 0xb 0x8f + +# CHECK: uxtb16 r9, r12, ror #16 +0x3f 0xfa 0xec 0xf9 From grosbach at apple.com Tue Aug 23 12:41:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 17:41:15 -0000 Subject: [llvm-commits] [llvm] r138338 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrThumb.td InstPrinter/ARMInstPrinter.cpp Message-ID: <20110823174115.5248C2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 12:41:15 2011 New Revision: 138338 URL: http://llvm.org/viewvc/llvm-project?rev=138338&view=rev Log: Clean up Thumb load/store multiple definitions. There is no non-writeback store multiple instruction in Thumb1, so don't define one. As a result load multiple is the only instantiation of the multiclass, so refactor that away entirely. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138338&r1=138337&r2=138338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Aug 23 12:41:15 2011 @@ -1930,7 +1930,6 @@ case ARM::STMIB_UPD: case ARM::tLDMIA: case ARM::tLDMIA_UPD: - case ARM::tSTMIA: case ARM::tSTMIA_UPD: case ARM::tPOP_RET: case ARM::tPOP: @@ -2196,7 +2195,6 @@ case ARM::STMDA_UPD: case ARM::STMDB_UPD: case ARM::STMIB_UPD: - case ARM::tSTMIA: case ARM::tSTMIA_UPD: case ARM::tPOP_RET: case ARM::tPOP: Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138338&r1=138337&r2=138338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 23 12:41:15 2011 @@ -694,44 +694,45 @@ // Load / store multiple Instructions. // -multiclass thumb_ldst_mult T1Enc, - bit L_bit, string baseOpc> { - def IA : - T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), - itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>, - T1Encoding { - bits<3> Rn; - bits<8> regs; - let Inst{10-8} = Rn; - let Inst{7-0} = regs; - } - - def IA_UPD : - InstTemplate, - PseudoInstExpansion<(!cast(!strconcat(baseOpc, "IA")) - tGPR:$Rn, pred:$p, reglist:$regs)> { - let Size = 2; - let OutOperandList = (outs GPR:$wb); - let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); - let Pattern = []; - let isCodeGenOnly = 1; - let isPseudo = 1; - list Predicates = [IsThumb]; - } -} - // These require base address to be written back or one of the loaded regs. let neverHasSideEffects = 1 in { let mayLoad = 1, hasExtraDefRegAllocReq = 1 in -defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, - {1,1,0,0,1,?}, 1, "tLDM">; +def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), + IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { + bits<3> Rn; + bits<8> regs; + let Inst{10-8} = Rn; + let Inst{7-0} = regs; +} + +// Writeback version is just a pseudo, as there's no encoding difference. +// Writeback happens iff the base register is not in the destination register +// list. +def tLDMIA_UPD : + InstTemplate, + PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { + let Size = 2; + let OutOperandList = (outs GPR:$wb); + let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); + let Pattern = []; + let isCodeGenOnly = 1; + let isPseudo = 1; + list Predicates = [IsThumb]; +} +// There is no non-writeback version of STM for Thumb. let mayStore = 1, hasExtraSrcRegAllocReq = 1 in -defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, - {1,1,0,0,0,?}, 0, "tSTM">; +def tSTMIA_UPD : T1I<(outs), + (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), + IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>, + T1Encoding<{1,1,0,0,0,?}> { + bits<3> Rn; + bits<8> regs; + let Inst{10-8} = Rn; + let Inst{7-0} = regs; +} } // neverHasSideEffects @@ -739,7 +740,6 @@ (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, Requires<[IsThumb, IsThumb1Only]>; - let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), IIC_iPop, @@ -1147,8 +1147,6 @@ "sub", "\t$Rd, $Rn, $Rm", [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; -// TODO: A7-96: STMIA - store multiple. - // Sign-extend byte def tSXTB : // A8.6.222 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=138338&r1=138337&r2=138338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Aug 23 12:41:15 2011 @@ -146,7 +146,7 @@ return; } - if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) { + if (Opcode == ARM::tLDMIA) { bool Writeback = true; unsigned BaseReg = MI->getOperand(0).getReg(); for (unsigned i = 3; i < MI->getNumOperands(); ++i) { @@ -154,12 +154,7 @@ Writeback = false; } - if (Opcode == ARM::tLDMIA) - O << "\tldm"; - else if (Opcode == ARM::tSTMIA) - O << "\tstm"; - else - llvm_unreachable("Unknown opcode!"); + O << "\tldm"; printPredicateOperand(MI, 1, O); O << '\t' << getRegisterName(BaseReg); From resistor at mac.com Tue Aug 23 12:45:18 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Aug 2011 17:45:18 -0000 Subject: [llvm-commits] [llvm] r138339 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrThumb2.td Disassembler/ARMDisassembler.cpp Message-ID: <20110823174518.3E4702A6C12C@llvm.org> Author: resistor Date: Tue Aug 23 12:45:18 2011 New Revision: 138339 URL: http://llvm.org/viewvc/llvm-project?rev=138339&view=rev Log: Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=138339&r1=138338&r2=138339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Aug 23 12:45:18 2011 @@ -134,7 +134,6 @@ // ARM imod and iflag operands, used only by the CPS instruction. def imod_op : Operand { let PrintMethod = "printCPSIMod"; - let DecoderMethod = "DecodeCPSIMod"; } def ProcIFlagsOperand : AsmOperandClass { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138339&r1=138338&r2=138339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 23 12:45:18 2011 @@ -3100,6 +3100,7 @@ let Inst{8} = M; let Inst{7-5} = iflags; let Inst{4-0} = mode; + let DecoderMethod = "DecodeT2CPSInstruction"; } let M = 1 in Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138339&r1=138338&r2=138339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 23 12:45:18 2011 @@ -103,6 +103,8 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, @@ -179,8 +181,6 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); @@ -1393,6 +1393,47 @@ return S; } +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + unsigned imod = fieldFromInstruction32(Insn, 9, 2); + unsigned M = fieldFromInstruction32(Insn, 8, 1); + unsigned iflags = fieldFromInstruction32(Insn, 5, 3); + unsigned mode = fieldFromInstruction32(Insn, 0, 5); + + DecodeStatus S = Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) CHECK(S, Fail); + + if (imod && M) { + Inst.setOpcode(ARM::t2CPS3p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + Inst.addOperand(MCOperand::CreateImm(mode)); + } else if (imod && !M) { + Inst.setOpcode(ARM::t2CPS2p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + if (mode) CHECK(S, Unpredictable); + } else if (!imod && M) { + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + if (iflags) CHECK(S, Unpredictable); + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + CHECK(S, Unpredictable); + } + + return S; +} + + static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = Success; @@ -3242,10 +3283,3 @@ return S; } -static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - if (Val == 0x1) return Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); - return Success; -} - From nadav.rotem at intel.com Tue Aug 23 12:48:43 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 23 Aug 2011 17:48:43 -0000 Subject: [llvm-commits] [llvm] r138340 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll Message-ID: <20110823174843.4AC282A6C12C@llvm.org> Author: nadav Date: Tue Aug 23 12:48:43 2011 New Revision: 138340 URL: http://llvm.org/viewvc/llvm-project?rev=138340&view=rev Log: Address Duncan's CR request: 1. Cleanup the tests in ConstantFolding.cpp 2. Implement isAllOnes for Constant, ConstantFP, ConstantVector Modified: llvm/trunk/include/llvm/Constant.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=138340&r1=138339&r2=138340&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constant.h (original) +++ llvm/trunk/include/llvm/Constant.h Tue Aug 23 12:48:43 2011 @@ -51,6 +51,9 @@ /// isNullValue - Return true if this is the value that would be returned by /// getNullValue. bool isNullValue() const; + /// isAllOnesValue - Return true if this is the value that would be returned by + /// getAllOnesValue. + bool isAllOnesValue() const; /// isNegativeZeroValue - Return true if the value is what would be returned /// by getZeroValueForNegation. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=138340&r1=138339&r2=138340&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Aug 23 12:48:43 2011 @@ -45,15 +45,9 @@ /// ConstantExpr if unfoldable. static Constant *FoldBitCast(Constant *C, Type *DestTy, const TargetData &TD) { - - ConstantVector *CV = dyn_cast(C); - IntegerType *IntVTy = dyn_cast(DestTy); - // When casting vectors to scalar integers, catch the - // obvious splat cases. - if (IntVTy && CV) { - if (CV->isNullValue()) return ConstantInt::getNullValue(IntVTy); - if (CV->isAllOnesValue()) return ConstantInt::getAllOnesValue(IntVTy); - } + // Catch the obvious splat cases. + if (C->isNullValue()) return Constant::getNullValue(DestTy); + if (C->isAllOnesValue()) return Constant::getAllOnesValue(DestTy); // The code below only handles casts to vectors currently. VectorType *DestVTy = dyn_cast(DestTy); @@ -68,6 +62,7 @@ } // If this is a bitcast from constant vector -> vector, fold it. + ConstantVector *CV = dyn_cast(C); if (CV == 0) return ConstantExpr::getBitCast(C, DestTy); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=138340&r1=138339&r2=138340&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Aug 23 12:48:43 2011 @@ -62,6 +62,21 @@ return isa(this) || isa(this); } +bool Constant::isAllOnesValue() const { + // Check for -1 integers + if (const ConstantInt *CI = dyn_cast(this)) + return CI->isAllOnesValue(); + + // +0.0 is null. + if (const ConstantFP *CFP = dyn_cast(this)) + return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue(); + + // Check for constant vectors + if (const ConstantVector *CV = dyn_cast(this)) + return CV->isAllOnesValue(); + + return false; +} // Constructor to create a '0' constant of arbitrary type... Constant *Constant::getNullValue(Type *Ty) { switch (Ty->getTypeID()) { @@ -126,7 +141,7 @@ SmallVector Elts; VectorType *VTy = cast(Ty); Elts.resize(VTy->getNumElements(), getAllOnesValue(VTy->getElementType())); - assert(Elts[0] && "Not a vector integer type!"); + assert(Elts[0] && "Invalid AllOnes value!"); return cast(ConstantVector::get(Elts)); } @@ -1064,13 +1079,16 @@ // Check out first element. const Constant *Elt = getOperand(0); const ConstantInt *CI = dyn_cast(Elt); - if (!CI || !CI->isAllOnesValue()) return false; + const ConstantFP *CF = dyn_cast(Elt); + // Then make sure all remaining elements point to the same value. for (unsigned I = 1, E = getNumOperands(); I < E; ++I) if (getOperand(I) != Elt) return false; - return true; + // First value is all-ones. + return (CI && CI->isAllOnesValue()) || + (CF && CF->isAllOnesValue()); } /// getSplatValue - If this is a splat constant, where all of the Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast.ll?rev=138340&r1=138339&r2=138340&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bitcast.ll Tue Aug 23 12:48:43 2011 @@ -113,3 +113,27 @@ ; CHECK: @ISPC0 ; CHECK: ret i64 0 } + + +define i64 @Vec2(i64 %in) { + %out = and i64 %in, xor (i64 bitcast (<4 x i16> to i64), i64 0) + ret i64 %out +; CHECK: @Vec2 +; CHECK: ret i64 0 +} + +define i64 @All11(i64 %in) { + %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1) + ret i64 %out +; CHECK: @All11 +; CHECK: ret i64 0 +} + + +define i64 @All111(i32 %in) { + %out = and i32 %in, xor (i64 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) + ret i32 %out +; CHECK: @All11 +; CHECK: ret i32 0 +} + From resistor at mac.com Tue Aug 23 12:51:38 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Aug 2011 17:51:38 -0000 Subject: [llvm-commits] [llvm] r138341 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110823175138.6C22B2A6C12C@llvm.org> Author: resistor Date: Tue Aug 23 12:51:38 2011 New Revision: 138341 URL: http://llvm.org/viewvc/llvm-project?rev=138341&view=rev Log: Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138341&r1=138340&r2=138341&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 23 12:51:38 2011 @@ -2392,9 +2392,15 @@ uint64_t Address, const void *Decoder) { DecodeStatus S = Success; - if (Inst.getOpcode() != ARM::t2PLDs) { - unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + switch (Inst.getOpcode()) { + case ARM::t2PLDs: + case ARM::t2PLDWs: + case ARM::t2PLIs: + break; + default: { + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + } } unsigned Rn = fieldFromInstruction32(Insn, 16, 4); Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138341&r1=138340&r2=138341&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Aug 23 12:51:38 2011 @@ -292,3 +292,6 @@ # CHECK: uxtb16 r9, r12, ror #16 0x3f 0xfa 0xec 0xf9 + +# CHECK: pldw [r11, r12, lsl #2] +0x3b 0xf8 0x2c 0xf0 From nadav.rotem at intel.com Tue Aug 23 12:56:54 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 23 Aug 2011 17:56:54 -0000 Subject: [llvm-commits] [llvm] r138342 - /llvm/trunk/test/Transforms/InstCombine/bitcast.ll Message-ID: <20110823175654.B13162A6C12C@llvm.org> Author: nadav Date: Tue Aug 23 12:56:54 2011 New Revision: 138342 URL: http://llvm.org/viewvc/llvm-project?rev=138342&view=rev Log: Fix a typo in the test from the previous commit. Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast.ll?rev=138342&r1=138341&r2=138342&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bitcast.ll Tue Aug 23 12:56:54 2011 @@ -130,10 +130,10 @@ } -define i64 @All111(i32 %in) { - %out = and i32 %in, xor (i64 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) +define i32 @All111(i32 %in) { + %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) ret i32 %out -; CHECK: @All11 +; CHECK: @All111 ; CHECK: ret i32 0 } From grosbach at apple.com Tue Aug 23 13:13:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:13:05 -0000 Subject: [llvm-commits] [llvm] r138344 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110823181305.2ADB32A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 13:13:04 2011 New Revision: 138344 URL: http://llvm.org/viewvc/llvm-project?rev=138344&view=rev Log: Factor low reg checking into a helper function. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138344&r1=138343&r2=138344&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 23 13:13:04 2011 @@ -3047,6 +3047,24 @@ } // Validate context-sensitive operand constraints. + +// return 'true' if register list contains non-low GPR registers, +// 'false' otherwise. If Reg is in the register list or is HiReg, set +// 'containsReg' to true. +static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, + unsigned HiReg, bool &containsReg) { + containsReg = false; + for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { + unsigned OpReg = Inst.getOperand(i).getReg(); + if (OpReg == Reg) + containsReg = true; + // Anything other than a low register isn't legal here. + if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) + return true; + } + return false; +} + // FIXME: We would really like to be able to tablegen'erate this. bool ARMAsmParser:: validateInstruction(MCInst &Inst, @@ -3101,22 +3119,16 @@ bool hasWritebackToken = (static_cast(Operands[3])->isToken() && static_cast(Operands[3])->getToken() == "!"); - bool doesWriteback = true; - for (unsigned i = 3; i < Inst.getNumOperands(); ++i) { - unsigned Reg = Inst.getOperand(i).getReg(); - if (Reg == Rn) - doesWriteback = false; - // Anything other than a low register isn't legal here. - if (!isARMLowRegister(Reg)) - return Error(Operands[3 + hasWritebackToken]->getStartLoc(), - "registers must be in range r0-r7"); - } + bool listContainsBase; + if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase)) + return Error(Operands[3 + hasWritebackToken]->getStartLoc(), + "registers must be in range r0-r7"); // If we should have writeback, then there should be a '!' token. - if (doesWriteback && !hasWritebackToken) + if (!listContainsBase && !hasWritebackToken) return Error(Operands[2]->getStartLoc(), "writeback operator '!' expected"); // Likewise, if we should not have writeback, there must not be a '!' - if (!doesWriteback && hasWritebackToken) + if (listContainsBase && hasWritebackToken) return Error(Operands[3]->getStartLoc(), "writeback operator '!' not allowed when base register " "in register list"); @@ -3124,23 +3136,17 @@ break; } case ARM::tPOP: { - for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { - unsigned Reg = Inst.getOperand(i).getReg(); - // Anything other than a low register isn't legal here. - if (!isARMLowRegister(Reg) && Reg != ARM::PC) - return Error(Operands[2]->getStartLoc(), - "registers must be in range r0-r7 or pc"); - } + bool listContainsBase; + if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase)) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or pc"); break; } case ARM::tPUSH: { - for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { - unsigned Reg = Inst.getOperand(i).getReg(); - // Anything other than a low register isn't legal here. - if (!isARMLowRegister(Reg) && Reg != ARM::LR) - return Error(Operands[2]->getStartLoc(), - "registers must be in range r0-r7 or lr"); - } + bool listContainsBase; + if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase)) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or lr"); break; } } From chandlerc at gmail.com Tue Aug 23 13:15:49 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 23 Aug 2011 11:15:49 -0700 Subject: [llvm-commits] [llvm] r135760 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt lib/Support/TargetRegistry.cpp lib/Target/CMakeLists.txt lib/Target/TargetRegistry.cpp In-Reply-To: References: <20110722081654.11A932A6C12E@llvm.org> <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> <24FFFF91-D94C-47EE-88A5-EF75658DEC6D@apple.com> <8C219416-76F7-49A8-A569-C3825DD861D6@apple.com> Message-ID: On Sun, Aug 14, 2011 at 12:06 PM, Chandler Carruth wrote: > On Sat, Aug 6, 2011 at 3:28 AM, Chandler Carruth wrote: > >> On Fri, Aug 5, 2011 at 10:40 PM, Chandler Carruth wrote: >> >>> On Mon, Aug 1, 2011 at 3:40 PM, Evan Cheng wrote: >>> >>>> I am not comfortable with a few weeks. Is it not possible to just move >>>> TargetRegistry.cpp back to Support? >>> >>> >>> Putting this into Support violates a lot of layering principles. I care a >>> lot about layering and other invariants, thats how we keep building and >>> using LLVM effectively. >>> >>> Anyways, I understand the need for an expedient solution. I think I have >>> a reasonable compromise -- we could move the registry into MC. The only >>> targets that don't actually need MC are the CBackend and the CppBackend. >>> That seems likely to be the ongoing trend. It would allow MC clients to not >>> pull in any part of Target. >>> >>> Best of all, that's where the other two pieces of the registry already >>> live: the Reloc and CodeModel classes. >>> >>> I'm trying this out now to ensure it actually works, and does in fact >>> shrink llvm-mc back down to size. >>> >> >> I've attached the patch. It looks like it will work. The disassembler (as >> well as many other libraries) no longer depends on Target from my testing. >> This look OK to commit? >> >> I was thinking if it cleans up stuff we could rename this the >> 'MachineRegistry'... but not sure it really matters. >> > > Ping. Adding Eric as he indicated on IRC a week ago he might be able to > review this, but i've not heard anything... > Ping?? ;] I could swear I remember Evan saying this should be fixed quickly.... =D -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/e825350f/attachment.html From grosbach at apple.com Tue Aug 23 13:15:37 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:15:37 -0000 Subject: [llvm-commits] [llvm] r138345 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s Message-ID: <20110823181537.C54022A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 13:15:37 2011 New Revision: 138345 URL: http://llvm.org/viewvc/llvm-project?rev=138345&view=rev Log: Thumb parsing and encoding for STM. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138345&r1=138344&r2=138345&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 23 13:15:37 2011 @@ -3149,6 +3149,13 @@ "registers must be in range r0-r7 or lr"); break; } + case ARM::tSTMIA_UPD: { + bool listContainsBase; + if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase)) + return Error(Operands[4]->getStartLoc(), + "registers must be in range r0-r7"); + break; + } } return false; Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138345&r1=138344&r2=138345&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 13:15:37 2011 @@ -425,3 +425,13 @@ @ CHECK: setend be @ encoding: [0x58,0xb6] @ CHECK: setend le @ encoding: [0x50,0xb6] + + + at ------------------------------------------------------------------------------ +@ STM + at ------------------------------------------------------------------------------ + stm r1!, {r2, r6} + stm r1!, {r1, r2, r3, r7} + +@ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1] +@ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1] Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138345&r1=138344&r2=138345&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug 23 13:15:37 2011 @@ -68,6 +68,15 @@ @ CHECK-ERRORS: ^ +@ Invalid writeback and register lists for STM + stm r1, {r2, r6} + stm r1!, {r2, r9} +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: stm r1, {r2, r6} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: registers must be in range r0-r7 +@ CHECK-ERRORS: stm r1!, {r2, r9} +@ CHECK-ERRORS: ^ @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 From evan.cheng at apple.com Tue Aug 23 13:24:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Aug 2011 11:24:23 -0700 Subject: [llvm-commits] [llvm] r138289 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp In-Reply-To: <3930F884-0000-4570-9945-38C0DA87927F@apple.com> References: <20110822230456.598B52A6C12C@llvm.org> <3930F884-0000-4570-9945-38C0DA87927F@apple.com> Message-ID: The only idea I have is to look for this statistics: "Number of instruction commuting performed". You're right it's hard to add a non-fragile test case so I wouldn't worry about it. Evan On Aug 22, 2011, at 4:25 PM, Jim Grosbach wrote: > Hey Evan, > > Thanks for the fix. I'm open to suggestions on how to create a non-fragile test case for something like this. I can reduce the code that failed because of it easily enough, but that'll be pretty fragile such that changes in either isel or the register allocator would likely perturb it. The failure was detected by the nightly test suite. While not optimal, perhaps that's sufficient? > > -Jim > > > On Aug 22, 2011, at 4:04 PM, Evan Cheng wrote: > >> Author: evancheng >> Date: Mon Aug 22 18:04:56 2011 >> New Revision: 138289 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=138289&view=rev >> Log: >> Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-) >> >> Modified: >> llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp >> >> Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=138289&r1=138288&r2=138289&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) >> +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Aug 22 18:04:56 2011 >> @@ -74,23 +74,25 @@ >> >> assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && >> "This only knows how to commute register operands so far"); >> + unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; >> unsigned Reg1 = MI->getOperand(Idx1).getReg(); >> unsigned Reg2 = MI->getOperand(Idx2).getReg(); >> bool Reg1IsKill = MI->getOperand(Idx1).isKill(); >> bool Reg2IsKill = MI->getOperand(Idx2).isKill(); >> - bool ChangeReg0 = false; >> - if (HasDef && MI->getOperand(0).getReg() == Reg1) { >> - // Must be two address instruction! >> - assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && >> - "Expecting a two-address instruction!"); >> + // If destination is tied to either of the commuted source register, then >> + // it must be updated. >> + if (HasDef && Reg0 == Reg1 && >> + MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { >> Reg2IsKill = false; >> - ChangeReg0 = true; >> + Reg0 = Reg2; >> + } else if (HasDef && Reg0 == Reg2 && >> + MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { >> + Reg1IsKill = false; >> + Reg0 = Reg1; >> } >> >> if (NewMI) { >> // Create a new instruction. >> - unsigned Reg0 = HasDef >> - ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; >> bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; >> MachineFunction &MF = *MI->getParent()->getParent(); >> if (HasDef) >> @@ -104,8 +106,8 @@ >> .addReg(Reg1, getKillRegState(Reg2IsKill)); >> } >> >> - if (ChangeReg0) >> - MI->getOperand(0).setReg(Reg2); >> + if (HasDef) >> + MI->getOperand(0).setReg(Reg0); >> MI->getOperand(Idx2).setReg(Reg1); >> MI->getOperand(Idx1).setReg(Reg2); >> MI->getOperand(Idx2).setIsKill(Reg1IsKill); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rafael.espindola at gmail.com Tue Aug 23 13:26:56 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 23 Aug 2011 18:26:56 -0000 Subject: [llvm-commits] [llvm] r138346 - /llvm/trunk/docs/LangRef.html Message-ID: <20110823182656.B2FE02A6C12C@llvm.org> Author: rafael Date: Tue Aug 23 13:26:56 2011 New Revision: 138346 URL: http://llvm.org/viewvc/llvm-project?rev=138346&view=rev Log: Fix an example in the documentation. Patch by Sanjoy Das! Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=138346&r1=138345&r2=138346&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Aug 23 13:26:56 2011 @@ -7701,7 +7701,7 @@ 
   %tramp = alloca [10 x i8], align 4 ; size and alignment only correct for X86
   %tramp1 = getelementptr [10 x i8]* %tramp, i32 0, i32 0
-  %p = call i8* @llvm.init.trampoline(i8* %tramp1, i8* bitcast (i32 (i8* nest , i32, i32)* @f to i8*), i8* %nval)
+  %p = call i8* @llvm.init.trampoline(i8* %tramp1, i8* bitcast (i32 (i8*, i32, i32)* @f to i8*), i8* %nval)
   %fp = bitcast i8* %p to i32 (i32, i32)*
From grosbach at apple.com Tue Aug 23 13:33:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:33:38 -0000 Subject: [llvm-commits] [llvm] r138347 - in /llvm/trunk/test/MC/ARM: basic-thumb-instructions.s thumb-diagnostics.s Message-ID: <20110823183338.F08B82A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 13:33:38 2011 New Revision: 138347 URL: http://llvm.org/viewvc/llvm-project?rev=138347&view=rev Log: Thumb parsing and encoding for STR. Not including tSTRspi. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138347&r1=138346&r2=138347&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 13:33:38 2011 @@ -435,3 +435,25 @@ @ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1] @ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1] + + + at ------------------------------------------------------------------------------ +@ STR (immediate) + at ------------------------------------------------------------------------------ + str r2, [r7] + str r2, [r7, #0] + str r5, [r1, #4] + str r3, [r7, #124] + +@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] +@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] +@ CHECK: str r5, [r1, #4] @ encoding: [0x4d,0x60] +@ CHECK: str r3, [r7, #124] @ encoding: [0xfb,0x67] + + + at ------------------------------------------------------------------------------ +@ STR (register) + at ------------------------------------------------------------------------------ + str r2, [r7, r3] + +@ CHECK: str r2, [r7, r3] @ encoding: [0xfa,0x50] Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138347&r1=138346&r2=138347&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug 23 13:33:38 2011 @@ -93,3 +93,18 @@ @ CHECK-ERRORS: error: destination register must match source register @ CHECK-ERRORS: muls r1, r2, r3 @ CHECK-ERRORS: ^ + + +@ Out of range immediates for STR instruction. + str r2, [r7, #-1] + str r5, [r1, #3] + str r3, [r7, #128] +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r2, [r7, #-1] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r5, [r1, #3] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r3, [r7, #128] +@ CHECK-ERRORS: ^ From grosbach at apple.com Tue Aug 23 13:39:41 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:39:41 -0000 Subject: [llvm-commits] [llvm] r138348 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823183941.66FB02A6C12D@llvm.org> Author: grosbach Date: Tue Aug 23 13:39:41 2011 New Revision: 138348 URL: http://llvm.org/viewvc/llvm-project?rev=138348&view=rev Log: Thumb parsing and encoding for tSTRspi. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138348&r1=138347&r2=138348&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 23 13:39:41 2011 @@ -194,6 +194,8 @@ // t_addrmode_sp := sp + imm8 * 4 // +// FIXME: This really shouldn't have an explicit SP operand at all. It should +// be implicit, just like in the instruction encoding itself. def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } def t_addrmode_sp : Operand, ComplexPattern { Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138348&r1=138347&r2=138348&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 13:39:41 2011 @@ -444,11 +444,19 @@ str r2, [r7, #0] str r5, [r1, #4] str r3, [r7, #124] + str r2, [sp] + str r3, [sp, #0] + str r4, [sp, #20] + str r5, [sp, #1020] @ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] @ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] @ CHECK: str r5, [r1, #4] @ encoding: [0x4d,0x60] @ CHECK: str r3, [r7, #124] @ encoding: [0xfb,0x67] +@ CHECK: str r2, [sp] @ encoding: [0x00,0x92] +@ CHECK: str r3, [sp] @ encoding: [0x00,0x93] +@ CHECK: str r4, [sp, #20] @ encoding: [0x05,0x94] +@ CHECK: str r5, [sp, #1020] @ encoding: [0xff,0x95] @------------------------------------------------------------------------------ From evan.cheng at apple.com Tue Aug 23 13:43:32 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Aug 2011 11:43:32 -0700 Subject: [llvm-commits] [llvm] r135760 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt lib/Support/TargetRegistry.cpp lib/Target/CMakeLists.txt lib/Target/TargetRegistry.cpp In-Reply-To: References: <20110722081654.11A932A6C12E@llvm.org> <8E0E92A0-3D18-45EB-AB84-51F0B7148DD5@apple.com> <24FFFF91-D94C-47EE-88A5-EF75658DEC6D@apple.com> <8C219416-76F7-49A8-A569-C3825DD861D6@apple.com> Message-ID: Sorry about the late reply. I just got back. On Aug 5, 2011, at 10:40 PM, Chandler Carruth wrote: > On Mon, Aug 1, 2011 at 3:40 PM, Evan Cheng wrote: > I am not comfortable with a few weeks. Is it not possible to just move TargetRegistry.cpp back to Support? > > Putting this into Support violates a lot of layering principles. I care a lot about layering and other invariants, thats how we keep building and using LLVM effectively. What layering principles? TargetRegistry is for tools to use MC and Target components without needing to know the implementation details. IMO it should be in a component that all LLVM clients need to link in, which is support. If you are concerned about TargetRegistry.h including MC/MCCodeGenInfo.h, we can move those enums to eliminate the dependency. > > Anyways, I understand the need for an expedient solution. I think I have a reasonable compromise -- we could move the registry into MC. The only targets that don't actually need MC are the CBackend and the CppBackend. That seems likely to be the ongoing trend. It would allow MC clients to not pull in any part of Target. > > Best of all, that's where the other two pieces of the registry already live: the Reloc and CodeModel classes. > > I'm trying this out now to ensure it actually works, and does in fact shrink llvm-mc back down to size. This is less bad than putting it in Target but I just don't see how TargetRegistry is a MC concept. cc'ing Chris for his input on this. Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/8fb80f62/attachment.html From grosbach at apple.com Tue Aug 23 13:43:06 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:43:06 -0000 Subject: [llvm-commits] [llvm] r138349 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823184306.DE8A02A6C130@llvm.org> Author: grosbach Date: Tue Aug 23 13:43:06 2011 New Revision: 138349 URL: http://llvm.org/viewvc/llvm-project?rev=138349&view=rev Log: Thumb parsing and encoding for STRB. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138349&r1=138348&r2=138349&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 13:43:06 2011 @@ -465,3 +465,23 @@ str r2, [r7, r3] @ CHECK: str r2, [r7, r3] @ encoding: [0xfa,0x50] + + + at ------------------------------------------------------------------------------ +@ STRB (immediate) + at ------------------------------------------------------------------------------ + strb r4, [r3] + strb r5, [r6, #0] + strb r6, [r7, #31] + +@ CHECK: strb r4, [r3] @ encoding: [0x1c,0x70] +@ CHECK: strb r5, [r6] @ encoding: [0x35,0x70] +@ CHECK: strb r6, [r7, #31] @ encoding: [0xfe,0x77] + + + at ------------------------------------------------------------------------------ +@ STRB (register) + at ------------------------------------------------------------------------------ + strb r6, [r4, r5] + +@ CHECK: strb r6, [r4, r5] @ encoding: [0x66,0x55] From supertri at google.com Tue Aug 23 13:49:23 2011 From: supertri at google.com (Caitlin Sadowski) Date: Tue, 23 Aug 2011 18:49:23 -0000 Subject: [llvm-commits] [llvm] r138351 - /llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Message-ID: <20110823184923.DCFCF2A6C130@llvm.org> Author: supertri Date: Tue Aug 23 13:49:23 2011 New Revision: 138351 URL: http://llvm.org/viewvc/llvm-project?rev=138351&view=rev Log: Thread safety: Adding in an option for variadic expr* array of arguments Modified: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Modified: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp?rev=138351&r1=138350&r2=138351&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Tue Aug 23 13:49:23 2011 @@ -489,6 +489,8 @@ Ptr = new SimpleArgument(Arg, Attr, "unsigned"); else if (ArgName == "VariadicUnsignedArgument") Ptr = new VariadicArgument(Arg, Attr, "unsigned"); + else if (ArgName == "VariadicExprArgument") + Ptr = new VariadicArgument(Arg, Attr, "Expr *"); else if (ArgName == "VersionArgument") Ptr = new VersionArgument(Arg, Attr); From grosbach at apple.com Tue Aug 23 13:56:20 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 18:56:20 -0000 Subject: [llvm-commits] [llvm] r138352 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823185620.F09BF2A6C12D@llvm.org> Author: grosbach Date: Tue Aug 23 13:56:20 2011 New Revision: 138352 URL: http://llvm.org/viewvc/llvm-project?rev=138352&view=rev Log: Thumb parsing and encoding for STRH. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138352&r1=138351&r2=138352&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 13:56:20 2011 @@ -485,3 +485,23 @@ strb r6, [r4, r5] @ CHECK: strb r6, [r4, r5] @ encoding: [0x66,0x55] + + + at ------------------------------------------------------------------------------ +@ STRH (immediate) + at ------------------------------------------------------------------------------ + strh r3, [r3] + strh r4, [r6, #2] + strh r5, [r7, #62] + +@ CHECK: strh r3, [r3] @ encoding: [0x1b,0x80] +@ CHECK: strh r4, [r6, #2] @ encoding: [0x74,0x80] +@ CHECK: strh r5, [r7, #62] @ encoding: [0xfd,0x87] + + + at ------------------------------------------------------------------------------ +@ STRH (register) + at ------------------------------------------------------------------------------ + strh r6, [r2, r6] + +@ CHECK: strh r6, [r2, r6] @ encoding: [0x96,0x53] From baldrick at free.fr Tue Aug 23 13:59:39 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 23 Aug 2011 20:59:39 +0200 Subject: [llvm-commits] [llvm] r138340 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll In-Reply-To: <20110823174843.4AC282A6C12C@llvm.org> References: <20110823174843.4AC282A6C12C@llvm.org> Message-ID: <4E53F89B.9070300@free.fr> Hi Nadav, thanks for doing this. > Address Duncan's CR request: > 1. Cleanup the tests in ConstantFolding.cpp > 2. Implement isAllOnes for Constant, ConstantFP, ConstantVector > > > > > Modified: > llvm/trunk/include/llvm/Constant.h > llvm/trunk/lib/Analysis/ConstantFolding.cpp > llvm/trunk/lib/VMCore/Constants.cpp > llvm/trunk/test/Transforms/InstCombine/bitcast.ll > > Modified: llvm/trunk/include/llvm/Constant.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=138340&r1=138339&r2=138340&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Constant.h (original) > +++ llvm/trunk/include/llvm/Constant.h Tue Aug 23 12:48:43 2011 > @@ -51,6 +51,9 @@ > /// isNullValue - Return true if this is the value that would be returned by > /// getNullValue. > bool isNullValue() const; I think there should be a blank line here. > + /// isAllOnesValue - Return true if this is the value that would be returned by > + /// getAllOnesValue. > + bool isAllOnesValue() const; > > /// isNegativeZeroValue - Return true if the value is what would be returned > /// by getZeroValueForNegation. > > Modified: llvm/trunk/lib/VMCore/Constants.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=138340&r1=138339&r2=138340&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Constants.cpp (original) > +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Aug 23 12:48:43 2011 > @@ -62,6 +62,21 @@ > return isa(this) || isa(this); > } > > +bool Constant::isAllOnesValue() const { > + // Check for -1 integers > + if (const ConstantInt *CI = dyn_cast(this)) > + return CI->isAllOnesValue(); I think the ConstantInt version of isAllOnesValue should be removed, and the logic put here instead (like for isNullValue). > + > + // +0.0 is null. This comment doesn't belong here. > + if (const ConstantFP *CFP = dyn_cast(this)) > + return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue(); > + > + // Check for constant vectors > + if (const ConstantVector *CV = dyn_cast(this)) > + return CV->isAllOnesValue(); I think the ConstantVector version of isAllOnesValue should be removed, and the logic put here instead (like for isNullValue). > + > + return false; > +} > // Constructor to create a '0' constant of arbitrary type... > Constant *Constant::getNullValue(Type *Ty) { > switch (Ty->getTypeID()) { > @@ -126,7 +141,7 @@ > SmallVector Elts; > VectorType *VTy = cast(Ty); > Elts.resize(VTy->getNumElements(), getAllOnesValue(VTy->getElementType())); > - assert(Elts[0]&& "Not a vector integer type!"); > + assert(Elts[0]&& "Invalid AllOnes value!"); > return cast(ConstantVector::get(Elts)); > } Please add support for all types, like for getNullValue. Ciao, Duncan. From nicholas at mxc.ca Tue Aug 23 14:01:24 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 23 Aug 2011 19:01:24 -0000 Subject: [llvm-commits] [llvm] r138354 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll Message-ID: <20110823190124.C20882A6C12D@llvm.org> Author: nicholas Date: Tue Aug 23 14:01:24 2011 New Revision: 138354 URL: http://llvm.org/viewvc/llvm-project?rev=138354&view=rev Log: PerformSubCombine to work on integers larger than i128. Fixes a crasher. Added: llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138354&r1=138353&r2=138354&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 23 14:01:24 2011 @@ -13293,20 +13293,18 @@ // X86 can't encode an immediate LHS of a sub. See if we can push the // negation into a preceding instruction. if (ConstantSDNode *C = dyn_cast(Op0)) { - uint64_t Op0C = C->getSExtValue(); - // If the RHS of the sub is a XOR with one use and a constant, invert the // immediate. Then add one to the LHS of the sub so we can turn // X-Y -> X+~Y+1, saving one register. if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && isa(Op1.getOperand(1))) { - uint64_t XorC = cast(Op1.getOperand(1))->getSExtValue(); + APInt XorC = cast(Op1.getOperand(1))->getAPIntValue(); EVT VT = Op0.getValueType(); SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, Op1.getOperand(0), DAG.getConstant(~XorC, VT)); return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, - DAG.getConstant(Op0C+1, VT)); + DAG.getConstant(C->getAPIntValue()+1, VT)); } } Added: llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll?rev=138354&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll Tue Aug 23 14:01:24 2011 @@ -0,0 +1,18 @@ +; RUN: llc -march=x86-64 -O2 < %s + +define void @test(i64 %add127.tr.i2686) { +entry: + %conv143.i2687 = and i64 %add127.tr.i2686, 72057594037927935 + %conv76.i2623 = zext i64 %conv143.i2687 to i128 + %mul148.i2338 = mul i128 0, %conv76.i2623 + %add149.i2339 = add i128 %mul148.i2338, 0 + %add.i2303 = add i128 0, 170141183460469229370468033484042534912 + %add6.i2270 = add i128 %add.i2303, 0 + %sub58.i2271 = sub i128 %add6.i2270, %add149.i2339 + %add71.i2272 = add i128 %sub58.i2271, 0 + %add105.i2273 = add i128 %add71.i2272, 0 + %add116.i2274 = add i128 %add105.i2273, 0 + %shr124.i2277 = lshr i128 %add116.i2274, 56 + %add116.tr.i2280 = trunc i128 %add116.i2274 to i64 + ret void +} From criswell at uiuc.edu Tue Aug 23 14:09:36 2011 From: criswell at uiuc.edu (John Criswell) Date: Tue, 23 Aug 2011 19:09:36 -0000 Subject: [llvm-commits] [poolalloc] r138355 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110823190936.21D512A6C12D@llvm.org> Author: criswell Date: Tue Aug 23 14:09:35 2011 New Revision: 138355 URL: http://llvm.org/viewvc/llvm-project?rev=138355&view=rev Log: Recognize the indirect function call checks added by SAFECode (funccheck() and funccheckui()). Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138355&r1=138354&r2=138355&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Aug 23 14:09:35 2011 @@ -260,6 +260,9 @@ {"poolcheckalign", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheckui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, From evan.cheng at apple.com Tue Aug 23 14:17:21 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Aug 2011 19:17:21 -0000 Subject: [llvm-commits] [llvm] r138356 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20110823191721.4586D2A6C12C@llvm.org> Author: evancheng Date: Tue Aug 23 14:17:21 2011 New Revision: 138356 URL: http://llvm.org/viewvc/llvm-project?rev=138356&view=rev Log: Fix 80 col violations. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=138356&r1=138355&r2=138356&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 23 14:17:21 2011 @@ -5877,9 +5877,11 @@ if (OpInfo.ConstraintVT != Input.ConstraintVT) { std::pair MatchRC = - TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); + TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, + OpInfo.ConstraintVT); std::pair InputRC = - TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); + TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, + Input.ConstraintVT); if ((OpInfo.ConstraintVT.isInteger() != Input.ConstraintVT.isInteger()) || (MatchRC.second != InputRC.second)) { From grosbach at apple.com Tue Aug 23 14:45:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 19:45:45 -0000 Subject: [llvm-commits] [llvm] r138359 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823194545.B1D7C2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 14:45:45 2011 New Revision: 138359 URL: http://llvm.org/viewvc/llvm-project?rev=138359&view=rev Log: Thumb parsing and encoding for SUB. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138359&r1=138358&r2=138359&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 14:45:45 2011 @@ -505,3 +505,31 @@ strh r6, [r2, r6] @ CHECK: strh r6, [r2, r6] @ encoding: [0x96,0x53] + + + at ------------------------------------------------------------------------------ +@ SUB (immediate) + at ------------------------------------------------------------------------------ + subs r1, r2, #3 + subs r2, #3 + subs r2, #8 + +@ CHECK: subs r1, r2, #3 @ encoding: [0xd1,0x1e] +@ CHECK: subs r2, #3 @ encoding: [0x03,0x3a] +@ CHECK: subs r2, #8 @ encoding: [0x08,0x3a] + + + at ------------------------------------------------------------------------------ +@ FIXME: SUB (SP minus immediate) + at ------------------------------------------------------------------------------ + at ------------------------------------------------------------------------------ +@ FIXME: SUB (SP minus register) + at ------------------------------------------------------------------------------ + + + at ------------------------------------------------------------------------------ +@ SUB (register) + at ------------------------------------------------------------------------------ + subs r1, r2, r3 + +@ CHECK: subs r1, r2, r3 @ encoding: [0xd1,0x1a] From grosbach at apple.com Tue Aug 23 14:49:10 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 19:49:10 -0000 Subject: [llvm-commits] [llvm] r138360 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s Message-ID: <20110823194910.C7A222A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 14:49:10 2011 New Revision: 138360 URL: http://llvm.org/viewvc/llvm-project?rev=138360&view=rev Log: Thumb parsing and encoding for SVC. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/test/MC/ARM/basic-thumb-instructions.s llvm/trunk/test/MC/ARM/thumb-diagnostics.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138360&r1=138359&r2=138360&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 23 14:49:10 2011 @@ -534,7 +534,7 @@ } -// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only +// A8.6.218 Supervisor Call (Software Interrupt) // A8.6.16 B: Encoding T1 // If Inst{11-8} == 0b1111 then SEE SVC let isCall = 1, Uses = [SP] in Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138360&r1=138359&r2=138360&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 14:49:10 2011 @@ -533,3 +533,13 @@ subs r1, r2, r3 @ CHECK: subs r1, r2, r3 @ encoding: [0xd1,0x1a] + + + at ------------------------------------------------------------------------------ +@ SVC + at ------------------------------------------------------------------------------ + svc #0 + svc #255 + +@ CHECK: svc #0 @ encoding: [0x00,0xdf] +@ CHECK: svc #255 @ encoding: [0xff,0xdf] Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138360&r1=138359&r2=138360&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Tue Aug 23 14:49:10 2011 @@ -108,3 +108,13 @@ @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled @ CHECK-ERRORS: str r3, [r7, #128] @ CHECK-ERRORS: ^ + +@ Out of range immediate for SVC instruction. + svc #-1 + svc #256 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: svc #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: svc #256 +@ CHECK-ERRORS: ^ From grosbach at apple.com Tue Aug 23 14:51:42 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 19:51:42 -0000 Subject: [llvm-commits] [llvm] r138361 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823195142.AEAFB2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 14:51:42 2011 New Revision: 138361 URL: http://llvm.org/viewvc/llvm-project?rev=138361&view=rev Log: Thumb parsing and encoding for SXTB and SXTH. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138361&r1=138360&r2=138361&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 14:51:42 2011 @@ -543,3 +543,13 @@ @ CHECK: svc #0 @ encoding: [0x00,0xdf] @ CHECK: svc #255 @ encoding: [0xff,0xdf] + + + at ------------------------------------------------------------------------------ +@ SXTB/SXTH + at ------------------------------------------------------------------------------ + sxtb r3, r5 + sxth r3, r5 + +@ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2] +@ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2] From grosbach at apple.com Tue Aug 23 14:53:17 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 19:53:17 -0000 Subject: [llvm-commits] [llvm] r138362 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823195317.C3B932A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 14:53:17 2011 New Revision: 138362 URL: http://llvm.org/viewvc/llvm-project?rev=138362&view=rev Log: Thumb parsing and encoding for TST. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138362&r1=138361&r2=138362&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 14:53:17 2011 @@ -553,3 +553,11 @@ @ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2] @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2] + + + at ------------------------------------------------------------------------------ +@ TST + at ------------------------------------------------------------------------------ + tst r6, r1 + +@ CHECK: tst r6, r1 @ encoding: [0x0e,0x42] From grosbach at apple.com Tue Aug 23 14:59:32 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 19:59:32 -0000 Subject: [llvm-commits] [llvm] r138363 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823195932.3491E2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 14:59:32 2011 New Revision: 138363 URL: http://llvm.org/viewvc/llvm-project?rev=138363&view=rev Log: Thumb parsing and encoding for UXTB and UXTH. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138363&r1=138362&r2=138363&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 14:59:32 2011 @@ -561,3 +561,13 @@ tst r6, r1 @ CHECK: tst r6, r1 @ encoding: [0x0e,0x42] + + + at ------------------------------------------------------------------------------ +@ UXTB/UXTH + at ------------------------------------------------------------------------------ + uxtb r7, r2 + uxth r1, r4 + +@ CHECK: uxtb r7, r2 @ encoding: [0xd7,0xb2] +@ CHECK: uxth r1, r4 @ encoding: [0xa1,0xb2] From grosbach at apple.com Tue Aug 23 15:02:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 20:02:30 -0000 Subject: [llvm-commits] [llvm] r138364 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110823200230.8A2772A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 15:02:30 2011 New Revision: 138364 URL: http://llvm.org/viewvc/llvm-project?rev=138364&view=rev Log: Thumb parsing and encoding for WFE, WFI and YIELD. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138364&r1=138363&r2=138364&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 23 15:02:30 2011 @@ -571,3 +571,15 @@ @ CHECK: uxtb r7, r2 @ encoding: [0xd7,0xb2] @ CHECK: uxth r1, r4 @ encoding: [0xa1,0xb2] + + + at ------------------------------------------------------------------------------ +@ WFE/WFI/YIELD + at ------------------------------------------------------------------------------ + wfe + wfi + yield + +@ CHECK: wfe @ encoding: [0x20,0xbf] +@ CHECK: wfi @ encoding: [0x30,0xbf] +@ CHECK: yield @ encoding: [0x10,0xbf] From echristo at apple.com Tue Aug 23 15:11:10 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 20:11:10 -0000 Subject: [llvm-commits] [llvm] r138366 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll Message-ID: <20110823201110.8C91D2A6C12C@llvm.org> Author: echristo Date: Tue Aug 23 15:11:10 2011 New Revision: 138366 URL: http://llvm.org/viewvc/llvm-project?rev=138366&view=rev Log: Revert "Address Duncan's CR request:" This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340) Conflicts: test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constant.h (original) +++ llvm/trunk/include/llvm/Constant.h Tue Aug 23 15:11:10 2011 @@ -51,9 +51,6 @@ /// isNullValue - Return true if this is the value that would be returned by /// getNullValue. bool isNullValue() const; - /// isAllOnesValue - Return true if this is the value that would be returned by - /// getAllOnesValue. - bool isAllOnesValue() const; /// isNegativeZeroValue - Return true if the value is what would be returned /// by getZeroValueForNegation. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Aug 23 15:11:10 2011 @@ -45,9 +45,15 @@ /// ConstantExpr if unfoldable. static Constant *FoldBitCast(Constant *C, Type *DestTy, const TargetData &TD) { - // Catch the obvious splat cases. - if (C->isNullValue()) return Constant::getNullValue(DestTy); - if (C->isAllOnesValue()) return Constant::getAllOnesValue(DestTy); + + ConstantVector *CV = dyn_cast(C); + IntegerType *IntVTy = dyn_cast(DestTy); + // When casting vectors to scalar integers, catch the + // obvious splat cases. + if (IntVTy && CV) { + if (CV->isNullValue()) return ConstantInt::getNullValue(IntVTy); + if (CV->isAllOnesValue()) return ConstantInt::getAllOnesValue(IntVTy); + } // The code below only handles casts to vectors currently. VectorType *DestVTy = dyn_cast(DestTy); @@ -62,7 +68,6 @@ } // If this is a bitcast from constant vector -> vector, fold it. - ConstantVector *CV = dyn_cast(C); if (CV == 0) return ConstantExpr::getBitCast(C, DestTy); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Aug 23 15:11:10 2011 @@ -62,21 +62,6 @@ return isa(this) || isa(this); } -bool Constant::isAllOnesValue() const { - // Check for -1 integers - if (const ConstantInt *CI = dyn_cast(this)) - return CI->isAllOnesValue(); - - // +0.0 is null. - if (const ConstantFP *CFP = dyn_cast(this)) - return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue(); - - // Check for constant vectors - if (const ConstantVector *CV = dyn_cast(this)) - return CV->isAllOnesValue(); - - return false; -} // Constructor to create a '0' constant of arbitrary type... Constant *Constant::getNullValue(Type *Ty) { switch (Ty->getTypeID()) { @@ -141,7 +126,7 @@ SmallVector Elts; VectorType *VTy = cast(Ty); Elts.resize(VTy->getNumElements(), getAllOnesValue(VTy->getElementType())); - assert(Elts[0] && "Invalid AllOnes value!"); + assert(Elts[0] && "Not a vector integer type!"); return cast(ConstantVector::get(Elts)); } @@ -1079,16 +1064,13 @@ // Check out first element. const Constant *Elt = getOperand(0); const ConstantInt *CI = dyn_cast(Elt); - const ConstantFP *CF = dyn_cast(Elt); - + if (!CI || !CI->isAllOnesValue()) return false; // Then make sure all remaining elements point to the same value. for (unsigned I = 1, E = getNumOperands(); I < E; ++I) if (getOperand(I) != Elt) return false; - // First value is all-ones. - return (CI && CI->isAllOnesValue()) || - (CF && CF->isAllOnesValue()); + return true; } /// getSplatValue - If this is a splat constant, where all of the Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast.ll?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bitcast.ll Tue Aug 23 15:11:10 2011 @@ -11,7 +11,7 @@ %t3 = xor <2 x i32> %t1, %t2 %t4 = extractelement <2 x i32> %t3, i32 0 ret i32 %t4 - + ; CHECK: @test1 ; CHECK: ret i32 0 } @@ -30,7 +30,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test2 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 0 ; CHECK-NEXT: bitcast <2 x i32> %B to <2 x float> @@ -55,7 +55,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test3 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 1 ; CHECK-NEXT: bitcast <2 x i64> %B to <4 x float> @@ -75,7 +75,7 @@ ; CHECK: @test4 ; CHECK-NEXT: insertelement <2 x i32> undef, i32 %A, i32 0 ; CHECK-NEXT: insertelement <2 x i32> {{.*}}, i32 %B, i32 1 - ; CHECK-NEXT: ret <2 x i32> + ; CHECK-NEXT: ret <2 x i32> } @@ -92,7 +92,7 @@ ; CHECK: @test5 ; CHECK-NEXT: insertelement <2 x float> undef, float %A, i32 0 ; CHECK-NEXT: insertelement <2 x float> {{.*}}, float %B, i32 1 - ; CHECK-NEXT: ret <2 x float> + ; CHECK-NEXT: ret <2 x float> } define <2 x float> @test6(float %A){ @@ -113,27 +113,3 @@ ; CHECK: @ISPC0 ; CHECK: ret i64 0 } - - -define i64 @Vec2(i64 %in) { - %out = and i64 %in, xor (i64 bitcast (<4 x i16> to i64), i64 0) - ret i64 %out -; CHECK: @Vec2 -; CHECK: ret i64 0 -} - -define i64 @All11(i64 %in) { - %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1) - ret i64 %out -; CHECK: @All11 -; CHECK: ret i64 0 -} - - -define i32 @All111(i32 %in) { - %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) - ret i32 %out -; CHECK: @All111 -; CHECK: ret i32 0 -} - From echristo at apple.com Tue Aug 23 15:13:04 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 13:13:04 -0700 Subject: [llvm-commits] [llvm] r138340 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll In-Reply-To: <20110823174843.4AC282A6C12C@llvm.org> References: <20110823174843.4AC282A6C12C@llvm.org> Message-ID: <090788E6-A909-4E7B-8F39-C70C33CD6CD6@apple.com> On Aug 23, 2011, at 10:48 AM, Nadav Rotem wrote: > Author: nadav > Date: Tue Aug 23 12:48:43 2011 > New Revision: 138340 > > URL: http://llvm.org/viewvc/llvm-project?rev=138340&view=rev > Log: > Address Duncan's CR request: > 1. Cleanup the tests in ConstantFolding.cpp > 2. Implement isAllOnes for Constant, ConstantFP, ConstantVector > > This broke the clang bots for the CodeGen/vector.c test - it was hitting an assert. I've reverted it for now. -eric From evan.cheng at apple.com Tue Aug 23 15:15:22 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Aug 2011 20:15:22 -0000 Subject: [llvm-commits] [llvm] r138367 - in /llvm/trunk: include/llvm/MC/ include/llvm/Support/ include/llvm/Target/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/MCTargetDesc/ lib/Target/Blackfin/MCTargetDesc/ lib/Target/CellSPU/MCTargetDesc/ lib/Target/MBlaze/MCTargetDesc/ lib/Target/MSP430/MCTargetDesc/ lib/Target/Mips/MCTargetDesc/ lib/Target/PTX/MCTargetDesc/ lib/Target/PowerPC/MCTargetDesc/ lib/Target/Sparc/MCTargetDesc/ lib/Target/SystemZ/MCTargetDesc/ lib/Target/X86/MCTargetDesc/ lib/Target/XCo... Message-ID: <20110823201522.433C02A6C12C@llvm.org> Author: evancheng Date: Tue Aug 23 15:15:21 2011 New Revision: 138367 URL: http://llvm.org/viewvc/llvm-project?rev=138367&view=rev Log: Some refactoring so TargetRegistry.h no longer has to include any files from MC. Added: llvm/trunk/include/llvm/Support/CodeGen.h Modified: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h llvm/trunk/include/llvm/MC/MCInstrAnalysis.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeGenInfo.h?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCCodeGenInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCCodeGenInfo.h Tue Aug 23 15:15:21 2011 @@ -15,17 +15,9 @@ #ifndef LLVM_MC_MCCODEGENINFO_H #define LLVM_MC_MCCODEGENINFO_H -namespace llvm { +#include "llvm/Support/CodeGen.h" - // Relocation model types. - namespace Reloc { - enum Model { Default, Static, PIC_, DynamicNoPIC }; - } - - // Code model types. - namespace CodeModel { - enum Model { Default, JITDefault, Small, Kernel, Medium, Large }; - } +namespace llvm { class MCCodeGenInfo { /// RelocationModel - Relocation model: statcic, pic, etc. Modified: llvm/trunk/include/llvm/MC/MCInstrAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrAnalysis.h?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrAnalysis.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Tue Aug 23 15:15:21 2011 @@ -23,8 +23,9 @@ friend class Target; const MCInstrInfo *Info; - MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {} public: + MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {} + virtual ~MCInstrAnalysis() {} virtual bool isBranch(const MCInst &Inst) const { Added: llvm/trunk/include/llvm/Support/CodeGen.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CodeGen.h?rev=138367&view=auto ============================================================================== --- llvm/trunk/include/llvm/Support/CodeGen.h (added) +++ llvm/trunk/include/llvm/Support/CodeGen.h Tue Aug 23 15:15:21 2011 @@ -0,0 +1,32 @@ +//===-- llvm/Support/CodeGen.h - CodeGen Concepts ---------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file define some types which define code generation concepts. For +// example, relocation model. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_CODEGEN_H +#define LLVM_SUPPORT_CODEGEN_H + +namespace llvm { + + // Relocation model types. + namespace Reloc { + enum Model { Default, Static, PIC_, DynamicNoPIC }; + } + + // Code model types. + namespace CodeModel { + enum Model { Default, JITDefault, Small, Kernel, Medium, Large }; + } + +} // end llvm namespace + +#endif Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Tue Aug 23 15:15:21 2011 @@ -19,8 +19,7 @@ #ifndef LLVM_TARGET_TARGETREGISTRY_H #define LLVM_TARGET_TARGETREGISTRY_H -#include "llvm/MC/MCCodeGenInfo.h" -#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/Support/CodeGen.h" #include "llvm/ADT/Triple.h" #include #include @@ -36,6 +35,7 @@ class MCCodeGenInfo; class MCContext; class MCDisassembler; + class MCInstrAnalysis; class MCInstPrinter; class MCInstrInfo; class MCRegisterInfo; @@ -291,7 +291,7 @@ /// MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const { if (!MCInstrAnalysisCtorFn) - return new MCInstrAnalysis(Info); + return 0; return MCInstrAnalysisCtorFn(Info); } @@ -890,6 +890,39 @@ } }; + /// RegisterMCInstrAnalysis - Helper template for registering a target + /// instruction analyzer implementation. This invokes the static "Create" + /// method on the class to actually do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCInstrAnalysis X(TheFooTarget); + /// } + template + struct RegisterMCInstrAnalysis { + RegisterMCInstrAnalysis(Target &T) { + TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator); + } + private: + static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) { + return new MCInstrAnalysisImpl(Info); + } + }; + + /// RegisterMCInstrAnalysisFn - Helper template for registering a target + /// instruction analyzer implementation. This invokes the specified function + /// to do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCInstrAnalysisFn X(TheFooTarget, TheFunction); + /// } + struct RegisterMCInstrAnalysisFn { + RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) { + TargetRegistry::RegisterMCInstrAnalysis(T, Fn); + } + }; + /// RegisterMCRegInfo - Helper template for registering a target register info /// implementation. This invokes the static "Create" method on the class to /// actually do the construction. Usage: Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Aug 23 15:15:21 2011 @@ -18,6 +18,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -15,6 +15,8 @@ #include "ARMMCAsmInfo.h" #include "ARMBaseInfo.h" #include "InstPrinter/ARMInstPrinter.h" +#include "llvm/MC/MCCodeGenInfo.h" +#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -216,17 +218,18 @@ TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); - TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget, - createARMMCInstrAnalysis); - TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget, - createARMMCInstrAnalysis); - // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, ARM_MC::createARMMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, ARM_MC::createARMMCSubtargetInfo); + // Register the MC instruction analyzer. + TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget, + createARMMCInstrAnalysis); + TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget, + createARMMCInstrAnalysis); + // Register the MC Code Emitter TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); Modified: llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "AlphaMCTargetDesc.h" #include "AlphaMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "BlackfinMCTargetDesc.h" #include "BlackfinMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -14,6 +14,7 @@ #include "SPUMCTargetDesc.h" #include "SPUMCAsmInfo.h" #include "llvm/MC/MachineLocation.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -14,6 +14,7 @@ #include "MBlazeMCTargetDesc.h" #include "MBlazeMCAsmInfo.h" #include "InstPrinter/MBlazeInstPrinter.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -14,6 +14,7 @@ #include "MSP430MCTargetDesc.h" #include "MSP430MCAsmInfo.h" #include "InstPrinter/MSP430InstPrinter.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -15,6 +15,7 @@ #include "MipsMCAsmInfo.h" #include "InstPrinter/MipsInstPrinter.h" #include "llvm/MC/MachineLocation.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "PTXMCTargetDesc.h" #include "PTXMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -15,6 +15,7 @@ #include "PPCMCAsmInfo.h" #include "InstPrinter/PPCInstPrinter.h" #include "llvm/MC/MachineLocation.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "SparcMCTargetDesc.h" #include "SparcMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "SystemZMCTargetDesc.h" #include "SystemZMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -16,6 +16,8 @@ #include "InstPrinter/X86ATTInstPrinter.h" #include "InstPrinter/X86IntelInstPrinter.h" #include "llvm/MC/MachineLocation.h" +#include "llvm/MC/MCCodeGenInfo.h" +#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -393,6 +395,10 @@ return 0; } +static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { + return new MCInstrAnalysis(Info); +} + // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { // Register the MC asm info. @@ -417,6 +423,12 @@ TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, X86_MC::createX86MCSubtargetInfo); + // Register the MC instruction analyzer. + TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target, + createX86MCInstrAnalysis); + TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target, + createX86MCInstrAnalysis); + // Register the code emitter. TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, createX86MCCodeEmitter); Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Tue Aug 23 15:15:21 2011 @@ -13,6 +13,7 @@ #include "XCoreMCTargetDesc.h" #include "XCoreMCAsmInfo.h" +#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=138367&r1=138366&r2=138367&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Aug 23 15:15:21 2011 @@ -22,6 +22,7 @@ #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/Support/CommandLine.h" From natebegeman at mac.com Tue Aug 23 15:27:46 2011 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 23 Aug 2011 20:27:46 -0000 Subject: [llvm-commits] [llvm] r138371 - in /llvm/trunk: include/llvm-c/Core.h lib/VMCore/Core.cpp Message-ID: <20110823202746.70B5C2A6C12C@llvm.org> Author: sampo Date: Tue Aug 23 15:27:46 2011 New Revision: 138371 URL: http://llvm.org/viewvc/llvm-project?rev=138371&view=rev Log: Add some useful accessors to c++ api that appear to be missing from the c api Modified: llvm/trunk/include/llvm-c/Core.h llvm/trunk/lib/VMCore/Core.cpp Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=138371&r1=138370&r2=138371&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Tue Aug 23 15:27:46 2011 @@ -744,6 +744,7 @@ LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val); LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val); LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB); +LLVMValueRef LLVMGetBasicBlockTerminator(LLVMBasicBlockRef BB); unsigned LLVMCountBasicBlocks(LLVMValueRef Fn); void LLVMGetBasicBlocks(LLVMValueRef Fn, LLVMBasicBlockRef *BasicBlocks); LLVMBasicBlockRef LLVMGetFirstBasicBlock(LLVMValueRef Fn); @@ -763,14 +764,16 @@ LLVMBasicBlockRef LLVMInsertBasicBlock(LLVMBasicBlockRef InsertBeforeBB, const char *Name); void LLVMDeleteBasicBlock(LLVMBasicBlockRef BB); +void LLVMRemoveBasicBlockFromParent(LLVMBasicBlockRef BB); void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos); void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos); -/* Operations on instructions */ -LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst); LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB); LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB); + +/* Operations on instructions */ +LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst); LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst); LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst); @@ -787,6 +790,9 @@ LLVMBool LLVMIsTailCall(LLVMValueRef CallInst); void LLVMSetTailCall(LLVMValueRef CallInst, LLVMBool IsTailCall); +/* Operations on switch instructions (only) */ +LLVMBasicBlockRef LLVMGetSwitchDefaultDest(LLVMValueRef SwitchInstr); + /* Operations on phi nodes */ void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues, LLVMBasicBlockRef *IncomingBlocks, unsigned Count); Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=138371&r1=138370&r2=138371&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Tue Aug 23 15:27:46 2011 @@ -1382,6 +1382,10 @@ return wrap(unwrap(BB)->getParent()); } +LLVMValueRef LLVMGetBasicBlockTerminator(LLVMBasicBlockRef BB) { + return wrap(unwrap(BB)->getTerminator()); +} + unsigned LLVMCountBasicBlocks(LLVMValueRef FnRef) { return unwrap(FnRef)->size(); } @@ -1454,6 +1458,10 @@ unwrap(BBRef)->eraseFromParent(); } +void LLVMRemoveBasicBlockFromParent(LLVMBasicBlockRef BBRef) { + unwrap(BBRef)->removeFromParent(); +} + void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos) { unwrap(BB)->moveBefore(unwrap(MovePos)); } @@ -1553,6 +1561,12 @@ unwrap(Call)->setTailCall(isTailCall); } +/*--.. Operations on switch instructions (only) ............................--*/ + +LLVMBasicBlockRef LLVMGetSwitchDefaultDest(LLVMValueRef Switch) { + return wrap(unwrap(Switch)->getDefaultDest()); +} + /*--.. Operations on phi nodes .............................................--*/ void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues, From grosbach at apple.com Tue Aug 23 15:53:08 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 20:53:08 -0000 Subject: [llvm-commits] [llvm] r138373 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20110823205308.BA4B52A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 15:53:08 2011 New Revision: 138373 URL: http://llvm.org/viewvc/llvm-project?rev=138373&view=rev Log: [SU]XT[BH] are only available on ARMv6 and up. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=138373&r1=138372&r2=138373&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Aug 23 15:53:08 2011 @@ -2002,12 +2002,14 @@ switch (SrcVT.getSimpleVT().SimpleTy) { default: return false; case MVT::i16: + if (!Subtarget->hasV6Ops()) return false; if (isZext) Opc = isThumb ? ARM::t2UXTH : ARM::UXTH; else Opc = isThumb ? ARM::t2SXTH : ARM::SXTH; break; case MVT::i8: + if (!Subtarget->hasV6Ops()) return false; if (isZext) Opc = isThumb ? ARM::t2UXTB : ARM::UXTB; else From echristo at apple.com Tue Aug 23 15:59:46 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 13:59:46 -0700 Subject: [llvm-commits] [llvm] r138373 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <20110823205308.BA4B52A6C12C@llvm.org> References: <20110823205308.BA4B52A6C12C@llvm.org> Message-ID: <2D71E186-A3BF-45D0-BD7F-96AAA388F13A@apple.com> On Aug 23, 2011, at 1:53 PM, Jim Grosbach wrote: > Author: grosbach > Date: Tue Aug 23 15:53:08 2011 > New Revision: 138373 > > URL: http://llvm.org/viewvc/llvm-project?rev=138373&view=rev > Log: > [SU]XT[BH] are only available on ARMv6 and up. > Hmm.. the pass probably makes this assumption in more places. Might be worth just making the whole thing conditional on that. Right now it's conditional on darwin which I think implies that anyhow (by default). -eric From grosbach at apple.com Tue Aug 23 16:04:57 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 14:04:57 -0700 Subject: [llvm-commits] [llvm] r138373 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <2D71E186-A3BF-45D0-BD7F-96AAA388F13A@apple.com> References: <20110823205308.BA4B52A6C12C@llvm.org> <2D71E186-A3BF-45D0-BD7F-96AAA388F13A@apple.com> Message-ID: <0818F1DC-9A48-4286-8867-817953002CFD@apple.com> On Aug 23, 2011, at 1:59 PM, Eric Christopher wrote: > > On Aug 23, 2011, at 1:53 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Tue Aug 23 15:53:08 2011 >> New Revision: 138373 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=138373&view=rev >> Log: >> [SU]XT[BH] are only available on ARMv6 and up. >> > > Hmm.. the pass probably makes this assumption in more places. Might be worth just making the whole thing conditional on that. Right now it's conditional on darwin which I think implies that anyhow (by default). That's just a little bit bigger hammer than I was wanting to swing for this. I'm totally OK with it if you think that's the best solution, though. -jim From echristo at apple.com Tue Aug 23 16:12:01 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Aug 2011 14:12:01 -0700 Subject: [llvm-commits] [llvm] r138373 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <0818F1DC-9A48-4286-8867-817953002CFD@apple.com> References: <20110823205308.BA4B52A6C12C@llvm.org> <2D71E186-A3BF-45D0-BD7F-96AAA388F13A@apple.com> <0818F1DC-9A48-4286-8867-817953002CFD@apple.com> Message-ID: On Aug 23, 2011, at 2:04 PM, Jim Grosbach wrote: > > On Aug 23, 2011, at 1:59 PM, Eric Christopher wrote: > >> >> On Aug 23, 2011, at 1:53 PM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Tue Aug 23 15:53:08 2011 >>> New Revision: 138373 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=138373&view=rev >>> Log: >>> [SU]XT[BH] are only available on ARMv6 and up. >>> >> >> Hmm.. the pass probably makes this assumption in more places. Might be worth just making the whole thing conditional on that. Right now it's conditional on darwin which I think implies that anyhow (by default). > > That's just a little bit bigger hammer than I was wanting to swing for this. I'm totally OK with it if you think that's the best solution, though. Hmm.. well, the code is pretty untested on processors that don't support armv6, then again most of the arm port is untested on processors that don't support armv6. Six of one? -eric From grosbach at apple.com Tue Aug 23 16:32:34 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 23 Aug 2011 21:32:34 -0000 Subject: [llvm-commits] [llvm] r138386 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20110823213234.5D3952A6C12C@llvm.org> Author: grosbach Date: Tue Aug 23 16:32:34 2011 New Revision: 138386 URL: http://llvm.org/viewvc/llvm-project?rev=138386&view=rev Log: Move ARM frame-unwinding EHABI handling a touch earlier. It should go before AsmPrinter MC pseudo expansion since it's based on MachineInstr, not MCInst. Otherwise any frame related pseudo instructions may be missed. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=138386&r1=138385&r2=138386&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Aug 23 16:32:34 2011 @@ -1151,6 +1151,10 @@ #include "ARMGenMCPseudoLowering.inc" void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { + // Emit unwinding stuff for frame-related instructions + if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup)) + EmitUnwindingInstruction(MI); + // Do any auto-generated pseudo lowerings. if (emitPseudoExpansionLowering(OutStreamer, MI)) return; @@ -1881,10 +1885,6 @@ MCInst TmpInst; LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - // Emit unwinding stuff for frame-related instructions - if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup)) - EmitUnwindingInstruction(MI); - OutStreamer.EmitInstruction(TmpInst); } From isanbard at gmail.com Tue Aug 23 16:33:05 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Aug 2011 21:33:05 -0000 Subject: [llvm-commits] [llvm] r138387 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20110823213305.9D23C2A6C12C@llvm.org> Author: void Date: Tue Aug 23 16:33:05 2011 New Revision: 138387 URL: http://llvm.org/viewvc/llvm-project?rev=138387&view=rev Log: A landingpad instruction is neither folded nor dead. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=138387&r1=138386&r2=138387&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 23 16:33:05 2011 @@ -808,6 +808,7 @@ return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. !isa(I) && // Terminators aren't folded. !isa(I) && // Debug instructions aren't folded. + !isa(I) && // Landingpad instructions aren't folded. !FuncInfo->isExportedInst(I); // Exported instrs must be computed. } From respindola at mozilla.com Tue Aug 23 16:35:13 2011 From: respindola at mozilla.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 23 Aug 2011 17:35:13 -0400 Subject: [llvm-commits] [patch] Delete the old IL level tail duplicator Message-ID: <4E541D11.7060300@mozilla.com> The old tail duplicator doesn't use the ssa updater and therefore has to run really early in the pipeline. I have tried creating a new one, but don't have the time to finish it right now. In any case, we haven't run the existing one for some time and should probably delete it. Is the attached patch OK? Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: tail.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/ab96c5f3/attachment.pl From rafael.espindola at gmail.com Tue Aug 23 16:37:36 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 23 Aug 2011 17:37:36 -0400 Subject: [llvm-commits] [patch] Delete the old IL level tail duplicator Message-ID: <4E541DA0.9030006@gmail.com> The old tail duplicator doesn't use the ssa updater and therefore has to run really early in the pipeline. I have tried creating a new one, but don't have the time to finish it right now. In any case, we haven't run the existing one for some time and should probably delete it. Is the attached patch OK? Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: tail.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/43cefdf8/attachment.pl From aaron at aaronballman.com Tue Aug 23 17:03:15 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Tue, 23 Aug 2011 17:03:15 -0500 Subject: [llvm-commits] [llvm] r138213 - /llvm/trunk/lib/Support/Windows/PathV2.inc In-Reply-To: References: <20110820213638.9E0D52A6C12C@llvm.org> Message-ID: On Mon, Aug 22, 2011 at 10:39 PM, NAKAMURA Takumi wrote: >>> Nitpick: Shall we handle "x:\path\to\com9.txt" here? >> >> I could certainly add that. ?Do we link against shlwapi.lib (available >> in Win2k and higher) so that I can use PathFindFileName? ?Or should I >> prefer our filename function from PathV2.cpp (this one only worries me >> in case we accidentally run into infinite loops at some point)? > > I think it would be enough to use PathV2 itself to parse path. Using > shell api might be overkill (and useless). > Note: "x:\path\to\com9.txt" is mapped to the device namespace. I've attached a patch to address this so that we now use the path "stem" to do the comparison. This means we'll catch DOS device names like "com9" as well as ill-named compete paths like x:\path\to\com9.txt. Additionally, I addressed your suggestion about the static declaration using array notation instead of pointer notation. However, I'd be curious to hear why you have this preference (you could email me off-list if you'd prefer). Thanks! ~Aaron -------------- next part -------------- A non-text attachment was scrubbed... Name: PathV2.diff Type: application/octet-stream Size: 1318 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/a1604485/attachment.obj From bruno.cardoso at gmail.com Tue Aug 23 17:06:37 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 23 Aug 2011 22:06:37 -0000 Subject: [llvm-commits] [llvm] r138392 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-splat.ll Message-ID: <20110823220637.8F6E92A6C12C@llvm.org> Author: bruno Date: Tue Aug 23 17:06:37 2011 New Revision: 138392 URL: http://llvm.org/viewvc/llvm-project?rev=138392&view=rev Log: Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit permutations. Also tidy up some patterns and make them close to their instruction definition! Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-splat.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138392&r1=138391&r2=138392&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 23 17:06:37 2011 @@ -4188,20 +4188,21 @@ assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) && "Vector size not supported"); - bool Is128 = VT.getSizeInBits() == 128; - EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32; - V = DAG.getNode(ISD::BITCAST, dl, NVT, V); - - if (Is128) { + if (VT.getSizeInBits() == 128) { + V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; - V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); + V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), + &SplatMask[0]); } else { - // The second half of indicies refer to the higher part, which is a - // duplication of the lower one. This makes this shuffle a perfect match - // for the VPERM instruction. + // To use VPERMILPS to splat scalars, the second half of indicies must + // refer to the higher part, which is a duplication of the lower one, + // because VPERMILPS can only handle in-lane permutations. int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; - V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); + + V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); + V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), + &SplatMask[0]); } return DAG.getNode(ISD::BITCAST, dl, VT, V); @@ -4217,6 +4218,9 @@ int NumElems = SrcVT.getVectorNumElements(); unsigned Size = SrcVT.getSizeInBits(); + assert(((Size == 128 && NumElems > 4) || Size == 256) && + "Unknown how to promote splat for type"); + // Extract the 128-bit part containing the splat element and update // the splat element index when it refers to the higher register. if (Size == 256) { @@ -4229,16 +4233,14 @@ // All i16 and i8 vector types can't be used directly by a generic shuffle // instruction because the target has no such instruction. Generate shuffles // which repeat i16 and i8 several times until they fit in i32, and then can - // be manipulated by target suported shuffles. After the insertion of the - // necessary shuffles, the result is bitcasted back to v4f32 or v8f32. + // be manipulated by target suported shuffles. EVT EltVT = SrcVT.getVectorElementType(); - if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16)) + if (EltVT == MVT::i8 || EltVT == MVT::i16) V1 = PromoteSplati8i16(V1, DAG, EltNo); // Recreate the 256-bit vector and place the same 128-bit vector // into the low and high part. This is necessary because we want - // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles - // inside each separate v4f32 lane. + // to use VPERM* to shuffle the vectors if (Size == 256) { SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, DAG.getConstant(0, MVT::i32), DAG, dl); @@ -6211,6 +6213,7 @@ // Handle splat operations if (SVOp->isSplat()) { unsigned NumElem = VT.getVectorNumElements(); + int Size = VT.getSizeInBits(); // Special case, this is the only place now where it's allowed to return // a vector_shuffle operation without using a target specific node, because // *hopefully* it will be optimized away by the dag combiner. FIXME: should @@ -6223,7 +6226,8 @@ return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1); // Handle splats by matching through known shuffle masks - if (VT.is128BitVector() && NumElem <= 4) + if ((Size == 128 && NumElem <= 4) || + (Size == 256 && NumElem < 8)) return SDValue(); // All remaning splats are promoted to target supported vector shuffles. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138392&r1=138391&r2=138392&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 23 17:06:37 2011 @@ -473,13 +473,90 @@ (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>; } -def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), - (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>; -let AddedComplexity = 20 in { - def : Pat<(v4f32 (movddup VR128:$src, (undef))), - (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>; - def : Pat<(v2i64 (movddup VR128:$src, (undef))), - (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>; +let Predicates = [HasAVX] in { + // MOVHPS patterns + def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), + (VMOVHPSrm VR128:$src1, addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, + (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (VMOVHPSrm VR128:$src1, addr:$src2)>; + + // MOVLHPS patterns + let AddedComplexity = 20 in { + def : Pat<(v4f32 (movddup VR128:$src, (undef))), + (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>; + def : Pat<(v2i64 (movddup VR128:$src, (undef))), + (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>; + + // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS + def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)), + (VMOVLHPSrr VR128:$src1, VR128:$src2)>; + } + def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), + (VMOVLHPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), + (VMOVLHPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), + (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; + + // MOVHLPS patterns + let AddedComplexity = 20 in { + // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS + def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)), + (VMOVHLPSrr VR128:$src1, VR128:$src2)>; + + // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS + def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))), + (VMOVHLPSrr VR128:$src1, VR128:$src1)>; + def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))), + (VMOVHLPSrr VR128:$src1, VR128:$src1)>; + } +} + +let Predicates = [HasSSE1] in { + // MOVHPS patterns + def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), + (MOVHPSrm VR128:$src1, addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, + (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (MOVHPSrm VR128:$src1, addr:$src2)>; + + // MOVLHPS patterns + let AddedComplexity = 20 in { + def : Pat<(v4f32 (movddup VR128:$src, (undef))), + (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>; + def : Pat<(v2i64 (movddup VR128:$src, (undef))), + (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>; + + // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS + def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr VR128:$src1, VR128:$src2)>; + } + def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; + + // MOVHLPS patterns + let AddedComplexity = 20 in { + // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS + def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)), + (MOVHLPSrr VR128:$src1, VR128:$src2)>; + + // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS + def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))), + (MOVHLPSrr VR128:$src1, VR128:$src1)>; + def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))), + (MOVHLPSrr VR128:$src1, VR128:$src1)>; + } } //===----------------------------------------------------------------------===// @@ -4011,22 +4088,6 @@ Requires<[HasSSE2]>; let AddedComplexity = 20 in { -// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS -def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr VR128:$src1, VR128:$src2)>; - -// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS -def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)), - (MOVHLPSrr VR128:$src1, VR128:$src2)>; - -// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS -def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))), - (MOVHLPSrr VR128:$src1, VR128:$src1)>; -def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))), - (MOVHLPSrr VR128:$src1, VR128:$src1)>; -} - -let AddedComplexity = 20 in { // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))), (MOVLPSrm VR128:$src1, addr:$src2)>; @@ -6023,20 +6084,6 @@ def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; -// Shuffle with MOVLHPS -def : Pat<(X86Movlhps VR128:$src1, - (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), - (MOVHPSrm VR128:$src1, addr:$src2)>; -def : Pat<(X86Movlhps VR128:$src1, - (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), - (MOVHPSrm VR128:$src1, addr:$src2)>; -def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; - // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem // is during lowering, where it's not possible to recognize the load fold cause // it has two uses through a bitcast. One use disappears at isel time and the @@ -6108,8 +6155,8 @@ def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)), (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>; -def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; +def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; // Shuffle with MOVLPD def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=138392&r1=138391&r2=138392&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Tue Aug 23 17:06:37 2011 @@ -21,8 +21,8 @@ } ; CHECK: vmovd +; CHECK-NEXT: vmovlhps %xmm ; CHECK-NEXT: vinsertf128 $1 -; CHECK-NEXT: vpermilps $0 define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp { entry: %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0 @@ -32,8 +32,8 @@ ret <4 x i64> %vecinit6.i } -; CHECK: vinsertf128 $1 -; CHECK-NEXT: vpermilps $0 +; CHECK: vshufpd $0 +; CHECK-NEXT: vinsertf128 $1 define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp { entry: %vecinit.i = insertelement <4 x double> undef, double %q, i32 0 From criswell at uiuc.edu Tue Aug 23 17:14:07 2011 From: criswell at uiuc.edu (John Criswell) Date: Tue, 23 Aug 2011 22:14:07 -0000 Subject: [llvm-commits] [poolalloc] r138394 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110823221407.471ED2A6C12C@llvm.org> Author: criswell Date: Tue Aug 23 17:14:07 2011 New Revision: 138394 URL: http://llvm.org/viewvc/llvm-project?rev=138394&view=rev Log: Added funccheck_debug() and funccheckui_debug() for special handling. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138394&r1=138393&r2=138394&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Aug 23 17:14:07 2011 @@ -263,6 +263,9 @@ {"funccheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheckui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheckui_debug",{NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, From aaron at aaronballman.com Tue Aug 23 17:19:49 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Tue, 23 Aug 2011 17:19:49 -0500 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References: Message-ID: On Tue, Aug 23, 2011 at 5:34 AM, NAKAMURA Takumi wrote: > Good evening, Aaron! > > About lib/Support/Windows/RWMutex.inc; > > ?- Would you like to try describing rwmutex on windows xp? > ? ?Oh yeah, I don't have any Windows XP hosts any more. :( In code or on the mailing list? Windows XP doesn't have slim reader/writer locks (they're a Vista and up API). So the RWMutex object supports reader/writer locks when possible, but fallsback on the more heavy-handed original implementation, which uses vanilla critical section objects. This implementation is correct on XP, just not as efficient as on Vista and higher. On Vista and up, you can have multiple non-blocked readers at once, but on XP you will only be able to have one reader at a time. If you'd like me to update the comments in the code, I certainly can. > ?- I think, rather to refer to kernel32.dll, GetModuleHandle(NULL) > would be more enough. > ? ?How do you think? I've never been too happy with that convention. While it would certainly work because Kernel32 is mapped into every executable's process space, I don't think the code would be as clear where the functions are coming from. Also, there's no performance penalty for calling LoadLibrary vs GetModuleHandle( NULL ) that I've ever heard of. Since the library is already loaded into memory, the loader will traverse the list of loaded modules in the PEB, see Kernel32 (early on) and return the module handle from there. > ?- It would be happier for us to have generic "delayed dll resolver" > for NT5.1-unavailable entries. > ? ?I think it might be the global ctor. How do you think? That's not a bad idea. I did a quick search of the code base, and this is the first case we're using lazy loading for OS APIs. My personal feeling is: if we need to do this a second time, a helper API could be designed to make this cleaner. But since this is only happening once, the helper may be overkill. > ?- How about to split RWMutexImpl to Windows XP and higher? I originally looked into that, but it would be a larger change than I was comfortable with. Right now, the Impl is a concrete class, and an OS version split would require it to be a bridge. If you think it's a better approach though, I can certainly tackle it. > ?- Could you consider unittests for rwmutex? Yes, I could probably write some up, at least for testing them on Windows. Can you recommend where I should put the unit tests though (I've not yet done something like this for LLVM). Thanks for the review! ~Aaron From isanbard at gmail.com Tue Aug 23 17:20:16 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Aug 2011 22:20:16 -0000 Subject: [llvm-commits] [llvm] r138397 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110823222016.60D592A6C12C@llvm.org> Author: void Date: Tue Aug 23 17:20:16 2011 New Revision: 138397 URL: http://llvm.org/viewvc/llvm-project?rev=138397&view=rev Log: Look at the end of the entry block for an invoke. The invoke could be at the end of the entry block. If it's the only one, then we won't process all of the landingpad instructions correctly. This code is currently ugly, but should be made much nicer once the new EH switch is thrown. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=138397&r1=138396&r2=138397&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Aug 23 17:20:16 2011 @@ -389,10 +389,23 @@ SmallVector EH_Exceptions; SmallVector JmpbufUpdatePoints; - // Note: Skip the entry block since there's nothing there that interests - // us. eh.selector and eh.exception shouldn't ever be there, and we - // want to disregard any allocas that are there. - for (Function::iterator BB = F.begin(), E = F.end(); ++BB != E;) { + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) { + // Note: Skip the entry block since there's nothing there that interests + // us. eh.selector and eh.exception shouldn't ever be there, and we + // want to disregard any allocas that are there. + // + // FIXME: This is awkward. The new EH scheme won't need to skip the entry + // block. + if (BB == F.begin()) { + if (InvokeInst *II = dyn_cast(F.begin()->getTerminator())) { + // FIXME: This will be always non-NULL in the new EH. + if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst()) + if (!PersonalityFn) PersonalityFn = LPI->getPersonalityFn(); + } + + continue; + } + for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) { if (CallInst *CI = dyn_cast(I)) { if (CI->getCalledFunction() == SelectorFn) { From aaron at aaronballman.com Tue Aug 23 17:27:48 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Tue, 23 Aug 2011 17:27:48 -0500 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References: Message-ID: On Tue, Aug 23, 2011 at 5:58 AM, NAKAMURA Takumi wrote: > Aaron, about Threading.diff, > > + ? ? ?(void)::WaitForSingleObject(param.evt, INFINITE); > > I guess thread object might be the signal object. You may wait for hThread. Good catch! You're right, the thread will suffice. I've attached an updated patch which should be more straight-forward. Thanks! ~Aaron -------------- next part -------------- A non-text attachment was scrubbed... Name: Threading.diff Type: application/octet-stream Size: 1648 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/112df9f7/attachment-0001.obj From grosser at fim.uni-passau.de Tue Aug 23 17:35:08 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 23 Aug 2011 22:35:08 -0000 Subject: [llvm-commits] [polly] r138400 - in /polly/trunk: include/polly/LinkAllPasses.h lib/Analysis/ScopDetection.cpp lib/Analysis/TempScopInfo.cpp Message-ID: <20110823223508.505252A6C12C@llvm.org> Author: grosser Date: Tue Aug 23 17:35:08 2011 New Revision: 138400 URL: http://llvm.org/viewvc/llvm-project?rev=138400&view=rev Log: Add some forgotten passes to LinkAllPasses Modified: polly/trunk/include/polly/LinkAllPasses.h polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/LinkAllPasses.h?rev=138400&r1=138399&r2=138400&view=diff ============================================================================== --- polly/trunk/include/polly/LinkAllPasses.h (original) +++ polly/trunk/include/polly/LinkAllPasses.h Tue Aug 23 17:35:08 2011 @@ -41,8 +41,10 @@ Pass *createJSONExporterPass(); Pass *createJSONImporterPass(); Pass *createRegionSimplifyPass(); + Pass *createScopDetectionPass(); Pass *createScopInfoPass(); Pass *createScheduleOptimizerPass(); + Pass *createTempScopInfoPass(); #ifdef OPENSCOP_FOUND Pass *createScopExporterPass(); @@ -85,8 +87,10 @@ createJSONExporterPass(); createJSONImporterPass(); createRegionSimplifyPass(); + createScopDetectionPass(); createScopInfoPass(); createScheduleOptimizerPass(); + createTempScopInfoPass(); #ifdef OPENSCOP_FOUND createScopExporterPass(); Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=138400&r1=138399&r2=138400&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Tue Aug 23 17:35:08 2011 @@ -653,3 +653,6 @@ static RegisterPass X("polly-detect", "Polly - Detect Scops in functions"); +Pass *polly::createScopDetectionPass() { + return new ScopDetection(); +} Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=138400&r1=138399&r2=138400&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Tue Aug 23 17:35:08 2011 @@ -460,3 +460,6 @@ static RegisterPass X("polly-analyze-ir", "Polly - Analyse the LLVM-IR in the detected regions"); +Pass *polly::createTempScopInfoPass() { + return new TempScopInfo(); +} From grosser at fim.uni-passau.de Tue Aug 23 17:35:23 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 23 Aug 2011 22:35:23 -0000 Subject: [llvm-commits] [polly] r138401 - /polly/trunk/lib/ScheduleOptimizer.cpp Message-ID: <20110823223523.44C332A6C12C@llvm.org> Author: grosser Date: Tue Aug 23 17:35:23 2011 New Revision: 138401 URL: http://llvm.org/viewvc/llvm-project?rev=138401&view=rev Log: ScheduleOptimizer: Fix another memory leak Modified: polly/trunk/lib/ScheduleOptimizer.cpp Modified: polly/trunk/lib/ScheduleOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=138401&r1=138400&r2=138401&view=diff ============================================================================== --- polly/trunk/lib/ScheduleOptimizer.cpp (original) +++ polly/trunk/lib/ScheduleOptimizer.cpp Tue Aug 23 17:35:23 2011 @@ -297,6 +297,7 @@ isl_union_map *suffixSchedule = tileBandList(children); partialSchedule = isl_union_map_flat_range_product(partialSchedule, suffixSchedule); + isl_band_list_free(children); } else if (Prevector) { isl_map *tileMap; isl_union_map *tileUnionMap; From grosser at fim.uni-passau.de Tue Aug 23 17:35:38 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 23 Aug 2011 22:35:38 -0000 Subject: [llvm-commits] [polly] r138402 - in /polly/trunk/lib: CMakeLists.txt RegisterPasses.cpp Message-ID: <20110823223538.87E202A6C12C@llvm.org> Author: grosser Date: Tue Aug 23 17:35:38 2011 New Revision: 138402 URL: http://llvm.org/viewvc/llvm-project?rev=138402&view=rev Log: Register Polly passes automatically Polly adds, after it is loaded into opt or clang, its passes to the default set of -O3 passes. This means optimizing a program with clang and Polly becomes as simple as executing. clang -Xclang -load -Xclang lib/LLVMPolly.so -O3 program.c The same should work for dragonegg powered gfortran, g++, ... or any other tool that uses the PassManagerBuilder. Warning: Even though using Polly became with this commit extremly easy, Polly is still Pre-Alpha Quality. This means in most cases it will rather destroy the world than doing anything positive. ;-) Added: polly/trunk/lib/RegisterPasses.cpp Modified: polly/trunk/lib/CMakeLists.txt Modified: polly/trunk/lib/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CMakeLists.txt?rev=138402&r1=138401&r2=138402&view=diff ============================================================================== --- polly/trunk/lib/CMakeLists.txt (original) +++ polly/trunk/lib/CMakeLists.txt Tue Aug 23 17:35:38 2011 @@ -31,6 +31,7 @@ MayAliasSet.cpp Pocc.cpp RegionSimplify.cpp + RegisterPasses.cpp ScheduleOptimizer.cpp Exchange/JSONExporter.cpp ${POLLY_EXCHANGE_FILES} Added: polly/trunk/lib/RegisterPasses.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=138402&view=auto ============================================================================== --- polly/trunk/lib/RegisterPasses.cpp (added) +++ polly/trunk/lib/RegisterPasses.cpp Tue Aug 23 17:35:38 2011 @@ -0,0 +1,81 @@ +//===------ RegisterPasses.cpp - Add the Polly Passes to default passes --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Add the Polly passes to the optimization passes executed at -O3. +// +//===----------------------------------------------------------------------===// +#include "llvm/Analysis/Passes.h" +#include "llvm/InitializePasses.h" +#include "llvm/PassManager.h" +#include "llvm/PassRegistry.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/Transforms/IPO/PassManagerBuilder.h" + +#include "polly/LinkAllPasses.h" + +static void registerPollyPasses(const llvm::PassManagerBuilder &Builder, + llvm::PassManagerBase &PM) { + // Polly is only enabled at -O3 + if (Builder.OptLevel != 3) + return; + + // We need to initialize the passes before we use them. + // + // This is not necessary for the opt tool, however clang crashes if passes + // are not initialized. (FIXME?) + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeDominatorTreePass(Registry); + initializePostDominatorTreePass(Registry); + initializeLoopInfoPass(Registry); + initializeScalarEvolutionPass(Registry); + initializeRegionInfoPass(Registry); + initializeDominanceFrontierPass(Registry); + initializeAliasAnalysisAnalysisGroup(Registry); + + // A standard set of optimization passes partially taken/copied from the + // set of default optimization passes. This set of passes is most probably + // not yet optimal. TODO: Investigate optimal set of passes. + PM.add(llvm::createPromoteMemoryToRegisterPass()); + PM.add(llvm::createInstructionCombiningPass()); // Clean up after IPCP & DAE + PM.add(llvm::createCFGSimplificationPass()); // Clean up after IPCP & DAE + PM.add(llvm::createTailCallEliminationPass()); // Eliminate tail calls + PM.add(llvm::createCFGSimplificationPass()); // Merge & remove BBs + PM.add(llvm::createReassociatePass()); // Reassociate expressions + PM.add(llvm::createLoopRotatePass()); // Rotate Loop + PM.add(llvm::createInstructionCombiningPass()); + PM.add(llvm::createIndVarSimplifyPass()); // Canonicalize indvars + PM.add(llvm::createRegionInfoPass()); + + PM.add(polly::createCodePreperationPass()); + PM.add(polly::createRegionSimplifyPass()); + + // FIXME: Needed as RegionSimplifyPass does destroy canonical induction + // variables. (It changes the order of the operands in the PHI nodes) + PM.add(llvm::createIndVarSimplifyPass()); + PM.add(polly::createScopDetectionPass()); + PM.add(polly::createIndependentBlocksPass()); + + // FIXME: We should not need to schedule this passes (and some more) + // explicitally, as it is alread required by the ScopInfo pass. + // However, without this clang crashes because of unitialized passes. + PM.add(polly::createTempScopInfoPass()); + PM.add(polly::createScopInfoPass()); + PM.add(polly::createDependencesPass()); + PM.add(polly::createScheduleOptimizerPass()); + PM.add(polly::createCloogInfoPass()); + PM.add(polly::createCodeGenerationPass()); +} + +// Execute Polly together with a set of preparing passes before all other +// optimizations. This is basically to be executed before any loop optimizer +// passes like LICM or LoopIdomPass. Those would complicate the code such that +// Polly would recognize less scops. +static llvm::RegisterStandardPasses +PassRegister(llvm::PassManagerBuilder::EP_EarlyAsPossible, + registerPollyPasses); From isanbard at gmail.com Tue Aug 23 17:55:03 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Aug 2011 22:55:03 -0000 Subject: [llvm-commits] [llvm] r138406 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110823225503.441842A6C12C@llvm.org> Author: void Date: Tue Aug 23 17:55:03 2011 New Revision: 138406 URL: http://llvm.org/viewvc/llvm-project?rev=138406&view=rev Log: Don't replace *all* uses with the new stuff. This is not necessarily the first or dominating use of the EH values. The IR breaks if it's not. So replace the specific value in the instruction with the new value. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=138406&r1=138405&r2=138406&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Aug 23 17:55:03 2011 @@ -347,7 +347,7 @@ continue; } - Inst->replaceAllUsesWith(CreateLandingPadLoad(F, ExnAddr, SelAddr, I)); + I->replaceUsesOfWith(Inst, CreateLandingPadLoad(F, ExnAddr, SelAddr, I)); } } From isanbard at gmail.com Tue Aug 23 19:00:23 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 24 Aug 2011 00:00:23 -0000 Subject: [llvm-commits] [llvm] r138416 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110824000023.2B46E2A6C12C@llvm.org> Author: void Date: Tue Aug 23 19:00:23 2011 New Revision: 138416 URL: http://llvm.org/viewvc/llvm-project?rev=138416&view=rev Log: Add the sentinal "no handle" value to the ResumeInst. A value of -1 at a call site tells the personality function that this call isn't handled by the current function. Since the ResumeInsts are converted to calls to _Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=138416&r1=138415&r2=138416&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Aug 23 19:00:23 2011 @@ -631,6 +631,8 @@ if (Callee != SelectorFn && Callee != ExceptionFn && !CI->doesNotThrow()) insertCallSiteStore(CI, -1, CallSite); + } else if (ResumeInst *RI = dyn_cast(I)) { + insertCallSiteStore(RI, -1, CallSite); } } From evan.cheng at apple.com Tue Aug 23 19:52:57 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Aug 2011 17:52:57 -0700 Subject: [llvm-commits] [PATCH] Crash in SplitBlock with incomplete dominator information In-Reply-To: References: Message-ID: Looks fine to me. Has someone committed this? Evan On Aug 18, 2011, at 5:00 PM, Nick Sumner wrote: > Hi, > > The attached patch fixes a crashing bug in SplitBlock when it is > called on a block with no dominator information even though dominators > were previously computed. This is originally from a bug report > (http://llvm.org/bugs/show_bug.cgi?id=10643), but I am cross-posting > to give it a record in the proper place until it can be committed. > > One example of a program suffering from this: > > #include > #include > > void foo() { > exit(0); > printf("No dominator info here\n"); > } > > > thanks, > Nick Sumner > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Tue Aug 23 21:32:53 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 23 Aug 2011 19:32:53 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r136345 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <4E50FFB6.7090607@free.fr> References: <20110728091343.E09F02A6C12C@llvm.org> <515E325F-1081-4CB8-8296-C8D1F5F06E8C@apple.com> <4E35A51A.6050009@free.fr> <4E36E21A.2050103@free.fr> <4E42368C.9020705@free.fr> <4E50FFB6.7090607@free.fr> Message-ID: <50D8E3DF-217A-49C4-88B2-6C8871C2DA49@apple.com> On Aug 21, 2011, at 5:53 AM, Duncan Sands wrote: > Hi Bob, does the attached patch fix things for you? Yes, it looks good. Are you ready to commit it? From dblaikie at gmail.com Wed Aug 24 00:16:05 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 23 Aug 2011 22:16:05 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: Here's a smaller version/start of my twine changes - perhaps it'll be easier to bite off to review. The description from my initial attempt: Here's some more Twine-ification of APIs. I realize this seems like a somewhat random assortment - I haven't, for example, fully changed some types to Twine (so there might be some functions in a type that take Twine, others that take StringRef still), but it does seem to be stable & I didn't want to just keep piling on more code. API changes: * Twine * appendTo(std::string&) Works like "toVector" but on std::strings. (I'd like to rename toVector to appendTo to make it clear it's appending, not overwriting - I added test cases to expose this existing deliberate design because when I 'fixed' it by clearing the vector in toVector I broke a bunch of stuff that was relying on it being appending) * assignTo(std::string&) clear() + appendTo * StringRef * StringRef(const char (&)[N]) an array constructor so it doesn't have to use strlen for string literals. For some reason this doesn't work in GCC (try making the StringRef(const char*) ctor explicit & GCC starts complaining about how it can't convert the const char* in 'return "foo";' into a StringRef). This is a little tricky - it doesn't include the trailing null character if one is present. This is to maintain compatibility with the existing implicit conversion from string arrays via the (const char*) ctor. * assignTo(std::string&) the same idea as Twine::appendTo(std::string&). This is more efficient than using str = strRef; because it doesn't produce an extra temporary buffer to return through. ctor initialization (std::string str = strRef;) is still efficient due to RVO. * booleanTest()/SafeBool I've made StringRef boolean testable so it can be used as a drop in replacement when null tests are required * TwineString - a type that makes retrieving/manipulating a Twine value a little simpler. Yes, it's a little dodgy that it derives from StringRef but it's 'good enough' to make Twines the default string arguments - any time you see a StringRef or std::string argument there should be a specific explanation. One current problem I have is that SmallString is convertible to StringRef and StringRef to Twine, but that seems to be insufficient to implicitly convert from SmallString to Twine - so I've added a few explicit Twine(smallstr) calls around. If there's a better way to approach this (ultimately we could add a SmallString option to Twine, but it'd be sort of nice not to have to do that either) I'm all ears. Aside: Twine:: toNullTerminatedStringRef scares me. A lot. It relies on UB to leave the null character beyond the end of the allocated buffer. Could we fix this to return a StringRef that doesn't include the null character (though I'm not sure this bit should matter, really - code asking for the null terminated StringRef is probably doing it to pass to a C API that's not going to care about the StringRef's concept of length), but leave the character itself in the buffer? (& I was thinking we could check if the Twine was a non-empty StringRef already, test the last character for null, then return a StringRef over that rather than using a new buffer - though this wouldn't work for my current StringRef(const char(&)[N]) ctor, since the length won't include the null character). -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/ed16c627/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: twine_partial.diff Type: text/x-patch Size: 43238 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110823/ed16c627/attachment.bin From craig.topper at gmail.com Wed Aug 24 01:14:18 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 24 Aug 2011 06:14:18 -0000 Subject: [llvm-commits] [llvm] r138427 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/avx-arith.ll Message-ID: <20110824061418.7E5DB2A6C12C@llvm.org> Author: ctopper Date: Wed Aug 24 01:14:18 2011 New Revision: 138427 URL: http://llvm.org/viewvc/llvm-project?rev=138427&view=rev Log: Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/test/CodeGen/X86/avx-arith.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138427&r1=138426&r2=138427&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 01:14:18 2011 @@ -998,6 +998,21 @@ setOperationAction(ISD::SELECT, MVT::v4i64, Custom); setOperationAction(ISD::SELECT, MVT::v8f32, Custom); + setOperationAction(ISD::ADD, MVT::v4i64, Custom); + setOperationAction(ISD::ADD, MVT::v8i32, Custom); + setOperationAction(ISD::ADD, MVT::v16i16, Custom); + setOperationAction(ISD::ADD, MVT::v32i8, Custom); + + setOperationAction(ISD::SUB, MVT::v4i64, Custom); + setOperationAction(ISD::SUB, MVT::v8i32, Custom); + setOperationAction(ISD::SUB, MVT::v16i16, Custom); + setOperationAction(ISD::SUB, MVT::v32i8, Custom); + + setOperationAction(ISD::MUL, MVT::v4i64, Custom); + setOperationAction(ISD::MUL, MVT::v8i32, Custom); + setOperationAction(ISD::MUL, MVT::v16i16, Custom); + // Don't lower v32i8 because there is no 128-bit byte mul + // Custom lower several nodes for 256-bit types. for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { @@ -9422,8 +9437,58 @@ return Op; } -SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { +// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit +// ones, and then concatenate the result back. +static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getValueType(); + + assert(VT.getSizeInBits() == 256 && VT.isInteger() && + "Unsupported value type for operation"); + + int NumElems = VT.getVectorNumElements(); + DebugLoc dl = Op.getDebugLoc(); + SDValue Idx0 = DAG.getConstant(0, MVT::i32); + SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); + + // Extract the LHS vectors + SDValue LHS = Op.getOperand(0); + SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); + SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); + + // Extract the RHS vectors + SDValue RHS = Op.getOperand(1); + SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); + SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); + + MVT EltVT = VT.getVectorElementType().getSimpleVT(); + EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); + + return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, + DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), + DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); +} + +SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { + assert(Op.getValueType().getSizeInBits() == 256 && + Op.getValueType().isInteger() && + "Only handle AVX 256-bit vector integer operation"); + return Lower256IntArith(Op, DAG); +} + +SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { + assert(Op.getValueType().getSizeInBits() == 256 && + Op.getValueType().isInteger() && + "Only handle AVX 256-bit vector integer operation"); + return Lower256IntArith(Op, DAG); +} + +SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { EVT VT = Op.getValueType(); + + // Decompose 256-bit ops into smaller 128-bit ops. + if (VT.getSizeInBits() == 256) + return Lower256IntArith(Op, DAG); + assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); DebugLoc dl = Op.getDebugLoc(); @@ -10013,7 +10078,7 @@ case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); case ISD::CTLZ: return LowerCTLZ(Op, DAG); case ISD::CTTZ: return LowerCTTZ(Op, DAG); - case ISD::MUL: return LowerMUL_V2I64(Op, DAG); + case ISD::MUL: return LowerMUL(Op, DAG); case ISD::SRA: case ISD::SRL: case ISD::SHL: return LowerShift(Op, DAG); @@ -10029,6 +10094,8 @@ case ISD::ADDE: case ISD::SUBC: case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); + case ISD::ADD: return LowerADD(Op, DAG); + case ISD::SUB: return LowerSUB(Op, DAG); } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=138427&r1=138426&r2=138427&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Aug 24 01:14:18 2011 @@ -819,7 +819,9 @@ SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; Modified: llvm/trunk/test/CodeGen/X86/avx-arith.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-arith.ll?rev=138427&r1=138426&r2=138427&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-arith.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-arith.ll Wed Aug 24 01:14:18 2011 @@ -131,3 +131,131 @@ } declare float @sqrtf(float) readnone + + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = add <4 x i64> %i, %j + ret <4 x i64> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpaddd %xmm +; CHECK-NEXT: vpaddd %xmm +; CHECK-NEXT: vinsertf128 $1 +define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = add <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpaddw %xmm +; CHECK-NEXT: vpaddw %xmm +; CHECK-NEXT: vinsertf128 $1 +define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = add <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpaddb %xmm +; CHECK-NEXT: vpaddb %xmm +; CHECK-NEXT: vinsertf128 $1 +define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %x = add <32 x i8> %i, %j + ret <32 x i8> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpsubq %xmm +; CHECK-NEXT: vpsubq %xmm +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = sub <4 x i64> %i, %j + ret <4 x i64> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpsubd %xmm +; CHECK-NEXT: vpsubd %xmm +; CHECK-NEXT: vinsertf128 $1 +define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = sub <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpsubw %xmm +; CHECK-NEXT: vpsubw %xmm +; CHECK-NEXT: vinsertf128 $1 +define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = sub <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpsubb %xmm +; CHECK-NEXT: vpsubb %xmm +; CHECK-NEXT: vinsertf128 $1 +define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %x = sub <32 x i8> %i, %j + ret <32 x i8> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpmulld %xmm +; CHECK-NEXT: vpmulld %xmm +; CHECK-NEXT: vinsertf128 $1 +define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = mul <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpmullw %xmm +; CHECK-NEXT: vpmullw %xmm +; CHECK-NEXT: vinsertf128 $1 +define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = mul <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vextractf128 $1 +; CHECK-NEXT: vextractf128 $1 +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsrlq $32, %xmm +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsllq $32, %xmm +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsrlq $32, %xmm +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsllq $32, %xmm +; CHECK-NEXT: vpsrlq $32, %xmm +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsllq $32, %xmm +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vpsrlq $32, %xmm +; CHECK-NEXT: vpmuludq %xmm +; CHECK-NEXT: vpsllq $32, %xmm +; CHECK-NEXT: vpaddq %xmm +; CHECK-NEXT: vinsertf128 $1 +define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = mul <4 x i64> %i, %j + ret <4 x i64> %x +} + From grosser at fim.uni-passau.de Wed Aug 24 02:33:05 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 24 Aug 2011 07:33:05 -0000 Subject: [llvm-commits] [polly] r138428 - /polly/trunk/lib/RegisterPasses.cpp Message-ID: <20110824073305.4DAEE2A6C12D@llvm.org> Author: grosser Date: Wed Aug 24 02:33:05 2011 New Revision: 138428 URL: http://llvm.org/viewvc/llvm-project?rev=138428&view=rev Log: RegisterPasses: Rework comments slightly Modified: polly/trunk/lib/RegisterPasses.cpp Modified: polly/trunk/lib/RegisterPasses.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=138428&r1=138427&r2=138428&view=diff ============================================================================== --- polly/trunk/lib/RegisterPasses.cpp (original) +++ polly/trunk/lib/RegisterPasses.cpp Wed Aug 24 02:33:05 2011 @@ -39,8 +39,9 @@ initializeAliasAnalysisAnalysisGroup(Registry); // A standard set of optimization passes partially taken/copied from the - // set of default optimization passes. This set of passes is most probably - // not yet optimal. TODO: Investigate optimal set of passes. + // set of default optimization passes. It is used to bring the code into + // a canonical form that can than be analyzed by Polly. This set of passes is + // most probably not yet optimal. TODO: Investigate optimal set of passes. PM.add(llvm::createPromoteMemoryToRegisterPass()); PM.add(llvm::createInstructionCombiningPass()); // Clean up after IPCP & DAE PM.add(llvm::createCFGSimplificationPass()); // Clean up after IPCP & DAE @@ -55,13 +56,14 @@ PM.add(polly::createCodePreperationPass()); PM.add(polly::createRegionSimplifyPass()); - // FIXME: Needed as RegionSimplifyPass does destroy canonical induction - // variables. (It changes the order of the operands in the PHI nodes) + // FIXME: Needed as RegionSimplifyPass destroys the canonical form of + // induction variables (It changes the order of the operands in the + // PHI nodes). PM.add(llvm::createIndVarSimplifyPass()); PM.add(polly::createScopDetectionPass()); PM.add(polly::createIndependentBlocksPass()); - // FIXME: We should not need to schedule this passes (and some more) + // FIXME: We should not need to schedule passes like the TempScopInfoPass // explicitally, as it is alread required by the ScopInfo pass. // However, without this clang crashes because of unitialized passes. PM.add(polly::createTempScopInfoPass()); @@ -72,10 +74,11 @@ PM.add(polly::createCodeGenerationPass()); } -// Execute Polly together with a set of preparing passes before all other -// optimizations. This is basically to be executed before any loop optimizer -// passes like LICM or LoopIdomPass. Those would complicate the code such that -// Polly would recognize less scops. +// Execute Polly together with a set of preparing passes. +// +// We run Polly that early to run before loop optimizer passes like LICM or +// the LoopIdomPass. Both transform the code in a way that Polly will recognize +// less scops. static llvm::RegisterStandardPasses PassRegister(llvm::PassManagerBuilder::EP_EarlyAsPossible, registerPollyPasses); From baldrick at free.fr Wed Aug 24 03:06:14 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Aug 2011 08:06:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r138429 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <20110824080614.F38F82A6C12D@llvm.org> Author: baldrick Date: Wed Aug 24 03:06:14 2011 New Revision: 138429 URL: http://llvm.org/viewvc/llvm-project?rev=138429&view=rev Log: As fallout from the new type system, a GCC pointer type may be converted to different LLVM pointer types depending on whether it is converted directly or as part of converting a containing struct. This broke some testcases in FrontendObjC in which the type of an initial value (which is built up field by field, so any fields with pointer type were being converted directly, not as a side effect of converting the containing struct) didn't match the type of the global value (for which the fields with pointer type were type converted as a side effect of converting the containing struct type - the type of the global). If such a mismatch happens, change the type of the global variable to match that of the initializer. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=138429&r1=138428&r2=138429&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Aug 24 03:06:14 2011 @@ -1381,6 +1381,22 @@ Constant *Init = TreeConstantToLLVM::Convert(DECL_INITIAL(decl)); // Set the initializer. + if (GV->getType()->getElementType() != Init->getType()) { + GV->removeFromParent(); + GlobalVariable *NGV = new GlobalVariable(*TheModule, Init->getType(), + GV->isConstant(), + GV->getLinkage(), 0, + GV->getName()); + NGV->setVisibility(GV->getVisibility()); + NGV->setSection(GV->getSection()); + NGV->setAlignment(GV->getAlignment()); + NGV->setLinkage(GV->getLinkage()); + GV->replaceAllUsesWith(TheFolder->CreateBitCast(NGV, GV->getType())); + changeLLVMConstant(GV, NGV); + delete GV; + SET_DECL_LLVM(decl, NGV); + GV = NGV; + } GV->setInitializer(Init); if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || GV->hasPrivateLinkage()) From baldrick at free.fr Wed Aug 24 03:07:50 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Aug 2011 10:07:50 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r136345 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <50D8E3DF-217A-49C4-88B2-6C8871C2DA49@apple.com> References: <20110728091343.E09F02A6C12C@llvm.org> <515E325F-1081-4CB8-8296-C8D1F5F06E8C@apple.com> <4E35A51A.6050009@free.fr> <4E36E21A.2050103@free.fr> <4E42368C.9020705@free.fr> <4E50FFB6.7090607@free.fr> <50D8E3DF-217A-49C4-88B2-6C8871C2DA49@apple.com> Message-ID: <4E54B156.4070209@free.fr> On 24/08/11 04:32, Bob Wilson wrote: > > On Aug 21, 2011, at 5:53 AM, Duncan Sands wrote: > >> Hi Bob, does the attached patch fix things for you? > > Yes, it looks good. Are you ready to commit it? Applied in commit 138429. Ciao, Duncan. From nadav.rotem at intel.com Wed Aug 24 04:22:59 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 24 Aug 2011 12:22:59 +0300 Subject: [llvm-commits] [llvm] r138366 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll In-Reply-To: <20110823201110.8C91D2A6C12C@llvm.org> References: <20110823201110.8C91D2A6C12C@llvm.org> Message-ID: <6594DDFF12B03D4E89690887C2486994029705F772@hasmsx504.ger.corp.intel.com> It looks like the crash is because getNullValue is not implemented for MMX types. The new constantfolding optimization triggered this bug. What's the plan for MMX types ? Should I add support to getNullValue ? Thanks, Nadav -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Eric Christopher Sent: Tuesday, August 23, 2011 23:11 To: llvm-commits at cs.uiuc.edu Subject: [llvm-commits] [llvm] r138366 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll Author: echristo Date: Tue Aug 23 15:11:10 2011 New Revision: 138366 URL: http://llvm.org/viewvc/llvm-project?rev=138366&view=rev Log: Revert "Address Duncan's CR request:" This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340) Conflicts: test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constant.h (original) +++ llvm/trunk/include/llvm/Constant.h Tue Aug 23 15:11:10 2011 @@ -51,9 +51,6 @@ /// isNullValue - Return true if this is the value that would be returned by /// getNullValue. bool isNullValue() const; - /// isAllOnesValue - Return true if this is the value that would be returned by - /// getAllOnesValue. - bool isAllOnesValue() const; /// isNegativeZeroValue - Return true if the value is what would be returned /// by getZeroValueForNegation. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Aug 23 15:11:10 2011 @@ -45,9 +45,15 @@ /// ConstantExpr if unfoldable. static Constant *FoldBitCast(Constant *C, Type *DestTy, const TargetData &TD) { - // Catch the obvious splat cases. - if (C->isNullValue()) return Constant::getNullValue(DestTy); - if (C->isAllOnesValue()) return Constant::getAllOnesValue(DestTy); + + ConstantVector *CV = dyn_cast(C); + IntegerType *IntVTy = dyn_cast(DestTy); + // When casting vectors to scalar integers, catch the + // obvious splat cases. + if (IntVTy && CV) { + if (CV->isNullValue()) return ConstantInt::getNullValue(IntVTy); + if (CV->isAllOnesValue()) return ConstantInt::getAllOnesValue(IntVTy); + } // The code below only handles casts to vectors currently. VectorType *DestVTy = dyn_cast(DestTy); @@ -62,7 +68,6 @@ } // If this is a bitcast from constant vector -> vector, fold it. - ConstantVector *CV = dyn_cast(C); if (CV == 0) return ConstantExpr::getBitCast(C, DestTy); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Aug 23 15:11:10 2011 @@ -62,21 +62,6 @@ return isa(this) || isa(this); } -bool Constant::isAllOnesValue() const { - // Check for -1 integers - if (const ConstantInt *CI = dyn_cast(this)) - return CI->isAllOnesValue(); - - // +0.0 is null. - if (const ConstantFP *CFP = dyn_cast(this)) - return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue(); - - // Check for constant vectors - if (const ConstantVector *CV = dyn_cast(this)) - return CV->isAllOnesValue(); - - return false; -} // Constructor to create a '0' constant of arbitrary type... Constant *Constant::getNullValue(Type *Ty) { switch (Ty->getTypeID()) { @@ -141,7 +126,7 @@ SmallVector Elts; VectorType *VTy = cast(Ty); Elts.resize(VTy->getNumElements(), getAllOnesValue(VTy->getElementType())); - assert(Elts[0] && "Invalid AllOnes value!"); + assert(Elts[0] && "Not a vector integer type!"); return cast(ConstantVector::get(Elts)); } @@ -1079,16 +1064,13 @@ // Check out first element. const Constant *Elt = getOperand(0); const ConstantInt *CI = dyn_cast(Elt); - const ConstantFP *CF = dyn_cast(Elt); - + if (!CI || !CI->isAllOnesValue()) return false; // Then make sure all remaining elements point to the same value. for (unsigned I = 1, E = getNumOperands(); I < E; ++I) if (getOperand(I) != Elt) return false; - // First value is all-ones. - return (CI && CI->isAllOnesValue()) || - (CF && CF->isAllOnesValue()); + return true; } /// getSplatValue - If this is a splat constant, where all of the Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast.ll?rev=138366&r1=138365&r2=138366&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bitcast.ll Tue Aug 23 15:11:10 2011 @@ -11,7 +11,7 @@ %t3 = xor <2 x i32> %t1, %t2 %t4 = extractelement <2 x i32> %t3, i32 0 ret i32 %t4 - + ; CHECK: @test1 ; CHECK: ret i32 0 } @@ -30,7 +30,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test2 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 0 ; CHECK-NEXT: bitcast <2 x i32> %B to <2 x float> @@ -55,7 +55,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test3 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 1 ; CHECK-NEXT: bitcast <2 x i64> %B to <4 x float> @@ -75,7 +75,7 @@ ; CHECK: @test4 ; CHECK-NEXT: insertelement <2 x i32> undef, i32 %A, i32 0 ; CHECK-NEXT: insertelement <2 x i32> {{.*}}, i32 %B, i32 1 - ; CHECK-NEXT: ret <2 x i32> + ; CHECK-NEXT: ret <2 x i32> } @@ -92,7 +92,7 @@ ; CHECK: @test5 ; CHECK-NEXT: insertelement <2 x float> undef, float %A, i32 0 ; CHECK-NEXT: insertelement <2 x float> {{.*}}, float %B, i32 1 - ; CHECK-NEXT: ret <2 x float> + ; CHECK-NEXT: ret <2 x float> } define <2 x float> @test6(float %A){ @@ -113,27 +113,3 @@ ; CHECK: @ISPC0 ; CHECK: ret i64 0 } - - -define i64 @Vec2(i64 %in) { - %out = and i64 %in, xor (i64 bitcast (<4 x i16> to i64), i64 0) - ret i64 %out -; CHECK: @Vec2 -; CHECK: ret i64 0 -} - -define i64 @All11(i64 %in) { - %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1) - ret i64 %out -; CHECK: @All11 -; CHECK: ret i64 0 -} - - -define i32 @All111(i32 %in) { - %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) - ret i32 %out -; CHECK: @All111 -; CHECK: ret i32 0 -} - _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From stoklund at 2pi.dk Wed Aug 24 04:47:02 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 24 Aug 2011 11:47:02 +0200 Subject: [llvm-commits] [llvm] r138163 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll In-Reply-To: <05AAB692-35F4-4AE4-B0FE-56EC584E4F46@apple.com> References: <20110820001725.627722A6C12C@llvm.org> <05AAB692-35F4-4AE4-B0FE-56EC584E4F46@apple.com> Message-ID: <3b756953218d5cb7f6164cd51d8a0425.squirrel@webmail.2pi.dk> On Wed, August 24, 2011 2:44 am, Evan Cheng wrote: > I could have sworn there is a good reason for the pseudo-instruction. Can > this change inhibit some optimization, e.g. coalescing, copy propagation? I think this was true before we started using the generic COPY instruction during register allocation. Now they are not needed any more. /jakob > On Aug 19, 2011, at 5:32 PM, Jakob Stoklund Olesen wrote: > >> >> On Aug 19, 2011, at 5:17 PM, Chad Rosier wrote: >> >>> Author: mcrosier >>> Date: Fri Aug 19 19:17:25 2011 >>> New Revision: 138163 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=138163&view=rev >>> Log: >>> VMOVQQQQs pseudo instructions are only created by >>> ARMBaseInstrInfo::copyPhysReg. >>> Therefore, rather then generate a pseudo instruction, which is later >>> expanded, >>> generate the necessary instructions in place. >> >> Nice! >> >> Does that mean the VMOVQQQQ pseudo-instruction can be deleted completely >> now? >> >> You can probably do the same trick with VMOVQQ. >> >> /jakob >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From geek4civic at gmail.com Wed Aug 24 05:14:18 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 24 Aug 2011 19:14:18 +0900 Subject: [llvm-commits] [llvm] r138213 - /llvm/trunk/lib/Support/Windows/PathV2.inc In-Reply-To: References: <20110820213638.9E0D52A6C12C@llvm.org> Message-ID: Aaron, 2011/8/24 Aaron Ballman : >>>> Nitpick: Shall we handle "x:\path\to\com9.txt" here? >>> >>> I could certainly add that. ?Do we link against shlwapi.lib (available >>> in Win2k and higher) so that I can use PathFindFileName? ?Or should I >>> prefer our filename function from PathV2.cpp (this one only worries me >>> in case we accidentally run into infinite loops at some point)? >> >> I think it would be enough to use PathV2 itself to parse path. Using >> shell api might be overkill (and useless). >> Note: "x:\path\to\com9.txt" is mapped to the device namespace. > > I've attached a patch to address this so that we now use the path > "stem" to do the comparison. ?This means we'll catch DOS device names > like "com9" as well as ill-named compete paths like > x:\path\to\com9.txt. I am sorry, it must be too bikeshed for us. Usually, it would be enough for us to detect *intentional* device names. (eg. "nul") I rethought maniac detection would be overkill here. FYI, "X:/existent/path/to/nul.blahblah/nonexistent/path/to" is mapped to device namespace. "X:/nonexistent/path/to/nul.blahblah" is not. In common cases, such a weird device names could raise error in somewhere, I expect. > Additionally, I addressed your suggestion about the static declaration > using array notation instead of pointer notation. ?However, I'd be > curious to hear why you have this preference (you could email me > off-list if you'd prefer). char const *foo[] = {"qux", "quux"}; It spends two R/W(.data) pointers(4 or 8 bytes per an element) and two literal constant(4 bytes and 5 bytes). (note, it is more possible "char const *const foo[] = ...", then pointers are allocated to .rodata) In contrast, char const foo[][5] = {'qux", "quux"}; It only spends 10 bytes of constant array. Yeah, I know it might be still my preference, thank you dou itashimashite! ...Takumi From richard at xmos.com Wed Aug 24 08:32:43 2011 From: richard at xmos.com (Richard Osborne) Date: Wed, 24 Aug 2011 13:32:43 -0000 Subject: [llvm-commits] [llvm] r138433 - in /llvm/trunk: lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Message-ID: <20110824133243.C45B02A6C12C@llvm.org> Author: friedgold Date: Wed Aug 24 08:32:43 2011 New Revision: 138433 URL: http://llvm.org/viewvc/llvm-project?rev=138433&view=rev Log: Add Uses=[SP] to call instructions. This fixes a miscompilation with a variable sized alloca. Added: llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=138433&r1=138432&r2=138433&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Wed Aug 24 08:32:43 2011 @@ -739,7 +739,7 @@ let isCall=1, // All calls clobber the link register and the non-callee-saved registers: -Defs = [R0, R1, R2, R3, R11, LR] in { +Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BL_u10 : _FU10< (outs), (ins calltarget:$target, variable_ops), @@ -981,7 +981,7 @@ let isCall=1, // All calls clobber the link register and the non-callee-saved registers: -Defs = [R0, R1, R2, R3, R11, LR] in { +Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), "bla $addr", [(XCoreBranchLink GRRegs:$addr)]>; Added: llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll?rev=138433&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll (added) +++ llvm/trunk/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll Wed Aug 24 08:32:43 2011 @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +declare void @g() +declare i8* @llvm.stacksave() nounwind +declare void @llvm.stackrestore(i8*) nounwind + +define void @f(i32** %p, i32 %size) { +allocas: + %0 = call i8* @llvm.stacksave() + %a = alloca i32, i32 %size + store i32* %a, i32** %p + call void @g() + call void @llvm.stackrestore(i8* %0) + ret void +} +; CHECK: f: +; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1] +; CHECK: set sp, [[REGISTER]] +; CHECK extsp 1 +; CHECK bl g From aaron at aaronballman.com Wed Aug 24 08:58:48 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Wed, 24 Aug 2011 08:58:48 -0500 Subject: [llvm-commits] [llvm] r138213 - /llvm/trunk/lib/Support/Windows/PathV2.inc In-Reply-To: References: <20110820213638.9E0D52A6C12C@llvm.org> Message-ID: On Wed, Aug 24, 2011 at 5:14 AM, NAKAMURA Takumi wrote: > I am sorry, it must be too bikeshed for us. > Usually, it would be enough for us to detect *intentional* device > names. (eg. "nul") > I rethought maniac detection would be overkill here. I can agree with that. :-) > FYI, "X:/existent/path/to/nul.blahblah/nonexistent/path/to" is mapped > to device namespace. > "X:/nonexistent/path/to/nul.blahblah" is not. Odd! I would have assumed either to be illegal paths in the same way X:\nonexistent\path\???.txt is just as reserved as X:\existent\path\???.txt is. > char const *foo[] = {"qux", "quux"}; It spends two R/W(.data) > pointers(4 or 8 bytes per an element) and two literal constant(4 bytes > and 5 bytes). > (note, it is more possible "char const *const foo[] = ...", then > pointers are allocated to .rodata) > > In contrast, char const foo[][5] = {'qux", "quux"}; It only spends 10 > bytes of constant array. I can see the logic now; thanks! Since we're going to skip the paranoid path checking, do you mind if we leave the existing code stand, or do you still have a strong preference for array notation? ~Aaron From eli.friedman at gmail.com Wed Aug 24 10:36:49 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 08:36:49 -0700 Subject: [llvm-commits] [llvm] r138366 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll In-Reply-To: <6594DDFF12B03D4E89690887C2486994029705F772@hasmsx504.ger.corp.intel.com> References: <20110823201110.8C91D2A6C12C@llvm.org> <6594DDFF12B03D4E89690887C2486994029705F772@hasmsx504.ger.corp.intel.com> Message-ID: On Wed, Aug 24, 2011 at 2:22 AM, Rotem, Nadav wrote: > It looks like the crash is because getNullValue is not implemented for MMX types. The new constantfolding optimization triggered this bug. > > What's the plan for MMX types ? Should I add support to getNullValue ? It's probably a bug if we're trying to constant-fold MMX types; it's not worth the effort to make that work. -Eli From criswell at uiuc.edu Wed Aug 24 10:55:19 2011 From: criswell at uiuc.edu (John Criswell) Date: Wed, 24 Aug 2011 15:55:19 -0000 Subject: [llvm-commits] [www] r138436 - /www/trunk/index.html Message-ID: <20110824155519.C72D92A6C12C@llvm.org> Author: criswell Date: Wed Aug 24 10:55:19 2011 New Revision: 138436 URL: http://llvm.org/viewvc/llvm-project?rev=138436&view=rev Log: Made the use of bold font for project names consistent (specifically, added bold type for the C++ ABI link). Fixed extreaneous comma in Klee description. Modified: www/trunk/index.html Modified: www/trunk/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=138436&r1=138435&r2=138436&view=diff ============================================================================== --- www/trunk/index.html (original) +++ www/trunk/index.html Wed Aug 24 10:55:19 2011 @@ -69,8 +69,8 @@ blazing fast and much more memory efficient than GDB at loading symbols.

-

  • The libc++ and libc++ ABI projects provide +

  • The libc++ and + libc++ ABI projects provide a standard conformant and high-performance implementation of the C++ Standard Library, including full support for C++'0x.

    • @@ -86,7 +86,7 @@

  • The klee project implements a "symbolic virtual machine" which uses a theorem prover to try to evaluate - all dynamic paths through a program, in an effort to find bugs and to prove + all dynamic paths through a program in an effort to find bugs and to prove properties of functions. A major feature of klee is that it can produce a testcase in the event that it detects a bug.

    • From echristo at apple.com Wed Aug 24 11:01:31 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 24 Aug 2011 09:01:31 -0700 Subject: [llvm-commits] [llvm] r138366 - in /llvm/trunk: include/llvm/Constant.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll In-Reply-To: References: <20110823201110.8C91D2A6C12C@llvm.org> <6594DDFF12B03D4E89690887C2486994029705F772@hasmsx504.ger.corp.intel.com> Message-ID: <7D11A511-825D-4C95-9740-D050382FFC09@apple.com> On Aug 24, 2011, at 8:36 AM, Eli Friedman wrote: > On Wed, Aug 24, 2011 at 2:22 AM, Rotem, Nadav wrote: >> It looks like the crash is because getNullValue is not implemented for MMX types. The new constantfolding optimization triggered this bug. >> >> What's the plan for MMX types ? Should I add support to getNullValue ? > > It's probably a bug if we're trying to constant-fold MMX types; it's > not worth the effort to make that work. Totally agreed. -eric From criswell at illinois.edu Wed Aug 24 11:06:44 2011 From: criswell at illinois.edu (John Criswell) Date: Wed, 24 Aug 2011 11:06:44 -0500 Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project Message-ID: <4E552194.1000807@illinois.edu> Dear All, Yesterday, I asked Chris if SAFECode qualified as an LLVM sub-project, and he replied that it did. To that end, I've created a patch to add SAFECode to the list of LLVM sub-projects on the main LLVM web page. The patch is attached for review. I have commit access, so I can commit the patch once someone reviews it. Thanks in advance, John Criswell -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: wwwpatch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/4e1cf864/attachment.pl From grosbach at apple.com Wed Aug 24 11:44:18 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 16:44:18 -0000 Subject: [llvm-commits] [llvm] r138437 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <20110824164418.16C452A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 11:44:17 2011 New Revision: 138437 URL: http://llvm.org/viewvc/llvm-project?rev=138437&view=rev Log: Tidy up. Trailing whitespace. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=138437&r1=138436&r2=138437&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Aug 24 11:44:17 2011 @@ -51,7 +51,7 @@ /// explicitly nulled out. void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { assert(isReg() && "Can only add reg operand to use lists"); - + // If the reginfo pointer is null, just explicitly null out or next/prev // pointers, to ensure they are not garbage. if (RegInfo == 0) { @@ -59,23 +59,23 @@ Contents.Reg.Next = 0; return; } - + // Otherwise, add this operand to the head of the registers use/def list. MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); - + // For SSA values, we prefer to keep the definition at the start of the list. // we do this by skipping over the definition if it is at the head of the // list. if (*Head && (*Head)->isDef()) Head = &(*Head)->Contents.Reg.Next; - + Contents.Reg.Next = *Head; if (Contents.Reg.Next) { assert(getReg() == Contents.Reg.Next->getReg() && "Different regs on the same list!"); Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; } - + Contents.Reg.Prev = Head; *Head = this; } @@ -86,7 +86,7 @@ assert(isOnRegUseList() && "Reg operand is not on a use list"); // Unlink this from the doubly linked list of operands. MachineOperand *NextOp = Contents.Reg.Next; - *Contents.Reg.Prev = NextOp; + *Contents.Reg.Prev = NextOp; if (NextOp) { assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); NextOp->Contents.Reg.Prev = Contents.Reg.Prev; @@ -97,7 +97,7 @@ void MachineOperand::setReg(unsigned Reg) { if (getReg() == Reg) return; // No change. - + // Otherwise, we have to change the register. If this operand is embedded // into a machine function, we need to update the old and new register's // use/def lists. @@ -109,7 +109,7 @@ AddRegOperandToRegInfo(&MF->getRegInfo()); return; } - + // Otherwise, just change the register, no problem. :) SmallContents.RegNo = Reg; } @@ -144,7 +144,7 @@ if (isReg() && getParent() && getParent()->getParent() && getParent()->getParent()->getParent()) RemoveRegOperandFromRegInfo(); - + OpKind = MO_Immediate; Contents.ImmVal = ImmVal; } @@ -155,7 +155,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) { - // If this operand is already a register operand, use setReg to update the + // If this operand is already a register operand, use setReg to update the // register's use/def lists. if (isReg()) { assert(!isEarlyClobber()); @@ -189,7 +189,7 @@ if (getType() != Other.getType() || getTargetFlags() != Other.getTargetFlags()) return false; - + switch (getType()) { default: llvm_unreachable("Unrecognized operand type"); case MachineOperand::MO_Register: @@ -322,7 +322,7 @@ default: llvm_unreachable("Unrecognized operand type"); } - + if (unsigned TF = getTargetFlags()) OS << "[TF=" << TF << ']'; } @@ -408,7 +408,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { assert((MMO.isLoad() || MMO.isStore()) && "SV has to be a load, store or both."); - + if (MMO.isVolatile()) OS << "Volatile "; @@ -417,7 +417,7 @@ if (MMO.isStore()) OS << "ST"; OS << MMO.getSize(); - + // Print the address information. OS << "["; if (!MMO.getValue()) @@ -510,7 +510,7 @@ } /// MachineInstr ctor - Work exactly the same as the ctor two above, except -/// that the MachineInstr is created and added to the end of the specified +/// that the MachineInstr is created and added to the end of the specified /// basic block. MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), @@ -605,7 +605,7 @@ /// addOperand - Add the specified operand to the instruction. If it is an /// implicit operand, it is added to the end of the operand list. If it is /// an explicit operand it is added at the end of the explicit operand list -/// (before the first implicit operand). +/// (before the first implicit operand). void MachineInstr::addOperand(const MachineOperand &Op) { bool isImpReg = Op.isReg() && Op.isImplicit(); assert((isImpReg || !OperandsComplete()) && @@ -620,10 +620,10 @@ // reallocate. if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { Operands.push_back(Op); - + // Set the parent of the operand. Operands.back().ParentMI = this; - + // If the operand is a register, update the operand's use list. if (Op.isReg()) { Operands.back().AddRegOperandToRegInfo(RegInfo); @@ -635,7 +635,7 @@ return; } } - + // Otherwise, we have to insert a real operand before any implicit ones. unsigned OpNo = Operands.size()-NumImplicitOps; @@ -660,7 +660,7 @@ // list, add the operand, then add the register operands back to their use // list. This also must handle the case when the operand list reallocates // to somewhere else. - + // If insertion of this operand won't cause reallocation of the operand // list, just remove the implicit operands, add the operand, then re-add all // the rest of the operands. @@ -668,7 +668,7 @@ assert(Operands[i].isReg() && "Should only be an implicit reg!"); Operands[i].RemoveRegOperandFromRegInfo(); } - + // Add the operand. If it is a register, add it to the reg list. Operands.insert(Operands.begin()+OpNo, Op); Operands[OpNo].ParentMI = this; @@ -679,7 +679,7 @@ if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) Operands[OpNo].setIsEarlyClobber(true); } - + // Re-add all the implicit ops. for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { assert(Operands[i].isReg() && "Should only be an implicit reg!"); @@ -690,10 +690,10 @@ // operands from their list, then readd them after the operand list is // reallocated. RemoveRegOperandsFromUseLists(); - + Operands.insert(Operands.begin()+OpNo, Op); Operands[OpNo].ParentMI = this; - + // Re-add all the operands. AddRegOperandsToUseLists(*RegInfo); @@ -709,13 +709,13 @@ /// void MachineInstr::RemoveOperand(unsigned OpNo) { assert(OpNo < Operands.size() && "Invalid operand number"); - + // Special case removing the last one. if (OpNo == Operands.size()-1) { // If needed, remove from the reg def/use list. if (Operands.back().isReg() && Operands.back().isOnRegUseList()) Operands.back().RemoveRegOperandFromRegInfo(); - + Operands.pop_back(); return; } @@ -730,7 +730,7 @@ Operands[i].RemoveRegOperandFromRegInfo(); } } - + Operands.erase(Operands.begin()+OpNo); if (RegInfo) { @@ -951,7 +951,7 @@ return -1; } - + /// isRegTiedToUseOperand - Given the index of a register def operand, /// check if the register def is tied to a source operand, due to either /// two-address elimination or inline assembly constraints. Returns the @@ -1212,7 +1212,7 @@ // conservatively assume it wasn't preserved. if (memoperands_empty()) return true; - + // Check the memory reference information for volatile references. for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) if ((*I)->isVolatile()) @@ -1319,7 +1319,7 @@ dbgs() << " " << *this; } -static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, +static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, raw_ostream &CommentOS) { const LLVMContext &Ctx = MF->getFunction()->getContext(); if (!DL.isUnknown()) { // Print source line info. @@ -1640,7 +1640,7 @@ // new implicit operand if required. if (Found || !AddIfNotFound) return Found; - + addOperand(MachineOperand::CreateReg(IncomingReg, true /*IsDef*/, true /*IsImp*/, From tonic at nondot.org Wed Aug 24 12:08:33 2011 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 24 Aug 2011 17:08:33 -0000 Subject: [llvm-commits] [www] r138440 - /www/trunk/demo/index.cgi Message-ID: <20110824170833.C9A252A6C12C@llvm.org> Author: tbrethou Date: Wed Aug 24 12:08:33 2011 New Revision: 138440 URL: http://llvm.org/viewvc/llvm-project?rev=138440&view=rev Log: Add colored diagnostics. Patch by David Blaikie! Modified: www/trunk/demo/index.cgi Modified: www/trunk/demo/index.cgi URL: http://llvm.org/viewvc/llvm-project/www/trunk/demo/index.cgi?rev=138440&r1=138439&r2=138440&view=diff ============================================================================== --- www/trunk/demo/index.cgi (original) +++ www/trunk/demo/index.cgi Wed Aug 24 12:08:33 2011 @@ -16,7 +16,7 @@ if ( !-d $ROOT ) { mkdir( $ROOT, 0777 ); } my $LOGFILE = "$ROOT/log.txt"; -my $FORM_URL = 'index.cgi'; +my $FORM_URL = 'test.cgi'; my $MAILADDR = 'sabre at nondot.org'; my $CONTACT_ADDRESS = 'Questions or comments? Email the LLVMdev mailing list.'; my $LOGO_IMAGE_URL = '../img/DragonSmall.png'; @@ -70,6 +70,12 @@ close LOG; } +sub syntaxHighlightConsoleOutput { + my ($input) = @_; + $input =~ s@\033\[(?:\d;)?(\d);?((?:\d\d)?)m@@g; + return $input; +} + sub dumpFile { my ( $header, $file ) = @_; my $result; @@ -80,7 +86,7 @@ close FILE; my $UnhilightedResult = $result; my $HtmlResult = - "

    $header

    \n
    \n" . $c->escapeHTML($result) . "\n
    \n"; + "

    $header

    \n
    \n" . syntaxHighlightConsoleOutput($c->escapeHTML($result)) . "\n
    \n"; if (wantarray) { return ( $UnhilightedResult, $HtmlResult ); } @@ -367,7 +373,7 @@ $options .= " -O3" if $c->param('optlevel') ne "None"; try_run( "llvm C/C++ front-end (clang)", - "clang -emit-llvm -msse3 -W -Wall $options $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", + "clang -fcolor-diagnostics -emit-llvm -msse3 -W -Wall $options $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", $outputFile ); if ( $c->param('showstats') && -s $timerFile ) { From resistor at mac.com Wed Aug 24 12:08:34 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Aug 2011 17:08:34 -0000 Subject: [llvm-commits] [llvm] r138441 - /llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110824170835.00E112A6C12D@llvm.org> Author: resistor Date: Wed Aug 24 12:08:34 2011 New Revision: 138441 URL: http://llvm.org/viewvc/llvm-project?rev=138441&view=rev Log: Port over more encoding tests to decoding tests. Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138441&r1=138440&r2=138441&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Wed Aug 24 12:08:34 2011 @@ -343,3 +343,151 @@ 0x58 0xb6 0x50 0xb6 + +#------------------------------------------------------------------------------ +# STM +#------------------------------------------------------------------------------ +# CHECK: stm r1!, {r2, r6} +# CHECK: stm r1!, {r1, r2, r3, r7} + +0x44 0xc1 +0x8e 0xc1 + + +#------------------------------------------------------------------------------ +# STR (immediate) +#------------------------------------------------------------------------------ +# CHECK: str r2, [r7] +# CHECK: str r2, [r7] +# CHECK: str r5, [r1, #4] +# CHECK: str r3, [r7, #124] +# CHECK: str r2, [sp] +# CHECK: str r3, [sp] +# CHECK: str r4, [sp, #20] +# CHECK: str r5, [sp, #1020] + +0x3a 0x60 +0x3a 0x60 +0x4d 0x60 +0xfb 0x67 +0x00 0x92 +0x00 0x93 +0x05 0x94 +0xff 0x95 + + +#------------------------------------------------------------------------------ +# STR (register) +#------------------------------------------------------------------------------ +# CHECK: str r2, [r7, r3] + +0xfa 0x50 + + +#------------------------------------------------------------------------------ +# STRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: strb r4, [r3] +# CHECK: strb r5, [r6] +# CHECK: strb r6, [r7, #31] + +0x1c 0x70 +0x35 0x70 +0xfe 0x77 + + +#------------------------------------------------------------------------------ +# STRB (register) +#------------------------------------------------------------------------------ +# CHECK: strb r6, [r4, r5] + +0x66 0x55 + + +#------------------------------------------------------------------------------ +# STRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: strh r3, [r3] +# CHECK: strh r4, [r6, #2] +# CHECK: strh r5, [r7, #62] + +0x1b 0x80 +0x74 0x80 +0xfd 0x87 + + +#------------------------------------------------------------------------------ +# STRH (register) +#------------------------------------------------------------------------------ +# CHECK: strh r6, [r2, r6] + +0x96 0x53 + + +#------------------------------------------------------------------------------ +# SUB (immediate) +#------------------------------------------------------------------------------ +# CHECK: subs r1, r2, #3 +# CHECK: subs r2, #3 +# CHECK: subs r2, #8 + +0xd1 0x1e +0x03 0x3a +0x08 0x3a + +#------------------------------------------------------------------------------ +# SUB (register) +#------------------------------------------------------------------------------ +# CHECK: subs r1, r2, r3 + +0xd1 0x1a + + +#------------------------------------------------------------------------------ +# SVC +#------------------------------------------------------------------------------ +# CHECK: svc #0 +# CHECK: svc #255 + +0x00 0xdf +0xff 0xdf + + +#------------------------------------------------------------------------------ +# SXTB/SXTH +#------------------------------------------------------------------------------ +# CHECK: sxtb r3, r5 +# CHECK: sxth r3, r5 + +0x6b 0xb2 +0x2b 0xb2 + + +#------------------------------------------------------------------------------ +# TST +#------------------------------------------------------------------------------ +# CHECK: tst r6, r1 + +0x0e 0x42 + + +#------------------------------------------------------------------------------ +# UXTB/UXTH +#------------------------------------------------------------------------------ +# CHECK: uxtb r7, r2 +# CHECK: uxth r1, r4 + +0xd7 0xb2 +0xa1 0xb2 + + +#------------------------------------------------------------------------------ +# WFE/WFI/YIELD +#------------------------------------------------------------------------------ +# CHECK: wfe +# CHECK: wfi +# CHECK: yield + +0x20 0xbf +0x30 0xbf +0x10 0xbf From resistor at mac.com Wed Aug 24 12:21:44 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Aug 2011 17:21:44 -0000 Subject: [llvm-commits] [llvm] r138443 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb2.td Disassembler/ARMDisassembler.cpp Message-ID: <20110824172144.2A1D92A6C12C@llvm.org> Author: resistor Date: Wed Aug 24 12:21:43 2011 New Revision: 138443 URL: http://llvm.org/viewvc/llvm-project?rev=138443&view=rev Log: Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138443&r1=138442&r2=138443&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 24 12:21:43 2011 @@ -14,6 +14,7 @@ // IT block predicate field def it_pred : Operand { let PrintMethod = "printMandatoryPredicateOperand"; + let DecoderMethod = "DecodeITCond"; } // IT block condition mask Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138443&r1=138442&r2=138443&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 24 12:21:43 2011 @@ -228,6 +228,8 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" #include "ARMGenInstrInfo.inc" @@ -3289,3 +3291,15 @@ return S; } +static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond, + uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + if (Cond == 0xF) { + Cond = 0xE; + CHECK(S, Unpredictable); + } + + Inst.addOperand(MCOperand::CreateImm(Cond)); + return S; +} + From grosbach at apple.com Wed Aug 24 12:46:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 17:46:13 -0000 Subject: [llvm-commits] [llvm] r138445 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/Thumb1FrameLowering.cpp lib/Target/ARM/Thumb1RegisterInfo.cpp lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/EDEmitter.cpp Message-ID: <20110824174614.18E532A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 12:46:13 2011 New Revision: 138445 URL: http://llvm.org/viewvc/llvm-project?rev=138445&view=rev Log: Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Aug 24 12:46:13 2011 @@ -1098,11 +1098,11 @@ MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this)); - MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) - .addFrameIndex(FrameIdx).addImm(Offset); + MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) + .addFrameIndex(FrameIdx).addImm(Offset)); if (!AFI->isThumb1OnlyFunction()) - AddDefaultCC(AddDefaultPred(MIB)); + AddDefaultCC(MIB); } void Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Aug 24 12:46:13 2011 @@ -2338,8 +2338,9 @@ int FI = cast(N)->getIndex(); SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); if (Subtarget->isThumb1Only()) { - return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, - CurDAG->getTargetConstant(0, MVT::i32)); + SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), + getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; + return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4); } else { unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? ARM::t2ADDri : ARM::ADDri); Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 12:46:13 2011 @@ -305,8 +305,8 @@ // This is rematerializable, which is particularly useful for taking the // address of locals. let isReMaterializable = 1 in -def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, - "add\t$dst, $sp, $rhs", []>, +def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm_s4:$rhs), IIC_iALUi, + "add", "\t$dst, $sp, $rhs", []>, T1Encoding<{1,0,1,0,1,?}> { // A6.2 & A8.6.8 bits<3> dst; @@ -317,8 +317,8 @@ } // ADD sp, sp, # -def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, - "add\t$dst, $rhs", []>, +def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs), + IIC_iALUi, "add", "\t$Rdn, $rhs", []>, T1Misc<{0,0,0,0,0,?,?}> { // A6.2.5 & A8.6.8 bits<7> rhs; @@ -328,8 +328,8 @@ // SUB sp, sp, # // FIXME: The encoding and the ASM string don't match up. -def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, - "sub\t$dst, $rhs", []>, +def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs), + IIC_iALUi, "sub", "\t$Rdn, $rhs", []>, T1Misc<{0,0,0,0,1,?,?}> { // A6.2.5 & A8.6.214 bits<7> rhs; @@ -338,25 +338,25 @@ } // ADD , sp -def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, - "add\t$dst, $rhs", []>, +def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$rhs), IIC_iALUr, + "add", "\t$Rdn, $rhs", []>, T1Special<{0,0,?,?}> { // A8.6.9 Encoding T1 - bits<4> dst; - let Inst{7} = dst{3}; + bits<4> Rdn; + let Inst{7} = Rdn{3}; let Inst{6-3} = 0b1101; - let Inst{2-0} = dst{2-0}; + let Inst{2-0} = Rdn{2-0}; let DecoderMethod = "DecodeThumbAddSPReg"; } // ADD sp, -def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, - "add\t$dst, $rhs", []>, +def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$rhs), IIC_iALUr, + "add", "\t$Rdn, $rhs", []>, T1Special<{0,0,?,?}> { // A8.6.9 Encoding T2 - bits<4> dst; + bits<4> Rdn; let Inst{7} = 1; - let Inst{6-3} = dst; + let Inst{6-3} = Rdn; let Inst{2-0} = 0b101; let DecoderMethod = "DecodeThumbAddSPReg"; } Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Wed Aug 24 12:46:13 2011 @@ -225,6 +225,13 @@ }]; } +// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the +// implied SP argument list. +// FIXME: It would be better to not use this at all and refactor the +// instructions to not have SP an an explicit argument. That makes +// frame index resolution a bit trickier, though. +def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; + // restricted GPR register class. Many Thumb2 instructions allow the full // register range for operands, but have undefined behaviours when PC // or SP (R13 or R15) are used. The ARM ISA refers to these operands Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Wed Aug 24 12:46:13 2011 @@ -133,9 +133,9 @@ // Adjust FP so it point to the stack slot that contains the previous FP. if (hasFP(MF)) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) .addFrameIndex(FramePtrSpillFI).addImm(0) - .setMIFlags(MachineInstr::FrameSetup); + .setMIFlags(MachineInstr::FrameSetup)); if (NumBytes > 508) // If offset is > 508 then sp cannot be adjusted in a single instruction, // try restoring from fp instead. Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Aug 24 12:46:13 2011 @@ -181,7 +181,6 @@ int Opc = 0; int ExtraOpc = 0; bool NeedCC = false; - bool NeedPred = false; if (DestReg == BaseReg && BaseReg == ARM::SP) { assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); @@ -216,7 +215,7 @@ } else { Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; NumBits = 8; - NeedPred = NeedCC = true; + NeedCC = true; } isTwoAddr = true; } @@ -262,8 +261,7 @@ if (NeedCC) MIB = AddDefaultT1CC(MIB); MIB.addReg(DestReg).addImm(ThisVal); - if (NeedPred) - MIB = AddDefaultPred(MIB); + MIB = AddDefaultPred(MIB); MIB.setMIFlags(MIFlags); } else { bool isKill = BaseReg != ARM::SP; @@ -271,8 +269,7 @@ if (NeedCC) MIB = AddDefaultT1CC(MIB); MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); - if (NeedPred) - MIB = AddDefaultPred(MIB); + MIB = AddDefaultPred(MIB); MIB.setMIFlags(MIFlags); BaseReg = DestReg; @@ -284,7 +281,7 @@ Scale = 1; Chunk = ((1 << NumBits) - 1) * Scale; Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; - NeedPred = NeedCC = isTwoAddr = true; + NeedCC = isTwoAddr = true; } } } @@ -404,7 +401,6 @@ unsigned Scale = 1; if (FrameReg != ARM::SP) { Opcode = ARM::tADDi3; - MI.setDesc(TII.get(Opcode)); NumBits = 3; } else { NumBits = 8; @@ -418,10 +414,9 @@ // Turn it into a move. MI.setDesc(TII.get(ARM::tMOVr)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); - // Remove offset and add predicate operands. + // Remove offset MI.RemoveOperand(FrameRegIdx+1); MachineInstrBuilder MIB(&MI); - AddDefaultPred(MIB); return true; } @@ -430,6 +425,7 @@ if (((Offset / Scale) & ~Mask) == 0) { // Replace the FrameIndex with sp / fp if (Opcode == ARM::tADDi3) { + MI.setDesc(TII.get(Opcode)); removeOperands(MI, FrameRegIdx); MachineInstrBuilder MIB(&MI); AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg) @@ -478,10 +474,6 @@ MI.setDesc(TII.get(ARM::tADDhirr)); MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true); MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false); - if (Opcode == ARM::tADDi3) { - MachineInstrBuilder MIB(&MI); - AddDefaultPred(MIB); - } } return true; } else { Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Aug 24 12:46:13 2011 @@ -235,9 +235,8 @@ if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?"); Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; - // FIXME: Fix Thumb1 immediate encoding. - BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) - .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) + .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags)); NumBytes = 0; continue; } Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Aug 24 12:46:13 2011 @@ -507,6 +507,7 @@ .addOperand(MI->getOperand(0)) .addOperand(MI->getOperand(1)) .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. + AddDefaultPred(MIB); // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=138445&r1=138444&r2=138445&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Aug 24 12:46:13 2011 @@ -556,6 +556,7 @@ REG("GPR"); REG("rGPR"); REG("GPRnopc"); + REG("GPRsp"); REG("tcGPR"); REG("cc_out"); REG("s_cc_out"); From baldrick at free.fr Wed Aug 24 12:58:02 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Aug 2011 17:58:02 -0000 Subject: [llvm-commits] [dragonegg] r138447 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp Message-ID: <20110824175802.177232A6C12C@llvm.org> Author: baldrick Date: Wed Aug 24 12:58:01 2011 New Revision: 138447 URL: http://llvm.org/viewvc/llvm-project?rev=138447&view=rev Log: Move to the new exception handling scheme: landingpad and resume instructions rather than eh.exception, eh.selector and explicit _Unwind_Resume calls. Based on a patch by Bill Wendling. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=138447&r1=138446&r2=138447&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Wed Aug 24 12:58:01 2011 @@ -332,12 +332,6 @@ /// run if an exception is thrown in this region). SmallVector FailureBlocks; - /// RewindBB - Block containing code that continues unwinding an exception. - BasicBlock *RewindBB; - - /// RewindTmp - Local holding the exception to continue unwinding. - AllocaInst *RewindTmp; - public: TreeToLLVM(tree_node *fndecl); ~TreeToLLVM(); @@ -460,10 +454,6 @@ /// an exception is thrown in a must-not-throw region. void EmitFailureBlocks(); - /// EmitRewindBlock - Emit the block containing code to continue unwinding an - /// exception. - void EmitRewindBlock(); - /// EmitDebugInfo - Return true if debug info is to be emitted for current /// function. bool EmitDebugInfo(); Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=138447&r1=138446&r2=138447&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed Aug 24 12:58:01 2011 @@ -164,8 +164,6 @@ Fn = 0; ReturnBB = 0; ReturnOffset = 0; - RewindBB = 0; - RewindTmp = 0; if (EmitDebugInfo()) { expanded_location Location = expand_location(DECL_SOURCE_LOCATION (fndecl)); @@ -952,7 +950,6 @@ // Now that phi nodes have been output, emit pending exception handling code. EmitLandingPads(); EmitFailureBlocks(); - EmitRewindBlock(); if (EmitDebugInfo()) { // FIXME: This should be output just before the return call generated above. @@ -1955,8 +1952,8 @@ // If a GCC post landing pad is shared by several exception handling regions, // or if there is a normal edge to it, then create LLVM landing pads for each - // eh region. Calls to eh.exception and eh.selector will then go in the LLVM - // landing pad, which branches to the GCC post landing pad. + // eh region. The landing pad instruction will then go in the LLVM landing + // pad, which then branches to the GCC post landing pad. for (unsigned LPadNo = 1; LPadNo < NormalInvokes.size(); ++LPadNo) { // Get the list of invokes for this GCC landing pad. SmallVector &InvokesForPad = NormalInvokes[LPadNo]; @@ -2023,15 +2020,12 @@ BranchInst::Create(PostPad, LPad); } - // Initialize the exception pointer and selector value for each exception - // handling region at the start of the corresponding landing pad. At this - // point each exception handling region has its own landing pad, which is - // only reachable via the unwind edges of the region's invokes. - std::vector Args; - Function *ExcIntr = Intrinsic::getDeclaration(TheModule, - Intrinsic::eh_exception); - Function *SlctrIntr = Intrinsic::getDeclaration(TheModule, - Intrinsic::eh_selector); + // Create the landing pad instruction for each exception handling region at + // the start of the corresponding landing pad. At this point each exception + // handling region has its own landing pad, which is only reachable via the + // unwind edges of the region's invokes. + Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(), + Builder.getInt32Ty(), NULL); for (unsigned LPadNo = 1; LPadNo < NormalInvokes.size(); ++LPadNo) { // Get the list of invokes for this GCC landing pad. SmallVector &InvokesForPad = NormalInvokes[LPadNo]; @@ -2050,96 +2044,76 @@ // Insert instructions at the start of the landing pad, but after any phis. Builder.SetInsertPoint(LPad, LPad->getFirstNonPHI()); - // Fetch the exception pointer. - Value *ExcPtr = Builder.CreateCall(ExcIntr, "exc_ptr"); - - // Store it if made use of elsewhere. - if (RegionNo < ExceptionPtrs.size() && ExceptionPtrs[RegionNo]) - Builder.CreateStore(ExcPtr, ExceptionPtrs[RegionNo]); - - // Get the exception selector. The first argument is the exception pointer. - Args.push_back(ExcPtr); - - // It is followed by the personality function. + // Create the landingpad instruction without any clauses. Clauses are added + // below. tree personality = DECL_FUNCTION_PERSONALITY(FnDecl); if (!personality) { assert(function_needs_eh_personality(cfun) == eh_personality_any && "No exception handling personality!"); personality = lang_hooks.eh_personality(); } - Args.push_back(Builder.CreateBitCast(DECL_LLVM(personality), - Type::getInt8PtrTy(Context))); + LandingPadInst *LPadInst = Builder.CreateLandingPad(UnwindDataTy, + DECL_LLVM(personality), + 0, "exc"); + + // Store the exception pointer if made use of elsewhere. + if (RegionNo < ExceptionPtrs.size() && ExceptionPtrs[RegionNo]) { + Value *ExcPtr = Builder.CreateExtractValue(LPadInst, 0, "exc_ptr"); + Builder.CreateStore(ExcPtr, ExceptionPtrs[RegionNo]); + } - Constant *CatchAll = TheModule->getGlobalVariable("llvm.eh.catch.all.value"); - if (!CatchAll) { - // The representation of a catch-all is language specific. - // TODO: Remove this hack. - Constant *Init = 0; - StringRef LanguageName = lang_hooks.name; - if (LanguageName == "GNU Ada") { - StringRef Name = "__gnat_all_others_value"; - Init = TheModule->getGlobalVariable(Name); - if (!Init) - Init = new GlobalVariable(*TheModule, ConvertType(integer_type_node), - /*isConstant*/true, - GlobalValue::ExternalLinkage, - /*Initializer*/NULL, Name); - } else { - // Other languages use a null pointer. - Init = Constant::getNullValue(Type::getInt8PtrTy(Context)); - } - CatchAll = new GlobalVariable(*TheModule, Init->getType(), true, - GlobalVariable::LinkOnceAnyLinkage, - Init, "llvm.eh.catch.all.value"); - cast(CatchAll)->setSection("llvm.metadata"); - AttributeUsedGlobals.insert(CatchAll); + // Store the selector value if made use of elsewhere. + if (RegionNo < ExceptionFilters.size() && ExceptionFilters[RegionNo]) { + Value *Filter = Builder.CreateExtractValue(LPadInst, 1, "filter"); + Builder.CreateStore(Filter, ExceptionFilters[RegionNo]); } - bool AllCaught = false; // Did we saw a catch-all or no-throw? - bool HasCleanup = false; // Did we see a cleanup? + // Add clauses to the landing pad instruction. + bool AllCaught = false; // Did we see a catch-all or no-throw? SmallSet AlreadyCaught; // Typeinfos known caught already. for (; region && !AllCaught; region = region->outer) switch (region->type) { case ERT_ALLOWED_EXCEPTIONS: { - // Filter. - - // Push a fake placeholder value for the length. The real length is - // computed below, once we know which typeinfos we are going to use. - unsigned LengthIndex = Args.size(); - Args.push_back(NULL); // Fake length value. - - // Add the type infos. + // Filter. Compute the list of type infos. AllCaught = true; + std::vector TypeInfos; for (tree type = region->u.allowed.type_list; type; type = TREE_CHAIN(type)) { Constant *TypeInfo = ConvertTypeInfo(TREE_VALUE(type)); - // No point in permitting a typeinfo to be thrown if we know it can - // never reach the filter. + // No point in letting a typeinfo through if we know it can't reach + // the filter in the first place. if (AlreadyCaught.count(TypeInfo)) continue; - Args.push_back(TypeInfo); + TypeInfo = TheFolder->CreateBitCast(TypeInfo, Builder.getInt8PtrTy()); + TypeInfos.push_back(TypeInfo); AllCaught = false; } - // The length is one more than the number of typeinfos. - Args[LengthIndex] = Builder.getInt32(Args.size() - LengthIndex); + // Add the list of typeinfos as a filter clause. + ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(), + TypeInfos.size()); + LPadInst->addClause(ConstantArray::get(FilterTy, TypeInfos)); break; } case ERT_CLEANUP: - HasCleanup = true; + LPadInst->setCleanup(true); break; - case ERT_MUST_NOT_THROW: - // Same as a zero-length filter. + case ERT_MUST_NOT_THROW: { + // Same as a zero-length filter: add an empty filter clause. + ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(), 0); + LPadInst->addClause(ConstantArray::get(FilterTy, + ArrayRef())); AllCaught = true; - Args.push_back(Builder.getInt32(1)); break; + } case ERT_TRY: // Catches. for (eh_catch c = region->u.eh_try.first_catch; c ; c = c->next_catch) if (!c->type_list) { - // Catch-all - push a null pointer. + // Catch-all - add a null pointer as a catch clause. + LPadInst->addClause(Constant::getNullValue(Builder.getInt8PtrTy())); AllCaught = true; - Args.push_back(Constant::getNullValue(Type::getInt8PtrTy(Context))); + break; } else { // Add the type infos. for (tree type = c->type_list; type; type = TREE_CHAIN(type)) { @@ -2147,36 +2121,11 @@ // No point in trying to catch a typeinfo that was already caught. if (!AlreadyCaught.insert(TypeInfo)) continue; - Args.push_back(TypeInfo); - AllCaught = TypeInfo == CatchAll; - if (AllCaught) - break; + LPadInst->addClause(TypeInfo); } } break; } - - if (HasCleanup) { - if (Args.size() == 2) - // Insert a sentinel indicating that this is a cleanup-only selector. - Args.push_back(Builder.getInt32(0)); - else if (!AllCaught) - // Some exceptions from this region may not be caught by any handler. - // Since invokes are required to branch to the unwind label no matter - // what exception is being unwound, append a catch-all. I have a plan - // that will make all such horrible hacks unnecessary, but unfortunately - // this comment is too short to explain it. - Args.push_back(CatchAll); - } - - // Emit the selector call. - Value *Filter = Builder.CreateCall(SlctrIntr, Args, "filter"); - - // Store it if made use of elsewhere. - if (RegionNo < ExceptionFilters.size() && ExceptionFilters[RegionNo]) - Builder.CreateStore(Filter, ExceptionFilters[RegionNo]); - - Args.clear(); } NormalInvokes.clear(); @@ -2226,23 +2175,17 @@ if (LandingPad) { BeginBlock(LandingPad); - // Generate an empty (i.e. catch-all) filter in the landing pad. - Function *ExcIntr = Intrinsic::getDeclaration(TheModule, - Intrinsic::eh_exception); - Function *SlctrIntr = Intrinsic::getDeclaration(TheModule, - Intrinsic::eh_selector); - Value *Args[3]; - // The exception pointer. - Args[0] = Builder.CreateCall(ExcIntr, "exc_ptr"); - // The personality function. + // Generate a landingpad instruction with an empty (i.e. catch-all) filter + // clause. + Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(), + Builder.getInt32Ty(), NULL); tree personality = DECL_FUNCTION_PERSONALITY(FnDecl); assert(personality && "No-throw region but no personality function!"); - Args[1] = Builder.CreateBitCast(DECL_LLVM(personality), - Type::getInt8PtrTy(Context)); - // One more than the filter length. - Args[2] = Builder.getInt32(1); - // Create the selector call. - Builder.CreateCall(SlctrIntr, Args, "filter"); + LandingPadInst *LPadInst = + Builder.CreateLandingPad(UnwindDataTy, DECL_LLVM(personality), 1, + "exc"); + ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(), 0); + LPadInst->addClause(ConstantArray::get(FilterTy, ArrayRef())); if (LandingPad != FailureBlock) { // Make sure all invokes unwind to the new landing pad. @@ -2279,34 +2222,6 @@ } } -/// EmitRewindBlock - Emit the block containing code to continue unwinding an -/// exception. -void TreeToLLVM::EmitRewindBlock() { - if (!RewindBB) - return; - - BeginBlock (RewindBB); - - // The exception pointer to continue unwinding. - assert(RewindTmp && "Rewind block but nothing to unwind?"); - Value *ExcPtr = Builder.CreateLoad(RewindTmp); - - // Generate an explicit call to _Unwind_Resume_or_Rethrow. - // FIXME: On ARM this should be a call to __cxa_end_cleanup with no arguments. - std::vector Params(1, Type::getInt8PtrTy(Context)); - FunctionType *FTy = FunctionType::get(Type::getVoidTy(Context), Params, - false); - Constant *RewindFn = - TheModule->getOrInsertFunction("_Unwind_Resume_or_Rethrow", FTy); - - // Pass it to _Unwind_Resume_or_Rethrow. - CallInst *Rewind = Builder.CreateCall(RewindFn, ExcPtr); - - // This call does not return. - Rewind->setDoesNotReturn(); - Builder.CreateUnreachable(); -} - //===----------------------------------------------------------------------===// // ... Expressions ... @@ -8135,7 +8050,7 @@ if (!AlreadyCaught.insert(TypeInfo)) continue; - TypeInfo = Builder.CreateBitCast(TypeInfo, Type::getInt8PtrTy(Context)); + TypeInfo = Builder.CreateBitCast(TypeInfo, Builder.getInt8PtrTy()); // Call get eh type id. Value *TypeID = Builder.CreateCall(TypeIDIntr, TypeInfo, "typeid"); @@ -8220,18 +8135,15 @@ return; } - // The exception unwinds out of the function. Note the exception to unwind. - if (!RewindTmp) { - RewindTmp = CreateTemporary(Type::getInt8PtrTy(Context)); - RewindTmp->setName("rewind_tmp"); - } + // Unwind the exception out of the function using a resume instruction. Value *ExcPtr = Builder.CreateLoad(getExceptionPtr(src_rgn->index)); - Builder.CreateStore(ExcPtr, RewindTmp); - - // Jump to the block containing the rewind code. - if (!RewindBB) - RewindBB = BasicBlock::Create(Context, "rewind"); - Builder.CreateBr(RewindBB); + Value *Filter = Builder.CreateLoad(getExceptionFilter(src_rgn->index)); + Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(), + Builder.getInt32Ty(), NULL); + Value *UnwindData = UndefValue::get(UnwindDataTy); + UnwindData = Builder.CreateInsertValue(UnwindData, ExcPtr, 0, "exc_ptr"); + UnwindData = Builder.CreateInsertValue(UnwindData, Filter, 1, "filter"); + Builder.CreateResume(UnwindData); } void TreeToLLVM::RenderGIMPLE_RETURN(gimple stmt) { From grosbach at apple.com Wed Aug 24 13:04:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 18:04:27 -0000 Subject: [llvm-commits] [llvm] r138448 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20110824180427.BD7A52A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 13:04:27 2011 New Revision: 138448 URL: http://llvm.org/viewvc/llvm-project?rev=138448&view=rev Log: Thumb add SP assembly syntax fix. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138448&r1=138447&r2=138448&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 13:04:27 2011 @@ -338,8 +338,8 @@ } // ADD , sp -def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$rhs), IIC_iALUr, - "add", "\t$Rdn, $rhs", []>, +def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr, + "add", "\t$Rdn, $sp, $Rn", []>, T1Special<{0,0,?,?}> { // A8.6.9 Encoding T1 bits<4> Rdn; From rafael.espindola at gmail.com Wed Aug 24 13:07:01 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 24 Aug 2011 18:07:01 -0000 Subject: [llvm-commits] [llvm] r138449 - /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Message-ID: <20110824180701.BE0EA2A6C12C@llvm.org> Author: rafael Date: Wed Aug 24 13:07:01 2011 New Revision: 138449 URL: http://llvm.org/viewvc/llvm-project?rev=138449&view=rev Log: Fix a crashing bug in SplitBlock when it is called on a block with no dominator information even though dominators were previously computed. Patch by Nick Sumner. Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=138449&r1=138448&r2=138449&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Wed Aug 24 13:07:01 2011 @@ -299,16 +299,17 @@ if (DominatorTree *DT = P->getAnalysisIfAvailable()) { // Old dominates New. New node dominates all other nodes dominated by Old. - DomTreeNode *OldNode = DT->getNode(Old); - std::vector Children; - for (DomTreeNode::iterator I = OldNode->begin(), E = OldNode->end(); - I != E; ++I) - Children.push_back(*I); + if (DomTreeNode *OldNode = DT->getNode(Old)) { + std::vector Children; + for (DomTreeNode::iterator I = OldNode->begin(), E = OldNode->end(); + I != E; ++I) + Children.push_back(*I); DomTreeNode *NewNode = DT->addNewBlock(New,Old); for (std::vector::iterator I = Children.begin(), E = Children.end(); I != E; ++I) DT->changeImmediateDominator(*I, NewNode); + } } return New; From evan.cheng at apple.com Wed Aug 24 13:08:44 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Aug 2011 18:08:44 -0000 Subject: [llvm-commits] [llvm] r138450 - in /llvm/trunk: examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ParallelJIT/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/ExecutionEngine/ lib/MC/ lib/MC/MCDisassembler/ lib/Support/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/Disassembler/ lib/Target/ARM/... Message-ID: <20110824180845.9D65D2A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 13:08:43 2011 New Revision: 138450 URL: http://llvm.org/viewvc/llvm-project?rev=138450&view=rev Log: Move TargetRegistry and TargetSelect from Target to Support where they belong. These are strictly utilities for registering targets and components. Added: llvm/trunk/include/llvm/Support/TargetRegistry.h - copied, changed from r138420, llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/include/llvm/Support/TargetSelect.h - copied, changed from r138420, llvm/trunk/include/llvm/Target/TargetSelect.h llvm/trunk/lib/Support/TargetRegistry.cpp - copied, changed from r138420, llvm/trunk/lib/Target/TargetRegistry.cpp Removed: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/include/llvm/Target/TargetSelect.h llvm/trunk/lib/Target/TargetRegistry.cpp Modified: llvm/trunk/examples/BrainF/BrainFDriver.cpp llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp llvm/trunk/examples/Fibonacci/fibonacci.cpp llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp llvm/trunk/examples/ParallelJIT/ParallelJIT.cpp llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/WinCOFFStreamer.cpp llvm/trunk/lib/Support/CMakeLists.txt llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp llvm/trunk/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinAsmPrinter.cpp llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp llvm/trunk/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp llvm/trunk/lib/Target/MBlaze/TargetInfo/MBlazeTargetInfo.cpp llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/lli/lli.cpp llvm/trunk/tools/llvm-mc/Disassembler.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp Modified: llvm/trunk/examples/BrainF/BrainFDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/BrainF/BrainFDriver.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/BrainF/BrainFDriver.cpp (original) +++ llvm/trunk/examples/BrainF/BrainFDriver.cpp Wed Aug 24 13:08:43 2011 @@ -31,9 +31,9 @@ #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/ExecutionEngine/GenericValue.h" #include "llvm/ExecutionEngine/JIT.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/raw_ostream.h" #include #include Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp (original) +++ llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Wed Aug 24 13:08:43 2011 @@ -56,11 +56,11 @@ #include "llvm/Intrinsics.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/IRBuilder.h" #include "llvm/Support/Dwarf.h" +#include "llvm/Support/TargetSelect.h" // FIXME: Although all systems tested with (Linux, OS X), do not need this // header file included. A user on ubuntu reported, undefined symbols Modified: llvm/trunk/examples/Fibonacci/fibonacci.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Fibonacci/fibonacci.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/Fibonacci/fibonacci.cpp (original) +++ llvm/trunk/examples/Fibonacci/fibonacci.cpp Wed Aug 24 13:08:43 2011 @@ -33,7 +33,7 @@ #include "llvm/ExecutionEngine/Interpreter.h" #include "llvm/ExecutionEngine/GenericValue.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" using namespace llvm; static Function *CreateFibFunction(Module *M, LLVMContext &Context) { Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original) +++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Wed Aug 24 13:08:43 2011 @@ -42,7 +42,7 @@ #include "llvm/ExecutionEngine/JIT.h" #include "llvm/ExecutionEngine/Interpreter.h" #include "llvm/ExecutionEngine/GenericValue.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/IRBuilder.h" Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp Wed Aug 24 13:08:43 2011 @@ -7,9 +7,9 @@ #include "llvm/Analysis/Verifier.h" #include "llvm/Analysis/Passes.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/IRBuilder.h" +#include "llvm/Support/TargetSelect.h" #include #include #include Modified: llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp Wed Aug 24 13:08:43 2011 @@ -7,9 +7,9 @@ #include "llvm/Analysis/Verifier.h" #include "llvm/Analysis/Passes.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/IRBuilder.h" +#include "llvm/Support/TargetSelect.h" #include #include #include Modified: llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp Wed Aug 24 13:08:43 2011 @@ -7,9 +7,9 @@ #include "llvm/Analysis/Verifier.h" #include "llvm/Analysis/Passes.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/IRBuilder.h" +#include "llvm/Support/TargetSelect.h" #include #include #include Modified: llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp Wed Aug 24 13:08:43 2011 @@ -7,9 +7,9 @@ #include "llvm/Analysis/Verifier.h" #include "llvm/Analysis/Passes.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/IRBuilder.h" +#include "llvm/Support/TargetSelect.h" #include #include #include Modified: llvm/trunk/examples/ParallelJIT/ParallelJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ParallelJIT/ParallelJIT.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/examples/ParallelJIT/ParallelJIT.cpp (original) +++ llvm/trunk/examples/ParallelJIT/ParallelJIT.cpp Wed Aug 24 13:08:43 2011 @@ -26,7 +26,7 @@ #include "llvm/ExecutionEngine/JIT.h" #include "llvm/ExecutionEngine/Interpreter.h" #include "llvm/ExecutionEngine/GenericValue.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" #include using namespace llvm; Copied: llvm/trunk/include/llvm/Support/TargetRegistry.h (from r138420, llvm/trunk/include/llvm/Target/TargetRegistry.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?p2=llvm/trunk/include/llvm/Support/TargetRegistry.h&p1=llvm/trunk/include/llvm/Target/TargetRegistry.h&r1=138420&r2=138450&rev=138450&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Support/TargetRegistry.h Wed Aug 24 13:08:43 2011 @@ -1,4 +1,4 @@ -//===-- Target/TargetRegistry.h - Target Registration -----------*- C++ -*-===// +//===-- Support/TargetRegistry.h - Target Registration ----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -16,8 +16,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETREGISTRY_H -#define LLVM_TARGET_TARGETREGISTRY_H +#ifndef LLVM_SUPPORT_TARGETREGISTRY_H +#define LLVM_SUPPORT_TARGETREGISTRY_H #include "llvm/Support/CodeGen.h" #include "llvm/ADT/Triple.h" Copied: llvm/trunk/include/llvm/Support/TargetSelect.h (from r138420, llvm/trunk/include/llvm/Target/TargetSelect.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetSelect.h?p2=llvm/trunk/include/llvm/Support/TargetSelect.h&p1=llvm/trunk/include/llvm/Target/TargetSelect.h&r1=138420&r2=138450&rev=138450&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Support/TargetSelect.h Wed Aug 24 13:08:43 2011 @@ -13,8 +13,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETSELECT_H -#define LLVM_TARGET_TARGETSELECT_H +#ifndef LLVM_SUPPORT_TARGETSELECT_H +#define LLVM_SUPPORT_TARGETSELECT_H #include "llvm/Config/llvm-config.h" Removed: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=138449&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h (removed) @@ -1,1121 +0,0 @@ -//===-- Target/TargetRegistry.h - Target Registration -----------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file exposes the TargetRegistry interface, which tools can use to access -// the appropriate target specific classes (TargetMachine, AsmPrinter, etc.) -// which have been registered. -// -// Target specific class implementations should register themselves using the -// appropriate TargetRegistry interfaces. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETREGISTRY_H -#define LLVM_TARGET_TARGETREGISTRY_H - -#include "llvm/Support/CodeGen.h" -#include "llvm/ADT/Triple.h" -#include -#include - -namespace llvm { - class AsmPrinter; - class Module; - class MCAssembler; - class MCAsmBackend; - class MCAsmInfo; - class MCAsmParser; - class MCCodeEmitter; - class MCCodeGenInfo; - class MCContext; - class MCDisassembler; - class MCInstrAnalysis; - class MCInstPrinter; - class MCInstrInfo; - class MCRegisterInfo; - class MCStreamer; - class MCSubtargetInfo; - class MCTargetAsmLexer; - class MCTargetAsmParser; - class TargetMachine; - class raw_ostream; - class formatted_raw_ostream; - - MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, - bool isVerboseAsm, - bool useLoc, bool useCFI, - MCInstPrinter *InstPrint, - MCCodeEmitter *CE, - MCAsmBackend *TAB, - bool ShowInst); - - /// Target - Wrapper for Target specific information. - /// - /// For registration purposes, this is a POD type so that targets can be - /// registered without the use of static constructors. - /// - /// Targets should implement a single global instance of this class (which - /// will be zero initialized), and pass that instance to the TargetRegistry as - /// part of their initialization. - class Target { - public: - friend struct TargetRegistry; - - typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT); - - typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T, - StringRef TT); - typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, - Reloc::Model RM, - CodeModel::Model CM); - typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); - typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info); - typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, - StringRef CPU, - StringRef Features); - typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, - StringRef TT, - StringRef CPU, - StringRef Features, - Reloc::Model RM, - CodeModel::Model CM); - typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, - MCStreamer &Streamer); - typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT); - typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T, - const MCRegisterInfo &MRI, - const MCAsmInfo &MAI); - typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI, - MCAsmParser &P); - typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); - typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI); - typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II, - const MCSubtargetInfo &STI, - MCContext &Ctx); - typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T, - StringRef TT, - MCContext &Ctx, - MCAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack); - typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx, - formatted_raw_ostream &OS, - bool isVerboseAsm, - bool useLoc, - bool useCFI, - MCInstPrinter *InstPrint, - MCCodeEmitter *CE, - MCAsmBackend *TAB, - bool ShowInst); - - private: - /// Next - The next registered target in the linked list, maintained by the - /// TargetRegistry. - Target *Next; - - /// TripleMatchQualityFn - The target function for rating the match quality - /// of a triple. - TripleMatchQualityFnTy TripleMatchQualityFn; - - /// Name - The target name. - const char *Name; - - /// ShortDesc - A short description of the target. - const char *ShortDesc; - - /// HasJIT - Whether this target supports the JIT. - bool HasJIT; - - /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if - /// registered. - MCAsmInfoCtorFnTy MCAsmInfoCtorFn; - - /// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo, - /// if registered. - MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; - - /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, - /// if registered. - MCInstrInfoCtorFnTy MCInstrInfoCtorFn; - - /// MCInstrAnalysisCtorFn - Constructor function for this target's - /// MCInstrAnalysis, if registered. - MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn; - - /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo, - /// if registered. - MCRegInfoCtorFnTy MCRegInfoCtorFn; - - /// MCSubtargetInfoCtorFn - Constructor function for this target's - /// MCSubtargetInfo, if registered. - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn; - - /// TargetMachineCtorFn - Construction function for this target's - /// TargetMachine, if registered. - TargetMachineCtorTy TargetMachineCtorFn; - - /// MCAsmBackendCtorFn - Construction function for this target's - /// MCAsmBackend, if registered. - MCAsmBackendCtorTy MCAsmBackendCtorFn; - - /// MCAsmLexerCtorFn - Construction function for this target's - /// MCTargetAsmLexer, if registered. - MCAsmLexerCtorTy MCAsmLexerCtorFn; - - /// MCAsmParserCtorFn - Construction function for this target's - /// MCTargetAsmParser, if registered. - MCAsmParserCtorTy MCAsmParserCtorFn; - - /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter, - /// if registered. - AsmPrinterCtorTy AsmPrinterCtorFn; - - /// MCDisassemblerCtorFn - Construction function for this target's - /// MCDisassembler, if registered. - MCDisassemblerCtorTy MCDisassemblerCtorFn; - - /// MCInstPrinterCtorFn - Construction function for this target's - /// MCInstPrinter, if registered. - MCInstPrinterCtorTy MCInstPrinterCtorFn; - - /// MCCodeEmitterCtorFn - Construction function for this target's - /// CodeEmitter, if registered. - MCCodeEmitterCtorTy MCCodeEmitterCtorFn; - - /// MCObjectStreamerCtorFn - Construction function for this target's - /// MCObjectStreamer, if registered. - MCObjectStreamerCtorTy MCObjectStreamerCtorFn; - - /// AsmStreamerCtorFn - Construction function for this target's - /// AsmStreamer, if registered (default = llvm::createAsmStreamer). - AsmStreamerCtorTy AsmStreamerCtorFn; - - public: - Target() : AsmStreamerCtorFn(llvm::createAsmStreamer) {} - - /// @name Target Information - /// @{ - - // getNext - Return the next registered target. - const Target *getNext() const { return Next; } - - /// getName - Get the target name. - const char *getName() const { return Name; } - - /// getShortDescription - Get a short description of the target. - const char *getShortDescription() const { return ShortDesc; } - - /// @} - /// @name Feature Predicates - /// @{ - - /// hasJIT - Check if this targets supports the just-in-time compilation. - bool hasJIT() const { return HasJIT; } - - /// hasTargetMachine - Check if this target supports code generation. - bool hasTargetMachine() const { return TargetMachineCtorFn != 0; } - - /// hasMCAsmBackend - Check if this target supports .o generation. - bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; } - - /// hasMCAsmLexer - Check if this target supports .s lexing. - bool hasMCAsmLexer() const { return MCAsmLexerCtorFn != 0; } - - /// hasAsmParser - Check if this target supports .s parsing. - bool hasMCAsmParser() const { return MCAsmParserCtorFn != 0; } - - /// hasAsmPrinter - Check if this target supports .s printing. - bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; } - - /// hasMCDisassembler - Check if this target has a disassembler. - bool hasMCDisassembler() const { return MCDisassemblerCtorFn != 0; } - - /// hasMCInstPrinter - Check if this target has an instruction printer. - bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; } - - /// hasMCCodeEmitter - Check if this target supports instruction encoding. - bool hasMCCodeEmitter() const { return MCCodeEmitterCtorFn != 0; } - - /// hasMCObjectStreamer - Check if this target supports streaming to files. - bool hasMCObjectStreamer() const { return MCObjectStreamerCtorFn != 0; } - - /// hasAsmStreamer - Check if this target supports streaming to files. - bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; } - - /// @} - /// @name Feature Constructors - /// @{ - - /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified - /// target triple. - /// - /// \arg Triple - This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. - MCAsmInfo *createMCAsmInfo(StringRef Triple) const { - if (!MCAsmInfoCtorFn) - return 0; - return MCAsmInfoCtorFn(*this, Triple); - } - - /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. - /// - MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM, - CodeModel::Model CM) const { - if (!MCCodeGenInfoCtorFn) - return 0; - return MCCodeGenInfoCtorFn(Triple, RM, CM); - } - - /// createMCInstrInfo - Create a MCInstrInfo implementation. - /// - MCInstrInfo *createMCInstrInfo() const { - if (!MCInstrInfoCtorFn) - return 0; - return MCInstrInfoCtorFn(); - } - - /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation. - /// - MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const { - if (!MCInstrAnalysisCtorFn) - return 0; - return MCInstrAnalysisCtorFn(Info); - } - - /// createMCRegInfo - Create a MCRegisterInfo implementation. - /// - MCRegisterInfo *createMCRegInfo(StringRef Triple) const { - if (!MCRegInfoCtorFn) - return 0; - return MCRegInfoCtorFn(Triple); - } - - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. - /// - /// \arg Triple - This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. - /// \arg CPU - This specifies the name of the target CPU. - /// \arg Features - This specifies the string representation of the - /// additional target features. - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, - StringRef Features) const { - if (!MCSubtargetInfoCtorFn) - return 0; - return MCSubtargetInfoCtorFn(Triple, CPU, Features); - } - - /// createTargetMachine - Create a target specific machine implementation - /// for the specified \arg Triple. - /// - /// \arg Triple - This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. - TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, - StringRef Features, - Reloc::Model RM = Reloc::Default, - CodeModel::Model CM = CodeModel::Default) const { - if (!TargetMachineCtorFn) - return 0; - return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM); - } - - /// createMCAsmBackend - Create a target specific assembly parser. - /// - /// \arg Triple - The target triple string. - /// \arg Backend - The target independent assembler object. - MCAsmBackend *createMCAsmBackend(StringRef Triple) const { - if (!MCAsmBackendCtorFn) - return 0; - return MCAsmBackendCtorFn(*this, Triple); - } - - /// createMCAsmLexer - Create a target specific assembly lexer. - /// - MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI, - const MCAsmInfo &MAI) const { - if (!MCAsmLexerCtorFn) - return 0; - return MCAsmLexerCtorFn(*this, MRI, MAI); - } - - /// createMCAsmParser - Create a target specific assembly parser. - /// - /// \arg Parser - The target independent parser implementation to use for - /// parsing and lexing. - MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, - MCAsmParser &Parser) const { - if (!MCAsmParserCtorFn) - return 0; - return MCAsmParserCtorFn(STI, Parser); - } - - /// createAsmPrinter - Create a target specific assembly printer pass. This - /// takes ownership of the MCStreamer object. - AsmPrinter *createAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) const{ - if (!AsmPrinterCtorFn) - return 0; - return AsmPrinterCtorFn(TM, Streamer); - } - - MCDisassembler *createMCDisassembler() const { - if (!MCDisassemblerCtorFn) - return 0; - return MCDisassemblerCtorFn(*this); - } - - MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant, - const MCAsmInfo &MAI) const { - if (!MCInstPrinterCtorFn) - return 0; - return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI); - } - - - /// createMCCodeEmitter - Create a target specific code emitter. - MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II, - const MCSubtargetInfo &STI, - MCContext &Ctx) const { - if (!MCCodeEmitterCtorFn) - return 0; - return MCCodeEmitterCtorFn(II, STI, Ctx); - } - - /// createMCObjectStreamer - Create a target specific MCStreamer. - /// - /// \arg TT - The target triple. - /// \arg Ctx - The target context. - /// \arg TAB - The target assembler backend object. Takes ownership. - /// \arg _OS - The stream object. - /// \arg _Emitter - The target independent assembler object.Takes ownership. - /// \arg RelaxAll - Relax all fixups? - /// \arg NoExecStack - Mark file as not needing a executable stack. - MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx, - MCAsmBackend &TAB, - raw_ostream &_OS, - MCCodeEmitter *_Emitter, - bool RelaxAll, - bool NoExecStack) const { - if (!MCObjectStreamerCtorFn) - return 0; - return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, - RelaxAll, NoExecStack); - } - - /// createAsmStreamer - Create a target specific MCStreamer. - MCStreamer *createAsmStreamer(MCContext &Ctx, - formatted_raw_ostream &OS, - bool isVerboseAsm, - bool useLoc, - bool useCFI, - MCInstPrinter *InstPrint, - MCCodeEmitter *CE, - MCAsmBackend *TAB, - bool ShowInst) const { - // AsmStreamerCtorFn is default to llvm::createAsmStreamer - return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI, - InstPrint, CE, TAB, ShowInst); - } - - /// @} - }; - - /// TargetRegistry - Generic interface to target specific features. - struct TargetRegistry { - class iterator { - const Target *Current; - explicit iterator(Target *T) : Current(T) {} - friend struct TargetRegistry; - public: - iterator(const iterator &I) : Current(I.Current) {} - iterator() : Current(0) {} - - bool operator==(const iterator &x) const { - return Current == x.Current; - } - bool operator!=(const iterator &x) const { - return !operator==(x); - } - - // Iterator traversal: forward iteration only - iterator &operator++() { // Preincrement - assert(Current && "Cannot increment end iterator!"); - Current = Current->getNext(); - return *this; - } - iterator operator++(int) { // Postincrement - iterator tmp = *this; - ++*this; - return tmp; - } - - const Target &operator*() const { - assert(Current && "Cannot dereference end iterator!"); - return *Current; - } - - const Target *operator->() const { - return &operator*(); - } - }; - - /// printRegisteredTargetsForVersion - Print the registered targets - /// appropriately for inclusion in a tool's version output. - static void printRegisteredTargetsForVersion(); - - /// @name Registry Access - /// @{ - - static iterator begin(); - - static iterator end() { return iterator(); } - - /// lookupTarget - Lookup a target based on a target triple. - /// - /// \param Triple - The triple to use for finding a target. - /// \param Error - On failure, an error string describing why no target was - /// found. - static const Target *lookupTarget(const std::string &Triple, - std::string &Error); - - /// getClosestTargetForJIT - Pick the best target that is compatible with - /// the current host. If no close target can be found, this returns null - /// and sets the Error string to a reason. - /// - /// Maintained for compatibility through 2.6. - static const Target *getClosestTargetForJIT(std::string &Error); - - /// @} - /// @name Target Registration - /// @{ - - /// RegisterTarget - Register the given target. Attempts to register a - /// target which has already been registered will be ignored. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Name - The target name. This should be a static string. - /// @param ShortDesc - A short target description. This should be a static - /// string. - /// @param TQualityFn - The triple match quality computation function for - /// this target. - /// @param HasJIT - Whether the target supports JIT code - /// generation. - static void RegisterTarget(Target &T, - const char *Name, - const char *ShortDesc, - Target::TripleMatchQualityFnTy TQualityFn, - bool HasJIT = false); - - /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCAsmInfo for the target. - static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCAsmInfoCtorFn) - T.MCAsmInfoCtorFn = Fn; - } - - /// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCCodeGenInfo for the target. - static void RegisterMCCodeGenInfo(Target &T, - Target::MCCodeGenInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCCodeGenInfoCtorFn) - T.MCCodeGenInfoCtorFn = Fn; - } - - /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCInstrInfo for the target. - static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCInstrInfoCtorFn) - T.MCInstrInfoCtorFn = Fn; - } - - /// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for - /// the given target. - static void RegisterMCInstrAnalysis(Target &T, - Target::MCInstrAnalysisCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCInstrAnalysisCtorFn) - T.MCInstrAnalysisCtorFn = Fn; - } - - /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCRegisterInfo for the target. - static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCRegInfoCtorFn) - T.MCRegInfoCtorFn = Fn; - } - - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for - /// the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a MCSubtargetInfo for the target. - static void RegisterMCSubtargetInfo(Target &T, - Target::MCSubtargetInfoCtorFnTy Fn) { - // Ignore duplicate registration. - if (!T.MCSubtargetInfoCtorFn) - T.MCSubtargetInfoCtorFn = Fn; - } - - /// RegisterTargetMachine - Register a TargetMachine implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct a TargetMachine for the target. - static void RegisterTargetMachine(Target &T, - Target::TargetMachineCtorTy Fn) { - // Ignore duplicate registration. - if (!T.TargetMachineCtorFn) - T.TargetMachineCtorFn = Fn; - } - - /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an AsmBackend for the target. - static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) { - if (!T.MCAsmBackendCtorFn) - T.MCAsmBackendCtorFn = Fn; - } - - /// RegisterMCAsmLexer - Register a MCTargetAsmLexer implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCAsmLexer for the target. - static void RegisterMCAsmLexer(Target &T, Target::MCAsmLexerCtorTy Fn) { - if (!T.MCAsmLexerCtorFn) - T.MCAsmLexerCtorFn = Fn; - } - - /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for - /// the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCTargetAsmParser for the target. - static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) { - if (!T.MCAsmParserCtorFn) - T.MCAsmParserCtorFn = Fn; - } - - /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given - /// target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an AsmPrinter for the target. - static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) { - // Ignore duplicate registration. - if (!T.AsmPrinterCtorFn) - T.AsmPrinterCtorFn = Fn; - } - - /// RegisterMCDisassembler - Register a MCDisassembler implementation for - /// the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCDisassembler for the target. - static void RegisterMCDisassembler(Target &T, - Target::MCDisassemblerCtorTy Fn) { - if (!T.MCDisassemblerCtorFn) - T.MCDisassemblerCtorFn = Fn; - } - - /// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCInstPrinter for the target. - static void RegisterMCInstPrinter(Target &T, - Target::MCInstPrinterCtorTy Fn) { - if (!T.MCInstPrinterCtorFn) - T.MCInstPrinterCtorFn = Fn; - } - - /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the - /// given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCCodeEmitter for the target. - static void RegisterMCCodeEmitter(Target &T, - Target::MCCodeEmitterCtorTy Fn) { - if (!T.MCCodeEmitterCtorFn) - T.MCCodeEmitterCtorFn = Fn; - } - - /// RegisterMCObjectStreamer - Register a object code MCStreamer - /// implementation for the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCStreamer for the target. - static void RegisterMCObjectStreamer(Target &T, - Target::MCObjectStreamerCtorTy Fn) { - if (!T.MCObjectStreamerCtorFn) - T.MCObjectStreamerCtorFn = Fn; - } - - /// RegisterAsmStreamer - Register an assembly MCStreamer implementation - /// for the given target. - /// - /// Clients are responsible for ensuring that registration doesn't occur - /// while another thread is attempting to access the registry. Typically - /// this is done by initializing all targets at program startup. - /// - /// @param T - The target being registered. - /// @param Fn - A function to construct an MCStreamer for the target. - static void RegisterAsmStreamer(Target &T, Target::AsmStreamerCtorTy Fn) { - if (T.AsmStreamerCtorFn == createAsmStreamer) - T.AsmStreamerCtorFn = Fn; - } - - /// @} - }; - - - //===--------------------------------------------------------------------===// - - /// RegisterTarget - Helper template for registering a target, for use in the - /// target's initialization function. Usage: - /// - /// - /// Target TheFooTarget; // The global target instance. - /// - /// extern "C" void LLVMInitializeFooTargetInfo() { - /// RegisterTarget X(TheFooTarget, "foo", "Foo description"); - /// } - template - struct RegisterTarget { - RegisterTarget(Target &T, const char *Name, const char *Desc) { - TargetRegistry::RegisterTarget(T, Name, Desc, - &getTripleMatchQuality, - HasJIT); - } - - static unsigned getTripleMatchQuality(const std::string &TT) { - if (Triple(TT).getArch() == TargetArchType) - return 20; - return 0; - } - }; - - /// RegisterMCAsmInfo - Helper template for registering a target assembly info - /// implementation. This invokes the static "Create" method on the class to - /// actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCAsmInfo X(TheFooTarget); - /// } - template - struct RegisterMCAsmInfo { - RegisterMCAsmInfo(Target &T) { - TargetRegistry::RegisterMCAsmInfo(T, &Allocator); - } - private: - static MCAsmInfo *Allocator(const Target &T, StringRef TT) { - return new MCAsmInfoImpl(T, TT); - } - - }; - - /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info - /// implementation. This invokes the specified function to do the - /// construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCAsmInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCAsmInfoFn { - RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCAsmInfo(T, Fn); - } - }; - - /// RegisterMCCodeGenInfo - Helper template for registering a target codegen info - /// implementation. This invokes the static "Create" method on the class - /// to actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCCodeGenInfo X(TheFooTarget); - /// } - template - struct RegisterMCCodeGenInfo { - RegisterMCCodeGenInfo(Target &T) { - TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); - } - private: - static MCCodeGenInfo *Allocator(StringRef TT, - Reloc::Model RM, CodeModel::Model CM) { - return new MCCodeGenInfoImpl(); - } - }; - - /// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen - /// info implementation. This invokes the specified function to do the - /// construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCCodeGenInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCCodeGenInfoFn { - RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCCodeGenInfo(T, Fn); - } - }; - - /// RegisterMCInstrInfo - Helper template for registering a target instruction - /// info implementation. This invokes the static "Create" method on the class - /// to actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCInstrInfo X(TheFooTarget); - /// } - template - struct RegisterMCInstrInfo { - RegisterMCInstrInfo(Target &T) { - TargetRegistry::RegisterMCInstrInfo(T, &Allocator); - } - private: - static MCInstrInfo *Allocator() { - return new MCInstrInfoImpl(); - } - }; - - /// RegisterMCInstrInfoFn - Helper template for registering a target - /// instruction info implementation. This invokes the specified function to - /// do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCInstrInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCInstrInfoFn { - RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCInstrInfo(T, Fn); - } - }; - - /// RegisterMCInstrAnalysis - Helper template for registering a target - /// instruction analyzer implementation. This invokes the static "Create" - /// method on the class to actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCInstrAnalysis X(TheFooTarget); - /// } - template - struct RegisterMCInstrAnalysis { - RegisterMCInstrAnalysis(Target &T) { - TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator); - } - private: - static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) { - return new MCInstrAnalysisImpl(Info); - } - }; - - /// RegisterMCInstrAnalysisFn - Helper template for registering a target - /// instruction analyzer implementation. This invokes the specified function - /// to do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCInstrAnalysisFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCInstrAnalysisFn { - RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) { - TargetRegistry::RegisterMCInstrAnalysis(T, Fn); - } - }; - - /// RegisterMCRegInfo - Helper template for registering a target register info - /// implementation. This invokes the static "Create" method on the class to - /// actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCRegInfo X(TheFooTarget); - /// } - template - struct RegisterMCRegInfo { - RegisterMCRegInfo(Target &T) { - TargetRegistry::RegisterMCRegInfo(T, &Allocator); - } - private: - static MCRegisterInfo *Allocator(StringRef TT) { - return new MCRegisterInfoImpl(); - } - }; - - /// RegisterMCRegInfoFn - Helper template for registering a target register - /// info implementation. This invokes the specified function to do the - /// construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCRegInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCRegInfoFn { - RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCRegInfo(T, Fn); - } - }; - - /// RegisterMCSubtargetInfo - Helper template for registering a target - /// subtarget info implementation. This invokes the static "Create" method - /// on the class to actually do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCSubtargetInfo X(TheFooTarget); - /// } - template - struct RegisterMCSubtargetInfo { - RegisterMCSubtargetInfo(Target &T) { - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); - } - private: - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, - StringRef FS) { - return new MCSubtargetInfoImpl(); - } - }; - - /// RegisterMCSubtargetInfoFn - Helper template for registering a target - /// subtarget info implementation. This invokes the specified function to - /// do the construction. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction); - /// } - struct RegisterMCSubtargetInfoFn { - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) { - TargetRegistry::RegisterMCSubtargetInfo(T, Fn); - } - }; - - /// RegisterTargetMachine - Helper template for registering a target machine - /// implementation, for use in the target machine initialization - /// function. Usage: - /// - /// extern "C" void LLVMInitializeFooTarget() { - /// extern Target TheFooTarget; - /// RegisterTargetMachine X(TheFooTarget); - /// } - template - struct RegisterTargetMachine { - RegisterTargetMachine(Target &T) { - TargetRegistry::RegisterTargetMachine(T, &Allocator); - } - - private: - static TargetMachine *Allocator(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - Reloc::Model RM, - CodeModel::Model CM) { - return new TargetMachineImpl(T, TT, CPU, FS, RM, CM); - } - }; - - /// RegisterMCAsmBackend - Helper template for registering a target specific - /// assembler backend. Usage: - /// - /// extern "C" void LLVMInitializeFooMCAsmBackend() { - /// extern Target TheFooTarget; - /// RegisterMCAsmBackend X(TheFooTarget); - /// } - template - struct RegisterMCAsmBackend { - RegisterMCAsmBackend(Target &T) { - TargetRegistry::RegisterMCAsmBackend(T, &Allocator); - } - - private: - static MCAsmBackend *Allocator(const Target &T, StringRef Triple) { - return new MCAsmBackendImpl(T, Triple); - } - }; - - /// RegisterMCAsmLexer - Helper template for registering a target specific - /// assembly lexer, for use in the target machine initialization - /// function. Usage: - /// - /// extern "C" void LLVMInitializeFooMCAsmLexer() { - /// extern Target TheFooTarget; - /// RegisterMCAsmLexer X(TheFooTarget); - /// } - template - struct RegisterMCAsmLexer { - RegisterMCAsmLexer(Target &T) { - TargetRegistry::RegisterMCAsmLexer(T, &Allocator); - } - - private: - static MCTargetAsmLexer *Allocator(const Target &T, - const MCRegisterInfo &MRI, - const MCAsmInfo &MAI) { - return new MCAsmLexerImpl(T, MRI, MAI); - } - }; - - /// RegisterMCAsmParser - Helper template for registering a target specific - /// assembly parser, for use in the target machine initialization - /// function. Usage: - /// - /// extern "C" void LLVMInitializeFooMCAsmParser() { - /// extern Target TheFooTarget; - /// RegisterMCAsmParser X(TheFooTarget); - /// } - template - struct RegisterMCAsmParser { - RegisterMCAsmParser(Target &T) { - TargetRegistry::RegisterMCAsmParser(T, &Allocator); - } - - private: - static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) { - return new MCAsmParserImpl(STI, P); - } - }; - - /// RegisterAsmPrinter - Helper template for registering a target specific - /// assembly printer, for use in the target machine initialization - /// function. Usage: - /// - /// extern "C" void LLVMInitializeFooAsmPrinter() { - /// extern Target TheFooTarget; - /// RegisterAsmPrinter X(TheFooTarget); - /// } - template - struct RegisterAsmPrinter { - RegisterAsmPrinter(Target &T) { - TargetRegistry::RegisterAsmPrinter(T, &Allocator); - } - - private: - static AsmPrinter *Allocator(TargetMachine &TM, MCStreamer &Streamer) { - return new AsmPrinterImpl(TM, Streamer); - } - }; - - /// RegisterMCCodeEmitter - Helper template for registering a target specific - /// machine code emitter, for use in the target initialization - /// function. Usage: - /// - /// extern "C" void LLVMInitializeFooMCCodeEmitter() { - /// extern Target TheFooTarget; - /// RegisterMCCodeEmitter X(TheFooTarget); - /// } - template - struct RegisterMCCodeEmitter { - RegisterMCCodeEmitter(Target &T) { - TargetRegistry::RegisterMCCodeEmitter(T, &Allocator); - } - - private: - static MCCodeEmitter *Allocator(const MCInstrInfo &II, - const MCSubtargetInfo &STI, - MCContext &Ctx) { - return new MCCodeEmitterImpl(); - } - }; - -} - -#endif Removed: llvm/trunk/include/llvm/Target/TargetSelect.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=138449&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Target/TargetSelect.h (removed) @@ -1,154 +0,0 @@ -//===- TargetSelect.h - Target Selection & Registration ---------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file provides utilities to make sure that certain classes of targets are -// linked into the main application executable, and initialize them as -// appropriate. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETSELECT_H -#define LLVM_TARGET_TARGETSELECT_H - -#include "llvm/Config/llvm-config.h" - -extern "C" { - // Declare all of the target-initialization functions that are available. -#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##TargetInfo(); -#include "llvm/Config/Targets.def" - -#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(); -#include "llvm/Config/Targets.def" - - // Declare all of the target-MC-initialization functions that are available. -#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##TargetMC(); -#include "llvm/Config/Targets.def" - - // Declare all of the available assembly printer initialization functions. -#define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter(); -#include "llvm/Config/AsmPrinters.def" - - // Declare all of the available assembly parser initialization functions. -#define LLVM_ASM_PARSER(TargetName) void LLVMInitialize##TargetName##AsmParser(); -#include "llvm/Config/AsmParsers.def" - - // Declare all of the available disassembler initialization functions. -#define LLVM_DISASSEMBLER(TargetName) \ - void LLVMInitialize##TargetName##Disassembler(); -#include "llvm/Config/Disassemblers.def" -} - -namespace llvm { - /// InitializeAllTargetInfos - The main program should call this function if - /// it wants access to all available targets that LLVM is configured to - /// support, to make them available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllTargetInfos() { -#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); -#include "llvm/Config/Targets.def" - } - - /// InitializeAllTargets - The main program should call this function if it - /// wants access to all available target machines that LLVM is configured to - /// support, to make them available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllTargets() { - // FIXME: Remove this, clients should do it. - InitializeAllTargetInfos(); - -#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target(); -#include "llvm/Config/Targets.def" - } - - /// InitializeAllTargetMCs - The main program should call this function if it - /// wants access to all available target MC that LLVM is configured to - /// support, to make them available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllTargetMCs() { -#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); -#include "llvm/Config/Targets.def" - } - - /// InitializeAllAsmPrinters - The main program should call this function if - /// it wants all asm printers that LLVM is configured to support, to make them - /// available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllAsmPrinters() { -#define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter(); -#include "llvm/Config/AsmPrinters.def" - } - - /// InitializeAllAsmParsers - The main program should call this function if it - /// wants all asm parsers that LLVM is configured to support, to make them - /// available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllAsmParsers() { -#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser(); -#include "llvm/Config/AsmParsers.def" - } - - /// InitializeAllDisassemblers - The main program should call this function if - /// it wants all disassemblers that LLVM is configured to support, to make - /// them available via the TargetRegistry. - /// - /// It is legal for a client to make multiple calls to this function. - inline void InitializeAllDisassemblers() { -#define LLVM_DISASSEMBLER(TargetName) LLVMInitialize##TargetName##Disassembler(); -#include "llvm/Config/Disassemblers.def" - } - - /// InitializeNativeTarget - The main program should call this function to - /// initialize the native target corresponding to the host. This is useful - /// for JIT applications to ensure that the target gets linked in correctly. - /// - /// It is legal for a client to make multiple calls to this function. - inline bool InitializeNativeTarget() { - // If we have a native target, initialize it to ensure it is linked in. -#ifdef LLVM_NATIVE_TARGET - LLVM_NATIVE_TARGETINFO(); - LLVM_NATIVE_TARGET(); - LLVM_NATIVE_TARGETMC(); - return false; -#else - return true; -#endif - } - - /// InitializeNativeTargetAsmPrinter - The main program should call - /// this function to initialize the native target asm printer. - inline bool InitializeNativeTargetAsmPrinter() { - // If we have a native target, initialize the corresponding asm printer. -#ifdef LLVM_NATIVE_ASMPRINTER - LLVM_NATIVE_ASMPRINTER(); - return false; -#else - return true; -#endif - } - - /// InitializeNativeTargetAsmParser - The main program should call - /// this function to initialize the native target asm parser. - inline bool InitializeNativeTargetAsmParser() { - // If we have a native target, initialize the corresponding asm parser. -#ifdef LLVM_NATIVE_ASMPARSER - LLVM_NATIVE_ASMPARSER(); - return false; -#else - return true; -#endif - } - -} - -#endif Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Wed Aug 24 13:08:43 2011 @@ -25,13 +25,13 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -32,13 +32,13 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Scalar.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; namespace llvm { Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Wed Aug 24 13:08:43 2011 @@ -17,11 +17,11 @@ #include "llvm/Module.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/SubtargetFeature.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/raw_ostream.h" #include "llvm/Support/Host.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; /// selectTarget - Pick a target either via -march or by guessing the native Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Aug 24 13:08:43 2011 @@ -26,7 +26,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Aug 24 13:08:43 2011 @@ -16,9 +16,9 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" namespace llvm { class Target; Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Aug 24 13:08:43 2011 @@ -33,8 +33,8 @@ #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/SourceMgr.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" using namespace llvm; bool EDDisassembler::sInitialized = false; Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Wed Aug 24 13:08:43 2011 @@ -25,12 +25,12 @@ #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCWin64EH.h" #include "llvm/MC/MCAsmBackend.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/StringMap.h" #include "llvm/Support/COFF.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Wed Aug 24 13:08:43 2011 @@ -72,6 +72,7 @@ SearchForAddressOfSpecialSymbol.cpp Signals.cpp system_error.cpp + TargetRegistry.cpp ThreadLocal.cpp Threading.cpp TimeValue.cpp Copied: llvm/trunk/lib/Support/TargetRegistry.cpp (from r138420, llvm/trunk/lib/Target/TargetRegistry.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetRegistry.cpp?p2=llvm/trunk/lib/Support/TargetRegistry.cpp&p1=llvm/trunk/lib/Target/TargetRegistry.cpp&r1=138420&r2=138450&rev=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegistry.cpp (original) +++ llvm/trunk/lib/Support/TargetRegistry.cpp Wed Aug 24 13:08:43 2011 @@ -7,9 +7,9 @@ // //===----------------------------------------------------------------------===// +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Host.h" #include "llvm/Support/raw_ostream.h" #include Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -45,13 +45,13 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include using namespace llvm; Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -17,8 +17,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeARMTarget() { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Wed Aug 24 13:08:43 2011 @@ -15,7 +15,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCTargetAsmLexer.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 13:08:43 2011 @@ -22,8 +22,8 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/OwningPtr.h" Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 24 13:08:43 2011 @@ -18,10 +18,10 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCContext.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" // Pull DecodeStatus and its enum values into the global namespace. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -21,8 +21,8 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_REGINFO_MC_DESC #include "ARMGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "ARM.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheARMTarget, llvm::TheThumbTarget; Modified: llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -26,8 +26,8 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -16,7 +16,6 @@ #include "AlphaMachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/ErrorHandling.h" Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,6 @@ #include "AlphaSubtarget.h" #include "Alpha.h" -#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "AlphaTargetMachine.h" #include "llvm/PassManager.h" #include "llvm/Support/FormattedStream.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeAlphaTarget() { Modified: llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "AlphaGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "Alpha.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; llvm::Target llvm::TheAlphaTarget; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -29,9 +29,9 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -16,10 +16,10 @@ #include "Blackfin.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_CTOR #include "BlackfinGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "BlackfinSubtarget.h" #include "Blackfin.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "BlackfinTargetMachine.h" #include "Blackfin.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Modified: llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "BlackfinGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "Blackfin.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Aug 24 13:08:43 2011 @@ -42,7 +42,6 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CFG.h" #include "llvm/Support/ErrorHandling.h" @@ -50,6 +49,7 @@ #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/Host.h" #include "llvm/Config/config.h" #include Modified: llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "CTargetMachine.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheCBackendTarget; Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Wed Aug 24 13:08:43 2011 @@ -10,7 +10,6 @@ TargetLoweringObjectFile.cpp TargetMachine.cpp TargetRegisterInfo.cpp - TargetRegistry.cpp TargetSubtargetInfo.cpp ) Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -18,7 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "SPUGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -29,10 +29,10 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -17,9 +17,9 @@ #include "SPUHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/MC/MCContext.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #define GET_INSTRINFO_CTOR Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "SPUSubtarget.h" #include "SPU.h" #include "SPURegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" #define GET_SUBTARGETINFO_TARGET_DESC Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -16,8 +16,8 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/DynamicLibrary.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Modified: llvm/trunk/lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "SPU.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheCellSPUTarget; Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Aug 24 13:08:43 2011 @@ -29,7 +29,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Config/config.h" #include Modified: llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "CPPTargetMachine.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheCppBackendTarget; Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Wed Aug 24 13:08:43 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCTargetAsmLexer.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include #include Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Wed Aug 24 13:08:43 2011 @@ -15,8 +15,8 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCTargetAsmParser.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Aug 24 13:08:43 2011 @@ -20,9 +20,9 @@ #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" // #include "MBlazeGenDecoderTables.inc" Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -38,10 +38,10 @@ #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -17,9 +17,9 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -15,7 +15,7 @@ #include "MBlaze.h" #include "MBlazeRegisterInfo.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -16,8 +16,8 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeMBlazeTarget() { Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp Wed Aug 24 13:08:43 2011 @@ -21,8 +21,8 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetRegistry.h" using namespace llvm; static unsigned getFixupKindSize(unsigned Kind) { Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -19,8 +19,8 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "MBlazeGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/MBlaze/TargetInfo/MBlazeTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/TargetInfo/MBlazeTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/TargetInfo/MBlazeTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/TargetInfo/MBlazeTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "MBlaze.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheMBlazeTarget; Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -18,7 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "MSP430GenInstrInfo.inc" Modified: llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -32,9 +32,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -20,8 +20,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_CTOR #include "MSP430GenInstrInfo.inc" Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "MSP430Subtarget.h" #include "MSP430.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -16,7 +16,7 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeMSP430Target() { Modified: llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "MSP430.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheMSP430Target; Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "MipsGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -35,11 +35,11 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Analysis/DebugInfo.h" Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -17,8 +17,8 @@ #include "InstPrinter/MipsInstPrinter.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "MipsSubtarget.h" #include "Mips.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "Mips.h" #include "MipsTargetMachine.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeMipsTarget() { Modified: llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "Mips.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheMipsTarget, llvm::TheMipselTarget; Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "PTXGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -32,12 +32,12 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Path.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -18,8 +18,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #define GET_INSTRINFO_CTOR Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "PTXSubtarget.h" #include "PTX.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "PTX.h" #include "PTXTargetMachine.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "PTX.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Wed Aug 24 13:08:43 2011 @@ -18,7 +18,7 @@ #include "llvm/Object/MachOFormat.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -20,7 +20,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "PPCGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -43,11 +43,11 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSet.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -24,9 +24,9 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/STLExtras.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -15,7 +15,7 @@ #include "PPC.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include #define GET_SUBTARGETINFO_TARGET_DESC Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -16,8 +16,8 @@ #include "llvm/PassManager.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializePowerPCTarget() { Modified: llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "PPC.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::ThePPC32Target, llvm::ThePPC64Target; Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "SparcGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -22,9 +22,9 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -17,8 +17,8 @@ #include "SparcSubtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "SparcSubtarget.h" #include "Sparc.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "Sparc.h" #include "SparcTargetMachine.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeSparcTarget() { Modified: llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "Sparc.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheSparcTarget; Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "SystemZGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -28,10 +28,8 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -21,8 +21,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_CTOR #include "SystemZGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -15,7 +15,7 @@ #include "SystemZ.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -10,7 +10,7 @@ #include "SystemZTargetMachine.h" #include "SystemZ.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeSystemZTarget() { Modified: llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "SystemZ.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheSystemZTarget; Removed: llvm/trunk/lib/Target/TargetRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegistry.cpp?rev=138449&view=auto ============================================================================== --- llvm/trunk/lib/Target/TargetRegistry.cpp (original) +++ llvm/trunk/lib/Target/TargetRegistry.cpp (removed) @@ -1,122 +0,0 @@ -//===--- TargetRegistry.cpp - Target registration -------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/Host.h" -#include "llvm/Support/raw_ostream.h" -#include -#include -using namespace llvm; - -// Clients are responsible for avoid race conditions in registration. -static Target *FirstTarget = 0; - -TargetRegistry::iterator TargetRegistry::begin() { - return iterator(FirstTarget); -} - -const Target *TargetRegistry::lookupTarget(const std::string &TT, - std::string &Error) { - // Provide special warning when no targets are initialized. - if (begin() == end()) { - Error = "Unable to find target for this triple (no targets are registered)"; - return 0; - } - const Target *Best = 0, *EquallyBest = 0; - unsigned BestQuality = 0; - for (iterator it = begin(), ie = end(); it != ie; ++it) { - if (unsigned Qual = it->TripleMatchQualityFn(TT)) { - if (!Best || Qual > BestQuality) { - Best = &*it; - EquallyBest = 0; - BestQuality = Qual; - } else if (Qual == BestQuality) - EquallyBest = &*it; - } - } - - if (!Best) { - Error = "No available targets are compatible with this triple, " - "see -version for the available targets."; - return 0; - } - - // Otherwise, take the best target, but make sure we don't have two equally - // good best targets. - if (EquallyBest) { - Error = std::string("Cannot choose between targets \"") + - Best->Name + "\" and \"" + EquallyBest->Name + "\""; - return 0; - } - - return Best; -} - -void TargetRegistry::RegisterTarget(Target &T, - const char *Name, - const char *ShortDesc, - Target::TripleMatchQualityFnTy TQualityFn, - bool HasJIT) { - assert(Name && ShortDesc && TQualityFn && - "Missing required target information!"); - - // Check if this target has already been initialized, we allow this as a - // convenience to some clients. - if (T.Name) - return; - - // Add to the list of targets. - T.Next = FirstTarget; - FirstTarget = &T; - - T.Name = Name; - T.ShortDesc = ShortDesc; - T.TripleMatchQualityFn = TQualityFn; - T.HasJIT = HasJIT; -} - -const Target *TargetRegistry::getClosestTargetForJIT(std::string &Error) { - const Target *TheTarget = lookupTarget(sys::getHostTriple(), Error); - - if (TheTarget && !TheTarget->hasJIT()) { - Error = "No JIT compatible target available for this host"; - return 0; - } - - return TheTarget; -} - -static int TargetArraySortFn(const void *LHS, const void *RHS) { - typedef std::pair pair_ty; - return ((const pair_ty*)LHS)->first.compare(((const pair_ty*)RHS)->first); -} - -void TargetRegistry::printRegisteredTargetsForVersion() { - std::vector > Targets; - size_t Width = 0; - for (TargetRegistry::iterator I = TargetRegistry::begin(), - E = TargetRegistry::end(); - I != E; ++I) { - Targets.push_back(std::make_pair(I->getName(), &*I)); - Width = std::max(Width, Targets.back().first.size()); - } - array_pod_sort(Targets.begin(), Targets.end(), TargetArraySortFn); - - raw_ostream &OS = outs(); - OS << " Registered Targets:\n"; - for (unsigned i = 0, e = Targets.size(); i != e; ++i) { - OS << " " << Targets[i].first; - OS.indent(Width - Targets[i].first.size()) << " - " - << Targets[i].second->getShortDescription() << '\n'; - } - if (Targets.empty()) - OS << " (none)\n"; -} Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp Wed Aug 24 13:08:43 2011 @@ -12,7 +12,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCTargetAsmLexer.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,6 @@ #include "MCTargetDesc/X86BaseInfo.h" #include "llvm/MC/MCTargetAsmParser.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -25,6 +24,7 @@ #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug 24 13:08:43 2011 @@ -21,9 +21,9 @@ #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #define GET_REGINFO_ENUM Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Aug 24 13:08:43 2011 @@ -24,8 +24,8 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetRegistry.h" using namespace llvm; // Option to allow disabling arithmetic relaxation to workaround PR9807, which Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -22,9 +22,9 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/Triple.h" #include "llvm/Support/Host.h" +#include "llvm/Support/TargetRegistry.h" #define GET_REGINFO_MC_DESC #include "X86GenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/TargetInfo/X86TargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "X86.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheX86_32Target, llvm::TheX86_64Target; Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -35,12 +35,12 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Target/Mangler.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Support/COFF.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/ADT/SmallString.h" using namespace llvm; Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -19,7 +19,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; extern "C" void LLVMInitializeX86Target() { Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Wed Aug 24 13:08:43 2011 @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC #include "XCoreGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp Wed Aug 24 13:08:43 2011 @@ -9,7 +9,7 @@ #include "XCore.h" #include "llvm/Module.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; Target llvm::TheXCoreTarget; Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Aug 24 13:08:43 2011 @@ -32,11 +32,11 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include #include Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Wed Aug 24 13:08:43 2011 @@ -17,10 +17,10 @@ #include "llvm/MC/MCContext.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_CTOR #include "XCoreGenInstrInfo.inc" Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Wed Aug 24 13:08:43 2011 @@ -13,7 +13,7 @@ #include "XCoreSubtarget.h" #include "XCore.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Aug 24 13:08:43 2011 @@ -14,7 +14,7 @@ #include "XCore.h" #include "llvm/Module.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; /// XCoreTargetMachine ctor - Create an ILP32 architecture model Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Wed Aug 24 13:08:43 2011 @@ -32,10 +32,10 @@ #include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/Host.h" #include "llvm/Support/Signals.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" #include using namespace llvm; Modified: llvm/trunk/tools/lli/lli.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/lli/lli.cpp (original) +++ llvm/trunk/tools/lli/lli.cpp Wed Aug 24 13:08:43 2011 @@ -33,7 +33,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Process.h" #include "llvm/Support/Signals.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" #include #ifdef __CYGWIN__ Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original) +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 24 13:08:43 2011 @@ -21,14 +21,14 @@ #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Triple.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/MemoryObject.h" -#include "llvm/Support/raw_ostream.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; typedef std::vector > ByteArrayTy; Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Aug 24 13:08:43 2011 @@ -26,8 +26,6 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/MC/SubtargetFeature.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileUtilities.h" @@ -39,6 +37,8 @@ #include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/Host.h" #include "llvm/Support/Signals.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/system_error.h" #include "Disassembler.h" using namespace llvm; Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Aug 24 13:08:43 2011 @@ -36,10 +36,10 @@ #include "llvm/Support/PrettyStackTrace.h" #include "llvm/Support/Signals.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/system_error.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" #include #include using namespace llvm; Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Aug 24 13:08:43 2011 @@ -33,8 +33,6 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/MemoryBuffer.h" @@ -43,6 +41,8 @@ #include "llvm/Support/Host.h" #include "llvm/Support/Program.h" #include "llvm/Support/Signals.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/system_error.h" #include "llvm/Config/config.h" #include "llvm/Transforms/IPO.h" Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Aug 24 13:08:43 2011 @@ -27,6 +27,8 @@ #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Support/system_error.h" #include "llvm/Target/Mangler.h" #include "llvm/MC/MCAsmInfo.h" @@ -41,8 +43,6 @@ #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/TargetSelect.h" using namespace llvm; Modified: llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp Wed Aug 24 13:08:43 2011 @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineCodeInfo.h" #include "llvm/ExecutionEngine/JIT.h" #include "llvm/Support/TypeBuilder.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" #include "gtest/gtest.h" #include Modified: llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp?rev=138450&r1=138449&r2=138450&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp Wed Aug 24 13:08:43 2011 @@ -27,7 +27,7 @@ #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TypeBuilder.h" -#include "llvm/Target/TargetSelect.h" +#include "llvm/Support/TargetSelect.h" #include "llvm/Type.h" #include From evan.cheng at apple.com Wed Aug 24 13:12:40 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Aug 2011 18:12:40 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r138453 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <20110824181241.089AA2A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 13:12:40 2011 New Revision: 138453 URL: http://llvm.org/viewvc/llvm-project?rev=138453&view=rev Log: TargetRegistry has been moved to Support. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=138453&r1=138452&r2=138453&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Aug 24 13:12:40 2011 @@ -41,7 +41,6 @@ #include "llvm/Target/TargetLibraryInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/IPO.h" @@ -52,6 +51,7 @@ #include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/Program.h" +#include "llvm/Support/TargetRegistry.h" #include extern "C" { From grosbach at apple.com Wed Aug 24 13:19:42 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 18:19:42 -0000 Subject: [llvm-commits] [llvm] r138457 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td AsmParser/ARMAsmParser.cpp Message-ID: <20110824181942.4C14B2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 13:19:42 2011 New Revision: 138457 URL: http://llvm.org/viewvc/llvm-project?rev=138457&view=rev Log: Add missing explicit writeback operand to tSTMIA_UPD. rdar://10014745 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138457&r1=138456&r2=138457&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 13:19:42 2011 @@ -726,9 +726,10 @@ // There is no non-writeback version of STM for Thumb. let mayStore = 1, hasExtraSrcRegAllocReq = 1 in -def tSTMIA_UPD : T1I<(outs), - (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), - IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>, +def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), + (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), + AddrModeNone, 2, IIC_iStore_mu, + "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, T1Encoding<{1,1,0,0,0,?}> { bits<3> Rn; bits<8> regs; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138457&r1=138456&r2=138457&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 13:19:42 2011 @@ -3152,7 +3152,7 @@ } case ARM::tSTMIA_UPD: { bool listContainsBase; - if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase)) + if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase)) return Error(Operands[4]->getStartLoc(), "registers must be in range r0-r7"); break; From bruno.cardoso at gmail.com Wed Aug 24 13:48:33 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 18:48:33 -0000 Subject: [llvm-commits] [llvm] r138461 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824184833.742952A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 13:48:33 2011 New Revision: 138461 URL: http://llvm.org/viewvc/llvm-project?rev=138461&view=rev Log: Mark VZEROALL as clobbering all YMM registers Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138461&r1=138460&r2=138461&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 13:48:33 2011 @@ -5876,9 +5876,13 @@ //===----------------------------------------------------------------------===// // VZERO - Zero YMM registers // -// Zero All YMM registers -def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", - [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>; +let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, + YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in { + // Zero All YMM registers + def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", + [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>; + +} // Zero Upper bits of YMM registers def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", From rdivacky at freebsd.org Wed Aug 24 14:14:34 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Wed, 24 Aug 2011 21:14:34 +0200 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg Message-ID: <20110824191434.GA29249@freebsd.org> Hi, PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit when the call is a vararg one. It should set the bit only with vararg call that has floating point arguments in registers and unset the bit otherwise. The attached patch fixes that + test. This is normally just an optimization but it's very important in the kernel where doing floating point stuff is lethal. OK to commit? thank you, roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ppc-cr1eq.patch Type: text/x-diff Size: 1888 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/62e1e4e8/attachment.bin -------------- next part -------------- ; RUN: llc < %s | FileCheck %s ; ModuleID = 'test.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target triple = "powerpc-unknown-freebsd" @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 define void @foo() nounwind { entry: ; CHECK: crxor 6, 6, 6 %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) ; CHECK: creqv 6, 6, 6 %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) ret void } declare i32 @printf(i8*, ...) From grosbach at apple.com Wed Aug 24 15:06:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 20:06:14 -0000 Subject: [llvm-commits] [llvm] r138467 - /llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Message-ID: <20110824200614.448482A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 15:06:14 2011 New Revision: 138467 URL: http://llvm.org/viewvc/llvm-project?rev=138467&view=rev Log: When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. rdar://10015134 Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=138467&r1=138466&r2=138467&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Aug 24 15:06:14 2011 @@ -168,6 +168,7 @@ if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && MI->getOperand(1).getReg() == ARM::R8) { O << "\tnop"; + printPredicateOperand(MI, 2, O); return; } From jvoung at google.com Wed Aug 24 15:12:51 2011 From: jvoung at google.com (Jan Voung) Date: Wed, 24 Aug 2011 13:12:51 -0700 Subject: [llvm-commits] PATCH: pruning llvm w/ config flags --enable-target-oses=os1, os2 similar to --enable-target=arch1, arch2. Message-ID: Hi all, Attached is a patch that can help prune the size of the llvm binaries (e.g., llc, lli) a bit. This is done by adding configure flags --enable-target-oses=os1,os2 and --enable-target-envs=env1,env2 similar to --enable-target=arch1,arch2. These flags generate pre-processor defines that are then checked within the Triple module to force certain code paths to be considered dead (if llvm is built with an LTO-enabled-compiler). The if-defs could be spread further to give the same benefit for non-LTO compilers, but that isn't done. Concretely, if you build LLVM w/ clang -O4 and --enable-target-oses=Linux, there is about a 170 KB savings (prunes most of the MC COFF support, plus some branches in various places). If --enable-target-envs=gnu is also specified then most of MC MachO code is also pruned: llc built with lto, x86+arm arches, all oses, all environments: 12757900 llc built with lto, x86+arm arches, only Linux, all environments: 12584978 llc built with lto, x86+arm arches, only Linux, only gnu environment: 12528216 Is this worth adding? Again, patch is attached, or you can view the patch online: http://codereview.chromium.org/7730004/ Thanks! - Jan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/66ef3fbf/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_enable_os_env.patch Type: text/x-patch Size: 33500 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/66ef3fbf/attachment.bin From nadav.rotem at intel.com Wed Aug 24 15:18:38 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 24 Aug 2011 20:18:38 -0000 Subject: [llvm-commits] [llvm] r138469 - in /llvm/trunk: include/llvm/Constant.h include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp lib/VMCore/Constants.cpp test/Transforms/InstCombine/bitcast.ll Message-ID: <20110824201838.AB0D02A6C12C@llvm.org> Author: nadav Date: Wed Aug 24 15:18:38 2011 New Revision: 138469 URL: http://llvm.org/viewvc/llvm-project?rev=138469&view=rev Log: Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api. Modified: llvm/trunk/include/llvm/Constant.h llvm/trunk/include/llvm/Constants.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/test/Transforms/InstCombine/bitcast.ll Modified: llvm/trunk/include/llvm/Constant.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=138469&r1=138468&r2=138469&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constant.h (original) +++ llvm/trunk/include/llvm/Constant.h Wed Aug 24 15:18:38 2011 @@ -52,6 +52,10 @@ /// getNullValue. bool isNullValue() const; + /// isAllOnesValue - Return true if this is the value that would be returned by + /// getAllOnesValue. + bool isAllOnesValue() const; + /// isNegativeZeroValue - Return true if the value is what would be returned /// by getZeroValueForNegation. bool isNegativeZeroValue() const; Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=138469&r1=138468&r2=138469&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Wed Aug 24 15:18:38 2011 @@ -170,7 +170,7 @@ /// to true. /// @returns true iff this constant's bits are all set to true. /// @brief Determine if the value is all ones. - bool isAllOnesValue() const { + bool isMinusOne() const { return Val.isAllOnesValue(); } Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=138469&r1=138468&r2=138469&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Wed Aug 24 15:18:38 2011 @@ -45,16 +45,12 @@ /// ConstantExpr if unfoldable. static Constant *FoldBitCast(Constant *C, Type *DestTy, const TargetData &TD) { - - ConstantVector *CV = dyn_cast(C); - IntegerType *IntVTy = dyn_cast(DestTy); - // When casting vectors to scalar integers, catch the - // obvious splat cases. - if (IntVTy && CV) { - if (CV->isNullValue()) return ConstantInt::getNullValue(IntVTy); - if (CV->isAllOnesValue()) return ConstantInt::getAllOnesValue(IntVTy); - } - + // Catch the obvious splat cases. + if (C->isNullValue() && !DestTy->isX86_MMXTy()) + return Constant::getNullValue(DestTy); + if (C->isAllOnesValue() && !DestTy->isX86_MMXTy()) + return Constant::getAllOnesValue(DestTy); + // The code below only handles casts to vectors currently. VectorType *DestVTy = dyn_cast(DestTy); if (DestVTy == 0) @@ -68,6 +64,7 @@ } // If this is a bitcast from constant vector -> vector, fold it. + ConstantVector *CV = dyn_cast(C); if (CV == 0) return ConstantExpr::getBitCast(C, DestTy); Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=138469&r1=138468&r2=138469&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Wed Aug 24 15:18:38 2011 @@ -62,6 +62,21 @@ return isa(this) || isa(this); } +bool Constant::isAllOnesValue() const { + // Check for -1 integers + if (const ConstantInt *CI = dyn_cast(this)) + return CI->isMinusOne(); + + // Check for FP which are bitcasted from -1 integers + if (const ConstantFP *CFP = dyn_cast(this)) + return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue(); + + // Check for constant vectors + if (const ConstantVector *CV = dyn_cast(this)) + return CV->isAllOnesValue(); + + return false; +} // Constructor to create a '0' constant of arbitrary type... Constant *Constant::getNullValue(Type *Ty) { switch (Ty->getTypeID()) { @@ -126,7 +141,7 @@ SmallVector Elts; VectorType *VTy = cast(Ty); Elts.resize(VTy->getNumElements(), getAllOnesValue(VTy->getElementType())); - assert(Elts[0] && "Not a vector integer type!"); + assert(Elts[0] && "Invalid AllOnes value!"); return cast(ConstantVector::get(Elts)); } @@ -1064,13 +1079,16 @@ // Check out first element. const Constant *Elt = getOperand(0); const ConstantInt *CI = dyn_cast(Elt); - if (!CI || !CI->isAllOnesValue()) return false; + const ConstantFP *CF = dyn_cast(Elt); + // Then make sure all remaining elements point to the same value. for (unsigned I = 1, E = getNumOperands(); I < E; ++I) if (getOperand(I) != Elt) return false; - return true; + // First value is all-ones. + return (CI && CI->isAllOnesValue()) || + (CF && CF->isAllOnesValue()); } /// getSplatValue - If this is a splat constant, where all of the Modified: llvm/trunk/test/Transforms/InstCombine/bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast.ll?rev=138469&r1=138468&r2=138469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bitcast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bitcast.ll Wed Aug 24 15:18:38 2011 @@ -11,7 +11,7 @@ %t3 = xor <2 x i32> %t1, %t2 %t4 = extractelement <2 x i32> %t3, i32 0 ret i32 %t4 - + ; CHECK: @test1 ; CHECK: ret i32 0 } @@ -30,7 +30,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test2 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 0 ; CHECK-NEXT: bitcast <2 x i32> %B to <2 x float> @@ -55,7 +55,7 @@ %add = fadd float %tmp24, %tmp4 ret float %add - + ; CHECK: @test3 ; CHECK-NEXT: %tmp24 = extractelement <2 x float> %A, i32 1 ; CHECK-NEXT: bitcast <2 x i64> %B to <4 x float> @@ -75,7 +75,7 @@ ; CHECK: @test4 ; CHECK-NEXT: insertelement <2 x i32> undef, i32 %A, i32 0 ; CHECK-NEXT: insertelement <2 x i32> {{.*}}, i32 %B, i32 1 - ; CHECK-NEXT: ret <2 x i32> + ; CHECK-NEXT: ret <2 x i32> } @@ -92,7 +92,7 @@ ; CHECK: @test5 ; CHECK-NEXT: insertelement <2 x float> undef, float %A, i32 0 ; CHECK-NEXT: insertelement <2 x float> {{.*}}, float %B, i32 1 - ; CHECK-NEXT: ret <2 x float> + ; CHECK-NEXT: ret <2 x float> } define <2 x float> @test6(float %A){ @@ -113,3 +113,27 @@ ; CHECK: @ISPC0 ; CHECK: ret i64 0 } + + +define i64 @Vec2(i64 %in) { + %out = and i64 %in, xor (i64 bitcast (<4 x i16> to i64), i64 0) + ret i64 %out +; CHECK: @Vec2 +; CHECK: ret i64 0 +} + +define i64 @All11(i64 %in) { + %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1) + ret i64 %out +; CHECK: @All11 +; CHECK: ret i64 0 +} + + +define i32 @All111(i32 %in) { + %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1) + ret i32 %out +; CHECK: @All111 +; CHECK: ret i32 0 +} + From benny.kra at googlemail.com Wed Aug 24 15:25:58 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 24 Aug 2011 20:25:58 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r138471 - /llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Message-ID: <20110824202558.E2BC42A6C12C@llvm.org> Author: d0k Date: Wed Aug 24 15:25:58 2011 New Revision: 138471 URL: http://llvm.org/viewvc/llvm-project?rev=138471&view=rev Log: Try to unbreak llvm-gcc buildbots. Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp?rev=138471&r1=138470&r2=138471&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Wed Aug 24 15:25:58 2011 @@ -35,8 +35,8 @@ #include "llvm/Support/PrettyStackTrace.h" #include "llvm/Support/IRBuilder.h" #include "llvm/Support/raw_os_ostream.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegistry.h" /// dummy_function - This is used when linking the LLVM libraries into a dynamic /// library, allowing the llvm backend to be shared across the various From eli.friedman at gmail.com Wed Aug 24 15:28:39 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 20:28:39 -0000 Subject: [llvm-commits] [llvm] r138472 - /llvm/trunk/docs/LangRef.html Message-ID: <20110824202840.155E32A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 15:28:39 2011 New Revision: 138472 URL: http://llvm.org/viewvc/llvm-project?rev=138472&view=rev Log: Some minor updates to atomic acquire/release docs in LangRef. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=138472&r1=138471&r2=138472&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Aug 24 15:28:39 2011 @@ -1634,14 +1634,15 @@ eventually see the write. This corresponds to the C++0x/C1x memory_order_relaxed.
    acquire
    -
    In addition to the guarantees of monotonic, if this operation -reads a value written by a release atomic operation, it -synchronizes-with that operation. This corresponds to the C++0x/C1x -memory_order_acquire.
    -
    release
    In addition to the guarantees of monotonic, -a synchronizes-with edge may be formed with an acquire -operation. This is intended to model C++'s memory_order_release.
    +a synchronizes-with edge may be formed with a release +operation. This is intended to model C++'s memory_order_acquire. +
    release
    +
    In addition to the guarantees of monotonic, if this operation +writes a value which is subsequently read by an acquire operation, +it synchronizes-with that operation. (This isn't a complete +description; see the C++0x definition of a release sequence.) This corresponds +to the C++0x/C1x memory_order_release.
    acq_rel (acquire+release)
    Acts as both an acquire and release operation on its address. This corresponds to the C++0x/C1x memory_order_acq_rel.
    From isanbard at gmail.com Wed Aug 24 15:28:44 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 24 Aug 2011 20:28:44 -0000 Subject: [llvm-commits] [llvm] r138473 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110824202844.207D62A6C12D@llvm.org> Author: void Date: Wed Aug 24 15:28:43 2011 New Revision: 138473 URL: http://llvm.org/viewvc/llvm-project?rev=138473&view=rev Log: Use getFirstInsertionPt instead of getFirstNonPHI so that it skips to the proper insertion place. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=138473&r1=138472&r2=138473&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Aug 24 15:28:43 2011 @@ -456,7 +456,7 @@ // platforms. if (WeakPH) { Value *Conv = new SIToFPInst(NewPHI, PN->getType(), "indvar.conv", - PN->getParent()->getFirstNonPHI()); + PN->getParent()->getFirstInsertionPt()); PN->replaceAllUsesWith(Conv); RecursivelyDeleteTriviallyDeadInstructions(PN); } @@ -1703,7 +1703,7 @@ BasicBlock *Preheader = L->getLoopPreheader(); if (!Preheader) return; - Instruction *InsertPt = ExitBlock->getFirstNonPHI(); + Instruction *InsertPt = ExitBlock->getFirstInsertionPt(); BasicBlock::iterator I = Preheader->getTerminator(); while (I != Preheader->begin()) { --I; @@ -1903,7 +1903,7 @@ // the end of the pass. while (!OldCannIVs.empty()) { PHINode *OldCannIV = OldCannIVs.pop_back_val(); - OldCannIV->insertBefore(L->getHeader()->getFirstNonPHI()); + OldCannIV->insertBefore(L->getHeader()->getFirstInsertionPt()); } } else if (ExpandBECount && ReuseIVForExit && needsLFTR(L, DT)) { From eli.friedman at gmail.com Wed Aug 24 15:50:09 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 20:50:09 -0000 Subject: [llvm-commits] [llvm] r138478 - in /llvm/trunk: include/llvm/CodeGen/ISDOpcodes.h include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Target/TargetSelectionDAG.td lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrCompiler.td Message-ID: <20110824205009.9A7842A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 15:50:09 2011 New Revision: 138478 URL: http://llvm.org/viewvc/llvm-project?rev=138478&view=rev Log: Basic x86 code generation for atomic load and store instructions. Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrCompiler.td Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Wed Aug 24 15:50:09 2011 @@ -597,22 +597,22 @@ // two integer constants: an AtomicOrdering and a SynchronizationScope. ATOMIC_FENCE, + // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) + // This corresponds to "load atomic" instruction. + ATOMIC_LOAD, + + // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) + // This corresponds to "store atomic" instruction. + ATOMIC_STORE, + // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) - // this corresponds to the atomic.lcs intrinsic. - // cmp is compared to *ptr, and if equal, swap is stored in *ptr. - // the return is always the original value in *ptr + // This corresponds to the cmpxchg instruction. ATOMIC_CMP_SWAP, // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) - // this corresponds to the atomic.swap intrinsic. - // amt is stored to *ptr atomically. - // the return is always the original value in *ptr - ATOMIC_SWAP, - // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) - // this corresponds to the atomic.load.[OpName] intrinsic. - // op(*ptr, amt) is stored to *ptr atomically. - // the return is always the original value in *ptr + // These correspond to the atomicrmw instruction. + ATOMIC_SWAP, ATOMIC_LOAD_ADD, ATOMIC_LOAD_SUB, ATOMIC_LOAD_AND, Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Aug 24 15:50:09 2011 @@ -598,16 +598,26 @@ AtomicOrdering Ordering, SynchronizationScope SynchScope); - /// getAtomic - Gets a node for an atomic op, produces result and chain and - /// takes 2 operands. + /// getAtomic - Gets a node for an atomic op, produces result (if relevant) + /// and chain and takes 2 operands. SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, + unsigned Alignment, AtomicOrdering Ordering, + SynchronizationScope SynchScope); + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, + SDValue Ptr, SDValue Val, MachineMemOperand *MMO, + AtomicOrdering Ordering, + SynchronizationScope SynchScope); + + /// getAtomic - Gets a node for an atomic op, produces result and chain and + /// takes 1 operand. + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, + SDValue Chain, SDValue Ptr, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope); - SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, - SDValue Ptr, SDValue Val, - MachineMemOperand *MMO, + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, + SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope); Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Aug 24 15:50:09 2011 @@ -976,6 +976,8 @@ N->getOpcode() == ISD::ATOMIC_LOAD_MAX || N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || + N->getOpcode() == ISD::ATOMIC_LOAD || + N->getOpcode() == ISD::ATOMIC_STORE || N->isTargetMemoryOpcode(); } }; @@ -1025,6 +1027,14 @@ InitAtomic(Ordering, SynchScope); InitOperands(Ops, Chain, Ptr, Val); } + AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT, + SDValue Chain, SDValue Ptr, + MachineMemOperand *MMO, + AtomicOrdering Ordering, SynchronizationScope SynchScope) + : MemSDNode(Opc, dl, VTL, MemVT, MMO) { + InitAtomic(Ordering, SynchScope); + InitOperands(Ops, Chain, Ptr); + } const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getVal() const { return getOperand(2); } @@ -1048,7 +1058,9 @@ N->getOpcode() == ISD::ATOMIC_LOAD_MIN || N->getOpcode() == ISD::ATOMIC_LOAD_MAX || N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || - N->getOpcode() == ISD::ATOMIC_LOAD_UMAX; + N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || + N->getOpcode() == ISD::ATOMIC_LOAD || + N->getOpcode() == ISD::ATOMIC_STORE; } }; Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Wed Aug 24 15:50:09 2011 @@ -214,6 +214,12 @@ def SDTAtomic2 : SDTypeProfile<1, 2, [ SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> ]>; +def SDTAtomicStore : SDTypeProfile<0, 2, [ + SDTCisPtrTy<0>, SDTCisInt<1> +]>; +def SDTAtomicLoad : SDTypeProfile<1, 1, [ + SDTCisInt<0>, SDTCisPtrTy<1> +]>; def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> @@ -427,6 +433,10 @@ [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; +def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; // Do not use ld, st directly. Use load, extload, sextload, zextload, store, // and truncst (see below). @@ -844,6 +854,28 @@ defm atomic_load_max : binary_atomic_op; defm atomic_load_umin : binary_atomic_op; defm atomic_load_umax : binary_atomic_op; +defm atomic_store : binary_atomic_op; + +def atomic_load_8 : + PatFrag<(ops node:$ptr), + (atomic_load node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i8; +}]>; +def atomic_load_16 : + PatFrag<(ops node:$ptr), + (atomic_load node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; +}]>; +def atomic_load_32 : + PatFrag<(ops node:$ptr), + (atomic_load node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; +}]>; +def atomic_load_64 : + PatFrag<(ops node:$ptr), + (atomic_load node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; //===----------------------------------------------------------------------===// // Selection DAG CONVERT_RNDSAT patterns Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 24 15:50:09 2011 @@ -819,6 +819,11 @@ Action = TLI.getOperationAction(Node->getOpcode(), InnerType); break; } + case ISD::ATOMIC_STORE: { + Action = TLI.getOperationAction(Node->getOpcode(), + Node->getOperand(2).getValueType()); + break; + } case ISD::SELECT_CC: case ISD::SETCC: case ISD::BR_CC: { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 24 15:50:09 2011 @@ -432,7 +432,9 @@ case ISD::ATOMIC_LOAD_MIN: case ISD::ATOMIC_LOAD_MAX: case ISD::ATOMIC_LOAD_UMIN: - case ISD::ATOMIC_LOAD_UMAX: { + case ISD::ATOMIC_LOAD_UMAX: + case ISD::ATOMIC_LOAD: + case ISD::ATOMIC_STORE: { const AtomicSDNode *AT = cast(N); ID.AddInteger(AT->getMemoryVT().getRawBits()); ID.AddInteger(AT->getRawSubclassData()); @@ -3904,12 +3906,14 @@ Opcode == ISD::ATOMIC_LOAD_MAX || Opcode == ISD::ATOMIC_LOAD_UMIN || Opcode == ISD::ATOMIC_LOAD_UMAX || - Opcode == ISD::ATOMIC_SWAP) && + Opcode == ISD::ATOMIC_SWAP || + Opcode == ISD::ATOMIC_STORE) && "Invalid Atomic Op"); EVT VT = Val.getValueType(); - SDVTList VTs = getVTList(VT, MVT::Other); + SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) : + getVTList(VT, MVT::Other); FoldingSetNodeID ID; ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Val}; @@ -3927,6 +3931,55 @@ return SDValue(N, 0); } +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, + EVT VT, SDValue Chain, + SDValue Ptr, + const Value* PtrVal, + unsigned Alignment, + AtomicOrdering Ordering, + SynchronizationScope SynchScope) { + if (Alignment == 0) // Ensure that codegen never sees alignment 0 + Alignment = getEVTAlignment(MemVT); + + MachineFunction &MF = getMachineFunction(); + unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; + + // For now, atomics are considered to be volatile always. + Flags |= MachineMemOperand::MOVolatile; + + MachineMemOperand *MMO = + MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags, + MemVT.getStoreSize(), Alignment); + + return getAtomic(Opcode, dl, MemVT, VT, Chain, Ptr, MMO, + Ordering, SynchScope); +} + +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, + EVT VT, SDValue Chain, + SDValue Ptr, + MachineMemOperand *MMO, + AtomicOrdering Ordering, + SynchronizationScope SynchScope) { + assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op"); + + SDVTList VTs = getVTList(VT, MVT::Other); + FoldingSetNodeID ID; + ID.AddInteger(MemVT.getRawBits()); + SDValue Ops[] = {Chain, Ptr}; + AddNodeIDNode(ID, Opcode, VTs, Ops, 2); + void* IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { + cast(E)->refineAlignment(MMO); + return SDValue(E, 0); + } + SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain, + Ptr, MMO, Ordering, SynchScope); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDValue(N, 0); +} + /// getMergeValues - Create a MERGE_VALUES node from the given operands. SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl) { @@ -5795,6 +5848,8 @@ case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; + case ISD::ATOMIC_LOAD: return "AtomicLoad"; + case ISD::ATOMIC_STORE: return "AtomicStore"; case ISD::PCMARKER: return "PCMarker"; case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; case ISD::SRCVALUE: return "SrcValue"; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Aug 24 15:50:09 2011 @@ -3149,6 +3149,9 @@ } void SelectionDAGBuilder::visitLoad(const LoadInst &I) { + if (I.isAtomic()) + return visitAtomicLoad(I); + const Value *SV = I.getOperand(0); SDValue Ptr = getValue(SV); @@ -3226,6 +3229,9 @@ } void SelectionDAGBuilder::visitStore(const StoreInst &I) { + if (I.isAtomic()) + return visitAtomicStore(I); + const Value *SrcV = I.getOperand(0); const Value *PtrV = I.getOperand(1); @@ -3277,6 +3283,7 @@ } static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, + SynchronizationScope Scope, bool Before, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI) { @@ -3294,19 +3301,21 @@ } SDValue Ops[3]; Ops[0] = Chain; - Ops[1] = DAG.getConstant(SequentiallyConsistent, TLI.getPointerTy()); - Ops[2] = DAG.getConstant(Order, TLI.getPointerTy()); + Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); + Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); } void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { DebugLoc dl = getCurDebugLoc(); AtomicOrdering Order = I.getOrdering(); + SynchronizationScope Scope = I.getSynchScope(); SDValue InChain = getRoot(); if (TLI.getInsertFencesForAtomic()) - InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, + DAG, TLI); SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, @@ -3316,12 +3325,14 @@ getValue(I.getCompareOperand()), getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, - I.getOrdering(), I.getSynchScope()); + TLI.getInsertFencesForAtomic() ? Monotonic : Order, + Scope); SDValue OutChain = L.getValue(1); if (TLI.getInsertFencesForAtomic()) - OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, + DAG, TLI); setValue(&I, L); DAG.setRoot(OutChain); @@ -3345,11 +3356,13 @@ case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; } AtomicOrdering Order = I.getOrdering(); + SynchronizationScope Scope = I.getSynchScope(); SDValue InChain = getRoot(); if (TLI.getInsertFencesForAtomic()) - InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, + DAG, TLI); SDValue L = DAG.getAtomic(NT, dl, @@ -3359,12 +3372,13 @@ getValue(I.getValOperand()), I.getPointerOperand(), 0 /* Alignment */, TLI.getInsertFencesForAtomic() ? Monotonic : Order, - I.getSynchScope()); + Scope); SDValue OutChain = L.getValue(1); if (TLI.getInsertFencesForAtomic()) - OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, + DAG, TLI); setValue(&I, L); DAG.setRoot(OutChain); @@ -3379,6 +3393,65 @@ DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); } +void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { + DebugLoc dl = getCurDebugLoc(); + AtomicOrdering Order = I.getOrdering(); + SynchronizationScope Scope = I.getSynchScope(); + + SDValue InChain = getRoot(); + + if (TLI.getInsertFencesForAtomic()) + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, + DAG, TLI); + + EVT VT = EVT::getEVT(I.getType()); + + SDValue L = + DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, + getValue(I.getPointerOperand()), + I.getPointerOperand(), I.getAlignment(), + TLI.getInsertFencesForAtomic() ? Monotonic : Order, + Scope); + + SDValue OutChain = L.getValue(1); + + if (TLI.getInsertFencesForAtomic()) + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, + DAG, TLI); + + setValue(&I, L); + DAG.setRoot(OutChain); +} + +void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { + DebugLoc dl = getCurDebugLoc(); + + AtomicOrdering Order = I.getOrdering(); + SynchronizationScope Scope = I.getSynchScope(); + + SDValue InChain = getRoot(); + + if (TLI.getInsertFencesForAtomic()) + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, + DAG, TLI); + + SDValue OutChain = + DAG.getAtomic(ISD::ATOMIC_STORE, dl, + getValue(I.getValueOperand()).getValueType().getSimpleVT(), + InChain, + getValue(I.getPointerOperand()), + getValue(I.getValueOperand()), + I.getPointerOperand(), I.getAlignment(), + TLI.getInsertFencesForAtomic() ? Monotonic : Order, + Scope); + + if (TLI.getInsertFencesForAtomic()) + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, + DAG, TLI); + + DAG.setRoot(OutChain); +} + /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC /// node. void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Wed Aug 24 15:50:09 2011 @@ -526,7 +526,9 @@ void visitPHI(const PHINode &I); void visitCall(const CallInst &I); bool visitMemCmpCall(const CallInst &I); - + void visitAtomicLoad(const LoadInst &I); + void visitAtomicStore(const StoreInst &I); + void visitInlineAsm(ImmutableCallSite CS); const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 15:50:09 2011 @@ -464,6 +464,7 @@ MVT VT = IntVTs[i]; setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); + setOperationAction(ISD::ATOMIC_STORE, VT, Custom); } if (!Subtarget->is64Bit()) { @@ -9999,6 +10000,26 @@ cast(Node)->getSynchScope()); } +static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { + SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); + + // Convert seq_cst store -> xchg + if (cast(Node)->getOrdering() == SequentiallyConsistent) { + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, + cast(Node)->getMemoryVT(), + Node->getOperand(0), + Node->getOperand(1), Node->getOperand(2), + cast(Node)->getSrcValue(), + cast(Node)->getAlignment(), + cast(Node)->getOrdering(), + cast(Node)->getSynchScope()); + return Swap.getValue(1); + } + // Other atomic stores have a simple pattern. + return Op; +} + static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { EVT VT = Op.getNode()->getValueType(0); @@ -10035,6 +10056,7 @@ case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); + case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=138478&r1=138477&r2=138478&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Aug 24 15:50:09 2011 @@ -1691,3 +1691,17 @@ (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; + +def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>; +def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>; +def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>; + +def : Pat<(atomic_store_8 addr:$ptr, GR8:$val), + (MOV8mr addr:$ptr, GR8:$val)>; +def : Pat<(atomic_store_16 addr:$ptr, GR16:$val), + (MOV16mr addr:$ptr, GR16:$val)>; +def : Pat<(atomic_store_32 addr:$ptr, GR32:$val), + (MOV32mr addr:$ptr, GR32:$val)>; +def : Pat<(atomic_store_64 addr:$ptr, GR64:$val), + (MOV64mr addr:$ptr, GR64:$val)>; From zwarich at apple.com Wed Aug 24 16:03:07 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 24 Aug 2011 21:03:07 -0000 Subject: [llvm-commits] [test-suite] r138480 - /test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile Message-ID: <20110824210307.9FD622A6C12C@llvm.org> Author: zwarich Date: Wed Aug 24 16:03:07 2011 New Revision: 138480 URL: http://llvm.org/viewvc/llvm-project?rev=138480&view=rev Log: Make 176.gcc work on Darwin platforms with a lower default stack size. Modified: test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile?rev=138480&r1=138479&r2=138480&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/176.gcc/Makefile Wed Aug 24 16:03:07 2011 @@ -21,6 +21,10 @@ CPPFLAGS += -DHOST_WORDS_BIG_ENDIAN endif +ifeq ($(TARGET_OS),Darwin) + LDFLAGS += -Xlinker -stack_size -Xlinker 0x800000 +endif + ifeq ($(ARCH),Sparc) ## SPEC portability note for GCC says to use these flags and cross fingers: CPPFLAGS += -DSPEC_CPU2000_LP64 From nicholas at mxc.ca Wed Aug 24 16:07:42 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 24 Aug 2011 14:07:42 -0700 Subject: [llvm-commits] [llvm] r138478 - in /llvm/trunk: include/llvm/CodeGen/ISDOpcodes.h include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Target/TargetSelectionDAG.td lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrCompiler.td In-Reply-To: <20110824205009.9A7842A6C12C@llvm.org> References: <20110824205009.9A7842A6C12C@llvm.org> Message-ID: <4E55681E.2030205@mxc.ca> Eli Friedman wrote: > Author: efriedma > Date: Wed Aug 24 15:50:09 2011 > New Revision: 138478 > > URL: http://llvm.org/viewvc/llvm-project?rev=138478&view=rev > Log: > Basic x86 code generation for atomic load and store instructions. Cool! > +static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG&DAG) { > + SDNode *Node = Op.getNode(); > + DebugLoc dl = Node->getDebugLoc(); > + > + // Convert seq_cst store -> xchg > + if (cast(Node)->getOrdering() == SequentiallyConsistent) { > + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, > + cast(Node)->getMemoryVT(), > + Node->getOperand(0), Extra space after = sign, also the rest of these lines don't line up. Nick > + Node->getOperand(1), Node->getOperand(2), > + cast(Node)->getSrcValue(), > + cast(Node)->getAlignment(), > + cast(Node)->getOrdering(), > + cast(Node)->getSynchScope()); > + return Swap.getValue(1); > + } > + // Other atomic stores have a simple pattern. > + return Op; > +} From isanbard at gmail.com Wed Aug 24 16:06:46 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 24 Aug 2011 21:06:46 -0000 Subject: [llvm-commits] [llvm] r138481 - in /llvm/trunk/lib: Analysis/ScalarEvolutionExpander.cpp Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20110824210646.9675C2A6C12C@llvm.org> Author: void Date: Wed Aug 24 16:06:46 2011 New Revision: 138481 URL: http://llvm.org/viewvc/llvm-project?rev=138481&view=rev Log: Skip the landingpad instruction when determining the insertion point. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=138481&r1=138480&r2=138481&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Wed Aug 24 16:06:46 2011 @@ -103,7 +103,8 @@ while ((isa(IP) && isa(cast(IP)->getOperand(0)) && cast(IP)->getOperand(0) != A) || - isa(IP)) + isa(IP) || + isa(IP)) ++IP; return ReuseOrCreateCast(A, Ty, Op, IP); } @@ -113,7 +114,9 @@ BasicBlock::iterator IP = I; ++IP; if (InvokeInst *II = dyn_cast(I)) IP = II->getNormalDest()->begin(); - while (isa(IP) || isa(IP)) ++IP; + while (isa(IP) || isa(IP) || + isa(IP)) + ++IP; return ReuseOrCreateCast(I, Ty, Op, IP); } @@ -1109,7 +1112,8 @@ BasicBlock::iterator SaveInsertPt = Builder.GetInsertPoint(); BasicBlock::iterator NewInsertPt = llvm::next(BasicBlock::iterator(cast(V))); - while (isa(NewInsertPt) || isa(NewInsertPt)) + while (isa(NewInsertPt) || isa(NewInsertPt) || + isa(NewInsertPt)) ++NewInsertPt; V = expandCodeFor(SE.getTruncateExpr(SE.getUnknown(V), Ty), 0, NewInsertPt); Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=138481&r1=138480&r2=138481&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Aug 24 16:06:46 2011 @@ -3423,6 +3423,9 @@ // Don't insert instructions before PHI nodes. while (isa(IP)) ++IP; + // Ignore landingpad instructions. + while (isa(IP)) ++IP; + // Ignore debug intrinsics. while (isa(IP)) ++IP; From eli.friedman at gmail.com Wed Aug 24 16:16:59 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 21:16:59 -0000 Subject: [llvm-commits] [llvm] r138486 - /llvm/trunk/test/CodeGen/X86/atomic-load-store.ll Message-ID: <20110824211659.7AA022A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 16:16:59 2011 New Revision: 138486 URL: http://llvm.org/viewvc/llvm-project?rev=138486&view=rev Log: Basic tests for atomic load and store on x86. Added: llvm/trunk/test/CodeGen/X86/atomic-load-store.ll Added: llvm/trunk/test/CodeGen/X86/atomic-load-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-load-store.ll?rev=138486&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic-load-store.ll (added) +++ llvm/trunk/test/CodeGen/X86/atomic-load-store.ll Wed Aug 24 16:16:59 2011 @@ -0,0 +1,22 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 | FileCheck %s + +define void @test1(i32* %ptr, i32 %val1) { +; CHECK: test1 +; CHECK: xchgl %esi, (%rdi) + store atomic i32 %val1, i32* %ptr seq_cst, align 4 + ret void +} + +define void @test2(i32* %ptr, i32 %val1) { +; CHECK: test2 +; CHECK: movl %esi, (%rdi) + store atomic i32 %val1, i32* %ptr release, align 4 + ret void +} + +define i32 @test3(i32* %ptr) { +; CHECK: test3 +; CHECK: movl (%rdi), %eax + %val = load atomic i32* %ptr seq_cst, align 4 + ret i32 %val +} From eli.friedman at gmail.com Wed Aug 24 16:17:30 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 21:17:30 -0000 Subject: [llvm-commits] [llvm] r138487 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110824211730.55EBD2A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 16:17:30 2011 New Revision: 138487 URL: http://llvm.org/viewvc/llvm-project?rev=138487&view=rev Log: Fix whitespace. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138487&r1=138486&r2=138487&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 16:17:30 2011 @@ -10006,14 +10006,14 @@ // Convert seq_cst store -> xchg if (cast(Node)->getOrdering() == SequentiallyConsistent) { - SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, - cast(Node)->getMemoryVT(), - Node->getOperand(0), - Node->getOperand(1), Node->getOperand(2), - cast(Node)->getSrcValue(), - cast(Node)->getAlignment(), - cast(Node)->getOrdering(), - cast(Node)->getSynchScope()); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, + cast(Node)->getMemoryVT(), + Node->getOperand(0), + Node->getOperand(1), Node->getOperand(2), + cast(Node)->getSrcValue(), + cast(Node)->getAlignment(), + cast(Node)->getOrdering(), + cast(Node)->getSynchScope()); return Swap.getValue(1); } // Other atomic stores have a simple pattern. From grosbach at apple.com Wed Aug 24 16:22:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 21:22:15 -0000 Subject: [llvm-commits] [llvm] r138488 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s utils/TableGen/EDEmitter.cpp Message-ID: <20110824212215.56BBC2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 16:22:15 2011 New Revision: 138488 URL: http://llvm.org/viewvc/llvm-project?rev=138488&view=rev Log: Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s llvm/trunk/test/MC/ARM/thumb-diagnostics.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138488&r1=138487&r2=138488&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 16:22:15 2011 @@ -78,8 +78,17 @@ } // Scaled 4 immediate. -def t_imm_s4 : Operand { +def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } +def t_imm0_1020s4 : Operand { let PrintMethod = "printThumbS4ImmOperand"; + let ParserMatchClass = t_imm0_1020s4_asmoperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } +def t_imm0_508s4 : Operand { + let PrintMethod = "printThumbS4ImmOperand"; + let ParserMatchClass = t_imm0_508s4_asmoperand; let OperandType = "OPERAND_IMMEDIATE"; } @@ -305,35 +314,39 @@ // This is rematerializable, which is particularly useful for taking the // address of locals. let isReMaterializable = 1 in -def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm_s4:$rhs), IIC_iALUi, - "add", "\t$dst, $sp, $rhs", []>, +def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), + IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, T1Encoding<{1,0,1,0,1,?}> { // A6.2 & A8.6.8 bits<3> dst; - bits<8> rhs; + bits<8> imm; let Inst{10-8} = dst; - let Inst{7-0} = rhs; + let Inst{7-0} = imm; let DecoderMethod = "DecodeThumbAddSpecialReg"; } // ADD sp, sp, # -def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs), - IIC_iALUi, "add", "\t$Rdn, $rhs", []>, +def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), + IIC_iALUi, "add", "\t$Rdn, $imm", []>, T1Misc<{0,0,0,0,0,?,?}> { // A6.2.5 & A8.6.8 - bits<7> rhs; - let Inst{6-0} = rhs; + bits<7> imm; + let Inst{6-0} = imm; let DecoderMethod = "DecodeThumbAddSPImm"; } +// Can optionally specify SP as a three operand instruction. +def : tInstAlias<"add${p} sp, sp, $imm", + (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; + // SUB sp, sp, # // FIXME: The encoding and the ASM string don't match up. -def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs), - IIC_iALUi, "sub", "\t$Rdn, $rhs", []>, +def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), + IIC_iALUi, "sub", "\t$Rdn, $imm", []>, T1Misc<{0,0,0,0,1,?,?}> { // A6.2.5 & A8.6.214 - bits<7> rhs; - let Inst{6-0} = rhs; + bits<7> imm; + let Inst{6-0} = imm; let DecoderMethod = "DecodeThumbAddSPImm"; } @@ -350,13 +363,13 @@ } // ADD sp, -def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$rhs), IIC_iALUr, - "add", "\t$Rdn, $rhs", []>, +def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, + "add", "\t$Rdn, $Rm", []>, T1Special<{0,0,?,?}> { // A8.6.9 Encoding T2 - bits<4> Rdn; + bits<4> Rm; let Inst{7} = 1; - let Inst{6-3} = Rdn; + let Inst{6-3} = Rm; let Inst{2-0} = 0b101; let DecoderMethod = "DecodeThumbAddSPReg"; } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138488&r1=138487&r2=138488&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 16:22:15 2011 @@ -412,6 +412,22 @@ bool isCondCode() const { return Kind == CondCode; } bool isCCOut() const { return Kind == CCOut; } bool isImm() const { return Kind == Immediate; } + bool isImm0_1020s4() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; + } + bool isImm0_508s4() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return ((Value & 3) == 0) && Value >= 0 && Value <= 508; + } bool isImm0_255() const { if (Kind != Immediate) return false; @@ -791,6 +807,22 @@ addExpr(Inst, getImm()); } + void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate is scaled by four in the encoding and is stored + // in the MCInst as such. Lop off the low two bits here. + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); + } + + void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate is scaled by four in the encoding and is stored + // in the MCInst as such. Lop off the low two bits here. + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); + } + void addImm0_255Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); @@ -2883,6 +2915,21 @@ static_cast(Operands[4])->isReg() && static_cast(Operands[1])->getReg() == 0) return true; + // Register-register 'add' for thumb does not have a cc_out operand + // when it's an ADD Rdm, SP, {Rdm|#imm} instruction. + if (isThumb() && Mnemonic == "add" && Operands.size() == 6 && + static_cast(Operands[3])->isReg() && + static_cast(Operands[4])->isReg() && + static_cast(Operands[4])->getReg() == ARM::SP && + static_cast(Operands[1])->getReg() == 0) + return true; + // Register-register 'add' for thumb does not have a cc_out operand + // when it's an ADD SP, #imm. + if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && + static_cast(Operands[3])->isReg() && + static_cast(Operands[3])->getReg() == ARM::SP && + static_cast(Operands[1])->getReg() == 0) + return true; return false; } Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138488&r1=138487&r2=138488&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 24 16:22:15 2011 @@ -45,11 +45,29 @@ @------------------------------------------------------------------------------ -@ FIXME: ADD (SP plus immediate) +@ ADD (SP plus immediate) @------------------------------------------------------------------------------ + add sp, #4 + add sp, #508 + add sp, sp, #4 + add r2, sp, #8 + add r2, sp, #1020 + +@ CHECK: add sp, #4 @ encoding: [0x01,0xb0] +@ CHECK: add sp, #508 @ encoding: [0x7f,0xb0] +@ CHECK: add sp, #4 @ encoding: [0x01,0xb0] +@ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa] +@ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa] + + @------------------------------------------------------------------------------ -@ FIXME: ADD (SP plus register) +@ ADD (SP plus register) @------------------------------------------------------------------------------ + add sp, r3 + add r2, sp, r2 + +@ CHECK: add sp, r3 @ encoding: [0x9d,0x44] +@ CHECK: add r2, sp, r2 @ encoding: [0x6a,0x44] @------------------------------------------------------------------------------ Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138488&r1=138487&r2=138488&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original) +++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Wed Aug 24 16:22:15 2011 @@ -118,3 +118,22 @@ @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled @ CHECK-ERRORS: svc #256 @ CHECK-ERRORS: ^ + + +@ Out of range immediate for ADD SP instructions + add sp, #-1 + add sp, #3 + add sp, sp, #512 + add r2, sp, #1024 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add sp, #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add sp, #3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add sp, sp, #512 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add r2, sp, #1024 +@ CHECK-ERRORS: ^ Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=138488&r1=138487&r2=138488&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Aug 24 16:22:15 2011 @@ -603,7 +603,8 @@ IMM("pkh_lsl_amt"); IMM("pkh_asr_amt"); IMM("jt2block_operand"); - IMM("t_imm_s4"); + IMM("t_imm0_1020s4"); + IMM("t_imm0_508s4"); IMM("pclabel"); IMM("adrlabel"); IMM("t_adrlabel"); From baldrick at free.fr Wed Aug 24 16:35:13 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Aug 2011 21:35:13 -0000 Subject: [llvm-commits] [dragonegg] r138491 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110824213513.CC7AB2A6C12C@llvm.org> Author: baldrick Date: Wed Aug 24 16:35:13 2011 New Revision: 138491 URL: http://llvm.org/viewvc/llvm-project?rev=138491&view=rev Log: Port commit 138453 (evancheng) from llvm-gcc. Original commit message: TargetRegistry has been moved to Support. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=138491&r1=138490&r2=138491&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Wed Aug 24 16:35:13 2011 @@ -42,9 +42,9 @@ #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLibraryInfo.h" -#include "llvm/Target/TargetRegistry.h" #include "llvm/Transforms/IPO.h" #include "llvm/Transforms/IPO/PassManagerBuilder.h" From resistor at mac.com Wed Aug 24 16:35:46 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Aug 2011 21:35:46 -0000 Subject: [llvm-commits] [llvm] r138492 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Message-ID: <20110824213547.0043E2A6C12C@llvm.org> Author: resistor Date: Wed Aug 24 16:35:46 2011 New Revision: 138492 URL: http://llvm.org/viewvc/llvm-project?rev=138492&view=rev Log: Be careful not to walk off the end of the operand info list while updating VFP predicates. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138492&r1=138491&r2=138492&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 24 16:35:46 2011 @@ -417,7 +417,8 @@ const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; MCInst::iterator I = MI.begin(); - for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { + unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; + for (unsigned i = 0; i < NumOps; ++i, ++I) { if (OpInfo[i].isPredicate() ) { I->setImm(CC); ++I; From grosbach at apple.com Wed Aug 24 16:42:28 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 21:42:28 -0000 Subject: [llvm-commits] [llvm] r138494 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110824214228.20F3B2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 16:42:27 2011 New Revision: 138494 URL: http://llvm.org/viewvc/llvm-project?rev=138494&view=rev Log: Thumb parsing and encoding for SUB (SP minu immediate). Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that form is Thumb2 only. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138494&r1=138493&r2=138494&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 16:42:27 2011 @@ -335,10 +335,6 @@ let DecoderMethod = "DecodeThumbAddSPImm"; } -// Can optionally specify SP as a three operand instruction. -def : tInstAlias<"add${p} sp, sp, $imm", - (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; - // SUB sp, sp, # // FIXME: The encoding and the ASM string don't match up. def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), @@ -350,6 +346,12 @@ let DecoderMethod = "DecodeThumbAddSPImm"; } +// Can optionally specify SP as a three operand instruction. +def : tInstAlias<"add${p} sp, sp, $imm", + (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; +def : tInstAlias<"sub${p} sp, sp, $imm", + (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; + // ADD , sp def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr, "add", "\t$Rdn, $sp, $Rn", []>, Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138494&r1=138493&r2=138494&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 16:42:27 2011 @@ -2923,9 +2923,13 @@ static_cast(Operands[4])->getReg() == ARM::SP && static_cast(Operands[1])->getReg() == 0) return true; - // Register-register 'add' for thumb does not have a cc_out operand - // when it's an ADD SP, #imm. - if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && + // Register-register 'add/sub' for thumb does not have a cc_out operand + // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also + // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't + // right, this will result in better diagnostics (which operand is off) + // anyway. + if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && + (Operands.size() == 5 || Operands.size() == 6) && static_cast(Operands[3])->isReg() && static_cast(Operands[3])->getReg() == ARM::SP && static_cast(Operands[1])->getReg() == 0) Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138494&r1=138493&r2=138494&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 24 16:42:27 2011 @@ -538,11 +538,13 @@ @------------------------------------------------------------------------------ -@ FIXME: SUB (SP minus immediate) - at ------------------------------------------------------------------------------ - at ------------------------------------------------------------------------------ -@ FIXME: SUB (SP minus register) +@ SUB (SP minus immediate) @------------------------------------------------------------------------------ + sub sp, #12 + sub sp, sp, #508 + +@ CHECK: sub sp, #12 @ encoding: [0x83,0xb0] +@ CHECK: sub sp, #508 @ encoding: [0xff,0xb0] @------------------------------------------------------------------------------ From chandlerc at google.com Wed Aug 24 17:02:58 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 24 Aug 2011 15:02:58 -0700 Subject: [llvm-commits] [llvm] r138478 - in /llvm/trunk: include/llvm/CodeGen/ISDOpcodes.h include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Target/TargetSelectionDAG.td lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/ Message-ID: On Wed, Aug 24, 2011 at 1:50 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Aug 24 15:50:09 2011 > New Revision: 138478 > > URL: http://llvm.org/viewvc/llvm-project?rev=138478&view=rev > Log: > Basic x86 code generation for atomic load and store instructions. > > > Modified: > llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h > llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > llvm/trunk/include/llvm/Target/TargetSelectionDAG.td > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/lib/Target/X86/X86InstrCompiler.td > Wait, no tests? None at all? =[ > > Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Wed Aug 24 15:50:09 2011 > @@ -597,22 +597,22 @@ > // two integer constants: an AtomicOrdering and a SynchronizationScope. > ATOMIC_FENCE, > > + // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) > + // This corresponds to "load atomic" instruction. > + ATOMIC_LOAD, > + > + // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) > + // This corresponds to "store atomic" instruction. > + ATOMIC_STORE, > + > // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) > - // this corresponds to the atomic.lcs intrinsic. > - // cmp is compared to *ptr, and if equal, swap is stored in *ptr. > - // the return is always the original value in *ptr > + // This corresponds to the cmpxchg instruction. > ATOMIC_CMP_SWAP, > > // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) > - // this corresponds to the atomic.swap intrinsic. > - // amt is stored to *ptr atomically. > - // the return is always the original value in *ptr > - ATOMIC_SWAP, > - > // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) > - // this corresponds to the atomic.load.[OpName] intrinsic. > - // op(*ptr, amt) is stored to *ptr atomically. > - // the return is always the original value in *ptr > + // These correspond to the atomicrmw instruction. > + ATOMIC_SWAP, > ATOMIC_LOAD_ADD, > ATOMIC_LOAD_SUB, > ATOMIC_LOAD_AND, > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Aug 24 15:50:09 2011 > @@ -598,16 +598,26 @@ > AtomicOrdering Ordering, > SynchronizationScope SynchScope); > > - /// getAtomic - Gets a node for an atomic op, produces result and chain > and > - /// takes 2 operands. > + /// getAtomic - Gets a node for an atomic op, produces result (if > relevant) > + /// and chain and takes 2 operands. > SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, > SDValue Ptr, SDValue Val, const Value* PtrVal, > + unsigned Alignment, AtomicOrdering Ordering, > + SynchronizationScope SynchScope); > + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue > Chain, > + SDValue Ptr, SDValue Val, MachineMemOperand *MMO, > + AtomicOrdering Ordering, > + SynchronizationScope SynchScope); > + > + /// getAtomic - Gets a node for an atomic op, produces result and chain > and > + /// takes 1 operand. > + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, > + SDValue Chain, SDValue Ptr, const Value* PtrVal, > unsigned Alignment, > AtomicOrdering Ordering, > SynchronizationScope SynchScope); > - SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue > Chain, > - SDValue Ptr, SDValue Val, > - MachineMemOperand *MMO, > + SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, > + SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, > AtomicOrdering Ordering, > SynchronizationScope SynchScope); > > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Aug 24 15:50:09 > 2011 > @@ -976,6 +976,8 @@ > N->getOpcode() == ISD::ATOMIC_LOAD_MAX || > N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || > N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || > + N->getOpcode() == ISD::ATOMIC_LOAD || > + N->getOpcode() == ISD::ATOMIC_STORE || > N->isTargetMemoryOpcode(); > } > }; > @@ -1025,6 +1027,14 @@ > InitAtomic(Ordering, SynchScope); > InitOperands(Ops, Chain, Ptr, Val); > } > + AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT, > + SDValue Chain, SDValue Ptr, > + MachineMemOperand *MMO, > + AtomicOrdering Ordering, SynchronizationScope SynchScope) > + : MemSDNode(Opc, dl, VTL, MemVT, MMO) { > + InitAtomic(Ordering, SynchScope); > + InitOperands(Ops, Chain, Ptr); > + } > > const SDValue &getBasePtr() const { return getOperand(1); } > const SDValue &getVal() const { return getOperand(2); } > @@ -1048,7 +1058,9 @@ > N->getOpcode() == ISD::ATOMIC_LOAD_MIN || > N->getOpcode() == ISD::ATOMIC_LOAD_MAX || > N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || > - N->getOpcode() == ISD::ATOMIC_LOAD_UMAX; > + N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || > + N->getOpcode() == ISD::ATOMIC_LOAD || > + N->getOpcode() == ISD::ATOMIC_STORE; > } > }; > > > Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) > +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Wed Aug 24 > 15:50:09 2011 > @@ -214,6 +214,12 @@ > def SDTAtomic2 : SDTypeProfile<1, 2, [ > SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> > ]>; > +def SDTAtomicStore : SDTypeProfile<0, 2, [ > + SDTCisPtrTy<0>, SDTCisInt<1> > +]>; > +def SDTAtomicLoad : SDTypeProfile<1, 1, [ > + SDTCisInt<0>, SDTCisPtrTy<1> > +]>; > > def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, > sf, su > SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, > SDTCisPtrTy<5> > @@ -427,6 +433,10 @@ > [SDNPHasChain, SDNPMayStore, SDNPMayLoad, > SDNPMemOperand]>; > def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, > [SDNPHasChain, SDNPMayStore, SDNPMayLoad, > SDNPMemOperand]>; > +def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, > SDNPMemOperand]>; > +def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, > SDNPMemOperand]>; > > // Do not use ld, st directly. Use load, extload, sextload, zextload, > store, > // and truncst (see below). > @@ -844,6 +854,28 @@ > defm atomic_load_max : binary_atomic_op; > defm atomic_load_umin : binary_atomic_op; > defm atomic_load_umax : binary_atomic_op; > +defm atomic_store : binary_atomic_op; > + > +def atomic_load_8 : > + PatFrag<(ops node:$ptr), > + (atomic_load node:$ptr), [{ > + return cast(N)->getMemoryVT() == MVT::i8; > +}]>; > +def atomic_load_16 : > + PatFrag<(ops node:$ptr), > + (atomic_load node:$ptr), [{ > + return cast(N)->getMemoryVT() == MVT::i16; > +}]>; > +def atomic_load_32 : > + PatFrag<(ops node:$ptr), > + (atomic_load node:$ptr), [{ > + return cast(N)->getMemoryVT() == MVT::i32; > +}]>; > +def atomic_load_64 : > + PatFrag<(ops node:$ptr), > + (atomic_load node:$ptr), [{ > + return cast(N)->getMemoryVT() == MVT::i64; > +}]>; > > > //===----------------------------------------------------------------------===// > // Selection DAG CONVERT_RNDSAT patterns > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 24 15:50:09 > 2011 > @@ -819,6 +819,11 @@ > Action = TLI.getOperationAction(Node->getOpcode(), InnerType); > break; > } > + case ISD::ATOMIC_STORE: { > + Action = TLI.getOperationAction(Node->getOpcode(), > + Node->getOperand(2).getValueType()); > + break; > + } > case ISD::SELECT_CC: > case ISD::SETCC: > case ISD::BR_CC: { > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 24 > 15:50:09 2011 > @@ -432,7 +432,9 @@ > case ISD::ATOMIC_LOAD_MIN: > case ISD::ATOMIC_LOAD_MAX: > case ISD::ATOMIC_LOAD_UMIN: > - case ISD::ATOMIC_LOAD_UMAX: { > + case ISD::ATOMIC_LOAD_UMAX: > + case ISD::ATOMIC_LOAD: > + case ISD::ATOMIC_STORE: { > const AtomicSDNode *AT = cast(N); > ID.AddInteger(AT->getMemoryVT().getRawBits()); > ID.AddInteger(AT->getRawSubclassData()); > @@ -3904,12 +3906,14 @@ > Opcode == ISD::ATOMIC_LOAD_MAX || > Opcode == ISD::ATOMIC_LOAD_UMIN || > Opcode == ISD::ATOMIC_LOAD_UMAX || > - Opcode == ISD::ATOMIC_SWAP) && > + Opcode == ISD::ATOMIC_SWAP || > + Opcode == ISD::ATOMIC_STORE) && > "Invalid Atomic Op"); > > EVT VT = Val.getValueType(); > > - SDVTList VTs = getVTList(VT, MVT::Other); > + SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) : > + getVTList(VT, MVT::Other); > FoldingSetNodeID ID; > ID.AddInteger(MemVT.getRawBits()); > SDValue Ops[] = {Chain, Ptr, Val}; > @@ -3927,6 +3931,55 @@ > return SDValue(N, 0); > } > > +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, > + EVT VT, SDValue Chain, > + SDValue Ptr, > + const Value* PtrVal, > + unsigned Alignment, > + AtomicOrdering Ordering, > + SynchronizationScope SynchScope) { > + if (Alignment == 0) // Ensure that codegen never sees alignment 0 > + Alignment = getEVTAlignment(MemVT); > + > + MachineFunction &MF = getMachineFunction(); > + unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; > + > + // For now, atomics are considered to be volatile always. > + Flags |= MachineMemOperand::MOVolatile; > + > + MachineMemOperand *MMO = > + MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags, > + MemVT.getStoreSize(), Alignment); > + > + return getAtomic(Opcode, dl, MemVT, VT, Chain, Ptr, MMO, > + Ordering, SynchScope); > +} > + > +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, > + EVT VT, SDValue Chain, > + SDValue Ptr, > + MachineMemOperand *MMO, > + AtomicOrdering Ordering, > + SynchronizationScope SynchScope) { > + assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op"); > + > + SDVTList VTs = getVTList(VT, MVT::Other); > + FoldingSetNodeID ID; > + ID.AddInteger(MemVT.getRawBits()); > + SDValue Ops[] = {Chain, Ptr}; > + AddNodeIDNode(ID, Opcode, VTs, Ops, 2); > + void* IP = 0; > + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { > + cast(E)->refineAlignment(MMO); > + return SDValue(E, 0); > + } > + SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, > Chain, > + Ptr, MMO, Ordering, > SynchScope); > + CSEMap.InsertNode(N, IP); > + AllNodes.push_back(N); > + return SDValue(N, 0); > +} > + > /// getMergeValues - Create a MERGE_VALUES node from the given operands. > SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, > DebugLoc dl) { > @@ -5795,6 +5848,8 @@ > case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; > case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; > case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; > + case ISD::ATOMIC_LOAD: return "AtomicLoad"; > + case ISD::ATOMIC_STORE: return "AtomicStore"; > case ISD::PCMARKER: return "PCMarker"; > case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; > case ISD::SRCVALUE: return "SrcValue"; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Aug 24 > 15:50:09 2011 > @@ -3149,6 +3149,9 @@ > } > > void SelectionDAGBuilder::visitLoad(const LoadInst &I) { > + if (I.isAtomic()) > + return visitAtomicLoad(I); > + > const Value *SV = I.getOperand(0); > SDValue Ptr = getValue(SV); > > @@ -3226,6 +3229,9 @@ > } > > void SelectionDAGBuilder::visitStore(const StoreInst &I) { > + if (I.isAtomic()) > + return visitAtomicStore(I); > + > const Value *SrcV = I.getOperand(0); > const Value *PtrV = I.getOperand(1); > > @@ -3277,6 +3283,7 @@ > } > > static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, > + SynchronizationScope Scope, > bool Before, DebugLoc dl, > SelectionDAG &DAG, > const TargetLowering &TLI) { > @@ -3294,19 +3301,21 @@ > } > SDValue Ops[3]; > Ops[0] = Chain; > - Ops[1] = DAG.getConstant(SequentiallyConsistent, TLI.getPointerTy()); > - Ops[2] = DAG.getConstant(Order, TLI.getPointerTy()); > + Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); > + Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); > return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); > } > > void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { > DebugLoc dl = getCurDebugLoc(); > AtomicOrdering Order = I.getOrdering(); > + SynchronizationScope Scope = I.getSynchScope(); > > SDValue InChain = getRoot(); > > if (TLI.getInsertFencesForAtomic()) > - InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); > + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, > + DAG, TLI); > > SDValue L = > DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, > @@ -3316,12 +3325,14 @@ > getValue(I.getCompareOperand()), > getValue(I.getNewValOperand()), > MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment > */, > - I.getOrdering(), I.getSynchScope()); > + TLI.getInsertFencesForAtomic() ? Monotonic : Order, > + Scope); > > SDValue OutChain = L.getValue(1); > > if (TLI.getInsertFencesForAtomic()) > - OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); > + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, > + DAG, TLI); > > setValue(&I, L); > DAG.setRoot(OutChain); > @@ -3345,11 +3356,13 @@ > case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; > } > AtomicOrdering Order = I.getOrdering(); > + SynchronizationScope Scope = I.getSynchScope(); > > SDValue InChain = getRoot(); > > if (TLI.getInsertFencesForAtomic()) > - InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); > + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, > + DAG, TLI); > > SDValue L = > DAG.getAtomic(NT, dl, > @@ -3359,12 +3372,13 @@ > getValue(I.getValOperand()), > I.getPointerOperand(), 0 /* Alignment */, > TLI.getInsertFencesForAtomic() ? Monotonic : Order, > - I.getSynchScope()); > + Scope); > > SDValue OutChain = L.getValue(1); > > if (TLI.getInsertFencesForAtomic()) > - OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); > + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, > + DAG, TLI); > > setValue(&I, L); > DAG.setRoot(OutChain); > @@ -3379,6 +3393,65 @@ > DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); > } > > +void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { > + DebugLoc dl = getCurDebugLoc(); > + AtomicOrdering Order = I.getOrdering(); > + SynchronizationScope Scope = I.getSynchScope(); > + > + SDValue InChain = getRoot(); > + > + if (TLI.getInsertFencesForAtomic()) > + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, > + DAG, TLI); > + > + EVT VT = EVT::getEVT(I.getType()); > + > + SDValue L = > + DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, > + getValue(I.getPointerOperand()), > + I.getPointerOperand(), I.getAlignment(), > + TLI.getInsertFencesForAtomic() ? Monotonic : Order, > + Scope); > + > + SDValue OutChain = L.getValue(1); > + > + if (TLI.getInsertFencesForAtomic()) > + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, > + DAG, TLI); > + > + setValue(&I, L); > + DAG.setRoot(OutChain); > +} > + > +void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { > + DebugLoc dl = getCurDebugLoc(); > + > + AtomicOrdering Order = I.getOrdering(); > + SynchronizationScope Scope = I.getSynchScope(); > + > + SDValue InChain = getRoot(); > + > + if (TLI.getInsertFencesForAtomic()) > + InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, > + DAG, TLI); > + > + SDValue OutChain = > + DAG.getAtomic(ISD::ATOMIC_STORE, dl, > + > getValue(I.getValueOperand()).getValueType().getSimpleVT(), > + InChain, > + getValue(I.getPointerOperand()), > + getValue(I.getValueOperand()), > + I.getPointerOperand(), I.getAlignment(), > + TLI.getInsertFencesForAtomic() ? Monotonic : Order, > + Scope); > + > + if (TLI.getInsertFencesForAtomic()) > + OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, > + DAG, TLI); > + > + DAG.setRoot(OutChain); > +} > + > /// visitTargetIntrinsic - Lower a call of a target intrinsic to an > INTRINSIC > /// node. > void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Wed Aug 24 > 15:50:09 2011 > @@ -526,7 +526,9 @@ > void visitPHI(const PHINode &I); > void visitCall(const CallInst &I); > bool visitMemCmpCall(const CallInst &I); > - > + void visitAtomicLoad(const LoadInst &I); > + void visitAtomicStore(const StoreInst &I); > + > void visitInlineAsm(ImmutableCallSite CS); > const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); > void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 15:50:09 2011 > @@ -464,6 +464,7 @@ > MVT VT = IntVTs[i]; > setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); > setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); > + setOperationAction(ISD::ATOMIC_STORE, VT, Custom); > } > > if (!Subtarget->is64Bit()) { > @@ -9999,6 +10000,26 @@ > cast(Node)->getSynchScope()); > } > > +static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { > + SDNode *Node = Op.getNode(); > + DebugLoc dl = Node->getDebugLoc(); > + > + // Convert seq_cst store -> xchg > + if (cast(Node)->getOrdering() == SequentiallyConsistent) { > + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, > + cast(Node)->getMemoryVT(), > + Node->getOperand(0), > + Node->getOperand(1), > Node->getOperand(2), > + > cast(Node)->getSrcValue(), > + > cast(Node)->getAlignment(), > + > cast(Node)->getOrdering(), > + > cast(Node)->getSynchScope()); > + return Swap.getValue(1); > + } > + // Other atomic stores have a simple pattern. > + return Op; > +} > + > static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { > EVT VT = Op.getNode()->getValueType(0); > > @@ -10035,6 +10056,7 @@ > case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); > case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); > case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); > + case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); > case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); > case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); > case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); > > Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=138478&r1=138477&r2=138478&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Aug 24 15:50:09 2011 > @@ -1691,3 +1691,17 @@ > (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; > def : Pat<(and GR64:$src1, i64immSExt32:$src2), > (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; > + > +def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>; > +def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>; > +def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>; > +def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>; > + > +def : Pat<(atomic_store_8 addr:$ptr, GR8:$val), > + (MOV8mr addr:$ptr, GR8:$val)>; > +def : Pat<(atomic_store_16 addr:$ptr, GR16:$val), > + (MOV16mr addr:$ptr, GR16:$val)>; > +def : Pat<(atomic_store_32 addr:$ptr, GR32:$val), > + (MOV32mr addr:$ptr, GR32:$val)>; > +def : Pat<(atomic_store_64 addr:$ptr, GR64:$val), > + (MOV64mr addr:$ptr, GR64:$val)>; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/1add7ec7/attachment-0001.html From chandlerc at google.com Wed Aug 24 17:03:23 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 24 Aug 2011 15:03:23 -0700 Subject: [llvm-commits] [llvm] r138486 - /llvm/trunk/test/CodeGen/X86/atomic-load-store.ll In-Reply-To: <20110824211659.7AA022A6C12C@llvm.org> References: <20110824211659.7AA022A6C12C@llvm.org> Message-ID: On Wed, Aug 24, 2011 at 2:16 PM, Eli Friedman wrote: > Basic tests for atomic load and store on x86. > Ahh, I see. Sorry for responding to the previous before seeing this one. =D -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/bef54061/attachment.html From grosbach at apple.com Wed Aug 24 17:19:48 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 22:19:48 -0000 Subject: [llvm-commits] [llvm] r138500 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110824221948.7D6E62A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 17:19:48 2011 New Revision: 138500 URL: http://llvm.org/viewvc/llvm-project?rev=138500&view=rev Log: Thumb .n mnemonic qualifiers can be ignored for now. We'll need to pay attention to them when we start getting more serious about the details of parsing thumb2 assembly. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138500&r1=138499&r2=138500&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 17:19:48 2011 @@ -3015,7 +3015,11 @@ Next = Name.find('.', Start + 1); StringRef ExtraToken = Name.slice(Start, Next); - Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); + // For now, we're only parsing Thumb1 (for the most part), so + // just ignore ".n" qualifiers. We'll use them to restrict + // matching when we do Thumb2. + if (ExtraToken != ".n") + Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); } // Read the remaining operands. From grosbach at apple.com Wed Aug 24 17:27:35 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 22:27:35 -0000 Subject: [llvm-commits] [llvm] r138501 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Message-ID: <20110824222735.B61A32A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 17:27:35 2011 New Revision: 138501 URL: http://llvm.org/viewvc/llvm-project?rev=138501&view=rev Log: ARM asm backend initialize isThumbMode based on target triple. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=138501&r1=138500&r2=138501&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Aug 24 17:27:35 2011 @@ -42,7 +42,7 @@ public: ARMAsmBackend(const Target &T, const StringRef TT) : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), - isThumbMode(false) {} + isThumbMode(TT.startswith("thumb")) {} ~ARMAsmBackend() { delete STI; From grosbach at apple.com Wed Aug 24 17:30:18 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 24 Aug 2011 22:30:18 -0000 Subject: [llvm-commits] [llvm] r138502 - /llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll Message-ID: <20110824223018.544BF2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 24 17:30:18 2011 New Revision: 138502 URL: http://llvm.org/viewvc/llvm-project?rev=138502&view=rev Log: Update tests for 138501. Modified: llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll Modified: llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll?rev=138502&r1=138501&r2=138502&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll (original) +++ llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll Wed Aug 24 17:30:18 2011 @@ -22,7 +22,7 @@ ; make sure that bl 0 (fff7feff) is correctly encoded -; CHECK: '_section_data', '70470000 2de90048 fff7feff bde80088' +; CHECK: '_section_data', '704700bf 2de90048 fff7feff bde80088' ; Offset Info Type Sym.Value Sym. Name ; 00000008 0000070a R_ARM_THM_CALL 00000001 foo From evan.cheng at apple.com Wed Aug 24 17:31:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Aug 2011 22:31:37 -0000 Subject: [llvm-commits] [llvm] r138504 - in /llvm/trunk: lib/MC/MCDwarf.cpp lib/MC/MCStreamer.cpp test/MC/MachO/debug_frame.s Message-ID: <20110824223137.38CA92A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 17:31:37 2011 New Revision: 138504 URL: http://llvm.org/viewvc/llvm-project?rev=138504&view=rev Log: Some autoconf tests use module level inline asm to test compiler's handling of .cfi_startproc. e.g. libffi: $ cat confopt.c asm (".cfi_startproc\n\t.cfi_endproc"); int main () { return 0; } Teach MC / dwarf emission to handle these cfi directives which essentially create an empty frame. rdar://10017184 Modified: llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/MC/MCStreamer.cpp llvm/trunk/test/MC/MachO/debug_frame.s Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=138504&r1=138503&r2=138504&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Aug 24 17:31:37 2011 @@ -895,7 +895,7 @@ const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); bool verboseAsm = streamer.isVerboseAsm(); - if (!MOFI->isFunctionEHFrameSymbolPrivate() && IsEH) { + if (IsEH && frame.Function && !MOFI->isFunctionEHFrameSymbolPrivate()) { MCSymbol *EHSym = context.GetOrCreateSymbol(frame.Function->getName() + Twine(".eh")); streamer.EmitEHSymAttributes(frame.Function, EHSym); Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=138504&r1=138503&r2=138504&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Aug 24 17:31:37 2011 @@ -190,14 +190,14 @@ MCDwarfFrameInfo *CurFrame = getCurrentFrameInfo(); if (CurFrame && !CurFrame->End) report_fatal_error("Starting a frame before finishing the previous one!"); - MCDwarfFrameInfo Frame; + MCDwarfFrameInfo Frame; Frame.Function = LastSymbol; // If the function is externally visible, we need to create a local // symbol to avoid relocations. StringRef Prefix = getContext().getAsmInfo().getPrivateGlobalPrefix(); - if (LastSymbol->getName().startswith(Prefix)) { + if (LastSymbol && LastSymbol->getName().startswith(Prefix)) { Frame.Begin = LastSymbol; } else { Frame.Begin = getContext().CreateTempSymbol(); Modified: llvm/trunk/test/MC/MachO/debug_frame.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/debug_frame.s?rev=138504&r1=138503&r2=138504&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/debug_frame.s (original) +++ llvm/trunk/test/MC/MachO/debug_frame.s Wed Aug 24 17:31:37 2011 @@ -1,5 +1,11 @@ // RUN: llvm-mc -triple i386-apple-darwin %s -filetype=obj -o - | macho-dump | FileCheck %s +// Make sure MC can handle file level .cfi_startproc and .cfi_endproc that creates +// an empty frame. +// rdar://10017184 +.cfi_startproc +.cfi_endproc + // Check that we don't produce a relocation for the CIE pointer and therefore // we have only one relocation in __debug_frame. @@ -22,17 +28,20 @@ // CHECK: (('section_name', '__debug_frame\x00\x00\x00') // CHECK-NEXT: ('segment_name', '__DWARF\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK-NEXT: ('address', 8) -// CHECK-NEXT: ('size', 36) +// CHECK-NEXT: ('size', 52) // CHECK-NEXT: ('offset', 332) // CHECK-NEXT: ('alignment', 2) -// CHECK-NEXT: ('reloc_offset', 368) -// CHECK-NEXT: ('num_reloc', 1) +// CHECK-NEXT: ('reloc_offset', 384) +// CHECK-NEXT: ('num_reloc', 2) // CHECK-NEXT: ('flags', 0x2000000) // CHECK-NEXT: ('reserved1', 0) // CHECK-NEXT: ('reserved2', 0) // CHECK-NEXT: ), // CHECK-NEXT: ('_relocations', [ // CHECK-NEXT: # Relocation 0 +// CHECK-NEXT: (('word-0', 0x2c), +// CHECK-NEXT: ('word-1', 0x4000001)), +// CHECK-NEXT: # Relocation 1 // CHECK-NEXT: (('word-0', 0x1c), // CHECK-NEXT: ('word-1', 0x4000001)), // CHECK-NEXT: ]) From eli.friedman at gmail.com Wed Aug 24 17:33:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 22:33:28 -0000 Subject: [llvm-commits] [llvm] r138505 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/atomic-load-store-wide.ll Message-ID: <20110824223328.510072A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 17:33:28 2011 New Revision: 138505 URL: http://llvm.org/viewvc/llvm-project?rev=138505&view=rev Log: Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. Added: llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138505&r1=138504&r2=138505&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 17:33:28 2011 @@ -468,6 +468,7 @@ } if (!Subtarget->is64Bit()) { + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); @@ -10003,15 +10004,20 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); + EVT VT = cast(Node)->getMemoryVT(); // Convert seq_cst store -> xchg - if (cast(Node)->getOrdering() == SequentiallyConsistent) { + // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) + // FIXME: On 32-bit, store -> fist or movq would be more efficient + // (The only way to get a 16-byte store is cmpxchg16b) + // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. + if (cast(Node)->getOrdering() == SequentiallyConsistent || + !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, cast(Node)->getMemoryVT(), Node->getOperand(0), Node->getOperand(1), Node->getOperand(2), - cast(Node)->getSrcValue(), - cast(Node)->getAlignment(), + cast(Node)->getMemOperand(), cast(Node)->getOrdering(), cast(Node)->getSynchScope()); return Swap.getValue(1); @@ -10121,6 +10127,28 @@ } } +static void ReplaceATOMIC_LOAD(SDNode *Node, + SmallVectorImpl &Results, + SelectionDAG &DAG) { + DebugLoc dl = Node->getDebugLoc(); + EVT VT = cast(Node)->getMemoryVT(); + + // Convert wide load -> cmpxchg8b/cmpxchg16b + // FIXME: On 32-bit, load -> fild or movq would be more efficient + // (The only way to get a 16-byte load is cmpxchg16b) + // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. + SDValue Zero = DAG.getConstant(0, cast(Node)->getMemoryVT()); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, + cast(Node)->getMemoryVT(), + Node->getOperand(0), + Node->getOperand(1), Zero, Zero, + cast(Node)->getMemOperand(), + cast(Node)->getOrdering(), + cast(Node)->getSynchScope()); + Results.push_back(Swap.getValue(0)); + Results.push_back(Swap.getValue(1)); +} + void X86TargetLowering:: ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl&Results, SelectionDAG &DAG, unsigned NewOp) const { @@ -10244,6 +10272,8 @@ case ISD::ATOMIC_SWAP: ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); return; + case ISD::ATOMIC_LOAD: + ReplaceATOMIC_LOAD(N, Results, DAG); } } Added: llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll?rev=138505&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll (added) +++ llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll Wed Aug 24 17:33:28 2011 @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +; 64-bit load/store on x86-32 +; FIXME: The generated code can be substantially improved. + +define void @test1(i64* %ptr, i64 %val1) { +; CHECK: test1 +; CHECK: cmpxchg8b +; CHECK-NEXT: jne + store atomic i64 %val1, i64* %ptr seq_cst, align 4 + ret void +} + +define i64 @test2(i64* %ptr) { +; CHECK: test2 +; CHECK: cmpxchg8b + %val = load atomic i64* %ptr seq_cst, align 4 + ret i64 %val +} From jediknil at belkadan.com Wed Aug 24 17:38:56 2011 From: jediknil at belkadan.com (Jordy Rose) Date: Wed, 24 Aug 2011 15:38:56 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: A couple comments, though this certainly isn't an area of the code I'm that familiar with. - Instead of appendTo(string&) and assignTo(string&), why not just add operator+=(string&, const Twine&) and operator=(string&, const Twine&) ? Seems more C++ to me. - Re: toNullTerminatedStringRef: A StringRef created from a null-terminated C string drops the null terminator, so you can't just "test the last character" to see if it's a null. In fact, having the last character of a StringRef be null is probably a bug. (Of course, you can't test /past/ the last character either, because one byte past valid memory is guaranteed to be a valid address but not guaranteed to be dereferenceable.) - You've got several copies of SafeBool.h in the file. I'm guessing this is the result of reverting and then reapplying patches. (I do this all the time too.) - TwineString definitely seems evil, but I haven't really thought about it hard enough to give a good reason why. I don't get why you're using a SmallVectorImpl instead of a SmallVector or SmallString, though. Jordy On Aug 23, 2011, at 22:16, David Blaikie wrote: > > Here's a smaller version/start of my twine changes - perhaps it'll be easier to bite off to review. > > The description from my initial attempt: > > Here's some more Twine-ification of APIs. I realize this seems like a > somewhat random assortment - I haven't, for example, fully changed > some types to Twine (so there might be some functions in a type that > take Twine, others that take StringRef still), but it does seem to be > stable & I didn't want to just keep piling on more code. > > API changes: > * Twine > * appendTo(std::string&) > Works like "toVector" but on std::strings. (I'd like to rename > toVector to appendTo to make it clear it's appending, not overwriting > - I added test cases to expose this existing deliberate design because > when I 'fixed' it by clearing the vector in toVector I broke a bunch > of stuff that was relying on it being appending) > * assignTo(std::string&) > clear() + appendTo > * StringRef > * StringRef(const char (&)[N]) > an array constructor so it doesn't have to use strlen for string > literals. For some reason this doesn't work in GCC (try making the > StringRef(const char*) ctor explicit & GCC starts complaining about > how it can't convert the const char* in 'return "foo";' into a > StringRef). This is a little tricky - it doesn't include the trailing > null character if one is present. This is to maintain compatibility > with the existing implicit conversion from string arrays via the > (const char*) ctor. > * assignTo(std::string&) > the same idea as Twine::appendTo(std::string&). This is more > efficient than using str = strRef; because it doesn't produce an extra > temporary buffer to return through. ctor initialization (std::string > str = strRef;) is still efficient due to RVO. > * booleanTest()/SafeBool > I've made StringRef boolean testable so it can be used as a drop > in replacement when null tests are required > * TwineString - a type that makes retrieving/manipulating a Twine > value a little simpler. Yes, it's a little dodgy that it derives from > StringRef but it's 'good enough' to make Twines the default string > arguments - any time you see a StringRef or std::string argument there > should be a specific explanation. > > One current problem I have is that SmallString is convertible to > StringRef and StringRef to Twine, but that seems to be insufficient to > implicitly convert from SmallString to Twine - so I've added a few > explicit Twine(smallstr) calls around. If there's a better way to > approach this (ultimately we could add a SmallString option to Twine, > but it'd be sort of nice not to have to do that either) I'm all ears. > > Aside: Twine:: > toNullTerminatedStringRef scares me. A lot. It relies on > UB to leave the null character beyond the end of the allocated buffer. > Could we fix this to return a StringRef that doesn't include the null > character (though I'm not sure this bit should matter, really - code > asking for the null terminated StringRef is probably doing it to pass > to a C API that's not going to care about the StringRef's concept of > length), but leave the character itself in the buffer? (& I was > thinking we could check if the Twine was a non-empty StringRef > already, test the last character for null, then return a StringRef > over that rather than using a new buffer - though this wouldn't work > for my current StringRef(const char(&)[N]) ctor, since the length > won't include the null character). > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Aug 24 17:40:23 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Aug 2011 22:40:23 -0000 Subject: [llvm-commits] [llvm] r138507 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb2.td Disassembler/ARMDisassembler.cpp Message-ID: <20110824224023.0F16D2A6C12C@llvm.org> Author: resistor Date: Wed Aug 24 17:40:22 2011 New Revision: 138507 URL: http://llvm.org/viewvc/llvm-project?rev=138507&view=rev Log: Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138507&r1=138506&r2=138507&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 24 17:40:22 2011 @@ -20,6 +20,7 @@ // IT block condition mask def it_mask : Operand { let PrintMethod = "printThumbITMask"; + let DecoderMethod = "DecodeITMask"; } // Shifted operands. No register controlled shifts for Thumb2. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138507&r1=138506&r2=138507&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 24 17:40:22 2011 @@ -230,6 +230,8 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" #include "ARMGenInstrInfo.inc" @@ -3304,3 +3306,14 @@ return S; } +static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask, + uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + if (Mask == 0) { + Mask = 0x8; + CHECK(S, Unpredictable); + } + Inst.addOperand(MCOperand::CreateImm(Mask)); + return S; +} + From bruno.cardoso at gmail.com Wed Aug 24 18:17:55 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:17:55 -0000 Subject: [llvm-commits] [llvm] r138514 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20110824231755.560162A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 18:17:55 2011 New Revision: 138514 URL: http://llvm.org/viewvc/llvm-project?rev=138514&view=rev Log: Move all SHUFP* patterns close to the SHUFP* definitions. Also be explicit about which subtarget they refer to, and add AVX versions of the ones we currently don't. Make the mask check more strict, to be clear it won't be used to match to 256-bit versions! Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138514&r1=138513&r2=138514&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 18:17:55 2011 @@ -3179,9 +3179,14 @@ } /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to SHUFP*. +/// specifies a shuffle of elements that is suitable for input to 128-bit +/// SHUFPS and SHUFPD. static bool isSHUFPMask(const SmallVectorImpl &Mask, EVT VT) { int NumElems = VT.getVectorNumElements(); + + if (VT.getSizeInBits() != 128) + return false; + if (NumElems != 2 && NumElems != 4) return false; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138514&r1=138513&r2=138514&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:17:55 2011 @@ -1475,6 +1475,107 @@ memopv2f64, SSEPackedDouble>, TB, OpSize; } +let Predicates = [HasSSE1] in { + def : Pat<(v4f32 (X86Shufps VR128:$src1, + (memopv4f32 addr:$src2), (i8 imm:$imm))), + (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; + def : Pat<(v4i32 (X86Shufps VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))), + (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; + // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but + // fall back to this for SSE1) + def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))), + (SHUFPSrri VR128:$src2, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special unary SHUFPSrri case. + def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))), + (SHUFPSrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; +} + +let Predicates = [HasSSE2] in { + // Special binary v4i32 shuffle cases with SHUFPS. + def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))), + (SHUFPSrri VR128:$src1, VR128:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + def : Pat<(v4i32 (shufp:$src3 VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)))), + (SHUFPSrmi VR128:$src1, addr:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special unary SHUFPDrri cases. + def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))), + (SHUFPDrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))), + (SHUFPDrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special binary v2i64 shuffle cases using SHUFPDrri. + def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)), + (SHUFPDrri VR128:$src1, VR128:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Generic SHUFPD patterns + def : Pat<(v2f64 (X86Shufps VR128:$src1, + (memopv2f64 addr:$src2), (i8 imm:$imm))), + (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; + def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; +} + +let Predicates = [HasAVX] in { + def : Pat<(v4f32 (X86Shufps VR128:$src1, + (memopv4f32 addr:$src2), (i8 imm:$imm))), + (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; + def : Pat<(v4i32 (X86Shufps VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))), + (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; + // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but + // fall back to this for SSE1) + def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))), + (VSHUFPSrri VR128:$src2, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special unary SHUFPSrri case. + def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))), + (VSHUFPSrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special binary v4i32 shuffle cases with SHUFPS. + def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))), + (VSHUFPSrri VR128:$src1, VR128:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + def : Pat<(v4i32 (shufp:$src3 VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)))), + (VSHUFPSrmi VR128:$src1, addr:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special unary SHUFPDrri cases. + def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))), + (VSHUFPDrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))), + (VSHUFPDrri VR128:$src1, VR128:$src1, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Special binary v2i64 shuffle cases using SHUFPDrri. + def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)), + (VSHUFPDrri VR128:$src1, VR128:$src2, + (SHUFFLE_get_shuf_imm VR128:$src3))>; + // Generic VSHUFPD patterns + def : Pat<(v2f64 (X86Shufps VR128:$src1, + (memopv2f64 addr:$src2), (i8 imm:$imm))), + (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>; + def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; + def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), + (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; +} + //===----------------------------------------------------------------------===// // SSE 1 & 2 - Unpack Instructions //===----------------------------------------------------------------------===// @@ -4049,44 +4150,15 @@ (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; } -// Special unary SHUFPSrri case. -def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))), - (SHUFPSrri VR128:$src1, VR128:$src1, - (SHUFFLE_get_shuf_imm VR128:$src3))>; let AddedComplexity = 5 in def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))), (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>, Requires<[HasSSE2]>; -// Special unary SHUFPDrri case. -def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))), - (SHUFPDrri VR128:$src1, VR128:$src1, - (SHUFFLE_get_shuf_imm VR128:$src3))>, - Requires<[HasSSE2]>; -// Special unary SHUFPDrri case. -def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))), - (SHUFPDrri VR128:$src1, VR128:$src1, - (SHUFFLE_get_shuf_imm VR128:$src3))>, - Requires<[HasSSE2]>; // Unary v4f32 shuffle with PSHUF* in order to fold a load. def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)), (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>, Requires<[HasSSE2]>; -// Special binary v4i32 shuffle cases with SHUFPS. -def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))), - (SHUFPSrri VR128:$src1, VR128:$src2, - (SHUFFLE_get_shuf_imm VR128:$src3))>, - Requires<[HasSSE2]>; -def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))), - (SHUFPSrmi VR128:$src1, addr:$src2, - (SHUFFLE_get_shuf_imm VR128:$src3))>, - Requires<[HasSSE2]>; -// Special binary v2i64 shuffle cases using SHUFPDrri. -def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)), - (SHUFPDrri VR128:$src1, VR128:$src2, - (SHUFFLE_get_shuf_imm VR128:$src3))>, - Requires<[HasSSE2]>; - let AddedComplexity = 20 in { // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))), @@ -4128,12 +4200,6 @@ Requires<[HasSSE2]>; } -// vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but -// fall back to this for SSE1) -def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))), - (SHUFPSrri VR128:$src2, VR128:$src1, - (SHUFFLE_get_shuf_imm VR128:$src3))>; - // Set lowest element and zero upper elements. def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; @@ -5924,49 +5990,6 @@ def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), (PSHUFDri VR128:$src1, imm:$imm)>; -// Shuffle with SHUFPD instruction. -def : Pat<(v2f64 (X86Shufps VR128:$src1, - (memopv2f64 addr:$src2), (i8 imm:$imm))), - (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Shufps VR128:$src1, - (memopv2f64 addr:$src2), (i8 imm:$imm))), - (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>; - -def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; - -def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; - -// Shuffle with SHUFPS instruction. -def : Pat<(v4f32 (X86Shufps VR128:$src1, - (memopv4f32 addr:$src2), (i8 imm:$imm))), - (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Shufps VR128:$src1, - (memopv4f32 addr:$src2), (i8 imm:$imm))), - (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; - -def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; - -def : Pat<(v4i32 (X86Shufps VR128:$src1, - (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))), - (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4i32 (X86Shufps VR128:$src1, - (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))), - (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>; - -def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; - // Shuffle with MOVHLPS instruction def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), (MOVHLPSrr VR128:$src1, VR128:$src2)>; From bruno.cardoso at gmail.com Wed Aug 24 18:17:57 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:17:57 -0000 Subject: [llvm-commits] [llvm] r138515 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231757.CFEDE2A6C12D@llvm.org> Author: bruno Date: Wed Aug 24 18:17:57 2011 New Revision: 138515 URL: http://llvm.org/viewvc/llvm-project?rev=138515&view=rev Log: Move all PSHUF* patterns close to the PSHUF* definitions. Also be explicit about which subtarget they refer to, and add AVX versions of the ones we currently don't. Remove old and now wrong comments! Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138515&r1=138514&r2=138515&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:17:57 2011 @@ -2986,6 +2986,34 @@ // SSE2 with ImmT == Imm8 and XD prefix. defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD, VEX; + + let AddedComplexity = 5 in + def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))), + (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>; + // Unary v4f32 shuffle with VPSHUF* in order to fold a load. + def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)), + (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>; + + def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)), + (i8 imm:$imm))), + (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>; + def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)), + (i8 imm:$imm))), + (VPSHUFDmi addr:$src1, imm:$imm)>; + def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))), + (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; + def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), + (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; + def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), + (VPSHUFHWri VR128:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), + (i8 imm:$imm))), + (VPSHUFHWmi addr:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))), + (VPSHUFLWri VR128:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), + (i8 imm:$imm))), + (VPSHUFLWmi addr:$src, imm:$imm)>; } let Predicates = [HasSSE2] in { @@ -2997,6 +3025,34 @@ // SSE2 with ImmT == Imm8 and XD prefix. defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD; + + let AddedComplexity = 5 in + def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))), + (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>; + // Unary v4f32 shuffle with PSHUF* in order to fold a load. + def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)), + (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>; + + def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)), + (i8 imm:$imm))), + (PSHUFDmi addr:$src1, imm:$imm)>; + def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)), + (i8 imm:$imm))), + (PSHUFDmi addr:$src1, imm:$imm)>; + def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))), + (PSHUFDri VR128:$src1, imm:$imm)>; + def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), + (PSHUFDri VR128:$src1, imm:$imm)>; + def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), + (PSHUFHWri VR128:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), + (i8 imm:$imm))), + (PSHUFHWmi addr:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))), + (PSHUFLWri VR128:$src, imm:$imm)>; + def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), + (i8 imm:$imm))), + (PSHUFLWmi addr:$src, imm:$imm)>; } //===---------------------------------------------------------------------===// @@ -4150,15 +4206,6 @@ (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; } -let AddedComplexity = 5 in -def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))), - (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[HasSSE2]>; -// Unary v4f32 shuffle with PSHUF* in order to fold a load. -def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)), - (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>, - Requires<[HasSSE2]>; - let AddedComplexity = 20 in { // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))), @@ -5964,32 +6011,6 @@ // The AVX version of some but not all of them are described here, and more // should come in a near future. -// Shuffle with PSHUFD instruction folding loads. The first two patterns match -// SSE2 loads, which are always promoted to v2i64. The last one should match -// the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD -// in SSE2, how does it ever worked? Anyway, the pattern will remain here until -// we investigate further. -def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)), - (i8 imm:$imm))), - (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)), - (i8 imm:$imm))), - (PSHUFDmi addr:$src1, imm:$imm)>; -def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)), - (i8 imm:$imm))), - (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked? - -// Shuffle with PSHUFD instruction. -def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (PSHUFDri VR128:$src1, imm:$imm)>; - -def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; -def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (PSHUFDri VR128:$src1, imm:$imm)>; - // Shuffle with MOVHLPS instruction def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), (MOVHLPSrr VR128:$src1, VR128:$src2)>; @@ -6155,18 +6176,6 @@ def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; -// Shuffle with PSHUFHW -def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), - (PSHUFHWri VR128:$src, imm:$imm)>; -def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))), - (PSHUFHWmi addr:$src, imm:$imm)>; - -// Shuffle with PSHUFLW -def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))), - (PSHUFLWri VR128:$src, imm:$imm)>; -def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))), - (PSHUFLWmi addr:$src, imm:$imm)>; - // Shuffle with MOVLPS def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))), (MOVLPSrm VR128:$src1, addr:$src2)>; From bruno.cardoso at gmail.com Wed Aug 24 18:18:00 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:00 -0000 Subject: [llvm-commits] [llvm] r138516 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231800.24F292A6C12E@llvm.org> Author: bruno Date: Wed Aug 24 18:17:59 2011 New Revision: 138516 URL: http://llvm.org/viewvc/llvm-project?rev=138516&view=rev Log: Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the pattern for 128-bit AVX mode. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138516&r1=138515&r2=138516&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:17:59 2011 @@ -514,6 +514,11 @@ def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))), (VMOVHLPSrr VR128:$src1, VR128:$src1)>; } + + def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), + (VMOVHLPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)), + (VMOVHLPSrr VR128:$src1, VR128:$src2)>; } let Predicates = [HasSSE1] in { @@ -557,6 +562,11 @@ def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))), (MOVHLPSrr VR128:$src1, VR128:$src1)>; } + + def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), + (MOVHLPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)), + (MOVHLPSrr VR128:$src1, VR128:$src2)>; } //===----------------------------------------------------------------------===// @@ -6011,12 +6021,6 @@ // The AVX version of some but not all of them are described here, and more // should come in a near future. -// Shuffle with MOVHLPS instruction -def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), - (MOVHLPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)), - (MOVHLPSrr VR128:$src1, VR128:$src2)>; - // Shuffle with MOVDDUP instruction def : Pat<(X86Movddup (memopv2f64 addr:$src)), (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; From bruno.cardoso at gmail.com Wed Aug 24 18:18:09 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:09 -0000 Subject: [llvm-commits] [llvm] r138520 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231809.9A4512A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 18:18:09 2011 New Revision: 138520 URL: http://llvm.org/viewvc/llvm-project?rev=138520&view=rev Log: Move code around! Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138520&r1=138519&r2=138520&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:18:09 2011 @@ -116,6 +116,71 @@ } //===----------------------------------------------------------------------===// +// Special COPY patterns +//===----------------------------------------------------------------------===// + +def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), + (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; + +//===----------------------------------------------------------------------===// +// AVX & SSE - Zero/One Vectors +//===----------------------------------------------------------------------===// + +// Alias instructions that map zero vector to pxor / xorp* for sse. +// We set canFoldAsLoad because this can be converted to a constant-pool +// load of an all-zeros value if folding it would be beneficial. +// FIXME: Change encoding to pseudo! This is blocked right now by the x86 +// JIT implementation, it does not expand the instructions below like +// X86MCInstLower does. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isCodeGenOnly = 1 in { +def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>; +def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v2f64 immAllZerosV))]>; +let ExeDomain = SSEPackedInt in +def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllZerosV))]>; +} + +// The same as done above but for AVX. The 128-bit versions are the +// same, but re-encoded. The 256-bit does not support PI version, and +// doesn't need it because on sandy bridge the register is set to zero +// at the rename stage without using any execution unit, so SET0PSY +// and SET0PDY can be used for vector int instructions without penalty +// FIXME: Change encoding to pseudo! This is blocked right now by the x86 +// JIT implementatioan, it does not expand the instructions below like +// X86MCInstLower does. +let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, + isCodeGenOnly = 1, Predicates = [HasAVX] in { +def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V; +def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V; +def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V; +def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V; +let ExeDomain = SSEPackedInt in +def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllZerosV))]>; +} + +def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>; +def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>; +def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>; + +// AVX has no support for 256-bit integer instructions, but since the 128-bit +// VPXOR instruction writes zero to its upper part, it's safe build zeros. +def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v8i32 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; + +def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v4i64 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; + +//===----------------------------------------------------------------------===// // SSE 1 & 2 - Move Instructions //===----------------------------------------------------------------------===// @@ -2455,7 +2520,7 @@ } //===----------------------------------------------------------------------===// -// SSE 1 & 2 - Misc Instructions (No AVX form) +// SSE 1 & 2 - Prefetch and memory fence //===----------------------------------------------------------------------===// // Prefetch intrinsic. @@ -2473,63 +2538,6 @@ TB, Requires<[HasSSE1]>; def : Pat<(X86SFence), (SFENCE)>; -// Alias instructions that map zero vector to pxor / xorp* for sse. -// We set canFoldAsLoad because this can be converted to a constant-pool -// load of an all-zeros value if folding it would be beneficial. -// FIXME: Change encoding to pseudo! This is blocked right now by the x86 -// JIT implementation, it does not expand the instructions below like -// X86MCInstLower does. -let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, - isCodeGenOnly = 1 in { -def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4f32 immAllZerosV))]>; -def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v2f64 immAllZerosV))]>; -let ExeDomain = SSEPackedInt in -def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4i32 immAllZerosV))]>; -} - -// The same as done above but for AVX. The 128-bit versions are the -// same, but re-encoded. The 256-bit does not support PI version, and -// doesn't need it because on sandy bridge the register is set to zero -// at the rename stage without using any execution unit, so SET0PSY -// and SET0PDY can be used for vector int instructions without penalty -// FIXME: Change encoding to pseudo! This is blocked right now by the x86 -// JIT implementatioan, it does not expand the instructions below like -// X86MCInstLower does. -let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, - isCodeGenOnly = 1, Predicates = [HasAVX] in { -def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V; -def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V; -def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", - [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V; -def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", - [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V; -let ExeDomain = SSEPackedInt in -def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4i32 immAllZerosV))]>; -} - -def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>; -def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>; -def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>; - -def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), - (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; - -// AVX has no support for 256-bit integer instructions, but since the 128-bit -// VPXOR instruction writes zero to its upper part, it's safe build zeros. -def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; -def : Pat<(bc_v8i32 (v8f32 immAllZerosV)), - (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; - -def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; -def : Pat<(bc_v4i64 (v8f32 immAllZerosV)), - (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; - //===----------------------------------------------------------------------===// // SSE 1 & 2 - Load/Store XCSR register //===----------------------------------------------------------------------===// From bruno.cardoso at gmail.com Wed Aug 24 18:18:04 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:04 -0000 Subject: [llvm-commits] [llvm] r138518 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231804.E37BC2A6C12D@llvm.org> Author: bruno Date: Wed Aug 24 18:18:04 2011 New Revision: 138518 URL: http://llvm.org/viewvc/llvm-project?rev=138518&view=rev Log: Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate the missing ones for AVX. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138518&r1=138517&r2=138518&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:18:04 2011 @@ -3776,6 +3776,42 @@ def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)), (MOVDDUPrm addr:$src)>; } + def : Pat<(X86Movddup (memopv2f64 addr:$src)), + (MOVDDUPrm addr:$src)>; + def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))), + (MOVDDUPrm addr:$src)>; + def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))), + (MOVDDUPrm addr:$src)>; + def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))), + (MOVDDUPrm addr:$src)>; + def : Pat<(X86Movddup (bc_v2f64 + (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (MOVDDUPrm addr:$src)>; +} + +let Predicates = [HasAVX] in { + def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))), + (undef)), + (VMOVDDUPrm addr:$src)>; + let AddedComplexity = 5 in { + def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>; + def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)), + (VMOVDDUPrm addr:$src)>; + def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>; + def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)), + (VMOVDDUPrm addr:$src)>; + } + def : Pat<(X86Movddup (memopv2f64 addr:$src)), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; + def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; + def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; + def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; + def : Pat<(X86Movddup (bc_v2f64 + (v2i64 (scalar_to_vector (loadi64 addr:$src))))), + (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; } //===---------------------------------------------------------------------===// @@ -6019,33 +6055,6 @@ // The AVX version of some but not all of them are described here, and more // should come in a near future. -// Shuffle with MOVDDUP instruction -def : Pat<(X86Movddup (memopv2f64 addr:$src)), - (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; -def : Pat<(X86Movddup (memopv2f64 addr:$src)), - (MOVDDUPrm addr:$src)>; - -def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))), - (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; -def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))), - (MOVDDUPrm addr:$src)>; - -def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))), - (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; -def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))), - (MOVDDUPrm addr:$src)>; - -def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))), - (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; -def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))), - (MOVDDUPrm addr:$src)>; - -def : Pat<(X86Movddup (bc_v2f64 - (v2i64 (scalar_to_vector (loadi64 addr:$src))))), - (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; -def : Pat<(X86Movddup (bc_v2f64 - (v2i64 (scalar_to_vector (loadi64 addr:$src))))), - (MOVDDUPrm addr:$src)>; // Shuffle with UNPCKLPS From bruno.cardoso at gmail.com Wed Aug 24 18:18:12 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:12 -0000 Subject: [llvm-commits] [llvm] r138521 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231812.2A6362A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 18:18:11 2011 New Revision: 138521 URL: http://llvm.org/viewvc/llvm-project?rev=138521&view=rev Log: Create a section for non-instructions patterns in the beginning of the file, and move more code around! Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138521&r1=138520&r2=138521&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:18:11 2011 @@ -116,12 +116,93 @@ } //===----------------------------------------------------------------------===// -// Special COPY patterns +// Non-instruction patterns //===----------------------------------------------------------------------===// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; +// Implicitly promote a 32-bit scalar to a vector. +def : Pat<(v4f32 (scalar_to_vector FR32:$src)), + (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>; +def : Pat<(v8f32 (scalar_to_vector FR32:$src)), + (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>; +// Implicitly promote a 64-bit scalar to a vector. +def : Pat<(v2f64 (scalar_to_vector FR64:$src)), + (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>; +def : Pat<(v4f64 (scalar_to_vector FR64:$src)), + (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>; + +// Bitcasts between 128-bit vector types. Return the original type since +// no instruction is needed for the conversion +let Predicates = [HasXMMInt] in { + def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; + def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; + def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; + def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; + def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; + def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; + def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; + def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; + def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; + def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; + def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; + def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; + def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; + def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; + def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; + def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; + def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; + def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; + def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; + def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; + def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; + def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; + def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; + def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; + def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; + def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; + def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; + def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; + def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; + def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; +} + +// Bitcasts between 256-bit vector types. Return the original type since +// no instruction is needed for the conversion +let Predicates = [HasAVX] in { + def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>; + def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>; + def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>; +} + //===----------------------------------------------------------------------===// // AVX & SSE - Zero/One Vectors //===----------------------------------------------------------------------===// @@ -237,19 +318,6 @@ (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; } -// Implicitly promote a 32-bit scalar to a vector. -def : Pat<(v4f32 (scalar_to_vector FR32:$src)), - (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>; -// Implicitly promote a 64-bit scalar to a vector. -def : Pat<(v2f64 (scalar_to_vector FR64:$src)), - (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>; -// Implicitly promote a 32-bit scalar to a vector. -def : Pat<(v8f32 (scalar_to_vector FR32:$src)), - (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>; -// Implicitly promote a 64-bit scalar to a vector. -def : Pat<(v4f64 (scalar_to_vector FR64:$src)), - (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>; - let AddedComplexity = 20 in { let Predicates = [HasSSE1] in { // MOVSSrm zeros the high parts of the register; represent this @@ -4248,10 +4316,6 @@ def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>, Requires<[In64BitMode]>; -//===---------------------------------------------------------------------===// -// Non-Instruction Patterns -//===---------------------------------------------------------------------===// - // extload f32 -> f64. This matches load+fextend because we have a hack in // the isel (PreprocessForFPConvert) that can introduce loads after dag // combine. @@ -4261,76 +4325,6 @@ def : Pat<(fextend (loadf32 addr:$src)), (CVTSS2SDrm addr:$src)>; -// Bitcasts between 128-bit vector types. Return the original type since -// no instruction is needed for the conversion -let Predicates = [HasXMMInt] in { - def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; - def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; - def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; - def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; - def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; - def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; - def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; - def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; - def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; - def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; - def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; - def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; - def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; - def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; - def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; - def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; - def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; - def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; - def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; - def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; - def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; - def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; - def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; - def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; - def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; - def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; - def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; - def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; - def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; - def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; -} - -// Bitcasts between 256-bit vector types. Return the original type since -// no instruction is needed for the conversion -let Predicates = [HasAVX] in { - def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>; - def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>; - def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>; - def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; - def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>; - def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; - def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>; - def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; - def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>; - def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>; - def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; - def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>; - def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>; - def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>; - def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>; - def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; - def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; - def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; - def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; - def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>; - def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>; - def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>; -} - // Move scalar to XMM zero-extended // movd to XMM register zero-extends let AddedComplexity = 15 in { From bruno.cardoso at gmail.com Wed Aug 24 18:18:07 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:07 -0000 Subject: [llvm-commits] [llvm] r138519 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231807.3684A2A6C12E@llvm.org> Author: bruno Date: Wed Aug 24 18:18:06 2011 New Revision: 138519 URL: http://llvm.org/viewvc/llvm-project?rev=138519&view=rev Log: Organize UNPCK* patterns, also add remaining for AVX. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138519&r1=138518&r2=138519&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:18:06 2011 @@ -1649,6 +1649,103 @@ } // Constraints = "$src1 = $dst" } // AddedComplexity +let Predicates = [HasSSE1] in { + def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))), + (UNPCKLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)), + (UNPCKLPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))), + (UNPCKHPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)), + (UNPCKHPSrr VR128:$src1, VR128:$src2)>; +} + +let Predicates = [HasSSE2] in { + def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))), + (UNPCKLPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)), + (UNPCKLPDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))), + (UNPCKHPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), + (UNPCKHPDrr VR128:$src1, VR128:$src2)>; + + // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the + // problem is during lowering, where it's not possible to recognize the load + // fold cause it has two uses through a bitcast. One use disappears at isel + // time and the fold opportunity reappears. + def : Pat<(v2f64 (X86Movddup VR128:$src)), + (UNPCKLPDrr VR128:$src, VR128:$src)>; + + let AddedComplexity = 10 in + def : Pat<(splat_lo (v2f64 VR128:$src), (undef)), + (UNPCKLPDrr VR128:$src, VR128:$src)>; +} + +let Predicates = [HasAVX] in { + def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))), + (VUNPCKLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)), + (VUNPCKLPSrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))), + (VUNPCKHPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)), + (VUNPCKHPSrr VR128:$src1, VR128:$src2)>; + + def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))), + (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)), + (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)), + (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))), + (VUNPCKLPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))), + (VUNPCKHPSYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)), + (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))), + (VUNPCKLPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)), + (VUNPCKLPDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))), + (VUNPCKHPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), + (VUNPCKHPDrr VR128:$src1, VR128:$src2)>; + + def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))), + (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)), + (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))), + (VUNPCKLPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)), + (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))), + (VUNPCKHPDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), + (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>; + + // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the + // problem is during lowering, where it's not possible to recognize the load + // fold cause it has two uses through a bitcast. One use disappears at isel + // time and the fold opportunity reappears. + def : Pat<(v2f64 (X86Movddup VR128:$src)), + (VUNPCKLPDrr VR128:$src, VR128:$src)>; + let AddedComplexity = 10 in + def : Pat<(splat_lo (v2f64 VR128:$src), (undef)), + (VUNPCKLPDrr VR128:$src, VR128:$src)>; +} + //===----------------------------------------------------------------------===// // SSE 1 & 2 - Extract Floating-Point Sign mask //===----------------------------------------------------------------------===// @@ -4244,8 +4341,6 @@ // Splat v2f64 / v2i64 let AddedComplexity = 10 in { -def : Pat<(splat_lo (v2f64 VR128:$src), (undef)), - (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(splat_lo (v2i64 VR128:$src), (undef)), (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; } @@ -6055,101 +6150,6 @@ // The AVX version of some but not all of them are described here, and more // should come in a near future. - - -// Shuffle with UNPCKLPS -def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))), - (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))), - (UNPCKLPSrm VR128:$src1, addr:$src2)>; - -def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)), - (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)), - (UNPCKLPSrr VR128:$src1, VR128:$src2)>; - -// Shuffle with VUNPCKHPSY -def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))), - (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)), - (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; -def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)), - (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; -def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))), - (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; - -// Shuffle with UNPCKHPS -def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))), - (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))), - (UNPCKHPSrm VR128:$src1, addr:$src2)>; - -def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)), - (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)), - (UNPCKHPSrr VR128:$src1, VR128:$src2)>; - -// Shuffle with VUNPCKHPSY -def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))), - (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)), - (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; - -def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))), - (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)), - (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; - -// Shuffle with UNPCKLPD -def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))), - (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))), - (UNPCKLPDrm VR128:$src1, addr:$src2)>; - -def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)), - (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)), - (UNPCKLPDrr VR128:$src1, VR128:$src2)>; - -// Shuffle with VUNPCKLPDY -def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))), - (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)), - (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; - -def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))), - (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)), - (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; - -// Shuffle with UNPCKHPD -def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))), - (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))), - (UNPCKHPDrm VR128:$src1, addr:$src2)>; - -def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), - (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)), - (UNPCKHPDrr VR128:$src1, VR128:$src2)>; - -// Shuffle with VUNPCKHPDY -def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))), - (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), - (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))), - (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)), - (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>; - -// FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem -// is during lowering, where it's not possible to recognize the load fold cause -// it has two uses through a bitcast. One use disappears at isel time and the -// fold opportunity reappears. -def : Pat<(v2f64 (X86Movddup VR128:$src)), - (UNPCKLPDrr VR128:$src, VR128:$src)>; - // Shuffle with MOVLHPD def : Pat<(v2f64 (X86Movlhpd VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), From bruno.cardoso at gmail.com Wed Aug 24 18:18:02 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 24 Aug 2011 23:18:02 -0000 Subject: [llvm-commits] [llvm] r138517 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110824231802.8D4922A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 18:18:02 2011 New Revision: 138517 URL: http://llvm.org/viewvc/llvm-project?rev=138517&view=rev Log: Organize and tidy up MOVDDUP section. Also update comments! Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138517&r1=138516&r2=138517&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 18:18:02 2011 @@ -3675,12 +3675,8 @@ (VCVTDQ2PDYrm addr:$src)>; //===---------------------------------------------------------------------===// -// SSE3 - Move Instructions +// SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP //===---------------------------------------------------------------------===// - -//===---------------------------------------------------------------------===// -// Replicate Single FP - MOVSHDUP and MOVSLDUP -// multiclass sse3_replicate_sfp op, SDNode OpNode, string OpcodeStr, ValueType vt, RegisterClass RC, PatFrag mem_frag, X86MemOperand x86memop> { @@ -3738,8 +3734,9 @@ } //===---------------------------------------------------------------------===// -// Replicate Double FP - MOVDDUP -// +// SSE3 - Replicate Double FP - MOVDDUP +//===---------------------------------------------------------------------===// + multiclass sse3_replicate_dfp { def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), @@ -3751,23 +3748,40 @@ (undef))))]>; } +// FIXME: Merge with above classe when there're patterns for the ymm version multiclass sse3_replicate_dfp_y { -def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), - !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - []>; -def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), - !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - []>; -} - let Predicates = [HasAVX] in { - // FIXME: Merge above classes when we have patterns for the ymm version - defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX; - defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX; + def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + []>; + def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), + []>; + } } + defm MOVDDUP : sse3_replicate_dfp<"movddup">; +defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX; +defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX; + +let Predicates = [HasSSE3] in { + def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))), + (undef)), + (MOVDDUPrm addr:$src)>; + let AddedComplexity = 5 in { + def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>; + def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)), + (MOVDDUPrm addr:$src)>; + def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>; + def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)), + (MOVDDUPrm addr:$src)>; + } +} + +//===---------------------------------------------------------------------===// +// SSE3 - Move Unaligned Integer +//===---------------------------------------------------------------------===// -// Move Unaligned Integer let Predicates = [HasAVX] in { def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vlddqu\t{$src, $dst|$dst, $src}", @@ -3780,22 +3794,6 @@ "lddqu\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; -def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))), - (undef)), - (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; - -// Several Move patterns -let AddedComplexity = 5 in { -def : Pat<(movddup (memopv2f64 addr:$src), (undef)), - (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; -def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)), - (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; -def : Pat<(movddup (memopv2i64 addr:$src), (undef)), - (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; -def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)), - (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; -} - //===---------------------------------------------------------------------===// // SSE3 - Arithmetic //===---------------------------------------------------------------------===// From evan.cheng at apple.com Wed Aug 24 19:54:42 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Aug 2011 00:54:42 -0000 Subject: [llvm-commits] [llvm] r138534 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <20110825005442.EE3B22A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 19:54:42 2011 New Revision: 138534 URL: http://llvm.org/viewvc/llvm-project?rev=138534&view=rev Log: Remove a out-of-place comment. Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138534&r1=138533&r2=138534&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 19:54:42 2011 @@ -81,7 +81,6 @@ : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { } -// Pass Pipeline Configuration bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { if (OptLevel != CodeGenOpt::None) From evan.cheng at apple.com Wed Aug 24 20:00:36 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Aug 2011 01:00:36 -0000 Subject: [llvm-commits] [llvm] r138536 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <20110825010036.BDFEA2A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 20:00:36 2011 New Revision: 138536 URL: http://llvm.org/viewvc/llvm-project?rev=138536&view=rev Log: Add a command line option to disable global merge pass. Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138536&r1=138535&r2=138536&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 20:00:36 2011 @@ -21,6 +21,11 @@ #include "llvm/Target/TargetOptions.h" using namespace llvm; +static cl::opt +EnableGlobalMerge("global-merge", + cl::desc("Enable global merge pass"), + cl::init(true)); + extern "C" void LLVMInitializeARMTarget() { // Register the target. RegisterTargetMachine X(TheARMTarget); @@ -83,7 +88,7 @@ bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - if (OptLevel != CodeGenOpt::None) + if (OptLevel != CodeGenOpt::None && EnableGlobalMerge) PM.add(createARMGlobalMergePass(getTargetLowering())); return false; From isanbard at gmail.com Wed Aug 24 20:08:34 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 01:08:34 -0000 Subject: [llvm-commits] [llvm] r138537 - in /llvm/trunk/lib/Transforms: InstCombine/InstCombineCalls.cpp Instrumentation/PathProfiling.cpp Instrumentation/ProfilingUtils.cpp Scalar/LoopStrengthReduce.cpp Scalar/ObjCARC.cpp Utils/LowerInvoke.cpp Message-ID: <20110825010834.E94052A6C12C@llvm.org> Author: void Date: Wed Aug 24 20:08:34 2011 New Revision: 138537 URL: http://llvm.org/viewvc/llvm-project?rev=138537&view=rev Log: When inserting new instructions, use getFirstInsertionPt instead of getFirstNonPHI so that it will skip over the landingpad instructions as well. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed Aug 24 20:08:34 2011 @@ -1145,7 +1145,7 @@ // If this is an invoke instruction, we should insert it after the first // non-phi, instruction in the normal successor block. if (InvokeInst *II = dyn_cast(Caller)) { - BasicBlock::iterator I = II->getNormalDest()->getFirstNonPHI(); + BasicBlock::iterator I = II->getNormalDest()->getFirstInsertionPt(); InsertNewInstBefore(NC, *I); } else { // Otherwise, it's a call, just insert cast right after the call. Modified: llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp Wed Aug 24 20:08:34 2011 @@ -909,7 +909,7 @@ pathNumber) { if(pathNumber == NULL || isa(pathNumber) || (((Instruction*)(pathNumber))->getParent()) != block) { - return(block->getFirstNonPHI()); + return(block->getFirstInsertionPt()); } else { Instruction* pathNumberInst = (Instruction*) (pathNumber); BasicBlock::iterator insertPoint; @@ -930,7 +930,7 @@ // A PHINode is created in the node, and its values initialized to -1U. void PathProfiler::preparePHI(BLInstrumentationNode* node) { BasicBlock* block = node->getBlock(); - BasicBlock::iterator insertPoint = block->getFirstNonPHI(); + BasicBlock::iterator insertPoint = block->getFirstInsertionPt(); pred_iterator PB = pred_begin(node->getBlock()), PE = pred_end(node->getBlock()); PHINode* phi = PHINode::Create(Type::getInt32Ty(*Context), @@ -999,7 +999,7 @@ BasicBlock::iterator insertPoint; if( atBeginning ) - insertPoint = block->getFirstNonPHI(); + insertPoint = block->getFirstInsertionPt(); else insertPoint = block->getTerminator(); @@ -1139,7 +1139,7 @@ } BasicBlock::iterator insertPoint = atBeginning ? - instrumentNode->getBlock()->getFirstNonPHI() : + instrumentNode->getBlock()->getFirstInsertionPt() : instrumentNode->getBlock()->getTerminator(); // add information from the bottom edge, if it exists @@ -1171,7 +1171,7 @@ // Insert instrumentation if this is a normal edge else { BasicBlock::iterator insertPoint = atBeginning ? - instrumentNode->getBlock()->getFirstNonPHI() : + instrumentNode->getBlock()->getFirstInsertionPt() : instrumentNode->getBlock()->getTerminator(); if( edge->isInitialization() ) { // initialize path number @@ -1232,7 +1232,7 @@ end = callEdges.end(); edge != end; edge++ ) { BLInstrumentationNode* node = (BLInstrumentationNode*)(*edge)->getSource(); - BasicBlock::iterator insertPoint = node->getBlock()->getFirstNonPHI(); + BasicBlock::iterator insertPoint = node->getBlock()->getFirstInsertionPt(); // Find the first function call while( ((Instruction&)(*insertPoint)).getOpcode() != Instruction::Call ) Modified: llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp Wed Aug 24 20:08:34 2011 @@ -107,7 +107,7 @@ void llvm::IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNum, GlobalValue *CounterArray, bool beginning) { // Insert the increment after any alloca or PHI instructions... - BasicBlock::iterator InsertPos = beginning ? BB->getFirstNonPHI() : + BasicBlock::iterator InsertPos = beginning ? BB->getFirstInsertionPt() : BB->getTerminator(); while (isa(InsertPos)) ++InsertPos; Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Aug 24 20:08:34 2011 @@ -3621,10 +3621,11 @@ // users. if (e != 1 && BB->getTerminator()->getNumSuccessors() > 1 && !isa(BB->getTerminator())) { - Loop *PNLoop = LI.getLoopFor(PN->getParent()); - if (!PNLoop || PN->getParent() != PNLoop->getHeader()) { + BasicBlock *Parent = PN->getParent(); + Loop *PNLoop = LI.getLoopFor(Parent); + if (!PNLoop || Parent != PNLoop->getHeader()) { // Split the critical edge. - BasicBlock *NewBB = SplitCriticalEdge(BB, PN->getParent(), P); + BasicBlock *NewBB = SplitCriticalEdge(BB, Parent, P); // If PN is outside of the loop and BB is in the loop, we want to // move the block to be immediately before the PHI block, not Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Wed Aug 24 20:08:34 2011 @@ -2687,8 +2687,8 @@ // The invoke's return value isn't available in the unwind block, // but our releases will never depend on it, because they must be // paired with retains from before the invoke. - InsertPts[0] = II->getNormalDest()->getFirstNonPHI(); - InsertPts[1] = II->getUnwindDest()->getFirstNonPHI(); + InsertPts[0] = II->getNormalDest()->getFirstInsertionPt(); + InsertPts[1] = II->getUnwindDest()->getFirstInsertionPt(); } else { // Insert code immediately after the last use. InsertPts[0] = llvm::next(BasicBlock::iterator(LastUse)); Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=138537&r1=138536&r2=138537&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Wed Aug 24 20:08:34 2011 @@ -240,14 +240,14 @@ CallInst* StackSaveRet = CallInst::Create(StackSaveFn, "ssret", II); new StoreInst(StackSaveRet, StackPtr, true, II); // volatile - BasicBlock::iterator NI = II->getNormalDest()->getFirstNonPHI(); + BasicBlock::iterator NI = II->getNormalDest()->getFirstInsertionPt(); // nonvolatile. new StoreInst(Constant::getNullValue(Type::getInt32Ty(II->getContext())), InvokeNum, false, NI); - Instruction* StackPtrLoad = new LoadInst(StackPtr, "stackptr.restore", true, - II->getUnwindDest()->getFirstNonPHI() - ); + Instruction* StackPtrLoad = + new LoadInst(StackPtr, "stackptr.restore", true, + II->getUnwindDest()->getFirstInsertionPt()); CallInst::Create(StackRestoreFn, StackPtrLoad, "")->insertAfter(StackPtrLoad); // Add a switch case to our unwind block. From isanbard at gmail.com Wed Aug 24 20:19:13 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 01:19:13 -0000 Subject: [llvm-commits] [llvm] r138539 - /llvm/trunk/test/Feature/exception.ll Message-ID: <20110825011913.5200C2A6C12C@llvm.org> Author: void Date: Wed Aug 24 20:19:13 2011 New Revision: 138539 URL: http://llvm.org/viewvc/llvm-project?rev=138539&view=rev Log: Add feature test for the new exception handling stuff. Added: llvm/trunk/test/Feature/exception.ll Added: llvm/trunk/test/Feature/exception.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/exception.ll?rev=138539&view=auto ============================================================================== --- llvm/trunk/test/Feature/exception.ll (added) +++ llvm/trunk/test/Feature/exception.ll Wed Aug 24 20:19:13 2011 @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll +; RUN: diff %t1.ll %t2.ll + + at _ZTIc = external constant i8* + at _ZTId = external constant i8* + at _ZTIPKc = external constant i8* + +define void @_Z3barv() uwtable optsize ssp { +entry: + invoke void @_Z3quxv() optsize + to label %try.cont unwind label %lpad + +try.cont: ; preds = %entry, %invoke.cont4 + ret void + +lpad: ; preds = %entry + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + catch i8** @_ZTIc + filter [2 x i8**] [i8** @_ZTIPKc, i8** @_ZTId] + resume { i8*, i32 } %exn +} + +declare void @_Z3quxv() optsize + +declare i32 @__gxx_personality_v0(...) From eli.friedman at gmail.com Wed Aug 24 20:20:54 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 24 Aug 2011 18:20:54 -0700 Subject: [llvm-commits] [llvm] r138536 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp In-Reply-To: <20110825010036.BDFEA2A6C12C@llvm.org> References: <20110825010036.BDFEA2A6C12C@llvm.org> Message-ID: On Wed, Aug 24, 2011 at 6:00 PM, Evan Cheng wrote: > Author: evancheng > Date: Wed Aug 24 20:00:36 2011 > New Revision: 138536 > > URL: http://llvm.org/viewvc/llvm-project?rev=138536&view=rev > Log: > Add a command line option to disable global merge pass. > > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138536&r1=138535&r2=138536&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 20:00:36 2011 > @@ -21,6 +21,11 @@ > ?#include "llvm/Target/TargetOptions.h" > ?using namespace llvm; > > +static cl::opt > +EnableGlobalMerge("global-merge", > + ? ? ? ? ? ? ? ? ?cl::desc("Enable global merge pass"), > + ? ? ? ? ? ? ? ? ?cl::init(true)); Did you forget to mark this hidden? -Eli From evan.cheng at apple.com Wed Aug 24 20:22:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Aug 2011 01:22:49 -0000 Subject: [llvm-commits] [llvm] r138540 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <20110825012250.0F5642A6C12C@llvm.org> Author: evancheng Date: Wed Aug 24 20:22:49 2011 New Revision: 138540 URL: http://llvm.org/viewvc/llvm-project?rev=138540&view=rev Log: Hide -global-merge option. Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138540&r1=138539&r2=138540&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 20:22:49 2011 @@ -22,7 +22,7 @@ using namespace llvm; static cl::opt -EnableGlobalMerge("global-merge", +EnableGlobalMerge("global-merge", cl::Hidden, cl::desc("Enable global merge pass"), cl::init(true)); From evan.cheng at apple.com Wed Aug 24 20:24:03 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Aug 2011 18:24:03 -0700 Subject: [llvm-commits] [llvm] r138536 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp In-Reply-To: References: <20110825010036.BDFEA2A6C12C@llvm.org> Message-ID: Fixed. Thanks. Evan On Aug 24, 2011, at 6:20 PM, Eli Friedman wrote: > On Wed, Aug 24, 2011 at 6:00 PM, Evan Cheng wrote: >> Author: evancheng >> Date: Wed Aug 24 20:00:36 2011 >> New Revision: 138536 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=138536&view=rev >> Log: >> Add a command line option to disable global merge pass. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=138536&r1=138535&r2=138536&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Aug 24 20:00:36 2011 >> @@ -21,6 +21,11 @@ >> #include "llvm/Target/TargetOptions.h" >> using namespace llvm; >> >> +static cl::opt >> +EnableGlobalMerge("global-merge", >> + cl::desc("Enable global merge pass"), >> + cl::init(true)); > > Did you forget to mark this hidden? > > -Eli From isanbard at gmail.com Wed Aug 24 20:30:18 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 01:30:18 -0000 Subject: [llvm-commits] [llvm] r138541 - in /llvm/trunk/test/Feature: callingconventions.ll calltest.ll Message-ID: <20110825013018.A75212A6C12C@llvm.org> Author: void Date: Wed Aug 24 20:30:18 2011 New Revision: 138541 URL: http://llvm.org/viewvc/llvm-project?rev=138541&view=rev Log: Update tests to the newest EH syntax. Modified: llvm/trunk/test/Feature/callingconventions.ll llvm/trunk/test/Feature/calltest.ll Modified: llvm/trunk/test/Feature/callingconventions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/callingconventions.ll?rev=138541&r1=138540&r2=138541&view=diff ============================================================================== --- llvm/trunk/test/Feature/callingconventions.ll (original) +++ llvm/trunk/test/Feature/callingconventions.ll Wed Aug 24 20:30:18 2011 @@ -26,25 +26,30 @@ } define cc42 void @bar3() { - invoke fastcc void @foo( ) - to label %Ok unwind label %U + invoke fastcc void @foo( ) + to label %Ok unwind label %U -Ok: ; preds = %0 - ret void +Ok: + ret void -U: ; preds = %0 - unwind +U: + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + resume { i8*, i32 } %exn } define void @bar4() { - call cc42 void @bar( ) - invoke cc42 void @bar3( ) - to label %Ok unwind label %U - -Ok: ; preds = %0 - ret void - -U: ; preds = %0 - unwind + call cc42 void @bar( ) + invoke cc42 void @bar3( ) + to label %Ok unwind label %U + +Ok: + ret void + +U: + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + resume { i8*, i32 } %exn } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Feature/calltest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/calltest.ll?rev=138541&r1=138540&r2=138541&view=diff ============================================================================== --- llvm/trunk/test/Feature/calltest.ll (original) +++ llvm/trunk/test/Feature/calltest.ll Wed Aug 24 20:30:18 2011 @@ -5,26 +5,30 @@ %FunTy = type i32 (i32) define void @invoke(%FunTy* %x) { - %foo = call i32 %x( i32 123 ) ; [#uses=0] - %foo2 = tail call i32 %x( i32 123 ) ; [#uses=0] - ret void + %foo = call i32 %x( i32 123 ) ; [#uses=0] + %foo2 = tail call i32 %x( i32 123 ) ; [#uses=0] + ret void } define i32 @main(i32 %argc) { - %retval = call i32 @test( i32 %argc ) ; [#uses=2] - %two = add i32 %retval, %retval ; [#uses=1] - %retval2 = invoke i32 @test( i32 %argc ) - to label %Next unwind label %Error ; [#uses=1] - -Next: ; preds = %0 - %two2 = add i32 %two, %retval2 ; [#uses=1] - call void @invoke( %FunTy* @test ) - ret i32 %two2 + %retval = call i32 @test( i32 %argc ) ; [#uses=2] + %two = add i32 %retval, %retval ; [#uses=1] + %retval2 = invoke i32 @test( i32 %argc ) + to label %Next unwind label %Error ; [#uses=1] -Error: ; preds = %0 - ret i32 -1 +Next: + %two2 = add i32 %two, %retval2 ; [#uses=1] + call void @invoke( %FunTy* @test ) + ret i32 %two2 + +Error: + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + ret i32 -1 } define i32 @test(i32 %i0) { ret i32 %i0 } + +declare i32 @__gxx_personality_v0(...) From eli.friedman at gmail.com Wed Aug 24 20:33:48 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 25 Aug 2011 01:33:48 -0000 Subject: [llvm-commits] [llvm] r138542 - in /llvm/trunk/test: FrontendC++/ FrontendObjC++/ FrontendObjC/ Message-ID: <20110825013348.A9D162A6C12C@llvm.org> Author: efriedma Date: Wed Aug 24 20:33:48 2011 New Revision: 138542 URL: http://llvm.org/viewvc/llvm-project?rev=138542&view=rev Log: Remove empty directories. Removed: llvm/trunk/test/FrontendC++/ llvm/trunk/test/FrontendObjC/ llvm/trunk/test/FrontendObjC++/ From echristo at apple.com Wed Aug 24 20:39:37 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 24 Aug 2011 18:39:37 -0700 Subject: [llvm-commits] [llvm] r138542 - in /llvm/trunk/test: FrontendC++/ FrontendObjC++/ FrontendObjC/ In-Reply-To: <20110825013348.A9D162A6C12C@llvm.org> References: <20110825013348.A9D162A6C12C@llvm.org> Message-ID: <7BFB99F1-EF94-4AE9-8A7C-0B116CB67A7D@apple.com> On Aug 24, 2011, at 6:33 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Aug 24 20:33:48 2011 > New Revision: 138542 > > URL: http://llvm.org/viewvc/llvm-project?rev=138542&view=rev > Log: > Remove empty directories. > > > Removed: > llvm/trunk/test/FrontendC++/ > llvm/trunk/test/FrontendObjC/ > llvm/trunk/test/FrontendObjC++/ Weird. Thought I had. *adds one more svn and git difference*. Thanks! -eric From bruno.cardoso at gmail.com Wed Aug 24 21:58:22 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 02:58:22 -0000 Subject: [llvm-commits] [llvm] r138545 - /llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Message-ID: <20110825025822.111952A6C12C@llvm.org> Author: bruno Date: Wed Aug 24 21:58:21 2011 New Revision: 138545 URL: http://llvm.org/viewvc/llvm-project?rev=138545&view=rev Log: Add memory version of SHUFPD to mask decoding! Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=138545&r1=138544&r2=138545&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Wed Aug 24 21:58:21 2011 @@ -136,9 +136,11 @@ break; case X86::SHUFPDrri: + Src2Name = getRegName(MI->getOperand(2).getReg()); + // FALL THROUGH. + case X86::SHUFPDrmi: DecodeSHUFPSMask(2, MI->getOperand(3).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); - Src2Name = getRegName(MI->getOperand(2).getReg()); break; case X86::SHUFPSrri: From bruno.cardoso at gmail.com Wed Aug 24 21:58:27 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 02:58:27 -0000 Subject: [llvm-commits] [llvm] r138546 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-basic.ll test/CodeGen/X86/avx-vshufp.ll Message-ID: <20110825025827.53DB92A6C12D@llvm.org> Author: bruno Date: Wed Aug 24 21:58:26 2011 New Revision: 138546 URL: http://llvm.org/viewvc/llvm-project?rev=138546&view=rev Log: Add support for 256-bit versions of VSHUFPD and VSHUFPS. Added: llvm/trunk/test/CodeGen/X86/avx-vshufp.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-basic.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138546&r1=138545&r2=138546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 24 21:58:26 2011 @@ -3178,6 +3178,152 @@ return true; } +/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to 256-bit +/// VSHUFPSY. +static bool isVSHUFPSYMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { + int NumElems = VT.getVectorNumElements(); + + if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) + return false; + + if (NumElems != 8) + return false; + + // VSHUFPSY divides the resulting vector into 4 chunks. + // The sources are also splitted into 4 chunks, and each destination + // chunk must come from a different source chunk. + // + // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 + // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 + // + // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, + // Y3..Y0, Y3..Y0, X3..X0, X3..X0 + // + int QuarterSize = NumElems/4; + int HalfSize = QuarterSize*2; + for (int i = 0; i < QuarterSize; ++i) + if (!isUndefOrInRange(Mask[i], 0, HalfSize)) + return false; + for (int i = QuarterSize; i < QuarterSize*2; ++i) + if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) + return false; + + // The mask of the second half must be the same as the first but with + // the appropriate offsets. This works in the same way as VPERMILPS + // works with masks. + for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { + if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) + return false; + int FstHalfIdx = i-HalfSize; + if (Mask[FstHalfIdx] < 0) + continue; + if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) + return false; + } + for (int i = QuarterSize*3; i < NumElems; ++i) { + if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) + return false; + int FstHalfIdx = i-HalfSize; + if (Mask[FstHalfIdx] < 0) + continue; + if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) + return false; + + } + + return true; +} + +/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle +/// the specified VECTOR_MASK mask with VSHUFPSY instruction. +static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { + ShuffleVectorSDNode *SVOp = cast(N); + EVT VT = SVOp->getValueType(0); + int NumElems = VT.getVectorNumElements(); + + assert(NumElems == 8 && VT.getSizeInBits() == 256 && + "Only supports v8i32 and v8f32 types"); + + int HalfSize = NumElems/2; + unsigned Mask = 0; + for (int i = 0; i != NumElems ; ++i) { + if (SVOp->getMaskElt(i) < 0) + continue; + // The mask of the first half must be equal to the second one. + unsigned Shamt = (i%HalfSize)*2; + unsigned Elt = SVOp->getMaskElt(i) % HalfSize; + Mask |= Elt << Shamt; + } + + return Mask; +} + +/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to 256-bit +/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS +/// version and the mask of the second half isn't binded with the first +/// one. +static bool isVSHUFPDYMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { + int NumElems = VT.getVectorNumElements(); + + if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) + return false; + + if (NumElems != 4) + return false; + + // VSHUFPSY divides the resulting vector into 4 chunks. + // The sources are also splitted into 4 chunks, and each destination + // chunk must come from a different source chunk. + // + // SRC1 => X3 X2 X1 X0 + // SRC2 => Y3 Y2 Y1 Y0 + // + // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 + // + int QuarterSize = NumElems/4; + int HalfSize = QuarterSize*2; + for (int i = 0; i < QuarterSize; ++i) + if (!isUndefOrInRange(Mask[i], 0, HalfSize)) + return false; + for (int i = QuarterSize; i < QuarterSize*2; ++i) + if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) + return false; + for (int i = QuarterSize*2; i < QuarterSize*3; ++i) + if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) + return false; + for (int i = QuarterSize*3; i < NumElems; ++i) + if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) + return false; + + return true; +} + +/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle +/// the specified VECTOR_MASK mask with VSHUFPDY instruction. +static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { + ShuffleVectorSDNode *SVOp = cast(N); + EVT VT = SVOp->getValueType(0); + int NumElems = VT.getVectorNumElements(); + + assert(NumElems == 4 && VT.getSizeInBits() == 256 && + "Only supports v4i64 and v4f64 types"); + + int HalfSize = NumElems/2; + unsigned Mask = 0; + for (int i = 0; i != NumElems ; ++i) { + if (SVOp->getMaskElt(i) < 0) + continue; + int Elt = SVOp->getMaskElt(i) % HalfSize; + Mask |= Elt << i; + } + + return Mask; +} + /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to 128-bit /// SHUFPS and SHUFPD. @@ -6068,6 +6214,22 @@ return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); } +static inline unsigned getSHUFPOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v8i32: // Use fp unit for int unpack. + case MVT::v8f32: + case MVT::v4i32: // Use fp unit for int unpack. + case MVT::v4f32: return X86ISD::SHUFPS; + case MVT::v4i64: // Use fp unit for int unpack. + case MVT::v4f64: + case MVT::v2i64: // Use fp unit for int unpack. + case MVT::v2f64: return X86ISD::SHUFPD; + default: + llvm_unreachable("Unknown type for shufp*"); + } + return 0; +} + static SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { SDValue V1 = Op.getOperand(0); @@ -6121,7 +6283,7 @@ assert(VT != MVT::v4i32 && "unsupported shuffle type"); // Invert the operand order and use SHUFPS to match it. - return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, + return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, X86::getShuffleSHUFImmediate(SVOp), DAG); } @@ -6357,13 +6519,8 @@ if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); - if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) - return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, - TargetMask, DAG); - - if (VT == MVT::v4f32) - return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, - TargetMask, DAG); + return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, + TargetMask, DAG); } // Check if this can be converted into a logical shift. @@ -6515,15 +6672,9 @@ X86::getShufflePSHUFLWImmediate(SVOp), DAG); - if (isSHUFPMask(M, VT)) { - unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); - if (VT == MVT::v4f32 || VT == MVT::v4i32) - return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, - TargetMask, DAG); - if (VT == MVT::v2f64 || VT == MVT::v2i64) - return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, - TargetMask, DAG); - } + if (isSHUFPMask(M, VT)) + return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, + X86::getShuffleSHUFImmediate(SVOp), DAG); if (X86::isUNPCKL_v_undef_Mask(SVOp)) return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); @@ -6550,6 +6701,16 @@ return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, getShuffleVPERM2F128Immediate(SVOp), DAG); + // Handle VSHUFPSY permutations + if (isVSHUFPSYMask(M, VT, Subtarget)) + return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, + getShuffleVSHUFPSYImmediate(SVOp), DAG); + + // Handle VSHUFPDY permutations + if (isVSHUFPDYMask(M, VT, Subtarget)) + return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, + getShuffleVSHUFPDYImmediate(SVOp), DAG); + //===--------------------------------------------------------------------===// // Since no target specific shuffle was selected for this generic one, // lower it into other known shuffles. FIXME: this isn't true yet, but Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138546&r1=138545&r2=138546&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 24 21:58:26 2011 @@ -1709,7 +1709,7 @@ def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)), (VSHUFPDrri VR128:$src1, VR128:$src2, (SHUFFLE_get_shuf_imm VR128:$src3))>; - // Generic VSHUFPD patterns + def : Pat<(v2f64 (X86Shufps VR128:$src1, (memopv2f64 addr:$src2), (i8 imm:$imm))), (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>; @@ -1717,6 +1717,31 @@ (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))), (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>; + + // 256-bit patterns + def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>; + def : Pat<(v8i32 (X86Shufps VR256:$src1, + (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))), + (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>; + + def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>; + def : Pat<(v8f32 (X86Shufps VR256:$src1, + (memopv8f32 addr:$src2), (i8 imm:$imm))), + (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>; + + def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>; + def : Pat<(v4i64 (X86Shufpd VR256:$src1, + (memopv4i64 addr:$src2), (i8 imm:$imm))), + (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>; + + def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))), + (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>; + def : Pat<(v4f64 (X86Shufpd VR256:$src1, + (memopv4f64 addr:$src2), (i8 imm:$imm))), + (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/CodeGen/X86/avx-basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=138546&r1=138545&r2=138546&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-basic.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-basic.ll Wed Aug 24 21:58:26 2011 @@ -64,10 +64,8 @@ ret <4 x i64> %shuffle } -; CHECK: vpunpckhqdq -; CHECK-NEXT: vextractf128 $1 -; CHECK-NEXT: movlhps -; CHECK-NEXT: vinsertf128 $1 +; CHECK: _B +; CHECK: vshufpd $1, %ymm define <4 x i64> @B(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> Added: llvm/trunk/test/CodeGen/X86/avx-vshufp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vshufp.ll?rev=138546&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-vshufp.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-vshufp.ll Wed Aug 24 21:58:26 2011 @@ -0,0 +1,29 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vshufps $-53, %ymm +define <8 x float> @A(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shuffle +} + +; CHECK: vshufpd $10, %ymm +define <4 x double> @B(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} + +; CHECK: vshufps $-53, %ymm +define <8 x float> @C(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shuffle +} + +; CHECK: vshufpd $2, %ymm +define <4 x double> @D(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp { +entry: + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} From benny.kra at googlemail.com Wed Aug 24 23:04:18 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 25 Aug 2011 04:04:18 -0000 Subject: [llvm-commits] [llvm] r138548 - /llvm/trunk/lib/MC/MCStreamer.cpp Message-ID: <20110825040418.C9A972A6C12C@llvm.org> Author: d0k Date: Wed Aug 24 23:04:18 2011 New Revision: 138548 URL: http://llvm.org/viewvc/llvm-project?rev=138548&view=rev Log: Initialize member variable. Modified: llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=138548&r1=138547&r2=138548&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Aug 24 23:04:18 2011 @@ -22,7 +22,8 @@ MCStreamer::MCStreamer(MCContext &Ctx) : Context(Ctx), EmitEHFrame(true), EmitDebugFrame(false), - CurrentW64UnwindInfo(0) { + CurrentW64UnwindInfo(0), + LastSymbol(0) { const MCSection *section = NULL; SectionStack.push_back(std::make_pair(section, section)); } From dblaikie at gmail.com Wed Aug 24 23:40:38 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 24 Aug 2011 21:40:38 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: On Wed, Aug 24, 2011 at 3:38 PM, Jordy Rose wrote: > A couple comments, though this certainly isn't an area of the code I'm that > familiar with. > Thanks for looking > - Instead of appendTo(string&) and assignTo(string&), why not just add > operator+=(string&, const Twine&) and operator=(string&, const Twine&) ? > Seems more C++ to me. > You're right about appendTo, op+=(std::string&, const Twine&) could just be a friend function of Twine. I'll make that change. Unfortunately op=(std::string&, const Twine&) can't be done because op= must be a non-static member function (of std::string). This is why I hadn't done appendTo as op+= too - I'd assumed it had the same restriction, though that doesn't appear to be the case. > - Re: toNullTerminatedStringRef: A StringRef created from a null-terminated > C string drops the null terminator, so you can't just "test the last > character" to see if it's a null. In fact, having the last character of a > StringRef be null is probably a bug. (Of course, you can't test /past/ the > last character either, because one byte past valid memory is guaranteed to > be a valid address but not guaranteed to be dereferenceable.) > Agreed - pity, though. [I wonder if we could squeeze in a bit (the high bit of the length?) somewhere to store "is this null terminated" - it seems a pity to lose that so often/so easily when going into the StringRef domain] > - You've got several copies of SafeBool.h in the file. I'm guessing this is > the result of reverting and then reapplying patches. (I do this all the time > too.) > Hrm, thanks for that. I'll make a fresh diff. I've done that & manually inspected the diff file & I only see SafeBool.h listed once now. > - TwineString definitely seems evil, but I haven't really thought about it > hard enough to give a good reason why. Oh, it is rather evil, just a moderately quick & dirty, but not utterly broken, solution. The most concrete reason I can come up with is that it muddies StringRef's semantics, mostly - TwineString is a StringRef, but it doesn't at all have the semantics of a StringRef, in fact it has the semantics of a string (mostly... some of the time... if it's not just actually a StringRef) To quote Chris from a previous email where this was discussed: "While it is kinda gross, a subclass of StringRef is probably the lowest friction path to do this." - http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-July/041804.html Not to say that I'm not open to other ideas... > I don't get why you're using a SmallVectorImpl instead of a SmallVector or > SmallString, though. > I think I just used SmallVectorImpl because it's the type that toStringRef required - but SmallString would make more sense if it's got no additional overhead/quirks (or SmallVector, presumably it really doesn't have extra overhead). Settled on SmallString. - David -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/3d39e7cd/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: twine_partial.diff Type: application/octet-stream Size: 43368 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110824/3d39e7cd/attachment-0001.obj From isanbard at gmail.com Thu Aug 25 00:55:40 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 05:55:40 -0000 Subject: [llvm-commits] [llvm] r138550 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/Generic/exception-handling.ll Message-ID: <20110825055540.E70E02A6C12C@llvm.org> Author: void Date: Thu Aug 25 00:55:40 2011 New Revision: 138550 URL: http://llvm.org/viewvc/llvm-project?rev=138550&view=rev Log: LSR wants to split the landing pad's critical edge. Let it do it, but use the proper function to do it. Added: llvm/trunk/test/CodeGen/Generic/exception-handling.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=138550&r1=138549&r2=138550&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Aug 25 00:55:40 2011 @@ -3625,7 +3625,14 @@ Loop *PNLoop = LI.getLoopFor(Parent); if (!PNLoop || Parent != PNLoop->getHeader()) { // Split the critical edge. - BasicBlock *NewBB = SplitCriticalEdge(BB, Parent, P); + BasicBlock *NewBB = 0; + if (!Parent->isLandingPad()) { + NewBB = SplitCriticalEdge(BB, Parent, P); + } else { + SmallVector NewBBs; + SplitLandingPadPredecessors(Parent, BB, "", "", P, NewBBs); + NewBB = NewBBs[0]; + } // If PN is outside of the loop and BB is in the loop, we want to // move the block to be immediately before the PHI block, not Added: llvm/trunk/test/CodeGen/Generic/exception-handling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/exception-handling.ll?rev=138550&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/exception-handling.ll (added) +++ llvm/trunk/test/CodeGen/Generic/exception-handling.ll Thu Aug 25 00:55:40 2011 @@ -0,0 +1,29 @@ +; RUN: llc < %s +; PR10733 +declare void @_Znam() + +define void @_ZNK14gIndexOdometer15AfterExcisionOfERi() uwtable align 2 { +_ZN6Gambit5ArrayIiEC2Ej.exit36: + br label %"9" + +"9": ; preds = %"10", %_ZN6Gambit5ArrayIiEC2Ej.exit36 + %indvar82 = phi i64 [ 0, %_ZN6Gambit5ArrayIiEC2Ej.exit36 ], [ %tmp85, %"10" ] + %tmp85 = add i64 %indvar82, 1 + %tmp = trunc i64 %tmp85 to i32 + invoke void @_ZNK14gIndexOdometer9NoIndicesEv() + to label %"10" unwind label %lpad27 + +"10": ; preds = %"9" + invoke void @_Znam() + to label %"9" unwind label %lpad27 + +lpad27: ; preds = %"10", %"9" + %0 = phi i32 [ undef, %"9" ], [ %tmp, %"10" ] + %1 = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0 + cleanup + resume { i8*, i32 } zeroinitializer +} + +declare void @_ZNK14gIndexOdometer9NoIndicesEv() + +declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*) From craig.topper at gmail.com Thu Aug 25 01:57:46 2011 From: craig.topper at gmail.com (Craig Topper) Date: Thu, 25 Aug 2011 06:57:46 -0000 Subject: [llvm-commits] [llvm] r138551 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/Disassembler/X86/simple-tests.txt Message-ID: <20110825065746.9D92F2A6C12C@llvm.org> Author: ctopper Date: Thu Aug 25 01:57:46 2011 New Revision: 138551 URL: http://llvm.org/viewvc/llvm-project?rev=138551&view=rev Log: Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138551&r1=138550&r2=138551&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 01:57:46 2011 @@ -1220,13 +1220,13 @@ let Predicates = [HasAVX] in { // SSE2 instructions without OpSize prefix def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX; def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX; def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX; def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX; } def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB; @@ -1236,12 +1236,12 @@ def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtps2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, - VEX, Requires<[HasAVX]>; + TB, VEX, Requires<[HasAVX]>; def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), "vcvtps2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd (load addr:$src)))]>, - VEX, Requires<[HasAVX]>; + TB, VEX, Requires<[HasAVX]>; def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, @@ -6159,13 +6159,13 @@ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in { // Zero All YMM registers def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", - [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>; + [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>; } // Zero Upper bits of YMM registers def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", - [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>; + [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>; //===----------------------------------------------------------------------===// // SSE Shuffle pattern fragments Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=138551&r1=138550&r2=138551&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Aug 25 01:57:46 2011 @@ -78,3 +78,9 @@ # CHECK: vandps %ymm3, %ymm1, %ymm0 0xc5 0xf4 0x54 0xc3 + +# CHECK: vzeroall +0xc5 0xfc 0x77 + +# CHECK: vcvtps2pd %xmm0, %ymm0 +0xc5 0xfc 0x5a 0xc0 From craig.topper at gmail.com Thu Aug 25 02:42:00 2011 From: craig.topper at gmail.com (Craig Topper) Date: Thu, 25 Aug 2011 07:42:00 -0000 Subject: [llvm-commits] [llvm] r138552 - in /llvm/trunk: test/MC/Disassembler/X86/simple-tests.txt utils/TableGen/X86DisassemblerTables.cpp Message-ID: <20110825074200.A62E82A6C12D@llvm.org> Author: ctopper Date: Thu Aug 25 02:42:00 2011 New Revision: 138552 URL: http://llvm.org/viewvc/llvm-project?rev=138552&view=rev Log: Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=138552&r1=138551&r2=138552&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Aug 25 02:42:00 2011 @@ -84,3 +84,6 @@ # CHECK: vcvtps2pd %xmm0, %ymm0 0xc5 0xfc 0x5a 0xc0 + +# CHECK: vandps (%rdx), %xmm1, %xmm7 +0xc5 0xf0 0x54 0x3a Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=138552&r1=138551&r2=138552&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original) +++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Thu Aug 25 02:42:00 2011 @@ -515,6 +515,8 @@ o << "IC_VEX_XD"; else if ((index & ATTR_VEX) && (index & ATTR_XS)) o << "IC_VEX_XS"; + else if (index & ATTR_VEX) + o << "IC_VEX"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_64BIT_REXW_XS"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) @@ -538,8 +540,6 @@ o << "IC_XD"; else if (index & ATTR_OPSIZE) o << "IC_OPSIZE"; - else if (index & ATTR_VEX) - o << "IC_VEX"; else o << "IC"; From craig.topper at gmail.com Thu Aug 25 03:11:02 2011 From: craig.topper at gmail.com (Craig Topper) Date: Thu, 25 Aug 2011 08:11:02 -0000 Subject: [llvm-commits] [llvm] r138553 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110825081102.2C1062A6C12D@llvm.org> Author: ctopper Date: Thu Aug 25 03:11:01 2011 New Revision: 138553 URL: http://llvm.org/viewvc/llvm-project?rev=138553&view=rev Log: Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138553&r1=138552&r2=138553&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 03:11:01 2011 @@ -416,22 +416,22 @@ } defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, - "movaps", SSEPackedSingle>, VEX; + "movaps", SSEPackedSingle>, TB, VEX; defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, - "movapd", SSEPackedDouble>, OpSize, VEX; + "movapd", SSEPackedDouble>, TB, OpSize, VEX; defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, - "movups", SSEPackedSingle>, VEX; + "movups", SSEPackedSingle>, TB, VEX; defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, - "movupd", SSEPackedDouble, 0>, OpSize, VEX; + "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX; defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32, - "movaps", SSEPackedSingle>, VEX; + "movaps", SSEPackedSingle>, TB, VEX; defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64, - "movapd", SSEPackedDouble>, OpSize, VEX; + "movapd", SSEPackedDouble>, TB, OpSize, VEX; defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32, - "movups", SSEPackedSingle>, VEX; + "movups", SSEPackedSingle>, TB, VEX; defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64, - "movupd", SSEPackedDouble, 0>, OpSize, VEX; + "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX; defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, "movaps", SSEPackedSingle>, TB; defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, @@ -1451,25 +1451,25 @@ let Defs = [EFLAGS] in { defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, - "ucomiss", SSEPackedSingle>, VEX; + "ucomiss", SSEPackedSingle>, TB, VEX; defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, - "ucomisd", SSEPackedDouble>, OpSize, VEX; + "ucomisd", SSEPackedDouble>, TB, OpSize, VEX; let Pattern = [] in { defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, - "comiss", SSEPackedSingle>, VEX; + "comiss", SSEPackedSingle>, TB, VEX; defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load, - "comisd", SSEPackedDouble>, OpSize, VEX; + "comisd", SSEPackedDouble>, TB, OpSize, VEX; } defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem, - load, "ucomiss", SSEPackedSingle>, VEX; + load, "ucomiss", SSEPackedSingle>, TB, VEX; defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem, - load, "ucomisd", SSEPackedDouble>, OpSize, VEX; + load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX; defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, - load, "comiss", SSEPackedSingle>, VEX; + load, "comiss", SSEPackedSingle>, TB, VEX; defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, - load, "comisd", SSEPackedDouble>, OpSize, VEX; + load, "comisd", SSEPackedDouble>, TB, OpSize, VEX; defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, "ucomiss", SSEPackedSingle>, TB; defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, @@ -1518,19 +1518,19 @@ defm VCMPPS : sse12_cmp_packed, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VCMPPD : sse12_cmp_packed, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; defm VCMPPSY : sse12_cmp_packed, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VCMPPDY : sse12_cmp_packed, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; let Constraints = "$src1 = $dst" in { defm CMPPS : sse12_cmp_packed, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64, VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedDouble>, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32, VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedSingle>, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64, VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedDouble>, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32, VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedSingle>, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64, VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedDouble>, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32, VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedSingle>, VEX_4V; + SSEPackedSingle>, TB, VEX_4V; defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64, VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedDouble>, OpSize, VEX_4V; + SSEPackedDouble>, TB, OpSize, VEX_4V; let Constraints = "$src1 = $dst" in { defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32, @@ -1963,14 +1963,14 @@ // Assembler Only def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), - "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX; + "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), - "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize, + "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, VEX; def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), - "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX; + "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), - "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize, + "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, VEX; } @@ -3184,7 +3184,7 @@ let Predicates = [HasAVX] in { let AddedComplexity = 5 in - defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize, + defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize, VEX; // SSE2 with ImmT == Imm8 and XS prefix. @@ -3399,7 +3399,7 @@ (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), - imm:$src2))]>, OpSize, VEX; + imm:$src2))]>, TB, OpSize, VEX; def PEXTRWri : PDIi8<0xC5, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", @@ -3408,11 +3408,11 @@ // Insert let Predicates = [HasAVX] in { - defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V; + defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V; def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR64:$src2, i32i8imm:$src3), "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", - []>, OpSize, VEX_4V; + []>, TB, OpSize, VEX_4V; } let Constraints = "$src1 = $dst" in From grosser at fim.uni-passau.de Thu Aug 25 03:40:53 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 25 Aug 2011 08:40:53 -0000 Subject: [llvm-commits] [polly] r138554 - /polly/trunk/lib/ScheduleOptimizer.cpp Message-ID: <20110825084053.1E1A52A6C12C@llvm.org> Author: grosser Date: Thu Aug 25 03:40:52 2011 New Revision: 138554 URL: http://llvm.org/viewvc/llvm-project?rev=138554&view=rev Log: ScheduleOptimizer: Fix another memleak Modified: polly/trunk/lib/ScheduleOptimizer.cpp Modified: polly/trunk/lib/ScheduleOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=138554&r1=138553&r2=138554&view=diff ============================================================================== --- polly/trunk/lib/ScheduleOptimizer.cpp (original) +++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Aug 25 03:40:52 2011 @@ -255,7 +255,7 @@ isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, 1); tilingMap = isl_basic_map_add_constraint(tilingMap, c); - c = isl_inequality_alloc(isl_dim_copy(dim)); + c = isl_inequality_alloc(dim); isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, 1); isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, -1); isl_constraint_set_constant_si(c, vectorWidth- 1); From grosser at fim.uni-passau.de Thu Aug 25 03:40:59 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 25 Aug 2011 08:40:59 -0000 Subject: [llvm-commits] [polly] r138555 - in /polly/trunk: lib/Analysis/Dependences.cpp lib/CodeGeneration.cpp lib/ScheduleOptimizer.cpp test/CMakeLists.txt test/ScheduleOptimizer/ test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll Message-ID: <20110825084059.590E02A6C12D@llvm.org> Author: grosser Date: Thu Aug 25 03:40:59 2011 New Revision: 138555 URL: http://llvm.org/viewvc/llvm-project?rev=138555&view=rev Log: Fix crashes due to unaligned parameters Due to the recent introduction of isl_id, parameters need now always to be aligned. This was not yet taken care of in the code path of vectorization and dependence analysis. Added: polly/trunk/test/ScheduleOptimizer/ polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll Modified: polly/trunk/lib/Analysis/Dependences.cpp polly/trunk/lib/CodeGeneration.cpp polly/trunk/lib/ScheduleOptimizer.cpp polly/trunk/test/CMakeLists.txt Modified: polly/trunk/lib/Analysis/Dependences.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/Dependences.cpp?rev=138555&r1=138554&r2=138555&view=diff ============================================================================== --- polly/trunk/lib/Analysis/Dependences.cpp (original) +++ polly/trunk/lib/Analysis/Dependences.cpp Thu Aug 25 03:40:59 2011 @@ -264,6 +264,7 @@ unsigned parallelDimension) { Scop *S = &getCurScop(); isl_union_map *schedule = getCombinedScheduleForDim(S, parallelDimension); + isl_dim *dimModel = isl_union_map_get_dim(schedule); // Calculate distance vector. isl_union_set *scheduleSubset; @@ -310,8 +311,7 @@ isl_union_set *distance_waw = isl_union_map_deltas(restrictedDeps_waw); - isl_dim *dim = isl_dim_set_alloc(S->getCtx(), S->getNumParams(), - parallelDimension); + isl_dim *dim = isl_dim_set_alloc(S->getCtx(), 0, parallelDimension); // [0, 0, 0, 0] - All zero isl_basic_set *allZeroBS = isl_basic_set_universe(isl_dim_copy(dim)); @@ -328,6 +328,7 @@ } isl_set *allZero = isl_set_from_basic_set(allZeroBS); + allZero = isl_set_align_params(allZero, isl_dim_copy(dimModel)); // All zero, last unknown. // [0, 0, 0, ?] @@ -345,6 +346,7 @@ } isl_set *lastUnknown = isl_set_from_basic_set(lastUnknownBS); + lastUnknown = isl_set_align_params(lastUnknown, dimModel); // Valid distance vectors isl_set *validDistances = isl_set_subtract(lastUnknown, allZero); Modified: polly/trunk/lib/CodeGeneration.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=138555&r1=138554&r2=138555&view=diff ============================================================================== --- polly/trunk/lib/CodeGeneration.cpp (original) +++ polly/trunk/lib/CodeGeneration.cpp Thu Aug 25 03:40:59 2011 @@ -1139,8 +1139,10 @@ isl_set *elements = isl_map_range(sub); - if (!isl_set_is_singleton(elements)) + if (!isl_set_is_singleton(elements)) { + isl_set_free(elements); return -1; + } isl_point *p = isl_set_sample_point(elements); Modified: polly/trunk/lib/ScheduleOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=138555&r1=138554&r2=138555&view=diff ============================================================================== --- polly/trunk/lib/ScheduleOptimizer.cpp (original) +++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Aug 25 03:40:59 2011 @@ -76,8 +76,7 @@ isl_map *scattering = stmt->getScattering(); isl_dim *dim = isl_dim_alloc(isl_map_get_ctx(scattering), - isl_map_n_param(scattering), - isl_map_n_out(scattering), + 0, isl_map_n_out(scattering), scatDimensions); isl_basic_map *changeScattering = isl_basic_map_universe(isl_dim_copy(dim)); @@ -96,6 +95,8 @@ isl_map *changeScatteringMap = isl_map_from_basic_map(changeScattering); + isl_dim *dimModel = isl_map_get_dim(scattering); + changeScatteringMap = isl_map_align_params(changeScatteringMap, dimModel); stmt->setScattering(isl_map_apply_range(scattering, changeScatteringMap)); isl_dim_free(dim); } @@ -128,7 +129,7 @@ // S(i,j) // static isl_basic_map *getTileMap(isl_ctx *ctx, int scheduleDimensions, - int parameterDimensions, int tileSize = 32) { + isl_dim *dimModel, int tileSize = 32) { // We construct // // tileMap := [p0] -> {[s0, s1] -> [t0, t1, p0, p1, a0, a1]: @@ -136,8 +137,8 @@ // s1 = a1 * 32 and s1 = p1 and t1 <= p1 < t1 + 32} // // and project out the auxilary dimensions a0 and a1. - isl_dim *dim = isl_dim_alloc(ctx, parameterDimensions, scheduleDimensions, - scheduleDimensions * 3); + isl_dim *dim = isl_dim_alloc(ctx, 0, scheduleDimensions, + scheduleDimensions * 3); isl_basic_map *tileMap = isl_basic_map_universe(isl_dim_copy(dim)); for (int x = 0; x < scheduleDimensions; x++) { @@ -188,7 +189,7 @@ isl_union_map *getTiledPartialSchedule(isl_band *band) { isl_union_map *partialSchedule; - int scheduleDimensions, parameterDimensions; + int scheduleDimensions; isl_ctx *ctx; isl_dim *dim; isl_basic_map *tileMap; @@ -198,15 +199,12 @@ ctx = isl_union_map_get_ctx(partialSchedule); dim = isl_union_map_get_dim(partialSchedule); scheduleDimensions = isl_band_n_member(band); - parameterDimensions = isl_dim_size(dim, isl_dim_param); - tileMap = getTileMap(ctx, scheduleDimensions, parameterDimensions); + tileMap = getTileMap(ctx, scheduleDimensions, dim); tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap)); - + tileUnionMap = isl_union_map_align_params(tileUnionMap, dim); partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap); - isl_dim_free(dim); - return partialSchedule; } @@ -288,8 +286,6 @@ partialSchedule = getTiledPartialSchedule(band); int scheduleDimensions = isl_band_n_member(band); isl_dim *dim = isl_union_map_get_dim(partialSchedule); - int parameterDimensions = isl_dim_size(dim, isl_dim_param); - isl_dim_free(dim); if (isl_band_has_children(band)) { @@ -307,9 +303,10 @@ for (int i = scheduleDimensions - 1 ; i >= 0 ; i--) { if (isl_band_member_is_zero_distance(band, i)) { tileMap = getPrevectorMap(ctx, scheduleDimensions + i, - scheduleDimensions * 2, - parameterDimensions); + scheduleDimensions * 2, 0); tileUnionMap = isl_union_map_from_map(tileMap); + tileUnionMap = isl_union_map_align_params(tileUnionMap, + isl_dim_copy(dim)); partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap); break; @@ -323,6 +320,7 @@ finalSchedule = partialSchedule; isl_band_free(band); + isl_dim_free(dim); } return finalSchedule; Modified: polly/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CMakeLists.txt?rev=138555&r1=138554&r2=138555&view=diff ============================================================================== --- polly/trunk/test/CMakeLists.txt (original) +++ polly/trunk/test/CMakeLists.txt Thu Aug 25 03:40:59 2011 @@ -1,6 +1,7 @@ set(POLLY_TEST_DIRECTORIES - "ScopInfo" "AffineIterator" + "ScopInfo" + "ScheduleOptimizer" "CodeGen" "OpenMP" "polybench" Added: polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll?rev=138555&view=auto ============================================================================== --- polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll (added) +++ polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll Thu Aug 25 03:40:59 2011 @@ -0,0 +1,50 @@ +; RUN: opt %loadPolly -polly-optimize-isl -polly-cloog -analyze %s -S | FileCheck %s +; RUN: opt %loadPolly -polly-optimize-isl -polly-cloog -analyze -enable-schedule-prevector %s -S | FileCheck %s -check-prefix=VECTOR + + +target datalayout = +"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-pc-linux-gnu" + +define void @f(i32* nocapture %A, i32 %N, i32 %C) nounwind { +bb: + %tmp1 = icmp sgt i32 %N, 0 + br i1 %tmp1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %bb + %tmp = zext i32 %N to i64 + br label %bb2 + +bb2: ; preds = %bb2, %.lr.ph + %indvar = phi i64 [ 0, %.lr.ph ], [ %indvar.next, %bb2 ] + %scevgep = getelementptr i32* %A, i64 %indvar + %tmp3 = load i32* %scevgep, align 4 + %tmp4 = add nsw i32 %tmp3, %C + store i32 %tmp4, i32* %scevgep, align 4 + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp eq i64 %indvar.next, %tmp + br i1 %exitcond, label %._crit_edge, label %bb2 + +._crit_edge: ; preds = %bb2, %bb + ret void +} + +; CHECK: if (M >= 1) { +; CHECK: for (c1=0;c1<=M-1;c1+=32) { +; CHECK: for (c2=c1;c2<=min(M-1,c1+31);c2++) { +; CHECK: Stmt_bb2(c2); +; CHECK: } +; CHECK: } +; CHECK: } + +; VECTOR: if (M >= 1) { +; VECTOR: for (c1=0;c1<=M-1;c1+=32) { +; VECTOR: for (c2=-4*floord(-c1,4);c2<=min(M-1,c1+31);c2+=4) { +; VECTOR: for (c3=c2;c3<=min(M-1,c2+3);c3++) { +; VECTOR: Stmt_bb2(c3); +; VECTOR: } +; VECTOR: } +; VECTOR: } +; VECTOR: } + + From aaron at aaronballman.com Thu Aug 25 10:46:37 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Thu, 25 Aug 2011 10:46:37 -0500 Subject: [llvm-commits] [PATCH] Support for instruction cache flushing on Windows Message-ID: On Windows, there was no implementation for llvm::sys::Memory::InvalidateInstructionCache, which I've rectified with this patch. Tested with Visual Studio 2010 and MinGW, though I will admit that it shows no functional differences on my particular hardware. That doesn't mean it won't be useful on other hardware though. ~Aaron -------------- next part -------------- A non-text attachment was scrubbed... Name: Memory1.diff Type: application/octet-stream Size: 479 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/4990493c/attachment.obj From bruno.cardoso at gmail.com Thu Aug 25 11:15:42 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 09:15:42 -0700 Subject: [llvm-commits] [llvm] r138553 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td In-Reply-To: <20110825081102.2C1062A6C12D@llvm.org> References: <20110825081102.2C1062A6C12D@llvm.org> Message-ID: Testcases? On Thu, Aug 25, 2011 at 1:11 AM, Craig Topper wrote: > Author: ctopper > Date: Thu Aug 25 03:11:01 2011 > New Revision: 138553 > > URL: http://llvm.org/viewvc/llvm-project?rev=138553&view=rev > Log: > Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678. > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td > > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138553&r1=138552&r2=138553&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 03:11:01 2011 > @@ -416,22 +416,22 @@ > ?} > > ?defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movaps", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movaps", SSEPackedSingle>, TB, VEX; > ?defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movapd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movapd", SSEPackedDouble>, TB, OpSize, VEX; > ?defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movups", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movups", SSEPackedSingle>, TB, VEX; > ?defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movupd", SSEPackedDouble, 0>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movupd", SSEPackedDouble, 0>, TB, OpSize, VEX; > > ?defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movaps", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movaps", SSEPackedSingle>, TB, VEX; > ?defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movapd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movapd", SSEPackedDouble>, TB, OpSize, VEX; > ?defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movups", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movups", SSEPackedSingle>, TB, VEX; > ?defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movupd", SSEPackedDouble, 0>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movupd", SSEPackedDouble, 0>, TB, OpSize, VEX; > ?defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "movaps", SSEPackedSingle>, TB; > ?defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64, > @@ -1451,25 +1451,25 @@ > > ?let Defs = [EFLAGS] in { > ? defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ucomiss", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ucomiss", SSEPackedSingle>, TB, VEX; > ? defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ucomisd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ucomisd", SSEPackedDouble>, TB, OpSize, VEX; > ? let Pattern = [] in { > ? ? defm VCOMISS ?: sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"comiss", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"comiss", SSEPackedSingle>, TB, VEX; > ? ? defm VCOMISD ?: sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"comisd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"comisd", SSEPackedDouble>, TB, OpSize, VEX; > ? } > > ? defm Int_VUCOMISS ?: sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "ucomiss", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "ucomiss", SSEPackedSingle>, TB, VEX; > ? defm Int_VUCOMISD ?: sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "ucomisd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX; > > ? defm Int_VCOMISS ?: sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "comiss", SSEPackedSingle>, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "comiss", SSEPackedSingle>, TB, VEX; > ? defm Int_VCOMISD ?: sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "comisd", SSEPackedDouble>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?load, "comisd", SSEPackedDouble>, TB, OpSize, VEX; > ? defm UCOMISS ?: sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "ucomiss", SSEPackedSingle>, TB; > ? defm UCOMISD ?: sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, > @@ -1518,19 +1518,19 @@ > ?defm VCMPPS : sse12_cmp_packed ? ? ? ? ? ? ? ?"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}", > ? ? ? ? ? ? ? ?"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}", > - ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ?defm VCMPPD : sse12_cmp_packed ? ? ? ? ? ? ? ?"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}", > ? ? ? ? ? ? ? ?"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}", > - ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > ?defm VCMPPSY : sse12_cmp_packed ? ? ? ? ? ? ? ?"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}", > ? ? ? ? ? ? ? ?"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}", > - ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ?defm VCMPPDY : sse12_cmp_packed ? ? ? ? ? ? ? ?"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}", > ? ? ? ? ? ? ? ?"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}", > - ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > ?let Constraints = "$src1 = $dst" in { > ? defm CMPPS : sse12_cmp_packed ? ? ? ? ? ? ? ? ?"cmp${cc}ps\t{$src, $dst|$dst, $src}", > @@ -1767,29 +1767,29 @@ > ?let AddedComplexity = 10 in { > ? defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32, > ? ? ? ? VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ? defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64, > ? ? ? ? VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > ? defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32, > ? ? ? ? VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ? defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64, > ? ? ? ? VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > > ? defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32, > ? ? ? ? VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ? defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64, > ? ? ? ? VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > ? defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32, > ? ? ? ? VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedSingle>, TB, VEX_4V; > ? defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64, > ? ? ? ? VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", > - ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, OpSize, VEX_4V; > + ? ? ? ? ? ? ? ? ? ? ? SSEPackedDouble>, TB, OpSize, VEX_4V; > > ? let Constraints = "$src1 = $dst" in { > ? ? defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32, > @@ -1963,14 +1963,14 @@ > > ? // Assembler Only > ? def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), > - ? ? ? ? ? ? "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX; > + ? ? ? ? ? ? "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; > ? def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), > - ? ? ? ? ? ? "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize, > + ? ? ? ? ? ? "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, > ? ? ? ? ? ? ?VEX; > ? def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), > - ? ? ? ? ? ? "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX; > + ? ? ? ? ? ? "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; > ? def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), > - ? ? ? ? ? ? "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize, > + ? ? ? ? ? ? "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, > ? ? ? ? ? ? ?VEX; > ?} > > @@ -3184,7 +3184,7 @@ > > ?let Predicates = [HasAVX] in { > ? let AddedComplexity = 5 in > - ?defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize, > + ?defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VEX; > > ? // SSE2 with ImmT == Imm8 and XS prefix. > @@ -3399,7 +3399,7 @@ > ? ? ? ? ? ? ? ? ? ? (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), > ? ? ? ? ? ? ? ? ? ? "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", > ? ? ? ? ? ? ? ? ? ? [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?imm:$src2))]>, OpSize, VEX; > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?imm:$src2))]>, TB, OpSize, VEX; > ?def PEXTRWri : PDIi8<0xC5, MRMSrcReg, > ? ? ? ? ? ? ? ? ? ? (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), > ? ? ? ? ? ? ? ? ? ? "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", > @@ -3408,11 +3408,11 @@ > > ?// Insert > ?let Predicates = [HasAVX] in { > - ?defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V; > + ?defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V; > ? def ?VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), > ? ? ? ?(ins VR128:$src1, GR64:$src2, i32i8imm:$src3), > ? ? ? ?"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", > - ? ? ? []>, OpSize, VEX_4V; > + ? ? ? []>, TB, OpSize, VEX_4V; > ?} > > ?let Constraints = "$src1 = $dst" in > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From aaron at aaronballman.com Thu Aug 25 11:32:57 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Thu, 25 Aug 2011 11:32:57 -0500 Subject: [llvm-commits] [PATCH] Removed FIXME from Memory.inc on Windows Message-ID: This patch addresses a FIXME in the Memory class on Windows. It now supports allocating blocks of memory around the "NearBlock" parameter. Additionally, it adds support for changing the protection for blocks of virtual memory. Tested with Visual Studio 2010 and MinGW. ~Aaron -------------- next part -------------- A non-text attachment was scrubbed... Name: Memory2.diff Type: application/octet-stream Size: 2713 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/8d6d1af9/attachment.obj From grosbach at apple.com Thu Aug 25 12:23:56 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 25 Aug 2011 17:23:56 -0000 Subject: [llvm-commits] [llvm] r138562 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110825172356.2171F2A6C12C@llvm.org> Author: grosbach Date: Thu Aug 25 12:23:55 2011 New Revision: 138562 URL: http://llvm.org/viewvc/llvm-project?rev=138562&view=rev Log: Explicitly disallow predication in Thumb1 assembly. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138562&r1=138561&r2=138562&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 25 12:23:55 2011 @@ -2952,6 +2952,12 @@ Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, ProcessorIMod); + // In Thumb1, only the branch (B) instruction can be predicated. + if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { + Parser.EatToEndOfStatement(); + return Error(NameLoc, "conditional execution not supported in Thumb1"); + } + Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); // FIXME: This is all a pretty gross hack. We should automatically handle From atrick at apple.com Thu Aug 25 12:40:54 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 25 Aug 2011 17:40:54 -0000 Subject: [llvm-commits] [llvm] r138566 - /llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Message-ID: <20110825174054.9D6D92A6C12C@llvm.org> Author: atrick Date: Thu Aug 25 12:40:54 2011 New Revision: 138566 URL: http://llvm.org/viewvc/llvm-project?rev=138566&view=rev Log: whitespace Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=138566&r1=138565&r2=138566&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Aug 25 12:40:54 2011 @@ -503,7 +503,7 @@ } } } else if (AFI->isThumb2Function()) { - // Use add , sp, # + // Use add , sp, # // ldr , [sp, #] // if at all possible to save space. if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) From atrick at apple.com Thu Aug 25 12:50:53 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 25 Aug 2011 17:50:53 -0000 Subject: [llvm-commits] [llvm] r138568 - in /llvm/trunk: lib/Target/ARM/ARMFrameLowering.cpp test/CodeGen/ARM/2011-08-25-ldmia_ret.ll Message-ID: <20110825175054.0B3322A6C12C@llvm.org> Author: atrick Date: Thu Aug 25 12:50:53 2011 New Revision: 138568 URL: http://llvm.org/viewvc/llvm-project?rev=138568&view=rev Log: ARM fix for missing implicit operands on ldmia_ret. rdar://10005094: miscompile of 176.gcc Added: llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=138568&r1=138567&r2=138568&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Aug 25 12:50:53 2011 @@ -646,8 +646,10 @@ .addReg(ARM::SP)); for (unsigned i = 0, e = Regs.size(); i < e; ++i) MIB.addReg(Regs[i], getDefRegState(true)); - if (DeleteRet) + if (DeleteRet) { + MIB->copyImplicitOps(&*MI); MI->eraseFromParent(); + } MI = MIB; } else if (Regs.size() == 1) { // If we adjusted the reg to PC from LR above, switch it back here. We Added: llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll?rev=138568&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll Thu Aug 25 12:50:53 2011 @@ -0,0 +1,100 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; Test that ldmia_ret preserves implicit operands for return values. +; +; This CFG is reduced from a benchmark miscompile. With current +; if-conversion heuristics, one of the return paths is if-converted +; into sw.bb18 resulting in an ldmia_ret in the middle of the +; block. The postra scheduler needs to know that the return implicitly +; uses the return register, otherwise its antidep breaker scavenges +; the register in order to hoist the constant load required to test +; the switch. + +declare i32 @getint() +declare i1 @getbool() +declare void @foo(i32) +declare i32 @bar(i32) + +define i32 @test(i32 %in1, i32 %in2) nounwind { +entry: + %call = tail call zeroext i1 @getbool() nounwind + br i1 %call, label %sw.bb18, label %sw.bb2 + +sw.bb2: ; preds = %entry + %cmp = tail call zeroext i1 @getbool() nounwind + br i1 %cmp, label %sw.epilog58, label %land.lhs.true + +land.lhs.true: ; preds = %sw.bb2 + %cmp13 = tail call zeroext i1 @getbool() nounwind + br i1 %cmp13, label %if.then, label %sw.epilog58 + +if.then: ; preds = %land.lhs.true + tail call void @foo(i32 %in1) nounwind + br label %sw.epilog58 + +; load the return value +; CHECK: movs [[RRET:r.]], #2 +; hoist the switch constant without clobbering RRET +; CHECK: movw +; CHECK-NOT: [[RRET]] +; CHECK: , #63707 +; CHECK-NOT: [[RRET]] +; CHECK: tst +; If-convert the return +; CHECK: it ne +; Fold the CSR+return into a pop +; CHECK: popne {r4, r5, r7, pc} +sw.bb18: + %call20 = tail call i32 @bar(i32 %in2) nounwind + switch i32 %call20, label %sw.default56 [ + i32 168, label %sw.bb21 + i32 165, label %sw.bb21 + i32 261, label %sw.epilog58 + i32 188, label %sw.epilog58 + i32 187, label %sw.epilog58 + i32 186, label %sw.epilog58 + i32 185, label %sw.epilog58 + i32 184, label %sw.epilog58 + i32 175, label %sw.epilog58 + i32 174, label %sw.epilog58 + i32 173, label %sw.epilog58 + i32 172, label %sw.epilog58 + i32 171, label %sw.epilog58 + i32 167, label %sw.epilog58 + i32 166, label %sw.epilog58 + i32 164, label %sw.epilog58 + i32 163, label %sw.epilog58 + i32 161, label %sw.epilog58 + i32 160, label %sw.epilog58 + i32 -1, label %sw.bb33 + ] + +sw.bb21: ; preds = %sw.bb18, %sw.bb18 + tail call void @foo(i32 %in2) nounwind + %call28 = tail call i32 @getint() nounwind + %tobool = icmp eq i32 %call28, 0 + br i1 %tobool, label %if.then29, label %sw.epilog58 + +if.then29: ; preds = %sw.bb21 + tail call void @foo(i32 %in2) nounwind + br label %sw.epilog58 + +sw.bb33: ; preds = %sw.bb18 + %cmp42 = tail call zeroext i1 @getbool() nounwind + br i1 %cmp42, label %sw.default56, label %land.lhs.true44 + +land.lhs.true44: ; preds = %sw.bb33 + %call50 = tail call i32 @getint() nounwind + %cmp51 = icmp slt i32 %call50, 0 + br i1 %cmp51, label %if.then53, label %sw.default56 + +if.then53: ; preds = %land.lhs.true44 + tail call void @foo(i32 %in2) nounwind + br label %sw.default56 + +sw.default56: ; preds = %sw.bb33, %land.lhs.true44, %if.then53, %sw.bb18 + br label %sw.epilog58 + +sw.epilog58: + %retval.0 = phi i32 [ 4, %sw.default56 ], [ 2, %sw.bb21 ], [ 2, %if.then29 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb2 ], [ 2, %land.lhs.true ], [ 2, %if.then ] + ret i32 %retval.0 +} From benny.kra at googlemail.com Thu Aug 25 13:05:56 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 25 Aug 2011 18:05:56 -0000 Subject: [llvm-commits] [llvm] r138573 - /llvm/trunk/lib/Support/Host.cpp Message-ID: <20110825180556.3BD802A6C12C@llvm.org> Author: d0k Date: Thu Aug 25 13:05:56 2011 New Revision: 138573 URL: http://llvm.org/viewvc/llvm-project?rev=138573&view=rev Log: Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX. Modified: llvm/trunk/lib/Support/Host.cpp Modified: llvm/trunk/lib/Support/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=138573&r1=138572&r2=138573&view=diff ============================================================================== --- llvm/trunk/lib/Support/Host.cpp (original) +++ llvm/trunk/lib/Support/Host.cpp Thu Aug 25 13:05:56 2011 @@ -213,13 +213,13 @@ case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. // As found in a Summer 2010 model iMac. case 37: // Intel Core i7, laptop version. + case 44: // Intel Core i7 processor and Intel Xeon processor. All + // processors are manufactured using the 32 nm process. return "corei7"; // SandyBridge: case 42: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. - case 44: // Intel Core i7 processor and Intel Xeon processor. All - // processors are manufactured using the 32 nm process. case 45: return "corei7-avx"; From dblaikie at gmail.com Thu Aug 25 13:20:46 2011 From: dblaikie at gmail.com (David Blaikie) Date: Thu, 25 Aug 2011 11:20:46 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: > > I think one of the reasons that I've seen SmallVectorImpl instead of > SmallVector or SmallString for a function parameter is in order to > avoid having the template parameter that specifies initial size, which > you would have to do otherwise. Yes - which is rather strange. Taking something that's not part of the type & binding it into the type... I don't really see the benefit there. In the case where you have a SmallString as a member I suppose it would be moderately inconvenient to override the default size in every ctor you have, compared to just specifying it as the template parameter, but that seems marginally beneficial over not having to specify the size whenever you refer to the type. > For example, see > "FindFunctionBackedges" which can be declared in BasicBlockUtils.h and > defined in BasicBlockUtils.cpp without having template instantiation. > I don't know if this applies to your situation. In my particular situation I'm just defining a member SmallString/Vector/VectorImpl in a trivial type (TwineString, that inherits from StringRef & has a ctor that takes a Twine & populates the Small and itself) so the argument/template disparity between Impl & its implementations isn't too much of a big deal to me either way. Just quirky. - David -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/0151739d/attachment.html From resistor at mac.com Thu Aug 25 13:30:18 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Aug 2011 18:30:18 -0000 Subject: [llvm-commits] [llvm] r138575 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110825183018.E32D72A6C12C@llvm.org> Author: resistor Date: Thu Aug 25 13:30:18 2011 New Revision: 138575 URL: http://llvm.org/viewvc/llvm-project?rev=138575&view=rev Log: Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138575&r1=138574&r2=138575&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 25 13:30:18 2011 @@ -2539,8 +2539,8 @@ Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138575&r1=138574&r2=138575&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Thu Aug 25 13:30:18 2011 @@ -29,6 +29,29 @@ 0x42 0x44 #------------------------------------------------------------------------------ +# ADD (SP plus immediate) +#------------------------------------------------------------------------------ +# CHECK: add sp, #508 +# CHECK: add sp, #4 +# CHECK: add r2, sp, #8 +# CHECK: add r2, sp, #1020 + +0x7f 0xb0 +0x01 0xb0 +0x02 0xaa +0xff 0xaa + + +#------------------------------------------------------------------------------ +# ADD (SP plus register) +#------------------------------------------------------------------------------ +# CHECK: add sp, r3 +# CHECK: add r2, sp, r2 + +0x9d 0x44 +0x6a 0x44 + +#------------------------------------------------------------------------------ # ASR (immediate) #------------------------------------------------------------------------------ # CHECK: asrs r2, r3, #32 @@ -442,6 +465,14 @@ 0xd1 0x1a +#------------------------------------------------------------------------------ +# SUB (SP minus immediate) +#------------------------------------------------------------------------------ +# CHECK: sub sp, #12 +# CHECK: sub sp, #508 + +0x83 0xb0 +0xff 0xb0 #------------------------------------------------------------------------------ # SVC From jediknil at belkadan.com Thu Aug 25 13:53:24 2011 From: jediknil at belkadan.com (Jordy Rose) Date: Thu, 25 Aug 2011 11:53:24 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: <8B824C4C-BA2D-49DD-A61F-B88772E4396B@belkadan.com> On Aug 25, 2011, at 11:20, David Blaikie wrote: >> I think one of the reasons that I've seen SmallVectorImpl instead of >> SmallVector or SmallString for a function parameter is in order to >> avoid having the template parameter that specifies initial size, which >> you would have to do otherwise. >> > Yes - which is rather strange. Taking something that's not part of the type & binding it into the type... I don't really see the benefit there. In the case where you have a SmallString as a member I suppose it would be moderately inconvenient to override the default size in every ctor you have, compared to just specifying it as the template parameter, but that seems marginally beneficial over not having to specify the size whenever you refer to the type. FWIW, the way Small* works is it allocates some initial number of elements directly inside the object, which means if it's stack-based, the entire object might live on the stack. // Entirely stack-based until you grow past 32 elements. SmallVector X // Minimum stack size, initial 32-element heap allocation SmallVectorImpl X(32); Without using alloca or VLAs there's no other way to do this besides specifying the size at compile-time. Since TwineString is a sort of adapter class, it makes sense for it to use stack-based storage for small strings, at least to me. Jordy From dblaikie at gmail.com Thu Aug 25 14:12:53 2011 From: dblaikie at gmail.com (David Blaikie) Date: Thu, 25 Aug 2011 12:12:53 -0700 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: <8B824C4C-BA2D-49DD-A61F-B88772E4396B@belkadan.com> References: <8B824C4C-BA2D-49DD-A61F-B88772E4396B@belkadan.com> Message-ID: > > FWIW, the way Small* works is it allocates some initial number of elements > directly inside the object, which means if it's stack-based, the entire > object might live on the stack. > I'd figured as much - which is why I was a bit surprised to see SmallVectorImpl's ctor taking the size at runtime... > // Entirely stack-based until you grow past 32 elements. > SmallVector X > // Minimum stack size, initial 32-element heap allocation > SmallVectorImpl X(32); > I /think/ that isn't the case. Line 68 of SmallVector.hcontains SmallVector's ctor and it has: "SmallVectorImpl (NumTsAvailable)" SmallVector is telling SmallVectorImpl how far past its own memory space it can walk... So my use of SmallVectorImpl was probably entirely erroneous/unsafe/broken. Perhaps SmallVectorImpl's ctor should be protected and/or it could use CRTP to access the size as a compile-time constant (rather than a ctor argument) from the derived type? Hmm, it's using it to runtime initialize the capacity pointer anyway... which only works because this thing never shrinks (so it doesn't have to remember how big the reserved space is because it'll never try to fit back into it if it outgrows it), so no real benefit to initializing the capacity as a compile time constant unless shrinking was supported (it'd save remembering the value as a runtime variable). Fun times, - David -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/e66ae35e/attachment.html From greened at obbligato.org Thu Aug 25 15:18:22 2011 From: greened at obbligato.org (David Greene) Date: Thu, 25 Aug 2011 20:18:22 -0000 Subject: [llvm-commits] [llvm] r138579 - /llvm/trunk/include/llvm/Constants.h Message-ID: <20110825201822.CD1B12A6C12C@llvm.org> Author: greened Date: Thu Aug 25 15:18:22 2011 New Revision: 138579 URL: http://llvm.org/viewvc/llvm-project?rev=138579&view=rev Log: Constify Comparison Make ConstantInt::uge() const so it may be used in const contexts. Modified: llvm/trunk/include/llvm/Constants.h Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=138579&r1=138578&r2=138579&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Thu Aug 25 15:18:22 2011 @@ -203,7 +203,7 @@ /// value. /// @returns true iff this constant is greater or equal to the given number. /// @brief Determine if the value is greater or equal to the given number. - bool uge(uint64_t Num) { + bool uge(uint64_t Num) const { return Val.getActiveBits() > 64 || Val.getZExtValue() >= Num; } From dag at cray.com Thu Aug 25 15:43:59 2011 From: dag at cray.com (David Greene) Date: Thu, 25 Aug 2011 15:43:59 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output Message-ID: Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. --- This patch fixed a bunch of problems we saw related to asm output file size. Please review. Thanks! -Dave lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 46 ++++++++++++++++++++++++++++++-- 1 files changed, 43 insertions(+), 3 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Compress-Repeated-Byte-Output.patch Type: text/x-patch Size: 2548 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/1618f4b4/attachment.bin From bruno.cardoso at gmail.com Thu Aug 25 16:40:34 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 21:40:34 -0000 Subject: [llvm-commits] [llvm] r138587 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110825214034.7B3D42A6C12C@llvm.org> Author: bruno Date: Thu Aug 25 16:40:34 2011 New Revision: 138587 URL: http://llvm.org/viewvc/llvm-project?rev=138587&view=rev Log: Make isMOVDDUP mask check more strict and update comments! Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138587&r1=138586&r2=138587&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 25 16:40:34 2011 @@ -3914,10 +3914,15 @@ } /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to MOVDDUP. +/// specifies a shuffle of elements that is suitable for input to 128-bit +/// version of MOVDDUP. bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { - int e = N->getValueType(0).getVectorNumElements() / 2; + EVT VT = N->getValueType(0); + + if (VT.getSizeInBits() != 128) + return false; + int e = VT.getVectorNumElements() / 2; for (int i = 0; i < e; ++i) if (!isUndefOrEqual(N->getMaskElt(i), i)) return false; From bruno.cardoso at gmail.com Thu Aug 25 16:40:37 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 21:40:37 -0000 Subject: [llvm-commits] [llvm] r138588 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-vmovddup.ll Message-ID: <20110825214038.037902A6C12D@llvm.org> Author: bruno Date: Thu Aug 25 16:40:37 2011 New Revision: 138588 URL: http://llvm.org/viewvc/llvm-project?rev=138588&view=rev Log: Add support for AVX 256-bit version of MOVDDUP! Added: llvm/trunk/test/CodeGen/X86/avx-vmovddup.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138588&r1=138587&r2=138588&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 25 16:40:37 2011 @@ -3560,6 +3560,13 @@ if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) return false; + // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern + // FIXME: Need a better way to get rid of this, there's no latency difference + // between UNPCKLPD and MOVDDUP, the later should always be checked first and + // the former later. We should also remove the "_undef" special mask. + if (NumElems == 4 && VT.getSizeInBits() == 256) + return false; + // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate // independently on 128-bit lanes. unsigned NumLanes = VT.getSizeInBits() / 128; @@ -3913,6 +3920,28 @@ return true; } +/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to 256-bit +/// version of MOVDDUP. +static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, + const X86Subtarget *Subtarget) { + EVT VT = N->getValueType(0); + int NumElts = VT.getVectorNumElements(); + bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; + + if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || + !V2IsUndef || NumElts != 4) + return false; + + for (int i = 0; i != NumElts/2; ++i) + if (!isUndefOrEqual(N->getMaskElt(i), 0)) + return false; + for (int i = NumElts/2; i != NumElts; ++i) + if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) + return false; + return true; +} + /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to 128-bit /// version of MOVDDUP. @@ -6691,6 +6720,10 @@ // supported in the AVX instruction set. // + // Handle VMOVDDUPY permutations + if (isMOVDDUPYMask(SVOp, Subtarget)) + return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); + // Handle VPERMILPS* permutations if (isVPERMILPSMask(M, VT, Subtarget)) return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138588&r1=138587&r2=138588&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 16:40:37 2011 @@ -4010,6 +4010,20 @@ def : Pat<(X86Movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src))))), (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>; + + // 256-bit version + def : Pat<(X86Movddup (memopv4f64 addr:$src)), + (VMOVDDUPYrm addr:$src)>; + def : Pat<(X86Movddup (memopv4i64 addr:$src)), + (VMOVDDUPYrm addr:$src)>; + def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))), + (VMOVDDUPYrm addr:$src)>; + def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))), + (VMOVDDUPYrm addr:$src)>; + def : Pat<(X86Movddup (v4f64 VR256:$src)), + (VMOVDDUPYrr VR256:$src)>; + def : Pat<(X86Movddup (v4i64 VR256:$src)), + (VMOVDDUPYrr VR256:$src)>; } //===---------------------------------------------------------------------===// Added: llvm/trunk/test/CodeGen/X86/avx-vmovddup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vmovddup.ll?rev=138588&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-vmovddup.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx-vmovddup.ll Thu Aug 25 16:40:37 2011 @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vmovddup %ymm +define <4 x i64> @A(<4 x i64> %a) { + %c = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> + ret <4 x i64> %c +} + +; CHECK: vmovddup (% +define <4 x i64> @B(<4 x i64>* %ptr) { + %a = load <4 x i64>* %ptr + %c = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> + ret <4 x i64> %c +} From nicholas at mxc.ca Thu Aug 25 16:46:20 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 25 Aug 2011 21:46:20 -0000 Subject: [llvm-commits] [llvm] r138589 - /llvm/trunk/lib/Target/ARM/ARM.td Message-ID: <20110825214620.992272A6C12C@llvm.org> Author: nicholas Date: Thu Aug 25 16:46:20 2011 New Revision: 138589 URL: http://llvm.org/viewvc/llvm-project?rev=138589&view=rev Log: Remove stray fullstop. Modified: llvm/trunk/lib/Target/ARM/ARM.td Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=138589&r1=138588&r2=138589&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Aug 25 16:46:20 2011 @@ -85,7 +85,7 @@ /// Some M architectures don't have the DSP extension (v7E-M vs. v7M) def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", - "Supports v7 DSP instructions in Thumb2.">; + "Supports v7 DSP instructions in Thumb2">; // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", From michael at lunarg.com Thu Aug 25 12:48:23 2011 From: michael at lunarg.com (Michael Ilseman) Date: Thu, 25 Aug 2011 11:48:23 -0600 Subject: [llvm-commits] Twine/StringRef enhancements & usage In-Reply-To: References: Message-ID: >> I don't get why you're using a SmallVectorImpl instead of a SmallVector or >> SmallString, though. > > I think I just used SmallVectorImpl because it's the type that toStringRef > required - but SmallString would make more sense if it's got no additional > overhead/quirks (or SmallVector, presumably it really doesn't have extra > overhead). > Settled on SmallString. I think one of the reasons that I've seen SmallVectorImpl instead of SmallVector or SmallString for a function parameter is in order to avoid having the template parameter that specifies initial size, which you would have to do otherwise. For example, see "FindFunctionBackedges" which can be declared in BasicBlockUtils.h and defined in BasicBlockUtils.cpp without having template instantiation. I don't know if this applies to your situation. As an aside, this happens to unfortunately not be symmetric with SmallSetImpl vs SmallSet where both take a size. On Wed, Aug 24, 2011 at 10:40 PM, David Blaikie wrote: > > > On Wed, Aug 24, 2011 at 3:38 PM, Jordy Rose wrote: >> >> A couple comments, though this certainly isn't an area of the code I'm >> that familiar with. > > Thanks for looking > >> >> - Instead of appendTo(string&) and assignTo(string&), why not just add >> operator+=(string&, const Twine&) and operator=(string&, const Twine&) ? >> Seems more C++ to me. > > You're right about appendTo, op+=(std::string&, const Twine&) could just be > a friend function of Twine. I'll make that change. > Unfortunately op=(std::string&, const Twine&) can't be done because op= must > be a non-static member function (of std::string). This is why I hadn't done > appendTo as op+= too - I'd assumed it had the same restriction, though that > doesn't appear to be the case. > >> >> - Re: toNullTerminatedStringRef: A StringRef created from a >> null-terminated C string drops the null terminator, so you can't just "test >> the last character" to see if it's a null. In fact, having the last >> character of a StringRef be null is probably a bug. (Of course, you can't >> test /past/ the last character either, because one byte past valid memory is >> guaranteed to be a valid address but not guaranteed to be dereferenceable.) > > Agreed - pity, though. [I wonder if we could squeeze in a bit (the high bit > of the length?) somewhere to store "is this null terminated" - it seems a > pity to lose that so often/so easily when going into the StringRef domain] > >> >> - You've got several copies of SafeBool.h in the file. I'm guessing this >> is the result of reverting and then reapplying patches. (I do this all the >> time too.) > > Hrm, thanks for that. I'll make a fresh diff. I've done that & manually > inspected the diff file & I only see SafeBool.h listed once now. > >> >> - TwineString definitely seems evil, but I haven't really thought about it >> hard enough to give a good reason why. > > Oh, it is rather evil, just a moderately quick & dirty, but not utterly > broken, solution. The most concrete reason I can come up with is that it > muddies StringRef's semantics, mostly - TwineString is a StringRef, but it > doesn't at all have the semantics of a StringRef, in fact it has the > semantics of a string (mostly... some of the time... if it's not just > actually a StringRef) > To quote Chris from a previous email where this was discussed: > > "While it is kinda gross, a subclass of StringRef is probably the lowest > friction path to do this." - > http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-July/041804.html > Not to say that I'm not open to other ideas... > >> >> I don't get why you're using a SmallVectorImpl instead of a SmallVector or >> SmallString, though. > > I think I just used SmallVectorImpl because it's the type that toStringRef > required - but SmallString would make more sense if it's got no additional > overhead/quirks (or SmallVector, presumably it really doesn't have extra > overhead). > Settled on SmallString. > - David > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From zvi.rackover at intel.com Thu Aug 25 16:04:26 2011 From: zvi.rackover at intel.com (Rackover, Zvi) Date: Fri, 26 Aug 2011 00:04:26 +0300 Subject: [llvm-commits] Fix Candidate for Bug 8460 Message-ID: <2B8953F251AC92428D9BBC92D9B218865E9427F702@hasmsx502.ger.corp.intel.com> Hi, Please review the attached fix candidate for bug 8460, and commit if acceptable. Zvi --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/55e4c372/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_bug8460.patch Type: application/octet-stream Size: 2046 bytes Desc: fix_bug8460.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/55e4c372/attachment.obj From bruno.cardoso at gmail.com Thu Aug 25 17:23:58 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 22:23:58 -0000 Subject: [llvm-commits] [llvm] r138592 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110825222358.8E80C2A6C12D@llvm.org> Author: bruno Date: Thu Aug 25 17:23:58 2011 New Revision: 138592 URL: http://llvm.org/viewvc/llvm-project?rev=138592&view=rev Log: Do the same as r138461. Mark VZEROALL as clobbering all YMM registers Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138592&r1=138591&r2=138592&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 17:23:58 2011 @@ -6175,12 +6175,11 @@ def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>; + // Zero Upper bits of YMM registers + def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", + [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>; } -// Zero Upper bits of YMM registers -def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", - [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>; - //===----------------------------------------------------------------------===// // SSE Shuffle pattern fragments //===----------------------------------------------------------------------===// From clattner at apple.com Thu Aug 25 17:34:08 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 25 Aug 2011 15:34:08 -0700 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: References: Message-ID: <9AC8EC0C-70CB-44EE-BF13-B894831661BD@apple.com> On Aug 25, 2011, at 1:43 PM, David Greene wrote: > > Emit a repeated sequence of bytes using .zero. This saves an enormous > amount of asm file space for certain programs. > --- > > This patch fixed a bunch of problems we saw related to asm output file size. > Please review. Thanks! Looks good with a few changes: +static bool isRepeatedByteSequence(const ConstantInt *CI, TargetMachine &TM) { This needs a doxygen comment, also please change it to be something like: static int isRepeatedByteSequence(const Value *V, TargetMachine &TM) { and have it return 0-255 for success and -1 for failure. It should handle the non-ConstantInt case as well. You could even generalize this predicate to handle structs and subarrays if you feel ambitious (but as a follow-on patch). + if (CI->isZero() || + CI->isAllOnesValue() || + TM.getTargetData()->getTypeAllocSize(CI->getType()) == 1) + return true; + + unsigned Bytes = TM.getTargetData()->getTypeAllocSize(CI->getType()); Please don't call getTypeAllocSize twice, use: + if (CI->isZero() || CI->isAllOnesValue()) return true; + unsigned Bytes = TM.getTargetData()->getTypeAllocSize(CI->getType()); if (Bytes == 1) return true; ... + uint64_t Value = CI->getZExtValue(); This will abort for int128_t, please check that the bitwidth of CI is <= 64 bits and a multiple of 8 bits. Please resend with this changes, thanks! -Chris From clattner at apple.com Thu Aug 25 17:35:36 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 25 Aug 2011 15:35:36 -0700 Subject: [llvm-commits] Fix Candidate for Bug 8460 (windows sys::Path) In-Reply-To: <2B8953F251AC92428D9BBC92D9B218865E9427F702@hasmsx502.ger.corp.intel.com> References: <2B8953F251AC92428D9BBC92D9B218865E9427F702@hasmsx502.ger.corp.intel.com> Message-ID: <5F30705B-9EAA-4D71-89F8-8DF85E00EBC5@apple.com> Hi Zvi, Please include the general area of the bug in the subject line, this makes it easier for reviewers of the appropriate interest to take a look. Thanks! -Chris On Aug 25, 2011, at 2:04 PM, Rackover, Zvi wrote: > Hi, > > Please review the attached fix candidate for bug 8460, and commit if acceptable. > > Zvi > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies._______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/0e826eac/attachment.html From joerg at britannica.bec.de Thu Aug 25 17:38:51 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Fri, 26 Aug 2011 00:38:51 +0200 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: References: Message-ID: <20110825223850.GB20095@britannica.bec.de> On Thu, Aug 25, 2011 at 03:43:59PM -0500, David Greene wrote: > > Emit a repeated sequence of bytes using .zero. This saves an enormous > amount of asm file space for certain programs. Is that only using .zero or actually using .fill as needed? Joerg From clattner at apple.com Thu Aug 25 17:48:51 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 25 Aug 2011 15:48:51 -0700 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <20110825223850.GB20095@britannica.bec.de> References: <20110825223850.GB20095@britannica.bec.de> Message-ID: <358FD591-BC39-4C23-92A4-97669EE7C90F@apple.com> On Aug 25, 2011, at 3:38 PM, Joerg Sonnenberger wrote: > On Thu, Aug 25, 2011 at 03:43:59PM -0500, David Greene wrote: >> >> Emit a repeated sequence of bytes using .zero. This saves an enormous >> amount of asm file space for certain programs. > > Is that only using .zero or actually using .fill as needed? It uses .fill if available. -Chris From zvi.rackover at intel.com Thu Aug 25 17:52:56 2011 From: zvi.rackover at intel.com (Rackover, Zvi) Date: Fri, 26 Aug 2011 01:52:56 +0300 Subject: [llvm-commits] [System Lib] Fix Candidate for Bug 8460 Message-ID: <2B8953F251AC92428D9BBC92D9B218865E9427F73D@hasmsx502.ger.corp.intel.com> Adding label to subject. From: Rackover, Zvi Sent: Friday, August 26, 2011 00:04 To: 'llvm-commits at cs.uiuc.edu' Subject: Fix Candidate for Bug 8460 Hi, Please review the attached fix candidate for bug 8460, and commit if acceptable. Zvi --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/7704e0d7/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_bug8460.patch Type: application/octet-stream Size: 2046 bytes Desc: fix_bug8460.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/7704e0d7/attachment.obj From bruno.cardoso at gmail.com Thu Aug 25 17:56:30 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Aug 2011 15:56:30 -0700 Subject: [llvm-commits] [llvm] r138592 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td In-Reply-To: <20110825222358.8E80C2A6C12D@llvm.org> References: <20110825222358.8E80C2A6C12D@llvm.org> Message-ID: Typo here. I meant VZEROUPPER. On Thu, Aug 25, 2011 at 3:23 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Thu Aug 25 17:23:58 2011 > New Revision: 138592 > > URL: http://llvm.org/viewvc/llvm-project?rev=138592&view=rev > Log: > Do the same as r138461. Mark VZEROALL as clobbering all YMM registers > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td > > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138592&r1=138591&r2=138592&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 17:23:58 2011 > @@ -6175,12 +6175,11 @@ > ? def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", > ? ? ? ? ? ? ? ? ? ?[(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>; > > + ?// Zero Upper bits of YMM registers > + ?def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", > + ? ? ? ? ? ? ? ? ? ? [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>; > ?} > > -// Zero Upper bits of YMM registers > -def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", > - ? ? ? ? ? ? ? ? ? [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>; > - > ?//===----------------------------------------------------------------------===// > ?// SSE Shuffle pattern fragments > ?//===----------------------------------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From Xiaoyi.Guo at amd.com Thu Aug 25 17:25:55 2011 From: Xiaoyi.Guo at amd.com (Guo, Xiaoyi) Date: Thu, 25 Aug 2011 17:25:55 -0500 Subject: [llvm-commits] Pass manager bug fix Message-ID: <27F465BDABE6954AABB2A4E3599BDAC702A49D213F@sausexmbp02.amd.com> Please review the attached fix for a problem in the pass manager, and commit if acceptable. The fix is against TOT and has passed regression tests. The problem is in the assignPassManager() methods. For example, in LoopPass::assignPassManager(): // Create new Loop Pass Manager if it does not exist. assert (!PMS.empty() && "Unable to create Loop Pass Manager"); PMDataManager *PMD = PMS.top(); // [1] Create new Call Graph Pass Manager LPPM = new LPPassManager(); LPPM->populateInheritedAnalysis(PMS); // [2] Set up new manager's top level manager PMTopLevelManager *TPM = PMD->getTopLevelManager(); TPM->addIndirectPassManager(LPPM); // [3] Assign manager to manage this new manager. This may create // and push new managers into PMS Pass *P = LPPM->getAsPass(); TPM->schedulePass(P); // [4] Push new manager into PMS PMS.push(LPPM); Step 3 above may create and push new managers into PMS, in which case the Depth of LPPM will no longer be correct. This may in turn cause other things to go wrong. For example, it may cause some analysis passes to be freed prematurely and cause crash. My fix is to not set the depth of a pass manager until it is pushed onto the stack. Regards, Xiaoyi -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/1adcab34/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: PassManager.diff Type: application/octet-stream Size: 9371 bytes Desc: PassManager.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/1adcab34/attachment.obj From isanbard at gmail.com Thu Aug 25 18:22:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 23:22:41 -0000 Subject: [llvm-commits] [llvm] r138602 - in /llvm/trunk: include/llvm/AutoUpgrade.h lib/VMCore/AutoUpgrade.cpp Message-ID: <20110825232241.12CED2A6C12C@llvm.org> Author: void Date: Thu Aug 25 18:22:40 2011 New Revision: 138602 URL: http://llvm.org/viewvc/llvm-project?rev=138602&view=rev Log: Initial check in that will auto-upgrade the old EH scheme to the new EH scheme. This upgrade suffers from the problems of the old EH scheme - i.e., that the calls to llvm.eh.exception() and llvm.eh.selector() can wander off and get lost. It makes a valiant effort to reclaim these little lost lambs. This is a first draft, so it hasn't yet been hooked up to the parser. Modified: llvm/trunk/include/llvm/AutoUpgrade.h llvm/trunk/lib/VMCore/AutoUpgrade.cpp Modified: llvm/trunk/include/llvm/AutoUpgrade.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/AutoUpgrade.h?rev=138602&r1=138601&r2=138602&view=diff ============================================================================== --- llvm/trunk/include/llvm/AutoUpgrade.h (original) +++ llvm/trunk/include/llvm/AutoUpgrade.h Thu Aug 25 18:22:40 2011 @@ -43,6 +43,10 @@ /// This function checks debug info intrinsics. If an intrinsic is invalid /// then this function simply removes the intrinsic. void CheckDebugInfoIntrinsics(Module *M); + + /// This function upgrades the old pre-3.0 exception handling system to the + /// new one. N.B. This will be removed in 3.1. + void UpgradeExceptionHandling(Module *M); } // End llvm namespace #endif Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=138602&r1=138601&r2=138602&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Thu Aug 25 18:22:40 2011 @@ -14,11 +14,15 @@ #include "llvm/AutoUpgrade.h" #include "llvm/Constants.h" #include "llvm/Function.h" +#include "llvm/Instruction.h" #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/IntrinsicInst.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CallSite.h" +#include "llvm/Support/CFG.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/IRBuilder.h" #include @@ -279,3 +283,200 @@ } } } + +/// FindExnAndSelIntrinsics - Find the eh_exception and eh_selector intrinsic +/// calls reachable from the unwind basic block. +static void FindExnAndSelIntrinsics(BasicBlock *BB, CallInst *&Exn, + CallInst *&Sel, + SmallPtrSet &Visited) { + if (!Visited.insert(BB)) return; + + for (BasicBlock::iterator + I = BB->begin(), E = BB->end(); I != E; ++I) { + if (CallInst *CI = dyn_cast(I)) { + switch (CI->getCalledFunction()->getIntrinsicID()) { + default: break; + case Intrinsic::eh_exception: + assert(!Exn && "Found more than one eh.exception call!"); + Exn = CI; + break; + case Intrinsic::eh_selector: + assert(!Sel && "Found more than one eh.selector call!"); + Sel = CI; + break; + } + + if (Exn && Sel) return; + } + } + + if (Exn && Sel) return; + + for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { + FindExnAndSelIntrinsics(*I, Exn, Sel, Visited); + if (Exn && Sel) return; + } +} + +/// TransferClausesToLandingPadInst - Transfer the exception handling clauses +/// from the eh_selector call to the new landingpad instruction. +static void TransferClausesToLandingPadInst(LandingPadInst *LPI, + CallInst *EHSel) { + LLVMContext &Context = LPI->getContext(); + unsigned N = EHSel->getNumArgOperands(); + + for (unsigned i = N - 1; i > 1; --i) { + if (const ConstantInt *CI = dyn_cast(EHSel->getArgOperand(i))){ + unsigned FilterLength = CI->getZExtValue(); + unsigned FirstCatch = i + FilterLength + !FilterLength; + assert(FirstCatch <= N && "Invalid filter length"); + + if (FirstCatch < N) + for (unsigned j = FirstCatch; j < N; ++j) { + Value *Val = EHSel->getArgOperand(j); + if (!Val->hasName() || Val->getName() != "llvm.eh.catch.all.value") { + LPI->addClause(EHSel->getArgOperand(j)); + } else { + GlobalVariable *GV = cast(Val); + LPI->addClause(GV->getInitializer()); + } + } + + if (!FilterLength) { + // Cleanup. + LPI->setCleanup(true); + } else { + // Filter. + SmallVector TyInfo; + TyInfo.reserve(FilterLength - 1); + for (unsigned j = i + 1; j < FirstCatch; ++j) + TyInfo.push_back(cast(EHSel->getArgOperand(j))); + ArrayType *AType = + ArrayType::get(!TyInfo.empty() ? TyInfo[0]->getType() : + PointerType::getUnqual(Type::getInt8Ty(Context)), + TyInfo.size()); + LPI->addClause(ConstantArray::get(AType, TyInfo)); + } + + N = i; + } + } + + if (N > 2) + for (unsigned j = 2; j < N; ++j) { + Value *Val = EHSel->getArgOperand(j); + if (!Val->hasName() || Val->getName() != "llvm.eh.catch.all.value") { + LPI->addClause(EHSel->getArgOperand(j)); + } else { + GlobalVariable *GV = cast(Val); + LPI->addClause(GV->getInitializer()); + } + } +} + +/// This function upgrades the old pre-3.0 exception handling system to the new +/// one. N.B. This will be removed in 3.1. +void llvm::UpgradeExceptionHandling(Module *M) { + Function *EHException = M->getFunction("llvm.eh.exception"); + Function *EHSelector = M->getFunction("llvm.eh.selector"); + if (!EHException || !EHSelector) + return; + + LLVMContext &Context = M->getContext(); + Type *ExnTy = PointerType::getUnqual(Type::getInt8Ty(Context)); + Type *SelTy = Type::getInt32Ty(Context); + Type *LPadSlotTy = StructType::get(ExnTy, SelTy, NULL); + + // This map stores the slots where the exception object and selector value are + // stored within a function. + SmallVector DeadInsts; + DenseMap > FnToLPadSlotMap; + for (Module::iterator + I = M->begin(), E = M->end(); I != E; ++I) { + Function &F = *I; + + for (Function::iterator + II = F.begin(), IE = F.end(); II != IE; ++II) { + BasicBlock *BB = &*II; + InvokeInst *Inst = dyn_cast(BB->getTerminator()); + if (!Inst) continue; + BasicBlock *UnwindDest = Inst->getUnwindDest(); + if (UnwindDest->isLandingPad()) continue; // All ready converted. + + // Store the exception object and selector value in the entry block. + Value *ExnSlot = 0; + Value *SelSlot = 0; + if (!FnToLPadSlotMap[&F].first) { + BasicBlock *Entry = &F.front(); + ExnSlot = new AllocaInst(ExnTy, "exn", Entry->getTerminator()); + SelSlot = new AllocaInst(SelTy, "sel", Entry->getTerminator()); + FnToLPadSlotMap[&F] = std::make_pair(ExnSlot, SelSlot); + } else { + ExnSlot = FnToLPadSlotMap[&F].first; + SelSlot = FnToLPadSlotMap[&F].second; + } + + // We're in an unwind block. Try to find the eh.exception and eh.selector + // calls. + IRBuilder<> Builder(Context); + Builder.SetInsertPoint(UnwindDest, UnwindDest->getFirstNonPHI()); + + SmallPtrSet Visited; + CallInst *Exn = 0; + CallInst *Sel = 0; + FindExnAndSelIntrinsics(UnwindDest, Exn, Sel, Visited); + assert(Exn && Sel && "Cannot find eh.exception and eh.selector calls!"); + + Value *PersFn = Sel->getArgOperand(1); + LandingPadInst *LPI = Builder.CreateLandingPad(LPadSlotTy, PersFn, 0); + Value *LPExn = Builder.CreateExtractValue(LPI, 0); + Value *LPSel = Builder.CreateExtractValue(LPI, 1); + Builder.CreateStore(LPExn, ExnSlot); + Builder.CreateStore(LPSel, SelSlot); + + TransferClausesToLandingPadInst(LPI, Sel); + + Exn->replaceAllUsesWith(LPExn); + Sel->replaceAllUsesWith(LPSel); + + DeadInsts.push_back(Exn); + DeadInsts.push_back(Sel); + } + } + + // Remove the dead instructions. + while (!DeadInsts.empty()) { + Instruction *Inst = DeadInsts.pop_back_val(); + Inst->eraseFromParent(); + } + + // Replace calls to "llvm.eh.resume" with the 'resume' instruction. Load the + // exception and selector values from the stored place. + Function *EHResume = M->getFunction("llvm.eh.resume"); + if (!EHResume) return; + + while (!EHResume->use_empty()) { + CallInst *Resume = cast(EHResume->use_back()); + BasicBlock *BB = Resume->getParent(); + Function *Fn = BB->getParent(); + std::pair &ExnSel = FnToLPadSlotMap[Fn]; + IRBuilder<> Builder(Context); + Builder.SetInsertPoint(BB, Resume); + + Value *Exn = Builder.CreateLoad(ExnSel.first, "exn"); + Value *Sel = Builder.CreateLoad(ExnSel.second, "sel"); + + Value *LPadVal = + Builder.CreateInsertValue(UndefValue::get(LPadSlotTy), + Exn, 0, "lpad.val"); + LPadVal = Builder.CreateInsertValue(LPadVal, Sel, 1, "lpad.val"); + Builder.CreateResume(LPadVal); + + // Remove all instructions after the 'resume.' + BasicBlock::iterator I = Resume; + while (I != BB->end()) { + Instruction *Inst = &*I++; + Inst->eraseFromParent(); + } + } +} From atrick at apple.com Thu Aug 25 18:38:52 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 25 Aug 2011 23:38:52 -0000 Subject: [llvm-commits] [zorg] r138603 - /zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Message-ID: <20110825233852.100792A6C12C@llvm.org> Author: atrick Date: Thu Aug 25 18:38:51 2011 New Revision: 138603 URL: http://llvm.org/viewvc/llvm-project?rev=138603&view=rev Log: whitespace Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=138603&r1=138602&r2=138603&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Thu Aug 25 18:38:51 2011 @@ -81,13 +81,13 @@ haltOnFailure=True, description=["rm build dir", "llvm"], workdir=".")) - + # Force without llvm-gcc so we don't run afoul of Frontend test failures. base_configure_args = [WithProperties("%%(builddir)s/%s/configure" % llvm_srcdir), '--disable-bindings'] base_configure_args += extra_configure_args if triple: - base_configure_args += ['--build=%s' % triple, + base_configure_args += ['--build=%s' % triple, '--host=%s' % triple, '--target=%s' % triple] args = base_configure_args + ["--without-llvmgcc", "--without-llvmgxx"] @@ -176,7 +176,7 @@ flunkOnFailure=False, haltOnFailure=False)) f.addStep(ShellCommand(name='pkg.upload', - description="upload root", + description="upload root", command=["scp", name, WithProperties( package_dst + "/%(buildername)s")], @@ -259,7 +259,7 @@ flunkOnFailure=False, haltOnFailure=False)) f.addStep(ShellCommand(name='pkg.upload', - description="upload root", + description="upload root", command=["scp", name, WithProperties( package_dst + "/%(buildername)s")], From atrick at apple.com Thu Aug 25 18:39:33 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 25 Aug 2011 23:39:33 -0000 Subject: [llvm-commits] [zorg] r138604 - /zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Message-ID: <20110825233933.C429A2A6C12C@llvm.org> Author: atrick Date: Thu Aug 25 18:39:33 2011 New Revision: 138604 URL: http://llvm.org/viewvc/llvm-project?rev=138604&view=rev Log: clang builders should include common LLVM suppression directives. Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=138604&r1=138603&r2=138604&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Thu Aug 25 18:39:33 2011 @@ -130,7 +130,7 @@ clangTestArgs += ' --vg' if valgrindLeakCheck: clangTestArgs += ' --vg-leak' - clangTestArgs += ' --vg-arg --suppressions=%(builddir)s/llvm/tools/clang/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp' + clangTestArgs += ' --vg-arg --suppressions=%(builddir)s/llvm/tools/clang/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp --suppressions=%(builddir)s/llvm/utils/valgrind/x86_64-pc-linux-gnu.supp' extraTestDirs = '' if run_cxx_tests: extraTestDirs += '%(builddir)s/llvm/tools/clang/utils/C++Tests' From isanbard at gmail.com Thu Aug 25 18:48:11 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 23:48:11 -0000 Subject: [llvm-commits] [llvm] r138605 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Message-ID: <20110825234811.AB3832A6C12C@llvm.org> Author: void Date: Thu Aug 25 18:48:11 2011 New Revision: 138605 URL: http://llvm.org/viewvc/llvm-project?rev=138605&view=rev Log: Look at only the terminators of the basic block. Also, if we're using the new EH scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on the new code. Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=138605&r1=138604&r2=138605&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Thu Aug 25 18:48:11 2011 @@ -663,14 +663,18 @@ /// InsertUnwindResumeCalls - Convert the ResumeInsts that are still present /// into calls to the appropriate _Unwind_Resume function. bool DwarfEHPrepare::InsertUnwindResumeCalls() { + bool UsesNewEH = false; SmallVector Resumes; - for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) - for (BasicBlock::iterator II = I->begin(), IE = I->end(); II != IE; ++II) - if (ResumeInst *RI = dyn_cast(II)) - Resumes.push_back(RI); + for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) { + TerminatorInst *TI = I->getTerminator(); + if (ResumeInst *RI = dyn_cast(TI)) + Resumes.push_back(RI); + else if (InvokeInst *II = dyn_cast(TI)) + UsesNewEH = II->getUnwindDest()->isLandingPad(); + } if (Resumes.empty()) - return false; + return UsesNewEH; // Find the rewind function if we didn't already. if (!RewindFunction) { From isanbard at gmail.com Thu Aug 25 18:48:38 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Aug 2011 23:48:38 -0000 Subject: [llvm-commits] [llvm] r138606 - in /llvm/trunk/test: Assembler/2003-06-17-InvokeDisassemble.ll CodeGen/Generic/2004-02-08-UnwindSupport.ll CodeGen/Generic/2007-02-25-invoke.ll CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll CodeGen/Generic/2007-12-17-InvokeAsm.ll CodeGen/Generic/2007-12-31-UnusedSelector.ll CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll CodeGen/Generic/2009-11-16-BadKillsCrash.ll CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll Message-ID: <20110825234838.1E6BA2A6C12C@llvm.org> Author: void Date: Thu Aug 25 18:48:37 2011 New Revision: 138606 URL: http://llvm.org/viewvc/llvm-project?rev=138606&view=rev Log: Update to the new EH scheme. Modified: llvm/trunk/test/Assembler/2003-06-17-InvokeDisassemble.ll llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll llvm/trunk/test/CodeGen/Generic/2007-02-25-invoke.ll llvm/trunk/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll llvm/trunk/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll llvm/trunk/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll Modified: llvm/trunk/test/Assembler/2003-06-17-InvokeDisassemble.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2003-06-17-InvokeDisassemble.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/Assembler/2003-06-17-InvokeDisassemble.ll (original) +++ llvm/trunk/test/Assembler/2003-06-17-InvokeDisassemble.ll Thu Aug 25 18:48:37 2011 @@ -1,9 +1,13 @@ ; RUN: llvm-as < %s | llvm-dis define void @test() { - invoke void @test( ) - to label %Next unwind label %Next + invoke void @test( ) + to label %Next unwind label %Next Next: ; preds = %0, %0 - ret void + %lpad = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + cleanup + ret void } + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll Thu Aug 25 18:48:37 2011 @@ -12,6 +12,9 @@ ret i32 1 EH: ; preds = %0 - ret i32 0 + %lpad = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + cleanup + ret i32 0 } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2007-02-25-invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-02-25-invoke.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-02-25-invoke.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2007-02-25-invoke.ll Thu Aug 25 18:48:37 2011 @@ -8,5 +8,9 @@ invcont: ret i32 %A blat: - ret i32 0 + %lpad = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + cleanup + ret i32 0 } + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll Thu Aug 25 18:48:37 2011 @@ -45,7 +45,9 @@ ret void cond_true1402: ; preds = %invcont282, %cond_false280, %cond_true235, %cond_true - ret void + %lpad = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + cleanup + ret void } declare void @_ZNSs14_M_replace_auxEjjjc() @@ -57,3 +59,5 @@ declare void @_ZNSs7reserveEj() declare void @_ZNSs6appendEPKcj() + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll Thu Aug 25 18:48:37 2011 @@ -2,12 +2,16 @@ define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() { entry: - invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null ) - to label %.noexc unwind label %cleanup144 + invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null ) + to label %.noexc unwind label %cleanup144 .noexc: ; preds = %entry - ret void + ret void cleanup144: ; preds = %entry - unwind + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup + unwind } + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll Thu Aug 25 18:48:37 2011 @@ -14,11 +14,14 @@ unreachable lpad: ; preds = %entry + %lpad1 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + catch i8* null invoke void @__cxa_end_catch( ) to label %bb14 unwind label %lpad17 lpad17: ; preds = %lpad - %eh_select20 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32( i8* null, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null ) ; [#uses=0] + %lpad2 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + catch i8* null unreachable UnifiedUnreachableBlock: ; preds = %entry Modified: llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll Thu Aug 25 18:48:37 2011 @@ -11,5 +11,9 @@ invoke i32 @b() to label %reg unwind label %reg reg: + %lpad = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + catch i8* null ret void } + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll Thu Aug 25 18:48:37 2011 @@ -64,10 +64,16 @@ lpad: ; preds = %bb.i93, %invcont24, %bb1.i, %invcont8 %__extracted.1 = phi i32 [ 0, %invcont8 ], [ %2, %bb1.i ], [ undef, %bb.i93 ], [ undef, %invcont24 ] ; [#uses=0] - %eh_ptr = call i8* @llvm.eh.exception() ; [#uses=1] + %lpad1 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + catch i8* null + %eh_ptr = extractvalue { i8*, i32 } %lpad1, 0 %6 = call i8* @__cxa_begin_catch(i8* %eh_ptr) nounwind ; [#uses=0] unreachable lpad74: ; preds = %entry + %lpad2 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + cleanup unreachable } + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll?rev=138606&r1=138605&r2=138606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll (original) +++ llvm/trunk/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll Thu Aug 25 18:48:37 2011 @@ -13,6 +13,9 @@ ret void handler: + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + catch i8* null ret void } +declare i32 @__gxx_personality_v0(...) From benny.kra at googlemail.com Thu Aug 25 20:22:29 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 01:22:29 -0000 Subject: [llvm-commits] [llvm] r138618 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/phi-undef-loadstore.ll Message-ID: <20110826012229.9B7272A6C12C@llvm.org> Author: d0k Date: Thu Aug 25 20:22:29 2011 New Revision: 138618 URL: http://llvm.org/viewvc/llvm-project?rev=138618&view=rev Log: SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side. This shrinks the size of a Release clang by 16k on x86_64. Added: llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=138618&r1=138617&r2=138618&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Aug 25 20:22:29 2011 @@ -2723,6 +2723,72 @@ return false; } +/// Check if passing a value to an instruction will cause undefined behavior. +static bool passingValueIsAlwaysUndefined(Value *V, Instruction *I) { + Constant *C = dyn_cast(V); + if (!C) + return false; + + if (!I->hasOneUse()) // FIXME: There is no reason to limit this to one use. + return false; + + if (C->isNullValue()) { + Instruction *Use = I->use_back(); + + // Now make sure that there are no instructions in between that can alter + // control flow (eg. calls) + for (BasicBlock::iterator i = ++BasicBlock::iterator(I); &*i != Use; ++i) + if (i == I->getParent()->end() || + !i->isSafeToSpeculativelyExecute()) + return false; + + // Look through GEPs. A load from a GEP derived from NULL is still undefined + if (GetElementPtrInst *GEP = dyn_cast(Use)) + if (GEP->getPointerOperand() == I) + return passingValueIsAlwaysUndefined(V, GEP); + + // Look through bitcasts. + if (BitCastInst *BC = dyn_cast(Use)) + return passingValueIsAlwaysUndefined(V, BC); + + // load from null is undefined + if (isa(Use)) + return true; + + // store to null is undef + if (isa(Use) && Use->getOperand(1) == I) + return true; + } + return false; +} + +/// If BB has an incoming value that will always trigger undefined behavior +/// (eg. null pointer derefence), remove the branch leading here. +static bool removeUndefIntroducingPredecessor(BasicBlock *BB) { + for (BasicBlock::iterator i = BB->begin(); + PHINode *PHI = dyn_cast(i); ++i) + for (unsigned i = 0, e = PHI->getNumIncomingValues(); i != e; ++i) + if (passingValueIsAlwaysUndefined(PHI->getIncomingValue(i), PHI)) { + TerminatorInst *T = PHI->getIncomingBlock(i)->getTerminator(); + IRBuilder<> Builder(T); + if (BranchInst *BI = dyn_cast(T)) { + BB->removePredecessor(PHI->getIncomingBlock(i)); + // Turn uncoditional branches into unreachables and remove the dead + // destination from conditional branches. + if (BI->isUnconditional()) + Builder.CreateUnreachable(); + else + Builder.CreateBr(BI->getSuccessor(0) == BB ? BI->getSuccessor(1) : + BI->getSuccessor(0)); + BI->eraseFromParent(); + return true; + } + // TODO: SwitchInst. + } + + return false; +} + bool SimplifyCFGOpt::run(BasicBlock *BB) { bool Changed = false; @@ -2746,6 +2812,9 @@ // Check for and eliminate duplicate PHI nodes in this block. Changed |= EliminateDuplicatePHINodes(BB); + // Check for and remove branches that will always cause undefined behavior. + Changed |= removeUndefIntroducingPredecessor(BB); + // Merge basic blocks into their predecessor if there is only one distinct // pred, and if there is only one distinct successor of the predecessor, and // if there are no PHI nodes. Added: llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll?rev=138618&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll Thu Aug 25 20:22:29 2011 @@ -0,0 +1,87 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +declare void @bar() nounwind + +define i32 @test1(i32* %a, i32 %b, i32* %c, i32 %d) nounwind { +entry: + %tobool = icmp eq i32 %b, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void @bar() nounwind + br label %if.end7 + +if.else: ; preds = %entry + %tobool3 = icmp eq i32 %d, 0 + br i1 %tobool3, label %if.end7, label %if.then4 + +if.then4: ; preds = %if.else + tail call void @bar() nounwind + br label %if.end7 + +if.end7: ; preds = %if.else, %if.then4, %if.then + %x.0 = phi i32* [ %a, %if.then ], [ %c, %if.then4 ], [ null, %if.else ] + %tmp9 = load i32* %x.0 + ret i32 %tmp9 + +; CHECK: @test1 +; CHECK: if.else: +; CHECK: br label %if.end7 + +; CHECK: phi i32* [ %a, %if.then ], [ %c, %if.else ] +} + +define i32 @test2(i32* %a, i32 %b, i32* %c, i32 %d) nounwind { +entry: + %tobool = icmp eq i32 %b, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void @bar() nounwind + br label %if.end7 + +if.else: ; preds = %entry + %tobool3 = icmp eq i32 %d, 0 + br i1 %tobool3, label %if.end7, label %if.then4 + +if.then4: ; preds = %if.else + tail call void @bar() nounwind + br label %if.end7 + +if.end7: ; preds = %if.else, %if.then4, %if.then + %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ] + %tmp9 = load i32* %x.0 + ret i32 %tmp9 +; CHECK: @test2 +; CHECK: if.else: +; CHECK: unreachable + +; CHECK-NOT: phi +} + +define i32 @test3(i32* %a, i32 %b, i32* %c, i32 %d) nounwind { +entry: + %tobool = icmp eq i32 %b, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void @bar() nounwind + br label %if.end7 + +if.else: ; preds = %entry + %tobool3 = icmp eq i32 %d, 0 + br i1 %tobool3, label %if.end7, label %if.then4 + +if.then4: ; preds = %if.else + tail call void @bar() nounwind + br label %if.end7 + +if.end7: ; preds = %if.else, %if.then4, %if.then + %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ] + tail call void @bar() nounwind + %tmp9 = load i32* %x.0 + ret i32 %tmp9 +; CHECK: @test3 +; CHECK: if.end7: +; CHECK: phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ] +} From eli.friedman at gmail.com Thu Aug 25 20:37:27 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 25 Aug 2011 18:37:27 -0700 Subject: [llvm-commits] [llvm] r138618 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/phi-undef-loadstore.ll In-Reply-To: <20110826012229.9B7272A6C12C@llvm.org> References: <20110826012229.9B7272A6C12C@llvm.org> Message-ID: On Thu, Aug 25, 2011 at 6:22 PM, Benjamin Kramer wrote: > Author: d0k > Date: Thu Aug 25 20:22:29 2011 > New Revision: 138618 > > URL: http://llvm.org/viewvc/llvm-project?rev=138618&view=rev > Log: > SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. > > In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side. > > This shrinks the size of a Release clang by 16k on x86_64. > > Added: > ? ?llvm/trunk/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll > Modified: > ? ?llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > > Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=138618&r1=138617&r2=138618&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Aug 25 20:22:29 2011 > @@ -2723,6 +2723,72 @@ > ? return false; > ?} > > +/// Check if passing a value to an instruction will cause undefined behavior. > +static bool passingValueIsAlwaysUndefined(Value *V, Instruction *I) { > + ?Constant *C = dyn_cast(V); > + ?if (!C) > + ? ?return false; > + > + ?if (!I->hasOneUse()) // FIXME: There is no reason to limit this to one use. > + ? ?return false; I assume this is a performance optimization? > + ?if (C->isNullValue()) { > + ? ?Instruction *Use = I->use_back(); > + > + ? ?// Now make sure that there are no instructions in between that can alter > + ? ?// control flow (eg. calls) > + ? ?for (BasicBlock::iterator i = ++BasicBlock::iterator(I); &*i != Use; ++i) > + ? ? ?if (i == I->getParent()->end() || > + ? ? ? ? ?!i->isSafeToSpeculativelyExecute()) > + ? ? ? ?return false; I->hasSideEffects() should be sufficient here... you don't care if there's an instruction with undefined behavior before the instruction with undefined behavior. :) > + ? ?// Look through GEPs. A load from a GEP derived from NULL is still undefined > + ? ?if (GetElementPtrInst *GEP = dyn_cast(Use)) > + ? ? ?if (GEP->getPointerOperand() == I) > + ? ? ? ?return passingValueIsAlwaysUndefined(V, GEP); > + > + ? ?// Look through bitcasts. > + ? ?if (BitCastInst *BC = dyn_cast(Use)) > + ? ? ?return passingValueIsAlwaysUndefined(V, BC); > + > + ? ?// load from null is undefined > + ? ?if (isa(Use)) > + ? ? ?return true; > + > + ? ?// store to null is undef > + ? ?if (isa(Use) && Use->getOperand(1) == I) > + ? ? ?return true; Missing address space checks? -Eli From benny.kra at googlemail.com Thu Aug 25 21:25:55 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 02:25:55 -0000 Subject: [llvm-commits] [llvm] r138619 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110826022555.ED89F2A6C12C@llvm.org> Author: d0k Date: Thu Aug 25 21:25:55 2011 New Revision: 138619 URL: http://llvm.org/viewvc/llvm-project?rev=138619&view=rev Log: Address review comments. - Reword comments. - Allow undefined behavior interfering with undefined behavior. - Add address space checks. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=138619&r1=138618&r2=138619&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Aug 25 21:25:55 2011 @@ -2729,7 +2729,7 @@ if (!C) return false; - if (!I->hasOneUse()) // FIXME: There is no reason to limit this to one use. + if (!I->hasOneUse()) // Only look at single-use instructions, for compile time return false; if (C->isNullValue()) { @@ -2738,8 +2738,7 @@ // Now make sure that there are no instructions in between that can alter // control flow (eg. calls) for (BasicBlock::iterator i = ++BasicBlock::iterator(I); &*i != Use; ++i) - if (i == I->getParent()->end() || - !i->isSafeToSpeculativelyExecute()) + if (i == I->getParent()->end() || i->mayHaveSideEffects()) return false; // Look through GEPs. A load from a GEP derived from NULL is still undefined @@ -2751,13 +2750,13 @@ if (BitCastInst *BC = dyn_cast(Use)) return passingValueIsAlwaysUndefined(V, BC); - // load from null is undefined - if (isa(Use)) - return true; - - // store to null is undef - if (isa(Use) && Use->getOperand(1) == I) - return true; + // Load from null is undefined. + if (LoadInst *LI = dyn_cast(Use)) + return LI->getPointerAddressSpace() == 0; + + // Store to null is undefined. + if (StoreInst *SI = dyn_cast(Use)) + return SI->getPointerAddressSpace() == 0 && SI->getPointerOperand() == I; } return false; } From benny.kra at googlemail.com Thu Aug 25 21:27:11 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 25 Aug 2011 19:27:11 -0700 Subject: [llvm-commits] [llvm] r138618 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/phi-undef-loadstore.ll In-Reply-To: References: <20110826012229.9B7272A6C12C@llvm.org> Message-ID: <3FBFD0DA-03CF-4A14-9892-6CC8E076C0E5@googlemail.com> On 25.08.2011, at 18:37, Eli Friedman wrote: > On Thu, Aug 25, 2011 at 6:22 PM, Benjamin Kramer > wrote: >> Author: d0k >> Date: Thu Aug 25 20:22:29 2011 >> New Revision: 138618 [?] >> +/// Check if passing a value to an instruction will cause undefined behavior. >> +static bool passingValueIsAlwaysUndefined(Value *V, Instruction *I) { >> + Constant *C = dyn_cast(V); >> + if (!C) >> + return false; >> + >> + if (!I->hasOneUse()) // FIXME: There is no reason to limit this to one use. >> + return false; > > I assume this is a performance optimization? Yup, I'll reword the comment. >> + if (C->isNullValue()) { >> + Instruction *Use = I->use_back(); >> + >> + // Now make sure that there are no instructions in between that can alter >> + // control flow (eg. calls) >> + for (BasicBlock::iterator i = ++BasicBlock::iterator(I); &*i != Use; ++i) >> + if (i == I->getParent()->end() || >> + !i->isSafeToSpeculativelyExecute()) >> + return false; > > I->hasSideEffects() should be sufficient here... you don't care if > there's an instruction with undefined behavior before the instruction > with undefined behavior. :) OK :) > >> + // Look through GEPs. A load from a GEP derived from NULL is still undefined >> + if (GetElementPtrInst *GEP = dyn_cast(Use)) >> + if (GEP->getPointerOperand() == I) >> + return passingValueIsAlwaysUndefined(V, GEP); >> + >> + // Look through bitcasts. >> + if (BitCastInst *BC = dyn_cast(Use)) >> + return passingValueIsAlwaysUndefined(V, BC); >> + >> + // load from null is undefined >> + if (isa(Use)) >> + return true; >> + >> + // store to null is undef >> + if (isa(Use) && Use->getOperand(1) == I) >> + return true; > > Missing address space checks? I always forget about that :( Thank you for the review! - Ben From eli.friedman at gmail.com Thu Aug 25 21:59:24 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 26 Aug 2011 02:59:24 -0000 Subject: [llvm-commits] [llvm] r138621 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/atomic-load-store.ll Message-ID: <20110826025924.D11BB2A6C12C@llvm.org> Author: efriedma Date: Thu Aug 25 21:59:24 2011 New Revision: 138621 URL: http://llvm.org/viewvc/llvm-project?rev=138621&view=rev Log: Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. Added: llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=138621&r1=138620&r2=138621&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 25 21:59:24 2011 @@ -2976,6 +2976,32 @@ Results.push_back(CallResult.second); break; } + case ISD::ATOMIC_LOAD: { + // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. + SDValue Zero = DAG.getConstant(0, cast(Node)->getMemoryVT()); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, + cast(Node)->getMemoryVT(), + Node->getOperand(0), + Node->getOperand(1), Zero, Zero, + cast(Node)->getMemOperand(), + cast(Node)->getOrdering(), + cast(Node)->getSynchScope()); + Results.push_back(Swap.getValue(0)); + Results.push_back(Swap.getValue(1)); + break; + } + case ISD::ATOMIC_STORE: { + // There is no libcall for atomic store; fake it with ATOMIC_SWAP. + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, + cast(Node)->getMemoryVT(), + Node->getOperand(0), + Node->getOperand(1), Node->getOperand(2), + cast(Node)->getMemOperand(), + cast(Node)->getOrdering(), + cast(Node)->getSynchScope()); + Results.push_back(Swap.getValue(1)); + break; + } // By default, atomic intrinsics are marked Legal and lowered. Targets // which don't support them directly, however, may want libcalls, in which // case they mark them Expand, and we get here. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=138621&r1=138620&r2=138621&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Aug 25 21:59:24 2011 @@ -3289,7 +3289,7 @@ const TargetLowering &TLI) { // Fence, if necessary if (Before) { - if (Order == AcquireRelease) + if (Order == AcquireRelease || Order == SequentiallyConsistent) Order = Release; else if (Order == Acquire || Order == Monotonic) return Chain; @@ -3400,10 +3400,6 @@ SDValue InChain = getRoot(); - if (TLI.getInsertFencesForAtomic()) - InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, - DAG, TLI); - EVT VT = EVT::getEVT(I.getType()); SDValue L = Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138621&r1=138620&r2=138621&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 25 21:59:24 2011 @@ -620,6 +620,8 @@ setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); // Since the libcalls include locking, fold in the fences setShouldFoldAtomicFences(true); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138621&r1=138620&r2=138621&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 25 21:59:24 2011 @@ -4705,6 +4705,29 @@ def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; +// Atomic load/store patterns +def : ARMPat<(atomic_load_8 ldst_so_reg:$src), + (LDRBrs ldst_so_reg:$src)>; +def : ARMPat<(atomic_load_8 addrmode_imm12:$src), + (LDRBi12 addrmode_imm12:$src)>; +def : ARMPat<(atomic_load_16 addrmode3:$src), + (LDRH addrmode3:$src)>; +def : ARMPat<(atomic_load_32 ldst_so_reg:$src), + (LDRrs ldst_so_reg:$src)>; +def : ARMPat<(atomic_load_32 addrmode_imm12:$src), + (LDRi12 addrmode_imm12:$src)>; +def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), + (STRBrs GPR:$val, ldst_so_reg:$ptr)>; +def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), + (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; +def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), + (STRH GPR:$val, addrmode3:$ptr)>; +def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), + (STRrs GPR:$val, ldst_so_reg:$ptr)>; +def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), + (STRi12 GPR:$val, addrmode_imm12:$ptr)>; + + //===----------------------------------------------------------------------===// // Thumb Support // Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138621&r1=138620&r2=138621&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Aug 25 21:59:24 2011 @@ -3474,3 +3474,41 @@ def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, Requires<[HasT2ExtractPack, IsThumb2]>; + +// Atomic load/store patterns +def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), + (t2LDRBi12 t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_load_8 t2addrmode_imm8:$addr), + (t2LDRBi8 t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), + (t2LDRBs t2addrmode_so_reg:$addr)>; +def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), + (t2LDRHi12 t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_load_16 t2addrmode_imm8:$addr), + (t2LDRHi8 t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), + (t2LDRHs t2addrmode_so_reg:$addr)>; +def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), + (t2LDRi12 t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_load_32 t2addrmode_imm8:$addr), + (t2LDRi8 t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), + (t2LDRs t2addrmode_so_reg:$addr)>; +def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), + (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_store_8 t2addrmode_imm8:$addr, GPR:$val), + (t2STRBi8 GPR:$val, t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), + (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; +def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), + (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val), + (t2STRHi8 GPR:$val, t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), + (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; +def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), + (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; +def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val), + (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>; +def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), + (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; Added: llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll?rev=138621&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll (added) +++ llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll Thu Aug 25 21:59:24 2011 @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO +; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE + +define void @test1(i32* %ptr, i32 %val1) { +; ARM: test1 +; ARM: dmb ish +; ARM-NEXT: str +; ARM-NEXT: dmb ish +; THUMBONE: test1 +; THUMBONE: __sync_lock_test_and_set_4 +; THUMBTWO: test1 +; THUMBTWO: dmb ish +; THUMBTWO-NEXT: str +; THUMBTWO-NEXT: dmb ish + store atomic i32 %val1, i32* %ptr seq_cst, align 4 + ret void +} + +define i32 @test2(i32* %ptr) { +; ARM: test2 +; ARM: ldr +; ARM-NEXT: dmb ish +; THUMBONE: test2 +; THUMBONE: __sync_val_compare_and_swap_4 +; THUMBTWO: test2 +; THUMBTWO: ldr +; THUMBTWO-NEXT: dmb ish + %val = load atomic i32* %ptr seq_cst, align 4 + ret i32 %val +} From atrick at apple.com Thu Aug 25 22:06:34 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 26 Aug 2011 03:06:34 -0000 Subject: [llvm-commits] [llvm] r138622 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h lib/Analysis/LoopInfo.cpp Message-ID: <20110826030634.B2B102A6C12C@llvm.org> Author: atrick Date: Thu Aug 25 22:06:34 2011 New Revision: 138622 URL: http://llvm.org/viewvc/llvm-project?rev=138622&view=rev Log: LoopInfo::updateUnloop fix, and verify Block->Loop maps. Fixes an oversight, and adds verification to catch it in the unloop.ll tests. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/lib/Analysis/LoopInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=138622&r1=138621&r2=138622&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Thu Aug 25 22:06:34 2011 @@ -33,6 +33,7 @@ #include "llvm/Pass.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/SmallVector.h" @@ -484,12 +485,13 @@ } /// verifyLoop - Verify loop structure of this loop and all nested loops. - void verifyLoopNest() const { + void verifyLoopNest(DenseSet *Loops) const { + Loops->insert(static_cast(this)); // Verify this loop. verifyLoop(); // Verify the subloops. for (iterator I = begin(), E = end(); I != E; ++I) - (*I)->verifyLoopNest(); + (*I)->verifyLoopNest(Loops); } void print(raw_ostream &OS, unsigned Depth = 0) const { @@ -640,6 +642,7 @@ DenseMap BBMap; std::vector TopLevelLoops; friend class LoopBase; + friend class LoopInfo; void operator=(const LoopInfoBase &); // do not implement LoopInfoBase(const LoopInfo &); // do not implement Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=138622&r1=138621&r2=138622&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LoopInfo.cpp Thu Aug 25 22:06:34 2011 @@ -509,6 +509,8 @@ assert(SubloopParents.count(Subloop) && "DFS failed to visit subloop"); if (SubloopParents[Subloop]) SubloopParents[Subloop]->addChildLoop(Subloop); + else + LI->addTopLevelLoop(Subloop); } } @@ -663,12 +665,21 @@ if (!VerifyLoopInfo) return; + DenseSet Loops; for (iterator I = begin(), E = end(); I != E; ++I) { assert(!(*I)->getParentLoop() && "Top-level loop has a parent!"); - (*I)->verifyLoopNest(); + (*I)->verifyLoopNest(&Loops); } - // TODO: check BBMap consistency. + // Verify that blocks are mapped to valid loops. + // + // FIXME: With an up-to-date DFS (see LoopIterator.h) and DominatorTree, we + // could also verify that the blocks are still in the correct loops. + for (DenseMap::const_iterator I = LI.BBMap.begin(), + E = LI.BBMap.end(); I != E; ++I) { + assert(Loops.count(I->second) && "orphaned loop"); + assert(I->second->contains(I->first) && "orphaned block"); + } } void LoopInfo::getAnalysisUsage(AnalysisUsage &AU) const { From craig.topper at gmail.com Thu Aug 25 23:49:29 2011 From: craig.topper at gmail.com (Craig Topper) Date: Fri, 26 Aug 2011 04:49:29 -0000 Subject: [llvm-commits] [llvm] r138623 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/Disassembler/X86/simple-tests.txt Message-ID: <20110826044929.EDDC82A6C12C@llvm.org> Author: ctopper Date: Thu Aug 25 23:49:29 2011 New Revision: 138623 URL: http://llvm.org/viewvc/llvm-project?rev=138623&view=rev Log: Fix disassembling of VCVTSD2SI Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138623&r1=138622&r2=138623&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Aug 25 23:49:29 2011 @@ -715,14 +715,6 @@ [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>; } -multiclass sse12_cvt_s_np opc, RegisterClass SrcRC, RegisterClass DstRC, - X86MemOperand x86memop, string asm> { - def rr : SI; - def rm : SI; -} - multiclass sse12_cvt_p opc, RegisterClass SrcRC, RegisterClass DstRC, SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, string asm, Domain d> { @@ -844,10 +836,12 @@ // Get rid of this hack or rename the intrinsics, there are several // intructions that only match with the intrinsic form, why create duplicates // to let them be recognized by the assembler? -defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem, +let Pattern = [] in { +defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX; -defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem, +defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W; +} defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si, f128mem, load, "cvtsd2si{l}">, XD; defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64, Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=138623&r1=138622&r2=138623&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Aug 25 23:49:29 2011 @@ -87,3 +87,12 @@ # CHECK: vandps (%rdx), %xmm1, %xmm7 0xc5 0xf0 0x54 0x3a + +# CHECK: vcvtss2sil %xmm0, %eax +0xc5 0xfa 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc5 0xfb 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %rax +0xc4 0xe1 0xfb 0x2d 0xc0 From resistor at mac.com Fri Aug 26 01:19:51 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 26 Aug 2011 06:19:51 -0000 Subject: [llvm-commits] [llvm] r138625 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Message-ID: <20110826061951.8CECD2A6C12C@llvm.org> Author: resistor Date: Fri Aug 26 01:19:51 2011 New Revision: 138625 URL: http://llvm.org/viewvc/llvm-project?rev=138625&view=rev Log: Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138625&r1=138624&r2=138625&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 01:19:51 2011 @@ -376,6 +376,8 @@ unsigned CC; if (!ITBlock.empty()) { CC = ITBlock.back(); + if (CC == 0xF) + CC = ARMCC::AL; ITBlock.pop_back(); } else CC = ARMCC::AL; From chandlerc at google.com Fri Aug 26 01:25:39 2011 From: chandlerc at google.com (Chandler Carruth) Date: Thu, 25 Aug 2011 23:25:39 -0700 Subject: [llvm-commits] [llvm] r138625 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: <20110826061951.8CECD2A6C12C@llvm.org> References: <20110826061951.8CECD2A6C12C@llvm.org> Message-ID: On Thu, Aug 25, 2011 at 11:19 PM, Owen Anderson wrote: > Author: resistor > Date: Fri Aug 26 01:19:51 2011 > New Revision: 138625 > > URL: http://llvm.org/viewvc/llvm-project?rev=138625&view=rev > Log: > Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT > instructions when decoding their successors. > This is the last disassembly crash detected by exhaustive Thumb2 > instruction space. Major thanks to Chandler Carruth for making this kind of > exhaustive testing possible. > Dare I say it... test case? :: ducks :: > > Modified: > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138625&r1=138624&r2=138625&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 > 01:19:51 2011 > @@ -376,6 +376,8 @@ > unsigned CC; > if (!ITBlock.empty()) { > CC = ITBlock.back(); > + if (CC == 0xF) > + CC = ARMCC::AL; > ITBlock.pop_back(); > } else > CC = ARMCC::AL; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110825/f4bc0829/attachment.html From resistor at mac.com Fri Aug 26 01:45:08 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 26 Aug 2011 06:45:08 -0000 Subject: [llvm-commits] [llvm] r138626 - /llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt Message-ID: <20110826064508.3BC5B2A6C12C@llvm.org> Author: resistor Date: Fri Aug 26 01:45:08 2011 New Revision: 138626 URL: http://llvm.org/viewvc/llvm-project?rev=138626&view=rev Log: Add a testcase for r138625. Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt?rev=138626&view=auto ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt (added) +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-thumb.txt Fri Aug 26 01:45:08 2011 @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep {potentially undefined instruction encoding} + +0xff 0xbf 0x6b 0x80 0x00 0x75 From rdivacky at freebsd.org Fri Aug 26 01:53:52 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Fri, 26 Aug 2011 08:53:52 +0200 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: <20110824191434.GA29249@freebsd.org> References: <20110824191434.GA29249@freebsd.org> Message-ID: <20110826065352.GA69924@freebsd.org> ping On Wed, Aug 24, 2011 at 09:14:34PM +0200, Roman Divacky wrote: > Hi, > > PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit > when the call is a vararg one. It should set the bit only with vararg > call that has floating point arguments in registers and unset the > bit otherwise. The attached patch fixes that + test. > > This is normally just an optimization but it's very important in the > kernel where doing floating point stuff is lethal. > > OK to commit? > > thank you, roman > ; RUN: llc < %s | FileCheck %s > ; ModuleID = 'test.c' > target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" > target triple = "powerpc-unknown-freebsd" > > @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 > @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 > > define void @foo() nounwind { > entry: > ; CHECK: crxor 6, 6, 6 > %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) > ; CHECK: creqv 6, 6, 6 > %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) > ret void > } > > declare i32 @printf(i8*, ...) > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Fri Aug 26 03:29:02 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 26 Aug 2011 08:29:02 -0000 Subject: [llvm-commits] [dragonegg] r138629 - /dragonegg/trunk/src/Constants.cpp Message-ID: <20110826082902.F30E52A6C12D@llvm.org> Author: baldrick Date: Fri Aug 26 03:29:02 2011 New Revision: 138629 URL: http://llvm.org/viewvc/llvm-project?rev=138629&view=rev Log: The GCC optimizers can create constant vectors of pointers. Since LLVM only supports vectors of integers, cast the pointers to integers of the same size. Modified: dragonegg/trunk/src/Constants.cpp Modified: dragonegg/trunk/src/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=138629&r1=138628&r2=138629&view=diff ============================================================================== --- dragonegg/trunk/src/Constants.cpp (original) +++ dragonegg/trunk/src/Constants.cpp Fri Aug 26 03:29:02 2011 @@ -937,9 +937,16 @@ // Make the IR more pleasant by returning as a vector if the GCC type was a // vector. However this is only correct if the initial values had the same // type as the vector element type, rather than some random other type. - return ActualEltTy == EltTy && TREE_CODE(init_type) == VECTOR_TYPE ? - ConstantVector::get(Elts) : - ConstantArray::get(ArrayType::get(ActualEltTy, Elts.size()), Elts); + if (TREE_CODE(init_type) == VECTOR_TYPE && ActualEltTy == EltTy) { + // If this is a vector of pointers, convert it to a vector of integers. + if (isa(EltTy)) { + IntegerType *IntPtrTy = getTargetData().getIntPtrType(Context); + for (unsigned i = 0, e = Elts.size(); i != e; ++i) + Elts[i] = Folder.CreatePtrToInt(Elts[i], IntPtrTy); + } + return ConstantVector::get(Elts); + } + return ConstantArray::get(ArrayType::get(ActualEltTy, Elts.size()), Elts); } /// FieldContents - A constant restricted to a range of bits. Any part of the From tobias at grosser.es Fri Aug 26 03:51:30 2011 From: tobias at grosser.es (Tobias Grosser) Date: Fri, 26 Aug 2011 09:51:30 +0100 Subject: [llvm-commits] [PATCH - Pending review] AMDIL Target Triple patch In-Reply-To: References: Message-ID: <4E575E92.40505@grosser.es> On 08/17/2011 10:59 PM, Villmow, Micah wrote: > Here is a patch that is against TOT. Can we get this patch reviewed? It is trivial. Still, I tested it. It applies cleanly, compiles and passes all checks for me. I don't see any reason why it should not be applied. Who can officially review this one? Cheers Tobi P.S.: I reposted this patch, proposed by Micah, separately, as the original thread got a little long and confusing. -------------- next part -------------- A non-text attachment was scrubbed... Name: amdil_triple.diff Type: text/x-diff Size: 1495 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/563a1a73/attachment.bin From nicholas at mxc.ca Fri Aug 26 04:31:55 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 26 Aug 2011 02:31:55 -0700 Subject: [llvm-commits] [PATCH - Pending review] AMDIL Target Triple patch In-Reply-To: <4E575E92.40505@grosser.es> References: <4E575E92.40505@grosser.es> Message-ID: <4E57680B.704@mxc.ca> Tobias Grosser wrote: > On 08/17/2011 10:59 PM, Villmow, Micah wrote: >> Here is a patch that is against TOT. > > Can we get this patch reviewed? Oh, I thought this landed already. It looks like it needs to be updated for the recent addition of "le32", but then Micah, please commit! Nick > > It is trivial. > > Still, I tested it. It applies cleanly, compiles and passes all checks > for me. I don't see any reason why it should not be applied. > > Who can officially review this one? > > Cheers > Tobi > > P.S.: I reposted this patch, proposed by Micah, separately, as the > original thread got a little long and confusing. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From tobias at grosser.es Fri Aug 26 05:00:55 2011 From: tobias at grosser.es (Tobias Grosser) Date: Fri, 26 Aug 2011 11:00:55 +0100 Subject: [llvm-commits] [PATCH - Pending review] AMDIL Target Triple patch In-Reply-To: <4E57680B.704@mxc.ca> References: <4E575E92.40505@grosser.es> <4E57680B.704@mxc.ca> Message-ID: <4E576ED7.105@grosser.es> On 08/26/2011 10:31 AM, Nick Lewycky wrote: > Tobias Grosser wrote: >> On 08/17/2011 10:59 PM, Villmow, Micah wrote: >>> Here is a patch that is against TOT. >> >> Can we get this patch reviewed? > > Oh, I thought this landed already. It looks like it needs to be updated > for the recent addition of "le32", but then Micah, please commit! Thanks Nick, this was fast! Tobi From kalle.raiskila at nokia.com Fri Aug 26 05:14:56 2011 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Fri, 26 Aug 2011 10:14:56 -0000 Subject: [llvm-commits] [llvm] r138630 - in /llvm/trunk/lib/Target/CellSPU: SPUFrameLowering.cpp SPUFrameLowering.h Message-ID: <20110826101456.7BD9B2A6C12C@llvm.org> Author: kraiskil Date: Fri Aug 26 05:14:56 2011 New Revision: 138630 URL: http://llvm.org/viewvc/llvm-project?rev=138630&view=rev Log: Don't insert branch hint lables that are never used. Modified: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h Modified: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp?rev=138630&r1=138629&r2=138630&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp Fri Aug 26 05:14:56 2011 @@ -181,18 +181,6 @@ MachineLocation FPSrc(MachineLocation::VirtualFP); Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); } - } else { - // This is a leaf function -- insert a branch hint iff there are - // sufficient number instructions in the basic block. Note that - // this is just a best guess based on the basic block's size. - if (MBB.size() >= (unsigned) SPUFrameLowering::branchHintPenalty()) { - MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); - dl = MBBI->getDebugLoc(); - - // Insert terminator label - BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)) - .addSym(MMI.getContext().CreateTempSymbol()); - } } } Modified: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h?rev=138630&r1=138629&r2=138630&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h Fri Aug 26 05:14:56 2011 @@ -74,17 +74,6 @@ static int FItoStackOffset(int frame_index) { return frame_index * stackSlotSize(); } - //! Number of instructions required to overcome hint-for-branch latency - /*! - HBR (hint-for-branch) instructions can be inserted when, for example, - we know that a given function is going to be called, such as printf(), - in the control flow graph. HBRs are only inserted if a sufficient number - of instructions occurs between the HBR and the target. Currently, HBRs - take 6 cycles, ergo, the magic number 6. - */ - static int branchHintPenalty() { - return 6; - } }; } From tobias at grosser.es Fri Aug 26 05:34:46 2011 From: tobias at grosser.es (Tobias Grosser) Date: Fri, 26 Aug 2011 11:34:46 +0100 Subject: [llvm-commits] Fix for MachineSink creating zombie defines In-Reply-To: <1312300748.26541.YahooMailNeo@web161517.mail.bf1.yahoo.com> References: <1311960396.91456.YahooMailNeo@web161515.mail.bf1.yahoo.com> <1311966783.69178.YahooMailNeo@web161508.mail.bf1.yahoo.com> <1312041947.68603.YahooMailNeo@web161513.mail.bf1.yahoo.com> <31F9BC7E-82C0-4899-9EF6-58EA2E74800E@2pi.dk> <1312300748.26541.YahooMailNeo@web161517.mail.bf1.yahoo.com> Message-ID: <4E5776C6.9070701@grosser.es> On 08/02/2011 04:59 PM, Jan Sjodin wrote: >> The patch looks good, but please fix the problem with uint64-to-float.ll first. As you correctly note, EFLAGS should not be live-in to the new blocks. We discussed this not so long ago, look for the "MachineSink and EFLAGS" thread from around June 5. >> > This looks a bit involved. I will see when I have time to look into it. Deadlines loom ahead and I do not have the extra time to make the code more optimial. I thought that since the compiler could generate wrong code that was important enough to push this patch to trunk asap. Hi Jan, did you find time to fix uint64-to-float.ll or do you think you will have time in the next couple of days? Cheers Tobi From greened at obbligato.org Fri Aug 26 10:28:38 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 26 Aug 2011 10:28:38 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <9AC8EC0C-70CB-44EE-BF13-B894831661BD@apple.com> (Chris Lattner's message of "Thu, 25 Aug 2011 15:34:08 -0700") References: <9AC8EC0C-70CB-44EE-BF13-B894831661BD@apple.com> Message-ID: Chris Lattner writes: > Looks good with a few changes: > > +static bool isRepeatedByteSequence(const ConstantInt *CI, TargetMachine &TM) { > > This needs a doxygen comment, also please change it to be something like: Ok. > static int isRepeatedByteSequence(const Value *V, TargetMachine &TM) { > > and have it return 0-255 for success and -1 for failure. It should > handle the non-ConstantInt case as well. You could even generalize > this predicate to handle structs and subarrays if you feel ambitious > (but as a follow-on patch). Are you saying the return value should be the value of the repeated byte? > + if (CI->isZero() || > + CI->isAllOnesValue() || > + TM.getTargetData()->getTypeAllocSize(CI->getType()) == 1) > + return true; > + > + unsigned Bytes = TM.getTargetData()->getTypeAllocSize(CI->getType()); > > Please don't call getTypeAllocSize twice, use: Good catch. > + if (CI->isZero() || CI->isAllOnesValue()) > return true; > > + unsigned Bytes = TM.getTargetData()->getTypeAllocSize(CI->getType()); > if (Bytes == 1) return true; > ... > > > + uint64_t Value = CI->getZExtValue(); > > This will abort for int128_t, please check that the bitwidth of CI is <= 64 bits and a multiple of 8 bits. Ah, ok. -Dave From greened at obbligato.org Fri Aug 26 10:29:14 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 26 Aug 2011 10:29:14 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <20110825223850.GB20095@britannica.bec.de> (Joerg Sonnenberger's message of "Fri, 26 Aug 2011 00:38:51 +0200") References: <20110825223850.GB20095@britannica.bec.de> Message-ID: Joerg Sonnenberger writes: > On Thu, Aug 25, 2011 at 03:43:59PM -0500, David Greene wrote: >> >> Emit a repeated sequence of bytes using .zero. This saves an enormous >> amount of asm file space for certain programs. > > Is that only using .zero or actually using .fill as needed? It'll use whatever the target has implemented for EmitFill. With gas it uses .zero. -Dave From clattner at apple.com Fri Aug 26 11:18:22 2011 From: clattner at apple.com (Chris Lattner) Date: Fri, 26 Aug 2011 09:18:22 -0700 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: References: <9AC8EC0C-70CB-44EE-BF13-B894831661BD@apple.com> Message-ID: <87B6CA74-1C75-47D3-8656-75EF34713FB2@apple.com> On Aug 26, 2011, at 8:28 AM, David A. Greene wrote: >> static int isRepeatedByteSequence(const Value *V, TargetMachine &TM) { >> >> and have it return 0-255 for success and -1 for failure. It should >> handle the non-ConstantInt case as well. You could even generalize >> this predicate to handle structs and subarrays if you feel ambitious >> (but as a follow-on patch). > > Are you saying the return value should be the value of the repeated > byte? Yep, that makes it easier to compare for identity on the caller side. Thanks David, -Chris From greened at obbligato.org Fri Aug 26 11:48:36 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 26 Aug 2011 11:48:36 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <87B6CA74-1C75-47D3-8656-75EF34713FB2@apple.com> (Chris Lattner's message of "Fri, 26 Aug 2011 09:18:22 -0700") References: <9AC8EC0C-70CB-44EE-BF13-B894831661BD@apple.com> <87B6CA74-1C75-47D3-8656-75EF34713FB2@apple.com> Message-ID: Chris Lattner writes: >> Are you saying the return value should be the value of the repeated >> byte? > > Yep, that makes it easier to compare for identity on the caller side. Right. I've reworked it that way. Testing now and will re-send once it's verified. -Dave From benny.kra at googlemail.com Fri Aug 26 12:00:30 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 17:00:30 -0000 Subject: [llvm-commits] [llvm] r138634 - in /llvm/trunk/test/TableGen: CStyleComment.td Include.td nested-comment.td Message-ID: <20110826170030.8982D2A6C12D@llvm.org> Author: d0k Date: Fri Aug 26 12:00:30 2011 New Revision: 138634 URL: http://llvm.org/viewvc/llvm-project?rev=138634&view=rev Log: We don't care if TableGen leaks memory. Modified: llvm/trunk/test/TableGen/CStyleComment.td llvm/trunk/test/TableGen/Include.td llvm/trunk/test/TableGen/nested-comment.td Modified: llvm/trunk/test/TableGen/CStyleComment.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/CStyleComment.td?rev=138634&r1=138633&r2=138634&view=diff ============================================================================== --- llvm/trunk/test/TableGen/CStyleComment.td (original) +++ llvm/trunk/test/TableGen/CStyleComment.td Fri Aug 26 12:00:30 2011 @@ -1,6 +1,7 @@ // Test that multiline, nested, comments work correctly. // // RUN: tblgen < %s +// XFAIL: vg_leak /* Foo bar Modified: llvm/trunk/test/TableGen/Include.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/Include.td?rev=138634&r1=138633&r2=138634&view=diff ============================================================================== --- llvm/trunk/test/TableGen/Include.td (original) +++ llvm/trunk/test/TableGen/Include.td Fri Aug 26 12:00:30 2011 @@ -1,4 +1,5 @@ // RUN: tblgen -I %p %s +// XFAIL: vg_leak def BeforeInclude; include "Include.inc" Modified: llvm/trunk/test/TableGen/nested-comment.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/nested-comment.td?rev=138634&r1=138633&r2=138634&view=diff ============================================================================== --- llvm/trunk/test/TableGen/nested-comment.td (original) +++ llvm/trunk/test/TableGen/nested-comment.td Fri Aug 26 12:00:30 2011 @@ -1,4 +1,5 @@ // RUN: tblgen < %s +// XFAIL: vg_leak /* foo From aaron at aaronballman.com Fri Aug 26 12:24:43 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Fri, 26 Aug 2011 12:24:43 -0500 Subject: [llvm-commits] [PATCH] Removing unused declarations from FileSystem.h In-Reply-To: References: Message-ID: Ping? On Sat, Aug 20, 2011 at 4:34 PM, Aaron Ballman wrote: > While working on some Win32 changes in PathV2, I noticed that there > were a number of declarations in FileSystem.h which have no definition > on any platform, and are not used anywhere in the source base. ?This > patch removes those declarations, so no one accidentally attempts to > make use of them. > > I confirmed the patch against Visual Studio 2010 and MinGW. ?However, > I'd feel more comfortable if someone is also able to verify in XCode. > > Thanks! > > ~Aaron > From echristo at apple.com Fri Aug 26 12:33:19 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 26 Aug 2011 10:33:19 -0700 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: <20110826065352.GA69924@freebsd.org> References: <20110824191434.GA29249@freebsd.org> <20110826065352.GA69924@freebsd.org> Message-ID: On Aug 25, 2011, at 11:53 PM, Roman Divacky wrote: > ping > > On Wed, Aug 24, 2011 at 09:14:34PM +0200, Roman Divacky wrote: >> Hi, >> >> PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit >> when the call is a vararg one. It should set the bit only with vararg >> call that has floating point arguments in registers and unset the >> bit otherwise. The attached patch fixes that + test. >> >> This is normally just an optimization but it's very important in the >> kernel where doing floating point stuff is lethal. >> >> OK to commit? >> >> thank you, roman > > >> ; RUN: llc < %s | FileCheck %s >> ; ModuleID = 'test.c' >> target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" >> target triple = "powerpc-unknown-freebsd" >> >> @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 >> @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 >> >> define void @foo() nounwind { >> entry: >> ; CHECK: crxor 6, 6, 6 >> %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) >> ; CHECK: creqv 6, 6, 6 >> %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) >> ret void >> } >> >> declare i32 @printf(i8*, ...) Patch? -eric From dag at cray.com Fri Aug 26 12:48:49 2011 From: dag at cray.com (David Greene) Date: Fri, 26 Aug 2011 12:48:49 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output Message-ID: Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. --- Here's an updated version of the patch. -Dave lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 61 +++++++++++++++++++++++++++++++-- 1 files changed, 58 insertions(+), 3 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Compress-Repeated-Byte-Output.patch Type: text/x-patch Size: 2704 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/53d0fec3/attachment.bin From resistor at mac.com Fri Aug 26 13:09:22 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 26 Aug 2011 18:09:22 -0000 Subject: [llvm-commits] [llvm] r138635 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/basic-thumb-instructions.s test/MC/Disassembler/ARM/basic-arm-instructions.txt test/MC/Disassembler/ARM/thumb1.txt Message-ID: <20110826180922.C18CD2A6C12D@llvm.org> Author: resistor Date: Fri Aug 26 13:09:22 2011 New Revision: 138635 URL: http://llvm.org/viewvc/llvm-project?rev=138635&view=rev Log: Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/basic-thumb-instructions.s llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 26 13:09:22 2011 @@ -1583,12 +1583,15 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> { bits<4> Rd; - bits<12> label; + bits<14> label; let Inst{27-25} = 0b001; + let Inst{24} = 0; + let Inst{23-22} = label{13-12}; + let Inst{21} = 0; let Inst{20} = 0; let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; - let Inst{11-0} = label; + let Inst{11-0} = label{11-0}; } def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 13:09:22 2011 @@ -2310,12 +2310,15 @@ CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); - if (Inst.getOpcode() == ARM::tADR) - Inst.addOperand(MCOperand::CreateReg(ARM::PC)); - else if (Inst.getOpcode() == ARM::tADDrSPi) - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - else - return Fail; + switch(Inst.getOpcode()) { + case ARM::tADR: + break; + case ARM::tADDrSPi: + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + break; + default: + return Fail; + } Inst.addOperand(MCOperand::CreateImm(imm)); return S; Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Aug 26 13:09:22 2011 @@ -570,9 +570,18 @@ uint32_t ARMMCCodeEmitter:: getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, - Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, + Fixups); + int32_t offset = MO.getImm(); + uint32_t Val = 0x2000; + if (offset < 0) { + Val = 0x1000; + offset *= -1; + } + Val |= offset; + return Val; } /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label @@ -580,9 +589,11 @@ uint32_t ARMMCCodeEmitter:: getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, - Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, + Fixups); + return MO.getImm(); } /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label @@ -590,9 +601,11 @@ uint32_t ARMMCCodeEmitter:: getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, - Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, + Fixups); + return MO.getImm(); } /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Aug 26 13:09:22 2011 @@ -129,6 +129,8 @@ adr r2, Lback adr r3, Lforward Lforward: + adr r2, #3 + adr r2, #-3 @ CHECK: Lback: @ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A] @@ -136,6 +138,8 @@ @ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A] @ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12 @ CHECK: Lforward: +@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2] +@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2] @------------------------------------------------------------------------------ Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 26 13:09:22 2011 @@ -74,10 +74,11 @@ @ ADR @------------------------------------------------------------------------------ adr r2, _baz + adr r2, #3 @ CHECK: adr r2, _baz @ encoding: [A,0xa2] @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10 - +@ CHECK: adr r2, #3 @ encoding: [0x03,0xa2] @------------------------------------------------------------------------------ @ ASR (immediate) Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Fri Aug 26 13:09:22 2011 @@ -164,6 +164,14 @@ 0x77 0x69 0x86 0xe0 0x65 0x40 0x84 0xe0 +#------------------------------------------------------------------------------ +# ADR +#------------------------------------------------------------------------------ +# CHECK: add r2, pc, #3 +# CHECK: sub r2, pc, #3 + +0x03 0x20 0x8f 0xe2 +0x03 0x20 0x4f 0xe2 #------------------------------------------------------------------------------ # AND Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138635&r1=138634&r2=138635&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Fri Aug 26 13:09:22 2011 @@ -52,6 +52,12 @@ 0x6a 0x44 #------------------------------------------------------------------------------ +# ADR +#------------------------------------------------------------------------------ +# CHECK: adr r2, #3 +0x03 0xa2 + +#------------------------------------------------------------------------------ # ASR (immediate) #------------------------------------------------------------------------------ # CHECK: asrs r2, r3, #32 From benny.kra at googlemail.com Fri Aug 26 13:21:36 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 18:21:36 -0000 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Message-ID: <20110826182136.9890A2A6C12D@llvm.org> Author: d0k Date: Fri Aug 26 13:21:36 2011 New Revision: 138636 URL: http://llvm.org/viewvc/llvm-project?rev=138636&view=rev Log: ARMDisassembler: Always return a size, even when disassembling fails. This should fix PR10772. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138636&r1=138635&r2=138636&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 13:21:36 2011 @@ -262,8 +262,10 @@ uint8_t bytes[4]; // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { + Size = 0; return Fail; + } // Encoded as a small-endian 32-bit word in the stream. uint32_t insn = (bytes[3] << 24) | @@ -329,6 +331,7 @@ MI.clear(); + Size = 0; return Fail; } @@ -442,8 +445,10 @@ uint8_t bytes[4]; // We want to read exactly 2 bytes of data. - if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { + Size = 0; return Fail; + } uint16_t insn16 = (bytes[1] << 8) | bytes[0]; DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); @@ -492,8 +497,10 @@ } // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { + Size = 0; return Fail; + } uint32_t insn32 = (bytes[3] << 8) | (bytes[2] << 0) | @@ -568,6 +575,7 @@ } } + Size = 0; return Fail; } From grosbach at apple.com Fri Aug 26 13:25:31 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 26 Aug 2011 11:25:31 -0700 Subject: [llvm-commits] [llvm] r138635 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/basic-thumb-instructions.s test/MC/Disassembler/ARM/basic-arm-instructions.txt test/MC/Disassembler/ARM/thumb1.txt In-Reply-To: <20110826180922.C18CD2A6C12D@llvm.org> References: <20110826180922.C18CD2A6C12D@llvm.org> Message-ID: <8868BA12-8C05-4E5A-AB9C-F1E518E6CB3B@apple.com> Sweet. Thanks, Owen. Nittiness inline. On Aug 26, 2011, at 11:09 AM, Owen Anderson wrote: > Author: resistor > Date: Fri Aug 26 13:09:22 2011 > New Revision: 138635 > > URL: http://llvm.org/viewvc/llvm-project?rev=138635&view=rev > Log: > Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp > llvm/trunk/test/MC/ARM/basic-arm-instructions.s > llvm/trunk/test/MC/ARM/basic-thumb-instructions.s > llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt > llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 26 13:09:22 2011 > @@ -1583,12 +1583,15 @@ > def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), > MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> { > bits<4> Rd; > - bits<12> label; > + bits<14> label; > let Inst{27-25} = 0b001; > + let Inst{24} = 0; > + let Inst{23-22} = label{13-12}; > + let Inst{21} = 0; > let Inst{20} = 0; > let Inst{19-16} = 0b1111; > let Inst{15-12} = Rd; > - let Inst{11-0} = label; > + let Inst{11-0} = label{11-0}; > } > def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), > 4, IIC_iALUi, []>; > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 13:09:22 2011 > @@ -2310,12 +2310,15 @@ > > CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); > > - if (Inst.getOpcode() == ARM::tADR) > - Inst.addOperand(MCOperand::CreateReg(ARM::PC)); > - else if (Inst.getOpcode() == ARM::tADDrSPi) > - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > - else > - return Fail; > + switch(Inst.getOpcode()) { > + case ARM::tADR: > + break; Not adding an explicit ARM::PC operand is intentional? Assuming so, a comment to the effect that we don't need an operand for tADR is probably in order. > + case ARM::tADDrSPi: > + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > + break; > + default: > + return Fail; > + } > I don't know that it's in the actual coding standards (I couldn't find it, anyway), but the code I'm used to seeing always puts the "default" case at the top of the switch() statement. > Inst.addOperand(MCOperand::CreateImm(imm)); > return S; > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Aug 26 13:09:22 2011 > @@ -570,9 +570,18 @@ > uint32_t ARMMCCodeEmitter:: > getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, > SmallVectorImpl &Fixups) const { > - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); > - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, > - Fixups); > + const MCOperand MO = MI.getOperand(OpIdx); > + if (MO.isExpr()) > + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, > + Fixups); > + int32_t offset = MO.getImm(); > + uint32_t Val = 0x2000; > + if (offset < 0) { > + Val = 0x1000; > + offset *= -1; > + } > + Val |= offset; > + return Val; > } > > /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label > @@ -580,9 +589,11 @@ > uint32_t ARMMCCodeEmitter:: > getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, > SmallVectorImpl &Fixups) const { > - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); > - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, > - Fixups); > + const MCOperand MO = MI.getOperand(OpIdx); > + if (MO.isExpr()) > + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, > + Fixups); > + return MO.getImm(); > } > > /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label > @@ -590,9 +601,11 @@ > uint32_t ARMMCCodeEmitter:: > getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, > SmallVectorImpl &Fixups) const { > - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); > - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, > - Fixups); > + const MCOperand MO = MI.getOperand(OpIdx); > + if (MO.isExpr()) > + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, > + Fixups); > + return MO.getImm(); > } > > /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' > > Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) > +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Aug 26 13:09:22 2011 > @@ -129,6 +129,8 @@ > adr r2, Lback > adr r3, Lforward > Lforward: > + adr r2, #3 > + adr r2, #-3 > > @ CHECK: Lback: > @ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A] > @@ -136,6 +138,8 @@ > @ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A] > @ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12 > @ CHECK: Lforward: > +@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2] > +@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2] > > > @------------------------------------------------------------------------------ > > Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) > +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 26 13:09:22 2011 > @@ -74,10 +74,11 @@ > @ ADR > @------------------------------------------------------------------------------ > adr r2, _baz > + adr r2, #3 > > @ CHECK: adr r2, _baz @ encoding: [A,0xa2] > @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10 > - > +@ CHECK: adr r2, #3 @ encoding: [0x03,0xa2] > Accidentally deleted a line of whitespace here, looks like. > @------------------------------------------------------------------------------ > @ ASR (immediate) > > Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original) > +++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Fri Aug 26 13:09:22 2011 > @@ -164,6 +164,14 @@ > 0x77 0x69 0x86 0xe0 > 0x65 0x40 0x84 0xe0 > > +#------------------------------------------------------------------------------ > +# ADR > +#------------------------------------------------------------------------------ > +# CHECK: add r2, pc, #3 > +# CHECK: sub r2, pc, #3 > + > +0x03 0x20 0x8f 0xe2 > +0x03 0x20 0x4f 0xe2 > > #------------------------------------------------------------------------------ > # AND > > Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138635&r1=138634&r2=138635&view=diff > ============================================================================== > --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original) > +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Fri Aug 26 13:09:22 2011 > @@ -52,6 +52,12 @@ > 0x6a 0x44 > > #------------------------------------------------------------------------------ > +# ADR > +#------------------------------------------------------------------------------ > +# CHECK: adr r2, #3 > +0x03 0xa2 > + > +#------------------------------------------------------------------------------ > # ASR (immediate) > #------------------------------------------------------------------------------ > # CHECK: asrs r2, r3, #32 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Fri Aug 26 13:26:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 26 Aug 2011 11:26:00 -0700 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: <20110826182136.9890A2A6C12D@llvm.org> References: <20110826182136.9890A2A6C12D@llvm.org> Message-ID: Testcase? On Aug 26, 2011, at 11:21 AM, Benjamin Kramer wrote: > Author: d0k > Date: Fri Aug 26 13:21:36 2011 > New Revision: 138636 > > URL: http://llvm.org/viewvc/llvm-project?rev=138636&view=rev > Log: > ARMDisassembler: Always return a size, even when disassembling fails. > > This should fix PR10772. > > Modified: > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138636&r1=138635&r2=138636&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 13:21:36 2011 > @@ -262,8 +262,10 @@ > uint8_t bytes[4]; > > // We want to read exactly 4 bytes of data. > - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { > + Size = 0; > return Fail; > + } > > // Encoded as a small-endian 32-bit word in the stream. > uint32_t insn = (bytes[3] << 24) | > @@ -329,6 +331,7 @@ > > MI.clear(); > > + Size = 0; > return Fail; > } > > @@ -442,8 +445,10 @@ > uint8_t bytes[4]; > > // We want to read exactly 2 bytes of data. > - if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) > + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { > + Size = 0; > return Fail; > + } > > uint16_t insn16 = (bytes[1] << 8) | bytes[0]; > DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); > @@ -492,8 +497,10 @@ > } > > // We want to read exactly 4 bytes of data. > - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { > + Size = 0; > return Fail; > + } > > uint32_t insn32 = (bytes[3] << 8) | > (bytes[2] << 0) | > @@ -568,6 +575,7 @@ > } > } > > + Size = 0; > return Fail; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Fri Aug 26 13:30:18 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 11:30:18 -0700 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: References: <20110826182136.9890A2A6C12D@llvm.org> Message-ID: On Fri, Aug 26, 2011 at 11:26, Jim Grosbach wrote: > Testcase? It's not directly testable from llvm-mc, but the valgrind buildbot complains about uninitialized variables without this patch. From grosbach at apple.com Fri Aug 26 13:37:55 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 26 Aug 2011 11:37:55 -0700 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: References: <20110826182136.9890A2A6C12D@llvm.org> Message-ID: <23B353D8-EDBA-437A-8521-C6F4D9DB4B61@apple.com> On Aug 26, 2011, at 11:30 AM, Benjamin Kramer wrote: > On Fri, Aug 26, 2011 at 11:26, Jim Grosbach wrote: >> Testcase? > > It's not directly testable from llvm-mc, but the valgrind buildbot > complains about uninitialized variables without this patch. That's odd. Along what execution path? The MC dissassembler and the Enhanced disassembler both early exit when failure is returned and never reference the Size value. At least according to my reading the code, anyway. What am I missing? -Jim From benny.kra at googlemail.com Fri Aug 26 13:45:16 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 26 Aug 2011 11:45:16 -0700 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: <23B353D8-EDBA-437A-8521-C6F4D9DB4B61@apple.com> References: <20110826182136.9890A2A6C12D@llvm.org> <23B353D8-EDBA-437A-8521-C6F4D9DB4B61@apple.com> Message-ID: On Fri, Aug 26, 2011 at 11:37, Jim Grosbach wrote: > > On Aug 26, 2011, at 11:30 AM, Benjamin Kramer wrote: > >> On Fri, Aug 26, 2011 at 11:26, Jim Grosbach wrote: >>> Testcase? >> >> It's not directly testable from llvm-mc, but the valgrind buildbot >> complains about uninitialized variables without this patch. > > That's odd. Along what execution path? The MC dissassembler and the Enhanced disassembler both early exit when failure is returned and never reference the Size value. At least according to my reading the code, anyway. What am I missing? The relevant code in llvm-mc's Disassembler.cpp:62 looks like this: > uint64_t Size; > uint64_t Index; > > for (Index = 0; Index < Bytes.size(); Index += Size) { > MCInst Inst; > > MCDisassembler::DecodeStatus S; > S = DisAsm.getInstruction(Inst, Size, memoryObject, Index, > /*REMOVE*/ nulls()); > switch (S) { > case MCDisassembler::Fail: > SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), > "invalid instruction encoding", "warning"); > if (Size == 0) > Size = 1; // skip illegible bytes > break; Size is passed by reference to DisAsm.getInstruction. When getInstruction doesn't set Size in the first iteration then Index becomes an undefined value in the next iteration. Some of our tests contain only invalid bytes and valgrind will complain. From grosbach at apple.com Fri Aug 26 13:48:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 26 Aug 2011 11:48:45 -0700 Subject: [llvm-commits] [llvm] r138636 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp In-Reply-To: References: <20110826182136.9890A2A6C12D@llvm.org> <23B353D8-EDBA-437A-8521-C6F4D9DB4B61@apple.com> Message-ID: <286B8A13-862F-438C-BD59-B3CEDA5BA9B5@apple.com> On Aug 26, 2011, at 11:45 AM, Benjamin Kramer wrote: > On Fri, Aug 26, 2011 at 11:37, Jim Grosbach wrote: >> >> On Aug 26, 2011, at 11:30 AM, Benjamin Kramer wrote: >> >>> On Fri, Aug 26, 2011 at 11:26, Jim Grosbach wrote: >>>> Testcase? >>> >>> It's not directly testable from llvm-mc, but the valgrind buildbot >>> complains about uninitialized variables without this patch. >> >> That's odd. Along what execution path? The MC dissassembler and the Enhanced disassembler both early exit when failure is returned and never reference the Size value. At least according to my reading the code, anyway. What am I missing? > > The relevant code in llvm-mc's Disassembler.cpp:62 looks like this: Ah, OK. That's why I didn't see it. llvm-mc is calling it directly, I was looking in the C bindings. > >> uint64_t Size; >> uint64_t Index; >> >> for (Index = 0; Index < Bytes.size(); Index += Size) { >> MCInst Inst; >> >> MCDisassembler::DecodeStatus S; >> S = DisAsm.getInstruction(Inst, Size, memoryObject, Index, >> /*REMOVE*/ nulls()); >> switch (S) { >> case MCDisassembler::Fail: >> SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), >> "invalid instruction encoding", "warning"); >> if (Size == 0) >> Size = 1; // skip illegible bytes >> break; > > Size is passed by reference to DisAsm.getInstruction. When > getInstruction doesn't set Size in the first iteration then Index > becomes an undefined value in the next iteration. Some of our tests > contain only invalid bytes and valgrind will complain. Makes sense. Thanks! -Jim From grosbach at apple.com Fri Aug 26 13:56:02 2011 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 26 Aug 2011 11:56:02 -0700 Subject: [llvm-commits] [llvm] r137830 - in /llvm/trunk: include/llvm/MC/ lib/Target/ARM/Disassembler/ lib/Target/MBlaze/Disassembler/ lib/Target/X86/Disassembler/ test/MC/Disassembler/ARM/ tools/llvm-mc/ utils/TableGen/ In-Reply-To: <20110817174416.558E12A6C12C@llvm.org> References: <20110817174416.558E12A6C12C@llvm.org> Message-ID: <848FF71B-5F72-4D02-8EA4-12BFDA137518@apple.com> Sorry for the late comments. I missed this catching these bits the first time around (saw the patch, just missed this aspect). On Aug 17, 2011, at 10:44 AM, Owen Anderson wrote: > Author: resistor > Date: Wed Aug 17 12:44:15 2011 > New Revision: 137830 > > URL: http://llvm.org/viewvc/llvm-project?rev=137830&view=rev > Log: > Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. > Patch by James Molloy. > > Modified: > llvm/trunk/include/llvm/MC/MCDisassembler.h > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h > llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp > llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h > llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp > llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h > llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt > llvm/trunk/tools/llvm-mc/Disassembler.cpp > llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp > llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp > llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h > > Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCDisassembler.h (original) > +++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Aug 17 12:44:15 2011 > @@ -25,6 +25,34 @@ > /// and provides an array of assembly instructions. > class MCDisassembler { > public: > + /// Ternary decode status. Most backends will just use Fail and > + /// Success, however some have a concept of an instruction with > + /// understandable semantics but which is architecturally > + /// incorrect. An example of this is ARM UNPREDICTABLE instructions > + /// which are disassemblable but cause undefined behaviour. > + /// > + /// Because it makes sense to disassemble these instructions, there > + /// is a "soft fail" failure mode that indicates the MCInst& is > + /// valid but architecturally incorrect. > + /// > + /// The enum numbers are deliberately chosen such that reduction > + /// from Success->SoftFail ->Fail can be done with a simple > + /// bitwise-AND: > + /// > + /// LEFT & TOP = | Success Unpredictable Fail > + /// --------------+----------------------------------- > + /// Success | Success Unpredictable Fail > + /// Unpredictable | Unpredictable Unpredictable Fail > + /// Fail | Fail Fail Fail > + /// > + /// An easy way of encoding this is as 0b11, 0b01, 0b00 for > + /// Success, SoftFail, Fail respectively. > + enum DecodeStatus { > + Fail = 0, > + SoftFail = 1, > + Success = 3 > + }; > + > /// Constructor - Performs initial setup for the disassembler. > MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {} > > @@ -41,8 +69,11 @@ > /// @param address - The address, in the memory space of region, of the first > /// byte of the instruction. > /// @param vStream - The stream to print warnings and diagnostic messages on. > - /// @return - True if the instruction is valid; false otherwise. > - virtual bool getInstruction(MCInst& instr, > + /// @return - MCDisassembler::Success if the instruction is valid, > + /// MCDisassembler::SoftFail if the instruction was > + /// disassemblable but invalid, > + /// MCDisassembler::Fail if the instruction was invalid. > + virtual DecodeStatus getInstruction(MCInst& instr, > uint64_t& size, > const MemoryObject ®ion, > uint64_t address, > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 12:44:15 2011 > @@ -24,188 +24,201 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/raw_ostream.h" > > +// Pull DecodeStatus and its enum values into the global namespace. > +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; > +#define Success llvm::MCDisassembler::Success > +#define Unpredictable llvm::MCDisassembler::SoftFail > +#define Fail llvm::MCDisassembler::Fail > + Please don't do this sort of thing (#defines to get around scoping). Reference the names explicitly, including the scoping operators, instead. > +// Helper macro to perform setwise reduction of the current running status > +// and another status, and return if the new status is Fail. > +#define CHECK(S,X) do { \ > + S = (DecodeStatus) ((int)S & (X)); \ It's better to use the enum values directly rather than casting integers like this. The code shouldn't know what the actual values of the enums are. > + if (S == Fail) return Fail; \ > + } while(0) > + Having an early exit buried in a macro obfuscates the code. The way the code previously did this is better. Please change this back or refactor differently. > // Forward declare these because the autogenerated code will reference them. > // Definitions are further down. > -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder); > > -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > > -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > > -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, > +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, > unsigned Insn, > uint64_t Adddress, > const void *Decoder); > -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > > > -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, > +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder); > -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder); > > #include "ARMGenDisassemblerTables.inc" > @@ -230,15 +243,14 @@ > return instInfoARM; > } > > - > -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > - const MemoryObject &Region, > - uint64_t Address,raw_ostream &os) const { > +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > + const MemoryObject &Region, > + uint64_t Address,raw_ostream &os) const { > uint8_t bytes[4]; > > // We want to read exactly 4 bytes of data. > if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > - return false; > + return Fail; > > // Encoded as a small-endian 32-bit word in the stream. > uint32_t insn = (bytes[3] << 24) | > @@ -247,10 +259,10 @@ > (bytes[0] << 0); > > // Calling the auto-generated decoder function. > - bool result = decodeARMInstruction32(MI, insn, Address, this); > - if (result) { > + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); > + if (result != Fail) { > Size = 4; > - return true; > + return result; > } > > // Instructions that are shared between ARM and Thumb modes. > @@ -258,53 +270,53 @@ > // fact that we fail to encode a few instructions properly for Thumb. > MI.clear(); > result = decodeCommonInstruction32(MI, insn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > - return true; > + return result; > } > > // VFP and NEON instructions, similarly, are shared between ARM > // and Thumb modes. > MI.clear(); > result = decodeVFPInstruction32(MI, insn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > - return true; > + return result; > } > > MI.clear(); > result = decodeNEONDataInstruction32(MI, insn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > // Add a fake predicate operand, because we share these instruction > // definitions with Thumb2 where these instructions are predicable. > - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > - return true; > + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > + return result; > } > > MI.clear(); > result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > // Add a fake predicate operand, because we share these instruction > // definitions with Thumb2 where these instructions are predicable. > - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > - return true; > + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > + return result; > } > > MI.clear(); > result = decodeNEONDupInstruction32(MI, insn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > // Add a fake predicate operand, because we share these instruction > // definitions with Thumb2 where these instructions are predicable. > - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > - return true; > + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > + return result; > } > > MI.clear(); > > - return false; > + return Fail; > } > > namespace llvm { > @@ -403,22 +415,21 @@ > } > } > > - > -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > - const MemoryObject &Region, > - uint64_t Address,raw_ostream &os) const { > +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > + const MemoryObject &Region, > + uint64_t Address,raw_ostream &os) const { > uint8_t bytes[4]; > > // We want to read exactly 2 bytes of data. > if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) > - return false; > + return Fail; > > uint16_t insn16 = (bytes[1] << 8) | bytes[0]; > - bool result = decodeThumbInstruction16(MI, insn16, Address, this); > - if (result) { > + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); > + if (result != Fail) { > Size = 2; > AddThumbPredicate(MI); > - return true; > + return result; > } > > MI.clear(); > @@ -428,12 +439,12 @@ > bool InITBlock = !ITBlock.empty(); > AddThumbPredicate(MI); > AddThumb1SBit(MI, InITBlock); > - return true; > + return result; > } > > MI.clear(); > result = decodeThumb2Instruction16(MI, insn16, Address, this); > - if (result) { > + if (result != Fail) { > Size = 2; > AddThumbPredicate(MI); > > @@ -456,12 +467,12 @@ > ITBlock.push_back(firstcond); > } > > - return true; > + return result; > } > > // We want to read exactly 4 bytes of data. > if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > - return false; > + return Fail; > > uint32_t insn32 = (bytes[3] << 8) | > (bytes[2] << 0) | > @@ -469,44 +480,44 @@ > (bytes[0] << 16); > MI.clear(); > result = decodeThumbInstruction32(MI, insn32, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > bool InITBlock = ITBlock.size(); > AddThumbPredicate(MI); > AddThumb1SBit(MI, InITBlock); > - return true; > + return result; > } > > MI.clear(); > result = decodeThumb2Instruction32(MI, insn32, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > AddThumbPredicate(MI); > - return true; > + return result; > } > > MI.clear(); > result = decodeCommonInstruction32(MI, insn32, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > AddThumbPredicate(MI); > - return true; > + return result; > } > > MI.clear(); > result = decodeVFPInstruction32(MI, insn32, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > UpdateThumbVFPPredicate(MI); > - return true; > + return result; > } > > MI.clear(); > result = decodeNEONDupInstruction32(MI, insn32, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > AddThumbPredicate(MI); > - return true; > + return result; > } > > if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { > @@ -515,10 +526,10 @@ > NEONLdStInsn &= 0xF0FFFFFF; > NEONLdStInsn |= 0x04000000; > result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > AddThumbPredicate(MI); > - return true; > + return result; > } > } > > @@ -529,14 +540,14 @@ > NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 > NEONDataInsn |= 0x12000000; // Set bits 28 and 25 > result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); > - if (result) { > + if (result != Fail) { > Size = 4; > AddThumbPredicate(MI); > - return true; > + return result; > } > } > > - return false; > + return Fail; > } > > > @@ -554,30 +565,30 @@ > ARM::R12, ARM::SP, ARM::LR, ARM::PC > }; > > -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 15) > - return false; > + return Fail; > > unsigned Register = GPRDecoderTable[RegNo]; > Inst.addOperand(MCOperand::CreateReg(Register)); > - return true; > + return Success; > } > > -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > - if (RegNo == 15) return false; > + if (RegNo == 15) return Fail; > return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > } > > -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 7) > - return false; > + return Fail; > return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > } > > -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > unsigned Register = 0; > switch (RegNo) { > @@ -600,16 +611,16 @@ > Register = ARM::R12; > break; > default: > - return false; > + return Fail; > } > > Inst.addOperand(MCOperand::CreateReg(Register)); > - return true; > + return Success; > } > > -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > - if (RegNo == 13 || RegNo == 15) return false; > + if (RegNo == 13 || RegNo == 15) return Fail; > return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > } > > @@ -624,14 +635,14 @@ > ARM::S28, ARM::S29, ARM::S30, ARM::S31 > }; > > -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 31) > - return false; > + return Fail; > > unsigned Register = SPRDecoderTable[RegNo]; > Inst.addOperand(MCOperand::CreateReg(Register)); > - return true; > + return Success; > } > > static const unsigned DPRDecoderTable[] = { > @@ -645,27 +656,27 @@ > ARM::D28, ARM::D29, ARM::D30, ARM::D31 > }; > > -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 31) > - return false; > + return Fail; > > unsigned Register = DPRDecoderTable[RegNo]; > Inst.addOperand(MCOperand::CreateReg(Register)); > - return true; > + return Success; > } > > -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 7) > - return false; > + return Fail; > return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); > } > > -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 15) > - return false; > + return Fail; > return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); > } > > @@ -677,65 +688,66 @@ > }; > > > -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > uint64_t Address, const void *Decoder) { > if (RegNo > 31) > - return false; > + return Fail; > RegNo >>= 1; > > unsigned Register = QPRDecoderTable[RegNo]; > Inst.addOperand(MCOperand::CreateReg(Register)); > - return true; > + return Success; > } > > -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > - if (Val == 0xF) return false; > + if (Val == 0xF) return Fail; > // AL predicate is not allowed on Thumb1 branches. > if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) > - return false; > + return Fail; > Inst.addOperand(MCOperand::CreateImm(Val)); > if (Val == ARMCC::AL) { > Inst.addOperand(MCOperand::CreateReg(0)); > } else > Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); > - return true; > + return Success; > } > > -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > if (Val) > Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); > else > Inst.addOperand(MCOperand::CreateReg(0)); > - return true; > + return Success; > } > > -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > uint32_t imm = Val & 0xFF; > uint32_t rot = (Val & 0xF00) >> 7; > uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); > Inst.addOperand(MCOperand::CreateImm(rot_imm)); > - return true; > + return Success; > } > > -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Val <<= 2; > Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); > - return true; > + return Success; > } > > -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > > unsigned Rm = fieldFromInstruction32(Val, 0, 4); > unsigned type = fieldFromInstruction32(Val, 5, 2); > unsigned imm = fieldFromInstruction32(Val, 7, 5); > > // Register-immediate > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > > ARM_AM::ShiftOpc Shift = ARM_AM::lsl; > switch (type) { > @@ -759,19 +771,20 @@ > unsigned Op = Shift | (imm << 3); > Inst.addOperand(MCOperand::CreateImm(Op)); > > - return true; > + return S; > } > > -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > > unsigned Rm = fieldFromInstruction32(Val, 0, 4); > unsigned type = fieldFromInstruction32(Val, 5, 2); > unsigned Rs = fieldFromInstruction32(Val, 8, 4); > > // Register-register > - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; > - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); > > ARM_AM::ShiftOpc Shift = ARM_AM::lsl; > switch (type) { > @@ -791,49 +804,55 @@ > > Inst.addOperand(MCOperand::CreateImm(Shift)); > > - return true; > + return S; > } > > -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > // Empty register lists are not allowed. > - if (CountPopulation_32(Val) == 0) return false; > + if (CountPopulation_32(Val) == 0) return Fail; > for (unsigned i = 0; i < 16; ++i) { > if (Val & (1 << i)) { > - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); > } > } > > - return true; > + return S; > } > > -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Vd = fieldFromInstruction32(Val, 8, 4); > unsigned regs = Val & 0xFF; > > - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; > + CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); > for (unsigned i = 0; i < (regs - 1); ++i) { > - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; > + CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Vd = fieldFromInstruction32(Val, 8, 4); > unsigned regs = (Val & 0xFF) / 2; > > - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); > for (unsigned i = 0; i < (regs - 1); ++i) { > - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > // This operand encodes a mask of contiguous zeros between a specified MSB > // and LSB. To decode it, we create the mask of all bits MSB-and-lower, > @@ -845,11 +864,13 @@ > uint32_t msb_mask = (1 << (msb+1)) - 1; > uint32_t lsb_mask = (1 << lsb) - 1; > Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); > - return true; > + return Success; > } > > -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > unsigned CRd = fieldFromInstruction32(Insn, 12, 4); > unsigned coproc = fieldFromInstruction32(Insn, 8, 4); > @@ -875,7 +896,7 @@ > case ARM::STCL_POST: > case ARM::STCL_OPTION: > if (coproc == 0xA || coproc == 0xB) > - return false; > + return Fail; > break; > default: > break; > @@ -883,7 +904,7 @@ > > Inst.addOperand(MCOperand::CreateImm(coproc)); > Inst.addOperand(MCOperand::CreateImm(CRd)); > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > switch (Inst.getOpcode()) { > case ARM::LDC_OPTION: > case ARM::LDCL_OPTION: > @@ -952,17 +973,19 @@ > case ARM::STCL_PRE: > case ARM::STCL_POST: > case ARM::STCL_OPTION: > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > break; > default: > break; > } > > - return true; > + return S; > } > > -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > @@ -982,13 +1005,13 @@ > case ARM::STRT_POST_IMM: > case ARM::STRBT_POST_REG: > case ARM::STRBT_POST_IMM: > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > break; > default: > break; > } > > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > > // On loads, the writeback operand comes after Rt. > switch (Inst.getOpcode()) { > @@ -1002,14 +1025,13 @@ > case ARM::LDRBT_POST_IMM: > case ARM::LDRT_POST_REG: > case ARM::LDRT_POST_IMM: > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > break; > default: > break; > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > > ARM_AM::AddrOpc Op = ARM_AM::add; > if (!fieldFromInstruction32(Insn, 23, 1)) > @@ -1022,10 +1044,10 @@ > else if (!P && writeback) > idx_mode = ARMII::IndexModePost; > > - if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE > + if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE > > if (reg) { > - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > ARM_AM::ShiftOpc Opc = ARM_AM::lsl; > switch( fieldFromInstruction32(Insn, 5, 2)) { > case 0: > @@ -1041,7 +1063,7 @@ > Opc = ARM_AM::ror; > break; > default: > - return false; > + return Fail; > } > unsigned amt = fieldFromInstruction32(Insn, 7, 5); > unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); > @@ -1053,13 +1075,15 @@ > Inst.addOperand(MCOperand::CreateImm(tmp)); > } > > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 13, 4); > unsigned Rm = fieldFromInstruction32(Val, 0, 4); > unsigned type = fieldFromInstruction32(Val, 5, 2); > @@ -1082,8 +1106,8 @@ > break; > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > unsigned shift; > if (U) > shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); > @@ -1091,11 +1115,13 @@ > shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); > Inst.addOperand(MCOperand::CreateImm(shift)); > > - return true; > + return S; > } > > -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > @@ -1116,7 +1142,7 @@ > case ARM::LDRD: > case ARM::LDRD_PRE: > case ARM::LDRD_POST: > - if (Rt & 0x1) return false; > + if (Rt & 0x1) return Fail; > break; > default: > break; > @@ -1136,16 +1162,14 @@ > case ARM::STRH: > case ARM::STRH_PRE: > case ARM::STRH_POST: > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > break; > default: > break; > } > } > > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > switch (Inst.getOpcode()) { > case ARM::STRD: > case ARM::STRD_PRE: > @@ -1153,8 +1177,7 @@ > case ARM::LDRD: > case ARM::LDRD_PRE: > case ARM::LDRD_POST: > - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > break; > default: > break; > @@ -1177,33 +1200,32 @@ > case ARM::LDRSB_POST: > case ARM::LDRHTr: > case ARM::LDRSBTr: > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > break; > default: > break; > } > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > > if (type) { > Inst.addOperand(MCOperand::CreateReg(0)); > Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); > } else { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(U)); > } > > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned mode = fieldFromInstruction32(Insn, 23, 2); > > @@ -1223,14 +1245,16 @@ > } > > Inst.addOperand(MCOperand::CreateImm(mode)); > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, > +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, > unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > unsigned reglist = fieldFromInstruction32(Insn, 0, 16); > @@ -1265,16 +1289,15 @@ > return DecodeRFEInstruction(Inst, Insn, Address, Decoder); > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied > - !DecodePredicateOperand(Inst, pred, Address, Decoder) || > - !DecodeRegListOperand(Inst, reglist, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > + CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > unsigned imod = fieldFromInstruction32(Insn, 18, 2); > unsigned M = fieldFromInstruction32(Insn, 17, 1); > @@ -1282,30 +1305,32 @@ > unsigned mode = fieldFromInstruction32(Insn, 0, 5); > > // imod == '01' --> UNPREDICTABLE > - if (imod == 1) return false; > + if (imod == 1) return Fail; > > if (M && mode && imod && iflags) { > Inst.setOpcode(ARM::CPS3p); > Inst.addOperand(MCOperand::CreateImm(imod)); > Inst.addOperand(MCOperand::CreateImm(iflags)); > Inst.addOperand(MCOperand::CreateImm(mode)); > - return true; > + return Success; > } else if (!mode && !M) { > Inst.setOpcode(ARM::CPS2p); > Inst.addOperand(MCOperand::CreateImm(imod)); > Inst.addOperand(MCOperand::CreateImm(iflags)); > - return true; > + return Success; > } else if (!imod && !iflags && M) { > Inst.setOpcode(ARM::CPS1p); > Inst.addOperand(MCOperand::CreateImm(mode)); > - return true; > + return Success; > } > > - return false; > + return Fail; > } > > -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 16, 4); > unsigned Rn = fieldFromInstruction32(Insn, 0, 4); > unsigned Rm = fieldFromInstruction32(Insn, 8, 4); > @@ -1315,57 +1340,60 @@ > if (pred == 0xF) > return DecodeCPSInstruction(Inst, Insn, Address, Decoder); > > - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || > - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || > - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || > - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); > > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned add = fieldFromInstruction32(Val, 12, 1); > unsigned imm = fieldFromInstruction32(Val, 0, 12); > unsigned Rn = fieldFromInstruction32(Val, 13, 4); > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > > if (!add) imm *= -1; > if (imm == 0 && !add) imm = INT32_MIN; > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return S; > } > > -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 9, 4); > unsigned U = fieldFromInstruction32(Val, 8, 1); > unsigned imm = fieldFromInstruction32(Val, 0, 8); > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > > if (U) > Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); > else > Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); > > - return true; > + return S; > } > > -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); > } > > -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; > > @@ -1373,39 +1401,42 @@ > Inst.setOpcode(ARM::BLXi); > imm |= fieldFromInstruction32(Insn, 24, 1) << 1; > Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); > - return true; > + return S; > } > > Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > > -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(64 - Val)); > - return true; > + return Success; > } > > -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rm = fieldFromInstruction32(Val, 0, 4); > unsigned align = fieldFromInstruction32(Val, 4, 2); > > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > if (!align) > Inst.addOperand(MCOperand::CreateImm(0)); > else > Inst.addOperand(MCOperand::CreateImm(4 << align)); > > - return true; > + return S; > } > > -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned wb = fieldFromInstruction32(Insn, 16, 4); > @@ -1414,7 +1445,7 @@ > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > > // First output register > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > > // Second output register > switch (Inst.getOpcode()) { > @@ -1466,7 +1497,7 @@ > case ARM::VLD4d8_UPD: > case ARM::VLD4d16_UPD: > case ARM::VLD4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); > break; > case ARM::VLD2b8: > case ARM::VLD2b16: > @@ -1486,7 +1517,7 @@ > case ARM::VLD4q8_UPD: > case ARM::VLD4q16_UPD: > case ARM::VLD4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); > default: > break; > } > @@ -1527,7 +1558,7 @@ > case ARM::VLD4d8_UPD: > case ARM::VLD4d16_UPD: > case ARM::VLD4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); > break; > case ARM::VLD3q8: > case ARM::VLD3q16: > @@ -1541,7 +1572,7 @@ > case ARM::VLD4q8_UPD: > case ARM::VLD4q16_UPD: > case ARM::VLD4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); > break; > default: > break; > @@ -1569,7 +1600,7 @@ > case ARM::VLD4d8_UPD: > case ARM::VLD4d16_UPD: > case ARM::VLD4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); > break; > case ARM::VLD4q8: > case ARM::VLD4q16: > @@ -1577,7 +1608,7 @@ > case ARM::VLD4q8_UPD: > case ARM::VLD4q16_UPD: > case ARM::VLD4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); > break; > default: > break; > @@ -1622,28 +1653,29 @@ > case ARM::VLD4q8_UPD: > case ARM::VLD4q16_UPD: > case ARM::VLD4q32_UPD: > - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); > break; > default: > break; > } > > // AddrMode6 Base (register+alignment) > - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); > > // AddrMode6 Offset (register) > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned wb = fieldFromInstruction32(Insn, 16, 4); > @@ -1690,25 +1722,24 @@ > case ARM::VST4q8_UPD: > case ARM::VST4q16_UPD: > case ARM::VST4q32_UPD: > - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); > break; > default: > break; > } > > // AddrMode6 Base (register+alignment) > - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); > > // AddrMode6 Offset (register) > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > // First input register > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > > // Second input register > switch (Inst.getOpcode()) { > @@ -1760,7 +1791,7 @@ > case ARM::VST4d8_UPD: > case ARM::VST4d16_UPD: > case ARM::VST4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); > break; > case ARM::VST2b8: > case ARM::VST2b16: > @@ -1780,7 +1811,7 @@ > case ARM::VST4q8_UPD: > case ARM::VST4q16_UPD: > case ARM::VST4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); > break; > default: > break; > @@ -1822,7 +1853,7 @@ > case ARM::VST4d8_UPD: > case ARM::VST4d16_UPD: > case ARM::VST4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); > break; > case ARM::VST3q8: > case ARM::VST3q16: > @@ -1836,7 +1867,7 @@ > case ARM::VST4q8_UPD: > case ARM::VST4q16_UPD: > case ARM::VST4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); > break; > default: > break; > @@ -1864,7 +1895,7 @@ > case ARM::VST4d8_UPD: > case ARM::VST4d16_UPD: > case ARM::VST4d32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); > break; > case ARM::VST4q8: > case ARM::VST4q16: > @@ -1872,17 +1903,19 @@ > case ARM::VST4q8_UPD: > case ARM::VST4q16_UPD: > case ARM::VST4q32_UPD: > - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); > break; > default: > break; > } > > - return true; > + return S; > } > > -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > @@ -1893,28 +1926,30 @@ > > align *= (1 << size); > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > if (regs == 2) { > - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); > } > if (Rm == 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > @@ -1924,54 +1959,57 @@ > unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; > align *= 2*size; > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); > if (Rm == 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || > - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || > - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) > - return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); > if (Rm == 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(0)); > > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > @@ -1993,29 +2031,30 @@ > } > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || > - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || > - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || > - !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) > - return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); > if (Rm == 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > > if (Rm == 0xD) > Inst.addOperand(MCOperand::CreateReg(0)); > else if (Rm != 0xF) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned imm = fieldFromInstruction32(Insn, 0, 4); > @@ -2026,9 +2065,9 @@ > unsigned Q = fieldFromInstruction32(Insn, 6, 1); > > if (Q) { > - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > } else { > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > } > > Inst.addOperand(MCOperand::CreateImm(imm)); > @@ -2038,62 +2077,66 @@ > case ARM::VORRiv2i32: > case ARM::VBICiv4i16: > case ARM::VBICiv2i32: > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > break; > case ARM::VORRiv8i16: > case ARM::VORRiv4i32: > case ARM::VBICiv8i16: > case ARM::VBICiv4i32: > - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > break; > default: > break; > } > > - return true; > + return S; > } > > -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; > unsigned size = fieldFromInstruction32(Insn, 18, 2); > > - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(8 << size)); > > - return true; > + return S; > } > > -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(8 - Val)); > - return true; > + return Success; > } > > -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(16 - Val)); > - return true; > + return Success; > } > > -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(32 - Val)); > - return true; > + return Success; > } > > -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(64 - Val)); > - return true; > + return Success; > } > > -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > @@ -2103,21 +2146,21 @@ > unsigned op = fieldFromInstruction32(Insn, 6, 1); > unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > if (op) { > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback > } > > for (unsigned i = 0; i < length; ++i) { > - if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > // The immediate needs to be a fully instantiated float. However, the > // auto-generated decoder is only able to fill in some of the bits > @@ -2139,102 +2182,110 @@ > fp_conv.integer |= (~b & 0x1) << 30; > > Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); > - return true; > + return Success; > } > > -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned dst = fieldFromInstruction16(Insn, 8, 3); > unsigned imm = fieldFromInstruction16(Insn, 0, 8); > > - if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; > + CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); > > if (Inst.getOpcode() == ARM::tADR) > Inst.addOperand(MCOperand::CreateReg(ARM::PC)); > else if (Inst.getOpcode() == ARM::tADDrSPi) > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > else > - return false; > + return Fail; > > Inst.addOperand(MCOperand::CreateImm(imm)); > - return true; > + return S; > } > > -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); > - return true; > + return Success; > } > > -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); > - return true; > + return Success; > } > > -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); > - return true; > + return Success; > } > > -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 0, 3); > unsigned Rm = fieldFromInstruction32(Val, 3, 3); > > - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || > - !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 0, 3); > unsigned imm = fieldFromInstruction32(Val, 3, 5); > > - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return S; > } > > -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(Val << 2)); > > - return true; > + return Success; > } > > -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > Inst.addOperand(MCOperand::CreateImm(Val << 2)); > > - return true; > + return Success; > } > > -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 6, 4); > unsigned Rm = fieldFromInstruction32(Val, 2, 4); > unsigned imm = fieldFromInstruction32(Val, 0, 2); > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > - !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return S; > } > > -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > if (Inst.getOpcode() != ARM::t2PLDs) { > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > } > > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > @@ -2257,57 +2308,60 @@ > Inst.addOperand(MCOperand::CreateReg(ARM::PC)); > break; > default: > - return false; > + return Fail; > } > > int imm = fieldFromInstruction32(Insn, 0, 12); > if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return S; > } > > unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); > addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; > addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; > - DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); > + CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > int imm = Val & 0xFF; > if (!(Val & 0x100)) imm *= -1; > Inst.addOperand(MCOperand::CreateImm(imm << 2)); > > - return true; > + return Success; > } > > -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 9, 4); > unsigned imm = fieldFromInstruction32(Val, 0, 9); > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > - !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > int imm = Val & 0xFF; > if (!(Val & 0x100)) imm *= -1; > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return Success; > } > > > -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 9, 4); > unsigned imm = fieldFromInstruction32(Val, 0, 9); > > @@ -2324,27 +2378,28 @@ > break; > } > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > - !DecodeT2Imm8(Inst, imm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); > > - return true; > + return S; > } > > > -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Val, 13, 4); > unsigned imm = fieldFromInstruction32(Val, 0, 12); > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return S; > } > > > -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder) { > unsigned imm = fieldFromInstruction16(Insn, 0, 7); > > @@ -2352,30 +2407,32 @@ > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > Inst.addOperand(MCOperand::CreateImm(imm)); > > - return true; > + return Success; > } > > -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > if (Inst.getOpcode() == ARM::tADDrSP) { > unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); > Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; > > - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); > } else if (Inst.getOpcode() == ARM::tADDspr) { > unsigned Rm = fieldFromInstruction16(Insn, 3, 4); > > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - return true; > + return S; > } > > -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > uint64_t Address, const void *Decoder) { > unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; > unsigned flags = fieldFromInstruction16(Insn, 0, 3); > @@ -2383,52 +2440,55 @@ > Inst.addOperand(MCOperand::CreateImm(imod)); > Inst.addOperand(MCOperand::CreateImm(flags)); > > - return true; > + return Success; > } > > -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned add = fieldFromInstruction32(Insn, 4, 1); > > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; > Inst.addOperand(MCOperand::CreateImm(add)); > > - return true; > + return S; > } > > -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); > - return true; > + return Success; > } > > -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > if (Val == 0xA || Val == 0xB) > - return false; > + return Fail; > > Inst.addOperand(MCOperand::CreateImm(Val)); > - return true; > + return Success; > } > > -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > if (Val == 0) > Inst.addOperand(MCOperand::CreateImm(32)); > else > Inst.addOperand(MCOperand::CreateImm(Val)); > - return true; > + return Success; > } > > -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned pred = fieldFromInstruction32(Insn, 22, 4); > if (pred == 0xE || pred == 0xF) { > unsigned opc = fieldFromInstruction32(Insn, 4, 2); > switch (opc) { > default: > - return false; > + return Fail; > case 0: > Inst.setOpcode(ARM::t2DSB); > break; > @@ -2437,7 +2497,7 @@ > break; > case 2: > Inst.setOpcode(ARM::t2ISB); > - return true; > + return Success; > } > > unsigned imm = fieldFromInstruction32(Insn, 0, 4); > @@ -2450,17 +2510,16 @@ > brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; > brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; > > - if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || > - !DecodePredicateOperand(Inst, pred, Address, Decoder)) > - return false; > + CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > // Decode a shifted immediate operand. These basically consist > // of an 8-bit value, and a 4-bit directive that specifies either > // a splat operation or a rotation. > -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > unsigned ctrl = fieldFromInstruction32(Val, 10, 2); > if (ctrl == 0) { > @@ -2488,26 +2547,26 @@ > Inst.addOperand(MCOperand::CreateImm(imm)); > } > > - return true; > + return Success; > } > > -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder){ > Inst.addOperand(MCOperand::CreateImm(Val << 1)); > - return true; > + return Success; > } > > -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder){ > Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); > - return true; > + return Success; > } > > -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > switch (Val) { > default: > - return false; > + return Fail; > case 0xF: // SY > case 0xE: // ST > case 0xB: // ISH > @@ -2520,55 +2579,61 @@ > } > > Inst.addOperand(MCOperand::CreateImm(Val)); > - return true; > + return Success; > } > > -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, > +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, > uint64_t Address, const void *Decoder) { > - if (!Val) return false; > + if (!Val) return Fail; > Inst.addOperand(MCOperand::CreateImm(Val)); > - return true; > + return Success; > } > > -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > > - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; > + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; > > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > > -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > unsigned Rt = fieldFromInstruction32(Insn, 0, 4); > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > > - if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); > > - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; > - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; > + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; > + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; > > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > unsigned imm = fieldFromInstruction32(Insn, 0, 12); > @@ -2576,18 +2641,20 @@ > imm |= fieldFromInstruction32(Insn, 23, 1) << 12; > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > > - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE > + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > - if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > + CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > unsigned imm = fieldFromInstruction32(Insn, 0, 12); > @@ -2595,18 +2662,20 @@ > imm |= fieldFromInstruction32(Insn, 23, 1) << 12; > unsigned pred = fieldFromInstruction32(Insn, 28, 4); > > - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE > + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE > > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; > - if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; > - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > + CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); > + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > > - return true; > + return S; > } > > -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2617,47 +2686,47 @@ > unsigned index = 0; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 5, 3); > break; > case 1: > if (fieldFromInstruction32(Insn, 5, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 6, 2); > if (fieldFromInstruction32(Insn, 4, 1)) > align = 2; > break; > case 2: > if (fieldFromInstruction32(Insn, 6, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 4, 2) != 0) > align = 4; > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2668,47 +2737,47 @@ > unsigned index = 0; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 5, 3); > break; > case 1: > if (fieldFromInstruction32(Insn, 5, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 6, 2); > if (fieldFromInstruction32(Insn, 4, 1)) > align = 2; > break; > case 2: > if (fieldFromInstruction32(Insn, 6, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 4, 2) != 0) > align = 4; > } > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > > -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2720,7 +2789,7 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > index = fieldFromInstruction32(Insn, 5, 3); > if (fieldFromInstruction32(Insn, 4, 1)) > @@ -2735,7 +2804,7 @@ > break; > case 2: > if (fieldFromInstruction32(Insn, 5, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 4, 1) != 0) > align = 8; > @@ -2744,28 +2813,28 @@ > break; > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2777,7 +2846,7 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > index = fieldFromInstruction32(Insn, 5, 3); > if (fieldFromInstruction32(Insn, 4, 1)) > @@ -2792,7 +2861,7 @@ > break; > case 2: > if (fieldFromInstruction32(Insn, 5, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 4, 1) != 0) > align = 8; > @@ -2802,26 +2871,26 @@ > } > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > > -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2833,53 +2902,53 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 5, 3); > break; > case 1: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 6, 2); > if (fieldFromInstruction32(Insn, 5, 1)) > inc = 2; > break; > case 2: > if (fieldFromInstruction32(Insn, 4, 2)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 6, 1)) > inc = 2; > break; > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2891,22 +2960,22 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 5, 3); > break; > case 1: > if (fieldFromInstruction32(Insn, 4, 1)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 6, 2); > if (fieldFromInstruction32(Insn, 5, 1)) > inc = 2; > break; > case 2: > if (fieldFromInstruction32(Insn, 4, 2)) > - return false; // UNDEFINED > + return Fail; // UNDEFINED > index = fieldFromInstruction32(Insn, 7, 1); > if (fieldFromInstruction32(Insn, 6, 1)) > inc = 2; > @@ -2914,27 +2983,27 @@ > } > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > > -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -2946,7 +3015,7 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > align = 4; > @@ -2968,33 +3037,33 @@ > break; > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > uint64_t Address, const void *Decoder) { > + DecodeStatus S = Success; > + > unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > @@ -3006,7 +3075,7 @@ > unsigned inc = 1; > switch (size) { > default: > - return false; > + return Fail; > case 0: > if (fieldFromInstruction32(Insn, 4, 1)) > align = 4; > @@ -3029,22 +3098,20 @@ > } > > if (Rm != 0xF) { // Writeback > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > } > - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(align)); > if (Rm != 0xF && Rm != 0xD) { > - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > - return false; > + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > } > > - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; > - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > Inst.addOperand(MCOperand::CreateImm(index)); > > - return true; > + return S; > } > > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h Wed Aug 17 12:44:15 2011 > @@ -40,11 +40,11 @@ > } > > /// getInstruction - See MCDisassembler. > - bool getInstruction(MCInst &instr, > - uint64_t &size, > - const MemoryObject ®ion, > - uint64_t address, > - raw_ostream &vStream) const; > + DecodeStatus getInstruction(MCInst &instr, > + uint64_t &size, > + const MemoryObject ®ion, > + uint64_t address, > + raw_ostream &vStream) const; > > /// getEDInfo - See MCDisassembler. > EDInstInfo *getEDInfo() const; > @@ -64,11 +64,11 @@ > } > > /// getInstruction - See MCDisassembler. > - bool getInstruction(MCInst &instr, > - uint64_t &size, > - const MemoryObject ®ion, > - uint64_t address, > - raw_ostream &vStream) const; > + DecodeStatus getInstruction(MCInst &instr, > + uint64_t &size, > + const MemoryObject ®ion, > + uint64_t address, > + raw_ostream &vStream) const; > > /// getEDInfo - See MCDisassembler. > EDInstInfo *getEDInfo() const; > > Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Aug 17 12:44:15 2011 > @@ -493,7 +493,7 @@ > // Public interface for the disassembler > // > > -bool MBlazeDisassembler::getInstruction(MCInst &instr, > +MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr, > uint64_t &size, > const MemoryObject ®ion, > uint64_t address, > @@ -508,7 +508,7 @@ > > // We want to read exactly 4 bytes of data. > if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read < 4) > - return false; > + return Fail; > > // Encoded as a big-endian 32-bit word in the stream. > insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0); > @@ -517,7 +517,7 @@ > // that it is a valid instruction. > unsigned opcode = getOPCODE(insn); > if (opcode == UNSUPPORTED) > - return false; > + return Fail; > > instr.setOpcode(opcode); > > @@ -529,11 +529,11 @@ > uint64_t tsFlags = MBlazeInsts[opcode].TSFlags; > switch ((tsFlags & MBlazeII::FormMask)) { > default: > - return false; > + return Fail; > > case MBlazeII::FRRRR: > if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RB)); > instr.addOperand(MCOperand::CreateReg(RA)); > @@ -541,7 +541,7 @@ > > case MBlazeII::FRRR: > if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RA)); > instr.addOperand(MCOperand::CreateReg(RB)); > @@ -550,23 +550,23 @@ > case MBlazeII::FRI: > switch (opcode) { > default: > - return false; > + return Fail; > case MBlaze::MFS: > if (RD == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); > break; > case MBlaze::MTS: > if (RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); > instr.addOperand(MCOperand::CreateReg(RA)); > break; > case MBlaze::MSRSET: > case MBlaze::MSRCLR: > if (RD == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateImm(insn&0x7FFF)); > break; > @@ -575,7 +575,7 @@ > > case MBlazeII::FRRI: > if (RD == UNSUPPORTED || RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RA)); > switch (opcode) { > @@ -592,35 +592,35 @@ > > case MBlazeII::FCRR: > if (RA == UNSUPPORTED || RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RA)); > instr.addOperand(MCOperand::CreateReg(RB)); > break; > > case MBlazeII::FCRI: > if (RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RA)); > instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > break; > > case MBlazeII::FRCR: > if (RD == UNSUPPORTED || RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RB)); > break; > > case MBlazeII::FRCI: > if (RD == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > break; > > case MBlazeII::FCCR: > if (RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RB)); > break; > > @@ -630,7 +630,7 @@ > > case MBlazeII::FRRCI: > if (RD == UNSUPPORTED || RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RA)); > instr.addOperand(MCOperand::CreateImm(getSHT(insn))); > @@ -638,35 +638,35 @@ > > case MBlazeII::FRRC: > if (RD == UNSUPPORTED || RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RA)); > break; > > case MBlazeII::FRCX: > if (RD == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateImm(getFSL(insn))); > break; > > case MBlazeII::FRCS: > if (RD == UNSUPPORTED || RS == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateReg(RS)); > break; > > case MBlazeII::FCRCS: > if (RS == UNSUPPORTED || RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RS)); > instr.addOperand(MCOperand::CreateReg(RA)); > break; > > case MBlazeII::FCRCX: > if (RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RA)); > instr.addOperand(MCOperand::CreateImm(getFSL(insn))); > break; > @@ -677,13 +677,13 @@ > > case MBlazeII::FCR: > if (RB == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RB)); > break; > > case MBlazeII::FRIR: > if (RD == UNSUPPORTED || RA == UNSUPPORTED) > - return false; > + return Fail; > instr.addOperand(MCOperand::CreateReg(RD)); > instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > instr.addOperand(MCOperand::CreateReg(RA)); > @@ -693,7 +693,7 @@ > // We always consume 4 bytes of data on success > size = 4; > > - return true; > + return Success; > } > > static MCDisassembler *createMBlazeDisassembler(const Target &T) { > > Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original) > +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Aug 17 12:44:15 2011 > @@ -40,7 +40,7 @@ > } > > /// getInstruction - See MCDisassembler. > - bool getInstruction(MCInst &instr, > + MCDisassembler::DecodeStatus getInstruction(MCInst &instr, > uint64_t &size, > const MemoryObject ®ion, > uint64_t address, > > Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) > +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug 17 12:44:15 2011 > @@ -106,11 +106,12 @@ > // Public interface for the disassembler > // > > -bool X86GenericDisassembler::getInstruction(MCInst &instr, > - uint64_t &size, > - const MemoryObject ®ion, > - uint64_t address, > - raw_ostream &vStream) const { > +MCDisassembler::DecodeStatus > +X86GenericDisassembler::getInstruction(MCInst &instr, > + uint64_t &size, > + const MemoryObject ®ion, > + uint64_t address, > + raw_ostream &vStream) const { > InternalInstruction internalInstr; > > int ret = decodeInstruction(&internalInstr, > @@ -123,11 +124,11 @@ > > if (ret) { > size = internalInstr.readerCursor - address; > - return false; > + return Fail; > } > else { > size = internalInstr.length; > - return !translateInstruction(instr, internalInstr); > + return (!translateInstruction(instr, internalInstr)) ? Success : Fail; > } > } > > > Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original) > +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Aug 17 12:44:15 2011 > @@ -112,11 +112,11 @@ > ~X86GenericDisassembler(); > > /// getInstruction - See MCDisassembler. > - bool getInstruction(MCInst &instr, > - uint64_t &size, > - const MemoryObject ®ion, > - uint64_t address, > - raw_ostream &vStream) const; > + DecodeStatus getInstruction(MCInst &instr, > + uint64_t &size, > + const MemoryObject ®ion, > + uint64_t address, > + raw_ostream &vStream) const; > > /// getEDInfo - See MCDisassembler. > EDInstInfo *getEDInfo() const; > > Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original) > +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Wed Aug 17 12:44:15 2011 > @@ -1,4 +1,4 @@ > -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} > +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} > > # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) > # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 > > Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original) > +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 17 12:44:15 2011 > @@ -65,15 +65,26 @@ > for (Index = 0; Index < Bytes.size(); Index += Size) { > MCInst Inst; > > - if (DisAsm.getInstruction(Inst, Size, memoryObject, Index, > - /*REMOVE*/ nulls())) { > - Printer.printInst(&Inst, Out); > - Out << "\n"; > - } else { > + MCDisassembler::DecodeStatus S; > + S = DisAsm.getInstruction(Inst, Size, memoryObject, Index, > + /*REMOVE*/ nulls()); > + switch (S) { Changing this to a switch statement is good. The C bindings in MCDisasembler.cpp and EDDisassembler.cpp need to be changed, too, though. They're still doing "!Disasm->getInstruction()" type constructs. > + case MCDisassembler::Fail: > SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), > "invalid instruction encoding", "warning"); > if (Size == 0) > Size = 1; // skip illegible bytes > + break; > + > + case MCDisassembler::SoftFail: > + SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), > + "potentially undefined instruction encoding", "warning"); > + // Fall through > + > + case MCDisassembler::Success: > + Printer.printInst(&Inst, Out); > + Out << "\n"; > + break; > } > } > > > Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Aug 17 12:44:15 2011 > @@ -128,5 +128,15 @@ > return; > } > > + // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. > + if (Target.getName() == "ARM" || > + Target.getName() == "Thumb") { > + FixedLenDecoderEmitter(Records, > + "CHECK(S, ", ");", > + "S", "Fail", > + "DecodeStatus S = Success;\n(void)S;").run(OS); > + return; > + } > + > FixedLenDecoderEmitter(Records).run(OS); > } > > Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Aug 17 12:44:15 2011 > @@ -238,19 +238,24 @@ > // Width of instructions > unsigned BitWidth; > > + // Parent emitter > + const FixedLenDecoderEmitter *Emitter; > + > public: > FilterChooser(const FilterChooser &FC) : > AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes), > Operands(FC.Operands), Filters(FC.Filters), > FilterBitValues(FC.FilterBitValues), Parent(FC.Parent), > - BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { } > + BestIndex(FC.BestIndex), BitWidth(FC.BitWidth), > + Emitter(FC.Emitter) { } > > FilterChooser(const std::vector &Insts, > const std::vector &IDs, > std::map > &Ops, > - unsigned BW) : > + unsigned BW, > + const FixedLenDecoderEmitter *E) : > AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), > - Parent(NULL), BestIndex(-1), BitWidth(BW) { > + Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) { > for (unsigned i = 0; i < BitWidth; ++i) > FilterBitValues.push_back(BIT_UNFILTERED); > > @@ -264,7 +269,8 @@ > FilterChooser &parent) : > AllInstructions(Insts), Opcodes(IDs), Operands(Ops), > Filters(), FilterBitValues(ParentFilterBitValues), > - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) { > + Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth), > + Emitter(parent.Emitter) { > doFilter(); > } > > @@ -563,17 +569,17 @@ > void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation, > std::string Namespace) { > o.indent(Indentation) << > - "static bool decode" << Namespace << "Instruction" << BitWidth > + "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction" << BitWidth > << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, " > << "const void *Decoder) {\n"; > - o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n"; > + o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n" << Emitter->Locals << "\n"; > > ++Indentation; ++Indentation; > // Emits code to decode the instructions. > emit(o, Indentation); > > o << '\n'; > - o.indent(Indentation) << "return false;\n"; > + o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n"; > --Indentation; --Indentation; > > o.indent(Indentation) << "}\n"; > @@ -744,8 +750,8 @@ > } > > if (Decoder != "") > - o.indent(Indentation) << " if (!" << Decoder > - << "(MI, tmp, Address, Decoder)) return false;\n"; > + o.indent(Indentation) << " " << Emitter->GuardPrefix << Decoder > + << "(MI, tmp, Address, Decoder)" << Emitter->GuardPostfix << "\n"; > else > o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n"; > > @@ -776,15 +782,15 @@ > I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { > // If a custom instruction decoder was specified, use that. > if (I->numFields() == 0 && I->Decoder.size()) { > - o.indent(Indentation) << " if (!" << I->Decoder > - << "(MI, insn, Address, Decoder)) return false;\n"; > + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder > + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n"; > break; > } > > emitBinaryParser(o, Indentation, *I); > } > > - o.indent(Indentation) << " return true; // " << nameWithID(Opc) > + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc) > << '\n'; > o.indent(Indentation) << "}\n"; > return true; > @@ -821,14 +827,14 @@ > I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { > // If a custom instruction decoder was specified, use that. > if (I->numFields() == 0 && I->Decoder.size()) { > - o.indent(Indentation) << " if (!" << I->Decoder > - << "(MI, insn, Address, Decoder)) return false;\n"; > + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder > + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n"; > break; > } > > emitBinaryParser(o, Indentation, *I); > } > - o.indent(Indentation) << " return true; // " << nameWithID(Opc) > + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc) > << '\n'; > o.indent(Indentation) << "}\n"; > > @@ -1426,7 +1432,7 @@ > > // Emit the decoder for this namespace+width combination. > FilterChooser FC(NumberedInstructions, I->second, Operands, > - 8*I->first.second); > + 8*I->first.second, this); > FC.emitTop(o, 0, I->first.first); > } > > > Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=137830&r1=137829&r2=137830&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original) > +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Aug 17 12:44:15 2011 > @@ -49,9 +49,16 @@ > > class FixedLenDecoderEmitter : public TableGenBackend { > public: > - FixedLenDecoderEmitter(RecordKeeper &R) : > + FixedLenDecoderEmitter(RecordKeeper &R, > + std::string GPrefix = "if (", > + std::string GPostfix = " == MCDisassembler::Fail) return MCDisassembler::Fail;", > + std::string ROK = "MCDisassembler::Success", > + std::string RFail = "MCDisassembler::Fail", > + std::string L = "") : > Records(R), Target(R), > - NumberedInstructions(Target.getInstructionsByEnumValue()) {} > + NumberedInstructions(Target.getInstructionsByEnumValue()), > + GuardPrefix(GPrefix), GuardPostfix(GPostfix), > + ReturnOK(ROK), ReturnFail(RFail), Locals(L) {} > > // run - Output the code emitter > void run(raw_ostream &o); > @@ -62,7 +69,10 @@ > std::vector NumberedInstructions; > std::vector Opcodes; > std::map > Operands; > - > +public: > + std::string GuardPrefix, GuardPostfix; > + std::string ReturnOK, ReturnFail; > + std::string Locals; > }; > > } // end llvm namespace > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dgregor at apple.com Fri Aug 26 14:05:18 2011 From: dgregor at apple.com (Douglas Gregor) Date: Fri, 26 Aug 2011 19:05:18 -0000 Subject: [llvm-commits] [llvm] r138640 - /llvm/trunk/utils/lit/lit/TestRunner.py Message-ID: <20110826190518.E938A2A6C12D@llvm.org> Author: dgregor Date: Fri Aug 26 14:05:18 2011 New Revision: 138640 URL: http://llvm.org/viewvc/llvm-project?rev=138640&view=rev Log: lit: Add %T as a replacement for the output directory Modified: llvm/trunk/utils/lit/lit/TestRunner.py Modified: llvm/trunk/utils/lit/lit/TestRunner.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138640&r1=138639&r2=138640&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/TestRunner.py (original) +++ llvm/trunk/utils/lit/lit/TestRunner.py Fri Aug 26 14:05:18 2011 @@ -397,7 +397,8 @@ sourcedir = os.path.dirname(sourcepath) execpath = test.getExecPath() execdir,execbase = os.path.split(execpath) - tmpBase = os.path.join(execdir, 'Output', execbase) + tmpDir = os.path.join(execdir, 'Output') + tmpBase = os.path.join(tmpDir, execbase) if test.index is not None: tmpBase += '_%d' % test.index @@ -414,6 +415,7 @@ ('%S', sourcedir), ('%p', sourcedir), ('%t', tmpBase + '.tmp'), + ('%T', tmpDir), # FIXME: Remove this once we kill DejaGNU. ('%abs_tmp', tmpBase + '.tmp'), ('#_MARKER_#', '%')]) From criswell at uiuc.edu Fri Aug 26 14:34:35 2011 From: criswell at uiuc.edu (John Criswell) Date: Fri, 26 Aug 2011 19:34:35 -0000 Subject: [llvm-commits] [poolalloc] r138641 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110826193436.020C82A6C12D@llvm.org> Author: criswell Date: Fri Aug 26 14:34:35 2011 New Revision: 138641 URL: http://llvm.org/viewvc/llvm-project?rev=138641&view=rev Log: Fixed a bug caught with the AssertGraph() method. When merging DSNodeHandles, we need to get references to them. Otherwise, the ScalarMap of the DSGraph isn't updated properly. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138641&r1=138640&r2=138641&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Aug 26 14:34:35 2011 @@ -500,8 +500,8 @@ if (CallInst* CI = dyn_cast(*ii)) { if (CI->getCalledValue() == F) { DSGraph* Graph = getDSGraph(*CI->getParent()->getParent()); - DSNodeHandle RetNode = Graph->getNodeForValue(CI); - DSNodeHandle ArgNode = Graph->getNodeForValue(CI->getArgOperand(arg)); + DSNodeHandle & RetNode = Graph->getNodeForValue(CI); + DSNodeHandle & ArgNode = Graph->getNodeForValue(CI->getArgOperand(arg)); RetNode.mergeWith(ArgNode); } } From resistor at mac.com Fri Aug 26 14:39:26 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 26 Aug 2011 19:39:26 -0000 Subject: [llvm-commits] [llvm] r138642 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Message-ID: <20110826193927.042812A6C12D@llvm.org> Author: resistor Date: Fri Aug 26 14:39:26 2011 New Revision: 138642 URL: http://llvm.org/viewvc/llvm-project?rev=138642&view=rev Log: Update for feedback from Jim. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138642&r1=138641&r2=138642&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 14:39:26 2011 @@ -2319,13 +2319,13 @@ CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); switch(Inst.getOpcode()) { + default: + return Fail; case ARM::tADR: - break; + break; // tADR does not explicitly represent the PC as an oeprand. case ARM::tADDrSPi: Inst.addOperand(MCOperand::CreateReg(ARM::SP)); break; - default: - return Fail; } Inst.addOperand(MCOperand::CreateImm(imm)); From criswell at uiuc.edu Fri Aug 26 14:42:21 2011 From: criswell at uiuc.edu (John Criswell) Date: Fri, 26 Aug 2011 19:42:21 -0000 Subject: [llvm-commits] [poolalloc] r138643 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110826194221.655C82A6C12D@llvm.org> Author: criswell Date: Fri Aug 26 14:42:21 2011 New Revision: 138643 URL: http://llvm.org/viewvc/llvm-project?rev=138643&view=rev Log: Added support for fastlscheck_debug, boundscheck_debug, boundscheckui_debug, and exactcheck2_debug(). We need to support debugging versions now since the Clang front-end can run the DebugInstrumentation pass in SAFECode. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=138643&r1=138642&r2=138643&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Aug 26 14:42:21 2011 @@ -259,17 +259,16 @@ {"fastlscheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"funccheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheckui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"funccheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"funccheckui_debug",{NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"poolcheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"fastlscheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalignui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"funccheckui_debug",{NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool_register_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool_unregister_stack", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, @@ -286,7 +285,6 @@ {"pool_register_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool_unregister_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - // CIF Intrinsics {"__if_pool_get_label", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"__if_pool_set_label", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, @@ -602,6 +600,11 @@ processRuntimeCheck (M, "boundscheck", 2); processRuntimeCheck (M, "boundscheckui", 2); processRuntimeCheck (M, "exactcheck2", 1); + + processRuntimeCheck (M, "boundscheck_debug", 2); + processRuntimeCheck (M, "boundscheckui_debug", 2); + processRuntimeCheck (M, "exactcheck2_debug", 1); + processRuntimeCheck (M, "pchk_getActualValue", 1); } From greened at obbligato.org Fri Aug 26 14:52:28 2011 From: greened at obbligato.org (David A. Greene) Date: Fri, 26 Aug 2011 14:52:28 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: (David Greene's message of "Fri, 26 Aug 2011 12:48:49 -0500") References: Message-ID: David Greene writes: > + else if (const ConstantArray *CA = dyn_cast(V)) { > + // Make sure all array elements are sequences of the same repeated > + // byte. > + int Byte = -1; > + for (int i = 0, e = CA->getNumOperands(); i != e; ++i) { > + int ThisByte = isRepeatedByteSequence(CA->getOperand(i), TM); > + if (ThisByte == -1) > + return -1; > + if (Byte == -1) > + Byte = ThisByte; > + if (Byte != ThisByte) > + return -1; > + } > + } Gah. I missed a return of Byte here. Will fix. -Dave From atrick at apple.com Fri Aug 26 15:01:36 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 26 Aug 2011 13:01:36 -0700 Subject: [llvm-commits] [llvm] r138640 - /llvm/trunk/utils/lit/lit/TestRunner.py In-Reply-To: <20110826190518.E938A2A6C12D@llvm.org> References: <20110826190518.E938A2A6C12D@llvm.org> Message-ID: <8E176856-8E3F-4DB4-BBB1-F9157B9E00C4@apple.com> I plan to improve this by allowing '%%' for literals so that tests like this still pass: ; RUN: echo {%Ty = type opaque @GV = external global %Ty*} | llvm-as > %t.1.bc If that's ok with everyone. -Andy On Aug 26, 2011, at 12:05 PM, Douglas Gregor wrote: > Author: dgregor > Date: Fri Aug 26 14:05:18 2011 > New Revision: 138640 > > URL: http://llvm.org/viewvc/llvm-project?rev=138640&view=rev > Log: > lit: Add %T as a replacement for the output directory > > Modified: > llvm/trunk/utils/lit/lit/TestRunner.py > > Modified: llvm/trunk/utils/lit/lit/TestRunner.py > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138640&r1=138639&r2=138640&view=diff > ============================================================================== > --- llvm/trunk/utils/lit/lit/TestRunner.py (original) > +++ llvm/trunk/utils/lit/lit/TestRunner.py Fri Aug 26 14:05:18 2011 > @@ -397,7 +397,8 @@ > sourcedir = os.path.dirname(sourcepath) > execpath = test.getExecPath() > execdir,execbase = os.path.split(execpath) > - tmpBase = os.path.join(execdir, 'Output', execbase) > + tmpDir = os.path.join(execdir, 'Output') > + tmpBase = os.path.join(tmpDir, execbase) > if test.index is not None: > tmpBase += '_%d' % test.index > > @@ -414,6 +415,7 @@ > ('%S', sourcedir), > ('%p', sourcedir), > ('%t', tmpBase + '.tmp'), > + ('%T', tmpDir), > # FIXME: Remove this once we kill DejaGNU. > ('%abs_tmp', tmpBase + '.tmp'), > ('#_MARKER_#', '%')]) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Fri Aug 26 15:09:48 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 26 Aug 2011 20:09:48 -0000 Subject: [llvm-commits] [llvm] r138647 - in /llvm/trunk/test: Linker/2003-01-30-LinkerTypeRename.ll Linker/2003-04-26-NullPtrLinkProblem.ll Linker/2003-06-02-TypeResolveProblem.ll Linker/2003-06-02-TypeResolveProblem2.ll Linker/2003-08-23-GlobalVarLinking.ll Linker/2003-11-18-TypeResolution.ll Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll Message-ID: <20110826200948.A2C672A6C12D@llvm.org> Author: atrick Date: Fri Aug 26 15:09:48 2011 New Revision: 138647 URL: http://llvm.org/viewvc/llvm-project?rev=138647&view=rev Log: Use %% for literals in RUN lines. Modified: llvm/trunk/test/Linker/2003-01-30-LinkerTypeRename.ll llvm/trunk/test/Linker/2003-04-26-NullPtrLinkProblem.ll llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem.ll llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem2.ll llvm/trunk/test/Linker/2003-08-23-GlobalVarLinking.ll llvm/trunk/test/Linker/2003-11-18-TypeResolution.ll llvm/trunk/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll Modified: llvm/trunk/test/Linker/2003-01-30-LinkerTypeRename.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-01-30-LinkerTypeRename.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-01-30-LinkerTypeRename.ll (original) +++ llvm/trunk/test/Linker/2003-01-30-LinkerTypeRename.ll Fri Aug 26 15:09:48 2011 @@ -1,9 +1,9 @@ -; This fails because the linker renames the non-opaque type not the opaque +; This fails because the linker renames the non-opaque type not the opaque ; one... -; RUN: echo {%Ty = type opaque @GV = external global %Ty*} | llvm-as > %t.1.bc +; RUN: echo {%%Ty = type opaque @GV = external global %%Ty*} | llvm-as > %t.1.bc ; RUN: llvm-as < %s > %t.2.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep {%Ty } | not grep opaque +; RUN: llvm-link %t.1.bc %t.2.bc -S | grep {%%Ty } | not grep opaque %Ty = type {i32} Modified: llvm/trunk/test/Linker/2003-04-26-NullPtrLinkProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-04-26-NullPtrLinkProblem.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-04-26-NullPtrLinkProblem.ll (original) +++ llvm/trunk/test/Linker/2003-04-26-NullPtrLinkProblem.ll Fri Aug 26 15:09:48 2011 @@ -1,7 +1,7 @@ ; This one fails because the LLVM runtime is allowing two null pointers of ; the same type to be created! -; RUN: echo {%T = type i32} | llvm-as > %t.2.bc +; RUN: echo {%%T = type i32} | llvm-as > %t.2.bc ; RUN: llvm-as %s -o %t.1.bc ; RUN: llvm-link %t.1.bc %t.2.bc Modified: llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem.ll (original) +++ llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem.ll Fri Aug 26 15:09:48 2011 @@ -1,4 +1,4 @@ -; RUN: echo {%T = type opaque} | llvm-as > %t.2.bc +; RUN: echo {%%T = type opaque} | llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc ; RUN: llvm-link %t.1.bc %t.2.bc Modified: llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem2.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem2.ll (original) +++ llvm/trunk/test/Linker/2003-06-02-TypeResolveProblem2.ll Fri Aug 26 15:09:48 2011 @@ -1,4 +1,4 @@ -; RUN: echo {%T = type i32} | llvm-as > %t.1.bc +; RUN: echo {%%T = type i32} | llvm-as > %t.1.bc ; RUN: llvm-as < %s > %t.2.bc ; RUN: llvm-link %t.1.bc %t.2.bc Modified: llvm/trunk/test/Linker/2003-08-23-GlobalVarLinking.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-08-23-GlobalVarLinking.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-08-23-GlobalVarLinking.ll (original) +++ llvm/trunk/test/Linker/2003-08-23-GlobalVarLinking.ll Fri Aug 26 15:09:48 2011 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s > %t.out1.bc -; RUN: echo {%T1 = type opaque %T2 = type opaque @S = external global \{ i32, %T1* \} declare void @F(%T2*)}\ +; RUN: echo {%%T1 = type opaque %%T2 = type opaque @S = external global \{ i32, %%T1* \} declare void @F(%%T2*)}\ ; RUN: | llvm-as > %t.out2.bc ; RUN: llvm-link %t.out1.bc %t.out2.bc -S | not grep opaque Modified: llvm/trunk/test/Linker/2003-11-18-TypeResolution.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2003-11-18-TypeResolution.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Linker/2003-11-18-TypeResolution.ll (original) +++ llvm/trunk/test/Linker/2003-11-18-TypeResolution.ll Fri Aug 26 15:09:48 2011 @@ -5,7 +5,7 @@ ; own. ; RUN: llvm-as < %s > %t.out2.bc -; RUN: echo "%T1 = type opaque @GVar = external global %T1*" | llvm-as > %t.out1.bc +; RUN: echo "%%T1 = type opaque @GVar = external global %%T1*" | llvm-as > %t.out1.bc ; RUN: llvm-link %t.out1.bc %t.out2.bc %T1 = type opaque Modified: llvm/trunk/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll?rev=138647&r1=138646&r2=138647&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2003-10-29-ArrayProblem.ll Fri Aug 26 15:09:48 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -scalarrepl -S | grep {alloca %T} +; RUN: opt < %s -scalarrepl -S | grep {alloca %%T} %T = type { [80 x i8], i32, i32 } declare i32 @.callback_1(i8*) From atrick at apple.com Fri Aug 26 15:19:52 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 26 Aug 2011 13:19:52 -0700 Subject: [llvm-commits] [llvm] r138640 - /llvm/trunk/utils/lit/lit/TestRunner.py In-Reply-To: <8E176856-8E3F-4DB4-BBB1-F9157B9E00C4@apple.com> References: <20110826190518.E938A2A6C12D@llvm.org> <8E176856-8E3F-4DB4-BBB1-F9157B9E00C4@apple.com> Message-ID: <8018B114-AED5-4C00-9A1D-86048FF2CB3C@apple.com> Ignore me. Lit already substitutes %% (it just doesn't complain when people forget). Tests fixed. On Aug 26, 2011, at 1:01 PM, Andrew Trick wrote: > I plan to improve this by allowing '%%' for literals so that tests like this still pass: > > ; RUN: echo {%Ty = type opaque @GV = external global %Ty*} | llvm-as > %t.1.bc > > If that's ok with everyone. > -Andy > > On Aug 26, 2011, at 12:05 PM, Douglas Gregor wrote: > >> Author: dgregor >> Date: Fri Aug 26 14:05:18 2011 >> New Revision: 138640 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=138640&view=rev >> Log: >> lit: Add %T as a replacement for the output directory >> >> Modified: >> llvm/trunk/utils/lit/lit/TestRunner.py >> >> Modified: llvm/trunk/utils/lit/lit/TestRunner.py >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138640&r1=138639&r2=138640&view=diff >> ============================================================================== >> --- llvm/trunk/utils/lit/lit/TestRunner.py (original) >> +++ llvm/trunk/utils/lit/lit/TestRunner.py Fri Aug 26 14:05:18 2011 >> @@ -397,7 +397,8 @@ >> sourcedir = os.path.dirname(sourcepath) >> execpath = test.getExecPath() >> execdir,execbase = os.path.split(execpath) >> - tmpBase = os.path.join(execdir, 'Output', execbase) >> + tmpDir = os.path.join(execdir, 'Output') >> + tmpBase = os.path.join(tmpDir, execbase) >> if test.index is not None: >> tmpBase += '_%d' % test.index >> >> @@ -414,6 +415,7 @@ >> ('%S', sourcedir), >> ('%p', sourcedir), >> ('%t', tmpBase + '.tmp'), >> + ('%T', tmpDir), >> # FIXME: Remove this once we kill DejaGNU. >> ('%abs_tmp', tmpBase + '.tmp'), >> ('#_MARKER_#', '%')]) >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dgregor at apple.com Fri Aug 26 15:22:54 2011 From: dgregor at apple.com (Douglas Gregor) Date: Fri, 26 Aug 2011 13:22:54 -0700 Subject: [llvm-commits] [llvm] r138640 - /llvm/trunk/utils/lit/lit/TestRunner.py In-Reply-To: <8018B114-AED5-4C00-9A1D-86048FF2CB3C@apple.com> References: <20110826190518.E938A2A6C12D@llvm.org> <8E176856-8E3F-4DB4-BBB1-F9157B9E00C4@apple.com> <8018B114-AED5-4C00-9A1D-86048FF2CB3C@apple.com> Message-ID: On Aug 26, 2011, at 1:19 PM, Andrew Trick wrote: > Ignore me. Lit already substitutes %% (it just doesn't complain when people forget). Tests fixed. Thanks! - Doug > On Aug 26, 2011, at 1:01 PM, Andrew Trick wrote: > >> I plan to improve this by allowing '%%' for literals so that tests like this still pass: >> >> ; RUN: echo {%Ty = type opaque @GV = external global %Ty*} | llvm-as > %t.1.bc >> >> If that's ok with everyone. >> -Andy >> >> On Aug 26, 2011, at 12:05 PM, Douglas Gregor wrote: >> >>> Author: dgregor >>> Date: Fri Aug 26 14:05:18 2011 >>> New Revision: 138640 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=138640&view=rev >>> Log: >>> lit: Add %T as a replacement for the output directory >>> >>> Modified: >>> llvm/trunk/utils/lit/lit/TestRunner.py >>> >>> Modified: llvm/trunk/utils/lit/lit/TestRunner.py >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138640&r1=138639&r2=138640&view=diff >>> ============================================================================== >>> --- llvm/trunk/utils/lit/lit/TestRunner.py (original) >>> +++ llvm/trunk/utils/lit/lit/TestRunner.py Fri Aug 26 14:05:18 2011 >>> @@ -397,7 +397,8 @@ >>> sourcedir = os.path.dirname(sourcepath) >>> execpath = test.getExecPath() >>> execdir,execbase = os.path.split(execpath) >>> - tmpBase = os.path.join(execdir, 'Output', execbase) >>> + tmpDir = os.path.join(execdir, 'Output') >>> + tmpBase = os.path.join(tmpDir, execbase) >>> if test.index is not None: >>> tmpBase += '_%d' % test.index >>> >>> @@ -414,6 +415,7 @@ >>> ('%S', sourcedir), >>> ('%p', sourcedir), >>> ('%t', tmpBase + '.tmp'), >>> + ('%T', tmpDir), >>> # FIXME: Remove this once we kill DejaGNU. >>> ('%abs_tmp', tmpBase + '.tmp'), >>> ('#_MARKER_#', '%')]) >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rdivacky at freebsd.org Fri Aug 26 15:26:26 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Fri, 26 Aug 2011 22:26:26 +0200 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: References: <20110824191434.GA29249@freebsd.org> <20110826065352.GA69924@freebsd.org> Message-ID: <20110826202626.GA70172@freebsd.org> > Patch? It was attached in the first mail :) I am attaching it once more. -------------- next part -------------- A non-text attachment was scrubbed... Name: ppc-cr1eq.patch Type: text/x-diff Size: 1888 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110826/410795f0/attachment.bin From baldrick at free.fr Fri Aug 26 15:37:10 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 26 Aug 2011 20:37:10 -0000 Subject: [llvm-commits] [test-suite] r138650 - in /test-suite/trunk/MultiSource: Applications/siod/Makefile Benchmarks/MiBench/consumer-lame/Makefile Message-ID: <20110826203710.4E0432A6C12D@llvm.org> Author: baldrick Date: Fri Aug 26 15:37:10 2011 New Revision: 138650 URL: http://llvm.org/viewvc/llvm-project?rev=138650&view=rev Log: The siod and consumer-lame tests appear to fail when using dragonegg, because their output does not match the output when they are built with gcc. But in fact it is gcc that is miscompiling these tests, so force comparison with the reference output to avoid these false negatives. Modified: test-suite/trunk/MultiSource/Applications/siod/Makefile test-suite/trunk/MultiSource/Benchmarks/MiBench/consumer-lame/Makefile Modified: test-suite/trunk/MultiSource/Applications/siod/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/siod/Makefile?rev=138650&r1=138649&r2=138650&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Applications/siod/Makefile (original) +++ test-suite/trunk/MultiSource/Applications/siod/Makefile Fri Aug 26 15:37:10 2011 @@ -5,5 +5,11 @@ RUN_OPTIONS = -v1 $(PROJ_SRC_DIR)/test.scm +# Define USE_REFERENCE_OUTPUT which is a signal to Makefile.programs that the +# natively compiled program should not be run but that its output should be +# "faked" by copying the reference output. This is because gcc-4.6 miscompiles +# siod, resulting in a program that fails to parse the Fibonacci test. +USE_REFERENCE_OUTPUT := 1 + include ../../Makefile.multisrc Modified: test-suite/trunk/MultiSource/Benchmarks/MiBench/consumer-lame/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/MiBench/consumer-lame/Makefile?rev=138650&r1=138649&r2=138650&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/MiBench/consumer-lame/Makefile (original) +++ test-suite/trunk/MultiSource/Benchmarks/MiBench/consumer-lame/Makefile Fri Aug 26 15:37:10 2011 @@ -4,4 +4,11 @@ CPPFLAGS = -DHAVEMPGLIB -DLAMEPARSE -DNDEBUG -D__NO_MATH_INLINES -O -DLAMESNDFILE LDFLAGS = -lm RUN_OPTIONS = -S $(PROJ_SRC_DIR)/large.wav Output/output_large.mp3 + +# Define USE_REFERENCE_OUTPUT which is a signal to Makefile.programs that the +# natively compiled program should not be run but that its output should be +# "faked" by copying the reference output. This is because gcc-4.6 miscompiles +# consumer-lame, resulting in a program that just dies horribly dumping core. +USE_REFERENCE_OUTPUT := 1 + include $(LEVEL)/MultiSource/Makefile.multisrc From isanbard at gmail.com Fri Aug 26 15:40:15 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 26 Aug 2011 20:40:15 -0000 Subject: [llvm-commits] [llvm] r138651 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/crash.ll Message-ID: <20110826204015.36DF42A6C12D@llvm.org> Author: void Date: Fri Aug 26 15:40:15 2011 New Revision: 138651 URL: http://llvm.org/viewvc/llvm-project?rev=138651&view=rev Log: Don't sink landingpad instructions during ind-var simplification. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=138651&r1=138650&r2=138651&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Aug 26 15:40:15 2011 @@ -1724,6 +1724,10 @@ if (isa(I)) continue; + // Skip landingpad instructions. + if (isa(I)) + continue; + // Don't sink static AllocaInsts out of the entry block, which would // turn them into dynamic allocas! if (AllocaInst *AI = dyn_cast(I)) Modified: llvm/trunk/test/Transforms/IndVarSimplify/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/crash.ll?rev=138651&r1=138650&r2=138651&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/crash.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/crash.ll Fri Aug 26 15:40:15 2011 @@ -53,3 +53,35 @@ %2 = add nsw i32 %r.0, 1 ; [#uses=1] br label %bb24 } + +; PR10770 + +declare void @__go_panic() noreturn + +declare void @__go_undefer() + +declare i32 @__gccgo_personality_v0(i32, i64, i8*, i8*) + +define void @main.main() uwtable { +entry: + invoke void @__go_panic() noreturn + to label %0 unwind label %"5.i" + +;