From nadav.rotem at intel.com Mon Aug 29 01:34:12 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 29 Aug 2011 09:34:12 +0300 Subject: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll In-Reply-To: <4E5A2F79.8060506@free.fr> References: <20110828115108.477FD2A6C13F@llvm.org> <4E5A2F79.8060506@free.fr> Message-ID: <6594DDFF12B03D4E89690887C248699402970B49B6@hasmsx504.ger.corp.intel.com> Hi Duncan, I attached a patch to fix the MMX type issue. I am still not sure about the legality of casting vectors to integers, as defined in isEliminableCastPair. Thanks, Nadav -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Sunday, August 28, 2011 15:07 To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll Hi Nadav, > Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. sadly this is not true because you are only allowed to bitcast an mmx type to and from a vector type, but you can bitcast vector to and from integers etc. > + // Bitcast of Bitcast can be done using a single cast. > + ConstantExpr *CE = dyn_cast(C); > + if (CE&& CE->getOpcode() == Instruction::BitCast) { > + return ConstantExpr::getBitCast(CE->getOperand(0), DestTy); > + } No need for curly brackets {}. > + // Bitcasts are transitive. > + if (BitCastInst* BSrc = dyn_cast(Src)) { > + return CastInst::Create(Instruction::BitCast, BSrc->getOperand(0), DestTy); > + } Likewise. Also, this could be: if (isa(Src)) return CastInst::Create(Instruction::BitCast, Src->getOperand(0), DestTy); Also, shouldn't you create the cast using instcombine's builder? Ciao, Duncan. _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: mmx_bitcast_patch.diff Type: application/octet-stream Size: 2557 bytes Desc: mmx_bitcast_patch.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/d25e54e6/attachment.obj From baldrick at free.fr Mon Aug 29 01:41:05 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 08:41:05 +0200 Subject: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll In-Reply-To: <6594DDFF12B03D4E89690887C248699402970B49B6@hasmsx504.ger.corp.intel.com> References: <20110828115108.477FD2A6C13F@llvm.org> <4E5A2F79.8060506@free.fr> <6594DDFF12B03D4E89690887C248699402970B49B6@hasmsx504.ger.corp.intel.com> Message-ID: <4E5B3481.4070902@free.fr> Hi Nadav, > I attached a patch to fix the MMX type issue. I am still not sure about the legality of casting vectors to integers, as defined in isEliminableCastPair. I think you should check the uses of isEliminableCastPair to see if you can see why it doesn't want to consider vectors. Assuming that there is no good reason, I think you should use isEliminableCastPair in your patch, and change isEliminableCastPair to allow vectors, but disallow mmx. Ciao, Duncan. PS: Don't forget to run the testsuite after making this change! > > Thanks, > Nadav > > > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands > Sent: Sunday, August 28, 2011 15:07 > To: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll > > Hi Nadav, > >> Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. > > sadly this is not true because you are only allowed to bitcast an mmx type > to and from a vector type, but you can bitcast vector to and from integers > etc. > >> + // Bitcast of Bitcast can be done using a single cast. >> + ConstantExpr *CE = dyn_cast(C); >> + if (CE&& CE->getOpcode() == Instruction::BitCast) { >> + return ConstantExpr::getBitCast(CE->getOperand(0), DestTy); >> + } > > No need for curly brackets {}. > >> + // Bitcasts are transitive. >> + if (BitCastInst* BSrc = dyn_cast(Src)) { >> + return CastInst::Create(Instruction::BitCast, BSrc->getOperand(0), DestTy); >> + } > > Likewise. Also, this could be: > if (isa(Src)) > return CastInst::Create(Instruction::BitCast, Src->getOperand(0), DestTy); > Also, shouldn't you create the cast using instcombine's builder? > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. From nadav.rotem at intel.com Mon Aug 29 07:57:27 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 29 Aug 2011 15:57:27 +0300 Subject: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll In-Reply-To: <4E5B3481.4070902@free.fr> References: <20110828115108.477FD2A6C13F@llvm.org> <4E5A2F79.8060506@free.fr> <6594DDFF12B03D4E89690887C248699402970B49B6@hasmsx504.ger.corp.intel.com> <4E5B3481.4070902@free.fr> Message-ID: <6594DDFF12B03D4E89690887C24869940297124C41@hasmsx504.ger.corp.intel.com> Hi Duncan, Here is another attempt. In the attached patch I had reverted r138722, and added an exception to isEliminableCastPair, which allows the bitcasting of A->B->A. I also added some new tests. Thanks, Nadav -----Original Message----- From: Duncan Sands [mailto:baldrick at free.fr] Sent: Monday, August 29, 2011 09:41 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll Hi Nadav, > I attached a patch to fix the MMX type issue. I am still not sure about the legality of casting vectors to integers, as defined in isEliminableCastPair. I think you should check the uses of isEliminableCastPair to see if you can see why it doesn't want to consider vectors. Assuming that there is no good reason, I think you should use isEliminableCastPair in your patch, and change isEliminableCastPair to allow vectors, but disallow mmx. Ciao, Duncan. PS: Don't forget to run the testsuite after making this change! > > Thanks, > Nadav > > > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands > Sent: Sunday, August 28, 2011 15:07 > To: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll > > Hi Nadav, > >> Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. > > sadly this is not true because you are only allowed to bitcast an mmx type > to and from a vector type, but you can bitcast vector to and from integers > etc. > >> + // Bitcast of Bitcast can be done using a single cast. >> + ConstantExpr *CE = dyn_cast(C); >> + if (CE&& CE->getOpcode() == Instruction::BitCast) { >> + return ConstantExpr::getBitCast(CE->getOperand(0), DestTy); >> + } > > No need for curly brackets {}. > >> + // Bitcasts are transitive. >> + if (BitCastInst* BSrc = dyn_cast(Src)) { >> + return CastInst::Create(Instruction::BitCast, BSrc->getOperand(0), DestTy); >> + } > > Likewise. Also, this could be: > if (isa(Src)) > return CastInst::Create(Instruction::BitCast, Src->getOperand(0), DestTy); > Also, shouldn't you create the cast using instcombine's builder? > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: bitcast_patch.diff Type: application/octet-stream Size: 3950 bytes Desc: bitcast_patch.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/f4d94354/attachment.obj From baldrick at free.fr Mon Aug 29 08:11:00 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 15:11:00 +0200 Subject: [llvm-commits] [llvm] r138722 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/cast.ll In-Reply-To: <6594DDFF12B03D4E89690887C24869940297124C41@hasmsx504.ger.corp.intel.com> References: <20110828115108.477FD2A6C13F@llvm.org> <4E5A2F79.8060506@free.fr> <6594DDFF12B03D4E89690887C248699402970B49B6@hasmsx504.ger.corp.intel.com> <4E5B3481.4070902@free.fr> <6594DDFF12B03D4E89690887C24869940297124C41@hasmsx504.ger.corp.intel.com> Message-ID: <4E5B8FE4.8030607@free.fr> Hi Nadav, > --- lib/VMCore/Instructions.cpp (revision 138427) > +++ lib/VMCore/Instructions.cpp (working copy) > @@ -2114,10 +2114,12 @@ > > // If either of the casts are a bitcast from scalar to vector, disallow the > // merging. > - if ((firstOp == Instruction::BitCast && > + // Bitcasts of A->B->A are okay. > + if ((SrcTy != DstTy) && > + ((firstOp == Instruction::BitCast && > isa(SrcTy) != isa(MidTy)) || > (secondOp == Instruction::BitCast && > - isa(MidTy) != isa(DstTy))) > + isa(MidTy) != isa(DstTy)))) > return 0; // Disallowed I think it would be better to say that it is OK if both instructions are bitcasts. The problematic case seems to be when one is a bitcast and the other is not (PR7311). Ciao, Duncan. > > int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin] From baldrick at free.fr Mon Aug 29 09:11:47 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 14:11:47 -0000 Subject: [llvm-commits] [dragonegg] r138732 - in /dragonegg/trunk/src: Convert.cpp Types.cpp Message-ID: <20110829141147.F1E002A6C12C@llvm.org> Author: baldrick Date: Mon Aug 29 09:11:47 2011 New Revision: 138732 URL: http://llvm.org/viewvc/llvm-project?rev=138732&view=rev Log: Partially revert commit 138663: output C functions void foo() as void @foo(...). Leave the Fortran changes (i.e. not abusing ...) in place. Modified: dragonegg/trunk/src/Convert.cpp dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=138732&r1=138731&r2=138732&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Mon Aug 29 09:11:47 2011 @@ -8431,8 +8431,7 @@ // If this is a K&R-style function: with a type that takes no arguments but // with arguments none the less, then calculate the LLVM type from the list // of arguments. - if (flag_functions_from_args || (TYPE_ARG_TYPES(function_type) == 0 && - gimple_call_num_args(stmt) > 0)) { + if (flag_functions_from_args) { tree *FirstArgAddr = gimple_call_num_args(stmt) > 0 ? gimple_call_arg_ptr(stmt, 0) : NULL; Ty = ConvertArgListToFnType(function_type, Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=138732&r1=138731&r2=138732&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Mon Aug 29 09:11:47 2011 @@ -893,7 +893,7 @@ // Finally, make the function type and result attributes. PAL = AttrListPtr::get(Attrs.begin(), Attrs.end()); - return FunctionType::get(RetTy, ArgTypes, stdarg_p(type)); + return FunctionType::get(RetTy, ArgTypes, Args == 0); } static Type *ConvertPointerTypeRecursive(tree type) { From Micah.Villmow at amd.com Mon Aug 29 10:17:15 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Mon, 29 Aug 2011 10:17:15 -0500 Subject: [llvm-commits] [PATCH - Pending review] AMDIL Target Triple patch In-Reply-To: <4E58A141.8000003@grosser.es> References:

<4E575E92.40505@grosser.es> <4E57680B.704@mxc.ca> <4E576ED7.105@grosser.es> <4E58A141.8000003@grosser.es> Message-ID: > -----Original Message----- > From: Tobias Grosser [mailto:tobias at grosser.es] > Sent: Saturday, August 27, 2011 12:48 AM > To: Villmow, Micah > Cc: Nick Lewycky; llvm-commits > Subject: Re: [llvm-commits] [PATCH - Pending review] AMDIL Target > Triple patch > > On 08/27/2011 01:05 AM, Villmow, Micah wrote: > > Here is the updated patch. > > >> On 08/26/2011 10:31 AM, Nick Lewycky wrote: > >>> It looks like it needs to be updated > >>> for the recent addition of "le32", but then Micah, please commit! > > Hi Micah, > > Nick already preapproved your updated patch. Please go ahead and > commit. [Villmow, Micah] I have commit access? I have never actually tried myself, but from the website it seems like you need an account. > > Tobi From Micah.Villmow at amd.com Mon Aug 29 10:40:01 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Mon, 29 Aug 2011 10:40:01 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

<4E575E92.40505@grosser.es> <4E57680B.704@mxc.ca> <4E576ED7.105@grosser.es> <4E58A141.8000003@grosser.es> Message-ID: <4E5BB4A4.4060607@grosser.es> On 08/29/2011 04:17 PM, Villmow, Micah wrote: > > >> -----Original Message----- >> From: Tobias Grosser [mailto:tobias at grosser.es] >> Sent: Saturday, August 27, 2011 12:48 AM >> To: Villmow, Micah >> Cc: Nick Lewycky; llvm-commits >> Subject: Re: [llvm-commits] [PATCH - Pending review] AMDIL Target >> Triple patch >> >> On 08/27/2011 01:05 AM, Villmow, Micah wrote: >>> Here is the updated patch. >> >>>> On 08/26/2011 10:31 AM, Nick Lewycky wrote: >>>>> It looks like it needs to be updated >>>>> for the recent addition of "le32", but then Micah, please commit! >> >> Hi Micah, >> >> Nick already preapproved your updated patch. Please go ahead and >> commit. > [Villmow, Micah] I have commit access? I have never actually tried myself, but from the website it seems like you need an account. I expected you to have commit access, sorry. Committed at r138734. Tobi From dag at cray.com Mon Aug 29 11:39:31 2011 From: dag at cray.com (David A. Greene) Date: Mon, 29 Aug 2011 11:39:31 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <8448FDD6-2174-47BA-B145-EB65294CB91B@apple.com> (Chris Lattner's message of "Fri, 26 Aug 2011 18:39:22 -0500") References: <8448FDD6-2174-47BA-B145-EB65294CB91B@apple.com> Message-ID: Chris Lattner writes: > On Aug 26, 2011, at 10:48 AM, David Greene wrote: > >> >> Emit a repeated sequence of bytes using .zero. This saves an enormous >> amount of asm file space for certain programs. >> --- > > In addition to the return, please remove these two cases, which are handled below with the generic code: > > + if (CI->isZero()) > + return 0; > + if (CI->isAllOnesValue()) > + return 0xfful; Ok. I was trying to speed up common cases. > > > + uint8_t Byte = Value & 0xffull; > > What's up with the ULL suffixes here and UL elsewhere? Please use > capital suffixes if you want to keep them. I'd recommend just > replacing this with uint8_t(Value) which is more explicit. ULL because Value is a 64-bit quantity. But yeah, a cast should work. > + if (Size == 1) > + return Byte; > > Please remove this, it isn't doing anything. Ok. > Your ConstantInt handling code still doesn't handle i11's. You need > to ensure that we have a multiple of 8 bits and a power of 2 (to avoid > tail padding being ignored). Didn't know we have such things. Will fix. > + return Byte; > + } > + else if > > No need for the else. Right. > + else if (const ConstantArray *CA = dyn_cast(V)) { > + // Make sure all array elements are sequences of the same repeated > + // byte. > + int Byte = -1; > + for (int i = 0, e = CA->getNumOperands(); i != e; ++i) { > > This is awkward. Just peel off one iteration: All right. -Dave From atrick at apple.com Mon Aug 29 12:07:00 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 29 Aug 2011 17:07:00 -0000 Subject: [llvm-commits] [llvm] r138737 - in /llvm/trunk: include/llvm/Analysis/LoopPass.h include/llvm/Analysis/RegionPass.h include/llvm/LinkAllPasses.h include/llvm/PassManagers.h lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Analysis/LoopPass.cpp lib/Analysis/RegionPass.cpp lib/VMCore/PassManager.cpp Message-ID: <20110829170701.040492A6C12F@llvm.org> Author: atrick Date: Mon Aug 29 12:07:00 2011 New Revision: 138737 URL: http://llvm.org/viewvc/llvm-project?rev=138737&view=rev Log: Reapply r138695. Fix PassManager stack depths. Patch by Xiaoyi Guo! Modified: llvm/trunk/include/llvm/Analysis/LoopPass.h llvm/trunk/include/llvm/Analysis/RegionPass.h llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/PassManagers.h llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp llvm/trunk/lib/Analysis/LoopPass.cpp llvm/trunk/lib/Analysis/RegionPass.cpp llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/include/llvm/Analysis/LoopPass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopPass.h?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopPass.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopPass.h Mon Aug 29 12:07:00 2011 @@ -84,7 +84,7 @@ class LPPassManager : public FunctionPass, public PMDataManager { public: static char ID; - explicit LPPassManager(int Depth); + explicit LPPassManager(); /// run - Execute all of the passes scheduled for execution. Keep track of /// whether any of the passes modifies the module, and if so, return true. Modified: llvm/trunk/include/llvm/Analysis/RegionPass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/RegionPass.h?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/RegionPass.h (original) +++ llvm/trunk/include/llvm/Analysis/RegionPass.h Mon Aug 29 12:07:00 2011 @@ -88,7 +88,7 @@ public: static char ID; - explicit RGPassManager(int Depth); + explicit RGPassManager(); /// @brief Execute all of the passes scheduled for execution. /// Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Mon Aug 29 12:07:00 2011 @@ -156,7 +156,7 @@ (void)new llvm::FindUsedTypes(); (void)new llvm::ScalarEvolution(); ((llvm::Function*)0)->viewCFGOnly(); - llvm::RGPassManager RGM(0); + llvm::RGPassManager RGM; ((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM); llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0); X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets Modified: llvm/trunk/include/llvm/PassManagers.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassManagers.h?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassManagers.h (original) +++ llvm/trunk/include/llvm/PassManagers.h Mon Aug 29 12:07:00 2011 @@ -263,7 +263,7 @@ class PMDataManager { public: - explicit PMDataManager(int Depth) : TPM(NULL), Depth(Depth) { + explicit PMDataManager() : TPM(NULL), Depth(0) { initializeAnalysisInfo(); } @@ -333,6 +333,7 @@ void setTopLevelManager(PMTopLevelManager *T) { TPM = T; } unsigned getDepth() const { return Depth; } + void setDepth(unsigned newDepth) { Depth = newDepth; } // Print routines used by debug-pass void dumpLastUses(Pass *P, unsigned Offset) const; @@ -408,8 +409,8 @@ class FPPassManager : public ModulePass, public PMDataManager { public: static char ID; - explicit FPPassManager(int Depth) - : ModulePass(ID), PMDataManager(Depth) { } + explicit FPPassManager() + : ModulePass(ID), PMDataManager() { } /// run - Execute all of the passes scheduled for execution. Keep track of /// whether any of the passes modifies the module, and if so, return true. Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Mon Aug 29 12:07:00 2011 @@ -44,8 +44,8 @@ class CGPassManager : public ModulePass, public PMDataManager { public: static char ID; - explicit CGPassManager(int Depth) - : ModulePass(ID), PMDataManager(Depth) { } + explicit CGPassManager() + : ModulePass(ID), PMDataManager() { } /// run - Execute all of the passes scheduled for execution. Keep track of /// whether any of the passes modifies the module, and if so, return true. @@ -543,7 +543,7 @@ PMDataManager *PMD = PMS.top(); // [1] Create new Call Graph Pass Manager - CGP = new CGPassManager(PMD->getDepth() + 1); + CGP = new CGPassManager(); // [2] Set up new manager's top level manager PMTopLevelManager *TPM = PMD->getTopLevelManager(); Modified: llvm/trunk/lib/Analysis/LoopPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopPass.cpp?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopPass.cpp (original) +++ llvm/trunk/lib/Analysis/LoopPass.cpp Mon Aug 29 12:07:00 2011 @@ -73,8 +73,8 @@ char LPPassManager::ID = 0; -LPPassManager::LPPassManager(int Depth) - : FunctionPass(ID), PMDataManager(Depth) { +LPPassManager::LPPassManager() + : FunctionPass(ID), PMDataManager() { skipThisLoop = false; redoThisLoop = false; LI = NULL; @@ -357,8 +357,8 @@ assert (!PMS.empty() && "Unable to create Loop Pass Manager"); PMDataManager *PMD = PMS.top(); - // [1] Create new Call Graph Pass Manager - LPPM = new LPPassManager(PMD->getDepth() + 1); + // [1] Create new Loop Pass Manager + LPPM = new LPPassManager(); LPPM->populateInheritedAnalysis(PMS); // [2] Set up new manager's top level manager Modified: llvm/trunk/lib/Analysis/RegionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/RegionPass.cpp?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/RegionPass.cpp (original) +++ llvm/trunk/lib/Analysis/RegionPass.cpp Mon Aug 29 12:07:00 2011 @@ -27,8 +27,8 @@ char RGPassManager::ID = 0; -RGPassManager::RGPassManager(int Depth) - : FunctionPass(ID), PMDataManager(Depth) { +RGPassManager::RGPassManager() + : FunctionPass(ID), PMDataManager() { skipThisRegion = false; redoThisRegion = false; RI = NULL; @@ -250,7 +250,7 @@ PMDataManager *PMD = PMS.top(); // [1] Create new Region Pass Manager - RGPM = new RGPassManager(PMD->getDepth() + 1); + RGPM = new RGPassManager(); RGPM->populateInheritedAnalysis(PMS); // [2] Set up new manager's top level manager Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=138737&r1=138736&r2=138737&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Aug 29 12:07:00 2011 @@ -167,8 +167,8 @@ public: static char ID; - explicit BBPassManager(int Depth) - : PMDataManager(Depth), FunctionPass(ID) {} + explicit BBPassManager() + : PMDataManager(), FunctionPass(ID) {} /// Execute all of the passes scheduled for execution. Keep track of /// whether any of the passes modifies the function, and if so, return true. @@ -228,9 +228,9 @@ bool wasRun; public: static char ID; - explicit FunctionPassManagerImpl(int Depth) : - Pass(PT_PassManager, ID), PMDataManager(Depth), - PMTopLevelManager(new FPPassManager(1)), wasRun(false) {} + explicit FunctionPassManagerImpl() : + Pass(PT_PassManager, ID), PMDataManager(), + PMTopLevelManager(new FPPassManager()), wasRun(false) {} /// add - Add a pass to the queue of passes to run. This passes ownership of /// the Pass to the PassManager. When the PassManager is destroyed, the pass @@ -303,8 +303,8 @@ class MPPassManager : public Pass, public PMDataManager { public: static char ID; - explicit MPPassManager(int Depth) : - Pass(PT_PassManager, ID), PMDataManager(Depth) { } + explicit MPPassManager() : + Pass(PT_PassManager, ID), PMDataManager() { } // Delete on the fly managers. virtual ~MPPassManager() { @@ -388,9 +388,9 @@ public: static char ID; - explicit PassManagerImpl(int Depth) : - Pass(PT_PassManager, ID), PMDataManager(Depth), - PMTopLevelManager(new MPPassManager(1)) {} + explicit PassManagerImpl() : + Pass(PT_PassManager, ID), PMDataManager(), + PMTopLevelManager(new MPPassManager()) {} /// add - Add a pass to the queue of passes to run. This passes ownership of /// the Pass to the PassManager. When the PassManager is destroyed, the pass @@ -1340,7 +1340,7 @@ /// Create new Function pass manager FunctionPassManager::FunctionPassManager(Module *m) : M(m) { - FPM = new FunctionPassManagerImpl(0); + FPM = new FunctionPassManagerImpl(); // FPM is the top level manager. FPM->setTopLevelManager(FPM); @@ -1626,7 +1626,7 @@ FunctionPassManagerImpl *FPP = OnTheFlyManagers[P]; if (!FPP) { - FPP = new FunctionPassManagerImpl(0); + FPP = new FunctionPassManagerImpl(); // FPP is the top level manager. FPP->setTopLevelManager(FPP); @@ -1677,7 +1677,7 @@ /// Create new pass manager PassManager::PassManager() { - PM = new PassManagerImpl(0); + PM = new PassManagerImpl(); // PM is the top level manager PM->setTopLevelManager(PM); } @@ -1761,13 +1761,23 @@ // Push PM on the stack and set its top level manager. void PMStack::push(PMDataManager *PM) { assert(PM && "Unable to push. Pass Manager expected"); + assert(PM->getDepth()==0 && "Pass Manager depth set too early"); if (!this->empty()) { + assert(PM->getPassManagerType() > this->top()->getPassManagerType() + && "pushing bad pass manager to PMStack"); PMTopLevelManager *TPM = this->top()->getTopLevelManager(); assert(TPM && "Unable to find top level manager"); TPM->addIndirectPassManager(PM); PM->setTopLevelManager(TPM); + PM->setDepth(this->top()->getDepth()+1); + } + else { + assert(PM->getPassManagerType() == PMT_ModulePassManager + || PM->getPassManagerType() == PMT_FunctionPassManager + && "pushing bad pass manager to PMStack"); + PM->setDepth(1); } S.push_back(PM); @@ -1823,7 +1833,7 @@ PMDataManager *PMD = PMS.top(); // [1] Create new Function Pass Manager - FPP = new FPPassManager(PMD->getDepth() + 1); + FPP = new FPPassManager(); FPP->populateInheritedAnalysis(PMS); // [2] Set up new manager's top level manager @@ -1860,7 +1870,7 @@ PMDataManager *PMD = PMS.top(); // [1] Create new Basic Block Manager - BBP = new BBPassManager(PMD->getDepth() + 1); + BBP = new BBPassManager(); // [2] Set up new manager's top level manager // Basic Block Pass Manager does not live by itself From resistor at mac.com Mon Aug 29 12:17:09 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 17:17:09 -0000 Subject: [llvm-commits] [llvm] r138739 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s Message-ID: <20110829171709.7B9062A6C12E@llvm.org> Author: resistor Date: Mon Aug 29 12:17:09 2011 New Revision: 138739 URL: http://llvm.org/viewvc/llvm-project?rev=138739&view=rev Log: Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138739&r1=138738&r2=138739&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 29 12:17:09 2011 @@ -717,7 +717,7 @@ const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); - return Val > -256 && Val < 256; + return (Val > -256 && Val < 256) || (Val == INT32_MIN); } bool isMSRMask() const { return Kind == MSRMask; } @@ -1106,6 +1106,7 @@ assert(CE && "non-constant post-idx-imm8 operand!"); int Imm = CE->getValue(); bool isAdd = Imm >= 0; + if (Imm == INT32_MIN) Imm = 0; Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; Inst.addOperand(MCOperand::CreateImm(Imm)); } @@ -2746,17 +2747,27 @@ return parseMemory(Operands); case AsmToken::LCurly: return parseRegisterList(Operands); - case AsmToken::Hash: + case AsmToken::Hash: { // #42 -> immediate. // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate S = Parser.getTok().getLoc(); Parser.Lex(); + bool isNegative = Parser.getTok().is(AsmToken::Minus); const MCExpr *ImmVal; if (getParser().ParseExpression(ImmVal)) return true; + const MCConstantExpr *CE = dyn_cast(ImmVal); + if (!CE) { + Error(S, "constant expression expected"); + return MatchOperand_ParseFail; + } + int32_t Val = CE->getValue(); + if (isNegative && Val == 0) + ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); return false; + } case AsmToken::Colon: { // ":lower16:" and ":upper16:" expression prefixes // FIXME: Check it's an expression prefix, Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=138739&r1=138738&r2=138739&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Aug 29 12:17:09 2011 @@ -687,6 +687,14 @@ @ CHECK: ldrex r1, [r7] @ encoding: [0x9f,0x1f,0x97,0xe1] @ CHECK: ldrexd r6, r7, [r8] @ encoding: [0x9f,0x6f,0xb8,0xe1] + at ------------------------------------------------------------------------------ +@ LDRHT + at ------------------------------------------------------------------------------ + ldrhthi r8, [r11], #-0 + ldrhthi r8, [r11], #0 + +@ CHECK: ldrhthi r8, [r11], #-0 @ encoding: [0xb0,0x80,0x7b,0x80] +@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80] @------------------------------------------------------------------------------ @ FIXME: LSL From criswell at uiuc.edu Mon Aug 29 12:17:57 2011 From: criswell at uiuc.edu (John Criswell) Date: Mon, 29 Aug 2011 17:17:57 -0000 Subject: [llvm-commits] [poolalloc] r138740 - /poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Message-ID: <20110829171757.0D0A92A6C12E@llvm.org> Author: criswell Date: Mon Aug 29 12:17:56 2011 New Revision: 138740 URL: http://llvm.org/viewvc/llvm-project?rev=138740&view=rev Log: Refactored the CloneAuxIntoGlobal() to remove quadratic behavior. This reduces the time spent on a test case from OpenSSH on Mac OS X from intolerable time (+1 hour, if I recall correctly) to 7 minutes of analysis time. Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=138740&r1=138739&r2=138740&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Mon Aug 29 12:17:56 2011 @@ -489,6 +489,11 @@ return MyID; // == Min } + bool compareDSCallSites (const DSCallSite & DS1, const DSCallSite & DS2) { + return (DS1.getCallSite().getCalledValue() < + DS2.getCallSite().getCalledValue()); + } + // // Method: CloneAuxIntoGlobal() // @@ -500,48 +505,105 @@ // site in its own list of unresolved call sites. // void BUDataStructures::CloneAuxIntoGlobal(DSGraph* G) { + // + // If this DSGraph has no unresolved call sites, do nothing. We do enough + // work that wastes time even when the list is empty that this extra check + // is probably worth it. + // + if (G->afc_begin() == G->afc_end()) + return; + DSGraph* GG = G->getGlobalsGraph(); ReachabilityCloner RC(GG, G, 0); // - // Scan through all unresolved call sites (call sites for which we do not yet - // know all of the callees) in the specified graph and see if the globals - // graph also has an unresolved call site for the same function pointer. If - // it does, merge them together; otherwise, just bring the unresolved call - // site into the global graph's set of unresolved call sites. + // Sort the lists of DSCallSites by the LLVM value that is used for the + // indirect call. // + G->getAuxFunctionCalls().sort (compareDSCallSites); + GG->getAuxFunctionCalls().sort (compareDSCallSites); + + // + // Determine which called values are both within the local graph DSCallsites + // and the global graph DSCallsites. Note that we require that the global + // graph have a DSNode for the called value. + // + std::set LocalCallValues; + std::set GlobalCallValues; + std::set CommonCallValues; for (DSGraph::afc_iterator ii = G->afc_begin(), ee = G->afc_end(); ii != ee; ++ii) { + Value * V = ii->getCallSite().getCalledValue(); + if (GG->hasNodeForValue(V)) { + LocalCallValues.insert (V); + } + } + + for (DSGraph::afc_iterator ii = GG->afc_begin(); + ii != GG->afc_end(); + ++ii) { + Value * V = ii->getCallSite().getCalledValue(); + GlobalCallValues.insert (V); + } + + std::set_intersection (LocalCallValues.begin(), LocalCallValues.end(), + GlobalCallValues.begin(), GlobalCallValues.end(), + std::inserter (CommonCallValues, + CommonCallValues.begin())); + LocalCallValues.clear(); + GlobalCallValues.clear(); + // + // Scan through all the unresolved call sites in the local graph for which + // the globals graph also considers the call site unresolved; merge such call + // sites together. + // + DSGraph::afc_iterator ii = G->afc_begin(); + DSGraph::afc_iterator GGii = GG->afc_begin(); + for (std::set::iterator iv = CommonCallValues.begin(); + iv != CommonCallValues.end(); + ++iv) { // - // If we can, merge with an existing call site for this instruction. + // Move the iterator in the local graph to the appropriate call site. + // In the process, if we see a call site that needs to be added to the + // globals graph, do that now. // - if (GG->hasNodeForValue(ii->getCallSite().getCalledValue())) { - // - // Determine whether the globals graph knows about this call site and - // consider it to be unresolved. - // - DSGraph::afc_iterator GGii; - for(GGii = GG->afc_begin(); GGii != GG->afc_end(); ++GGii) - if (GGii->getCallSite().getCalledValue() == - ii->getCallSite().getCalledValue()) - break; - - // - // If the globals graph knows about the call site, merge it in. - // Otherwise, just record it as an unresolved call site. - // - if (GGii != GG->afc_end()) - RC.cloneCallSite(*ii).mergeWith(*GGii); - else - GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); - } else { + Value * V = *iv; + while (ii->getCallSite().getCalledValue() != V) { GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); + ++ii; } + + // + // Move the iterator in the global graph to the appropriate call site. + // + while (GGii->getCallSite().getCalledValue() != V) + ++GGii; + + // + // Merge the two call sites together. + // + RC.cloneCallSite(*ii).mergeWith(*GGii); + + // + // Make sure not to repeat any merges. + // + ++ii; + ++GGii; + } + + // + // We've now merged all DSCallSites that were known both to the local graph + // and the globals graph. Now, there are still some local call sites that + // need to be *added* to the globals graph. Do that now. + // + for (; ii != G->afc_end(); ++ii) { + GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); } } + // // Description: // Inline all graphs in the callgraph and remove callsites that are completely From baldrick at free.fr Mon Aug 29 12:36:09 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 17:36:09 -0000 Subject: [llvm-commits] [dragonegg] r138743 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110829173609.D3EC32A6C131@llvm.org> Author: baldrick Date: Mon Aug 29 12:36:09 2011 New Revision: 138743 URL: http://llvm.org/viewvc/llvm-project?rev=138743&view=rev Log: Touch the minimum possible number of bytes when loading from/ storing to a bitfield. This fixes PR9448, a buffer overflow due to writing too much. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=138743&r1=138742&r2=138743&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Mon Aug 29 12:36:09 2011 @@ -2242,7 +2242,6 @@ LValue LV = EmitLV(exp); LV.Volatile = TREE_THIS_VOLATILE(exp); // TODO: Arrange for Volatile to already be set in the LValue. - Type *Ty = ConvertType(TREE_TYPE(exp)); unsigned Alignment = LV.getAlignment(); if (!LV.isBitfield()) { @@ -2250,72 +2249,43 @@ return LoadRegisterFromMemory(LV, TREE_TYPE(exp), Builder); } else { // This is a bitfield reference. + Type *Ty = getRegType(TREE_TYPE(exp)); if (!LV.BitSize) return Constant::getNullValue(Ty); - Type *ValTy = cast(LV.Ptr->getType())->getElementType(); - unsigned ValSizeInBits = ValTy->getPrimitiveSizeInBits(); - - // The number of loads needed to read the entire bitfield. - unsigned Strides = 1 + (LV.BitStart + LV.BitSize - 1) / ValSizeInBits; - - assert(ValTy->isIntegerTy() && "Invalid bitfield lvalue!"); - assert(ValSizeInBits > LV.BitStart && "Bad bitfield lvalue!"); - assert(ValSizeInBits >= LV.BitSize && "Bad bitfield lvalue!"); - assert(2*ValSizeInBits > LV.BitSize+LV.BitStart && "Bad bitfield lvalue!"); - - Value *Result = NULL; - - for (unsigned I = 0; I < Strides; I++) { - unsigned Index = BYTES_BIG_ENDIAN ? I : Strides - I - 1; // MSB first - unsigned ThisFirstBit = Index * ValSizeInBits; - unsigned ThisLastBitPlusOne = ThisFirstBit + ValSizeInBits; - if (ThisFirstBit < LV.BitStart) - ThisFirstBit = LV.BitStart; - if (ThisLastBitPlusOne > LV.BitStart+LV.BitSize) - ThisLastBitPlusOne = LV.BitStart+LV.BitSize; - - Value *Ptr = Index ? - Builder.CreateGEP(LV.Ptr, Builder.getInt32(Index)) : LV.Ptr; - LoadInst *LI = Builder.CreateLoad(Ptr, LV.Volatile); - LI->setAlignment(Alignment); - Value *Val = LI; - - unsigned BitsInVal = ThisLastBitPlusOne - ThisFirstBit; - unsigned FirstBitInVal = ThisFirstBit % ValSizeInBits; - - if (BYTES_BIG_ENDIAN) - FirstBitInVal = ValSizeInBits-FirstBitInVal-BitsInVal; - - // Mask the bits out by shifting left first, then shifting right. The - // LLVM optimizer will turn this into an AND if this is an unsigned - // expression. - - if (FirstBitInVal+BitsInVal != ValSizeInBits) { - Value *ShAmt = ConstantInt::get(ValTy, ValSizeInBits - - (FirstBitInVal+BitsInVal)); - Val = Builder.CreateShl(Val, ShAmt); - } - - // Shift right required? - if (ValSizeInBits != BitsInVal) { - bool AddSignBits = !TYPE_UNSIGNED(TREE_TYPE(exp)) && !Result; - Value *ShAmt = ConstantInt::get(ValTy, ValSizeInBits-BitsInVal); - Val = AddSignBits ? - Builder.CreateAShr(Val, ShAmt) : Builder.CreateLShr(Val, ShAmt); - } - - if (Result) { - Value *ShAmt = ConstantInt::get(ValTy, BitsInVal); - Result = Builder.CreateShl(Result, ShAmt); - Result = Builder.CreateOr(Result, Val); - } else { - Result = Val; - } - } - - return Builder.CreateIntCast(Result, getRegType(TREE_TYPE(exp)), - /*isSigned*/!TYPE_UNSIGNED(TREE_TYPE(exp))); + // Load the minimum number of bytes that covers the field. + unsigned LoadSizeInBits = LV.BitStart + LV.BitSize; + LoadSizeInBits = RoundUpToAlignment(LoadSizeInBits, BITS_PER_UNIT); + Type *LoadType = IntegerType::get(Context, LoadSizeInBits); + + // Load the bits. + Value *Ptr = Builder.CreateBitCast(LV.Ptr, LoadType->getPointerTo()); + Value *Val = Builder.CreateLoad(Ptr, LV.Volatile); + cast(Val)->setAlignment(Alignment); + + // Mask the bits out by shifting left first, then shifting right. The + // optimizers will turn this into an "and" in the unsigned case. + + // Shift the sign bit of the bitfield to the sign bit position in the loaded + // type. This zaps any extra bits occurring after the end of the bitfield. + unsigned FirstBitInVal = BYTES_BIG_ENDIAN ? + LoadSizeInBits - LV.BitStart - LV.BitSize : LV.BitStart; + if (FirstBitInVal + LV.BitSize != LoadSizeInBits) { + Value *ShAmt = ConstantInt::get(LoadType, LoadSizeInBits - + (FirstBitInVal + LV.BitSize)); + Val = Builder.CreateShl(Val, ShAmt); + } + // Shift the first bit of the bitfield to be bit zero. This zaps any extra + // bits that occurred before the start of the bitfield. In the signed case + // this also duplicates the sign bit, giving a sign extended value. + bool isSigned = !TYPE_UNSIGNED(TREE_TYPE(exp)); + Value *ShAmt = ConstantInt::get(LoadType, LoadSizeInBits - LV.BitSize); + Val = isSigned ? + Builder.CreateAShr(Val, ShAmt) : Builder.CreateLShr(Val, ShAmt); + + // Get the bits as a value of the correct type. + // FIXME: This assumes the result is an integer. + return Builder.CreateIntCast(Val, Ty, isSigned); } } @@ -5686,8 +5656,6 @@ FieldPtr = Builder.CreateBitCast(FieldPtr, FieldTy->getPointerTo()); } - assert(BitStart < 8 && "Bit offset not properly incorporated in the pointer"); - // The alignment is given by DECL_ALIGN. Be conservative and don't assume // that the field is properly aligned even if the type is not. LVAlign = MinAlign(LVAlign, DECL_ALIGN(FieldDecl) / 8); @@ -5696,103 +5664,21 @@ if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl))) FieldPtr = EmitFieldAnnotation(FieldPtr, FieldDecl); + // Make sure we return a pointer to the right type. + Type *EltTy = ConvertType(TREE_TYPE(exp)); + FieldPtr = Builder.CreateBitCast(FieldPtr, EltTy->getPointerTo()); + if (!isBitfield(FieldDecl)) { assert(BitStart == 0 && "Not a bitfield but not at a byte offset!"); - // Make sure we return a pointer to the right type. - Type *EltTy = ConvertType(TREE_TYPE(exp)); - FieldPtr = Builder.CreateBitCast(FieldPtr, EltTy->getPointerTo()); return LValue(FieldPtr, LVAlign); } - // If this is a bitfield, the declared type must be an integral type. - assert(FieldTy->isIntegerTy() && "Invalid bitfield"); - + assert(BitStart < 8 && "Bit offset not properly incorporated in the pointer"); assert(DECL_SIZE(FieldDecl) && TREE_CODE(DECL_SIZE(FieldDecl)) == INTEGER_CST && "Variable sized bitfield?"); unsigned BitfieldSize = TREE_INT_CST_LOW(DECL_SIZE(FieldDecl)); - - Type *LLVMFieldTy = - cast(FieldPtr->getType())->getElementType(); - - // If the LLVM notion of the field type contains the entire bitfield being - // accessed, use the LLVM type. This avoids pointer casts and other bad - // things that are difficult to clean up later. This occurs in cases like - // "struct X{ unsigned long long x:50; unsigned y:2; }" when accessing y. - // We want to access the field as a ulong, not as a uint with an offset. - if (LLVMFieldTy->isIntegerTy() && - LLVMFieldTy->getPrimitiveSizeInBits() >= BitStart + BitfieldSize && - LLVMFieldTy->getPrimitiveSizeInBits() == - TD.getTypeAllocSizeInBits(LLVMFieldTy)) - FieldTy = LLVMFieldTy; - else - // If the field result type T is a bool or some other curiously sized - // integer type, then not all bits may be accessible by advancing a T* - // and loading through it. For example, if the result type is i1 then - // only the first bit in each byte would be loaded. Even if T is byte - // sized like an i24 there may be trouble: incrementing a T* will move - // the position by 32 bits not 24, leaving the upper 8 of those 32 bits - // inaccessible. Avoid this by rounding up the size appropriately. - FieldTy = IntegerType::get(Context, TD.getTypeAllocSizeInBits(FieldTy)); - - assert(FieldTy->getPrimitiveSizeInBits() == - TD.getTypeAllocSizeInBits(FieldTy) && "Field type not sequential!"); - - // If this is a bitfield, the field may span multiple fields in the LLVM - // type. As such, cast the pointer to be a pointer to the declared type. - FieldPtr = Builder.CreateBitCast(FieldPtr, FieldTy->getPointerTo()); - - unsigned LLVMValueBitSize = FieldTy->getPrimitiveSizeInBits(); - // Finally, because bitfields can span LLVM fields, and because the start - // of the first LLVM field (where FieldPtr currently points) may be up to - // 63 bits away from the start of the bitfield), it is possible that - // *FieldPtr doesn't contain any of the bits for this bitfield. If needed, - // adjust FieldPtr so that it is close enough to the bitfield that - // *FieldPtr contains the first needed bit. Be careful to make sure that - // the pointer remains appropriately aligned. - if (BitStart >= LLVMValueBitSize) { - // In this case, we know that the alignment of the field is less than - // the size of the field. To get the pointer close enough, add some - // number of alignment units to the pointer. - unsigned ByteAlignment = TD.getABITypeAlignment(FieldTy); - // It is possible that an individual field is Packed. This information is - // not reflected in FieldTy. Check DECL_PACKED here. - if (DECL_PACKED(FieldDecl)) - ByteAlignment = 1; - assert(ByteAlignment*8 <= LLVMValueBitSize && "Unknown overlap case!"); - unsigned NumAlignmentUnits = BitStart/(ByteAlignment*8); - assert(NumAlignmentUnits && "Not adjusting pointer?"); - - // Compute the byte offset, and add it to the pointer. - unsigned ByteOffset = NumAlignmentUnits*ByteAlignment; - LVAlign = MinAlign(LVAlign, ByteOffset); - - Constant *Offset = ConstantInt::get(TD.getIntPtrType(Context), ByteOffset); - FieldPtr = Builder.CreatePtrToInt(FieldPtr, Offset->getType()); - FieldPtr = Builder.CreateAdd(FieldPtr, Offset); - FieldPtr = Builder.CreateIntToPtr(FieldPtr, FieldTy->getPointerTo()); - - // Adjust bitstart to account for the pointer movement. - BitStart -= ByteOffset*8; - - // Check that this worked. Note that the bitfield may extend beyond - // the end of *FieldPtr, for example because BitfieldSize is the same - // as LLVMValueBitSize but BitStart > 0. - assert(BitStart < LLVMValueBitSize && - BitStart+BitfieldSize < 2*LLVMValueBitSize && - "Couldn't get bitfield into value!"); - } - - // Okay, everything is good. Return this as a bitfield if we can't - // return it as a normal l-value. (e.g. "struct X { int X : 32 };" ). - LValue LV(FieldPtr, LVAlign); - if (BitfieldSize != LLVMValueBitSize || BitStart != 0) { - // Writing these fields directly rather than using the appropriate LValue - // constructor works around a miscompilation by gcc-4.4 in Release mode. - LV.BitStart = BitStart; - LV.BitSize = BitfieldSize; - } - return LV; + return LValue(FieldPtr, LVAlign, BitStart, BitfieldSize); } LValue TreeToLLVM::EmitLV_DECL(tree exp) { @@ -8494,77 +8380,44 @@ // Last case, this is a store to a bitfield, so we have to emit a // read/modify/write sequence. - if (!LV.BitSize) return; - unsigned Alignment = LV.getAlignment(); - - Type *ValTy = cast(LV.Ptr->getType())->getElementType(); - unsigned ValSizeInBits = ValTy->getPrimitiveSizeInBits(); - - // The number of stores needed to write the entire bitfield. - unsigned Strides = 1 + (LV.BitStart + LV.BitSize - 1) / ValSizeInBits; - - assert(ValTy->isIntegerTy() && "Invalid bitfield lvalue!"); - assert(ValSizeInBits > LV.BitStart && "Bad bitfield lvalue!"); - assert(ValSizeInBits >= LV.BitSize && "Bad bitfield lvalue!"); - assert(2*ValSizeInBits > LV.BitSize+LV.BitStart && "Bad bitfield lvalue!"); - - bool Signed = !TYPE_UNSIGNED(TREE_TYPE(lhs)); - RHS = CastToAnyType(RHS, Signed, ValTy, Signed); - - for (unsigned I = 0; I < Strides; I++) { - unsigned Index = BYTES_BIG_ENDIAN ? Strides - I - 1 : I; // LSB first - unsigned ThisFirstBit = Index * ValSizeInBits; - unsigned ThisLastBitPlusOne = ThisFirstBit + ValSizeInBits; - if (ThisFirstBit < LV.BitStart) - ThisFirstBit = LV.BitStart; - if (ThisLastBitPlusOne > LV.BitStart+LV.BitSize) - ThisLastBitPlusOne = LV.BitStart+LV.BitSize; - - Value *Ptr = Index ? - Builder.CreateGEP(LV.Ptr, Builder.getInt32(Index)) : LV.Ptr; - LoadInst *LI = Builder.CreateLoad(Ptr, LV.Volatile); - LI->setAlignment(Alignment); - Value *OldVal = LI; - Value *NewVal = RHS; - - unsigned BitsInVal = ThisLastBitPlusOne - ThisFirstBit; - unsigned FirstBitInVal = ThisFirstBit % ValSizeInBits; - - if (BYTES_BIG_ENDIAN) - FirstBitInVal = ValSizeInBits-FirstBitInVal-BitsInVal; - - // If not storing into the zero'th bit, shift the Src value to the left. - if (FirstBitInVal) { - Value *ShAmt = ConstantInt::get(ValTy, FirstBitInVal); - NewVal = Builder.CreateShl(NewVal, ShAmt); - } - - // Next, if this doesn't touch the top bit, mask out any bits that shouldn't - // be set in the result. - uint64_t MaskVal = 1; - MaskVal = ((MaskVal << BitsInVal)-1) << FirstBitInVal; - Constant *Mask = Builder.getInt64(MaskVal); - Mask = Builder.getFolder().CreateTruncOrBitCast(Mask, ValTy); - - if (FirstBitInVal+BitsInVal != ValSizeInBits) - NewVal = Builder.CreateAnd(NewVal, Mask); - - // Next, mask out the bits this bit-field should include from the old value. - Mask = Builder.getFolder().CreateNot(Mask); - OldVal = Builder.CreateAnd(OldVal, Mask); - - // Finally, merge the two together and store it. - NewVal = Builder.CreateOr(OldVal, NewVal); - - StoreInst *SI = Builder.CreateStore(NewVal, Ptr, LV.Volatile); - SI->setAlignment(Alignment); - - if (I + 1 < Strides) { - Value *ShAmt = ConstantInt::get(ValTy, BitsInVal); - RHS = Builder.CreateLShr(RHS, ShAmt); - } - } + // Load and store the minimum number of bytes that covers the field. + unsigned LoadSizeInBits = LV.BitStart + LV.BitSize; + LoadSizeInBits = RoundUpToAlignment(LoadSizeInBits, BITS_PER_UNIT); + Type *LoadType = IntegerType::get(Context, LoadSizeInBits); + + // Load the bits. + Value *Ptr = Builder.CreateBitCast(LV.Ptr, LoadType->getPointerTo()); + Value *Val = Builder.CreateLoad(Ptr, LV.Volatile); + cast(Val)->setAlignment(LV.getAlignment()); + + // Get the right-hand side as a value of the same type. + // FIXME: This assumes the right-hand side is an integer. + bool isSigned = !TYPE_UNSIGNED(TREE_TYPE(lhs)); + RHS = CastToAnyType(RHS, isSigned, LoadType, isSigned); + + // Shift the right-hand side so that its bits are in the right position. + unsigned FirstBitInVal = BYTES_BIG_ENDIAN ? + LoadSizeInBits - LV.BitStart - LV.BitSize : LV.BitStart; + if (FirstBitInVal) { + Value *ShAmt = ConstantInt::get(LoadType, FirstBitInVal); + RHS = Builder.CreateShl(RHS, ShAmt); + } + // Mask out any bits in the right-hand side that shouldn't be in the result. + // The lower bits are zero already, so this only changes bits off the end. + APInt Mask = APInt::getBitsSet(LoadSizeInBits, FirstBitInVal, + FirstBitInVal + LV.BitSize); + if (FirstBitInVal + LV.BitSize != LoadSizeInBits) + RHS = Builder.CreateAnd(RHS, ConstantInt::get(Context, Mask)); + + // Mask out those bits in the original value that are being replaced by the + // right-hand side. + Val = Builder.CreateAnd(Val, ConstantInt::get(Context, ~Mask)); + + // Finally, merge the two together and store it. + Val = Builder.CreateOr(Val, RHS); + StoreInst *SI = Builder.CreateStore(Val, Ptr, LV.Volatile); + SI->setAlignment(LV.getAlignment()); } From bruno.cardoso at gmail.com Mon Aug 29 12:51:24 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 29 Aug 2011 17:51:24 -0000 Subject: [llvm-commits] [llvm] r138744 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110829175124.984462A6C131@llvm.org> Author: bruno Date: Mon Aug 29 12:51:24 2011 New Revision: 138744 URL: http://llvm.org/viewvc/llvm-project?rev=138744&view=rev Log: Move non-intruction patterns to a more appropriate place! Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138744&r1=138743&r2=138744&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Aug 29 12:51:24 2011 @@ -119,9 +119,42 @@ // Non-instruction patterns //===----------------------------------------------------------------------===// +// A vector extract of the first f32 position is a subregister copy def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; +// A 128-bit subvector extract from the first 256-bit vector position +// is a subregister copy that needs no instruction. +def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))), + (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>; +def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))), + (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>; + +def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))), + (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>; +def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), + (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; + +def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))), + (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>; +def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))), + (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>; + +// A 128-bit subvector insert to the first 256-bit vector position +// is a subregister copy that needs no instruction. +def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)), + (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)), + (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)), + (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)), + (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)), + (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; +def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)), + (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; + // Implicitly promote a 32-bit scalar to a vector. def : Pat<(v4f32 (scalar_to_vector FR32:$src)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>; @@ -5951,20 +5984,6 @@ (VINSERTF128rr VR256:$src1, VR128:$src2, (INSERT_get_vinsertf128_imm VR256:$ins))>; -// Special COPY patterns -def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)), - (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; -def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)), - (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; -def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)), - (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; -def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)), - (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; -def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)), - (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; -def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)), - (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; - //===----------------------------------------------------------------------===// // VEXTRACTF128 - Extract packed floating-point values // @@ -6009,23 +6028,6 @@ (v32i8 VR256:$src1), (EXTRACT_get_vextractf128_imm VR128:$ext)))>; -// Special COPY patterns -def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))), - (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>; -def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))), - (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>; - -def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))), - (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>; -def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))), - (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>; - -def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))), - (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>; -def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))), - (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>; - - //===----------------------------------------------------------------------===// // VMASKMOV - Conditional SIMD Packed Loads and Stores // From matthewbg at google.com Mon Aug 29 12:54:20 2011 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Mon, 29 Aug 2011 17:54:20 -0000 Subject: [llvm-commits] [llvm] r138745 - /llvm/trunk/unittests/ADT/APFloatTest.cpp Message-ID: <20110829175420.D5A512A6C131@llvm.org> Author: matthewbg Date: Mon Aug 29 12:54:20 2011 New Revision: 138745 URL: http://llvm.org/viewvc/llvm-project?rev=138745&view=rev Log: Fix a test that wasn't testing the right thing. The APFloat "Zero" test was actually calling the APFloat(const fltSemantics &, integerPart) constructor, and EXPECT_EQ was treating 0 and -0 as equal. Modified: llvm/trunk/unittests/ADT/APFloatTest.cpp Modified: llvm/trunk/unittests/ADT/APFloatTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APFloatTest.cpp?rev=138745&r1=138744&r2=138745&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/APFloatTest.cpp (original) +++ llvm/trunk/unittests/ADT/APFloatTest.cpp Mon Aug 29 12:54:20 2011 @@ -34,11 +34,13 @@ namespace { TEST(APFloatTest, Zero) { - EXPECT_EQ(0.0f, APFloat(APFloat::IEEEsingle, 0.0f).convertToFloat()); - EXPECT_EQ(-0.0f, APFloat(APFloat::IEEEsingle, -0.0f).convertToFloat()); - - EXPECT_EQ(0.0, APFloat(APFloat::IEEEdouble, 0.0).convertToDouble()); - EXPECT_EQ(-0.0, APFloat(APFloat::IEEEdouble, -0.0).convertToDouble()); + EXPECT_EQ(0.0f, APFloat(0.0f).convertToFloat()); + EXPECT_EQ(-0.0f, APFloat(-0.0f).convertToFloat()); + EXPECT_TRUE(APFloat(-0.0f).isNegative()); + + EXPECT_EQ(0.0, APFloat(0.0).convertToDouble()); + EXPECT_EQ(-0.0, APFloat(-0.0).convertToDouble()); + EXPECT_TRUE(APFloat(-0.0).isNegative()); } TEST(APFloatTest, fromZeroDecimalString) { From resistor at mac.com Mon Aug 29 12:59:41 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 17:59:41 -0000 Subject: [llvm-commits] [llvm] r138746 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20110829175941.ABBB82A6C131@llvm.org> Author: resistor Date: Mon Aug 29 12:59:41 2011 New Revision: 138746 URL: http://llvm.org/viewvc/llvm-project?rev=138746&view=rev Log: Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=138746&r1=138745&r2=138746&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Aug 29 12:59:41 2011 @@ -908,10 +908,16 @@ } else if (isLd) { if (isAM2) { int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); - // LDR_PRE, LDR_POST, - BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) - .addReg(Base, RegState::Define) - .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); + // LDR_PRE, LDR_POST + if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) + .addReg(Base, RegState::Define) + .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); + } else { + BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) + .addReg(Base, RegState::Define) + .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); + } } else { int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; // t2LDR_PRE, t2LDR_POST From resistor at mac.com Mon Aug 29 13:02:40 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 18:02:40 -0000 Subject: [llvm-commits] [llvm] r138747 - /llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll Message-ID: <20110829180240.60E1E2A6C131@llvm.org> Author: resistor Date: Mon Aug 29 13:02:40 2011 New Revision: 138747 URL: http://llvm.org/viewvc/llvm-project?rev=138747&view=rev Log: Add testcase for r138746. Added: llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll Added: llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll?rev=138747&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll Mon Aug 29 13:02:40 2011 @@ -0,0 +1,34 @@ +; RUN: llc -O3 -mtriple=armv6-apple-darwin -relocation-model=pic < %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" + +define void @compdecomp() nounwind { +entry: + %heap = alloca [256 x i32], align 4 + br i1 undef, label %bb25.lr.ph, label %bb17 + +bb17: ; preds = %bb17, %entry + br label %bb17 + +bb25.lr.ph: ; preds = %entry + %0 = sdiv i32 undef, 2 + br label %bb5.i + +bb.i: ; preds = %bb5.i + %1 = shl nsw i32 %k_addr.0.i, 1 + %.sum8.i = add i32 %1, -1 + %2 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum8.i + %3 = load i32* %2, align 4 + br i1 false, label %bb5.i, label %bb4.i + +bb4.i: ; preds = %bb.i + %.sum10.i = add i32 %k_addr.0.i, -1 + %4 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum10.i + store i32 %3, i32* %4, align 4 + br label %bb5.i + +bb5.i: ; preds = %bb5.i, %bb4.i, %bb.i, %bb25.lr.ph + %k_addr.0.i = phi i32 [ %1, %bb4.i ], [ undef, %bb25.lr.ph ], [ undef, %bb5.i ], [ undef, %bb.i ] + %5 = icmp slt i32 %0, %k_addr.0.i + br i1 %5, label %bb5.i, label %bb.i +} From benny.kra at googlemail.com Mon Aug 29 13:14:15 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 29 Aug 2011 18:14:15 -0000 Subject: [llvm-commits] [llvm] r138748 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <20110829181415.D33882A6C12E@llvm.org> Author: d0k Date: Mon Aug 29 13:14:15 2011 New Revision: 138748 URL: http://llvm.org/viewvc/llvm-project?rev=138748&view=rev Log: Make GCC happy by adding parens. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=138748&r1=138747&r2=138748&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Aug 29 13:14:15 2011 @@ -1774,8 +1774,8 @@ PM->setDepth(this->top()->getDepth()+1); } else { - assert(PM->getPassManagerType() == PMT_ModulePassManager - || PM->getPassManagerType() == PMT_FunctionPassManager + assert((PM->getPassManagerType() == PMT_ModulePassManager + || PM->getPassManagerType() == PMT_FunctionPassManager) && "pushing bad pass manager to PMStack"); PM->setDepth(1); } From benny.kra at googlemail.com Mon Aug 29 13:14:17 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 29 Aug 2011 18:14:17 -0000 Subject: [llvm-commits] [llvm] r138749 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <20110829181417.B3E3F2A6C12F@llvm.org> Author: d0k Date: Mon Aug 29 13:14:17 2011 New Revision: 138749 URL: http://llvm.org/viewvc/llvm-project?rev=138749&view=rev Log: Dump with dbgs() instead of printf. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=138749&r1=138748&r2=138749&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Aug 29 13:14:17 2011 @@ -28,7 +28,6 @@ #include "llvm/Support/Mutex.h" #include "llvm/ADT/StringMap.h" #include -#include #include using namespace llvm; @@ -193,7 +192,7 @@ // Print passes managed by this manager void dumpPassStructure(unsigned Offset) { - llvm::dbgs() << std::string(Offset*2, ' ') << "BasicBlockPass Manager\n"; + llvm::dbgs().indent(Offset*2) << "BasicBlockPass Manager\n"; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { BasicBlockPass *BP = getContainedPass(Index); BP->dumpPassStructure(Offset + 1); @@ -349,7 +348,7 @@ // Print passes managed by this manager void dumpPassStructure(unsigned Offset) { - llvm::dbgs() << std::string(Offset*2, ' ') << "ModulePass Manager\n"; + llvm::dbgs().indent(Offset*2) << "ModulePass Manager\n"; for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) { ModulePass *MP = getContainedPass(Index); MP->dumpPassStructure(Offset + 1); @@ -1787,10 +1786,10 @@ void PMStack::dump() const { for (std::vector::const_iterator I = S.begin(), E = S.end(); I != E; ++I) - printf("%s ", (*I)->getAsPass()->getPassName()); + dbgs() << (*I)->getAsPass()->getPassName() << ' '; if (!S.empty()) - printf("\n"); + dbgs() << '\n'; } /// Find appropriate Module Pass Manager in the PM Stack and From grosbach at apple.com Mon Aug 29 13:22:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 18:22:04 -0000 Subject: [llvm-commits] [llvm] r138750 - /llvm/trunk/include/llvm/MC/MCInstrDesc.h Message-ID: <20110829182204.977E32A6C12E@llvm.org> Author: grosbach Date: Mon Aug 29 13:22:04 2011 New Revision: 138750 URL: http://llvm.org/viewvc/llvm-project?rev=138750&view=rev Log: Tidy up. 80 columns. Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=138750&r1=138749&r2=138750&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Mon Aug 29 13:22:04 2011 @@ -73,7 +73,7 @@ /// isLookupPtrRegClass - Set if this operand is a pointer value and it /// requires a callback to look up its register class. - bool isLookupPtrRegClass() const { return Flags&(1 < Author: efriedma Date: Mon Aug 29 13:23:02 2011 New Revision: 138751 URL: http://llvm.org/viewvc/llvm-project?rev=138751&view=rev Log: Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138751&r1=138750&r2=138751&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Aug 29 13:23:02 2011 @@ -596,6 +596,7 @@ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use // the default expansion. + // FIXME: This should be checking for v6k, not just v6. if (Subtarget->hasDataBarrier() || (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { // membarrier needs custom lowering; the rest are legal and handled Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=138751&r1=138750&r2=138751&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Mon Aug 29 13:23:02 2011 @@ -153,6 +153,9 @@ setOperationAction(ISD::JumpTable, MVT::i64, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setStackPointerRegisterToSaveRestore(Alpha::R30); setJumpBufSize(272); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=138751&r1=138750&r2=138751&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Aug 29 13:23:02 2011 @@ -178,6 +178,9 @@ setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setInsertFencesForAtomic(true); if (Subtarget->isSingleFloat()) Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=138751&r1=138750&r2=138751&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 29 13:23:02 2011 @@ -365,6 +365,9 @@ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); } + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setBooleanContents(ZeroOrOneBooleanContent); if (TM.getSubtarget().isPPC64()) { From isanbard at gmail.com Mon Aug 29 13:25:59 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 29 Aug 2011 18:25:59 -0000 Subject: [llvm-commits] [llvm] r138752 - /llvm/trunk/lib/MC/MCObjectFileInfo.cpp Message-ID: <20110829182559.8AD0D2A6C12E@llvm.org> Author: void Date: Mon Aug 29 13:25:59 2011 New Revision: 138752 URL: http://llvm.org/viewvc/llvm-project?rev=138752&view=rev Log: Initialize CompactUnwindSection so that other targets won't use an uninitialized value. Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=138752&r1=138751&r2=138752&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Mon Aug 29 13:25:59 2011 @@ -505,7 +505,8 @@ PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = TTypeEncoding = dwarf::DW_EH_PE_absptr; - EHFrameSection = 0; // Created on demand. + EHFrameSection = 0; // Created on demand. + CompactUnwindSection = 0; // Used only be select targets. Triple T(TT); Triple::ArchType Arch = T.getArch(); From wendling at apple.com Mon Aug 29 13:28:34 2011 From: wendling at apple.com (Bill Wendling) Date: Mon, 29 Aug 2011 11:28:34 -0700 Subject: [llvm-commits] [llvm] r138748 - /llvm/trunk/lib/VMCore/PassManager.cpp In-Reply-To: <20110829181415.D33882A6C12E@llvm.org> References: <20110829181415.D33882A6C12E@llvm.org> Message-ID: <9C94D1D0-EFD7-4B09-8E10-7BEBCE23F451@apple.com> On Aug 29, 2011, at 11:14 AM, Benjamin Kramer wrote: > Author: d0k > Date: Mon Aug 29 13:14:15 2011 > New Revision: 138748 > > URL: http://llvm.org/viewvc/llvm-project?rev=138748&view=rev > Log: > Make GCC happy by adding parens. > It makes me happy to. :-) -bw > Modified: > llvm/trunk/lib/VMCore/PassManager.cpp > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=138748&r1=138747&r2=138748&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Aug 29 13:14:15 2011 > @@ -1774,8 +1774,8 @@ > PM->setDepth(this->top()->getDepth()+1); > } > else { > - assert(PM->getPassManagerType() == PMT_ModulePassManager > - || PM->getPassManagerType() == PMT_FunctionPassManager > + assert((PM->getPassManagerType() == PMT_ModulePassManager > + || PM->getPassManagerType() == PMT_FunctionPassManager) > && "pushing bad pass manager to PMStack"); > PM->setDepth(1); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dag at cray.com Mon Aug 29 14:18:08 2011 From: dag at cray.com (David Greene) Date: Mon, 29 Aug 2011 14:18:08 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output Message-ID: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. --- Here's another updated version of the patch, including testcase. -Dave lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 62 ++++++++++++++++++++++++- test/CodeGen/X86/2011-08-29-BlockConstant.ll | 37 +++++++++++++++ 2 files changed, 96 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/X86/2011-08-29-BlockConstant.ll -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Compress-Repeated-Byte-Output.patch Type: text/x-patch Size: 5598 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/5d85d91a/attachment.bin From resistor at mac.com Mon Aug 29 14:36:44 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 19:36:44 -0000 Subject: [llvm-commits] [llvm] r138754 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/simple-fp-encoding.s Message-ID: <20110829193644.921212A6C12C@llvm.org> Author: resistor Date: Mon Aug 29 14:36:44 2011 New Revision: 138754 URL: http://llvm.org/viewvc/llvm-project?rev=138754&view=rev Log: Improve handling of #-0 offsets for many more pre-indexed addressing modes. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-arm-instructions.s llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138754&r1=138753&r2=138754&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 29 14:36:44 2011 @@ -638,7 +638,8 @@ // Immediate offset in range [-1020, 1020] and a multiple of 4. if (!Mem.OffsetImm) return true; int64_t Val = Mem.OffsetImm->getValue(); - return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0); + return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || + Val == INT32_MIN; } bool isMemRegOffset() const { if (Kind != Memory || !Mem.OffsetRegNum) @@ -709,7 +710,7 @@ // Immediate offset in range [-4095, 4095]. if (!Mem.OffsetImm) return true; int64_t Val = Mem.OffsetImm->getValue(); - return Val > -4096 && Val < 4096; + return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); } bool isPostIdxImm8() const { if (Kind != Immediate) @@ -2565,8 +2566,7 @@ Parser.Lex(); // Eat the '#'. E = Parser.getTok().getLoc(); - // FIXME: Special case #-0 so we can correctly set the U bit. - + bool isNegative = getParser().getTok().is(AsmToken::Minus); const MCExpr *Offset; if (getParser().ParseExpression(Offset)) return true; @@ -2578,6 +2578,11 @@ if (!CE) return Error (E, "constant expression expected"); + // If the constant was #-0, represent it as INT32_MIN. + int32_t Val = CE->getValue(); + if (isNegative && Val == 0) + CE = MCConstantExpr::Create(INT32_MIN, getContext()); + // Now we should have the closing ']' E = Parser.getTok().getLoc(); if (Parser.getTok().isNot(AsmToken::RBrac)) Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=138754&r1=138753&r2=138754&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Aug 29 14:36:44 2011 @@ -446,7 +446,9 @@ O << "[" << getRegisterName(MO1.getReg()); - if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) { + unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); + unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); + if (ImmOffs || Op == ARM_AM::sub) { O << ", #" << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) << ImmOffs * 4; Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138754&r1=138753&r2=138754&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Mon Aug 29 14:36:44 2011 @@ -432,8 +432,10 @@ bool isAdd = true; // Special value for #-0 - if (SImm == INT32_MIN) + if (SImm == INT32_MIN) { SImm = 0; + isAdd = false; + } // Immediate is always encoded as positive. The 'U' bit controls add vs sub. if (SImm < 0) { Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=138754&r1=138753&r2=138754&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Aug 29 14:36:44 2011 @@ -1884,6 +1884,14 @@ @ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1] @ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1] + at ------------------------------------------------------------------------------ +@ STR + at ------------------------------------------------------------------------------ + strpl r3, [r10, #-0]! + strpl r3, [r10, #0]! + +@ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55] +@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55] @------------------------------------------------------------------------------ @ SUB Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=138754&r1=138753&r2=138754&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Aug 29 14:36:44 2011 @@ -2,7 +2,7 @@ @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] vadd.f64 d16, d17, d16 - + @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] vadd.f32 s0, s1, s0 @@ -47,7 +47,7 @@ @ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] vabs.f32 s0, s0 - + @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 @@ -116,7 +116,7 @@ @ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] @ vmrs apsr_nzcv, fpscr - + @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 @@ -173,13 +173,13 @@ @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] vldr.64 d1, [r2, #32] vldr.64 d1, [r2, #-32] - + @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] vldr.64 d2, [r3] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] -@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed] vldr.64 d3, [pc] vldr.64 d3, [pc,#0] vldr.64 d3, [pc,#-0] @@ -191,13 +191,13 @@ @ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] vldr.32 s1, [r2, #32] vldr.32 s1, [r2, #-32] - + @ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] vldr.32 s2, [r3] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] -@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed] vldr.32 s5, [pc] vldr.32 s5, [pc,#0] vldr.32 s5, [pc,#-0] From bruno.cardoso at gmail.com Mon Aug 29 14:42:10 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 29 Aug 2011 19:42:10 -0000 Subject: [llvm-commits] [test-suite] r138755 - /test-suite/trunk/TEST.llc.Makefile Message-ID: <20110829194210.6A4602A6C12C@llvm.org> Author: bruno Date: Mon Aug 29 14:42:10 2011 New Revision: 138755 URL: http://llvm.org/viewvc/llvm-project?rev=138755&view=rev Log: llc "-f" option is long gone! Modified: test-suite/trunk/TEST.llc.Makefile Modified: test-suite/trunk/TEST.llc.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.llc.Makefile?rev=138755&r1=138754&r2=138755&view=diff ============================================================================== --- test-suite/trunk/TEST.llc.Makefile (original) +++ test-suite/trunk/TEST.llc.Makefile Mon Aug 29 14:42:10 2011 @@ -6,7 +6,7 @@ # ##===----------------------------------------------------------------------===## -LLC_OPTS = $(LLCFLAGS) -f -o=/dev/null -stats -time-passes +LLC_OPTS = $(LLCFLAGS) -o=/dev/null -stats -time-passes CURDIR := $(shell cd .; pwd) PROGDIR := $(PROJ_SRC_ROOT) RELDIR := $(subst $(PROGDIR),,$(CURDIR)) From greened at obbligato.org Mon Aug 29 14:55:37 2011 From: greened at obbligato.org (David A. Greene) Date: Mon, 29 Aug 2011 14:55:37 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <7A05FCBC-BAF7-4FCD-9ACD-F6BBA8C5AE6E@apple.com> (Chris Lattner's message of "Fri, 26 Aug 2011 16:39:36 -0700") References: <7A05FCBC-BAF7-4FCD-9ACD-F6BBA8C5AE6E@apple.com> Message-ID: Chris Lattner writes: > Also, you need a testcase. Already had it done. :) I posted it with the revised patch. -Dave From nadav.rotem at intel.com Mon Aug 29 14:58:37 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Mon, 29 Aug 2011 19:58:37 -0000 Subject: [llvm-commits] [llvm] r138756 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp lib/VMCore/Instructions.cpp test/Transforms/InstCombine/cast.ll Message-ID: <20110829195837.4FB312A6C12C@llvm.org> Author: nadav Date: Mon Aug 29 14:58:36 2011 New Revision: 138756 URL: http://llvm.org/viewvc/llvm-project?rev=138756&view=rev Log: Fixes following the CR by Chris and Duncan: Optimize chained bitcasts of the form A->B->A. Undo r138722 and change isEliminableCastPair to allow this case. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/test/Transforms/InstCombine/cast.ll Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=138756&r1=138755&r2=138756&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Aug 29 14:58:36 2011 @@ -51,12 +51,6 @@ if (C->isAllOnesValue() && !DestTy->isX86_MMXTy()) return Constant::getAllOnesValue(DestTy); - // Bitcast of Bitcast can be done using a single cast. - ConstantExpr *CE = dyn_cast(C); - if (CE && CE->getOpcode() == Instruction::BitCast) { - return ConstantExpr::getBitCast(CE->getOperand(0), DestTy); - } - // The code below only handles casts to vectors currently. VectorType *DestVTy = dyn_cast(DestTy); if (DestVTy == 0) Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=138756&r1=138755&r2=138756&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Mon Aug 29 14:58:36 2011 @@ -1659,11 +1659,6 @@ if (DestTy == Src->getType()) return ReplaceInstUsesWith(CI, Src); - // Bitcasts are transitive. - if (BitCastInst* BSrc = dyn_cast(Src)) { - return CastInst::Create(Instruction::BitCast, BSrc->getOperand(0), DestTy); - } - if (PointerType *DstPTy = dyn_cast(DestTy)) { PointerType *SrcPTy = cast(SrcTy); Type *DstElTy = DstPTy->getElementType(); Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=138756&r1=138755&r2=138756&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Aug 29 14:58:36 2011 @@ -2059,8 +2059,7 @@ /// If no such cast is permited, the function returns 0. unsigned CastInst::isEliminableCastPair( Instruction::CastOps firstOp, Instruction::CastOps secondOp, - Type *SrcTy, Type *MidTy, Type *DstTy, Type *IntPtrTy) -{ + Type *SrcTy, Type *MidTy, Type *DstTy, Type *IntPtrTy) { // Define the 144 possibilities for these two cast instructions. The values // in this matrix determine what to do in a given situation and select the // case in the switch below. The rows correspond to firstOp, the columns @@ -2113,12 +2112,16 @@ }; // If either of the casts are a bitcast from scalar to vector, disallow the - // merging. - if ((firstOp == Instruction::BitCast && - isa(SrcTy) != isa(MidTy)) || - (secondOp == Instruction::BitCast && - isa(MidTy) != isa(DstTy))) - return 0; // Disallowed + // merging. However, bitcast of A->B->A are allowed. + bool isFirstBitcast = (firstOp == Instruction::BitCast); + bool isSecondBitcast = (secondOp == Instruction::BitCast); + bool chainedBitcast = (SrcTy == DstTy && isFirstBitcast && isSecondBitcast); + + // Check if any of the bitcasts convert scalars<->vectors. + if ((isFirstBitcast && isa(SrcTy) != isa(MidTy)) || + (isSecondBitcast && isa(MidTy) != isa(DstTy))) + // Unless we are bitcasing to the original type, disallow optimizations. + if (!chainedBitcast) return 0; int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin] [secondOp-Instruction::CastOpsBegin]; Modified: llvm/trunk/test/Transforms/InstCombine/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast.ll?rev=138756&r1=138755&r2=138756&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast.ll Mon Aug 29 14:58:36 2011 @@ -632,15 +632,48 @@ define <4 x float> @test64(<4 x float> %c) nounwind { %t0 = bitcast <4 x float> %c to <4 x i32> - %t1 = bitcast <4 x i32> %t0 to <2 x double> - %t2 = bitcast <2 x double> %t1 to <4 x float> - ret <4 x float> %t2 + %t1 = bitcast <4 x i32> %t0 to <4 x float> + ret <4 x float> %t1 ; CHECK: @test64 ; CHECK-NEXT: ret <4 x float> %c } +define <4 x float> @test65(<4 x float> %c) nounwind { + %t0 = bitcast <4 x float> %c to <2 x double> + %t1 = bitcast <2 x double> %t0 to <4 x float> + ret <4 x float> %t1 +; CHECK: @test65 +; CHECK-NEXT: ret <4 x float> %c +} + +define <2 x float> @test66(<2 x float> %c) nounwind { + %t0 = bitcast <2 x float> %c to double + %t1 = bitcast double %t0 to <2 x float> + ret <2 x float> %t1 +; CHECK: @test66 +; CHECK-NEXT: ret <2 x float> %c +} + define float @test2c() { ret float extractelement (<2 x float> bitcast (double bitcast (<2 x float> to double) to <2 x float>), i32 0) ; CHECK: @test2c ; CHECK-NOT: extractelement } + +define i64 @test_mmx(<2 x i32> %c) nounwind { + %A = bitcast <2 x i32> %c to x86_mmx + %B = bitcast x86_mmx %A to <2 x i32> + %C = bitcast <2 x i32> %B to i64 + ret i64 %C +; CHECK: @test_mmx +; CHECK-NOT: x86_mmx +} + +define i64 @test_mmx_const(<2 x i32> %c) nounwind { + %A = bitcast <2 x i32> zeroinitializer to x86_mmx + %B = bitcast x86_mmx %A to <2 x i32> + %C = bitcast <2 x i32> %B to i64 + ret i64 %C +; CHECK: @test_mmx_const +; CHECK-NOT: x86_mmx +} From atrick at apple.com Mon Aug 29 15:12:53 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 29 Aug 2011 13:12:53 -0700 Subject: [llvm-commits] [zorg] r138711 - /zorg/trunk/zorg/buildbot/builders/ClangBuilder.py In-Reply-To: <20110827211857.29E1E2A6C13A@llvm.org> References: <20110827211857.29E1E2A6C13A@llvm.org> Message-ID: Thanks for fixing this. I was too busy looking at the red bots to check the green one. I also wanted to make sure llvm-x86_64-linux-vg_leak doesn't make noise about TableGen any more. My failed attempt at this was: + We don't care if tblgen leaks + Memcheck:Leak + obj:*/tblgen See r138652 where I tried to cleanup some XFAILS. I don't know anyone here with a working valgrind (unsupported on Lion). If you have any idea what's wrong with my syntax, I'll give it another try. -Andy On Aug 27, 2011, at 2:18 PM, Nick Lewycky wrote: > Author: nicholas > Date: Sat Aug 27 16:18:56 2011 > New Revision: 138711 > > URL: http://llvm.org/viewvc/llvm-project?rev=138711&view=rev > Log: > Pass the valgrind flag through to valgrind. Fixes: > lit.py: error: no such option: --suppressions > > Modified: > zorg/trunk/zorg/buildbot/builders/ClangBuilder.py > > Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py > URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=138711&r1=138710&r2=138711&view=diff > ============================================================================== > --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) > +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Sat Aug 27 16:18:56 2011 > @@ -130,7 +130,7 @@ > clangTestArgs += ' --vg' > if valgrindLeakCheck: > clangTestArgs += ' --vg-leak' > - clangTestArgs += ' --vg-arg --suppressions=%(builddir)s/llvm/tools/clang/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp --suppressions=%(builddir)s/llvm/utils/valgrind/x86_64-pc-linux-gnu.supp' > + clangTestArgs += ' --vg-arg --suppressions=%(builddir)s/llvm/tools/clang/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp --vg-arg --suppressions=%(builddir)s/llvm/utils/valgrind/x86_64-pc-linux-gnu.supp' > extraTestDirs = '' > if run_cxx_tests: > extraTestDirs += '%(builddir)s/llvm/tools/clang/utils/C++Tests' > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Mon Aug 29 15:16:50 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 20:16:50 -0000 Subject: [llvm-commits] [llvm] r138758 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <20110829201650.AC1CA2A6C12C@llvm.org> Author: resistor Date: Mon Aug 29 15:16:50 2011 New Revision: 138758 URL: http://llvm.org/viewvc/llvm-project?rev=138758&view=rev Log: addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=138758&r1=138757&r2=138758&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Aug 29 15:16:50 2011 @@ -133,6 +133,8 @@ SDValue &Offset, SDValue &Opc); bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc); + bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, + SDValue &Offset, SDValue &Opc); bool SelectAddrOffsetNone(SDValue N, SDValue &Base); bool SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); @@ -753,6 +755,19 @@ return true; } +bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, + SDValue &Offset, SDValue &Opc) { + int Val; + if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. + Offset = CurDAG->getRegister(0, MVT::i32); + Opc = CurDAG->getTargetConstant(Val, MVT::i32); + return true; + } + + return false; +} + + bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { unsigned Opcode = Op->getOpcode(); @@ -1319,9 +1334,13 @@ bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); unsigned Opcode = 0; bool Match = false; - if (LoadedVT == MVT::i32 && + if (LoadedVT == MVT::i32 && isPre && + SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) { + Opcode = ARM::LDR_PRE_IMM; + Match = true; + } else if (LoadedVT == MVT::i32 && !isPre && SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { - Opcode = isPre ? ARM::LDR_PRE_IMM : ARM::LDR_POST_IMM; + Opcode = ARM::LDR_POST_IMM; Match = true; } else if (LoadedVT == MVT::i32 && SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { @@ -1341,9 +1360,14 @@ Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; } } else { - if (SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { + if (isPre && + SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) { + Match = true; + Opcode = ARM::LDRB_PRE_IMM; + } else if (!isPre && + SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { Match = true; - Opcode = isPre ? ARM::LDRB_PRE_IMM : ARM::LDRB_POST_IMM; + Opcode = ARM::LDRB_POST_IMM; } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { Match = true; Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; From isanbard at gmail.com Mon Aug 29 15:39:23 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 29 Aug 2011 20:39:23 -0000 Subject: [llvm-commits] [llvm] r138759 - in /llvm/trunk/test/Transforms/SimplifyCFG: 2003-08-05-InvokeCrash.ll 2003-08-05-MishandleInvoke.ll 2005-10-02-InvokeSimplify.ll 2006-10-29-InvokeCrash.ll 2009-06-15-InvokeCrash.ll Message-ID: <20110829203923.F37FC2A6C12C@llvm.org> Author: void Date: Mon Aug 29 15:39:23 2011 New Revision: 138759 URL: http://llvm.org/viewvc/llvm-project?rev=138759&view=rev Log: Update tests to new EH model. Add landingpad instructions to landing pads. Modified: llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-InvokeCrash.ll llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-MishandleInvoke.ll llvm/trunk/test/Transforms/SimplifyCFG/2005-10-02-InvokeSimplify.ll llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll llvm/trunk/test/Transforms/SimplifyCFG/2009-06-15-InvokeCrash.ll Modified: llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-InvokeCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-InvokeCrash.ll?rev=138759&r1=138758&r2=138759&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-InvokeCrash.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-InvokeCrash.ll Mon Aug 29 15:39:23 2011 @@ -8,6 +8,9 @@ Ret: ; preds = %0 ret i32 %A Ret2: ; preds = %0 + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null ret i32 undef } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-MishandleInvoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-MishandleInvoke.ll?rev=138759&r1=138758&r2=138759&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-MishandleInvoke.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2003-08-05-MishandleInvoke.ll Mon Aug 29 15:39:23 2011 @@ -6,7 +6,10 @@ invoke i32 @test( ) to label %Ret unwind label %Ret ; :1 [#uses=0] Ret: ; preds = %0, %0 + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null %A = add i32 0, 1 ; [#uses=1] ret i32 %A } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SimplifyCFG/2005-10-02-InvokeSimplify.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2005-10-02-InvokeSimplify.ll?rev=138759&r1=138758&r2=138759&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2005-10-02-InvokeSimplify.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2005-10-02-InvokeSimplify.ll Mon Aug 29 15:39:23 2011 @@ -4,6 +4,8 @@ %X = invoke i1 @foo( ) to label %N unwind label %F ; [#uses=1] F: ; preds = %0 + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null ret i1 false N: ; preds = %0 br i1 %X, label %A, label %B @@ -13,3 +15,4 @@ ret i1 true } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll?rev=138759&r1=138758&r2=138759&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll Mon Aug 29 15:39:23 2011 @@ -275,12 +275,16 @@ invoke void @_ZN12QFontMetricsD1Ev( %struct.QFontMetrics* %tmp.upgrd.2 ) to label %cleanup171 unwind label %cleanup173 cleanup168: ; preds = %invcont151, %invcont148, %invcont146 + %val168 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN12QFontMetricsD1Ev( %struct.QFontMetrics* %tmp.upgrd.2 ) to label %cleanup173 unwind label %cleanup173 cleanup171: ; preds = %invcont153 invoke void @_ZN5QFontD1Ev( %struct.QFont* %tmp.upgrd.3 ) to label %finally170 unwind label %cleanup192 cleanup173: ; preds = %cleanup168, %cleanup168, %invcont153, %invcont144 + %val173 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN5QFontD1Ev( %struct.QFont* %tmp.upgrd.3 ) to label %cleanup192 unwind label %cleanup192 finally170: ; preds = %cleanup171 @@ -300,12 +304,16 @@ invoke void @_ZN5QFontD1Ev( %struct.QFont* %font ) to label %cleanup190 unwind label %cleanup192 cleanup187: ; preds = %invcont181, %invcont179, %invcont177 + %val187 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN5QFontD1Ev( %struct.QFont* %font ) to label %cleanup192 unwind label %cleanup192 cleanup190: ; preds = %cleanup185 invoke void @_ZN16QTextFrameFormatD1Ev( %struct.QTextBlockFormat* %fmt ) to label %cond_next194 unwind label %cleanup329 cleanup192: ; preds = %cleanup187, %cleanup187, %cleanup185, %finally170, %cleanup173, %cleanup173, %cleanup171, %invcont141, %invcont124, %invcont122, %invcont120, %invcont118, %invcont117, %invcont114, %invcont111 + %val192 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN16QTextFrameFormatD1Ev( %struct.QTextBlockFormat* %fmt ) to label %cleanup329 unwind label %cleanup329 cond_next194: ; preds = %cleanup190, %invcont83 @@ -450,6 +458,8 @@ call void @_ZN8QPainterD1Ev( %struct.QPainter* %p ) ret void cleanup329: ; preds = %cond_true319, %cond_true302, %cond_next293, %cond_true277, %cond_true266, %cond_next258, %cond_next244, %cond_next225, %cond_true220, %invcont210, %cond_next208, %cond_false204, %cond_true200, %cond_next194, %cleanup192, %cleanup192, %cleanup190, %invcont106, %invcont104, %invcont103, %invcont100, %invcont98, %invcont94, %cond_false, %invcont83, %invcont79, %invcont57, %invcont51, %invcont45, %cond_next42, %invcont37, %cond_true35, %invcont29, %invcont25, %cond_true24, %cond_next, %entry + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup call void @_ZN8QPainterD1Ev( %struct.QPainter* %p ) unwind } @@ -553,3 +563,5 @@ declare i1 @_ZN8QPrinter7newPageEv(%struct.QPrinter*) declare void @_ZN8QPainterD1Ev(%struct.QPainter*) + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SimplifyCFG/2009-06-15-InvokeCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2009-06-15-InvokeCrash.ll?rev=138759&r1=138758&r2=138759&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2009-06-15-InvokeCrash.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2009-06-15-InvokeCrash.ll Mon Aug 29 15:39:23 2011 @@ -277,12 +277,16 @@ invoke void @_ZN12QFontMetricsD1Ev( %struct.QFontMetrics* %tmp.upgrd.2 ) to label %cleanup171 unwind label %cleanup173 cleanup168: ; preds = %invcont151, %invcont148, %invcont146 + %val168 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN12QFontMetricsD1Ev( %struct.QFontMetrics* %tmp.upgrd.2 ) to label %cleanup173 unwind label %cleanup173 cleanup171: ; preds = %invcont153 invoke void @_ZN5QFontD1Ev( %struct.QFont* %tmp.upgrd.3 ) to label %finally170 unwind label %cleanup192 cleanup173: ; preds = %cleanup168, %cleanup168, %invcont153, %invcont144 + %val173 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN5QFontD1Ev( %struct.QFont* %tmp.upgrd.3 ) to label %cleanup192 unwind label %cleanup192 finally170: ; preds = %cleanup171 @@ -302,12 +306,16 @@ invoke void @_ZN5QFontD1Ev( %struct.QFont* %font ) to label %cleanup190 unwind label %cleanup192 cleanup187: ; preds = %invcont181, %invcont179, %invcont177 + %val187 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN5QFontD1Ev( %struct.QFont* %font ) to label %cleanup192 unwind label %cleanup192 cleanup190: ; preds = %cleanup185 invoke void @_ZN16QTextFrameFormatD1Ev( %struct.QTextBlockFormat* %fmt ) to label %cond_next194 unwind label %cleanup329 cleanup192: ; preds = %cleanup187, %cleanup187, %cleanup185, %finally170, %cleanup173, %cleanup173, %cleanup171, %invcont141, %invcont124, %invcont122, %invcont120, %invcont118, %invcont117, %invcont114, %invcont111 + %val192 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup invoke void @_ZN16QTextFrameFormatD1Ev( %struct.QTextBlockFormat* %fmt ) to label %cleanup329 unwind label %cleanup329 cond_next194: ; preds = %cleanup190, %invcont83 @@ -452,6 +460,8 @@ call void @_ZN8QPainterD1Ev( %struct.QPainter* %p ) ret void cleanup329: ; preds = %cond_true319, %cond_true302, %cond_next293, %cond_true277, %cond_true266, %cond_next258, %cond_next244, %cond_next225, %cond_true220, %invcont210, %cond_next208, %cond_false204, %cond_true200, %cond_next194, %cleanup192, %cleanup192, %cleanup190, %invcont106, %invcont104, %invcont103, %invcont100, %invcont98, %invcont94, %cond_false, %invcont83, %invcont79, %invcont57, %invcont51, %invcont45, %cond_next42, %invcont37, %cond_true35, %invcont29, %invcont25, %cond_true24, %cond_next, %entry + %val329 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup call void @_ZN8QPainterD1Ev( %struct.QPainter* %p ) unwind } @@ -555,3 +565,5 @@ declare i1 @_ZN8QPrinter7newPageEv(%struct.QPrinter*) declare void @_ZN8QPainterD1Ev(%struct.QPainter*) + +declare i32 @__gxx_personality_v0(...) From resistor at mac.com Mon Aug 29 15:42:00 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 20:42:00 -0000 Subject: [llvm-commits] [llvm] r138760 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110829204200.6DB222A6C12C@llvm.org> Author: resistor Date: Mon Aug 29 15:42:00 2011 New Revision: 138760 URL: http://llvm.org/viewvc/llvm-project?rev=138760&view=rev Log: Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138760&r1=138759&r2=138760&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 29 15:42:00 2011 @@ -1507,6 +1507,7 @@ let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = 0b1111; let Inst{11-0} = shift{11-0}; + let Inst{4} = 0; } } From krasin at chromium.org Mon Aug 29 15:58:32 2011 From: krasin at chromium.org (Ivan Krasin) Date: Mon, 29 Aug 2011 13:58:32 -0700 Subject: [llvm-commits] [PATCH]llvm-ld: add support of deps with the specific version (like liblzma.so.1.0.0) Message-ID: Hi llvm team! This CL adds support of deps which does not end with ".so" to llvm-ld. It happens (for example) when you want to have a dependency on the .so with the specific version, like liblzma.so.1.0.0 or libcrypto.so.0.9.8. The patch is attached and is also available online: http://codereview.chromium.org/7793002/ Please, let me know if it's fine to commit. -- krasin -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_ld_1.diff Type: text/x-patch Size: 715 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/b8976151/attachment.bin From baldrick at free.fr Mon Aug 29 15:59:50 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 22:59:50 +0200 Subject: [llvm-commits] [llvm] r138756 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCasts.cpp lib/VMCore/Instructions.cpp test/Transforms/InstCombine/cast.ll In-Reply-To: <20110829195837.4FB312A6C12C@llvm.org> References: <20110829195837.4FB312A6C12C@llvm.org> Message-ID: <4E5BFDC6.8040907@free.fr> Hi Nadav, > --- llvm/trunk/lib/VMCore/Instructions.cpp (original) > +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Aug 29 14:58:36 2011 > @@ -2059,8 +2059,7 @@ > /// If no such cast is permited, the function returns 0. > unsigned CastInst::isEliminableCastPair( > Instruction::CastOps firstOp, Instruction::CastOps secondOp, > - Type *SrcTy, Type *MidTy, Type *DstTy, Type *IntPtrTy) > -{ > + Type *SrcTy, Type *MidTy, Type *DstTy, Type *IntPtrTy) { > // Define the 144 possibilities for these two cast instructions. The values > // in this matrix determine what to do in a given situation and select the > // case in the switch below. The rows correspond to firstOp, the columns > @@ -2113,12 +2112,16 @@ > }; > > // If either of the casts are a bitcast from scalar to vector, disallow the > - // merging. > - if ((firstOp == Instruction::BitCast&& > - isa(SrcTy) != isa(MidTy)) || > - (secondOp == Instruction::BitCast&& > - isa(MidTy) != isa(DstTy))) > - return 0; // Disallowed > + // merging. However, bitcast of A->B->A are allowed. > + bool isFirstBitcast = (firstOp == Instruction::BitCast); > + bool isSecondBitcast = (secondOp == Instruction::BitCast); > + bool chainedBitcast = (SrcTy == DstTy&& isFirstBitcast&& isSecondBitcast); if they are both bitcasts I don't see why you need to require SrcTy == DstTy as well. > + > + // Check if any of the bitcasts convert scalars<->vectors. > + if ((isFirstBitcast&& isa(SrcTy) != isa(MidTy)) || > + (isSecondBitcast&& isa(MidTy) != isa(DstTy))) > + // Unless we are bitcasing to the original type, disallow optimizations. bitcasing -> bitcasting > + if (!chainedBitcast) return 0; > > int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin] > [secondOp-Instruction::CastOpsBegin]; Ciao, Duncan. From baldrick at free.fr Mon Aug 29 16:01:28 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 29 Aug 2011 23:01:28 +0200 Subject: [llvm-commits] [llvm] r138752 - /llvm/trunk/lib/MC/MCObjectFileInfo.cpp In-Reply-To: <20110829182559.8AD0D2A6C12E@llvm.org> References: <20110829182559.8AD0D2A6C12E@llvm.org> Message-ID: <4E5BFE28.6060801@free.fr> Hi Bill, > --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) > +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Mon Aug 29 13:25:59 2011 > @@ -505,7 +505,8 @@ > PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = > TTypeEncoding = dwarf::DW_EH_PE_absptr; > > - EHFrameSection = 0; // Created on demand. > + EHFrameSection = 0; // Created on demand. > + CompactUnwindSection = 0; // Used only be select targets. only be -> only by Probably also: select targets -> selected targets Ciao, Duncan. > > Triple T(TT); > Triple::ArchType Arch = T.getArch(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Aug 29 16:03:12 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 29 Aug 2011 21:03:12 -0000 Subject: [llvm-commits] [llvm] r138764 - /llvm/trunk/lib/MC/MCObjectFileInfo.cpp Message-ID: <20110829210312.9318C2A6C12E@llvm.org> Author: void Date: Mon Aug 29 16:03:12 2011 New Revision: 138764 URL: http://llvm.org/viewvc/llvm-project?rev=138764&view=rev Log: Fix grammar, noticed by Duncan. Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=138764&r1=138763&r2=138764&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Mon Aug 29 16:03:12 2011 @@ -506,7 +506,7 @@ TTypeEncoding = dwarf::DW_EH_PE_absptr; EHFrameSection = 0; // Created on demand. - CompactUnwindSection = 0; // Used only be select targets. + CompactUnwindSection = 0; // Used only by selected targets. Triple T(TT); Triple::ArchType Arch = T.getArch(); From wendling at apple.com Mon Aug 29 16:04:59 2011 From: wendling at apple.com (Bill Wendling) Date: Mon, 29 Aug 2011 14:04:59 -0700 Subject: [llvm-commits] [llvm] r138752 - /llvm/trunk/lib/MC/MCObjectFileInfo.cpp In-Reply-To: <4E5BFE28.6060801@free.fr> References: <20110829182559.8AD0D2A6C12E@llvm.org> <4E5BFE28.6060801@free.fr> Message-ID: <1BE786B0-0771-4F19-BA9C-84EAECFE7062@apple.com> On Aug 29, 2011, at 2:01 PM, Duncan Sands wrote: > Hi Bill, > >> --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) >> +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Mon Aug 29 13:25:59 2011 >> @@ -505,7 +505,8 @@ >> PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = >> TTypeEncoding = dwarf::DW_EH_PE_absptr; >> >> - EHFrameSection = 0; // Created on demand. >> + EHFrameSection = 0; // Created on demand. >> + CompactUnwindSection = 0; // Used only be select targets. > > only be -> only by > Probably also: select targets -> selected targets > What say you? Is well no English? :-) -bw From resistor at mac.com Mon Aug 29 16:14:19 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 21:14:19 -0000 Subject: [llvm-commits] [llvm] r138766 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20110829211419.E38842A6C12C@llvm.org> Author: resistor Date: Mon Aug 29 16:14:19 2011 New Revision: 138766 URL: http://llvm.org/viewvc/llvm-project?rev=138766&view=rev Log: Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=138766&r1=138765&r2=138766&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Aug 29 16:14:19 2011 @@ -907,13 +907,14 @@ getKillRegState(MO.isKill()))); } else if (isLd) { if (isAM2) { - int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); // LDR_PRE, LDR_POST if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { + int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes; BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) .addReg(Base, RegState::Define) .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); } else { + int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) .addReg(Base, RegState::Define) .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); From grosbach at apple.com Mon Aug 29 16:15:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 21:15:21 -0000 Subject: [llvm-commits] [llvm] r138767 - /llvm/trunk/include/llvm/Support/SMLoc.h Message-ID: <20110829211521.16EC92A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 16:15:20 2011 New Revision: 138767 URL: http://llvm.org/viewvc/llvm-project?rev=138767&view=rev Log: Tidy up. Whitespace. Modified: llvm/trunk/include/llvm/Support/SMLoc.h Modified: llvm/trunk/include/llvm/Support/SMLoc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SMLoc.h?rev=138767&r1=138766&r2=138767&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SMLoc.h (original) +++ llvm/trunk/include/llvm/Support/SMLoc.h Mon Aug 29 16:15:20 2011 @@ -18,19 +18,19 @@ namespace llvm { // SMLoc - Represents a location in source code. -class SMLoc { +class SMLoc { const char *Ptr; public: SMLoc() : Ptr(0) {} SMLoc(const SMLoc &RHS) : Ptr(RHS.Ptr) {} - + bool isValid() const { return Ptr != 0; } - + bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; } bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; } - + const char *getPointer() const { return Ptr; } - + static SMLoc getFromPointer(const char *Ptr) { SMLoc L; L.Ptr = Ptr; From eli.friedman at gmail.com Mon Aug 29 16:15:46 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 29 Aug 2011 21:15:46 -0000 Subject: [llvm-commits] [llvm] r138768 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/uint_to_fp-2.ll Message-ID: <20110829211546.AB8302A6C12C@llvm.org> Author: efriedma Date: Mon Aug 29 16:15:46 2011 New Revision: 138768 URL: http://llvm.org/viewvc/llvm-project?rev=138768&view=rev Log: Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/uint_to_fp-2.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138768&r1=138767&r2=138768&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 29 16:15:46 2011 @@ -7713,6 +7713,9 @@ SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Op.getOperand(0)); + // Zero out the upper parts of the register. + Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG); + Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), DAG.getIntPtrConstant(0)); Modified: llvm/trunk/test/CodeGen/X86/uint_to_fp-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/uint_to_fp-2.ll?rev=138768&r1=138767&r2=138768&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/uint_to_fp-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/uint_to_fp-2.ll Mon Aug 29 16:15:46 2011 @@ -1,8 +1,33 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1 -; rdar://6504833 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -define float @f(i32 %x) nounwind readnone { +; rdar://6504833 +define float @test1(i32 %x) nounwind readnone { +; CHECK: test1 +; CHECK: movd +; CHECK: orpd +; CHECK: subsd +; CHECK: cvtsd2ss +; CHECK: movss +; CHECK: flds +; CHECK: ret entry: %0 = uitofp i32 %x to float ret float %0 } + +; PR10802 +define float @test2(<4 x i32> %x) nounwind readnone ssp { +; CHECK: test2 +; CHECK: xorps [[ZERO:%xmm[0-9]+]] +; CHECK: movss {{.*}}, [[ZERO]] +; CHECK: orps +; CHECK: subsd +; CHECK: cvtsd2ss +; CHECK: movss +; CHECK: flds +; CHECK: ret +entry: + %vecext = extractelement <4 x i32> %x, i32 0 + %conv = uitofp i32 %vecext to float + ret float %conv +} From atrick at apple.com Mon Aug 29 16:25:05 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 29 Aug 2011 14:25:05 -0700 Subject: [llvm-commits] Pass manager bug fix In-Reply-To: <27F465BDABE6954AABB2A4E3599BDAC702A49D213F@sausexmbp02.amd.com> References: <27F465BDABE6954AABB2A4E3599BDAC702A49D213F@sausexmbp02.amd.com> Message-ID: <1FE8E4D9-9E82-4796-9446-7664120CF0FE@apple.com> Checked in as r138737. Thanks for the fix! -Andy On Aug 25, 2011, at 3:25 PM, Guo, Xiaoyi wrote: > Please review the attached fix for a problem in the pass manager, and commit if acceptable. The fix is against TOT and has passed regression tests. > > The problem is in the assignPassManager() methods. For example, in LoopPass::assignPassManager(): > > // Create new Loop Pass Manager if it does not exist. > assert (!PMS.empty() && "Unable to create Loop Pass Manager"); > PMDataManager *PMD = PMS.top(); > > // [1] Create new Call Graph Pass Manager > LPPM = new LPPassManager(); > LPPM->populateInheritedAnalysis(PMS); > > // [2] Set up new manager's top level manager > PMTopLevelManager *TPM = PMD->getTopLevelManager(); > TPM->addIndirectPassManager(LPPM); > > // [3] Assign manager to manage this new manager. This may create > // and push new managers into PMS > Pass *P = LPPM->getAsPass(); > TPM->schedulePass(P); > > // [4] Push new manager into PMS > PMS.push(LPPM); > > > Step 3 above may create and push new managers into PMS, in which case the Depth of LPPM will no longer be correct. This may in turn cause other things to go wrong. For example, it may cause some analysis passes to be freed prematurely and cause crash. > > My fix is to not set the depth of a pass manager until it is pushed onto the stack. > > Regards, > Xiaoyi > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/d177797f/attachment.html From Xiaoyi.Guo at amd.com Mon Aug 29 16:27:12 2011 From: Xiaoyi.Guo at amd.com (Guo, Xiaoyi) Date: Mon, 29 Aug 2011 16:27:12 -0500 Subject: [llvm-commits] Pass manager bug fix In-Reply-To: <1FE8E4D9-9E82-4796-9446-7664120CF0FE@apple.com> References: <27F465BDABE6954AABB2A4E3599BDAC702A49D213F@sausexmbp02.amd.com> <1FE8E4D9-9E82-4796-9446-7664120CF0FE@apple.com> Message-ID: <27F465BDABE6954AABB2A4E3599BDAC702A49D2AA7@sausexmbp02.amd.com> Thank you ! Xiaoyi From: Andrew Trick [mailto:atrick at apple.com] Sent: Monday, August 29, 2011 2:25 PM To: Guo, Xiaoyi Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] Pass manager bug fix Checked in as r138737. Thanks for the fix! -Andy On Aug 25, 2011, at 3:25 PM, Guo, Xiaoyi wrote: Please review the attached fix for a problem in the pass manager, and commit if acceptable. The fix is against TOT and has passed regression tests. The problem is in the assignPassManager() methods. For example, in LoopPass::assignPassManager(): // Create new Loop Pass Manager if it does not exist. assert (!PMS.empty() && "Unable to create Loop Pass Manager"); PMDataManager *PMD = PMS.top(); // [1] Create new Call Graph Pass Manager LPPM = new LPPassManager(); LPPM->populateInheritedAnalysis(PMS); // [2] Set up new manager's top level manager PMTopLevelManager *TPM = PMD->getTopLevelManager(); TPM->addIndirectPassManager(LPPM); // [3] Assign manager to manage this new manager. This may create // and push new managers into PMS Pass *P = LPPM->getAsPass(); TPM->schedulePass(P); // [4] Push new manager into PMS PMS.push(LPPM); Step 3 above may create and push new managers into PMS, in which case the Depth of LPPM will no longer be correct. This may in turn cause other things to go wrong. For example, it may cause some analysis passes to be freed prematurely and cause crash. My fix is to not set the depth of a pass manager until it is pushed onto the stack. Regards, Xiaoyi _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/d88db27c/attachment-0001.html From enderby at apple.com Mon Aug 29 17:06:29 2011 From: enderby at apple.com (Kevin Enderby) Date: Mon, 29 Aug 2011 22:06:29 -0000 Subject: [llvm-commits] [llvm] r138771 - in /llvm/trunk: test/MC/Disassembler/X86/x86-32.txt utils/TableGen/X86RecognizableInstr.cpp Message-ID: <20110829220629.14C372A6C12C@llvm.org> Author: enderby Date: Mon Aug 29 17:06:28 2011 New Revision: 138771 URL: http://llvm.org/viewvc/llvm-project?rev=138771&view=rev Log: Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=138771&r1=138770&r2=138771&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon Aug 29 17:06:28 2011 @@ -24,3 +24,6 @@ # CHECK: pshufb 0x0f 0x38 0x00 0xc0 + +# CHECK: crc32b %al, %eax +0xf2 0x0f 0x38 0xf0 0xc0 Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=138771&r1=138770&r2=138771&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Aug 29 17:06:28 2011 @@ -68,7 +68,7 @@ DC = 7, DD = 8, DE = 9, DF = 10, XD = 11, XS = 12, T8 = 13, P_TA = 14, - A6 = 15, A7 = 16 + A6 = 15, A7 = 16, TF = 17 }; } @@ -257,7 +257,7 @@ } void RecognizableInstr::processInstr(DisassemblerTables &tables, - const CodeGenInstruction &insn, + const CodeGenInstruction &insn, InstrUID uid) { // Ignore "asm parser only" instructions. @@ -805,6 +805,7 @@ opcodeToSet = Opcode; break; case X86Local::T8: + case X86Local::TF: opcodeType = THREEBYTE_38; if (needsModRMForDecode(Form)) filter = new ModFilter(isRegFormat(Form)); From aaron at aaronballman.com Mon Aug 29 17:09:07 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Mon, 29 Aug 2011 17:09:07 -0500 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References:

Message-ID: Ping? On Tue, Aug 23, 2011 at 5:27 PM, Aaron Ballman wrote: > On Tue, Aug 23, 2011 at 5:58 AM, NAKAMURA Takumi wrote: >> Aaron, about Threading.diff, >> >> + ? ? ?(void)::WaitForSingleObject(param.evt, INFINITE); >> >> I guess thread object might be the signal object. You may wait for hThread. > > Good catch! ?You're right, the thread will suffice. ?I've attached an > updated patch which should be more straight-forward. > > Thanks! > > ~Aaron > From aaron at aaronballman.com Mon Aug 29 17:09:22 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Mon, 29 Aug 2011 17:09:22 -0500 Subject: [llvm-commits] [PATCH] Improved threading support on Windows In-Reply-To: References:

Message-ID: Ping? On Tue, Aug 23, 2011 at 5:19 PM, Aaron Ballman wrote: > On Tue, Aug 23, 2011 at 5:34 AM, NAKAMURA Takumi wrote: >> Good evening, Aaron! >> >> About lib/Support/Windows/RWMutex.inc; >> >> ?- Would you like to try describing rwmutex on windows xp? >> ? ?Oh yeah, I don't have any Windows XP hosts any more. :( > > In code or on the mailing list? > > Windows XP doesn't have slim reader/writer locks (they're a Vista and > up API). ?So the RWMutex object supports reader/writer locks when > possible, but fallsback on the more heavy-handed original > implementation, which uses vanilla critical section objects. ?This > implementation is correct on XP, just not as efficient as on Vista and > higher. ?On Vista and up, you can have multiple non-blocked readers at > once, but on XP you will only be able to have one reader at a time. > > If you'd like me to update the comments in the code, I certainly can. > >> ?- I think, rather to refer to kernel32.dll, GetModuleHandle(NULL) >> would be more enough. >> ? ?How do you think? > > I've never been too happy with that convention. ?While it would > certainly work because Kernel32 is mapped into every executable's > process space, I don't think the code would be as clear where the > functions are coming from. ?Also, there's no performance penalty for > calling LoadLibrary vs GetModuleHandle( NULL ) that I've ever heard > of. ?Since the library is already loaded into memory, the loader will > traverse the list of loaded modules in the PEB, see Kernel32 (early > on) and return the module handle from there. > >> ?- It would be happier for us to have generic "delayed dll resolver" >> for NT5.1-unavailable entries. >> ? ?I think it might be the global ctor. How do you think? > > That's not a bad idea. ?I did a quick search of the code base, and > this is the first case we're using lazy loading for OS APIs. ?My > personal feeling is: if we need to do this a second time, a helper API > could be designed to make this cleaner. ?But since this is only > happening once, the helper may be overkill. > >> ?- How about to split RWMutexImpl to Windows XP and higher? > > I originally looked into that, but it would be a larger change than I > was comfortable with. ?Right now, the Impl is a concrete class, and an > OS version split would require it to be a bridge. ?If you think it's a > better approach though, I can certainly tackle it. > >> ?- Could you consider unittests for rwmutex? > > Yes, I could probably write some up, at least for testing them on > Windows. ?Can you recommend where I should put the unit tests though > (I've not yet done something like this for LLVM). > > Thanks for the review! > > ~Aaron > From atrick at apple.com Mon Aug 29 17:20:20 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 29 Aug 2011 15:20:20 -0700 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: References: Message-ID: Can we call this ignoreStdErr instead of noStdErr, then add the command line option --ignore-stderr? ("noStdErr" could be misinterpreted as something like --quiet). I'm curious how you're currently setting litConfig.noStdErr. -Andy On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/3ad7001d/attachment.html From grosbach at apple.com Mon Aug 29 17:24:09 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 22:24:09 -0000 Subject: [llvm-commits] [llvm] r138773 - in /llvm/trunk: include/llvm/MC/MCInstrDesc.h lib/CodeGen/MachineInstr.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s test/MC/ARM/thumb2-diagnostics.s Message-ID: <20110829222409.96B8E2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 17:24:09 2011 New Revision: 138773 URL: http://llvm.org/viewvc/llvm-project?rev=138773&view=rev Log: Thumb2 parsing and encoding for IT blocks. Added: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s llvm/trunk/test/MC/ARM/thumb2-diagnostics.s Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=138773&r1=138772&r2=138773&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Mon Aug 29 17:24:09 2011 @@ -289,6 +289,18 @@ return Flags & (1 << MCID::Barrier); } + /// findFirstPredOperandIdx() - Find the index of the first operand in the + /// operand list that is used to represent the predicate. It returns -1 if + /// none is found. + int findFirstPredOperandIdx() const { + if (isPredicable()) { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) + if (OpInfo[i].isPredicate()) + return i; + } + return -1; + } + /// isTerminator - Returns true if this instruction part of the terminator for /// a basic block. Typically this is things like return and branch /// instructions. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=138773&r1=138772&r2=138773&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Aug 29 17:24:09 2011 @@ -942,6 +942,10 @@ /// operand list that is used to represent the predicate. It returns -1 if /// none is found. int MachineInstr::findFirstPredOperandIdx() const { + // Don't call MCID.findFirstPredOperandIdx() because this variant + // is sometimes called on an instruction that's not yet complete, and + // so the number of operands is less than the MCID indicates. In + // particular, the PTX target does this. const MCInstrDesc &MCID = getDesc(); if (MCID.isPredicable()) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138773&r1=138772&r2=138773&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Aug 29 17:24:09 2011 @@ -44,6 +44,28 @@ MCSubtargetInfo &STI; MCAsmParser &Parser; + struct { + ARMCC::CondCodes Cond; // Condition for IT block. + unsigned Mask:4; // Condition mask for instructions. + // Starting at first 1 (from lsb). + // '1' condition as indicated in IT. + // '0' inverse of condition (else). + // Count of instructions in IT block is + // 4 - trailingzeroes(mask) + + bool FirstCond; // Explicit flag for when we're parsing the + // First instruction in the IT block. It's + // implied in the mask, so needs special + // handling. + + unsigned CurPosition; // Current position in parsing of IT + // block. In range [0,3]. Initialized + // according to count of instructions in block. + // ~0U if no active IT block. + } ITState; + bool inITBlock() { return ITState.CurPosition != ~0U;} + + MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -165,6 +187,7 @@ public: enum ARMMatchResultTy { Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, + Match_RequiresNotITBlock, Match_RequiresV6, Match_RequiresThumb2 }; @@ -175,6 +198,9 @@ // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + + // Not in an ITBlock to start with. + ITState.CurPosition = ~0U; } // Implementation of the MCTargetAsmParser interface: @@ -3085,18 +3111,23 @@ // where the conditional bit0 is zero, the instruction post-processing // will adjust the mask accordingly. if (Mnemonic == "it") { + SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); + if (ITMask.size() > 3) { + Parser.EatToEndOfStatement(); + return Error(Loc, "too many conditions on IT instruction"); + } unsigned Mask = 8; for (unsigned i = ITMask.size(); i != 0; --i) { char pos = ITMask[i - 1]; if (pos != 't' && pos != 'e') { Parser.EatToEndOfStatement(); - return Error(NameLoc, "illegal IT instruction mask '" + ITMask + "'"); + return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); } Mask >>= 1; if (ITMask[i - 1] == 't') Mask |= 8; } - Operands.push_back(ARMOperand::CreateITMask(Mask, NameLoc)); + Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); } // FIXME: This is all a pretty gross hack. We should automatically handle @@ -3128,18 +3159,18 @@ } // Add the carry setting operand, if necessary. - // - // FIXME: It would be awesome if we could somehow invent a location such that - // match errors on this operand would print a nice diagnostic about how the - // 's' character in the mnemonic resulted in a CCOut operand. - if (CanAcceptCarrySet) + if (CanAcceptCarrySet) { + SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, - NameLoc)); + Loc)); + } // Add the predication code operand, if necessary. if (CanAcceptPredicationCode) { + SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + + CarrySetting); Operands.push_back(ARMOperand::CreateCondCode( - ARMCC::CondCodes(PredicationCode), NameLoc)); + ARMCC::CondCodes(PredicationCode), Loc)); } // Add the processor imod operand, if necessary. @@ -3261,10 +3292,57 @@ return false; } +// FIXME: We would really prefer to have MCInstrInfo (the wrapper around +// the ARMInsts array) instead. Getting that here requires awkward +// API changes, though. Better way? +namespace llvm { +extern MCInstrDesc ARMInsts[]; +} +static MCInstrDesc &getInstDesc(unsigned Opcode) { + return ARMInsts[Opcode]; +} + // FIXME: We would really like to be able to tablegen'erate this. bool ARMAsmParser:: validateInstruction(MCInst &Inst, const SmallVectorImpl &Operands) { + MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); + SMLoc Loc = Operands[0]->getStartLoc(); + // Check the IT block state first. + if (inITBlock()) { + unsigned bit = 1; + if (ITState.FirstCond) + ITState.FirstCond = false; + else + bit = (ITState.Mask >> (4 - ITState.CurPosition)) & 1; + // Increment our position in the IT block first thing, as we want to + // move forward even if we find an error in the IT block. + unsigned TZ = CountTrailingZeros_32(ITState.Mask); + if (++ITState.CurPosition == 4 - TZ) + ITState.CurPosition = ~0U; // Done with the IT block after this. + // The instruction must be predicable. + if (!MCID.isPredicable()) + return Error(Loc, "instructions in IT block must be predicable"); + unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); + unsigned ITCond = bit ? ITState.Cond : + ARMCC::getOppositeCondition(ITState.Cond); + if (Cond != ITCond) { + // Find the condition code Operand to get its SMLoc information. + SMLoc CondLoc; + for (unsigned i = 1; i < Operands.size(); ++i) + if (static_cast(Operands[i])->isCondCode()) + CondLoc = Operands[i]->getStartLoc(); + return Error(CondLoc, "incorrect condition in IT block; got '" + + StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + + "', but expected '" + + ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); + } + // Check for non-'al' condition codes outside of the IT block. + } else if (isThumbTwo() && MCID.isPredicable() && + Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != + ARMCC::AL) + return Error(Loc, "predicated instructions must be in IT block"); + switch (Inst.getOpcode()) { case ARM::LDRD: case ARM::LDRD_PRE: @@ -3413,29 +3491,28 @@ // so mask that in if needed MCOperand &MO = Inst.getOperand(1); unsigned Mask = MO.getImm(); + unsigned OrigMask = Mask; + unsigned TZ = CountTrailingZeros_32(Mask); if ((Inst.getOperand(0).getImm() & 1) == 0) { - unsigned TZ = CountTrailingZeros_32(Mask); assert(Mask && TZ <= 3 && "illegal IT mask value!"); for (unsigned i = 3; i != TZ; --i) Mask ^= 1 << i; } else Mask |= 0x10; MO.setImm(Mask); + + // Set up the IT block state according to the IT instruction we just + // matched. + assert(!inITBlock() && "nested IT blocks?!"); + ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); + ITState.Mask = OrigMask; // Use the original mask, not the updated one. + ITState.CurPosition = 0; + ITState.FirstCond = true; break; } } } -// FIXME: We would really prefer to have MCInstrInfo (the wrapper around -// the ARMInsts array) instead. Getting that here requires awkward -// API changes, though. Better way? -namespace llvm { -extern MCInstrDesc ARMInsts[]; -} -static MCInstrDesc &getInstDesc(unsigned Opcode) { - return ARMInsts[Opcode]; -} - unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { // 16-bit thumb arithmetic instructions either require or preclude the 'S' // suffix depending on whether they're in an IT block or not. @@ -3457,10 +3534,12 @@ return Match_MnemonicFail; // If we're parsing Thumb2, which form is legal depends on whether we're // in an IT block. - // FIXME: We don't yet do IT blocks, so just always consider it to be - // that we aren't in one until we do. - if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) + if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && + !inITBlock()) return Match_RequiresITBlock; + if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && + inITBlock()) + return Match_RequiresNotITBlock; } // Some high-register supporting Thumb1 encodings only allow both registers // to be from r0-r7 when in Thumb2. @@ -3518,6 +3597,8 @@ case Match_ConversionFail: // The converter function will have already emited a diagnostic. return true; + case Match_RequiresNotITBlock: + return Error(IDLoc, "flag setting instruction only valid outside IT block"); case Match_RequiresITBlock: return Error(IDLoc, "instruction only valid inside IT block"); case Match_RequiresV6: Added: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=138773&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (added) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Aug 29 17:24:09 2011 @@ -0,0 +1,32 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ For complex constructs like shifter operands, check more thoroughly for them +@ once then spot check that following instructions accept the form generally. +@ This gives us good coverage while keeping the overall size of the test +@ more reasonable. + + +@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax. + +_func: +@ CHECK: _func + + at ------------------------------------------------------------------------------ +@ IT + at ------------------------------------------------------------------------------ +@ Test encodings of a few full IT blocks, not just the IT instruction + + iteet eq + addeq r0, r1, r2 + nopne + subne r5, r6, r7 + addeq r1, r2, #4 + +@ CHECK: iteet eq @ encoding: [0x0d,0xbf] +@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18] +@ CHECK: nopne @ encoding: [0x00,0xbf] +@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] +@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] Added: llvm/trunk/test/MC/ARM/thumb2-diagnostics.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-diagnostics.s?rev=138773&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2-diagnostics.s (added) +++ llvm/trunk/test/MC/ARM/thumb2-diagnostics.s Mon Aug 29 17:24:09 2011 @@ -0,0 +1,30 @@ +@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +@ Ill-formed IT block instructions. + itet eq + addle r0, r1, r2 + nop + it le + iteeee gt + ittfe le + nopeq + +@ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq' +@ CHECK-ERRORS: addle r0, r1, r2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne' +@ CHECK-ERRORS: nop +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instructions in IT block must be predicable +@ CHECK-ERRORS: it le +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: too many conditions on IT instruction +@ CHECK-ERRORS: iteeee gt +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: illegal IT block condition mask 'tfe' +@ CHECK-ERRORS: ittfe le +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: predicated instructions must be in IT block +@ CHECK-ERRORS: nopeq +@ CHECK-ERRORS: ^ From grosbach at apple.com Mon Aug 29 18:00:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 23:00:19 -0000 Subject: [llvm-commits] [llvm] r138777 - /llvm/trunk/test/MC/ARM/thumb2_instructions.s Message-ID: <20110829230019.C3C1B2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 18:00:19 2011 New Revision: 138777 URL: http://llvm.org/viewvc/llvm-project?rev=138777&view=rev Log: Remove test file. Superceded by other more exhaustive tests. Removed: llvm/trunk/test/MC/ARM/thumb2_instructions.s Removed: llvm/trunk/test/MC/ARM/thumb2_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2_instructions.s?rev=138776&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2_instructions.s (original) +++ llvm/trunk/test/MC/ARM/thumb2_instructions.s (removed) @@ -1,14 +0,0 @@ -@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t -@ RUN: FileCheck < %t %s - -@ FIXME: This test is completely bogus. Replace it with real tests. -@ XFAIL: * - .syntax unified - .text - -@ FIXME: This is not the correct instruction representation, but at least we are -@ parsing the ldr to something. -@ -@ CHECK: ldr r0, [r7, #258] - ldr r0, [r7, #-8] - From grosbach at apple.com Mon Aug 29 18:01:39 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 23:01:39 -0000 Subject: [llvm-commits] [llvm] r138778 - /llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20110829230139.17A732A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 18:01:38 2011 New Revision: 138778 URL: http://llvm.org/viewvc/llvm-project?rev=138778&view=rev Log: Thumb2 assembly parsing and encoding support for ADC(immediate). Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=138778&r1=138777&r2=138778&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Aug 29 18:01:38 2011 @@ -15,6 +15,29 @@ @ CHECK: _func @------------------------------------------------------------------------------ +@ ADC (immediate) + at ------------------------------------------------------------------------------ + adc r0, r1, #4 + adcs r0, r1, #0 + adc r1, r2, #255 + adc r3, r7, #0x00550055 + adc r8, r12, #0xaa00aa00 + adc r9, r7, #0xa5a5a5a5 + adc r5, r3, #0x87000000 + adc r4, r2, #0x7f800000 + adc r4, r2, #0x00000680 + +@ CHECK: adc r0, r1, #4 @ encoding: [0x41,0xf1,0x04,0x00] +@ CHECK: adcs r0, r1, #0 @ encoding: [0x51,0xf1,0x00,0x00] +@ CHECK: adc r1, r2, #255 @ encoding: [0x42,0xf1,0xff,0x01] +@ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13] +@ CHECK: adc r8, r12, #2852170240 @ encoding: [0x4c,0xf1,0xaa,0x28] +@ CHECK: adc r9, r7, #2779096485 @ encoding: [0x47,0xf1,0xa5,0x39] +@ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45] +@ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44] +@ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64] + + at ------------------------------------------------------------------------------ @ IT @------------------------------------------------------------------------------ @ Test encodings of a few full IT blocks, not just the IT instruction From grosbach at apple.com Mon Aug 29 18:04:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 23:04:05 -0000 Subject: [llvm-commits] [llvm] r138779 - /llvm/trunk/test/MC/ARM/thumb2.s Message-ID: <20110829230405.29B9E2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 18:04:04 2011 New Revision: 138779 URL: http://llvm.org/viewvc/llvm-project?rev=138779&view=rev Log: Remove redundant tests from XFAIL'ed test file. Modified: llvm/trunk/test/MC/ARM/thumb2.s Modified: llvm/trunk/test/MC/ARM/thumb2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=138779&r1=138778&r2=138779&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2.s (original) +++ llvm/trunk/test/MC/ARM/thumb2.s Mon Aug 29 18:04:04 2011 @@ -2,17 +2,6 @@ @ XFAIL: * .code 16 -@ CHECK: adc r1, r1, #171 @ encoding: [0xab,0x01,0x41,0xf1] - adc r1, r1, #171 -@ CHECK: adc r1, r1, #1179666 @ encoding: [0x12,0x11,0x41,0xf1] - adc r1, r1, #1179666 -@ CHECK: adc r1, r1, #872428544 @ encoding: [0x34,0x21,0x41,0xf1] - adc r1, r1, #872428544 -@ CHECK: adc r1, r1, #1448498774 @ encoding: [0x56,0x31,0x41,0xf1] - adc r1, r1, #1448498774 -@ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1] - adc r1, r1, #66846720 - @ CHECK: mvn r0, #187 @ encoding: [0xbb,0x00,0x6f,0xf0] mvn r0, #187 @ CHECK: mvn r0, #11141290 @ encoding: [0xaa,0x10,0x6f,0xf0] From resistor at mac.com Mon Aug 29 18:15:25 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 29 Aug 2011 23:15:25 -0000 Subject: [llvm-commits] [llvm] r138780 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.s Message-ID: <20110829231525.A0F3D2A6C12C@llvm.org> Author: resistor Date: Mon Aug 29 18:15:25 2011 New Revision: 138780 URL: http://llvm.org/viewvc/llvm-project?rev=138780&view=rev Log: Add missing encoding information for some of the GPR<->FP register moves. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=138780&r1=138779&r2=138780&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Aug 29 18:15:25 2011 @@ -513,9 +513,19 @@ } def VMOVRRS : AVConv3I<0b11000101, 0b1010, - (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2), - IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2", + (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), + IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", [/* For disassembly only; pattern left blank */]> { + bits<5> src1; + bits<4> Rt; + bits<4> Rt2; + + // Encode instruction operands. + let Inst{3-0} = src1{3-0}; + let Inst{5} = src1{4}; + let Inst{15-12} = Rt; + let Inst{19-16} = Rt2; + let Inst{7-6} = 0b00; // Some single precision VFP instructions may be executed on both NEON and VFP @@ -555,6 +565,17 @@ (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", [/* For disassembly only; pattern left blank */]> { + // Instruction operands. + bits<5> dst1; + bits<4> src1; + bits<4> src2; + + // Encode instruction operands. + let Inst{3-0} = dst1{3-0}; + let Inst{5} = dst1{4}; + let Inst{15-12} = src1; + let Inst{19-16} = src2; + let Inst{7-6} = 0b00; // Some single precision VFP instructions may be executed on both NEON and VFP Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=138780&r1=138779&r2=138780&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Aug 29 18:15:25 2011 @@ -234,3 +234,6 @@ vcvtr.s32.f32 s0, s1 vcvtr.u32.f64 s0, d0 vcvtr.u32.f32 s0, s1 + +@ CHECK: vmovne s25, s26, r2, r5 + vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c] From grosbach at apple.com Mon Aug 29 18:20:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 23:20:54 -0000 Subject: [llvm-commits] [llvm] r138781 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110829232055.075972A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 18:20:54 2011 New Revision: 138781 URL: http://llvm.org/viewvc/llvm-project?rev=138781&view=rev Log: Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138781&r1=138780&r2=138781&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 29 18:20:54 2011 @@ -3519,3 +3519,23 @@ (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>; def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; + + +//===----------------------------------------------------------------------===// +// Assembler aliases +// + +// Aliases for ADC without the ".w" optional width specifier. +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", + (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", + (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, + pred:$p, cc_out:$s)>; + +// Aliases for SBC without the ".w" optional width specifier. +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", + (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", + (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, + pred:$p, cc_out:$s)>; + From grosbach at apple.com Mon Aug 29 18:24:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 29 Aug 2011 23:24:15 -0000 Subject: [llvm-commits] [llvm] r138782 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110829232415.7CE322A6C12C@llvm.org> Author: grosbach Date: Mon Aug 29 18:24:15 2011 New Revision: 138782 URL: http://llvm.org/viewvc/llvm-project?rev=138782&view=rev Log: Revert 138781. It's not playing nicely with the immediate forms for ADC. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138782&r1=138781&r2=138782&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 29 18:24:15 2011 @@ -3519,23 +3519,3 @@ (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>; def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; - - -//===----------------------------------------------------------------------===// -// Assembler aliases -// - -// Aliases for ADC without the ".w" optional width specifier. -def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", - (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; -def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", - (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, - pred:$p, cc_out:$s)>; - -// Aliases for SBC without the ".w" optional width specifier. -def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", - (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; -def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", - (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, - pred:$p, cc_out:$s)>; - From jvoung at google.com Mon Aug 29 18:58:36 2011 From: jvoung at google.com (Jan Voung) Date: Mon, 29 Aug 2011 16:58:36 -0700 Subject: [llvm-commits] PATCH: pruning llvm w/ config flags --enable-target-oses=os1, os2 similar to --enable-target=arch1, arch2. In-Reply-To: References: Message-ID: Ping. - Is this approach acceptable? - I guess it is hard to test if this has any effect / depends on the compiler. - Is trimming the size of the llvm binaries (via config flags) useful to others? - Other examples: - make "include/llvm/Intrinsics.td" not #include intrinsincs for targets that were not enabled through "--enable-target" - config flags to avoid building unused register allocators, other passes On Wed, Aug 24, 2011 at 1:12 PM, Jan Voung wrote: > Hi all, > > Attached is a patch that can help prune the size of the llvm binaries > (e.g., llc, lli) a bit. This is done by adding configure flags > --enable-target-oses=os1,os2 and --enable-target-envs=env1,env2 similar to > --enable-target=arch1,arch2. These flags generate pre-processor defines > that are then checked within the Triple module to force certain code paths > to be considered dead (if llvm is built with an LTO-enabled-compiler). > > The if-defs could be spread further to give the same benefit for non-LTO > compilers, but that isn't done. > > Concretely, if you build LLVM w/ clang -O4 and --enable-target-oses=Linux, > there is about a 170 KB savings (prunes most of the MC COFF support, plus > some branches in various places). If --enable-target-envs=gnu is also > specified then most of MC MachO code is also pruned: > > llc built with lto, x86+arm arches, all oses, all environments: 12757900 > llc built with lto, x86+arm arches, only Linux, all environments: 12584978 > llc built with lto, x86+arm arches, only Linux, only gnu environment: > 12528216 > > Is this worth adding? > > Again, patch is attached, or you can view the patch online: > http://codereview.chromium.org/7730004/ > > Thanks! > - Jan > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/197b096e/attachment.html From Micah.Villmow at amd.com Mon Aug 29 19:07:41 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Mon, 29 Aug 2011 19:07:41 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

Message-ID: > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Friday, August 26, 2011 7:03 PM > To: Villmow, Micah > Cc: llvm-commits > Subject: Re: [llvm-commits] Patch to add support for > WidenVecRes_MERGE_VALUES > > On Fri, Aug 26, 2011 at 6:34 PM, Villmow, Micah > wrote: > > This is a patch to fix LLVM bug10736 which occurs with our AMDIL > backend. > > I've also added a test case, but since the AMDIL backend isn't in the > tree yet, I don't know how much good it will do. > > Please review. > > It looks correct, but it doesn't seem very general... there should > really just be a generic DecomposeMERGE_VALUES usable from every > handler that just has a single "ReplaceValueWith(SDValue(N, i), > SDValue(N->getOperand(i)));" loop. (Long-term, we really should just > get rid of MERGE_VALUES, but it's a substantial amount of work.) > > -Eli [Villmow, Micah] Here is an updated patch. This version merges the common code between SplitRes_MERGE_VALUES and WidenVecRes_MERGE_VALUES into a seperate function and has them call this function and then modify the resulting value. -------------- next part -------------- A non-text attachment was scrubbed... Name: AMDIL_Bug_10736-2.patch Type: application/octet-stream Size: 5099 bytes Desc: AMDIL_Bug_10736-2.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110829/fd01e6a8/attachment.obj From evan.cheng at apple.com Mon Aug 29 20:34:54 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 30 Aug 2011 01:34:54 -0000 Subject: [llvm-commits] [llvm] r138791 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/2011-08-29-SchedCycle.ll test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Message-ID: <20110830013454.B88D72A6C12C@llvm.org> Author: evancheng Date: Mon Aug 29 20:34:54 2011 New Revision: 138791 URL: http://llvm.org/viewvc/llvm-project?rev=138791&view=rev Log: Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 Added: llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Aug 29 20:34:54 2011 @@ -374,6 +374,13 @@ return ARM::GPRRegisterClass; } +const TargetRegisterClass * +ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { + if (RC == &ARM::CCRRegClass) + return 0; // Can't copy CCR registers. + return RC; +} + unsigned ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Aug 29 20:34:54 2011 @@ -116,6 +116,8 @@ unsigned &NewSubIdx) const; const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const; + const TargetRegisterClass* + getCrossCopyRegClass(const TargetRegisterClass *RC) const; const TargetRegisterClass* getLargestLegalSuperClass(const TargetRegisterClass *RC) const; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Aug 29 20:34:54 2011 @@ -551,6 +551,14 @@ setOperationAction(ISD::SRL, MVT::i64, Custom); setOperationAction(ISD::SRA, MVT::i64, Custom); + if (!Subtarget->isThumb1Only()) { + // FIXME: We should do this for Thumb1 as well. + setOperationAction(ISD::ADDC, MVT::i32, Custom); + setOperationAction(ISD::ADDE, MVT::i32, Custom); + setOperationAction(ISD::SUBC, MVT::i32, Custom); + setOperationAction(ISD::SUBE, MVT::i32, Custom); + } + // ARM does not have ROTL. setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Custom); @@ -813,6 +821,11 @@ case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; case ARMISD::RRX: return "ARMISD::RRX"; + case ARMISD::ADDC: return "ARMISD::ADDC"; + case ARMISD::ADDE: return "ARMISD::ADDE"; + case ARMISD::SUBC: return "ARMISD::SUBC"; + case ARMISD::SUBE: return "ARMISD::SUBE"; + case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; @@ -4812,6 +4825,27 @@ return N0; } +static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getNode()->getValueType(0); + SDVTList VTs = DAG.getVTList(VT, MVT::i32); + + unsigned Opc; + bool ExtraOp = false; + switch (Op.getOpcode()) { + default: assert(0 && "Invalid code"); + case ISD::ADDC: Opc = ARMISD::ADDC; break; + case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; + case ISD::SUBC: Opc = ARMISD::SUBC; break; + case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; + } + + if (!ExtraOp) + return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), + Op.getOperand(1)); + return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), + Op.getOperand(1), Op.getOperand(2)); +} + SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { default: llvm_unreachable("Don't know how to custom lower this!"); @@ -4859,6 +4893,10 @@ case ISD::MUL: return LowerMUL(Op, DAG); case ISD::SDIV: return LowerSDIV(Op, DAG); case ISD::UDIV: return LowerUDIV(Op, DAG); + case ISD::ADDC: + case ISD::ADDE: + case ISD::SUBC: + case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); } return SDValue(); } @@ -5208,76 +5246,6 @@ llvm_unreachable("Expecting a BB with two successors!"); } -// FIXME: This opcode table should obviously be expressed in the target -// description. We probably just need a "machine opcode" value in the pseudo -// instruction. But the ideal solution maybe to simply remove the "S" version -// of the opcode altogether. -struct AddSubFlagsOpcodePair { - unsigned PseudoOpc; - unsigned MachineOpc; -}; - -static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { - {ARM::ADCSri, ARM::ADCri}, - {ARM::ADCSrr, ARM::ADCrr}, - {ARM::ADCSrsi, ARM::ADCrsi}, - {ARM::ADCSrsr, ARM::ADCrsr}, - {ARM::SBCSri, ARM::SBCri}, - {ARM::SBCSrr, ARM::SBCrr}, - {ARM::SBCSrsi, ARM::SBCrsi}, - {ARM::SBCSrsr, ARM::SBCrsr}, - {ARM::RSBSri, ARM::RSBri}, - {ARM::RSBSrr, ARM::RSBrr}, - {ARM::RSBSrsi, ARM::RSBrsi}, - {ARM::RSBSrsr, ARM::RSBrsr}, - {ARM::RSCSri, ARM::RSCri}, - {ARM::RSCSrsi, ARM::RSCrsi}, - {ARM::RSCSrsr, ARM::RSCrsr}, - {ARM::t2ADCSri, ARM::t2ADCri}, - {ARM::t2ADCSrr, ARM::t2ADCrr}, - {ARM::t2ADCSrs, ARM::t2ADCrs}, - {ARM::t2SBCSri, ARM::t2SBCri}, - {ARM::t2SBCSrr, ARM::t2SBCrr}, - {ARM::t2SBCSrs, ARM::t2SBCrs}, - {ARM::t2RSBSri, ARM::t2RSBri}, - {ARM::t2RSBSrs, ARM::t2RSBrs}, -}; - -// Convert and Add or Subtract with Carry and Flags to a generic opcode with -// CPSR operand. e.g. ADCS (...) -> ADC (... CPSR). -// -// FIXME: Somewhere we should assert that CPSR is in the correct -// position to be recognized by the target descrition as the 'S' bit. -bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI, - MachineBasicBlock *BB) const { - unsigned OldOpc = MI->getOpcode(); - unsigned NewOpc = 0; - - // This is only called for instructions that need remapping, so iterating over - // the tiny opcode table is not costly. - static const int NPairs = - sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); - for (const AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0], - *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) { - if (OldOpc == Pair->PseudoOpc) { - NewOpc = Pair->MachineOpc; - break; - } - } - if (!NewOpc) - return false; - - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); - for (unsigned i = 0; i < MI->getNumOperands(); ++i) - MIB.addOperand(MI->getOperand(i)); - AddDefaultPred(MIB); - MIB.addReg(ARM::CPSR, RegState::Define); // S bit - MI->eraseFromParent(); - return true; -} - MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { @@ -5286,9 +5254,6 @@ bool isThumb2 = Subtarget->isThumb2(); switch (MI->getOpcode()) { default: { - if (RemapAddSubWithFlags(MI, BB)) - return BB; - MI->dump(); llvm_unreachable("Unexpected instr type to insert"); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Aug 29 20:34:54 2011 @@ -71,6 +71,11 @@ SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. + ADDC, // Add with carry + ADDE, // Add using carry + SUBC, // Sub with carry + SUBE, // Sub using carry + VMOVRRD, // double to two gprs. VMOVDRR, // Two gprs to double. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 29 20:34:54 2011 @@ -70,6 +70,18 @@ def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; // Node definitions. def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>; @@ -120,6 +132,12 @@ def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; +def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; +def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; +def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; + def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>; @@ -263,24 +281,11 @@ let ParserMatchClass = Imm0_65535AsmOperand; } +class BinOpWithFlagFrag : + PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; class UnOpFrag : PatFrag<(ops node:$Src), res>; -/// adde and sube predicates - True based on whether the carry flag output -/// will be needed or not. -def adde_dead_carry : - PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), - [{return !N->hasAnyUseOfValue(1);}]>; -def sube_dead_carry : - PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), - [{return !N->hasAnyUseOfValue(1);}]>; -def adde_live_carry : - PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), - [{return N->hasAnyUseOfValue(1);}]>; -def sube_live_carry : - PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), - [{return N->hasAnyUseOfValue(1);}]>; - // An 'and' node with a single use. def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ return N->hasOneUse(); @@ -939,6 +944,161 @@ } +/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are +/// reversed. The 'rr' form is only defined for the disassembler; for codegen +/// it is equivalent to the AsI1_bin_irs counterpart. +multiclass AsI1_rbin_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, string baseOpc, bit Commutable = 0> { + // The register-immediate version is re-materializable. This is useful + // in particular for taking the address of a local. + let isReMaterializable = 1 in { + def ri : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> imm; + let Inst{25} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-0} = imm; + } + } + def rr : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<4> Rm; + let Inst{11-4} = 0b00000000; + let Inst{25} = 0; + let Inst{3-0} = Rm; + let Inst{15-12} = Rd; + let Inst{19-16} = Rn; + } + + def rsi : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-5} = shift{11-5}; + let Inst{4} = 0; + let Inst{3-0} = shift{3-0}; + } + + def rsr : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-8} = shift{11-8}; + let Inst{7} = 0; + let Inst{6-5} = shift{6-5}; + let Inst{4} = 1; + let Inst{3-0} = shift{3-0}; + } + + // Assembly aliases for optional destination operand when it's the same + // as the source operand. + def : InstAlias(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, + so_imm:$imm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, + GPR:$Rm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, + so_reg_imm:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, + so_reg_reg:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + +} + +/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit. +let isCodeGenOnly = 1, Defs = [CPSR] in { +multiclass AsI1_rbin_s_is opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0> { + def ri : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> imm; + let Inst{25} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-0} = imm; + } + + def rr : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<4> Rm; + let Inst{11-4} = 0b00000000; + let Inst{25} = 0; + let Inst{3-0} = Rm; + let Inst{15-12} = Rd; + let Inst{19-16} = Rn; + } + + def rsi : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-5} = shift{11-5}; + let Inst{4} = 0; + let Inst{3-0} = shift{3-0}; + } + + def rsr : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-8} = shift{11-8}; + let Inst{7} = 0; + let Inst{6-5} = shift{6-5}; + let Inst{4} = 1; + let Inst{3-0} = shift{3-0}; + } +} +} + /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. let isCodeGenOnly = 1, Defs = [CPSR] in { @@ -947,7 +1107,7 @@ PatFrag opnode, bit Commutable = 0> { def ri : AI1 { + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> { bits<4> Rd; bits<4> Rn; bits<12> imm; @@ -959,7 +1119,7 @@ } def rr : AI1 { + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; @@ -974,7 +1134,7 @@ def rsi : AI1 { + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> { bits<4> Rd; bits<4> Rn; bits<12> shift; @@ -987,10 +1147,10 @@ let Inst{3-0} = shift{3-0}; } - def rsr : AI1 { + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> { bits<4> Rd; bits<4> Rn; bits<12> shift; @@ -1130,10 +1290,10 @@ /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, string baseOpc, bit Commutable = 0> { - let Uses = [CPSR] in { + let Defs = [CPSR], Uses = [CPSR] in { def ri : AsI1, + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1145,7 +1305,7 @@ } def rr : AsI1, + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1160,7 +1320,7 @@ def rsi : AsI1, + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1175,7 +1335,7 @@ def rsr : AsI1, + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1190,6 +1350,7 @@ let Inst{3-0} = shift{3-0}; } } + // Assembly aliases for optional destination operand when it's the same // as the source operand. def : InstAlias; } -// Carry setting variants -// NOTE: CPSR def omitted because it will be handled by the custom inserter. -let usesCustomInserter = 1 in { -multiclass AI1_adde_sube_s_irs { - def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - 4, IIC_iALUi, - [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>; - def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), - 4, IIC_iALUr, - [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { - let isCommutable = Commutable; +/// AI1_rsc_irs - Define instructions and patterns for rsc +multiclass AI1_rsc_irs opcod, string opc, PatFrag opnode, + string baseOpc> { + let Defs = [CPSR], Uses = [CPSR] in { + def ri : AsI1, + Requires<[IsARM]> { + bits<4> Rd; + bits<4> Rn; + bits<12> imm; + let Inst{25} = 1; + let Inst{15-12} = Rd; + let Inst{19-16} = Rn; + let Inst{11-0} = imm; } - def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>; - def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>; -} + def rr : AsI1 { + bits<4> Rd; + bits<4> Rn; + bits<4> Rm; + let Inst{11-4} = 0b00000000; + let Inst{25} = 0; + let Inst{3-0} = Rm; + let Inst{15-12} = Rd; + let Inst{19-16} = Rn; + } + def rsi : AsI1, + Requires<[IsARM]> { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-5} = shift{11-5}; + let Inst{4} = 0; + let Inst{3-0} = shift{3-0}; + } + def rsr : AsI1, + Requires<[IsARM]> { + bits<4> Rd; + bits<4> Rn; + bits<12> shift; + let Inst{25} = 0; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-8} = shift{11-8}; + let Inst{7} = 0; + let Inst{6-5} = shift{6-5}; + let Inst{4} = 1; + let Inst{3-0} = shift{3-0}; + } + } + + // Assembly aliases for optional destination operand when it's the same + // as the source operand. + def : InstAlias(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, + so_imm:$imm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, + GPR:$Rm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, + so_reg_imm:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, + so_reg_reg:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; } let canFoldAsLoad = 1, isReMaterializable = 1 in { @@ -2882,182 +3106,44 @@ // ADD and SUB with 's' bit set. defm ADDS : AI1_bin_s_irs<0b0100, "adds", IIC_iALUi, IIC_iALUr, IIC_iALUsr, - BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; defm SUBS : AI1_bin_s_irs<0b0010, "subs", IIC_iALUi, IIC_iALUr, IIC_iALUsr, - BinOpFrag<(subc node:$LHS, node:$RHS)>>; + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; defm ADC : AI1_adde_sube_irs<0b0101, "adc", - BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, + BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, "ADC", 1>; defm SBC : AI1_adde_sube_irs<0b0110, "sbc", - BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>, + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, "SBC">; -// ADC and SUBC with 's' bit set. -let usesCustomInserter = 1 in { -defm ADCS : AI1_adde_sube_s_irs< - BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; -defm SBCS : AI1_adde_sube_s_irs< - BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; -} - -def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, - IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm", - [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> { - bits<4> Rd; - bits<4> Rn; - bits<12> imm; - let Inst{25} = 1; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; - let Inst{11-0} = imm; -} - -def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, - IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm", []> { - bits<4> Rd; - bits<4> Rn; - bits<4> Rm; - let Inst{11-4} = 0b00000000; - let Inst{25} = 0; - let Inst{3-0} = Rm; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; -} - -def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), - DPSoRegImmFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift", - [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> { - bits<4> Rd; - bits<4> Rn; - bits<12> shift; - let Inst{25} = 0; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-5} = shift{11-5}; - let Inst{4} = 0; - let Inst{3-0} = shift{3-0}; -} - -def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), - DPSoRegRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift", - [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> { - bits<4> Rd; - bits<4> Rn; - bits<12> shift; - let Inst{25} = 0; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-8} = shift{11-8}; - let Inst{7} = 0; - let Inst{6-5} = shift{6-5}; - let Inst{4} = 1; - let Inst{3-0} = shift{3-0}; -} - -// RSB with 's' bit set. -// NOTE: CPSR def omitted because it will be handled by the custom inserter. -let usesCustomInserter = 1 in { -def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - 4, IIC_iALUi, - [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>; -def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), - 4, IIC_iALUr, []>; -def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>; -def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>; -} - -let Uses = [CPSR] in { -def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm", - [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, - Requires<[IsARM]> { - bits<4> Rd; - bits<4> Rn; - bits<12> imm; - let Inst{25} = 1; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; - let Inst{11-0} = imm; -} -def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), - DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm", []> { - bits<4> Rd; - bits<4> Rn; - bits<4> Rm; - let Inst{11-4} = 0b00000000; - let Inst{25} = 0; - let Inst{3-0} = Rm; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; -} -def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), - DPSoRegImmFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift", - [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>, - Requires<[IsARM]> { - bits<4> Rd; - bits<4> Rn; - bits<12> shift; - let Inst{25} = 0; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-5} = shift{11-5}; - let Inst{4} = 0; - let Inst{3-0} = shift{3-0}; -} -def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), - DPSoRegRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift", - [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>, - Requires<[IsARM]> { - bits<4> Rd; - bits<4> Rn; - bits<12> shift; - let Inst{25} = 0; - let Inst{19-16} = Rn; - let Inst{15-12} = Rd; - let Inst{11-8} = shift{11-8}; - let Inst{7} = 0; - let Inst{6-5} = shift{6-5}; - let Inst{4} = 1; - let Inst{3-0} = shift{3-0}; -} -} - +defm RSB : AsI1_rbin_irs <0b0011, "rsb", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, + BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">; +defm RSBS : AsI1_rbin_s_is<0b0011, "rsb", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; -// NOTE: CPSR def omitted because it will be handled by the custom inserter. -let usesCustomInserter = 1, Uses = [CPSR] in { -def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - 4, IIC_iALUi, - [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>; -def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>; -def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), - 4, IIC_iALUsr, - [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>; -} +defm RSC : AI1_rsc_irs<0b0111, "rsc", + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, + "RSC">; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. // The assume-no-carry-in form uses the negation of the input since add/sub // assume opposite meanings of the carry flag (i.e., carry == !borrow). // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory // details. -def : ARMPat<(add GPR:$src, so_imm_neg:$imm), - (SUBri GPR:$src, so_imm_neg:$imm)>; -def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), - (SUBSri GPR:$src, so_imm_neg:$imm)>; +def : ARMPat<(add GPR:$src, so_imm_neg:$imm), + (SUBri GPR:$src, so_imm_neg:$imm)>; +def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), + (SUBSri GPR:$src, so_imm_neg:$imm)>; + // The with-carry-in form matches bitwise not instead of the negation. // Effectively, the inverse interpretation of the carry flag already accounts // for part of the negation. -def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm), - (SBCri GPR:$src, so_imm_not:$imm)>; -def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm), - (SBCSri GPR:$src, so_imm_not:$imm)>; +def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), + (SBCri GPR:$src, so_imm_not:$imm)>; // Note: These are implemented in C++ code, because they have to generate // ADD/SUBrs instructions, which use a complex pattern that a xform function @@ -4803,29 +4889,6 @@ def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; -// RSB two-operand forms (optional explicit destination operand) -def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm", - (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; -def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm", - (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; -def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", - (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, - cc_out:$s)>; -def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", - (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, - cc_out:$s)>; -// RSC two-operand forms (optional explicit destination operand) -def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm", - (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; -def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm", - (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; -def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", - (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, - cc_out:$s)>; -def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", - (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, - cc_out:$s)>; - // SSAT/USAT optional shift operand. def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 29 20:34:54 2011 @@ -582,7 +582,7 @@ def ri : T2TwoRegImm< (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -593,7 +593,7 @@ def rr : T2ThreeReg< (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -607,7 +607,7 @@ def rs : T2TwoRegShiftedReg< (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -682,13 +682,13 @@ /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns /// for a binary operation that produces a value and use the carry /// bit. It's not predicable. -let Uses = [CPSR] in { +let Defs = [CPSR], Uses = [CPSR] in { multiclass T2I_adde_sube_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, opc, "\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; @@ -698,7 +698,7 @@ // register def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, Requires<[IsThumb2]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; @@ -712,7 +712,7 @@ def rs : T2sTwoRegShiftedReg< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -721,28 +721,6 @@ } } -// Carry setting variants -// NOTE: CPSR def omitted because it will be handled by the custom inserter. -let usesCustomInserter = 1 in { -multiclass T2I_adde_sube_s_irs { - // shifted imm - def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), - 4, IIC_iALUi, - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>; - // register - def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), - 4, IIC_iALUr, - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { - let isCommutable = Commutable; - } - // shifted register - def rs : t2PseudoInst< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), - 4, IIC_iALUsi, - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>; -} -} - /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register /// version is not needed since this is only for codegen. let isCodeGenOnly = 1, Defs = [CPSR] in { @@ -751,7 +729,7 @@ def ri : T2TwoRegImm< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { + [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -762,7 +740,7 @@ def rs : T2TwoRegShiftedReg< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { + [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -1678,25 +1656,21 @@ // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. defm t2ADDS : T2I_bin_s_irs <0b1000, "add", IIC_iALUi, IIC_iALUr, IIC_iALUsi, - BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", IIC_iALUi, IIC_iALUr, IIC_iALUsi, - BinOpFrag<(subc node:$LHS, node:$RHS)>>; + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", - BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; + BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", - BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; -defm t2ADCS : T2I_adde_sube_s_irs, 1>; -defm t2SBCS : T2I_adde_sube_s_irs>; + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; // RSB defm t2RSB : T2I_rbin_irs <0b1110, "rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", - BinOpFrag<(subc node:$LHS, node:$RHS)>>; + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. // The assume-no-carry-in form uses the negation of the input since add/sub @@ -1713,23 +1687,18 @@ def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; let AddedComplexity = 1 in -def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm), +def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm), (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; -def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm), +def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; // The with-carry-in form matches bitwise not instead of the negation. // Effectively, the inverse interpretation of the carry flag already accounts // for part of the negation. let AddedComplexity = 1 in -def : T2Pat<(adde_dead_carry rGPR:$src, imm0_255_not:$imm), +def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), (t2SBCri rGPR:$src, imm0_255_not:$imm)>; -def : T2Pat<(adde_dead_carry rGPR:$src, t2_so_imm_not:$imm), +def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; -let AddedComplexity = 1 in -def : T2Pat<(adde_live_carry rGPR:$src, imm0_255_not:$imm), - (t2SBCSri rGPR:$src, imm0_255_not:$imm)>; -def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm), - (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>; // Select Bytes -- for disassembly only Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Aug 29 20:34:54 2011 @@ -347,5 +347,6 @@ // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { + let CopyCost = -1; // Don't allow copying of status registers. let isAllocatable = 0; } Added: llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll?rev=138791&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll Mon Aug 29 20:34:54 2011 @@ -0,0 +1,45 @@ +; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o - + +; When a i64 sub is expanded to subc + sube. +; libcall #1 +; \ +; \ subc +; \ / \ +; \ / \ +; \ / libcall #2 +; sube +; +; If the libcalls are not serialized (i.e. both have chains which are dag +; entry), legalizer can serialize them in arbitrary orders. If it's +; unlucky, it can force libcall #2 before libcall #1 in the above case. +; +; subc +; | +; libcall #2 +; | +; libcall #1 +; | +; sube +; +; However since subc and sube are "glued" together, this ends up being a +; cycle when the scheduler combine subc and sube as a single scheduling +; unit. +; +; The right solution is to fix LegalizeType too chains the libcalls together. +; However, LegalizeType is not processing nodes in order. The fix now is to +; fix subc / sube (and addc / adde) to use physical register dependency instead. +; rdar://10019576 + +define void @t() nounwind { +entry: + %tmp = load i64* undef, align 4 + %tmp5 = udiv i64 %tmp, 30 + %tmp13 = and i64 %tmp5, 64739244643450880 + %tmp16 = sub i64 0, %tmp13 + %tmp19 = and i64 %tmp16, 63 + %tmp20 = urem i64 %tmp19, 3 + %tmp22 = and i64 %tmp16, -272346829004752 + store i64 %tmp22, i64* undef, align 4 + store i64 %tmp20, i64* undef, align 4 + ret void +} Modified: llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll?rev=138791&r1=138790&r2=138791&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Mon Aug 29 20:34:54 2011 @@ -6,8 +6,8 @@ ; -- The loop following the load should only use a single add-literation ; instruction. ; CHECK: ldr.64 -; CHECK: adds r{{[0-9]+}}, #1 -; CHECK-NOT: adds r{{[0-9]+}}, #1 +; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 +; CHECK-NOT: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 ; CHECK: subsections_via_symbols From bob.wilson at apple.com Tue Aug 30 00:36:03 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 30 Aug 2011 05:36:03 -0000 Subject: [llvm-commits] [llvm] r138794 - /llvm/trunk/lib/CodeGen/InlineSpiller.cpp Message-ID: <20110830053603.09A292A6C12C@llvm.org> Author: bwilson Date: Tue Aug 30 00:36:02 2011 New Revision: 138794 URL: http://llvm.org/viewvc/llvm-project?rev=138794&view=rev Log: Do not try to rematerialize a value from a partial definition. I don't currently have a good testcase for this; will try to get one tomorrow. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=138794&r1=138793&r2=138794&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Aug 30 00:36:02 2011 @@ -189,6 +189,20 @@ return 0; } +/// isFullDefOf - Return true if MI defines the full contents of a register. +/// Since this is in the context of spilling, it does not do anything special +/// for physical registers. +static bool isFullDefOf(const MachineInstr *MI, unsigned Reg) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef() || MO.getSubReg()) + continue; + if (MO.getReg() == Reg) + return true; + } + return false; +} + /// isSnippet - Identify if a live interval is a snippet that should be spilled. /// It is assumed that SnipLI is a virtual register with the same original as /// Edit->getReg(). @@ -306,6 +320,7 @@ MachineBasicBlock *SpillMBB = UseMBB; unsigned SpillDepth = Loops.getLoopDepth(SpillMBB); bool SeenOrigPHI = false; // Original PHI met. + bool SeenNonReloadDef = false; do { unsigned Reg; @@ -407,12 +422,18 @@ } // Potential remat candidate. + SeenNonReloadDef = true; + if (!isFullDefOf(MI, Reg)) { + DEBUG(dbgs() << " partial def " << PrintReg(Reg) << ':' + << VNI->id << '@' << VNI->def << '\t' << *MI); + continue; + } DEBUG(dbgs() << " def " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def << '\t' << *MI); SVI.DefMI = MI; } while (!WorkList.empty()); - if (SeenOrigPHI || SVI.DefMI) + if (SeenOrigPHI || SeenNonReloadDef) SVI.AllDefsAreReloads = false; DEBUG({ From craig.topper at gmail.com Tue Aug 30 02:09:35 2011 From: craig.topper at gmail.com (Craig Topper) Date: Tue, 30 Aug 2011 07:09:35 -0000 Subject: [llvm-commits] [llvm] r138795 - in /llvm/trunk: test/MC/Disassembler/X86/simple-tests.txt utils/TableGen/X86RecognizableInstr.cpp Message-ID: <20110830070935.726972A6C12C@llvm.org> Author: ctopper Date: Tue Aug 30 02:09:35 2011 New Revision: 138795 URL: http://llvm.org/viewvc/llvm-project?rev=138795&view=rev Log: Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=138795&r1=138794&r2=138795&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Tue Aug 30 02:09:35 2011 @@ -96,3 +96,6 @@ # CHECK: vcvtsd2si %xmm0, %rax 0xc4 0xe1 0xfb 0x2d 0xc0 + +# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) +0xc4 0xe2 0x71 0x2f 0x00 Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=138795&r1=138794&r2=138795&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue Aug 30 02:09:35 2011 @@ -623,20 +623,43 @@ case X86Local::MRMDestReg: // Operand 1 is a register operand in the R/M field. // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestRegFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestRegFrm"); + HANDLE_OPERAND(rmRegister) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; case X86Local::MRMDestMem: // Operand 1 is a memory operand (possibly SIB-extended) // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestMemFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestMemFrm"); HANDLE_OPERAND(memory) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; From tobias at grosser.es Tue Aug 30 02:11:42 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 30 Aug 2011 08:11:42 +0100 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

Message-ID: <4E5C8D2E.9010006@grosser.es> On 08/30/2011 01:07 AM, Villmow, Micah wrote: > [Villmow, Micah] Here is an updated patch. This version merges the common > code between SplitRes_MERGE_VALUES and WidenVecRes_MERGE_VALUES into a > seperate function and has them call this function and then modify the > resulting value. Two comments inline, otherwise it looks good to me. (Review by official reviewer still necessary). Cheers Tobi > Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h > =================================================================== > --- lib/CodeGen/SelectionDAG/LegalizeTypes.h (revision 138781) > +++ lib/CodeGen/SelectionDAG/LegalizeTypes.h (working copy) > @@ -148,12 +148,20 @@ > SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); > bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); > bool CustomWidenLowerNode(SDNode *N, EVT VT); > + > + // DecomposeMERGE_VALUES takes a SDNode and returns the first > + // operand that illegal operand that needs to be modified. Is this correct grammar? What do you mean? - DecomposeMERGE_VALUES takes a SDNode and returns the first operand that needs to be modified. - DecomposeMERGE_VALUES takes a SDNode and returns the first illegal operand. - DecomposeMERGE_VALUES takes a SDNode and returns the first illegal operand which needs to be modified. > + // All other nodes are legalized, whether they are legal or not. > + // The resulting SDValue needs to be modified to make it legal. > + SDValue DecomposeMERGE_VALUES(SDNode *N); > + > SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index); > SDValue JoinIntegers(SDValue Lo, SDValue Hi); > SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); > SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > const SDValue *Ops, unsigned NumOps, bool isSigned, > DebugLoc dl); > + > std::pair ExpandChainLibCall(RTLIB::Libcall LC, > SDNode *Node, bool isSigned); > std::pair ExpandAtomic(SDNode *Node); > void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue&Lo, > Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > =================================================================== > --- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (revision 138781) > +++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (working copy) > @@ -1557,6 +1558,12 @@ > WidenVT, WidenLHS, DAG.getValueType(ExtVT)); > } > > +SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N) > +{ The '{' should be in the previous line to match coding standards in this file. > + SDValue WidenVec = DecomposeMERGE_VALUES(N); > + return GetWidenedVector(WidenVec); > +} > + > SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { > SDValue InOp = N->getOperand(0); > EVT InVT = InOp.getValueType(); From james.molloy at arm.com Tue Aug 30 02:23:29 2011 From: james.molloy at arm.com (James Molloy) Date: Tue, 30 Aug 2011 07:23:29 -0000 Subject: [llvm-commits] [llvm] r138796 - /llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Message-ID: <20110830072329.300D22A6C12C@llvm.org> Author: jamesm Date: Tue Aug 30 02:23:29 2011 New Revision: 138796 URL: http://llvm.org/viewvc/llvm-project?rev=138796&view=rev Log: Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc at gmail.com) Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h?rev=138796&r1=138795&r2=138796&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Tue Aug 30 02:23:29 2011 @@ -1,4 +1,4 @@ -//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,12 @@ // //===----------------------------------------------------------------------===// // -// This file provides Alpha specific target descriptions. +// This file provides Mips specific target descriptions. // //===----------------------------------------------------------------------===// -#ifndef ALPHAMCTARGETDESC_H -#define ALPHAMCTARGETDESC_H +#ifndef MIPSMCTARGETDESC_H +#define MIPSMCTARGETDESC_H namespace llvm { class MCSubtargetInfo; From james.molloy at arm.com Tue Aug 30 02:24:47 2011 From: james.molloy at arm.com (James Molloy) Date: Tue, 30 Aug 2011 07:24:47 -0000 Subject: [llvm-commits] [llvm] r138797 - /llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h Message-ID: <20110830072447.9CBF22A6C12C@llvm.org> Author: jamesm Date: Tue Aug 30 02:24:47 2011 New Revision: 138797 URL: http://llvm.org/viewvc/llvm-project?rev=138797&view=rev Log: Fix typo in MSP430MCTargetDesc.h. Patch supplied by Liu (projlc at gmail.com) Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h?rev=138797&r1=138796&r2=138797&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h (original) +++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h Tue Aug 30 02:24:47 2011 @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef ALPHAMCTARGETDESC_H -#define ALPHAMCTARGETDESC_H +#ifndef MSP430MCTARGETDESC_H +#define MSP430MCTARGETDESC_H namespace llvm { class MCSubtargetInfo; From james.molloy at arm.com Tue Aug 30 02:26:11 2011 From: james.molloy at arm.com (James Molloy) Date: Tue, 30 Aug 2011 07:26:11 -0000 Subject: [llvm-commits] [llvm] r138798 - /llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h Message-ID: <20110830072611.ED1912A6C12C@llvm.org> Author: jamesm Date: Tue Aug 30 02:26:11 2011 New Revision: 138798 URL: http://llvm.org/viewvc/llvm-project?rev=138798&view=rev Log: Fix typo in BlackfinFrameLowering.h Patch supplied by Liu (projlc at gmail.com) Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h?rev=138798&r1=138797&r2=138798&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h Tue Aug 30 02:26:11 2011 @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef ALPHA_FRAMEINFO_H -#define ALPHA_FRAMEINFO_H +#ifndef BLACKFIN_FRAMEINFO_H +#define BLACKFIN_FRAMEINFO_H #include "Blackfin.h" #include "BlackfinSubtarget.h" From james.molloy at arm.com Tue Aug 30 02:27:02 2011 From: james.molloy at arm.com (James Molloy) Date: Tue, 30 Aug 2011 07:27:02 -0000 Subject: [llvm-commits] [llvm] r138799 - /llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h Message-ID: <20110830072702.893A72A6C12C@llvm.org> Author: jamesm Date: Tue Aug 30 02:27:02 2011 New Revision: 138799 URL: http://llvm.org/viewvc/llvm-project?rev=138799&view=rev Log: Fix typos in SPUMCTargetDesc.h Patch supplied by Liu (projlc at gmail.com) Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h?rev=138799&r1=138798&r2=138799&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h (original) +++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h Tue Aug 30 02:27:02 2011 @@ -1,4 +1,4 @@ -//===-- SPUMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +//===-- SPUMCTargetDesc.h - CellSPU Target Descriptions ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file provides Alpha specific target descriptions. +// This file provides CellSPU specific target descriptions. // //===----------------------------------------------------------------------===// From baldrick at free.fr Tue Aug 30 02:31:06 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 30 Aug 2011 07:31:06 -0000 Subject: [llvm-commits] [dragonegg] r138800 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110830073107.066702A6C12D@llvm.org> Author: baldrick Date: Tue Aug 30 02:31:06 2011 New Revision: 138800 URL: http://llvm.org/viewvc/llvm-project?rev=138800&view=rev Log: If something goes wrong while emitting a function (eg: we come across an unsupported feature) don't just skip output of other functions, since otherwise GCC assertions will fire. Instead just do the minimum to make GCC happy, while not outputting any LLVM IR. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=138800&r1=138799&r2=138800&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Tue Aug 30 02:31:06 2011 @@ -1371,12 +1371,6 @@ } -/// gate_emission - Whether to turn gimple into LLVM IR. -static bool gate_emission(void) { - // Don't bother doing anything if the program has errors. - return !errorcount && !sorrycount; // Do not process broken code. -} - /// emit_current_function - Turn the current gimple function into LLVM IR. This /// is called once for each function in the compilation unit. static void emit_current_function() { @@ -1558,7 +1552,7 @@ { IPA_PASS, "emit_aliases", /* name */ - gate_emission, /* gate */ + NULL, /* gate */ NULL, /* execute */ NULL, /* sub */ NULL, /* next */ @@ -1589,10 +1583,11 @@ /// once for each function in the compilation unit if GCC optimizations are /// enabled. static unsigned int rtl_emit_function (void) { - InitializeBackend(); - - // Convert the function. - emit_current_function(); + if (!errorcount && !sorrycount) { + InitializeBackend(); + // Convert the function. + emit_current_function(); + } // Free any data structures. execute_free_datastructures(); @@ -1608,7 +1603,7 @@ { RTL_PASS, "rtl_emit_function", /* name */ - gate_emission, /* gate */ + NULL, /* gate */ rtl_emit_function, /* execute */ NULL, /* sub */ NULL, /* next */ From baldrick at free.fr Tue Aug 30 04:20:45 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 30 Aug 2011 09:20:45 -0000 Subject: [llvm-commits] [dragonegg] r138801 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp Message-ID: <20110830092045.C9BF02A6C12C@llvm.org> Author: baldrick Date: Tue Aug 30 04:20:45 2011 New Revision: 138801 URL: http://llvm.org/viewvc/llvm-project?rev=138801&view=rev Log: Add support for builtin_unreachable. Put some builtins in alphabetical order while there. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=138801&r1=138800&r2=138801&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Tue Aug 30 04:20:45 2011 @@ -623,25 +623,29 @@ Value *EmitBuiltinLFLOOR(gimple_statement_d *stmt); Value *EmitBuiltinCEXPI(gimple_statement_d *stmt); - bool EmitBuiltinConstantP(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinAdjustTrampoline(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinAlloca(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinBZero(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinConstantP(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinExpect(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinExtendPointer(gimple_statement_d *stmt, Value *&Result); - bool EmitBuiltinVAStart(gimple_statement_d *stmt); - bool EmitBuiltinVAEnd(gimple_statement_d *stmt); - bool EmitBuiltinVACopy(gimple_statement_d *stmt); + bool EmitBuiltinExtractReturnAddr(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinFrobReturnAddr(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinInitTrampoline(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinMemCopy(gimple_statement_d *stmt, Value *&Result, bool isMemMove, bool SizeCheck); bool EmitBuiltinMemSet(gimple_statement_d *stmt, Value *&Result, bool SizeCheck); - bool EmitBuiltinBZero(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinPrefetch(gimple_statement_d *stmt); bool EmitBuiltinReturnAddr(gimple_statement_d *stmt, Value *&Result, bool isFrame); - bool EmitBuiltinExtractReturnAddr(gimple_statement_d *stmt, Value *&Result); - bool EmitBuiltinFrobReturnAddr(gimple_statement_d *stmt, Value *&Result); - bool EmitBuiltinStackSave(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinStackRestore(gimple_statement_d *stmt); + bool EmitBuiltinStackSave(gimple_statement_d *stmt, Value *&Result); + bool EmitBuiltinUnreachable(); + bool EmitBuiltinVACopy(gimple_statement_d *stmt); + bool EmitBuiltinVAEnd(gimple_statement_d *stmt); + bool EmitBuiltinVAStart(gimple_statement_d *stmt); + bool EmitBuiltinEHPointer(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinDwarfCFA(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinDwarfSPColumn(gimple_statement_d *stmt, Value *&Result); @@ -649,8 +653,6 @@ bool EmitBuiltinEHReturn(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinInitDwarfRegSizes(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinUnwindInit(gimple_statement_d *stmt, Value *&Result); - bool EmitBuiltinAdjustTrampoline(gimple_statement_d *stmt, Value *&Result); - bool EmitBuiltinInitTrampoline(gimple_statement_d *stmt, Value *&Result); // Complex Math Expressions. Value *CreateComplex(Value *Real, Value *Imag); Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=138801&r1=138800&r2=138801&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue Aug 30 04:20:45 2011 @@ -3714,10 +3714,21 @@ case BUILT_IN_VA_START: return EmitBuiltinVAStart(stmt); case BUILT_IN_VA_END: return EmitBuiltinVAEnd(stmt); case BUILT_IN_VA_COPY: return EmitBuiltinVACopy(stmt); - case BUILT_IN_CONSTANT_P: return EmitBuiltinConstantP(stmt, Result); + + case BUILT_IN_ADJUST_TRAMPOLINE: + return EmitBuiltinAdjustTrampoline(stmt, Result); case BUILT_IN_ALLOCA: return EmitBuiltinAlloca(stmt, Result); - case BUILT_IN_EXTEND_POINTER: return EmitBuiltinExtendPointer(stmt, Result); + case BUILT_IN_BZERO: return EmitBuiltinBZero(stmt, Result); + case BUILT_IN_CONSTANT_P: return EmitBuiltinConstantP(stmt, Result); case BUILT_IN_EXPECT: return EmitBuiltinExpect(stmt, Result); + case BUILT_IN_EXTEND_POINTER: return EmitBuiltinExtendPointer(stmt, Result); + case BUILT_IN_EXTRACT_RETURN_ADDR: + return EmitBuiltinExtractReturnAddr(stmt, Result); + case BUILT_IN_FRAME_ADDRESS: return EmitBuiltinReturnAddr(stmt, Result,true); + case BUILT_IN_FROB_RETURN_ADDR: + return EmitBuiltinFrobReturnAddr(stmt, Result); + case BUILT_IN_INIT_TRAMPOLINE: + return EmitBuiltinInitTrampoline(stmt, Result); case BUILT_IN_MEMCPY: return EmitBuiltinMemCopy(stmt, Result, false, false); case BUILT_IN_MEMCPY_CHK: return EmitBuiltinMemCopy(stmt, Result, @@ -3728,21 +3739,12 @@ true, true); case BUILT_IN_MEMSET: return EmitBuiltinMemSet(stmt, Result, false); case BUILT_IN_MEMSET_CHK: return EmitBuiltinMemSet(stmt, Result, true); - case BUILT_IN_BZERO: return EmitBuiltinBZero(stmt, Result); case BUILT_IN_PREFETCH: return EmitBuiltinPrefetch(stmt); - case BUILT_IN_FRAME_ADDRESS: return EmitBuiltinReturnAddr(stmt, Result,true); case BUILT_IN_RETURN_ADDRESS: return EmitBuiltinReturnAddr(stmt, Result,false); - case BUILT_IN_STACK_SAVE: return EmitBuiltinStackSave(stmt, Result); case BUILT_IN_STACK_RESTORE: return EmitBuiltinStackRestore(stmt); - case BUILT_IN_EXTRACT_RETURN_ADDR: - return EmitBuiltinExtractReturnAddr(stmt, Result); - case BUILT_IN_FROB_RETURN_ADDR: - return EmitBuiltinFrobReturnAddr(stmt, Result); - case BUILT_IN_ADJUST_TRAMPOLINE: - return EmitBuiltinAdjustTrampoline(stmt, Result); - case BUILT_IN_INIT_TRAMPOLINE: - return EmitBuiltinInitTrampoline(stmt, Result); + case BUILT_IN_STACK_SAVE: return EmitBuiltinStackSave(stmt, Result); + case BUILT_IN_UNREACHABLE: return EmitBuiltinUnreachable(); // Exception handling builtins. case BUILT_IN_EH_POINTER: @@ -5021,6 +5023,10 @@ return true; } +bool TreeToLLVM::EmitBuiltinUnreachable() { + Builder.CreateUnreachable(); + return true; +} // Exception handling builtins. From Micah.Villmow at amd.com Tue Aug 30 07:04:00 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Tue, 30 Aug 2011 07:04:00 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: <4E5C8D2E.9010006@grosser.es> References:

<4E5C8D2E.9010006@grosser.es> Message-ID: Thanks for the feedback, new revision attached. > -----Original Message----- > From: Tobias Grosser [mailto:tobias at grosser.es] > Sent: Tuesday, August 30, 2011 12:12 AM > To: Villmow, Micah > Cc: Eli Friedman; llvm-commits > Subject: Re: [llvm-commits] Patch to add support for > WidenVecRes_MERGE_VALUES > > On 08/30/2011 01:07 AM, Villmow, Micah wrote: > > [Villmow, Micah] Here is an updated patch. This version merges the > common > > code between SplitRes_MERGE_VALUES and WidenVecRes_MERGE_VALUES into > a > > seperate function and has them call this function and then modify the > > resulting value. > > Two comments inline, otherwise it looks good to me. > (Review by official reviewer still necessary). > > Cheers > Tobi > > > > Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h > > =================================================================== > > --- lib/CodeGen/SelectionDAG/LegalizeTypes.h (revision 138781) > > +++ lib/CodeGen/SelectionDAG/LegalizeTypes.h (working copy) > > @@ -148,12 +148,20 @@ > > SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); > > bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); > > bool CustomWidenLowerNode(SDNode *N, EVT VT); > > + > > + // DecomposeMERGE_VALUES takes a SDNode and returns the first > > + // operand that illegal operand that needs to be modified. > Is this correct grammar? What do you mean? > - DecomposeMERGE_VALUES takes a SDNode and returns the first > operand that needs to be modified. > - DecomposeMERGE_VALUES takes a SDNode and returns the first > illegal operand. > - DecomposeMERGE_VALUES takes a SDNode and returns the first > illegal operand which needs to be modified. > > > + // All other nodes are legalized, whether they are legal or not. > > + // The resulting SDValue needs to be modified to make it legal. > > + SDValue DecomposeMERGE_VALUES(SDNode *N); > > + > > SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, > SDValue Index); > > SDValue JoinIntegers(SDValue Lo, SDValue Hi); > > SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); > > SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > > const SDValue *Ops, unsigned NumOps, bool > isSigned, > > DebugLoc dl); > > + > > std::pair ExpandChainLibCall(RTLIB::Libcall > LC, > > > SDNode *Node, bool isSigned); > > std::pair ExpandAtomic(SDNode *Node); > > void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue&Lo, > > Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > > =================================================================== > > --- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (revision > 138781) > > +++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (working > copy) > > @@ -1557,6 +1558,12 @@ > > WidenVT, WidenLHS, DAG.getValueType(ExtVT)); > > } > > > > +SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N) > > +{ > The '{' should be in the previous line to match coding standards in > this > file. > > > + SDValue WidenVec = DecomposeMERGE_VALUES(N); > > + return GetWidenedVector(WidenVec); > > +} > > + > > SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { > > SDValue InOp = N->getOperand(0); > > EVT InVT = InOp.getValueType(); -------------- next part -------------- A non-text attachment was scrubbed... Name: AMDIL_Bug_10736-3.patch Type: application/octet-stream Size: 5084 bytes Desc: AMDIL_Bug_10736-3.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/f2313590/attachment.obj From 6yearold at gmail.com Tue Aug 30 07:09:46 2011 From: 6yearold at gmail.com (arrowdodger) Date: Tue, 30 Aug 2011 16:09:46 +0400 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: References:

Message-ID: On Tue, Aug 30, 2011 at 2:20 AM, Andrew Trick wrote: > Can we call this ignoreStdErr instead of noStdErr > Done. , then add the command line option --ignore-stderr? > > ("noStdErr" could be misinterpreted as something like --quiet). > > I'm curious how you're currently setting litConfig.noStdErr. > > -Andy > > On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: > > > > > Firstly, i've solved this exactly in such way, but Daniel Dunbar suggested me to remove command line option and add default constructor to TclTest class. So this option can be turned on/off in test/lit.site.cfg. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/55506f3c/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: lit.patch Type: text/x-patch Size: 3613 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/55506f3c/attachment.bin From rdivacky at freebsd.org Tue Aug 30 09:13:07 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 30 Aug 2011 16:13:07 +0200 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: <20110824191434.GA29249@freebsd.org> References: <20110824191434.GA29249@freebsd.org> Message-ID: <20110830141307.GA97660@freebsd.org> ping^2 On Wed, Aug 24, 2011 at 09:14:34PM +0200, Roman Divacky wrote: > Hi, > > PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit > when the call is a vararg one. It should set the bit only with vararg > call that has floating point arguments in registers and unset the > bit otherwise. The attached patch fixes that + test. > > This is normally just an optimization but it's very important in the > kernel where doing floating point stuff is lethal. > > OK to commit? > > thank you, roman > ; RUN: llc < %s | FileCheck %s > ; ModuleID = 'test.c' > target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" > target triple = "powerpc-unknown-freebsd" > > @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 > @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 > > define void @foo() nounwind { > entry: > ; CHECK: crxor 6, 6, 6 > %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) > ; CHECK: creqv 6, 6, 6 > %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) > ret void > } > > declare i32 @printf(i8*, ...) > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sanjoy at playingwithpointers.com Tue Aug 30 10:39:30 2011 From: sanjoy at playingwithpointers.com (Sanjoy Das) Date: Tue, 30 Aug 2011 21:09:30 +0530 Subject: [llvm-commits] [PATCH] Segmented Stacks Message-ID: <4E5D0432.7040504@playingwithpointers.com> I've attached my pre-midterm GSoC work (after review on llvmdev). The documentation is only partially filled in, I'll add more details once support for Go is also merged (the current trampoline work I'm doing). Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-New-command-line-option-to-enable-segmented-stacks.patch Type: text/x-diff Size: 1699 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0006.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Prologue-code-emission-for-X86.patch Type: text/x-diff Size: 12186 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0007.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-New-SelectionDAG-node-and-pseudo-instructions-for-va.patch Type: text/x-diff Size: 4330 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0008.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0004-Support-for-variable-sized-allocas.patch Type: text/x-diff Size: 10680 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0009.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-Test-code.patch Type: text/x-diff Size: 2732 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0010.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0006-Documentation.patch Type: text/x-diff Size: 6179 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/434bd542/attachment-0011.bin From evan.cheng at apple.com Tue Aug 30 11:16:15 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 30 Aug 2011 09:16:15 -0700 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: <20110830141307.GA97660@freebsd.org> References: <20110824191434.GA29249@freebsd.org> <20110830141307.GA97660@freebsd.org> Message-ID: <25F5EA49-8D08-4EF0-B24D-12EDB56EC849@apple.com> Looks fine to me. Evan On Aug 30, 2011, at 7:13 AM, Roman Divacky wrote: > ping^2 > > On Wed, Aug 24, 2011 at 09:14:34PM +0200, Roman Divacky wrote: >> Hi, >> >> PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit >> when the call is a vararg one. It should set the bit only with vararg >> call that has floating point arguments in registers and unset the >> bit otherwise. The attached patch fixes that + test. >> >> This is normally just an optimization but it's very important in the >> kernel where doing floating point stuff is lethal. >> >> OK to commit? >> >> thank you, roman > > >> ; RUN: llc < %s | FileCheck %s >> ; ModuleID = 'test.c' >> target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" >> target triple = "powerpc-unknown-freebsd" >> >> @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 >> @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 >> >> define void @foo() nounwind { >> entry: >> ; CHECK: crxor 6, 6, 6 >> %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) >> ; CHECK: creqv 6, 6, 6 >> %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) >> ret void >> } >> >> declare i32 @printf(i8*, ...) > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Tue Aug 30 11:20:39 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 30 Aug 2011 09:20:39 -0700 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: References:

Message-ID: <7519A774-C048-4151-96E9-067E52D3AB49@apple.com> On Aug 30, 2011, at 5:09 AM, arrowdodger wrote: > On Tue, Aug 30, 2011 at 2:20 AM, Andrew Trick wrote: > Can we call this ignoreStdErr instead of noStdErr > > Done. > > , then add the command line option --ignore-stderr? > > ("noStdErr" could be misinterpreted as something like --quiet). > > I'm curious how you're currently setting litConfig.noStdErr. > > -Andy > > On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: > >> > > > Firstly, i've solved this exactly in such way, but Daniel Dunbar suggested me to remove command line option and add default constructor to TclTest class. So this option can be turned on/off in test/lit.site.cfg. > Looks fine to me. Can you add a comment in lit.site.cfg with an example? I know how to set TestingConfig options, but not LitConfig options. -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/ae227f9b/attachment.html From 6yearold at gmail.com Tue Aug 30 11:49:52 2011 From: 6yearold at gmail.com (arrowdodger) Date: Tue, 30 Aug 2011 20:49:52 +0400 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: <7519A774-C048-4151-96E9-067E52D3AB49@apple.com> References:

<7519A774-C048-4151-96E9-067E52D3AB49@apple.com> Message-ID: On Tue, Aug 30, 2011 at 8:20 PM, Andrew Trick wrote: > On Aug 30, 2011, at 5:09 AM, arrowdodger wrote: > > On Tue, Aug 30, 2011 at 2:20 AM, Andrew Trick wrote: > >> Can we call this ignoreStdErr instead of noStdErr >> > > Done. > > , then add the command line option --ignore-stderr? >> >> ("noStdErr" could be misinterpreted as something like --quiet). >> >> I'm curious how you're currently setting litConfig.noStdErr. >> >> -Andy >> >> On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: >> >> >> >> >> > Firstly, i've solved this exactly in such way, but Daniel Dunbar suggested > me to remove command line option and add default constructor to TclTest > class. So this option can be turned on/off in test/lit.site.cfg. > > > > Looks fine to me. Can you add a comment in lit.site.cfg with an example? I > know how to set TestingConfig options, but not LitConfig options. > > -Andy > Sorry, i've mistaken lit.site.cfg with lit.cfg. The latter is the right file to put comment in. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/3cbe74ca/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: lit.patch Type: text/x-patch Size: 4113 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/3cbe74ca/attachment.bin From rdivacky at freebsd.org Tue Aug 30 12:04:16 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 30 Aug 2011 17:04:16 -0000 Subject: [llvm-commits] [llvm] r138802 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCInstrInfo.td test/CodeGen/PowerPC/cr1eq.ll Message-ID: <20110830170416.46B0A2A6C12C@llvm.org> Author: rdivacky Date: Tue Aug 30 12:04:16 2011 New Revision: 138802 URL: http://llvm.org/viewvc/llvm-project?rev=138802&view=rev Log: Set CR1EQ only when lowering vararg floating arguments (not any vararg arguments as before), unset CR1EQ otherwise. Added: llvm/trunk/test/CodeGen/PowerPC/cr1eq.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=138802&r1=138801&r2=138802&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Aug 30 12:04:16 2011 @@ -2946,6 +2946,7 @@ SmallVector TailCallArguments; SmallVector MemOpChains; + bool seenFloatArg = false; // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; @@ -2990,6 +2991,7 @@ } if (VA.isRegLoc()) { + seenFloatArg |= VA.getLocVT().isFloatingPoint(); // Put argument in a physical register. RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else { @@ -3016,9 +3018,11 @@ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); - // Set CR6 to true if this is a vararg call. + // Set CR6 to true if this is a vararg call with floating args passed in + // registers. if (isVarArg) { - SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); + SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET, + dl, MVT::i32), 0); RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR)); } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=138802&r1=138801&r2=138802&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Aug 30 12:04:16 2011 @@ -1053,6 +1053,10 @@ "creqv $dst, $dst, $dst", BrCR, []>; +def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), + "crxor $dst, $dst, $dst", BrCR, + []>; + // XFX-Form instructions. Instructions that deal with SPRs. // let Uses = [CTR] in { Added: llvm/trunk/test/CodeGen/PowerPC/cr1eq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr1eq.ll?rev=138802&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/cr1eq.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/cr1eq.ll Tue Aug 30 12:04:16 2011 @@ -0,0 +1,18 @@ +; RUN: llc < %s | FileCheck %s +; ModuleID = 'test.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-freebsd" + + at .str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 + at .str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 + +define void @foo() nounwind { +entry: +; CHECK: crxor 6, 6, 6 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) +; CHECK: creqv 6, 6, 6 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) + ret void +} + +declare i32 @printf(i8*, ...) From atrick at apple.com Tue Aug 30 12:05:30 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 30 Aug 2011 10:05:30 -0700 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: References:

<7519A774-C048-4151-96E9-067E52D3AB49@apple.com> Message-ID: Thanks, please commit. On Aug 30, 2011, at 9:49 AM, arrowdodger wrote: > On Tue, Aug 30, 2011 at 8:20 PM, Andrew Trick wrote: > On Aug 30, 2011, at 5:09 AM, arrowdodger wrote: > >> On Tue, Aug 30, 2011 at 2:20 AM, Andrew Trick wrote: >> Can we call this ignoreStdErr instead of noStdErr >> >> Done. >> >> , then add the command line option --ignore-stderr? >> >> ("noStdErr" could be misinterpreted as something like --quiet). >> >> I'm curious how you're currently setting litConfig.noStdErr. >> >> -Andy >> >> On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: >> >>> >> >> >> Firstly, i've solved this exactly in such way, but Daniel Dunbar suggested me to remove command line option and add default constructor to TclTest class. So this option can be turned on/off in test/lit.site.cfg. >> > > Looks fine to me. Can you add a comment in lit.site.cfg with an example? I know how to set TestingConfig options, but not LitConfig options. > > -Andy > > Sorry, i've mistaken lit.site.cfg with lit.cfg. The latter is the right file to put comment in. > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/1bdc863e/attachment.html From 6yearold at gmail.com Tue Aug 30 12:24:18 2011 From: 6yearold at gmail.com (arrowdodger) Date: Tue, 30 Aug 2011 21:24:18 +0400 Subject: [llvm-commits] [PATCH][llvm-lit] Add option to ignore stderr output. In-Reply-To: References:

<7519A774-C048-4151-96E9-067E52D3AB49@apple.com>

Message-ID: On Tue, Aug 30, 2011 at 9:05 PM, Andrew Trick wrote: > Thanks, please commit. > > On Aug 30, 2011, at 9:49 AM, arrowdodger wrote: > > On Tue, Aug 30, 2011 at 8:20 PM, Andrew Trick wrote: > >> On Aug 30, 2011, at 5:09 AM, arrowdodger wrote: >> >> On Tue, Aug 30, 2011 at 2:20 AM, Andrew Trick wrote: >> >>> Can we call this ignoreStdErr instead of noStdErr >>> >> >> Done. >> >> , then add the command line option --ignore-stderr? >>> >>> ("noStdErr" could be misinterpreted as something like --quiet). >>> >>> I'm curious how you're currently setting litConfig.noStdErr. >>> >>> -Andy >>> >>> On Aug 27, 2011, at 4:40 AM, arrowdodger wrote: >>> >>> >>> >>> >>> >> Firstly, i've solved this exactly in such way, but Daniel Dunbar suggested >> me to remove command line option and add default constructor to TclTest >> class. So this option can be turned on/off in test/lit.site.cfg. >> >> >> >> Looks fine to me. Can you add a comment in lit.site.cfg with an example? I >> know how to set TestingConfig options, but not LitConfig options. >> >> -Andy >> > > Sorry, i've mistaken lit.site.cfg with lit.cfg. The latter is the right > file to put comment in. > > > > I don't have commit access, please commit it for me. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/112d512d/attachment.html From echristo at apple.com Tue Aug 30 12:27:44 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 10:27:44 -0700 Subject: [llvm-commits] [PATCH]: set CR1EQ on PPC32 only when seeing floating var arg In-Reply-To: <20110830141307.GA97660@freebsd.org> References: <20110824191434.GA29249@freebsd.org> <20110830141307.GA97660@freebsd.org> Message-ID: <34E767B3-A6C2-49B9-A8D7-5122C4EFD866@apple.com> I responded with an OK on the 26th? -eric On Aug 30, 2011, at 7:13 AM, Roman Divacky wrote: > ping^2 > > On Wed, Aug 24, 2011 at 09:14:34PM +0200, Roman Divacky wrote: >> Hi, >> >> PPC32 formal arguments lowering is slightly broken, it sets CR1EQ bit >> when the call is a vararg one. It should set the bit only with vararg >> call that has floating point arguments in registers and unset the >> bit otherwise. The attached patch fixes that + test. >> >> This is normally just an optimization but it's very important in the >> kernel where doing floating point stuff is lethal. >> >> OK to commit? >> >> thank you, roman > > >> ; RUN: llc < %s | FileCheck %s >> ; ModuleID = 'test.c' >> target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" >> target triple = "powerpc-unknown-freebsd" >> >> @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 >> @.str1 = private unnamed_addr constant [4 x i8] c"%f\0A\00", align 1 >> >> define void @foo() nounwind { >> entry: >> ; CHECK: crxor 6, 6, 6 >> %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 1) >> ; CHECK: creqv 6, 6, 6 >> %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), double 1.100000e+00) >> ret void >> } >> >> declare i32 @printf(i8*, ...) > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Aug 30 12:34:11 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 30 Aug 2011 10:34:11 -0700 Subject: [llvm-commits] [llvm] r138791 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/2011-08-29-SchedCycle.ll test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll In-Reply-To: <20110830013454.B88D72A6C12C@llvm.org> References: <20110830013454.B88D72A6C12C@llvm.org> Message-ID: <436241FF-0030-44B0-99B4-40387121927C@apple.com> The patch is incomplete. I'm working on a follow up now. Evan On Aug 29, 2011, at 6:34 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Aug 29 20:34:54 2011 > New Revision: 138791 > > URL: http://llvm.org/viewvc/llvm-project?rev=138791&view=rev > Log: > Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical > register dependency (rather than glue them together). This is general > goodness as it gives scheduler more freedom. However it is motivated by > a nasty bug in isel. > > When a i64 sub is expanded to subc + sube. > libcall #1 > \ > \ subc > \ / \ > \ / \ > \ / libcall #2 > sube > > If the libcalls are not serialized (i.e. both have chains which are dag > entry), legalizer can serialize them in arbitrary orders. If it's > unlucky, it can force libcall #2 before libcall #1 in the above case. > > subc > | > libcall #2 > | > libcall #1 > | > sube > > However since subc and sube are "glued" together, this ends up being a > cycle when the scheduler combine subc and sube as a single scheduling > unit. > > The right solution is to fix LegalizeType too chains the libcalls together. > However, LegalizeType is not processing nodes in order so that's harder than > it should be. For now, the move to physical register dependency will do. > > rdar://10019576 > > Added: > llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll > Modified: > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.h > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td > llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Aug 29 20:34:54 2011 > @@ -374,6 +374,13 @@ > return ARM::GPRRegisterClass; > } > > +const TargetRegisterClass * > +ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { > + if (RC == &ARM::CCRRegClass) > + return 0; // Can't copy CCR registers. > + return RC; > +} > + > unsigned > ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, > MachineFunction &MF) const { > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Aug 29 20:34:54 2011 > @@ -116,6 +116,8 @@ > unsigned &NewSubIdx) const; > > const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const; > + const TargetRegisterClass* > + getCrossCopyRegClass(const TargetRegisterClass *RC) const; > > const TargetRegisterClass* > getLargestLegalSuperClass(const TargetRegisterClass *RC) const; > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Aug 29 20:34:54 2011 > @@ -551,6 +551,14 @@ > setOperationAction(ISD::SRL, MVT::i64, Custom); > setOperationAction(ISD::SRA, MVT::i64, Custom); > > + if (!Subtarget->isThumb1Only()) { > + // FIXME: We should do this for Thumb1 as well. > + setOperationAction(ISD::ADDC, MVT::i32, Custom); > + setOperationAction(ISD::ADDE, MVT::i32, Custom); > + setOperationAction(ISD::SUBC, MVT::i32, Custom); > + setOperationAction(ISD::SUBE, MVT::i32, Custom); > + } > + > // ARM does not have ROTL. > setOperationAction(ISD::ROTL, MVT::i32, Expand); > setOperationAction(ISD::CTTZ, MVT::i32, Custom); > @@ -813,6 +821,11 @@ > case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; > case ARMISD::RRX: return "ARMISD::RRX"; > > + case ARMISD::ADDC: return "ARMISD::ADDC"; > + case ARMISD::ADDE: return "ARMISD::ADDE"; > + case ARMISD::SUBC: return "ARMISD::SUBC"; > + case ARMISD::SUBE: return "ARMISD::SUBE"; > + > case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; > case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; > > @@ -4812,6 +4825,27 @@ > return N0; > } > > +static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { > + EVT VT = Op.getNode()->getValueType(0); > + SDVTList VTs = DAG.getVTList(VT, MVT::i32); > + > + unsigned Opc; > + bool ExtraOp = false; > + switch (Op.getOpcode()) { > + default: assert(0 && "Invalid code"); > + case ISD::ADDC: Opc = ARMISD::ADDC; break; > + case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; > + case ISD::SUBC: Opc = ARMISD::SUBC; break; > + case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; > + } > + > + if (!ExtraOp) > + return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), > + Op.getOperand(1)); > + return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), > + Op.getOperand(1), Op.getOperand(2)); > +} > + > SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { > switch (Op.getOpcode()) { > default: llvm_unreachable("Don't know how to custom lower this!"); > @@ -4859,6 +4893,10 @@ > case ISD::MUL: return LowerMUL(Op, DAG); > case ISD::SDIV: return LowerSDIV(Op, DAG); > case ISD::UDIV: return LowerUDIV(Op, DAG); > + case ISD::ADDC: > + case ISD::ADDE: > + case ISD::SUBC: > + case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); > } > return SDValue(); > } > @@ -5208,76 +5246,6 @@ > llvm_unreachable("Expecting a BB with two successors!"); > } > > -// FIXME: This opcode table should obviously be expressed in the target > -// description. We probably just need a "machine opcode" value in the pseudo > -// instruction. But the ideal solution maybe to simply remove the "S" version > -// of the opcode altogether. > -struct AddSubFlagsOpcodePair { > - unsigned PseudoOpc; > - unsigned MachineOpc; > -}; > - > -static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { > - {ARM::ADCSri, ARM::ADCri}, > - {ARM::ADCSrr, ARM::ADCrr}, > - {ARM::ADCSrsi, ARM::ADCrsi}, > - {ARM::ADCSrsr, ARM::ADCrsr}, > - {ARM::SBCSri, ARM::SBCri}, > - {ARM::SBCSrr, ARM::SBCrr}, > - {ARM::SBCSrsi, ARM::SBCrsi}, > - {ARM::SBCSrsr, ARM::SBCrsr}, > - {ARM::RSBSri, ARM::RSBri}, > - {ARM::RSBSrr, ARM::RSBrr}, > - {ARM::RSBSrsi, ARM::RSBrsi}, > - {ARM::RSBSrsr, ARM::RSBrsr}, > - {ARM::RSCSri, ARM::RSCri}, > - {ARM::RSCSrsi, ARM::RSCrsi}, > - {ARM::RSCSrsr, ARM::RSCrsr}, > - {ARM::t2ADCSri, ARM::t2ADCri}, > - {ARM::t2ADCSrr, ARM::t2ADCrr}, > - {ARM::t2ADCSrs, ARM::t2ADCrs}, > - {ARM::t2SBCSri, ARM::t2SBCri}, > - {ARM::t2SBCSrr, ARM::t2SBCrr}, > - {ARM::t2SBCSrs, ARM::t2SBCrs}, > - {ARM::t2RSBSri, ARM::t2RSBri}, > - {ARM::t2RSBSrs, ARM::t2RSBrs}, > -}; > - > -// Convert and Add or Subtract with Carry and Flags to a generic opcode with > -// CPSR operand. e.g. ADCS (...) -> ADC (... CPSR). > -// > -// FIXME: Somewhere we should assert that CPSR is in the correct > -// position to be recognized by the target descrition as the 'S' bit. > -bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI, > - MachineBasicBlock *BB) const { > - unsigned OldOpc = MI->getOpcode(); > - unsigned NewOpc = 0; > - > - // This is only called for instructions that need remapping, so iterating over > - // the tiny opcode table is not costly. > - static const int NPairs = > - sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair); > - for (const AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0], > - *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) { > - if (OldOpc == Pair->PseudoOpc) { > - NewOpc = Pair->MachineOpc; > - break; > - } > - } > - if (!NewOpc) > - return false; > - > - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); > - DebugLoc dl = MI->getDebugLoc(); > - MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); > - for (unsigned i = 0; i < MI->getNumOperands(); ++i) > - MIB.addOperand(MI->getOperand(i)); > - AddDefaultPred(MIB); > - MIB.addReg(ARM::CPSR, RegState::Define); // S bit > - MI->eraseFromParent(); > - return true; > -} > - > MachineBasicBlock * > ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, > MachineBasicBlock *BB) const { > @@ -5286,9 +5254,6 @@ > bool isThumb2 = Subtarget->isThumb2(); > switch (MI->getOpcode()) { > default: { > - if (RemapAddSubWithFlags(MI, BB)) > - return BB; > - > MI->dump(); > llvm_unreachable("Unexpected instr type to insert"); > } > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Aug 29 20:34:54 2011 > @@ -71,6 +71,11 @@ > SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. > RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. > > + ADDC, // Add with carry > + ADDE, // Add using carry > + SUBC, // Sub with carry > + SUBE, // Sub using carry > + > VMOVRRD, // double to two gprs. > VMOVDRR, // Two gprs to double. > > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 29 20:34:54 2011 > @@ -70,6 +70,18 @@ > def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, > SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; > > +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, > + [SDTCisSameAs<0, 2>, > + SDTCisSameAs<0, 3>, > + SDTCisInt<0>, SDTCisVT<1, i32>]>; > + > +// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR > +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, > + [SDTCisSameAs<0, 2>, > + SDTCisSameAs<0, 3>, > + SDTCisInt<0>, > + SDTCisVT<1, i32>, > + SDTCisVT<4, i32>]>; > // Node definitions. > def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; > def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>; > @@ -120,6 +132,12 @@ > def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; > def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; > > +def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, > + [SDNPCommutative]>; > +def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; > +def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; > +def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; > + > def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; > def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", > SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>; > @@ -263,24 +281,11 @@ > let ParserMatchClass = Imm0_65535AsmOperand; > } > > +class BinOpWithFlagFrag : > + PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; > class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; > class UnOpFrag : PatFrag<(ops node:$Src), res>; > > -/// adde and sube predicates - True based on whether the carry flag output > -/// will be needed or not. > -def adde_dead_carry : > - PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), > - [{return !N->hasAnyUseOfValue(1);}]>; > -def sube_dead_carry : > - PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), > - [{return !N->hasAnyUseOfValue(1);}]>; > -def adde_live_carry : > - PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), > - [{return N->hasAnyUseOfValue(1);}]>; > -def sube_live_carry : > - PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), > - [{return N->hasAnyUseOfValue(1);}]>; > - > // An 'and' node with a single use. > def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ > return N->hasOneUse(); > @@ -939,6 +944,161 @@ > > } > > +/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are > +/// reversed. The 'rr' form is only defined for the disassembler; for codegen > +/// it is equivalent to the AsI1_bin_irs counterpart. > +multiclass AsI1_rbin_irs opcod, string opc, > + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, > + PatFrag opnode, string baseOpc, bit Commutable = 0> { > + // The register-immediate version is re-materializable. This is useful > + // in particular for taking the address of a local. > + let isReMaterializable = 1 in { > + def ri : AsI1 + iii, opc, "\t$Rd, $Rn, $imm", > + [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> imm; > + let Inst{25} = 1; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-0} = imm; > + } > + } > + def rr : AsI1 + iir, opc, "\t$Rd, $Rn, $Rm", > + [/* pattern left blank */]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<4> Rm; > + let Inst{11-4} = 0b00000000; > + let Inst{25} = 0; > + let Inst{3-0} = Rm; > + let Inst{15-12} = Rd; > + let Inst{19-16} = Rn; > + } > + > + def rsi : AsI1 + (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, > + iis, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-5} = shift{11-5}; > + let Inst{4} = 0; > + let Inst{3-0} = shift{3-0}; > + } > + > + def rsr : AsI1 + (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, > + iis, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-8} = shift{11-8}; > + let Inst{7} = 0; > + let Inst{6-5} = shift{6-5}; > + let Inst{4} = 1; > + let Inst{3-0} = shift{3-0}; > + } > + > + // Assembly aliases for optional destination operand when it's the same > + // as the source operand. > + def : InstAlias + (!cast(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, > + so_imm:$imm, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, > + GPR:$Rm, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, > + so_reg_imm:$shift, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, > + so_reg_reg:$shift, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + > +} > + > +/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit. > +let isCodeGenOnly = 1, Defs = [CPSR] in { > +multiclass AsI1_rbin_s_is opcod, string opc, > + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, > + PatFrag opnode, bit Commutable = 0> { > + def ri : AsI1 + iii, opc, "\t$Rd, $Rn, $imm", > + [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> imm; > + let Inst{25} = 1; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-0} = imm; > + } > + > + def rr : AsI1 + iir, opc, "\t$Rd, $Rn, $Rm", > + [/* pattern left blank */]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<4> Rm; > + let Inst{11-4} = 0b00000000; > + let Inst{25} = 0; > + let Inst{3-0} = Rm; > + let Inst{15-12} = Rd; > + let Inst{19-16} = Rn; > + } > + > + def rsi : AsI1 + (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, > + iis, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-5} = shift{11-5}; > + let Inst{4} = 0; > + let Inst{3-0} = shift{3-0}; > + } > + > + def rsr : AsI1 + (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, > + iis, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-8} = shift{11-8}; > + let Inst{7} = 0; > + let Inst{6-5} = shift{6-5}; > + let Inst{4} = 1; > + let Inst{3-0} = shift{3-0}; > + } > +} > +} > + > /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the > /// instruction modifies the CPSR register. > let isCodeGenOnly = 1, Defs = [CPSR] in { > @@ -947,7 +1107,7 @@ > PatFrag opnode, bit Commutable = 0> { > def ri : AI1 iii, opc, "\t$Rd, $Rn, $imm", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> { > bits<4> Rd; > bits<4> Rn; > bits<12> imm; > @@ -959,7 +1119,7 @@ > } > def rr : AI1 iir, opc, "\t$Rd, $Rn, $Rm", > - [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> { > bits<4> Rd; > bits<4> Rn; > bits<4> Rm; > @@ -974,7 +1134,7 @@ > def rsi : AI1 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, > iis, opc, "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> { > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> { > bits<4> Rd; > bits<4> Rn; > bits<12> shift; > @@ -987,10 +1147,10 @@ > let Inst{3-0} = shift{3-0}; > } > > - def rsr : AI1 + def rsr : AI1 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, > iis, opc, "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> { > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> { > bits<4> Rd; > bits<4> Rn; > bits<12> shift; > @@ -1130,10 +1290,10 @@ > /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. > multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, > string baseOpc, bit Commutable = 0> { > - let Uses = [CPSR] in { > + let Defs = [CPSR], Uses = [CPSR] in { > def ri : AsI1 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, > Requires<[IsARM]> { > bits<4> Rd; > bits<4> Rn; > @@ -1145,7 +1305,7 @@ > } > def rr : AsI1 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", > - [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, > Requires<[IsARM]> { > bits<4> Rd; > bits<4> Rn; > @@ -1160,7 +1320,7 @@ > def rsi : AsI1 (ins GPR:$Rn, so_reg_imm:$shift), > DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, > Requires<[IsARM]> { > bits<4> Rd; > bits<4> Rn; > @@ -1175,7 +1335,7 @@ > def rsr : AsI1 (ins GPR:$Rn, so_reg_reg:$shift), > DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, > + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>, > Requires<[IsARM]> { > bits<4> Rd; > bits<4> Rn; > @@ -1190,6 +1350,7 @@ > let Inst{3-0} = shift{3-0}; > } > } > + > // Assembly aliases for optional destination operand when it's the same > // as the source operand. > def : InstAlias @@ -1214,25 +1375,88 @@ > Requires<[IsARM]>; > } > > -// Carry setting variants > -// NOTE: CPSR def omitted because it will be handled by the custom inserter. > -let usesCustomInserter = 1 in { > -multiclass AI1_adde_sube_s_irs { > - def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), > - 4, IIC_iALUi, > - [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>; > - def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), > - 4, IIC_iALUr, > - [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { > - let isCommutable = Commutable; > +/// AI1_rsc_irs - Define instructions and patterns for rsc > +multiclass AI1_rsc_irs opcod, string opc, PatFrag opnode, > + string baseOpc> { > + let Defs = [CPSR], Uses = [CPSR] in { > + def ri : AsI1 + DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", > + [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, > + Requires<[IsARM]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> imm; > + let Inst{25} = 1; > + let Inst{15-12} = Rd; > + let Inst{19-16} = Rn; > + let Inst{11-0} = imm; > } > - def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>; > - def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>; > -} > + def rr : AsI1 + DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", > + [/* pattern left blank */]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<4> Rm; > + let Inst{11-4} = 0b00000000; > + let Inst{25} = 0; > + let Inst{3-0} = Rm; > + let Inst{15-12} = Rd; > + let Inst{19-16} = Rn; > + } > + def rsi : AsI1 + DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, > + Requires<[IsARM]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-5} = shift{11-5}; > + let Inst{4} = 0; > + let Inst{3-0} = shift{3-0}; > + } > + def rsr : AsI1 + DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", > + [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, > + Requires<[IsARM]> { > + bits<4> Rd; > + bits<4> Rn; > + bits<12> shift; > + let Inst{25} = 0; > + let Inst{19-16} = Rn; > + let Inst{15-12} = Rd; > + let Inst{11-8} = shift{11-8}; > + let Inst{7} = 0; > + let Inst{6-5} = shift{6-5}; > + let Inst{4} = 1; > + let Inst{3-0} = shift{3-0}; > + } > + } > + > + // Assembly aliases for optional destination operand when it's the same > + // as the source operand. > + def : InstAlias + (!cast(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, > + so_imm:$imm, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, > + GPR:$Rm, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, > + so_reg_imm:$shift, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > + def : InstAlias + (!cast(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, > + so_reg_reg:$shift, pred:$p, > + cc_out:$s)>, > + Requires<[IsARM]>; > } > > let canFoldAsLoad = 1, isReMaterializable = 1 in { > @@ -2882,182 +3106,44 @@ > // ADD and SUB with 's' bit set. > defm ADDS : AI1_bin_s_irs<0b0100, "adds", > IIC_iALUi, IIC_iALUr, IIC_iALUsr, > - BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; > + BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; > defm SUBS : AI1_bin_s_irs<0b0010, "subs", > IIC_iALUi, IIC_iALUr, IIC_iALUsr, > - BinOpFrag<(subc node:$LHS, node:$RHS)>>; > + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; > > defm ADC : AI1_adde_sube_irs<0b0101, "adc", > - BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, > + BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, > "ADC", 1>; > defm SBC : AI1_adde_sube_irs<0b0110, "sbc", > - BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>, > + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, > "SBC">; > > -// ADC and SUBC with 's' bit set. > -let usesCustomInserter = 1 in { > -defm ADCS : AI1_adde_sube_s_irs< > - BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; > -defm SBCS : AI1_adde_sube_s_irs< > - BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; > -} > - > -def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, > - IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm", > - [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> imm; > - let Inst{25} = 1; > - let Inst{15-12} = Rd; > - let Inst{19-16} = Rn; > - let Inst{11-0} = imm; > -} > - > -def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, > - IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm", []> { > - bits<4> Rd; > - bits<4> Rn; > - bits<4> Rm; > - let Inst{11-4} = 0b00000000; > - let Inst{25} = 0; > - let Inst{3-0} = Rm; > - let Inst{15-12} = Rd; > - let Inst{19-16} = Rn; > -} > - > -def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), > - DPSoRegImmFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> shift; > - let Inst{25} = 0; > - let Inst{19-16} = Rn; > - let Inst{15-12} = Rd; > - let Inst{11-5} = shift{11-5}; > - let Inst{4} = 0; > - let Inst{3-0} = shift{3-0}; > -} > - > -def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), > - DPSoRegRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> shift; > - let Inst{25} = 0; > - let Inst{19-16} = Rn; > - let Inst{15-12} = Rd; > - let Inst{11-8} = shift{11-8}; > - let Inst{7} = 0; > - let Inst{6-5} = shift{6-5}; > - let Inst{4} = 1; > - let Inst{3-0} = shift{3-0}; > -} > - > -// RSB with 's' bit set. > -// NOTE: CPSR def omitted because it will be handled by the custom inserter. > -let usesCustomInserter = 1 in { > -def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), > - 4, IIC_iALUi, > - [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>; > -def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), > - 4, IIC_iALUr, []>; > -def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>; > -def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>; > -} > - > -let Uses = [CPSR] in { > -def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), > - DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm", > - [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, > - Requires<[IsARM]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> imm; > - let Inst{25} = 1; > - let Inst{15-12} = Rd; > - let Inst{19-16} = Rn; > - let Inst{11-0} = imm; > -} > -def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), > - DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm", []> { > - bits<4> Rd; > - bits<4> Rn; > - bits<4> Rm; > - let Inst{11-4} = 0b00000000; > - let Inst{25} = 0; > - let Inst{3-0} = Rm; > - let Inst{15-12} = Rd; > - let Inst{19-16} = Rn; > -} > -def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), > - DPSoRegImmFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>, > - Requires<[IsARM]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> shift; > - let Inst{25} = 0; > - let Inst{19-16} = Rn; > - let Inst{15-12} = Rd; > - let Inst{11-5} = shift{11-5}; > - let Inst{4} = 0; > - let Inst{3-0} = shift{3-0}; > -} > -def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), > - DPSoRegRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift", > - [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>, > - Requires<[IsARM]> { > - bits<4> Rd; > - bits<4> Rn; > - bits<12> shift; > - let Inst{25} = 0; > - let Inst{19-16} = Rn; > - let Inst{15-12} = Rd; > - let Inst{11-8} = shift{11-8}; > - let Inst{7} = 0; > - let Inst{6-5} = shift{6-5}; > - let Inst{4} = 1; > - let Inst{3-0} = shift{3-0}; > -} > -} > - > +defm RSB : AsI1_rbin_irs <0b0011, "rsb", > + IIC_iALUi, IIC_iALUr, IIC_iALUsr, > + BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">; > +defm RSBS : AsI1_rbin_s_is<0b0011, "rsb", > + IIC_iALUi, IIC_iALUr, IIC_iALUsr, > + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; > > -// NOTE: CPSR def omitted because it will be handled by the custom inserter. > -let usesCustomInserter = 1, Uses = [CPSR] in { > -def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), > - 4, IIC_iALUi, > - [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>; > -def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>; > -def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), > - 4, IIC_iALUsr, > - [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>; > -} > +defm RSC : AI1_rsc_irs<0b0111, "rsc", > + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, > + "RSC">; > > // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. > // The assume-no-carry-in form uses the negation of the input since add/sub > // assume opposite meanings of the carry flag (i.e., carry == !borrow). > // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory > // details. > -def : ARMPat<(add GPR:$src, so_imm_neg:$imm), > - (SUBri GPR:$src, so_imm_neg:$imm)>; > -def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), > - (SUBSri GPR:$src, so_imm_neg:$imm)>; > +def : ARMPat<(add GPR:$src, so_imm_neg:$imm), > + (SUBri GPR:$src, so_imm_neg:$imm)>; > +def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), > + (SUBSri GPR:$src, so_imm_neg:$imm)>; > + > // The with-carry-in form matches bitwise not instead of the negation. > // Effectively, the inverse interpretation of the carry flag already accounts > // for part of the negation. > -def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm), > - (SBCri GPR:$src, so_imm_not:$imm)>; > -def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm), > - (SBCSri GPR:$src, so_imm_not:$imm)>; > +def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), > + (SBCri GPR:$src, so_imm_not:$imm)>; > > // Note: These are implemented in C++ code, because they have to generate > // ADD/SUBrs instructions, which use a complex pattern that a xform function > @@ -4803,29 +4889,6 @@ > def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; > def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; > > -// RSB two-operand forms (optional explicit destination operand) > -def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm", > - (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; > -def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm", > - (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; > -def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", > - (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, > - cc_out:$s)>; > -def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift", > - (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, > - cc_out:$s)>; > -// RSC two-operand forms (optional explicit destination operand) > -def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm", > - (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>; > -def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm", > - (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>; > -def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", > - (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, > - cc_out:$s)>; > -def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift", > - (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, > - cc_out:$s)>; > - > // SSAT/USAT optional shift operand. > def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", > (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 29 20:34:54 2011 > @@ -582,7 +582,7 @@ > def ri : T2TwoRegImm< > (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, > !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", > - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { > + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> { > let Inst{31-27} = 0b11110; > let Inst{25} = 0; > let Inst{24-21} = opcod; > @@ -593,7 +593,7 @@ > def rr : T2ThreeReg< > (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, > !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm", > - [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { > + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> { > let isCommutable = Commutable; > let Inst{31-27} = 0b11101; > let Inst{26-25} = 0b01; > @@ -607,7 +607,7 @@ > def rs : T2TwoRegShiftedReg< > (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, > !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm", > - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { > + [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { > let Inst{31-27} = 0b11101; > let Inst{26-25} = 0b01; > let Inst{24-21} = opcod; > @@ -682,13 +682,13 @@ > /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns > /// for a binary operation that produces a value and use the carry > /// bit. It's not predicable. > -let Uses = [CPSR] in { > +let Defs = [CPSR], Uses = [CPSR] in { > multiclass T2I_adde_sube_irs opcod, string opc, PatFrag opnode, > bit Commutable = 0> { > // shifted imm > def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), > IIC_iALUi, opc, "\t$Rd, $Rn, $imm", > - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, > + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, > Requires<[IsThumb2]> { > let Inst{31-27} = 0b11110; > let Inst{25} = 0; > @@ -698,7 +698,7 @@ > // register > def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, > opc, ".w\t$Rd, $Rn, $Rm", > - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, > + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, > Requires<[IsThumb2]> { > let isCommutable = Commutable; > let Inst{31-27} = 0b11101; > @@ -712,7 +712,7 @@ > def rs : T2sTwoRegShiftedReg< > (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), > IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", > - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, > + [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, > Requires<[IsThumb2]> { > let Inst{31-27} = 0b11101; > let Inst{26-25} = 0b01; > @@ -721,28 +721,6 @@ > } > } > > -// Carry setting variants > -// NOTE: CPSR def omitted because it will be handled by the custom inserter. > -let usesCustomInserter = 1 in { > -multiclass T2I_adde_sube_s_irs { > - // shifted imm > - def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), > - 4, IIC_iALUi, > - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>; > - // register > - def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), > - 4, IIC_iALUr, > - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { > - let isCommutable = Commutable; > - } > - // shifted register > - def rs : t2PseudoInst< > - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), > - 4, IIC_iALUsi, > - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>; > -} > -} > - > /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register > /// version is not needed since this is only for codegen. > let isCodeGenOnly = 1, Defs = [CPSR] in { > @@ -751,7 +729,7 @@ > def ri : T2TwoRegImm< > (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, > !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", > - [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { > + [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { > let Inst{31-27} = 0b11110; > let Inst{25} = 0; > let Inst{24-21} = opcod; > @@ -762,7 +740,7 @@ > def rs : T2TwoRegShiftedReg< > (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), > IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm", > - [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { > + [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { > let Inst{31-27} = 0b11101; > let Inst{26-25} = 0b01; > let Inst{24-21} = opcod; > @@ -1678,25 +1656,21 @@ > // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. > defm t2ADDS : T2I_bin_s_irs <0b1000, "add", > IIC_iALUi, IIC_iALUr, IIC_iALUsi, > - BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; > + BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; > defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", > IIC_iALUi, IIC_iALUr, IIC_iALUsi, > - BinOpFrag<(subc node:$LHS, node:$RHS)>>; > + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; > > defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", > - BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; > + BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; > defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", > - BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; > -defm t2ADCS : T2I_adde_sube_s_irs - node:$RHS)>, 1>; > -defm t2SBCS : T2I_adde_sube_s_irs - node:$RHS)>>; > + BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; > > // RSB > defm t2RSB : T2I_rbin_irs <0b1110, "rsb", > BinOpFrag<(sub node:$LHS, node:$RHS)>>; > defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", > - BinOpFrag<(subc node:$LHS, node:$RHS)>>; > + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; > > // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. > // The assume-no-carry-in form uses the negation of the input since add/sub > @@ -1713,23 +1687,18 @@ > def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), > (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; > let AddedComplexity = 1 in > -def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm), > +def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm), > (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; > -def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm), > +def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), > (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; > // The with-carry-in form matches bitwise not instead of the negation. > // Effectively, the inverse interpretation of the carry flag already accounts > // for part of the negation. > let AddedComplexity = 1 in > -def : T2Pat<(adde_dead_carry rGPR:$src, imm0_255_not:$imm), > +def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), > (t2SBCri rGPR:$src, imm0_255_not:$imm)>; > -def : T2Pat<(adde_dead_carry rGPR:$src, t2_so_imm_not:$imm), > +def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), > (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; > -let AddedComplexity = 1 in > -def : T2Pat<(adde_live_carry rGPR:$src, imm0_255_not:$imm), > - (t2SBCSri rGPR:$src, imm0_255_not:$imm)>; > -def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm), > - (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>; > > // Select Bytes -- for disassembly only > > > Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Aug 29 20:34:54 2011 > @@ -347,5 +347,6 @@ > > // Condition code registers. > def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { > + let CopyCost = -1; // Don't allow copying of status registers. > let isAllocatable = 0; > } > > Added: llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll?rev=138791&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/2011-08-29-SchedCycle.ll Mon Aug 29 20:34:54 2011 > @@ -0,0 +1,45 @@ > +; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o - > + > +; When a i64 sub is expanded to subc + sube. > +; libcall #1 > +; \ > +; \ subc > +; \ / \ > +; \ / \ > +; \ / libcall #2 > +; sube > +; > +; If the libcalls are not serialized (i.e. both have chains which are dag > +; entry), legalizer can serialize them in arbitrary orders. If it's > +; unlucky, it can force libcall #2 before libcall #1 in the above case. > +; > +; subc > +; | > +; libcall #2 > +; | > +; libcall #1 > +; | > +; sube > +; > +; However since subc and sube are "glued" together, this ends up being a > +; cycle when the scheduler combine subc and sube as a single scheduling > +; unit. > +; > +; The right solution is to fix LegalizeType too chains the libcalls together. > +; However, LegalizeType is not processing nodes in order. The fix now is to > +; fix subc / sube (and addc / adde) to use physical register dependency instead. > +; rdar://10019576 > + > +define void @t() nounwind { > +entry: > + %tmp = load i64* undef, align 4 > + %tmp5 = udiv i64 %tmp, 30 > + %tmp13 = and i64 %tmp5, 64739244643450880 > + %tmp16 = sub i64 0, %tmp13 > + %tmp19 = and i64 %tmp16, 63 > + %tmp20 = urem i64 %tmp19, 3 > + %tmp22 = and i64 %tmp16, -272346829004752 > + store i64 %tmp22, i64* undef, align 4 > + store i64 %tmp20, i64* undef, align 4 > + ret void > +} > > Modified: llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll?rev=138791&r1=138790&r2=138791&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll (original) > +++ llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Mon Aug 29 20:34:54 2011 > @@ -6,8 +6,8 @@ > ; -- The loop following the load should only use a single add-literation > ; instruction. > ; CHECK: ldr.64 > -; CHECK: adds r{{[0-9]+}}, #1 > -; CHECK-NOT: adds r{{[0-9]+}}, #1 > +; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 > +; CHECK-NOT: adds r{{[0-9]+}}, r{{[0-9]+}}, #1 > ; CHECK: subsections_via_symbols > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Tue Aug 30 12:42:33 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 30 Aug 2011 17:42:33 -0000 Subject: [llvm-commits] [llvm] r138804 - in /llvm/trunk: test/lit.cfg utils/lit/lit/LitConfig.py utils/lit/lit/TestFormats.py utils/lit/lit/TestRunner.py utils/lit/lit/main.py Message-ID: <20110830174233.49D322A6C12C@llvm.org> Author: atrick Date: Tue Aug 30 12:42:33 2011 New Revision: 138804 URL: http://llvm.org/viewvc/llvm-project?rev=138804&view=rev Log: Lit option for ignoring stderr output. This is useful for testing a build a temporarily hand instrumented build. Patch by arrowdodger! Modified: llvm/trunk/test/lit.cfg llvm/trunk/utils/lit/lit/LitConfig.py llvm/trunk/utils/lit/lit/TestFormats.py llvm/trunk/utils/lit/lit/TestRunner.py llvm/trunk/utils/lit/lit/main.py Modified: llvm/trunk/test/lit.cfg URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=138804&r1=138803&r2=138804&view=diff ============================================================================== --- llvm/trunk/test/lit.cfg (original) +++ llvm/trunk/test/lit.cfg Tue Aug 30 12:42:33 2011 @@ -12,6 +12,9 @@ # testFormat: The test format to use to interpret tests. config.test_format = lit.formats.TclTest() +# To ignore test output on stderr so it doesn't trigger failures uncomment this: +#config.test_format = lit.formats.TclTest(ignoreStdErr=True) + # suffixes: A list of file extensions to treat as test files, this is actually # set by on_clone(). config.suffixes = [] Modified: llvm/trunk/utils/lit/lit/LitConfig.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/LitConfig.py?rev=138804&r1=138803&r2=138804&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/LitConfig.py (original) +++ llvm/trunk/utils/lit/lit/LitConfig.py Tue Aug 30 12:42:33 2011 @@ -20,7 +20,7 @@ def __init__(self, progname, path, quiet, useValgrind, valgrindLeakCheck, valgrindArgs, useTclAsSh, - noExecute, debug, isWindows, + noExecute, ignoreStdErr, debug, isWindows, params): # The name of the test runner. self.progname = progname @@ -32,6 +32,7 @@ self.valgrindUserArgs = list(valgrindArgs) self.useTclAsSh = bool(useTclAsSh) self.noExecute = noExecute + self.ignoreStdErr = ignoreStdErr self.debug = debug self.isWindows = bool(isWindows) self.params = dict(params) Modified: llvm/trunk/utils/lit/lit/TestFormats.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestFormats.py?rev=138804&r1=138803&r2=138804&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/TestFormats.py (original) +++ llvm/trunk/utils/lit/lit/TestFormats.py Tue Aug 30 12:42:33 2011 @@ -125,7 +125,11 @@ self.execute_external) class TclTest(FileBasedTest): + def __init__(self, ignoreStdErr=False): + self.ignoreStdErr = ignoreStdErr + def execute(self, test, litConfig): + litConfig.ignoreStdErr = self.ignoreStdErr return TestRunner.executeTclTest(test, litConfig) ### Modified: llvm/trunk/utils/lit/lit/TestRunner.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138804&r1=138803&r2=138804&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/TestRunner.py (original) +++ llvm/trunk/utils/lit/lit/TestRunner.py Tue Aug 30 12:42:33 2011 @@ -535,13 +535,13 @@ # considered to fail if there is any standard error output. out,err,exitCode = res if isXFail: - ok = exitCode != 0 or err + ok = exitCode != 0 or err and not litConfig.ignoreStdErr if ok: status = Test.XFAIL else: status = Test.XPASS else: - ok = exitCode == 0 and not err + ok = exitCode == 0 and (not err or litConfig.ignoreStdErr) if ok: status = Test.PASS else: @@ -552,7 +552,7 @@ # Set a flag for formatTestOutput so it can explain why the test was # considered to have failed, despite having an exit code of 0. - failDueToStderr = exitCode == 0 and err + failDueToStderr = exitCode == 0 and err and not litConfig.ignoreStdErr return formatTestOutput(status, out, err, exitCode, failDueToStderr, script) Modified: llvm/trunk/utils/lit/lit/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/main.py?rev=138804&r1=138803&r2=138804&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/main.py (original) +++ llvm/trunk/utils/lit/lit/main.py Tue Aug 30 12:42:33 2011 @@ -328,6 +328,7 @@ valgrindArgs = [], useTclAsSh = False, noExecute = False, + ignoreStdErr = False, debug = False, isWindows = (platform.system()=='Windows'), params = {}) @@ -485,6 +486,7 @@ valgrindArgs = opts.valgrindArgs, useTclAsSh = opts.useTclAsSh, noExecute = opts.noExecute, + ignoreStdErr = False, debug = opts.debug, isWindows = (platform.system()=='Windows'), params = userParams) From grosser at fim.uni-passau.de Tue Aug 30 13:26:12 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 30 Aug 2011 18:26:12 -0000 Subject: [llvm-commits] [llvm] r138805 - /llvm/trunk/docs/Bugpoint.html Message-ID: <20110830182612.4D5972A6C12C@llvm.org> Author: grosser Date: Tue Aug 30 13:26:11 2011 New Revision: 138805 URL: http://llvm.org/viewvc/llvm-project?rev=138805&view=rev Log: Update docs: Bugpoint understands -O[123] Eli added this in revision 132695. Modified: llvm/trunk/docs/Bugpoint.html Modified: llvm/trunk/docs/Bugpoint.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Bugpoint.html?rev=138805&r1=138804&r2=138805&view=diff ============================================================================== --- llvm/trunk/docs/Bugpoint.html (original) +++ llvm/trunk/docs/Bugpoint.html Tue Aug 30 13:26:11 2011 @@ -216,18 +216,6 @@ the list of specified optimizations to be randomized and applied to the program. This process will repeat until a bug is found or the user kills bugpoint. - -

bugpoint does not understand the -O option - that is used to specify optimization level to opt. You - can use e.g.

- -

opt -O2 -debug-pass=Arguments foo.bc -disable-output

- -

to get a list of passes that are used with -O2 and - then pass this list to bugpoint.

- From benny.kra at googlemail.com Tue Aug 30 13:33:34 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 30 Aug 2011 18:33:34 -0000 Subject: [llvm-commits] [llvm] r138806 - /llvm/trunk/include/llvm/Support/MachO.h Message-ID: <20110830183334.4AC772A6C12C@llvm.org> Author: d0k Date: Tue Aug 30 13:33:34 2011 New Revision: 138806 URL: http://llvm.org/viewvc/llvm-project?rev=138806&view=rev Log: Add load commands from Lion to Macho.h. Modified: llvm/trunk/include/llvm/Support/MachO.h Modified: llvm/trunk/include/llvm/Support/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MachO.h?rev=138806&r1=138805&r2=138806&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MachO.h (original) +++ llvm/trunk/include/llvm/Support/MachO.h Tue Aug 30 13:33:34 2011 @@ -110,6 +110,10 @@ LoadCommandDynamicLinkerInfo = 0x00000022u, // LC_DYLD_INFO LoadCommandDynamicLinkerInfoOnly = 0x80000022u, // LC_DYLD_INFO_ONLY LoadCommandDylibLoadUpward = 0x80000023u, // LC_LOAD_UPWARD_DYLIB + LoadCommandVersionMinMacOSX = 0x00000024u, // LC_VERSION_MIN_MACOSX + LoadCommandVersionMinIPhoneOS = 0x00000025u, // LC_VERSION_MIN_IPHONEOS + LoadCommandFunctionStarts = 0x00000026u, // LC_FUNCTION_STARTS + LoadCommandDyldEnvironment = 0x00000027u, // LC_DYLD_ENVIRONMENT // Constant bits for the "flags" field in llvm::MachO::segment_command SegmentCommandFlagBitHighVM = 0x1u, // SG_HIGHVM @@ -569,6 +573,13 @@ uint32_t cryptid; }; + struct version_min_command { + uint32_t cmd; + uint32_t cmdsize; + uint32_t version; + uint32_t reserved; + }; + struct dyld_info_command { uint32_t cmd; uint32_t cmdsize; From benny.kra at googlemail.com Tue Aug 30 13:33:37 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 30 Aug 2011 18:33:37 -0000 Subject: [llvm-commits] [llvm] r138807 - in /llvm/trunk: include/llvm/Object/MachOFormat.h include/llvm/Object/MachOObject.h lib/Object/MachOObject.cpp tools/macho-dump/macho-dump.cpp Message-ID: <20110830183337.75CB72A6C12D@llvm.org> Author: d0k Date: Tue Aug 30 13:33:37 2011 New Revision: 138807 URL: http://llvm.org/viewvc/llvm-project?rev=138807&view=rev Log: Teach macho-dump how to dump linkedit_data load commands. Modified: llvm/trunk/include/llvm/Object/MachOFormat.h llvm/trunk/include/llvm/Object/MachOObject.h llvm/trunk/lib/Object/MachOObject.cpp llvm/trunk/tools/macho-dump/macho-dump.cpp Modified: llvm/trunk/include/llvm/Object/MachOFormat.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachOFormat.h?rev=138807&r1=138806&r2=138807&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachOFormat.h (original) +++ llvm/trunk/include/llvm/Object/MachOFormat.h Tue Aug 30 13:33:37 2011 @@ -137,7 +137,10 @@ LCT_Symtab = 0x2, LCT_Dysymtab = 0xb, LCT_Segment64 = 0x19, - LCT_UUID = 0x1b + LCT_UUID = 0x1b, + LCT_CodeSignature = 0x1d, + LCT_SegmentSplitInfo = 0x1e, + LCT_FunctionStarts = 0x26 }; /// \brief Load command structure. @@ -218,6 +221,13 @@ uint32_t NumLocalRelocationTableEntries; }; + struct LinkeditDataLoadCommand { + uint32_t Type; + uint32_t Size; + uint32_t DataOffset; + uint32_t DataSize; + }; + /// @} /// @name Section Data /// @{ Modified: llvm/trunk/include/llvm/Object/MachOObject.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachOObject.h?rev=138807&r1=138806&r2=138807&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachOObject.h (original) +++ llvm/trunk/include/llvm/Object/MachOObject.h Tue Aug 30 13:33:37 2011 @@ -150,6 +150,9 @@ void ReadDysymtabLoadCommand( const LoadCommandInfo &LCI, InMemoryStruct &Res) const; + void ReadLinkeditDataLoadCommand( + const LoadCommandInfo &LCI, + InMemoryStruct &Res) const; void ReadIndirectSymbolTableEntry( const macho::DysymtabLoadCommand &DLC, unsigned Index, Modified: llvm/trunk/lib/Object/MachOObject.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObject.cpp?rev=138807&r1=138806&r2=138807&view=diff ============================================================================== --- llvm/trunk/lib/Object/MachOObject.cpp (original) +++ llvm/trunk/lib/Object/MachOObject.cpp Tue Aug 30 13:33:37 2011 @@ -244,6 +244,18 @@ } template<> +void SwapStruct(macho::LinkeditDataLoadCommand &Value) { + SwapValue(Value.Type); + SwapValue(Value.Size); + SwapValue(Value.DataOffset); + SwapValue(Value.DataSize); +} +void MachOObject::ReadLinkeditDataLoadCommand(const LoadCommandInfo &LCI, + InMemoryStruct &Res) const { + ReadInMemoryStruct(*this, Buffer->getBuffer(), LCI.Offset, Res); +} + +template<> void SwapStruct(macho::IndirectSymbolTableEntry &Value) { SwapValue(Value.Index); } Modified: llvm/trunk/tools/macho-dump/macho-dump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/macho-dump/macho-dump.cpp?rev=138807&r1=138806&r2=138807&view=diff ============================================================================== --- llvm/trunk/tools/macho-dump/macho-dump.cpp (original) +++ llvm/trunk/tools/macho-dump/macho-dump.cpp Tue Aug 30 13:33:37 2011 @@ -310,6 +310,20 @@ return Res; } +static int DumpLinkeditDataCommand(MachOObject &Obj, + const MachOObject::LoadCommandInfo &LCI) { + InMemoryStruct LLC; + Obj.ReadLinkeditDataLoadCommand(LCI, LLC); + if (!LLC) + return Error("unable to read segment load command"); + + outs() << " ('dataoff', " << LLC->DataOffset << ")\n" + << " ('datasize', " << LLC->DataSize << ")\n"; + + return 0; +} + + static int DumpLoadCommand(MachOObject &Obj, unsigned Index) { const MachOObject::LoadCommandInfo &LCI = Obj.getLoadCommandInfo(Index); int Res = 0; @@ -330,6 +344,11 @@ case macho::LCT_Dysymtab: Res = DumpDysymtabCommand(Obj, LCI); break; + case macho::LCT_CodeSignature: + case macho::LCT_SegmentSplitInfo: + case macho::LCT_FunctionStarts: + Res = DumpLinkeditDataCommand(Obj, LCI); + break; default: Warning("unknown load command: " + Twine(LCI.Command.Type)); break; From tobias at grosser.es Tue Aug 30 13:35:08 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 30 Aug 2011 19:35:08 +0100 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

<4E5C8D2E.9010006@grosser.es> Message-ID: <4E5D2D5C.1050209@grosser.es> On 08/30/2011 01:04 PM, Villmow, Micah wrote: > Thanks for the feedback, new revision attached. There seems one unneeded white space change. (Can be fixed on commit) > SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > const SDValue *Ops, unsigned NumOps, bool isSigned, > DebugLoc dl); > + > std::pair ExpandChainLibCall(RTLIB::Libcall Otherwise, it looks good. Let's see if Eli has any additional comments. Cheers Tobi From echristo at apple.com Tue Aug 30 13:35:59 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 11:35:59 -0700 Subject: [llvm-commits] PATCH: pruning llvm w/ config flags --enable-target-oses=os1, os2 similar to --enable-target=arch1, arch2. In-Reply-To: References:

Message-ID: <66BF1CD4-DBAA-4146-9CFD-CA0C669434B8@apple.com> On Aug 29, 2011, at 4:58 PM, Jan Voung wrote: > Ping. > > - Is this approach acceptable? > - I guess it is hard to test if this has any effect / depends on the compiler. > - Is trimming the size of the llvm binaries (via config flags) useful to others? > - Other examples: > - make "include/llvm/Intrinsics.td" not #include intrinsincs for targets that were not enabled through "--enable-target" > - config flags to avoid building unused register allocators, other passes > Sorry, I didn't notice this the first time. I'll take a look shortly. -eric From resistor at mac.com Tue Aug 30 13:51:55 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 18:51:55 -0000 Subject: [llvm-commits] [llvm] r138809 - in /llvm/trunk: lib/Transforms/Scalar/DeadStoreElimination.cpp test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Message-ID: <20110830185155.522C42A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 13:51:55 2011 New Revision: 138809 URL: http://llvm.org/viewvc/llvm-project?rev=138809&view=rev Log: When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does. Added: llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=138809&r1=138808&r2=138809&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Tue Aug 30 13:51:55 2011 @@ -617,8 +617,9 @@ DeleteDeadInstruction(Dead, *MD, &DeadStackObjects); ++NumFastStores; MadeChange = true; - continue; } + + continue; } // Remove any dead non-memory-mutating instructions. Added: llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll?rev=138809&view=auto ============================================================================== --- llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll (added) +++ llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Tue Aug 30 13:51:55 2011 @@ -0,0 +1,27 @@ +; RUN: opt -dse -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin" + +%"class.std::auto_ptr" = type { i32* } + +; CHECK: @_Z3foov +define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp { +_ZNSt8auto_ptrIiED1Ev.exit: + %temp.lvalue = alloca %"class.std::auto_ptr", align 8 + call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) + %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 + %tmp.i.i = load i32** %_M_ptr.i.i, align 8, !tbaa !0 +; CHECK-NOT: store i32* null + store i32* null, i32** %_M_ptr.i.i, align 8, !tbaa !0 + %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0 + store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8, !tbaa !0 +; CHECK: ret void + ret void +} + +declare void @_Z3barv(%"class.std::auto_ptr"* sret) + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From evan.cheng at apple.com Tue Aug 30 14:09:48 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 30 Aug 2011 19:09:48 -0000 Subject: [llvm-commits] [llvm] r138810 - in /llvm/trunk: include/llvm/MC/MCInstrDesc.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/InstrEmitter.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp Message-ID: <20110830190948.C61A82A6C12C@llvm.org> Author: evancheng Date: Tue Aug 30 14:09:48 2011 New Revision: 138810 URL: http://llvm.org/viewvc/llvm-project?rev=138810&view=rev Log: Follow up to r138791. Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Tue Aug 30 14:09:48 2011 @@ -116,6 +116,7 @@ Commutable, ConvertibleTo3Addr, UsesCustomInserter, + HasPostISelHook, Rematerializable, CheapAsAMove, ExtraSrcRegAllocReq, @@ -476,6 +477,14 @@ return Flags & (1 << MCID::UsesCustomInserter); } + /// hasPostISelHook - Return true if this instruction requires *adjustment* + /// after instruction selection by calling a target hook. For example, this + /// can be used to fill in ARM 's' optional operand depending on whether + /// the conditional flag register is used. + bool hasPostISelHook() const { + return Flags & (1 << MCID::HasPostISelHook); + } + /// isRematerializable - Returns true if this instruction is a candidate for /// remat. This flag is deprecated, please don't use it anymore. If this /// flag is set, the isReallyTriviallyReMaterializable() method is called to Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Tue Aug 30 14:09:48 2011 @@ -328,6 +328,7 @@ bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomInserter = 0; // Pseudo instr needing special help. + bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Aug 30 14:09:48 2011 @@ -1471,6 +1471,13 @@ virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; + /// AdjustInstrPostInstrSelection - This method should be implemented by + /// targets that mark instructions with the 'hasPostISelHook' flag. These + /// instructions must be adjusted after instruction selection by target hooks. + /// e.g. To fill in optional defs for ARM 's' setting instructions. + virtual void + AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; + //===--------------------------------------------------------------------===// // Addressing mode description hooks (used by LSR etc). // Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Aug 30 14:09:48 2011 @@ -761,6 +761,10 @@ i != e; ++i) MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); } + + // Run post-isel target hook to adjust this instruction if needed. + if (II.hasPostISelHook()) + TLI->AdjustInstrPostInstrSelection(MI, Node); } /// EmitSpecialNode - Generate machine code for a target-independent node and Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 30 14:09:48 2011 @@ -177,6 +177,16 @@ return 0; } +void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, + SDNode *Node) const { +#ifndef NDEBUG + dbgs() << "If a target marks an instruction with " + "'hasPostISelHook', it must implement " + "TargetLowering::AdjustInstrPostInstrSelection!"; +#endif + llvm_unreachable(0); +} + //===----------------------------------------------------------------------===// // SelectionDAGISel code //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 30 14:09:48 2011 @@ -5474,6 +5474,29 @@ } } +void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, + SDNode *Node) const { + // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, + // RSB, RSC. Coming out of isel, they have an implicit CPSR def, but the + // optional operand is not filled in. If the carry bit is used, then change + // the optional operand to CPSR. Otherwise, remove the CPSR implicit def. + const MCInstrDesc &MCID = MI->getDesc(); + if (Node->hasAnyUseOfValue(1)) { + MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2); + MO.setReg(ARM::CPSR); + MO.setIsDef(true); + } else { + for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands(); + i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { + MI->RemoveOperand(i); + break; + } + } + } +} + //===----------------------------------------------------------------------===// // ARM Optimization Hooks //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Aug 30 14:09:48 2011 @@ -249,6 +249,9 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; + virtual void + AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; + SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 30 14:09:48 2011 @@ -1290,7 +1290,7 @@ /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, string baseOpc, bit Commutable = 0> { - let Defs = [CPSR], Uses = [CPSR] in { + let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { def ri : AsI1, @@ -1378,7 +1378,7 @@ /// AI1_rsc_irs - Define instructions and patterns for rsc multiclass AI1_rsc_irs opcod, string opc, PatFrag opnode, string baseOpc> { - let Defs = [CPSR], Uses = [CPSR] in { + let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { def ri : AsI1, Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 30 14:09:48 2011 @@ -1661,10 +1661,12 @@ IIC_iALUi, IIC_iALUr, IIC_iALUsi, BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; +let hasPostISelHook = 1 in { defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; +} // RSB defm t2RSB : T2I_rbin_irs <0b1110, "rsb", Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Tue Aug 30 14:09:48 2011 @@ -309,6 +309,7 @@ isReMaterializable = R->getValueAsBit("isReMaterializable"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); usesCustomInserter = R->getValueAsBit("usesCustomInserter"); + hasPostISelHook = R->getValueAsBit("hasPostISelHook"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); isNotDuplicable = R->getValueAsBit("isNotDuplicable"); hasSideEffects = R->getValueAsBit("hasSideEffects"); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Tue Aug 30 14:09:48 2011 @@ -233,6 +233,7 @@ bool isReMaterializable; bool hasDelaySlot; bool usesCustomInserter; + bool hasPostISelHook; bool hasCtrlDep; bool isNotDuplicable; bool hasSideEffects; Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=138810&r1=138809&r2=138810&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Aug 30 14:09:48 2011 @@ -288,6 +288,7 @@ if (Inst.isNotDuplicable) OS << "|(1< References: <20110817174416.558E12A6C12C@llvm.org> <848FF71B-5F72-4D02-8EA4-12BFDA137518@apple.com> Message-ID: ping? On Aug 26, 2011, at 11:56 AM, Jim Grosbach wrote: > Sorry for the late comments. I missed this catching these bits the first time around (saw the patch, just missed this aspect). > > On Aug 17, 2011, at 10:44 AM, Owen Anderson wrote: > >> Author: resistor >> Date: Wed Aug 17 12:44:15 2011 >> New Revision: 137830 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=137830&view=rev >> Log: >> Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. >> Patch by James Molloy. >> >> Modified: >> llvm/trunk/include/llvm/MC/MCDisassembler.h >> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp >> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h >> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp >> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h >> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp >> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h >> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt >> llvm/trunk/tools/llvm-mc/Disassembler.cpp >> llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp >> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp >> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h >> >> Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/MC/MCDisassembler.h (original) >> +++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Aug 17 12:44:15 2011 >> @@ -25,6 +25,34 @@ >> /// and provides an array of assembly instructions. >> class MCDisassembler { >> public: >> + /// Ternary decode status. Most backends will just use Fail and >> + /// Success, however some have a concept of an instruction with >> + /// understandable semantics but which is architecturally >> + /// incorrect. An example of this is ARM UNPREDICTABLE instructions >> + /// which are disassemblable but cause undefined behaviour. >> + /// >> + /// Because it makes sense to disassemble these instructions, there >> + /// is a "soft fail" failure mode that indicates the MCInst& is >> + /// valid but architecturally incorrect. >> + /// >> + /// The enum numbers are deliberately chosen such that reduction >> + /// from Success->SoftFail ->Fail can be done with a simple >> + /// bitwise-AND: >> + /// >> + /// LEFT & TOP = | Success Unpredictable Fail >> + /// --------------+----------------------------------- >> + /// Success | Success Unpredictable Fail >> + /// Unpredictable | Unpredictable Unpredictable Fail >> + /// Fail | Fail Fail Fail >> + /// >> + /// An easy way of encoding this is as 0b11, 0b01, 0b00 for >> + /// Success, SoftFail, Fail respectively. >> + enum DecodeStatus { >> + Fail = 0, >> + SoftFail = 1, >> + Success = 3 >> + }; >> + >> /// Constructor - Performs initial setup for the disassembler. >> MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {} >> >> @@ -41,8 +69,11 @@ >> /// @param address - The address, in the memory space of region, of the first >> /// byte of the instruction. >> /// @param vStream - The stream to print warnings and diagnostic messages on. >> - /// @return - True if the instruction is valid; false otherwise. >> - virtual bool getInstruction(MCInst& instr, >> + /// @return - MCDisassembler::Success if the instruction is valid, >> + /// MCDisassembler::SoftFail if the instruction was >> + /// disassemblable but invalid, >> + /// MCDisassembler::Fail if the instruction was invalid. >> + virtual DecodeStatus getInstruction(MCInst& instr, >> uint64_t& size, >> const MemoryObject ®ion, >> uint64_t address, >> >> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 12:44:15 2011 >> @@ -24,188 +24,201 @@ >> #include "llvm/Support/ErrorHandling.h" >> #include "llvm/Support/raw_ostream.h" >> >> +// Pull DecodeStatus and its enum values into the global namespace. >> +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; >> +#define Success llvm::MCDisassembler::Success >> +#define Unpredictable llvm::MCDisassembler::SoftFail >> +#define Fail llvm::MCDisassembler::Fail >> + > > Please don't do this sort of thing (#defines to get around scoping). Reference the names explicitly, including the scoping operators, instead. > >> +// Helper macro to perform setwise reduction of the current running status >> +// and another status, and return if the new status is Fail. >> +#define CHECK(S,X) do { \ >> + S = (DecodeStatus) ((int)S & (X)); \ > > It's better to use the enum values directly rather than casting integers like this. The code shouldn't know what the actual values of the enums are. > >> + if (S == Fail) return Fail; \ >> + } while(0) >> + > > Having an early exit buried in a macro obfuscates the code. The way the code previously did this is better. Please change this back or refactor differently. > >> // Forward declare these because the autogenerated code will reference them. >> // Definitions are further down. >> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder); >> >> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> >> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> >> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, >> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, >> unsigned Insn, >> uint64_t Adddress, >> const void *Decoder); >> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> >> >> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, >> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder); >> >> #include "ARMGenDisassemblerTables.inc" >> @@ -230,15 +243,14 @@ >> return instInfoARM; >> } >> >> - >> -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, >> - const MemoryObject &Region, >> - uint64_t Address,raw_ostream &os) const { >> +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, >> + const MemoryObject &Region, >> + uint64_t Address,raw_ostream &os) const { >> uint8_t bytes[4]; >> >> // We want to read exactly 4 bytes of data. >> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) >> - return false; >> + return Fail; >> >> // Encoded as a small-endian 32-bit word in the stream. >> uint32_t insn = (bytes[3] << 24) | >> @@ -247,10 +259,10 @@ >> (bytes[0] << 0); >> >> // Calling the auto-generated decoder function. >> - bool result = decodeARMInstruction32(MI, insn, Address, this); >> - if (result) { >> + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); >> + if (result != Fail) { >> Size = 4; >> - return true; >> + return result; >> } >> >> // Instructions that are shared between ARM and Thumb modes. >> @@ -258,53 +270,53 @@ >> // fact that we fail to encode a few instructions properly for Thumb. >> MI.clear(); >> result = decodeCommonInstruction32(MI, insn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> - return true; >> + return result; >> } >> >> // VFP and NEON instructions, similarly, are shared between ARM >> // and Thumb modes. >> MI.clear(); >> result = decodeVFPInstruction32(MI, insn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeNEONDataInstruction32(MI, insn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> // Add a fake predicate operand, because we share these instruction >> // definitions with Thumb2 where these instructions are predicable. >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; >> - return true; >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; >> + return result; >> } >> >> MI.clear(); >> result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> // Add a fake predicate operand, because we share these instruction >> // definitions with Thumb2 where these instructions are predicable. >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; >> - return true; >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; >> + return result; >> } >> >> MI.clear(); >> result = decodeNEONDupInstruction32(MI, insn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> // Add a fake predicate operand, because we share these instruction >> // definitions with Thumb2 where these instructions are predicable. >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; >> - return true; >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; >> + return result; >> } >> >> MI.clear(); >> >> - return false; >> + return Fail; >> } >> >> namespace llvm { >> @@ -403,22 +415,21 @@ >> } >> } >> >> - >> -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, >> - const MemoryObject &Region, >> - uint64_t Address,raw_ostream &os) const { >> +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, >> + const MemoryObject &Region, >> + uint64_t Address,raw_ostream &os) const { >> uint8_t bytes[4]; >> >> // We want to read exactly 2 bytes of data. >> if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) >> - return false; >> + return Fail; >> >> uint16_t insn16 = (bytes[1] << 8) | bytes[0]; >> - bool result = decodeThumbInstruction16(MI, insn16, Address, this); >> - if (result) { >> + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); >> + if (result != Fail) { >> Size = 2; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> >> MI.clear(); >> @@ -428,12 +439,12 @@ >> bool InITBlock = !ITBlock.empty(); >> AddThumbPredicate(MI); >> AddThumb1SBit(MI, InITBlock); >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeThumb2Instruction16(MI, insn16, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 2; >> AddThumbPredicate(MI); >> >> @@ -456,12 +467,12 @@ >> ITBlock.push_back(firstcond); >> } >> >> - return true; >> + return result; >> } >> >> // We want to read exactly 4 bytes of data. >> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) >> - return false; >> + return Fail; >> >> uint32_t insn32 = (bytes[3] << 8) | >> (bytes[2] << 0) | >> @@ -469,44 +480,44 @@ >> (bytes[0] << 16); >> MI.clear(); >> result = decodeThumbInstruction32(MI, insn32, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> bool InITBlock = ITBlock.size(); >> AddThumbPredicate(MI); >> AddThumb1SBit(MI, InITBlock); >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeThumb2Instruction32(MI, insn32, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeCommonInstruction32(MI, insn32, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeVFPInstruction32(MI, insn32, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> UpdateThumbVFPPredicate(MI); >> - return true; >> + return result; >> } >> >> MI.clear(); >> result = decodeNEONDupInstruction32(MI, insn32, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> >> if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { >> @@ -515,10 +526,10 @@ >> NEONLdStInsn &= 0xF0FFFFFF; >> NEONLdStInsn |= 0x04000000; >> result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> } >> >> @@ -529,14 +540,14 @@ >> NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 >> NEONDataInsn |= 0x12000000; // Set bits 28 and 25 >> result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); >> - if (result) { >> + if (result != Fail) { >> Size = 4; >> AddThumbPredicate(MI); >> - return true; >> + return result; >> } >> } >> >> - return false; >> + return Fail; >> } >> >> >> @@ -554,30 +565,30 @@ >> ARM::R12, ARM::SP, ARM::LR, ARM::PC >> }; >> >> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 15) >> - return false; >> + return Fail; >> >> unsigned Register = GPRDecoderTable[RegNo]; >> Inst.addOperand(MCOperand::CreateReg(Register)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> - if (RegNo == 15) return false; >> + if (RegNo == 15) return Fail; >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); >> } >> >> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 7) >> - return false; >> + return Fail; >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); >> } >> >> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> unsigned Register = 0; >> switch (RegNo) { >> @@ -600,16 +611,16 @@ >> Register = ARM::R12; >> break; >> default: >> - return false; >> + return Fail; >> } >> >> Inst.addOperand(MCOperand::CreateReg(Register)); >> - return true; >> + return Success; >> } >> >> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> - if (RegNo == 13 || RegNo == 15) return false; >> + if (RegNo == 13 || RegNo == 15) return Fail; >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); >> } >> >> @@ -624,14 +635,14 @@ >> ARM::S28, ARM::S29, ARM::S30, ARM::S31 >> }; >> >> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 31) >> - return false; >> + return Fail; >> >> unsigned Register = SPRDecoderTable[RegNo]; >> Inst.addOperand(MCOperand::CreateReg(Register)); >> - return true; >> + return Success; >> } >> >> static const unsigned DPRDecoderTable[] = { >> @@ -645,27 +656,27 @@ >> ARM::D28, ARM::D29, ARM::D30, ARM::D31 >> }; >> >> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 31) >> - return false; >> + return Fail; >> >> unsigned Register = DPRDecoderTable[RegNo]; >> Inst.addOperand(MCOperand::CreateReg(Register)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 7) >> - return false; >> + return Fail; >> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >> } >> >> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 15) >> - return false; >> + return Fail; >> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >> } >> >> @@ -677,65 +688,66 @@ >> }; >> >> >> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, >> uint64_t Address, const void *Decoder) { >> if (RegNo > 31) >> - return false; >> + return Fail; >> RegNo >>= 1; >> >> unsigned Register = QPRDecoderTable[RegNo]; >> Inst.addOperand(MCOperand::CreateReg(Register)); >> - return true; >> + return Success; >> } >> >> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> - if (Val == 0xF) return false; >> + if (Val == 0xF) return Fail; >> // AL predicate is not allowed on Thumb1 branches. >> if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) >> - return false; >> + return Fail; >> Inst.addOperand(MCOperand::CreateImm(Val)); >> if (Val == ARMCC::AL) { >> Inst.addOperand(MCOperand::CreateReg(0)); >> } else >> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> if (Val) >> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); >> else >> Inst.addOperand(MCOperand::CreateReg(0)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> uint32_t imm = Val & 0xFF; >> uint32_t rot = (Val & 0xF00) >> 7; >> uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); >> Inst.addOperand(MCOperand::CreateImm(rot_imm)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Val <<= 2; >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); >> unsigned type = fieldFromInstruction32(Val, 5, 2); >> unsigned imm = fieldFromInstruction32(Val, 7, 5); >> >> // Register-immediate >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> >> ARM_AM::ShiftOpc Shift = ARM_AM::lsl; >> switch (type) { >> @@ -759,19 +771,20 @@ >> unsigned Op = Shift | (imm << 3); >> Inst.addOperand(MCOperand::CreateImm(Op)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); >> unsigned type = fieldFromInstruction32(Val, 5, 2); >> unsigned Rs = fieldFromInstruction32(Val, 8, 4); >> >> // Register-register >> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; >> - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); >> >> ARM_AM::ShiftOpc Shift = ARM_AM::lsl; >> switch (type) { >> @@ -791,49 +804,55 @@ >> >> Inst.addOperand(MCOperand::CreateImm(Shift)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> // Empty register lists are not allowed. >> - if (CountPopulation_32(Val) == 0) return false; >> + if (CountPopulation_32(Val) == 0) return Fail; >> for (unsigned i = 0; i < 16; ++i) { >> if (Val & (1 << i)) { >> - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); >> } >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Vd = fieldFromInstruction32(Val, 8, 4); >> unsigned regs = Val & 0xFF; >> >> - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; >> + CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); >> for (unsigned i = 0; i < (regs - 1); ++i) { >> - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; >> + CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Vd = fieldFromInstruction32(Val, 8, 4); >> unsigned regs = (Val & 0xFF) / 2; >> >> - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); >> for (unsigned i = 0; i < (regs - 1); ++i) { >> - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> // This operand encodes a mask of contiguous zeros between a specified MSB >> // and LSB. To decode it, we create the mask of all bits MSB-and-lower, >> @@ -845,11 +864,13 @@ >> uint32_t msb_mask = (1 << (msb+1)) - 1; >> uint32_t lsb_mask = (1 << lsb) - 1; >> Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> unsigned CRd = fieldFromInstruction32(Insn, 12, 4); >> unsigned coproc = fieldFromInstruction32(Insn, 8, 4); >> @@ -875,7 +896,7 @@ >> case ARM::STCL_POST: >> case ARM::STCL_OPTION: >> if (coproc == 0xA || coproc == 0xB) >> - return false; >> + return Fail; >> break; >> default: >> break; >> @@ -883,7 +904,7 @@ >> >> Inst.addOperand(MCOperand::CreateImm(coproc)); >> Inst.addOperand(MCOperand::CreateImm(CRd)); >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> switch (Inst.getOpcode()) { >> case ARM::LDC_OPTION: >> case ARM::LDCL_OPTION: >> @@ -952,17 +973,19 @@ >> case ARM::STCL_PRE: >> case ARM::STCL_POST: >> case ARM::STCL_OPTION: >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> break; >> default: >> break; >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> @@ -982,13 +1005,13 @@ >> case ARM::STRT_POST_IMM: >> case ARM::STRBT_POST_REG: >> case ARM::STRBT_POST_IMM: >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> break; >> default: >> break; >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> >> // On loads, the writeback operand comes after Rt. >> switch (Inst.getOpcode()) { >> @@ -1002,14 +1025,13 @@ >> case ARM::LDRBT_POST_IMM: >> case ARM::LDRT_POST_REG: >> case ARM::LDRT_POST_IMM: >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> break; >> default: >> break; >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> >> ARM_AM::AddrOpc Op = ARM_AM::add; >> if (!fieldFromInstruction32(Insn, 23, 1)) >> @@ -1022,10 +1044,10 @@ >> else if (!P && writeback) >> idx_mode = ARMII::IndexModePost; >> >> - if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE >> + if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE >> >> if (reg) { >> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); >> ARM_AM::ShiftOpc Opc = ARM_AM::lsl; >> switch( fieldFromInstruction32(Insn, 5, 2)) { >> case 0: >> @@ -1041,7 +1063,7 @@ >> Opc = ARM_AM::ror; >> break; >> default: >> - return false; >> + return Fail; >> } >> unsigned amt = fieldFromInstruction32(Insn, 7, 5); >> unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); >> @@ -1053,13 +1075,15 @@ >> Inst.addOperand(MCOperand::CreateImm(tmp)); >> } >> >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); >> unsigned type = fieldFromInstruction32(Val, 5, 2); >> @@ -1082,8 +1106,8 @@ >> break; >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> unsigned shift; >> if (U) >> shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); >> @@ -1091,11 +1115,13 @@ >> shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); >> Inst.addOperand(MCOperand::CreateImm(shift)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> @@ -1116,7 +1142,7 @@ >> case ARM::LDRD: >> case ARM::LDRD_PRE: >> case ARM::LDRD_POST: >> - if (Rt & 0x1) return false; >> + if (Rt & 0x1) return Fail; >> break; >> default: >> break; >> @@ -1136,16 +1162,14 @@ >> case ARM::STRH: >> case ARM::STRH_PRE: >> case ARM::STRH_POST: >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> break; >> default: >> break; >> } >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> switch (Inst.getOpcode()) { >> case ARM::STRD: >> case ARM::STRD_PRE: >> @@ -1153,8 +1177,7 @@ >> case ARM::LDRD: >> case ARM::LDRD_PRE: >> case ARM::LDRD_POST: >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); >> break; >> default: >> break; >> @@ -1177,33 +1200,32 @@ >> case ARM::LDRSB_POST: >> case ARM::LDRHTr: >> case ARM::LDRSBTr: >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> break; >> default: >> break; >> } >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> >> if (type) { >> Inst.addOperand(MCOperand::CreateReg(0)); >> Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); >> } else { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(U)); >> } >> >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned mode = fieldFromInstruction32(Insn, 23, 2); >> >> @@ -1223,14 +1245,16 @@ >> } >> >> Inst.addOperand(MCOperand::CreateImm(mode)); >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, >> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, >> unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> unsigned reglist = fieldFromInstruction32(Insn, 0, 16); >> @@ -1265,16 +1289,15 @@ >> return DecodeRFEInstruction(Inst, Insn, Address, Decoder); >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied >> - !DecodePredicateOperand(Inst, pred, Address, Decoder) || >> - !DecodeRegListOperand(Inst, reglist, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> + CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> unsigned imod = fieldFromInstruction32(Insn, 18, 2); >> unsigned M = fieldFromInstruction32(Insn, 17, 1); >> @@ -1282,30 +1305,32 @@ >> unsigned mode = fieldFromInstruction32(Insn, 0, 5); >> >> // imod == '01' --> UNPREDICTABLE >> - if (imod == 1) return false; >> + if (imod == 1) return Fail; >> >> if (M && mode && imod && iflags) { >> Inst.setOpcode(ARM::CPS3p); >> Inst.addOperand(MCOperand::CreateImm(imod)); >> Inst.addOperand(MCOperand::CreateImm(iflags)); >> Inst.addOperand(MCOperand::CreateImm(mode)); >> - return true; >> + return Success; >> } else if (!mode && !M) { >> Inst.setOpcode(ARM::CPS2p); >> Inst.addOperand(MCOperand::CreateImm(imod)); >> Inst.addOperand(MCOperand::CreateImm(iflags)); >> - return true; >> + return Success; >> } else if (!imod && !iflags && M) { >> Inst.setOpcode(ARM::CPS1p); >> Inst.addOperand(MCOperand::CreateImm(mode)); >> - return true; >> + return Success; >> } >> >> - return false; >> + return Fail; >> } >> >> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rn = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 8, 4); >> @@ -1315,57 +1340,60 @@ >> if (pred == 0xF) >> return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >> >> - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || >> - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || >> - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); >> >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned add = fieldFromInstruction32(Val, 12, 1); >> unsigned imm = fieldFromInstruction32(Val, 0, 12); >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> >> if (!add) imm *= -1; >> if (imm == 0 && !add) imm = INT32_MIN; >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); >> unsigned U = fieldFromInstruction32(Val, 8, 1); >> unsigned imm = fieldFromInstruction32(Val, 0, 8); >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> >> if (U) >> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); >> else >> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); >> } >> >> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; >> >> @@ -1373,39 +1401,42 @@ >> Inst.setOpcode(ARM::BLXi); >> imm |= fieldFromInstruction32(Insn, 24, 1) << 1; >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); >> - return true; >> + return S; >> } >> >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(64 - Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); >> unsigned align = fieldFromInstruction32(Val, 4, 2); >> >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> if (!align) >> Inst.addOperand(MCOperand::CreateImm(0)); >> else >> Inst.addOperand(MCOperand::CreateImm(4 << align)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned wb = fieldFromInstruction32(Insn, 16, 4); >> @@ -1414,7 +1445,7 @@ >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> >> // First output register >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> >> // Second output register >> switch (Inst.getOpcode()) { >> @@ -1466,7 +1497,7 @@ >> case ARM::VLD4d8_UPD: >> case ARM::VLD4d16_UPD: >> case ARM::VLD4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); >> break; >> case ARM::VLD2b8: >> case ARM::VLD2b16: >> @@ -1486,7 +1517,7 @@ >> case ARM::VLD4q8_UPD: >> case ARM::VLD4q16_UPD: >> case ARM::VLD4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); >> default: >> break; >> } >> @@ -1527,7 +1558,7 @@ >> case ARM::VLD4d8_UPD: >> case ARM::VLD4d16_UPD: >> case ARM::VLD4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); >> break; >> case ARM::VLD3q8: >> case ARM::VLD3q16: >> @@ -1541,7 +1572,7 @@ >> case ARM::VLD4q8_UPD: >> case ARM::VLD4q16_UPD: >> case ARM::VLD4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); >> break; >> default: >> break; >> @@ -1569,7 +1600,7 @@ >> case ARM::VLD4d8_UPD: >> case ARM::VLD4d16_UPD: >> case ARM::VLD4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); >> break; >> case ARM::VLD4q8: >> case ARM::VLD4q16: >> @@ -1577,7 +1608,7 @@ >> case ARM::VLD4q8_UPD: >> case ARM::VLD4q16_UPD: >> case ARM::VLD4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); >> break; >> default: >> break; >> @@ -1622,28 +1653,29 @@ >> case ARM::VLD4q8_UPD: >> case ARM::VLD4q16_UPD: >> case ARM::VLD4q32_UPD: >> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); >> break; >> default: >> break; >> } >> >> // AddrMode6 Base (register+alignment) >> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); >> >> // AddrMode6 Offset (register) >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned wb = fieldFromInstruction32(Insn, 16, 4); >> @@ -1690,25 +1722,24 @@ >> case ARM::VST4q8_UPD: >> case ARM::VST4q16_UPD: >> case ARM::VST4q32_UPD: >> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); >> break; >> default: >> break; >> } >> >> // AddrMode6 Base (register+alignment) >> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); >> >> // AddrMode6 Offset (register) >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> // First input register >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> >> // Second input register >> switch (Inst.getOpcode()) { >> @@ -1760,7 +1791,7 @@ >> case ARM::VST4d8_UPD: >> case ARM::VST4d16_UPD: >> case ARM::VST4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); >> break; >> case ARM::VST2b8: >> case ARM::VST2b16: >> @@ -1780,7 +1811,7 @@ >> case ARM::VST4q8_UPD: >> case ARM::VST4q16_UPD: >> case ARM::VST4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); >> break; >> default: >> break; >> @@ -1822,7 +1853,7 @@ >> case ARM::VST4d8_UPD: >> case ARM::VST4d16_UPD: >> case ARM::VST4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); >> break; >> case ARM::VST3q8: >> case ARM::VST3q16: >> @@ -1836,7 +1867,7 @@ >> case ARM::VST4q8_UPD: >> case ARM::VST4q16_UPD: >> case ARM::VST4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); >> break; >> default: >> break; >> @@ -1864,7 +1895,7 @@ >> case ARM::VST4d8_UPD: >> case ARM::VST4d16_UPD: >> case ARM::VST4d32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); >> break; >> case ARM::VST4q8: >> case ARM::VST4q16: >> @@ -1872,17 +1903,19 @@ >> case ARM::VST4q8_UPD: >> case ARM::VST4q16_UPD: >> case ARM::VST4q32_UPD: >> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); >> break; >> default: >> break; >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> @@ -1893,28 +1926,30 @@ >> >> align *= (1 << size); >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> if (regs == 2) { >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); >> } >> if (Rm == 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> @@ -1924,54 +1959,57 @@ >> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; >> align *= 2*size; >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); >> if (Rm == 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || >> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || >> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); >> if (Rm == 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(0)); >> >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> @@ -1993,29 +2031,30 @@ >> } >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || >> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || >> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || >> - !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); >> if (Rm == 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> >> if (Rm == 0xD) >> Inst.addOperand(MCOperand::CreateReg(0)); >> else if (Rm != 0xF) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned imm = fieldFromInstruction32(Insn, 0, 4); >> @@ -2026,9 +2065,9 @@ >> unsigned Q = fieldFromInstruction32(Insn, 6, 1); >> >> if (Q) { >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); >> } else { >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> } >> >> Inst.addOperand(MCOperand::CreateImm(imm)); >> @@ -2038,62 +2077,66 @@ >> case ARM::VORRiv2i32: >> case ARM::VBICiv4i16: >> case ARM::VBICiv2i32: >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> break; >> case ARM::VORRiv8i16: >> case ARM::VORRiv4i32: >> case ARM::VBICiv8i16: >> case ARM::VBICiv4i32: >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); >> break; >> default: >> break; >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; >> unsigned size = fieldFromInstruction32(Insn, 18, 2); >> >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(8 << size)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(8 - Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(16 - Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(32 - Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(64 - Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> @@ -2103,21 +2146,21 @@ >> unsigned op = fieldFromInstruction32(Insn, 6, 1); >> unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> if (op) { >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback >> } >> >> for (unsigned i = 0; i < length; ++i) { >> - if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> // The immediate needs to be a fully instantiated float. However, the >> // auto-generated decoder is only able to fill in some of the bits >> @@ -2139,102 +2182,110 @@ >> fp_conv.integer |= (~b & 0x1) << 30; >> >> Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned dst = fieldFromInstruction16(Insn, 8, 3); >> unsigned imm = fieldFromInstruction16(Insn, 0, 8); >> >> - if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; >> + CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); >> >> if (Inst.getOpcode() == ARM::tADR) >> Inst.addOperand(MCOperand::CreateReg(ARM::PC)); >> else if (Inst.getOpcode() == ARM::tADDrSPi) >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> else >> - return false; >> + return Fail; >> >> Inst.addOperand(MCOperand::CreateImm(imm)); >> - return true; >> + return S; >> } >> >> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 0, 3); >> unsigned Rm = fieldFromInstruction32(Val, 3, 3); >> >> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 0, 3); >> unsigned imm = fieldFromInstruction32(Val, 3, 5); >> >> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(Val << 2)); >> >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> Inst.addOperand(MCOperand::CreateImm(Val << 2)); >> >> - return true; >> + return Success; >> } >> >> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 6, 4); >> unsigned Rm = fieldFromInstruction32(Val, 2, 4); >> unsigned imm = fieldFromInstruction32(Val, 0, 2); >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> if (Inst.getOpcode() != ARM::t2PLDs) { >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> } >> >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> @@ -2257,57 +2308,60 @@ >> Inst.addOperand(MCOperand::CreateReg(ARM::PC)); >> break; >> default: >> - return false; >> + return Fail; >> } >> >> int imm = fieldFromInstruction32(Insn, 0, 12); >> if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return S; >> } >> >> unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); >> addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; >> addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; >> - DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); >> + CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> int imm = Val & 0xFF; >> if (!(Val & 0x100)) imm *= -1; >> Inst.addOperand(MCOperand::CreateImm(imm << 2)); >> >> - return true; >> + return Success; >> } >> >> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); >> unsigned imm = fieldFromInstruction32(Val, 0, 9); >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> int imm = Val & 0xFF; >> if (!(Val & 0x100)) imm *= -1; >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return Success; >> } >> >> >> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); >> unsigned imm = fieldFromInstruction32(Val, 0, 9); >> >> @@ -2324,27 +2378,28 @@ >> break; >> } >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || >> - !DecodeT2Imm8(Inst, imm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); >> unsigned imm = fieldFromInstruction32(Val, 0, 12); >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder) { >> unsigned imm = fieldFromInstruction16(Insn, 0, 7); >> >> @@ -2352,30 +2407,32 @@ >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> Inst.addOperand(MCOperand::CreateImm(imm)); >> >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> if (Inst.getOpcode() == ARM::tADDrSP) { >> unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); >> Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; >> >> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); >> } else if (Inst.getOpcode() == ARM::tADDspr) { >> unsigned Rm = fieldFromInstruction16(Insn, 3, 4); >> >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - return true; >> + return S; >> } >> >> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, >> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, >> uint64_t Address, const void *Decoder) { >> unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; >> unsigned flags = fieldFromInstruction16(Insn, 0, 3); >> @@ -2383,52 +2440,55 @@ >> Inst.addOperand(MCOperand::CreateImm(imod)); >> Inst.addOperand(MCOperand::CreateImm(flags)); >> >> - return true; >> + return Success; >> } >> >> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned add = fieldFromInstruction32(Insn, 4, 1); >> >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; >> Inst.addOperand(MCOperand::CreateImm(add)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> if (Val == 0xA || Val == 0xB) >> - return false; >> + return Fail; >> >> Inst.addOperand(MCOperand::CreateImm(Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> if (Val == 0) >> Inst.addOperand(MCOperand::CreateImm(32)); >> else >> Inst.addOperand(MCOperand::CreateImm(Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned pred = fieldFromInstruction32(Insn, 22, 4); >> if (pred == 0xE || pred == 0xF) { >> unsigned opc = fieldFromInstruction32(Insn, 4, 2); >> switch (opc) { >> default: >> - return false; >> + return Fail; >> case 0: >> Inst.setOpcode(ARM::t2DSB); >> break; >> @@ -2437,7 +2497,7 @@ >> break; >> case 2: >> Inst.setOpcode(ARM::t2ISB); >> - return true; >> + return Success; >> } >> >> unsigned imm = fieldFromInstruction32(Insn, 0, 4); >> @@ -2450,17 +2510,16 @@ >> brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; >> brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; >> >> - if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || >> - !DecodePredicateOperand(Inst, pred, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> // Decode a shifted immediate operand. These basically consist >> // of an 8-bit value, and a 4-bit directive that specifies either >> // a splat operation or a rotation. >> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> unsigned ctrl = fieldFromInstruction32(Val, 10, 2); >> if (ctrl == 0) { >> @@ -2488,26 +2547,26 @@ >> Inst.addOperand(MCOperand::CreateImm(imm)); >> } >> >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder){ >> Inst.addOperand(MCOperand::CreateImm(Val << 1)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder){ >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); >> - return true; >> + return Success; >> } >> >> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> switch (Val) { >> default: >> - return false; >> + return Fail; >> case 0xF: // SY >> case 0xE: // ST >> case 0xB: // ISH >> @@ -2520,55 +2579,61 @@ >> } >> >> Inst.addOperand(MCOperand::CreateImm(Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, >> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, >> uint64_t Address, const void *Decoder) { >> - if (!Val) return false; >> + if (!Val) return Fail; >> Inst.addOperand(MCOperand::CreateImm(Val)); >> - return true; >> + return Success; >> } >> >> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> >> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; >> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; >> >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> unsigned Rt = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> >> - if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); >> >> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; >> - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; >> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; >> + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; >> >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> unsigned imm = fieldFromInstruction32(Insn, 0, 12); >> @@ -2576,18 +2641,20 @@ >> imm |= fieldFromInstruction32(Insn, 23, 1) << 12; >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> >> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE >> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> - if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> + CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); >> unsigned imm = fieldFromInstruction32(Insn, 0, 12); >> @@ -2595,18 +2662,20 @@ >> imm |= fieldFromInstruction32(Insn, 23, 1) << 12; >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); >> >> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE >> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE >> >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; >> - if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); >> + CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2617,47 +2686,47 @@ >> unsigned index = 0; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 5, 3); >> break; >> case 1: >> if (fieldFromInstruction32(Insn, 5, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 6, 2); >> if (fieldFromInstruction32(Insn, 4, 1)) >> align = 2; >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 6, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 4, 2) != 0) >> align = 4; >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2668,47 +2737,47 @@ >> unsigned index = 0; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 5, 3); >> break; >> case 1: >> if (fieldFromInstruction32(Insn, 5, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 6, 2); >> if (fieldFromInstruction32(Insn, 4, 1)) >> align = 2; >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 6, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 4, 2) != 0) >> align = 4; >> } >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2720,7 +2789,7 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> index = fieldFromInstruction32(Insn, 5, 3); >> if (fieldFromInstruction32(Insn, 4, 1)) >> @@ -2735,7 +2804,7 @@ >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 5, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 4, 1) != 0) >> align = 8; >> @@ -2744,28 +2813,28 @@ >> break; >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2777,7 +2846,7 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> index = fieldFromInstruction32(Insn, 5, 3); >> if (fieldFromInstruction32(Insn, 4, 1)) >> @@ -2792,7 +2861,7 @@ >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 5, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 4, 1) != 0) >> align = 8; >> @@ -2802,26 +2871,26 @@ >> } >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2833,53 +2902,53 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 5, 3); >> break; >> case 1: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 6, 2); >> if (fieldFromInstruction32(Insn, 5, 1)) >> inc = 2; >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 4, 2)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 6, 1)) >> inc = 2; >> break; >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2891,22 +2960,22 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 5, 3); >> break; >> case 1: >> if (fieldFromInstruction32(Insn, 4, 1)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 6, 2); >> if (fieldFromInstruction32(Insn, 5, 1)) >> inc = 2; >> break; >> case 2: >> if (fieldFromInstruction32(Insn, 4, 2)) >> - return false; // UNDEFINED >> + return Fail; // UNDEFINED >> index = fieldFromInstruction32(Insn, 7, 1); >> if (fieldFromInstruction32(Insn, 6, 1)) >> inc = 2; >> @@ -2914,27 +2983,27 @@ >> } >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> >> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -2946,7 +3015,7 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> align = 4; >> @@ -2968,33 +3037,33 @@ >> break; >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, >> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, >> uint64_t Address, const void *Decoder) { >> + DecodeStatus S = Success; >> + >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); >> @@ -3006,7 +3075,7 @@ >> unsigned inc = 1; >> switch (size) { >> default: >> - return false; >> + return Fail; >> case 0: >> if (fieldFromInstruction32(Insn, 4, 1)) >> align = 4; >> @@ -3029,22 +3098,20 @@ >> } >> >> if (Rm != 0xF) { // Writeback >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> } >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(align)); >> if (Rm != 0xF && Rm != 0xD) { >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) >> - return false; >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); >> } >> >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); >> Inst.addOperand(MCOperand::CreateImm(index)); >> >> - return true; >> + return S; >> } >> >> >> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h (original) >> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h Wed Aug 17 12:44:15 2011 >> @@ -40,11 +40,11 @@ >> } >> >> /// getInstruction - See MCDisassembler. >> - bool getInstruction(MCInst &instr, >> - uint64_t &size, >> - const MemoryObject ®ion, >> - uint64_t address, >> - raw_ostream &vStream) const; >> + DecodeStatus getInstruction(MCInst &instr, >> + uint64_t &size, >> + const MemoryObject ®ion, >> + uint64_t address, >> + raw_ostream &vStream) const; >> >> /// getEDInfo - See MCDisassembler. >> EDInstInfo *getEDInfo() const; >> @@ -64,11 +64,11 @@ >> } >> >> /// getInstruction - See MCDisassembler. >> - bool getInstruction(MCInst &instr, >> - uint64_t &size, >> - const MemoryObject ®ion, >> - uint64_t address, >> - raw_ostream &vStream) const; >> + DecodeStatus getInstruction(MCInst &instr, >> + uint64_t &size, >> + const MemoryObject ®ion, >> + uint64_t address, >> + raw_ostream &vStream) const; >> >> /// getEDInfo - See MCDisassembler. >> EDInstInfo *getEDInfo() const; >> >> Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) >> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Aug 17 12:44:15 2011 >> @@ -493,7 +493,7 @@ >> // Public interface for the disassembler >> // >> >> -bool MBlazeDisassembler::getInstruction(MCInst &instr, >> +MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr, >> uint64_t &size, >> const MemoryObject ®ion, >> uint64_t address, >> @@ -508,7 +508,7 @@ >> >> // We want to read exactly 4 bytes of data. >> if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read < 4) >> - return false; >> + return Fail; >> >> // Encoded as a big-endian 32-bit word in the stream. >> insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0); >> @@ -517,7 +517,7 @@ >> // that it is a valid instruction. >> unsigned opcode = getOPCODE(insn); >> if (opcode == UNSUPPORTED) >> - return false; >> + return Fail; >> >> instr.setOpcode(opcode); >> >> @@ -529,11 +529,11 @@ >> uint64_t tsFlags = MBlazeInsts[opcode].TSFlags; >> switch ((tsFlags & MBlazeII::FormMask)) { >> default: >> - return false; >> + return Fail; >> >> case MBlazeII::FRRRR: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RB)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> @@ -541,7 +541,7 @@ >> >> case MBlazeII::FRRR: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> instr.addOperand(MCOperand::CreateReg(RB)); >> @@ -550,23 +550,23 @@ >> case MBlazeII::FRI: >> switch (opcode) { >> default: >> - return false; >> + return Fail; >> case MBlaze::MFS: >> if (RD == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); >> break; >> case MBlaze::MTS: >> if (RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> break; >> case MBlaze::MSRSET: >> case MBlaze::MSRCLR: >> if (RD == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateImm(insn&0x7FFF)); >> break; >> @@ -575,7 +575,7 @@ >> >> case MBlazeII::FRRI: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> switch (opcode) { >> @@ -592,35 +592,35 @@ >> >> case MBlazeII::FCRR: >> if (RA == UNSUPPORTED || RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RA)); >> instr.addOperand(MCOperand::CreateReg(RB)); >> break; >> >> case MBlazeII::FCRI: >> if (RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RA)); >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); >> break; >> >> case MBlazeII::FRCR: >> if (RD == UNSUPPORTED || RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RB)); >> break; >> >> case MBlazeII::FRCI: >> if (RD == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); >> break; >> >> case MBlazeII::FCCR: >> if (RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RB)); >> break; >> >> @@ -630,7 +630,7 @@ >> >> case MBlazeII::FRRCI: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> instr.addOperand(MCOperand::CreateImm(getSHT(insn))); >> @@ -638,35 +638,35 @@ >> >> case MBlazeII::FRRC: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> break; >> >> case MBlazeII::FRCX: >> if (RD == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateImm(getFSL(insn))); >> break; >> >> case MBlazeII::FRCS: >> if (RD == UNSUPPORTED || RS == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateReg(RS)); >> break; >> >> case MBlazeII::FCRCS: >> if (RS == UNSUPPORTED || RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RS)); >> instr.addOperand(MCOperand::CreateReg(RA)); >> break; >> >> case MBlazeII::FCRCX: >> if (RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RA)); >> instr.addOperand(MCOperand::CreateImm(getFSL(insn))); >> break; >> @@ -677,13 +677,13 @@ >> >> case MBlazeII::FCR: >> if (RB == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RB)); >> break; >> >> case MBlazeII::FRIR: >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) >> - return false; >> + return Fail; >> instr.addOperand(MCOperand::CreateReg(RD)); >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); >> instr.addOperand(MCOperand::CreateReg(RA)); >> @@ -693,7 +693,7 @@ >> // We always consume 4 bytes of data on success >> size = 4; >> >> - return true; >> + return Success; >> } >> >> static MCDisassembler *createMBlazeDisassembler(const Target &T) { >> >> Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original) >> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Aug 17 12:44:15 2011 >> @@ -40,7 +40,7 @@ >> } >> >> /// getInstruction - See MCDisassembler. >> - bool getInstruction(MCInst &instr, >> + MCDisassembler::DecodeStatus getInstruction(MCInst &instr, >> uint64_t &size, >> const MemoryObject ®ion, >> uint64_t address, >> >> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) >> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug 17 12:44:15 2011 >> @@ -106,11 +106,12 @@ >> // Public interface for the disassembler >> // >> >> -bool X86GenericDisassembler::getInstruction(MCInst &instr, >> - uint64_t &size, >> - const MemoryObject ®ion, >> - uint64_t address, >> - raw_ostream &vStream) const { >> +MCDisassembler::DecodeStatus >> +X86GenericDisassembler::getInstruction(MCInst &instr, >> + uint64_t &size, >> + const MemoryObject ®ion, >> + uint64_t address, >> + raw_ostream &vStream) const { >> InternalInstruction internalInstr; >> >> int ret = decodeInstruction(&internalInstr, >> @@ -123,11 +124,11 @@ >> >> if (ret) { >> size = internalInstr.readerCursor - address; >> - return false; >> + return Fail; >> } >> else { >> size = internalInstr.length; >> - return !translateInstruction(instr, internalInstr); >> + return (!translateInstruction(instr, internalInstr)) ? Success : Fail; >> } >> } >> >> >> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original) >> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Aug 17 12:44:15 2011 >> @@ -112,11 +112,11 @@ >> ~X86GenericDisassembler(); >> >> /// getInstruction - See MCDisassembler. >> - bool getInstruction(MCInst &instr, >> - uint64_t &size, >> - const MemoryObject ®ion, >> - uint64_t address, >> - raw_ostream &vStream) const; >> + DecodeStatus getInstruction(MCInst &instr, >> + uint64_t &size, >> + const MemoryObject ®ion, >> + uint64_t address, >> + raw_ostream &vStream) const; >> >> /// getEDInfo - See MCDisassembler. >> EDInstInfo *getEDInfo() const; >> >> Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original) >> +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Wed Aug 17 12:44:15 2011 >> @@ -1,4 +1,4 @@ >> -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} >> +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} >> >> # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) >> # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 >> >> Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original) >> +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 17 12:44:15 2011 >> @@ -65,15 +65,26 @@ >> for (Index = 0; Index < Bytes.size(); Index += Size) { >> MCInst Inst; >> >> - if (DisAsm.getInstruction(Inst, Size, memoryObject, Index, >> - /*REMOVE*/ nulls())) { >> - Printer.printInst(&Inst, Out); >> - Out << "\n"; >> - } else { >> + MCDisassembler::DecodeStatus S; >> + S = DisAsm.getInstruction(Inst, Size, memoryObject, Index, >> + /*REMOVE*/ nulls()); >> + switch (S) { > > > Changing this to a switch statement is good. The C bindings in MCDisasembler.cpp and EDDisassembler.cpp need to be changed, too, though. They're still doing "!Disasm->getInstruction()" type constructs. > > >> + case MCDisassembler::Fail: >> SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), >> "invalid instruction encoding", "warning"); >> if (Size == 0) >> Size = 1; // skip illegible bytes >> + break; >> + >> + case MCDisassembler::SoftFail: >> + SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), >> + "potentially undefined instruction encoding", "warning"); >> + // Fall through >> + >> + case MCDisassembler::Success: >> + Printer.printInst(&Inst, Out); >> + Out << "\n"; >> + break; >> } >> } >> >> >> Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Aug 17 12:44:15 2011 >> @@ -128,5 +128,15 @@ >> return; >> } >> >> + // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. >> + if (Target.getName() == "ARM" || >> + Target.getName() == "Thumb") { >> + FixedLenDecoderEmitter(Records, >> + "CHECK(S, ", ");", >> + "S", "Fail", >> + "DecodeStatus S = Success;\n(void)S;").run(OS); >> + return; >> + } >> + >> FixedLenDecoderEmitter(Records).run(OS); >> } >> >> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Aug 17 12:44:15 2011 >> @@ -238,19 +238,24 @@ >> // Width of instructions >> unsigned BitWidth; >> >> + // Parent emitter >> + const FixedLenDecoderEmitter *Emitter; >> + >> public: >> FilterChooser(const FilterChooser &FC) : >> AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes), >> Operands(FC.Operands), Filters(FC.Filters), >> FilterBitValues(FC.FilterBitValues), Parent(FC.Parent), >> - BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { } >> + BestIndex(FC.BestIndex), BitWidth(FC.BitWidth), >> + Emitter(FC.Emitter) { } >> >> FilterChooser(const std::vector &Insts, >> const std::vector &IDs, >> std::map > &Ops, >> - unsigned BW) : >> + unsigned BW, >> + const FixedLenDecoderEmitter *E) : >> AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), >> - Parent(NULL), BestIndex(-1), BitWidth(BW) { >> + Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) { >> for (unsigned i = 0; i < BitWidth; ++i) >> FilterBitValues.push_back(BIT_UNFILTERED); >> >> @@ -264,7 +269,8 @@ >> FilterChooser &parent) : >> AllInstructions(Insts), Opcodes(IDs), Operands(Ops), >> Filters(), FilterBitValues(ParentFilterBitValues), >> - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) { >> + Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth), >> + Emitter(parent.Emitter) { >> doFilter(); >> } >> >> @@ -563,17 +569,17 @@ >> void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation, >> std::string Namespace) { >> o.indent(Indentation) << >> - "static bool decode" << Namespace << "Instruction" << BitWidth >> + "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction" << BitWidth >> << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, " >> << "const void *Decoder) {\n"; >> - o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n"; >> + o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n" << Emitter->Locals << "\n"; >> >> ++Indentation; ++Indentation; >> // Emits code to decode the instructions. >> emit(o, Indentation); >> >> o << '\n'; >> - o.indent(Indentation) << "return false;\n"; >> + o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n"; >> --Indentation; --Indentation; >> >> o.indent(Indentation) << "}\n"; >> @@ -744,8 +750,8 @@ >> } >> >> if (Decoder != "") >> - o.indent(Indentation) << " if (!" << Decoder >> - << "(MI, tmp, Address, Decoder)) return false;\n"; >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << Decoder >> + << "(MI, tmp, Address, Decoder)" << Emitter->GuardPostfix << "\n"; >> else >> o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n"; >> >> @@ -776,15 +782,15 @@ >> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { >> // If a custom instruction decoder was specified, use that. >> if (I->numFields() == 0 && I->Decoder.size()) { >> - o.indent(Indentation) << " if (!" << I->Decoder >> - << "(MI, insn, Address, Decoder)) return false;\n"; >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder >> + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n"; >> break; >> } >> >> emitBinaryParser(o, Indentation, *I); >> } >> >> - o.indent(Indentation) << " return true; // " << nameWithID(Opc) >> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc) >> << '\n'; >> o.indent(Indentation) << "}\n"; >> return true; >> @@ -821,14 +827,14 @@ >> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { >> // If a custom instruction decoder was specified, use that. >> if (I->numFields() == 0 && I->Decoder.size()) { >> - o.indent(Indentation) << " if (!" << I->Decoder >> - << "(MI, insn, Address, Decoder)) return false;\n"; >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder >> + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n"; >> break; >> } >> >> emitBinaryParser(o, Indentation, *I); >> } >> - o.indent(Indentation) << " return true; // " << nameWithID(Opc) >> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc) >> << '\n'; >> o.indent(Indentation) << "}\n"; >> >> @@ -1426,7 +1432,7 @@ >> >> // Emit the decoder for this namespace+width combination. >> FilterChooser FC(NumberedInstructions, I->second, Operands, >> - 8*I->first.second); >> + 8*I->first.second, this); >> FC.emitTop(o, 0, I->first.first); >> } >> >> >> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=137830&r1=137829&r2=137830&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original) >> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Aug 17 12:44:15 2011 >> @@ -49,9 +49,16 @@ >> >> class FixedLenDecoderEmitter : public TableGenBackend { >> public: >> - FixedLenDecoderEmitter(RecordKeeper &R) : >> + FixedLenDecoderEmitter(RecordKeeper &R, >> + std::string GPrefix = "if (", >> + std::string GPostfix = " == MCDisassembler::Fail) return MCDisassembler::Fail;", >> + std::string ROK = "MCDisassembler::Success", >> + std::string RFail = "MCDisassembler::Fail", >> + std::string L = "") : >> Records(R), Target(R), >> - NumberedInstructions(Target.getInstructionsByEnumValue()) {} >> + NumberedInstructions(Target.getInstructionsByEnumValue()), >> + GuardPrefix(GPrefix), GuardPostfix(GPostfix), >> + ReturnOK(ROK), ReturnFail(RFail), Locals(L) {} >> >> // run - Output the code emitter >> void run(raw_ostream &o); >> @@ -62,7 +69,10 @@ >> std::vector NumberedInstructions; >> std::vector Opcodes; >> std::map > Operands; >> - >> +public: >> + std::string GuardPrefix, GuardPostfix; >> + std::string ReturnOK, ReturnFail; >> + std::string Locals; >> }; >> >> } // end llvm namespace >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rafael.espindola at gmail.com Tue Aug 30 14:29:02 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 19:29:02 -0000 Subject: [llvm-commits] [llvm] r138811 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp Message-ID: <20110830192902.48C8C2A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 14:29:02 2011 New Revision: 138811 URL: http://llvm.org/viewvc/llvm-project?rev=138811&view=rev Log: Command line option to enable support for segmented stacks: -segmented-stacks. Patch by Sanjoy Das! Modified: llvm/trunk/include/llvm/Target/TargetOptions.h llvm/trunk/lib/Target/TargetMachine.cpp Modified: llvm/trunk/include/llvm/Target/TargetOptions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=138811&r1=138810&r2=138811&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOptions.h (original) +++ llvm/trunk/include/llvm/Target/TargetOptions.h Tue Aug 30 14:29:02 2011 @@ -158,6 +158,8 @@ /// instead of an ISD::TRAP node. extern StringRef getTrapFunctionName(); + extern bool EnableSegmentedStacks; + } // End llvm namespace #endif Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=138811&r1=138810&r2=138811&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Tue Aug 30 14:29:02 2011 @@ -47,6 +47,7 @@ bool StrongPHIElim; bool HasDivModLibcall; bool AsmVerbosityDefault(false); + bool EnableSegmentedStacks; } static cl::opt @@ -178,6 +179,12 @@ FunctionSections("ffunction-sections", cl::desc("Emit functions into separate sections"), cl::init(false)); +static cl::opt +SegmentedStacks("segmented-stacks", + cl::desc("Use segmented stacks if possible."), + cl::location(EnableSegmentedStacks), + cl::init(false)); + //--------------------------------------------------------------------------- // TargetMachine Class // From rafael.espindola at gmail.com Tue Aug 30 14:39:58 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 19:39:58 -0000 Subject: [llvm-commits] [llvm] r138812 - in /llvm/trunk: include/llvm/Target/TargetFrameLowering.h lib/CodeGen/PrologEpilogInserter.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86MachineFunctionInfo.h Message-ID: <20110830193959.23C292A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 14:39:58 2011 New Revision: 138812 URL: http://llvm.org/viewvc/llvm-project?rev=138812&view=rev Log: Emit segmented-stack specific code into function prologues for X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.h Modified: llvm/trunk/include/llvm/Target/TargetFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameLowering.h?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetFrameLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Tue Aug 30 14:39:58 2011 @@ -114,6 +114,10 @@ virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const = 0; + /// Adjust the prologue to have the function use segmented stacks. This works + /// by adding a check even before the "normal" function prologue. + virtual void adjustForSegmentedStacks(MachineFunction &MF) const { } + /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee /// saved registers and returns true if it isn't possible / profitable to do /// so by issuing a series of store instructions via Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Tue Aug 30 14:39:58 2011 @@ -29,6 +29,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" @@ -699,6 +700,13 @@ if (!I->empty() && I->back().getDesc().isReturn()) TFI.emitEpilogue(Fn, *I); } + + // Emit additional code that is required support segmented stacks, if we've + // been asked for it. This, when linked with a runtime with support for + // segmented stacks (libgcc is one), will result allocating stack space in + // small chunks instead of one large contiguous block. + if (EnableSegmentedStacks) + TFI.adjustForSegmentedStacks(Fn); } /// replaceFrameIndices - Replace all MO_FrameIndex operands with physical Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Aug 30 14:39:58 2011 @@ -15,6 +15,7 @@ #include "X86InstrBuilder.h" #include "X86InstrInfo.h" #include "X86MachineFunctionInfo.h" +#include "X86Subtarget.h" #include "X86TargetMachine.h" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -645,7 +646,8 @@ !RegInfo->needsStackRealignment(MF) && !MFI->hasVarSizedObjects() && // No dynamic alloca. !MFI->adjustsStack() && // No calls. - !IsWin64) { // Win64 has no Red Zone + !IsWin64 && // Win64 has no Red Zone + !EnableSegmentedStacks) { // Regular stack uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); if (HasFP) MinSize += SlotSize; StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); @@ -1275,3 +1277,160 @@ FrameIdx = 0; } } + +static bool +HasNestArgument(const MachineFunction *MF) { + const Function *F = MF->getFunction(); + for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); + I != E; I++) { + if (I->hasNestAttr()) + return true; + } + return false; +} + +static unsigned +GetScratchRegister(bool Is64Bit, const MachineFunction &MF) { + if (Is64Bit) { + return X86::R11; + } else { + CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv(); + bool IsNested = HasNestArgument(&MF); + + if (CallingConvention == CallingConv::X86_FastCall) { + if (IsNested) { + report_fatal_error("Segmented stacks does not supprot fastcall with " + "nested fucntion."); + return -1; + } else { + return X86::EAX; + } + } else { + if (IsNested) + return X86::EDX; + else + return X86::ECX; + } + } +} + +void +X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { + MachineBasicBlock &prologueMBB = MF.front(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + const X86InstrInfo &TII = *TM.getInstrInfo(); + uint64_t StackSize; + bool Is64Bit = STI.is64Bit(); + unsigned TlsReg, TlsOffset; + DebugLoc DL; + const X86Subtarget *ST = &MF.getTarget().getSubtarget(); + + unsigned ScratchReg = GetScratchRegister(Is64Bit, MF); + assert(!MF.getRegInfo().isLiveIn(ScratchReg) && + "Scratch register is live-in"); + + if (MF.getFunction()->isVarArg()) + report_fatal_error("Segmented stacks do not support vararg functions."); + if (!ST->isTargetLinux()) + report_fatal_error("Segmented stacks supported only on linux."); + + MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock(); + MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock(); + X86MachineFunctionInfo *X86FI = MF.getInfo(); + bool IsNested = false; + + // We need to know if the function has a nest argument only in 64 bit mode. + if (Is64Bit) + IsNested = HasNestArgument(&MF); + + for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(), + e = prologueMBB.livein_end(); i != e; i++) { + allocMBB->addLiveIn(*i); + checkMBB->addLiveIn(*i); + } + + if (IsNested) + allocMBB->addLiveIn(X86::R10); + + MF.push_front(allocMBB); + MF.push_front(checkMBB); + + // Eventually StackSize will be calculated by a link-time pass; which will + // also decide whether checking code needs to be injected into this particular + // prologue. + StackSize = MFI->getStackSize(); + + // Read the limit off the current stacklet off the stack_guard location. + if (Is64Bit) { + TlsReg = X86::FS; + TlsOffset = 0x70; + + BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) + .addImm(0).addReg(0).addImm(-StackSize).addReg(0); + BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg) + .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); + } else { + TlsReg = X86::GS; + TlsOffset = 0x30; + + BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP) + .addImm(0).addReg(0).addImm(-StackSize).addReg(0); + BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg) + .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); + } + + // This jump is taken if SP >= (Stacklet Limit + Stack Space required). + // It jumps to normal execution of the function body. + BuildMI(checkMBB, DL, TII.get(X86::JG_4)).addMBB(&prologueMBB); + + // On 32 bit we first push the arguments size and then the frame size. On 64 + // bit, we pass the stack frame size in r10 and the argument size in r11. + if (Is64Bit) { + // Functions with nested arguments use R10, so it needs to be saved across + // the call to _morestack + + if (IsNested) + BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); + + BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) + .addImm(StackSize); + BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) + .addImm(X86FI->getArgumentStackSize()); + MF.getRegInfo().setPhysRegUsed(X86::R10); + MF.getRegInfo().setPhysRegUsed(X86::R11); + } else { + // Since we'll call __morestack, stack alignment needs to be preserved. + BuildMI(allocMBB, DL, TII.get(X86::SUB32ri), X86::ESP).addReg(X86::ESP) + .addImm(8); + BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) + .addImm(X86FI->getArgumentStackSize()); + BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) + .addImm(StackSize); + } + + // __morestack is in libgcc + if (Is64Bit) + BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32)) + .addExternalSymbol("__morestack"); + else + BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32)) + .addExternalSymbol("__morestack"); + + // __morestack only seems to remove 8 bytes off the stack. Add back the + // additional 8 bytes we added before pushing the arguments. + if (!Is64Bit) + BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP) + .addImm(8); + BuildMI(allocMBB, DL, TII.get(X86::RET)); + + if (Is64Bit && IsNested) + BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::R10).addReg(X86::RAX); + + allocMBB->addSuccessor(&prologueMBB); + checkMBB->addSuccessor(allocMBB); + checkMBB->addSuccessor(&prologueMBB); + +#ifndef NDEBUG + MF.verify(); +#endif +} Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Tue Aug 30 14:39:58 2011 @@ -41,6 +41,8 @@ void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + void adjustForSegmentedStacks(MachineFunction &MF) const; + void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS = NULL) const; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 14:39:58 2011 @@ -1931,6 +1931,8 @@ FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); } + FuncInfo->setArgumentStackSize(StackSize); + return Chain; } Modified: llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.h?rev=138812&r1=138811&r2=138812&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86MachineFunctionInfo.h Tue Aug 30 14:39:58 2011 @@ -65,6 +65,9 @@ unsigned VarArgsGPOffset; /// VarArgsFPOffset - X86-64 vararg func fp reg offset. unsigned VarArgsFPOffset; + /// ArgumentStackSize - The number of bytes on stack consumed by the arguments + /// being passed on the stack. + unsigned ArgumentStackSize; public: X86MachineFunctionInfo() : ForceFramePointer(false), @@ -77,7 +80,8 @@ VarArgsFrameIndex(0), RegSaveFrameIndex(0), VarArgsGPOffset(0), - VarArgsFPOffset(0) {} + VarArgsFPOffset(0), + ArgumentStackSize(0) {} explicit X86MachineFunctionInfo(MachineFunction &MF) : ForceFramePointer(false), @@ -91,7 +95,8 @@ VarArgsFrameIndex(0), RegSaveFrameIndex(0), VarArgsGPOffset(0), - VarArgsFPOffset(0) {} + VarArgsFPOffset(0), + ArgumentStackSize(0) {} bool getForceFramePointer() const { return ForceFramePointer;} void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; } @@ -128,6 +133,9 @@ unsigned getVarArgsFPOffset() const { return VarArgsFPOffset; } void setVarArgsFPOffset(unsigned Offset) { VarArgsFPOffset = Offset; } + + unsigned getArgumentStackSize() const { return ArgumentStackSize; } + void setArgumentStackSize(unsigned size) { ArgumentStackSize = size; } }; } // End llvm namespace From rafael.espindola at gmail.com Tue Aug 30 14:43:21 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 19:43:21 -0000 Subject: [llvm-commits] [llvm] r138814 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrCompiler.td X86InstrInfo.td Message-ID: <20110830194321.91B082A6C12E@llvm.org> Author: rafael Date: Tue Aug 30 14:43:21 2011 New Revision: 138814 URL: http://llvm.org/viewvc/llvm-project?rev=138814&view=rev Log: Adds a SelectionDAG node X86SegAlloca which will be custom lowered from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrCompiler.td llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138814&r1=138813&r2=138814&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 14:43:21 2011 @@ -10636,6 +10636,7 @@ case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; + case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=138814&r1=138813&r2=138814&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Aug 30 14:43:21 2011 @@ -286,6 +286,11 @@ // WIN_ALLOCA - Windows's _chkstk call to do stack probing. WIN_ALLOCA, + // SEG_ALLOCA - For allocating variable amounts of stack space when using + // segmented stacks. Check if the current stacklet has enough space, and + // defects to heap allocation if not. + SEG_ALLOCA, + // Memory barrier MEMBARRIER, MFENCE, Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=138814&r1=138813&r2=138814&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Aug 30 14:43:21 2011 @@ -106,6 +106,26 @@ def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), "# dynamic stack allocation", [(X86WinAlloca)]>; + +// When using segmented stacks these are lowered into instructions which first +// check if the current stacklet has enough free memory. If it does, memory is +// allocated by bumping the stack pointer. Otherwise memory is allocated from +// the heap. + +let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in +def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), + "# variable sized alloca for segmented stacks", + [(set GR32:$dst, + (X86SegAlloca GR32:$size))]>, + Requires<[In32BitMode]>; + +let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in +def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), + "# variable sized alloca for segmented stacks", + [(set GR64:$dst, + (X86SegAlloca GR64:$size))]>, + Requires<[In64BitMode]>; + } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=138814&r1=138813&r2=138814&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Aug 30 14:43:21 2011 @@ -97,6 +97,8 @@ def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; @@ -228,6 +230,9 @@ def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; From rafael.espindola at gmail.com Tue Aug 30 14:47:04 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 19:47:04 -0000 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <20110830194704.AA1372A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 14:47:04 2011 New Revision: 138818 URL: http://llvm.org/viewvc/llvm-project?rev=138818&view=rev Log: Adds support for variable sized allocas. For a variable sized alloca, code is inserted to first check if the current stacklet has enough space. If so, space is allocated by simply decrementing the stack pointer. Otherwise a runtime routine (__morestack_allocate_stack_space in libgcc) is called which allocates the required memory from the heap. Patch by Sanjoy Das. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138818&r1=138817&r2=138818&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 14:47:04 2011 @@ -51,6 +51,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetOptions.h" using namespace llvm; using namespace dwarf; @@ -522,8 +523,9 @@ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), - (Subtarget->isTargetCOFF() - && !Subtarget->isTargetEnvMacho() + ((Subtarget->isTargetCOFF() + && !Subtarget->isTargetEnvMacho()) || + EnableSegmentedStacks ? Custom : Expand)); if (!UseSoftFloat && X86ScalarSSEf64) { @@ -8844,8 +8846,10 @@ SDValue X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { - assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && - "This should be used only on Windows targets"); + assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || + EnableSegmentedStacks) && + "This should be used only on Windows targets or when segmented stacks " + "are being used."); assert(!Subtarget->isTargetEnvMacho()); DebugLoc dl = Op.getDebugLoc(); @@ -8854,23 +8858,49 @@ SDValue Size = Op.getOperand(1); // FIXME: Ensure alignment here - SDValue Flag; + bool Is64Bit = Subtarget->is64Bit(); + EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; - EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; - unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); + if (EnableSegmentedStacks) { + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &MRI = MF.getRegInfo(); - Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); - Flag = Chain.getValue(1); + if (Is64Bit) { + // The 64 bit implementation of segmented stacks needs to clobber both r10 + // r11. This makes it impossible to use it along with nested paramenters. + const Function *F = MF.getFunction(); + + for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); + I != E; I++) + if (I->hasNestAttr()) + report_fatal_error("Cannot use segmented stacks with functions that " + "have nested arguments."); + } + + const TargetRegisterClass *AddrRegClass = + getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); + unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); + Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); + SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, + DAG.getRegister(Vreg, SPTy)); + SDValue Ops1[2] = { Value, Chain }; + return DAG.getMergeValues(Ops1, 2, dl); + } else { + SDValue Flag; + unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); + Flag = Chain.getValue(1); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); - Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); - Flag = Chain.getValue(1); + Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); + Flag = Chain.getValue(1); - Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); - SDValue Ops1[2] = { Chain.getValue(0), Chain }; - return DAG.getMergeValues(Ops1, 2, dl); + SDValue Ops1[2] = { Chain.getValue(0), Chain }; + return DAG.getMergeValues(Ops1, 2, dl); + } } SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { @@ -11635,6 +11665,119 @@ } MachineBasicBlock * +X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, + bool Is64Bit) const { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc DL = MI->getDebugLoc(); + MachineFunction *MF = BB->getParent(); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + + assert(EnableSegmentedStacks); + + unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; + unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; + + // BB: + // ... [Till the alloca] + // If stacklet is not large enough, jump to mallocMBB + // + // bumpMBB: + // Allocate by subtracting from RSP + // Jump to continueMBB + // + // mallocMBB: + // Allocate by call to runtime + // + // continueMBB: + // ... + // [rest of original BB] + // + + MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); + + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetRegisterClass *AddrRegClass = + getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); + + unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), + bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), + tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), + sizeVReg = MI->getOperand(1).getReg(), + physSPReg = Is64Bit ? X86::RSP : X86::ESP; + + MachineFunction::iterator MBBIter = BB; + ++MBBIter; + + MF->insert(MBBIter, bumpMBB); + MF->insert(MBBIter, mallocMBB); + MF->insert(MBBIter, continueMBB); + + continueMBB->splice(continueMBB->begin(), BB, llvm::next + (MachineBasicBlock::iterator(MI)), BB->end()); + continueMBB->transferSuccessorsAndUpdatePHIs(BB); + + // Add code to the main basic block to check if the stack limit has been hit, + // and if so, jump to mallocMBB otherwise to bumpMBB. + BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); + BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg) + .addReg(tmpSPVReg).addReg(sizeVReg); + BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) + .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) + .addReg(tmpSPVReg); + BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); + + // bumpMBB simply decreases the stack pointer, since we know the current + // stacklet has enough space. + BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) + .addReg(tmpSPVReg); + BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) + .addReg(tmpSPVReg); + BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); + + // Calls into a routine in libgcc to allocate more space from the heap. + if (Is64Bit) { + BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) + .addReg(sizeVReg); + BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) + .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); + } else { + BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) + .addImm(12); + BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); + BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) + .addExternalSymbol("__morestack_allocate_stack_space"); + } + + if (!Is64Bit) + BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) + .addImm(16); + + BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) + .addReg(Is64Bit ? X86::RAX : X86::EAX); + BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); + + // Set up the CFG correctly. + BB->addSuccessor(bumpMBB); + BB->addSuccessor(mallocMBB); + mallocMBB->addSuccessor(continueMBB); + bumpMBB->addSuccessor(continueMBB); + + // Take care of the PHI nodes. + BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), + MI->getOperand(0).getReg()) + .addReg(mallocPtrVReg).addMBB(mallocMBB) + .addReg(bumpSPPtrVReg).addMBB(bumpMBB); + + // Delete the original pseudo instruction. + MI->eraseFromParent(); + + // And we're done. + return continueMBB; +} + +MachineBasicBlock * X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); @@ -11769,6 +11912,10 @@ return BB; case X86::WIN_ALLOCA: return EmitLoweredWinAlloca(MI, BB); + case X86::SEG_ALLOCA_32: + return EmitLoweredSegAlloca(MI, BB, false); + case X86::SEG_ALLOCA_64: + return EmitLoweredSegAlloca(MI, BB, true); case X86::TLSCall_32: case X86::TLSCall_64: return EmitLoweredTLSCall(MI, BB); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=138818&r1=138817&r2=138818&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Aug 30 14:47:04 2011 @@ -942,6 +942,10 @@ MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, + MachineBasicBlock *BB, + bool Is64Bit) const; + MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const; From nicolas.geoffray at lip6.fr Tue Aug 30 14:50:33 2011 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Tue, 30 Aug 2011 19:50:33 -0000 Subject: [llvm-commits] [llvm] r138819 - /llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Message-ID: <20110830195033.AD3582A6C12C@llvm.org> Author: geoffray Date: Tue Aug 30 14:50:33 2011 New Revision: 138819 URL: http://llvm.org/viewvc/llvm-project?rev=138819&view=rev Log: The code model of JIT should default to JITDefault. Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=138819&r1=138818&r2=138819&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Tue Aug 30 14:50:33 2011 @@ -204,7 +204,7 @@ bool GVsWithCode = true, Reloc::Model RM = Reloc::Default, CodeModel::Model CMM = - CodeModel::Default); + CodeModel::JITDefault); /// addModule - Add a Module to the list of modules that we can JIT from. /// Note that this takes ownership of the Module: when the ExecutionEngine is From rafael.espindola at gmail.com Tue Aug 30 14:51:30 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 19:51:30 -0000 Subject: [llvm-commits] [llvm] r138820 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Message-ID: <20110830195130.27BF22A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 14:51:29 2011 New Revision: 138820 URL: http://llvm.org/viewvc/llvm-project?rev=138820&view=rev Log: Some test code to check if correct code is being generated. Patch by Sanjoy Das. Added: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Added: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=138820&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (added) +++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Tue Aug 30 14:51:29 2011 @@ -0,0 +1,87 @@ +; RUN: llc < %s -march=x86 -segmented-stacks | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86-64 -segmented-stacks | FileCheck %s -check-prefix=X64 + +; Just to prevent the alloca from being optimized away +declare void @dummy_use(i32*, i32) + +define i32 @test_basic(i32 %l) { + %mem = alloca i32, i32 %l + call void @dummy_use (i32* %mem, i32 %l) + %terminate = icmp eq i32 %l, 0 + br i1 %terminate, label %true, label %false + +true: + ret i32 0 + +false: + %newlen = sub i32 %l, 1 + %retvalue = call i32 @test_basic(i32 %newlen) + ret i32 %retvalue + +; X32: test_basic: + +; X32: leal -12(%esp), %ecx +; X32-NEXT: cmpl %gs:48, %ecx + +; X32: subl $8, %esp +; X32-NEXT: pushl $4 +; X32-NEXT: pushl $12 +; X32-NEXT: calll __morestack +; X32-NEXT: addl $8, %esp +; X32-NEXT: ret + +; X32: movl %eax, %esp + +; X32: subl $12, %esp +; X32-NEXT: pushl %ecx +; X32-NEXT: calll __morestack_allocate_stack_space +; X32-NEXT: addl $16, %esp + +; X64: test_basic: + +; X64: leaq -24(%rsp), %r11 +; X64-NEXT: cmpq %fs:112, %r11 + +; X64: movabsq $24, %r10 +; X64-NEXT: movabsq $0, %r11 +; X64-NEXT: callq __morestack +; X64-NEXT: ret + +; X64: movq %rsp, %rax +; X64-NEXT: subq %rcx, %rax +; X64-NEXT: cmpq %rax, %fs:112 + +; X64: movq %rax, %rsp + +; X64: movq %rcx, %rdi +; X64-NEXT: callq __morestack_allocate_stack_space + +} + +define i32 @test_nested(i32 * nest %closure, i32 %other) { + %addend = load i32 * %closure + %result = add i32 %other, %addend + ret i32 %result + +; X32: leal (%esp), %edx +; X32-NEXT: cmpl %gs:48, %edx + + +; X32: subl $8, %esp +; X32-NEXT: pushl $4 +; X32-NEXT: pushl $0 +; X32-NEXT: calll __morestack +; X32-NEXT: addl $8, %esp +; X32-NEXT: ret + +; X64: leaq (%rsp), %r11 +; X64-NEXT: cmpq %fs:112, %r11 + +; X64: movq %r10, %rax +; X64-NEXT: movabsq $0, %r10 +; X64-NEXT: movabsq $0, %r11 +; X64-NEXT: callq __morestack +; X64-NEXT: ret +; X64-NEXT: movq %rax, %r10 + +} From eli.friedman at gmail.com Tue Aug 30 14:55:43 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 30 Aug 2011 12:55:43 -0700 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: <4E5D2D5C.1050209@grosser.es> References:

<4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser wrote: > On 08/30/2011 01:04 PM, Villmow, Micah wrote: >> >> Thanks for the feedback, new revision attached. > > There seems one unneeded white space change. (Can be fixed on commit) > >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool isSigned, >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); >> + >> ? ? ? ?std::pair ? ExpandChainLibCall(RTLIB::Libcall > > Otherwise, it looks good. Let's see if Eli has any additional comments. Looks fine. Note that it would be nice to make sure we implement MERGE_VALUES for all the other cases in type legalization... (integer promotion, vector scalarization, etc.) -Eli From resistor at mac.com Tue Aug 30 15:03:11 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 20:03:11 -0000 Subject: [llvm-commits] [llvm] r138822 - /llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Message-ID: <20110830200311.AE1962A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 15:03:11 2011 New Revision: 138822 URL: http://llvm.org/viewvc/llvm-project?rev=138822&view=rev Log: Port Thumb2 assembler tests over to disassembler tests. Added: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Added: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=138822&view=auto ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (added) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Tue Aug 30 15:03:11 2011 @@ -0,0 +1,41 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# ADC (immediate) +#------------------------------------------------------------------------------ +# CHECK: adc r0, r1, #4 +# CHECK: adcs r0, r1, #0 +# CHECK: adc r1, r2, #255 +# CHECK: adc r3, r7, #5570645 +# CHECK: adc r8, r12, #2852170240 +# CHECK: adc r9, r7, #2779096485 +# CHECK: adc r5, r3, #2264924160 +# CHECK: adc r4, r2, #2139095040 +# CHECK: adc r4, r2, #1664 + +0x41 0xf1 0x04 0x00 +0x51 0xf1 0x00 0x00 +0x42 0xf1 0xff 0x01 +0x47 0xf1 0x55 0x13 +0x4c 0xf1 0xaa 0x28 +0x47 0xf1 0xa5 0x39 +0x43 0xf1 0x07 0x45 +0x42 0xf1 0xff 0x44 +0x42 0xf5 0xd0 0x64 + +#------------------------------------------------------------------------------ +# IT +#------------------------------------------------------------------------------ +# Test encodings of a few full IT blocks, not just the IT instruction + +# CHECK: iteet eq +# CHECK: addeq r0, r1, r2 +# CHECK: nopne +# CHECK: subne r5, r6, r7 +# CHECK: addeq r1, r2, #4 + +0x0d 0xbf +0x88 0x18 +0x00 0xbf +0xf5 0x1b +0x11 0x1d From greened at obbligato.org Tue Aug 30 15:05:11 2011 From: greened at obbligato.org (David A. Greene) Date: Tue, 30 Aug 2011 15:05:11 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> (David Greene's message of "Mon, 29 Aug 2011 14:18:08 -0500") References: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Message-ID: David Greene writes: > Emit a repeated sequence of bytes using .zero. This saves an enormous > amount of asm file space for certain programs. > --- > > Here's another updated version of the patch, including testcase. Ping? -Dave From Micah.Villmow at amd.com Tue Aug 30 15:06:16 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Tue, 30 Aug 2011 15:06:16 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

<4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: Eli, So for the other cases, it would just be call DecomposeMERGE_VALUES and then call the correct legalization function on the return value, correct? I'll send a second patch with those later. Micah > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Tuesday, August 30, 2011 12:56 PM > To: Tobias Grosser > Cc: Villmow, Micah; llvm-commits > Subject: Re: [llvm-commits] Patch to add support for > WidenVecRes_MERGE_VALUES > > On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser > wrote: > > On 08/30/2011 01:04 PM, Villmow, Micah wrote: > >> > >> Thanks for the feedback, new revision attached. > > > > There seems one unneeded white space change. (Can be fixed on commit) > > > >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool > isSigned, > >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); > >> + > >> ? ? ? ?std::pair > ExpandChainLibCall(RTLIB::Libcall > > > > Otherwise, it looks good. Let's see if Eli has any additional > comments. > > Looks fine. > > Note that it would be nice to make sure we implement MERGE_VALUES for > all the other cases in type legalization... (integer promotion, vector > scalarization, etc.) > > -Eli From eli.friedman at gmail.com Tue Aug 30 15:08:43 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 30 Aug 2011 13:08:43 -0700 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References:

<4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: On Tue, Aug 30, 2011 at 1:06 PM, Villmow, Micah wrote: > Eli, > ?So for the other cases, it would just be call DecomposeMERGE_VALUES and then call the correct > legalization function on the return value, correct? Yes. > I'll send a second patch with those later. Great, thanks. -Eli > Micah > >> -----Original Message----- >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> Sent: Tuesday, August 30, 2011 12:56 PM >> To: Tobias Grosser >> Cc: Villmow, Micah; llvm-commits >> Subject: Re: [llvm-commits] Patch to add support for >> WidenVecRes_MERGE_VALUES >> >> On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser >> wrote: >> > On 08/30/2011 01:04 PM, Villmow, Micah wrote: >> >> >> >> Thanks for the feedback, new revision attached. >> > >> > There seems one unneeded white space change. (Can be fixed on commit) >> > >> >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, >> >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool >> isSigned, >> >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); >> >> + >> >> ? ? ? ?std::pair >> ExpandChainLibCall(RTLIB::Libcall >> > >> > Otherwise, it looks good. Let's see if Eli has any additional >> comments. >> >> Looks fine. >> >> Note that it would be nice to make sure we implement MERGE_VALUES for >> all the other cases in type legalization... (integer promotion, vector >> scalarization, etc.) >> >> -Eli > > > From rafael.espindola at gmail.com Tue Aug 30 15:25:49 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 20:25:49 -0000 Subject: [llvm-commits] [llvm] r138823 - /llvm/trunk/docs/SegmentedStacks.html Message-ID: <20110830202549.A3D0B2A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 15:25:49 2011 New Revision: 138823 URL: http://llvm.org/viewvc/llvm-project?rev=138823&view=rev Log: Preliminary documentation in docs/SegmentedStacks.html. Added: llvm/trunk/docs/SegmentedStacks.html Added: llvm/trunk/docs/SegmentedStacks.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SegmentedStacks.html?rev=138823&view=auto ============================================================================== --- llvm/trunk/docs/SegmentedStacks.html (added) +++ llvm/trunk/docs/SegmentedStacks.html Tue Aug 30 15:25:49 2011 @@ -0,0 +1,99 @@ + + + + Segmented Stacks in LLVM + + + + + +

Segmented Stacks in LLVM

Written by Sanjoy Das

+ +

Introduction
Implementation Details +
1. Allocating Stacklets
2. Variable Sized Allocas
+
Results +
1. Go on LLVM
2. Runtime ABI
+

+ +

Introduction

+ Segmented stack allows stack space to be allocated incrementally than as a monolithic chunk (of some worst case size) at thread initialization. This is done by allocating stack blocks (henceforth called stacklets) and linking them into a doubly linked list. The function prologue is responsible for checking if the current stacklet has enough space for the function to execute; and if not, call into the libgcc runtime to allocate more stack space. Support for segmented stacks on x86 / Linux is currently being worked on. +

+ The runtime functionality is already there in libgcc. +

+ +

Implementation Details

Allocating Stacklets

+ As mentioned above, the function prologue checks if the current stacklet has enough space. The current approach is to use a slot in the TCB to store the current stack limit (minus the amount of space needed to allocate a new block) - this slot's offset is again dictated by libgcc. The generated assembly looks like this on x86-64: +

+	          leaq	-8(%rsp), %r10
+	          cmpq	%fs:112,  %r10
+	          jg	.LBB0_2
+
+            # More stack space needs to be allocated
+	          movabsq	$8, %r10 # The amount of space needed
+	          movabsq	$0, %r11 # The total size of arguments passed on stack
+	          callq	__morestack
+	          ret # The reason for this extra return is explained below
+            .LBB0_2:
+            # Usual prologue continues here
+

+ The size of function arguments on the stack needs to be passed to __morestack (this function is implemented in libgcc) since that number of bytes has to be copied from the previous stacklet to the current one. This is so that SP (and FP) relative addressing of function arguments work as expected. +

+ The unusual ret is needed to have the function which made a call to __morestack return correctly. __morestack, instead of returning, calls into .LBB0_2. This is possible since both, the size of the ret instruction and the PC of call to __morestack are known. When the function body returns, control is transferred back to __morestack. __morestack then de-allocates the new stacklet, restores the correct SP value, and does a second return, which returns control to the correct caller. +

+ +

Variable Sized Allocas

+ The section on allocating stacklets automatically assumes that every stack frame will be of fixed size. However, LLVM allows the use of the llvm.alloca intrinsic to allocate dynamically sized blocks of memory on the stack. When faced with such a variable-sized alloca, code is generated to +

Check if the current stacklet has enough space. If yes, just bump the SP, like in the normal case.
If not, generate a call to libgcc, which allocates the memory from the heap.

+ The memory allocated from the heap is linked into a list in the current stacklet, and freed along with the same. This prevents a memory leak. +

+ +

+ + +

+ + Sanjoy Das
+ LLVM Compiler Infrastructure
+ Last modified: $Date$ +

+ + + From echristo at apple.com Tue Aug 30 15:31:48 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 13:31:48 -0700 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <20110830194704.AA1372A6C12C@llvm.org> References: <20110830194704.AA1372A6C12C@llvm.org> Message-ID: On Aug 30, 2011, at 12:47 PM, Rafael Espindola wrote: > (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), > - (Subtarget->isTargetCOFF() > - && !Subtarget->isTargetEnvMacho() > + ((Subtarget->isTargetCOFF() > + && !Subtarget->isTargetEnvMacho()) || > + EnableSegmentedStacks > ? Custom : Expand)); This set of conditionals needs to be taken out into a field and shot in the head. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/90aa3ea3/attachment.html From chandlerc at google.com Tue Aug 30 15:51:14 2011 From: chandlerc at google.com (Chandler Carruth) Date: Tue, 30 Aug 2011 13:51:14 -0700 Subject: [llvm-commits] AddressSanitizer, first patch In-Reply-To: References: Message-ID: Adding Eric as this fell out of his inbox... On Fri, Aug 19, 2011 at 11:14 AM, Kostya Serebryany wrote: > Hello llvm-commits, > > I would ask you to consider the following patch, which adds the basic > functionality of AddressSanitizer, a memory error detector. > > Quick description: > The tool finds stack and heap out-of-bound bugs and use-after-free bugs. > It consists of an LLVM instrumentation pass and a run-time library which > replaces malloc. > The LLVM pass instruments all memory accesses and inserts redzones around > stack objects and globals. > The run-time library inserts redzones around heap objects and handles > error reporting. > The slowdown introduced by the tool varies between 1.5x and 2.5x (on > CPU2006 the average is 1.73x). > > Until now the tool was developed as a separate project. > It has been quite successful at finding bugs for the Chromium browser > project > ( > http://blog.chromium.org/2011/06/testing-chromium-addresssanitizer-fast.html > ) > and other pieces of Google code. > > For the full description of the tool please read > http://code.google.com/p/address-sanitizer/wiki/AddressSanitizer > > http://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm > http://code.google.com/p/address-sanitizer/wiki/PerformanceNumbers > > > This patch adds the basic instrumentation functionality (w/o stack and > global redzones) and one test. > > If/when this patch is submitted, the following patches will follow: > clang/driver support (flags, etc) > stack/globals support > run-time librrary > integration tests > > The patch file is attached, or it can be viewed at > http://codereview.appspot.com/4867059/ > > Thanks, > > --kcc > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/1de0d0e0/attachment.html From jyasskin at google.com Tue Aug 30 15:53:29 2011 From: jyasskin at google.com (Jeffrey Yasskin) Date: Tue, 30 Aug 2011 20:53:29 -0000 Subject: [llvm-commits] [llvm] r138825 - in /llvm/trunk: include/llvm/MC/EDInstInfo.h lib/MC/MCDisassembler/EDInst.h lib/MC/MCDisassembler/EDToken.cpp lib/MC/MCDisassembler/EDToken.h lib/Target/X86/X86AsmPrinter.cpp unittests/VMCore/MetadataTest.cpp Message-ID: <20110830205329.7B6142A6C12C@llvm.org> Author: jyasskin Date: Tue Aug 30 15:53:29 2011 New Revision: 138825 URL: http://llvm.org/viewvc/llvm-project?rev=138825&view=rev Log: Fix C++0x narrowing errors when char is unsigned. In the case of EDInstInfo, this would actually cause a bug when -1 became 255 and was then compared >=0 in llvm-mc/Disassembler.cpp. Modified: llvm/trunk/include/llvm/MC/EDInstInfo.h llvm/trunk/lib/MC/MCDisassembler/EDInst.h llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp llvm/trunk/lib/MC/MCDisassembler/EDToken.h llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp llvm/trunk/unittests/VMCore/MetadataTest.cpp Modified: llvm/trunk/include/llvm/MC/EDInstInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/EDInstInfo.h?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/EDInstInfo.h (original) +++ llvm/trunk/include/llvm/MC/EDInstInfo.h Tue Aug 30 15:53:29 2011 @@ -21,7 +21,7 @@ uint8_t numOperands; uint8_t operandTypes[EDIS_MAX_OPERANDS]; uint8_t operandFlags[EDIS_MAX_OPERANDS]; - const char operandOrders[EDIS_MAX_SYNTAXES][EDIS_MAX_OPERANDS]; + const signed char operandOrders[EDIS_MAX_SYNTAXES][EDIS_MAX_OPERANDS]; }; } // namespace llvm Modified: llvm/trunk/lib/MC/MCDisassembler/EDInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDInst.h?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDInst.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDInst.h Tue Aug 30 15:53:29 2011 @@ -73,7 +73,7 @@ std::string String; /// The order in which operands from the InstInfo's operand information appear /// in String - const char* OperandOrder; + const signed char* OperandOrder; /// The result of the parseOperands() function CachedResult ParseResult; Modified: llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp Tue Aug 30 15:53:29 2011 @@ -87,7 +87,7 @@ int EDToken::tokenize(std::vector &tokens, std::string &str, - const char *operandOrder, + const signed char *operandOrder, EDDisassembler &disassembler) { SmallVector parsedOperands; SmallVector asmTokens; Modified: llvm/trunk/lib/MC/MCDisassembler/EDToken.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDToken.h?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDToken.h (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDToken.h Tue Aug 30 15:53:29 2011 @@ -125,7 +125,7 @@ // assembly syntax static int tokenize(std::vector &tokens, std::string &str, - const char *operandOrder, + const signed char *operandOrder, EDDisassembler &disassembler); /// getString - Directs a character pointer to the string, returning 0 on Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Tue Aug 30 15:53:29 2011 @@ -504,8 +504,8 @@ // .indirect_symbol _foo OutStreamer.EmitSymbolAttribute(Stubs[i].second.getPointer(), MCSA_IndirectSymbol); - // hlt; hlt; hlt; hlt; hlt hlt = 0xf4 = -12. - const char HltInsts[] = { -12, -12, -12, -12, -12 }; + // hlt; hlt; hlt; hlt; hlt hlt = 0xf4. + const char HltInsts[] = "\xf4\xf4\xf4\xf4\xf4"; OutStreamer.EmitBytes(StringRef(HltInsts, 5), 0/*addrspace*/); } Modified: llvm/trunk/unittests/VMCore/MetadataTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/MetadataTest.cpp?rev=138825&r1=138824&r2=138825&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/MetadataTest.cpp (original) +++ llvm/trunk/unittests/VMCore/MetadataTest.cpp Tue Aug 30 15:53:29 2011 @@ -63,7 +63,7 @@ // Test printing of MDString with non-printable characters. TEST_F(MDStringTest, PrintingComplex) { - char str[5] = {0, '\n', '"', '\\', -1}; + char str[5] = {0, '\n', '"', '\\', (char)-1}; MDString *s = MDString::get(Context, StringRef(str+0, 5)); std::string Str; raw_string_ostream oss(Str); From isanbard at gmail.com Tue Aug 30 15:54:11 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 30 Aug 2011 20:54:11 -0000 Subject: [llvm-commits] [llvm] r138826 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110830205411.E40FC2A6C12C@llvm.org> Author: void Date: Tue Aug 30 15:54:11 2011 New Revision: 138826 URL: http://llvm.org/viewvc/llvm-project?rev=138826&view=rev Log: Enable compact unwind info by default. This only applies to Darwin when CFI is disabled. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138826&r1=138825&r2=138826&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Aug 30 15:54:11 2011 @@ -35,13 +35,6 @@ // FIXME: completely move here. extern cl::opt ForceStackAlign; -// FIXME: Remove once linker support is available. The feature exists only on -// Darwin at the moment. -static cl::opt -GenerateCompactUnwind("gen-compact-unwind", - cl::desc("Generate compact unwind encoding"), - cl::Hidden); - bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { return !MF.getFrameInfo()->hasVarSizedObjects(); } @@ -908,8 +901,7 @@ } // Darwin 10.7 and greater has support for compact unwind encoding. - if (GenerateCompactUnwind && - STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) + if (STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); } From criswell at uiuc.edu Tue Aug 30 16:05:33 2011 From: criswell at uiuc.edu (John Criswell) Date: Tue, 30 Aug 2011 21:05:33 -0000 Subject: [llvm-commits] [poolalloc] r138827 - /poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Message-ID: <20110830210533.BB9132A6C12C@llvm.org> Author: criswell Date: Tue Aug 30 16:05:33 2011 New Revision: 138827 URL: http://llvm.org/viewvc/llvm-project?rev=138827&view=rev Log: Refactored CloneAuxIntoGlobal() again to avoid having to sort the list of DSCallSites in the local and global DSGraphs on every execution. This speeds up the test case from OpenSSH from 125 seconds to 44 seconds for the -dsa-bu pass without the -debug command-line option. Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=138827&r1=138826&r2=138827&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Tue Aug 30 16:05:33 2011 @@ -517,90 +517,71 @@ ReachabilityCloner RC(GG, G, 0); // - // Sort the lists of DSCallSites by the LLVM value that is used for the - // indirect call. - // - G->getAuxFunctionCalls().sort (compareDSCallSites); - GG->getAuxFunctionCalls().sort (compareDSCallSites); - - // // Determine which called values are both within the local graph DSCallsites // and the global graph DSCallsites. Note that we require that the global // graph have a DSNode for the called value. // - std::set LocalCallValues; - std::set GlobalCallValues; - std::set CommonCallValues; + std::map CommonCallValues; for (DSGraph::afc_iterator ii = G->afc_begin(), ee = G->afc_end(); ii != ee; ++ii) { + // + // If the globals graph has a DSNode for the LLVM value used in the local + // unresolved call site, then it might have a DSCallSite for it, too. + // Record this call site as a potential call site that will need to be + // merged. + // + // Otherwise, just add the call site to the globals graph. + // Value * V = ii->getCallSite().getCalledValue(); if (GG->hasNodeForValue(V)) { - LocalCallValues.insert (V); + DSCallSite & DS = *ii; + CommonCallValues[V] = &DS; + } else { + GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); } } - for (DSGraph::afc_iterator ii = GG->afc_begin(); - ii != GG->afc_end(); - ++ii) { - Value * V = ii->getCallSite().getCalledValue(); - GlobalCallValues.insert (V); - } - - std::set_intersection (LocalCallValues.begin(), LocalCallValues.end(), - GlobalCallValues.begin(), GlobalCallValues.end(), - std::inserter (CommonCallValues, - CommonCallValues.begin())); - LocalCallValues.clear(); - GlobalCallValues.clear(); - // - // Scan through all the unresolved call sites in the local graph for which - // the globals graph also considers the call site unresolved; merge such call - // sites together. + // Scan through all the unresolved call sites in the globals graph and see if + // the local graph has a call using the same LLVM value. If so, merge the + // call sites. // - DSGraph::afc_iterator ii = G->afc_begin(); DSGraph::afc_iterator GGii = GG->afc_begin(); - for (std::set::iterator iv = CommonCallValues.begin(); - iv != CommonCallValues.end(); - ++iv) { - // - // Move the iterator in the local graph to the appropriate call site. - // In the process, if we see a call site that needs to be added to the - // globals graph, do that now. - // - Value * V = *iv; - while (ii->getCallSite().getCalledValue() != V) { - GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); - ++ii; - } - + for (; GGii != GG->afc_end(); ++GGii) { // - // Move the iterator in the global graph to the appropriate call site. + // Determine if this unresolved call site is also in the local graph. + // If so, then merge it. // - while (GGii->getCallSite().getCalledValue() != V) - ++GGii; - - // - // Merge the two call sites together. - // - RC.cloneCallSite(*ii).mergeWith(*GGii); + Value * CalledValue = GGii->getCallSite().getCalledValue(); + std::map::iterator v; + v = CommonCallValues.find (CalledValue); + if (v != CommonCallValues.end()) { + // + // Merge the unresolved call site into the globals graph. + // + RC.cloneCallSite(*(v->second)).mergeWith(*GGii); - // - // Make sure not to repeat any merges. - // - ++ii; - ++GGii; + // + // Mark that this call site was merged by removing the called LLVM value + // from the set of values common to both the local and global DSGraphs. + // + CommonCallValues.erase (v); + } } // // We've now merged all DSCallSites that were known both to the local graph // and the globals graph. Now, there are still some local call sites that - // need to be *added* to the globals graph. Do that now. + // need to be *added* to the globals graph; they are in DSCallSites remaining + // in CommonCallValues. // - for (; ii != G->afc_end(); ++ii) { - GG->addAuxFunctionCall(RC.cloneCallSite(*ii)); + std::map::iterator v = CommonCallValues.begin (); + for (; v != CommonCallValues.end(); ++v) { + GG->addAuxFunctionCall(RC.cloneCallSite(*(v->second))); } + + return; } From isanbard at gmail.com Tue Aug 30 16:08:45 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 30 Aug 2011 21:08:45 -0000 Subject: [llvm-commits] [test-suite] r138828 - /test-suite/trunk/SingleSource/Regression/C++/EH/simple_rethrow.cpp Message-ID: <20110830210845.80CA12A6C12C@llvm.org> Author: void Date: Tue Aug 30 16:08:45 2011 New Revision: 138828 URL: http://llvm.org/viewvc/llvm-project?rev=138828&view=rev Log: Silence warnings about "control may reach end of non-void function" Modified: test-suite/trunk/SingleSource/Regression/C++/EH/simple_rethrow.cpp Modified: test-suite/trunk/SingleSource/Regression/C++/EH/simple_rethrow.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/EH/simple_rethrow.cpp?rev=138828&r1=138827&r2=138828&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Regression/C++/EH/simple_rethrow.cpp (original) +++ test-suite/trunk/SingleSource/Regression/C++/EH/simple_rethrow.cpp Tue Aug 30 16:08:45 2011 @@ -1,11 +1,11 @@ #include -int throws() { +void throws() { printf("Throwing int\n"); throw 16; }; -int callsthrows() { +void callsthrows() { try { throws(); } catch (...) { From benny.kra at googlemail.com Tue Aug 30 16:10:04 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 30 Aug 2011 14:10:04 -0700 Subject: [llvm-commits] [llvm] r138826 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp In-Reply-To: <20110830205411.E40FC2A6C12C@llvm.org> References: <20110830205411.E40FC2A6C12C@llvm.org> Message-ID: On Tue, Aug 30, 2011 at 13:54, Bill Wendling wrote: > Author: void > Date: Tue Aug 30 15:54:11 2011 > New Revision: 138826 > > URL: http://llvm.org/viewvc/llvm-project?rev=138826&view=rev > Log: > Enable compact unwind info by default. This only applies to Darwin when CFI is > disabled. > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86FrameLowering.cpp > > Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138826&r1=138825&r2=138826&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Aug 30 15:54:11 2011 > @@ -35,13 +35,6 @@ > ?// FIXME: completely move here. > ?extern cl::opt ForceStackAlign; > > -// FIXME: Remove once linker support is available. The feature exists only on > -// Darwin at the moment. > -static cl::opt > -GenerateCompactUnwind("gen-compact-unwind", > - ? ? ? ? ? ? ? ? ? ? ?cl::desc("Generate compact unwind encoding"), > - ? ? ? ? ? ? ? ? ? ? ?cl::Hidden); > - > ?bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { > ? return !MF.getFrameInfo()->hasVarSizedObjects(); > ?} > @@ -908,8 +901,7 @@ > ? } > > ? // Darwin 10.7 and greater has support for compact unwind encoding. > - ?if (GenerateCompactUnwind && > - ? ? ?STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) > + ?if (STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) > ? ? MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); > ?} The comment says 10.6 doesn't support compact unwinding but the code says it does? - Ben From resistor at mac.com Tue Aug 30 16:11:06 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 21:11:06 -0000 Subject: [llvm-commits] [llvm] r138829 - in /llvm/trunk: lib/Transforms/Scalar/DeadStoreElimination.cpp test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Message-ID: <20110830211106.B7B082A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 16:11:06 2011 New Revision: 138829 URL: http://llvm.org/viewvc/llvm-project?rev=138829&view=rev Log: Speculatively revert r138809 in an attempt to fix DragonEgg. Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=138829&r1=138828&r2=138829&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Tue Aug 30 16:11:06 2011 @@ -617,9 +617,8 @@ DeleteDeadInstruction(Dead, *MD, &DeadStackObjects); ++NumFastStores; MadeChange = true; + continue; } - - continue; } // Remove any dead non-memory-mutating instructions. Modified: llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll?rev=138829&r1=138828&r2=138829&view=diff ============================================================================== --- llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll (original) +++ llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Tue Aug 30 16:11:06 2011 @@ -1,27 +0,0 @@ -; RUN: opt -dse -S < %s | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin" - -%"class.std::auto_ptr" = type { i32* } - -; CHECK: @_Z3foov -define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp { -_ZNSt8auto_ptrIiED1Ev.exit: - %temp.lvalue = alloca %"class.std::auto_ptr", align 8 - call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) - %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 - %tmp.i.i = load i32** %_M_ptr.i.i, align 8, !tbaa !0 -; CHECK-NOT: store i32* null - store i32* null, i32** %_M_ptr.i.i, align 8, !tbaa !0 - %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0 - store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8, !tbaa !0 -; CHECK: ret void - ret void -} - -declare void @_Z3barv(%"class.std::auto_ptr"* sret) - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From resistor at mac.com Tue Aug 30 16:17:20 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 21:17:20 -0000 Subject: [llvm-commits] [llvm] r138830 - /llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Message-ID: <20110830211721.0431D2A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 16:17:20 2011 New Revision: 138830 URL: http://llvm.org/viewvc/llvm-project?rev=138830&view=rev Log: Remove empty file. Removed: llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll Removed: llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll?rev=138829&view=auto ============================================================================== (empty) From rafael.espindola at gmail.com Tue Aug 30 16:19:37 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 21:19:37 -0000 Subject: [llvm-commits] [llvm] r138831 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Message-ID: <20110830211937.5D7532A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 16:19:37 2011 New Revision: 138831 URL: http://llvm.org/viewvc/llvm-project?rev=138831&view=rev Log: Add a triple. Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=138831&r1=138830&r2=138831&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (original) +++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Tue Aug 30 16:19:37 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -segmented-stacks | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -march=x86-64 -segmented-stacks | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=i686-linux -segmented-stacks | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-linux -segmented-stacks | FileCheck %s -check-prefix=X64 ; Just to prevent the alloca from being optimized away declare void @dummy_use(i32*, i32) From isanbard at gmail.com Tue Aug 30 16:23:25 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 30 Aug 2011 21:23:25 -0000 Subject: [llvm-commits] [llvm] r138832 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110830212325.0D8F92A6C12C@llvm.org> Author: void Date: Tue Aug 30 16:23:24 2011 New Revision: 138832 URL: http://llvm.org/viewvc/llvm-project?rev=138832&view=rev Log: Fix off-by-one error Benjamin noticed. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138832&r1=138831&r2=138832&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Aug 30 16:23:24 2011 @@ -901,7 +901,7 @@ } // Darwin 10.7 and greater has support for compact unwind encoding. - if (STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6)) + if (STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); } From echristo at apple.com Tue Aug 30 16:24:42 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 14:24:42 -0700 Subject: [llvm-commits] [llvm] r138831 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll In-Reply-To: <20110830211937.5D7532A6C12C@llvm.org> References: <20110830211937.5D7532A6C12C@llvm.org> Message-ID: <117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com> On Aug 30, 2011, at 2:19 PM, Rafael Espindola wrote: > Author: rafael > Date: Tue Aug 30 16:19:37 2011 > New Revision: 138831 > > URL: http://llvm.org/viewvc/llvm-project?rev=138831&view=rev > Log: > Add a triple. > > Modified: > llvm/trunk/test/CodeGen/X86/segmented-stacks.ll > > Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=138831&r1=138830&r2=138831&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (original) > +++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Tue Aug 30 16:19:37 2011 > @@ -1,5 +1,5 @@ > -; RUN: llc < %s -march=x86 -segmented-stacks | FileCheck %s -check-prefix=X32 > -; RUN: llc < %s -march=x86-64 -segmented-stacks | FileCheck %s -check-prefix=X64 > +; RUN: llc < %s -mtriple=i686-linux -segmented-stacks | FileCheck %s -check-prefix=X32 > +; RUN: llc < %s -mtriple=x86_64-linux -segmented-stacks | FileCheck %s -check-prefix=X64 So this means we'll still segfault the compiler if segmented stacks are used with some darwin code? -eric From rafael.espindola at gmail.com Tue Aug 30 16:28:15 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 30 Aug 2011 17:28:15 -0400 Subject: [llvm-commits] [patch] Delete the old IL level tail duplicator In-Reply-To: <4E541DA0.9030006@gmail.com> References: <4E541DA0.9030006@gmail.com> Message-ID: <4E5D55EF.2030402@gmail.com> ping On 08/23/2011 05:37 PM, Rafael ?vila de Esp?ndola wrote: > The old tail duplicator doesn't use the ssa updater and therefore has to > run really early in the pipeline. > > I have tried creating a new one, but don't have the time to finish it > right now. In any case, we haven't run the existing one for some time > and should probably delete it. > > Is the attached patch OK? > > Cheers, > Rafael > From zwarich at apple.com Tue Aug 30 16:37:34 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 30 Aug 2011 14:37:34 -0700 Subject: [llvm-commits] [patch] Delete the old IL level tail duplicator In-Reply-To: <4E541DA0.9030006@gmail.com> References: <4E541DA0.9030006@gmail.com> Message-ID: The code being deleted looks pretty suspicious in places, and we don't use it. I'm all for deleting it. Cameron On Aug 23, 2011, at 2:37 PM, Rafael ?vila de Esp?ndola wrote: > The old tail duplicator doesn't use the ssa updater and therefore has to run really early in the pipeline. > > I have tried creating a new one, but don't have the time to finish it right now. In any case, we haven't run the existing one for some time and should probably delete it. > > Is the attached patch OK? > > Cheers, > Rafael > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From wendling at apple.com Tue Aug 30 16:48:40 2011 From: wendling at apple.com (Bill Wendling) Date: Tue, 30 Aug 2011 14:48:40 -0700 Subject: [llvm-commits] [patch] Delete the old IL level tail duplicator In-Reply-To: References: <4E541DA0.9030006@gmail.com> Message-ID: <6CE66D9C-FA6C-4049-AA22-0ECCF2A40B19@apple.com> If you do delete it, please mention it in the ReleaseNotes.html doc. -bw On Aug 30, 2011, at 2:37 PM, Cameron Zwarich wrote: > The code being deleted looks pretty suspicious in places, and we don't use it. I'm all for deleting it. > > Cameron > > On Aug 23, 2011, at 2:37 PM, Rafael ?vila de Esp?ndola wrote: > >> The old tail duplicator doesn't use the ssa updater and therefore has to run really early in the pipeline. >> >> I have tried creating a new one, but don't have the time to finish it right now. In any case, we haven't run the existing one for some time and should probably delete it. >> >> Is the attached patch OK? >> >> Cheers, >> Rafael >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Tue Aug 30 16:58:18 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 21:58:18 -0000 Subject: [llvm-commits] [llvm] r138833 - /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Message-ID: <20110830215818.47A2F2A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 16:58:18 2011 New Revision: 138833 URL: http://llvm.org/viewvc/llvm-project?rev=138833&view=rev Log: Clean up whitespace. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138833&r1=138832&r2=138833&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Aug 30 16:58:18 2011 @@ -113,7 +113,7 @@ /// immediate Thumb2 direct branch target. uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; - + /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate /// branch target. uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, @@ -508,9 +508,9 @@ for (int i = 0; i < NumOp-1; ++i) { const MCOperand &MCOp1 = MI.getOperand(i); const MCOperand &MCOp2 = MI.getOperand(i + 1); - if (MCOp1.isImm() && MCOp2.isReg() && + if (MCOp1.isImm() && MCOp2.isReg() && (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { - if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) + if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) return true; } } @@ -538,10 +538,10 @@ SmallVectorImpl &Fixups) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) { - if (HasConditionalBranch(MI)) + if (HasConditionalBranch(MI)) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_condbranch, Fixups); - return ::getBranchTargetOpValue(MI, OpIdx, + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbranch, Fixups); } @@ -553,10 +553,10 @@ SmallVectorImpl &Fixups) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) { - if (HasConditionalBranch(MI)) + if (HasConditionalBranch(MI)) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_condbranch, Fixups); - return ::getBranchTargetOpValue(MI, OpIdx, + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbranch, Fixups); } @@ -1350,7 +1350,7 @@ Size = Desc.getSize(); else llvm_unreachable("Unexpected instruction size!"); - + uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); // Thumb 32-bit wide instructions need to emit the high order halfword // first. From resistor at mac.com Tue Aug 30 17:03:20 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 22:03:20 -0000 Subject: [llvm-commits] [llvm] r138834 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110830220320.BEA5C2A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 17:03:20 2011 New Revision: 138834 URL: http://llvm.org/viewvc/llvm-project?rev=138834&view=rev Log: Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138834&r1=138833&r2=138834&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Aug 30 17:03:20 2011 @@ -484,7 +484,10 @@ uint32_t ARMMCCodeEmitter:: getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups); + return (MO.getImm() >> 1); } /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138834&r1=138833&r2=138834&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 30 17:03:20 2011 @@ -105,12 +105,15 @@ @------------------------------------------------------------------------------ b _baz beq _bar + b #1838 + b #-420 @ CHECK: b _baz @ encoding: [A,0xe0'A'] @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br @ CHECK: beq _bar @ encoding: [A,0xd0] @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc - +@ CHECK: b #1838 @ encoding: [0x97,0xe3] +@ CHECK: b #-420 @ encoding: [0x2e,0xe7] @------------------------------------------------------------------------------ @ BICS From resistor at mac.com Tue Aug 30 17:10:04 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 22:10:04 -0000 Subject: [llvm-commits] [llvm] r138835 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110830221004.1C6D02A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 17:10:03 2011 New Revision: 138835 URL: http://llvm.org/viewvc/llvm-project?rev=138835&view=rev Log: Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138835&r1=138834&r2=138835&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Aug 30 17:10:03 2011 @@ -930,7 +930,10 @@ uint32_t ARMMCCodeEmitter:: getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); + return (MO.getImm() >> 2); } /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138835&r1=138834&r2=138835&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Tue Aug 30 17:10:03 2011 @@ -224,10 +224,13 @@ @ LDR (literal) @------------------------------------------------------------------------------ ldr r1, _foo + ldr r3, #604 + ldr r3, #368 @ CHECK: ldr r1, _foo @ encoding: [A,0x49] @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp - +@ CHECK: ldr r3, #604 @ encoding: [0x97,0x4b] +@ CHECK: ldr r3, #368 @ encoding: [0x5c,0x4b] @------------------------------------------------------------------------------ @ LDR (register) From benny.kra at googlemail.com Tue Aug 30 17:10:58 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 30 Aug 2011 22:10:58 -0000 Subject: [llvm-commits] [llvm] r138836 - in /llvm/trunk: include/llvm/Object/MachOObject.h lib/Object/MachOObject.cpp tools/macho-dump/macho-dump.cpp Message-ID: <20110830221058.BF17B2A6C12C@llvm.org> Author: d0k Date: Tue Aug 30 17:10:58 2011 New Revision: 138836 URL: http://llvm.org/viewvc/llvm-project?rev=138836&view=rev Log: Teach macho-dump to dump the uleb128s referred to by linkedit_data segments. Modified: llvm/trunk/include/llvm/Object/MachOObject.h llvm/trunk/lib/Object/MachOObject.cpp llvm/trunk/tools/macho-dump/macho-dump.cpp Modified: llvm/trunk/include/llvm/Object/MachOObject.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachOObject.h?rev=138836&r1=138835&r2=138836&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachOObject.h (original) +++ llvm/trunk/include/llvm/Object/MachOObject.h Tue Aug 30 17:10:58 2011 @@ -174,6 +174,7 @@ void ReadSymbol64TableEntry( uint64_t SymbolTableOffset, unsigned Index, InMemoryStruct &Res) const; + void ReadULEB128s(uint64_t Index, SmallVectorImpl &Out) const; /// @} Modified: llvm/trunk/lib/Object/MachOObject.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObject.cpp?rev=138836&r1=138835&r2=138836&view=diff ============================================================================== --- llvm/trunk/lib/Object/MachOObject.cpp (original) +++ llvm/trunk/lib/Object/MachOObject.cpp Tue Aug 30 17:10:58 2011 @@ -9,6 +9,7 @@ #include "llvm/Object/MachOObject.h" #include "llvm/ADT/StringRef.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/Host.h" #include "llvm/Support/SwapByteOrder.h" @@ -355,6 +356,31 @@ ReadInMemoryStruct(*this, Buffer->getBuffer(), Offset, Res); } + +void MachOObject::ReadULEB128s(uint64_t Index, + SmallVectorImpl &Out) const { + const char *ptr = Buffer->getBufferStart() + Index; + uint64_t data = 0; + uint64_t delta = 0; + uint32_t shift = 0; + while (true) { + assert(ptr < Buffer->getBufferEnd() && "index out of bounds"); + assert(shift < 64 && "too big for uint64_t"); + + uint8_t byte = *ptr++; + delta |= ((byte & 0x7F) << shift); + shift += 7; + if (byte < 0x80) { + if (delta == 0) + break; + data += delta; + Out.push_back(data); + delta = 0; + shift = 0; + } + } +} + /* ** */ // Object Dumping Facilities void MachOObject::dump() const { print(dbgs()); dbgs() << '\n'; } Modified: llvm/trunk/tools/macho-dump/macho-dump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/macho-dump/macho-dump.cpp?rev=138836&r1=138835&r2=138836&view=diff ============================================================================== --- llvm/trunk/tools/macho-dump/macho-dump.cpp (original) +++ llvm/trunk/tools/macho-dump/macho-dump.cpp Tue Aug 30 17:10:58 2011 @@ -318,7 +318,16 @@ return Error("unable to read segment load command"); outs() << " ('dataoff', " << LLC->DataOffset << ")\n" - << " ('datasize', " << LLC->DataSize << ")\n"; + << " ('datasize', " << LLC->DataSize << ")\n" + << " ('_addresses', [\n"; + + SmallVector Addresses; + Obj.ReadULEB128s(LLC->DataOffset, Addresses); + for (unsigned i = 0, e = Addresses.size(); i != e; ++i) + outs() << " # Address " << i << '\n' + << " ('address', " << format("0x%x", Addresses[i]) << "),\n"; + + outs() << " ])\n"; return 0; } From resistor at mac.com Tue Aug 30 17:15:18 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 22:15:18 -0000 Subject: [llvm-commits] [llvm] r138837 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20110830221518.216B82A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 17:15:17 2011 New Revision: 138837 URL: http://llvm.org/viewvc/llvm-project?rev=138837&view=rev Log: Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138837&r1=138836&r2=138837&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Aug 30 17:15:17 2011 @@ -501,7 +501,10 @@ uint32_t ARMMCCodeEmitter:: getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); + return (MO.getImm() >> 1); } /// Return true if this branch has a non-always predication Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=138837&r1=138836&r2=138837&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Aug 30 17:15:17 2011 @@ -38,6 +38,15 @@ @ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64] @------------------------------------------------------------------------------ +@ CBZ/CBNZ + at ------------------------------------------------------------------------------ + cbnz r7, #6 + cbnz r7, #12 + +@ CHECK: cbnz r7, #6 @ encoding: [0x1f,0xb9] +@ CHECK: cbnz r7, #12 @ encoding: [0x37,0xb9] + + at ------------------------------------------------------------------------------ @ IT @------------------------------------------------------------------------------ @ Test encodings of a few full IT blocks, not just the IT instruction From resistor at mac.com Tue Aug 30 17:58:27 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 30 Aug 2011 22:58:27 -0000 Subject: [llvm-commits] [llvm] r138840 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb2.txt Message-ID: <20110830225827.630442A6C12C@llvm.org> Author: resistor Date: Tue Aug 30 17:58:27 2011 New Revision: 138840 URL: http://llvm.org/viewvc/llvm-project?rev=138840&view=rev Log: Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138840&r1=138839&r2=138840&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 30 17:58:27 2011 @@ -19,7 +19,6 @@ def it_pred : Operand { let PrintMethod = "printMandatoryPredicateOperand"; let ParserMatchClass = it_pred_asmoperand; - let DecoderMethod = "DecodeITCond"; } // IT block condition mask @@ -27,7 +26,6 @@ def it_mask : Operand { let PrintMethod = "printThumbITMask"; let ParserMatchClass = it_mask_asmoperand; - let DecoderMethod = "DecodeITMask"; } // Shifted operands. No register controlled shifts for Thumb2. @@ -3013,6 +3011,8 @@ bits<4> mask; let Inst{7-4} = cc; let Inst{3-0} = mask; + + let DecoderMethod = "DecodeIT"; } // Branch and Exchange Jazelle -- for disassembly only Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138840&r1=138839&r2=138840&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 30 17:58:27 2011 @@ -230,9 +230,7 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" @@ -480,18 +478,20 @@ // code and mask operands so that we can apply them correctly // to the subsequent instructions. if (MI.getOpcode() == ARM::t2IT) { + // (3 - the number of trailing zeros) is the number of then / else. unsigned firstcond = MI.getOperand(0).getImm(); - uint32_t mask = MI.getOperand(1).getImm(); - unsigned zeros = CountTrailingZeros_32(mask); - mask >>= zeros+1; - - for (unsigned i = 0; i < 4 - (zeros+1); ++i) { - if (firstcond ^ (mask & 1)) - ITBlock.push_back(firstcond ^ 1); + unsigned Mask = MI.getOperand(1).getImm(); + unsigned CondBit0 = Mask >> 4 & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + assert(NumTZ <= 3 && "Invalid IT mask!"); + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == CondBit0; + if (T) + ITBlock.insert(ITBlock.begin(), firstcond); else - ITBlock.push_back(firstcond); - mask >>= 1; + ITBlock.insert(ITBlock.begin(), firstcond ^ 1); } + ITBlock.push_back(firstcond); } @@ -3109,7 +3109,7 @@ } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF) { + if (Rm != 0xF) { if (Rm != 0xD) CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); else @@ -3345,26 +3345,28 @@ return S; } -static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { DecodeStatus S = Success; - if (Cond == 0xF) { - Cond = 0xE; + unsigned pred = fieldFromInstruction16(Insn, 4, 4); + // The InstPrinter needs to have the low bit of the predicate in + // the mask operand to be able to print it properly. + unsigned mask = fieldFromInstruction16(Insn, 0, 5); + + if (pred == 0xF) { + pred = 0xE; CHECK(S, Unpredictable); } - Inst.addOperand(MCOperand::CreateImm(Cond)); - return S; -} - -static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask, - uint64_t Address, const void *Decoder) { - DecodeStatus S = Success; - if (Mask == 0) { - Mask = 0x8; + if ((mask & 0xF) == 0) { + // Preserve the high bit of the mask, which is the low bit of + // the predicate. + mask &= 0x10; + mask |= 0x8; CHECK(S, Unpredictable); } - Inst.addOperand(MCOperand::CreateImm(Mask)); + + Inst.addOperand(MCOperand::CreateImm(pred)); + Inst.addOperand(MCOperand::CreateImm(mask)); return S; } - Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=138840&r1=138839&r2=138840&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Tue Aug 30 17:58:27 2011 @@ -39,3 +39,15 @@ 0x00 0xbf 0xf5 0x1b 0x11 0x1d + +# CHECK: ittee ls +# CHECK: addls r0, r1, r2 +# CHECK: nopls +# CHECK: subhi r5, r6, r7 +# CHECK: addhi r1, r2, #4 + +0x99 0xbf +0x88 0x18 +0x00 0xbf +0xf5 0x1b +0x11 0x1d From rafael.espindola at gmail.com Tue Aug 30 18:00:45 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 30 Aug 2011 19:00:45 -0400 Subject: [llvm-commits] [llvm] r138831 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll In-Reply-To: <117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com> References: <20110830211937.5D7532A6C12C@llvm.org> <117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com> Message-ID: <4E5D6B9D.7040101@gmail.com> > So this means we'll still segfault the compiler if segmented stacks are used with some darwin code? Segfault? I thought it was a fatal error from: if (!ST->isTargetLinux()) report_fatal_error("Segmented stacks supported only on linux."); If not, we do have a bug. > -eric Cheers, Rafael From rafael.espindola at gmail.com Tue Aug 30 18:03:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 30 Aug 2011 23:03:45 -0000 Subject: [llvm-commits] [llvm] r138841 - in /llvm/trunk: docs/ include/llvm/ include/llvm/Transforms/ lib/Transforms/Scalar/ test/Transforms/LoopDeletion/ test/Transforms/LoopSimplify/ test/Transforms/TailDup/ test/Transforms/TailDup/X86/ Message-ID: <20110830230346.1EA5D2A6C12C@llvm.org> Author: rafael Date: Tue Aug 30 18:03:45 2011 New Revision: 138841 URL: http://llvm.org/viewvc/llvm-project?rev=138841&view=rev Log: Remove the old tail duplication pass. It is not used and is unable to update ssa, so it has to be run really early in the pipeline. Any replacement should probably use the SSAUpdater. Removed: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp llvm/trunk/test/Transforms/TailDup/2003-06-24-Simpleloop.ll llvm/trunk/test/Transforms/TailDup/2003-07-22-InfiniteLoop.ll llvm/trunk/test/Transforms/TailDup/2003-08-23-InvalidatedPointers.ll llvm/trunk/test/Transforms/TailDup/2003-08-31-UnreachableBlocks.ll llvm/trunk/test/Transforms/TailDup/2004-04-01-DemoteRegToStack.ll llvm/trunk/test/Transforms/TailDup/2008-05-13-InfiniteLoop.ll llvm/trunk/test/Transforms/TailDup/2009-07-31-phicrash.ll llvm/trunk/test/Transforms/TailDup/MergeTest.ll llvm/trunk/test/Transforms/TailDup/PHIUpdateTest.ll llvm/trunk/test/Transforms/TailDup/X86/if-tail-dup.ll llvm/trunk/test/Transforms/TailDup/basictest.ll llvm/trunk/test/Transforms/TailDup/basictest2.ll Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Transforms/Scalar.h llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt llvm/trunk/lib/Transforms/Scalar/Scalar.cpp llvm/trunk/test/Transforms/LoopDeletion/2008-05-06-Phi.ll llvm/trunk/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Tue Aug 30 18:03:45 2011 @@ -583,6 +583,8 @@

The LowerSetJmp pass wasn't used effectively by any target and has been removed.
The old TailDup pass was not used in the standard pipeline + and was unable to update ssa form, so it has been removed.
The syntax of volatile loads and stores in IR has been changed to "load volatile"/"store volatile". The old syntax ("volatile load"/"volatile store") Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Tue Aug 30 18:03:45 2011 @@ -219,7 +219,6 @@ void initializeStripSymbolsPass(PassRegistry&); void initializeStrongPHIEliminationPass(PassRegistry&); void initializeTailCallElimPass(PassRegistry&); -void initializeTailDupPass(PassRegistry&); void initializeTargetDataPass(PassRegistry&); void initializeTargetLibraryInfoPass(PassRegistry&); void initializeTwoAddressInstructionPassPass(PassRegistry&); Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Tue Aug 30 18:03:45 2011 @@ -127,7 +127,6 @@ (void) llvm::createStripDeadDebugInfoPass(); (void) llvm::createStripDeadPrototypesPass(); (void) llvm::createTailCallEliminationPass(); - (void) llvm::createTailDuplicationPass(); (void) llvm::createJumpThreadingPass(); (void) llvm::createUnifyFunctionExitNodesPass(); (void) llvm::createInstCountPass(); Modified: llvm/trunk/include/llvm/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm/Transforms/Scalar.h Tue Aug 30 18:03:45 2011 @@ -176,13 +176,6 @@ //===----------------------------------------------------------------------===// // -// TailDuplication - Eliminate unconditional branches through controlled code -// duplication, creating simpler CFG structures. -// -FunctionPass *createTailDuplicationPass(); - -//===----------------------------------------------------------------------===// -// // JumpThreading - Thread control through mult-pred/multi-succ blocks where some // preds always go to some succ. // Modified: llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt Tue Aug 30 18:03:45 2011 @@ -29,7 +29,6 @@ SimplifyCFGPass.cpp SimplifyLibCalls.cpp Sink.cpp - TailDuplication.cpp TailRecursionElimination.cpp ) Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Tue Aug 30 18:03:45 2011 @@ -63,7 +63,6 @@ initializeCFGSimplifyPassPass(Registry); initializeSimplifyLibCallsPass(Registry); initializeSinkingPass(Registry); - initializeTailDupPass(Registry); initializeTailCallElimPass(Registry); } Removed: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp?rev=138840&view=auto ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp (removed) @@ -1,373 +0,0 @@ -//===- TailDuplication.cpp - Simplify CFG through tail duplication --------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This pass performs a limited form of tail duplication, intended to simplify -// CFGs by removing some unconditional branches. This pass is necessary to -// straighten out loops created by the C front-end, but also is capable of -// making other code nicer. After this pass is run, the CFG simplify pass -// should be run to clean up the mess. -// -// This pass could be enhanced in the future to use profile information to be -// more aggressive. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "tailduplicate" -#include "llvm/Transforms/Scalar.h" -#include "llvm/Constant.h" -#include "llvm/Function.h" -#include "llvm/Instructions.h" -#include "llvm/IntrinsicInst.h" -#include "llvm/Pass.h" -#include "llvm/Type.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/ADT/SmallPtrSet.h" -#include "llvm/Analysis/InstructionSimplify.h" -#include "llvm/Support/CFG.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Transforms/Utils/Local.h" -#include -using namespace llvm; - -STATISTIC(NumEliminated, "Number of unconditional branches eliminated"); - -static cl::opt -TailDupThreshold("taildup-threshold", - cl::desc("Max block size to tail duplicate"), - cl::init(1), cl::Hidden); - -namespace { - class TailDup : public FunctionPass { - bool runOnFunction(Function &F); - public: - static char ID; // Pass identification, replacement for typeid - TailDup() : FunctionPass(ID) { - initializeTailDupPass(*PassRegistry::getPassRegistry()); - } - - private: - inline bool shouldEliminateUnconditionalBranch(TerminatorInst *, unsigned); - inline void eliminateUnconditionalBranch(BranchInst *BI); - SmallPtrSet CycleDetector; - }; -} - -char TailDup::ID = 0; -INITIALIZE_PASS(TailDup, "tailduplicate", "Tail Duplication", false, false) - -// Public interface to the Tail Duplication pass -FunctionPass *llvm::createTailDuplicationPass() { return new TailDup(); } - -/// runOnFunction - Top level algorithm - Loop over each unconditional branch in -/// the function, eliminating it if it looks attractive enough. CycleDetector -/// prevents infinite loops by checking that we aren't redirecting a branch to -/// a place it already pointed to earlier; see PR 2323. -bool TailDup::runOnFunction(Function &F) { - bool Changed = false; - CycleDetector.clear(); - for (Function::iterator I = F.begin(), E = F.end(); I != E; ) { - if (shouldEliminateUnconditionalBranch(I->getTerminator(), - TailDupThreshold)) { - eliminateUnconditionalBranch(cast(I->getTerminator())); - Changed = true; - } else { - ++I; - CycleDetector.clear(); - } - } - return Changed; -} - -/// shouldEliminateUnconditionalBranch - Return true if this branch looks -/// attractive to eliminate. We eliminate the branch if the destination basic -/// block has <= 5 instructions in it, not counting PHI nodes. In practice, -/// since one of these is a terminator instruction, this means that we will add -/// up to 4 instructions to the new block. -/// -/// We don't count PHI nodes in the count since they will be removed when the -/// contents of the block are copied over. -/// -bool TailDup::shouldEliminateUnconditionalBranch(TerminatorInst *TI, - unsigned Threshold) { - BranchInst *BI = dyn_cast(TI); - if (!BI || !BI->isUnconditional()) return false; // Not an uncond branch! - - BasicBlock *Dest = BI->getSuccessor(0); - if (Dest == BI->getParent()) return false; // Do not loop infinitely! - - // Do not inline a block if we will just get another branch to the same block! - TerminatorInst *DTI = Dest->getTerminator(); - if (BranchInst *DBI = dyn_cast(DTI)) - if (DBI->isUnconditional() && DBI->getSuccessor(0) == Dest) - return false; // Do not loop infinitely! - - // FIXME: DemoteRegToStack cannot yet demote invoke instructions to the stack, - // because doing so would require breaking critical edges. This should be - // fixed eventually. - if (!DTI->use_empty()) - return false; - - // Do not bother with blocks with only a single predecessor: simplify - // CFG will fold these two blocks together! - pred_iterator PI = pred_begin(Dest), PE = pred_end(Dest); - ++PI; - if (PI == PE) return false; // Exactly one predecessor! - - BasicBlock::iterator I = Dest->getFirstNonPHI(); - - for (unsigned Size = 0; I != Dest->end(); ++I) { - if (Size == Threshold) return false; // The block is too large. - - // Don't tail duplicate call instructions. They are very large compared to - // other instructions. - if (isa(I) || isa(I)) return false; - - // Also alloca and malloc. - if (isa(I)) return false; - - // Some vector instructions can expand into a number of instructions. - if (isa(I) || isa(I) || - isa(I)) return false; - - // Only count instructions that are not debugger intrinsics. - if (!isa(I)) ++Size; - } - - // Do not tail duplicate a block that has thousands of successors into a block - // with a single successor if the block has many other predecessors. This can - // cause an N^2 explosion in CFG edges (and PHI node entries), as seen in - // cases that have a large number of indirect gotos. - unsigned NumSuccs = DTI->getNumSuccessors(); - if (NumSuccs > 8) { - unsigned TooMany = 128; - if (NumSuccs >= TooMany) return false; - TooMany = TooMany/NumSuccs; - for (; PI != PE; ++PI) - if (TooMany-- == 0) return false; - } - - // If this unconditional branch is a fall-through, be careful about - // tail duplicating it. In particular, we don't want to taildup it if the - // original block will still be there after taildup is completed: doing so - // would eliminate the fall-through, requiring unconditional branches. - Function::iterator DestI = Dest; - if (&*--DestI == BI->getParent()) { - // The uncond branch is a fall-through. Tail duplication of the block is - // will eliminate the fall-through-ness and end up cloning the terminator - // at the end of the Dest block. Since the original Dest block will - // continue to exist, this means that one or the other will not be able to - // fall through. One typical example that this helps with is code like: - // if (a) - // foo(); - // if (b) - // foo(); - // Cloning the 'if b' block into the end of the first foo block is messy. - - // The messy case is when the fall-through block falls through to other - // blocks. This is what we would be preventing if we cloned the block. - DestI = Dest; - if (++DestI != Dest->getParent()->end()) { - BasicBlock *DestSucc = DestI; - // If any of Dest's successors are fall-throughs, don't do this xform. - for (succ_iterator SI = succ_begin(Dest), SE = succ_end(Dest); - SI != SE; ++SI) - if (*SI == DestSucc) - return false; - } - } - - // Finally, check that we haven't redirected to this target block earlier; - // there are cases where we loop forever if we don't check this (PR 2323). - if (!CycleDetector.insert(Dest)) - return false; - - return true; -} - -/// FindObviousSharedDomOf - We know there is a branch from SrcBlock to -/// DestBlock, and that SrcBlock is not the only predecessor of DstBlock. If we -/// can find a predecessor of SrcBlock that is a dominator of both SrcBlock and -/// DstBlock, return it. -static BasicBlock *FindObviousSharedDomOf(BasicBlock *SrcBlock, - BasicBlock *DstBlock) { - // SrcBlock must have a single predecessor. - pred_iterator PI = pred_begin(SrcBlock), PE = pred_end(SrcBlock); - if (PI == PE || ++PI != PE) return 0; - - BasicBlock *SrcPred = *pred_begin(SrcBlock); - - // Look at the predecessors of DstBlock. One of them will be SrcBlock. If - // there is only one other pred, get it, otherwise we can't handle it. - PI = pred_begin(DstBlock); PE = pred_end(DstBlock); - BasicBlock *DstOtherPred = 0; - BasicBlock *P = *PI; - if (P == SrcBlock) { - if (++PI == PE) return 0; - DstOtherPred = *PI; - if (++PI != PE) return 0; - } else { - DstOtherPred = P; - if (++PI == PE || *PI != SrcBlock || ++PI != PE) return 0; - } - - // We can handle two situations here: "if then" and "if then else" blocks. An - // 'if then' situation is just where DstOtherPred == SrcPred. - if (DstOtherPred == SrcPred) - return SrcPred; - - // Check to see if we have an "if then else" situation, which means that - // DstOtherPred will have a single predecessor and it will be SrcPred. - PI = pred_begin(DstOtherPred); PE = pred_end(DstOtherPred); - if (PI != PE && *PI == SrcPred) { - if (++PI != PE) return 0; // Not a single pred. - return SrcPred; // Otherwise, it's an "if then" situation. Return the if. - } - - // Otherwise, this is something we can't handle. - return 0; -} - - -/// eliminateUnconditionalBranch - Clone the instructions from the destination -/// block into the source block, eliminating the specified unconditional branch. -/// If the destination block defines values used by successors of the dest -/// block, we may need to insert PHI nodes. -/// -void TailDup::eliminateUnconditionalBranch(BranchInst *Branch) { - BasicBlock *SourceBlock = Branch->getParent(); - BasicBlock *DestBlock = Branch->getSuccessor(0); - assert(SourceBlock != DestBlock && "Our predicate is broken!"); - - DEBUG(dbgs() << "TailDuplication[" << SourceBlock->getParent()->getName() - << "]: Eliminating branch: " << *Branch); - - // See if we can avoid duplicating code by moving it up to a dominator of both - // blocks. - if (BasicBlock *DomBlock = FindObviousSharedDomOf(SourceBlock, DestBlock)) { - DEBUG(dbgs() << "Found shared dominator: " << DomBlock->getName() << "\n"); - - // If there are non-phi instructions in DestBlock that have no operands - // defined in DestBlock, and if the instruction has no side effects, we can - // move the instruction to DomBlock instead of duplicating it. - BasicBlock::iterator BBI = DestBlock->getFirstNonPHI(); - while (!isa(BBI)) { - Instruction *I = BBI++; - - bool CanHoist = I->isSafeToSpeculativelyExecute() && - !I->mayReadFromMemory(); - if (CanHoist) { - for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) - if (Instruction *OpI = dyn_cast(I->getOperand(op))) - if (OpI->getParent() == DestBlock || - (isa(OpI) && OpI->getParent() == DomBlock)) { - CanHoist = false; - break; - } - if (CanHoist) { - // Remove from DestBlock, move right before the term in DomBlock. - DestBlock->getInstList().remove(I); - DomBlock->getInstList().insert(DomBlock->getTerminator(), I); - DEBUG(dbgs() << "Hoisted: " << *I); - } - } - } - } - - // Tail duplication can not update SSA properties correctly if the values - // defined in the duplicated tail are used outside of the tail itself. For - // this reason, we spill all values that are used outside of the tail to the - // stack. - for (BasicBlock::iterator I = DestBlock->begin(); I != DestBlock->end(); ++I) - if (I->isUsedOutsideOfBlock(DestBlock)) { - // We found a use outside of the tail. Create a new stack slot to - // break this inter-block usage pattern. - DemoteRegToStack(*I); - } - - // We are going to have to map operands from the original block B to the new - // copy of the block B'. If there are PHI nodes in the DestBlock, these PHI - // nodes also define part of this mapping. Loop over these PHI nodes, adding - // them to our mapping. - // - std::map ValueMapping; - - BasicBlock::iterator BI = DestBlock->begin(); - bool HadPHINodes = isa(BI); - for (; PHINode *PN = dyn_cast(BI); ++BI) - ValueMapping[PN] = PN->getIncomingValueForBlock(SourceBlock); - - // Clone the non-phi instructions of the dest block into the source block, - // keeping track of the mapping... - // - for (; BI != DestBlock->end(); ++BI) { - Instruction *New = BI->clone(); - New->setName(BI->getName()); - SourceBlock->getInstList().push_back(New); - ValueMapping[BI] = New; - } - - // Now that we have built the mapping information and cloned all of the - // instructions (giving us a new terminator, among other things), walk the new - // instructions, rewriting references of old instructions to use new - // instructions. - // - BI = Branch; ++BI; // Get an iterator to the first new instruction - for (; BI != SourceBlock->end(); ++BI) - for (unsigned i = 0, e = BI->getNumOperands(); i != e; ++i) { - std::map::const_iterator I = - ValueMapping.find(BI->getOperand(i)); - if (I != ValueMapping.end()) - BI->setOperand(i, I->second); - } - - // Next we check to see if any of the successors of DestBlock had PHI nodes. - // If so, we need to add entries to the PHI nodes for SourceBlock now. - for (succ_iterator SI = succ_begin(DestBlock), SE = succ_end(DestBlock); - SI != SE; ++SI) { - BasicBlock *Succ = *SI; - for (BasicBlock::iterator PNI = Succ->begin(); isa(PNI); ++PNI) { - PHINode *PN = cast(PNI); - // Ok, we have a PHI node. Figure out what the incoming value was for the - // DestBlock. - Value *IV = PN->getIncomingValueForBlock(DestBlock); - - // Remap the value if necessary... - std::map::const_iterator I = ValueMapping.find(IV); - if (I != ValueMapping.end()) - IV = I->second; - PN->addIncoming(IV, SourceBlock); - } - } - - // Next, remove the old branch instruction, and any PHI node entries that we - // had. - BI = Branch; ++BI; // Get an iterator to the first new instruction - DestBlock->removePredecessor(SourceBlock); // Remove entries in PHI nodes... - SourceBlock->getInstList().erase(Branch); // Destroy the uncond branch... - - // Final step: now that we have finished everything up, walk the cloned - // instructions one last time, constant propagating and DCE'ing them, because - // they may not be needed anymore. - // - if (HadPHINodes) { - while (BI != SourceBlock->end()) { - Instruction *Inst = BI++; - if (isInstructionTriviallyDead(Inst)) - Inst->eraseFromParent(); - else if (Value *V = SimplifyInstruction(Inst)) { - Inst->replaceAllUsesWith(V); - Inst->eraseFromParent(); - } - } - } - - ++NumEliminated; // We just killed a branch! -} Modified: llvm/trunk/test/Transforms/LoopDeletion/2008-05-06-Phi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopDeletion/2008-05-06-Phi.ll?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopDeletion/2008-05-06-Phi.ll (original) +++ llvm/trunk/test/Transforms/LoopDeletion/2008-05-06-Phi.ll Tue Aug 30 18:03:45 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -inline -tailduplicate -instcombine -jump-threading -licm -loop-unswitch -instcombine -indvars -loop-deletion -gvn -simplifycfg -verify -disable-output +; RUN: opt < %s -inline -instcombine -jump-threading -licm -loop-unswitch -instcombine -indvars -loop-deletion -gvn -simplifycfg -verify -disable-output target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin9" Modified: llvm/trunk/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll?rev=138841&r1=138840&r2=138841&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll (original) +++ llvm/trunk/test/Transforms/LoopSimplify/2003-08-15-PreheadersFail.ll Tue Aug 30 18:03:45 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -tailduplicate -instcombine -simplifycfg -licm -disable-output +; RUN: opt < %s -instcombine -simplifycfg -licm -disable-output target datalayout = "e-p:32:32" @yy_base = external global [787 x i16] ; <[787 x i16]*> [#uses=1] @yy_state_ptr = external global i32* ; [#uses=3] Removed: llvm/trunk/test/Transforms/TailDup/2003-06-24-Simpleloop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2003-06-24-Simpleloop.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2003-06-24-Simpleloop.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2003-06-24-Simpleloop.ll (removed) @@ -1,15 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define void @motion_result7() { -entry: - br label %endif -endif: ; preds = %no_exit, %entry - %i.1 = phi i32 [ %inc, %no_exit ], [ 0, %entry ] ; [#uses=1] - %inc = add i32 %i.1, 1 ; [#uses=1] - br i1 false, label %no_exit, label %UnifiedExitNode -no_exit: ; preds = %endif - br i1 false, label %UnifiedExitNode, label %endif -UnifiedExitNode: ; preds = %no_exit, %endif - ret void -} - Removed: llvm/trunk/test/Transforms/TailDup/2003-07-22-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2003-07-22-InfiniteLoop.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2003-07-22-InfiniteLoop.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2003-07-22-InfiniteLoop.ll (removed) @@ -1,11 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define i32 @sum() { -entry: - br label %loopentry -loopentry: ; preds = %loopentry, %entry - %i.0 = phi i32 [ 1, %entry ], [ %tmp.3, %loopentry ] ; [#uses=1] - %tmp.3 = add i32 %i.0, 1 ; [#uses=1] - br label %loopentry -} - Removed: llvm/trunk/test/Transforms/TailDup/2003-08-23-InvalidatedPointers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2003-08-23-InvalidatedPointers.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2003-08-23-InvalidatedPointers.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2003-08-23-InvalidatedPointers.ll (removed) @@ -1,29 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define i32 @sell_haggle() { -entry: - br i1 false, label %then.5, label %UnifiedExitNode -then.5: ; preds = %entry - br i1 false, label %loopentry.1.preheader, label %else.1 -else.1: ; preds = %then.5 - br label %loopentry.1.preheader -loopentry.1.preheader: ; preds = %else.1, %then.5 - %final_ask.0 = phi i32 [ 0, %else.1 ], [ 0, %then.5 ] ; [#uses=2] - br label %loopentry.1 -loopentry.1: ; preds = %endif.17, %loopentry.1.preheader - switch i32 0, label %UnifiedExitNode [ - i32 2, label %UnifiedExitNode - i32 1, label %endif.16 - ] -endif.16: ; preds = %loopentry.1 - br i1 false, label %then.17, label %UnifiedExitNode -then.17: ; preds = %endif.16 - br i1 false, label %then.18, label %endif.17 -then.18: ; preds = %then.17 - br i1 false, label %endif.17, label %UnifiedExitNode -endif.17: ; preds = %then.18, %then.17 - %cur_ask.3 = phi i32 [ %final_ask.0, %then.17 ], [ %final_ask.0, %then.18 ] ; [#uses=0] - br i1 false, label %loopentry.1, label %UnifiedExitNode -UnifiedExitNode: ; preds = %endif.17, %then.18, %endif.16, %loopentry.1, %loopentry.1, %entry - ret i32 0 -} Removed: llvm/trunk/test/Transforms/TailDup/2003-08-31-UnreachableBlocks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2003-08-31-UnreachableBlocks.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2003-08-31-UnreachableBlocks.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2003-08-31-UnreachableBlocks.ll (removed) @@ -1,17 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define i32 @foo() { -entry: - br label %return.i -after_ret.i: ; No predecessors! - br label %return.i -return.i: ; preds = %after_ret.i, %entry - %tmp.3 = ptrtoint i32* null to i32 ; [#uses=1] - br label %return.i1 -after_ret.i1: ; No predecessors! - br label %return.i1 -return.i1: ; preds = %after_ret.i1, %return.i - %tmp.8 = sub i32 %tmp.3, 0 ; [#uses=0] - ret i32 0 -} - Removed: llvm/trunk/test/Transforms/TailDup/2004-04-01-DemoteRegToStack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2004-04-01-DemoteRegToStack.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2004-04-01-DemoteRegToStack.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2004-04-01-DemoteRegToStack.ll (removed) @@ -1,20 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define void @interpret() { -entry: - br label %retry -retry: ; preds = %endif.4, %entry - %tmp.8 = call i32 @interp( ) ; [#uses=3] - switch i32 0, label %endif.4 [ - i32 -25, label %return - i32 -16, label %return - ] -endif.4: ; preds = %retry - br i1 false, label %return, label %retry -return: ; preds = %endif.4, %retry, %retry - %result.0 = phi i32 [ %tmp.8, %retry ], [ %tmp.8, %retry ], [ %tmp.8, %endif.4 ] ; [#uses=0] - ret void -} - -declare i32 @interp() - Removed: llvm/trunk/test/Transforms/TailDup/2008-05-13-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2008-05-13-InfiniteLoop.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2008-05-13-InfiniteLoop.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2008-05-13-InfiniteLoop.ll (removed) @@ -1,26 +0,0 @@ -; RUN: opt < %s -tailduplicate | llc -; PR2323 - -define i32 @func_27(i32 %p_28) nounwind { -entry: - %tmp125 = trunc i32 %p_28 to i8 ; [#uses=1] - %tmp5.i = icmp eq i8 %tmp125, 0 ; [#uses=1] - br i1 %tmp5.i, label %bb8.i, label %bb.i - -bb.i: ; preds = %entry - br label %bb39.i - -bb8.i: ; preds = %entry - br label %bb11.i - -bb11.i: ; preds = %bb39.i, %bb8.i - %tmp126 = trunc i32 %p_28 to i8 ; [#uses=1] - br label %bb39.i - -bb39.i: ; preds = %bb11.i, %bb.i - %tmp127 = trunc i32 %p_28 to i8 ; [#uses=1] - br label %bb11.i - -func_29.exit: ; No predecessors! - ret i32 undef -} Removed: llvm/trunk/test/Transforms/TailDup/2009-07-31-phicrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2009-07-31-phicrash.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2009-07-31-phicrash.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2009-07-31-phicrash.ll (removed) @@ -1,14 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output -; PR4662 - -define void @a() { -BB: - br label %BB6 - -BB6: - %tmp9 = phi i64 [ 0, %BB ], [ 5, %BB34 ] - br label %BB34 - -BB34: - br label %BB6 -} Removed: llvm/trunk/test/Transforms/TailDup/MergeTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/MergeTest.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/MergeTest.ll (original) +++ llvm/trunk/test/Transforms/TailDup/MergeTest.ll (removed) @@ -1,27 +0,0 @@ -; RUN: opt < %s -tailduplicate -taildup-threshold=2 -S | grep add | not grep uses=1 - -define i32 @test1(i1 %C, i32 %A, i32* %P) { -entry: - br i1 %C, label %L1, label %L2 -L1: ; preds = %entry - store i32 1, i32* %P - br label %L2 -L2: ; preds = %L1, %entry - %X = add i32 %A, 17 ; [#uses=1] - ret i32 %X -} - -define i32 @test2(i1 %C, i32 %A, i32* %P) { -entry: - br i1 %C, label %L1, label %L2 -L1: ; preds = %entry - store i32 1, i32* %P - br label %L3 -L2: ; preds = %entry - store i32 7, i32* %P - br label %L3 -L3: ; preds = %L2, %L1 - %X = add i32 %A, 17 ; [#uses=1] - ret i32 %X -} - Removed: llvm/trunk/test/Transforms/TailDup/PHIUpdateTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/PHIUpdateTest.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/PHIUpdateTest.ll (original) +++ llvm/trunk/test/Transforms/TailDup/PHIUpdateTest.ll (removed) @@ -1,16 +0,0 @@ -; This test checks to make sure phi nodes are updated properly -; -; RUN: opt < %s -tailduplicate -disable-output - -define i32 @test(i1 %c, i32 %X, i32 %Y) { - br label %L -L: ; preds = %F, %0 - %A = add i32 %X, %Y ; [#uses=1] - br i1 %c, label %T, label %F -F: ; preds = %L - br i1 %c, label %L, label %T -T: ; preds = %F, %L - %V = phi i32 [ %A, %L ], [ 0, %F ] ; [#uses=1] - ret i32 %V -} - Removed: llvm/trunk/test/Transforms/TailDup/X86/if-tail-dup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/X86/if-tail-dup.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/X86/if-tail-dup.ll (original) +++ llvm/trunk/test/Transforms/TailDup/X86/if-tail-dup.ll (removed) @@ -1,49 +0,0 @@ -; RUN: opt < %s -tailduplicate | \ -; RUN: llc -march=x86 -o %t -; RUN: grep {\\\} %t -; RUN: not grep jmp %t -; END. -; This should have no unconditional jumps in it. The C source is: - -;void foo(int c, int* P) { -; if (c & 1) P[0] = 1; -; if (c & 2) P[1] = 1; -; if (c & 4) P[2] = 1; -; if (c & 8) P[3] = 1; -;} - -define void @foo(i32 %c, i32* %P) { -entry: - %tmp1 = and i32 %c, 1 ; [#uses=1] - %tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; [#uses=1] - br i1 %tmp1.upgrd.1, label %cond_next, label %cond_true -cond_true: ; preds = %entry - store i32 1, i32* %P - br label %cond_next -cond_next: ; preds = %cond_true, %entry - %tmp5 = and i32 %c, 2 ; [#uses=1] - %tmp5.upgrd.2 = icmp eq i32 %tmp5, 0 ; [#uses=1] - br i1 %tmp5.upgrd.2, label %cond_next10, label %cond_true6 -cond_true6: ; preds = %cond_next - %tmp8 = getelementptr i32* %P, i32 1 ; [#uses=1] - store i32 1, i32* %tmp8 - br label %cond_next10 -cond_next10: ; preds = %cond_true6, %cond_next - %tmp13 = and i32 %c, 4 ; [#uses=1] - %tmp13.upgrd.3 = icmp eq i32 %tmp13, 0 ; [#uses=1] - br i1 %tmp13.upgrd.3, label %cond_next18, label %cond_true14 -cond_true14: ; preds = %cond_next10 - %tmp16 = getelementptr i32* %P, i32 2 ; [#uses=1] - store i32 1, i32* %tmp16 - br label %cond_next18 -cond_next18: ; preds = %cond_true14, %cond_next10 - %tmp21 = and i32 %c, 8 ; [#uses=1] - %tmp21.upgrd.4 = icmp eq i32 %tmp21, 0 ; [#uses=1] - br i1 %tmp21.upgrd.4, label %return, label %cond_true22 -cond_true22: ; preds = %cond_next18 - %tmp24 = getelementptr i32* %P, i32 3 ; [#uses=1] - store i32 1, i32* %tmp24 - ret void -return: ; preds = %cond_next18 - ret void -} Removed: llvm/trunk/test/Transforms/TailDup/basictest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/basictest.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/basictest.ll (original) +++ llvm/trunk/test/Transforms/TailDup/basictest.ll (removed) @@ -1,20 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -declare void @__main() - -define i32 @main() { -entry: - call void @__main( ) - br label %loopentry -loopentry: ; preds = %no_exit, %entry - %i.0 = phi i32 [ %inc, %no_exit ], [ 0, %entry ] ; [#uses=3] - %tmp.1 = icmp sle i32 %i.0, 99 ; [#uses=1] - br i1 %tmp.1, label %no_exit, label %return -no_exit: ; preds = %loopentry - %tmp.51 = call i32 @main( ) ; [#uses=0] - %inc = add i32 %i.0, 1 ; [#uses=1] - br label %loopentry -return: ; preds = %loopentry - ret i32 %i.0 -} - Removed: llvm/trunk/test/Transforms/TailDup/basictest2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/basictest2.ll?rev=138840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailDup/basictest2.ll (original) +++ llvm/trunk/test/Transforms/TailDup/basictest2.ll (removed) @@ -1,15 +0,0 @@ -; RUN: opt < %s -tailduplicate -disable-output - -define void @ab() { -entry: - br label %loopentry.5 -loopentry.5: ; preds = %no_exit.5, %entry - %poscnt.1 = phi i64 [ 0, %entry ], [ %tmp.289, %no_exit.5 ] ; [#uses=1] - %tmp.289 = ashr i64 %poscnt.1, 1 ; [#uses=1] - br i1 false, label %no_exit.5, label %loopexit.5 -no_exit.5: ; preds = %loopentry.5 - br label %loopentry.5 -loopexit.5: ; preds = %loopentry.5 - ret void -} - From clattner at apple.com Tue Aug 30 18:08:14 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 30 Aug 2011 16:08:14 -0700 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> References: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Message-ID: On Aug 29, 2011, at 12:18 PM, David Greene wrote: > > Emit a repeated sequence of bytes using .zero. This saves an enormous > amount of asm file space for certain programs. > --- > > Here's another updated version of the patch, including testcase. Looks good with a few changes: + if ((Value & 0xffull) != Byte) return -1; Please use a cast instead of ffull + for (int i = 1, e = CA->getNumOperands(); i != e; ++i) { Please declare 'i' as 'unsigned' instead of 'int'. + at x = global [500 x i64] zeroinitializer, align 64 ; <[500 x i64]*> +; CHECK: .zero 4000 Please add a "CHECK: x:" line above this, similarly for y. Please remove the main function from the testcase. Please commit with these changes, thanks David. -Chris From atrick at apple.com Tue Aug 30 18:10:21 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 30 Aug 2011 16:10:21 -0700 Subject: [llvm-commits] [llvm] r138831 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll In-Reply-To: <4E5D6B9D.7040101@gmail.com> References: <20110830211937.5D7532A6C12C@llvm.org> <117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com> <4E5D6B9D.7040101@gmail.com> Message-ID: On Aug 30, 2011, at 4:00 PM, Rafael ?vila de Esp?ndola wrote: >> So this means we'll still segfault the compiler if segmented stacks are used with some darwin code? > > Segfault? I thought it was a fatal error from: > > if (!ST->isTargetLinux()) > report_fatal_error("Segmented stacks supported only on linux."); > > If not, we do have a bug. > >> -eric > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits The first darwin failure after r138821 was: Assertion failed: (!Subtarget->isTargetEnvMacho()), function LowerDYNAMIC_STACKALLOC, file .../llvm/lib/Target/X86/X86ISelLowering.cpp, line 8853. Not sure what happens in the release build. -Andy From echristo at apple.com Tue Aug 30 18:10:49 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 16:10:49 -0700 Subject: [llvm-commits] [llvm] r138831 - /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll In-Reply-To: <4E5D6B9D.7040101@gmail.com> References: <20110830211937.5D7532A6C12C@llvm.org> <117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com> <4E5D6B9D.7040101@gmail.com> Message-ID: <80B074E7-2906-45D0-BA09-2043BA10FE11@apple.com> On Aug 30, 2011, at 4:00 PM, Rafael ?vila de Esp?ndola wrote: >> So this means we'll still segfault the compiler if segmented stacks are used with some darwin code? > > Segfault? I thought it was a fatal error from: > > if (!ST->isTargetLinux()) > report_fatal_error("Segmented stacks supported only on linux."); > > If not, we do have a bug. Sorry, assertion as Andy just followed up :) -eric From echristo at apple.com Tue Aug 30 18:59:35 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 16:59:35 -0700 Subject: [llvm-commits] PATCH: pruning llvm w/ config flags --enable-target-oses=os1, os2 similar to --enable-target=arch1, arch2. In-Reply-To: References: Message-ID: <558928B5-547F-46F8-8F27-CEEBA86EE2EA@apple.com> On Aug 29, 2011, at 4:58 PM, Jan Voung wrote: > Ping. > > - Is this approach acceptable? > - I guess it is hard to test if this has any effect / depends on the compiler. I'm not really wild about this approach, no. I'd prefer separating out the targets from each other and then conditionally compiling in support rather than relying on DCE and LTO to decide whether or not the code should be there. I'm open to other ideas/discussion on it though. > - Is trimming the size of the llvm binaries (via config flags) useful to others? > - Other examples: > - make "include/llvm/Intrinsics.td" not #include intrinsincs for targets that were not enabled through "--enable-target" > - config flags to avoid building unused register allocators, other passes This is quite useful in general, I'm just not a fan of the current method. The cleanups that you have are definitely useful patches and I hope you'll submit those separately. Thanks! -eric From benny.kra at googlemail.com Tue Aug 30 19:02:59 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 31 Aug 2011 00:02:59 -0000 Subject: [llvm-commits] [llvm] r138843 - /llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Message-ID: <20110831000259.403512A6C12C@llvm.org> Author: d0k Date: Tue Aug 30 19:02:59 2011 New Revision: 138843 URL: http://llvm.org/viewvc/llvm-project?rev=138843&view=rev Log: Fix test typo. Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=138843&r1=138842&r2=138843&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Tue Aug 30 19:02:59 2011 @@ -18,7 +18,7 @@ ; CHECK-NOT: [[A3]] ; CHECK: 5th=[[A5:%...]] ; CHECK-NOT: [[A1]] -; CHECK-NOT; [[A5]] +; CHECK-NOT: [[A5]] ; CHECK: =4th ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th. From eli.friedman at gmail.com Tue Aug 30 19:31:30 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 00:31:30 -0000 Subject: [llvm-commits] [llvm] r138845 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-64bit.ll Message-ID: <20110831003130.3BACA2A6C12C@llvm.org> Author: efriedma Date: Tue Aug 30 19:31:29 2011 New Revision: 138845 URL: http://llvm.org/viewvc/llvm-project?rev=138845&view=rev Log: Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. Added: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=138845&r1=138844&r2=138845&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 30 19:31:29 2011 @@ -254,6 +254,8 @@ SDNode *SelectConcatVector(SDNode *N); + SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, @@ -2309,6 +2311,21 @@ return PairDRegs(VT, N->getOperand(0), N->getOperand(1)); } +SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { + SDValue Chain = Node->getOperand(0); + SDValue In1 = Node->getOperand(1); + SDValue In2L = Node->getOperand(2); + SDValue In2H = Node->getOperand(3); + MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); + MemOp[0] = cast(Node)->getMemOperand(); + const SDValue Ops[] = { In1, In2L, In2H, Chain}; + SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), + MVT::i32, MVT::i32, MVT::Other, Ops, + array_lengthof(Ops)); + cast(ResNode)->setMemRefs(MemOp, MemOp + 1); + return ResNode; +} + SDNode *ARMDAGToDAGISel::Select(SDNode *N) { DebugLoc dl = N->getDebugLoc(); @@ -3089,6 +3106,21 @@ case ISD::CONCAT_VECTORS: return SelectConcatVector(N); + + case ARMISD::ATOMOR64_DAG: + return SelectAtomic64(N, ARM::ATOMOR6432); + case ARMISD::ATOMXOR64_DAG: + return SelectAtomic64(N, ARM::ATOMXOR6432); + case ARMISD::ATOMADD64_DAG: + return SelectAtomic64(N, ARM::ATOMADD6432); + case ARMISD::ATOMSUB64_DAG: + return SelectAtomic64(N, ARM::ATOMSUB6432); + case ARMISD::ATOMNAND64_DAG: + return SelectAtomic64(N, ARM::ATOMNAND6432); + case ARMISD::ATOMAND64_DAG: + return SelectAtomic64(N, ARM::ATOMAND6432); + case ARMISD::ATOMSWAP64_DAG: + return SelectAtomic64(N, ARM::ATOMSWAP6432); } return SelectCode(N); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138845&r1=138844&r2=138845&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 30 19:31:29 2011 @@ -611,6 +611,13 @@ // normally. setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + // Custom lowering for 64-bit ops + setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. setInsertFencesForAtomic(true); } else { @@ -4846,6 +4853,29 @@ Op.getOperand(1), Op.getOperand(2)); } +static void +ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl& Results, + SelectionDAG &DAG, unsigned NewOp) { + EVT T = Node->getValueType(0); + DebugLoc dl = Node->getDebugLoc(); + assert (T == MVT::i64 && "Only know how to expand i64 atomics"); + + SDValue Chain = Node->getOperand(0); + SDValue In1 = Node->getOperand(1); + SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(2), DAG.getIntPtrConstant(0)); + SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(2), DAG.getIntPtrConstant(1)); + SDValue Ops[] = { Chain, In1, In2L, In2H }; + SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); + SDValue Result = + DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, + cast(Node)->getMemOperand()); + SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); + Results.push_back(Result.getValue(2)); +} + SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { default: llvm_unreachable("Don't know how to custom lower this!"); @@ -4918,6 +4948,29 @@ case ISD::SRA: Res = Expand64BitShift(N, DAG, Subtarget); break; + case ISD::ATOMIC_LOAD_ADD: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); + return; + case ISD::ATOMIC_LOAD_AND: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); + return; + case ISD::ATOMIC_LOAD_NAND: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); + return; + case ISD::ATOMIC_LOAD_OR: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); + return; + case ISD::ATOMIC_LOAD_SUB: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); + return; + case ISD::ATOMIC_LOAD_XOR: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); + return; + case ISD::ATOMIC_SWAP: + ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); + return; + //case ISD::ATOMIC_CMP_SWAP: + // ReplaceATOMIC_CMPXCHG_64(N, Results, DAG); } if (Res.getNode()) Results.push_back(Res); @@ -5237,6 +5290,113 @@ return BB; } +MachineBasicBlock * +ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, + unsigned Op1, unsigned Op2, + bool NeedsCarry) const { + // This also handles ATOMIC_SWAP, indicated by Op1==0. + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction *MF = BB->getParent(); + MachineFunction::iterator It = BB; + ++It; + + unsigned destlo = MI->getOperand(0).getReg(); + unsigned desthi = MI->getOperand(1).getReg(); + unsigned ptr = MI->getOperand(2).getReg(); + unsigned vallo = MI->getOperand(3).getReg(); + unsigned valhi = MI->getOperand(4).getReg(); + DebugLoc dl = MI->getDebugLoc(); + bool isThumb2 = Subtarget->isThumb2(); + + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + if (isThumb2) { + MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); + MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); + MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); + } + + unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; + unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; + + MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MF->insert(It, loopMBB); + MF->insert(It, exitMBB); + + // Transfer the remainder of BB and its successor edges to exitMBB. + exitMBB->splice(exitMBB->begin(), BB, + llvm::next(MachineBasicBlock::iterator(MI)), + BB->end()); + exitMBB->transferSuccessorsAndUpdatePHIs(BB); + + TargetRegisterClass *TRC = + isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; + unsigned storesuccess = MRI.createVirtualRegister(TRC); + + // thisMBB: + // ... + // fallthrough --> loopMBB + BB->addSuccessor(loopMBB); + + // loopMBB: + // ldrexd r2, r3, ptr + // r0, r2, incr + // r1, r3, incr + // strexd storesuccess, r0, r1, ptr + // cmp storesuccess, #0 + // bne- loopMBB + // fallthrough --> exitMBB + // + // Note that the registers are explicitly specified because there is not any + // way to force the register allocator to allocate a register pair. + // + // FIXME: The hardcoded registers are not necessary for Thumb2, but we + // need to properly enforce the restriction that the two output registers + // for ldrexd must be different. + BB = loopMBB; + // Load + AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) + .addReg(ARM::R2, RegState::Define) + .addReg(ARM::R3, RegState::Define).addReg(ptr)); + // Copy r2/r3 into dest. (This copy will normally be coalesced.) + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); + if (Op1) { + // Perform binary operation + AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) + .addReg(destlo).addReg(vallo)) + .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); + AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) + .addReg(desthi).addReg(valhi)).addReg(0); + } else { + // Copy to physregs for strexd + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); + } + + // Store + AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) + .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); + // Cmp+jump + AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) + .addReg(storesuccess).addImm(0)); + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) + .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); + + BB->addSuccessor(loopMBB); + BB->addSuccessor(exitMBB); + + // exitMBB: + // ... + BB = exitMBB; + + MI->eraseFromParent(); // The instruction is gone now. + + return BB; +} + static MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), @@ -5374,6 +5534,25 @@ case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); + + case ARM::ATOMADD6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, + isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, true); + case ARM::ATOMSUB6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, + isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, true); + case ARM::ATOMOR6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, + isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, false); + case ARM::ATOMXOR6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, + isThumb2 ? ARM::t2EORrr : ARM::EORrr, false); + case ARM::ATOMAND6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, + isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, false); + case ARM::ATOMSWAP6432: + return EmitAtomicBinary64(MI, BB, 0, 0, false); + case ARM::tMOVCCr_pseudo: { // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=138845&r1=138844&r2=138845&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Aug 30 19:31:29 2011 @@ -211,7 +211,17 @@ VST4_UPD, VST2LN_UPD, VST3LN_UPD, - VST4LN_UPD + VST4LN_UPD, + + // 64-bit atomic ops (value split into two registers) + ATOMADD64_DAG, + ATOMSUB64_DAG, + ATOMOR64_DAG, + ATOMXOR64_DAG, + ATOMAND64_DAG, + ATOMNAND64_DAG, + ATOMSWAP64_DAG, + ATOMCMPXCHG64_DAG }; } @@ -493,6 +503,11 @@ MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode) const; + MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, + MachineBasicBlock *BB, + unsigned Op1, + unsigned Op2, + bool NeedsCarry) const; MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138845&r1=138844&r2=138845&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 30 19:31:29 2011 @@ -69,6 +69,8 @@ def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDTARMatomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, + SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, [SDTCisSameAs<0, 2>, @@ -162,6 +164,28 @@ def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; +def ARMAtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def ARMAtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTARMatomicBinary, + [SDNPHasChain, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; + //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // @@ -1609,6 +1633,32 @@ [(ARMcallseq_start timm:$amt)]>; } +// Atomic pseudo-insts which will be lowered to ldrexd/strexd loops. +// (These psuedos use a hand-written selection code). +let usesCustomInserter = 1, Uses = [CPSR] in { +def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$src1, GPR:$src2), + NoItinerary, []>; +} + def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>, Requires<[IsARM, HasV6T2]> { let Inst{27-16} = 0b001100100000; Added: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll?rev=138845&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll (added) +++ llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Tue Aug 30 19:31:29 2011 @@ -0,0 +1,83 @@ +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s + +define i64 @test1(i64* %ptr, i64 %val) { +; CHECK: test1 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: adds r0, r2 +; CHECK: adc r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw add i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test2(i64* %ptr, i64 %val) { +; CHECK: test2 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: subs r0, r2 +; CHECK: sbc r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw sub i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test3(i64* %ptr, i64 %val) { +; CHECK: test3 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: and r0, r2 +; CHECK: and r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw and i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test4(i64* %ptr, i64 %val) { +; CHECK: test4 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: orr r0, r2 +; CHECK: orr r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw or i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test5(i64* %ptr, i64 %val) { +; CHECK: test5 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: eor r0, r2 +; CHECK: eor r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw xor i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test6(i64* %ptr, i64 %val) { +; CHECK: test6 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst + ret i64 %r +} \ No newline at end of file From eli.friedman at gmail.com Tue Aug 30 19:41:05 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 00:41:05 -0000 Subject: [llvm-commits] [llvm] r138846 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-64bit.ll Message-ID: <20110831004105.E49482A6C12C@llvm.org> Author: efriedma Date: Tue Aug 30 19:41:05 2011 New Revision: 138846 URL: http://llvm.org/viewvc/llvm-project?rev=138846&view=rev Log: Some minor cleanups for r138845. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138846&r1=138845&r2=138846&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 30 19:41:05 2011 @@ -164,28 +164,6 @@ def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; -def ARMAtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def ARMAtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTARMatomicBinary, - [SDNPHasChain, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; - //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // Modified: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll?rev=138846&r1=138845&r2=138846&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Tue Aug 30 19:41:05 2011 @@ -80,4 +80,4 @@ ; CHECK: dmb ish %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst ret i64 %r -} \ No newline at end of file +} From Micah.Villmow at amd.com Tue Aug 30 20:45:09 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Tue, 30 Aug 2011 20:45:09 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References: <4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: Here is a combined patch. > -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Tuesday, August 30, 2011 1:09 PM > To: Villmow, Micah > Cc: Tobias Grosser; llvm-commits > Subject: Re: [llvm-commits] Patch to add support for > WidenVecRes_MERGE_VALUES > > On Tue, Aug 30, 2011 at 1:06 PM, Villmow, Micah > wrote: > > Eli, > > ?So for the other cases, it would just be call DecomposeMERGE_VALUES > and then call the correct > > legalization function on the return value, correct? > > Yes. > > > I'll send a second patch with those later. > > Great, thanks. > > -Eli > > > Micah > > > >> -----Original Message----- > >> From: Eli Friedman [mailto:eli.friedman at gmail.com] > >> Sent: Tuesday, August 30, 2011 12:56 PM > >> To: Tobias Grosser > >> Cc: Villmow, Micah; llvm-commits > >> Subject: Re: [llvm-commits] Patch to add support for > >> WidenVecRes_MERGE_VALUES > >> > >> On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser > >> wrote: > >> > On 08/30/2011 01:04 PM, Villmow, Micah wrote: > >> >> > >> >> Thanks for the feedback, new revision attached. > >> > > >> > There seems one unneeded white space change. (Can be fixed on > commit) > >> > > >> >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > >> >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool > >> isSigned, > >> >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); > >> >> + > >> >> ? ? ? ?std::pair > >> ExpandChainLibCall(RTLIB::Libcall > >> > > >> > Otherwise, it looks good. Let's see if Eli has any additional > >> comments. > >> > >> Looks fine. > >> > >> Note that it would be nice to make sure we implement MERGE_VALUES > for > >> all the other cases in type legalization... (integer promotion, > vector > >> scalarization, etc.) > >> > >> -Eli > > > > > > -------------- next part -------------- A non-text attachment was scrubbed... Name: LegalizeMERGE_VALUES.patch Type: application/octet-stream Size: 12022 bytes Desc: LegalizeMERGE_VALUES.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/39a5c1a1/attachment.obj From evan.cheng at apple.com Tue Aug 30 21:05:24 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 31 Aug 2011 02:05:24 -0000 Subject: [llvm-commits] [llvm] r138848 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-38.ll Message-ID: <20110831020525.21AB02A6C12C@llvm.org> Author: evancheng Date: Tue Aug 30 21:05:24 2011 New Revision: 138848 URL: http://llvm.org/viewvc/llvm-project?rev=138848&view=rev Log: Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138848&r1=138847&r2=138848&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 21:05:24 2011 @@ -6236,8 +6236,11 @@ if (HasSSE2 && VT == MVT::v2f64) return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); - // v4f32 or v4i32 - return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); + // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) + return DAG.getNode(ISD::BITCAST, dl, VT, + getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, + DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), + DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); } static Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138848&r1=138847&r2=138848&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 30 21:05:24 2011 @@ -691,11 +691,12 @@ // MOVHPS patterns def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVHPSrm VR128:$src1, addr:$src2)>; def : Pat<(X86Movlhps VR128:$src1, - (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (bc_v4f32 (v2i64 (X86vzload addr:$src2)))), (MOVHPSrm VR128:$src1, addr:$src2)>; // MOVLHPS patterns Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll?rev=138848&r1=138847&r2=138848&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Tue Aug 30 21:05:24 2011 @@ -24,3 +24,22 @@ ret <2 x i64> %shuffle } +; rdar://10050549 +%struct.Float2 = type { float, float } + +define <4 x float> @loadhpi(%struct.Float2* %vPtr, <4 x float> %vecin1) nounwind readonly ssp { +entry: +; CHECK: loadhpi +; CHECK-NOT: movq +; CHECK: movhps ( + %tmp1 = bitcast %struct.Float2* %vPtr to <1 x i64>* + %addptr7 = getelementptr inbounds <1 x i64>* %tmp1, i64 0 + %tmp2 = bitcast <1 x i64>* %addptr7 to float* + %tmp3 = load float* %tmp2, align 4 + %vec = insertelement <4 x float> undef, float %tmp3, i32 0 + %addptr.i12 = getelementptr inbounds float* %tmp2, i64 1 + %tmp4 = load float* %addptr.i12, align 4 + %vecin2 = insertelement <4 x float> %vec, float %tmp4, i32 1 + %shuffle = shufflevector <4 x float> %vecin1, <4 x float> %vecin2, <4 x i32> + ret <4 x float> %shuffle +} From sanjoy at playingwithpointers.com Tue Aug 30 22:00:27 2011 From: sanjoy at playingwithpointers.com (Sanjoy Das) Date: Wed, 31 Aug 2011 08:30:27 +0530 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: References: <20110830194704.AA1372A6C12C@llvm.org> Message-ID: <4E5DA3CB.6020604@playingwithpointers.com> > This set of conditionals needs to be taken out into a field and shot in the head. Like this? Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: p.patch Type: text/x-diff Size: 1297 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110831/6b59b1f1/attachment.bin From echristo at apple.com Tue Aug 30 21:58:34 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 19:58:34 -0700 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <4E5DA3CB.6020604@playingwithpointers.com> References: <20110830194704.AA1372A6C12C@llvm.org> <4E5DA3CB.6020604@playingwithpointers.com> Message-ID: <768AC3F5-AEC7-47EB-A3F0-7F1B7D5458A1@apple.com> On Aug 30, 2011, at 8:00 PM, Sanjoy Das wrote: >> This set of conditionals needs to be taken out into a field and shot in the head. > > Like this? Much nicer. Do you have commit access? -eric From sanjoy at playingwithpointers.com Tue Aug 30 22:04:22 2011 From: sanjoy at playingwithpointers.com (Sanjoy Das) Date: Wed, 31 Aug 2011 08:34:22 +0530 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <768AC3F5-AEC7-47EB-A3F0-7F1B7D5458A1@apple.com> References: <20110830194704.AA1372A6C12C@llvm.org> <4E5DA3CB.6020604@playingwithpointers.com> <768AC3F5-AEC7-47EB-A3F0-7F1B7D5458A1@apple.com> Message-ID: <4E5DA4B6.9000406@playingwithpointers.com> > Much nicer. Do you have commit access? No. -- Sanjoy Das http://playingwithpointers.com From bruno.cardoso at gmail.com Tue Aug 30 22:04:09 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 03:04:09 -0000 Subject: [llvm-commits] [llvm] r138849 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrInfo.cpp Message-ID: <20110831030410.214A22A6C12C@llvm.org> Author: bruno Date: Tue Aug 30 22:04:09 2011 New Revision: 138849 URL: http://llvm.org/viewvc/llvm-project?rev=138849&view=rev Log: Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, whenever AVX is enabled. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138849&r1=138848&r2=138849&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 22:04:09 2011 @@ -11215,7 +11215,9 @@ if (!(Op.isReg() && Op.isImplicit())) MIB.addOperand(Op); } - BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) + BuildMI(*BB, MI, dl, + TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), + MI->getOperand(0).getReg()) .addReg(X86::XMM0); MI->eraseFromParent(); @@ -11570,6 +11572,7 @@ MBB->addSuccessor(EndMBB); } + unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; // In the XMM save block, save all the XMM argument registers. for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; @@ -11578,7 +11581,7 @@ MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), MachineMemOperand::MOStore, /*Size=*/16, /*Align=*/16); - BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) + BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) .addFrameIndex(RegSaveFrameIndex) .addImm(/*Scale=*/1) .addReg(/*IndexReg=*/0) Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=138849&r1=138848&r2=138849&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Aug 30 22:04:09 2011 @@ -1959,7 +1959,8 @@ else Opc = X86::MOV8rr; } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) - Opc = X86::MOVAPSrr; + Opc = TM.getSubtarget().hasAVX() ? + X86::VMOVAPSrr : X86::MOVAPSrr; else if (X86::VR256RegClass.contains(DestReg, SrcReg)) Opc = X86::VMOVAPSYrr; else if (X86::VR64RegClass.contains(DestReg, SrcReg)) @@ -2044,13 +2045,19 @@ case 10: assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); return load ? X86::LD_Fp80m : X86::ST_FpP80m; - case 16: + case 16: { assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); + bool HasAVX = TM.getSubtarget().hasAVX(); // If stack is realigned we can use aligned stores. if (isStackAligned) - return load ? X86::MOVAPSrm : X86::MOVAPSmr; + return load ? + (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : + (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); else - return load ? X86::MOVUPSrm : X86::MOVUPSmr; + return load ? + (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : + (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); + } case 32: assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); // If stack is realigned we can use aligned stores. From bruno.cardoso at gmail.com Tue Aug 30 22:04:14 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 03:04:14 -0000 Subject: [llvm-commits] [llvm] r138850 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110831030414.6BEC92A6C12D@llvm.org> Author: bruno Date: Tue Aug 30 22:04:14 2011 New Revision: 138850 URL: http://llvm.org/viewvc/llvm-project?rev=138850&view=rev Log: Remove unnecessary AVX checks Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138850&r1=138849&r2=138850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 30 22:04:14 2011 @@ -3232,14 +3232,14 @@ def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)), (i8 imm:$imm))), - (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>; + (VPSHUFDmi addr:$src1, imm:$imm)>; def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)), (i8 imm:$imm))), (VPSHUFDmi addr:$src1, imm:$imm)>; def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; + (VPSHUFDri VR128:$src1, imm:$imm)>; def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))), - (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>; + (VPSHUFDri VR128:$src1, imm:$imm)>; def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), (VPSHUFHWri VR128:$src, imm:$imm)>; def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), From bruno.cardoso at gmail.com Tue Aug 30 22:04:20 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 03:04:20 -0000 Subject: [llvm-commits] [llvm] r138851 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll Message-ID: <20110831030420.B79302A6C12C@llvm.org> Author: bruno Date: Tue Aug 30 22:04:20 2011 New Revision: 138851 URL: http://llvm.org/viewvc/llvm-project?rev=138851&view=rev Log: - Move all MOVSS and MOVSD patterns close to their definitions - Duplicate some store patterns to their AVX forms! - Catched a bug while restricting the patterns subtarget, fix it and update a testcase to check it properly Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138851&r1=138850&r2=138851&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 22:04:20 2011 @@ -6319,11 +6319,11 @@ // this is horrible, but will stay like this until we move all shuffle // matching to x86 specific nodes. Note that for the 1st condition all // types are matched with movsd. - if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) - return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); - else if (HasSSE2) + if (HasSSE2) { + if (NumElems == 2) + return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); - + } assert(VT != MVT::v4i32 && "unsupported shuffle type"); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138851&r1=138850&r2=138851&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 30 22:04:20 2011 @@ -295,7 +295,13 @@ (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; //===----------------------------------------------------------------------===// -// SSE 1 & 2 - Move Instructions +// SSE 1 & 2 - Move FP Scalar Instructions +// +// Move Instructions. Register-to-register movss/movsd is not used for FR32/64 +// register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr +// is used instead. Register-to-register movss/movsd is not modeled as an +// INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable +// in terms of a copy, and just mentioned, we don't use movss/movsd for copies. //===----------------------------------------------------------------------===// class sse12_move_rr : @@ -309,11 +315,7 @@ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set RC:$dst, (mem_pat addr:$src))]>; -// Move Instructions. Register-to-register movss/movsd is not used for FR32/64 -// register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr -// is used instead. Register-to-register movss/movsd is not modeled as an -// INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable -// in terms of a copy, and just mentioned, we don't use movss/movsd for copies. +// AVX def VMOVSSrr : sse12_move_rr, XS, VEX_4V; def VMOVSDrr : sse12_move_rr, XS, VEX; - let AddedComplexity = 20 in def VMOVSDrm : sse12_move_rm, XD, VEX; } +def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), + "movss\t{$src, $dst|$dst, $src}", + [(store FR32:$src, addr:$dst)]>, XS, VEX; +def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), + "movsd\t{$src, $dst|$dst, $src}", + [(store FR64:$src, addr:$dst)]>, XD, VEX; + +// SSE1 & 2 let Constraints = "$src1 = $dst" in { def MOVSSrr : sse12_move_rr, XS; @@ -340,19 +349,37 @@ def MOVSDrm : sse12_move_rm, XD; } -let AddedComplexity = 15 in { -// Extract the low 32-bit value from one vector and insert it into another. -def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)), - (MOVSSrr (v4f32 VR128:$src1), - (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; -// Extract the low 64-bit value from one vector and insert it into another. -def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)), - (MOVSDrr (v2f64 VR128:$src1), - (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; -} +def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), + "movss\t{$src, $dst|$dst, $src}", + [(store FR32:$src, addr:$dst)]>; +def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), + "movsd\t{$src, $dst|$dst, $src}", + [(store FR64:$src, addr:$dst)]>; -let AddedComplexity = 20 in { +// Patterns let Predicates = [HasSSE1] in { + let AddedComplexity = 15 in { + // Extract the low 32-bit value from one vector and insert it into another. + def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)), + (MOVSSrr (v4f32 VR128:$src1), + (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; + def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)), + (MOVSSrr (v4i32 VR128:$src1), + (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; + + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSS to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), + (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>; + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (MOVSSrr (v4f32 (V_SET0PS)), + (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (MOVSSrr (v4i32 (V_SET0PI)), + (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>; + } + + let AddedComplexity = 20 in { // MOVSSrm zeros the high parts of the register; represent this // with SUBREG_TO_REG. def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), @@ -361,8 +388,48 @@ (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>; def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>; + } + + // Extract and store. + def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (MOVSSmr addr:$dst, + (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; + + // Shuffle with MOVSS + def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), + (MOVSSrr VR128:$src1, FR32:$src2)>; + def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)), + (MOVSSrr (v4i32 VR128:$src1), + (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (MOVSSrr (v4f32 VR128:$src1), + (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; } + let Predicates = [HasSSE2] in { + let AddedComplexity = 15 in { + // Extract the low 64-bit value from one vector and insert it into another. + def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)), + (MOVSDrr (v2f64 VR128:$src1), + (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; + def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)), + (MOVSDrr (v2i64 VR128:$src1), + (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; + + // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd + def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVSD to the lower bits. + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), + (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>; + } + + let AddedComplexity = 20 in { // MOVSDrm zeros the high parts of the register; represent this // with SUBREG_TO_REG. def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), @@ -375,66 +442,161 @@ (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>; def : Pat<(v2f64 (X86vzload addr:$src)), (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>; -} -} + } -let AddedComplexity = 20, Predicates = [HasAVX] in { -// MOVSSrm zeros the high parts of the register; represent this -// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 -def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; -def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; -def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; -// MOVSDrm zeros the high parts of the register; represent this -// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 -def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), - (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))), - (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), - (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), - (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -def : Pat<(v2f64 (X86vzload addr:$src)), - (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -// Represent the same patterns above but in the form they appear for -// 256-bit types -def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, - (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; -def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, - (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))), - (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>; -} + // Extract and store. + def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), + addr:$dst), + (MOVSDmr addr:$dst, + (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>; + + // Shuffle with MOVSD + def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))), + (MOVSDrr VR128:$src1, FR64:$src2)>; + def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)), + (MOVSDrr (v2i64 VR128:$src1), + (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (MOVSDrr (v2f64 VR128:$src1), + (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; + def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>; + def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>; + + // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem + // is during lowering, where it's not possible to recognize the fold cause + // it has two uses through a bitcast. One use disappears at isel time and the + // fold opportunity reappears. + def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>; + def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>; +} + +let Predicates = [HasAVX] in { + let AddedComplexity = 15 in { + // Extract the low 32-bit value from one vector and insert it into another. + def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)), + (VMOVSSrr (v4f32 VR128:$src1), + (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; + def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)), + (VMOVSSrr (v4i32 VR128:$src1), + (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; + + // Extract the low 64-bit value from one vector and insert it into another. + def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)), + (VMOVSDrr (v2f64 VR128:$src1), + (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; + def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)), + (VMOVSDrr (v2i64 VR128:$src1), + (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; + + // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd + def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + + // Move scalar to XMM zero-extended, zeroing a VR128 then do a + // MOVS{S,D} to the lower bits. + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), + (VMOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>; + def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), + (VMOVSSrr (v4f32 (V_SET0PS)), + (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>; + def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), + (VMOVSSrr (v4i32 (V_SET0PI)), + (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>; + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), + (VMOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>; + } -// Store scalar value to memory. -def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), - "movss\t{$src, $dst|$dst, $src}", - [(store FR32:$src, addr:$dst)]>; -def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), - "movsd\t{$src, $dst|$dst, $src}", - [(store FR64:$src, addr:$dst)]>; + let AddedComplexity = 20 in { + // MOVSSrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; + def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; + def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; -def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), - "movss\t{$src, $dst|$dst, $src}", - [(store FR32:$src, addr:$dst)]>, XS, VEX; -def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), - "movsd\t{$src, $dst|$dst, $src}", - [(store FR64:$src, addr:$dst)]>, XD, VEX; + // MOVSDrm zeros the high parts of the register; represent this + // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 + def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), + (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; + def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))), + (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; + def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), + (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; + def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), + (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; + def : Pat<(v2f64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>; -// Extract and store. -def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), - addr:$dst), - (MOVSSmr addr:$dst, - (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; -def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), - addr:$dst), - (MOVSDmr addr:$dst, - (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>; + // Represent the same patterns above but in the form they appear for + // 256-bit types + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))), + (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>; + } + + // Extract and store. + def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), + addr:$dst), + (VMOVSSmr addr:$dst, + (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; + def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), + addr:$dst), + (VMOVSDmr addr:$dst, + (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>; + + // Shuffle with VMOVSS + def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), + (VMOVSSrr VR128:$src1, FR32:$src2)>; + def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)), + (VMOVSSrr (v4i32 VR128:$src1), + (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; + def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), + (VMOVSSrr (v4f32 VR128:$src1), + (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; + + // Shuffle with VMOVSD + def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))), + (VMOVSDrr VR128:$src1, FR64:$src2)>; + def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)), + (VMOVSDrr (v2i64 VR128:$src1), + (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; + def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), + (VMOVSDrr (v2f64 VR128:$src1), + (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; + def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), + sub_sd))>; + def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), + sub_sd))>; + + // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem + // is during lowering, where it's not possible to recognize the fold cause + // it has two uses through a bitcast. One use disappears at isel time and the + // fold opportunity reappears. + def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), + sub_sd))>; + def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)), + (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), + sub_sd))>; +} + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Aligned/Unaligned FP Instructions +//===----------------------------------------------------------------------===// -// Move Aligned/Unaligned floating point values multiclass sse12_mov_packed opc, RegisterClass RC, X86MemOperand x86memop, PatFrag ld_frag, string asm, Domain d, @@ -4392,22 +4554,6 @@ def : Pat<(fextend (loadf32 addr:$src)), (CVTSS2SDrm addr:$src)>; -// Move scalar to XMM zero-extended -// movd to XMM register zero-extends -let AddedComplexity = 15 in { -// Zeroing a VR128 then do a MOVS{S|D} to the lower bits. -def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), - (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>; -def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), - (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>; -def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), - (MOVSSrr (v4f32 (V_SET0PS)), - (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>; -def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), - (MOVSSrr (v4i32 (V_SET0PI)), - (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>; -} - // Splat v2f64 / v2i64 let AddedComplexity = 10 in { def : Pat<(splat_lo (v2i64 VR128:$src), (undef)), @@ -4437,24 +4583,6 @@ def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), (MOVLPDmr addr:$src1, VR128:$src2)>; -let AddedComplexity = 15 in { -// Setting the lowest element in the vector. -def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)), - (MOVSSrr (v4i32 VR128:$src1), - (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; -def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)), - (MOVSDrr (v2i64 VR128:$src1), - (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; - -// vector_shuffle v1, v2 <4, 5, 2, 3> using movsd -def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>, - Requires<[HasSSE2]>; -def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>, - Requires<[HasSSE2]>; -} - // Set lowest element and zero upper elements. def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; @@ -6200,30 +6328,6 @@ (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; -// Shuffle with MOVSS -def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), - (MOVSSrr VR128:$src1, FR32:$src2)>; -def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)), - (MOVSSrr (v4i32 VR128:$src1), - (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>; -def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), - (MOVSSrr (v4f32 VR128:$src1), - (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; - -// Shuffle with MOVSD -def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))), - (MOVSDrr VR128:$src1, FR64:$src2)>; -def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr (v2i64 VR128:$src1), - (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>; -def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr (v2f64 VR128:$src1), - (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; -def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>; -def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; - // Shuffle with MOVLPS def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))), (MOVLPSrm VR128:$src1, addr:$src2)>; @@ -6232,15 +6336,6 @@ def : Pat<(X86Movlps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVLPSrm VR128:$src1, addr:$src2)>; -// FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem -// is during lowering, where it's not possible to recognize the load fold cause -// it has two uses through a bitcast. One use disappears at isel time and the -// fold opportunity reappears. -def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>; - -def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; // Shuffle with MOVLPD def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), Modified: llvm/trunk/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll?rev=138851&r1=138850&r2=138851&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll Tue Aug 30 22:04:20 2011 @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 +; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 | FileCheck %s ; PR2484 define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind { entry: +; CHECK: shufps $-28, %xmm %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %shuffle From geek4civic at gmail.com Tue Aug 30 22:56:17 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 31 Aug 2011 03:56:17 -0000 Subject: [llvm-commits] [llvm] r138852 - /llvm/trunk/utils/lit/lit/TestRunner.py Message-ID: <20110831035617.3C4272A6C12C@llvm.org> Author: chapuni Date: Tue Aug 30 22:56:17 2011 New Revision: 138852 URL: http://llvm.org/viewvc/llvm-project?rev=138852&view=rev Log: lit: Normalize pathsep slashes also on %T. On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths. Modified: llvm/trunk/utils/lit/lit/TestRunner.py Modified: llvm/trunk/utils/lit/lit/TestRunner.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=138852&r1=138851&r2=138852&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/TestRunner.py (original) +++ llvm/trunk/utils/lit/lit/TestRunner.py Tue Aug 30 22:56:17 2011 @@ -406,6 +406,7 @@ if normalize_slashes: sourcepath = sourcepath.replace('\\', '/') sourcedir = sourcedir.replace('\\', '/') + tmpDir = tmpDir.replace('\\', '/') tmpBase = tmpBase.replace('\\', '/') # We use #_MARKER_# to hide %% while we do the other substitutions. From geek4civic at gmail.com Tue Aug 30 23:02:46 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 31 Aug 2011 13:02:46 +0900 Subject: [llvm-commits] [llvm] r138640 - /llvm/trunk/utils/lit/lit/TestRunner.py In-Reply-To: <20110826190518.E938A2A6C12D@llvm.org> References: <20110826190518.E938A2A6C12D@llvm.org> Message-ID: Doug, 2011/8/27 Douglas Gregor : > Author: dgregor > Date: Fri Aug 26 14:05:18 2011 > New Revision: 138640 > > URL: http://llvm.org/viewvc/llvm-project?rev=138640&view=rev > Log: > lit: Add %T as a replacement for the output directory It was the potential trigger why clang/test/Modules had been hanging on mingw msys. Fixed in r138852. %T has been used since r138679. Excuse me to bother you! ...though, it seems bogus paths might crash clang... ...Takumi From echristo at apple.com Tue Aug 30 23:17:21 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 31 Aug 2011 04:17:21 -0000 Subject: [llvm-commits] [llvm] r138853 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110831041721.6A5742A6C12C@llvm.org> Author: echristo Date: Tue Aug 30 23:17:21 2011 New Revision: 138853 URL: http://llvm.org/viewvc/llvm-project?rev=138853&view=rev Log: Rework this conditional a bit. Patch by Sanjoy Das Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138853&r1=138852&r2=138853&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 23:17:21 2011 @@ -521,12 +521,16 @@ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, - (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), - ((Subtarget->isTargetCOFF() - && !Subtarget->isTargetEnvMacho()) || - EnableSegmentedStacks - ? Custom : Expand)); + + if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) + setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? + MVT::i64 : MVT::i32, Custom); + else if (EnableSegmentedStacks) + setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? + MVT::i64 : MVT::i32, Custom); + else + setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? + MVT::i64 : MVT::i32, Expand); if (!UseSoftFloat && X86ScalarSSEf64) { // f32 and f64 use SSE. From echristo at apple.com Tue Aug 30 23:21:39 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 30 Aug 2011 21:21:39 -0700 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <4E5DA4B6.9000406@playingwithpointers.com> References: <20110830194704.AA1372A6C12C@llvm.org> <4E5DA3CB.6020604@playingwithpointers.com> <768AC3F5-AEC7-47EB-A3F0-7F1B7D5458A1@apple.com> <4E5DA4B6.9000406@playingwithpointers.com> Message-ID: <20D455E3-8DCA-4ACB-830C-F531F050AEB9@apple.com> On Aug 30, 2011, at 8:04 PM, Sanjoy Das wrote: >> Much nicer. Do you have commit access? > > No. Committed here: http://llvm.org/viewvc/llvm-project?rev=138853&view=rev -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110830/01251d56/attachment.html From baldrick at free.fr Wed Aug 31 01:33:46 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 08:33:46 +0200 Subject: [llvm-commits] [llvm] r138812 - in /llvm/trunk: include/llvm/Target/TargetFrameLowering.h lib/CodeGen/PrologEpilogInserter.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86FrameLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86MachineFunctionInfo.h In-Reply-To: <20110830193959.23C292A6C12C@llvm.org> References: <20110830193959.23C292A6C12C@llvm.org> Message-ID: <4E5DD5CA.3050408@free.fr> Hi Rafael, > --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) > +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Tue Aug 30 14:39:58 2011 > @@ -29,6 +29,7 @@ > #include "llvm/CodeGen/MachineRegisterInfo.h" > #include "llvm/CodeGen/RegisterScavenging.h" > #include "llvm/Target/TargetMachine.h" > +#include "llvm/Target/TargetOptions.h" > #include "llvm/Target/TargetRegisterInfo.h" > #include "llvm/Target/TargetFrameLowering.h" > #include "llvm/Target/TargetInstrInfo.h" > @@ -699,6 +700,13 @@ > if (!I->empty()&& I->back().getDesc().isReturn()) > TFI.emitEpilogue(Fn, *I); > } > + > + // Emit additional code that is required support segmented stacks, if we've required support -> required to support > + // been asked for it. This, when linked with a runtime with support for > + // segmented stacks (libgcc is one), will result allocating stack space in result allocating -> result in allocating > +static unsigned > +GetScratchRegister(bool Is64Bit, const MachineFunction&MF) { > + if (Is64Bit) { > + return X86::R11; > + } else { > + CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv(); > + bool IsNested = HasNestArgument(&MF); > + > + if (CallingConvention == CallingConv::X86_FastCall) { > + if (IsNested) { > + report_fatal_error("Segmented stacks does not supprot fastcall with " supprot -> support > + "nested fucntion."); fucntion -> function > + return -1; > + } else { > + return X86::EAX; > + } > + } else { > + if (IsNested) > + return X86::EDX; > + else > + return X86::ECX; > + } > + } > +} Ciao, Duncan. From baldrick at free.fr Wed Aug 31 01:57:09 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 08:57:09 +0200 Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <20110830194704.AA1372A6C12C@llvm.org> References: <20110830194704.AA1372A6C12C@llvm.org> Message-ID: <4E5DDB45.3000000@free.fr> Hi Rafael, > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 30 14:47:04 2011 > @@ -8844,8 +8846,10 @@ > SDValue > X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, > SelectionDAG&DAG) const { > - assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())&& > - "This should be used only on Windows targets"); > + assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || > + EnableSegmentedStacks)&& > + "This should be used only on Windows targets or when segmented stacks " > + "are being used."); It's not usual to have a full stop at the end of assertion messages. > assert(!Subtarget->isTargetEnvMacho()); Here there should be a message if the assertion fails. > DebugLoc dl = Op.getDebugLoc(); > > @@ -8854,23 +8858,49 @@ > SDValue Size = Op.getOperand(1); > // FIXME: Ensure alignment here > > - SDValue Flag; > + bool Is64Bit = Subtarget->is64Bit(); > + EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; > > - EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; > - unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); > + if (EnableSegmentedStacks) { > + MachineFunction&MF = DAG.getMachineFunction(); > + MachineRegisterInfo&MRI = MF.getRegInfo(); > > - Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); > - Flag = Chain.getValue(1); > + if (Is64Bit) { > + // The 64 bit implementation of segmented stacks needs to clobber both r10 > + // r11. This makes it impossible to use it along with nested paramenters. paramenters -> parameters What are the restrictions on using segmented stacks with nested functions exactly? Hopefully the implementation can fully support Go. Does GCC have the same restrictions? > + const Function *F = MF.getFunction(); > + > + for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); > + I != E; I++) > + if (I->hasNestAttr()) > + report_fatal_error("Cannot use segmented stacks with functions that " > + "have nested arguments."); > + } Ciao, Duncan. From baldrick at free.fr Wed Aug 31 02:03:59 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 09:03:59 +0200 Subject: [llvm-commits] [llvm] r138814 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrCompiler.td X86InstrInfo.td In-Reply-To: <20110830194321.91B082A6C12E@llvm.org> References: <20110830194321.91B082A6C12E@llvm.org> Message-ID: <4E5DDCDF.1090205@free.fr> Hi Rafael, > --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Aug 30 14:43:21 2011 > @@ -286,6 +286,11 @@ > // WIN_ALLOCA - Windows's _chkstk call to do stack probing. > WIN_ALLOCA, > > + // SEG_ALLOCA - For allocating variable amounts of stack space when using > + // segmented stacks. Check if the current stacklet has enough space, and > + // defects to heap allocation if not. defects to? > + SEG_ALLOCA, > + > // Memory barrier > MEMBARRIER, > MFENCE, > Ciao, Duncan. From baldrick at free.fr Wed Aug 31 02:19:00 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 09:19:00 +0200 Subject: [llvm-commits] [llvm] r138829 - in /llvm/trunk: lib/Transforms/Scalar/DeadStoreElimination.cpp test/Transforms/DeadStoreElimination/2011-08-30-EndOfFunction.ll In-Reply-To: <20110830211106.B7B082A6C12C@llvm.org> References: <20110830211106.B7B082A6C12C@llvm.org> Message-ID: <4E5DE064.1050608@free.fr> Hi Owen, > Speculatively revert r138809 in an attempt to fix DragonEgg. thanks for doing this. Dragonegg came back to life so I guess this patch was the culprit. Shall I try to get you a testcase? Ciao, Duncan. From james.molloy at arm.com Wed Aug 31 06:07:19 2011 From: james.molloy at arm.com (James Molloy) Date: Wed, 31 Aug 2011 12:07:19 +0100 Subject: [llvm-commits] [llvm] r137830 - in /llvm/trunk: include/llvm/MC/ lib/Target/ARM/Disassembler/ lib/Target/MBlaze/Disassembler/ lib/Target/X86/Disassembler/ test/MC/Disassembler/ARM/ tools/llvm-mc/ utils/TableGen/ In-Reply-To: References: <20110817174416.558E12A6C12C@llvm.org> <848FF71B-5F72-4D02-8EA4-12BFDA137518@apple.com> Message-ID: <005301cc67ce$27108620$75319260$@molloy@arm.com> Hi Jim, Apologies, somehow my spam filter got ahold of both of your replies. Lucky I checked it so soon after your ping, really :( Changing to switch() in Disassembler.cpp, need to change in MCDisassembler and EDDisassembler -------------------------------------------------------------------------------- ------------- I will do. Fail -> llvm::MCDisassembler::Fail ---------------------------------- Can do; now that I've done the grunt work a simple regex will suffice to do that. I'd suggest "using namespace llvm;" though to shorten it slightly - are you OK with that? No early exit ------------- I can remove this. I thought it made the code flow easier, but I see your point that hiding the early exit is inadvisable. Use enum values instead of & ---------------------------- I implemented this as a binary-AND for two reasons: * Makes the macro, which is used everywhere, more compact and quicker than using if-statements. * Allows for more return types to be added if needed without any change to the code. If instead you'd prefer me to write the macro as a big switch: #define CHECK(S, X) do { switch ((X)) { case MCDisassembler::Success: break; case MCDisassembler::SoftFail: S = MCDisassembler::SoftFail; break; case MCDisassembler::Fail: S = MCDisassembler::Fail; default: llvm_unreachable(); } I can, or better possibly as we're going the whole hog and not caring so much about comparison speed: bool Check(MCDisassembler::DecodeStatus &Out, MCDisassembler::DecodeStatus In) { switch (In) { case MCDisassembler::Success: return true; case MCDisassembler::SoftFail: Out = In; return true; case MCDisassembler::Fail: Out = In; return false; default: llvm_unreachable(); } } Then the CHECK() lines could be changed to: if (!Check(S, ...)) return MCDisassembler::Fail; Which would satisfy your above criterion? Cheers, James > -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: 30 August 2011 20:15 > To: James Molloy > Cc: llvm-commits LLVM; Owen Anderson > Subject: Re: [llvm-commits] [llvm] r137830 - in /llvm/trunk: > include/llvm/MC/ lib/Target/ARM/Disassembler/ > lib/Target/MBlaze/Disassembler/ lib/Target/X86/Disassembler/ > test/MC/Disassembler/ARM/ tools/llvm-mc/ utils/TableGen/ > > ping? > > On Aug 26, 2011, at 11:56 AM, Jim Grosbach wrote: > > > Sorry for the late comments. I missed this catching these bits the first > time around (saw the patch, just missed this aspect). > > > > On Aug 17, 2011, at 10:44 AM, Owen Anderson wrote: > > > >> Author: resistor > >> Date: Wed Aug 17 12:44:15 2011 > >> New Revision: 137830 > >> > >> URL: http://llvm.org/viewvc/llvm-project?rev=137830&view=rev > >> Log: > >> Allow the MCDisassembler to return a "soft fail" status code, indicating > an instruction that is disassemblable, but invalid. Only used for ARM > UNPREDICTABLE instructions at the moment. > >> Patch by James Molloy. > >> > >> Modified: > >> llvm/trunk/include/llvm/MC/MCDisassembler.h > >> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > >> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h > >> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp > >> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h > >> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp > >> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h > >> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt > >> llvm/trunk/tools/llvm-mc/Disassembler.cpp > >> llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp > >> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp > >> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h > >> > >> Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=137830&r1=137829&r2 > =137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/include/llvm/MC/MCDisassembler.h (original) > >> +++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Aug 17 12:44:15 2011 > >> @@ -25,6 +25,34 @@ > >> /// and provides an array of assembly instructions. > >> class MCDisassembler { > >> public: > >> + /// Ternary decode status. Most backends will just use Fail and > >> + /// Success, however some have a concept of an instruction with > >> + /// understandable semantics but which is architecturally > >> + /// incorrect. An example of this is ARM UNPREDICTABLE instructions > >> + /// which are disassemblable but cause undefined behaviour. > >> + /// > >> + /// Because it makes sense to disassemble these instructions, there > >> + /// is a "soft fail" failure mode that indicates the MCInst& is > >> + /// valid but architecturally incorrect. > >> + /// > >> + /// The enum numbers are deliberately chosen such that reduction > >> + /// from Success->SoftFail ->Fail can be done with a simple > >> + /// bitwise-AND: > >> + /// > >> + /// LEFT & TOP = | Success Unpredictable Fail > >> + /// --------------+----------------------------------- > >> + /// Success | Success Unpredictable Fail > >> + /// Unpredictable | Unpredictable Unpredictable Fail > >> + /// Fail | Fail Fail Fail > >> + /// > >> + /// An easy way of encoding this is as 0b11, 0b01, 0b00 for > >> + /// Success, SoftFail, Fail respectively. > >> + enum DecodeStatus { > >> + Fail = 0, > >> + SoftFail = 1, > >> + Success = 3 > >> + }; > >> + > >> /// Constructor - Performs initial setup for the disassembler. > >> MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {} > >> > >> @@ -41,8 +69,11 @@ > >> /// @param address - The address, in the memory space of region, of > the first > >> /// byte of the instruction. > >> /// @param vStream - The stream to print warnings and diagnostic > messages on. > >> - /// @return - True if the instruction is valid; false > otherwise. > >> - virtual bool getInstruction(MCInst& instr, > >> + /// @return - MCDisassembler::Success if the instruction is > valid, > >> + /// MCDisassembler::SoftFail if the instruction was > >> + /// disassemblable but > invalid, > >> + /// MCDisassembler::Fail if the instruction was > invalid. > >> + virtual DecodeStatus getInstruction(MCInst& instr, > >> uint64_t& size, > >> const MemoryObject ®ion, > >> uint64_t address, > >> > >> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=1378 > 30&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > (original) > >> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug > 17 12:44:15 2011 > >> @@ -24,188 +24,201 @@ > >> #include "llvm/Support/ErrorHandling.h" > >> #include "llvm/Support/raw_ostream.h" > >> > >> +// Pull DecodeStatus and its enum values into the global namespace. > >> +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; > >> +#define Success llvm::MCDisassembler::Success > >> +#define Unpredictable llvm::MCDisassembler::SoftFail > >> +#define Fail llvm::MCDisassembler::Fail > >> + > > > > Please don't do this sort of thing (#defines to get around scoping). > Reference the names explicitly, including the scoping operators, instead. > > > >> +// Helper macro to perform setwise reduction of the current running > status > >> +// and another status, and return if the new status is Fail. > >> +#define CHECK(S,X) do { \ > >> + S = (DecodeStatus) ((int)S & (X)); \ > > > > It's better to use the enum values directly rather than casting integers > like this. The code shouldn't know what the actual values of the enums are. > > > >> + if (S == Fail) return Fail; \ > >> + } while(0) > >> + > > > > Having an early exit buried in a macro obfuscates the code. The way the > code previously did this is better. Please change this back or refactor > differently. > > > >> // Forward declare these because the autogenerated code will reference > them. > >> // Definitions are further down. > >> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder); > >> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void > *Decoder); > >> > >> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> > >> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> > >> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, > >> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst > & Inst, > >> unsigned Insn, > >> uint64_t Adddress, > >> const void *Decoder); > >> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder); > >> > >> > >> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, > uint16_t Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, > >> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder); > >> > >> #include "ARMGenDisassemblerTables.inc" > >> @@ -230,15 +243,14 @@ > >> return instInfoARM; > >> } > >> > >> - > >> -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > >> - const MemoryObject &Region, > >> - uint64_t Address,raw_ostream &os) > const { > >> +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t > &Size, > >> + const MemoryObject > &Region, > >> + uint64_t > Address,raw_ostream &os) const { > >> uint8_t bytes[4]; > >> > >> // We want to read exactly 4 bytes of data. > >> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > >> - return false; > >> + return Fail; > >> > >> // Encoded as a small-endian 32-bit word in the stream. > >> uint32_t insn = (bytes[3] << 24) | > >> @@ -247,10 +259,10 @@ > >> (bytes[0] << 0); > >> > >> // Calling the auto-generated decoder function. > >> - bool result = decodeARMInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, > this); > >> + if (result != Fail) { > >> Size = 4; > >> - return true; > >> + return result; > >> } > >> > >> // Instructions that are shared between ARM and Thumb modes. > >> @@ -258,53 +270,53 @@ > >> // fact that we fail to encode a few instructions properly for Thumb. > >> MI.clear(); > >> result = decodeCommonInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> - return true; > >> + return result; > >> } > >> > >> // VFP and NEON instructions, similarly, are shared between ARM > >> // and Thumb modes. > >> MI.clear(); > >> result = decodeVFPInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeNEONDataInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> // Add a fake predicate operand, because we share these instruction > >> // definitions with Thumb2 where these instructions are predicable. > >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > >> - return true; > >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> // Add a fake predicate operand, because we share these instruction > >> // definitions with Thumb2 where these instructions are predicable. > >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > >> - return true; > >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeNEONDupInstruction32(MI, insn, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> // Add a fake predicate operand, because we share these instruction > >> // definitions with Thumb2 where these instructions are predicable. > >> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; > >> - return true; > >> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; > >> + return result; > >> } > >> > >> MI.clear(); > >> > >> - return false; > >> + return Fail; > >> } > >> > >> namespace llvm { > >> @@ -403,22 +415,21 @@ > >> } > >> } > >> > >> - > >> -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, > >> - const MemoryObject &Region, > >> - uint64_t Address,raw_ostream > &os) const { > >> +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t > &Size, > >> + const MemoryObject > &Region, > >> + uint64_t > Address,raw_ostream &os) const { > >> uint8_t bytes[4]; > >> > >> // We want to read exactly 2 bytes of data. > >> if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) > >> - return false; > >> + return Fail; > >> > >> uint16_t insn16 = (bytes[1] << 8) | bytes[0]; > >> - bool result = decodeThumbInstruction16(MI, insn16, Address, this); > >> - if (result) { > >> + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, > this); > >> + if (result != Fail) { > >> Size = 2; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> @@ -428,12 +439,12 @@ > >> bool InITBlock = !ITBlock.empty(); > >> AddThumbPredicate(MI); > >> AddThumb1SBit(MI, InITBlock); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeThumb2Instruction16(MI, insn16, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 2; > >> AddThumbPredicate(MI); > >> > >> @@ -456,12 +467,12 @@ > >> ITBlock.push_back(firstcond); > >> } > >> > >> - return true; > >> + return result; > >> } > >> > >> // We want to read exactly 4 bytes of data. > >> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) > >> - return false; > >> + return Fail; > >> > >> uint32_t insn32 = (bytes[3] << 8) | > >> (bytes[2] << 0) | > >> @@ -469,44 +480,44 @@ > >> (bytes[0] << 16); > >> MI.clear(); > >> result = decodeThumbInstruction32(MI, insn32, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> bool InITBlock = ITBlock.size(); > >> AddThumbPredicate(MI); > >> AddThumb1SBit(MI, InITBlock); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeThumb2Instruction32(MI, insn32, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeCommonInstruction32(MI, insn32, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeVFPInstruction32(MI, insn32, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> UpdateThumbVFPPredicate(MI); > >> - return true; > >> + return result; > >> } > >> > >> MI.clear(); > >> result = decodeNEONDupInstruction32(MI, insn32, Address, this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> > >> if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { > >> @@ -515,10 +526,10 @@ > >> NEONLdStInsn &= 0xF0FFFFFF; > >> NEONLdStInsn |= 0x04000000; > >> result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, > this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> } > >> > >> @@ -529,14 +540,14 @@ > >> NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to > bit 24 > >> NEONDataInsn |= 0x12000000; // Set bits 28 and 25 > >> result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, > this); > >> - if (result) { > >> + if (result != Fail) { > >> Size = 4; > >> AddThumbPredicate(MI); > >> - return true; > >> + return result; > >> } > >> } > >> > >> - return false; > >> + return Fail; > >> } > >> > >> > >> @@ -554,30 +565,30 @@ > >> ARM::R12, ARM::SP, ARM::LR, ARM::PC > >> }; > >> > >> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 15) > >> - return false; > >> + return Fail; > >> > >> unsigned Register = GPRDecoderTable[RegNo]; > >> Inst.addOperand(MCOperand::CreateReg(Register)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void > *Decoder) { > >> - if (RegNo == 15) return false; > >> + if (RegNo == 15) return Fail; > >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > >> } > >> > >> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 7) > >> - return false; > >> + return Fail; > >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > >> } > >> > >> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void *Decoder) > { > >> unsigned Register = 0; > >> switch (RegNo) { > >> @@ -600,16 +611,16 @@ > >> Register = ARM::R12; > >> break; > >> default: > >> - return false; > >> + return Fail; > >> } > >> > >> Inst.addOperand(MCOperand::CreateReg(Register)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void *Decoder) > { > >> - if (RegNo == 13 || RegNo == 15) return false; > >> + if (RegNo == 13 || RegNo == 15) return Fail; > >> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); > >> } > >> > >> @@ -624,14 +635,14 @@ > >> ARM::S28, ARM::S29, ARM::S30, ARM::S31 > >> }; > >> > >> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 31) > >> - return false; > >> + return Fail; > >> > >> unsigned Register = SPRDecoderTable[RegNo]; > >> Inst.addOperand(MCOperand::CreateReg(Register)); > >> - return true; > >> + return Success; > >> } > >> > >> static const unsigned DPRDecoderTable[] = { > >> @@ -645,27 +656,27 @@ > >> ARM::D28, ARM::D29, ARM::D30, ARM::D31 > >> }; > >> > >> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 31) > >> - return false; > >> + return Fail; > >> > >> unsigned Register = DPRDecoderTable[RegNo]; > >> Inst.addOperand(MCOperand::CreateReg(Register)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 7) > >> - return false; > >> + return Fail; > >> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); > >> } > >> > >> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, > unsigned RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 15) > >> - return false; > >> + return Fail; > >> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); > >> } > >> > >> @@ -677,65 +688,66 @@ > >> }; > >> > >> > >> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, > >> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned > RegNo, > >> uint64_t Address, const void *Decoder) > { > >> if (RegNo > 31) > >> - return false; > >> + return Fail; > >> RegNo >>= 1; > >> > >> unsigned Register = QPRDecoderTable[RegNo]; > >> Inst.addOperand(MCOperand::CreateReg(Register)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> - if (Val == 0xF) return false; > >> + if (Val == 0xF) return Fail; > >> // AL predicate is not allowed on Thumb1 branches. > >> if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) > >> - return false; > >> + return Fail; > >> Inst.addOperand(MCOperand::CreateImm(Val)); > >> if (Val == ARMCC::AL) { > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> } else > >> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> if (Val) > >> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); > >> else > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> uint32_t imm = Val & 0xFF; > >> uint32_t rot = (Val & 0xF00) >> 7; > >> uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); > >> Inst.addOperand(MCOperand::CreateImm(rot_imm)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Val <<= 2; > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> > >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); > >> unsigned type = fieldFromInstruction32(Val, 5, 2); > >> unsigned imm = fieldFromInstruction32(Val, 7, 5); > >> > >> // Register-immediate > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> > >> ARM_AM::ShiftOpc Shift = ARM_AM::lsl; > >> switch (type) { > >> @@ -759,19 +771,20 @@ > >> unsigned Op = Shift | (imm << 3); > >> Inst.addOperand(MCOperand::CreateImm(Op)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> > >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); > >> unsigned type = fieldFromInstruction32(Val, 5, 2); > >> unsigned Rs = fieldFromInstruction32(Val, 8, 4); > >> > >> // Register-register > >> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); > >> > >> ARM_AM::ShiftOpc Shift = ARM_AM::lsl; > >> switch (type) { > >> @@ -791,49 +804,55 @@ > >> > >> Inst.addOperand(MCOperand::CreateImm(Shift)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> // Empty register lists are not allowed. > >> - if (CountPopulation_32(Val) == 0) return false; > >> + if (CountPopulation_32(Val) == 0) return Fail; > >> for (unsigned i = 0; i < 16; ++i) { > >> if (Val & (1 << i)) { > >> - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); > >> } > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Vd = fieldFromInstruction32(Val, 8, 4); > >> unsigned regs = Val & 0xFF; > >> > >> - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); > >> for (unsigned i = 0; i < (regs - 1); ++i) { > >> - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Vd = fieldFromInstruction32(Val, 8, 4); > >> unsigned regs = (Val & 0xFF) / 2; > >> > >> - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); > >> for (unsigned i = 0; i < (regs - 1); ++i) { > >> - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void > *Decoder) { > >> // This operand encodes a mask of contiguous zeros between a specified > MSB > >> // and LSB. To decode it, we create the mask of all bits MSB-and- > lower, > >> @@ -845,11 +864,13 @@ > >> uint32_t msb_mask = (1 << (msb+1)) - 1; > >> uint32_t lsb_mask = (1 << lsb) - 1; > >> Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> unsigned CRd = fieldFromInstruction32(Insn, 12, 4); > >> unsigned coproc = fieldFromInstruction32(Insn, 8, 4); > >> @@ -875,7 +896,7 @@ > >> case ARM::STCL_POST: > >> case ARM::STCL_OPTION: > >> if (coproc == 0xA || coproc == 0xB) > >> - return false; > >> + return Fail; > >> break; > >> default: > >> break; > >> @@ -883,7 +904,7 @@ > >> > >> Inst.addOperand(MCOperand::CreateImm(coproc)); > >> Inst.addOperand(MCOperand::CreateImm(CRd)); > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> switch (Inst.getOpcode()) { > >> case ARM::LDC_OPTION: > >> case ARM::LDCL_OPTION: > >> @@ -952,17 +973,19 @@ > >> case ARM::STCL_PRE: > >> case ARM::STCL_POST: > >> case ARM::STCL_OPTION: > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> @@ -982,13 +1005,13 @@ > >> case ARM::STRT_POST_IMM: > >> case ARM::STRBT_POST_REG: > >> case ARM::STRBT_POST_IMM: > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> > >> // On loads, the writeback operand comes after Rt. > >> switch (Inst.getOpcode()) { > >> @@ -1002,14 +1025,13 @@ > >> case ARM::LDRBT_POST_IMM: > >> case ARM::LDRT_POST_REG: > >> case ARM::LDRT_POST_IMM: > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> > >> ARM_AM::AddrOpc Op = ARM_AM::add; > >> if (!fieldFromInstruction32(Insn, 23, 1)) > >> @@ -1022,10 +1044,10 @@ > >> else if (!P && writeback) > >> idx_mode = ARMII::IndexModePost; > >> > >> - if (writeback && (Rn == 15 || Rn == Rt)) return false; // > UNPREDICTABLE > >> + if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // > UNPREDICTABLE > >> > >> if (reg) { > >> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > >> ARM_AM::ShiftOpc Opc = ARM_AM::lsl; > >> switch( fieldFromInstruction32(Insn, 5, 2)) { > >> case 0: > >> @@ -1041,7 +1063,7 @@ > >> Opc = ARM_AM::ror; > >> break; > >> default: > >> - return false; > >> + return Fail; > >> } > >> unsigned amt = fieldFromInstruction32(Insn, 7, 5); > >> unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); > >> @@ -1053,13 +1075,15 @@ > >> Inst.addOperand(MCOperand::CreateImm(tmp)); > >> } > >> > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); > >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); > >> unsigned type = fieldFromInstruction32(Val, 5, 2); > >> @@ -1082,8 +1106,8 @@ > >> break; > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> unsigned shift; > >> if (U) > >> shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); > >> @@ -1091,11 +1115,13 @@ > >> shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); > >> Inst.addOperand(MCOperand::CreateImm(shift)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> @@ -1116,7 +1142,7 @@ > >> case ARM::LDRD: > >> case ARM::LDRD_PRE: > >> case ARM::LDRD_POST: > >> - if (Rt & 0x1) return false; > >> + if (Rt & 0x1) return Fail; > >> break; > >> default: > >> break; > >> @@ -1136,16 +1162,14 @@ > >> case ARM::STRH: > >> case ARM::STRH_PRE: > >> case ARM::STRH_POST: > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> switch (Inst.getOpcode()) { > >> case ARM::STRD: > >> case ARM::STRD_PRE: > >> @@ -1153,8 +1177,7 @@ > >> case ARM::LDRD: > >> case ARM::LDRD_PRE: > >> case ARM::LDRD_POST: > >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > >> break; > >> default: > >> break; > >> @@ -1177,33 +1200,32 @@ > >> case ARM::LDRSB_POST: > >> case ARM::LDRHTr: > >> case ARM::LDRSBTr: > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> > >> if (type) { > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); > >> } else { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(U)); > >> } > >> > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned mode = fieldFromInstruction32(Insn, 23, 2); > >> > >> @@ -1223,14 +1245,16 @@ > >> } > >> > >> Inst.addOperand(MCOperand::CreateImm(mode)); > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, > >> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst > &Inst, > >> unsigned Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> unsigned reglist = fieldFromInstruction32(Insn, 0, 16); > >> @@ -1265,16 +1289,15 @@ > >> return DecodeRFEInstruction(Inst, Insn, Address, Decoder); > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied > >> - !DecodePredicateOperand(Inst, pred, Address, Decoder) || > >> - !DecodeRegListOperand(Inst, reglist, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> + CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> unsigned imod = fieldFromInstruction32(Insn, 18, 2); > >> unsigned M = fieldFromInstruction32(Insn, 17, 1); > >> @@ -1282,30 +1305,32 @@ > >> unsigned mode = fieldFromInstruction32(Insn, 0, 5); > >> > >> // imod == '01' --> UNPREDICTABLE > >> - if (imod == 1) return false; > >> + if (imod == 1) return Fail; > >> > >> if (M && mode && imod && iflags) { > >> Inst.setOpcode(ARM::CPS3p); > >> Inst.addOperand(MCOperand::CreateImm(imod)); > >> Inst.addOperand(MCOperand::CreateImm(iflags)); > >> Inst.addOperand(MCOperand::CreateImm(mode)); > >> - return true; > >> + return Success; > >> } else if (!mode && !M) { > >> Inst.setOpcode(ARM::CPS2p); > >> Inst.addOperand(MCOperand::CreateImm(imod)); > >> Inst.addOperand(MCOperand::CreateImm(iflags)); > >> - return true; > >> + return Success; > >> } else if (!imod && !iflags && M) { > >> Inst.setOpcode(ARM::CPS1p); > >> Inst.addOperand(MCOperand::CreateImm(mode)); > >> - return true; > >> + return Success; > >> } > >> > >> - return false; > >> + return Fail; > >> } > >> > >> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rn = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 8, 4); > >> @@ -1315,57 +1340,60 @@ > >> if (pred == 0xF) > >> return DecodeCPSInstruction(Inst, Insn, Address, Decoder); > >> > >> - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || > >> - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || > >> - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); > >> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); > >> > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned add = fieldFromInstruction32(Val, 12, 1); > >> unsigned imm = fieldFromInstruction32(Val, 0, 12); > >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> > >> if (!add) imm *= -1; > >> if (imm == 0 && !add) imm = INT32_MIN; > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); > >> unsigned U = fieldFromInstruction32(Val, 8, 1); > >> unsigned imm = fieldFromInstruction32(Val, 0, 8); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> > >> if (U) > >> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, > imm))); > >> else > >> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, > imm))); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); > >> } > >> > >> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; > >> > >> @@ -1373,39 +1401,42 @@ > >> Inst.setOpcode(ARM::BLXi); > >> imm |= fieldFromInstruction32(Insn, 24, 1) << 1; > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); > >> - return true; > >> + return S; > >> } > >> > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(64 - Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rm = fieldFromInstruction32(Val, 0, 4); > >> unsigned align = fieldFromInstruction32(Val, 4, 2); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> if (!align) > >> Inst.addOperand(MCOperand::CreateImm(0)); > >> else > >> Inst.addOperand(MCOperand::CreateImm(4 << align)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned wb = fieldFromInstruction32(Insn, 16, 4); > >> @@ -1414,7 +1445,7 @@ > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> > >> // First output register > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> > >> // Second output register > >> switch (Inst.getOpcode()) { > >> @@ -1466,7 +1497,7 @@ > >> case ARM::VLD4d8_UPD: > >> case ARM::VLD4d16_UPD: > >> case ARM::VLD4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, > Decoder)); > >> break; > >> case ARM::VLD2b8: > >> case ARM::VLD2b16: > >> @@ -1486,7 +1517,7 @@ > >> case ARM::VLD4q8_UPD: > >> case ARM::VLD4q16_UPD: > >> case ARM::VLD4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, > Decoder)); > >> default: > >> break; > >> } > >> @@ -1527,7 +1558,7 @@ > >> case ARM::VLD4d8_UPD: > >> case ARM::VLD4d16_UPD: > >> case ARM::VLD4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, > Decoder)); > >> break; > >> case ARM::VLD3q8: > >> case ARM::VLD3q16: > >> @@ -1541,7 +1572,7 @@ > >> case ARM::VLD4q8_UPD: > >> case ARM::VLD4q16_UPD: > >> case ARM::VLD4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, > Decoder)); > >> break; > >> default: > >> break; > >> @@ -1569,7 +1600,7 @@ > >> case ARM::VLD4d8_UPD: > >> case ARM::VLD4d16_UPD: > >> case ARM::VLD4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, > Decoder)); > >> break; > >> case ARM::VLD4q8: > >> case ARM::VLD4q16: > >> @@ -1577,7 +1608,7 @@ > >> case ARM::VLD4q8_UPD: > >> case ARM::VLD4q16_UPD: > >> case ARM::VLD4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, > Decoder)); > >> break; > >> default: > >> break; > >> @@ -1622,28 +1653,29 @@ > >> case ARM::VLD4q8_UPD: > >> case ARM::VLD4q16_UPD: > >> case ARM::VLD4q32_UPD: > >> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> // AddrMode6 Base (register+alignment) > >> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); > >> > >> // AddrMode6 Offset (register) > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned wb = fieldFromInstruction32(Insn, 16, 4); > >> @@ -1690,25 +1722,24 @@ > >> case ARM::VST4q8_UPD: > >> case ARM::VST4q16_UPD: > >> case ARM::VST4q32_UPD: > >> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> // AddrMode6 Base (register+alignment) > >> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); > >> > >> // AddrMode6 Offset (register) > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> // First input register > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> > >> // Second input register > >> switch (Inst.getOpcode()) { > >> @@ -1760,7 +1791,7 @@ > >> case ARM::VST4d8_UPD: > >> case ARM::VST4d16_UPD: > >> case ARM::VST4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, > Decoder)); > >> break; > >> case ARM::VST2b8: > >> case ARM::VST2b16: > >> @@ -1780,7 +1811,7 @@ > >> case ARM::VST4q8_UPD: > >> case ARM::VST4q16_UPD: > >> case ARM::VST4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, > Decoder)); > >> break; > >> default: > >> break; > >> @@ -1822,7 +1853,7 @@ > >> case ARM::VST4d8_UPD: > >> case ARM::VST4d16_UPD: > >> case ARM::VST4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, > Decoder)); > >> break; > >> case ARM::VST3q8: > >> case ARM::VST3q16: > >> @@ -1836,7 +1867,7 @@ > >> case ARM::VST4q8_UPD: > >> case ARM::VST4q16_UPD: > >> case ARM::VST4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, > Decoder)); > >> break; > >> default: > >> break; > >> @@ -1864,7 +1895,7 @@ > >> case ARM::VST4d8_UPD: > >> case ARM::VST4d16_UPD: > >> case ARM::VST4d32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, > Decoder)); > >> break; > >> case ARM::VST4q8: > >> case ARM::VST4q16: > >> @@ -1872,17 +1903,19 @@ > >> case ARM::VST4q8_UPD: > >> case ARM::VST4q16_UPD: > >> case ARM::VST4q32_UPD: > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, > Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> @@ -1893,28 +1926,30 @@ > >> > >> align *= (1 << size); > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> if (regs == 2) { > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, > Decoder)); > >> } > >> if (Rm == 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> @@ -1924,54 +1959,57 @@ > >> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; > >> align *= 2*size; > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, > Decoder)); > >> if (Rm == 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || > >> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || > >> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, > Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, > Decoder)); > >> if (Rm == 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(0)); > >> > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> @@ -1993,29 +2031,30 @@ > >> } > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || > >> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || > >> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || > >> - !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, > Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, > Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, > Decoder)); > >> if (Rm == 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> > >> if (Rm == 0xD) > >> Inst.addOperand(MCOperand::CreateReg(0)); > >> else if (Rm != 0xF) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned imm = fieldFromInstruction32(Insn, 0, 4); > >> @@ -2026,9 +2065,9 @@ > >> unsigned Q = fieldFromInstruction32(Insn, 6, 1); > >> > >> if (Q) { > >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > >> } else { > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> } > >> > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> @@ -2038,62 +2077,66 @@ > >> case ARM::VORRiv2i32: > >> case ARM::VBICiv4i16: > >> case ARM::VBICiv2i32: > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> break; > >> case ARM::VORRiv8i16: > >> case ARM::VORRiv4i32: > >> case ARM::VBICiv8i16: > >> case ARM::VBICiv4i32: > >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > >> break; > >> default: > >> break; > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; > >> unsigned size = fieldFromInstruction32(Insn, 18, 2); > >> > >> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(8 << size)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(8 - Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(16 - Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(32 - Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(64 - Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> @@ -2103,21 +2146,21 @@ > >> unsigned op = fieldFromInstruction32(Insn, 6, 1); > >> unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> if (op) { > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; // Writeback > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // > Writeback > >> } > >> > >> for (unsigned i = 0; i < length; ++i) { > >> - if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) > return false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, > Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> // The immediate needs to be a fully instantiated float. However, the > >> // auto-generated decoder is only able to fill in some of the bits > >> @@ -2139,102 +2182,110 @@ > >> fp_conv.integer |= (~b & 0x1) << 30; > >> > >> Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, > uint16_t Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned dst = fieldFromInstruction16(Insn, 8, 3); > >> unsigned imm = fieldFromInstruction16(Insn, 0, 8); > >> > >> - if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return > false; > >> + CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); > >> > >> if (Inst.getOpcode() == ARM::tADR) > >> Inst.addOperand(MCOperand::CreateReg(ARM::PC)); > >> else if (Inst.getOpcode() == ARM::tADDrSPi) > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> else > >> - return false; > >> + return Fail; > >> > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 0, 3); > >> unsigned Rm = fieldFromInstruction32(Val, 3, 3); > >> > >> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 0, 3); > >> unsigned imm = fieldFromInstruction32(Val, 3, 5); > >> > >> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> Inst.addOperand(MCOperand::CreateImm(Val << 2)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> Inst.addOperand(MCOperand::CreateImm(Val << 2)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 6, 4); > >> unsigned Rm = fieldFromInstruction32(Val, 2, 4); > >> unsigned imm = fieldFromInstruction32(Val, 0, 2); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> if (Inst.getOpcode() != ARM::t2PLDs) { > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> } > >> > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> @@ -2257,57 +2308,60 @@ > >> Inst.addOperand(MCOperand::CreateReg(ARM::PC)); > >> break; > >> default: > >> - return false; > >> + return Fail; > >> } > >> > >> int imm = fieldFromInstruction32(Insn, 0, 12); > >> if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return S; > >> } > >> > >> unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); > >> addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; > >> addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; > >> - DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); > >> + CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> int imm = Val & 0xFF; > >> if (!(Val & 0x100)) imm *= -1; > >> Inst.addOperand(MCOperand::CreateImm(imm << 2)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); > >> unsigned imm = fieldFromInstruction32(Val, 0, 9); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> int imm = Val & 0xFF; > >> if (!(Val & 0x100)) imm *= -1; > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> > >> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 9, 4); > >> unsigned imm = fieldFromInstruction32(Val, 0, 9); > >> > >> @@ -2324,27 +2378,28 @@ > >> break; > >> } > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || > >> - !DecodeT2Imm8(Inst, imm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Val, 13, 4); > >> unsigned imm = fieldFromInstruction32(Val, 0, 12); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t > Insn, > >> uint64_t Address, const void *Decoder) { > >> unsigned imm = fieldFromInstruction16(Insn, 0, 7); > >> > >> @@ -2352,30 +2407,32 @@ > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t > Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> if (Inst.getOpcode() == ARM::tADDrSP) { > >> unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); > >> Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); > >> } else if (Inst.getOpcode() == ARM::tADDspr) { > >> unsigned Rm = fieldFromInstruction16(Insn, 3, 4); > >> > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> Inst.addOperand(MCOperand::CreateReg(ARM::SP)); > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > >> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, > >> uint64_t Address, const void *Decoder) { > >> unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; > >> unsigned flags = fieldFromInstruction16(Insn, 0, 3); > >> @@ -2383,52 +2440,55 @@ > >> Inst.addOperand(MCOperand::CreateImm(imod)); > >> Inst.addOperand(MCOperand::CreateImm(flags)); > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned add = fieldFromInstruction32(Insn, 4, 1); > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; > >> Inst.addOperand(MCOperand::CreateImm(add)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) { > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> if (Val == 0xA || Val == 0xB) > >> - return false; > >> + return Fail; > >> > >> Inst.addOperand(MCOperand::CreateImm(Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> if (Val == 0) > >> Inst.addOperand(MCOperand::CreateImm(32)); > >> else > >> Inst.addOperand(MCOperand::CreateImm(Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned > Insn, > >> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, > unsigned Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned pred = fieldFromInstruction32(Insn, 22, 4); > >> if (pred == 0xE || pred == 0xF) { > >> unsigned opc = fieldFromInstruction32(Insn, 4, 2); > >> switch (opc) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> Inst.setOpcode(ARM::t2DSB); > >> break; > >> @@ -2437,7 +2497,7 @@ > >> break; > >> case 2: > >> Inst.setOpcode(ARM::t2ISB); > >> - return true; > >> + return Success; > >> } > >> > >> unsigned imm = fieldFromInstruction32(Insn, 0, 4); > >> @@ -2450,17 +2510,16 @@ > >> brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; > >> brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; > >> > >> - if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || > >> - !DecodePredicateOperand(Inst, pred, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> // Decode a shifted immediate operand. These basically consist > >> // of an 8-bit value, and a 4-bit directive that specifies either > >> // a splat operation or a rotation. > >> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> unsigned ctrl = fieldFromInstruction32(Val, 10, 2); > >> if (ctrl == 0) { > >> @@ -2488,26 +2547,26 @@ > >> Inst.addOperand(MCOperand::CreateImm(imm)); > >> } > >> > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void > *Decoder){ > >> Inst.addOperand(MCOperand::CreateImm(Val << 1)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned > Val, > >> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, > unsigned Val, > >> uint64_t Address, const void > *Decoder){ > >> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned > Val, > >> uint64_t Address, const void *Decoder) > { > >> switch (Val) { > >> default: > >> - return false; > >> + return Fail; > >> case 0xF: // SY > >> case 0xE: // ST > >> case 0xB: // ISH > >> @@ -2520,55 +2579,61 @@ > >> } > >> > >> Inst.addOperand(MCOperand::CreateImm(Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, > >> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, > >> uint64_t Address, const void *Decoder) { > >> - if (!Val) return false; > >> + if (!Val) return Fail; > >> Inst.addOperand(MCOperand::CreateImm(Val)); > >> - return true; > >> + return Success; > >> } > >> > >> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> > >> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; > >> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned > Insn, > >> uint64_t Address, const void > *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> unsigned Rt = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> > >> - if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); > >> > >> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; > >> - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; > >> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; > >> + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> unsigned imm = fieldFromInstruction32(Insn, 0, 12); > >> @@ -2576,18 +2641,20 @@ > >> imm |= fieldFromInstruction32(Insn, 23, 1) << 12; > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> > >> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE > >> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> - if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return > false; > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> + CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rt = fieldFromInstruction32(Insn, 12, 4); > >> unsigned imm = fieldFromInstruction32(Insn, 0, 12); > >> @@ -2595,18 +2662,20 @@ > >> imm |= fieldFromInstruction32(Insn, 23, 1) << 12; > >> unsigned pred = fieldFromInstruction32(Insn, 28, 4); > >> > >> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE > >> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE > >> > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return > false; > >> - if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return > false; > >> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); > >> + CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); > >> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2617,47 +2686,47 @@ > >> unsigned index = 0; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 5, 3); > >> break; > >> case 1: > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 6, 2); > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> align = 2; > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 6, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 4, 2) != 0) > >> align = 4; > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2668,47 +2737,47 @@ > >> unsigned index = 0; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 5, 3); > >> break; > >> case 1: > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 6, 2); > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> align = 2; > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 6, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 4, 2) != 0) > >> align = 4; > >> } > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2720,7 +2789,7 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> index = fieldFromInstruction32(Insn, 5, 3); > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> @@ -2735,7 +2804,7 @@ > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 4, 1) != 0) > >> align = 8; > >> @@ -2744,28 +2813,28 @@ > >> break; > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2777,7 +2846,7 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> index = fieldFromInstruction32(Insn, 5, 3); > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> @@ -2792,7 +2861,7 @@ > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 4, 1) != 0) > >> align = 8; > >> @@ -2802,26 +2871,26 @@ > >> } > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2833,53 +2902,53 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 5, 3); > >> break; > >> case 1: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 6, 2); > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> inc = 2; > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 4, 2)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 6, 1)) > >> inc = 2; > >> break; > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2891,22 +2960,22 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 5, 3); > >> break; > >> case 1: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 6, 2); > >> if (fieldFromInstruction32(Insn, 5, 1)) > >> inc = 2; > >> break; > >> case 2: > >> if (fieldFromInstruction32(Insn, 4, 2)) > >> - return false; // UNDEFINED > >> + return Fail; // UNDEFINED > >> index = fieldFromInstruction32(Insn, 7, 1); > >> if (fieldFromInstruction32(Insn, 6, 1)) > >> inc = 2; > >> @@ -2914,27 +2983,27 @@ > >> } > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -2946,7 +3015,7 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> align = 4; > >> @@ -2968,33 +3037,33 @@ > >> break; > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > >> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, > >> uint64_t Address, const void *Decoder) { > >> + DecodeStatus S = Success; > >> + > >> unsigned Rn = fieldFromInstruction32(Insn, 16, 4); > >> unsigned Rm = fieldFromInstruction32(Insn, 0, 4); > >> unsigned Rd = fieldFromInstruction32(Insn, 12, 4); > >> @@ -3006,7 +3075,7 @@ > >> unsigned inc = 1; > >> switch (size) { > >> default: > >> - return false; > >> + return Fail; > >> case 0: > >> if (fieldFromInstruction32(Insn, 4, 1)) > >> align = 4; > >> @@ -3029,22 +3098,20 @@ > >> } > >> > >> if (Rm != 0xF) { // Writeback > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> } > >> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return > false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(align)); > >> if (Rm != 0xF && Rm != 0xD) { > >> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) > >> - return false; > >> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); > >> } > >> > >> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return > false; > >> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return > false; > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); > >> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); > >> Inst.addOperand(MCOperand::CreateImm(index)); > >> > >> - return true; > >> + return S; > >> } > >> > >> > >> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h?rev=137830 > &r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h (original) > >> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h Wed Aug 17 > 12:44:15 2011 > >> @@ -40,11 +40,11 @@ > >> } > >> > >> /// getInstruction - See MCDisassembler. > >> - bool getInstruction(MCInst &instr, > >> - uint64_t &size, > >> - const MemoryObject ®ion, > >> - uint64_t address, > >> - raw_ostream &vStream) const; > >> + DecodeStatus getInstruction(MCInst &instr, > >> + uint64_t &size, > >> + const MemoryObject ®ion, > >> + uint64_t address, > >> + raw_ostream &vStream) const; > >> > >> /// getEDInfo - See MCDisassembler. > >> EDInstInfo *getEDInfo() const; > >> @@ -64,11 +64,11 @@ > >> } > >> > >> /// getInstruction - See MCDisassembler. > >> - bool getInstruction(MCInst &instr, > >> - uint64_t &size, > >> - const MemoryObject ®ion, > >> - uint64_t address, > >> - raw_ostream &vStream) const; > >> + DecodeStatus getInstruction(MCInst &instr, > >> + uint64_t &size, > >> + const MemoryObject ®ion, > >> + uint64_t address, > >> + raw_ostream &vStream) const; > >> > >> /// getEDInfo - See MCDisassembler. > >> EDInstInfo *getEDInfo() const; > >> > >> Modified: > llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?re > v=137830&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp > (original) > >> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed > Aug 17 12:44:15 2011 > >> @@ -493,7 +493,7 @@ > >> // Public interface for the disassembler > >> // > >> > >> -bool MBlazeDisassembler::getInstruction(MCInst &instr, > >> +MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst > &instr, > >> uint64_t &size, > >> const MemoryObject ®ion, > >> uint64_t address, > >> @@ -508,7 +508,7 @@ > >> > >> // We want to read exactly 4 bytes of data. > >> if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read > < 4) > >> - return false; > >> + return Fail; > >> > >> // Encoded as a big-endian 32-bit word in the stream. > >> insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | > (bytes[3]<<0); > >> @@ -517,7 +517,7 @@ > >> // that it is a valid instruction. > >> unsigned opcode = getOPCODE(insn); > >> if (opcode == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> > >> instr.setOpcode(opcode); > >> > >> @@ -529,11 +529,11 @@ > >> uint64_t tsFlags = MBlazeInsts[opcode].TSFlags; > >> switch ((tsFlags & MBlazeII::FormMask)) { > >> default: > >> - return false; > >> + return Fail; > >> > >> case MBlazeII::FRRRR: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> @@ -541,7 +541,7 @@ > >> > >> case MBlazeII::FRRR: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> @@ -550,23 +550,23 @@ > >> case MBlazeII::FRI: > >> switch (opcode) { > >> default: > >> - return false; > >> + return Fail; > >> case MBlaze::MFS: > >> if (RD == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); > >> break; > >> case MBlaze::MTS: > >> if (RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> break; > >> case MBlaze::MSRSET: > >> case MBlaze::MSRCLR: > >> if (RD == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateImm(insn&0x7FFF)); > >> break; > >> @@ -575,7 +575,7 @@ > >> > >> case MBlazeII::FRRI: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> switch (opcode) { > >> @@ -592,35 +592,35 @@ > >> > >> case MBlazeII::FCRR: > >> if (RA == UNSUPPORTED || RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> break; > >> > >> case MBlazeII::FCRI: > >> if (RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > >> break; > >> > >> case MBlazeII::FRCR: > >> if (RD == UNSUPPORTED || RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> break; > >> > >> case MBlazeII::FRCI: > >> if (RD == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > >> break; > >> > >> case MBlazeII::FCCR: > >> if (RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> break; > >> > >> @@ -630,7 +630,7 @@ > >> > >> case MBlazeII::FRRCI: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> instr.addOperand(MCOperand::CreateImm(getSHT(insn))); > >> @@ -638,35 +638,35 @@ > >> > >> case MBlazeII::FRRC: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> break; > >> > >> case MBlazeII::FRCX: > >> if (RD == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateImm(getFSL(insn))); > >> break; > >> > >> case MBlazeII::FRCS: > >> if (RD == UNSUPPORTED || RS == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateReg(RS)); > >> break; > >> > >> case MBlazeII::FCRCS: > >> if (RS == UNSUPPORTED || RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RS)); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> break; > >> > >> case MBlazeII::FCRCX: > >> if (RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> instr.addOperand(MCOperand::CreateImm(getFSL(insn))); > >> break; > >> @@ -677,13 +677,13 @@ > >> > >> case MBlazeII::FCR: > >> if (RB == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RB)); > >> break; > >> > >> case MBlazeII::FRIR: > >> if (RD == UNSUPPORTED || RA == UNSUPPORTED) > >> - return false; > >> + return Fail; > >> instr.addOperand(MCOperand::CreateReg(RD)); > >> instr.addOperand(MCOperand::CreateImm(getIMM(insn))); > >> instr.addOperand(MCOperand::CreateReg(RA)); > >> @@ -693,7 +693,7 @@ > >> // We always consume 4 bytes of data on success > >> size = 4; > >> > >> - return true; > >> + return Success; > >> } > >> > >> static MCDisassembler *createMBlazeDisassembler(const Target &T) { > >> > >> Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev= > 137830&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h > (original) > >> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed > Aug 17 12:44:15 2011 > >> @@ -40,7 +40,7 @@ > >> } > >> > >> /// getInstruction - See MCDisassembler. > >> - bool getInstruction(MCInst &instr, > >> + MCDisassembler::DecodeStatus getInstruction(MCInst &instr, > >> uint64_t &size, > >> const MemoryObject ®ion, > >> uint64_t address, > >> > >> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=1378 > 30&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp > (original) > >> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug > 17 12:44:15 2011 > >> @@ -106,11 +106,12 @@ > >> // Public interface for the disassembler > >> // > >> > >> -bool X86GenericDisassembler::getInstruction(MCInst &instr, > >> - uint64_t &size, > >> - const MemoryObject ®ion, > >> - uint64_t address, > >> - raw_ostream &vStream) const > { > >> +MCDisassembler::DecodeStatus > >> +X86GenericDisassembler::getInstruction(MCInst &instr, > >> + uint64_t &size, > >> + const MemoryObject ®ion, > >> + uint64_t address, > >> + raw_ostream &vStream) const { > >> InternalInstruction internalInstr; > >> > >> int ret = decodeInstruction(&internalInstr, > >> @@ -123,11 +124,11 @@ > >> > >> if (ret) { > >> size = internalInstr.readerCursor - address; > >> - return false; > >> + return Fail; > >> } > >> else { > >> size = internalInstr.length; > >> - return !translateInstruction(instr, internalInstr); > >> + return (!translateInstruction(instr, internalInstr)) ? Success : > Fail; > >> } > >> } > >> > >> > >> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=137830 > &r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original) > >> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Aug 17 > 12:44:15 2011 > >> @@ -112,11 +112,11 @@ > >> ~X86GenericDisassembler(); > >> > >> /// getInstruction - See MCDisassembler. > >> - bool getInstruction(MCInst &instr, > >> - uint64_t &size, > >> - const MemoryObject ®ion, > >> - uint64_t address, > >> - raw_ostream &vStream) const; > >> + DecodeStatus getInstruction(MCInst &instr, > >> + uint64_t &size, > >> + const MemoryObject ®ion, > >> + uint64_t address, > >> + raw_ostream &vStream) const; > >> > >> /// getEDInfo - See MCDisassembler. > >> EDInstInfo *getEDInfo() const; > >> > >> Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST- > arm.txt?rev=137830&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt > (original) > >> +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Wed > Aug 17 12:44:15 2011 > >> @@ -1,4 +1,4 @@ > >> -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep > {invalid instruction encoding} > >> +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep > {potentially undefined instruction encoding} > >> > >> # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) > >> # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 > 8 7 6 5 4 3 2 1 0 > >> > >> Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp > >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm- > mc/Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original) > >> +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 17 12:44:15 2011 > >> @@ -65,15 +65,26 @@ > >> for (Index = 0; Index < Bytes.size(); Index += Size) { > >> MCInst Inst; > >> > >> - if (DisAsm.getInstruction(Inst, Size, memoryObject, Index, > >> - /*REMOVE*/ nulls())) { > >> - Printer.printInst(&Inst, Out); > >> - Out << "\n"; > >> - } else { > >> + MCDisassembler::DecodeStatus S; > >> + S = DisAsm.getInstruction(Inst, Size, memoryObject, Index, > >> + /*REMOVE*/ nulls()); > >> + switch (S) { > > > > > > Changing this to a switch statement is good. The C bindings in > MCDisasembler.cpp and EDDisassembler.cpp need to be changed, too, though. > They're still doing "!Disasm->getInstruction()" type constructs. > > > > > >> + case MCDisassembler::Fail: > >> SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), > >> "invalid instruction encoding", "warning"); > >> if (Size == 0) > >> Size = 1; // skip illegible bytes > >> + break; > >> + > >> + case MCDisassembler::SoftFail: > >> + SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second), > >> + "potentially undefined instruction encoding", > "warning"); > >> + // Fall through > >> + > >> + case MCDisassembler::Success: > >> + Printer.printInst(&Inst, Out); > >> + Out << "\n"; > >> + break; > >> } > >> } > >> > >> > >> Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=137830&r1=137 > 829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original) > >> +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Aug 17 > 12:44:15 2011 > >> @@ -128,5 +128,15 @@ > >> return; > >> } > >> > >> + // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. > >> + if (Target.getName() == "ARM" || > >> + Target.getName() == "Thumb") { > >> + FixedLenDecoderEmitter(Records, > >> + "CHECK(S, ", ");", > >> + "S", "Fail", > >> + "DecodeStatus S = > Success;\n(void)S;").run(OS); > >> + return; > >> + } > >> + > >> FixedLenDecoderEmitter(Records).run(OS); > >> } > >> > >> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=137830&r1= > 137829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) > >> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Aug 17 > 12:44:15 2011 > >> @@ -238,19 +238,24 @@ > >> // Width of instructions > >> unsigned BitWidth; > >> > >> + // Parent emitter > >> + const FixedLenDecoderEmitter *Emitter; > >> + > >> public: > >> FilterChooser(const FilterChooser &FC) : > >> AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes), > >> Operands(FC.Operands), Filters(FC.Filters), > >> FilterBitValues(FC.FilterBitValues), Parent(FC.Parent), > >> - BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { } > >> + BestIndex(FC.BestIndex), BitWidth(FC.BitWidth), > >> + Emitter(FC.Emitter) { } > >> > >> FilterChooser(const std::vector &Insts, > >> const std::vector &IDs, > >> std::map > &Ops, > >> - unsigned BW) : > >> + unsigned BW, > >> + const FixedLenDecoderEmitter *E) : > >> AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), > >> - Parent(NULL), BestIndex(-1), BitWidth(BW) { > >> + Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) { > >> for (unsigned i = 0; i < BitWidth; ++i) > >> FilterBitValues.push_back(BIT_UNFILTERED); > >> > >> @@ -264,7 +269,8 @@ > >> FilterChooser &parent) : > >> AllInstructions(Insts), Opcodes(IDs), Operands(Ops), > >> Filters(), FilterBitValues(ParentFilterBitValues), > >> - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) { > >> + Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth), > >> + Emitter(parent.Emitter) { > >> doFilter(); > >> } > >> > >> @@ -563,17 +569,17 @@ > >> void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation, > >> std::string Namespace) { > >> o.indent(Indentation) << > >> - "static bool decode" << Namespace << "Instruction" << BitWidth > >> + "static MCDisassembler::DecodeStatus decode" << Namespace << > "Instruction" << BitWidth > >> << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, " > >> << "const void *Decoder) {\n"; > >> - o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n"; > >> + o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n" << > Emitter->Locals << "\n"; > >> > >> ++Indentation; ++Indentation; > >> // Emits code to decode the instructions. > >> emit(o, Indentation); > >> > >> o << '\n'; > >> - o.indent(Indentation) << "return false;\n"; > >> + o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n"; > >> --Indentation; --Indentation; > >> > >> o.indent(Indentation) << "}\n"; > >> @@ -744,8 +750,8 @@ > >> } > >> > >> if (Decoder != "") > >> - o.indent(Indentation) << " if (!" << Decoder > >> - << "(MI, tmp, Address, Decoder)) return > false;\n"; > >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << Decoder > >> + << "(MI, tmp, Address, Decoder)" << Emitter- > >GuardPostfix << "\n"; > >> else > >> o.indent(Indentation) << " > MI.addOperand(MCOperand::CreateImm(tmp));\n"; > >> > >> @@ -776,15 +782,15 @@ > >> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { > >> // If a custom instruction decoder was specified, use that. > >> if (I->numFields() == 0 && I->Decoder.size()) { > >> - o.indent(Indentation) << " if (!" << I->Decoder > >> - << "(MI, insn, Address, Decoder)) return > false;\n"; > >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I- > >Decoder > >> + << "(MI, insn, Address, Decoder)" << > Emitter->GuardPostfix << "\n"; > >> break; > >> } > >> > >> emitBinaryParser(o, Indentation, *I); > >> } > >> > >> - o.indent(Indentation) << " return true; // " << nameWithID(Opc) > >> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // > " << nameWithID(Opc) > >> << '\n'; > >> o.indent(Indentation) << "}\n"; > >> return true; > >> @@ -821,14 +827,14 @@ > >> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { > >> // If a custom instruction decoder was specified, use that. > >> if (I->numFields() == 0 && I->Decoder.size()) { > >> - o.indent(Indentation) << " if (!" << I->Decoder > >> - << "(MI, insn, Address, Decoder)) return > false;\n"; > >> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I- > >Decoder > >> + << "(MI, insn, Address, Decoder)" << > Emitter->GuardPostfix << "\n"; > >> break; > >> } > >> > >> emitBinaryParser(o, Indentation, *I); > >> } > >> - o.indent(Indentation) << " return true; // " << nameWithID(Opc) > >> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " > << nameWithID(Opc) > >> << '\n'; > >> o.indent(Indentation) << "}\n"; > >> > >> @@ -1426,7 +1432,7 @@ > >> > >> // Emit the decoder for this namespace+width combination. > >> FilterChooser FC(NumberedInstructions, I->second, Operands, > >> - 8*I->first.second); > >> + 8*I->first.second, this); > >> FC.emitTop(o, 0, I->first.first); > >> } > >> > >> > >> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h > >> URL: http://llvm.org/viewvc/llvm- > project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=137830&r1=13 > 7829&r2=137830&view=diff > >> > =========================================================================== > === > >> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original) > >> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Aug 17 > 12:44:15 2011 > >> @@ -49,9 +49,16 @@ > >> > >> class FixedLenDecoderEmitter : public TableGenBackend { > >> public: > >> - FixedLenDecoderEmitter(RecordKeeper &R) : > >> + FixedLenDecoderEmitter(RecordKeeper &R, > >> + std::string GPrefix = "if (", > >> + std::string GPostfix = " == > MCDisassembler::Fail) return MCDisassembler::Fail;", > >> + std::string ROK = > "MCDisassembler::Success", > >> + std::string RFail = "MCDisassembler::Fail", > >> + std::string L = "") : > >> Records(R), Target(R), > >> - NumberedInstructions(Target.getInstructionsByEnumValue()) {} > >> + NumberedInstructions(Target.getInstructionsByEnumValue()), > >> + GuardPrefix(GPrefix), GuardPostfix(GPostfix), > >> + ReturnOK(ROK), ReturnFail(RFail), Locals(L) {} > >> > >> // run - Output the code emitter > >> void run(raw_ostream &o); > >> @@ -62,7 +69,10 @@ > >> std::vector NumberedInstructions; > >> std::vector Opcodes; > >> std::map > Operands; > >> - > >> +public: > >> + std::string GuardPrefix, GuardPostfix; > >> + std::string ReturnOK, ReturnFail; > >> + std::string Locals; > >> }; > >> > >> } // end llvm namespace > >> > >> > >> _______________________________________________ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > From 6yearold at gmail.com Wed Aug 31 07:06:13 2011 From: 6yearold at gmail.com (arrowdodger) Date: Wed, 31 Aug 2011 16:06:13 +0400 Subject: [llvm-commits] [PATCH] Rename LLVM_MULTITHREADED define and fix build without threads In-Reply-To: References: Message-ID: On Sat, Aug 6, 2011 at 2:21 PM, arrowdodger <6yearold at gmail.com> wrote: > Hi, there is LLVM_MULTITHREADED define which is actually indicates presence > of atomic builtins in the host system. Such name may confuse developers in > future and already confused someone at lib/Support/Threading.cpp - he used > this define to check whether LLVM is built with threading support. This > mistake is currently blocking single-threaded build on Unix. > > This patch do following things: > 1. Rename LLVM_MULTITHREADED to LLVM_HAVE_ATOMICS in CMake checking code > and configure.ac, fix description of this option. > 2. Replaces all uses of old define with new one. > 3. Fix lib/Support/Threading.cpp file by using ENABLE_THREADS define > instead of LLVM_MULTITHREADED. > Ping. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110831/2ae9513f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm.atomics.define.diff Type: text/x-patch Size: 6452 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110831/2ae9513f/attachment.bin From proljc at gmail.com Wed Aug 31 03:49:10 2011 From: proljc at gmail.com (Liu) Date: Wed, 31 Aug 2011 16:49:10 +0800 Subject: [llvm-commits] Fix MIPS InstPrinter Makefile typo Message-ID: Hi all I find a typo in lib/Target/Mips/InstPrinter/Makefile and fix it. --Liu -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-Fix-MIPS-InstPrinter-Makefile-typo.patch Type: text/x-patch Size: 847 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110831/9b84e4fd/attachment.bin From bob.wilson at apple.com Wed Aug 31 11:17:25 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 31 Aug 2011 09:17:25 -0700 Subject: [llvm-commits] [llvm] r138794 - /llvm/trunk/lib/CodeGen/InlineSpiller.cpp In-Reply-To: <20110830053603.09A292A6C12C@llvm.org> References: <20110830053603.09A292A6C12C@llvm.org> Message-ID: <0594814C-899C-426F-A55F-1D33927BD159@apple.com> Jakob wants to try a less conservative fix. I'm going to leave it up to him to find a testcase. On Aug 29, 2011, at 10:36 PM, Bob Wilson wrote: > Author: bwilson > Date: Tue Aug 30 00:36:02 2011 > New Revision: 138794 > > URL: http://llvm.org/viewvc/llvm-project?rev=138794&view=rev > Log: > Do not try to rematerialize a value from a partial definition. > I don't currently have a good testcase for this; will try to get one > tomorrow. > > Modified: > llvm/trunk/lib/CodeGen/InlineSpiller.cpp > > Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=138794&r1=138793&r2=138794&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) > +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Aug 30 00:36:02 2011 > @@ -189,6 +189,20 @@ > return 0; > } > > +/// isFullDefOf - Return true if MI defines the full contents of a register. > +/// Since this is in the context of spilling, it does not do anything special > +/// for physical registers. > +static bool isFullDefOf(const MachineInstr *MI, unsigned Reg) { > + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { > + const MachineOperand &MO = MI->getOperand(i); > + if (!MO.isReg() || !MO.isDef() || MO.getSubReg()) > + continue; > + if (MO.getReg() == Reg) > + return true; > + } > + return false; > +} > + > /// isSnippet - Identify if a live interval is a snippet that should be spilled. > /// It is assumed that SnipLI is a virtual register with the same original as > /// Edit->getReg(). > @@ -306,6 +320,7 @@ > MachineBasicBlock *SpillMBB = UseMBB; > unsigned SpillDepth = Loops.getLoopDepth(SpillMBB); > bool SeenOrigPHI = false; // Original PHI met. > + bool SeenNonReloadDef = false; > > do { > unsigned Reg; > @@ -407,12 +422,18 @@ > } > > // Potential remat candidate. > + SeenNonReloadDef = true; > + if (!isFullDefOf(MI, Reg)) { > + DEBUG(dbgs() << " partial def " << PrintReg(Reg) << ':' > + << VNI->id << '@' << VNI->def << '\t' << *MI); > + continue; > + } > DEBUG(dbgs() << " def " << PrintReg(Reg) << ':' > << VNI->id << '@' << VNI->def << '\t' << *MI); > SVI.DefMI = MI; > } while (!WorkList.empty()); > > - if (SeenOrigPHI || SVI.DefMI) > + if (SeenOrigPHI || SeenNonReloadDef) > SVI.AllDefsAreReloads = false; > > DEBUG({ > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From greened at obbligato.org Wed Aug 31 11:19:03 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 31 Aug 2011 11:19:03 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: (Chris Lattner's message of "Tue, 30 Aug 2011 16:08:14 -0700") References: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Message-ID: Chris Lattner writes: > + for (int i = 1, e = CA->getNumOperands(); i != e; ++i) { > > Please declare 'i' as 'unsigned' instead of 'int'. I'm not objecting to this, but rather am curious. Typing loop counters as unsigned can do all sorts of horrible things to analysis and optimization due to wraparound requirements. I've got into the habit of always typing loop counters as signed to avoid these issues. Is there a specific reason to prefer unsigned? -Dave From eli.friedman at gmail.com Wed Aug 31 11:19:52 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 16:19:52 -0000 Subject: [llvm-commits] [llvm] r138856 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110831161952.2E9472A6C12C@llvm.org> Author: efriedma Date: Wed Aug 31 11:19:51 2011 New Revision: 138856 URL: http://llvm.org/viewvc/llvm-project?rev=138856&view=rev Log: Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138856&r1=138855&r2=138856&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Aug 31 11:19:51 2011 @@ -901,7 +901,8 @@ } // Darwin 10.7 and greater has support for compact unwind encoding. - if (STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) + if (STI.getTargetTriple().isMacOSX() && + !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); } From rafael.espindola at gmail.com Wed Aug 31 11:43:33 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 31 Aug 2011 16:43:33 -0000 Subject: [llvm-commits] [llvm] r138858 - in /llvm/trunk/lib: CodeGen/PrologEpilogInserter.cpp Target/X86/X86FrameLowering.cpp Message-ID: <20110831164333.9072F2A6C12C@llvm.org> Author: rafael Date: Wed Aug 31 11:43:33 2011 New Revision: 138858 URL: http://llvm.org/viewvc/llvm-project?rev=138858&view=rev Log: Spelling and grammar fixes to problems found by Duncan. Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=138858&r1=138857&r2=138858&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Aug 31 11:43:33 2011 @@ -701,10 +701,10 @@ TFI.emitEpilogue(Fn, *I); } - // Emit additional code that is required support segmented stacks, if we've - // been asked for it. This, when linked with a runtime with support for - // segmented stacks (libgcc is one), will result allocating stack space in - // small chunks instead of one large contiguous block. + // Emit additional code that is required to support segmented stacks, if + // we've been asked for it. This, when linked with a runtime with support + // for segmented stacks (libgcc is one), will result in allocating stack + // space in small chunks instead of one large contiguous block. if (EnableSegmentedStacks) TFI.adjustForSegmentedStacks(Fn); } Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=138858&r1=138857&r2=138858&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Aug 31 11:43:33 2011 @@ -1292,8 +1292,8 @@ if (CallingConvention == CallingConv::X86_FastCall) { if (IsNested) { - report_fatal_error("Segmented stacks does not supprot fastcall with " - "nested fucntion."); + report_fatal_error("Segmented stacks does not support fastcall with " + "nested function."); return -1; } else { return X86::EAX; From clattner at apple.com Wed Aug 31 11:47:24 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 31 Aug 2011 09:47:24 -0700 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: References: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Message-ID: On Aug 31, 2011, at 9:19 AM, David A. Greene wrote: > Chris Lattner writes: > >> + for (int i = 1, e = CA->getNumOperands(); i != e; ++i) { >> >> Please declare 'i' as 'unsigned' instead of 'int'. > > I'm not objecting to this, but rather am curious. > > Typing loop counters as unsigned can do all sorts of horrible things to > analysis and optimization due to wraparound requirements. This isn't the case for loops that start at a constant and stride by 1. > I've got into > the habit of always typing loop counters as signed to avoid these > issues. Is there a specific reason to prefer unsigned? The value is unsigned, it conveys intentions more clearly. This is quite consistent in the codebase. -Chris From benny.kra at googlemail.com Wed Aug 31 11:49:06 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 31 Aug 2011 16:49:06 -0000 Subject: [llvm-commits] [llvm] r138859 - /llvm/trunk/test/CodeGen/X86/tail-call-got.ll Message-ID: <20110831164906.1B0FD2A6C12C@llvm.org> Author: d0k Date: Wed Aug 31 11:49:05 2011 New Revision: 138859 URL: http://llvm.org/viewvc/llvm-project?rev=138859&view=rev Log: This test requires sse, otherwise x87 ops will block tailcall optimization Modified: llvm/trunk/test/CodeGen/X86/tail-call-got.ll Modified: llvm/trunk/test/CodeGen/X86/tail-call-got.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-call-got.ll?rev=138859&r1=138858&r2=138859&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tail-call-got.ll (original) +++ llvm/trunk/test/CodeGen/X86/tail-call-got.ll Wed Aug 31 11:49:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=pic | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mattr=+sse2 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i386-unknown-freebsd9.0" From stoklund at 2pi.dk Wed Aug 31 12:00:02 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 31 Aug 2011 17:00:02 -0000 Subject: [llvm-commits] [llvm] r138861 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20110831170002.D95362A6C12C@llvm.org> Author: stoklund Date: Wed Aug 31 12:00:02 2011 New Revision: 138861 URL: http://llvm.org/viewvc/llvm-project?rev=138861&view=rev Log: Put VMOVS widening under a command line option, off by default. It appears that our use of the imp-use and imp-def flags with sub-registers is not yet robust enough to support this. The failing test case is complicated, I am working on a reduction. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138861&r1=138860&r2=138861&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Aug 31 12:00:02 2011 @@ -46,6 +46,10 @@ EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); +static cl::opt +WidenVMOVS("widen-vmovs", cl::Hidden, + cl::desc("Widen ARM vmovs to vmovd when possible")); + /// ARM_MLxEntry - Record information about MLA / MLS instructions. struct ARM_MLxEntry { unsigned MLxOpc; // MLA / MLS opcode @@ -637,7 +641,8 @@ // a VMOVD since that can be converted to a NEON-domain move by // NEONMoveFix.cpp. Check that MI is the original COPY instruction, and // that it really defines the whole D-register. - if ((DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 && + if (WidenVMOVS && + (DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 && I != MBB.end() && I->isCopy() && I->getOperand(0).getReg() == DestReg && I->getOperand(1).getReg() == SrcReg) { From benny.kra at googlemail.com Wed Aug 31 12:01:03 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 31 Aug 2011 10:01:03 -0700 Subject: [llvm-commits] [llvm] r138810 - in /llvm/trunk: include/llvm/MC/MCInstrDesc.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/InstrEmitter.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/AR Message-ID: On Tue, Aug 30, 2011 at 12:09, Evan Cheng wrote: > Author: evancheng > Date: Tue Aug 30 14:09:48 2011 > New Revision: 138810 > > URL: http://llvm.org/viewvc/llvm-project?rev=138810&view=rev > Log: > Follow up to r138791. > > Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to > call a target hook to adjust the instruction. For ARM, this is used to > adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC > instructions have implicit def of CPSR (required since it now uses CPSR physical > register dependency rather than "glue"). If the carry flag is used, then the > target hook will *fill in* the optional operand with CPSR. Otherwise, the hook > will remove the CPSR implicit def from the MachineInstr. Hi Evan, looks like this (or your previous patch) breaks some tests on arm: $ llc < test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll -march=arm LLVM ERROR: Can't handle live physical register dependency! - Ben From grosbach at apple.com Wed Aug 31 12:07:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 17:07:33 -0000 Subject: [llvm-commits] [llvm] r138862 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110831170733.C239B2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 12:07:33 2011 New Revision: 138862 URL: http://llvm.org/viewvc/llvm-project?rev=138862&view=rev Log: Tweak Thumb1 ADD encoding selection a bit. When the destination register of an add immediate instruction is explicitly specified, encoding T1 is preferred, else encoding T2 is preferred. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138862&r1=138861&r2=138862&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 31 12:07:33 2011 @@ -3473,8 +3473,11 @@ } break; case ARM::tADDi8: - // If the immediate is in the range 0-7, we really wanted tADDi3. - if (Inst.getOperand(3).getImm() < 8) + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was + // explicitly specified. From the ARM ARM: "Encoding T1 is preferred + // to encoding T2 if is specified and encoding T2 is preferred + // to encoding T1 if is omitted." + if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) Inst.setOpcode(ARM::tADDi3); break; case ARM::tBcc: Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138862&r1=138861&r2=138862&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 31 12:07:33 2011 @@ -26,11 +26,13 @@ @ ADD (immediate) @------------------------------------------------------------------------------ adds r1, r2, #3 +@ When Rd is not explicitly specified, encoding T2 is preferred even though +@ the literal is in the range [0,7] which would allow encoding T1. adds r2, #3 adds r2, #8 @ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c] -@ CHECK: adds r2, r2, #3 @ encoding: [0xd2,0x1c] +@ CHECK: adds r2, #3 @ encoding: [0x03,0x32] @ CHECK: adds r2, #8 @ encoding: [0x08,0x32] From eli.friedman at gmail.com Wed Aug 31 12:14:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 10:14:07 -0700 Subject: [llvm-commits] [llvm] r138724 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-InitOrder.ll In-Reply-To: <20110828131722.BB5362A6C13F@llvm.org> References: <20110828131722.BB5362A6C13F@llvm.org> Message-ID: On Sun, Aug 28, 2011 at 6:17 AM, Duncan Sands wrote: > Author: baldrick > Date: Sun Aug 28 08:17:22 2011 > New Revision: 138724 > > URL: http://llvm.org/viewvc/llvm-project?rev=138724&view=rev > Log: > Fix PR5329: pay attention to constructor/destructor priority > when outputting them. ?With this, the entire LLVM testsuite > passes when built with dragonegg. > > Added: > ? ?llvm/trunk/test/CodeGen/X86/2011-08-29-InitOrder.ll > Modified: > ? ?llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=138724&r1=138723&r2=138724&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sun Aug 28 08:17:22 2011 > @@ -1228,22 +1228,45 @@ > ? } > ?} > > -/// EmitXXStructorList - Emit the ctor or dtor list. ?This just prints out the > -/// function pointers, ignoring the init priority. > +typedef std::pair Structor; > + > +static bool priority_order(const Structor& lhs, const Structor& rhs) > +{ > + ?return lhs.first < rhs.first; > +} > + > +/// EmitXXStructorList - Emit the ctor or dtor list taking into account the init > +/// priority. > ?void AsmPrinter::EmitXXStructorList(const Constant *List) { > ? // Should be an array of '{ int, void ()* }' structs. ?The first value is the > - ?// init priority, which we ignore. > + ?// init priority. > ? if (!isa(List)) return; > - ?const ConstantArray *InitList = cast(List); > - ?for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) > - ? ?if (ConstantStruct *CS = dyn_cast(InitList->getOperand(i))){ > - ? ? ?if (CS->getNumOperands() != 2) return; ?// Not array of 2-element structs. > - > - ? ? ?if (CS->getOperand(1)->isNullValue()) > - ? ? ? ?return; ?// Found a null terminator, exit printing. > - ? ? ?// Emit the function pointer. > - ? ? ?EmitGlobalConstant(CS->getOperand(1)); > - ? ?} > + > + ?// Sanity check the structors list. > + ?const ConstantArray *InitList = dyn_cast(List); > + ?if (!InitList) return; // Not an array! > + ?StructType *ETy = dyn_cast(InitList->getType()->getElementType()); > + ?if (!ETy || ETy->getNumElements() != 2) return; // Not an array of pairs! > + ?if (!isa(ETy->getTypeAtIndex(0U)) || > + ? ? ?!isa(ETy->getTypeAtIndex(1U))) return; // Not (int, ptr). > + > + ?// Gather the structors in a form that's convenient for sorting by priority. > + ?SmallVector Structors; > + ?for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) { > + ? ?ConstantStruct *CS = dyn_cast(InitList->getOperand(i)); > + ? ?if (!CS) continue; // Malformed. > + ? ?if (CS->getOperand(1)->isNullValue()) > + ? ? ?break; ?// Found a null terminator, skip the rest. > + ? ?ConstantInt *Priority = dyn_cast(CS->getOperand(0)); > + ? ?if (!Priority) continue; // Malformed. > + ? ?Structors.push_back(std::make_pair(Priority->getLimitedValue(65535), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CS->getOperand(1))); > + ?} > + > + ?// Emit the function pointers in reverse priority order. > + ?std::sort(Structors.rbegin(), Structors.rend(), priority_order); > + ?for (unsigned i = 0, e = Structors.size(); i != e; ++i) > + ? ?EmitGlobalConstant(Structors[i].second); Doesn't this need to use std::stable_sort()? -Eli From baldrick at free.fr Wed Aug 31 12:21:35 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 19:21:35 +0200 Subject: [llvm-commits] [llvm] r138724 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-InitOrder.ll In-Reply-To: References: <20110828131722.BB5362A6C13F@llvm.org> Message-ID: <4E5E6D9F.9080207@free.fr> > Doesn't this need to use std::stable_sort()? I don't see why. It just needs to use a deterministic sort. Ciao, Duncan. From greened at obbligato.org Wed Aug 31 12:30:56 2011 From: greened at obbligato.org (David Greene) Date: Wed, 31 Aug 2011 17:30:56 -0000 Subject: [llvm-commits] [llvm] r138864 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-BlockConstant.ll Message-ID: <20110831173056.53C0D2A6C12C@llvm.org> Author: greened Date: Wed Aug 31 12:30:56 2011 New Revision: 138864 URL: http://llvm.org/viewvc/llvm-project?rev=138864&view=rev Log: Compress Repeated Byte Output Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. Added: llvm/trunk/test/CodeGen/X86/2011-08-29-BlockConstant.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=138864&r1=138863&r2=138864&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Aug 31 12:30:56 2011 @@ -44,6 +44,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/Timer.h" using namespace llvm; @@ -1520,12 +1521,67 @@ static void EmitGlobalConstantImpl(const Constant *C, unsigned AddrSpace, AsmPrinter &AP); +/// isRepeatedByteSequence - Determine whether the given value is +/// composed of a repeated sequence of identical bytes and return the +/// byte value. If it is not a repeated sequence, return -1. +static int isRepeatedByteSequence(const Value *V, TargetMachine &TM) { + + if (const ConstantInt *CI = dyn_cast(V)) { + if (CI->getBitWidth() > 64) return -1; + + uint64_t Size = TM.getTargetData()->getTypeAllocSize(V->getType()); + uint64_t Value = CI->getZExtValue(); + + // Make sure the constant is at least 8 bits long and has a power + // of 2 bit width. This guarantees the constant bit width is + // always a multiple of 8 bits, avoiding issues with padding out + // to Size and other such corner cases. + if (CI->getBitWidth() < 8 || !isPowerOf2_64(CI->getBitWidth())) return -1; + + uint8_t Byte = static_cast(Value); + + for (unsigned i = 1; i < Size; ++i) { + Value >>= 8; + if (static_cast(Value) != Byte) return -1; + } + return Byte; + } + if (const ConstantArray *CA = dyn_cast(V)) { + // Make sure all array elements are sequences of the same repeated + // byte. + if (CA->getNumOperands() == 0) return -1; + + int Byte = isRepeatedByteSequence(CA->getOperand(0), TM); + if (Byte == -1) return -1; + + for (unsigned i = 1, e = CA->getNumOperands(); i != e; ++i) { + int ThisByte = isRepeatedByteSequence(CA->getOperand(i), TM); + if (ThisByte == -1) return -1; + if (Byte != ThisByte) return -1; + } + return Byte; + } + + return -1; +} + static void EmitGlobalConstantArray(const ConstantArray *CA, unsigned AddrSpace, AsmPrinter &AP) { if (AddrSpace != 0 || !CA->isString()) { - // Not a string. Print the values in successive locations - for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) - EmitGlobalConstantImpl(CA->getOperand(i), AddrSpace, AP); + // Not a string. Print the values in successive locations. + + // See if we can aggregate some values. Make sure it can be + // represented as a series of bytes of the constant value. + int Value = isRepeatedByteSequence(CA, AP.TM); + + if (Value != -1) { + unsigned Bytes = AP.TM.getTargetData()->getTypeAllocSize(CA->getType()); + AP.OutStreamer.EmitFill(Bytes, Value, AddrSpace); + } + else { + for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) + EmitGlobalConstantImpl(CA->getOperand(i), AddrSpace, AP); + } return; } Added: llvm/trunk/test/CodeGen/X86/2011-08-29-BlockConstant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-08-29-BlockConstant.ll?rev=138864&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-08-29-BlockConstant.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-08-29-BlockConstant.ll Wed Aug 31 12:30:56 2011 @@ -0,0 +1,34 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + + at x = global [500 x i64] zeroinitializer, align 64 ; <[500 x i64]*> +; CHECK: x: +; CHECK: .zero 4000 + + at y = global [63 x i64] [ + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262, + i64 6799976246779207262, i64 6799976246779207262, i64 6799976246779207262], + align 64 ; <[63 x i64]*> 0x5e5e5e5e +; CHECK: y: +; CHECK: .zero 504,94 From eli.friedman at gmail.com Wed Aug 31 12:32:56 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 10:32:56 -0700 Subject: [llvm-commits] [llvm] r138724 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-InitOrder.ll In-Reply-To: <4E5E6D9F.9080207@free.fr> References: <20110828131722.BB5362A6C13F@llvm.org> <4E5E6D9F.9080207@free.fr> Message-ID: On Wed, Aug 31, 2011 at 10:21 AM, Duncan Sands wrote: >> Doesn't this need to use std::stable_sort()? > > I don't see why. ?It just needs to use a deterministic sort. Oh, wait, right... BTW, does init_priority actually work properly (cross-object) with this patch? -Eli From greened at obbligato.org Wed Aug 31 12:45:39 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 31 Aug 2011 12:45:39 -0500 Subject: [llvm-commits] [PATCH] Compress Repeated Byte Output In-Reply-To: (Chris Lattner's message of "Wed, 31 Aug 2011 09:47:24 -0700") References: <49792adc030c171e70d14a80ff98bbc774e21d3e.1314645441.git.dag@cray.com> Message-ID: Chris Lattner writes: >> Typing loop counters as unsigned can do all sorts of horrible things to >> analysis and optimization due to wraparound requirements. > > This isn't the case for loops that start at a constant and stride by 1. How so? You can't, for example, expect the usual properties of algebra to hold. That disallows all kinds of distributions, reassociations, etc. which in turn can negatively affect the ability to, for example, determine loop dependence information. Yes, these are corner cases but they do crop up -- surprisingly often. > > Is there a specific reason to prefer unsigned? > > The value is unsigned, it conveys intentions more clearly. Conveys to whom or what? It restricts the compiler. If you're ok with that, that's fine but it is something to be aware of. > This is quite consistent in the codebase. Yes, I know. I'm wary of absolute rules like this that work for many cases but cause real (performance) issues in other cases. -Dave From clattner at apple.com Wed Aug 31 12:46:29 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 31 Aug 2011 10:46:29 -0700 Subject: [llvm-commits] [llvm] r138864 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-BlockConstant.ll In-Reply-To: <20110831173056.53C0D2A6C12C@llvm.org> References: <20110831173056.53C0D2A6C12C@llvm.org> Message-ID: <557CB305-5387-4A64-BE6E-AA53F86BFC94@apple.com> On Aug 31, 2011, at 10:30 AM, David Greene wrote: > Author: greened > Date: Wed Aug 31 12:30:56 2011 > New Revision: 138864 > > URL: http://llvm.org/viewvc/llvm-project?rev=138864&view=rev > Log: > Compress Repeated Byte Output > > Emit a repeated sequence of bytes using .zero. This saves an enormous > amount of asm file space for certain programs. Looks good David, one minor thing that I missed before: > + if (Value != -1) { > + unsigned Bytes = AP.TM.getTargetData()->getTypeAllocSize(CA->getType()); > + AP.OutStreamer.EmitFill(Bytes, Value, AddrSpace); > + } "Bytes" should be a uint64_t. Sizes should be 64-bit, even if "index counts" are not. -Chris From ahatanak at gmail.com Wed Aug 31 12:49:04 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 31 Aug 2011 17:49:04 -0000 Subject: [llvm-commits] [llvm] r138866 - /llvm/trunk/lib/Target/Mips/InstPrinter/Makefile Message-ID: <20110831174904.65F7F2A6C12C@llvm.org> Author: ahatanak Date: Wed Aug 31 12:49:04 2011 New Revision: 138866 URL: http://llvm.org/viewvc/llvm-project?rev=138866&view=rev Log: Fix typo. Patch by Liu. Modified: llvm/trunk/lib/Target/Mips/InstPrinter/Makefile Modified: llvm/trunk/lib/Target/Mips/InstPrinter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/Makefile?rev=138866&r1=138865&r2=138866&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/Makefile (original) +++ llvm/trunk/lib/Target/Mips/InstPrinter/Makefile Wed Aug 31 12:49:04 2011 @@ -10,7 +10,7 @@ LEVEL = ../../../.. LIBRARYNAME = LLVMMipsAsmPrinter -# Hack: we need to include 'main' arm target directory to grab private headers +# Hack: we need to include 'main' mips target directory to grab private headers CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. include $(LEVEL)/Makefile.common From eli.friedman at gmail.com Wed Aug 31 12:52:22 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 17:52:22 -0000 Subject: [llvm-commits] [llvm] r138868 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-64bit.ll Message-ID: <20110831175222.DBEA22A6C12C@llvm.org> Author: efriedma Date: Wed Aug 31 12:52:22 2011 New Revision: 138868 URL: http://llvm.org/viewvc/llvm-project?rev=138868&view=rev Log: 64-bit atomic cmpxchg for ARM. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=138868&r1=138867&r2=138868&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Aug 31 12:52:22 2011 @@ -2312,16 +2312,20 @@ } SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { - SDValue Chain = Node->getOperand(0); - SDValue In1 = Node->getOperand(1); - SDValue In2L = Node->getOperand(2); - SDValue In2H = Node->getOperand(3); + SmallVector Ops; + Ops.push_back(Node->getOperand(1)); // Ptr + Ops.push_back(Node->getOperand(2)); // Low part of Val1 + Ops.push_back(Node->getOperand(3)); // High part of Val1 + if (Opc == ARM::ATOMCMPXCHG6432) { + Ops.push_back(Node->getOperand(4)); // Low part of Val2 + Ops.push_back(Node->getOperand(5)); // High part of Val2 + } + Ops.push_back(Node->getOperand(0)); // Chain MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = cast(Node)->getMemOperand(); - const SDValue Ops[] = { In1, In2L, In2H, Chain}; SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), - MVT::i32, MVT::i32, MVT::Other, Ops, - array_lengthof(Ops)); + MVT::i32, MVT::i32, MVT::Other, + Ops.data() ,Ops.size()); cast(ResNode)->setMemRefs(MemOp, MemOp + 1); return ResNode; } @@ -3121,6 +3125,8 @@ return SelectAtomic64(N, ARM::ATOMAND6432); case ARMISD::ATOMSWAP64_DAG: return SelectAtomic64(N, ARM::ATOMSWAP6432); + case ARMISD::ATOMCMPXCHG64_DAG: + return SelectAtomic64(N, ARM::ATOMCMPXCHG6432); } return SelectCode(N); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=138868&r1=138867&r2=138868&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 31 12:52:22 2011 @@ -618,6 +618,7 @@ setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. setInsertFencesForAtomic(true); } else { @@ -4854,24 +4855,34 @@ } static void -ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl& Results, - SelectionDAG &DAG, unsigned NewOp) { +ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl& Results, + SelectionDAG &DAG, unsigned NewOp) { EVT T = Node->getValueType(0); DebugLoc dl = Node->getDebugLoc(); assert (T == MVT::i64 && "Only know how to expand i64 atomics"); - SDValue Chain = Node->getOperand(0); - SDValue In1 = Node->getOperand(1); - SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - Node->getOperand(2), DAG.getIntPtrConstant(0)); - SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - Node->getOperand(2), DAG.getIntPtrConstant(1)); - SDValue Ops[] = { Chain, In1, In2L, In2H }; + SmallVector Ops; + Ops.push_back(Node->getOperand(0)); // Chain + Ops.push_back(Node->getOperand(1)); // Ptr + // Low part of Val1 + Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(2), DAG.getIntPtrConstant(0))); + // High part of Val1 + Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(2), DAG.getIntPtrConstant(1))); + if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { + // High part of Val1 + Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(3), DAG.getIntPtrConstant(0))); + // High part of Val2 + Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Node->getOperand(3), DAG.getIntPtrConstant(1))); + } SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); SDValue Result = - DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, + DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, cast(Node)->getMemOperand()); - SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; + SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); Results.push_back(Result.getValue(2)); } @@ -4949,28 +4960,29 @@ Res = Expand64BitShift(N, DAG, Subtarget); break; case ISD::ATOMIC_LOAD_ADD: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); return; case ISD::ATOMIC_LOAD_AND: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); return; case ISD::ATOMIC_LOAD_NAND: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); return; case ISD::ATOMIC_LOAD_OR: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); return; case ISD::ATOMIC_LOAD_SUB: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); return; case ISD::ATOMIC_LOAD_XOR: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); return; case ISD::ATOMIC_SWAP: - ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); + return; + case ISD::ATOMIC_CMP_SWAP: + ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); return; - //case ISD::ATOMIC_CMP_SWAP: - // ReplaceATOMIC_CMPXCHG_64(N, Results, DAG); } if (Res.getNode()) Results.push_back(Res); @@ -5293,7 +5305,7 @@ MachineBasicBlock * ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, unsigned Op1, unsigned Op2, - bool NeedsCarry) const { + bool NeedsCarry, bool IsCmpxchg) const { // This also handles ATOMIC_SWAP, indicated by Op1==0. const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); @@ -5321,8 +5333,17 @@ unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *contBB, *cont2BB; + if (IsCmpxchg) { + contBB = MF->CreateMachineBasicBlock(LLVM_BB); + cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); + } MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); MF->insert(It, loopMBB); + if (IsCmpxchg) { + MF->insert(It, contBB); + MF->insert(It, cont2BB); + } MF->insert(It, exitMBB); // Transfer the remainder of BB and its successor edges to exitMBB. @@ -5363,7 +5384,27 @@ // Copy r2/r3 into dest. (This copy will normally be coalesced.) BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); - if (Op1) { + + if (IsCmpxchg) { + // Add early exit + for (unsigned i = 0; i < 2; i++) { + AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : + ARM::CMPrr)) + .addReg(i == 0 ? destlo : desthi) + .addReg(i == 0 ? vallo : valhi)); + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) + .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); + BB->addSuccessor(exitMBB); + BB->addSuccessor(i == 0 ? contBB : cont2BB); + BB = (i == 0 ? contBB : cont2BB); + } + + // Copy to physregs for strexd + unsigned setlo = MI->getOperand(5).getReg(); + unsigned sethi = MI->getOperand(6).getReg(); + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); + BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); + } else if (Op1) { // Perform binary operation AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) .addReg(destlo).addReg(vallo)) @@ -5537,21 +5578,27 @@ case ARM::ATOMADD6432: return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, - isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, true); + isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, + /*NeedsCarry*/ true); case ARM::ATOMSUB6432: return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, - isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, true); + isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, + /*NeedsCarry*/ true); case ARM::ATOMOR6432: return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, - isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, false); + isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); case ARM::ATOMXOR6432: return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, - isThumb2 ? ARM::t2EORrr : ARM::EORrr, false); + isThumb2 ? ARM::t2EORrr : ARM::EORrr); case ARM::ATOMAND6432: return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, - isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, false); + isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); case ARM::ATOMSWAP6432: return EmitAtomicBinary64(MI, BB, 0, 0, false); + case ARM::ATOMCMPXCHG6432: + return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, + isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, + /*NeedsCarry*/ false, /*IsCmpxchg*/true); case ARM::tMOVCCr_pseudo: { // To "insert" a SELECT_CC instruction, we actually have to insert the Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=138868&r1=138867&r2=138868&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Aug 31 12:52:22 2011 @@ -507,7 +507,8 @@ MachineBasicBlock *BB, unsigned Op1, unsigned Op2, - bool NeedsCarry) const; + bool NeedsCarry = false, + bool IsCmpxchg = false) const; MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138868&r1=138867&r2=138868&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Aug 31 12:52:22 2011 @@ -69,8 +69,6 @@ def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; -def SDTARMatomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, - SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, [SDTCisSameAs<0, 2>, @@ -1635,6 +1633,10 @@ def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), (ins GPR:$addr, GPR:$src1, GPR:$src2), NoItinerary, []>; +def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), + (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2, + GPR:$set1, GPR:$set2), + NoItinerary, []>; } def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>, Modified: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll?rev=138868&r1=138867&r2=138868&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Wed Aug 31 12:52:22 2011 @@ -81,3 +81,18 @@ %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst ret i64 %r } + +define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { +; CHECK: test7 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: cmp r2 +; CHECK: cmpeq r3 +; CHECK: bne +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst + ret i64 %r +} From dpatel at apple.com Wed Aug 31 13:04:31 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 31 Aug 2011 18:04:31 -0000 Subject: [llvm-commits] [llvm] r138869 - /llvm/trunk/lib/Analysis/DebugInfo.cpp Message-ID: <20110831180431.87A0E2A6C12C@llvm.org> Author: dpatel Date: Wed Aug 31 13:04:31 2011 New Revision: 138869 URL: http://llvm.org/viewvc/llvm-project?rev=138869&view=rev Log: After r138010, subroutine type does not have context info. Update type verifier accordingly. This fixes ptype.exp gdb testsuite regressions. Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=138869&r1=138868&r2=138869&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Aug 31 13:04:31 2011 @@ -367,6 +367,7 @@ Tag != dwarf::DW_TAG_reference_type && Tag != dwarf::DW_TAG_restrict_type && Tag != dwarf::DW_TAG_vector_type && Tag != dwarf::DW_TAG_array_type && Tag != dwarf::DW_TAG_enumeration_type + && Tag != dwarf::DW_TAG_subroutine_type && getFilename().empty()) return false; return true; From krasin at chromium.org Wed Aug 31 13:16:07 2011 From: krasin at chromium.org (Ivan Krasin) Date: Wed, 31 Aug 2011 11:16:07 -0700 Subject: [llvm-commits] [PATCH]llvm-ld: add support of deps with the specific version (like liblzma.so.1.0.0) In-Reply-To: References: Message-ID: Friendly ping. On Mon, Aug 29, 2011 at 1:58 PM, Ivan Krasin wrote: > Hi llvm team! > > This CL adds support of deps which does not end with ".so" to llvm-ld. > It happens (for example) when you want to have a dependency on the .so > with the specific version, like liblzma.so.1.0.0 or > libcrypto.so.0.9.8. > > The patch is attached and is also available online: > http://codereview.chromium.org/7793002/ > > Please, let me know if it's fine to commit. > > -- krasin > From grosbach at apple.com Wed Aug 31 13:23:08 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 18:23:08 -0000 Subject: [llvm-commits] [llvm] r138871 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20110831182308.5F8BC2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 13:23:08 2011 New Revision: 138871 URL: http://llvm.org/viewvc/llvm-project?rev=138871&view=rev Log: Thumb2 parsing and encoding for ADC(register). Also add instruction aliases for non-.w versions of SBC since they're the same. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138871&r1=138870&r2=138871&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 31 13:23:08 2011 @@ -35,8 +35,9 @@ [shl,srl,sra,rotr]> { let EncoderMethod = "getT2SORegOpValue"; let PrintMethod = "printT2SOOperand"; - let MIOperandInfo = (ops rGPR, i32imm); let DecoderMethod = "DecodeSORegImmOperand"; + let ParserMatchClass = ShiftedImmAsmOperand; + let MIOperandInfo = (ops rGPR, i32imm); } // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value @@ -3490,3 +3491,23 @@ (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>; def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; + + +//===----------------------------------------------------------------------===// +// Assembler aliases +// + +// Aliases for ADC without the ".w" optional width specifier. +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", + (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", + (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, + pred:$p, cc_out:$s)>; + +// Aliases for SBC without the ".w" optional width specifier. +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", + (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", + (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, + pred:$p, cc_out:$s)>; + Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=138871&r1=138870&r2=138871&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Aug 31 13:23:08 2011 @@ -38,6 +38,28 @@ @ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64] @------------------------------------------------------------------------------ +@ ADC (register) + at ------------------------------------------------------------------------------ + adc r4, r5, r6 + adcs r4, r5, r6 + adc.w r9, r1, r3 + adcs.w r9, r1, r3 + adc r0, r1, r3, ror #4 + adcs r0, r1, r3, lsl #7 + adc.w r0, r1, r3, lsr #31 + adcs.w r0, r1, r3, asr #32 + +@ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04] +@ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04] +@ CHECK: adc.w r9, r1, r3 @ encoding: [0x41,0xeb,0x03,0x09] +@ CHECK: adcs.w r9, r1, r3 @ encoding: [0x51,0xeb,0x03,0x09] +@ CHECK: adc.w r0, r1, r3, ror #4 @ encoding: [0x41,0xeb,0x33,0x10] +@ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] +@ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70] +@ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00] + + + at ------------------------------------------------------------------------------ @ CBZ/CBNZ @------------------------------------------------------------------------------ cbnz r7, #6 From eli.friedman at gmail.com Wed Aug 31 13:26:09 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 18:26:09 -0000 Subject: [llvm-commits] [llvm] r138872 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h test/CodeGen/ARM/atomic-64bit.ll Message-ID: <20110831182609.45A302A6C12C@llvm.org> Author: efriedma Date: Wed Aug 31 13:26:09 2011 New Revision: 138872 URL: http://llvm.org/viewvc/llvm-project?rev=138872&view=rev Log: Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=138872&r1=138871&r2=138872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Aug 31 13:26:09 2011 @@ -1057,6 +1057,7 @@ case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; + case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break; case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: @@ -2323,6 +2324,20 @@ } } +void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N, + SDValue &Lo, SDValue &Hi) { + DebugLoc dl = N->getDebugLoc(); + EVT VT = cast(N)->getMemoryVT(); + SDValue Zero = DAG.getConstant(0, VT); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, + N->getOperand(0), + N->getOperand(1), Zero, Zero, + cast(N)->getMemOperand(), + cast(N)->getOrdering(), + cast(N)->getSynchScope()); + ReplaceValueWith(SDValue(N, 0), Swap.getValue(0)); + ReplaceValueWith(SDValue(N, 1), Swap.getValue(1)); +} //===----------------------------------------------------------------------===// // Integer Operand Expansion @@ -2367,6 +2382,8 @@ case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; case ISD::RETURNADDR: case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; + + case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break; } // If the result is null, the sub-method took care of registering results etc. @@ -2744,6 +2761,19 @@ return MakeLibCall(LC, DstVT, &Op, 1, true, dl); } +SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); + SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, + cast(N)->getMemoryVT(), + N->getOperand(0), + N->getOperand(1), N->getOperand(2), + cast(N)->getMemOperand(), + cast(N)->getOrdering(), + cast(N)->getSynchScope()); + return Swap.getValue(1); +} + + SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { SDValue InOp0 = N->getOperand(0); EVT InVT = InOp0.getValueType(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=138872&r1=138871&r2=138872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Aug 31 13:26:09 2011 @@ -320,6 +320,8 @@ void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi); + void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi); + void ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi); bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi); @@ -339,6 +341,7 @@ SDValue ExpandIntOp_TRUNCATE(SDNode *N); SDValue ExpandIntOp_UINT_TO_FP(SDNode *N); SDValue ExpandIntOp_RETURNADDR(SDNode *N); + SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N); void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, DebugLoc dl); Modified: llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll?rev=138872&r1=138871&r2=138872&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-64bit.ll Wed Aug 31 13:26:09 2011 @@ -6,7 +6,7 @@ ; CHECK: ldrexd r2, r3 ; CHECK: adds r0, r2 ; CHECK: adc r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -20,7 +20,7 @@ ; CHECK: ldrexd r2, r3 ; CHECK: subs r0, r2 ; CHECK: sbc r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -34,7 +34,7 @@ ; CHECK: ldrexd r2, r3 ; CHECK: and r0, r2 ; CHECK: and r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -48,7 +48,7 @@ ; CHECK: ldrexd r2, r3 ; CHECK: orr r0, r2 ; CHECK: orr r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -62,7 +62,7 @@ ; CHECK: ldrexd r2, r3 ; CHECK: eor r0, r2 ; CHECK: eor r1, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -74,7 +74,7 @@ ; CHECK: test6 ; CHECK: dmb ish ; CHECK: ldrexd r2, r3 -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish @@ -89,10 +89,40 @@ ; CHECK: cmp r2 ; CHECK: cmpeq r3 ; CHECK: bne -; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 ; CHECK: cmp ; CHECK: bne ; CHECK: dmb ish %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst ret i64 %r } + +; Compiles down to cmpxchg +; FIXME: Should compile to a single ldrexd +define i64 @test8(i64* %ptr) { +; CHECK: test8 +; CHECK: ldrexd r2, r3 +; CHECK: cmp r2 +; CHECK: cmpeq r3 +; CHECK: bne +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = load atomic i64* %ptr seq_cst, align 8 + ret i64 %r +} + +; Compiles down to atomicrmw xchg; there really isn't any more efficient +; way to write it. +define void @test9(i64* %ptr, i64 %val) { +; CHECK: test9 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: strexd {{[a-z0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + store atomic i64 %val, i64* %ptr seq_cst, align 8 + ret void +} From evan.cheng at apple.com Wed Aug 31 13:28:46 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 31 Aug 2011 11:28:46 -0700 Subject: [llvm-commits] [llvm] r138810 - in /llvm/trunk: include/llvm/MC/MCInstrDesc.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/InstrEmitter.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/AR In-Reply-To: References: Message-ID: This is a test (which does i256 math) where the ARM backend just can't handle yet. The only solution for now is to xfail it. Are there others? Evan On Aug 31, 2011, at 10:01 AM, Benjamin Kramer wrote: > On Tue, Aug 30, 2011 at 12:09, Evan Cheng wrote: >> Author: evancheng >> Date: Tue Aug 30 14:09:48 2011 >> New Revision: 138810 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=138810&view=rev >> Log: >> Follow up to r138791. >> >> Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to >> call a target hook to adjust the instruction. For ARM, this is used to >> adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC >> instructions have implicit def of CPSR (required since it now uses CPSR physical >> register dependency rather than "glue"). If the carry flag is used, then the >> target hook will *fill in* the optional operand with CPSR. Otherwise, the hook >> will remove the CPSR implicit def from the MachineInstr. > > Hi Evan, > > looks like this (or your previous patch) breaks some tests on arm: > > $ llc < test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll -march=arm > LLVM ERROR: Can't handle live physical register dependency! > > - Ben From grosbach at apple.com Wed Aug 31 13:29:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 18:29:05 -0000 Subject: [llvm-commits] [llvm] r138873 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110831182905.71EE62A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 13:29:05 2011 New Revision: 138873 URL: http://llvm.org/viewvc/llvm-project?rev=138873&view=rev Log: tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138873&r1=138872&r2=138873&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 31 13:29:05 2011 @@ -3337,10 +3337,10 @@ "', but expected '" + ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); } - // Check for non-'al' condition codes outside of the IT block. + // Check for non-'al' condition codes outside of the IT block. } else if (isThumbTwo() && MCID.isPredicable() && Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != - ARMCC::AL) + ARMCC::AL && Inst.getOpcode() != ARM::tBcc) return Error(Loc, "predicated instructions must be in IT block"); switch (Inst.getOpcode()) { From resistor at mac.com Wed Aug 31 13:30:20 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 31 Aug 2011 18:30:20 -0000 Subject: [llvm-commits] [llvm] r138874 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110831183020.EAD9C2A6C12C@llvm.org> Author: resistor Date: Wed Aug 31 13:30:20 2011 New Revision: 138874 URL: http://llvm.org/viewvc/llvm-project?rev=138874&view=rev Log: Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138874&r1=138873&r2=138874&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Aug 31 13:30:20 2011 @@ -465,11 +465,34 @@ return 0; } +// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are +// determined by negating them and XOR'ing them with bit 23. +static int32_t encodeThumbBLOffset(int32_t offset) { + offset >>= 1; + uint32_t S = (offset & 0x800000) >> 23; + uint32_t J1 = (offset & 0x400000) >> 22; + uint32_t J2 = (offset & 0x200000) >> 21; + J1 = (~J1 & 0x1); + J2 = (~J2 & 0x1); + J1 ^= S; + J2 ^= S; + + offset &= ~0x600000; + offset |= J1 << 22; + offset |= J2 << 21; + + return offset; +} + /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. uint32_t ARMMCCodeEmitter:: getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, + Fixups); + return encodeThumbBLOffset(MO.getImm()); } /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate @@ -477,7 +500,11 @@ uint32_t ARMMCCodeEmitter:: getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, + Fixups); + return encodeThumbBLOffset(MO.getImm()); } /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. @@ -486,7 +513,8 @@ SmallVectorImpl &Fixups) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, + Fixups); return (MO.getImm() >> 1); } Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138874&r1=138873&r2=138874&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 31 13:30:20 2011 @@ -118,6 +118,15 @@ @ CHECK: b #-420 @ encoding: [0x2e,0xe7] @------------------------------------------------------------------------------ +@ BL/BLX + at ------------------------------------------------------------------------------ + blx #884800 + blx #1769600 + +@ CHECK: blx #884800 @ encoding: [0xd8,0xf0,0x20,0xe8] +@ CHECK: blx #1769600 @ encoding: [0xb0,0xf1,0x40,0xe8] + + at ------------------------------------------------------------------------------ @ BICS @------------------------------------------------------------------------------ bics r1, r6 From benny.kra at googlemail.com Wed Aug 31 13:32:08 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 31 Aug 2011 11:32:08 -0700 Subject: [llvm-commits] [llvm] r138810 - in /llvm/trunk: include/llvm/MC/MCInstrDesc.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/InstrEmitter.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/AR In-Reply-To: References: Message-ID: On Wed, Aug 31, 2011 at 11:28, Evan Cheng wrote: > This is a test (which does i256 math) where the ARM backend just can't handle yet. The only solution for now is to xfail it. Are there others? I didn't see any other tests fail. - Ben From grosbach at apple.com Wed Aug 31 13:35:47 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 18:35:47 -0000 Subject: [llvm-commits] [llvm] r138876 - /llvm/trunk/test/MC/ARM/thumb-nop.s Message-ID: <20110831183547.20EB62A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 13:35:46 2011 New Revision: 138876 URL: http://llvm.org/viewvc/llvm-project?rev=138876&view=rev Log: Thumb NOP encoding varies depending on ARCH revision. Added: llvm/trunk/test/MC/ARM/thumb-nop.s Added: llvm/trunk/test/MC/ARM/thumb-nop.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-nop.s?rev=138876&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/thumb-nop.s (added) +++ llvm/trunk/test/MC/ARM/thumb-nop.s Wed Aug 31 13:35:46 2011 @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s -check-prefix=CHECK-V6 +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s -check-prefix=CHECK-V7 + + .syntax unified + + nop + +@ CHECK-V6: nop @ encoding: [0xc0,0x46] +@ CHECK-V7: nop @ encoding: [0x00,0xbf] From eli.friedman at gmail.com Wed Aug 31 13:36:04 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 18:36:04 -0000 Subject: [llvm-commits] [llvm] r138877 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp Message-ID: <20110831183604.DA3C62A6C12C@llvm.org> Author: efriedma Date: Wed Aug 31 13:36:04 2011 New Revision: 138877 URL: http://llvm.org/viewvc/llvm-project?rev=138877&view=rev Log: Fill in type legalization for MERGE_VALUES in all the various cases. Patch by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Wed Aug 31 13:36:04 2011 @@ -55,6 +55,7 @@ #endif llvm_unreachable("Do not know how to soften the result of this operator!"); + case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N); break; case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; case ISD::ConstantFP: @@ -107,6 +108,13 @@ return BitConvertToInteger(N->getOperand(0)); } +SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N) { + SDValue Op = DecomposeMERGE_VALUES(N); + return Op.getValueType().isVector() ? + BitConvertVectorToIntegerVector(Op) : + BitConvertToInteger(Op); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) { // Convert the inputs to integers, and build a new pair out of them. return DAG.getNode(ISD::BUILD_PAIR, N->getDebugLoc(), @@ -827,11 +835,11 @@ #endif llvm_unreachable("Do not know how to expand the result of this operator!"); - case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; + case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Aug 31 13:36:04 2011 @@ -48,6 +48,7 @@ N->dump(&DAG); dbgs() << "\n"; #endif llvm_unreachable("Do not know how to promote this operator!"); + case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N); break; case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; @@ -136,6 +137,13 @@ SetPromotedInteger(SDValue(N, ResNo), Res); } +SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N) { + SDValue Op = DecomposeMERGE_VALUES(N); + assert(Op.getValueType().isInteger() + && "Must decompose to an integer type!"); + return GetPromotedInteger(Op); +} + SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { // Sign-extend the new bits, and continue the assertion. SDValue Op = SExtPromotedInteger(N->getOperand(0)); @@ -1548,6 +1556,13 @@ // use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } +void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, + SDValue &Lo, SDValue &Hi) { + SDValue Res = DecomposeMERGE_VALUES(N); + assert(Res.getValueType().isInteger() + && "Cannot split a non-integer value."); + SplitInteger(Res, Lo, Hi); +} void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Wed Aug 31 13:36:04 2011 @@ -946,6 +946,25 @@ return true; } +SDValue DAGTypeLegalizer::DecomposeMERGE_VALUES(SDNode *N) { + unsigned i; + // A MERGE_VALUES node can produce any number of values. + // We know that the first illegal type needs to be handled. + for (i = 0; isTypeLegal(N->getValueType(i)); ++i) + ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); + + // The first illegal result must be the one that needs to be handled. + SDValue BadValue = N->getOperand(i); + + // Legalize the rest of the results into the input operands whether they + // are legal or not. + unsigned e = N->getNumValues(); + for (++i; i != e; ++i) + ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); + + return BadValue; +} + /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type /// which is split into two not necessarily identical pieces. void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Aug 31 13:36:04 2011 @@ -148,12 +148,20 @@ SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); bool CustomWidenLowerNode(SDNode *N, EVT VT); + + // DecomposeMERGE_VALUES takes a SDNode and returns the first + // illegal operand that needs to be modified. + // All other nodes are legalized, whether they are legal or not. + // The resulting SDValue needs to be modified to make it legal. + SDValue DecomposeMERGE_VALUES(SDNode *N); + SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index); SDValue JoinIntegers(SDValue Lo, SDValue Hi); SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl); + std::pair ExpandChainLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); std::pair ExpandAtomic(SDNode *Node); @@ -206,6 +214,7 @@ // Integer Result Promotion. void PromoteIntegerResult(SDNode *N, unsigned ResNo); + SDValue PromoteIntRes_MERGE_VALUES(SDNode *N); SDValue PromoteIntRes_AssertSext(SDNode *N); SDValue PromoteIntRes_AssertZext(SDNode *N); SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); @@ -289,6 +298,7 @@ // Integer Result Expansion. void ExpandIntegerResult(SDNode *N, unsigned ResNo); + void ExpandIntRes_MERGE_VALUES (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi); @@ -365,6 +375,7 @@ // Result Float to Integer Conversion. void SoftenFloatResult(SDNode *N, unsigned OpNo); + SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N); SDValue SoftenFloatRes_BITCAST(SDNode *N); SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N); SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N); @@ -491,6 +502,7 @@ // Vector Result Scalarization: <1 x ty> -> ty. void ScalarizeVectorResult(SDNode *N, unsigned OpNo); + SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N); SDValue ScalarizeVecRes_BinOp(SDNode *N); SDValue ScalarizeVecRes_UnaryOp(SDNode *N); SDValue ScalarizeVecRes_InregOp(SDNode *N); @@ -584,6 +596,7 @@ // Widen Vector Result Promotion. void WidenVectorResult(SDNode *N, unsigned ResNo); + SDValue WidenVecRes_MERGE_VALUES(SDNode* N); SDValue WidenVecRes_BITCAST(SDNode* N); SDValue WidenVecRes_BUILD_VECTOR(SDNode* N); SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N); @@ -702,6 +715,7 @@ } // Generic Result Expansion. + void ExpandRes_MERGE_VALUES (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Wed Aug 31 13:36:04 2011 @@ -31,6 +31,11 @@ // These routines assume that the Lo/Hi part is stored first in memory on // little/big-endian machines, followed by the Hi/Lo part. This means that // they cannot be used as is on vectors, for which Lo is always stored first. +void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, + SDValue &Lo, SDValue &Hi) { + SDValue Op = DecomposeMERGE_VALUES(N); + GetExpandedOp(Op, Lo, Hi); +} void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { EVT OutVT = N->getValueType(0); @@ -428,23 +433,8 @@ void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, SDValue &Lo, SDValue &Hi) { - // A MERGE_VALUES node can produce any number of values. We know that the - // first illegal one needs to be expanded into Lo/Hi. - unsigned i; - - // The string of legal results gets turned into input operands, which have - // the same type. - for (i = 0; isTypeLegal(N->getValueType(i)); ++i) - ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); - - // The first illegal result must be the one that needs to be expanded. - GetSplitOp(N->getOperand(i), Lo, Hi); - - // Legalize the rest of the results into the input operands whether they are - // legal or not. - unsigned e = N->getNumValues(); - for (++i; i != e; ++i) - ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); + SDValue Op = DecomposeMERGE_VALUES(N); + GetSplitOp(Op, Lo, Hi); } void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=138877&r1=138876&r2=138877&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Aug 31 13:36:04 2011 @@ -47,6 +47,7 @@ report_fatal_error("Do not know how to scalarize the result of this " "operator!\n"); + case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N); break; case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; case ISD::BUILD_VECTOR: R = N->getOperand(0); break; case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; @@ -130,6 +131,11 @@ LHS.getValueType(), LHS, RHS); } +SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N) { + SDValue Op = DecomposeMERGE_VALUES(N); + return GetScalarizedVector(Op); +} + SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { EVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), @@ -1205,6 +1211,7 @@ #endif llvm_unreachable("Do not know how to widen the result of this operator!"); + case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N); break; case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; @@ -1557,6 +1564,12 @@ WidenVT, WidenLHS, DAG.getValueType(ExtVT)); } +SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N) +{ + SDValue WidenVec = DecomposeMERGE_VALUES(N); + return GetWidenedVector(WidenVec); +} + SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { SDValue InOp = N->getOperand(0); EVT InVT = InOp.getValueType(); From eli.friedman at gmail.com Wed Aug 31 13:37:31 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 11:37:31 -0700 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References: <4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: r138877. -Eli On Tue, Aug 30, 2011 at 6:45 PM, Villmow, Micah wrote: > Here is a combined patch. > >> -----Original Message----- >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> Sent: Tuesday, August 30, 2011 1:09 PM >> To: Villmow, Micah >> Cc: Tobias Grosser; llvm-commits >> Subject: Re: [llvm-commits] Patch to add support for >> WidenVecRes_MERGE_VALUES >> >> On Tue, Aug 30, 2011 at 1:06 PM, Villmow, Micah >> wrote: >> > Eli, >> > ?So for the other cases, it would just be call DecomposeMERGE_VALUES >> and then call the correct >> > legalization function on the return value, correct? >> >> Yes. >> >> > I'll send a second patch with those later. >> >> Great, thanks. >> >> -Eli >> >> > Micah >> > >> >> -----Original Message----- >> >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> >> Sent: Tuesday, August 30, 2011 12:56 PM >> >> To: Tobias Grosser >> >> Cc: Villmow, Micah; llvm-commits >> >> Subject: Re: [llvm-commits] Patch to add support for >> >> WidenVecRes_MERGE_VALUES >> >> >> >> On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser >> >> wrote: >> >> > On 08/30/2011 01:04 PM, Villmow, Micah wrote: >> >> >> >> >> >> Thanks for the feedback, new revision attached. >> >> > >> >> > There seems one unneeded white space change. (Can be fixed on >> commit) >> >> > >> >> >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, >> >> >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool >> >> isSigned, >> >> >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); >> >> >> + >> >> >> ? ? ? ?std::pair >> >> ExpandChainLibCall(RTLIB::Libcall >> >> > >> >> > Otherwise, it looks good. Let's see if Eli has any additional >> >> comments. >> >> >> >> Looks fine. >> >> >> >> Note that it would be nice to make sure we implement MERGE_VALUES >> for >> >> all the other cases in type legalization... (integer promotion, >> vector >> >> scalarization, etc.) >> >> >> >> -Eli >> > >> > >> > > > From grosbach at apple.com Wed Aug 31 13:39:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 18:39:40 -0000 Subject: [llvm-commits] [llvm] r138879 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110831183940.1642B2A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 13:39:39 2011 New Revision: 138879 URL: http://llvm.org/viewvc/llvm-project?rev=138879&view=rev Log: Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. When we want encoding T3 (the wide encoding), we can explicitly check for that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly handle encodings T1 and T2 when in Thumb2 mode. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138879&r1=138878&r2=138879&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 31 13:39:39 2011 @@ -3004,9 +3004,7 @@ Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" || - // FIXME: We need a better way. This really confused Thumb2 - // parsing for 'mov'. - (Mnemonic == "mov" && !isThumbOne())) { + (Mnemonic == "mov" && !isThumb())) { CanAcceptCarrySet = true; } else { CanAcceptCarrySet = false; From eli.friedman at gmail.com Wed Aug 31 13:37:31 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 11:37:31 -0700 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References: <4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: r138877. -Eli On Tue, Aug 30, 2011 at 6:45 PM, Villmow, Micah wrote: > Here is a combined patch. > >> -----Original Message----- >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> Sent: Tuesday, August 30, 2011 1:09 PM >> To: Villmow, Micah >> Cc: Tobias Grosser; llvm-commits >> Subject: Re: [llvm-commits] Patch to add support for >> WidenVecRes_MERGE_VALUES >> >> On Tue, Aug 30, 2011 at 1:06 PM, Villmow, Micah >> wrote: >> > Eli, >> > ?So for the other cases, it would just be call DecomposeMERGE_VALUES >> and then call the correct >> > legalization function on the return value, correct? >> >> Yes. >> >> > I'll send a second patch with those later. >> >> Great, thanks. >> >> -Eli >> >> > Micah >> > >> >> -----Original Message----- >> >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> >> Sent: Tuesday, August 30, 2011 12:56 PM >> >> To: Tobias Grosser >> >> Cc: Villmow, Micah; llvm-commits >> >> Subject: Re: [llvm-commits] Patch to add support for >> >> WidenVecRes_MERGE_VALUES >> >> >> >> On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser >> >> wrote: >> >> > On 08/30/2011 01:04 PM, Villmow, Micah wrote: >> >> >> >> >> >> Thanks for the feedback, new revision attached. >> >> > >> >> > There seems one unneeded white space change. (Can be fixed on >> commit) >> >> > >> >> >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, >> >> >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool >> >> isSigned, >> >> >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); >> >> >> + >> >> >> ? ? ? ?std::pair >> >> ExpandChainLibCall(RTLIB::Libcall >> >> > >> >> > Otherwise, it looks good. Let's see if Eli has any additional >> >> comments. >> >> >> >> Looks fine. >> >> >> >> Note that it would be nice to make sure we implement MERGE_VALUES >> for >> >> all the other cases in type legalization... (integer promotion, >> vector >> >> scalarization, etc.) >> >> >> >> -Eli >> > >> > >> > > > From gkistanova at gmail.com Wed Aug 31 14:24:19 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Wed, 31 Aug 2011 19:24:19 -0000 Subject: [llvm-commits] [zorg] r138882 - in /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py Message-ID: <20110831192419.B8EF52A6C12C@llvm.org> Author: gkistanova Date: Wed Aug 31 14:24:19 2011 New Revision: 138882 URL: http://llvm.org/viewvc/llvm-project?rev=138882&view=rev Log: Remove tests from the builder. Cosmetic changes. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=138882&r1=138881&r2=138882&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Aug 31 14:24:19 2011 @@ -305,7 +305,7 @@ 'slavenames':["kistanova8"], 'builddir':"clang-native-mingw32-win7", 'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-mingw32', - useTwoStage=True, + useTwoStage=True, test=False, stage1_config='Release+Asserts', stage2_config='Release+Asserts'), 'category' : 'clang'}, Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=138882&r1=138881&r2=138882&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Wed Aug 31 14:24:19 2011 @@ -60,8 +60,8 @@ # Ubuntu pandaboard cortex-a9 create_slave("kistanova6", properties={'jobs' : 2}, max_builds=1), - # FreeBSD 8.2 X86_64 - create_slave("kistanova7", properties={'jobs' : 2}, max_builds=1), + # FreeBSD 8.2 X86_64 + create_slave("kistanova7", properties={'jobs' : 2}, max_builds=1), # Windows 7 Ultimate create_slave("kistanova8", properties={'jobs' : 1}, max_builds=1), From baldrick at free.fr Wed Aug 31 14:46:18 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 31 Aug 2011 21:46:18 +0200 Subject: [llvm-commits] [llvm] r138877 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp In-Reply-To: <20110831183604.DA3C62A6C12C@llvm.org> References: <20110831183604.DA3C62A6C12C@llvm.org> Message-ID: <4E5E8F8A.2070700@free.fr> Hi Eli, > +SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N) { > + SDValue Op = DecomposeMERGE_VALUES(N); > + return Op.getValueType().isVector() ? > + BitConvertVectorToIntegerVector(Op) : > + BitConvertToInteger(Op); how can you get a vector here? > +SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N) { > + SDValue Op = DecomposeMERGE_VALUES(N); > + assert(Op.getValueType().isInteger() > +&& "Must decompose to an integer type!"); Here this might be a vector of integers, so I think this assertion is wrong. (For the moment you need to pass the -promote-elements flag to llc to have vectors turn up in the integer promotion code). > + return GetPromotedInteger(Op); > +} > + > SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { > // Sign-extend the new bits, and continue the assertion. > SDValue Op = SExtPromotedInteger(N->getOperand(0)); > @@ -1548,6 +1556,13 @@ > // use the new one. > ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); > } Missing blank line. > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Wed Aug 31 13:36:04 2011 > @@ -946,6 +946,25 @@ > return true; > } > > +SDValue DAGTypeLegalizer::DecomposeMERGE_VALUES(SDNode *N) { I know the comment describing DecomposeMERGE_VALUES is in the header, but it would be nice to have to here too. > + unsigned i; > + // A MERGE_VALUES node can produce any number of values. > + // We know that the first illegal type needs to be handled. Perhaps it should be clarified that this is the case because the type legalizer always legalizes results in order. > + for (i = 0; isTypeLegal(N->getValueType(i)); ++i) > + ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); > + > + // The first illegal result must be the one that needs to be handled. This comment repeats the previous comment. > + SDValue BadValue = N->getOperand(i); It's not bad, it's illegal :) How about IllegalValue instead. > + > + // Legalize the rest of the results into the input operands whether they This isn't legalizing, so how about: Map the rest of the results to the input operands whether they > + // are legal or not. > + unsigned e = N->getNumValues(); > + for (++i; i != e; ++i) > + ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); > + > + return BadValue; > +} > + > /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type > /// which is split into two not necessarily identical pieces. > void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT&LoVT, EVT&HiVT) { > > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Aug 31 13:36:04 2011 > @@ -148,12 +148,20 @@ > SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); > bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); > bool CustomWidenLowerNode(SDNode *N, EVT VT); > + > + // DecomposeMERGE_VALUES takes a SDNode and returns the first > + // illegal operand that needs to be modified. "that needs to be modified" is redundant. There is no such thing as an illegal operand that doesn't need to be modified. > + // All other nodes are legalized, whether they are legal or not. I find this line confusing. They aren't being legalized. > + // The resulting SDValue needs to be modified to make it legal. > + SDValue DecomposeMERGE_VALUES(SDNode *N); > + > SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index); > SDValue JoinIntegers(SDValue Lo, SDValue Hi); > SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); > SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > const SDValue *Ops, unsigned NumOps, bool isSigned, > DebugLoc dl); I didn't check the rest. Ciao, Duncan. From grosbach at apple.com Wed Aug 31 14:50:28 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 31 Aug 2011 19:50:28 -0000 Subject: [llvm-commits] [llvm] r138883 - /llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110831195029.08CB42A6C12C@llvm.org> Author: grosbach Date: Wed Aug 31 14:50:28 2011 New Revision: 138883 URL: http://llvm.org/viewvc/llvm-project?rev=138883&view=rev Log: Run the Thumb1 parser tests in Thumb2 mode, as well. Thumb2 is a superset of Thumb1, so all of the encodings should still work. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138883&r1=138882&r2=138883&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 31 14:50:28 2011 @@ -1,4 +1,9 @@ + at --- +@ Run these test in both Thumb1 and Thumb2 modes, as all of the encodings +@ should be valid, and parse the same, in both. + at --- @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s .syntax unified .globl _func @@ -384,15 +389,6 @@ @ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42] - - at ------------------------------------------------------------------------------ -@ NOP - at ------------------------------------------------------------------------------ - nop - -@ CHECK: nop @ encoding: [0xc0,0x46] - - @------------------------------------------------------------------------------ @ ORR @------------------------------------------------------------------------------ From resistor at mac.com Wed Aug 31 15:00:11 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 31 Aug 2011 20:00:11 -0000 Subject: [llvm-commits] [llvm] r138885 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <20110831200011.744462A6C12C@llvm.org> Author: resistor Date: Wed Aug 31 15:00:11 2011 New Revision: 138885 URL: http://llvm.org/viewvc/llvm-project?rev=138885&view=rev Log: When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=138885&r1=138884&r2=138885&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Aug 31 15:00:11 2011 @@ -759,8 +759,15 @@ bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { + unsigned Opcode = Op->getOpcode(); + ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) + ? cast(Op)->getAddressingMode() + : cast(Op)->getAddressingMode(); + ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) + ? ARM_AM::add : ARM_AM::sub; int Val; if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. + if (AddSub == ARM_AM::sub) Val *= -1; Offset = CurDAG->getRegister(0, MVT::i32); Opc = CurDAG->getTargetConstant(Val, MVT::i32); return true; @@ -2316,7 +2323,7 @@ Ops.push_back(Node->getOperand(1)); // Ptr Ops.push_back(Node->getOperand(2)); // Low part of Val1 Ops.push_back(Node->getOperand(3)); // High part of Val1 - if (Opc == ARM::ATOMCMPXCHG6432) { + if (Opc == ARM::ATOMCMPXCHG6432) { Ops.push_back(Node->getOperand(4)); // Low part of Val2 Ops.push_back(Node->getOperand(5)); // High part of Val2 } From eli.friedman at gmail.com Wed Aug 31 15:13:26 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 31 Aug 2011 20:13:26 -0000 Subject: [llvm-commits] [llvm] r138887 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeFloatTypes.cpp LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h Message-ID: <20110831201326.9A9AB2A6C12C@llvm.org> Author: efriedma Date: Wed Aug 31 15:13:26 2011 New Revision: 138887 URL: http://llvm.org/viewvc/llvm-project?rev=138887&view=rev Log: Misc cleanup; addresses Duncan's comments on r138877. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=138887&r1=138886&r2=138887&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Wed Aug 31 15:13:26 2011 @@ -110,9 +110,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N) { SDValue Op = DecomposeMERGE_VALUES(N); - return Op.getValueType().isVector() ? - BitConvertVectorToIntegerVector(Op) : - BitConvertToInteger(Op); + return BitConvertToInteger(Op); } SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=138887&r1=138886&r2=138887&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Aug 31 15:13:26 2011 @@ -139,8 +139,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N) { SDValue Op = DecomposeMERGE_VALUES(N); - assert(Op.getValueType().isInteger() - && "Must decompose to an integer type!"); return GetPromotedInteger(Op); } @@ -1556,11 +1554,10 @@ // use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } + void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, - SDValue &Lo, SDValue &Hi) { + SDValue &Lo, SDValue &Hi) { SDValue Res = DecomposeMERGE_VALUES(N); - assert(Res.getValueType().isInteger() - && "Cannot split a non-integer value."); SplitInteger(Res, Lo, Hi); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=138887&r1=138886&r2=138887&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Wed Aug 31 15:13:26 2011 @@ -948,21 +948,22 @@ SDValue DAGTypeLegalizer::DecomposeMERGE_VALUES(SDNode *N) { unsigned i; - // A MERGE_VALUES node can produce any number of values. - // We know that the first illegal type needs to be handled. + // A MERGE_VALUES node can produce any number of values. + // Replace the results other than the first illegal one with the + // corresponding input operands. for (i = 0; isTypeLegal(N->getValueType(i)); ++i) ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); - // The first illegal result must be the one that needs to be handled. - SDValue BadValue = N->getOperand(i); + // The first illegal result is the one which needs to be handled; + // type legalization legalizes values in order. + SDValue IllegalValue = N->getOperand(i); - // Legalize the rest of the results into the input operands whether they - // are legal or not. + // Continue replacing results. unsigned e = N->getNumValues(); for (++i; i != e; ++i) ReplaceValueWith(SDValue(N, i), SDValue(N->getOperand(i))); - return BadValue; + return IllegalValue; } /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=138887&r1=138886&r2=138887&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Aug 31 15:13:26 2011 @@ -149,10 +149,9 @@ bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); bool CustomWidenLowerNode(SDNode *N, EVT VT); - // DecomposeMERGE_VALUES takes a SDNode and returns the first - // illegal operand that needs to be modified. - // All other nodes are legalized, whether they are legal or not. - // The resulting SDValue needs to be modified to make it legal. + // DecomposeMERGE_VALUES takes a SDNode and returns the first + // illegal value. All other results are replaced with the + // corresponding input operand. SDValue DecomposeMERGE_VALUES(SDNode *N); SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index); @@ -162,9 +161,9 @@ const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl); - std::pair ExpandChainLibCall(RTLIB::Libcall LC, - SDNode *Node, bool isSigned); - std::pair ExpandAtomic(SDNode *Node); + std::pair ExpandChainLibCall(RTLIB::Libcall LC, + SDNode *Node, bool isSigned); + std::pair ExpandAtomic(SDNode *Node); SDValue PromoteTargetBoolean(SDValue Bool, EVT VT); void ReplaceValueWith(SDValue From, SDValue To); From resistor at mac.com Wed Aug 31 15:26:14 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 31 Aug 2011 20:26:14 -0000 Subject: [llvm-commits] [llvm] r138889 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb-instructions.s Message-ID: <20110831202614.E4B562A6C12C@llvm.org> Author: resistor Date: Wed Aug 31 15:26:14 2011 New Revision: 138889 URL: http://llvm.org/viewvc/llvm-project?rev=138889&view=rev Log: Fix encoding for tBcc with immediate offset operand. Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138889&r1=138888&r2=138889&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Aug 31 15:26:14 2011 @@ -522,7 +522,11 @@ uint32_t ARMMCCodeEmitter:: getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups); + const MCOperand MO = MI.getOperand(OpIdx); + if (MO.isExpr()) + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, + Fixups); + return (MO.getImm() >> 1); } /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138889&r1=138888&r2=138889&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Wed Aug 31 15:26:14 2011 @@ -114,6 +114,8 @@ beq _bar b #1838 b #-420 + beq #336 + beq #160 @ CHECK: b _baz @ encoding: [A,0xe0'A'] @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br @@ -121,6 +123,8 @@ @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc @ CHECK: b #1838 @ encoding: [0x97,0xe3] @ CHECK: b #-420 @ encoding: [0x2e,0xe7] +@ CHECK: beq #336 @ encoding: [0xa8,0xd0] +@ CHECK: beq #160 @ encoding: [0x50,0xd0] @------------------------------------------------------------------------------ @ BL/BLX From isanbard at gmail.com Wed Aug 31 15:55:20 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 31 Aug 2011 20:55:20 -0000 Subject: [llvm-commits] [llvm] r138890 - /llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Message-ID: <20110831205520.D0EEC2A6C12C@llvm.org> Author: void Date: Wed Aug 31 15:55:20 2011 New Revision: 138890 URL: http://llvm.org/viewvc/llvm-project?rev=138890&view=rev Log: Make sure we aren't deleting the landingpad instruction. The landingpad instruction is required in the landing pad block. Because we're not deleting terminating instructions, the invoke may still jump to here (see Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad instruction, but keep it around until code-gen can remove the basic block. Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=138890&r1=138889&r2=138890&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Wed Aug 31 15:55:20 2011 @@ -1681,15 +1681,31 @@ static void DeleteInstructionInBlock(BasicBlock *BB) { DEBUG(dbgs() << " BasicBlock Dead:" << *BB); ++NumDeadBlocks; - + + // Check to see if there are non-terminating instructions to delete. + if (isa(BB->begin())) + return; + // Delete the instructions backwards, as it has a reduced likelihood of // having to update as many def-use and use-def chains. - while (!isa(BB->begin())) { - Instruction *I = --BasicBlock::iterator(BB->getTerminator()); - + std::vector WorkList; + WorkList.reserve(BB->size()); + BasicBlock::iterator I = --BasicBlock::iterator(BB->getTerminator()); + + while (true) { if (!I->use_empty()) I->replaceAllUsesWith(UndefValue::get(I->getType())); - BB->getInstList().erase(I); + WorkList.push_back(I); + if (I == BB->begin()) + break; + --I; + } + + for (std::vector::iterator + II = WorkList.begin(), IE = WorkList.end(); II != IE; ++II) { + if (isa(*II)) + continue; + BB->getInstList().erase(*II); ++NumInstRemoved; } } From isanbard at gmail.com Wed Aug 31 15:55:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 31 Aug 2011 20:55:41 -0000 Subject: [llvm-commits] [llvm] r138891 - in /llvm/trunk/test/Transforms/SCCP: 2003-08-26-InvokeHandling.ll 2004-11-16-DeadInvoke.ll 2007-05-16-InvokeCrash.ll 2009-01-14-IPSCCP-Invoke.ll ipsccp-basic.ll Message-ID: <20110831205541.27ACC2A6C12C@llvm.org> Author: void Date: Wed Aug 31 15:55:40 2011 New Revision: 138891 URL: http://llvm.org/viewvc/llvm-project?rev=138891&view=rev Log: Update the tests to the new EH scheme. Modified: llvm/trunk/test/Transforms/SCCP/2003-08-26-InvokeHandling.ll llvm/trunk/test/Transforms/SCCP/2004-11-16-DeadInvoke.ll llvm/trunk/test/Transforms/SCCP/2007-05-16-InvokeCrash.ll llvm/trunk/test/Transforms/SCCP/2009-01-14-IPSCCP-Invoke.ll llvm/trunk/test/Transforms/SCCP/ipsccp-basic.ll Modified: llvm/trunk/test/Transforms/SCCP/2003-08-26-InvokeHandling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/2003-08-26-InvokeHandling.ll?rev=138891&r1=138890&r2=138891&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SCCP/2003-08-26-InvokeHandling.ll (original) +++ llvm/trunk/test/Transforms/SCCP/2003-08-26-InvokeHandling.ll Wed Aug 31 15:55:40 2011 @@ -8,11 +8,16 @@ br i1 %cond, label %Inv, label %Cont Inv: ; preds = %Entry invoke void @foo( ) - to label %Ok unwind label %Cont + to label %Ok unwind label %LPad Ok: ; preds = %Inv br label %Cont +LPad: + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + br label %Cont Cont: ; preds = %Ok, %Inv, %Entry - %X = phi i32 [ 0, %Entry ], [ 1, %Ok ], [ 0, %Inv ] ; [#uses=1] + %X = phi i32 [ 0, %Entry ], [ 1, %Ok ], [ 0, %LPad ] ; [#uses=1] ret i32 %X } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SCCP/2004-11-16-DeadInvoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/2004-11-16-DeadInvoke.ll?rev=138891&r1=138890&r2=138891&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SCCP/2004-11-16-DeadInvoke.ll (original) +++ llvm/trunk/test/Transforms/SCCP/2004-11-16-DeadInvoke.ll Wed Aug 31 15:55:40 2011 @@ -6,8 +6,13 @@ br i1 true, label %T, label %F F: ; preds = %0 %X = invoke i32 @foo( ) - to label %T unwind label %T ; [#uses=0] -T: ; preds = %F, %F, %0 + to label %T unwind label %LP ; [#uses=0] +LP: + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + br label %T +T: ret void } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SCCP/2007-05-16-InvokeCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/2007-05-16-InvokeCrash.ll?rev=138891&r1=138890&r2=138891&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SCCP/2007-05-16-InvokeCrash.ll (original) +++ llvm/trunk/test/Transforms/SCCP/2007-05-16-InvokeCrash.ll Wed Aug 31 15:55:40 2011 @@ -31,7 +31,9 @@ bb177: ; preds = %bb149 unreachable cleanup: ; preds = %bb149, %bb114, %bb67 - unwind + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + resume { i8*, i32 } %val } declare double @sin(double) @@ -39,3 +41,5 @@ declare double @log(double) declare double @sqrt(double) + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/SCCP/2009-01-14-IPSCCP-Invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/2009-01-14-IPSCCP-Invoke.ll?rev=138891&r1=138890&r2=138891&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SCCP/2009-01-14-IPSCCP-Invoke.ll (original) +++ llvm/trunk/test/Transforms/SCCP/2009-01-14-IPSCCP-Invoke.ll Wed Aug 31 15:55:40 2011 @@ -7,6 +7,8 @@ to label %UnifiedReturnBlock unwind label %lpad lpad: + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup unreachable UnifiedReturnBlock: Modified: llvm/trunk/test/Transforms/SCCP/ipsccp-basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SCCP/ipsccp-basic.ll?rev=138891&r1=138890&r2=138891&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SCCP/ipsccp-basic.ll (original) +++ llvm/trunk/test/Transforms/SCCP/ipsccp-basic.ll Wed Aug 31 15:55:40 2011 @@ -90,6 +90,8 @@ %c = call i64 @test4c(i64 %b) ret i64 %c B: + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null ret i64 0 } ; CHECK: define i64 @test4b() @@ -121,6 +123,8 @@ %c = call i64 @test5c({i64,i64} %a) ret i64 %c B: + %val = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null ret i64 0 } @@ -204,3 +208,4 @@ ret void } +declare i32 @__gxx_personality_v0(...) From Micah.Villmow at amd.com Wed Aug 31 15:59:04 2011 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Wed, 31 Aug 2011 15:59:04 -0500 Subject: [llvm-commits] Patch to add support for WidenVecRes_MERGE_VALUES In-Reply-To: References: <4E5C8D2E.9010006@grosser.es> <4E5D2D5C.1050209@grosser.es> Message-ID: Thanks, closed bug10736. > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Eli Friedman > Sent: Wednesday, August 31, 2011 11:38 AM > To: Villmow, Micah > Cc: llvm-commits; Tobias Grosser > Subject: Re: [llvm-commits] Patch to add support for > WidenVecRes_MERGE_VALUES > > r138877. > > -Eli > > On Tue, Aug 30, 2011 at 6:45 PM, Villmow, Micah > wrote: > > Here is a combined patch. > > > >> -----Original Message----- > >> From: Eli Friedman [mailto:eli.friedman at gmail.com] > >> Sent: Tuesday, August 30, 2011 1:09 PM > >> To: Villmow, Micah > >> Cc: Tobias Grosser; llvm-commits > >> Subject: Re: [llvm-commits] Patch to add support for > >> WidenVecRes_MERGE_VALUES > >> > >> On Tue, Aug 30, 2011 at 1:06 PM, Villmow, Micah > > >> wrote: > >> > Eli, > >> > ?So for the other cases, it would just be call > DecomposeMERGE_VALUES > >> and then call the correct > >> > legalization function on the return value, correct? > >> > >> Yes. > >> > >> > I'll send a second patch with those later. > >> > >> Great, thanks. > >> > >> -Eli > >> > >> > Micah > >> > > >> >> -----Original Message----- > >> >> From: Eli Friedman [mailto:eli.friedman at gmail.com] > >> >> Sent: Tuesday, August 30, 2011 12:56 PM > >> >> To: Tobias Grosser > >> >> Cc: Villmow, Micah; llvm-commits > >> >> Subject: Re: [llvm-commits] Patch to add support for > >> >> WidenVecRes_MERGE_VALUES > >> >> > >> >> On Tue, Aug 30, 2011 at 11:35 AM, Tobias Grosser > > >> >> wrote: > >> >> > On 08/30/2011 01:04 PM, Villmow, Micah wrote: > >> >> >> > >> >> >> Thanks for the feedback, new revision attached. > >> >> > > >> >> > There seems one unneeded white space change. (Can be fixed on > >> commit) > >> >> > > >> >> >> SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, > >> >> >> ? ? ? ? ? ? ? ? ? ?const SDValue *Ops, unsigned NumOps, bool > >> >> isSigned, > >> >> >> ? ? ? ? ? ? ? ? ? ?DebugLoc dl); > >> >> >> + > >> >> >> ? ? ? ?std::pair > >> >> ExpandChainLibCall(RTLIB::Libcall > >> >> > > >> >> > Otherwise, it looks good. Let's see if Eli has any additional > >> >> comments. > >> >> > >> >> Looks fine. > >> >> > >> >> Note that it would be nice to make sure we implement MERGE_VALUES > >> for > >> >> all the other cases in type legalization... (integer promotion, > >> vector > >> >> scalarization, etc.) > >> >> > >> >> -Eli > >> > > >> > > >> > > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Wed Aug 31 16:04:11 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 31 Aug 2011 21:04:11 -0000 Subject: [llvm-commits] [llvm] r138894 - in /llvm/trunk/test: CodeGen/Generic/2004-02-08-UnwindSupport.ll CodeGen/PowerPC/2007-11-16-landingpad-split.ll Transforms/ObjCARC/basic.ll Transforms/ObjCARC/invoke.ll Transforms/ObjCARC/retain-not-declared.ll Transforms/PruneEH/2003-09-14-ExternalCall.ll Message-ID: <20110831210411.8A0C52A6C12C@llvm.org> Author: void Date: Wed Aug 31 16:04:11 2011 New Revision: 138894 URL: http://llvm.org/viewvc/llvm-project?rev=138894&view=rev Log: Update more tests to the new EH scheme. Modified: llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll llvm/trunk/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll llvm/trunk/test/Transforms/ObjCARC/basic.ll llvm/trunk/test/Transforms/ObjCARC/invoke.ll llvm/trunk/test/Transforms/ObjCARC/retain-not-declared.ll llvm/trunk/test/Transforms/PruneEH/2003-09-14-ExternalCall.ll Modified: llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll Wed Aug 31 16:04:11 2011 @@ -12,6 +12,9 @@ ret i32 1 EH: ; preds = %0 + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup ret i32 0 } +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll Wed Aug 31 16:04:11 2011 @@ -18,11 +18,10 @@ br label %bb30 unwind: ; preds = %cond_true, %entry - %eh_ptr = call i8* @llvm.eh.exception() ; [#uses=2] - %eh_select = call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64(i8* %eh_ptr, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i8* null) ; [#uses=0] + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + catch i8* null call void @llvm.stackrestore(i8* %tmp4) - call void @_Unwind_Resume(i8* %eh_ptr) - unreachable + resume { i8*, i32 } %exn invcont23: ; preds = %cond_true %tmp27 = load i64* %tmp26, align 8 ; [#uses=1] @@ -46,14 +45,8 @@ declare void @Foo(i8**) -declare i8* @llvm.eh.exception() nounwind - -declare i64 @llvm.eh.selector.i64(i8*, i8*, ...) nounwind - -declare void @__gxx_personality_v0() - -declare void @_Unwind_Resume(i8*) - declare void @Bar(i64, %struct.Range*) declare void @llvm.stackrestore(i8*) nounwind + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/ObjCARC/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/basic.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/basic.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/basic.ll Wed Aug 31 16:04:11 2011 @@ -698,6 +698,8 @@ lpad20: ; preds = %invoke.cont23, %if.then12 %tmp502 = phi double* [ undef, %invoke.cont23 ], [ %self, %if.then12 ] + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup unreachable if.end: ; preds = %invoke.cont23 @@ -1998,3 +2000,5 @@ } !0 = metadata !{} + +declare i32 @__gxx_personality_v0(...) Modified: llvm/trunk/test/Transforms/ObjCARC/invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/invoke.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/invoke.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/invoke.ll Wed Aug 31 16:04:11 2011 @@ -27,6 +27,8 @@ ret void lpad: ; preds = %entry + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup call void @objc_release(i8* %zipFile) nounwind, !clang.imprecise_release !0 ret void } @@ -56,6 +58,8 @@ br label %done lpad: ; preds = %entry + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup call void @callee() br label %done @@ -64,4 +68,6 @@ ret void } +declare i32 @__gxx_personality_v0(...) + !0 = metadata !{} Modified: llvm/trunk/test/Transforms/ObjCARC/retain-not-declared.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/retain-not-declared.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/retain-not-declared.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/retain-not-declared.ll Wed Aug 31 16:04:11 2011 @@ -51,11 +51,17 @@ unreachable lpad91: ; preds = %entry + %exn91 = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup unreachable lpad100: ; preds = %invoke.cont93 + %exn100 = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup call void @objc_release(i8* %tmp2) nounwind, !clang.imprecise_release !0 unreachable } +declare i32 @__gxx_personality_v0(...) + !0 = metadata !{} Modified: llvm/trunk/test/Transforms/PruneEH/2003-09-14-ExternalCall.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PruneEH/2003-09-14-ExternalCall.ll?rev=138894&r1=138893&r2=138894&view=diff ============================================================================== --- llvm/trunk/test/Transforms/PruneEH/2003-09-14-ExternalCall.ll (original) +++ llvm/trunk/test/Transforms/PruneEH/2003-09-14-ExternalCall.ll Wed Aug 31 16:04:11 2011 @@ -6,6 +6,9 @@ invoke void @External( ) to label %Cont unwind label %Cont Cont: ; preds = %0, %0 + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + cleanup ret void } +declare i32 @__gxx_personality_v0(...) From greened at obbligato.org Wed Aug 31 16:07:56 2011 From: greened at obbligato.org (David A. Greene) Date: Wed, 31 Aug 2011 16:07:56 -0500 Subject: [llvm-commits] [llvm] r138864 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2011-08-29-BlockConstant.ll In-Reply-To: <557CB305-5387-4A64-BE6E-AA53F86BFC94@apple.com> (Chris Lattner's message of "Wed, 31 Aug 2011 10:46:29 -0700") References: <20110831173056.53C0D2A6C12C@llvm.org> <557CB305-5387-4A64-BE6E-AA53F86BFC94@apple.com> Message-ID: Chris Lattner writes: >> + if (Value != -1) { >> + unsigned Bytes = AP.TM.getTargetData()->getTypeAllocSize(CA->getType()); >> + AP.OutStreamer.EmitFill(Bytes, Value, AddrSpace); >> + } > > "Bytes" should be a uint64_t. Sizes should be 64-bit, even if "index counts" are not. Good catch. Will fix. -Dave From jvoung at google.com Wed Aug 31 16:15:33 2011 From: jvoung at google.com (Jan Voung) Date: Wed, 31 Aug 2011 14:15:33 -0700 Subject: [llvm-commits] PATCH: pruning llvm w/ config flags --enable-target-oses=os1, os2 similar to --enable-target=arch1, arch2. In-Reply-To: <558928B5-547F-46F8-8F27-CEEBA86EE2EA@apple.com> References: <558928B5-547F-46F8-8F27-CEEBA86EE2EA@apple.com> Message-ID: On Tue, Aug 30, 2011 at 4:59 PM, Eric Christopher wrote: > > On Aug 29, 2011, at 4:58 PM, Jan Voung wrote: > > - Is this approach acceptable? > > - I guess it is hard to test if this has any effect / depends on the > compiler. > > I'm not really wild about this approach, no. I'd prefer separating out the > targets from each other and then conditionally compiling in support rather > than relying on DCE and LTO to decide whether or not the code should be > there. I'm open to other ideas/discussion on it though. Hmm I'll have to think a bit more about how to facilitate conditionally compiling-in support (e.g., the way lib/Target/X is done). The OS and environment checks + inline code are currently quite widespread. Here is an estimate: grep -r "isOSDarwin" . | grep -v "\.svn" | wc -l 44 grep -r "isMacOSX" . | grep -v "\.svn" | wc -l 30 grep -r "isTargetDarwin" . | grep -v "\.svn" | wc -l 58 grep -r "Triple::Darwin" . | grep -v "\.svn" | wc -l 21 grep -r "Triple::MachO" . | grep -v "\.svn" | wc -l 9 grep -r "Triple::IOS" . | grep -v "\.svn" | wc -l 4 grep -r "Triple::MacOSX" . | grep -v "\.svn" | wc -l 4 grep -r "isOSWindows" . | grep -v "\.svn" | wc -l 11 grep -r "isTargetWindows" . | grep -v "\.svn" | wc -l 13 grep -r "isTargetCygwin" . | grep -v "\.svn" | wc -l 3 grep -r "isTargetCygMing" . | grep -v "\.svn" | wc -l 14 grep -r "Triple::Win32" . | grep -v "\.svn" | wc -l 14 grep -r "Triple::Cygwin" . | grep -v "\.svn" | wc -l 10 grep -r "Triple::MinGW32" . | grep -v "\.svn" | wc -l 14 grep -r "Triple::Linux" . | grep -v "\.svn" | wc -l 14 grep -r "isTargetLinux" . | grep -v "\.svn" | wc -l 5 grep -r "Triple::OpenBSD" . | grep -v "\.svn" | wc -l 7 ... Total matches so far: 275 Perhaps there are some cases that may be easy to refactor, yet account for most of the bytes. Refactoring everything will probably take a while. The fact that many of them overlap in certain ways (e.g., isTargetCygMing) makes it... harder. Anyway, I'll think about it more. Thanks! > > - Is trimming the size of the llvm binaries (via config flags) useful to > others? > > - Other examples: > > - make "include/llvm/Intrinsics.td" not #include intrinsincs for > targets that were not enabled through "--enable-target" > > - config flags to avoid building unused register allocators, other > passes > > This is quite useful in general, I'm just not a fan of the current method. > > The cleanups that you have are definitely useful patches and I hope you'll > submit those separately. Thanks! > > -eric > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110831/dd054960/attachment-0001.html From bruno.cardoso at gmail.com Wed Aug 31 16:15:22 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 21:15:22 -0000 Subject: [llvm-commits] [llvm] r138895 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110831211522.707CE2A6C12C@llvm.org> Author: bruno Date: Wed Aug 31 16:15:22 2011 New Revision: 138895 URL: http://llvm.org/viewvc/llvm-project?rev=138895&view=rev Log: Remove "_Int" forms of MOVUPSmr and MOVAPSmr Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138895&r1=138894&r2=138895&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 31 16:15:22 2011 @@ -682,22 +682,19 @@ "movupd\t{$src, $dst|$dst, $src}", [(store (v2f64 VR128:$src), addr:$dst)]>; -// Intrinsic forms of MOVUPS/D load and store -def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs), - (ins f128mem:$dst, VR128:$src), - "movups\t{$src, $dst|$dst, $src}", - [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX; -def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs), - (ins f128mem:$dst, VR128:$src), - "movupd\t{$src, $dst|$dst, $src}", - [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX; - -def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), - "movups\t{$src, $dst|$dst, $src}", - [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; -def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), - "movupd\t{$src, $dst|$dst, $src}", - [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; +let Predicates = [HasAVX] in { + def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src), + (VMOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src), + (VMOVUPDmr addr:$dst, VR128:$src)>; +} + +let Predicates = [HasSSE1] in + def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src), + (MOVUPSmr addr:$dst, VR128:$src)>; +let Predicates = [HasSSE2] in + def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src), + (MOVUPDmr addr:$dst, VR128:$src)>; // Move Low/High packed floating point values multiclass sse12_mov_hilo_packedopc, RegisterClass RC, From bruno.cardoso at gmail.com Wed Aug 31 16:15:30 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 21:15:30 -0000 Subject: [llvm-commits] [llvm] r138896 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110831211530.340392A6C12C@llvm.org> Author: bruno Date: Wed Aug 31 16:15:29 2011 New Revision: 138896 URL: http://llvm.org/viewvc/llvm-project?rev=138896&view=rev Log: Move MOVAPS,MOVUPS patterns close to the instructions definition Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138896&r1=138895&r2=138896&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 31 16:15:29 2011 @@ -696,7 +696,98 @@ def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src), (MOVUPDmr addr:$dst, VR128:$src)>; -// Move Low/High packed floating point values +// Use movaps / movups for SSE integer load / store (one byte shorter). +// The instructions selected below are then converted to MOVDQA/MOVDQU +// during the SSE domain pass. +let Predicates = [HasSSE1] in { + def : Pat<(alignedloadv4i32 addr:$src), + (MOVAPSrm addr:$src)>; + def : Pat<(loadv4i32 addr:$src), + (MOVUPSrm addr:$src)>; + def : Pat<(alignedloadv2i64 addr:$src), + (MOVAPSrm addr:$src)>; + def : Pat<(loadv2i64 addr:$src), + (MOVUPSrm addr:$src)>; + + def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (MOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v2i64 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (MOVUPSmr addr:$dst, VR128:$src)>; +} + +// Use vmovaps/vmovups for AVX integer load/store. +let Predicates = [HasAVX] in { + // 128-bit load/store + def : Pat<(alignedloadv4i32 addr:$src), + (VMOVAPSrm addr:$src)>; + def : Pat<(loadv4i32 addr:$src), + (VMOVUPSrm addr:$src)>; + def : Pat<(alignedloadv2i64 addr:$src), + (VMOVAPSrm addr:$src)>; + def : Pat<(loadv2i64 addr:$src), + (VMOVUPSrm addr:$src)>; + + def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), + (VMOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), + (VMOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), + (VMOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), + (VMOVAPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v2i64 VR128:$src), addr:$dst), + (VMOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v4i32 VR128:$src), addr:$dst), + (VMOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v8i16 VR128:$src), addr:$dst), + (VMOVUPSmr addr:$dst, VR128:$src)>; + def : Pat<(store (v16i8 VR128:$src), addr:$dst), + (VMOVUPSmr addr:$dst, VR128:$src)>; + + // 256-bit load/store + def : Pat<(alignedloadv4i64 addr:$src), + (VMOVAPSYrm addr:$src)>; + def : Pat<(loadv4i64 addr:$src), + (VMOVUPSYrm addr:$src)>; + def : Pat<(alignedloadv8i32 addr:$src), + (VMOVAPSYrm addr:$src)>; + def : Pat<(loadv8i32 addr:$src), + (VMOVUPSYrm addr:$src)>; + def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst), + (VMOVAPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v4i64 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v8i32 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v16i16 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; + def : Pat<(store (v32i8 VR256:$src), addr:$dst), + (VMOVUPSYmr addr:$dst, VR256:$src)>; +} + + +//===----------------------------------------------------------------------===// +// SSE 1 & 2 - Move Low/High packed FP Instructions +//===----------------------------------------------------------------------===// + multiclass sse12_mov_hilo_packedopc, RegisterClass RC, PatFrag mov_frag, string base_opc, string asm_opr> { @@ -4584,93 +4675,6 @@ def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; -// Use movaps / movups for SSE integer load / store (one byte shorter). -// The instructions selected below are then converted to MOVDQA/MOVDQU -// during the SSE domain pass. -let Predicates = [HasSSE1] in { - def : Pat<(alignedloadv4i32 addr:$src), - (MOVAPSrm addr:$src)>; - def : Pat<(loadv4i32 addr:$src), - (MOVUPSrm addr:$src)>; - def : Pat<(alignedloadv2i64 addr:$src), - (MOVAPSrm addr:$src)>; - def : Pat<(loadv2i64 addr:$src), - (MOVUPSrm addr:$src)>; - - def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), - (MOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), - (MOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), - (MOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), - (MOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v2i64 VR128:$src), addr:$dst), - (MOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v4i32 VR128:$src), addr:$dst), - (MOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v8i16 VR128:$src), addr:$dst), - (MOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v16i8 VR128:$src), addr:$dst), - (MOVUPSmr addr:$dst, VR128:$src)>; -} - -// Use vmovaps/vmovups for AVX integer load/store. -let Predicates = [HasAVX] in { - // 128-bit load/store - def : Pat<(alignedloadv4i32 addr:$src), - (VMOVAPSrm addr:$src)>; - def : Pat<(loadv4i32 addr:$src), - (VMOVUPSrm addr:$src)>; - def : Pat<(alignedloadv2i64 addr:$src), - (VMOVAPSrm addr:$src)>; - def : Pat<(loadv2i64 addr:$src), - (VMOVUPSrm addr:$src)>; - - def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), - (VMOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), - (VMOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), - (VMOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), - (VMOVAPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v2i64 VR128:$src), addr:$dst), - (VMOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v4i32 VR128:$src), addr:$dst), - (VMOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v8i16 VR128:$src), addr:$dst), - (VMOVUPSmr addr:$dst, VR128:$src)>; - def : Pat<(store (v16i8 VR128:$src), addr:$dst), - (VMOVUPSmr addr:$dst, VR128:$src)>; - - // 256-bit load/store - def : Pat<(alignedloadv4i64 addr:$src), - (VMOVAPSYrm addr:$src)>; - def : Pat<(loadv4i64 addr:$src), - (VMOVUPSYrm addr:$src)>; - def : Pat<(alignedloadv8i32 addr:$src), - (VMOVAPSYrm addr:$src)>; - def : Pat<(loadv8i32 addr:$src), - (VMOVUPSYrm addr:$src)>; - def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst), - (VMOVAPSYmr addr:$dst, VR256:$src)>; - def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst), - (VMOVAPSYmr addr:$dst, VR256:$src)>; - def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst), - (VMOVAPSYmr addr:$dst, VR256:$src)>; - def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst), - (VMOVAPSYmr addr:$dst, VR256:$src)>; - def : Pat<(store (v4i64 VR256:$src), addr:$dst), - (VMOVUPSYmr addr:$dst, VR256:$src)>; - def : Pat<(store (v8i32 VR256:$src), addr:$dst), - (VMOVUPSYmr addr:$dst, VR256:$src)>; - def : Pat<(store (v16i16 VR256:$src), addr:$dst), - (VMOVUPSYmr addr:$dst, VR256:$src)>; - def : Pat<(store (v32i8 VR256:$src), addr:$dst), - (VMOVUPSYmr addr:$dst, VR256:$src)>; -} - //===----------------------------------------------------------------------===// // SSE4.1 - Packed Move with Sign/Zero Extend //===----------------------------------------------------------------------===// From bruno.cardoso at gmail.com Wed Aug 31 16:15:32 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 31 Aug 2011 21:15:32 -0000 Subject: [llvm-commits] [llvm] r138897 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20110831211532.874EA2A6C12D@llvm.org> Author: bruno Date: Wed Aug 31 16:15:32 2011 New Revision: 138897 URL: http://llvm.org/viewvc/llvm-project?rev=138897&view=rev Log: Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=138897&r1=138896&r2=138897&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Aug 31 16:15:32 2011 @@ -783,9 +783,8 @@ (VMOVUPSYmr addr:$dst, VR256:$src)>; } - //===----------------------------------------------------------------------===// -// SSE 1 & 2 - Move Low/High packed FP Instructions +// SSE 1 & 2 - Move Low packed FP Instructions //===----------------------------------------------------------------------===// multiclass sse12_mov_hilo_packedopc, RegisterClass RC, @@ -810,14 +809,10 @@ let AddedComplexity = 20 in { defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp", "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V; - defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp", - "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V; } let Constraints = "$src1 = $dst", AddedComplexity = 20 in { defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp", "\t{$src2, $dst|$dst, $src2}">; - defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp", - "\t{$src2, $dst|$dst, $src2}">; } def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), @@ -837,6 +832,147 @@ [(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))), addr:$dst)]>; +let Predicates = [HasAVX] in { + let AddedComplexity = 20 in { + // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS + def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))), + (VMOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))), + (VMOVLPSrm VR128:$src1, addr:$src2)>; + // vector_shuffle v1, (load v2) <2, 1> using MOVLPS + def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))), + (VMOVLPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))), + (VMOVLPDrm VR128:$src1, addr:$src2)>; + } + + // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS + def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), + (VMOVLPSmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), + VR128:$src2)), addr:$src1), + (VMOVLPSmr addr:$src1, VR128:$src2)>; + + // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS + def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), + (VMOVLPDmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), + (VMOVLPDmr addr:$src1, VR128:$src2)>; + + // Shuffle with VMOVLPS + def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))), + (VMOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))), + (VMOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(X86Movlps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), + (VMOVLPSrm VR128:$src1, addr:$src2)>; + + // Shuffle with VMOVLPD + def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), + (VMOVLPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))), + (VMOVLPDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2f64 (X86Movlpd VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)))), + (VMOVLPDrm VR128:$src1, addr:$src2)>; + + // Store patterns + def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), + addr:$src1), + (VMOVLPSmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v4i32 (X86Movlps + (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1), + (VMOVLPSmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)), + addr:$src1), + (VMOVLPDmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)), + addr:$src1), + (VMOVLPDmr addr:$src1, VR128:$src2)>; +} + +let Predicates = [HasSSE1] in { + let AddedComplexity = 20 in { + // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS + def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + } + + // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS + def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), + VR128:$src2)), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + + // Shuffle with MOVLPS + def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(X86Movlps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + + // Store patterns + def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), + addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + def : Pat<(store (v4i32 (X86Movlps + (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), + addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; +} + +let Predicates = [HasSSE2] in { + let AddedComplexity = 20 in { + // vector_shuffle v1, (load v2) <2, 1> using MOVLPS + def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),